From ddf52e2cdd977f14fc04035c88672ac204aec713 Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Fri, 31 Oct 2025 16:32:45 +0800 Subject: [PATCH 01/45] [log]Update V5.2.2 Released Changelog. --- ChangeLog.md | 181 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/ChangeLog.md b/ChangeLog.md index 161bc1c0da..8504f9fb13 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,3 +1,184 @@ +# RT-Thread v5.2.2 Released + +Change Log Since v5.2.1 Release. + +## Kernel + +* Fix scheduling exception caused by interrupt preemption in rt_schedule.[(#10715)](https://github.com/RT-Thread/rt-thread/pull/10715) +* Fix the legacy issue related to the length of the object name version.[(#10537)](https://github.com/RT-Thread/rt-thread/pull/10537) +* Fixed buffer overflow vulnerability in object.[(#10523)](https://github.com/RT-Thread/rt-thread/pull/10523) +* Add up scheduler critical switch flag.[(#10581)](https://github.com/RT-Thread/rt-thread/pull/10581) +* Update the default value of RT_NAME_MAX to 12.[(#10839)](https://github.com/RT-Thread/rt-thread/pull/10839) +* Feat the rt_scheduler lock nest uses atomic operations.[(#10621)](https://github.com/RT-Thread/rt-thread/pull/10621) + +## Components + +* **Drivers** + * **Serial:** + * serial_v1 + * Fix correct data loss logic when RX ring buffer is full. + * serial_v2 + * Fix the bug of RX flush under DMA. + * Add serial V2 buffer configuration via Kconfig. + * Feat optimize serial v2. [(#10603)](https://github.com/RT-Thread/rt-thread/pull/10603) + * Feat modify the default configuration of the RT_SERIAL_CONFIG_DEFAULT structure to support parameters in the absence of DMA configuration. + * **RTC:** + * Add the alarm using local time for calculation. + * **CAN:** + * Fixed the issue where the thread calling CAN int TX was suspended when CAN at the bottom layer failed to work. + * Feat: Implement non-blocking send mechanism and enhance CAN driver functionality. + * **SPI:** + * Add SPI device detach function.[(#10733)](https://github.com/RT-Thread/rt-thread/pull/10733) + * Update and fix up the SPI. + * **ADC:** + * Fixed cppcheck error. + * Remove build warnings. + * **ktime:** + * Remove unused rt_ktime_hrtimer_getcnt for hrtimer. + * **wlan:** + * Update SECURITY_UNKNOWN value. +* **LWP** + * Fix potential signal handler infinite loop for riscv. + * Feat: Restore TP register in arch_thread_signal_enter to fix user-mode memory access. +* **Libc** + * Add comments for some pthread functions. + * pthreads: Fix pthread_cond_timedwait lacks timeout wakeup. + * ensure compatibility with newlib <3.4.0 by handling removed __sdidinit. [(#10791)](https://github.com/RT-Thread/rt-thread/pull/10791) +* **DFS** + * **DFS v2**: + * Fix bugs for function _get_parent_path(). [(#10539)](https://github.com/RT-Thread/rt-thread/pull/10539) +* **Net** + * **SAL/Socket:** + * Fixed CI compilation failure in sal/src/sal_socket.c. + * Fix memory leak when sal_socket failed. + * improve the error return of sal. + * **Netdev:** + * Fixed compilation errors when enabling IPv6 and IPv4 dual-stack support. + * Fixed netdev_unregister missing correct return value. [(#10693)](https://github.com/RT-Thread/rt-thread/pull/10693) + * Expose netdev_set_dns and netdev_set_if. [(#10128)](https://github.com/RT-Thread/rt-thread/pull/10128) + * **AT:** + * at_client add deInit port. [(#10598)](https://github.com/RT-Thread/rt-thread/pull/10598) +* **Finsh:** + + * Fixed clear out the useless copy operations. [(#10699)](https://github.com/RT-Thread/rt-thread/pull/10699) + * Feat add support for the Home, Insert, Delete and End keys, and improve input mode processing.[(#10595)](https://github.com/RT-Thread/rt-thread/pull/10595) + * Feat: Add new features (delete by word, switch cursor, etc.). +* **USB:** + * Update (cherryusb): update to v1.5.1. + * Fixed several issues related to cherryusb.[(#10844)](https://github.com/RT-Thread/rt-thread/pull/10844) +* **Ulog:** + * Fix:filter should not be associated with ULOG_USING_COLOR and ULOG_USING_SYSLOG configurations. +* **IPC:** + * Pass rt_tick_t for RT_TIMER_CTRL_SET_TIME and RT_TIMER_CTRL_GET_TIME.[(#10717)](https://github.com/RT-Thread/rt-thread/pull/10717) + +## DM + +* NVME: fix up the QUEUE alloc error no check. +* Thermal: Fix up the C99, 6.8.1 Labeled statements p4; Fix up the PWM-FAN remove handle data ptr. +* PCI: Add SoC PCI Kconfig import; Multiple PCI-related fixes; Fix and optimize interrupt-related issues. +* WDT: Support related to Intel 6300ESB/Synopsys Watchdog, etc. + +## Libcpu + +* **AArch64:** + * Fix up MMU and linker warning. + * Fix rt_aspace_init error when KERNEL_VADDR_START >= 0x80000000. + * Add the configuration of libcpu/aarch64 KERNEL ASPACE START. + * Update Hypercall API. + * Remove unused rt_hw_set_gtimer_frq. +* **Cortex-M33:** + * Fix the M33 assembly syntax errors and fix the compilation error of BSP. + * Added HardFault_Handler to save floating point registers. +* **Cortex-M4:** + * Fixed compilation error. + * Added HardFault_Handler to save floating point registers. + +* **Cortex-M3:** + * The parameter passed to the unified rt_exception_hook is exception_stack. [(#10619)](https://github.com/RT-Thread/rt-thread/pull/10619) +* **RISC-V:** + * Fix type mismatch of `_query`. + * Fix the support for RV32E. RV32E does not support the s2 register. Modify it to the s1 register. + * Use volatile RW for claim and complete. + * Add spaces to fix `Wliteral-suffix`. + * Add comment for the round down of symb_pc. + * Remove `rt_hw_cpu_id` in `cpuport.h` to fix error. + +## Tools + +* Add support for package.json, refactor BuildPackage function to handle new format. +* Add documents for tools script; Add NG for tools. [(#10572)](https://github.com/RT-Thread/rt-thread/pull/10572) +* Add workspace generation for RT-Thread root directory. +* Add vsc_workspace target in scons. +* Add DTC (Devicetree Compiler) tools. +* Add clang-format formatting script for CI. +* Optimize the file opening method. +* Clang format ignore migration. +* Improve[clang-format]: optimize the formatting logic for RT-Thread coding standard. + +## Action + +* Fixed CI: ARDUINO_ADAFRUIT_SENSORLAB compilation failure issue. +* Fixed CI compilation failure in sal/src/sal_socket.c.[(#10854)](https://github.com/RT-Thread/rt-thread/pull/10854) +* Merge same tag with different paths, remove Path display from CI comment. +* Add Copilot review title keywords. +* Add concurrency control to GitHub Actions. [(#10761)](https://github.com/RT-Thread/rt-thread/pull/10761) +* integrate utest run ci. [(#10748)](https://github.com/RT-Thread/rt-thread/pull/10748) +* Improve the comment instructions for the PR format bot.[(#10747)](https://github.com/RT-Thread/rt-thread/pull/10747) + +## Documents + +* **Doxygen:** + * Fix some document issues. + * Update naming rule for utest-case. + * Update doc for env to latest. + * Update some document content. + * Group name all in lowercase. [(#10530)](https://github.com/RT-Thread/rt-thread/pull/10530) + * Grouping and page optimization related to device driver. + * use layout to control the HTML display. + * Add doxygen comments for scheduler. [(#10366)](https://github.com/RT-Thread/rt-thread/pull/10366) and lwp + * update doxygen version to v1.9.8 . + +## Utest + +* Add netdev/lwip/filesystem/memory pool/SAL/system performance API test case. +* Support autocomplete of utest cases for `utest_run`. [(#10701)](https://github.com/RT-Thread/rt-thread/pull/10701) +* Feat:reorganize utest menu. +* Feat:rename files and update naming according to new rule. +* Feat:reorganize utest framework structure (initial version). +* Feat:unify config name. [(#10808)](https://github.com/RT-Thread/rt-thread/pull/10808) +* Feat:integrate test cases into utest framework. [(#10665)](https://github.com/RT-Thread/rt-thread/pull/10665) +* Move driver-related test cases under `drivers`. +* Move and enhance C++ test cases. + +## BSP + +* Some driver issues have been resolved and some driver support has been added. + +* **Added/Updated BSPs:** + + * **xuantie：** + * E901 + + * **Renesas:** + * ek-ra6e2 + * ek-ra4e2 + * ek-ra2a1 + * ek-ra2e2 + * ek-ra4m1 + * **GD32:** + * gd32h759i-eval + * gd32470i-eval + * gd32e230-lckfb + * **NXP:** + * MCX E247 + * FRDM-MCXE247 + * FRDM-MCXA346 + * **HPMicro:** + * hpm6p00evk + * hpm5e00evk + * **Phytium** + * **Raspberry RP2350** + # RT-Thread v5.2.1 Released Change Log Since v5.2.0 Release -- Gitee From 931045879d7930f3741cb482ea94b9117eeec7e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=9F=B3=E9=B8=BF=E8=B6=85?= <13010364+shi-hongchao@user.noreply.gitee.com> Date: Wed, 10 Dec 2025 11:16:37 +0800 Subject: [PATCH 02/45] =?UTF-8?q?feat(bsp/gd32):=20=E5=A2=9E=E5=8A=A0GDF0R?= =?UTF-8?q?G=E8=8A=AF=E7=89=87BSP?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/gd32/arm/gd32405rg/.config | 1457 ++++++++ bsp/gd32/arm/gd32405rg/.gitignore | 3 + bsp/gd32/arm/gd32405rg/Kconfig | 12 + bsp/gd32/arm/gd32405rg/README.md | 107 + .../arm/gd32405rg/README_assets/image.png | Bin 0 -> 96755 bytes .../gd32405rg/RTE/_rt-thread/RTE_Components.h | 20 + bsp/gd32/arm/gd32405rg/SConscript | 15 + bsp/gd32/arm/gd32405rg/SConstruct | 77 + .../arm/gd32405rg/applications/SConscript | 15 + bsp/gd32/arm/gd32405rg/applications/main.c | 35 + bsp/gd32/arm/gd32405rg/board/Kconfig | 354 ++ bsp/gd32/arm/gd32405rg/board/SConscript | 17 + bsp/gd32/arm/gd32405rg/board/board.c | 173 + bsp/gd32/arm/gd32405rg/board/board.h | 47 + .../arm/gd32405rg/board/gd32f4xx_libopt.h | 45 + .../gd32405rg/board/linker_scripts/link.icf | 40 + .../gd32405rg/board/linker_scripts/link.ld | 143 + .../gd32405rg/board/linker_scripts/link.sct | 18 + bsp/gd32/arm/gd32405rg/figures/board.jpg | Bin 0 -> 98061 bytes bsp/gd32/arm/gd32405rg/project.ewd | 3056 +++++++++++++++++ bsp/gd32/arm/gd32405rg/project.ewp | 2196 ++++++++++++ bsp/gd32/arm/gd32405rg/project.ewt | 3040 ++++++++++++++++ bsp/gd32/arm/gd32405rg/project.eww | 10 + bsp/gd32/arm/gd32405rg/project.uvoptx | 1075 ++++++ bsp/gd32/arm/gd32405rg/project.uvproj | 1270 +++++++ bsp/gd32/arm/gd32405rg/project.uvprojx | 2319 +++++++++++++ bsp/gd32/arm/gd32405rg/rtconfig.h | 430 +++ bsp/gd32/arm/gd32405rg/rtconfig.py | 151 + bsp/gd32/arm/gd32405rg/template.ewp | 1889 ++++++++++ bsp/gd32/arm/gd32405rg/template.uvoptx | 185 + bsp/gd32/arm/gd32405rg/template.uvproj | 628 ++++ bsp/gd32/arm/gd32405rg/template.uvprojx | 414 +++ 32 files changed, 19241 insertions(+) create mode 100644 bsp/gd32/arm/gd32405rg/.config create mode 100644 bsp/gd32/arm/gd32405rg/.gitignore create mode 100644 bsp/gd32/arm/gd32405rg/Kconfig create mode 100644 bsp/gd32/arm/gd32405rg/README.md create mode 100644 bsp/gd32/arm/gd32405rg/README_assets/image.png create mode 100644 bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h create mode 100644 bsp/gd32/arm/gd32405rg/SConscript create mode 100644 bsp/gd32/arm/gd32405rg/SConstruct create mode 100644 bsp/gd32/arm/gd32405rg/applications/SConscript create mode 100644 bsp/gd32/arm/gd32405rg/applications/main.c create mode 100644 bsp/gd32/arm/gd32405rg/board/Kconfig create mode 100644 bsp/gd32/arm/gd32405rg/board/SConscript create mode 100644 bsp/gd32/arm/gd32405rg/board/board.c create mode 100644 bsp/gd32/arm/gd32405rg/board/board.h create mode 100644 bsp/gd32/arm/gd32405rg/board/gd32f4xx_libopt.h create mode 100644 bsp/gd32/arm/gd32405rg/board/linker_scripts/link.icf create mode 100644 bsp/gd32/arm/gd32405rg/board/linker_scripts/link.ld create mode 100644 bsp/gd32/arm/gd32405rg/board/linker_scripts/link.sct create mode 100644 bsp/gd32/arm/gd32405rg/figures/board.jpg create mode 100644 bsp/gd32/arm/gd32405rg/project.ewd create mode 100644 bsp/gd32/arm/gd32405rg/project.ewp create mode 100644 bsp/gd32/arm/gd32405rg/project.ewt create mode 100644 bsp/gd32/arm/gd32405rg/project.eww create mode 100644 bsp/gd32/arm/gd32405rg/project.uvoptx create mode 100644 bsp/gd32/arm/gd32405rg/project.uvproj create mode 100644 bsp/gd32/arm/gd32405rg/project.uvprojx create mode 100644 bsp/gd32/arm/gd32405rg/rtconfig.h create mode 100644 bsp/gd32/arm/gd32405rg/rtconfig.py create mode 100644 bsp/gd32/arm/gd32405rg/template.ewp create mode 100644 bsp/gd32/arm/gd32405rg/template.uvoptx create mode 100644 bsp/gd32/arm/gd32405rg/template.uvproj create mode 100644 bsp/gd32/arm/gd32405rg/template.uvprojx diff --git a/bsp/gd32/arm/gd32405rg/.config b/bsp/gd32/arm/gd32405rg/.config new file mode 100644 index 0000000000..c74192943e --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/.config @@ -0,0 +1,1457 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER=y +CONFIG_PKG_GD32_ARM_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/gd32/gd32-arm-cmsis" +CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_GD32_ARM_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER=y +CONFIG_PKG_GD32_ARM_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/gd32/gd32-arm-series" +CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_GD32_ARM_SERIES_DRIVER_VER="latest" +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_GD32=y +CONFIG_SOC_SERIES_GD32F4xx=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_GD32405RG=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_USBD is not set +# CONFIG_BSP_USING_USBH is not set +CONFIG_BSP_USING_GD_DBG=y +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/gd32/arm/gd32405rg/.gitignore b/bsp/gd32/arm/gd32405rg/.gitignore new file mode 100644 index 0000000000..afea5775a7 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/.gitignore @@ -0,0 +1,3 @@ +compile_commands* +*.uvguix.* +EventRecorderStub.* diff --git a/bsp/gd32/arm/gd32405rg/Kconfig b/bsp/gd32/arm/gd32405rg/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/gd32/arm/gd32405rg/README.md b/bsp/gd32/arm/gd32405rg/README.md new file mode 100644 index 0000000000..c131b286a9 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/README.md @@ -0,0 +1,107 @@ +# GD32405RG BSP说明 + +## 简介 + +GD32405RG是-兆易创新推出的一款GD32F4XX系列的MCU，最高主频高达168M。参考GD32F407V-START开发板BSP + +开发板外观如下图所示(仅芯片，没有开发板图片，下图为GD32407V-START开发板)： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- GD32405RGT6，主频 168MHz，1024KB FLASH ，128KB RAM + 64KB TCMRAM (其他F4 BSP的RAM存在问题，实际的RAM布局应该像我这样) + ![memrey map](README_assets/image.png) + +- 常用接口：USB 接口 + +- 调试接口：DAP-LINK + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------------------------------ | +| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...81 | +| UART | 支持 | UART0 - UART5 | +| I2C | 支持 | I2C1 | +| SPI | 支持 | SPI0 -  SPI2 | +| SPI FLASH | 支持 | | +| ADC | 支持 | ADC0 - ADC2 | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发，IAR/MDK4未做修改，如果您使用IAR/MDK4需要做一些简单修改。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，使用USB转TTL模块连接PA2(MCU TX)和PA3(MCU RX)，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 DAP-Link 仿真器下载程序，在通过 DAP-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Jan 9 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口0的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5` 命令重新生成工程，或者使用Scons构建 + +## 注意事项 + +1. 该BSP使用的外部高速时钟为8MHz，PLL倍频到200MHz，请根据实际情况进行时钟配置。 + board/SConscript中，请根据实际情况修改HXTAL_VALUE： + ```python + CPPDEFINES = ['GD32F405', 'HXTAL_VALUE=8000000U'] + ``` + board/board.c中，根据实际情况修改`system_clock_8M_200M`实现： + ```c + void rt_hw_board_init() + { + /* config system clock HSE 8M to 200M */ + system_clock_8M_200M(); + + ``` + +## 联系人信息 + +维护人: + +- [ShiHongchao](https://gitee.com/shi-hongchao), 邮箱： 或者 diff --git a/bsp/gd32/arm/gd32405rg/README_assets/image.png b/bsp/gd32/arm/gd32405rg/README_assets/image.png new file mode 100644 index 0000000000000000000000000000000000000000..ecafcce5ee48d6db1864c9dbb1e80614e56a68ad GIT binary patch literal 96755 zcmbrmbySsa^gVb%q(eYL8c9J)=~h5MxH_kHgBK5@=Id+&3DRh4D&uqm(+2n3$IoU}RuftrUvpv+;S z!cXo!=IcNp=n(SKk2Kv-whS>0Zp)8xS((VS(g`uVP<>a-`t;VLn`*%!XpbJDklaAO zjV7O&VG?1Y&7Jk(Zpa4|hPzf#j4vn%175UGf1942HjFQ+lb>@OBh&xg#MUP-Ad@HiTJQU+=xn?AeZd_~3z6PeNLv`|qB0^Sp-<3pW@B zd~S7$dfk7xA21)bzWxH^!9$gUbes;IDc4(_J)+SSw)zGJRKCR$o+l0o%~#%!(B9)w z9^JIPn$aRgTip2F!+_;!f`(*4E#>TEVj@7URxK56<6s)pr8KzxGwVU7CvRQ8_v%4< zeKudWl93Le? z=|MI~E&F7V_8<*uHSV`ydOo~xAMpvsxW^0eWr6S2Rg(4Z#BpTvBrvA%6A&n8>*K92IyzB7& zE?X2T-@lW^zbRW`&sDb714UyNMw)6%slxWIDEWq z^m6GnT7~%D*V=qK7Llw!rx%ffuWX9D8xrmf{1}SKWOrXhi|}wQ+mp+zM%MYBKb@=F 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zCLwfiu^}UVLkI%oy$)&v&VG=VO+j7fsd$yqk{$~w_nUqrCWd4VZVlh1q=`*h`b=lV134|5&QI|f%meyGJ=QeC)y?zc?dHIa){V%PD+xh>{ddx4fmHFuS zxV{URWGykT9`0bh+t(2H>tto)4Q|IgCY?K<5TweawM1!muH%cGT8-O$B$F+9lkh+a zpZDmXrFZ&+WHqHZ$D$TY(v_TEk%gY~;LNiE( zPC~D0Zfjs-!~R&46^l$_=gFY19~-`ZTsg$P>%2Iu(W6JE;$#g3vj|q~imc!nh1i!x Y;|}tL{22;}TZMmio9s2dM|O?;A2nT-%m4rY literal 0 HcmV?d00001 diff --git a/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h b/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h new file mode 100644 index 0000000000..29cf3e0e73 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h @@ -0,0 +1,20 @@ +/* + * UVISION generated file: DO NOT EDIT! + * Generated by: uVision version 5.42.0.0 + * + * Project: 'template' + * Target: 'rt-thread' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "gd32f4xx.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/bsp/gd32/arm/gd32405rg/SConscript b/bsp/gd32/arm/gd32405rg/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/gd32/arm/gd32405rg/SConstruct b/bsp/gd32/arm/gd32405rg/SConstruct new file mode 100644 index 0000000000..72997f103f --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/SConstruct @@ -0,0 +1,77 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "gd32-arm-cmsis-latest"), + os.path.join("packages", "gd32-arm-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('env') +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# include drivers with specific build directory +drivers_objs = SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript'), + variant_dir='build/libraries/gd32_drivers', + duplicate=0) +objs.extend(drivers_objs) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/gd32/arm/gd32405rg/applications/SConscript b/bsp/gd32/arm/gd32405rg/applications/SConscript new file mode 100644 index 0000000000..9bb9abae89 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/gd32/arm/gd32405rg/applications/main.c b/bsp/gd32/arm/gd32405rg/applications/main.c new file mode 100644 index 0000000000..73777282de --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/applications/main.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 BruceOu first implementation + */ + +#include +#include +#include +#include + +/* defined the LED2 pin: PB5 */ +#define LED2_PIN GET_PIN(B, 5) + +int main(void) +{ + int count = 1; + + /* set LED2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/gd32/arm/gd32405rg/board/Kconfig b/bsp/gd32/arm/gd32405rg/board/Kconfig new file mode 100644 index 0000000000..f62e148f3c --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/Kconfig @@ -0,0 +1,354 @@ +menu "Hardware Drivers Config" + +config SOC_SERIES_GD32F4xx + bool + default y + +config SOC_GD32405RG + bool + select SOC_SERIES_GD32F4xx + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 + default 64 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 + default 0 + + config BSP_UART0_DMA_PING_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA + default 32 + + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 + default 64 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 + default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 32 + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 + default 64 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 + default 0 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 32 + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 + default 64 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 + default 0 + + config BSP_UART3_DMA_PING_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA + default 32 + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 + default 64 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 + default 0 + + config BSP_UART4_DMA_PING_BUFSIZE + int "Set UART4 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA + default 32 + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 + default 64 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 + default 0 + + config BSP_UART5_DMA_PING_BUFSIZE + int "Set UART5 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA + default 32 + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM10 + bool "Enable TIM10" + default n + + config BSP_USING_TIM11 + bool "Enable TIM11" + default n + + config BSP_USING_TIM12 + bool "Enable TIM13" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + config BSP_USING_ALARM + bool "Enable RTC alarm" + select RT_USING_ALARM + default n + if BSP_USING_ALARM + choice + prompt "Select rtc alarm device" + default BSP_USING_ALARM0 + + config BSP_USING_ALARM0 + bool "Enable RTC Alarm0" + + config BSP_USING_ALARM1 + bool "Enable RTC Alarm1" + endchoice + endif + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + + source "$(BSP_DIR)/../libraries/gd32_drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/gd32/arm/gd32405rg/board/SConscript b/bsp/gd32/arm/gd32405rg/board/SConscript new file mode 100644 index 0000000000..409d6be0ae --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/SConscript @@ -0,0 +1,17 @@ +import os +import rtconfig +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +CPPDEFINES = ['GD32F405', 'HXTAL_VALUE=8000000U'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/gd32/arm/gd32405rg/board/board.c b/bsp/gd32/arm/gd32405rg/board/board.c new file mode 100644 index 0000000000..54923688ab --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/board.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 BruceOu first implementation + * 2024-03-19 Evlers add serial supports + */ +#include +#include +#include +#include + +#ifdef RT_USING_SERIAL_V2 +#include "drv_usart_v2.h" +#else +#include "drv_usart.h" +#endif + + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + NVIC_SetPriority(SysTick_IRQn, 0); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void system_clock_8M_200M(void); + +/** + * This function will initial GD32 board. + */ +void rt_hw_board_init() +{ + /* config system clock HSE 8M to 200M */ + system_clock_8M_200M(); + + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + /* Set the Vector Table base location at 0x08000000 */ + SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); +#endif + + SystemClock_Config(); + +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + +#ifdef BSP_USING_SDRAM + rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); +#else + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/** + * @brief config system clock HSE 8M PLL to 200M + * @param none + */ +static void system_clock_8M_200M(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* reset RCU */ + rcu_deinit(); + + /* enable HXTAL */ + RCU_CTL |= RCU_CTL_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do{ + timeout++; + stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); + }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + + /* if fail */ + if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ + while(1){ + } + } + + RCU_APB1EN |= RCU_APB1EN_PMUEN; + PMU_CTL |= PMU_CTL_LDOVS; + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/4 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; + + /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ + RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | + (RCU_PLLSRC_HXTAL) | (9U << 24U)); + + /* enable PLL */ + RCU_CTL |= RCU_CTL_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ + } + + /* Enable the high-drive to extend the clock frequency to 200 Mhz */ + PMU_CTL |= PMU_CTL_HDEN; + while(0U == (PMU_CS & PMU_CS_HDRF)){ + } + + /* select the high-drive mode */ + PMU_CTL |= PMU_CTL_HDS; + while(0U == (PMU_CS & PMU_CS_HDSRF)){ + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLLP; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ + } + + /* Update SystemCoreClock variable */ + SystemCoreClock = 200000000U; // 200MHz +} + +/*@}*/ diff --git a/bsp/gd32/arm/gd32405rg/board/board.h b/bsp/gd32/arm/gd32405rg/board/board.h new file mode 100644 index 0000000000..2e56f9cbf4 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/board.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-20 BruceOu first implementation + * 2024-03-19 Evlers remove the include of drv_usart.h + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "gd32f4xx.h" +#include "drv_gpio.h" + +#include "gd32f4xx_exti.h" + +#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */ +#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ + +// Internal SRAM memory size[Kbytes] <8-64> +// Default: 64 +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +extern char __ICFEDIT_region_RAM_end__; +#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ +#else +#define GD32_SRAM_SIZE 128 +#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) +#endif + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END GD32_SRAM_END + +#endif + diff --git a/bsp/gd32/arm/gd32405rg/board/gd32f4xx_libopt.h b/bsp/gd32/arm/gd32405rg/board/gd32f4xx_libopt.h new file mode 100644 index 0000000000..d26e3d15ec --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/gd32f4xx_libopt.h @@ -0,0 +1,45 @@ +/*! + \file gd32f4xx_libopt.h + \brief library optional for gd32f4xx +*/ + +/* + Copyright (C) 2016 GigaDevice + + 2016-10-19, V1.0.0, firmware for GD32F4xx +*/ + +#ifndef GD32F4XX_LIBOPT_H +#define GD32F4XX_LIBOPT_H +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_adc.h" +#include "gd32f4xx_can.h" +#include "gd32f4xx_crc.h" +#include "gd32f4xx_ctc.h" +#include "gd32f4xx_dac.h" +#include "gd32f4xx_dbg.h" +#include "gd32f4xx_dci.h" +#include "gd32f4xx_dma.h" +//#include "gd32f4xx_enet.h" +#include "gd32f4xx_exmc.h" +#include "gd32f4xx_exti.h" +#include "gd32f4xx_fmc.h" +#include "gd32f4xx_fwdgt.h" +#include "gd32f4xx_gpio.h" +#include "gd32f4xx_syscfg.h" +#include "gd32f4xx_i2c.h" +#include "gd32f4xx_ipa.h" +#include "gd32f4xx_iref.h" +#include "gd32f4xx_pmu.h" +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_rtc.h" +#include "gd32f4xx_sdio.h" +#include "gd32f4xx_spi.h" +#include "gd32f4xx_timer.h" +#include "gd32f4xx_tli.h" +#include "gd32f4xx_trng.h" +#include "gd32f4xx_usart.h" +#include "gd32f4xx_wwdgt.h" +#include "gd32f4xx_misc.h" + +#endif /* GD32F4XX_LIBOPT_H */ diff --git a/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.icf b/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.icf new file mode 100644 index 0000000000..c38df1f506 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +export symbol __ICFEDIT_region_RAM_end__; + +define symbol __region_RAM1_start__ = 0x10000000; +define symbol __region_RAM1_end__ = 0x1000FFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +keep { section .rti_fn* }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM1_region { section .sram }; diff --git a/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.ld b/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.ld new file mode 100644 index 0000000000..2505b86d57 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.ld @@ -0,0 +1,143 @@ +/* + * linker script for GD32F4xx with GNU ld + * BruceOu 2021-12-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */ + TCMDATA (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 128KB tcmsram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.sct b/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.sct new file mode 100644 index 0000000000..3116818f02 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/linker_scripts/link.sct @@ -0,0 +1,18 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data at SRAM + .ANY (+RW +ZI) + } + RW_IRAM2 0x10000000 0x00010000 { ; RW data at TCMSRAM + .ANY (+RW +ZI) + } +} + diff --git a/bsp/gd32/arm/gd32405rg/figures/board.jpg b/bsp/gd32/arm/gd32405rg/figures/board.jpg new file mode 100644 index 0000000000000000000000000000000000000000..4dece91b3ff233d6f3144f2237818a7c71dac171 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c + + + + + gd32f4xx_misc.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + + + gd32f4xx_rcu.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + + + gd32f4xx_syscfg.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + + + gd32f4xx_usart.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + + + + + diff --git a/bsp/gd32/arm/gd32405rg/project.uvprojx b/bsp/gd32/arm/gd32405rg/project.uvprojx new file mode 100644 index 0000000000..5d4e1c6e1d --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/project.uvprojx @@ -0,0 +1,2319 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + GD32F405RG + GigaDevice + GigaDevice.GD32F4xx_DFP.3.2.0 + https://gd32mcu.com/data/documents/pack/ + IRAM(0x20000000,0x020000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB -FS08000000 -FL0100000 -FP0($$Device:GD32F405RG$Flash\GD32F4xx_1MB.FLM)) + 0 + $$Device:GD32F405RG$Device\F4XX\Include\gd32f4xx.h + + + + + + + + + + $$Device:GD32F405RG$SVD\GD32F4xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + GD32F405, __CLK_TCK=RT_TICK_PER_SECOND, HXTAL_VALUE=8000000, RT_USING_LIBC, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, __RTTHREAD__ + + applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\phy;..\..\..\..\components\libc\compilers\common\extension;.;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\net\utest;..\..\..\..\include;..\..\..\..\components\drivers\include;board;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\smp_call;packages\gd32-arm-cmsis-latest\GD32F4xx;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;..\libraries\gd32_drivers;..\..\..\..\components\drivers\include;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\libcpu\arm\common;packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;..\..\..\..\components\drivers\include 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rt_vsnprintf_tiny.c + 1 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + kstring.c + 1 + ..\..\..\..\src\klibc\kstring.c + + + rt_vsscanf.c + 1 + ..\..\..\..\src\klibc\rt_vsscanf.c + + + kerrno.c + 1 + ..\..\..\..\src\klibc\kerrno.c + + + + + libcpu + + + atomic_arm.c + 1 + ..\..\..\..\libcpu\arm\common\atomic_arm.c + + + div0.c + 1 + ..\..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Libraries + + + startup_gd32f4xx.s + 2 + packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s + + + system_gd32f4xx.c + 1 + packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Source\system_gd32f4xx.c + + + gd32f4xx_dma.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c + + + gd32f4xx_exti.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + + + gd32f4xx_gpio.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + + + gd32f4xx_i2c.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c + + + gd32f4xx_misc.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + gd32f4xx_rcu.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + gd32f4xx_syscfg.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + gd32f4xx_usart.c + 1 + packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/gd32/arm/gd32405rg/rtconfig.h b/bsp/gd32/arm/gd32405rg/rtconfig.h new file mode 100644 index 0000000000..d143777126 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/rtconfig.h @@ -0,0 +1,430 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +#define PKG_USING_GD32_ARM_CMSIS_DRIVER +#define PKG_USING_GD32_ARM_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_GD32_ARM_SERIES_DRIVER +#define PKG_USING_GD32_ARM_SERIES_DRIVER_LATEST_VERSION +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_GD32 +#define SOC_SERIES_GD32F4xx + +/* Hardware Drivers Config */ + +#define SOC_GD32405RG + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_GD_DBG +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/gd32/arm/gd32405rg/rtconfig.py b/bsp/gd32/arm/gd32405rg/rtconfig.py new file mode 100644 index 0000000000..d37afd4c07 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/rtconfig.py @@ -0,0 +1,151 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + #DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F407xK' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' -S' + AFLAGS += ' --fpu VFPv4_sp' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/gd32/arm/gd32405rg/template.ewp b/bsp/gd32/arm/gd32405rg/template.ewp new file mode 100644 index 0000000000..c3cff156ac --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/template.ewp @@ -0,0 +1,1889 @@ + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 22 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/gd32/arm/gd32405rg/template.uvoptx b/bsp/gd32/arm/gd32405rg/template.uvoptx new file mode 100644 index 0000000000..1499ed81f2 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/template.uvoptx @@ -0,0 +1,185 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB.FLM -FS08000000 -FL0100000 -FP0($$Device:GD32F405RG$Flash\GD32F4xx_1MB.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F4xx_1MB -FL0100000 -FS08000000 -FP0($$Device:GD32F405RG$Flash\GD32F4xx_1MB.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/gd32/arm/gd32405rg/template.uvproj b/bsp/gd32/arm/gd32405rg/template.uvproj new file mode 100644 index 0000000000..deb72d33b0 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/template.uvproj @@ -0,0 +1,628 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 0 + + + GD32F407VK + GigaDevice + IRAM(0x20000000,0x020000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x300000) CPUTYPE("Cortex-M4") FPU2 CLOCK(25000000) + + "Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code") + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F407VK$Flash\GD32F4xx_3MB.FLM)) + 0 + gd32f4xx.h + + + + + + + + + + SFD\GD\GD32F4xx\GD32F4xx.SFR + 0 + 0 + + + + GD\GD32F4xx\ + GD\GD32F4xx\ + + 0 + 0 + 0 + 0 + 1 + + .\output\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 3 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 1 + 0x8000000 + 0x300000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x300000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x30000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application + + + main.c + 1 + ..\main.c + + + gd32f4xx_it.c + 1 + ..\gd32f4xx_it.c + + + + + CMSIS + + + system_gd32f4xx.c + 1 + ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c + + + + + GD32F4xx_Peripherals + + + gd32f4xx_adc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c + + + gd32f4xx_can.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c + + + gd32f4xx_crc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c + + + gd32f4xx_ctc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c + + + gd32f4xx_dac.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c + + + gd32f4xx_dbg.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c + + + gd32f4xx_dci.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c + + + gd32f4xx_dma.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c + + + gd32f4xx_enet.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c + + + gd32f4xx_exmc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c + + + gd32f4xx_exti.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c + + + gd32f4xx_fmc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c + + + gd32f4xx_fwdgt.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c + + + gd32f4xx_gpio.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c + + + gd32f4xx_i2c.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c + + + gd32f4xx_ipa.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c + + + gd32f4xx_iref.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c + + + gd32f4xx_misc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c + + + gd32f4xx_pmu.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c + + + gd32f4xx_rcu.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c + + + gd32f4xx_rtc.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c + + + gd32f4xx_sdio.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c + + + gd32f4xx_spi.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c + + + gd32f4xx_syscfg.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c + + + gd32f4xx_timer.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c + + + gd32f4xx_tli.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c + + + gd32f4xx_trng.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c + + + gd32f4xx_usart.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + + gd32f4xx_wwdgt.c + 1 + ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c + + + + + GD32F4xx_START + + + gd32f407r_start.c + 1 + ..\..\..\Library\Utilities\gd32f407r_start.c + + + + + Startup + + + startup_gd32f4xx.s + 2 + ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s + + + + + Doc + + + readme.txt + 5 + ..\readme.txt + + + + + + + + diff --git a/bsp/gd32/arm/gd32405rg/template.uvprojx b/bsp/gd32/arm/gd32405rg/template.uvprojx new file mode 100644 index 0000000000..27f58a77c5 --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/template.uvprojx @@ -0,0 +1,414 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + GD32F405RG + GigaDevice + GigaDevice.GD32F4xx_DFP.3.2.0 + https://gd32mcu.com/data/documents/pack/ + IRAM(0x20000000,0x020000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB -FS08000000 -FL0100000 -FP0($$Device:GD32F405RG$Flash\GD32F4xx_1MB.FLM)) + 0 + $$Device:GD32F405RG$Device\F4XX\Include\gd32f4xx.h + + + + + + + + + + $$Device:GD32F405RG$SVD\GD32F4xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\gd32_rom.ld + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + -- Gitee From eb7576d00f1c8d8c16fc97bedc3cbe74ce0fcbfa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=9F=B3=E9=B8=BF=E8=B6=85?= <13010364+shi-hongchao@user.noreply.gitee.com> Date: Tue, 6 Jan 2026 20:46:19 +0800 Subject: [PATCH 03/45] =?UTF-8?q?feat(bsp/gd32):=20=E6=B7=BB=E5=8A=A0PWM?= =?UTF-8?q?=E5=92=8C=E6=9B=B4=E5=A4=9A=E7=A1=AC=E4=BB=B6=E5=AE=9A=E6=97=B6?= =?UTF-8?q?=E5=99=A8=E6=94=AF=E6=8C=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - 在Kconfig中添加BSP_USING_PWM和BSP_USING_HWTIMER配置项 - 修正PWM时钟获取逻辑，使其能正确得到APB1/APB2上的定时器时钟源频率，添加在pwm结构体通道引脚资源配置项 - 修改硬件定时器初始化逻辑，修正定时器中断处理函数，适配GD32F4xx系列 - 在main.c中添加hwtimer_test和pwm_test测试函数 - 修复PWM和硬件定时器的依赖关系配置 --- bsp/gd32/arm/gd32405rg/.config | 19 +- bsp/gd32/arm/gd32405rg/applications/main.c | 102 +++ bsp/gd32/arm/gd32405rg/board/Kconfig | 120 +++- bsp/gd32/arm/gd32405rg/project.uvoptx | 214 ++++-- bsp/gd32/arm/gd32405rg/project.uvprojx | 163 ++++- bsp/gd32/arm/gd32405rg/rtconfig.h | 15 + .../arm/libraries/gd32_drivers/drv_hwtimer.c | 174 ++++- bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c | 652 ++++++++++-------- 8 files changed, 1064 insertions(+), 395 deletions(-) diff --git a/bsp/gd32/arm/gd32405rg/.config b/bsp/gd32/arm/gd32405rg/.config index c74192943e..d9defb3a43 100644 --- a/bsp/gd32/arm/gd32405rg/.config +++ b/bsp/gd32/arm/gd32405rg/.config @@ -254,7 +254,7 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set @@ -274,7 +274,7 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set -# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -1442,7 +1442,20 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set -# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_HWTIMER is not set +CONFIG_BSP_USING_PWM=y +CONFIG_BSP_USING_PWM0=y +CONFIG_BSP_USING_PWM1=y +CONFIG_BSP_USING_PWM2=y +CONFIG_BSP_USING_PWM3=y +CONFIG_BSP_USING_PWM4=y +CONFIG_BSP_USING_PWM7=y +CONFIG_BSP_USING_PWM8=y +CONFIG_BSP_USING_PWM9=y +CONFIG_BSP_USING_PWM10=y +CONFIG_BSP_USING_PWM11=y +CONFIG_BSP_USING_PWM12=y +CONFIG_BSP_USING_PWM13=y # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_SDIO is not set diff --git a/bsp/gd32/arm/gd32405rg/applications/main.c b/bsp/gd32/arm/gd32405rg/applications/main.c index 73777282de..fa263c7cca 100644 --- a/bsp/gd32/arm/gd32405rg/applications/main.c +++ b/bsp/gd32/arm/gd32405rg/applications/main.c @@ -33,3 +33,105 @@ int main(void) return RT_EOK; } + +#ifdef BSP_USING_HWTIMER +/* hwtimer callback function */ +static rt_err_t hwtimer_test_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +#define HWTIMER_DEV_NAME "timer13" + +/* hwtimer test */ +static void hwtimer_test(void) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; /* 定时器超时值 */ + rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ + rt_hwtimer_mode_t mode; /* 定时器模式 */ + rt_uint32_t freq = 10000; /* 计数频率 */ + + /* 查找定时器设备 */ + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return; + } + + /* 以读写方式打开设备 */ + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return; + } + + /* 设置超时回调函数 */ + rt_device_set_rx_indicate(hw_dev, hwtimer_test_cb); + + /* 设置计数频率(若未设置该项，默认为1Mhz 或 支持的最小计数频率) */ + rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq); + /* 设置模式为周期性定时器（若未设置，默认是HWTIMER_MODE_ONESHOT）*/ + mode = HWTIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return; + } + + /* 设置定时器超时值为5s并启动定时器 */ + timeout_s.sec = 5; /* 秒 */ + timeout_s.usec = 0; /* 微秒 */ + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return; + } +} +MSH_CMD_EXPORT(hwtimer_test, hwtimer test); +#endif //BSP_USING_HWTIMER + +#ifdef BSP_USING_PWM + +/* pwm test */ +static void pwm_test(void) +{ + rt_err_t ret = RT_EOK; + struct rt_device_pwm *pwm2 = RT_NULL, *pwm8 = RT_NULL, *pwm1 = RT_NULL, *pwm4 = RT_NULL; + rt_uint32_t period = 1000; /* 周期 */ + rt_uint32_t pulse = 500; /* 占空比 */ + + /* 查找PWM设备 */ + pwm2 = (struct rt_device_pwm *)rt_device_find("pwm2"); + if (pwm2 == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", "pwm2"); + return; + } + rt_pwm_set(pwm2, 3, period, pulse); + rt_pwm_enable(pwm2, 3); + rt_pwm_set(pwm2, 4, period, pulse); + rt_pwm_enable(pwm2, 4); + + pwm8 = (struct rt_device_pwm *)rt_device_find("pwm8"); + rt_pwm_set(pwm8, 2, period, pulse); + rt_pwm_enable(pwm8, 2); + + pwm1 = (struct rt_device_pwm *)rt_device_find("pwm1"); + rt_pwm_set(pwm1, 3, period, pulse); + rt_pwm_enable(pwm1, 3); + + pwm4 = (struct rt_device_pwm *)rt_device_find("pwm4"); + rt_pwm_set(pwm4, 1, period, pulse); + rt_pwm_enable(pwm4, 1); + rt_pwm_set(pwm4, 2, period, pulse); + rt_pwm_enable(pwm4, 2); +} +MSH_CMD_EXPORT(pwm_test, pwm test); +#endif // BSP_USING_PWM diff --git a/bsp/gd32/arm/gd32405rg/board/Kconfig b/bsp/gd32/arm/gd32405rg/board/Kconfig index f62e148f3c..ea08346a41 100644 --- a/bsp/gd32/arm/gd32405rg/board/Kconfig +++ b/bsp/gd32/arm/gd32405rg/board/Kconfig @@ -271,24 +271,134 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_TIM + menuconfig BSP_USING_HWTIMER bool "Enable timer" default n select RT_USING_HWTIMER - if BSP_USING_TIM - config BSP_USING_TIM10 + if BSP_USING_HWTIMER + config BSP_USING_HWTIMER0 + bool "Enable TIM0" + default n + + config BSP_USING_HWTIMER1 + bool "Enable TIM1" + default n + + config BSP_USING_HWTIMER2 + bool "Enable TIM2" + default n + + config BSP_USING_HWTIMER3 + bool "Enable TIM3" + default n + + config BSP_USING_HWTIMER4 + bool "Enable TIM4" + default n + + config BSP_USING_HWTIMER5 + bool "Enable TIM5" + default n + + config BSP_USING_HWTIMER6 + bool "Enable TIM6" + default y + + config BSP_USING_HWTIMER7 + bool "Enable TIM7" + default n + + config BSP_USING_HWTIMER8 + bool "Enable TIM8" + default n + + config BSP_USING_HWTIMER9 + bool "Enable TIM9" + default n + + config BSP_USING_HWTIMER10 bool "Enable TIM10" default n - config BSP_USING_TIM11 + config BSP_USING_HWTIMER11 bool "Enable TIM11" default n - config BSP_USING_TIM12 + config BSP_USING_HWTIMER12 + bool "Enable TIM12" + default n + + config BSP_USING_HWTIMER13 bool "Enable TIM13" default n endif + menuconfig BSP_USING_PWM + bool "Enable pwm" + select RT_USING_PWM + default n + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0" + depends on !BSP_USING_HWTIMER0 + default n + + config BSP_USING_PWM1 + bool "Enable PWM1" + depends on !BSP_USING_HWTIMER1 + default n + + config BSP_USING_PWM2 + bool "Enable PWM2" + depends on !BSP_USING_HWTIMER2 + default n + + config BSP_USING_PWM3 + bool "Enable PWM3" + depends on !BSP_USING_HWTIMER3 + default n + + config BSP_USING_PWM4 + bool "Enable PWM4" + depends on !BSP_USING_HWTIMER4 + default n + + config BSP_USING_PWM7 + bool "Enable PWM7" + depends on !BSP_USING_HWTIMER7 + default n + + config BSP_USING_PWM8 + bool "Enable PWM8" + depends on !BSP_USING_HWTIMER8 + default n + + config BSP_USING_PWM9 + bool "Enable PWM9" + depends on !BSP_USING_HWTIMER9 + default n + + config BSP_USING_PWM10 + bool "Enable PWM10" + depends on !BSP_USING_HWTIMER10 + default n + + config BSP_USING_PWM11 + bool "Enable PWM11" + depends on !BSP_USING_HWTIMER11 + default n + + config BSP_USING_PWM12 + bool "Enable PWM12" + depends on !BSP_USING_HWTIMER12 + default n + + config BSP_USING_PWM13 + bool "Enable PWM13" + depends on !BSP_USING_HWTIMER13 + default n + endif + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC diff --git a/bsp/gd32/arm/gd32405rg/project.uvoptx b/bsp/gd32/arm/gd32405rg/project.uvoptx index 39aa7f55fb..e8e6ea1538 100644 --- a/bsp/gd32/arm/gd32405rg/project.uvoptx +++ b/bsp/gd32/arm/gd32405rg/project.uvoptx @@ -193,9 +193,13 @@ - System Viewer\RCU + System Viewer\TIMER1 35905 + + System Viewer\TIMER2 + 35904 + @@ -349,6 +353,18 @@ 0 0 0 + ..\..\..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 ..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c dev_i2c_bit_ops.c 0 @@ -356,7 +372,7 @@ 3 - 12 + 13 1 0 0 @@ -368,7 +384,7 @@ 3 - 13 + 14 1 0 0 @@ -380,7 +396,7 @@ 3 - 14 + 15 1 0 0 @@ -392,7 +408,7 @@ 3 - 15 + 16 1 0 0 @@ -404,7 +420,7 @@ 3 - 16 + 17 1 0 0 @@ -416,7 +432,7 @@ 3 - 17 + 18 1 0 0 @@ -428,7 +444,7 @@ 3 - 18 + 19 1 0 0 @@ -440,7 +456,7 @@ 3 - 19 + 20 1 0 0 @@ -452,7 +468,7 @@ 3 - 20 + 21 1 0 0 @@ -464,7 +480,7 @@ 3 - 21 + 22 1 0 0 @@ -476,7 +492,7 @@ 3 - 22 + 23 1 0 0 @@ -488,7 +504,19 @@ 3 - 23 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\misc\rt_drv_pwm.c + rt_drv_pwm.c + 0 + 0 + + + 3 + 25 1 0 0 @@ -500,7 +528,7 @@ 3 - 24 + 26 1 0 0 @@ -520,7 +548,7 @@ 0 4 - 25 + 27 1 0 0 @@ -532,7 +560,7 @@ 4 - 26 + 28 1 0 0 @@ -544,7 +572,31 @@ 4 - 27 + 29 + 1 + 0 + 0 + 0 + ..\libraries\gd32_drivers\drv_hwtimer.c + drv_hwtimer.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\libraries\gd32_drivers\drv_pwm.c + drv_pwm.c + 0 + 0 + + + 4 + 31 1 0 0 @@ -564,49 +616,49 @@ 0 5 - 28 + 32 1 0 0 0 - ..\..\..\..\components\finsh\shell.c - shell.c + ..\..\..\..\components\finsh\msh_parse.c + msh_parse.c 0 0 5 - 29 + 33 1 0 0 0 - ..\..\..\..\components\finsh\msh.c - msh.c + ..\..\..\..\components\finsh\shell.c + shell.c 0 0 5 - 30 + 34 1 0 0 0 - ..\..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\..\components\finsh\msh.c + msh.c 0 0 5 - 31 + 35 1 0 0 0 - ..\..\..\..\components\finsh\msh_parse.c - msh_parse.c + ..\..\..\..\components\finsh\cmd.c + cmd.c 0 0 @@ -620,7 +672,7 @@ 0 6 - 32 + 36 1 0 0 @@ -632,7 +684,7 @@ 6 - 33 + 37 1 0 0 @@ -644,7 +696,7 @@ 6 - 34 + 38 1 0 0 @@ -656,7 +708,7 @@ 6 - 35 + 39 1 0 0 @@ -668,7 +720,7 @@ 6 - 36 + 40 1 0 0 @@ -680,7 +732,7 @@ 6 - 37 + 41 1 0 0 @@ -692,7 +744,7 @@ 6 - 38 + 42 1 0 0 @@ -704,7 +756,7 @@ 6 - 39 + 43 1 0 0 @@ -716,7 +768,7 @@ 6 - 40 + 44 1 0 0 @@ -728,7 +780,7 @@ 6 - 41 + 45 1 0 0 @@ -740,7 +792,7 @@ 6 - 42 + 46 1 0 0 @@ -752,7 +804,7 @@ 6 - 43 + 47 1 0 0 @@ -764,7 +816,7 @@ 6 - 44 + 48 1 0 0 @@ -776,7 +828,7 @@ 6 - 45 + 49 1 0 0 @@ -788,7 +840,7 @@ 6 - 46 + 50 1 0 0 @@ -808,61 +860,61 @@ 0 7 - 47 + 51 1 0 0 0 - ..\..\..\..\src\klibc\kstdio.c - kstdio.c + ..\..\..\..\src\klibc\kstring.c + kstring.c 0 0 7 - 48 + 52 1 0 0 0 - ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c - rt_vsnprintf_tiny.c + ..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c 0 0 7 - 49 + 53 1 0 0 0 - ..\..\..\..\src\klibc\kstring.c - kstring.c + ..\..\..\..\src\klibc\kerrno.c + kerrno.c 0 0 7 - 50 + 54 1 0 0 0 - ..\..\..\..\src\klibc\rt_vsscanf.c - rt_vsscanf.c + ..\..\..\..\src\klibc\kstdio.c + kstdio.c 0 0 7 - 51 + 55 1 0 0 0 - ..\..\..\..\src\klibc\kerrno.c - kerrno.c + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c 0 0 @@ -876,7 +928,7 @@ 0 8 - 52 + 56 1 0 0 @@ -888,7 +940,7 @@ 8 - 53 + 57 1 0 0 @@ -900,7 +952,7 @@ 8 - 54 + 58 1 0 0 @@ -912,7 +964,7 @@ 8 - 55 + 59 2 0 0 @@ -924,7 +976,7 @@ 8 - 56 + 60 1 0 0 @@ -938,13 +990,13 @@ Libraries - 0 + 1 0 0 0 9 - 57 + 61 2 0 0 @@ -956,7 +1008,7 @@ 9 - 58 + 62 1 0 0 @@ -968,7 +1020,7 @@ 9 - 59 + 63 1 0 0 @@ -980,7 +1032,7 @@ 9 - 60 + 64 1 0 0 @@ -992,7 +1044,7 @@ 9 - 61 + 65 1 0 0 @@ -1004,7 +1056,7 @@ 9 - 62 + 66 1 0 0 @@ -1016,7 +1068,7 @@ 9 - 63 + 67 1 0 0 @@ -1028,7 +1080,7 @@ 9 - 64 + 68 1 0 0 @@ -1040,7 +1092,7 @@ 9 - 65 + 69 1 0 0 @@ -1052,7 +1104,7 @@ 9 - 66 + 70 1 0 0 @@ -1062,6 +1114,18 @@ 0 0 + + 9 + 71 + 1 + 0 + 0 + 0 + .\packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c + gd32f4xx_timer.c + 0 + 0 + diff --git a/bsp/gd32/arm/gd32405rg/project.uvprojx b/bsp/gd32/arm/gd32405rg/project.uvprojx index 5d4e1c6e1d..9ab03ac12e 100644 --- a/bsp/gd32/arm/gd32405rg/project.uvprojx +++ b/bsp/gd32/arm/gd32405rg/project.uvprojx @@ -338,9 +338,9 @@ 0 - GD32F405, __CLK_TCK=RT_TICK_PER_SECOND, HXTAL_VALUE=8000000, RT_USING_LIBC, USE_STDPERIPH_DRIVER, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, __RTTHREAD__ + RT_USING_LIBC, HXTAL_VALUE=8000000U, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, GD32F405, __STDC_LIMIT_MACROS - applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\phy;..\..\..\..\components\libc\compilers\common\extension;.;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\net\utest;..\..\..\..\include;..\..\..\..\components\drivers\include;board;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\smp_call;packages\gd32-arm-cmsis-latest\GD32F4xx;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;..\libraries\gd32_drivers;..\..\..\..\components\drivers\include;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\libcpu\arm\common;packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;..\..\..\..\components\drivers\include + packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;packages\gd32-arm-cmsis-latest\GD32F4xx;.;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\net\utest;applications;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\drivers\phy;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;board;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\libcpu\arm\common;..\..\..\..\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\libraries\gd32_drivers;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\eventfd @@ -371,7 +371,7 @@ 0x08000000 0x20000000 - .\board\linker_scripts\link.sct + .\gd32_rom.ld @@ -495,6 +495,62 @@ + + hwtimer.c + 1 + ..\..\..\..\components\drivers\hwtimer\hwtimer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + dev_i2c_bit_ops.c 1 @@ -1167,6 +1223,62 @@ + + rt_drv_pwm.c + 1 + ..\..\..\..\components\drivers\misc\rt_drv_pwm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + dev_pin.c 1 @@ -1294,6 +1406,16 @@ 1 ..\libraries\gd32_drivers\drv_gpio.c + + drv_hwtimer.c + 1 + ..\libraries\gd32_drivers\drv_hwtimer.c + + + drv_pwm.c + 1 + ..\libraries\gd32_drivers\drv_pwm.c + drv_usart.c 1 @@ -1304,6 +1426,11 @@ Finsh + + msh_parse.c + 1 + ..\..\..\..\components\finsh\msh_parse.c + shell.c 1 @@ -1319,11 +1446,6 @@ 1 ..\..\..\..\components\finsh\cmd.c - - msh_parse.c - 1 - ..\..\..\..\components\finsh\msh_parse.c - @@ -2174,16 +2296,6 @@ klibc - - kstdio.c - 1 - ..\..\..\..\src\klibc\kstdio.c - - - rt_vsnprintf_tiny.c - 1 - ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c - kstring.c 1 @@ -2199,6 +2311,16 @@ 1 ..\..\..\..\src\klibc\kerrno.c + + kstdio.c + 1 + ..\..\..\..\src\klibc\kstdio.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + @@ -2284,6 +2406,11 @@ 1 packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + gd32f4xx_timer.c + 1 + .\packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c + diff --git a/bsp/gd32/arm/gd32405rg/rtconfig.h b/bsp/gd32/arm/gd32405rg/rtconfig.h index d143777126..598194241a 100644 --- a/bsp/gd32/arm/gd32405rg/rtconfig.h +++ b/bsp/gd32/arm/gd32405rg/rtconfig.h @@ -149,7 +149,9 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_I2C #define RT_USING_I2C_BITOPS +#define RT_USING_PWM #define RT_USING_PIN +#define RT_USING_HWTIMER /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -420,6 +422,19 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_USING_PWM +#define BSP_USING_PWM0 +#define BSP_USING_PWM1 +#define BSP_USING_PWM2 +#define BSP_USING_PWM3 +#define BSP_USING_PWM4 +#define BSP_USING_PWM7 +#define BSP_USING_PWM8 +#define BSP_USING_PWM9 +#define BSP_USING_PWM10 +#define BSP_USING_PWM11 +#define BSP_USING_PWM12 +#define BSP_USING_PWM13 #define BSP_USING_GD_DBG /* end of On-chip Peripheral Drivers */ diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c index 1c22b10467..bb53cd6b33 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c @@ -6,6 +6,10 @@ * Change Logs: * Date Author Notes * 2021-02-25 iysheng first version + * 2025-12-26 shihongchao Configure GD32F4xx chips interrupt handlers, + * relocate clock and interrupt initialization + * to the _init function, and implement deinit + * functionality */ #include @@ -114,16 +118,30 @@ static void __set_timerx_freq(uint32_t timerx, uint32_t freq) static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { uint32_t timer_base = (uint32_t)timer->parent.user_data; + gd32_hwtimer_device *hwtimer = rt_container_of(timer, gd32_hwtimer_device, hwtimer_dev); timer_parameter_struct initpara; if (state) { + rcu_periph_clock_enable(hwtimer->hw_data.rcu); + NVIC_SetPriority(hwtimer->hw_data.irqn, 0); + NVIC_EnableIRQ(hwtimer->hw_data.irqn); + timer_interrupt_enable(timer_base, TIMER_INT_UP); + timer_internal_clock_config(timer_base); timer_struct_para_init(&initpara); initpara.period = timer->info->maxcnt; timer_init(timer_base, &initpara); __set_timerx_freq(timer_base, timer->info->maxfreq); } + else + { + rcu_periph_clock_disable(hwtimer->hw_data.rcu); + NVIC_DisableIRQ(hwtimer->hw_data.irqn); + timer_interrupt_disable(timer_base, TIMER_INT_UP); + + timer_disable(timer_base); + } } static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \ @@ -200,7 +218,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer0", { TIMER0, +#ifdef SOC_SERIES_GD32F4xx + TIMER0_UP_TIMER9_IRQn, +#else TIMER0_UP_IRQn, +#endif RCU_TIMER0, }, {0}, @@ -285,7 +307,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer5", { TIMER5, +#ifdef SOC_SERIES_GD32F4xx + TIMER5_DAC_IRQn, +#else TIMER5_IRQn, +#endif RCU_TIMER5, }, {0}, @@ -319,7 +345,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer7", { TIMER7, +#ifdef SOC_SERIES_GD32F4xx + TIMER7_UP_TIMER12_IRQn, +#else TIMER7_UP_IRQn, +#endif RCU_TIMER7, }, {0}, @@ -336,7 +366,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer8", { TIMER8, +#ifdef SOC_SERIES_GD32F4xx + TIMER0_BRK_TIMER8_IRQn, +#else TIMER8_IRQn, +#endif RCU_TIMER8, }, {0}, @@ -353,7 +387,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer9", { TIMER9, +#ifdef SOC_SERIES_GD32F4xx + TIMER0_UP_TIMER9_IRQn, +#else TIMER9_IRQn, +#endif RCU_TIMER9, }, {0}, @@ -370,7 +408,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer10", { TIMER10, +#ifdef SOC_SERIES_GD32F4xx + TIMER0_TRG_CMT_TIMER10_IRQn, +#else TIMER10_IRQn, +#endif RCU_TIMER10, }, {0}, @@ -387,7 +429,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer11", { TIMER11, +#ifdef SOC_SERIES_GD32F4xx + TIMER7_BRK_TIMER11_IRQn, +#else TIMER11_IRQn, +#endif RCU_TIMER11, }, {0}, @@ -404,7 +450,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer12", { TIMER12, +#ifdef SOC_SERIES_GD32F4xx + TIMER7_UP_TIMER12_IRQn, +#else TIMER12_IRQn, +#endif RCU_TIMER12, }, {0}, @@ -421,7 +471,11 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { "timer13", { TIMER13, +#ifdef SOC_SERIES_GD32F4xx + TIMER7_TRG_CMT_TIMER13_IRQn, +#else TIMER13_IRQn, +#endif RCU_TIMER13, }, {0}, @@ -436,12 +490,31 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { }; #ifdef BSP_USING_HWTIMER0 +#ifdef SOC_SERIES_GD32F4xx +void TIMER0_UP_TIMER9_IRQHandler(void) +#else void TIMER0_UP_IRQHandler(void) +#endif { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \ +#ifdef BSP_USING_HWTIMER0 + if(timer_interrupt_flag_get((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP)) + { + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + } +#endif +#ifdef BSP_USING_HWTIMER9 + if(timer_interrupt_flag_get((uint32_t)g_gd32_hwtimer[TIM9_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP)) + { + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM9_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM9_INDEX].hwtimer_dev.parent.user_data, \ TIMER_INT_UP); + } +#endif rt_interrupt_leave(); } #endif @@ -491,7 +564,11 @@ void TIMER4_IRQHandler(void) #endif #ifdef BSP_USING_HWTIMER5 +#ifdef SOC_SERIES_GD32F4xx +void TIMER5_DAC_IRQHandler(void) +#else void TIMER5_IRQHandler(void) +#endif { rt_interrupt_enter(); rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev); @@ -512,7 +589,34 @@ void TIMER6_IRQHandler(void) } #endif +#ifdef SOC_SERIES_GD32F4xx +#if defined(BSP_USING_HWTIMER7) || defined(BSP_USING_HWTIMER12) +void TIMER7_UP_TIMER12_IRQHandler(void) +{ + rt_interrupt_enter(); #ifdef BSP_USING_HWTIMER7 + if(timer_interrupt_flag_get((uint32_t)g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP)) + { + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + } +#endif +#ifdef BSP_USING_HWTIMER12 + if(timer_interrupt_flag_get((uint32_t)g_gd32_hwtimer[TIM12_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP)) + { + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM12_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM12_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + } +#endif + rt_interrupt_leave(); +} +#endif +#else +#if defined(BSP_USING_HWTIMER7) void TIMER7_UP_IRQHandler(void) { rt_interrupt_enter(); @@ -522,6 +626,68 @@ void TIMER7_UP_IRQHandler(void) rt_interrupt_leave(); } #endif +#endif + + +#ifdef BSP_USING_HWTIMER8 +#ifdef SOC_SERIES_GD32F4xx +void TIMER0_BRK_TIMER8_IRQHandler(void) +#else +void TIMER8_UP_IRQHandler(void) +#endif +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM8_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM8_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIMER10 +#ifdef SOC_SERIES_GD32F4xx +void TIMER0_TRG_CMT_TIMER10_IRQHandler(void) +#else +void TIMER10_IRQHandler(void) +#endif +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM10_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM10_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIMER11 +#ifdef SOC_SERIES_GD32F4xx +void TIMER7_BRK_TIMER11_IRQHandler(void) +#else +void TIMER10_IRQHandler(void) +#endif +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM11_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM11_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_HWTIMER13 +#ifdef SOC_SERIES_GD32F4xx +void TIMER7_TRG_CMT_TIMER13_IRQHandler(void) +#else +void TIMER10_IRQHandler(void) +#endif +{ + rt_interrupt_enter(); + rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM13_INDEX].hwtimer_dev); + timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM13_INDEX].hwtimer_dev.parent.user_data, \ + TIMER_INT_UP); + rt_interrupt_leave(); +} +#endif static int rt_hwtimer_init(void) { @@ -532,10 +698,6 @@ static int rt_hwtimer_init(void) g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops; g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info; - rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu); - NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0); - NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn); - timer_interrupt_enable(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UP); ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \ g_gd32_hwtimer[i].dev_name, (void *)g_gd32_hwtimer[i].hw_data.reg_base); if (RT_EOK != ret) diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c index a95c5d634a..a0ef9eebd4 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_pwm.c @@ -6,15 +6,21 @@ * Change Logs: * Date Author Notes * 2023-06-05 zengjianwei first version - * 2025-06-23 Yucai Liu Support for non-complementary PWM output with advanced timers + * 2025-06-23 Yucai Liu Support for non-complementary PWM output with + * advanced timers + * 2025-12-26 shihongchao Optimize the timer clock frequency acquisition + * method; optimize the gd32_pwm structure to make + * it easier to configure; optimize the RCU enable + * logic; optimize GPIO configuration to maintain + * floating input mode when channels are disabled, + * reducing power consumption. */ #include -#include #include #include -#ifdef RT_USING_PWM +#ifdef BSP_USING_PWM /* #define DRV_DEBUG */ #define LOG_TAG "drv.pwm" @@ -24,208 +30,186 @@ #define MIN_PERIOD 3 #define MIN_PULSE 2 -typedef struct -{ - rt_int8_t TimerIndex; /* timer index:0~13 */ - rt_uint32_t Port; /* gpio port:GPIOA/GPIOB/GPIOC/... */ - rt_uint32_t pin; /* gpio pin:GPIO_PIN_0~GPIO_PIN_15 */ - /* timer channel: -2 is ch_1n, -1 is ch_0n, 0 is ch0, 1 is ch1 */ - rt_int16_t channel; - char *name; -} TIMER_PORT_CHANNEL_MAP_S; +typedef struct{ + uint32_t gpio_port; + uint32_t gpio_af; + uint16_t gpio_pin; +}channel_type; struct gd32_pwm { - struct rt_device_pwm pwm_device; - TIMER_PORT_CHANNEL_MAP_S tim_handle; + struct rt_device_pwm pwm_device; /* 继承pwm设备 */ + char *name; /* 设备名称 */ + uint32_t timerx; /* PWM依赖的的硬件定时器 */ + rcu_clock_freq_enum apb_of; /* TIMER从属的APB总线 */ + channel_type channels[4]; /* PWM通道 */ + channel_type nchannels[3]; /* PWM反相通道, 只有高级定时器支持 */ }; static struct gd32_pwm gd32_pwm_obj[] = { -#ifdef RT_USING_PWM1 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm1"}}, -#endif - -#ifdef RT_USING_PWM2 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm2"}}, -#endif - -#ifdef RT_USING_PWM3 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm3"}}, +#ifdef BSP_USING_PWM0 + { + .name = "pwm0", + .timerx = TIMER0, + .apb_of = CK_APB2, + .channels = { + {GPIOC, GPIO_AF_1, GPIO_PIN_0}, + {GPIOA, GPIO_AF_1, GPIO_PIN_1}, + {GPIOA, GPIO_AF_1, GPIO_PIN_2}, + {GPIOA, GPIO_AF_1, GPIO_PIN_3}, + }, + .nchannels = { + {GPIOB, GPIO_AF_1, GPIO_PIN_13}, + {GPIOB, GPIO_AF_1, GPIO_PIN_14}, + {GPIOB, GPIO_AF_1, GPIO_PIN_15}, + } + }, #endif -#ifdef RT_USING_PWM4 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm4"}}, +#ifdef BSP_USING_PWM1 + { + .name = "pwm1", + .timerx = TIMER1, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + {GPIOA, GPIO_AF_1, GPIO_PIN_1}, + {GPIOA, GPIO_AF_1, GPIO_PIN_2}, + {GPIOB, GPIO_AF_1, GPIO_PIN_2}, + }, + }, #endif -#ifdef RT_USING_PWM5 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm5"}}, +#ifdef BSP_USING_PWM2 + { + .name = "pwm2", + .timerx = TIMER2, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_6}, + {GPIOA, GPIO_AF_1, GPIO_PIN_7}, + {GPIOB, GPIO_AF_2, GPIO_PIN_0}, + {GPIOB, GPIO_AF_2, GPIO_PIN_1}, + }, + }, #endif -#ifdef RT_USING_PWM6 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm6"}}, +#ifdef BSP_USING_PWM3 + { + .name = "pwm3", + .timerx = TIMER3, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + {GPIOA, GPIO_AF_1, GPIO_PIN_1}, + {GPIOA, GPIO_AF_1, GPIO_PIN_2}, + {GPIOA, GPIO_AF_1, GPIO_PIN_3}, + }, + }, #endif -#ifdef RT_USING_PWM7 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm7"}}, +#ifdef BSP_USING_PWM4 + { + .name = "pwm4", + .timerx = TIMER4, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_2, GPIO_PIN_0}, + {GPIOA, GPIO_AF_2, GPIO_PIN_1}, + {GPIOA, GPIO_AF_1, GPIO_PIN_2}, + {GPIOA, GPIO_AF_1, GPIO_PIN_3}, + }, + }, #endif -#ifdef RT_USING_PWM8 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm8"}}, +#ifdef BSP_USING_PWM7 + { + .name = "pwm7", + .timerx = TIMER7, + .apb_of = CK_APB2, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + {GPIOA, GPIO_AF_1, GPIO_PIN_1}, + {GPIOC, GPIO_AF_1, GPIO_PIN_8}, + {GPIOA, GPIO_AF_1, GPIO_PIN_3}, + }, + .nchannels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_5}, + {GPIOB, GPIO_AF_1, GPIO_PIN_0}, + {GPIOB, GPIO_AF_1, GPIO_PIN_1}, + } + }, #endif -#ifdef RT_USING_PWM9 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm9"}}, +#ifdef BSP_USING_PWM8 + { + .name = "pwm8", + .timerx = TIMER8, + .apb_of = CK_APB2, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_2}, + {GPIOA, GPIO_AF_3, GPIO_PIN_3}, + }, // L1通用定时器为两通道定时器 + }, #endif -#ifdef RT_USING_PWM10 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm10"}}, +#ifdef BSP_USING_PWM9 + { + .name = "pwm9", + .timerx = TIMER9, + .apb_of = CK_APB2, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + }, // L2通用定时器为单通道定时器 + }, #endif -#ifdef RT_USING_PWM11 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm11"}}, +#ifdef BSP_USING_PWM10 + { + .name = "pwm10", + .timerx = TIMER10, + .apb_of = CK_APB2, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + }, // L2通用定时器为单通道定时器 + }, #endif -#ifdef RT_USING_PWM12 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm12"}}, +#ifdef BSP_USING_PWM11 + { + .name = "pwm11", + .timerx = TIMER11, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + {GPIOA, GPIO_AF_1, GPIO_PIN_1}, + }, // L1通用定时器为两通道定时器 + }, #endif -#ifdef RT_USING_PWM13 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm13"}}, +#ifdef BSP_USING_PWM12 + { + .name = "pwm12", + .timerx = TIMER12, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_0}, + }, // L2通用定时器为单通道定时器 + }, #endif -#ifdef RT_USING_PWM14 - {.tim_handle = {3, GPIOB, GPIO_PIN_8, 2, "pwm14"}}, +#ifdef BSP_USING_PWM13 + { + .name = "pwm13", + .timerx = TIMER13, + .apb_of = CK_APB1, + .channels = { + {GPIOA, GPIO_AF_1, GPIO_PIN_7}, + }, // L2通用定时器为单通道定时器 + }, #endif }; -typedef struct -{ - rt_uint32_t Port[7]; - rt_int8_t TimerIndex[14]; -} TIMER_PERIPH_LIST_S; - -static TIMER_PERIPH_LIST_S gd32_timer_periph_list = { - .Port = {0, 0, 0, 0, 0, 0, 0}, - .TimerIndex = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, -}; - -/* - * 将所有用到的 gpio port 和 timer 不重复地列举出来，以方便后面不重复地初始化 - */ -static rt_err_t pwm_find_timer_periph(void) -{ - rt_int16_t i, j, k; - - /* find gpio port of defined table */ - for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) - { - /* find -1 of gd32_periph_list's member of Port */ - for (j = 0; j < sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]); ++j) - { - if (0 == gd32_timer_periph_list.Port[j]) - { - break; - } - } - - if (j >= sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0])) - { - LOG_E("Can not find -1 of gd32_periph_list's member of Port!\n"); - break; - } - - /* find the different of Port */ - for (k = 0; k < j; ++k) - { - if (gd32_pwm_obj[i].tim_handle.Port == gd32_timer_periph_list.Port[k]) - { - break; - } - } - - /* if can not find the same Port */ - if (k == j) - { - gd32_timer_periph_list.Port[j] = gd32_pwm_obj[i].tim_handle.Port; - } - } - - /* find timer periph of defined table */ - for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) - { - /* find -1 of gd32_periph_list's member of TimerIndex */ - for (j = 0; j < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++j) - { - if (-1 == gd32_timer_periph_list.TimerIndex[j]) - { - break; - } - } - - if (j >= sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0])) - { - LOG_E("Can not find -1 of gd32_periph_list's member of TimerIndex!\n"); - break; - } - - /* find the different of TimerIndex */ - for (k = 0; k < j; ++k) - { - if (gd32_pwm_obj[i].tim_handle.TimerIndex == gd32_timer_periph_list.TimerIndex[k]) - { - break; - } - } - - /* if can not find the same TimerIndex */ - if (k == j) - { - gd32_timer_periph_list.TimerIndex[j] = gd32_pwm_obj[i].tim_handle.TimerIndex; - } - } - - return RT_EOK; -} - -static rt_uint32_t index_to_timer(rt_int8_t TimerIndex) -{ - switch (TimerIndex) - { - case 0: - return TIMER0; - case 1: - return TIMER1; - case 2: - return TIMER2; - case 3: - return TIMER3; - case 4: - return TIMER4; - case 5: - return TIMER5; - case 6: - return TIMER6; - case 7: - return TIMER7; - case 8: - return TIMER8; - case 9: - return TIMER9; - case 10: - return TIMER10; - case 11: - return TIMER11; - case 12: - return TIMER12; - case 13: - return TIMER13; - - default: - LOG_E("Unsport timer periph!\n"); - } - return TIMER0; -} - static void gpio_clock_enable(rt_uint32_t Port) { switch (Port) @@ -257,54 +241,52 @@ static void gpio_clock_enable(rt_uint32_t Port) } } -static void timer_clock_enable(rt_int8_t TimerIndex) +static void timer_clock_enable(uint32_t timer) { - switch (TimerIndex) + switch (timer) { - case 0: + case TIMER0: rcu_periph_clock_enable(RCU_TIMER0); break; - case 1: + case TIMER1: rcu_periph_clock_enable(RCU_TIMER1); break; - case 2: + case TIMER2: rcu_periph_clock_enable(RCU_TIMER2); break; - case 3: + case TIMER3: rcu_periph_clock_enable(RCU_TIMER3); break; - case 4: + case TIMER4: rcu_periph_clock_enable(RCU_TIMER4); break; - case 5: + case TIMER5: rcu_periph_clock_enable(RCU_TIMER5); break; - case 6: + case TIMER6: rcu_periph_clock_enable(RCU_TIMER6); break; - case 7: + case TIMER7: rcu_periph_clock_enable(RCU_TIMER7); break; -#ifndef GD32F30X_HD - case 8: + case TIMER8: rcu_periph_clock_enable(RCU_TIMER8); break; - case 9: + case TIMER9: rcu_periph_clock_enable(RCU_TIMER9); break; - case 10: + case TIMER10: rcu_periph_clock_enable(RCU_TIMER10); break; - case 11: + case TIMER11: rcu_periph_clock_enable(RCU_TIMER11); break; - case 12: + case TIMER12: rcu_periph_clock_enable(RCU_TIMER12); break; - case 13: + case TIMER13: rcu_periph_clock_enable(RCU_TIMER13); break; -#endif default: LOG_E("Unsport timer periph!\n"); } @@ -314,96 +296,168 @@ static void rcu_config(void) { rt_int16_t i; - for (i = 0; i < sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]); ++i) + for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) { - if (0 == gd32_timer_periph_list.Port[i]) + /* enable GPIO clock */ + switch (gd32_pwm_obj[i].timerx) { + /* 高级定时器 */ + case TIMER0: + case TIMER7: + gpio_clock_enable(gd32_pwm_obj[i].nchannels[0].gpio_port); + gpio_clock_enable(gd32_pwm_obj[i].nchannels[1].gpio_port); + gpio_clock_enable(gd32_pwm_obj[i].nchannels[2].gpio_port); + + /* L0 通用定时器 */ + case TIMER1: + case TIMER2: + case TIMER3: + case TIMER4: + gpio_clock_enable(gd32_pwm_obj[i].channels[2].gpio_port); + gpio_clock_enable(gd32_pwm_obj[i].channels[3].gpio_port); + + /* L1 通用定时器 */ + case TIMER8: + case TIMER11: + gpio_clock_enable(gd32_pwm_obj[i].channels[1].gpio_port); + + /* L2 通用定时器 */ + case TIMER9: + case TIMER10: + case TIMER12: + case TIMER13: + gpio_clock_enable(gd32_pwm_obj[i].channels[0].gpio_port); + break; + + default: + LOG_E("Unsport timer periph at rcu_config!\n"); break; } - - /* enable GPIO clock */ - gpio_clock_enable(gd32_timer_periph_list.Port[i]); } - rcu_periph_clock_enable(RCU_AF); - - for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i) + for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) { - if (-1 == gd32_timer_periph_list.TimerIndex[i]) - { - break; - } - /* enable timer clock */ - timer_clock_enable(gd32_timer_periph_list.TimerIndex[i]); - timer_deinit(index_to_timer(gd32_timer_periph_list.TimerIndex[i])); + timer_clock_enable(gd32_pwm_obj[i].timerx); + timer_deinit(gd32_pwm_obj[i].timerx); } } -static void gpio_config(void) +/** + * @brief 配置PWM输出引脚为pwm输出模式 + * @param pwm pwm 对象 + * @param configuration pwm驱动框架传递的配置信息 + */ +static void gpio_config_pwmout(const struct gd32_pwm *pwm, + const struct rt_pwm_configuration *configuration) { - rt_int16_t i; - - /* config the GPIO as analog mode */ - for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) + channel_type channel; + uint8_t channel_num = configuration->channel; + if(configuration->complementary) { - gpio_init(gd32_pwm_obj[i].tim_handle.Port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, gd32_pwm_obj[i].tim_handle.pin); + if(channel_num > 3) channel_num = 3; + channel = pwm->nchannels[channel_num-1]; } + else + { + if(channel_num > 4) channel_num = 4; + channel = pwm->channels[channel_num-1]; + } + gpio_mode_set(channel.gpio_port, GPIO_MODE_AF, GPIO_PUPD_NONE, channel.gpio_pin); + gpio_output_options_set(channel.gpio_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, channel.gpio_pin); + gpio_af_set(channel.gpio_port, channel.gpio_af, channel.gpio_pin); } -static void timer_init_para(timer_parameter_struct *initpara) +/** + * @brief 配置PWM输出引脚为pwm浮空输入模式 + * @param pwm pwm 对象 + * @param configuration pwm驱动框架传递的配置信息 + */ +static void gpio_config_input(const struct gd32_pwm *pwm, + const struct rt_pwm_configuration *configuration) { - rt_int16_t i; - - for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i) + channel_type channel = {0}; + uint8_t channel_num = configuration->channel; + if(configuration->complementary) { - /* config timer */ - if (-1 != gd32_timer_periph_list.TimerIndex[i]) - { - timer_init(index_to_timer(gd32_timer_periph_list.TimerIndex[i]), initpara); - } + if(channel_num > 3) channel_num = 3; + channel = pwm->nchannels[channel_num-1]; + } + else + { + if(channel_num > 4) channel_num = 4; + channel = pwm->channels[channel_num-1]; } + gpio_mode_set(channel.gpio_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, channel.gpio_pin); } -static void channel_output_config(timer_oc_parameter_struct *ocpara) +static void channel_output_config(rt_uint32_t timer_periph, timer_oc_parameter_struct *ocpara) { rt_int16_t i; - rt_uint32_t timer_periph; - /* config the channel config */ - for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) + switch (timer_periph) { - if (gd32_pwm_obj[i].tim_handle.channel < 0) - { - ocpara->outputstate = TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_ENABLE; - gd32_pwm_obj[i].tim_handle.channel = -(gd32_pwm_obj[i].tim_handle.channel + 1); - } - timer_periph = index_to_timer(gd32_pwm_obj[i].tim_handle.TimerIndex); - timer_channel_output_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, ocpara); + /* 高级定时器 */ + case TIMER0: + case TIMER7: + timer_primary_output_config(timer_periph, ENABLE); + + /* L0通用定时器 */ + case TIMER1: + case TIMER2: + case TIMER3: + case TIMER4: + timer_channel_output_config(timer_periph, TIMER_CH_2, ocpara); + timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_2, 7999); + timer_channel_output_mode_config(timer_periph, TIMER_CH_2, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(timer_periph, TIMER_CH_2, TIMER_OC_SHADOW_DISABLE); + /* auto-reload preload shadow reg enable */ + /* timer_auto_reload_shadow_enable(timer_periph); */ + timer_channel_output_state_config(timer_periph, TIMER_CH_2, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_2, TIMER_CCXN_DISABLE); - timer_channel_output_pulse_value_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, 7999); - timer_channel_output_mode_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_OC_MODE_PWM0); - timer_channel_output_shadow_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_OC_SHADOW_DISABLE); + timer_channel_output_config(timer_periph, TIMER_CH_3, ocpara); + timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_3, 7999); + timer_channel_output_mode_config(timer_periph, TIMER_CH_3, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(timer_periph, TIMER_CH_3, TIMER_OC_SHADOW_DISABLE); /* auto-reload preload shadow reg enable */ /* timer_auto_reload_shadow_enable(timer_periph); */ - timer_channel_output_state_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_CCX_DISABLE); - timer_channel_complementary_output_state_config(timer_periph, gd32_pwm_obj[i].tim_handle.channel, TIMER_CCXN_DISABLE); + timer_channel_output_state_config(timer_periph, TIMER_CH_3, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_3, TIMER_CCXN_DISABLE); + + /* L1通用定时器 */ + case TIMER8: + case TIMER11: + timer_channel_output_config(timer_periph, TIMER_CH_1, ocpara); + timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_1, 7999); + timer_channel_output_mode_config(timer_periph, TIMER_CH_1, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(timer_periph, TIMER_CH_1, TIMER_OC_SHADOW_DISABLE); + /* auto-reload preload shadow reg enable */ + /* timer_auto_reload_shadow_enable(timer_periph); */ + timer_channel_output_state_config(timer_periph, TIMER_CH_1, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_1, TIMER_CCXN_DISABLE); + + /* L2通用定时器 */ + case TIMER9: + case TIMER10: + case TIMER12: + case TIMER13: + timer_channel_output_config(timer_periph, TIMER_CH_0, ocpara); + timer_channel_output_pulse_value_config(timer_periph, TIMER_CH_0, 7999); + timer_channel_output_mode_config(timer_periph, TIMER_CH_0, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(timer_periph, TIMER_CH_0, TIMER_OC_SHADOW_DISABLE); + /* auto-reload preload shadow reg enable */ + /* timer_auto_reload_shadow_enable(timer_periph); */ + timer_channel_output_state_config(timer_periph, TIMER_CH_0, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(timer_periph, TIMER_CH_0, TIMER_CCXN_DISABLE); + break; + + default: + LOG_E("Unsport timer periph at channel_output_config!\n"); + break; } - /* enable timer */ - for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i) - { - if (-1 != gd32_timer_periph_list.TimerIndex[i]) - { - timer_periph = index_to_timer(gd32_timer_periph_list.TimerIndex[i]); - if (timer_periph == TIMER0 || timer_periph == TIMER7) - { - timer_primary_output_config(timer_periph, ENABLE); - } - timer_enable(timer_periph); - } - } + timer_enable(timer_periph); } static void timer_config(void) @@ -412,58 +466,76 @@ static void timer_config(void) timer_parameter_struct timer_initpara; /* TIMER configuration */ - timer_initpara.prescaler = 119; + timer_initpara.prescaler = 199; timer_initpara.alignedmode = TIMER_COUNTER_EDGE; timer_initpara.counterdirection = TIMER_COUNTER_UP; timer_initpara.period = 15999; timer_initpara.clockdivision = TIMER_CKDIV_DIV1; timer_initpara.repetitioncounter = 0; - timer_init_para(&timer_initpara); + for (size_t i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) + { + timer_init(gd32_pwm_obj[i].timerx, &timer_initpara); + } /* CHX configuration in PWM mode */ - timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_ocintpara.outputstate = TIMER_CCX_DISABLE; timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE; timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; - channel_output_config(&timer_ocintpara); + /* config the channel config */ + for (size_t i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); ++i) + { + channel_output_config(gd32_pwm_obj[i].timerx, &timer_ocintpara); + } } -static rt_err_t drv_pwm_enable(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm_configuration *configuration, +static rt_err_t drv_pwm_enable(struct gd32_pwm *pwm, const struct rt_pwm_configuration *configuration, rt_bool_t enable) { if (!enable) { - timer_channel_output_state_config(index_to_timer(pstTimerMap->TimerIndex), configuration->channel, - TIMER_CCX_DISABLE); + gpio_config_input(pwm, configuration); + if (configuration->complementary == RT_TRUE) + { + timer_channel_complementary_output_state_config(pwm->timerx, configuration->channel-1, + TIMER_CCXN_DISABLE); + } + else + { + timer_channel_output_state_config(pwm->timerx, configuration->channel-1, + TIMER_CCX_DISABLE); + } } else { + gpio_config_pwmout(pwm, configuration); if (configuration->complementary == RT_TRUE) { - timer_channel_output_state_config( - index_to_timer(pstTimerMap->TimerIndex), configuration->channel - 1, TIMER_CCXN_ENABLE); + timer_channel_complementary_output_state_config(pwm->timerx, configuration->channel-1, + TIMER_CCXN_ENABLE); } else { - timer_channel_output_state_config( - index_to_timer(pstTimerMap->TimerIndex), configuration->channel, TIMER_CCX_ENABLE); + timer_channel_output_state_config(pwm->timerx, configuration->channel-1, + TIMER_CCX_ENABLE); } } return RT_EOK; } -static rt_err_t drv_pwm_get(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_get(const struct gd32_pwm *pwm, struct rt_pwm_configuration *configuration) { rt_uint64_t tim_clock; rt_uint16_t psc; rt_uint32_t chxcv; - tim_clock = rcu_clock_freq_get(CK_SYS); + rt_uint8_t coef = (RCU_CFG1&RCU_CFG1_TIMERSEL)?4:2; + tim_clock = rcu_clock_freq_get(pwm->apb_of)*coef; - psc = timer_prescaler_read(index_to_timer(pstTimerMap->TimerIndex)); + psc = timer_prescaler_read(pwm->timerx); if (psc == TIMER_CKDIV_DIV2) { tim_clock = tim_clock / 2; @@ -473,21 +545,22 @@ static rt_err_t drv_pwm_get(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm tim_clock = tim_clock / 4; } - chxcv = timer_channel_capture_value_register_read(index_to_timer(pstTimerMap->TimerIndex), configuration->channel); + chxcv = timer_channel_capture_value_register_read(pwm->timerx, configuration->channel-1); /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ tim_clock /= 1000000UL; - configuration->period = (TIMER_CAR(index_to_timer(pstTimerMap->TimerIndex)) + 1) * (psc + 1) * 1000UL / tim_clock; + configuration->period = (TIMER_CAR(pwm->timerx) + 1) * (psc + 1) * 1000UL / tim_clock; configuration->pulse = (chxcv + 1) * (psc + 1) * 1000UL / tim_clock; return RT_EOK; } -static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm_configuration *configuration) +static rt_err_t drv_pwm_set(struct gd32_pwm *pwm, struct rt_pwm_configuration *configuration) { rt_uint32_t period, pulse; rt_uint64_t tim_clock, psc; - tim_clock = rcu_clock_freq_get(CK_SYS); + rt_uint8_t coef = (RCU_CFG1&RCU_CFG1_TIMERSEL)?4:2; + tim_clock = rcu_clock_freq_get(pwm->apb_of)*coef; /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ tim_clock /= 1000000UL; @@ -495,14 +568,14 @@ static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm psc = period / MAX_PERIOD + 1; period = period / psc; - timer_prescaler_config(index_to_timer(pstTimerMap->TimerIndex), psc - 1, TIMER_PSC_RELOAD_NOW); + timer_prescaler_config(pwm->timerx, psc - 1, TIMER_PSC_RELOAD_NOW); if (period < MIN_PERIOD) { period = MIN_PERIOD; } - timer_autoreload_value_config(index_to_timer(pstTimerMap->TimerIndex), period - 1); + timer_autoreload_value_config(pwm->timerx, period - 1); pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL; if (pulse < MIN_PULSE) @@ -514,11 +587,11 @@ static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm pulse = period; } - timer_channel_output_pulse_value_config(index_to_timer(pstTimerMap->TimerIndex), configuration->channel, pulse); - timer_counter_value_config(index_to_timer(pstTimerMap->TimerIndex), 0); + timer_channel_output_pulse_value_config(pwm->timerx, configuration->channel-1, pulse); + timer_counter_value_config(pwm->timerx, 0); /* Update frequency value */ - timer_event_software_generate(index_to_timer(pstTimerMap->TimerIndex), TIMER_EVENT_SRC_UPG); + timer_event_software_generate(pwm->timerx, TIMER_EVENT_SRC_UPG); return RT_EOK; } @@ -526,18 +599,18 @@ static rt_err_t drv_pwm_set(TIMER_PORT_CHANNEL_MAP_S *pstTimerMap, struct rt_pwm static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) { struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; - TIMER_PORT_CHANNEL_MAP_S *pstTimerMap = (TIMER_PORT_CHANNEL_MAP_S *)device->parent.user_data; + struct gd32_pwm *pwm = (struct gd32_pwm *)device; switch (cmd) { case PWM_CMD_ENABLE: - return drv_pwm_enable(pstTimerMap, configuration, RT_TRUE); + return drv_pwm_enable(pwm, configuration, RT_TRUE); case PWM_CMD_DISABLE: - return drv_pwm_enable(pstTimerMap, configuration, RT_FALSE); + return drv_pwm_enable(pwm, configuration, RT_FALSE); case PWM_CMD_SET: - return drv_pwm_set(pstTimerMap, configuration); + return drv_pwm_set(pwm, configuration); case PWM_CMD_GET: - return drv_pwm_get(pstTimerMap, configuration); + return drv_pwm_get(pwm, configuration); default: return -RT_EINVAL; } @@ -547,15 +620,18 @@ static struct rt_pwm_ops drv_ops = {drv_pwm_control}; static rt_err_t gd32_hw_pwm_init(void) { - pwm_find_timer_periph(); rcu_config(); - gpio_config(); timer_config(); + /* + * gpio 此处不配置，当pwm通道使能时会配置为pwmout，失能时会配置为浮空输入 + * gpio 默认为浮空输入 + */ + return RT_EOK; } -static int gd32_pwm_init(void) +static int rt_hw_pwm_init(void) { int i = 0; int result = RT_EOK; @@ -573,14 +649,14 @@ static int gd32_pwm_init(void) for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); i++) { /* register pwm device */ - if (rt_device_pwm_register(&gd32_pwm_obj[i].pwm_device, gd32_pwm_obj[i].tim_handle.name, &drv_ops, - &gd32_pwm_obj[i].tim_handle)== RT_EOK ) + if (rt_device_pwm_register(&gd32_pwm_obj[i].pwm_device, gd32_pwm_obj[i].name, &drv_ops, + RT_NULL)== RT_EOK ) { - LOG_D("%s register success", gd32_pwm_obj[i].tim_handle.name); + LOG_D("%s register success", gd32_pwm_obj[i].name); } else { - LOG_E("%s register failed", gd32_pwm_obj[i].tim_handle.name); + LOG_E("%s register failed", gd32_pwm_obj[i].name); result = -RT_ERROR; } } @@ -588,6 +664,6 @@ static int gd32_pwm_init(void) __exit: return result; } -INIT_DEVICE_EXPORT(gd32_pwm_init); +INIT_DEVICE_EXPORT(rt_hw_pwm_init); #endif /* RT_USING_PWM */ -- Gitee From f3a45ba2fd46bb4fc1bd7f6662bfcf3f0e0b626f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=9F=B3=E9=B8=BF=E8=B6=85?= <13010364+shi-hongchao@user.noreply.gitee.com> Date: Sun, 11 Jan 2026 19:18:36 +0800 Subject: [PATCH 04/45] =?UTF-8?q?fix(bsp/gd32/arm):=20=E4=BF=AE=E5=A4=8Dgd?= =?UTF-8?q?32=E7=A1=AC=E4=BB=B6i2c=E9=A9=B1=E5=8A=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - 硬件i2c主机接收驱动采用方案B，但不支持接收小于3字节，现修复该问题 - 增加方案A。 --- bsp/gd32/arm/gd32405rg/.config | 20 +-- bsp/gd32/arm/gd32405rg/board/Kconfig | 29 +++ bsp/gd32/arm/gd32405rg/project.uvoptx | 166 +++++++----------- bsp/gd32/arm/gd32405rg/project.uvprojx | 38 ++-- bsp/gd32/arm/gd32405rg/rtconfig.h | 16 +- .../arm/libraries/gd32_drivers/drv_hard_i2c.c | 86 +++++++-- 6 files changed, 200 insertions(+), 155 deletions(-) diff --git a/bsp/gd32/arm/gd32405rg/.config b/bsp/gd32/arm/gd32405rg/.config index d9defb3a43..8dcdda7301 100644 --- a/bsp/gd32/arm/gd32405rg/.config +++ b/bsp/gd32/arm/gd32405rg/.config @@ -1440,22 +1440,16 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART4 is not set # CONFIG_BSP_USING_UART5 is not set +CONFIG_BSP_USING_HARD_I2C=y +CONFIG_BSP_USING_RECEIVING_A=y +# CONFIG_BSP_USING_RECEIVING_B is not set +CONFIG_BSP_USING_HARD_I2C0=y +# CONFIG_BSP_USING_HARD_I2C1 is not set +# CONFIG_BSP_USING_HARD_I2C2 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_HWTIMER is not set -CONFIG_BSP_USING_PWM=y -CONFIG_BSP_USING_PWM0=y -CONFIG_BSP_USING_PWM1=y -CONFIG_BSP_USING_PWM2=y -CONFIG_BSP_USING_PWM3=y -CONFIG_BSP_USING_PWM4=y -CONFIG_BSP_USING_PWM7=y -CONFIG_BSP_USING_PWM8=y -CONFIG_BSP_USING_PWM9=y -CONFIG_BSP_USING_PWM10=y -CONFIG_BSP_USING_PWM11=y -CONFIG_BSP_USING_PWM12=y -CONFIG_BSP_USING_PWM13=y +# CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set # CONFIG_BSP_USING_SDIO is not set diff --git a/bsp/gd32/arm/gd32405rg/board/Kconfig b/bsp/gd32/arm/gd32405rg/board/Kconfig index ea08346a41..36805b18fb 100644 --- a/bsp/gd32/arm/gd32405rg/board/Kconfig +++ b/bsp/gd32/arm/gd32405rg/board/Kconfig @@ -232,6 +232,35 @@ menu "On-chip Peripheral Drivers" default 32 endif + menuconfig BSP_USING_HARD_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + if BSP_USING_HARD_I2C + choice + prompt "Select I2C Receiving Scheme" + default BSP_USING_RECEIVING_A + + config BSP_USING_RECEIVING_A + bool "master receiving secheme A --- requires that the software be capable of responding quickly to the 12C event." + + config BSP_USING_RECEIVING_B + bool "master receiving secheme B --- don't requires that the software be capable of responding quickly to the 12C event." + endchoice + + config BSP_USING_HARD_I2C0 + bool "enable hard I2C0" + default n + + config BSP_USING_HARD_I2C1 + bool "enable hard I2C1" + default n + + config BSP_USING_HARD_I2C2 + bool "enable hard I2C2" + default n + endif + menuconfig BSP_USING_SPI bool "Enable SPI BUS" default n diff --git a/bsp/gd32/arm/gd32405rg/project.uvoptx b/bsp/gd32/arm/gd32405rg/project.uvoptx index e8e6ea1538..7fd705460a 100644 --- a/bsp/gd32/arm/gd32405rg/project.uvoptx +++ b/bsp/gd32/arm/gd32405rg/project.uvoptx @@ -117,26 +117,6 @@ BIN\CMSIS_AGDI.dll - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - - 0 CMSIS_AGDI @@ -155,12 +135,12 @@ 0 0 - 1 + 0 0 0 0 0 - 1 + 0 0 0 0 @@ -191,16 +171,6 @@ - - - System Viewer\TIMER1 - 35905 - - - System Viewer\TIMER2 - 35904 - - @@ -577,6 +547,18 @@ 0 0 0 + ..\libraries\gd32_drivers\drv_hard_i2c.c + drv_hard_i2c.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 ..\libraries\gd32_drivers\drv_hwtimer.c drv_hwtimer.c 0 @@ -584,7 +566,7 @@ 4 - 30 + 31 1 0 0 @@ -596,7 +578,7 @@ 4 - 31 + 32 1 0 0 @@ -616,49 +598,49 @@ 0 5 - 32 + 33 1 0 0 0 - ..\..\..\..\components\finsh\msh_parse.c - msh_parse.c + ..\..\..\..\components\finsh\msh.c + msh.c 0 0 5 - 33 + 34 1 0 0 0 - ..\..\..\..\components\finsh\shell.c - shell.c + ..\..\..\..\components\finsh\cmd.c + cmd.c 0 0 5 - 34 + 35 1 0 0 0 - ..\..\..\..\components\finsh\msh.c - msh.c + ..\..\..\..\components\finsh\shell.c + shell.c 0 0 5 - 35 + 36 1 0 0 0 - ..\..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\..\components\finsh\msh_parse.c + msh_parse.c 0 0 @@ -672,7 +654,7 @@ 0 6 - 36 + 37 1 0 0 @@ -684,7 +666,7 @@ 6 - 37 + 38 1 0 0 @@ -696,7 +678,7 @@ 6 - 38 + 39 1 0 0 @@ -708,7 +690,7 @@ 6 - 39 + 40 1 0 0 @@ -720,7 +702,7 @@ 6 - 40 + 41 1 0 0 @@ -732,7 +714,7 @@ 6 - 41 + 42 1 0 0 @@ -744,7 +726,7 @@ 6 - 42 + 43 1 0 0 @@ -756,7 +738,7 @@ 6 - 43 + 44 1 0 0 @@ -768,7 +750,7 @@ 6 - 44 + 45 1 0 0 @@ -780,7 +762,7 @@ 6 - 45 + 46 1 0 0 @@ -792,7 +774,7 @@ 6 - 46 + 47 1 0 0 @@ -804,7 +786,7 @@ 6 - 47 + 48 1 0 0 @@ -816,7 +798,7 @@ 6 - 48 + 49 1 0 0 @@ -828,7 +810,7 @@ 6 - 49 + 50 1 0 0 @@ -840,7 +822,7 @@ 6 - 50 + 51 1 0 0 @@ -860,19 +842,19 @@ 0 7 - 51 + 52 1 0 0 0 - ..\..\..\..\src\klibc\kstring.c - kstring.c + ..\..\..\..\src\klibc\kerrno.c + kerrno.c 0 0 7 - 52 + 53 1 0 0 @@ -884,19 +866,19 @@ 7 - 53 + 54 1 0 0 0 - ..\..\..\..\src\klibc\kerrno.c - kerrno.c + ..\..\..\..\src\klibc\kstring.c + kstring.c 0 0 7 - 54 + 55 1 0 0 @@ -908,7 +890,7 @@ 7 - 55 + 56 1 0 0 @@ -928,7 +910,7 @@ 0 8 - 56 + 57 1 0 0 @@ -940,7 +922,7 @@ 8 - 57 + 58 1 0 0 @@ -952,7 +934,7 @@ 8 - 58 + 59 1 0 0 @@ -964,7 +946,7 @@ 8 - 59 + 60 2 0 0 @@ -976,7 +958,7 @@ 8 - 60 + 61 1 0 0 @@ -990,13 +972,13 @@ Libraries - 1 + 0 0 0 0 9 - 61 + 62 2 0 0 @@ -1008,7 +990,7 @@ 9 - 62 + 63 1 0 0 @@ -1020,7 +1002,7 @@ 9 - 63 + 64 1 0 0 @@ -1032,7 +1014,7 @@ 9 - 64 + 65 1 0 0 @@ -1044,7 +1026,7 @@ 9 - 65 + 66 1 0 0 @@ -1056,7 +1038,7 @@ 9 - 66 + 67 1 0 0 @@ -1068,7 +1050,7 @@ 9 - 67 + 68 1 0 0 @@ -1080,7 +1062,7 @@ 9 - 68 + 69 1 0 0 @@ -1092,7 +1074,7 @@ 9 - 69 + 70 1 0 0 @@ -1104,7 +1086,7 @@ 9 - 70 + 71 1 0 0 @@ -1114,18 +1096,6 @@ 0 0 - - 9 - 71 - 1 - 0 - 0 - 0 - .\packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c - gd32f4xx_timer.c - 0 - 0 - diff --git a/bsp/gd32/arm/gd32405rg/project.uvprojx b/bsp/gd32/arm/gd32405rg/project.uvprojx index 9ab03ac12e..69f501cf6d 100644 --- a/bsp/gd32/arm/gd32405rg/project.uvprojx +++ b/bsp/gd32/arm/gd32405rg/project.uvprojx @@ -338,9 +338,9 @@ 0 - RT_USING_LIBC, HXTAL_VALUE=8000000U, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, GD32F405, __STDC_LIMIT_MACROS + RT_USING_LIBC, GD32F405, __RTTHREAD__, USE_STDPERIPH_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, HXTAL_VALUE=8000000U - packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;packages\gd32-arm-cmsis-latest\GD32F4xx;.;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\net\utest;applications;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\drivers\phy;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;board;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\libcpu\arm\common;..\..\..\..\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\libraries\gd32_drivers;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\eventfd + applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\posix\io\eventfd;board;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\smp_call;..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\include;..\..\..\..\libcpu\arm\cortex-m4;packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;..\..\..\..\components\libc\posix\io\epoll;..\libraries\gd32_drivers;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\net\utest;..\..\..\..\components\drivers\phy;..\..\..\..\include;packages\gd32-arm-cmsis-latest\GD32F4xx;.;..\..\..\..\components\drivers\include;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include @@ -1406,6 +1406,11 @@ 1 ..\libraries\gd32_drivers\drv_gpio.c + + drv_hard_i2c.c + 1 + ..\libraries\gd32_drivers\drv_hard_i2c.c + drv_hwtimer.c 1 @@ -1427,24 +1432,24 @@ Finsh - msh_parse.c + msh.c 1 - ..\..\..\..\components\finsh\msh_parse.c + ..\..\..\..\components\finsh\msh.c - shell.c + cmd.c 1 - ..\..\..\..\components\finsh\shell.c + ..\..\..\..\components\finsh\cmd.c - msh.c + shell.c 1 - ..\..\..\..\components\finsh\msh.c + ..\..\..\..\components\finsh\shell.c - cmd.c + msh_parse.c 1 - ..\..\..\..\components\finsh\cmd.c + ..\..\..\..\components\finsh\msh_parse.c @@ -2297,9 +2302,9 @@ klibc - kstring.c + kerrno.c 1 - ..\..\..\..\src\klibc\kstring.c + ..\..\..\..\src\klibc\kerrno.c rt_vsscanf.c @@ -2307,9 +2312,9 @@ ..\..\..\..\src\klibc\rt_vsscanf.c - kerrno.c + kstring.c 1 - ..\..\..\..\src\klibc\kerrno.c + ..\..\..\..\src\klibc\kstring.c kstdio.c @@ -2406,11 +2411,6 @@ 1 packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c - - gd32f4xx_timer.c - 1 - .\packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c - diff --git a/bsp/gd32/arm/gd32405rg/rtconfig.h b/bsp/gd32/arm/gd32405rg/rtconfig.h index 598194241a..ad67872218 100644 --- a/bsp/gd32/arm/gd32405rg/rtconfig.h +++ b/bsp/gd32/arm/gd32405rg/rtconfig.h @@ -422,19 +422,9 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART0 -#define BSP_USING_PWM -#define BSP_USING_PWM0 -#define BSP_USING_PWM1 -#define BSP_USING_PWM2 -#define BSP_USING_PWM3 -#define BSP_USING_PWM4 -#define BSP_USING_PWM7 -#define BSP_USING_PWM8 -#define BSP_USING_PWM9 -#define BSP_USING_PWM10 -#define BSP_USING_PWM11 -#define BSP_USING_PWM12 -#define BSP_USING_PWM13 +#define BSP_USING_HARD_I2C +#define BSP_USING_RECEIVING_A +#define BSP_USING_HARD_I2C0 #define BSP_USING_GD_DBG /* end of On-chip Peripheral Drivers */ diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_hard_i2c.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_hard_i2c.c index 725b306fde..48dd5154e4 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_hard_i2c.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_hard_i2c.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2021-12-20 BruceOu the first version + * 2026-01-11 ShiHongchao Fix the I2C master receive mode B software + * flow and add support for mode A */ #include "drv_hard_i2c.h" @@ -112,8 +114,8 @@ static const struct gd32_i2c_bus gd_i2c_config[] = { RCU_I2C0, RCU_GPIOB, RCU_GPIOB, /* periph clock, scl gpio clock, sda gpio clock */ - GPIOB, GPIO_AF_4, GPIO_PIN_6, /* scl port, scl alternate, scl pin */ - GPIOB, GPIO_AF_4, GPIO_PIN_7, /* sda port, sda alternate, sda pin */ + GPIOB, GPIO_AF_4, GPIO_PIN_8, /* scl port, scl alternate, scl pin */ + GPIOB, GPIO_AF_4, GPIO_PIN_9, /* sda port, sda alternate, sda pin */ &i2c0, "hwi2c0", @@ -229,13 +231,52 @@ static void gd32_i2c_gpio_init(const struct gd32_i2c_bus *i2c) static uint8_t gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint8_t *p_buffer, rt_uint16_t data_byte) { if (data_byte == 0) return 1; - /* while there is data to be read */ +#ifdef BSP_USING_RECEIVING_A + /* + In single-byte reception, disable ACK because the master needs to send + NACK after receiving the first byte,indicating no more data will be + received, then immediately send the stop condition + */ + if(data_byte == 1) + { + /* disable acknowledge */ + i2c_ack_config(i2c_periph, I2C_ACK_DISABLE); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + } +#endif + + /* while there is data to be read */ while(data_byte) { #if defined (SOC_SERIES_GD32F5xx) || defined (SOC_SERIES_GD32F4xx) if(IS_I2C_LEGACY(i2c_periph)) { +#ifdef BSP_USING_RECEIVING_A + /* + After receiving the second-to-last byte, ACK should be disabled + and STOP should be set, to ensure that NACK is sent after receiving + the last byte and the stop condition is transmitted + */ + if(2 == data_byte) + { + /* wait until BTC bit is set */ + while(!i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)); + /* disable acknowledge */ + i2c_ack_config(i2c_periph, I2C_ACK_DISABLE); + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(i2c_periph); + } +#elif defined(BSP_USING_RECEIVING_B) + /* + For 3-byte reception: Wait for byte transfer completion, then + disable ACK so NACK is automatically sent after receiving the + last byte + For 2-byte reception: Wait for byte transfer completion, then + send stop condition to ensure direct stop after receiving the + last byte instead of sending ACK + */ if(3 == data_byte) { /* wait until BTC bit is set */ @@ -243,14 +284,16 @@ static uint8_t gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint8_t *p_buffer, rt_ui /* disable acknowledge */ i2c_ack_config(i2c_periph, I2C_ACK_DISABLE); } - - if(2 == data_byte) + else if(2 == data_byte) { /* wait until BTC bit is set */ while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); /* send a stop condition to I2C bus */ i2c_stop_on_bus(i2c_periph); } +#else +#error "Please select the receiving secheme." +#endif /* wait until RBNE bit is set */ if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) { @@ -379,11 +422,18 @@ static rt_ssize_t gd32_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct rt_ { i2c_stop_on_bus(gd32_i2c->i2c_periph); } - /* enable acknowledge */ + /* enable acknowledge */ i2c_ack_config(gd32_i2c->i2c_periph, I2C_ACK_ENABLE); - /* i2c master sends start signal only when the bus is idle */ + /* i2c master sends start signal only when the bus is idle */ while(i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_I2CBSY)); - /* send the start signal */ +#ifdef BSP_USING_RECEIVING_B + /* */ + if(msg->len == 2) + { + i2c_ackpos_config(gd32_i2c->i2c_periph, I2C_ACKPOS_NEXT); + } +#endif + /* send the start signal */ i2c_start_on_bus(gd32_i2c->i2c_periph); /* i2c master sends START signal successfully */ while(!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_SBSEND)); @@ -391,14 +441,26 @@ static rt_ssize_t gd32_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct rt_ i2c_master_addressing(gd32_i2c->i2c_periph, msg->addr, I2C_RECEIVER); while(!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_ADDSEND)); - /* address flag set means i2c slave sends ACK */ +#ifdef BSP_USING_RECEIVING_B + if(msg->len <= 2) + { + i2c_ack_config(gd32_i2c->i2c_periph, I2C_ACK_DISABLE); + } +#endif + /* address flag set means i2c slave sends ACK */ i2c_flag_clear(gd32_i2c->i2c_periph, I2C_FLAG_ADDSEND); +#ifdef BSP_USING_RECEIVING_B + if(msg->len == 1) + { + i2c_stop_on_bus(gd32_i2c->i2c_periph); + } +#endif }else { - /* configure slave address */ + /* configure slave address */ while(i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_I2CBSY)); - //i2c_transfer_byte_number_config(gd32_i2c->i2c_periph, w_total_byte); - /* send a start condition to I2C bus */ + //i2c_transfer_byte_number_config(gd32_i2c->i2c_periph, w_total_byte); + /* send a start condition to I2C bus */ i2c_start_on_bus(gd32_i2c->i2c_periph); while(!i2c_flag_get(gd32_i2c->i2c_periph, I2C_FLAG_SBSEND)); -- Gitee From 9bf3a54191587777269daf39b3f7bd7fc9f0067a Mon Sep 17 00:00:00 2001 From: DaiLingxiang <3070269033@qq.com> Date: Fri, 16 Jan 2026 12:31:35 +0800 Subject: [PATCH 05/45] bsp/stm32f407-micu:add aht20,icm20608,ssd1306 support --- bsp/stm32/stm32f407-micu/board/Kconfig | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/bsp/stm32/stm32f407-micu/board/Kconfig b/bsp/stm32/stm32f407-micu/board/Kconfig index 0ce9e220b6..fc65f2af28 100644 --- a/bsp/stm32/stm32f407-micu/board/Kconfig +++ b/bsp/stm32/stm32f407-micu/board/Kconfig @@ -24,6 +24,23 @@ menu "Onboard Peripheral Drivers" select RT_USING_SFUD default n + config BSP_USING_AHT20 + bool "Enable AHT20(i2c1)" + select BSP_USING_I2C + select BSP_USING_I2C1 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_AHT10 + default n + + config BSP_USING_ICM20608 + bool "Enable ICM20608(i2c1)" + select BSP_USING_I2C + select BSP_USING_I2C1 + select PKG_USING_SENSORS_DRIVERS + select PKG_USING_ICM20608 + default n + + endmenu menu "On-chip Peripheral Drivers" @@ -226,6 +243,16 @@ endmenu menu "Board extended module Drivers" + config BSP_USING_SSD1306 + bool "Enable SSD1306 OLED" + select BSP_USING_I2C + select BSP_USING_I2C2 + select PKG_USING_SSD1306 + default n + help + Enable SSD1306 OLED display (connected to I2C2 on this board). + + endmenu endmenu \ No newline at end of file -- Gitee From 3ca5cd53f53d036604d663ac988aeb778bc52813 Mon Sep 17 00:00:00 2001 From: milo <1569491816@qq.com> Date: Fri, 16 Jan 2026 22:29:25 +0800 Subject: [PATCH 06/45] [fix] fix normalization issue of mktime and timegm --- components/libc/compilers/common/ctime.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/libc/compilers/common/ctime.c b/components/libc/compilers/common/ctime.c index 159667bbcf..bcd19fc8aa 100644 --- a/components/libc/compilers/common/ctime.c +++ b/components/libc/compilers/common/ctime.c @@ -391,7 +391,6 @@ time_t timegm(struct tm * const t) return (time_t)-1; } - years = (time_t)t->tm_year - 70; if (t->tm_sec > 60) /* seconds after the minute - [0, 60] including leap second */ { t->tm_min += t->tm_sec / 60; @@ -433,6 +432,8 @@ time_t timegm(struct tm * const t) return (time_t) -1; } + years = (time_t)t->tm_year - 70; + /* Days since 1970 is 365 * number of years + number of leap years since 1970 */ day = years * 365 + (years + 1) / 4; -- Gitee From d76eca13840eba4a94cbd22e184076998ad3e973 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Mon, 19 Jan 2026 09:05:49 +0800 Subject: [PATCH 07/45] fix(Kconfig): Update the default value of FINSH_THREAD_PRIORITY to support different thread priorities --- components/finsh/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/components/finsh/Kconfig b/components/finsh/Kconfig index 67a50a28d7..4aa83b34d7 100644 --- a/components/finsh/Kconfig +++ b/components/finsh/Kconfig @@ -20,7 +20,9 @@ if RT_USING_MSH config FINSH_THREAD_PRIORITY int "The priority level value of thread" - default 20 + default 5 if RT_THREAD_PRIORITY_8 + default 20 if RT_THREAD_PRIORITY_32 + default 160 if RT_THREAD_PRIORITY_256 config FINSH_THREAD_STACK_SIZE int "The stack size for thread" -- Gitee From b3c71a6f345dcb1f2609e7057480245dc78e985f Mon Sep 17 00:00:00 2001 From: Eric Chan <55314107+LinuxMint-User@users.noreply.github.com> Date: Tue, 13 Jan 2026 20:43:02 +0800 Subject: [PATCH 08/45] Fix: fix xpt2046_touch_readpoint type error Fix & Improve: fix touch event bug with LVGL Fix touch event bug with LVGL. Improve the touch sliding experience of resistive screens. [ci][stm32f407] add lcd attach config CI check Fix: minor modification Fix format issue. Fix Ci attach file. --- .../.ci/attachconfig/onboard-lcd-touch.attach | 32 ++++ .../board/ports/touch/drv_touch_xpt.c | 13 +- .../board/ports/touch/drv_xpt2046_init.c | 153 ++++++++++++++++-- 3 files changed, 179 insertions(+), 19 deletions(-) create mode 100644 bsp/stm32/stm32f407-atk-explorer/.ci/attachconfig/onboard-lcd-touch.attach diff --git a/bsp/stm32/stm32f407-atk-explorer/.ci/attachconfig/onboard-lcd-touch.attach b/bsp/stm32/stm32f407-atk-explorer/.ci/attachconfig/onboard-lcd-touch.attach new file mode 100644 index 0000000000..013e303529 --- /dev/null +++ b/bsp/stm32/stm32f407-atk-explorer/.ci/attachconfig/onboard-lcd-touch.attach @@ -0,0 +1,32 @@ +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +CONFIG_RT_USING_SPI_BITOPS=y +CONFIG_RT_USING_SOFT_SPI=y +CONFIG_RT_USING_SOFT_SPI0=y +CONFIG_RT_SOFT_SPI0_SCK_PIN=1 +CONFIG_RT_SOFT_SPI0_MISO_PIN=2 +CONFIG_RT_SOFT_SPI0_MOSI_PIN=3 +CONFIG_RT_SOFT_SPI0_BUS_NAME="spi0" +CONFIG_RT_SOFT_SPI0_TIMING_DELAY=1 +CONFIG_RT_USING_SOFT_SPI1=y +CONFIG_RT_SOFT_SPI1_SCK_PIN=4 +CONFIG_RT_SOFT_SPI1_MISO_PIN=5 +CONFIG_RT_SOFT_SPI1_MOSI_PIN=6 +CONFIG_RT_SOFT_SPI1_BUS_NAME="spi1" +CONFIG_RT_SOFT_SPI1_TIMING_DELAY=1 +CONFIG_RT_USING_TOUCH=y +CONFIG_RT_TOUCH_PIN_IRQ=y +CONFIG_BSP_USING_SRAM=y +CONFIG_BSP_USING_ONBOARD_LCD=y +CONFIG_BSP_USING_ONBOARD_LCD_TEST=y +CONFIG_BSP_USING_TOUCH=y +CONFIG_BSP_USING_TOUCH_RES=y +CONFIG_BSP_XPT2046_CS_PIN="PC.13" +CONFIG_BSP_XPT2046_IRQ_PIN="PB.1" +CONFIG_BSP_USING_SOFT_SPI=y +CONFIG_BSP_USING_SOFT_SPI1=y +CONFIG_BSP_S_SPI1_SCK_PIN=16 +CONFIG_BSP_S_SPI1_MISO_PIN=18 +CONFIG_BSP_S_SPI1_MOSI_PIN=91 +CONFIG_BSP_USING_EXT_FMC_IO=y +CONFIG_BSP_USING_FMC=y diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_touch_xpt.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_touch_xpt.c index 204f393038..915b8be636 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_touch_xpt.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_touch_xpt.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2022-6-27 solar first version + * Date Author Notes + * 2022-6-27 solar first version + * 2026-01-12 LinuxMint-User fix xpt2046_touch_readpoint type error */ #include @@ -30,6 +31,7 @@ rt_err_t xpt2046_calibration(const char *lcd_name,const char *touch_name) LOG_E(LOG_TAG " cannot find lcd device named %s", lcd_name); return -RT_ERROR; } + if (rt_device_open(lcd, RT_DEVICE_OFLAG_RDWR) != RT_EOK) { LOG_E(LOG_TAG " cannot open lcd device named %s", lcd_name); @@ -101,6 +103,7 @@ rt_err_t xpt2046_calibration(const char *lcd_name,const char *touch_name) { break; } + switch (raw_idx) { case 1: @@ -151,7 +154,7 @@ rt_err_t xpt2046_calibration(const char *lcd_name,const char *touch_name) return RT_EOK; } -static rt_ssize_t xpt2046_touch_readpoint(struct rt_touch_device *touch, void *buf, rt_size_t touch_num) +static rt_size_t xpt2046_touch_readpoint(struct rt_touch_device *touch, void *buf, rt_size_t touch_num) { if (touch_num != 0) { @@ -185,6 +188,7 @@ static rt_ssize_t xpt2046_touch_readpoint(struct rt_touch_device *touch, void *b y_cum += temp; } } + if (!x_count || !y_count) { result->event = RT_TOUCH_EVENT_NONE; @@ -264,3 +268,4 @@ static int xpt2046_hw_init(void) INIT_DEVICE_EXPORT(xpt2046_hw_init); #endif /* BSP_USING_TOUCH_RES */ + diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_xpt2046_init.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_xpt2046_init.c index 40eefad667..09ad6bf898 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_xpt2046_init.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/touch/drv_xpt2046_init.c @@ -1,11 +1,13 @@ /* - * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2022-6-27 solar first version + * 2026-01-12 LinuxMint-User fix touch event bug with LVGL + * 2026-01-13 LinuxMint-User improve the touch sliding experience of resistive screens */ #include @@ -42,6 +44,7 @@ void xpt2046_init_hw(void) rt_kprintf("can't find touch device:%s\n", TOUCH_DEVICE_NAME); return; } + if (rt_device_open(touch, RT_DEVICE_FLAG_INT_RX) != RT_EOK) { rt_kprintf("can't open touch device:%s\n", TOUCH_DEVICE_NAME); @@ -87,38 +90,157 @@ void xpt2046_init_hw(void) void xpt2046_entry(void *parameter) { - /* Find the touch device */ rt_device_t touch = rt_device_find(TOUCH_DEVICE_NAME); if (touch == RT_NULL) { rt_kprintf("can't find touch device:%s\n", TOUCH_DEVICE_NAME); return; } -#ifndef PKG_USING_LVGL + + #ifndef PKG_USING_LVGL rt_device_t lcd = rt_device_find(TFTLCD_DEVICE_NAME); if (lcd == RT_NULL) { - rt_kprintf("can't find display device:%s\n", TFTLCD_DEVICE_NAME); - return; + rt_kprintf("can't find display device:%s\n", TFTLCD_DEVICE_NAME); + return; } -#endif /* PKG_USING_LVGL */ + #endif + + static rt_bool_t is_touching = RT_FALSE; + static int no_touch_count = 0; + static int touch_hold_count = 0; + static int last_x = 0, last_y = 0; + static int stable_x = 0, stable_y = 0; + + /* 5-point moving average filter for coordinate smoothing */ + #define HISTORY_SIZE 5 + static int history_x[HISTORY_SIZE] = {0}; + static int history_y[HISTORY_SIZE] = {0}; + static int history_index = 0; + static int history_count = 0; + + static const int DEBOUNCE_COUNT = 2; + static const int RELEASE_DEBOUNCE_COUNT = 5; + static const int MIN_MOVE_DISTANCE = 3; + static const int SMOOTHING_FACTOR = 2; + + rt_memset(history_x, 0, sizeof(history_x)); + rt_memset(history_y, 0, sizeof(history_y)); + while (1) { - /* Prepare variable to read out the touch data */ struct rt_touch_data read_data; rt_memset(&read_data, 0, sizeof(struct rt_touch_data)); + if (rt_device_read(touch, 0, &read_data, 1) == 1) { -#ifdef PKG_USING_LVGL - lv_port_indev_input(read_data.x_coordinate, read_data.y_coordinate, - ((read_data.event = RT_TOUCH_EVENT_DOWN) ? LV_INDEV_STATE_PR : LV_INDEV_STATE_REL)); -#else /* PKG_USING_LVGL */ + int current_x = read_data.x_coordinate; + int current_y = read_data.y_coordinate; + + history_x[history_index] = current_x; + history_y[history_index] = current_y; + history_index = (history_index + 1) % HISTORY_SIZE; + if (history_count < HISTORY_SIZE) history_count++; + + int avg_x = 0, avg_y = 0; + if (history_count > 0) + { + for (int i = 0; i < history_count; i++) + { + avg_x += history_x[i]; + avg_y += history_y[i]; + } + avg_x /= history_count; + avg_y /= history_count; + } + else + { + avg_x = current_x; + avg_y = current_y; + } + + no_touch_count = 0; + + #ifdef PKG_USING_LVGL + if (!is_touching) + { + touch_hold_count++; + + if (touch_hold_count >= DEBOUNCE_COUNT) + { + is_touching = true; + stable_x = avg_x; + stable_y = avg_y; + touch_hold_count = 0; + + lv_port_indev_input(stable_x, stable_y, LV_INDEV_STATE_PR); + + last_x = stable_x; + last_y = stable_y; + } + } + else + { + touch_hold_count = 0; + + int dx = avg_x - last_x; + int dy = avg_y - last_y; + int distance = dx * dx + dy * dy; + + if (distance >= MIN_MOVE_DISTANCE * MIN_MOVE_DISTANCE) + { + /* Interpolation smoothing to reduce jitter */ + int smooth_x = last_x + (avg_x - last_x) / SMOOTHING_FACTOR; + int smooth_y = last_y + (avg_y - last_y) / SMOOTHING_FACTOR; + + lv_port_indev_input(smooth_x, smooth_y, LV_INDEV_STATE_PR); + + last_x = smooth_x; + last_y = smooth_y; + stable_x = smooth_x; + stable_y = smooth_y; + } + else + { + lv_port_indev_input(stable_x, stable_y, LV_INDEV_STATE_PR); + } + } + + #else const rt_uint32_t black = 0x0; - rt_graphix_ops(lcd)->set_pixel((const char *)(&black), - read_data.x_coordinate, - read_data.y_coordinate); -#endif /* PKG_USING_LVGL */ + rt_graphix_ops(lcd)->set_pixel((const char *)(&black), avg_x, avg_y); + #endif } + else + { + no_touch_count++; + touch_hold_count = 0; + + if (is_touching) + { + if (no_touch_count >= RELEASE_DEBOUNCE_COUNT) + { + #ifdef PKG_USING_LVGL + lv_port_indev_input(stable_x, stable_y, LV_INDEV_STATE_REL); + #endif + + is_touching = RT_FALSE; + no_touch_count = 0; + + history_count = 0; + history_index = 0; + rt_memset(history_x, 0, sizeof(history_x)); + rt_memset(history_y, 0, sizeof(history_y)); + } + else + { + #ifdef PKG_USING_LVGL + lv_port_indev_input(stable_x, stable_y, LV_INDEV_STATE_PR); + #endif + } + } + } + rt_thread_mdelay(1); } } @@ -134,3 +256,4 @@ static int touch_xpt2046_init(void) INIT_COMPONENT_EXPORT(touch_xpt2046_init); #endif /* BSP_USING_TOUCH_RES */ + -- Gitee From a68cc2e71a1a33c384018c65235b036195784a95 Mon Sep 17 00:00:00 2001 From: ricky <1486344514@qq.com> Date: Mon, 19 Jan 2026 11:31:00 +0800 Subject: [PATCH 09/45] =?UTF-8?q?[tool]=20tools/targets/vsc.py=20:=20impro?= =?UTF-8?q?ve=20compile=5Fcommands=20handling=20and=20w=E2=80=A6=20(#11138?= =?UTF-8?q?)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [tool] tools/targets/vsc.py : improve compile_commands handling and workspace excludes - broaden source file extension detection to include C++ and asm - resolve compile_commands path to absolute and pass its directory to clangd - limit excludes scan to rt-thread/packages and always include board/linker_scripts --- tools/targets/vsc.py | 51 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/tools/targets/vsc.py b/tools/targets/vsc.py index b4de67dcfb..f6ea8e37df 100644 --- a/tools/targets/vsc.py +++ b/tools/targets/vsc.py @@ -88,7 +88,8 @@ def extract_source_dirs(compile_commands): for entry in compile_commands: file_path = os.path.abspath(entry['file']) - if file_path.endswith('.c'): + file_ext = os.path.splitext(file_path)[1].lower() + if file_ext in ('.c', '.cc', '.cpp', '.cxx', '.s', '.asm'): dir_path = os.path.dirname(file_path) source_dirs.add(dir_path) # command or arguments @@ -126,6 +127,26 @@ def is_path_in_tree(path, tree): return False +def should_force_include(path, root_path): + rel_path = os.path.relpath(path, root_path).replace('\\', '/') + return ( + rel_path == 'board/linker_scripts' or + rel_path.startswith('board/linker_scripts/') + ) + +def limit_excludes_to_root_dirs(root_path, names): + allowed = set(os.path.normpath(os.path.join(root_path, name)) for name in names) + return [p for p in allowed if os.path.isdir(p)] + +def is_under_roots(path, root_path, names): + norm = os.path.normpath(path) + for name in names: + root = os.path.normpath(os.path.join(root_path, name)) + if norm == root or norm.startswith(root + os.path.sep): + return True + return False + + def generate_code_workspace_file(source_dirs,command_json_path,root_path): current_working_directory = os.getcwd() current_folder_name = os.path.basename(current_working_directory) @@ -139,7 +160,13 @@ def generate_code_workspace_file(source_dirs,command_json_path,root_path): continue root_rel_path = os.path.relpath(root_path, current_working_directory) - command_json_path = os.path.relpath(current_working_directory, root_path) + os.sep + command_json_abs_path = command_json_path + if not os.path.isabs(command_json_abs_path): + command_json_abs_path = os.path.abspath( + os.path.join(current_working_directory, command_json_abs_path) + ) + command_json_dir = os.path.dirname(command_json_abs_path) + command_json_dir = os.path.relpath(command_json_dir, root_path) workspace_data = { "folders": [ { @@ -148,7 +175,7 @@ def generate_code_workspace_file(source_dirs,command_json_path,root_path): ], "settings": { "clangd.arguments": [ - f"--compile-commands-dir={command_json_path}", + f"--compile-commands-dir={command_json_dir}", "--header-insertion=never" ], "files.exclude": {dir.replace('\\','/'): True for dir in sorted(relative_dirs)} @@ -161,8 +188,11 @@ def generate_code_workspace_file(source_dirs,command_json_path,root_path): print(f'Workspace file {workspace_filename} created.') def command_json_to_workspace(root_path,command_json_path): - - with open('build/compile_commands.json', 'r') as f: + command_json_abs_path = command_json_path + if not os.path.isabs(command_json_abs_path): + command_json_abs_path = os.path.abspath(command_json_abs_path) + + with open(command_json_abs_path, 'r') as f: compile_commands = json.load(f) source_dirs = extract_source_dirs(compile_commands) @@ -182,17 +212,19 @@ def command_json_to_workspace(root_path,command_json_path): # os.chdir(root_path) # 轮询root文件夹下面的每一个文件夹和子文件夹 for root, dirs, files in os.walk(root_path): + if not is_under_roots(root, root_path, ('rt-thread', 'packages')): + continue # 检查当前root是否在filtered_tree中 - if not is_path_in_tree(root, filtered_tree): + if not is_path_in_tree(root, filtered_tree) and not should_force_include(root, root_path): exclude_fold.add(root) dirs[:] = [] # 不往下轮询子文件夹 continue for dir in dirs: dir_path = os.path.join(root, dir) - if not is_path_in_tree(dir_path, filtered_tree): + if not is_path_in_tree(dir_path, filtered_tree) and not should_force_include(dir_path, root_path): exclude_fold.add(dir_path) - generate_code_workspace_file(exclude_fold,command_json_path,root_path) + generate_code_workspace_file(exclude_fold,command_json_abs_path,root_path) def delete_repeatelist(data): temp_dict = set([str(item) for item in data]) @@ -245,8 +277,7 @@ def GenerateCFiles(env): Generate vscode.code-workspace files by build/compile_commands.json """ if os.path.exists('build/compile_commands.json'): - - command_json_to_workspace(env['RTT_ROOT'],'build/compile_commands.json') + command_json_to_workspace(os.getcwd(), 'build/compile_commands.json') return """ Generate vscode.code-workspace files -- Gitee From 306505ea24d22f908e052836918029d82259bc83 Mon Sep 17 00:00:00 2001 From: PeakRacing <1473454180@qq.com> Date: Tue, 20 Jan 2026 10:36:25 +0800 Subject: [PATCH 10/45] =?UTF-8?q?update:=E6=9B=B4=E6=96=B0=E7=BB=B4?= =?UTF-8?q?=E6=8A=A4=E8=80=85=E4=BF=A1=E6=81=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/airm2m/air32f103/README.md | 2 +- bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h | 2 +- bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/adc_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/dma_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/pwm_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/usbd_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_adc.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_crypto.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h | 2 +- .../libraries/HAL_Drivers/drivers/drv_flash/drv_flash_wb.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c | 2 +- bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h | 2 +- bsp/stm32/libraries/templates/stm32wbxx/applications/main.c | 2 +- bsp/stm32/stm32f407-armfly-v5/README.md | 2 +- bsp/stm32/stm32f407-armfly-v5/applications/main.c | 2 +- bsp/stm32/stm32f407-armfly-v5/board/board.c | 2 +- bsp/stm32/stm32f407-armfly-v5/board/board.h | 2 +- bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h | 2 +- bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c | 2 +- bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c | 2 +- bsp/stm32/stm32wb55-st-nucleo/README.md | 2 +- bsp/stm32/stm32wb55-st-nucleo/applications/main.c | 2 +- bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h | 2 +- 32 files changed, 32 insertions(+), 32 deletions(-) diff --git a/bsp/airm2m/air32f103/README.md b/bsp/airm2m/air32f103/README.md index 852b4b2f4e..d5ed050706 100644 --- a/bsp/airm2m/air32f103/README.md +++ b/bsp/airm2m/air32f103/README.md @@ -106,6 +106,6 @@ msh > 维护人: -- [**Dozingfiretruck (打盹的消防车)**](https://github.com/Dozingfiretruck) +- [**PeakRacing**](https://github.com/PeakRacing) - [**淘宝地址**](https://item.taobao.com/item.htm?spm=a1z10.5-c-s.w4002-24045920841.15.29395bcdUExSHR&id=666216389131) diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h b/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h index 162ca55656..8a1373f027 100644 --- a/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_config.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2018-10-30 SummerGift first version - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx * 2021-08-27 Jiao first version */ diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h b/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h index 9169da5dd9..757265e110 100644 --- a/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h +++ b/bsp/fm33lc026/libraries/HAL_Drivers/drv_usart.h @@ -7,7 +7,7 @@ * Date Author Notes * 2018.10.30 SummerGift first version * 2019.03.05 whj4674672 add stm32h7 - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx */ #ifndef __DRV_USART_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/adc_config.h index d62977ed8b..0de7f3beb3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/adc_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/adc_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __ADC_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/dma_config.h index 2d34ca76e4..adbab77de2 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/dma_config.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __DMA_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/pwm_config.h index 6f52ca2044..5823ac678d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/pwm_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version * 2023-04-08 Wangyuqiang complete PWM defination */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h index c02de26ab2..60964576c5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/qspi_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __QSPI_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h index 8e628aaf88..fa63a162de 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/spi_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __SPI_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h index 1c8c178bd0..1aa956e255 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __TIM_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h index 0ab2c29aac..b36e7bd94c 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/uart_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __UART_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/usbd_config.h index dd61e64a8d..6c074ce4cf 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/usbd_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/usbd_config.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #ifndef __USBD_CONFIG_H__ #define __USBD_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_adc.c index 3348c7698f..64d8469125 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_adc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_adc.c @@ -9,7 +9,7 @@ * 2018-12-12 greedyhao Porting for stm32f7xx * 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue * 2020-06-17 thread-liu Porting for stm32mp1xx - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx * 2022-05-22 Stanley Lwin Add stm32_adc_get_vref * 2022-12-26 wdfk-prog Change the order of configuration channels and calibration functions */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h index cc53b17029..ddd665ac49 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_config.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2018-10-30 SummerGift first version - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx */ #ifndef __DRV_CONFIG_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_crypto.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_crypto.c index 5ded4f16ee..89d0515c29 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_crypto.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_crypto.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2019-07-10 Ernest 1st version - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx * 2020-11-26 thread-liu add hash * 2020-11-26 thread-liu add cryp * 2020-12-11 WKJay fix build problem diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h index 3fe4ff8978..1fc6ffee44 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2018-11-10 SummerGift first version - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx */ #ifndef __DRV_DMA_H_ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_flash/drv_flash_wb.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_flash/drv_flash_wb.c index e8924f494f..642c9953d7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_flash/drv_flash_wb.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_flash/drv_flash_wb.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-10-14 Dozingfiretruck first version + * 2020-10-14 PeakRacing first version */ #include diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c index 83828c7a38..b86c4ba93b 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-04 balanceTWK first version - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx * 2021-02-05 Meco Man fix the problem of mixing local time and UTC time * 2021-07-05 iysheng implement RTC framework V2.0 * 2025-06-05 RCSN add local time conversion for get timeval and set stamp diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c index 07be86130d..6f3a5a6dd0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c @@ -10,7 +10,7 @@ * 2019-01-03 zylx modify DMA initialization and spixfer function * 2020-01-15 whj4674672 Porting for stm32h7xx * 2020-06-18 thread-liu Porting for stm32mp1xx - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx */ #include diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c index 5ff7005791..4533df7a64 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c @@ -8,7 +8,7 @@ * 2018-12-10 zylx first version * 2020-06-16 thread-liu Porting for stm32mp1 * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx * 2020-11-18 leizhixiong add STM32H7 series support * 2023-08-21 Donocean fix the MCU crash when using timer6 * 2023-12-24 Meco Man add TIMx existing check diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c index 5174fbe769..86be2bc419 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.c @@ -10,7 +10,7 @@ * 2020-03-20 SummerGift fix bug caused by ORE * 2020-05-02 whj4674672 support stm32h7 uart dma * 2020-09-09 forest-rain support stm32wl uart - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx */ #include "board.h" diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h index 1d505b7d3a..f8b5e16af9 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_usart.h @@ -7,7 +7,7 @@ * Date Author Notes * 2018-10-30 SummerGift first version * 2019-03-05 whj4674672 add stm32h7 - * 2020-10-14 Dozingfiretruck Porting for stm32wbxx + * 2020-10-14 PeakRacing Porting for stm32wbxx */ #ifndef __DRV_USART_H__ diff --git a/bsp/stm32/libraries/templates/stm32wbxx/applications/main.c b/bsp/stm32/libraries/templates/stm32wbxx/applications/main.c index ce87056796..d7a3a330c9 100644 --- a/bsp/stm32/libraries/templates/stm32wbxx/applications/main.c +++ b/bsp/stm32/libraries/templates/stm32wbxx/applications/main.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-09-29 Dozingfiretruck first version + * 2020-09-29 PeakRacing first version */ #include diff --git a/bsp/stm32/stm32f407-armfly-v5/README.md b/bsp/stm32/stm32f407-armfly-v5/README.md index 0b43676e2a..8bf93f7460 100644 --- a/bsp/stm32/stm32f407-armfly-v5/README.md +++ b/bsp/stm32/stm32f407-armfly-v5/README.md @@ -130,4 +130,4 @@ msh > 维护人: -- [Dozingfiretruck](https://gitee.com/Dozingfiretruck), 邮箱： \ No newline at end of file +- [PeakRacing](https://gitee.com/PeakRacing), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f407-armfly-v5/applications/main.c b/bsp/stm32/stm32f407-armfly-v5/applications/main.c index d4ffbccdbf..b8f4116435 100644 --- a/bsp/stm32/stm32f407-armfly-v5/applications/main.c +++ b/bsp/stm32/stm32f407-armfly-v5/applications/main.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-13 Dozingfiretruck first version + * 2020-07-13 PeakRacing first version * 2023-12-03 Meco Man support nano version */ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.c b/bsp/stm32/stm32f407-armfly-v5/board/board.c index e80bcb0e7c..739b731834 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/board.c +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-13 Dozingfiretruck first version + * 2020-07-13 PeakRacing first version */ #include diff --git a/bsp/stm32/stm32f407-armfly-v5/board/board.h b/bsp/stm32/stm32f407-armfly-v5/board/board.h index 4e8feb60fd..0fe7bfbade 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/board.h +++ b/bsp/stm32/stm32f407-armfly-v5/board/board.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-13 Dozingfiretruck first version + * 2020-07-13 PeakRacing first version */ #ifndef __BOARD_H__ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h index c512fcef35..8a15f487e7 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/fal_cfg.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-13 Dozingfiretruck first version + * 2020-07-13 PeakRacing first version */ #ifndef _FAL_CFG_H_ diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c index 2b6e48ba3f..47e4371797 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/sdcard_port.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-13 Dozingfiretruck first version + * 2020-07-13 PeakRacing first version */ #include diff --git a/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c index 1f038b839b..b4e24b94f9 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c +++ b/bsp/stm32/stm32f407-armfly-v5/board/ports/spi_flash_init.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-07-13 Dozingfiretruck first version + * 2020-07-13 PeakRacing first version */ #include diff --git a/bsp/stm32/stm32wb55-st-nucleo/README.md b/bsp/stm32/stm32wb55-st-nucleo/README.md index f782e85456..28e9a93e48 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/README.md +++ b/bsp/stm32/stm32wb55-st-nucleo/README.md @@ -113,4 +113,4 @@ msh > 维护人: -- [Dozingfiretruck](https://gitee.com/Dozingfiretruck), 邮箱：<1473454180@qq.com> \ No newline at end of file +- [PeakRacing](https://gitee.com/PeakRacing), 邮箱：<1473454180@qq.com> \ No newline at end of file diff --git a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c index b4a71ebc08..a3ce887e5c 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/applications/main.c +++ b/bsp/stm32/stm32wb55-st-nucleo/applications/main.c @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-09-29 Dozingfiretruck first version + * 2020-09-29 PeakRacing first version */ #include diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h index e3c93996e7..09763f126e 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h +++ b/bsp/stm32/stm32wb55-st-nucleo/board/ports/fal_cfg.h @@ -5,7 +5,7 @@ * * Change Logs: * Date Author Notes - * 2020-09-29 Dozingfiretruck first version + * 2020-09-29 PeakRacing first version */ #ifndef _FAL_CFG_H_ -- Gitee From 7641ef68855601bc73252546bf41a96d6078444e Mon Sep 17 00:00:00 2001 From: lhxj <2743257167@qq.com> Date: Thu, 25 Dec 2025 17:56:52 +0800 Subject: [PATCH 11/45] [drivers] Fix OFW bus conflict and prevent duplicate device creation Problem: When enumerating device tree nodes, platform bus and native buses (I2C/SPI) may create duplicate devices for the same OFW node, causing cross-bus conflicts. This triggers assertion failure '(dev->bus != new_bus)' in rt_bus_reload_driver_device() during boot on minimal DM-enabled systems. Root Cause: 1. Platform bus tries to reload devices that already belong to other buses by calling rt_bus_reload_driver_device(dev->bus, dev), which violates the API contract (requires dev->bus != new_bus). 2. Native buses (I2C/SPI) do not mark OFW nodes as occupied, so platform bus creates duplicate platform devices for I2C/SPI client nodes. Solution: 1. components/drivers/core/platform_ofw.c: Return RT_EOK when np->dev exists, letting the native bus handle device lifecycle instead of cross-bus reload. 2. components/drivers/i2c/dev_i2c_bus.c: Mark i2c_client_np->dev during scan to prevent platform bus from duplicating I2C client devices. 3. components/drivers/spi/dev_spi_bus.c: Mark spi_dev_np->dev during scan to prevent platform bus from duplicating SPI devices. Tested on Spacemit K1 RISC-V platform with minimal DM configuration. Signed-off-by: lhxj <2743257167@qq.com> --- components/drivers/core/platform_ofw.c | 19 +++++++++---------- components/drivers/i2c/dev_i2c_bus.c | 4 ++++ components/drivers/spi/dev_spi_bus.c | 6 +++++- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/components/drivers/core/platform_ofw.c b/components/drivers/core/platform_ofw.c index 38065dd3eb..d617f112fa 100644 --- a/components/drivers/core/platform_ofw.c +++ b/components/drivers/core/platform_ofw.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2023-06-04 GuEe-GUI the first version + * 2025-12-25 lhxj fix OFW bus conflict and prevent duplicate device creation */ #include @@ -223,16 +224,14 @@ rt_err_t rt_platform_ofw_request(struct rt_ofw_node *np) if (dev) { - /* Was create */ - if (dev->drv) - { - /* Was probe OK */ - err = RT_EOK; - } - else - { - err = rt_bus_reload_driver_device(dev->bus, dev); - } + /* + * Device was already created (np->dev != NULL). + * - If it's already probed (dev->drv != NULL), nothing to do. + * - If not yet probed (dev->drv == NULL), it belongs to its native bus + * (e.g. I2C/SPI) which will handle probing; platform bus should not reload + * or transfer it, to avoid cross-bus conflicts. + */ + err = RT_EOK; } else { diff --git a/components/drivers/i2c/dev_i2c_bus.c b/components/drivers/i2c/dev_i2c_bus.c index 9e202dbd9a..6cad46951c 100644 --- a/components/drivers/i2c/dev_i2c_bus.c +++ b/components/drivers/i2c/dev_i2c_bus.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-12-06 GuEe-GUI first version + * 2025-12-25 lhxj mark OFW node as taken to prevent platform bus duplication */ #include @@ -63,6 +64,9 @@ void i2c_bus_scan_clients(struct rt_i2c_bus_device *bus) rt_dm_dev_set_name(&client->parent, "%s", client->name); + /* Mark this OFW node as taken to prevent platform bus from creating duplicate device */ + i2c_client_np->dev = &client->parent; + rt_i2c_device_register(client); if (i2c_client_np != child_np) diff --git a/components/drivers/spi/dev_spi_bus.c b/components/drivers/spi/dev_spi_bus.c index ed1f29eac8..32829b3d85 100644 --- a/components/drivers/spi/dev_spi_bus.c +++ b/components/drivers/spi/dev_spi_bus.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-12-06 GuEe-GUI first version + * 2025-12-25 lhxj mark OFW node as taken to prevent platform bus duplication; fix cppcheck warning */ #include "dev_spi_dm.h" @@ -69,6 +70,9 @@ void spi_bus_scan_devices(struct rt_spi_bus *bus) continue; } + /* Mark this OFW node as taken to prevent platform bus from creating duplicate device */ + spi_dev_np->dev = &spi_dev->parent; + rt_spi_device_register(spi_dev); } } @@ -163,7 +167,7 @@ static rt_err_t spi_probe(rt_device_t dev) rt_spidev_device_init(device, rt_dm_dev_get_name(&device->parent)); } - return err; + return RT_EOK; } static rt_err_t spi_remove(rt_device_t dev) -- Gitee From f556099146dd50f770c609711d48e17a201952bc Mon Sep 17 00:00:00 2001 From: dongly Date: Fri, 19 Dec 2025 11:18:43 +0800 Subject: [PATCH 12/45] [bsp] fix rtconfig.py SyntaxWarning --- bsp/Infineon/libraries/templates/PSOC62/rtconfig.py | 2 +- bsp/Infineon/libraries/templates/XMC7200D/rtconfig.py | 2 +- bsp/Infineon/psoc6-cy8ckit-062-BLE/rtconfig.py | 2 +- bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/rtconfig.py | 2 +- bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.py | 2 +- bsp/Infineon/psoc6-cy8ckit-062s4/rtconfig.py | 2 +- bsp/Infineon/psoc6-cy8cproto-062S3-4343W/rtconfig.py | 2 +- bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.py | 2 +- bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py | 2 +- bsp/Infineon/xmc7200-kit_xmc7200_evk/rtconfig.py | 2 +- bsp/airm2m/air105/rtconfig.py | 2 +- bsp/airm2m/air32f103/rtconfig.py | 2 +- bsp/apm32/apm32e103ze-evalboard/rtconfig.py | 2 +- bsp/apm32/apm32e103ze-tinyboard/rtconfig.py | 2 +- bsp/apm32/apm32f030r8-miniboard/rtconfig.py | 2 +- bsp/apm32/apm32f051r8-evalboard/rtconfig.py | 2 +- bsp/apm32/apm32f072vb-miniboard/rtconfig.py | 2 +- bsp/apm32/apm32f091vc-miniboard/rtconfig.py | 2 +- bsp/apm32/apm32f103vb-miniboard/rtconfig.py | 2 +- bsp/apm32/apm32f103xe-minibroard/rtconfig.py | 2 +- bsp/apm32/apm32f107vc-evalboard/rtconfig.py | 2 +- bsp/apm32/apm32f407ig-minibroard/rtconfig.py | 2 +- bsp/apm32/apm32f407zg-evalboard/rtconfig.py | 2 +- bsp/apm32/apm32s103vb-miniboard/rtconfig.py | 2 +- bsp/at32/at32a403a-start/rtconfig.py | 2 +- bsp/at32/at32a423-start/rtconfig.py | 2 +- bsp/at32/at32f402-start/rtconfig.py | 2 +- bsp/at32/at32f403a-start/rtconfig.py | 2 +- bsp/at32/at32f405-start/rtconfig.py | 2 +- bsp/at32/at32f407-start/rtconfig.py | 2 +- bsp/at32/at32f413-start/rtconfig.py | 2 +- bsp/at32/at32f415-start/rtconfig.py | 2 +- bsp/at32/at32f421-start/rtconfig.py | 2 +- bsp/at32/at32f423-start/rtconfig.py | 2 +- bsp/at32/at32f425-start/rtconfig.py | 2 +- bsp/at32/at32f435-start/rtconfig.py | 2 +- bsp/at32/at32f437-start/rtconfig.py | 2 +- bsp/at32/at32f455-start/rtconfig.py | 2 +- bsp/at32/at32f456-start/rtconfig.py | 2 +- bsp/at32/at32f457-start/rtconfig.py | 2 +- bsp/at32/at32m412-start/rtconfig.py | 2 +- bsp/at32/at32m416-start/rtconfig.py | 2 +- bsp/fm33lc026/rtconfig.py | 2 +- bsp/ft32/ft32f072xb-starter/rtconfig.py | 2 +- bsp/gd32/arm/gd32103c-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32105c-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32105r-start/rtconfig.py | 2 +- bsp/gd32/arm/gd32107c-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32205r-start/rtconfig.py | 2 +- bsp/gd32/arm/gd32207i-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32303c-start/rtconfig.py | 2 +- bsp/gd32/arm/gd32303e-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32305r-start/rtconfig.py | 2 +- bsp/gd32/arm/gd32307e-start/rtconfig.py | 2 +- bsp/gd32/arm/gd32407v-lckfb/rtconfig.py | 2 +- bsp/gd32/arm/gd32407v-start/rtconfig.py | 2 +- bsp/gd32/arm/gd32450z-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32470i-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32470z-lckfb/rtconfig.py | 2 +- bsp/gd32/arm/gd32527I-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32e503v-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32h759i-eval/rtconfig.py | 2 +- bsp/gd32/arm/gd32h759i-start/rtconfig.py | 2 +- bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py | 2 +- bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py | 2 +- bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py | 2 +- bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py | 2 +- bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py | 2 +- bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.py | 2 +- bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py | 2 +- bsp/hc32l196/rtconfig.py | 2 +- bsp/hk32/hk32f030c8-mini/rtconfig.py | 2 +- bsp/ht32/ht32f12366/rtconfig.py | 2 +- bsp/ht32/ht32f52352/rtconfig.py | 2 +- bsp/ht32/ht32f53252/rtconfig.py | 2 +- bsp/mm32/mm32f3270-100ask-pitaya/rtconfig.py | 2 +- bsp/msp432e401y-LaunchPad/rtconfig.py | 2 +- bsp/n32/n32g43xcl-stb/rtconfig.py | 2 +- bsp/n32/n32g457qel-stb/rtconfig.py | 2 +- bsp/n32/n32g45xcl-stb/rtconfig.py | 2 +- bsp/n32/n32g45xml-stb/rtconfig.py | 2 +- bsp/n32/n32g45xrl-stb/rtconfig.py | 2 +- bsp/n32/n32g45xvl-stb/rtconfig.py | 2 +- bsp/n32/n32g4frml-stb/rtconfig.py | 2 +- bsp/n32/n32l40xcl-stb/rtconfig.py | 2 +- bsp/n32/n32l436-evb/rtconfig.py | 2 +- bsp/n32/n32l43xml-stb/rtconfig.py | 2 +- bsp/n32/n32l43xrl-stb/rtconfig.py | 2 +- bsp/n32/n32wb45xl-evb/rtconfig.py | 2 +- bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32f10x/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32f3xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py | 2 +- bsp/stm32/libraries/templates/stm32mp1xx/rtconfig.py | 2 +- bsp/stm32/stm32f072-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f091-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f103-100ask-mini/rtconfig.py | 2 +- bsp/stm32/stm32f103-100ask-pro/rtconfig.py | 2 +- bsp/stm32/stm32f103-atk-nano/rtconfig.py | 2 +- bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py | 2 +- bsp/stm32/stm32f103-blue-pill/rtconfig.py | 2 +- bsp/stm32/stm32f103-dofly-M3S/rtconfig.py | 2 +- bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py | 2 +- bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py | 2 +- bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py | 2 +- bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py | 2 +- bsp/stm32/stm32f103-keysking-learning/rtconfig.py | 2 +- bsp/stm32/stm32f103-onenet-nbiot/rtconfig.py | 2 +- bsp/stm32/stm32f103-yf-ufun/rtconfig.py | 2 +- bsp/stm32/stm32f103-ys-f1pro/rtconfig.py | 2 +- bsp/stm32/stm32f107-uc-eval/rtconfig.py | 2 +- bsp/stm32/stm32f207-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f302-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f334-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f401-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f401-weact-blackpill/rtconfig.py | 2 +- bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py | 2 +- bsp/stm32/stm32f405zg-mini-template/rtconfig.py | 2 +- bsp/stm32/stm32f407-armfly-v5/rtconfig.py | 2 +- bsp/stm32/stm32f407-atk-explorer/rtconfig.py | 2 +- bsp/stm32/stm32f407-fk407m2-zgt6/rtconfig.py | 2 +- bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py | 2 +- bsp/stm32/stm32f407-micu/rtconfig.py | 2 +- bsp/stm32/stm32f407-robomaster-c/rtconfig.py | 2 +- bsp/stm32/stm32f407-rt-spark/rtconfig.py | 2 +- bsp/stm32/stm32f407-st-discovery/rtconfig.py | 2 +- bsp/stm32/stm32f410-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f411-atk-nano/rtconfig.py | 2 +- bsp/stm32/stm32f411-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f411-weact-blackpill/rtconfig.py | 2 +- bsp/stm32/stm32f413-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f427-robomaster-a/rtconfig.py | 2 +- bsp/stm32/stm32f429-armfly-v6/rtconfig.py | 2 +- bsp/stm32/stm32f429-atk-apollo/rtconfig.py | 2 +- bsp/stm32/stm32f429-fire-challenger/rtconfig.py | 2 +- bsp/stm32/stm32f429-st-disco/rtconfig.py | 2 +- bsp/stm32/stm32f446-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32f469-st-disco/rtconfig.py | 2 +- bsp/stm32/stm32f767-atk-apollo/rtconfig.py | 2 +- bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py | 2 +- bsp/stm32/stm32f769-st-disco/rtconfig.py | 2 +- bsp/stm32/stm32g030-tiny-board/rtconfig.py | 2 +- bsp/stm32/stm32g070-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32g071-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32g431-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32g474-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32g491-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32h723-lxb-disco/rtconfig.py | 2 +- bsp/stm32/stm32h723-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32h730-esphosted-evb/rtconfig.py | 2 +- bsp/stm32/stm32h743-armfly-v7/rtconfig.py | 2 +- bsp/stm32/stm32h743-atk-apollo/rtconfig.py | 2 +- bsp/stm32/stm32h743-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32h747-st-discovery/rtconfig.py | 2 +- bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py | 2 +- bsp/stm32/stm32h750-artpi/rtconfig.py | 2 +- bsp/stm32/stm32h750-fk750m1-vbt6/rtconfig.py | 2 +- bsp/stm32/stm32h750-weact-ministm32h7xx/rtconfig.py | 2 +- bsp/stm32/stm32h7r7-artpi2/rtconfig.py | 2 +- bsp/stm32/stm32h7s7-st-disco/rtconfig.py | 2 +- bsp/stm32/stm32l010-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32l053-st-nucleo/rtconfig.py | 2 +- bsp/stm32/stm32mp157a-st-discovery/rtconfig.py | 2 +- bsp/stm32/stm32mp157a-st-ev1/rtconfig.py | 2 +- bsp/tm4c123bsp/rtconfig.py | 2 +- 170 files changed, 170 insertions(+), 170 deletions(-) diff --git a/bsp/Infineon/libraries/templates/PSOC62/rtconfig.py b/bsp/Infineon/libraries/templates/PSOC62/rtconfig.py index 4f41f6d9c2..894f6c293b 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/rtconfig.py +++ b/bsp/Infineon/libraries/templates/PSOC62/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/libraries/templates/XMC7200D/rtconfig.py b/bsp/Infineon/libraries/templates/XMC7200D/rtconfig.py index 283ed8e6ca..0dcdaa5c40 100644 --- a/bsp/Infineon/libraries/templates/XMC7200D/rtconfig.py +++ b/bsp/Infineon/libraries/templates/XMC7200D/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/psoc6-cy8ckit-062-BLE/rtconfig.py b/bsp/Infineon/psoc6-cy8ckit-062-BLE/rtconfig.py index 4f41f6d9c2..894f6c293b 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-BLE/rtconfig.py +++ b/bsp/Infineon/psoc6-cy8ckit-062-BLE/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/rtconfig.py b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/rtconfig.py index 25e6679827..4b4885055e 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/rtconfig.py +++ b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.py b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.py index 25e6679827..4b4885055e 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.py +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/psoc6-cy8ckit-062s4/rtconfig.py b/bsp/Infineon/psoc6-cy8ckit-062s4/rtconfig.py index 4f41f6d9c2..894f6c293b 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062s4/rtconfig.py +++ b/bsp/Infineon/psoc6-cy8ckit-062s4/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/rtconfig.py b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/rtconfig.py index 25e6679827..4b4885055e 100644 --- a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/rtconfig.py +++ b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.py b/bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.py index 25e6679827..4b4885055e 100644 --- a/bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.py +++ b/bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py b/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py index b7c20229f5..a08b29958a 100644 --- a/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py +++ b/bsp/Infineon/xmc7100d-f144k4160aa/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/Infineon/xmc7200-kit_xmc7200_evk/rtconfig.py b/bsp/Infineon/xmc7200-kit_xmc7200_evk/rtconfig.py index 283ed8e6ca..0dcdaa5c40 100644 --- a/bsp/Infineon/xmc7200-kit_xmc7200_evk/rtconfig.py +++ b/bsp/Infineon/xmc7200-kit_xmc7200_evk/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/airm2m/air105/rtconfig.py b/bsp/airm2m/air105/rtconfig.py index 2b44ba2996..4b7a12385d 100644 --- a/bsp/airm2m/air105/rtconfig.py +++ b/bsp/airm2m/air105/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/airm2m/air32f103/rtconfig.py b/bsp/airm2m/air32f103/rtconfig.py index f0ab55a0e4..d04a49f7ef 100644 --- a/bsp/airm2m/air32f103/rtconfig.py +++ b/bsp/airm2m/air32f103/rtconfig.py @@ -75,7 +75,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32e103ze-evalboard/rtconfig.py b/bsp/apm32/apm32e103ze-evalboard/rtconfig.py index 7b1531669a..37a1bf71ae 100644 --- a/bsp/apm32/apm32e103ze-evalboard/rtconfig.py +++ b/bsp/apm32/apm32e103ze-evalboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32e103ze-tinyboard/rtconfig.py b/bsp/apm32/apm32e103ze-tinyboard/rtconfig.py index 7b1531669a..37a1bf71ae 100644 --- a/bsp/apm32/apm32e103ze-tinyboard/rtconfig.py +++ b/bsp/apm32/apm32e103ze-tinyboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f030r8-miniboard/rtconfig.py b/bsp/apm32/apm32f030r8-miniboard/rtconfig.py index eca7e715d3..035956988b 100644 --- a/bsp/apm32/apm32f030r8-miniboard/rtconfig.py +++ b/bsp/apm32/apm32f030r8-miniboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f051r8-evalboard/rtconfig.py b/bsp/apm32/apm32f051r8-evalboard/rtconfig.py index eca7e715d3..035956988b 100644 --- a/bsp/apm32/apm32f051r8-evalboard/rtconfig.py +++ b/bsp/apm32/apm32f051r8-evalboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f072vb-miniboard/rtconfig.py b/bsp/apm32/apm32f072vb-miniboard/rtconfig.py index 2fd6753c9b..b35806edda 100644 --- a/bsp/apm32/apm32f072vb-miniboard/rtconfig.py +++ b/bsp/apm32/apm32f072vb-miniboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f091vc-miniboard/rtconfig.py b/bsp/apm32/apm32f091vc-miniboard/rtconfig.py index 2fd6753c9b..b35806edda 100644 --- a/bsp/apm32/apm32f091vc-miniboard/rtconfig.py +++ b/bsp/apm32/apm32f091vc-miniboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f103vb-miniboard/rtconfig.py b/bsp/apm32/apm32f103vb-miniboard/rtconfig.py index 483a7656f8..0a94eb8b22 100644 --- a/bsp/apm32/apm32f103vb-miniboard/rtconfig.py +++ b/bsp/apm32/apm32f103vb-miniboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f103xe-minibroard/rtconfig.py b/bsp/apm32/apm32f103xe-minibroard/rtconfig.py index 7b1531669a..37a1bf71ae 100644 --- a/bsp/apm32/apm32f103xe-minibroard/rtconfig.py +++ b/bsp/apm32/apm32f103xe-minibroard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f107vc-evalboard/rtconfig.py b/bsp/apm32/apm32f107vc-evalboard/rtconfig.py index 7b1531669a..37a1bf71ae 100644 --- a/bsp/apm32/apm32f107vc-evalboard/rtconfig.py +++ b/bsp/apm32/apm32f107vc-evalboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f407ig-minibroard/rtconfig.py b/bsp/apm32/apm32f407ig-minibroard/rtconfig.py index 45c2f0bc96..83e0233b20 100644 --- a/bsp/apm32/apm32f407ig-minibroard/rtconfig.py +++ b/bsp/apm32/apm32f407ig-minibroard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32f407zg-evalboard/rtconfig.py b/bsp/apm32/apm32f407zg-evalboard/rtconfig.py index 8153d85923..6bb1bd7030 100644 --- a/bsp/apm32/apm32f407zg-evalboard/rtconfig.py +++ b/bsp/apm32/apm32f407zg-evalboard/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/apm32/apm32s103vb-miniboard/rtconfig.py b/bsp/apm32/apm32s103vb-miniboard/rtconfig.py index 7b1531669a..37a1bf71ae 100644 --- a/bsp/apm32/apm32s103vb-miniboard/rtconfig.py +++ b/bsp/apm32/apm32s103vb-miniboard/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32a403a-start/rtconfig.py b/bsp/at32/at32a403a-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32a403a-start/rtconfig.py +++ b/bsp/at32/at32a403a-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32a423-start/rtconfig.py b/bsp/at32/at32a423-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32a423-start/rtconfig.py +++ b/bsp/at32/at32a423-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f402-start/rtconfig.py b/bsp/at32/at32f402-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f402-start/rtconfig.py +++ b/bsp/at32/at32f402-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f403a-start/rtconfig.py b/bsp/at32/at32f403a-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f403a-start/rtconfig.py +++ b/bsp/at32/at32f403a-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f405-start/rtconfig.py b/bsp/at32/at32f405-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f405-start/rtconfig.py +++ b/bsp/at32/at32f405-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f407-start/rtconfig.py b/bsp/at32/at32f407-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f407-start/rtconfig.py +++ b/bsp/at32/at32f407-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f413-start/rtconfig.py b/bsp/at32/at32f413-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f413-start/rtconfig.py +++ b/bsp/at32/at32f413-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f415-start/rtconfig.py b/bsp/at32/at32f415-start/rtconfig.py index 84a45272f9..438cfb028d 100644 --- a/bsp/at32/at32f415-start/rtconfig.py +++ b/bsp/at32/at32f415-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f421-start/rtconfig.py b/bsp/at32/at32f421-start/rtconfig.py index 84a45272f9..438cfb028d 100644 --- a/bsp/at32/at32f421-start/rtconfig.py +++ b/bsp/at32/at32f421-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f423-start/rtconfig.py b/bsp/at32/at32f423-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f423-start/rtconfig.py +++ b/bsp/at32/at32f423-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f425-start/rtconfig.py b/bsp/at32/at32f425-start/rtconfig.py index 84a45272f9..438cfb028d 100644 --- a/bsp/at32/at32f425-start/rtconfig.py +++ b/bsp/at32/at32f425-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f435-start/rtconfig.py b/bsp/at32/at32f435-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f435-start/rtconfig.py +++ b/bsp/at32/at32f435-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f437-start/rtconfig.py b/bsp/at32/at32f437-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f437-start/rtconfig.py +++ b/bsp/at32/at32f437-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f455-start/rtconfig.py b/bsp/at32/at32f455-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f455-start/rtconfig.py +++ b/bsp/at32/at32f455-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f456-start/rtconfig.py b/bsp/at32/at32f456-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f456-start/rtconfig.py +++ b/bsp/at32/at32f456-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32f457-start/rtconfig.py b/bsp/at32/at32f457-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32f457-start/rtconfig.py +++ b/bsp/at32/at32f457-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32m412-start/rtconfig.py b/bsp/at32/at32m412-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32m412-start/rtconfig.py +++ b/bsp/at32/at32m412-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/at32/at32m416-start/rtconfig.py b/bsp/at32/at32m416-start/rtconfig.py index fa627618e8..03ef518902 100644 --- a/bsp/at32/at32m416-start/rtconfig.py +++ b/bsp/at32/at32m416-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/fm33lc026/rtconfig.py b/bsp/fm33lc026/rtconfig.py index 19cd290404..aa5a02af42 100644 --- a/bsp/fm33lc026/rtconfig.py +++ b/bsp/fm33lc026/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/ft32/ft32f072xb-starter/rtconfig.py b/bsp/ft32/ft32f072xb-starter/rtconfig.py index 9818b62f9d..defc57f149 100644 --- a/bsp/ft32/ft32f072xb-starter/rtconfig.py +++ b/bsp/ft32/ft32f072xb-starter/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32103c-eval/rtconfig.py b/bsp/gd32/arm/gd32103c-eval/rtconfig.py index a06cb7c4e6..cc2b68f0ea 100644 --- a/bsp/gd32/arm/gd32103c-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32103c-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32105c-eval/rtconfig.py b/bsp/gd32/arm/gd32105c-eval/rtconfig.py index a06cb7c4e6..cc2b68f0ea 100644 --- a/bsp/gd32/arm/gd32105c-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32105c-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32105r-start/rtconfig.py b/bsp/gd32/arm/gd32105r-start/rtconfig.py index 6c9b6ea8dc..20c8f2bc3b 100644 --- a/bsp/gd32/arm/gd32105r-start/rtconfig.py +++ b/bsp/gd32/arm/gd32105r-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3.fp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32107c-eval/rtconfig.py b/bsp/gd32/arm/gd32107c-eval/rtconfig.py index a06cb7c4e6..cc2b68f0ea 100644 --- a/bsp/gd32/arm/gd32107c-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32107c-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32205r-start/rtconfig.py b/bsp/gd32/arm/gd32205r-start/rtconfig.py index a06cb7c4e6..cc2b68f0ea 100644 --- a/bsp/gd32/arm/gd32205r-start/rtconfig.py +++ b/bsp/gd32/arm/gd32205r-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32207i-eval/rtconfig.py b/bsp/gd32/arm/gd32207i-eval/rtconfig.py index a06cb7c4e6..cc2b68f0ea 100644 --- a/bsp/gd32/arm/gd32207i-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32207i-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32303c-start/rtconfig.py b/bsp/gd32/arm/gd32303c-start/rtconfig.py index 93e0bbe48f..555edb6d01 100644 --- a/bsp/gd32/arm/gd32303c-start/rtconfig.py +++ b/bsp/gd32/arm/gd32303c-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32303e-eval/rtconfig.py b/bsp/gd32/arm/gd32303e-eval/rtconfig.py index 93e0bbe48f..555edb6d01 100644 --- a/bsp/gd32/arm/gd32303e-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32303e-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32305r-start/rtconfig.py b/bsp/gd32/arm/gd32305r-start/rtconfig.py index 93e0bbe48f..555edb6d01 100644 --- a/bsp/gd32/arm/gd32305r-start/rtconfig.py +++ b/bsp/gd32/arm/gd32305r-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32307e-start/rtconfig.py b/bsp/gd32/arm/gd32307e-start/rtconfig.py index 93e0bbe48f..555edb6d01 100644 --- a/bsp/gd32/arm/gd32307e-start/rtconfig.py +++ b/bsp/gd32/arm/gd32307e-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32407v-lckfb/rtconfig.py b/bsp/gd32/arm/gd32407v-lckfb/rtconfig.py index d37afd4c07..f6fe699ce4 100644 --- a/bsp/gd32/arm/gd32407v-lckfb/rtconfig.py +++ b/bsp/gd32/arm/gd32407v-lckfb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32407v-start/rtconfig.py b/bsp/gd32/arm/gd32407v-start/rtconfig.py index d37afd4c07..f6fe699ce4 100644 --- a/bsp/gd32/arm/gd32407v-start/rtconfig.py +++ b/bsp/gd32/arm/gd32407v-start/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32450z-eval/rtconfig.py b/bsp/gd32/arm/gd32450z-eval/rtconfig.py index 99336a8ad4..d150e13252 100644 --- a/bsp/gd32/arm/gd32450z-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32450z-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32470i-eval/rtconfig.py b/bsp/gd32/arm/gd32470i-eval/rtconfig.py index b2361d1052..fcb68ff6a0 100644 --- a/bsp/gd32/arm/gd32470i-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32470i-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armclang': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py b/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py index ac947b28c1..1a71c0e964 100644 --- a/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py +++ b/bsp/gd32/arm/gd32470z-lckfb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armclang': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32527I-eval/rtconfig.py b/bsp/gd32/arm/gd32527I-eval/rtconfig.py index af4839de00..38013f507c 100644 --- a/bsp/gd32/arm/gd32527I-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32527I-eval/rtconfig.py @@ -107,7 +107,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M33.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32e503v-eval/rtconfig.py b/bsp/gd32/arm/gd32e503v-eval/rtconfig.py index 93e0bbe48f..555edb6d01 100644 --- a/bsp/gd32/arm/gd32e503v-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32e503v-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32h759i-eval/rtconfig.py b/bsp/gd32/arm/gd32h759i-eval/rtconfig.py index 5df9eca7e6..d0db2c1742 100644 --- a/bsp/gd32/arm/gd32h759i-eval/rtconfig.py +++ b/bsp/gd32/arm/gd32h759i-eval/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/gd32/arm/gd32h759i-start/rtconfig.py b/bsp/gd32/arm/gd32h759i-start/rtconfig.py index 5df9eca7e6..d0db2c1742 100644 --- a/bsp/gd32/arm/gd32h759i-start/rtconfig.py +++ b/bsp/gd32/arm/gd32h759i-start/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py +++ b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py +++ b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py b/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py +++ b/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.py b/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.py +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py index 568d50f2a6..0af49fd02b 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hc32l196/rtconfig.py b/bsp/hc32l196/rtconfig.py index a63cea240e..ca2b698076 100644 --- a/bsp/hc32l196/rtconfig.py +++ b/bsp/hc32l196/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/hk32/hk32f030c8-mini/rtconfig.py b/bsp/hk32/hk32f030c8-mini/rtconfig.py index 97aa33f0c5..d6e1b750b0 100644 --- a/bsp/hk32/hk32f030c8-mini/rtconfig.py +++ b/bsp/hk32/hk32f030c8-mini/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/ht32/ht32f12366/rtconfig.py b/bsp/ht32/ht32f12366/rtconfig.py index 33ae6cc4fa..159b468889 100644 --- a/bsp/ht32/ht32f12366/rtconfig.py +++ b/bsp/ht32/ht32f12366/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/ht32/ht32f52352/rtconfig.py b/bsp/ht32/ht32f52352/rtconfig.py index 0525f0267a..59ebb20215 100644 --- a/bsp/ht32/ht32f52352/rtconfig.py +++ b/bsp/ht32/ht32f52352/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/ht32/ht32f53252/rtconfig.py b/bsp/ht32/ht32f53252/rtconfig.py index 6f853dccc2..1350ba71bf 100644 --- a/bsp/ht32/ht32f53252/rtconfig.py +++ b/bsp/ht32/ht32f53252/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/mm32/mm32f3270-100ask-pitaya/rtconfig.py b/bsp/mm32/mm32f3270-100ask-pitaya/rtconfig.py index 0c161f9756..2eafb3e54a 100644 --- a/bsp/mm32/mm32f3270-100ask-pitaya/rtconfig.py +++ b/bsp/mm32/mm32f3270-100ask-pitaya/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/msp432e401y-LaunchPad/rtconfig.py b/bsp/msp432e401y-LaunchPad/rtconfig.py index 4b90fc76bf..9d45314715 100644 --- a/bsp/msp432e401y-LaunchPad/rtconfig.py +++ b/bsp/msp432e401y-LaunchPad/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g43xcl-stb/rtconfig.py b/bsp/n32/n32g43xcl-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g43xcl-stb/rtconfig.py +++ b/bsp/n32/n32g43xcl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g457qel-stb/rtconfig.py b/bsp/n32/n32g457qel-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g457qel-stb/rtconfig.py +++ b/bsp/n32/n32g457qel-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g45xcl-stb/rtconfig.py b/bsp/n32/n32g45xcl-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g45xcl-stb/rtconfig.py +++ b/bsp/n32/n32g45xcl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g45xml-stb/rtconfig.py b/bsp/n32/n32g45xml-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g45xml-stb/rtconfig.py +++ b/bsp/n32/n32g45xml-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g45xrl-stb/rtconfig.py b/bsp/n32/n32g45xrl-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g45xrl-stb/rtconfig.py +++ b/bsp/n32/n32g45xrl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g45xvl-stb/rtconfig.py b/bsp/n32/n32g45xvl-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g45xvl-stb/rtconfig.py +++ b/bsp/n32/n32g45xvl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g4frml-stb/rtconfig.py b/bsp/n32/n32g4frml-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32g4frml-stb/rtconfig.py +++ b/bsp/n32/n32g4frml-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32l40xcl-stb/rtconfig.py b/bsp/n32/n32l40xcl-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32l40xcl-stb/rtconfig.py +++ b/bsp/n32/n32l40xcl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32l436-evb/rtconfig.py b/bsp/n32/n32l436-evb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32l436-evb/rtconfig.py +++ b/bsp/n32/n32l436-evb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32l43xml-stb/rtconfig.py b/bsp/n32/n32l43xml-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32l43xml-stb/rtconfig.py +++ b/bsp/n32/n32l43xml-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32l43xrl-stb/rtconfig.py b/bsp/n32/n32l43xrl-stb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32l43xrl-stb/rtconfig.py +++ b/bsp/n32/n32l43xrl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32wb45xl-evb/rtconfig.py b/bsp/n32/n32wb45xl-evb/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/n32/n32wb45xl-evb/rtconfig.py +++ b/bsp/n32/n32wb45xl-evb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py index c7cbe3fb64..0c111382af 100755 --- a/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py +++ b/bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py @@ -79,7 +79,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py index 9b8d8076e0..76f60a8b01 100644 --- a/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f0xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py index 7ed928ddba..094633253e 100644 --- a/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f10x/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py index 3e047b559c..2b11276521 100644 --- a/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f2xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32f3xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f3xx/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/libraries/templates/stm32f3xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f3xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f4xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py index 06215daed3..2417d2eba7 100644 --- a/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py index 8da8c57718..ad180fbfdf 100644 --- a/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32h7xx/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py index fa54f25493..c89dbafcd4 100644 --- a/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32l1xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/libraries/templates/stm32mp1xx/rtconfig.py b/bsp/stm32/libraries/templates/stm32mp1xx/rtconfig.py index d2446f9fde..70a527b6fe 100644 --- a/bsp/stm32/libraries/templates/stm32mp1xx/rtconfig.py +++ b/bsp/stm32/libraries/templates/stm32mp1xx/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f072-st-nucleo/rtconfig.py b/bsp/stm32/stm32f072-st-nucleo/rtconfig.py index 9818b62f9d..defc57f149 100644 --- a/bsp/stm32/stm32f072-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f072-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f091-st-nucleo/rtconfig.py b/bsp/stm32/stm32f091-st-nucleo/rtconfig.py index 5f41e855a3..d84dcf07c1 100644 --- a/bsp/stm32/stm32f091-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f091-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-100ask-mini/rtconfig.py b/bsp/stm32/stm32f103-100ask-mini/rtconfig.py index d1e49f8cb1..1169581b53 100644 --- a/bsp/stm32/stm32f103-100ask-mini/rtconfig.py +++ b/bsp/stm32/stm32f103-100ask-mini/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-100ask-pro/rtconfig.py b/bsp/stm32/stm32f103-100ask-pro/rtconfig.py index d1e49f8cb1..1169581b53 100644 --- a/bsp/stm32/stm32f103-100ask-pro/rtconfig.py +++ b/bsp/stm32/stm32f103-100ask-pro/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-atk-nano/rtconfig.py b/bsp/stm32/stm32f103-atk-nano/rtconfig.py index 4f3ce9e99a..f77904a462 100644 --- a/bsp/stm32/stm32f103-atk-nano/rtconfig.py +++ b/bsp/stm32/stm32f103-atk-nano/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py b/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py index 558924a36a..71a9ed0a53 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py +++ b/bsp/stm32/stm32f103-atk-warshipv3/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-blue-pill/rtconfig.py b/bsp/stm32/stm32f103-blue-pill/rtconfig.py index 5334a94faa..b8c631c4ef 100644 --- a/bsp/stm32/stm32f103-blue-pill/rtconfig.py +++ b/bsp/stm32/stm32f103-blue-pill/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py b/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py index 61ba95699e..ffb2af80c6 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py +++ b/bsp/stm32/stm32f103-dofly-M3S/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py b/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py index ea0c3aee4a..80adfae3bc 100644 --- a/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py +++ b/bsp/stm32/stm32f103-dofly-lyc8/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py index b90f7e65a9..aea30bd9f3 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py +++ b/bsp/stm32/stm32f103-fire-arbitrary/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py b/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py index 558924a36a..71a9ed0a53 100644 --- a/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py +++ b/bsp/stm32/stm32f103-gizwits-gokitv21/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py b/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py index 558924a36a..71a9ed0a53 100644 --- a/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py +++ b/bsp/stm32/stm32f103-hw100k-ibox/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-keysking-learning/rtconfig.py b/bsp/stm32/stm32f103-keysking-learning/rtconfig.py index 5334a94faa..b8c631c4ef 100644 --- a/bsp/stm32/stm32f103-keysking-learning/rtconfig.py +++ b/bsp/stm32/stm32f103-keysking-learning/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-onenet-nbiot/rtconfig.py b/bsp/stm32/stm32f103-onenet-nbiot/rtconfig.py index 03db7f3826..ca39ddee7c 100644 --- a/bsp/stm32/stm32f103-onenet-nbiot/rtconfig.py +++ b/bsp/stm32/stm32f103-onenet-nbiot/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-yf-ufun/rtconfig.py b/bsp/stm32/stm32f103-yf-ufun/rtconfig.py index 558924a36a..71a9ed0a53 100644 --- a/bsp/stm32/stm32f103-yf-ufun/rtconfig.py +++ b/bsp/stm32/stm32f103-yf-ufun/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f103-ys-f1pro/rtconfig.py b/bsp/stm32/stm32f103-ys-f1pro/rtconfig.py index 558924a36a..71a9ed0a53 100644 --- a/bsp/stm32/stm32f103-ys-f1pro/rtconfig.py +++ b/bsp/stm32/stm32f103-ys-f1pro/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f107-uc-eval/rtconfig.py b/bsp/stm32/stm32f107-uc-eval/rtconfig.py index b90f7e65a9..aea30bd9f3 100644 --- a/bsp/stm32/stm32f107-uc-eval/rtconfig.py +++ b/bsp/stm32/stm32f107-uc-eval/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f207-st-nucleo/rtconfig.py b/bsp/stm32/stm32f207-st-nucleo/rtconfig.py index 3e047b559c..2b11276521 100644 --- a/bsp/stm32/stm32f207-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f207-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M3 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f302-st-nucleo/rtconfig.py b/bsp/stm32/stm32f302-st-nucleo/rtconfig.py index 9d514aa1a8..e564a53fbe 100644 --- a/bsp/stm32/stm32f302-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f302-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f334-st-nucleo/rtconfig.py b/bsp/stm32/stm32f334-st-nucleo/rtconfig.py index 9d514aa1a8..e564a53fbe 100644 --- a/bsp/stm32/stm32f334-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f334-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f401-st-nucleo/rtconfig.py b/bsp/stm32/stm32f401-st-nucleo/rtconfig.py index cc91404e87..f843ab6fa3 100644 --- a/bsp/stm32/stm32f401-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f401-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f401-weact-blackpill/rtconfig.py b/bsp/stm32/stm32f401-weact-blackpill/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f401-weact-blackpill/rtconfig.py +++ b/bsp/stm32/stm32f401-weact-blackpill/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py b/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py index 1027da3a96..7a11d11066 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py +++ b/bsp/stm32/stm32f405-smdz-breadfruit/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f405zg-mini-template/rtconfig.py b/bsp/stm32/stm32f405zg-mini-template/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f405zg-mini-template/rtconfig.py +++ b/bsp/stm32/stm32f405zg-mini-template/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-armfly-v5/rtconfig.py b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f407-armfly-v5/rtconfig.py +++ b/bsp/stm32/stm32f407-armfly-v5/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-atk-explorer/rtconfig.py b/bsp/stm32/stm32f407-atk-explorer/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f407-atk-explorer/rtconfig.py +++ b/bsp/stm32/stm32f407-atk-explorer/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-fk407m2-zgt6/rtconfig.py b/bsp/stm32/stm32f407-fk407m2-zgt6/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f407-fk407m2-zgt6/rtconfig.py +++ b/bsp/stm32/stm32f407-fk407m2-zgt6/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py b/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py index 8195d720df..771c140e4f 100644 --- a/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py +++ b/bsp/stm32/stm32f407-lckfb-skystar/rtconfig.py @@ -77,7 +77,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-micu/rtconfig.py b/bsp/stm32/stm32f407-micu/rtconfig.py index 3d6cf9996b..20d2c181a2 100644 --- a/bsp/stm32/stm32f407-micu/rtconfig.py +++ b/bsp/stm32/stm32f407-micu/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-robomaster-c/rtconfig.py b/bsp/stm32/stm32f407-robomaster-c/rtconfig.py index fa38f4e52b..492309124c 100644 --- a/bsp/stm32/stm32f407-robomaster-c/rtconfig.py +++ b/bsp/stm32/stm32f407-robomaster-c/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-rt-spark/rtconfig.py b/bsp/stm32/stm32f407-rt-spark/rtconfig.py index 41c4b00ffb..83aea1098e 100644 --- a/bsp/stm32/stm32f407-rt-spark/rtconfig.py +++ b/bsp/stm32/stm32f407-rt-spark/rtconfig.py @@ -78,7 +78,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f407-st-discovery/rtconfig.py b/bsp/stm32/stm32f407-st-discovery/rtconfig.py index d2446f9fde..70a527b6fe 100644 --- a/bsp/stm32/stm32f407-st-discovery/rtconfig.py +++ b/bsp/stm32/stm32f407-st-discovery/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f410-st-nucleo/rtconfig.py b/bsp/stm32/stm32f410-st-nucleo/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/stm32/stm32f410-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f410-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f411-atk-nano/rtconfig.py b/bsp/stm32/stm32f411-atk-nano/rtconfig.py index f92cd4c85f..7352b3dbb8 100644 --- a/bsp/stm32/stm32f411-atk-nano/rtconfig.py +++ b/bsp/stm32/stm32f411-atk-nano/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f411-st-nucleo/rtconfig.py b/bsp/stm32/stm32f411-st-nucleo/rtconfig.py index 72a60ae53f..4d1781fd68 100644 --- a/bsp/stm32/stm32f411-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f411-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f411-weact-blackpill/rtconfig.py b/bsp/stm32/stm32f411-weact-blackpill/rtconfig.py index c3765e6f08..2a0371110c 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/rtconfig.py +++ b/bsp/stm32/stm32f411-weact-blackpill/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f413-st-nucleo/rtconfig.py b/bsp/stm32/stm32f413-st-nucleo/rtconfig.py index f92cd4c85f..7352b3dbb8 100644 --- a/bsp/stm32/stm32f413-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f413-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f427-robomaster-a/rtconfig.py b/bsp/stm32/stm32f427-robomaster-a/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f427-robomaster-a/rtconfig.py +++ b/bsp/stm32/stm32f427-robomaster-a/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f429-armfly-v6/rtconfig.py b/bsp/stm32/stm32f429-armfly-v6/rtconfig.py index df5ad74299..605ef8bfcc 100644 --- a/bsp/stm32/stm32f429-armfly-v6/rtconfig.py +++ b/bsp/stm32/stm32f429-armfly-v6/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f429-atk-apollo/rtconfig.py b/bsp/stm32/stm32f429-atk-apollo/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f429-atk-apollo/rtconfig.py +++ b/bsp/stm32/stm32f429-atk-apollo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f429-fire-challenger/rtconfig.py b/bsp/stm32/stm32f429-fire-challenger/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f429-fire-challenger/rtconfig.py +++ b/bsp/stm32/stm32f429-fire-challenger/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f429-st-disco/rtconfig.py b/bsp/stm32/stm32f429-st-disco/rtconfig.py index d2446f9fde..70a527b6fe 100644 --- a/bsp/stm32/stm32f429-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f429-st-disco/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f446-st-nucleo/rtconfig.py b/bsp/stm32/stm32f446-st-nucleo/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32f446-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32f446-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f469-st-disco/rtconfig.py b/bsp/stm32/stm32f469-st-disco/rtconfig.py index d2446f9fde..70a527b6fe 100644 --- a/bsp/stm32/stm32f469-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f469-st-disco/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f767-atk-apollo/rtconfig.py b/bsp/stm32/stm32f767-atk-apollo/rtconfig.py index 663c053f39..266b5df1a3 100644 --- a/bsp/stm32/stm32f767-atk-apollo/rtconfig.py +++ b/bsp/stm32/stm32f767-atk-apollo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py b/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py index ea1f99f4cb..1b0f9fa211 100644 --- a/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py +++ b/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32f769-st-disco/rtconfig.py b/bsp/stm32/stm32f769-st-disco/rtconfig.py index 65a3b8e2a5..28fd66d3b7 100644 --- a/bsp/stm32/stm32f769-st-disco/rtconfig.py +++ b/bsp/stm32/stm32f769-st-disco/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32g030-tiny-board/rtconfig.py b/bsp/stm32/stm32g030-tiny-board/rtconfig.py index 9b8d8076e0..76f60a8b01 100644 --- a/bsp/stm32/stm32g030-tiny-board/rtconfig.py +++ b/bsp/stm32/stm32g030-tiny-board/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32g070-st-nucleo/rtconfig.py b/bsp/stm32/stm32g070-st-nucleo/rtconfig.py index afd5f66e4a..68329427c5 100644 --- a/bsp/stm32/stm32g070-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g070-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32g071-st-nucleo/rtconfig.py b/bsp/stm32/stm32g071-st-nucleo/rtconfig.py index afd5f66e4a..68329427c5 100644 --- a/bsp/stm32/stm32g071-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g071-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32g431-st-nucleo/rtconfig.py b/bsp/stm32/stm32g431-st-nucleo/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32g431-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g431-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32g474-st-nucleo/rtconfig.py b/bsp/stm32/stm32g474-st-nucleo/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32g474-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g474-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32g491-st-nucleo/rtconfig.py b/bsp/stm32/stm32g491-st-nucleo/rtconfig.py index 5e5bc02064..fce7a2e43a 100644 --- a/bsp/stm32/stm32g491-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32g491-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h723-lxb-disco/rtconfig.py b/bsp/stm32/stm32h723-lxb-disco/rtconfig.py index 4df33fb29f..0faa569ce1 100644 --- a/bsp/stm32/stm32h723-lxb-disco/rtconfig.py +++ b/bsp/stm32/stm32h723-lxb-disco/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h723-st-nucleo/rtconfig.py b/bsp/stm32/stm32h723-st-nucleo/rtconfig.py index 15ddd3158a..35537f6859 100644 --- a/bsp/stm32/stm32h723-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32h723-st-nucleo/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h730-esphosted-evb/rtconfig.py b/bsp/stm32/stm32h730-esphosted-evb/rtconfig.py index a2488720bf..4b252fcd5e 100644 --- a/bsp/stm32/stm32h730-esphosted-evb/rtconfig.py +++ b/bsp/stm32/stm32h730-esphosted-evb/rtconfig.py @@ -80,7 +80,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h743-armfly-v7/rtconfig.py b/bsp/stm32/stm32h743-armfly-v7/rtconfig.py index 15ddd3158a..35537f6859 100644 --- a/bsp/stm32/stm32h743-armfly-v7/rtconfig.py +++ b/bsp/stm32/stm32h743-armfly-v7/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h743-atk-apollo/rtconfig.py b/bsp/stm32/stm32h743-atk-apollo/rtconfig.py index 15ddd3158a..35537f6859 100644 --- a/bsp/stm32/stm32h743-atk-apollo/rtconfig.py +++ b/bsp/stm32/stm32h743-atk-apollo/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h743-st-nucleo/rtconfig.py b/bsp/stm32/stm32h743-st-nucleo/rtconfig.py index 15ddd3158a..35537f6859 100644 --- a/bsp/stm32/stm32h743-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32h743-st-nucleo/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h747-st-discovery/rtconfig.py b/bsp/stm32/stm32h747-st-discovery/rtconfig.py index 15ddd3158a..35537f6859 100644 --- a/bsp/stm32/stm32h747-st-discovery/rtconfig.py +++ b/bsp/stm32/stm32h747-st-discovery/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py b/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py index 15ddd3158a..35537f6859 100644 --- a/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py +++ b/bsp/stm32/stm32h750-armfly-h7-tool/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h750-artpi/rtconfig.py b/bsp/stm32/stm32h750-artpi/rtconfig.py index 8db22e414c..10461925ab 100644 --- a/bsp/stm32/stm32h750-artpi/rtconfig.py +++ b/bsp/stm32/stm32h750-artpi/rtconfig.py @@ -75,7 +75,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h750-fk750m1-vbt6/rtconfig.py b/bsp/stm32/stm32h750-fk750m1-vbt6/rtconfig.py index c826e54dab..30278c93d7 100644 --- a/bsp/stm32/stm32h750-fk750m1-vbt6/rtconfig.py +++ b/bsp/stm32/stm32h750-fk750m1-vbt6/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h750-weact-ministm32h7xx/rtconfig.py b/bsp/stm32/stm32h750-weact-ministm32h7xx/rtconfig.py index c826e54dab..30278c93d7 100644 --- a/bsp/stm32/stm32h750-weact-ministm32h7xx/rtconfig.py +++ b/bsp/stm32/stm32h750-weact-ministm32h7xx/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h7r7-artpi2/rtconfig.py b/bsp/stm32/stm32h7r7-artpi2/rtconfig.py index 00713f92b1..a3372112b1 100644 --- a/bsp/stm32/stm32h7r7-artpi2/rtconfig.py +++ b/bsp/stm32/stm32h7r7-artpi2/rtconfig.py @@ -71,7 +71,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32h7s7-st-disco/rtconfig.py b/bsp/stm32/stm32h7s7-st-disco/rtconfig.py index fa67b76941..f759087e0e 100644 --- a/bsp/stm32/stm32h7s7-st-disco/rtconfig.py +++ b/bsp/stm32/stm32h7s7-st-disco/rtconfig.py @@ -74,7 +74,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M7.fp.sp' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32l010-st-nucleo/rtconfig.py b/bsp/stm32/stm32l010-st-nucleo/rtconfig.py index b38196abb7..ceaa712702 100644 --- a/bsp/stm32/stm32l010-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l010-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32l053-st-nucleo/rtconfig.py b/bsp/stm32/stm32l053-st-nucleo/rtconfig.py index b38196abb7..ceaa712702 100644 --- a/bsp/stm32/stm32l053-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32l053-st-nucleo/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M0 ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32mp157a-st-discovery/rtconfig.py b/bsp/stm32/stm32mp157a-st-discovery/rtconfig.py index d2446f9fde..70a527b6fe 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/rtconfig.py +++ b/bsp/stm32/stm32mp157a-st-discovery/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py index d2446f9fde..70a527b6fe 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py +++ b/bsp/stm32/stm32mp157a-st-ev1/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/tm4c123bsp/rtconfig.py b/bsp/tm4c123bsp/rtconfig.py index a5be259c78..d9033972af 100644 --- a/bsp/tm4c123bsp/rtconfig.py +++ b/bsp/tm4c123bsp/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' -- Gitee From 5d1f199e9e44b14e93b6de7e68f73567ee3f371a Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Mon, 26 Jan 2026 13:36:01 +0800 Subject: [PATCH 13/45] feat(fal): add Kconfig options for device name length and block count --- components/fal/Kconfig | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/components/fal/Kconfig b/components/fal/Kconfig index 559014d694..b680afdb62 100644 --- a/components/fal/Kconfig +++ b/components/fal/Kconfig @@ -47,5 +47,26 @@ if RT_USING_FAL default "norflash0" endif + config FAL_DEV_NAME_MAX + int "FAL device/partition name max length" + default 24 + range 8 128 + help + Configure the maximum length of flash/partition device name used by FAL. + This value corresponds to macro FAL_DEV_NAME_MAX. + Increase it if your flash device name or partition name is longer. + Note: Larger value may increase memory usage in some implementations. + + config FAL_DEV_BLK_MAX + int "FAL max flash device blocks" + default 6 + range 1 32 + help + Configure the maximum number of flash device blocks managed by FAL. + This value corresponds to macro FAL_DEV_BLK_MAX. + If you have multiple flash devices (onchip/spi-nor/spi-nand, etc.) + or multiple underlying blocks, increase this value accordingly. + Note: Larger value may increase RAM/ROM usage. + endif -- Gitee From 97e1f014a174069adc741c4e565d4d3ec343bf51 Mon Sep 17 00:00:00 2001 From: vm22 <565000561@qq.com> Date: Sun, 25 Jan 2026 13:02:41 +0800 Subject: [PATCH 14/45] cmake: make CPPDEFINES handling robust for SCons-generated values [tools][cmake] fix type handling when generating CMake targets [Root Cause] Unexpected macro definition types during `scons --target=cmake` could trigger a TypeError and abort CMakeLists.txt generation. [Solution] Add support for handling different macro definition types. [Affect Area] cmake.py [Test Suggestion] Run `scons --target=cmake` and verify CMakeLists.txt is generated successfully with different macro definition formats. --- tools/targets/cmake.py | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/tools/targets/cmake.py b/tools/targets/cmake.py index e6c733217d..e1840e68bd 100644 --- a/tools/targets/cmake.py +++ b/tools/targets/cmake.py @@ -18,6 +18,7 @@ * 2024-11-18 kaidegit fix processing groups with similar name * 2025-02-22 kaidegit fix missing some flags added in Sconscript * 2025-02-24 kaidegit remove some code that is unnecessary but takes time, get them from env + * 2026-01-22 xym-ee Fix handling of tuple-based CPPDEFINES from SCons in CMake project generation. """ import os @@ -187,7 +188,24 @@ def GenerateCFiles(env, project, project_name): cm_file.write("ADD_DEFINITIONS(\n") for i in env['CPPDEFINES']: - cm_file.write("\t-D" + i + "\n") + # Handle CPPDEFINES from SCons (str / tuple) + if isinstance(i, tuple): + # e.g. ('STM32F407xx',) + if len(i) == 1: + cm_file.write("\t-D" + str(i[0]) + "\n") + # e.g. ('FOO', None) + elif len(i) == 2: + if i[1] is None: + cm_file.write("\t-D" + str(i[0]) + "\n") + # e.g. ('FOO', 1) + else: + cm_file.write("\t-D{}={}\n".format(i[0], i[1])) + else: + # unexpected form, fallback to name only + cm_file.write("\t-D" + str(i[0]) + "\n") + else: + # generic macro (commonly a string), ensure robust string conversion + cm_file.write("\t-D" + str(i) + "\n") cm_file.write(")\n\n") libgroups = [] -- Gitee From cdc50db5709b9b9b868c9ba19738957af17c6fa6 Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Mon, 26 Jan 2026 10:59:39 +0800 Subject: [PATCH 15/45] update(cherryusb): update to v1.6.0 Signed-off-by: sakumisu <1203593632@qq.com> --- components/drivers/usb/Kconfig | 2 +- components/drivers/usb/cherryusb/.gitignore | 1 + components/drivers/usb/cherryusb/Kconfig | 388 ++++---- components/drivers/usb/cherryusb/Kconfig.rtt | 462 --------- .../drivers/usb/cherryusb/Kconfig.rttpkg | 500 ---------- components/drivers/usb/cherryusb/README.md | 53 +- components/drivers/usb/cherryusb/README_zh.md | 11 +- components/drivers/usb/cherryusb/SConscript | 44 +- components/drivers/usb/cherryusb/VERSION | 4 +- .../drivers/usb/cherryusb/cherryusb.cmake | 37 +- .../usb/cherryusb/cherryusb_config_template.h | 10 +- .../usb/cherryusb/class/aoa/usbh_aoa.c | 4 - .../usb/cherryusb/class/audio/usb_audio.h | 104 +- .../drivers/usb/cherryusb/class/cdc/usb_cdc.h | 38 +- .../usb/cherryusb/class/cdc/usbh_cdc_acm.c | 285 ------ .../usb/cherryusb/class/cdc/usbh_cdc_acm.h | 50 - .../usb/cherryusb/class/cdc/usbh_cdc_ecm.c | 10 - .../usb/cherryusb/class/cdc/usbh_cdc_ncm.c | 10 - .../usb/cherryusb/class/dfu/usbd_dfu.c | 3 +- .../usb/cherryusb/class/gamepad/usb_gamepad.h | 224 +++++ .../cherryusb/class/gamepad/usbd_gamepad.c | 209 ++++ .../cherryusb/class/gamepad/usbd_gamepad.h | 22 + .../drivers/usb/cherryusb/class/hid/usb_hid.h | 229 ++--- .../usb/cherryusb/class/hid/usbh_hid.c | 455 ++++++++- .../usb/cherryusb/class/hid/usbh_hid.h | 81 ++ .../usb/cherryusb/class/hub/usbh_hub.c | 57 +- .../usb/cherryusb/class/midi/usb_midi.h | 15 + .../usb/cherryusb/class/serial/usbh_cdc_acm.c | 266 +++++ .../usb/cherryusb/class/serial/usbh_cdc_acm.h | 19 + .../class/{vendor => }/serial/usbh_ch34x.c | 408 ++++---- .../class/{vendor => }/serial/usbh_ch34x.h | 32 +- .../usb/cherryusb/class/serial/usbh_cp210x.c | 507 ++++++++++ .../usb/cherryusb/class/serial/usbh_cp210x.h | 187 ++++ .../class/{vendor => }/serial/usbh_ftdi.c | 457 ++++----- .../usb/cherryusb/class/serial/usbh_ftdi.h | 341 +++++++ .../usb/cherryusb/class/serial/usbh_gsm.c | 131 +++ .../usb/cherryusb/class/serial/usbh_pl2303.c | 726 ++++++++++++++ .../usb/cherryusb/class/serial/usbh_pl2303.h | 43 + .../usb/cherryusb/class/serial/usbh_serial.c | 743 ++++++++++++++ .../usb/cherryusb/class/serial/usbh_serial.h | 182 ++++ .../cherryusb/class/vendor/net/usbh_asix.c | 10 - .../cherryusb/class/vendor/net/usbh_rtl8152.c | 20 +- .../class/vendor/serial/usbh_cp210x.c | 328 ------- .../class/vendor/serial/usbh_cp210x.h | 73 -- .../cherryusb/class/vendor/serial/usbh_ftdi.h | 96 -- .../class/vendor/serial/usbh_pl2303.c | 449 --------- .../class/vendor/serial/usbh_pl2303.h | 62 -- .../usb/cherryusb/class/vendor/wifi/.gitkeep | 0 .../usb/cherryusb/class/vendor/wifi/README.md | 6 - .../cherryusb/class/vendor/wifi/usbh_bl616.c | 513 ---------- .../cherryusb/class/vendor/wifi/usbh_bl616.h | 220 ----- .../usb/cherryusb/class/video/usbh_video.c | 138 +-- .../usb/cherryusb/class/video/usbh_video.h | 5 +- .../usb/cherryusb/class/wireless/usbh_rndis.c | 19 +- .../drivers/usb/cherryusb/common/usb_def.h | 206 +++- .../drivers/usb/cherryusb/common/usb_otg.h | 39 + .../drivers/usb/cherryusb/common/usb_util.h | 21 +- .../usb/cherryusb/common/usb_version.h | 4 +- .../drivers/usb/cherryusb/core/usbd_core.c | 238 +---- .../drivers/usb/cherryusb/core/usbd_core.h | 11 +- .../drivers/usb/cherryusb/core/usbh_core.c | 594 ++++++++---- .../drivers/usb/cherryusb/core/usbh_core.h | 42 +- .../drivers/usb/cherryusb/core/usbotg_core.c | 155 +++ .../drivers/usb/cherryusb/core/usbotg_core.h | 27 + .../cherryusb/demo/adb/usbd_adb_template.c | 88 +- .../demo/audio_v1_mic_multichan_template.c | 118 +-- .../audio_v1_mic_speaker_multichan_template.c | 250 ++--- .../demo/audio_v2_mic_multichan_template.c | 146 +-- .../audio_v2_mic_speaker_multichan_template.c | 211 ++-- .../audio_v2_speaker_multichan_template.c | 138 +-- .../demo/bootuf2/msc_bootuf2_template.c | 86 +- .../cherryusb/demo/cdc_acm_hid_msc_template.c | 149 +-- .../cherryusb/demo/cdc_acm_mavlink_template.c | 87 +- .../usb/cherryusb/demo/cdc_acm_msc_template.c | 87 +- .../cherryusb/demo/cdc_acm_multi_template.c | 89 +- .../demo/cdc_acm_rttchardev_template.c | 112 +-- .../usb/cherryusb/demo/cdc_acm_template.c | 86 +- .../usb/cherryusb/demo/cdc_ecm_template.c | 119 +-- .../usb/cherryusb/demo/cdc_rndis_template.c | 88 +- .../demo/dfu_with_st_tool_template.c | 134 +-- .../usb/cherryusb/demo/gamepad_template.c | 250 +++++ .../demo/hid_custom_inout_template.c | 243 +---- .../cherryusb/demo/hid_keyboard_template.c | 155 +-- .../usb/cherryusb/demo/hid_mouse_template.c | 156 +-- .../demo/hid_remote_wakeup_template.c | 156 +-- .../usb/cherryusb/demo/midi_template.c | 189 +--- .../usb/cherryusb/demo/msc_ram_template.c | 85 +- .../drivers/usb/cherryusb/demo/usb_host.c | 216 +++-- .../usb/cherryusb/demo/usbh_bl616_wifi_cli.c | 182 ++++ .../demo/video_audiov1_hid_template.c | 183 +--- .../demo/video_static_h264_template.c | 94 +- .../demo/video_static_mjpeg_template.c | 94 +- .../demo/video_static_yuyv_template.c | 95 +- .../usb/cherryusb/demo/webusb_hid_template.c | 309 +----- .../usb/cherryusb/demo/winusb1.0_template.c | 375 ++----- .../cherryusb/demo/winusb2.0_cdc_template.c | 252 +---- .../cherryusb/demo/winusb2.0_hid_template.c | 550 ----------- .../usb/cherryusb/demo/winusb2.0_template.c | 263 +++++ .../drivers/usb/cherryusb/idf_component.yml | 2 +- .../usb/cherryusb/platform/daplink/dap_main.c | 496 +++++++--- .../usb/cherryusb/platform/daplink/dap_main.h | 116 +-- .../cherryusb/platform/rtthread/usb_check.c | 9 +- .../usb/cherryusb/platform/rtthread/usb_msh.c | 8 +- .../cherryusb/platform/rtthread/usbd_serial.c | 12 +- .../cherryusb/platform/rtthread/usbh_dfs.c | 15 +- .../cherryusb/platform/rtthread/usbh_lwip.c | 12 +- .../cherryusb/platform/rtthread/usbh_serial.c | 914 ------------------ .../cherryusb/port/chipidea/usb_dc_chipidea.c | 13 +- .../drivers/usb/cherryusb/port/dwc2/README.md | 6 +- .../usb/cherryusb/port/dwc2/usb_dc_dwc2.c | 202 ++-- .../usb/cherryusb/port/dwc2/usb_dwc2_reg.h | 2 + .../usb/cherryusb/port/dwc2/usb_glue_at.c | 11 +- .../usb/cherryusb/port/dwc2/usb_glue_esp.c | 7 +- .../usb/cherryusb/port/dwc2/usb_glue_hc.c | 298 +++++- .../cherryusb/port/dwc2/usb_glue_infineon.c | 154 +++ .../cherryusb/port/dwc2/usb_glue_kendryte.c | 9 +- .../usb/cherryusb/port/dwc2/usb_glue_st.c | 33 +- .../usb/cherryusb/port/dwc2/usb_hc_dwc2.c | 133 +-- .../usb/cherryusb/port/ehci/usb_glue_aic.c | 62 +- .../usb/cherryusb/port/ehci/usb_glue_t113.c | 128 ++- .../usb/cherryusb/port/ehci/usb_hc_ehci.c | 4 + .../usb/cherryusb/port/hpmicro/usb_dc_hpm.c | 17 +- .../usb/cherryusb/port/hpmicro/usb_glue_hpm.c | 82 +- .../usb/cherryusb/port/hpmicro/usb_hc_hpm.c | 14 +- .../usb/cherryusb/port/kinetis/usb_glue_mcx.c | 4 +- .../usb/cherryusb/port/musb/usb_glue_sifli.c | 2 +- .../usb/cherryusb/port/musb/usb_glue_ti.c | 163 ++++ .../usb/cherryusb/port/musb/usb_hc_musb.c | 60 +- .../drivers/usb/cherryusb/tools/audacity/url | 1 + .../cherryusb/tools/chryusb_configurator/url | 1 + .../usb/cherryusb/tools/packet capture/url | 3 + .../usb/cherryusb/tools/stm32_dfuse/url | 1 + .../tools/test_srcipts/test_cdc_speed.py | 49 + .../tools/test_srcipts/test_hid_inout.py | 68 ++ .../usb/cherryusb/tools/uf2/uf2conv.py | 361 +++++++ 135 files changed, 9348 insertions(+), 10585 deletions(-) delete mode 100644 components/drivers/usb/cherryusb/Kconfig.rtt delete mode 100644 components/drivers/usb/cherryusb/Kconfig.rttpkg delete mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c delete mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h create mode 100644 components/drivers/usb/cherryusb/class/gamepad/usb_gamepad.h create mode 100644 components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.c create mode 100644 components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.h create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.c create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.h rename components/drivers/usb/cherryusb/class/{vendor => }/serial/usbh_ch34x.c (36%) rename components/drivers/usb/cherryusb/class/{vendor => }/serial/usbh_ch34x.h (48%) create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_cp210x.c create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_cp210x.h rename components/drivers/usb/cherryusb/class/{vendor => }/serial/usbh_ftdi.c (38%) create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_ftdi.h create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_gsm.c create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_pl2303.c create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_pl2303.h create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_serial.c create mode 100644 components/drivers/usb/cherryusb/class/serial/usbh_serial.h delete mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c delete mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h delete mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h delete mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c delete mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/wifi/.gitkeep delete mode 100644 components/drivers/usb/cherryusb/class/vendor/wifi/README.md delete mode 100644 components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c delete mode 100644 components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h create mode 100644 components/drivers/usb/cherryusb/common/usb_otg.h create mode 100644 components/drivers/usb/cherryusb/core/usbotg_core.c create mode 100644 components/drivers/usb/cherryusb/core/usbotg_core.h create mode 100644 components/drivers/usb/cherryusb/demo/gamepad_template.c create mode 100644 components/drivers/usb/cherryusb/demo/usbh_bl616_wifi_cli.c delete mode 100644 components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c create mode 100644 components/drivers/usb/cherryusb/demo/winusb2.0_template.c delete mode 100644 components/drivers/usb/cherryusb/platform/rtthread/usbh_serial.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c create mode 100644 components/drivers/usb/cherryusb/port/musb/usb_glue_ti.c create mode 100644 components/drivers/usb/cherryusb/tools/audacity/url create mode 100644 components/drivers/usb/cherryusb/tools/chryusb_configurator/url create mode 100644 components/drivers/usb/cherryusb/tools/packet capture/url create mode 100644 components/drivers/usb/cherryusb/tools/stm32_dfuse/url create mode 100644 components/drivers/usb/cherryusb/tools/test_srcipts/test_cdc_speed.py create mode 100644 components/drivers/usb/cherryusb/tools/test_srcipts/test_hid_inout.py create mode 100644 components/drivers/usb/cherryusb/tools/uf2/uf2conv.py diff --git a/components/drivers/usb/Kconfig b/components/drivers/usb/Kconfig index 3af62ab03e..cd8e4ebf86 100644 --- a/components/drivers/usb/Kconfig +++ b/components/drivers/usb/Kconfig @@ -1 +1 @@ -rsource "cherryusb/Kconfig.rtt" +rsource "cherryusb/Kconfig" diff --git a/components/drivers/usb/cherryusb/.gitignore b/components/drivers/usb/cherryusb/.gitignore index 22b1a7fa27..9ebda7a011 100644 --- a/components/drivers/usb/cherryusb/.gitignore +++ b/components/drivers/usb/cherryusb/.gitignore @@ -1,4 +1,5 @@ .vscode +build **/Drivers/** **/MDK-ARM/DebugConfig/** **/MDK-ARM/RTE/** diff --git a/components/drivers/usb/cherryusb/Kconfig b/components/drivers/usb/cherryusb/Kconfig index 4c3c655ceb..35a8e15f28 100644 --- a/components/drivers/usb/cherryusb/Kconfig +++ b/components/drivers/usb/cherryusb/Kconfig @@ -1,146 +1,155 @@ -# Kconfig file for CherryUSB -menuconfig CHERRYUSB - bool "CherryUSB Configuration" +# Kconfig file for package CherryUSB +menuconfig RT_USING_CHERRYUSB + bool "Using USB with CherryUSB" default n -if CHERRYUSB +if RT_USING_CHERRYUSB - menuconfig CHERRYUSB_DEVICE + menuconfig RT_CHERRYUSB_DEVICE bool "Enable usb device mode" default n - if CHERRYUSB_DEVICE + if RT_CHERRYUSB_DEVICE choice CHERRYUSB_DEVICE_SPEED prompt "Select usb device speed" - default CHERRYUSB_DEVICE_SPEED_FS - config CHERRYUSB_DEVICE_SPEED_FS + default RT_CHERRYUSB_DEVICE_SPEED_FS + config RT_CHERRYUSB_DEVICE_SPEED_FS bool "FS" - config CHERRYUSB_DEVICE_SPEED_HS + config RT_CHERRYUSB_DEVICE_SPEED_HS bool "HS" - config CHERRYUSB_DEVICE_SPEED_AUTO + config RT_CHERRYUSB_DEVICE_SPEED_AUTO bool "AUTO" endchoice choice CHERRYUSB_DEVICE_IP prompt "Select usb device ip, and some ip need config in usb_config.h, please check" - default CHERRYUSB_DEVICE_CUSTOM - config CHERRYUSB_DEVICE_CUSTOM + default RT_CHERRYUSB_DEVICE_CUSTOM + config RT_CHERRYUSB_DEVICE_CUSTOM bool "CUSTOM (Implement it yourself)" - config CHERRYUSB_DEVICE_FSDEV_ST + config RT_CHERRYUSB_DEVICE_FSDEV_ST bool "fsdev_st" - config CHERRYUSB_DEVICE_FSDEV_CUSTOM + config RT_CHERRYUSB_DEVICE_FSDEV_CUSTOM bool "fsdev_custom" - config CHERRYUSB_DEVICE_DWC2_ST + config RT_CHERRYUSB_DEVICE_DWC2_ST bool "dwc2_st" - config CHERRYUSB_DEVICE_DWC2_ESP + config RT_CHERRYUSB_DEVICE_DWC2_ESP bool "dwc2_esp" - config CHERRYUSB_DEVICE_DWC2_KENDRYTE + config RT_CHERRYUSB_DEVICE_DWC2_KENDRYTE bool "dwc2_kendryte" - config CHERRYUSB_DEVICE_DWC2_AT + config RT_CHERRYUSB_DEVICE_DWC2_INFINEON + bool "dwc2_infineon" + config RT_CHERRYUSB_DEVICE_DWC2_AT bool "dwc2_at" - config CHERRYUSB_DEVICE_DWC2_HC + config RT_CHERRYUSB_DEVICE_DWC2_HC bool "dwc2_hc" - config CHERRYUSB_DEVICE_DWC2_NATION + config RT_CHERRYUSB_DEVICE_DWC2_NATION bool "dwc2_nation" - config CHERRYUSB_DEVICE_DWC2_GD + config RT_CHERRYUSB_DEVICE_DWC2_GD bool "dwc2_gd" - config CHERRYUSB_DEVICE_DWC2_CUSTOM + config RT_CHERRYUSB_DEVICE_DWC2_CUSTOM bool "dwc2_custom" - config CHERRYUSB_DEVICE_MUSB_ES + config RT_CHERRYUSB_DEVICE_MUSB_ES bool "musb_es" - config CHERRYUSB_DEVICE_MUSB_SUNXI + config RT_CHERRYUSB_DEVICE_MUSB_SUNXI bool "musb_sunxi" - config CHERRYUSB_DEVICE_MUSB_BK + config RT_CHERRYUSB_DEVICE_MUSB_BK bool "musb_bk" - config CHERRYUSB_DEVICE_MUSB_SIFLI + config RT_CHERRYUSB_DEVICE_MUSB_SIFLI bool "musb_sifli" - config CHERRYUSB_DEVICE_MUSB_CUSTOM + config RT_CHERRYUSB_DEVICE_MUSB_CUSTOM bool "musb_custom" - config CHERRYUSB_DEVICE_CHIPIDEA_MCX + config RT_CHERRYUSB_DEVICE_CHIPIDEA_MCX bool "chipidea_mcx" - config CHERRYUSB_DEVICE_CHIPIDEA_CUSTOM + config RT_CHERRYUSB_DEVICE_CHIPIDEA_CUSTOM bool "chipidea_custom" - config CHERRYUSB_DEVICE_KINETIS_MCX + config RT_CHERRYUSB_DEVICE_KINETIS_MCX bool "kinetis_mcx" - config CHERRYUSB_DEVICE_KINETIS_MM32 + config RT_CHERRYUSB_DEVICE_KINETIS_MM32 bool "kinetis_mm32" - config CHERRYUSB_DEVICE_KINETIS_CUSTOM + config RT_CHERRYUSB_DEVICE_KINETIS_CUSTOM bool "kinetis_custom" - config CHERRYUSB_DEVICE_BL + config RT_CHERRYUSB_DEVICE_BL bool "bouffalo" - config CHERRYUSB_DEVICE_HPM + config RT_CHERRYUSB_DEVICE_HPM bool "hpm" - config CHERRYUSB_DEVICE_AIC + config RT_CHERRYUSB_DEVICE_AIC bool "aic" - config CHERRYUSB_DEVICE_RP2040 + config RT_CHERRYUSB_DEVICE_RP2040 bool "rp2040" - config CHERRYUSB_DEVICE_CH32 + config RT_CHERRYUSB_DEVICE_CH32 bool "ch32" - config CHERRYUSB_DEVICE_PUSB2 + config RT_CHERRYUSB_DEVICE_PUSB2 bool "pusb2" + config RT_CHERRYUSB_DEVICE_NRF5X + bool "nrf5x" endchoice - config CHERRYUSB_DEVICE_CDC_ACM + config RT_CHERRYUSB_DEVICE_CDC_ACM bool prompt "Enable usb cdc acm device" default n - config CHERRYUSB_DEVICE_HID + config RT_CHERRYUSB_DEVICE_HID bool prompt "Enable usb hid device" default n - config CHERRYUSB_DEVICE_MSC + config RT_CHERRYUSB_DEVICE_MSC bool prompt "Enable usb msc device" default n - config CHERRYUSB_DEVICE_AUDIO + config RT_CHERRYUSB_DEVICE_AUDIO bool prompt "Enable usb audio device" default n - config CHERRYUSB_DEVICE_VIDEO + config RT_CHERRYUSB_DEVICE_VIDEO bool prompt "Enable usb video device" default n - config CHERRYUSB_DEVICE_CDC_RNDIS + config RT_CHERRYUSB_DEVICE_CDC_RNDIS bool prompt "Enable usb cdc rndis device" default n - config CHERRYUSB_DEVICE_CDC_ECM + config RT_CHERRYUSB_DEVICE_CDC_ECM bool prompt "Enable usb cdc ecm device" default n - config CHERRYUSB_DEVICE_CDC_NCM + config RT_CHERRYUSB_DEVICE_CDC_NCM bool prompt "Enable usb cdc ncm device" default n - config CHERRYUSB_DEVICE_MTP + config RT_CHERRYUSB_DEVICE_MTP bool prompt "Enable usb mtp device, it is commercial charge" default n - config CHERRYUSB_DEVICE_ADB + config RT_CHERRYUSB_DEVICE_ADB bool prompt "Enable usb adb device" default n - config CHERRYUSB_DEVICE_DFU + config RT_CHERRYUSB_DEVICE_DFU bool prompt "Enable usb dfu device" default n - config USBDEV_REQUEST_BUFFER_LEN + config RT_CHERRYUSB_DEVICE_CDC_ACM_CHARDEV + bool + prompt "Enable chardev for cdc acm device" + default n + + config CONFIG_USBDEV_REQUEST_BUFFER_LEN int prompt "Set device control transfer max buffer size" default 512 - config USBDEV_MSC_MAX_BUFSIZE + config CONFIG_USBDEV_MSC_MAX_BUFSIZE int prompt "Set usb msc device max buffer size" default 512 @@ -148,286 +157,339 @@ if CHERRYUSB Set the maximum buffer size for usb msc device, it is used to transfer data. you can change it to a larger value if you need larger speed but must be a power of blocksize. - config USBDEV_RNDIS_USING_LWIP + config CONFIG_USBDEV_RNDIS_USING_LWIP bool prompt "Enable usb rndis device with lwip for lan" default n - config USBDEV_CDC_ECM_USING_LWIP + config CONFIG_USBDEV_CDC_ECM_USING_LWIP bool prompt "Enable usb cdc ecm device with lwip for lan" default n choice CHERRYUSB_DEVICE_TEMPLATE prompt "Select usb device template, please select class driver first" - default CHERRYUSB_DEVICE_TEMPLATE_NONE - config CHERRYUSB_DEVICE_TEMPLATE_NONE + default RT_CHERRYUSB_DEVICE_TEMPLATE_NONE + config RT_CHERRYUSB_DEVICE_TEMPLATE_NONE bool prompt "none (Implement it yourself)" - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM bool prompt "cdc_acm" - depends on CHERRYUSB_DEVICE_CDC_ACM - config CHERRYUSB_DEVICE_TEMPLATE_MSC + depends on RT_CHERRYUSB_DEVICE_CDC_ACM + config RT_CHERRYUSB_DEVICE_TEMPLATE_MSC bool prompt "msc_ram" - depends on CHERRYUSB_DEVICE_MSC - config CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD + depends on RT_CHERRYUSB_DEVICE_MSC + config RT_CHERRYUSB_DEVICE_TEMPLATE_MSC_BLKDEV + bool + prompt "msc_blkdev" + depends on RT_CHERRYUSB_DEVICE_MSC + config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD bool prompt "hid_keyboard" - depends on CHERRYUSB_DEVICE_HID - config CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE + depends on RT_CHERRYUSB_DEVICE_HID + config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE bool prompt "hid_mouse" - depends on CHERRYUSB_DEVICE_HID - config CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM + depends on RT_CHERRYUSB_DEVICE_HID + config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM bool prompt "hid_custom" - depends on CHERRYUSB_DEVICE_HID - config CHERRYUSB_DEVICE_TEMPLATE_VIDEO + depends on RT_CHERRYUSB_DEVICE_HID + config RT_CHERRYUSB_DEVICE_TEMPLATE_VIDEO bool prompt "video" - depends on CHERRYUSB_DEVICE_VIDEO - config CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER + depends on RT_CHERRYUSB_DEVICE_VIDEO + config RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER bool prompt "audio_v1_mic_speaker_multichan" - depends on CHERRYUSB_DEVICE_AUDIO - config CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER + depends on RT_CHERRYUSB_DEVICE_AUDIO + config RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER bool prompt "audio_v2_mic_speaker_multichan" - depends on CHERRYUSB_DEVICE_AUDIO - config CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS + depends on RT_CHERRYUSB_DEVICE_AUDIO + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS bool prompt "cdc_rndis" - depends on CHERRYUSB_DEVICE_CDC_RNDIS - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM + depends on RT_CHERRYUSB_DEVICE_CDC_RNDIS + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM bool prompt "cdc_ecm" - depends on CHERRYUSB_DEVICE_CDC_ECM - config CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM + depends on RT_CHERRYUSB_DEVICE_CDC_ECM + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM bool prompt "cdc_ncm" - depends on CHERRYUSB_DEVICE_CDC_NCM - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC + depends on RT_CHERRYUSB_DEVICE_CDC_NCM + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC bool prompt "cdc_acm_msc" - depends on CHERRYUSB_DEVICE_CDC_ACM && CHERRYUSB_DEVICE_MSC - config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID + depends on RT_CHERRYUSB_DEVICE_CDC_ACM && RT_CHERRYUSB_DEVICE_MSC + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID bool prompt "cdc_acm_msc_hid" - depends on CHERRYUSB_DEVICE_CDC_ACM && CHERRYUSB_DEVICE_MSC && CHERRYUSB_DEVICE_HID - config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 + depends on RT_CHERRYUSB_DEVICE_CDC_ACM && RT_CHERRYUSB_DEVICE_MSC && RT_CHERRYUSB_DEVICE_HID + config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 bool prompt "winusbv1" - config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC + config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2 + bool + prompt "winusbv2" + config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC bool prompt "winusbv2_cdc" - depends on CHERRYUSB_DEVICE_CDC_ACM - config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID + depends on RT_CHERRYUSB_DEVICE_CDC_ACM + config RT_CHERRYUSB_DEVICE_TEMPLATE_WEBUSB_HID + bool + prompt "webusb_hid" + depends on RT_CHERRYUSB_DEVICE_HID + config RT_CHERRYUSB_DEVICE_TEMPLATE_ADB + bool + prompt "adb" + depends on RT_CHERRYUSB_DEVICE_ADB + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_CHARDEV bool - prompt "winusbv2_hid" - depends on CHERRYUSB_DEVICE_HID + prompt "cdc_acm_chardev" + depends on RT_CHERRYUSB_DEVICE_CDC_ACM_CHARDEV endchoice + + config CONFIG_USBDEV_MSC_BLOCK_DEV_NAME + string "usb device msc block device name" + depends on RT_CHERRYUSB_DEVICE_TEMPLATE_MSC_BLKDEV + default "sd0" + endif - menuconfig CHERRYUSB_HOST + menuconfig RT_CHERRYUSB_HOST bool "Enable usb host mode" default n - if CHERRYUSB_HOST + if RT_CHERRYUSB_HOST choice CHERRYUSB_HOST_IP prompt "Select usb host ip, and some ip need config in usb_config.h, please check" - default CHERRYUSB_HOST_CUSTOM - config CHERRYUSB_HOST_CUSTOM + default RT_CHERRYUSB_HOST_CUSTOM + config RT_CHERRYUSB_HOST_CUSTOM bool "CUSTOM (Implement it yourself)" - config CHERRYUSB_HOST_EHCI_BL + config RT_CHERRYUSB_HOST_EHCI_BL bool "ehci_bouffalo" - config CHERRYUSB_HOST_EHCI_HPM + config RT_CHERRYUSB_HOST_EHCI_HPM bool "ehci_hpm" - config CHERRYUSB_HOST_EHCI_AIC + config RT_CHERRYUSB_HOST_EHCI_AIC bool "ehci_aic" - config CHERRYUSB_HOST_EHCI_MCX + config RT_CHERRYUSB_HOST_EHCI_MCX bool "ehci_mcx" - config CHERRYUSB_HOST_EHCI_NUC980 + config RT_CHERRYUSB_HOST_EHCI_NUC980 bool "ehci_nuc980" - config CHERRYUSB_HOST_EHCI_MA35D0 + config RT_CHERRYUSB_HOST_EHCI_MA35D0 bool "ehci_ma35d0" - config CHERRYUSB_HOST_EHCI_CUSTOM + config RT_CHERRYUSB_HOST_EHCI_CUSTOM bool "ehci_custom" - config CHERRYUSB_HOST_DWC2_ST + config RT_CHERRYUSB_HOST_DWC2_ST bool "dwc2_st" - config CHERRYUSB_HOST_DWC2_ESP + config RT_CHERRYUSB_HOST_DWC2_ESP bool "dwc2_esp" - config CHERRYUSB_HOST_DWC2_KENDRYTE + config RT_CHERRYUSB_HOST_DWC2_KENDRYTE bool "dwc2_kendryte" - config CHERRYUSB_HOST_DWC2_HC + config RT_CHERRYUSB_HOST_DWC2_INFINEON + bool "dwc2_infineon" + config RT_CHERRYUSB_HOST_DWC2_AT + bool "dwc2_at, f405 only" + config RT_CHERRYUSB_HOST_DWC2_HC bool "dwc2_hc" - config CHERRYUSB_HOST_DWC2_NATION + config RT_CHERRYUSB_HOST_DWC2_NATION bool "dwc2_nation" - config CHERRYUSB_HOST_DWC2_CUSTOM + config RT_CHERRYUSB_HOST_DWC2_CUSTOM bool "dwc2_custom" - config CHERRYUSB_HOST_MUSB_ES + config RT_CHERRYUSB_HOST_MUSB_ES bool "musb_es" - config CHERRYUSB_HOST_MUSB_SUNXI + config RT_CHERRYUSB_HOST_MUSB_SUNXI bool "musb_sunxi" - config CHERRYUSB_HOST_MUSB_BK + config RT_CHERRYUSB_HOST_MUSB_BK bool "musb_bk" - config CHERRYUSB_HOST_MUSB_SIFLI + config RT_CHERRYUSB_HOST_MUSB_SIFLI bool "musb_sifli" - config CHERRYUSB_HOST_MUSB_CUSTOM + config RT_CHERRYUSB_HOST_MUSB_CUSTOM bool "musb_custom" - config CHERRYUSB_HOST_PUSB2 + config RT_CHERRYUSB_HOST_PUSB2 bool "pusb2" - config CHERRYUSB_HOST_XHCI_PHYTIUM - bool "xhci_phytium" - config CHERRYUSB_HOST_XHCI_CUSTOM + config RT_CHERRYUSB_HOST_XHCI bool "xhci" - config CHERRYUSB_HOST_KINETIS_MCX - bool "kinetis_mcx" - config CHERRYUSB_HOST_KINETIS_MM32 - bool "kinetis_mm32" - config CHERRYUSB_HOST_KINETIS_CUSTOM - bool "kinetis_custom" - config CHERRYUSB_HOST_RP2040 + config RT_CHERRYUSB_HOST_RP2040 bool "rp2040" endchoice - config CHERRYUSB_HOST_CDC_ACM + config RT_CHERRYUSB_HOST_CDC_ACM bool prompt "Enable usb cdc acm driver" + select CONFIG_USBHOST_SERIAL default n - config CHERRYUSB_HOST_HID + config RT_CHERRYUSB_HOST_HID bool prompt "Enable usb hid driver" default n - config CHERRYUSB_HOST_MSC + config RT_CHERRYUSB_HOST_MSC bool prompt "Enable usb msc driver" default n + select RT_USING_DFS + select RT_USING_DFS_ELMFAT - config CHERRYUSB_HOST_CDC_ECM + config RT_CHERRYUSB_HOST_CDC_ECM bool prompt "Enable usb cdc ecm driver" - select USBHOST_PLATFORM_CDC_ECM + select RT_USING_LWIP + select CONFIG_USBHOST_PLATFORM_CDC_ECM default n - config CHERRYUSB_HOST_CDC_RNDIS + config RT_CHERRYUSB_HOST_CDC_RNDIS bool prompt "Enable usb rndis driver" - select USBHOST_PLATFORM_CDC_RNDIS + select RT_USING_LWIP + select CONFIG_USBHOST_PLATFORM_CDC_RNDIS default n - config CHERRYUSB_HOST_CDC_NCM + config RT_CHERRYUSB_HOST_CDC_NCM bool prompt "Enable usb cdc ncm driver" - select USBHOST_PLATFORM_CDC_NCM + select RT_USING_LWIP + select CONFIG_USBHOST_PLATFORM_CDC_NCM default n - config CHERRYUSB_HOST_VIDEO + config RT_CHERRYUSB_HOST_VIDEO bool prompt "Enable usb video driver, it is commercial charge" default n - config CHERRYUSB_HOST_AUDIO + config RT_CHERRYUSB_HOST_AUDIO bool prompt "Enable usb audio driver, it is commercial charge" default n - config CHERRYUSB_HOST_BLUETOOTH + config RT_CHERRYUSB_HOST_BLUETOOTH bool prompt "Enable usb bluetooth driver" default n - config CHERRYUSB_HOST_ASIX + config RT_CHERRYUSB_HOST_ASIX bool prompt "Enable usb asix driver" - select USBHOST_PLATFORM_ASIX + select RT_USING_LWIP + select CONFIG_USBHOST_PLATFORM_ASIX default n - config CHERRYUSB_HOST_RTL8152 + config RT_CHERRYUSB_HOST_RTL8152 bool prompt "Enable usb rtl8152 driver" - select USBHOST_PLATFORM_RTL8152 + select RT_USING_LWIP + select CONFIG_USBHOST_PLATFORM_RTL8152 default n - config CHERRYUSB_HOST_FTDI + config RT_CHERRYUSB_HOST_FTDI bool prompt "Enable usb ftdi driver" + select CONFIG_USBHOST_SERIAL default n - config CHERRYUSB_HOST_CH34X + config RT_CHERRYUSB_HOST_CH34X bool prompt "Enable usb ch34x driver" + select CONFIG_USBHOST_SERIAL default n - config CHERRYUSB_HOST_CP210X + config RT_CHERRYUSB_HOST_CP210X bool prompt "Enable usb cp210x driver" + select CONFIG_USBHOST_SERIAL default n - config CHERRYUSB_HOST_PL2303 + config RT_CHERRYUSB_HOST_PL2303 bool prompt "Enable usb pl2303 driver" + select CONFIG_USBHOST_SERIAL default n - config CHERRYUSB_HOST_AOA + config RT_CHERRYUSB_HOST_GSM bool - prompt "Enable usb aoa driver" + prompt "Enable usb gsm driver for 4g module" + select CONFIG_USBHOST_SERIAL default n - config USBHOST_PLATFORM_CDC_ECM + config CONFIG_USBHOST_SERIAL bool - config USBHOST_PLATFORM_CDC_RNDIS + config CONFIG_USBHOST_PLATFORM_CDC_ECM bool - config USBHOST_PLATFORM_CDC_NCM + config CONFIG_USBHOST_PLATFORM_CDC_RNDIS bool - config USBHOST_PLATFORM_ASIX + config CONFIG_USBHOST_PLATFORM_CDC_NCM bool - config USBHOST_PLATFORM_RTL8152 + config CONFIG_USBHOST_PLATFORM_ASIX bool - config USBHOST_PSC_PRIO + config CONFIG_USBHOST_PLATFORM_RTL8152 + bool + + config CONFIG_USBHOST_PSC_PRIO int prompt "Set hubport change thread priority, 0 is the max priority" default 0 - config USBHOST_PSC_STACKSIZE + config CONFIG_USBHOST_PSC_STACKSIZE int prompt "Set hubport change thread stacksize" default 4096 - config USBHOST_REQUEST_BUFFER_LEN + config CONFIG_USBHOST_REQUEST_BUFFER_LEN int prompt "Set host control transfer max buffer size" default 512 - config USBHOST_CONTROL_TRANSFER_TIMEOUT + config CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT int prompt "Set host control transfer timeout, unit is ms" default 500 + config CONFIG_USBHOST_SERIAL_RX_SIZE + int + prompt "Set host serial rx max buffer size" + default 2048 + + config RT_LWIP_PBUF_POOL_BUFSIZE + int "The size of each pbuf in the pbuf pool" + range 1500 2000 + default 1600 + + config CONFIG_USB_DFS_MOUNT_POINT + string "usb host dfs mount point" + depends on RT_CHERRYUSB_HOST_MSC + default "/" + menu "Select USB host template, please select class driver first" - config TEST_USBH_CDC_ACM - int - prompt "demo for test cdc acm" - default 0 - depends on CHERRYUSB_HOST_CDC_ACM - config TEST_USBH_HID + config CONFIG_TEST_USBH_SERIAL + bool + prompt "demo for test seial, cannot enable this demo, you can use rt-thread device api to test" + default n + depends on CONFIG_USBHOST_SERIAL + config CONFIG_TEST_USBH_HID int prompt "demo for test hid" default 0 - depends on CHERRYUSB_HOST_HID - config TEST_USBH_MSC - int - prompt "demo for test msc" - default 0 - depends on CHERRYUSB_HOST_MSC + depends on RT_CHERRYUSB_HOST_HID + config CONFIG_TEST_USBH_MSC + bool + prompt "demo for test msc, cannot enable this demo, you can use rt-thread dfs api to test" + default n + depends on RT_CHERRYUSB_HOST_MSC + config CONFIG_TEST_USBH_NET + bool + prompt "demo for test net, cannot enable this demo, you can use lwip api to test" + default n + depends on RT_CHERRYUSB_HOST_CDC_ECM || RT_CHERRYUSB_HOST_CDC_RNDIS || RT_CHERRYUSB_HOST_CDC_NCM || RT_CHERRYUSB_HOST_ASIX || RT_CHERRYUSB_HOST_RTL8152 endmenu endif endif diff --git a/components/drivers/usb/cherryusb/Kconfig.rtt b/components/drivers/usb/cherryusb/Kconfig.rtt deleted file mode 100644 index 9e1d7a500c..0000000000 --- a/components/drivers/usb/cherryusb/Kconfig.rtt +++ /dev/null @@ -1,462 +0,0 @@ -# Kconfig file for package CherryUSB -menuconfig RT_USING_CHERRYUSB - bool "Using USB with CherryUSB" - default n - -if RT_USING_CHERRYUSB - - menuconfig RT_CHERRYUSB_DEVICE - bool "Enable usb device mode" - default n - - if RT_CHERRYUSB_DEVICE - choice - prompt "Select usb device speed" - default RT_CHERRYUSB_DEVICE_SPEED_FS - config RT_CHERRYUSB_DEVICE_SPEED_FS - bool "FS" - config RT_CHERRYUSB_DEVICE_SPEED_HS - bool "HS" - config RT_CHERRYUSB_DEVICE_SPEED_AUTO - bool "AUTO" - endchoice - - choice - prompt "Select usb device ip, and some ip need config in usb_config.h, please check" - default RT_CHERRYUSB_DEVICE_CUSTOM - config RT_CHERRYUSB_DEVICE_CUSTOM - bool "CUSTOM (Implement it yourself)" - config RT_CHERRYUSB_DEVICE_FSDEV_ST - bool "fsdev_st" - config RT_CHERRYUSB_DEVICE_FSDEV_CUSTOM - bool "fsdev_custom" - config RT_CHERRYUSB_DEVICE_DWC2_ST - bool "dwc2_st" - config RT_CHERRYUSB_DEVICE_DWC2_ESP - bool "dwc2_esp" - config RT_CHERRYUSB_DEVICE_DWC2_KENDRYTE - bool "dwc2_kendryte" - config RT_CHERRYUSB_DEVICE_DWC2_AT - bool "dwc2_at" - config RT_CHERRYUSB_DEVICE_DWC2_HC - bool "dwc2_hc" - config RT_CHERRYUSB_DEVICE_DWC2_NATION - bool "dwc2_nation" - config RT_CHERRYUSB_DEVICE_DWC2_GD - bool "dwc2_gd" - config RT_CHERRYUSB_DEVICE_DWC2_CUSTOM - bool "dwc2_custom" - config RT_CHERRYUSB_DEVICE_MUSB_ES - bool "musb_es" - config RT_CHERRYUSB_DEVICE_MUSB_SUNXI - bool "musb_sunxi" - config RT_CHERRYUSB_DEVICE_MUSB_BK - bool "musb_bk" - config RT_CHERRYUSB_DEVICE_MUSB_SIFLI - bool "musb_sifli" - config RT_CHERRYUSB_DEVICE_MUSB_CUSTOM - bool "musb_custom" - config RT_CHERRYUSB_DEVICE_CHIPIDEA_MCX - bool "chipidea_mcx" - config RT_CHERRYUSB_DEVICE_CHIPIDEA_CUSTOM - bool "chipidea_custom" - config RT_CHERRYUSB_DEVICE_KINETIS_MCX - bool "kinetis_mcx" - config RT_CHERRYUSB_DEVICE_KINETIS_MM32 - bool "kinetis_mm32" - config RT_CHERRYUSB_DEVICE_KINETIS_CUSTOM - bool "kinetis_custom" - config RT_CHERRYUSB_DEVICE_BL - bool "bouffalo" - config RT_CHERRYUSB_DEVICE_HPM - bool "hpm" - config RT_CHERRYUSB_DEVICE_AIC - bool "aic" - config RT_CHERRYUSB_DEVICE_RP2040 - bool "rp2040" - config RT_CHERRYUSB_DEVICE_CH32 - bool "ch32" - config RT_CHERRYUSB_DEVICE_PUSB2 - bool "pusb2" - config RT_CHERRYUSB_DEVICE_NRF5X - bool "nrf5x" - endchoice - - config RT_CHERRYUSB_DEVICE_CDC_ACM - bool - prompt "Enable usb cdc acm device" - default n - - config RT_CHERRYUSB_DEVICE_HID - bool - prompt "Enable usb hid device" - default n - - config RT_CHERRYUSB_DEVICE_MSC - bool - prompt "Enable usb msc device" - default n - - config RT_CHERRYUSB_DEVICE_AUDIO - bool - prompt "Enable usb audio device" - default n - - config RT_CHERRYUSB_DEVICE_VIDEO - bool - prompt "Enable usb video device" - default n - - config RT_CHERRYUSB_DEVICE_CDC_RNDIS - bool - prompt "Enable usb cdc rndis device" - default n - - config RT_CHERRYUSB_DEVICE_CDC_ECM - bool - prompt "Enable usb cdc ecm device" - default n - - config RT_CHERRYUSB_DEVICE_CDC_NCM - bool - prompt "Enable usb cdc ncm device" - default n - - config RT_CHERRYUSB_DEVICE_MTP - bool - prompt "Enable usb mtp device, it is commercial charge" - default n - - config RT_CHERRYUSB_DEVICE_ADB - bool - prompt "Enable usb adb device" - default n - - config RT_CHERRYUSB_DEVICE_DFU - bool - prompt "Enable usb dfu device" - default n - - config RT_CHERRYUSB_DEVICE_CDC_ACM_CHARDEV - bool - prompt "Enable chardev for cdc acm device" - default n - - config CONFIG_USBDEV_REQUEST_BUFFER_LEN - int - prompt "Set device control transfer max buffer size" - default 512 - - config CONFIG_USBDEV_MSC_MAX_BUFSIZE - int - prompt "Set usb msc device max buffer size" - default 512 - help - Set the maximum buffer size for usb msc device, it is used to transfer data. - you can change it to a larger value if you need larger speed but must be a power of blocksize. - - config CONFIG_USBDEV_RNDIS_USING_LWIP - bool - prompt "Enable usb rndis device with lwip for lan" - default n - - config CONFIG_USBDEV_CDC_ECM_USING_LWIP - bool - prompt "Enable usb cdc ecm device with lwip for lan" - default n - - choice - prompt "Select usb device template, please select class driver first" - default RT_CHERRYUSB_DEVICE_TEMPLATE_NONE - config RT_CHERRYUSB_DEVICE_TEMPLATE_NONE - bool - prompt "none (Implement it yourself)" - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM - bool - prompt "cdc_acm" - depends on RT_CHERRYUSB_DEVICE_CDC_ACM - config RT_CHERRYUSB_DEVICE_TEMPLATE_MSC - bool - prompt "msc_ram" - depends on RT_CHERRYUSB_DEVICE_MSC - config RT_CHERRYUSB_DEVICE_TEMPLATE_MSC_BLKDEV - bool - prompt "msc_blkdev" - depends on RT_CHERRYUSB_DEVICE_MSC - config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD - bool - prompt "hid_keyboard" - depends on RT_CHERRYUSB_DEVICE_HID - config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE - bool - prompt "hid_mouse" - depends on RT_CHERRYUSB_DEVICE_HID - config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM - bool - prompt "hid_custom" - depends on RT_CHERRYUSB_DEVICE_HID - config RT_CHERRYUSB_DEVICE_TEMPLATE_VIDEO - bool - prompt "video" - depends on RT_CHERRYUSB_DEVICE_VIDEO - config RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER - bool - prompt "audio_v1_mic_speaker_multichan" - depends on RT_CHERRYUSB_DEVICE_AUDIO - config RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER - bool - prompt "audio_v2_mic_speaker_multichan" - depends on RT_CHERRYUSB_DEVICE_AUDIO - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS - bool - prompt "cdc_rndis" - depends on RT_CHERRYUSB_DEVICE_CDC_RNDIS - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM - bool - prompt "cdc_ecm" - depends on RT_CHERRYUSB_DEVICE_CDC_ECM - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM - bool - prompt "cdc_ncm" - depends on RT_CHERRYUSB_DEVICE_CDC_NCM - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC - bool - prompt "cdc_acm_msc" - depends on RT_CHERRYUSB_DEVICE_CDC_ACM && RT_CHERRYUSB_DEVICE_MSC - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID - bool - prompt "cdc_acm_msc_hid" - depends on RT_CHERRYUSB_DEVICE_CDC_ACM && RT_CHERRYUSB_DEVICE_MSC && RT_CHERRYUSB_DEVICE_HID - config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 - bool - prompt "winusbv1" - config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC - bool - prompt "winusbv2_cdc" - depends on RT_CHERRYUSB_DEVICE_CDC_ACM - config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID - bool - prompt "winusbv2_hid" - depends on RT_CHERRYUSB_DEVICE_HID - config RT_CHERRYUSB_DEVICE_TEMPLATE_ADB - bool - prompt "adb" - depends on RT_CHERRYUSB_DEVICE_ADB - config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_CHARDEV - bool - prompt "cdc_acm_chardev" - depends on RT_CHERRYUSB_DEVICE_CDC_ACM_CHARDEV - endchoice - - config CONFIG_USBDEV_MSC_BLOCK_DEV_NAME - string "usb device msc block device name" - depends on RT_CHERRYUSB_DEVICE_TEMPLATE_MSC_BLKDEV - default "sd0" - - endif - - menuconfig RT_CHERRYUSB_HOST - bool "Enable usb host mode" - default n - - if RT_CHERRYUSB_HOST - choice - prompt "Select usb host ip, and some ip need config in usb_config.h, please check" - default RT_CHERRYUSB_HOST_CUSTOM - config RT_CHERRYUSB_HOST_CUSTOM - bool "CUSTOM (Implement it yourself)" - config RT_CHERRYUSB_HOST_EHCI_BL - bool "ehci_bouffalo" - config RT_CHERRYUSB_HOST_EHCI_HPM - bool "ehci_hpm" - config RT_CHERRYUSB_HOST_EHCI_AIC - bool "ehci_aic" - config RT_CHERRYUSB_HOST_EHCI_MCX - bool "ehci_mcx" - config RT_CHERRYUSB_HOST_EHCI_NUC980 - bool "ehci_nuc980" - config RT_CHERRYUSB_HOST_EHCI_MA35D0 - bool "ehci_ma35d0" - config RT_CHERRYUSB_HOST_EHCI_CUSTOM - bool "ehci_custom" - config RT_CHERRYUSB_HOST_DWC2_ST - bool "dwc2_st" - config RT_CHERRYUSB_HOST_DWC2_ESP - bool "dwc2_esp" - config RT_CHERRYUSB_HOST_DWC2_KENDRYTE - bool "dwc2_kendryte" - config RT_CHERRYUSB_HOST_DWC2_HC - bool "dwc2_hc" - config RT_CHERRYUSB_HOST_DWC2_NATION - bool "dwc2_nation" - config RT_CHERRYUSB_HOST_DWC2_CUSTOM - bool "dwc2_custom" - config RT_CHERRYUSB_HOST_MUSB_ES - bool "musb_es" - config RT_CHERRYUSB_HOST_MUSB_SUNXI - bool "musb_sunxi" - config RT_CHERRYUSB_HOST_MUSB_BK - bool "musb_bk" - config RT_CHERRYUSB_HOST_MUSB_SIFLI - bool "musb_sifli" - config RT_CHERRYUSB_HOST_MUSB_CUSTOM - bool "musb_custom" - config RT_CHERRYUSB_HOST_PUSB2 - bool "pusb2" - config RT_CHERRYUSB_HOST_XHCI - bool "xhci" - config RT_CHERRYUSB_HOST_RP2040 - bool "rp2040" - endchoice - - config RT_CHERRYUSB_HOST_CDC_ACM - bool - prompt "Enable usb cdc acm driver" - default n - - config RT_CHERRYUSB_HOST_HID - bool - prompt "Enable usb hid driver" - default n - - config RT_CHERRYUSB_HOST_MSC - bool - prompt "Enable usb msc driver" - default n - select RT_USING_DFS - select RT_USING_DFS_ELMFAT - - config RT_CHERRYUSB_HOST_CDC_ECM - bool - prompt "Enable usb cdc ecm driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_CDC_ECM - default n - - config RT_CHERRYUSB_HOST_CDC_RNDIS - bool - prompt "Enable usb rndis driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_CDC_RNDIS - default n - - config RT_CHERRYUSB_HOST_CDC_NCM - bool - prompt "Enable usb cdc ncm driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_CDC_NCM - default n - - config RT_CHERRYUSB_HOST_VIDEO - bool - prompt "Enable usb video driver, it is commercial charge" - default n - - config RT_CHERRYUSB_HOST_AUDIO - bool - prompt "Enable usb audio driver, it is commercial charge" - default n - - config RT_CHERRYUSB_HOST_BLUETOOTH - bool - prompt "Enable usb bluetooth driver" - default n - - config RT_CHERRYUSB_HOST_ASIX - bool - prompt "Enable usb asix driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_ASIX - default n - - config RT_CHERRYUSB_HOST_RTL8152 - bool - prompt "Enable usb rtl8152 driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_RTL8152 - default n - - config RT_CHERRYUSB_HOST_FTDI - bool - prompt "Enable usb ftdi driver" - default n - - config RT_CHERRYUSB_HOST_CH34X - bool - prompt "Enable usb ch34x driver" - default n - - config RT_CHERRYUSB_HOST_CP210X - bool - prompt "Enable usb cp210x driver" - default n - - config RT_CHERRYUSB_HOST_PL2303 - bool - prompt "Enable usb pl2303 driver" - default n - - config CONFIG_USBHOST_PLATFORM_CDC_ECM - bool - - config CONFIG_USBHOST_PLATFORM_CDC_RNDIS - bool - - config CONFIG_USBHOST_PLATFORM_CDC_NCM - bool - - config CONFIG_USBHOST_PLATFORM_ASIX - bool - - config CONFIG_USBHOST_PLATFORM_RTL8152 - bool - - config CONFIG_USBHOST_PSC_PRIO - int - prompt "Set hubport change thread priority, 0 is the max priority" - default 0 - - config CONFIG_USBHOST_PSC_STACKSIZE - int - prompt "Set hubport change thread stacksize" - default 4096 - - config CONFIG_USBHOST_REQUEST_BUFFER_LEN - int - prompt "Set host control transfer max buffer size" - default 512 - - config CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT - int - prompt "Set host control transfer timeout, unit is ms" - default 500 - - config RT_LWIP_PBUF_POOL_BUFSIZE - int "The size of each pbuf in the pbuf pool" - range 1500 2000 - default 1600 - - config CONFIG_USB_DFS_MOUNT_POINT - string "usb host dfs mount point" - depends on RT_CHERRYUSB_HOST_MSC - default "/" - - menu "Select USB host template, please select class driver first" - config CONFIG_TEST_USBH_CDC_ACM - int - prompt "demo for test cdc acm, cannot enable this demo, we have used serial framework instead" - default 0 - depends on RT_CHERRYUSB_HOST_CDC_ACM - config CONFIG_TEST_USBH_HID - int - prompt "demo for test hid" - default 0 - depends on RT_CHERRYUSB_HOST_HID - config CONFIG_TEST_USBH_MSC - int - prompt "demo for test msc, cannot enable this demo, we have used dfs instead" - default 0 - depends on RT_CHERRYUSB_HOST_MSC - endmenu - endif -endif diff --git a/components/drivers/usb/cherryusb/Kconfig.rttpkg b/components/drivers/usb/cherryusb/Kconfig.rttpkg deleted file mode 100644 index e5a0e430a5..0000000000 --- a/components/drivers/usb/cherryusb/Kconfig.rttpkg +++ /dev/null @@ -1,500 +0,0 @@ -# Kconfig file for package CherryUSB -menuconfig PKG_USING_CHERRYUSB - depends on RT_VER_NUM < 0x50200 - bool "CherryUSB: tiny and portable USB host/device stack for embedded system with USB IP" - default n - -if PKG_USING_CHERRYUSB - - menuconfig PKG_CHERRYUSB_DEVICE - bool "Enable usb device mode" - default n - - if PKG_CHERRYUSB_DEVICE - choice - prompt "Select usb device speed" - default PKG_CHERRYUSB_DEVICE_SPEED_FS - config PKG_CHERRYUSB_DEVICE_SPEED_FS - bool "FS" - config PKG_CHERRYUSB_DEVICE_SPEED_HS - bool "HS" - config PKG_CHERRYUSB_DEVICE_SPEED_AUTO - bool "AUTO" - endchoice - - choice - prompt "Select usb device ip, and some ip need config in usb_config.h, please check" - default PKG_CHERRYUSB_DEVICE_CUSTOM - config PKG_CHERRYUSB_DEVICE_CUSTOM - bool "CUSTOM (Implement it yourself)" - config PKG_CHERRYUSB_DEVICE_FSDEV_ST - bool "fsdev_st" - config PKG_CHERRYUSB_DEVICE_FSDEV_CUSTOM - bool "fsdev_custom" - config PKG_CHERRYUSB_DEVICE_DWC2_ST - bool "dwc2_st" - config PKG_CHERRYUSB_DEVICE_DWC2_ESP - bool "dwc2_esp" - config PKG_CHERRYUSB_DEVICE_DWC2_KENDRYTE - bool "dwc2_kendryte" - config PKG_CHERRYUSB_DEVICE_DWC2_AT - bool "dwc2_at" - config PKG_CHERRYUSB_DEVICE_DWC2_HC - bool "dwc2_hc" - config PKG_CHERRYUSB_DEVICE_DWC2_NATION - bool "dwc2_nation" - config PKG_CHERRYUSB_DEVICE_DWC2_GD - bool "dwc2_gd" - config PKG_CHERRYUSB_DEVICE_DWC2_CUSTOM - bool "dwc2_custom" - config PKG_CHERRYUSB_DEVICE_MUSB_ES - bool "musb_es" - config PKG_CHERRYUSB_DEVICE_MUSB_SUNXI - bool "musb_sunxi" - config PKG_CHERRYUSB_DEVICE_MUSB_BK - bool "musb_bk" - config PKG_CHERRYUSB_DEVICE_MUSB_SIFLI - bool "musb_sifli" - config PKG_CHERRYUSB_DEVICE_MUSB_CUSTOM - bool "musb_custom" - config PKG_CHERRYUSB_DEVICE_CHIPIDEA_MCX - bool "chipidea_mcx" - config PKG_CHERRYUSB_DEVICE_CHIPIDEA_CUSTOM - bool "chipidea_custom" - config PKG_CHERRYUSB_DEVICE_KINETIS_MCX - bool "kinetis_mcx" - config PKG_CHERRYUSB_DEVICE_KINETIS_MM32 - bool "kinetis_mm32" - config PKG_CHERRYUSB_DEVICE_KINETIS_CUSTOM - bool "kinetis_custom" - config PKG_CHERRYUSB_DEVICE_BL - bool "bouffalo" - config PKG_CHERRYUSB_DEVICE_HPM - bool "hpm" - config PKG_CHERRYUSB_DEVICE_AIC - bool "aic" - config PKG_CHERRYUSB_DEVICE_RP2040 - bool "rp2040" - config PKG_CHERRYUSB_DEVICE_CH32 - bool "ch32" - config PKG_CHERRYUSB_DEVICE_PUSB2 - bool "pusb2" - endchoice - - config PKG_CHERRYUSB_DEVICE_CDC_ACM - bool - prompt "Enable usb cdc acm device" - default n - - config PKG_CHERRYUSB_DEVICE_HID - bool - prompt "Enable usb hid device" - default n - - config PKG_CHERRYUSB_DEVICE_MSC - bool - prompt "Enable usb msc device" - default n - - config PKG_CHERRYUSB_DEVICE_AUDIO - bool - prompt "Enable usb audio device" - default n - - config PKG_CHERRYUSB_DEVICE_VIDEO - bool - prompt "Enable usb video device" - default n - - config PKG_CHERRYUSB_DEVICE_CDC_RNDIS - bool - prompt "Enable usb cdc rndis device" - default n - - config PKG_CHERRYUSB_DEVICE_CDC_ECM - bool - prompt "Enable usb cdc ecm device" - default n - - config PKG_CHERRYUSB_DEVICE_CDC_NCM - bool - prompt "Enable usb cdc ncm device" - default n - - config PKG_CHERRYUSB_DEVICE_MTP - bool - prompt "Enable usb mtp device, it is commercial charge" - default n - - config PKG_CHERRYUSB_DEVICE_ADB - bool - prompt "Enable usb adb device" - default n - - config PKG_CHERRYUSB_DEVICE_DFU - bool - prompt "Enable usb dfu device" - default n - - config PKG_CHERRYUSB_DEVICE_CDC_ACM_CHARDEV - bool - prompt "Enable chardev for cdc acm device" - default n - - config CONFIG_USBDEV_REQUEST_BUFFER_LEN - int - prompt "Set device control transfer max buffer size" - default 512 - - config CONFIG_USBDEV_MSC_MAX_BUFSIZE - int - prompt "Set usb msc device max buffer size" - default 512 - help - Set the maximum buffer size for usb msc device, it is used to transfer data. - you can change it to a larger value if you need larger speed but must be a power of blocksize. - - config CONFIG_USBDEV_RNDIS_USING_LWIP - bool - prompt "Enable usb rndis device with lwip for lan" - default n - - config CONFIG_USBDEV_CDC_ECM_USING_LWIP - bool - prompt "Enable usb cdc ecm device with lwip for lan" - default n - - choice - prompt "Select usb device template, please select class driver first" - default PKG_CHERRYUSB_DEVICE_TEMPLATE_NONE - config PKG_CHERRYUSB_DEVICE_TEMPLATE_NONE - bool - prompt "none (Implement it yourself)" - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM - bool - prompt "cdc_acm" - depends on PKG_CHERRYUSB_DEVICE_CDC_ACM - config PKG_CHERRYUSB_DEVICE_TEMPLATE_MSC - bool - prompt "msc_ram" - depends on PKG_CHERRYUSB_DEVICE_MSC - config PKG_CHERRYUSB_DEVICE_TEMPLATE_MSC_BLKDEV - bool - prompt "msc_blkdev" - depends on PKG_CHERRYUSB_DEVICE_MSC - config PKG_CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD - bool - prompt "hid_keyboard" - depends on PKG_CHERRYUSB_DEVICE_HID - config PKG_CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE - bool - prompt "hid_mouse" - depends on PKG_CHERRYUSB_DEVICE_HID - config PKG_CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM - bool - prompt "hid_custom" - depends on PKG_CHERRYUSB_DEVICE_HID - config PKG_CHERRYUSB_DEVICE_TEMPLATE_VIDEO - bool - prompt "video" - depends on PKG_CHERRYUSB_DEVICE_VIDEO - config PKG_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER - bool - prompt "audio_v1_mic_speaker_multichan" - depends on PKG_CHERRYUSB_DEVICE_AUDIO - config PKG_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER - bool - prompt "audio_v2_mic_speaker_multichan" - depends on PKG_CHERRYUSB_DEVICE_AUDIO - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS - bool - prompt "cdc_rndis" - depends on PKG_CHERRYUSB_DEVICE_CDC_RNDIS - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM - bool - prompt "cdc_ecm" - depends on PKG_CHERRYUSB_DEVICE_CDC_ECM - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM - bool - prompt "cdc_ncm" - depends on PKG_CHERRYUSB_DEVICE_CDC_NCM - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC - bool - prompt "cdc_acm_msc" - depends on PKG_CHERRYUSB_DEVICE_CDC_ACM && PKG_CHERRYUSB_DEVICE_MSC - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID - bool - prompt "cdc_acm_msc_hid" - depends on PKG_CHERRYUSB_DEVICE_CDC_ACM && PKG_CHERRYUSB_DEVICE_MSC && PKG_CHERRYUSB_DEVICE_HID - config PKG_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 - bool - prompt "winusbv1" - config PKG_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC - bool - prompt "winusbv2_cdc" - depends on PKG_CHERRYUSB_DEVICE_CDC_ACM - config PKG_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID - bool - prompt "winusbv2_hid" - depends on PKG_CHERRYUSB_DEVICE_HID - config PKG_CHERRYUSB_DEVICE_TEMPLATE_ADB - bool - prompt "adb" - depends on PKG_CHERRYUSB_DEVICE_ADB - config PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_CHARDEV - bool - prompt "cdc_acm_chardev" - depends on PKG_CHERRYUSB_DEVICE_CDC_ACM_CHARDEV - endchoice - - config CONFIG_USBDEV_MSC_BLOCK_DEV_NAME - string "usb device msc block device name" - depends on PKG_CHERRYUSB_DEVICE_TEMPLATE_MSC_BLKDEV - default "sd0" - - endif - - menuconfig PKG_CHERRYUSB_HOST - bool "Enable usb host mode" - default n - - if PKG_CHERRYUSB_HOST - choice - prompt "Select usb host ip, and some ip need config in usb_config.h, please check" - default PKG_CHERRYUSB_HOST_CUSTOM - config PKG_CHERRYUSB_HOST_CUSTOM - bool "CUSTOM (Implement it yourself)" - config PKG_CHERRYUSB_HOST_EHCI_BL - bool "ehci_bouffalo" - config PKG_CHERRYUSB_HOST_EHCI_HPM - bool "ehci_hpm" - config PKG_CHERRYUSB_HOST_EHCI_AIC - bool "ehci_aic" - config PKG_CHERRYUSB_HOST_EHCI_MCX - bool "ehci_mcx" - config PKG_CHERRYUSB_HOST_EHCI_NUC980 - bool "ehci_nuc980" - config PKG_CHERRYUSB_HOST_EHCI_MA35D0 - bool "ehci_ma35d0" - config PKG_CHERRYUSB_HOST_EHCI_CUSTOM - bool "ehci_custom" - config PKG_CHERRYUSB_HOST_DWC2_ST - bool "dwc2_st" - config PKG_CHERRYUSB_HOST_DWC2_ESP - bool "dwc2_esp" - config PKG_CHERRYUSB_HOST_DWC2_KENDRYTE - bool "dwc2_kendryte" - config PKG_CHERRYUSB_HOST_DWC2_HC - bool "dwc2_hc" - config PKG_CHERRYUSB_HOST_DWC2_NATION - bool "dwc2_nation" - config PKG_CHERRYUSB_HOST_DWC2_CUSTOM - bool "dwc2_custom" - config PKG_CHERRYUSB_HOST_MUSB_ES - bool "musb_es" - config PKG_CHERRYUSB_HOST_MUSB_SUNXI - bool "musb_sunxi" - config PKG_CHERRYUSB_HOST_MUSB_BK - bool "musb_bk" - config PKG_CHERRYUSB_HOST_MUSB_SIFLI - bool "musb_sifli" - config PKG_CHERRYUSB_HOST_MUSB_CUSTOM - bool "musb_custom" - config PKG_CHERRYUSB_HOST_PUSB2 - bool "pusb2" - config PKG_CHERRYUSB_HOST_XHCI - bool "xhci" - config PKG_CHERRYUSB_HOST_RP2040 - bool "rp2040" - endchoice - - config PKG_CHERRYUSB_HOST_CDC_ACM - bool - prompt "Enable usb cdc acm driver" - default n - - config PKG_CHERRYUSB_HOST_HID - bool - prompt "Enable usb hid driver" - default n - - config PKG_CHERRYUSB_HOST_MSC - bool - prompt "Enable usb msc driver" - default n - select RT_USING_DFS - select RT_USING_DFS_ELMFAT - - config PKG_CHERRYUSB_HOST_CDC_ECM - bool - prompt "Enable usb cdc ecm driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_CDC_ECM - default n - - config PKG_CHERRYUSB_HOST_CDC_RNDIS - bool - prompt "Enable usb rndis driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_CDC_RNDIS - default n - - config PKG_CHERRYUSB_HOST_CDC_NCM - bool - prompt "Enable usb cdc ncm driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_CDC_NCM - default n - - config PKG_CHERRYUSB_HOST_VIDEO - bool - prompt "Enable usb video driver, it is commercial charge" - default n - - config PKG_CHERRYUSB_HOST_AUDIO - bool - prompt "Enable usb audio driver, it is commercial charge" - default n - - config PKG_CHERRYUSB_HOST_BLUETOOTH - bool - prompt "Enable usb bluetooth driver" - default n - - config PKG_CHERRYUSB_HOST_ASIX - bool - prompt "Enable usb asix driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_ASIX - default n - - config PKG_CHERRYUSB_HOST_RTL8152 - bool - prompt "Enable usb rtl8152 driver" - select RT_USING_LWIP - select CONFIG_USBHOST_PLATFORM_RTL8152 - default n - - config PKG_CHERRYUSB_HOST_FTDI - bool - prompt "Enable usb ftdi driver" - default n - - config PKG_CHERRYUSB_HOST_CH34X - bool - prompt "Enable usb ch34x driver" - default n - - config PKG_CHERRYUSB_HOST_CP210X - bool - prompt "Enable usb cp210x driver" - default n - - config PKG_CHERRYUSB_HOST_PL2303 - bool - prompt "Enable usb pl2303 driver" - default n - - config CONFIG_USBHOST_PLATFORM_CDC_ECM - bool - - config CONFIG_USBHOST_PLATFORM_CDC_RNDIS - bool - - config CONFIG_USBHOST_PLATFORM_CDC_NCM - bool - - config CONFIG_USBHOST_PLATFORM_ASIX - bool - - config CONFIG_USBHOST_PLATFORM_RTL8152 - bool - - config CONFIG_USBHOST_PSC_PRIO - int - prompt "Set hubport change thread priority, 0 is the max priority" - default 0 - - config CONFIG_USBHOST_PSC_STACKSIZE - int - prompt "Set hubport change thread stacksize" - default 4096 - - config CONFIG_USBHOST_REQUEST_BUFFER_LEN - int - prompt "Set host control transfer max buffer size" - default 512 - - config CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT - int - prompt "Set host control transfer timeout, unit is ms" - default 500 - - config RT_LWIP_PBUF_POOL_BUFSIZE - int "The size of each pbuf in the pbuf pool" - range 1500 2000 - default 1600 - - config CONFIG_USB_DFS_MOUNT_POINT - string "usb host dfs mount point" - depends on RT_CHERRYUSB_HOST_MSC - default "/" - - menu "Select USB host template, please select class driver first" - config CONFIG_TEST_USBH_CDC_ACM - int - prompt "demo for test cdc acm, cannot enable this demo, we have used serial framework instead" - default 0 - depends on PKG_CHERRYUSB_HOST_CDC_ACM - config CONFIG_TEST_USBH_HID - int - prompt "demo for test hid" - default 0 - depends on PKG_CHERRYUSB_HOST_HID - config CONFIG_TEST_USBH_MSC - int - prompt "demo for test msc, cannot enable this demo, we have used dfs instead" - default 0 - depends on PKG_CHERRYUSB_HOST_MSC - endmenu - endif - - config PKG_CHERRYUSB_PATH - string - default "/packages/system/CherryUSB" - - choice - prompt "Version" - default PKG_USING_CHERRYUSB_V010502 - help - Select the package version - - config PKG_USING_CHERRYUSB_LATEST_VERSION - bool "latest" - config PKG_USING_CHERRYUSB_V010502 - bool "v1.5.2" - config PKG_USING_CHERRYUSB_V010501 - bool "v1.5.1" - config PKG_USING_CHERRYUSB_V010500 - bool "v1.5.0" - config PKG_USING_CHERRYUSB_V010403 - bool "v1.4.3" - config PKG_USING_CHERRYUSB_V010301 - bool "v1.3.1" - config PKG_USING_CHERRYUSB_V010200 - bool "v1.2.0" - config PKG_USING_CHERRYUSB_V001002 - bool "v0.10.2" - endchoice - - config PKG_CHERRYUSB_VER - string - default "latest" if PKG_USING_CHERRYUSB_LATEST_VERSION - default "v1.5.2" if PKG_USING_CHERRYUSB_V010502 - default "v1.5.1" if PKG_USING_CHERRYUSB_V010501 - default "v1.5.0" if PKG_USING_CHERRYUSB_V010500 - default "v1.4.3" if PKG_USING_CHERRYUSB_V010403 - default "v1.3.1" if PKG_USING_CHERRYUSB_V010301 - default "v1.2.0" if PKG_USING_CHERRYUSB_V010200 - default "v0.10.2" if PKG_USING_CHERRYUSB_V001002 -endif diff --git a/components/drivers/usb/cherryusb/README.md b/components/drivers/usb/cherryusb/README.md index fcb6f13c96..d514f1fb08 100644 --- a/components/drivers/usb/cherryusb/README.md +++ b/components/drivers/usb/cherryusb/README.md @@ -40,6 +40,8 @@ Taking into account USB performance issues and trying to achieve the theoretical - Unlimited length make it easier to interface with hardware DMA and take advantage of DMA - Packetization is handled in interrupt +Performance show：https://cherryusb.cherry-embedded.org/show/ + ## Directory Structure | Directory | Description | @@ -103,14 +105,15 @@ CherryUSB Host Stack has the following functions: - Support blocking transfers and asynchronous transfers - Support Composite Device - Multi-level HUB support, expandable up to 7 levels(Testing hub with 10 ports works well,only support dwc2/ehci/xhci/rp2040) -- Support Communication Device Class (CDC_ACM, CDC_ECM) +- Support Communication Device Class (CDC_ACM, CDC_ECM, CDC_NCM) - Support Human Interface Device (HID) - Support Mass Storage Class (MSC) - Support USB Video CLASS (UVC1.0, UVC1.5) - Support USB Audio CLASS (UAC1.0) - Support Remote NDIS (RNDIS) - Support USB Bluetooth class (support nimble and zephyr bluetooth stack, support **CLASS:0xE0** or vendor class like cdc acm) -- Support Vendor class (serial, net, wifi) +- Support Vendor Serial Class(CH34X、CP210X、PL2303、FTDI、GSM) +- Support Vendor network Class(RTL8152、AX88772) - Support USB modeswitch - Support Android Open Accessory - Support multi host with the same USB IP @@ -141,14 +144,14 @@ Among them, `sizeof(struct usbh_hub)` and `sizeof(struct usbh_hubport)` are affe #define CONFIG_USBHOST_MAX_EXTHUBS 1 #define CONFIG_USBHOST_MAX_EHPORTS 4 #define CONFIG_USBHOST_MAX_INTERFACES 8 -#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 2 #define CONFIG_USBHOST_MAX_ENDPOINTS 4 ``` x is affected by the following macros: ``` -#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_SERIAL_CLASS 4 #define CONFIG_USBHOST_MAX_HID_CLASS 4 #define CONFIG_USBHOST_MAX_MSC_CLASS 2 #define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 @@ -179,32 +182,33 @@ Quickly start, USB basic concepts, API manual, Class basic concepts and examples ## Video Tutorial -CherryUSB Cheese (based V1.4.3): https://www.bilibili.com/cheese/play/ss707687201 . +CherryUSB Cheese (>= V1.4.3): https://www.bilibili.com/cheese/play/ss707687201 . ## Descriptor Generator Tool -TODO +Cherry Descriptor: https://desc.cherry-embedded.org/en ## Demo Repo -| Manufacturer | CHIP or Series | USB IP| Repo Url | Support version | Support status | +| Manufacturer | CHIP or Series | USB IP| Repo Url | Support version | Note | |:--------------------:|:------------------:|:-----:|:--------:|:------------------:|:-------------:| -|Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Long-term | -|ST | STM32F1x/STM32F4/STM32H7 | fsdev/dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | -|HPMicro | HPM6000/HPM5000 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | -|Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Long-term | -|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|>=1.4.0 | Long-term | -|Artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term | -|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | Long-term | -|NXP | mcx | kinetis/chipidea/ehci |[nxp_mcx_repo](https://github.com/CherryUSB/cherryusb_mcx)|<= latest | Long-term | -|Kendryte | k230 | dwc2 |[k230_repo](https://github.com/CherryUSB/k230_sdk)|v1.2.0 | Long-term | -|Actionstech | ATS30xx | dwc2 |[action_zephyr_repo](https://github.com/CherryUSB/lv_port_actions_technology/tree/master/action_technology_sdk)|>=1.4.0 | Long-term | -|Nationstech | n32h4x | dwc2 |[nation_repo](https://github.com/CherryUSB/cherryusb_nation)|>=1.5.0 | Long-term | -|Raspberry pi | rp2040/rp2350 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|<= latest | Long-term | -|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with musb | -|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with musb | -|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | TBD | -|WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2/>=v1.5.0 | TBD | +|Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Official | +|ST | STM32F1x/STM32F4/STM32H7 | fsdev/dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Community | +|HPMicro | HPM6000/HPM5000 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Official | +|Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Official | +|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|>=1.4.0 | Official | +|Artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Official | +|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)/[espressif](https://github.com/espressif/esp-idf/tree/master/examples/peripherals/usb)|<= latest | Official | +|Kendryte | k230 | dwc2 |[k230_repo](https://github.com/CherryUSB/k230_sdk)|v1.2.0 | Official | +|Actionstech | ATS30xx | dwc2 |[action_zephyr_repo](https://github.com/CherryUSB/lv_port_actions_technology/tree/master/action_technology_sdk)|>=1.4.0 | Official | +|SiFli | SF32LB5x | musb |[SiFli_sdk](https://github.com/OpenSiFli/SiFli-SDK)|>=1.5.0 | Official | +|NXP | mcx | kinetis/chipidea/ehci |[nxp_mcx_repo](https://github.com/CherryUSB/cherryusb_mcx)|<= latest | Community | +|Nationstech | n32h4x | dwc2 |[nation_repo](https://github.com/CherryUSB/cherryusb_nation)|>=1.5.0 | Official ongoing | +|Raspberry pi | rp2040/rp2350 | rp2040 |[pico-sdk](https://github.com/CherryUSB/pico-sdk)|<= latest | Official ongoing | +|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | no more update | +|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | Official | +|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | Official | +|WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2/>=v1.5.0 | no more update | ## Package Support @@ -226,5 +230,4 @@ CherryUSB discord: https://discord.com/invite/wFfvrSAey8. Thanks to the following companies for their support (in no particular order): - - + diff --git a/components/drivers/usb/cherryusb/README_zh.md b/components/drivers/usb/cherryusb/README_zh.md index 64287a558b..cf76f3ea28 100644 --- a/components/drivers/usb/cherryusb/README_zh.md +++ b/components/drivers/usb/cherryusb/README_zh.md @@ -112,7 +112,8 @@ CherryUSB Host 协议栈当前实现以下功能： - Support USB Audio CLASS (UAC1.0) - 支持 Remote NDIS (RNDIS) - 支持 USB Bluetooth (支持 nimble and zephyr bluetooth 协议栈，支持 **CLASS: 0xE0** 或者厂家自定义类，类似于 cdc acm 功能) -- 支持 Vendor 类 class (serial, net, wifi) +- 支持 Vendor Serial 类(CH34X、CP210X、PL2303、FTDI、GSM) +- 支持 Vendor network 类(RTL8152、AX88772) - 支持 USB modeswitch - 支持 Android Open Accessory - 支持相同 USB IP 的多主机 @@ -150,7 +151,7 @@ CherryUSB Host 协议栈资源占用说明（GCC 10.2 with -O2，关闭 log） x 受以下宏影响： ``` -#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_SERIAL_CLASS 4 #define CONFIG_USBHOST_MAX_HID_CLASS 4 #define CONFIG_USBHOST_MAX_MSC_CLASS 2 #define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 @@ -181,11 +182,11 @@ CherryUSB 快速入门、USB 基本概念、API 手册、Class 基本概念和 ## 视频教程 -CherryUSB 课程（基于 V1.4.3）：https://www.bilibili.com/cheese/play/ss707687201 。 +CherryUSB 课程（>= V1.4.3）：https://www.bilibili.com/cheese/play/ss707687201 。 ## 描述符生成工具 -TODO +Cherry Descriptor: https://desc.cherry-embedded.org/zh ## 示例仓库 @@ -197,7 +198,7 @@ TODO |Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Official | |Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|>=1.4.0 | Official | |Artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Official | -|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | Official ongoing | +|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)/[espressif](https://github.com/espressif/esp-idf/tree/master/examples/peripherals/usb)|<= latest | Official | |Kendryte | k230 | dwc2 |[k230_repo](https://github.com/CherryUSB/k230_sdk)|v1.2.0 | Official | |Actionstech | ATS30xx | dwc2 |[action_zephyr_repo](https://github.com/CherryUSB/lv_port_actions_technology/tree/master/action_technology_sdk)|>=1.4.0 | Official | |SiFli | SF32LB5x | musb |[SiFli_sdk](https://github.com/OpenSiFli/SiFli-SDK)|>=1.5.0 | Official | diff --git a/components/drivers/usb/cherryusb/SConscript b/components/drivers/usb/cherryusb/SConscript index a2a80fdc37..b134dec2ad 100644 --- a/components/drivers/usb/cherryusb/SConscript +++ b/components/drivers/usb/cherryusb/SConscript @@ -14,9 +14,8 @@ path += [cwd + '/class/wireless'] path += [cwd + '/class/midi'] path += [cwd + '/class/adb'] path += [cwd + '/class/dfu'] -path += [cwd + '/class/midi'] +path += [cwd + '/class/serial'] path += [cwd + '/class/vendor/net'] -path += [cwd + '/class/vendor/serial'] path += [cwd + '/class/vendor/wifi'] src = [] @@ -47,6 +46,9 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']): if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_KENDRYTE']): src += Glob('port/dwc2/usb_dc_dwc2.c') src += Glob('port/dwc2/usb_glue_kendryte.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_INFINEON']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + src += Glob('port/dwc2/usb_glue_infineon.c') if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_AT']): src += Glob('port/dwc2/usb_dc_dwc2.c') src += Glob('port/dwc2/usb_glue_at.c') @@ -112,6 +114,9 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']): LIBS = ['libpusb2_dc_a32_softfp_neon.a'] if GetDepend(['RT_CHERRYUSB_DEVICE_NRF5X']): src += Glob('port/nrf5x/usb_dc_nrf5x.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_RP2040']): + path += [cwd + '/port/rp2040'] + src += Glob('port/rp2040/usb_dc_rp2040.c') if GetDepend(['RT_CHERRYUSB_DEVICE_CDC_ACM']): src += Glob('class/cdc/usbd_cdc_acm.c') @@ -166,10 +171,12 @@ if GetDepend(['RT_CHERRYUSB_DEVICE']): src += Glob('demo/cdc_acm_hid_msc_template.c') if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1']): src += Glob('demo/winusb1.0_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2']): + src += Glob('demo/winusb2.0_template.c') if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC']): src += Glob('demo/winusb2.0_cdc_template.c') - if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID']): - src += Glob('demo/winusb2.0_hid_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WEBUSB_HID']): + src += Glob('demo/webusb_hid_template.c') if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_ADB']): src += Glob('demo/adb/usbd_adb_template.c') if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_CHARDEV']): @@ -216,6 +223,12 @@ if GetDepend(['RT_CHERRYUSB_HOST']): if GetDepend(['RT_CHERRYUSB_HOST_DWC2_KENDRYTE']): src += Glob('port/dwc2/usb_hc_dwc2.c') src += Glob('port/dwc2/usb_glue_kendryte.c') + if GetDepend(['RT_CHERRYUSB_HOST_DWC2_INFINEON']): + src += Glob('port/dwc2/usb_hc_dwc2.c') + src += Glob('port/dwc2/usb_glue_infineon.c') + if GetDepend(['RT_CHERRYUSB_HOST_DWC2_AT']): + src += Glob('port/dwc2/usb_hc_dwc2.c') + src += Glob('port/dwc2/usb_glue_at.c') if GetDepend(['RT_CHERRYUSB_HOST_DWC2_HC']): src += Glob('port/dwc2/usb_hc_dwc2.c') src += Glob('port/dwc2/usb_glue_hc.c') @@ -266,8 +279,12 @@ if GetDepend(['RT_CHERRYUSB_HOST']): LIBPATH = [cwd + '/port/xhci/phytium'] LIBS = ['libxhci_a32_softfp_neon.a'] + if GetDepend(['RT_CHERRYUSB_HOST_RP2040']): + path += [cwd + '/port/rp2040'] + src += Glob('port/rp2040/usb_hc_rp2040.c') + if GetDepend(['RT_CHERRYUSB_HOST_CDC_ACM']): - src += Glob('class/cdc/usbh_cdc_acm.c') + src += Glob('class/serial/usbh_cdc_acm.c') if GetDepend(['RT_CHERRYUSB_HOST_HID']): src += Glob('class/hid/usbh_hid.c') if GetDepend(['RT_CHERRYUSB_HOST_MSC']): @@ -289,23 +306,26 @@ if GetDepend(['RT_CHERRYUSB_HOST']): if GetDepend(['RT_CHERRYUSB_HOST_RTL8152']): src += Glob('class/vendor/net/usbh_rtl8152.c') if GetDepend(['RT_CHERRYUSB_HOST_FTDI']): - src += Glob('class/vendor/serial/usbh_ftdi.c') + src += Glob('class/serial/usbh_ftdi.c') if GetDepend(['RT_CHERRYUSB_HOST_CH34X']): - src += Glob('class/vendor/serial/usbh_ch34x.c') + src += Glob('class/serial/usbh_ch34x.c') if GetDepend(['RT_CHERRYUSB_HOST_CP210X']): - src += Glob('class/vendor/serial/usbh_cp210x.c') + src += Glob('class/serial/usbh_cp210x.c') if GetDepend(['RT_CHERRYUSB_HOST_PL2303']): - src += Glob('class/vendor/serial/usbh_pl2303.c') + src += Glob('class/serial/usbh_pl2303.c') - if GetDepend(['CONFIG_TEST_USBH_HID']): + if GetDepend(['RT_TEST_USBH_HID']): + CPPDEFINES+=['CONFIG_TEST_USBH_HID'] src += Glob('demo/usb_host.c') if GetDepend(['RT_CHERRYUSB_HOST_CDC_ACM']) \ or GetDepend(['RT_CHERRYUSB_HOST_FTDI']) \ or GetDepend(['RT_CHERRYUSB_HOST_CH34X']) \ or GetDepend(['RT_CHERRYUSB_HOST_CP210X']) \ - or GetDepend(['RT_CHERRYUSB_HOST_PL2303']): - src += Glob('platform/rtthread/usbh_serial.c') + or GetDepend(['RT_CHERRYUSB_HOST_PL2303']) \ + or GetDepend(['RT_CHERRYUSB_HOST_GSM']): + src += Glob('class/serial/usbh_serial.c') + src += Glob('platform/rtthread/usbh_rtserial.c') if GetDepend('RT_USING_DFS') and GetDepend(['RT_CHERRYUSB_HOST_MSC']): src += Glob('platform/rtthread/usbh_dfs.c') diff --git a/components/drivers/usb/cherryusb/VERSION b/components/drivers/usb/cherryusb/VERSION index 7aa5f8b8df..bf6627b8a1 100644 --- a/components/drivers/usb/cherryusb/VERSION +++ b/components/drivers/usb/cherryusb/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 1 -VERSION_MINOR = 5 -PATCHLEVEL = 2 +VERSION_MINOR = 6 +PATCHLEVEL = 0 VERSION_TWEAK = 0 EXTRAVERSION = 0 diff --git a/components/drivers/usb/cherryusb/cherryusb.cmake b/components/drivers/usb/cherryusb/cherryusb.cmake index 3d7c28b3d9..6957324936 100644 --- a/components/drivers/usb/cherryusb/cherryusb.cmake +++ b/components/drivers/usb/cherryusb/cherryusb.cmake @@ -47,10 +47,11 @@ list( ${CMAKE_CURRENT_LIST_DIR}/class/midi ${CMAKE_CURRENT_LIST_DIR}/class/adb ${CMAKE_CURRENT_LIST_DIR}/class/dfu + ${CMAKE_CURRENT_LIST_DIR}/class/serial ${CMAKE_CURRENT_LIST_DIR}/class/vendor/net - ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial ${CMAKE_CURRENT_LIST_DIR}/class/vendor/wifi ${CMAKE_CURRENT_LIST_DIR}/class/aoa + ${CMAKE_CURRENT_LIST_DIR}/class/gamepad ) if(CONFIG_CHERRYUSB_DEVICE) @@ -85,6 +86,9 @@ if(CONFIG_CHERRYUSB_DEVICE) if(CONFIG_CHERRYUSB_DEVICE_ADB) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/adb/usbd_adb.c) endif() + if(CONFIG_CHERRYUSB_DEVICE_GAMEPAD) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/gamepad/usbd_gamepad.c) + endif() if(CONFIG_CHERRYUSB_DEVICE_FSDEV_ST) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/fsdev/usb_dc_fsdev.c) @@ -156,7 +160,7 @@ if(CONFIG_CHERRYUSB_HOST) ) if(CONFIG_CHERRYUSB_HOST_CDC_ACM) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_acm.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_cdc_acm.c) endif() if(CONFIG_CHERRYUSB_HOST_CDC_ECM) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_ecm.c) @@ -235,30 +239,39 @@ if(CONFIG_CHERRYUSB_HOST) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/net/usbh_rtl8152.c) endif() if(CONFIG_CHERRYUSB_HOST_CH34X) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_ch34x.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_ch34x.c) endif() if(CONFIG_CHERRYUSB_HOST_CP210X) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_cp210x.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_cp210x.c) endif() if(CONFIG_CHERRYUSB_HOST_FTDI) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_ftdi.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_ftdi.c) endif() if(CONFIG_CHERRYUSB_HOST_PL2303) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_pl2303.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_pl2303.c) endif() - if(CONFIG_CHERRYUSB_HOST_BL616) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/wifi/usbh_bl616.c) + if(CONFIG_CHERRYUSB_HOST_GSM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_gsm.c) endif() if(CONFIG_CHERRYUSB_HOST_AOA) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/aoa/usbh_aoa.c) endif() + if(CONFIG_CHERRYUSB_HOST_CDC_ACM + OR CONFIG_CHERRYUSB_HOST_CH34X + OR CONFIG_CHERRYUSB_HOST_CP210X + OR CONFIG_CHERRYUSB_HOST_FTDI + OR CONFIG_CHERRYUSB_HOST_PL2303 + OR CONFIG_CHERRYUSB_HOST_GSM + ) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/serial/usbh_serial.c) + endif() + if(CONFIG_CHERRYUSB_HOST_CDC_ECM OR CONFIG_CHERRYUSB_HOST_CDC_RNDIS OR CONFIG_CHERRYUSB_HOST_CDC_NCM OR CONFIG_CHERRYUSB_HOST_ASIX OR CONFIG_CHERRYUSB_HOST_RTL8152 - OR CONFIG_CHERRYUSB_HOST_BL616 ) if("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "idf") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/platform/idf/usbh_net.c) @@ -335,11 +348,15 @@ if(CONFIG_CHERRYUSB_HOST) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/rp2040/usb_hc_rp2040.c) endif() - if(CONFIG_TEST_USBH_CDC_ACM OR CONFIG_TEST_USBH_HID OR CONFIG_TEST_USBH_MSC) + if(CONFIG_TEST_USBH_SERIAL OR CONFIG_TEST_USBH_HID OR CONFIG_TEST_USBH_MSC) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/demo/usb_host.c) endif() endif() +if(CONFIG_CHERRYUSB_DEVICE AND CONFIG_CHERRYUSB_HOST) +list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/core/usbotg_core.c) +endif() + if(DEFINED CONFIG_CHERRYUSB_OSAL) if("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "freertos") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_freertos.c) diff --git a/components/drivers/usb/cherryusb/cherryusb_config_template.h b/components/drivers/usb/cherryusb/cherryusb_config_template.h index 1e8aab740c..9f06900528 100644 --- a/components/drivers/usb/cherryusb/cherryusb_config_template.h +++ b/components/drivers/usb/cherryusb/cherryusb_config_template.h @@ -157,7 +157,7 @@ #define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 2 #define CONFIG_USBHOST_MAX_ENDPOINTS 4 -#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_SERIAL_CLASS 4 #define CONFIG_USBHOST_MAX_HID_CLASS 4 #define CONFIG_USBHOST_MAX_MSC_CLASS 2 #define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 @@ -188,6 +188,10 @@ #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 #endif +#ifndef CONFIG_USBHOST_SERIAL_RX_SIZE +#define CONFIG_USBHOST_SERIAL_RX_SIZE 2048 +#endif + #ifndef CONFIG_USBHOST_MSC_TIMEOUT #define CONFIG_USBHOST_MSC_TIMEOUT 5000 #endif @@ -301,6 +305,7 @@ /* ---------------- MUSB Configuration ---------------- */ #define CONFIG_USB_MUSB_PIPE_NUM 8 // #define CONFIG_USB_MUSB_SUNXI +// #define CONFIG_USB_MUSB_WITHOUT_MULTIPOINT /* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. @@ -317,4 +322,7 @@ #define usb_ramaddr2phyaddr(addr) (addr) #endif +/* Enable OTG support, only support hpmicro now */ +// #define CONFIG_USB_OTG_ENABLE + #endif diff --git a/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c b/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c index ddae957148..02d9fab553 100644 --- a/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c +++ b/components/drivers/usb/cherryusb/class/aoa/usbh_aoa.c @@ -176,9 +176,6 @@ int usbh_aoa_register_hid(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *repo int usbh_aoa_send_hid_event(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *event, uint32_t event_len) { struct usb_setup_packet *setup; - int ret; - uint8_t len; - uint32_t offset; if (!aoa_class || !aoa_class->hport) { return -USB_ERR_INVAL; @@ -198,7 +195,6 @@ int usbh_aoa_send_hid_event(struct usbh_aoa *aoa_class, uint16_t id, uint8_t *ev static int usbh_aoa_connect(struct usbh_hubport *hport, uint8_t intf) { struct usb_endpoint_descriptor *ep_desc; - int ret = 0; struct usbh_aoa *aoa_class = &g_aoa_class; diff --git a/components/drivers/usb/cherryusb/class/audio/usb_audio.h b/components/drivers/usb/cherryusb/class/audio/usb_audio.h index eb518b7bcb..6c25c3de21 100644 --- a/components/drivers/usb/cherryusb/class/audio/usb_audio.h +++ b/components/drivers/usb/cherryusb/class/audio/usb_audio.h @@ -88,18 +88,6 @@ #define AUDIO_ENDPOINT_UNDEFINED 0x00U #define AUDIO_ENDPOINT_GENERAL 0x01U -/* Feature Unit Control Bits */ -#define AUDIO_CONTROL_MUTE 0x0001 -#define AUDIO_CONTROL_VOLUME 0x0002 -#define AUDIO_CONTROL_BASS 0x0004 -#define AUDIO_CONTROL_MID 0x0008 -#define AUDIO_CONTROL_TREBLE 0x0010 -#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020 -#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040 -#define AUDIO_CONTROL_DEALY 0x0080 -#define AUDIO_CONTROL_BASS_BOOST 0x0100 -#define AUDIO_CONTROL_LOUDNESS 0x0200 - /* Encoder Type Codes */ #define AUDIO_ENCODER_UNDEF 0x00 #define AUDIO_ENCODER_OTHER 0x01 @@ -245,22 +233,34 @@ #define AUDIO_FU_CONTROL_OVERFLOW 0x0f #define AUDIO_FU_CONTROL_LATENCY 0x10 -#define AUDIO_V2_FU_CONTROL_UNDEF 0x00 -#define AUDIO_V2_FU_CONTROL_MUTE (0x03 << 0) -#define AUDIO_V2_FU_CONTROL_VOLUME (0x03 << 2) -#define AUDIO_V2_FU_CONTROL_BASS (0x03 << 4) -#define AUDIO_V2_FU_CONTROL_MID (0x03 << 6) -#define AUDIO_V2_FU_CONTROL_TREBLE (0x03 << 8) -#define AUDIO_V2_FU_CONTROL_EQUALIZER (0x03 << 10) -#define AUDIO_V2_FU_CONTROL_AGC (0x03 << 12) -#define AUDIO_V2_FU_CONTROL_DELAY (0x03 << 14) -#define AUDIO_V2_FU_CONTROL_BASS_BOOST (0x03 << 16) -#define AUDIO_V2_FU_CONTROL_LOUDNESS (0x03 << 18) -#define AUDIO_V2_FU_CONTROL_INP_GAIN (0x03 << 20) -#define AUDIO_V2_FU_CONTROL_INP_GAIN_PAD (0x03 << 22) -#define AUDIO_V2_FU_CONTROL_PHASE_INVERT (0x03 << 24) -#define AUDIO_V2_FU_CONTROL_UNDERFLOW (0x03 << 26) -#define AUDIO_V2_FU_CONTROL_OVERFLOW (0x03 << 28) +/* Feature Unit Control Bits */ +#define AUDIO_CONTROL_MUTE 0x0001 +#define AUDIO_CONTROL_VOLUME 0x0002 +#define AUDIO_CONTROL_BASS 0x0004 +#define AUDIO_CONTROL_MID 0x0008 +#define AUDIO_CONTROL_TREBLE 0x0010 +#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020 +#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040 +#define AUDIO_CONTROL_DEALY 0x0080 +#define AUDIO_CONTROL_BASS_BOOST 0x0100 +#define AUDIO_CONTROL_LOUDNESS 0x0200 + +#define AUDIO_V2_CONTROL_UNDEF 0x00 +#define AUDIO_V2_CONTROL_MUTE (0x03 << 0) +#define AUDIO_V2_CONTROL_VOLUME (0x03 << 2) +#define AUDIO_V2_CONTROL_BASS (0x03 << 4) +#define AUDIO_V2_CONTROL_MID (0x03 << 6) +#define AUDIO_V2_CONTROL_TREBLE (0x03 << 8) +#define AUDIO_V2_CONTROL_EQUALIZER (0x03 << 10) +#define AUDIO_V2_CONTROL_AGC (0x03 << 12) +#define AUDIO_V2_CONTROL_DELAY (0x03 << 14) +#define AUDIO_V2_CONTROL_BASS_BOOST (0x03 << 16) +#define AUDIO_V2_CONTROL_LOUDNESS (0x03 << 18) +#define AUDIO_V2_CONTROL_INP_GAIN (0x03 << 20) +#define AUDIO_V2_CONTROL_INP_GAIN_PAD (0x03 << 22) +#define AUDIO_V2_CONTROL_PHASE_INVERT (0x03 << 24) +#define AUDIO_V2_CONTROL_UNDERFLOW (0x03 << 26) +#define AUDIO_V2_CONTROL_OVERFLOW (0x03 << 28) /* Parametric Equalizer Section Effect Unit Control Selectors */ #define AUDIO_PE_CONTROL_UNDEF 0x00 @@ -605,7 +605,7 @@ struct audio_cs_if_ac_header_descriptor { uint8_t baInterfaceNr[]; } __PACKED; -#define AUDIO_SIZEOF_AC_HEADER_DESC(n) (8 + n) +#define AUDIO_SIZEOF_AC_HEADER_DESC(bInCollection) (8 + (bInCollection)) struct audio_cs_if_ac_input_terminal_descriptor { uint8_t bLength; @@ -646,7 +646,7 @@ struct audio_cs_if_ac_feature_unit_descriptor { uint8_t iFeature; } __PACKED; -#define AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(ch, n) (7 + (ch + 1) * n) +#define AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(bNrChannels, bControlSize) (7 + ((bNrChannels) + 1) * (bControlSize)) struct audio_cs_if_ac_selector_unit_descriptor { uint8_t bLength; @@ -658,7 +658,7 @@ struct audio_cs_if_ac_selector_unit_descriptor { uint8_t iSelector; } __PACKED; -#define AUDIO_SIZEOF_AC_SELECTOR_UNIT_DESC(n) (6 + n) +#define AUDIO_SIZEOF_AC_SELECTOR_UNIT_DESC(bNrInPins) (6 + (bNrInPins)) struct audio_cs_if_as_general_descriptor { uint8_t bLength; @@ -683,7 +683,7 @@ struct audio_cs_if_as_format_type_descriptor { uint8_t tSamFreq[3]; } __PACKED; -#define AUDIO_SIZEOF_FORMAT_TYPE_DESC(n) (8 + 3 * n) +#define AUDIO_SIZEOF_FORMAT_TYPE_DESC(bSamFreqType) (8 + 3 * (bSamFreqType)) struct audio_ep_descriptor { uint8_t bLength; @@ -738,7 +738,7 @@ struct audio_cs_ep_ep_general_descriptor { PP_NARG(__VA_ARGS__), /* bInCollection */ \ __VA_ARGS__ /* baInterfaceNr */ -#define AUDIO_AC_DESCRIPTOR_INIT_LEN(n) (0x08 + 0x09 + 0x08 + n) +#define AUDIO_AC_DESCRIPTOR_LEN(bInCollection) (0x08 + 0x09 + 0x08 + bInCollection) #define AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bNrChannels, wChannelConfig) \ 0x0C, /* bLength */ \ @@ -880,8 +880,8 @@ struct audio_cs_ep_ep_general_descriptor { 0x03, /* bRefresh, 8ms */ \ 0x00 /* bSynchAddress */ -#define AUDIO_AS_DESCRIPTOR_INIT_LEN(n) (0x09 + 0x09 + 0x07 + 0x08 + 3 * n + 0x09 + 0x07) -#define AUDIO_AS_FEEDBACK_DESCRIPTOR_INIT_LEN(n) (0x09 + 0x09 + 0x07 + 0x08 + 3 * n + 0x09 + 0x07 + 0x09) +#define AUDIO_AS_DESCRIPTOR_LEN(bSamFreqType) (0x09 + 0x09 + 0x07 + 0x08 + 3 * (bSamFreqType) + 0x09 + 0x07) +#define AUDIO_AS_FEEDBACK_DESCRIPTOR_LEN(bSamFreqType) (0x09 + 0x09 + 0x07 + 0x08 + 3 * (bSamFreqType) + 0x09 + 0x07 + 0x09) #define AUDIO_AS_ALTSETTING_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval, ...) \ 0x09, /* bLength */ \ @@ -924,9 +924,9 @@ struct audio_cs_ep_ep_general_descriptor { 0x00, /* wLockDelay */ \ 0x00 -#define AUDIO_AS_ALTSETTING_DESCRIPTOR_INIT_LEN(n) (0x09 + 0x07 + 0x08 + 3 * n + 0x09 + 0x07) +#define AUDIO_AS_ALTSETTING_DESCRIPTOR_LEN(bSamFreqType) (0x09 + 0x07 + 0x08 + 3 * (bSamFreqType) + 0x09 + 0x07) -#define AUDIO_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ +#define AUDIO_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ bInterfaceNumber, /* bInterfaceNumber */ \ @@ -937,19 +937,6 @@ struct audio_cs_ep_ep_general_descriptor { AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ 0x00 /* iInterface */ -#define AUDIO_MS_STANDARD_DESCRIPTOR_INIT(bInterfaceNumber, bNumEndpoints) \ - 0x09, /* bLength */ \ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ - bInterfaceNumber, /* bInterfaceNumber */ \ - 0x00, /* bAlternateSetting */ \ - bNumEndpoints, /* bNumEndpoints */ \ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ - AUDIO_SUBCLASS_MIDISTREAMING, /* bInterfaceSubClass */ \ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ - 0x00 /* iInterface */ - -#define AUDIO_MS_STANDARD_DESCRIPTOR_INIT_LEN 0x09 - struct audio_v2_channel_cluster_descriptor { uint8_t bNrChannels; uint32_t bmChannelConfig; @@ -993,7 +980,7 @@ struct audio_v2_cs_if_ac_clock_selector_descriptor { uint8_t iClockSelector; } __PACKED; -#define AUDIO_SIZEOF_AC_CLOCK_SELECTOR_DESC(n) (7 + n) +#define AUDIO_SIZEOF_AC_CLOCK_SELECTOR_DESC(bNrInPins) (7 + (bNrInPins)) struct audio_v2_cs_if_ac_clock_multiplier_descriptor { uint8_t bLength; @@ -1005,7 +992,7 @@ struct audio_v2_cs_if_ac_clock_multiplier_descriptor { uint8_t iClockMultiplier; } __PACKED; -#define AUDIO_SIZEOF_AC_CLOCK_MULTIPLIER_DESC() (7) +#define AUDIO_SIZEOF_AC_CLOCK_MULTIPLIER_DESC (7) struct audio_v2_cs_if_ac_input_terminal_descriptor { uint8_t bLength; @@ -1049,7 +1036,7 @@ struct audio_v2_cs_if_ac_feature_unit_descriptor { uint8_t iFeature; } __PACKED; -#define AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(ch) (6 + (ch + 1) * 4) +#define AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(bNrChannels) (6 + ((bNrChannels) + 1) * 4) struct audio_v2_cs_if_as_general_descriptor { uint8_t bLength; @@ -1124,7 +1111,7 @@ struct audio_v2_control_range3_param_block { WBVAL(wTotalLength), /* wTotalLength */ \ bmControls /* bmControls */ \ -#define AUDIO_V2_AC_DESCRIPTOR_INIT_LEN (0x08 + 0x09 + 0x09) +#define AUDIO_V2_AC_DESCRIPTOR_LEN (0x08 + 0x09 + 0x09) #define AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(bClockID, bmAttributes, bmControls) \ 0x08, /* bLength */ \ @@ -1262,7 +1249,7 @@ struct audio_v2_control_range3_param_block { 0x00, /* wLockDelay */ \ 0x00 -#define AUDIO_V2_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ +#define AUDIO_V2_AS_ALTSETTING0_DESCRIPTOR_INIT(bInterfaceNumber) \ 0x09, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ bInterfaceNumber, /* bInterfaceNumber */ \ @@ -1331,9 +1318,10 @@ struct audio_v2_control_range3_param_block { // clang-format on -#define AUDIO_V2_AS_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08) -#define AUDIO_V2_AS_ALTSETTING_DESCRIPTOR_INIT_LEN (0x09 + 0x10 + 0x06 + 0x07 + 0x08) -#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07) +#define AUDIO_V2_AS_DESCRIPTOR_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_ALTSETTING0_DESCRIPTOR_LEN (0x09) +#define AUDIO_V2_AS_ALTSETTING_DESCRIPTOR_LEN (0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07) #define AUDIO_SAMPLE_FREQ_NUM(num) (uint8_t)(num), (uint8_t)((num >> 8)) #define AUDIO_SAMPLE_FREQ_3B(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) diff --git a/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h b/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h index d1546eec57..6a8e807d3c 100644 --- a/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h +++ b/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h @@ -217,12 +217,12 @@ #define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ #define CDC_SERIAL_STATE_BREAK_Pos (2) #define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos) -#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */ -#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1) -#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos) -#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */ -#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0) -#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos) +#define CDC_SERIAL_STATE_DSR (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_DSR_Pos (1) +#define CDC_SERIAL_STATE_DSR_Msk (1 << CDC_SERIAL_STATE_DSR_Pos) +#define CDC_SERIAL_STATE_DCD (1 << 0) /* state of receiver carrier */ +#define CDC_SERIAL_STATE_DCD_Pos (0) +#define CDC_SERIAL_STATE_DCD_Msk (1 << CDC_SERIAL_STATE_DCD_Pos) #define CDC_ECM_XMIT_OK (1 << 0) #define CDC_ECM_RVC_OK (1 << 1) @@ -551,10 +551,9 @@ struct cdc_ncm_ndp16 { #define DBVAL_BE(x) ((x >> 24) & 0xFF), ((x >> 16) & 0xFF), ((x >> 8) & 0xFF), (x & 0xFF) /*Length of template descriptor: 71 bytes*/ -#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 7 + 7) +#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 7 + 7) // clang-format off -#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ -eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ +#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ /* Interface Associate */ \ 0x08, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ @@ -587,10 +586,10 @@ eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ str_idx, /* Device's MAC string index */\ - DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ - WBVAL(wMaxSegmentSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ - WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ - bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + DBVAL_BE(0x00000000), /* Ethernet statistics (bitmap) */\ + WBVAL(1514), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(0), /* wNumberMCFilters: the number of multicast filters */ \ + 0, /* bNumberPowerFilters: the number of wakeup power filters */ \ 0x07, /* bLength */ \ USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ int_ep, /* bEndpointAddress */ \ @@ -621,10 +620,9 @@ eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) // clang-format on /*Length of template descriptor: 77 bytes*/ -#define CDC_NCM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 7 + 7) +#define CDC_NCM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 7 + 7) // clang-format off -#define CDC_NCM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ -eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ +#define CDC_NCM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ /* Interface Associate */ \ 0x08, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ @@ -657,10 +655,10 @@ eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ str_idx, /* Device's MAC string index */\ - DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ - WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ - WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ - bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + DBVAL_BE(0x00000000), /* Ethernet statistics (bitmap) */\ + WBVAL(1514), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(0), /* wNumberMCFilters: the number of multicast filters */ \ + 0, /* bNumberPowerFilters: the number of wakeup power filters */ \ 0x06, \ CDC_CS_INTERFACE, \ CDC_FUNC_DESC_NCM, \ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c deleted file mode 100644 index 2fc54eed6b..0000000000 --- a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2022, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "usbh_core.h" -#include "usbh_cdc_acm.h" - -#undef USB_DBG_TAG -#define USB_DBG_TAG "usbh_cdc_acm" -#include "usb_log.h" - -#define DEV_FORMAT "/dev/ttyACM%d" - -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_acm_buf[CONFIG_USBHOST_MAX_CDC_ACM_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; - -static struct usbh_cdc_acm g_cdc_acm_class[CONFIG_USBHOST_MAX_CDC_ACM_CLASS]; -static uint32_t g_devinuse = 0; - -static struct usbh_cdc_acm *usbh_cdc_acm_class_alloc(void) -{ - uint8_t devno; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_CDC_ACM_CLASS; devno++) { - if ((g_devinuse & (1U << devno)) == 0) { - g_devinuse |= (1U << devno); - memset(&g_cdc_acm_class[devno], 0, sizeof(struct usbh_cdc_acm)); - g_cdc_acm_class[devno].minor = devno; - return &g_cdc_acm_class[devno]; - } - } - return NULL; -} - -static void usbh_cdc_acm_class_free(struct usbh_cdc_acm *cdc_acm_class) -{ - uint8_t devno = cdc_acm_class->minor; - - if (devno < 32) { - g_devinuse &= ~(1U << devno); - } - memset(cdc_acm_class, 0, sizeof(struct usbh_cdc_acm)); -} - -int usbh_cdc_acm_set_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding) -{ - struct usb_setup_packet *setup; - - if (!cdc_acm_class || !cdc_acm_class->hport) { - return -USB_ERR_INVAL; - } - setup = cdc_acm_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CDC_REQUEST_SET_LINE_CODING; - setup->wValue = 0; - setup->wIndex = cdc_acm_class->intf; - setup->wLength = 7; - - memcpy(g_cdc_acm_buf[cdc_acm_class->minor], line_coding, sizeof(struct cdc_line_coding)); - - return usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf[cdc_acm_class->minor]); -} - -int usbh_cdc_acm_get_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding) -{ - struct usb_setup_packet *setup; - int ret; - - if (!cdc_acm_class || !cdc_acm_class->hport) { - return -USB_ERR_INVAL; - } - setup = cdc_acm_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CDC_REQUEST_GET_LINE_CODING; - setup->wValue = 0; - setup->wIndex = cdc_acm_class->intf; - setup->wLength = 7; - - ret = usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf[cdc_acm_class->minor]); - if (ret < 0) { - return ret; - } - memcpy(line_coding, g_cdc_acm_buf[cdc_acm_class->minor], sizeof(struct cdc_line_coding)); - return ret; -} - -int usbh_cdc_acm_set_line_state(struct usbh_cdc_acm *cdc_acm_class, bool dtr, bool rts) -{ - struct usb_setup_packet *setup; - - if (!cdc_acm_class || !cdc_acm_class->hport) { - return -USB_ERR_INVAL; - } - setup = cdc_acm_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; - setup->wValue = (dtr << 0) | (rts << 1); - setup->wIndex = cdc_acm_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(cdc_acm_class->hport, setup, NULL); -} - -static int usbh_cdc_acm_connect(struct usbh_hubport *hport, uint8_t intf) -{ - struct usb_endpoint_descriptor *ep_desc; - int ret = 0; - - struct usbh_cdc_acm *cdc_acm_class = usbh_cdc_acm_class_alloc(); - if (cdc_acm_class == NULL) { - USB_LOG_ERR("Fail to alloc cdc_acm_class\r\n"); - return -USB_ERR_NOMEM; - } - - cdc_acm_class->hport = hport; - cdc_acm_class->intf = intf; - - hport->config.intf[intf].priv = cdc_acm_class; - hport->config.intf[intf + 1].priv = NULL; - -#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY - ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; - USBH_EP_INIT(cdc_acm_class->intin, ep_desc); -#endif - for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { - ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; - - if (ep_desc->bEndpointAddress & 0x80) { - USBH_EP_INIT(cdc_acm_class->bulkin, ep_desc); - } else { - USBH_EP_INIT(cdc_acm_class->bulkout, ep_desc); - } - } - - snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, cdc_acm_class->minor); - - USB_LOG_INFO("Register CDC ACM Class:%s\r\n", hport->config.intf[intf].devname); - -#if 0 - USB_LOG_INFO("Test cdc acm rx and tx and rx for 5 times, baudrate is 115200\r\n"); - - struct cdc_line_coding linecoding; - uint8_t count = 5; - - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_cdc_acm_set_line_coding(cdc_acm_class, &linecoding); - usbh_cdc_acm_set_line_state(cdc_acm_class, true, false); - - memset(g_cdc_acm_buf, 'a', sizeof(g_cdc_acm_buf)); - ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, g_cdc_acm_buf, sizeof(g_cdc_acm_buf), 0xfffffff); - USB_LOG_RAW("out ret:%d\r\n", ret); - while (count--) { - ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, g_cdc_acm_buf, sizeof(g_cdc_acm_buf), 0xfffffff); - USB_LOG_RAW("in ret:%d\r\n", ret); - if (ret > 0) { - for (uint32_t i = 0; i < ret; i++) { - USB_LOG_RAW("%02x ", g_cdc_acm_buf[i]); - } - } - USB_LOG_RAW("\r\n"); - } -#endif - - usbh_cdc_acm_run(cdc_acm_class); - return ret; -} - -static int usbh_cdc_acm_disconnect(struct usbh_hubport *hport, uint8_t intf) -{ - int ret = 0; - - struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)hport->config.intf[intf].priv; - - if (cdc_acm_class) { - if (cdc_acm_class->bulkin) { - usbh_kill_urb(&cdc_acm_class->bulkin_urb); - } - - if (cdc_acm_class->bulkout) { - usbh_kill_urb(&cdc_acm_class->bulkout_urb); - } - -#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY - if (cdc_acm_class->intin) { - usbh_kill_urb(&cdc_acm_class->intin_urb); - } -#endif - - if (hport->config.intf[intf].devname[0] != '\0') { - usb_osal_thread_schedule_other(); - USB_LOG_INFO("Unregister CDC ACM Class:%s\r\n", hport->config.intf[intf].devname); - usbh_cdc_acm_stop(cdc_acm_class); - } - - usbh_cdc_acm_class_free(cdc_acm_class); - } - - return ret; -} - -int usbh_cdc_acm_bulk_in_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &cdc_acm_class->bulkin_urb; - - usbh_bulk_urb_fill(urb, cdc_acm_class->hport, cdc_acm_class->bulkin, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -int usbh_cdc_acm_bulk_out_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &cdc_acm_class->bulkout_urb; - - usbh_bulk_urb_fill(urb, cdc_acm_class->hport, cdc_acm_class->bulkout, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -static int usbh_cdc_data_connect(struct usbh_hubport *hport, uint8_t intf) -{ - (void)hport; - (void)intf; - return 0; -} - -static int usbh_cdc_data_disconnect(struct usbh_hubport *hport, uint8_t intf) -{ - (void)hport; - (void)intf; - return 0; -} - -__WEAK void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) -{ - (void)cdc_acm_class; -} - -__WEAK void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) -{ - (void)cdc_acm_class; -} - -const struct usbh_class_driver cdc_acm_class_driver = { - .driver_name = "cdc_acm", - .connect = usbh_cdc_acm_connect, - .disconnect = usbh_cdc_acm_disconnect -}; - -const struct usbh_class_driver cdc_data_class_driver = { - .driver_name = "cdc_data", - .connect = usbh_cdc_data_connect, - .disconnect = usbh_cdc_data_disconnect -}; - -CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_class_info = { - .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, - .bInterfaceClass = USB_DEVICE_CLASS_CDC, - .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, - .bInterfaceProtocol = 0x00, - .id_table = NULL, - .class_driver = &cdc_acm_class_driver -}; - -CLASS_INFO_DEFINE const struct usbh_class_info cdc_data_class_info = { - .match_flags = USB_CLASS_MATCH_INTF_CLASS, - .bInterfaceClass = USB_DEVICE_CLASS_CDC_DATA, - .bInterfaceSubClass = 0x00, - .bInterfaceProtocol = 0x00, - .id_table = NULL, - .class_driver = &cdc_data_class_driver -}; diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h deleted file mode 100644 index 80800bf9f2..0000000000 --- a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2022, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef USBH_CDC_ACM_H -#define USBH_CDC_ACM_H - -#include "usb_cdc.h" - -struct usbh_cdc_acm { - struct usbh_hubport *hport; - struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ - struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ -#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY - struct usb_endpoint_descriptor *intin; /* INTR IN endpoint (optional) */ -#endif - struct usbh_urb bulkout_urb; - struct usbh_urb bulkin_urb; -#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY - struct usbh_urb intin_urb; -#endif - - struct cdc_line_coding linecoding; - - uint8_t intf; - uint8_t minor; - - void *user_data; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -int usbh_cdc_acm_set_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding); -int usbh_cdc_acm_get_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding); -int usbh_cdc_acm_set_line_state(struct usbh_cdc_acm *cdc_acm_class, bool dtr, bool rts); - -int usbh_cdc_acm_bulk_in_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); -int usbh_cdc_acm_bulk_out_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); - -void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class); -void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class); - -#ifdef __cplusplus -} -#endif - -#endif /* USBH_CDC_ACM_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c index 73eaa430e9..0c64ff11bd 100644 --- a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c @@ -306,16 +306,6 @@ int usbh_cdc_ecm_eth_output(uint32_t buflen) return usbh_submit_urb(&g_cdc_ecm_class.bulkout_urb); } -__WEAK void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class) -{ - (void)cdc_ecm_class; -} - -__WEAK void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class) -{ - (void)cdc_ecm_class; -} - const struct usbh_class_driver cdc_ecm_class_driver = { .driver_name = "cdc_ecm", .connect = usbh_cdc_ecm_connect, diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c index 2ee6e4cece..fa2ccc0cc8 100644 --- a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c @@ -386,16 +386,6 @@ int usbh_cdc_ncm_eth_output(uint32_t buflen) return usbh_submit_urb(&g_cdc_ncm_class.bulkout_urb); } -__WEAK void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class) -{ - (void)cdc_ncm_class; -} - -__WEAK void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class) -{ - (void)cdc_ncm_class; -} - const struct usbh_class_driver cdc_ncm_class_driver = { .driver_name = "cdc_ncm", .connect = usbh_cdc_ncm_connect, diff --git a/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c b/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c index a870aee3a9..2da382884b 100644 --- a/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c +++ b/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c @@ -106,7 +106,6 @@ static void dfu_request_upload(struct usb_setup_packet *setup, uint8_t **data, u { struct usb_setup_packet *req = setup; uint32_t addr; - uint8_t *phaddr; /* Data setup request */ if (req->wLength > 0U) { if ((g_usbd_dfu.dev_state == DFU_STATE_DFU_IDLE) || (g_usbd_dfu.dev_state == DFU_STATE_DFU_UPLOAD_IDLE)) { @@ -143,7 +142,7 @@ static void dfu_request_upload(struct usb_setup_packet *setup, uint8_t **data, u addr = ((g_usbd_dfu.wblock_num - 2U) * USBD_DFU_XFER_SIZE) + g_usbd_dfu.data_ptr; /* Return the physical address where data are stored */ - phaddr = dfu_read_flash((uint8_t *)addr, g_usbd_dfu.buffer.d8, g_usbd_dfu.wlength); + dfu_read_flash((uint8_t *)addr, g_usbd_dfu.buffer.d8, g_usbd_dfu.wlength); /* Send the status data over EP0 */ memcpy(*data, g_usbd_dfu.buffer.d8, g_usbd_dfu.wlength); diff --git a/components/drivers/usb/cherryusb/class/gamepad/usb_gamepad.h b/components/drivers/usb/cherryusb/class/gamepad/usb_gamepad.h new file mode 100644 index 0000000000..28e2e6465d --- /dev/null +++ b/components/drivers/usb/cherryusb/class/gamepad/usb_gamepad.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_GAMEPAD_H +#define USB_GAMEPAD_H + +#include "usb_hid.h" + +/* + * GAMEPAD BUTTON LAYOUT + * + * ____________________________ __ + * / [__L2__] [__R2__] \ | + * / [__ L1 __] [__ R1 __] \ | Triggers + * __/________________________________\__ __| + * / _ \ | + * / /\ __ (B4) \ | + * / || __ |A1| __ _ _ \ | Main Pad + * | <===DP===> |S1| |S2| (B3) -|- (B2)| | + * \ || ¯¯ ¯¯ _ / | + * /\ \/ / \ / \ (B1) /\ __| + * / \________ | LS | ____ | RS | _______/ \ | + * | / \ \___/ / \ \___/ / \ | | Sticks + * | / \_____/ \_____/ \ | __| + * | / L3 R3 \ | + * \_____/ \_____/ + * + * |________|______| |______|___________| + * D-Pad Left Right Face + * Stick Stick Buttons + * + * Extended: A2=Touchpad/Capture A3=Mute L4/R4=Paddles + */ + +// W3C Gamepad API standard button order +// Bit position = W3C button index (trivial conversion: 1 << index) +// +// Gamepad XInput Switch PS3/4/5 DInput +// ------ ------ ------ ------- ------ + +// Face buttons (right cluster) +#define USB_GAMEPAD_BUTTON_B1 (1 << 0) // A B Cross 2 +#define USB_GAMEPAD_BUTTON_B2 (1 << 1) // B A Circle 3 +#define USB_GAMEPAD_BUTTON_B3 (1 << 2) // X Y Square 1 +#define USB_GAMEPAD_BUTTON_B4 (1 << 3) // Y X Triangle 4 + +// Shoulder buttons +#define USB_GAMEPAD_BUTTON_L1 (1 << 4) // LB L L1 5 +#define USB_GAMEPAD_BUTTON_R1 (1 << 5) // RB R R1 6 +#define USB_GAMEPAD_BUTTON_L2 (1 << 6) // LT ZL L2 7 +#define USB_GAMEPAD_BUTTON_R2 (1 << 7) // RT ZR R2 8 + +// Center cluster +#define USB_GAMEPAD_BUTTON_S1 (1 << 8) // Back - Select 9 +#define USB_GAMEPAD_BUTTON_S2 (1 << 9) // Start + Start 10 + +// Stick clicks +#define USB_GAMEPAD_BUTTON_L3 (1 << 10) // LS LS L3 11 +#define USB_GAMEPAD_BUTTON_R3 (1 << 11) // RS RS R3 12 + +// D-pad +#define USB_GAMEPAD_BUTTON_DU (1 << 12) // D-Up D-Up D-Up Hat +#define USB_GAMEPAD_BUTTON_DD (1 << 13) // D-Down D-Down D-Down Hat +#define USB_GAMEPAD_BUTTON_DL (1 << 14) // D-Left D-Left D-Left Hat +#define USB_GAMEPAD_BUTTON_DR (1 << 15) // D-Right D-Right D-Right Hat + +// Auxiliary +#define USB_GAMEPAD_BUTTON_A1 (1 << 16) // Guide Home PS 13 +#define USB_GAMEPAD_BUTTON_A2 (1 << 17) // - Capture Touchpad 14 +#define USB_GAMEPAD_BUTTON_A3 (1 << 18) // - - Mute - +#define USB_GAMEPAD_BUTTON_A4 (1 << 19) // - - - - + +// Paddles (extended) +#define USB_GAMEPAD_BUTTON_L4 (1 << 20) // P1 - - - +#define USB_GAMEPAD_BUTTON_R4 (1 << 21) // P2 - - - + +#define XINPUT_VID 0x045E // Microsoft +#define XINPUT_PID 0x028E // Xbox 360 Controller +#define XINPUT_BCD_DEVICE 0x0114 // v1.14 + +/* XInput (Xbox 360) USB */ + +// XInput Interface Class/Subclass/Protocol +#define XINPUT_INTERFACE_CLASS 0xFF +#define XINPUT_INTERFACE_SUBCLASS 0x5D +#define XINPUT_INTERFACE_PROTOCOL 0x01 + +#define XINPUT_BUTTON_MASK_UP (1U << 0) +#define XINPUT_BUTTON_MASK_DOWN (1U << 1) +#define XINPUT_BUTTON_MASK_LEFT (1U << 2) +#define XINPUT_BUTTON_MASK_RIGHT (1U << 3) +#define XINPUT_BUTTON_MASK_START (1U << 4) +#define XINPUT_BUTTON_MASK_BACK (1U << 5) +#define XINPUT_BUTTON_MASK_L3 (1U << 6) +#define XINPUT_BUTTON_MASK_R3 (1U << 7) +#define XINPUT_BUTTON_MASK_LB (1U << 8) +#define XINPUT_BUTTON_MASK_RB (1U << 9) +#define XINPUT_BUTTON_MASK_GUIDE (1U << 10) +//#define XINPUT_BUTTON_MASK_UNUSED (1U << 11) +#define XINPUT_BUTTON_MASK_A (1U << 12) +#define XINPUT_BUTTON_MASK_B (1U << 13) +#define XINPUT_BUTTON_MASK_X (1U << 14) +#define XINPUT_BUTTON_MASK_Y (1U << 15) + +// LED patterns for report_id 0x01 +#define XINPUT_LED_OFF 0x00 +#define XINPUT_LED_BLINK 0x01 +#define XINPUT_LED_FLASH_1 0x02 +#define XINPUT_LED_FLASH_2 0x03 +#define XINPUT_LED_FLASH_3 0x04 +#define XINPUT_LED_FLASH_4 0x05 +#define XINPUT_LED_ON_1 0x06 +#define XINPUT_LED_ON_2 0x07 +#define XINPUT_LED_ON_3 0x08 +#define XINPUT_LED_ON_4 0x09 +#define XINPUT_LED_ROTATE 0x0A +#define XINPUT_LED_BLINK_SLOW 0x0B +#define XINPUT_LED_BLINK_SLOW_1 0x0C +#define XINPUT_LED_BLINK_SLOW_2 0x0D + +struct xinput_in_report { + uint8_t report_id; /* Always 0x00 */ + uint8_t report_size; /* Always 0x14 (20) */ + uint16_t buttons; /* DPAD, Start, Back, L3, R3, LB, RB, Guide, A, B, X, Y */ + uint8_t lt; /* Left trigger (0-255) */ + uint8_t rt; /* Right trigger (0-255) */ + int16_t lx; /* Left stick X (-32768 to 32767) */ + int16_t ly; /* Left stick Y (-32768 to 32767) */ + int16_t rx; /* Right stick X (-32768 to 32767) */ + int16_t ry; /* Right stick Y (-32768 to 32767) */ + uint8_t reserved[6]; /* Reserved/padding */ +} __PACKED; + +struct xinput_out_report { + uint8_t report_id; // 0x00 = rumble, 0x01 = LED + uint8_t report_size; // 0x08 + uint8_t led; // LED pattern (0x00 for rumble) + uint8_t rumble_l; // Left motor (large, 0-255) + uint8_t rumble_r; // Right motor (small, 0-255) + uint8_t reserved[3]; // Padding +} __PACKED; + +// clang-format off +#define XINPUT_DESCRIPTOR_LEN (9 + 16 + 7 + 7) + +#define XINPUT_DESCRIPTOR_INIT(bInterfaceNumber, out_ep, in_ep) \ + USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, 0x00, 0x02, 0xff, 0x5d, 0x01, 0x00), /* XInput proprietary descriptor (0x21) */ \ + 16, 0x21, 0x00, 0x01, 0x01, 0x24, in_ep, 0x14, 0x03, 0x00, 0x03, 0x13, out_ep, 0x00, 0x03, 0x00, \ + USB_ENDPOINT_DESCRIPTOR_INIT(in_ep, 0x03, 32, 0x01), \ + USB_ENDPOINT_DESCRIPTOR_INIT(out_ep, 0x03, 32, 0x08) +// clang-format on + +#define SWITCH_VID 0x0F0D // 0x057E Nintendo Pro Controller +#define SWITCH_PID 0x0092 // 0x2009 +#define SWITCH_BCD_DEVICE 0x0100 // v1.00 + +// Button masks (16-bit) +#define SWITCH_MASK_Y (1U << 0) +#define SWITCH_MASK_B (1U << 1) +#define SWITCH_MASK_A (1U << 2) +#define SWITCH_MASK_X (1U << 3) +#define SWITCH_MASK_L (1U << 4) +#define SWITCH_MASK_R (1U << 5) +#define SWITCH_MASK_ZL (1U << 6) +#define SWITCH_MASK_ZR (1U << 7) +#define SWITCH_MASK_MINUS (1U << 8) +#define SWITCH_MASK_PLUS (1U << 9) +#define SWITCH_MASK_L3 (1U << 10) +#define SWITCH_MASK_R3 (1U << 11) +#define SWITCH_MASK_HOME (1U << 12) +#define SWITCH_MASK_CAPTURE (1U << 13) + +// D-pad / Hat switch values +#define SWITCH_HAT_UP 0x00 +#define SWITCH_HAT_UP_RIGHT 0x01 +#define SWITCH_HAT_RIGHT 0x02 +#define SWITCH_HAT_DOWN_RIGHT 0x03 +#define SWITCH_HAT_DOWN 0x04 +#define SWITCH_HAT_DOWN_LEFT 0x05 +#define SWITCH_HAT_LEFT 0x06 +#define SWITCH_HAT_UP_LEFT 0x07 +#define SWITCH_HAT_CENTER 0x08 + +// Analog stick range +#define SWITCH_JOYSTICK_MIN 0x00 +#define SWITCH_JOYSTICK_MID 0x80 +#define SWITCH_JOYSTICK_MAX 0xFF + +struct switch_in_report { + uint16_t buttons; // 16 button bits + uint8_t hat; // D-pad (hat switch, 0-8) + uint8_t lx; // Left stick X (0-255, 128 = center) + uint8_t ly; // Left stick Y (0-255, 128 = center) + uint8_t rx; // Right stick X (0-255, 128 = center) + uint8_t ry; // Right stick Y (0-255, 128 = center) + uint8_t vendor; // Vendor-specific byte +} __PACKED; + +struct switch_out_report { + uint8_t data[8]; // Vendor-specific rumble data +} __PACKED; + +#define HID_SWITCH_REPORT_DESC_SIZE 86 + +// clang-format off +#define SWITCH_DESCRIPTOR_LEN HID_CUSTOM_INOUT_DESCRIPTOR_LEN + +#define SWITCH_DESCRIPTOR_INIT(bInterfaceNumber, out_ep, in_ep) \ + HID_CUSTOM_INOUT_DESCRIPTOR_INIT(bInterfaceNumber, 0x00, HID_SWITCH_REPORT_DESC_SIZE, out_ep, in_ep, 64, 0x01) +// clang-format on + +struct usb_gamepad_report { + uint32_t buttons; + uint8_t lt; + uint8_t rt; + uint8_t lx; + uint8_t ly; + uint8_t rx; + uint8_t ry; +}; + +#endif /* USB_GAMEPAD_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.c b/components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.c new file mode 100644 index 0000000000..8ffbfda8a3 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" +#include "usbd_gamepad.h" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t gamepad_report_buffer[64]; + +static int xinput_vendor_class_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + struct xinput_in_report xinput_report; + + memset(&xinput_report, 0, sizeof(xinput_report)); + xinput_report.report_size = 20; + + memcpy(*data, &xinput_report, sizeof(xinput_report)); + *len = sizeof(xinput_report); + return 0; +} + +int usbd_gamepad_xinput_send_report(uint8_t ep, struct usb_gamepad_report *report) +{ + struct xinput_in_report *xinput_report; + + xinput_report = (struct xinput_in_report *)gamepad_report_buffer; + memset(xinput_report, 0, sizeof(xinput_report)); + xinput_report->report_size = 20; + + if (report->buttons & USB_GAMEPAD_BUTTON_DU) + xinput_report->buttons |= XINPUT_BUTTON_MASK_UP; + if (report->buttons & USB_GAMEPAD_BUTTON_DD) + xinput_report->buttons |= XINPUT_BUTTON_MASK_DOWN; + if (report->buttons & USB_GAMEPAD_BUTTON_DL) + xinput_report->buttons |= XINPUT_BUTTON_MASK_LEFT; + if (report->buttons & USB_GAMEPAD_BUTTON_DR) + xinput_report->buttons |= XINPUT_BUTTON_MASK_RIGHT; + if (report->buttons & USB_GAMEPAD_BUTTON_S2) + xinput_report->buttons |= XINPUT_BUTTON_MASK_START; + if (report->buttons & USB_GAMEPAD_BUTTON_S1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_BACK; + if (report->buttons & USB_GAMEPAD_BUTTON_L3) + xinput_report->buttons |= XINPUT_BUTTON_MASK_L3; + if (report->buttons & USB_GAMEPAD_BUTTON_R3) + xinput_report->buttons |= XINPUT_BUTTON_MASK_R3; + if (report->buttons & USB_GAMEPAD_BUTTON_L1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_LB; + if (report->buttons & USB_GAMEPAD_BUTTON_R1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_RB; + if (report->buttons & USB_GAMEPAD_BUTTON_A1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_GUIDE; + if (report->buttons & USB_GAMEPAD_BUTTON_B1) + xinput_report->buttons |= XINPUT_BUTTON_MASK_A; + if (report->buttons & USB_GAMEPAD_BUTTON_B2) + xinput_report->buttons |= XINPUT_BUTTON_MASK_B; + if (report->buttons & USB_GAMEPAD_BUTTON_B3) + xinput_report->buttons |= XINPUT_BUTTON_MASK_X; + if (report->buttons & USB_GAMEPAD_BUTTON_B4) + xinput_report->buttons |= XINPUT_BUTTON_MASK_Y; + + // Analog triggers (0-255), fall back to digital if analog is 0 but button pressed + xinput_report->lt = report->lt; + xinput_report->rt = report->rt; + if (xinput_report->lt == 0 && (report->buttons & USB_GAMEPAD_BUTTON_L2)) + xinput_report->lt = 0xFF; + if (xinput_report->rt == 0 && (report->buttons & USB_GAMEPAD_BUTTON_R2)) + xinput_report->rt = 0xFF; + + return usbd_ep_start_write(0, ep, gamepad_report_buffer, sizeof(struct xinput_in_report)); +} + +// Convert gamepad dpad mask to switch hat value +static uint8_t convert_dpad_to_switch_hat(uint32_t buttons) +{ + // Joypad uses active-high (1 = pressed) + uint8_t up = (buttons & USB_GAMEPAD_BUTTON_DU) ? 1 : 0; + uint8_t down = (buttons & USB_GAMEPAD_BUTTON_DD) ? 1 : 0; + uint8_t left = (buttons & USB_GAMEPAD_BUTTON_DL) ? 1 : 0; + uint8_t right = (buttons & USB_GAMEPAD_BUTTON_DR) ? 1 : 0; + + if (up && right) + return SWITCH_HAT_UP_RIGHT; + if (up && left) + return SWITCH_HAT_UP_LEFT; + if (down && right) + return SWITCH_HAT_DOWN_RIGHT; + if (down && left) + return SWITCH_HAT_DOWN_LEFT; + if (up) + return SWITCH_HAT_UP; + if (down) + return SWITCH_HAT_DOWN; + if (left) + return SWITCH_HAT_LEFT; + if (right) + return SWITCH_HAT_RIGHT; + + return SWITCH_HAT_CENTER; +} + +int usbd_gamepad_switch_send_report(uint8_t ep, struct usb_gamepad_report *report) +{ + struct switch_in_report *switch_report; + + switch_report = (struct switch_in_report *)gamepad_report_buffer; + memset(switch_report, 0, sizeof(switch_report)); + + if (report->buttons & USB_GAMEPAD_BUTTON_S1) + switch_report->buttons |= SWITCH_MASK_MINUS; + if (report->buttons & USB_GAMEPAD_BUTTON_S2) + switch_report->buttons |= SWITCH_MASK_PLUS; + if (report->buttons & USB_GAMEPAD_BUTTON_L1) + switch_report->buttons |= SWITCH_MASK_L; + if (report->buttons & USB_GAMEPAD_BUTTON_R1) + switch_report->buttons |= SWITCH_MASK_R; + if (report->buttons & USB_GAMEPAD_BUTTON_L2) + switch_report->buttons |= SWITCH_MASK_ZL; + if (report->buttons & USB_GAMEPAD_BUTTON_R2) + switch_report->buttons |= SWITCH_MASK_ZR; + if (report->buttons & USB_GAMEPAD_BUTTON_L3) + switch_report->buttons |= SWITCH_MASK_L3; + if (report->buttons & USB_GAMEPAD_BUTTON_R3) + switch_report->buttons |= SWITCH_MASK_R3; + if (report->buttons & USB_GAMEPAD_BUTTON_A1) + switch_report->buttons |= SWITCH_MASK_HOME; + if (report->buttons & USB_GAMEPAD_BUTTON_A2) + switch_report->buttons |= SWITCH_MASK_CAPTURE; + if (report->buttons & USB_GAMEPAD_BUTTON_B1) + switch_report->buttons |= SWITCH_MASK_B; + if (report->buttons & USB_GAMEPAD_BUTTON_B2) + switch_report->buttons |= SWITCH_MASK_A; + if (report->buttons & USB_GAMEPAD_BUTTON_B3) + switch_report->buttons |= SWITCH_MASK_Y; + if (report->buttons & USB_GAMEPAD_BUTTON_B4) + switch_report->buttons |= SWITCH_MASK_X; + + switch_report->hat = convert_dpad_to_switch_hat(report->buttons); + + // Analog sticks (HID convention: 0=up, 255=down - no inversion needed) + switch_report->lx = report->lx; + switch_report->ly = report->ly; + switch_report->rx = report->rx; + switch_report->ry = report->ry; + + switch_report->vendor = 0; + + return usbd_ep_start_write(0, ep, gamepad_report_buffer, sizeof(struct switch_in_report)); +} + +struct usbd_interface *usbd_gamepad_xinput_init_intf(struct usbd_interface *intf) +{ + intf->class_interface_handler = NULL; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = xinput_vendor_class_request_handler; + intf->notify_handler = NULL; + + return intf; +} + +static const uint8_t hid_switch_report_desc[HID_SWITCH_REPORT_DESC_SIZE] = { + 0x05, 0x01, // Usage Page (Generic Desktop Ctrls) + 0x09, 0x05, // Usage (Game Pad) + 0xA1, 0x01, // Collection (Application) + 0x15, 0x00, // Logical Minimum (0) + 0x25, 0x01, // Logical Maximum (1) + 0x35, 0x00, // Physical Minimum (0) + 0x45, 0x01, // Physical Maximum (1) + 0x75, 0x01, // Report Size (1) + 0x95, 0x10, // Report Count (16) + 0x05, 0x09, // Usage Page (Button) + 0x19, 0x01, // Usage Minimum (Button 1) + 0x29, 0x10, // Usage Maximum (Button 16) + 0x81, 0x02, // Input (Data,Var,Abs) + 0x05, 0x01, // Usage Page (Generic Desktop Ctrls) + 0x25, 0x07, // Logical Maximum (7) + 0x46, 0x3B, 0x01, // Physical Maximum (315) + 0x75, 0x04, // Report Size (4) + 0x95, 0x01, // Report Count (1) + 0x65, 0x14, // Unit (Eng Rot:Angular Pos) + 0x09, 0x39, // Usage (Hat switch) + 0x81, 0x42, // Input (Data,Var,Abs,Null) + 0x65, 0x00, // Unit (None) + 0x95, 0x01, // Report Count (1) + 0x81, 0x01, // Input (Const) - 4-bit padding + 0x26, 0xFF, 0x00, // Logical Maximum (255) + 0x46, 0xFF, 0x00, // Physical Maximum (255) + 0x09, 0x30, // Usage (X) - Left Stick X + 0x09, 0x31, // Usage (Y) - Left Stick Y + 0x09, 0x32, // Usage (Z) - Right Stick X + 0x09, 0x35, // Usage (Rz) - Right Stick Y + 0x75, 0x08, // Report Size (8) + 0x95, 0x04, // Report Count (4) + 0x81, 0x02, // Input (Data,Var,Abs) + 0x06, 0x00, 0xFF, // Usage Page (Vendor Defined) + 0x09, 0x20, // Usage (0x20) + 0x95, 0x01, // Report Count (1) + 0x81, 0x02, // Input (Data,Var,Abs) - Vendor byte + 0x0A, 0x21, 0x26, // Usage (0x2621) + 0x95, 0x08, // Report Count (8) + 0x91, 0x02, // Output (Data,Var,Abs) - Rumble + 0xC0, // End Collection +}; + +struct usbd_interface *usbd_gamepad_switch_init_intf(struct usbd_interface *intf) +{ + return usbd_hid_init_intf(0, intf, hid_switch_report_desc, HID_SWITCH_REPORT_DESC_SIZE); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.h b/components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.h new file mode 100644 index 0000000000..8f4f20a833 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/gamepad/usbd_gamepad.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_GAMEPAD_H +#define USBD_GAMEPAD_H + +#include "usb_gamepad.h" + +#define USBD_GAMEPAD_MODE_XINPUT 0 +#define USBD_GAMEPAD_MODE_SWITCH 1 +#define USBD_GAMEPAD_MODE_XBOXONE 2 +#define USBD_GAMEPAD_MODE_PS4 3 + +struct usbd_interface *usbd_gamepad_xinput_init_intf(struct usbd_interface *intf); +struct usbd_interface *usbd_gamepad_switch_init_intf(struct usbd_interface *intf); + +int usbd_gamepad_xinput_send_report(uint8_t ep, struct usb_gamepad_report *report); +int usbd_gamepad_switch_send_report(uint8_t ep, struct usb_gamepad_report *report); + +#endif /* USBD_GAMEPAD_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/hid/usb_hid.h b/components/drivers/usb/cherryusb/class/hid/usb_hid.h index ea6c0f2556..b2bd571330 100644 --- a/components/drivers/usb/cherryusb/class/hid/usb_hid.h +++ b/components/drivers/usb/cherryusb/class/hid/usb_hid.h @@ -35,7 +35,7 @@ #define HID_REPORT_OUTPUT 0x02 #define HID_REPORT_FEATURE 0x03 -/* HID Descriptor ***********************************************************/ +/* HID Descriptor */ #define HID_COUNTRY_NONE 0x00 /* Not Supported */ #define HID_COUNTRY_ARABIC 0x01 /* Arabic */ @@ -74,99 +74,114 @@ #define HID_COUNTRY_YUGOSLAVIA 0x34 /* Yugoslavia */ #define HID_COUNTRY_TURKISHF 0x35 /* Turkish-F */ -/* HID report items */ -#define HID_REPORT_ITEM_SIZE_MASK 0x03 -#define HID_REPORT_ITEM_SIZE_0 0x00 /* No data follows */ -#define HID_REPORT_ITEM_SIZE_1 0x01 /* 1 byte of data follows */ -#define HID_REPORT_ITEM_SIZE_2 0x02 /* 2 bytes of data follow */ -#define HID_REPORT_ITEM_SIZE_4 0x03 /* 4 bytes of data follow */ -#define HID_REPORT_ITEM_TYPE_MASK 0x0c -#define HID_REPORT_ITEM_TYPE_MAIN 0x00 -#define HID_REPORT_ITEM_TYPE_GLOBAL 0x04 -#define HID_REPORT_ITEM_TYPE_LOCAL 0x08 -#define HID_REPORT_ITEM_TAG_MASK 0xf0 +/* HID report See specification at + * https://www.usb.org/sites/default/files/hid1_11.pdf + * https://www.usb.org/sites/default/files/hut1_22.pdf + */ + +#define HID_SIZE_MASK (0x3 << 0) +#define HID_TYPE_MASK (0x3 << 2) +#define HID_TAG_MASK (0xF << 4) + +#define HID_ITEMTYPE_MAIN (0x0 << 2) +#define HID_ITEMTYPE_GLOBAL (0x1 << 2) +#define HID_ITEMTYPE_LOCAL (0x2 << 2) +#define HID_ITEMTYPE_LONG (0x3 << 2) /* Main Items (HID 6.2.2.4) */ -#define HID_MAIN_ITEM_CONSTANT (1 << 0) /* Constant(1) vs Data(0) */ -#define HID_MAIN_ITEM_VARIABLE (1 << 1) /* Variable(1) vs Array(0) */ -#define HID_MAIN_ITEM_RELATIVE (1 << 2) /* Relative(1) vs Absolute(0) */ -#define HID_MAIN_ITEM_WRAP (1 << 3) /* Wrap(1) vs No Wrap(0) */ -#define HID_MAIN_ITEM_NONLINEAR (1 << 4) /* Non Linear(1) vs Linear(0) */ -#define HID_MAIN_ITEM_NOPREFERRED (1 << 5) /* No Preferred (1) vs Preferred State(0) */ -#define HID_MAIN_ITEM_NULLSTATE (1 << 6) /* Null state(1) vs No Null position(0) */ -#define HID_MAIN_ITEM_VOLATILE (1 << 7) /* Volatile(1) vs Non volatile(0) */ -#define HID_MAIN_ITEM_BUFFEREDBYTES (1 << 8) /* Buffered Bytes(1) vs Bit Field(0) */ - -#define HID_MAIN_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) -#define HID_MAIN_ITEM_INPUT_PREFIX 0x80 -#define HID_MAIN_ITEM_INPUT_CONSTANT HID_MAIN_ITEM_CONSTANT -#define HID_MAIN_ITEM_INPUT_VARIABLE HID_MAIN_ITEM_VARIABLE -#define HID_MAIN_ITEM_INPUT_RELATIVE HID_MAIN_ITEM_RELATIVE -#define HID_MAIN_ITEM_INPUT_WRAP HID_MAIN_ITEM_WRAP -#define HID_MAIN_ITEM_INPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR -#define HID_MAIN_ITEM_INPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED -#define HID_MAIN_ITEM_INPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE -#define HID_MAIN_ITEM_INPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES - -#define HID_MAIN_ITEM_OUTPUT_PREFIX 0x90 -#define HID_MAIN_ITEM_OUTPUT_CONSTANT HID_MAIN_ITEM_CONSTANT -#define HID_MAIN_ITEM_OUTPUT_VARIABLE HID_MAIN_ITEM_VARIABLE -#define HID_MAIN_ITEM_OUTPUT_RELATIVE HID_MAIN_ITEM_RELATIVE -#define HID_MAIN_ITEM_OUTPUT_WRAP HID_MAIN_ITEM_WRAP -#define HID_MAIN_ITEM_OUTPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR -#define HID_MAIN_ITEM_OUTPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED -#define HID_MAIN_ITEM_OUTPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE -#define HID_MAIN_ITEM_OUTPUT_VOLATILE HID_MAIN_ITEM_VOLATILE -#define HID_MAIN_ITEM_OUTPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES - -#define HID_MAIN_ITEM_FEATURE_PREFIX 0xb0 -#define HID_MAIN_ITEM_FEATURE_CONSTANT HID_MAIN_ITEM_CONSTANT -#define HID_MAIN_ITEM_FEATURE_VARIABLE HID_MAIN_ITEM_VARIABLE -#define HID_MAIN_ITEM_FEATURE_RELATIVE HID_MAIN_ITEM_RELATIVE -#define HID_MAIN_ITEM_FEATURE_WRAP HID_MAIN_ITEM_WRAP -#define HID_MAIN_ITEM_FEATURE_NONLINEAR HID_MAIN_ITEM_NONLINEAR -#define HID_MAIN_ITEM_FEATURE_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED -#define HID_MAIN_ITEM_FEATURE_NULLSTATE HID_MAIN_ITEM_NULLSTATE -#define HID_MAIN_ITEM_FEATURE_VOLATILE HID_MAIN_ITEM_VOLATILE -#define HID_MAIN_ITEM_FEATURE_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES - -#define HID_MAIN_ITEM_COLLECTION_PREFIX 0xa0 -#define HID_MAIN_ITEM_COLLECTION_PHYSICAL 0x00 /* Physical (group of axes) */ -#define HID_MAIN_ITEM_COLLECTION_APPL 0x01 /* Application (mouse, keyboard) */ -#define HID_MAIN_ITEM_COLLECTION_LOGICAL 0x02 /* Logical (interrelated data) */ -#define HID_MAIN_ITEM_COLLECTION_REPORT 0x03 /* Report */ -#define HID_MAIN_ITEM_COLLECTION_ARRAY 0x04 /* Named Array */ -#define HID_MAIN_ITEM_COLLECTION_SWITCH 0x05 /* Usage Switch */ -#define HID_MAIN_ITEM_COLLECTION_MODIFIER 0x06 /* Usage Modifier */ -#define HID_MAIN_ITEM_ENDCOLLECTION_PREFIX 0xc0 +#define HID_MAINITEM_TAG_INPUT (0x08 << 4) +#define HID_MAINITEM_TAG_OUTPUT (0x09 << 4) +#define HID_MAINITEM_TAG_COLLECTION (0x0a << 4) +#define HID_MAINITEM_TAG_FEATURE (0x0b << 4) +#define HID_MAINITEM_TAG_ENDCOLLECTION (0x0c << 4) + +#define HID_MAINITEM_CONSTANT (1 << 0) /* Constant(1) vs Data(0) */ +#define HID_MAINITEM_VARIABLE (1 << 1) /* Variable(1) vs Array(0) */ +#define HID_MAINITEM_RELATIVE (1 << 2) /* Relative(1) vs Absolute(0) */ +#define HID_MAINITEM_WRAP (1 << 3) /* Wrap(1) vs No Wrap(0) */ +#define HID_MAINITEM_NONLINEAR (1 << 4) /* Non Linear(1) vs Linear(0) */ +#define HID_MAINITEM_NOPREFERRED (1 << 5) /* No Preferred (1) vs Preferred State(0) */ +#define HID_MAINITEM_NULLSTATE (1 << 6) /* Null state(1) vs No Null position(0) */ +#define HID_MAINITEM_VOLATILE (1 << 7) /* Volatile(1) vs Non volatile(0) */ +#define HID_MAINITEM_BUFFEREDBYTES (1 << 8) /* Buffered Bytes(1) vs Bit Field(0) */ + +#define HID_MAINITEM_COLLECTION_PHYSICAL 0x00 /* Physical (group of axes) */ +#define HID_MAINITEM_COLLECTION_APPL 0x01 /* Application (mouse, keyboard) */ +#define HID_MAINITEM_COLLECTION_LOGICAL 0x02 /* Logical (interrelated data) */ +#define HID_MAINITEM_COLLECTION_REPORT 0x03 /* Report */ +#define HID_MAINITEM_COLLECTION_ARRAY 0x04 /* Named Array */ +#define HID_MAINITEM_COLLECTION_SWITCH 0x05 /* Usage Switch */ +#define HID_MAINITEM_COLLECTION_MODIFIER 0x06 /* Usage Modifier */ /* Global Items (HID 6.2.2.7) */ -#define HID_GLOBAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) -#define HID_GLOBAL_ITEM_USAGEPAGE_PREFIX 0x04 /* Usage Page */ -#define HID_GLOBAL_ITEM_LOGICALMIN_PREFIX 0x14 /* Logical Minimum */ -#define HID_GLOBAL_ITEM_LOGICALMAX_PREFIX 0x24 /* Logical Maximum */ -#define HID_GLOBAL_ITEM_PHYSICALMIN_PREFIX 0x34 /* Physical Minimum */ -#define HID_GLOBAL_ITEM_PHYSMICALAX_PREFIX 0x44 /* Physical Maximum */ -#define HID_GLOBAL_ITEM_UNITEXP_PREFIX 0x54 /* Unit Exponent */ -#define HID_GLOBAL_ITEM_UNIT_PREFIX 0x64 /* Unit */ -#define HID_GLOBAL_ITEM_REPORTSIZE_PREFIX 0x74 /* Report Size */ -#define HID_GLOBAL_ITEM_REPORTID_PREFIX 0x84 /* Report ID */ -#define HID_GLOBAL_ITEM_REPORTCOUNT_PREFIX 0x94 /* Report Count */ -#define HID_GLOBAL_ITEM_PUSH_PREFIX 0xa4 /* Push */ -#define HID_GLOBAL_ITEM_POP_PREFIX 0xb4 /* Pop */ +#define HID_GLOBALITEM_TAG_USAGE_PAGE (0x00 << 4) +#define HID_GLOBALITEM_TAG_LOGICAL_MIN (0x01 << 4) +#define HID_GLOBALITEM_TAG_LOGICAL_MAX (0x02 << 4) +#define HID_GLOBALITEM_TAG_PHYSICAL_MIN (0x03 << 4) +#define HID_GLOBALITEM_TAG_PHYSICAL_MAX (0x04 << 4) +#define HID_GLOBALITEM_TAG_UNIT_EXP (0x05 << 4) +#define HID_GLOBALITEM_TAG_UNIT (0x06 << 4) +#define HID_GLOBALITEM_TAG_REPORT_SIZE (0x07 << 4) +#define HID_GLOBALITEM_TAG_REPORT_ID (0x08 << 4) +#define HID_GLOBALITEM_TAG_REPORT_COUNT (0x09 << 4) +#define HID_GLOBALITEM_TAG_PUSH (0x0a << 4) +#define HID_GLOBALITEM_TAG_POP (0x0b << 4) /* Local Items (HID 6.2.2.8) */ -#define HID_LOCAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) -#define HID_LOCAL_ITEM_USAGE_PREFIX 0x08 /* Usage */ -#define HID_LOCAL_ITEM_USAGEMIN_PREFIX 0x18 /* Usage Minimum */ -#define HID_LOCAL_ITEM_USAGEMAX_PREFIX 0x28 /* Usage Maximum */ -#define HID_LOCAL_ITEM_DESIGNATORIDX_PREFIX 0x38 /* Designator Index */ -#define HID_LOCAL_ITEM_DESIGNATORMIN_PREFIX 0x48 /* Designator Minimum */ -#define HID_LOCAL_ITEM_DESIGNATORMAX_PREFIX 0x58 /* Designator Maximum */ -#define HID_LOCAL_ITEM_STRINGIDX_PREFIX 0x78 /* String Index */ -#define HID_LOCAL_ITEM_STRINGMIN_PREFIX 0x88 /* String Minimum */ -#define HID_LOCAL_ITEM_STRINGMAX_PREFIX 0x98 /* xx */ -#define HID_LOCAL_ITEM_DELIMITER_PREFIX 0xa8 /* Delimiter */ +#define HID_LOCALITEM_TAG_USAGE (0x00 << 4) +#define HID_LOCALITEM_TAG_USAGE_MIN (0x01 << 4) +#define HID_LOCALITEM_TAG_USAGE_MAX (0x02 << 4) +#define HID_LOCALITEM_TAG_DESIG_INDEX (0x03 << 4) +#define HID_LOCALITEM_TAG_DESIG_MIN (0x04 << 4) +#define HID_LOCALITEM_TAG_DESIG_MAX (0x05 << 4) +/* No 6 in spec */ +#define HID_LOCALITEM_TAG_STRING_INDEX (0x07 << 4) +#define HID_LOCALITEM_TAG_STRING_MIN (0x08 << 4) +#define HID_LOCALITEM_TAG_STRING_MAX (0x09 << 4) +#define HID_LOCALITEM_TAG_DELIMITER (0x0a << 4) /* Also listed as reserved in spec! */ + +/* Usage pages (HuT 3) */ +#define HID_USAGE_PAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_USAGE_PAGE_GENERIC_DESKTOP_CONTROLS 0x01 /* Generic Desktop Controls */ +#define HID_USAGE_PAGE_SIMULATION_CONTROLS 0x02 /* Simulation Controls */ +#define HID_USAGE_PAGE_VR_CONTROLS 0x03 /* VR Controls */ +#define HID_USAGE_PAGE_SPORT_CONTROLS 0x04 /* Sport Controls */ +#define HID_USAGE_PAGE_GAME_CONTROLS 0x05 /* Game Controls */ +#define HID_USAGE_PAGE_GENERIC_DEVICE_CONTROLS 0x06 /* Generic Device Controls */ +#define HID_USAGE_PAGE_KEYBOARD_KEYPAD 0x07 /* Keyboard/Keypad */ +#define HID_USAGE_PAGE_LED 0x08 /* LEDs */ +#define HID_USAGE_PAGE_BUTTON 0x09 /* Button */ +#define HID_USAGE_PAGE_ORDINAL 0x0a /* Ordinal */ +#define HID_USAGE_PAGE_TELEPHONY 0x0b /* Telephony */ +#define HID_USAGE_PAGE_CONSUMER 0x0c /* Consumer */ +#define HID_USAGE_PAGE_DIGITIZER 0x0d /* Digitizer */ +#define HID_USAGE_PAGE_HAPTICS /* 0x0e Reserved */ +#define HID_USAGE_PAGE_PID 0x0f /* PID Page Physical Interface Device */ +#define HID_USAGE_PAGE_UNICODE 0x10 /* Unicode */ +#define HID_USAGE_PAGE_SOC 0x11 /* Sensor Orientation Category */ +#define HID_USAGE_PAGE_EYE_AND_HEAD_TRACKER 0x12 /* Eye and Head Tracker */ + /* 0x13 Reserved */ +#define HID_USAGE_PAGE_ALPHA_DISPLAY 0x14 /* Alphanumeric Display */ + /* 0x15-3f Reserved */ +#define HID_USAGE_PAGE_MEDICAL 0x40 /* Medical Instruments */ +#define HID_USAGE_PAGE_BRAILLE_DISPLAY 0x41 /* Braille Display */ + /* 0x42-0x58 Reserved */ +#define HID_USAGE_PAGE_LIGHTING_AND_ILLUMINATION 0x59 /* Lighting and Illumination */ + /* 0x5a-0x7f Reserved */ +#define HID_USAGE_PAGE_USB_MONITOR 0x80 /* USB Monitor */ +#define HID_USAGE_PAGE_USB_ENUMERATED_VALUES 0x81 /* USB Enumerated Values */ +#define HID_USAGE_PAGE_VESA_VIRTUAL_CONTROLS 0x82 /* VESA Virtual Controls */ +#define HID_USAGE_PAGE_POWER_DEVICE 0x84 /* Power Device */ +#define HID_USAGE_PAGE_BATTERY_SYSTEM 0x85 /* Battery System */ +#define HID_USAGE_PAGE_BARCODE_SCANNER 0x8c /* Bar Code Scanner page */ +#define HID_USAGE_PAGE_SCALE 0x8d /* Scale page */ +#define HID_USAGE_PAGE_MSR 0x8e /* Magnetic Stripe Reading (MSR) Devices */ +#define HID_USAGE_PAGE_POS 0x8f /* Point of Sale devices */ +#define HID_USAGE_PAGE_CAMERA_CONTROL 0x90 /* Camera Control Page */ +#define HID_USAGE_PAGE_ARCADE 0x91 +#define HID_USAGE_PAGE_GAMING_DEVICE 0x92 +#define HID_USAGE_PAGE_FIDO_ALLIANCE 0xF1D0 +#define HID_USAGE_PAGE_VENDOR_PAGE_HBYTE 0xFF00 /* Modifier Keys (HID 8.3) */ #define HID_MODIFIER_LCTRL (1 << 0) /* Left Ctrl */ @@ -205,38 +220,6 @@ #define HID_JS_INPUT_REPORT_BUTTON3 (1 << 6) #define HID_JS_INPUT_REPORT_BUTTON4 (1 << 7) -/* Usage pages (HuT 3) */ -#define HID_USAGE_PAGE_UNDEFINED 0x00 /* Undefined */ -#define HID_USAGE_PAGE_GENERIC_DCTRL 0x01 /* Generic Desktop Controls */ -#define HID_USAGE_PAGE_SIMCTRL 0x02 /* Simulation Controls */ -#define HID_USAGE_PAGE_VRCTRL 0x03 /* VR Controls */ -#define HID_USAGE_PAGE_SPORTCTRL 0x04 /* Sport Controls */ -#define HID_USAGE_PAGE_GAMECTRL 0x05 /* Game Controls */ -#define HID_USAGE_PAGE_GENERIC_DEVCTRL 0x06 /* Generic Device Controls */ -#define HID_USAGE_PAGE_KBD 0x07 /* Keyboard/Keypad */ -#define HID_USAGE_PAGE_LEDS 0x08 /* LEDs */ -#define HID_USAGE_PAGE_BUTTON 0x09 /* Button */ -#define HID_USAGE_PAGE_ORDINAL 0x0a /* Ordinal */ -#define HID_USAGE_PAGE_TELEPHONY 0x0b /* Telephony */ -#define HID_USAGE_PAGE_CONSUMER 0x0c /* Consumer */ -#define HID_USAGE_PAGE_DIGITIZER 0x0d /* Digitizer */ - /* 0x0e Reserved */ -#define HID_USAGE_PAGE_PIDPAGE 0x0f /* PID Page Physical Interface Device */ -#define HID_USAGE_PAGE_UNICODE 0x10 /* Unicode */ - /* 0x11-13 Reserved */ -#define HID_USAGE_PAGE_ALPHA_DISPLAY 0x14 /* Alphanumeric Display */ - /* 0x15-3f Reserved */ -#define HID_USAGE_PAGE_MEDICAL 0x40 /* Medical Instruments */ - /* 0x41-7f Reserved */ - /* 0x80-83 Monitor Devices */ - /* 0x84-87 Power Devices */ - /* 0x88-8b Reserved */ -#define HID_USAGE_PAGE_BARCODE_SCANNER 0x8c /* Bar Code Scanner page */ -#define HID_USAGE_PAGE_SCALE 0x8d /* Scale page */ -#define HID_USAGE_PAGE_MSR 0x8e /* Magnetic Stripe Reading (MSR) Devices */ -#define HID_USAGE_PAGE_POS 0x8f /* Point of Sale devices */ -#define HID_USAGE_PAGE_CAMERA_CTRL 0x90 /* Camera Control Page */ - /* Generic Desktop Page Usage IDs (HuT 4) */ #define HID_DESKTOP_USAGE_UNDEFINED 0x00 /* Undefined */ #define HID_DESKTOP_USAGE_POINTER 0x01 /* Pointer */ @@ -634,7 +617,7 @@ struct usb_hid_js_report { #define HID_CUSTOM_INOUT_DESCRIPTOR_LEN (9 + 9 + 7 + 7) -#define HID_CUSTOM_INOUT_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, in_ep, out_ep,wMaxPacketSize, bInterval) \ +#define HID_CUSTOM_INOUT_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, out_ep, in_ep, wMaxPacketSize, bInterval) \ 0x09, /* bLength: Interface Descriptor size */ \ USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ @@ -654,13 +637,13 @@ struct usb_hid_js_report { WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ 0x07, /* bLength: Endpoint Descriptor size */ \ USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ - in_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + out_ep, /* bEndpointAddress: Endpoint Address (OUT) */ \ 0x03, /* bmAttributes: Interrupt endpoint */ \ WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ bInterval, /* bInterval: Polling Interval */ \ 0x07, /* bLength: Endpoint Descriptor size */ \ USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ - out_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + in_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ 0x03, /* bmAttributes: Interrupt endpoint */ \ WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ bInterval /* bInterval: Polling Interval */ diff --git a/components/drivers/usb/cherryusb/class/hid/usbh_hid.c b/components/drivers/usb/cherryusb/class/hid/usbh_hid.c index 5c400c7b17..4fd1a91a01 100644 --- a/components/drivers/usb/cherryusb/class/hid/usbh_hid.c +++ b/components/drivers/usb/cherryusb/class/hid/usbh_hid.c @@ -20,7 +20,7 @@ #define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ #define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_buf[CONFIG_USBHOST_MAX_HID_CLASS][USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_buf[CONFIG_USBHOST_MAX_HID_CLASS][USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; static struct usbh_hid g_hid_class[CONFIG_USBHOST_MAX_HID_CLASS]; static uint32_t g_devinuse = 0; @@ -106,7 +106,7 @@ int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer) if (ret < 8) { return ret; } - memcpy(buffer, g_hid_buf[hid_class->minor], MIN(ret - 8, 1)); + memcpy(buffer, g_hid_buf[hid_class->minor], MIN((uint32_t)ret - 8, 1)); return ret; } @@ -148,7 +148,7 @@ int usbh_hid_get_protocol(struct usbh_hid *hid_class, uint8_t *protocol) if (ret < 8) { return ret; } - memcpy(protocol, g_hid_buf[hid_class->minor], MIN(ret - 8, 1)); + memcpy(protocol, g_hid_buf[hid_class->minor], MIN((uint32_t)ret - 8, 1)); return ret; } @@ -173,7 +173,6 @@ int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen) { struct usb_setup_packet *setup; - int ret; if (!hid_class || !hid_class->hport) { return -USB_ERR_INVAL; @@ -186,18 +185,12 @@ int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t setup->wIndex = 0; setup->wLength = buflen; - ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf[hid_class->minor]); - if (ret < 8) { - return ret; - } - memcpy(buffer, g_hid_buf[hid_class->minor], MIN(ret - 8, buflen)); - return ret; + return usbh_control_transfer(hid_class->hport, setup, buffer); } int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) { struct usb_endpoint_descriptor *ep_desc; - int ret; uint8_t cur_iface = 0xff; uint8_t *p; bool found = false; @@ -249,23 +242,6 @@ int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) return -USB_ERR_INVAL; } found: - // /* 0x0 = boot protocol, 0x1 = report protocol */ - // ret = usbh_hid_set_protocol(hid_class, 0x1); - // if (ret < 0) { - // return ret; - // } - - ret = usbh_hid_set_idle(hid_class, 0, 0); - if (ret < 0) { - USB_LOG_WRN("Do not support set idle\r\n"); - } - - /* We read report desc but do nothing (because of too much memory usage for parsing report desc, parsed by users) */ - ret = usbh_hid_get_report_descriptor(hid_class, g_hid_buf[hid_class->minor], MIN(sizeof(g_hid_buf[hid_class->minor]), hid_class->report_size)); - if (ret < 0) { - return ret; - } - for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; if (ep_desc->bEndpointAddress & 0x80) { @@ -280,7 +256,7 @@ found: USB_LOG_INFO("Register HID Class:%s\r\n", hport->config.intf[intf].devname); usbh_hid_run(hid_class); - return ret; + return 0; } int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf) @@ -310,6 +286,427 @@ int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf) return ret; } +static uint32_t hid_get_itemval(const uint8_t *data, unsigned int idx, unsigned int size) +{ + uint32_t value = 0; + + for (unsigned int i = 1; i <= size; i++) + value |= data[idx + i] << (8 * (i - 1)); + + return value; +} + +struct hid_report *usbh_hid_report_parse(const uint8_t *data, uint32_t report_len, uint32_t max_usages) +{ + uint32_t i = 0; + uint32_t itemtag, itemtype, itemsize; + uint32_t itemval; + struct hid_report_field field; + uint32_t usage_page = 0, usage = 0, usage_min = 0, usage_max = 0, flags = 0; + uint32_t *usages; + struct hid_report *hid_report; + + hid_report = usb_osal_malloc(sizeof(struct hid_report)); + if (!hid_report) { + USB_LOG_ERR("hid report malloc failed\r\n"); + return NULL; + } + + usages = usb_osal_malloc(sizeof(uint32_t) * max_usages); + if (!usages) { + USB_LOG_ERR("hid usages malloc failed\r\n"); + goto err; + } + + memset(hid_report, 0, sizeof(struct hid_report)); + memset(&field, 0, sizeof(struct hid_report_field)); + + while (i < report_len) { + itemtag = data[i] & HID_TAG_MASK; + itemtype = data[i] & HID_TYPE_MASK; + itemsize = data[i] & HID_SIZE_MASK; + + if (itemsize == 3) /* HID spec: 6.2.2.2 - Short Items */ + itemsize = 4; + + itemval = hid_get_itemval(data, i, itemsize); + + USB_LOG_DBG("itemtype 0x%02x, itemtag 0x%02x, itemsize %d, itemval 0x%08x\r\n", + itemtype, itemtag, itemsize, itemval); + + switch (itemtype) { + case HID_ITEMTYPE_MAIN: + switch (itemtag) { + case HID_MAINITEM_TAG_INPUT: + if ((flags & HID_REPORT_FLAG_REQUIRED_MASK) != HID_REPORT_FLAG_REQUIRED_MASK) + goto err; + + if (hid_report->input_count >= CONFIG_USBHOST_HID_MAX_INPUT) { + USB_LOG_ERR("hid input fields exceed max limit\r\n"); + goto err; + } + + field.flags = flags; + field.properties = itemval; + field.usage_page = usage_page; + memcpy(&hid_report->input_fields[hid_report->input_count], &field, sizeof(struct hid_report_field)); + if (field.usage_count > 0) { + hid_report->input_fields[hid_report->input_count].usages = usb_osal_malloc(sizeof(uint32_t) * field.usage_count); + if (!hid_report->input_fields[hid_report->input_count].usages) { + USB_LOG_ERR("hid input usages malloc failed\r\n"); + goto err; + } + memcpy(hid_report->input_fields[hid_report->input_count].usages, usages, sizeof(uint32_t) * field.usage_count); + } + + hid_report->input_count++; + + /* only keep the global items */ + flags &= HID_REPORT_FLAG_GLOBAL_MASK; + memset(&field, 0, sizeof(struct hid_report_field)); + break; + case HID_MAINITEM_TAG_OUTPUT: + if ((flags & HID_REPORT_FLAG_REQUIRED_MASK) != HID_REPORT_FLAG_REQUIRED_MASK) + goto err; + + if (hid_report->output_count >= CONFIG_USBHOST_HID_MAX_OUTPUT) { + USB_LOG_ERR("hid output fields exceed max limit\r\n"); + goto err; + } + + field.flags = flags; + field.properties = itemval; + field.usage_page = usage_page; + memcpy(&hid_report->output_fields[hid_report->output_count], &field, sizeof(struct hid_report_field)); + if (field.usage_count > 0) { + hid_report->output_fields[hid_report->output_count].usages = usb_osal_malloc(sizeof(uint32_t) * field.usage_count); + if (!hid_report->output_fields[hid_report->output_count].usages) { + USB_LOG_ERR("hid output usages malloc failed\r\n"); + goto err; + } + memcpy(hid_report->output_fields[hid_report->output_count].usages, usages, sizeof(uint32_t) * field.usage_count); + } + + hid_report->output_count++; + + /* only keep the global items */ + flags &= HID_REPORT_FLAG_GLOBAL_MASK; + memset(&field, 0, sizeof(struct hid_report_field)); + break; + case HID_MAINITEM_TAG_COLLECTION: + memset(&field, 0, sizeof(struct hid_report_field)); + break; + case HID_MAINITEM_TAG_FEATURE: + + if (hid_report->feature_count >= CONFIG_USBHOST_HID_MAX_FEATURE) { + USB_LOG_ERR("hid feature fields exceed max limit\r\n"); + goto err; + } + + field.flags = flags; + field.properties = itemval; + field.usage_page = usage_page; + memcpy(&hid_report->feature_fields[hid_report->feature_count], &field, sizeof(struct hid_report_field)); + if (field.usage_count > 0) { + hid_report->feature_fields[hid_report->feature_count].usages = usb_osal_malloc(sizeof(uint32_t) * field.usage_count); + if (!hid_report->feature_fields[hid_report->feature_count].usages) { + USB_LOG_ERR("hid feature usages malloc failed\r\n"); + goto err; + } + memcpy(hid_report->feature_fields[hid_report->feature_count].usages, usages, sizeof(uint32_t) * field.usage_count); + } + + hid_report->feature_count++; + + memset(&field, 0, sizeof(struct hid_report_field)); + + break; + case HID_MAINITEM_TAG_ENDCOLLECTION: + break; + default: + goto err; + } + break; + case HID_ITEMTYPE_GLOBAL: + switch (itemtag) { + case HID_GLOBALITEM_TAG_USAGE_PAGE: + usage_page = itemval; + + if (usage_page > UINT16_MAX) + goto err; + + flags |= HID_REPORT_FLAG_USAGE_PAGE; + break; + case HID_GLOBALITEM_TAG_LOGICAL_MIN: + field.logical_min = (int32_t)itemval; + flags |= HID_REPORT_FLAG_LOGICAL_MIN; + break; + case HID_GLOBALITEM_TAG_LOGICAL_MAX: + field.logical_max = (int32_t)itemval; + flags |= HID_REPORT_FLAG_LOGICAL_MAX; + break; + case HID_GLOBALITEM_TAG_REPORT_SIZE: + field.report_size = itemval; + flags |= HID_REPORT_FLAG_REPORT_SIZE; + break; + case HID_GLOBALITEM_TAG_REPORT_COUNT: + field.report_count = itemval; + flags |= HID_REPORT_FLAG_REPORT_COUNT; + break; + case HID_GLOBALITEM_TAG_REPORT_ID: + hid_report->uses_report_id = true; + field.report_id = itemval; + flags |= HID_REPORT_FLAG_REPORT_ID; + break; + default: + goto err; + } + break; + case HID_ITEMTYPE_LOCAL: + switch (itemtag) { + case HID_LOCALITEM_TAG_USAGE: + usage = itemval; + /* Extended usage (size 4) combines both usage page and id */ + if (itemsize != 4) { + if (!(flags & HID_REPORT_FLAG_USAGE_PAGE)) + goto err; + usage |= usage_page << 16; + } + + usages[field.usage_count++] = usage; + + break; + case HID_LOCALITEM_TAG_USAGE_MIN: + usage_min = itemval; + if (itemsize == 4) { + /* Usage max must be extended as well */ + flags |= HID_REPORT_FLAG_EXTENDED_USAGE; + } else { + if (!(flags & HID_REPORT_FLAG_USAGE_PAGE)) + goto err; + usage_min |= usage_page << 16; + } + field.usage_min = usage_min; + flags |= HID_REPORT_FLAG_USAGE_MIN; + break; + case HID_LOCALITEM_TAG_USAGE_MAX: + if (!(flags & HID_REPORT_FLAG_USAGE_MIN)) + goto err; + + usage_max = itemval; + if (flags & HID_REPORT_FLAG_EXTENDED_USAGE) { + /* Fail if max is not extended usage (HID spec 6.2.2.8) */ + if (itemsize != 4) + goto err; + } else if (itemsize == 4) { + /* Fail because min wasn't extended, but max is */ + goto err; + } else { + if (!(flags & HID_REPORT_FLAG_USAGE_PAGE)) + goto err; + usage_max |= usage_page << 16; + } + + /* Usage min and max must be on the same page */ + if (USAGE_PAGE(usage_min) != USAGE_PAGE(usage_max)) { + goto err; + } + + if (usage_min > usage_max) { + goto err; + } + + for (uint32_t j = usage_min; j <= usage_max; j++) { + usages[field.usage_count++] = j; + } + + field.usage_max = usage_max; + flags |= HID_REPORT_FLAG_USAGE_MAX; + flags &= ~(HID_REPORT_FLAG_USAGE_MIN | HID_REPORT_FLAG_EXTENDED_USAGE); + break; + default: + goto err; + } + break; + default: + goto err; + } + + i += (1 + itemsize); + } + usb_osal_free(usages); + return hid_report; +err: + if (hid_report) { + usb_osal_free(hid_report); + + for (uint32_t j = 0; j < hid_report->input_count; j++) + usb_osal_free(hid_report->input_fields[j].usages); + + for (uint32_t j = 0; j < hid_report->output_count; j++) + usb_osal_free(hid_report->output_fields[j].usages); + + for (uint32_t j = 0; j < hid_report->feature_count; j++) + usb_osal_free(hid_report->feature_fields[j].usages); + } + + if (usages) + usb_osal_free(usages); + return NULL; +} + +void usbh_hid_report_free(struct hid_report *hid_report) +{ + if (hid_report) { + for (uint32_t j = 0; j < hid_report->input_count; j++) + usb_osal_free(hid_report->input_fields[j].usages); + + for (uint32_t j = 0; j < hid_report->output_count; j++) + usb_osal_free(hid_report->output_fields[j].usages); + + for (uint32_t j = 0; j < hid_report->feature_count; j++) + usb_osal_free(hid_report->feature_fields[j].usages); + + usb_osal_free(hid_report); + } +} + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_report_buf[2048]; + +static const char *hid_property_string(uint32_t value) +{ + uint32_t off = 0; + static char buffer[160]; + + memset(buffer, 0, sizeof(buffer)); + + if (value & HID_MAINITEM_CONSTANT) + off += snprintf(buffer + off, sizeof(buffer) - off, "Constant, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "Data, "); + + if (value & HID_MAINITEM_VARIABLE) + off += snprintf(buffer + off, sizeof(buffer) - off, "Variable, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "Array, "); + + if (value & HID_MAINITEM_RELATIVE) + off += snprintf(buffer + off, sizeof(buffer) - off, "Relative, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "Absolute, "); + + if (value & HID_MAINITEM_WRAP) + off += snprintf(buffer + off, sizeof(buffer) - off, "Wrap, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "NoWrap, "); + + if (value & HID_MAINITEM_NONLINEAR) + off += snprintf(buffer + off, sizeof(buffer) - off, "NonLinear, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "Linear, "); + + if (value & HID_MAINITEM_NOPREFERRED) + off += snprintf(buffer + off, sizeof(buffer) - off, "NoPreferred, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "Preferred, "); + + if (value & HID_MAINITEM_NULLSTATE) + off += snprintf(buffer + off, sizeof(buffer) - off, "NullState, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "NoNullState, "); + + if (value & HID_MAINITEM_VOLATILE) + off += snprintf(buffer + off, sizeof(buffer) - off, "Volatile, "); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "NonVolatile, "); + + if (value & HID_MAINITEM_BUFFEREDBYTES) + off += snprintf(buffer + off, sizeof(buffer) - off, "BufferedBytes"); + else + off += snprintf(buffer + off, sizeof(buffer) - off, "BitField"); + + return buffer; + +} + +static void usbh_hid_field_info_print(uint32_t idx, struct hid_report_field *field) +{ + USB_LOG_RAW(" Field %u:\r\n", idx); + USB_LOG_RAW(" Usage Page: 0x%04x\r\n", (unsigned int)field->usage_page); + USB_LOG_RAW(" Report ID: %u\r\n", (unsigned int)field->report_id); + USB_LOG_RAW(" Report Size: %ubit\r\n", (unsigned int)field->report_size); + USB_LOG_RAW(" Report Count: %u\r\n", (unsigned int)field->report_count); + USB_LOG_RAW(" Logical Min: %d\r\n", field->logical_min); + USB_LOG_RAW(" Logical Max: %d\r\n", field->logical_max); + USB_LOG_RAW(" Usage Count: %u\r\n", (unsigned int)field->usage_count); + if (field->usage_count > 0) { + if (field->usage_count == 1) { + USB_LOG_RAW(" Usage: 0x%04x\r\n", USAGE_ID(field->usages[0])); + } else { + USB_LOG_RAW(" Usages(0x%04x ~ 0x%04x)\r\n", USAGE_ID(field->usage_min), USAGE_ID(field->usage_max)); + } + } + USB_LOG_RAW(" Flags: 0x%04x\r\n", (unsigned int)field->flags); + USB_LOG_RAW(" Properties: 0x%04x(%s)\r\n", (unsigned int)field->properties, hid_property_string(field->properties)); +} + +int lshid(int argc, char **argv) +{ + struct usbh_hid *hid_class; + struct hid_report *hid_report; + int ret; + + if (argc < 2) { + USB_LOG_ERR("please input correct command: lshid path\r\n"); + return -1; + } + + hid_class = usbh_find_class_instance(argv[1]); + if (!hid_class) { + USB_LOG_ERR("cannot find hid device\r\n"); + return -1; + } + + if (hid_class->report_size > sizeof(g_hid_report_buf)) { + USB_LOG_ERR("hid report buffer is too small\r\n"); + return -1; + } + + ret = usbh_hid_get_report_descriptor(hid_class, g_hid_report_buf, hid_class->report_size); + if (ret < 0) { + USB_LOG_ERR("get hid report descriptor failed, errcode: %d\r\n", ret); + return -1; + } + + hid_report = usbh_hid_report_parse(g_hid_report_buf, hid_class->report_size, 1024); + if (hid_report) { + USB_LOG_RAW("HID report parsed successfully\r\n"); + + USB_LOG_RAW("Input fields: %u\r\n", (unsigned int)hid_report->input_count); + for (uint32_t i = 0; i < hid_report->input_count; i++) { + struct hid_report_field *field = &hid_report->input_fields[i]; + usbh_hid_field_info_print(i, field); + } + + USB_LOG_RAW("Output fields: %u\r\n", (unsigned int)hid_report->output_count); + for (uint32_t i = 0; i < hid_report->output_count; i++) { + struct hid_report_field *field = &hid_report->output_fields[i]; + usbh_hid_field_info_print(i, field); + } + + USB_LOG_RAW("Feature fields: %u\r\n", (unsigned int)hid_report->feature_count); + for (uint32_t i = 0; i < hid_report->feature_count; i++) { + struct hid_report_field *field = &hid_report->feature_fields[i]; + usbh_hid_field_info_print(i, field); + } + + usbh_hid_report_free(hid_report); + } else { + USB_LOG_ERR("HID report parsed failed\r\n"); + } + return 0; +} + __WEAK void usbh_hid_run(struct usbh_hid *hid_class) { (void)hid_class; diff --git a/components/drivers/usb/cherryusb/class/hid/usbh_hid.h b/components/drivers/usb/cherryusb/class/hid/usbh_hid.h index 8b87e0c0b5..fa5c7663af 100644 --- a/components/drivers/usb/cherryusb/class/hid/usbh_hid.h +++ b/components/drivers/usb/cherryusb/class/hid/usbh_hid.h @@ -8,6 +8,82 @@ #include "usb_hid.h" +/* local items */ +#define HID_REPORT_FLAG_USAGE_MIN (1 << 0) +#define HID_REPORT_FLAG_USAGE_MAX (1 << 1) + +/* global items */ +#define HID_REPORT_FLAG_REPORT_ID (1 << 2) +#define HID_REPORT_FLAG_REPORT_COUNT (1 << 3) +#define HID_REPORT_FLAG_REPORT_SIZE (1 << 4) +#define HID_REPORT_FLAG_LOGICAL_MIN (1 << 5) +#define HID_REPORT_FLAG_LOGICAL_MAX (1 << 6) +#define HID_REPORT_FLAG_USAGE_PAGE (1 << 7) + +/* main items */ +#define HID_REPORT_FLAG_INPUT (1 << 8) +#define HID_REPORT_FLAG_OUTPUT (1 << 9) +#define HID_REPORT_FLAG_FEATURE (1 << 10) + +#define HID_REPORT_FLAG_EXTENDED_USAGE (1 << 11) + +/* masks */ + +#define HID_REPORT_FLAG_GLOBAL_MASK (HID_REPORT_FLAG_REPORT_ID | \ + HID_REPORT_FLAG_REPORT_COUNT | \ + HID_REPORT_FLAG_REPORT_SIZE | \ + HID_REPORT_FLAG_LOGICAL_MIN | \ + HID_REPORT_FLAG_LOGICAL_MAX | \ + HID_REPORT_FLAG_USAGE_PAGE) + +#define HID_REPORT_FLAG_REQUIRED_MASK (HID_REPORT_FLAG_REPORT_COUNT | \ + HID_REPORT_FLAG_REPORT_SIZE | \ + HID_REPORT_FLAG_LOGICAL_MIN | \ + HID_REPORT_FLAG_LOGICAL_MAX) + +#define USAGE_ID(usage) (usage & 0x0000FFFF) +#define USAGE_PAGE(usage) ((usage & 0xFFFF0000) >> 16) + +#ifndef CONFIG_USBHOST_HID_MAX_INPUT +#define CONFIG_USBHOST_HID_MAX_INPUT 16 +#endif + +#ifndef CONFIG_USBHOST_HID_MAX_OUTPUT +#define CONFIG_USBHOST_HID_MAX_OUTPUT 16 +#endif + +#ifndef CONFIG_USBHOST_HID_MAX_FEATURE +#define CONFIG_USBHOST_HID_MAX_FEATURE 16 +#endif + +struct hid_report_field { + uint32_t *usages; /* usage page + usage */ + uint32_t usage_count; + uint32_t usage_page; + + uint32_t report_id; /* optional */ + uint32_t report_count; + uint32_t report_size; + int32_t logical_min; + int32_t logical_max; + uint32_t properties; + + uint32_t usage_min; + uint32_t usage_max; + + uint32_t flags; +}; + +struct hid_report { + bool uses_report_id; + uint32_t input_count; + struct hid_report_field input_fields[CONFIG_USBHOST_HID_MAX_INPUT]; + uint32_t output_count; + struct hid_report_field output_fields[CONFIG_USBHOST_HID_MAX_OUTPUT]; + uint32_t feature_count; + struct hid_report_field feature_fields[CONFIG_USBHOST_HID_MAX_FEATURE]; +}; + struct usbh_hid { struct usbh_hubport *hport; struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ @@ -36,9 +112,14 @@ int usbh_hid_get_protocol(struct usbh_hid *hid_class, uint8_t *protocol); int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); +struct hid_report *usbh_hid_report_parse(const uint8_t *data, uint32_t report_len, uint32_t max_usages); +void usbh_hid_report_free(struct hid_report *hid_report); + void usbh_hid_run(struct usbh_hid *hid_class); void usbh_hid_stop(struct usbh_hid *hid_class); +int lshid(int argc, char **argv); + #ifdef __cplusplus } #endif diff --git a/components/drivers/usb/cherryusb/class/hub/usbh_hub.c b/components/drivers/usb/cherryusb/class/hub/usbh_hub.c index 008c600cee..910aa0c2cd 100644 --- a/components/drivers/usb/cherryusb/class/hub/usbh_hub.c +++ b/components/drivers/usb/cherryusb/class/hub/usbh_hub.c @@ -238,6 +238,7 @@ int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) { struct usb_setup_packet roothub_setup; struct usb_setup_packet *setup; + int ret; if (hub->is_roothub) { setup = &roothub_setup; @@ -246,9 +247,22 @@ int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) setup->wValue = feature; setup->wIndex = port; setup->wLength = 0; - return usbh_roothub_control(hub->bus, setup, NULL); + + ret = usbh_roothub_control(hub->bus, setup, NULL); + + if ((feature == HUB_PORT_FEATURE_RESET) && (ret >= 0)) { + hub->bus->event_handler(hub->bus->busid, hub->index, port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_RESET); + } + + return ret; } else { - return _usbh_hub_set_feature(hub, port, feature); + ret = _usbh_hub_set_feature(hub, port, feature); + + if ((feature == HUB_PORT_FEATURE_RESET) && (ret >= 0)) { + hub->bus->event_handler(hub->bus->busid, hub->index, port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_RESET); + } + + return ret; } } @@ -337,11 +351,11 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) } /* - * Super-Speed hubs need to know their depth to be able to - * parse the bits of the route-string that correspond to - * their downstream port number. - * - */ + * Super-Speed hubs need to know their depth to be able to + * parse the bits of the route-string that correspond to + * their downstream port number. + * + */ if ((hport->depth != 0) && (hport->speed == USB_SPEED_SUPER)) { ret = usbh_hub_set_depth(hub, hport->depth - 1); if (ret < 0) { @@ -373,6 +387,11 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) hub->tt_think = ((hub->hub_desc.wHubCharacteristics & HUB_CHAR_TTTT_MASK) >> 5); } + if (hub->nports > CONFIG_USBHOST_MAX_EHPORTS) { + USB_LOG_ERR("Hub nports %u overflow\r\n", hub->nports); + return -USB_ERR_NOMEM; + } + for (uint8_t port = 0; port < hub->nports; port++) { hub->child[port].port = port + 1; hub->child[port].parent = hub; @@ -470,6 +489,8 @@ static void usbh_hub_events(struct usbh_hub *hub) int ret; size_t flags; + (void)speed_table; + if (!hub->connected) { return; } @@ -560,6 +581,8 @@ static void usbh_hub_events(struct usbh_hub *hub) /* Last, check connect status */ if (portstatus & HUB_PORT_STATUS_CONNECTION) { + hub->bus->event_handler(hub->bus->busid, hub->index, port + 1, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_CONNECTED); + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_RESET); if (ret < 0) { USB_LOG_ERR("Failed to reset port %u, errorcode: %d\r\n", port + 1, ret); @@ -641,7 +664,6 @@ static void usbh_hub_events(struct usbh_hub *hub) child = &hub->child[port]; /** release child sources */ usbh_hubport_release(child); - USB_LOG_INFO("Device on Bus %u, Hub %u, Port %u disconnected\r\n", hub->bus->busid, hub->index, port + 1); } } } @@ -660,12 +682,15 @@ static void usbh_hub_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) struct usbh_bus *bus = (struct usbh_bus *)CONFIG_USB_OSAL_THREAD_GET_ARGV; usb_hc_init(bus); + bus->event_handler(bus->busid, USB_HUB_INDEX_ANY, USB_HUB_PORT_ANY, USB_INTERFACE_ANY, USBH_EVENT_INIT); while (1) { ret = usb_osal_mq_recv(bus->hub_mq, (uintptr_t *)&hub, USB_OSAL_WAITING_FOREVER); if (ret < 0) { continue; } + usb_osal_mutex_take(bus->mutex); usbh_hub_events(hub); + usb_osal_mutex_give(bus->mutex); } } @@ -695,6 +720,12 @@ int usbh_hub_initialize(struct usbh_bus *bus) return -1; } + bus->mutex = usb_osal_mutex_create(); + if (bus->mutex == NULL) { + USB_LOG_ERR("Failed to create bus mutex\r\n"); + return -1; + } + snprintf(thread_name, 32, "usbh_hub%u", bus->busid); bus->hub_thread = usb_osal_thread_create(thread_name, CONFIG_USBHOST_PSC_STACKSIZE, CONFIG_USBHOST_PSC_PRIO, usbh_hub_thread, bus); if (bus->hub_thread == NULL) { @@ -708,8 +739,8 @@ int usbh_hub_deinitialize(struct usbh_bus *bus) { struct usbh_hubport *hport; struct usbh_hub *hub; - size_t flags; + usb_osal_mutex_take(bus->mutex); hub = &bus->hcd.roothub; for (uint8_t port = 0; port < hub->nports; port++) { hport = &hub->child[port]; @@ -717,15 +748,13 @@ int usbh_hub_deinitialize(struct usbh_bus *bus) usbh_hubport_release(hport); } - flags = usb_osal_enter_critical_section(); - usb_hc_deinit(bus); - usb_osal_leave_critical_section(flags); - - usb_osal_mq_delete(bus->hub_mq); usb_osal_thread_delete(bus->hub_thread); + usb_osal_mq_delete(bus->hub_mq); + usb_osal_mutex_give(bus->mutex); + usb_osal_mutex_delete(bus->mutex); return 0; } diff --git a/components/drivers/usb/cherryusb/class/midi/usb_midi.h b/components/drivers/usb/cherryusb/class/midi/usb_midi.h index 3e7a846f4e..e68675a77d 100644 --- a/components/drivers/usb/cherryusb/class/midi/usb_midi.h +++ b/components/drivers/usb/cherryusb/class/midi/usb_midi.h @@ -6,6 +6,8 @@ #ifndef USB_MIDI_H #define USB_MIDI_H +#include "usb_audio.h" + /* bDescriptorSubType */ #define MIDI_VC_HEADER_DESCRIPTOR_SUBTYPE 0x01U #define MIDI_MS_HEADER_DESCRIPTOR_SUBTYPE 0x01U @@ -201,6 +203,19 @@ struct midi_cs_ep_ms_general_descriptor { #define MIDI_SIZEOF_MS_GENERAL_DESC(n) (4 + n) // clang-format off +#define MIDI_STANDARD_DESCRIPTOR_INIT(bInterfaceNumber, bNumEndpoints) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_MIDISTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + +#define MIDI_STANDARD_DESCRIPTOR_LEN 0x09 + #define MIDI_CS_HEADER_DESCRIPTOR_INIT(wTotalLength) \ 0x07, /* bLength */ \ USB_CS_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.c b/components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.c new file mode 100644 index 0000000000..cf5363efa5 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2022 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_cdc_acm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_acm" +#include "usb_log.h" + +struct usbh_cdc_acm { + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +static int usbh_cdc_acm_attach(struct usbh_serial *serial) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_cdc_acm *cdc_acm_class = usb_osal_malloc(sizeof(struct usbh_cdc_acm)); + if (!cdc_acm_class) { + USB_LOG_ERR("No memory for cdc_acm_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(cdc_acm_class, 0, sizeof(struct usbh_cdc_acm)); + serial->priv = cdc_acm_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_acm_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!cdc_acm_class->intin) { + USB_LOG_ERR("Failed to find interrupt endpoint\r\n"); + ret = -USB_ERR_NODEV; + goto errout; + } + return 0; +errout: + serial->priv = NULL; + usb_osal_free(cdc_acm_class); + return ret; +} + +static void usbh_cdc_acm_detach(struct usbh_serial *serial) +{ + struct usbh_cdc_acm *cdc_acm_class; + + if (!serial || !serial->priv) { + return; + } + + cdc_acm_class = (struct usbh_cdc_acm *)serial->priv; + if (cdc_acm_class->intin) { + usbh_kill_urb(&cdc_acm_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(cdc_acm_class); +} + +static int usbh_cdc_acm_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + memcpy(serial->iobuffer, line_coding, sizeof(struct cdc_line_coding)); + + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); +} + +static int usbh_cdc_acm_get_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(line_coding, serial->iobuffer, sizeof(struct cdc_line_coding)); + return ret; +} + +static int usbh_cdc_acm_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; + setup->wValue = (dtr << 0) | (rts << 1); + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_cdc_acm_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_cdc_acm *cdc_acm_class; + uintptr_t flags; + uint16_t status; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + cdc_acm_class = (struct usbh_cdc_acm *)serial->priv; + + status = (cdc_acm_class->modem_status & CDC_SERIAL_STATE_DSR ? USBH_SERIAL_TIOCM_DSR : 0) | + (cdc_acm_class->modem_status & CDC_SERIAL_STATE_RING ? USBH_SERIAL_TIOCM_RI : 0) | + (cdc_acm_class->modem_status & CDC_SERIAL_STATE_DCD ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + usb_osal_leave_critical_section(flags); + + return status; +} + +#ifdef CONFIG_USBH_SERIAL_GET_MODEM_STATUS +static int __usbh_cdc_acm_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_cdc_acm *cdc_acm_class; + struct cdc_acm_notification *notification; + uint16_t difference; + uintptr_t flags; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + cdc_acm_class = (struct usbh_cdc_acm *)serial->priv; + + usbh_int_urb_fill(&cdc_acm_class->intin_urb, serial->hport, cdc_acm_class->intin, &serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET], cdc_acm_class->intin->wMaxPacketSize, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(&cdc_acm_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (cdc_acm_class->intin_urb.actual_length < sizeof(struct cdc_acm_notification)) { + return -USB_ERR_INVAL; + } + + notification = (struct cdc_acm_notification *)&serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET]; + if (notification->bNotificationType != CDC_NOTIFICATION_SERIAL_STATE) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + difference = cdc_acm_class->modem_status ^ notification->data; + cdc_acm_class->modem_status = notification->data; + + if (difference & CDC_SERIAL_STATE_DSR) + serial->iocount.dsr++; + if (difference & CDC_SERIAL_STATE_DCD) + serial->iocount.dcd++; + if (notification->data & CDC_SERIAL_STATE_BREAK) + serial->iocount.brk++; + if (notification->data & CDC_SERIAL_STATE_FRAMING) + serial->iocount.frame++; + if (notification->data & CDC_SERIAL_STATE_PARITY) + serial->iocount.parity++; + if (notification->data & CDC_SERIAL_STATE_OVERRUN) + serial->iocount.overrun++; + + usb_osal_leave_critical_section(flags); + + return ret; +} +#endif + +static const struct usbh_serial_driver cdc_acm_driver = { + .driver_name = "cdc_acm", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_cdc_acm_attach, + .detach = usbh_cdc_acm_detach, + .set_flow_control = NULL, + .set_line_coding = usbh_cdc_acm_set_line_coding, + .get_line_coding = usbh_cdc_acm_get_line_coding, + .set_line_state = usbh_cdc_acm_set_line_state, + .get_modem_status = usbh_cdc_acm_get_modem_status, +}; + +static int usbh_cdc_acm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &cdc_acm_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_cdc_acm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +const struct usbh_class_driver cdc_acm_class_driver = { + .driver_name = "cdc_acm", + .connect = usbh_cdc_acm_connect, + .disconnect = usbh_cdc_acm_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_none_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_NONE, + .id_table = NULL, + .class_driver = &cdc_acm_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_at_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = CDC_COMMON_PROTOCOL_AT_COMMANDS, + .id_table = NULL, + .class_driver = &cdc_acm_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.h b/components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.h new file mode 100644 index 0000000000..2940cd9c1a --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_cdc_acm.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2022 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_ACM_H +#define USBH_CDC_ACM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_ACM_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c b/components/drivers/usb/cherryusb/class/serial/usbh_ch34x.c similarity index 36% rename from components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c rename to components/drivers/usb/cherryusb/class/serial/usbh_ch34x.c index 3941d47dcb..4e31a1afa3 100644 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c +++ b/components/drivers/usb/cherryusb/class/serial/usbh_ch34x.c @@ -1,44 +1,24 @@ /* - * Copyright (c) 2024, sakumisu + * Copyright (c) 2024 ~ 2025, sakumisu * * SPDX-License-Identifier: Apache-2.0 */ #include "usbh_core.h" +#include "usbh_serial.h" #include "usbh_ch34x.h" -#define DEV_FORMAT "/dev/ttyUSB%d" +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_ch43x" +#include "usb_log.h" -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_ch34x_buf[USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; - -#define CONFIG_USBHOST_MAX_CP210X_CLASS 1 - -static struct usbh_ch34x g_ch34x_class[CONFIG_USBHOST_MAX_CP210X_CLASS]; -static uint32_t g_devinuse = 0; - -static struct usbh_ch34x *usbh_ch34x_class_alloc(void) -{ - uint8_t devno; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_CP210X_CLASS; devno++) { - if ((g_devinuse & (1U << devno)) == 0) { - g_devinuse |= (1U << devno); - memset(&g_ch34x_class[devno], 0, sizeof(struct usbh_ch34x)); - g_ch34x_class[devno].minor = devno; - return &g_ch34x_class[devno]; - } - } - return NULL; -} +struct usbh_ch34x { + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; -static void usbh_ch34x_class_free(struct usbh_ch34x *ch34x_class) -{ - uint8_t devno = ch34x_class->minor; - - if (devno < 32) { - g_devinuse &= ~(1U << devno); - } - memset(ch34x_class, 0, sizeof(struct usbh_ch34x)); -} +/* refer to https://github.com/WCHSoftGroup/ch341ser_linux/blob/main/driver/ch341.c */ static int usbh_ch34x_get_baudrate_div(uint32_t baudrate, uint8_t *factor, uint8_t *divisor) { @@ -88,65 +68,137 @@ static int usbh_ch34x_get_baudrate_div(uint32_t baudrate, uint8_t *factor, uint8 return 0; } -static int usbh_ch34x_get_version(struct usbh_ch34x *ch34x_class) +static int usbh_ch34x_control_out(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_ch34x_control_in(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t *data, uint16_t size) { struct usb_setup_packet *setup; int ret; - if (!ch34x_class || !ch34x_class->hport) { + if (!serial || !serial->hport) { return -USB_ERR_INVAL; } - setup = ch34x_class->hport->setup; + setup = serial->hport->setup; setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = CH34X_READ_VERSION; - setup->wValue = 0; - setup->wIndex = 0; - setup->wLength = 2; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = size; - ret = usbh_control_transfer(ch34x_class->hport, setup, g_ch34x_buf); + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); if (ret < 0) { return ret; } + memcpy(data, serial->iobuffer, size); - USB_LOG_INFO("Ch34x chip version %02x:%02x\r\n", g_ch34x_buf[0], g_ch34x_buf[1]); return ret; } -static int usbh_ch34x_flow_ctrl(struct usbh_ch34x *ch34x_class) +static int usbh_ch34x_get_version(struct usbh_serial *serial) { - struct usb_setup_packet *setup; + int ret; + uint8_t buf[2]; - if (!ch34x_class || !ch34x_class->hport) { - return -USB_ERR_INVAL; + ret = usbh_ch34x_control_in(serial, CH34X_READ_VERSION, 0, 0, buf, 2); + if (ret < 0) { + return ret; } - setup = ch34x_class->hport->setup; - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = CH34X_WRITE_REG; - setup->wValue = 0x2727; - setup->wIndex = 0; - setup->wLength = 0; + USB_LOG_INFO("chip version: 0x%02x\r\n", buf[0]); + return ret; +} + +static int usbh_ch34x_attach(struct usbh_serial *serial) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; - return usbh_control_transfer(ch34x_class->hport, setup, NULL); + struct usbh_ch34x *ch34x_class = usb_osal_malloc(sizeof(struct usbh_ch34x)); + if (!ch34x_class) { + USB_LOG_ERR("No memory for ch34x_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(ch34x_class, 0, sizeof(struct usbh_ch34x)); + serial->priv = ch34x_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(ch34x_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!ch34x_class->intin) { + USB_LOG_ERR("Failed to find interrupt endpoint\r\n"); + ret = -USB_ERR_NODEV; + goto errout; + } + + ret = usbh_ch34x_get_version(serial); + ret |= usbh_ch34x_control_out(serial, CH34X_SERIAL_INIT, 0, 0); + ret |= usbh_ch34x_control_out(serial, CH34X_WRITE_REG, 0x1312, 0xd982); + ret |= usbh_ch34x_control_out(serial, CH34X_WRITE_REG, 0x0f2c, 0x0007); + if (ret < 0) { + goto errout; + } + + return 0; +errout: + serial->priv = NULL; + usb_osal_free(ch34x_class); + return ret; } -int usbh_ch34x_set_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding) +static void usbh_ch34x_detach(struct usbh_serial *serial) { - struct usb_setup_packet *setup; - uint16_t reg_value = 0; - uint16_t value = 0; - uint8_t factor = 0; - uint8_t divisor = 0; + struct usbh_ch34x *ch34x_class; - if (!ch34x_class || !ch34x_class->hport) { - return -USB_ERR_INVAL; + if (!serial || !serial->priv) { + return; + } + + ch34x_class = (struct usbh_ch34x *)serial->priv; + if (ch34x_class->intin) { + usbh_kill_urb(&ch34x_class->intin_urb); } - setup = ch34x_class->hport->setup; + serial->priv = NULL; + usb_osal_free(ch34x_class); +} - memcpy((uint8_t *)&ch34x_class->line_coding, line_coding, sizeof(struct cdc_line_coding)); +static int usbh_ch34x_set_flow_ctrl(struct usbh_serial *serial, bool hardctrl) +{ + return usbh_ch34x_control_out(serial, CH34X_WRITE_REG, 0x2727, hardctrl ? 0x0101 : 0x0000); +} - /* refer to https://github.com/WCHSoftGroup/ch341ser_linux/blob/main/driver/ch341.c */ +static int usbh_ch34x_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + uint16_t reg_value = 0; + uint16_t value = 0; + uint16_t index = 0; + uint8_t factor = 0; + uint8_t divisor = 0; switch (line_coding->bParityType) { case 0: @@ -188,178 +240,156 @@ int usbh_ch34x_set_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_c reg_value |= CH341_L_SB; } - reg_value |= 0xC0; + usbh_ch34x_get_baudrate_div(line_coding->dwDTERate, &factor, &divisor); + reg_value |= 0xC0; value |= 0x9c; value |= reg_value << 8; + index |= 0x80 | divisor; + index |= (uint16_t)factor << 8; - usbh_ch34x_get_baudrate_div(line_coding->dwDTERate, &factor, &divisor); - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = CH34X_SERIAL_INIT; - setup->wValue = value; - setup->wIndex = (factor << 8) | 0x80 | divisor; - setup->wLength = 0; - - return usbh_control_transfer(ch34x_class->hport, setup, NULL); + return usbh_ch34x_control_out(serial, CH34X_SERIAL_INIT, value, index); } -int usbh_ch34x_get_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding) +static int usbh_ch34x_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) { - memcpy(line_coding, (uint8_t *)&ch34x_class->line_coding, sizeof(struct cdc_line_coding)); - return 0; + uint16_t value = 0; + uint8_t control = 0; + + control = (dtr << 5) | (rts << 6); + value = (uint8_t)~control; + + return usbh_ch34x_control_out(serial, CH34X_MODEM_CTRL, value, 0x0000); } -int usbh_ch34x_set_line_state(struct usbh_ch34x *ch34x_class, bool dtr, bool rts) +static int usbh_ch34x_get_modem_status(struct usbh_serial *serial) { - struct usb_setup_packet *setup; + struct usbh_ch34x *ch34x_class; + uintptr_t flags; + uint16_t status; - if (!ch34x_class || !ch34x_class->hport) { + if (!serial || !serial->hport || !serial->priv) { return -USB_ERR_INVAL; } - setup = ch34x_class->hport->setup; - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = CH34X_MODEM_CTRL; - setup->wValue = 0x0f | (dtr << 5) | (rts << 6); - setup->wIndex = 0; - setup->wLength = 0; + flags = usb_osal_enter_critical_section(); - return usbh_control_transfer(ch34x_class->hport, setup, NULL); -} + ch34x_class = (struct usbh_ch34x *)serial->priv; -static int usbh_ch34x_connect(struct usbh_hubport *hport, uint8_t intf) -{ - struct usb_endpoint_descriptor *ep_desc; - int ret = 0; + status = (ch34x_class->modem_status & CH341_CTI_DS ? USBH_SERIAL_TIOCM_DSR : 0) | + (ch34x_class->modem_status & CH341_CTI_C ? USBH_SERIAL_TIOCM_CTS : 0) | + (ch34x_class->modem_status & CH341_CTRL_RI ? USBH_SERIAL_TIOCM_RI : 0) | + (ch34x_class->modem_status & CH341_CTI_DC ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); - struct usbh_ch34x *ch34x_class = usbh_ch34x_class_alloc(); - if (ch34x_class == NULL) { - USB_LOG_ERR("Fail to alloc ch34x_class\r\n"); - return -USB_ERR_NOMEM; - } - - ch34x_class->hport = hport; - ch34x_class->intf = intf; + usb_osal_leave_critical_section(flags); - hport->config.intf[intf].priv = ch34x_class; + return status; +} - usbh_ch34x_get_version(ch34x_class); - usbh_ch34x_flow_ctrl(ch34x_class); +#ifdef CONFIG_USBH_SERIAL_GET_MODEM_STATUS +static int __usbh_ch34x_get_modem_status(struct usbh_serial *serial, uint16_t *status) +{ + struct usbh_ch34x *ch34x_class; + uint8_t type = 0; + uint8_t data = 0; + uint16_t difference; + uintptr_t flags; + int ret; - for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { - ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; - if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { - continue; - } else { - if (ep_desc->bEndpointAddress & 0x80) { - USBH_EP_INIT(ch34x_class->bulkin, ep_desc); - } else { - USBH_EP_INIT(ch34x_class->bulkout, ep_desc); - } - } + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; } + ch34x_class = (struct usbh_ch34x *)serial->priv; - snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, ch34x_class->minor); - - USB_LOG_INFO("Register CH34X Class:%s\r\n", hport->config.intf[intf].devname); + usbh_int_urb_fill(&ch34x_class->intin_urb, serial->hport, ch34x_class->intin, &serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET], ch34x_class->intin->wMaxPacketSize, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(&ch34x_class->intin_urb); + if (ret < 0) { + return ret; + } -#if 0 - USB_LOG_INFO("Test ch34x rx and tx and rx for 5 times, baudrate is 115200\r\n"); + if (ret < 4) { + return -USB_ERR_INVAL; + } - struct cdc_line_coding linecoding; - uint8_t count = 5; + flags = usb_osal_enter_critical_section(); - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_ch34x_set_line_coding(ch34x_class, &linecoding); - usbh_ch34x_set_line_state(ch34x_class, true, false); + type = serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET]; + if (type & CH341_CTT_M) { + data = ~serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET + 2] & CH341_CTI_ST; + difference = data ^ (ch34x_class->modem_status & CH341_CTI_ST); + ch34x_class->modem_status = data; - memset(g_ch34x_buf, 'a', sizeof(g_ch34x_buf)); - ret = usbh_ch34x_bulk_out_transfer(ch34x_class, g_ch34x_buf, sizeof(g_ch34x_buf), 0xfffffff); - USB_LOG_RAW("out ret:%d\r\n", ret); - while (count--) { - ret = usbh_ch34x_bulk_in_transfer(ch34x_class, g_ch34x_buf, sizeof(g_ch34x_buf), 0xfffffff); - USB_LOG_RAW("in ret:%d\r\n", ret); - if (ret > 0) { - for (uint32_t i = 0; i < ret; i++) { - USB_LOG_RAW("%02x ", g_ch34x_buf[i]); + if (difference) { + if (difference & CH341_CTI_C) { + serial->iocount.cts++; + } + if (difference & CH341_CTI_DS) { + serial->iocount.dsr++; + } + if (difference & CH341_CTRL_RI) { + serial->iocount.rng++; + } + if (difference & CH341_CTI_DC) { + serial->iocount.dcd++; } - USB_LOG_RAW("\r\n"); } } -#endif - usbh_ch34x_run(ch34x_class); - return ret; -} -static int usbh_ch34x_disconnect(struct usbh_hubport *hport, uint8_t intf) -{ - int ret = 0; - - struct usbh_ch34x *ch34x_class = (struct usbh_ch34x *)hport->config.intf[intf].priv; + if (type & CH341_CTT_O) { + serial->iocount.overrun++; + } + if ((type & CH341_CTT_F) == CH341_CTT_F) { + serial->iocount.frame++; + } + if (type & CH341_CTT_P) { + serial->iocount.parity++; + } - if (ch34x_class) { - if (ch34x_class->bulkin) { - usbh_kill_urb(&ch34x_class->bulkin_urb); - } + usb_osal_leave_critical_section(flags); - if (ch34x_class->bulkout) { - usbh_kill_urb(&ch34x_class->bulkout_urb); - } + return ret; +} +#endif - if (hport->config.intf[intf].devname[0] != '\0') { - usb_osal_thread_schedule_other(); - USB_LOG_INFO("Unregister CH34X Class:%s\r\n", hport->config.intf[intf].devname); - usbh_ch34x_stop(ch34x_class); - } +static const struct usbh_serial_driver ch34x_driver = { + .driver_name = "ch34x", - usbh_ch34x_class_free(ch34x_class); - } + .ignore_rx_header = 0, + .ignore_tx_header = 0, - return ret; -} + .attach = usbh_ch34x_attach, + .detach = usbh_ch34x_detach, + .set_flow_control = usbh_ch34x_set_flow_ctrl, + .set_line_coding = usbh_ch34x_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_ch34x_set_line_state, + .get_modem_status = usbh_ch34x_get_modem_status, +}; -int usbh_ch34x_bulk_in_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +static int usbh_ch34x_connect(struct usbh_hubport *hport, uint8_t intf) { - int ret; - struct usbh_urb *urb = &ch34x_class->bulkin_urb; - - usbh_bulk_urb_fill(urb, ch34x_class->hport, ch34x_class->bulkin, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; + return usbh_serial_probe(hport, intf, &ch34x_driver) ? 0 : -USB_ERR_NOMEM; } -int usbh_ch34x_bulk_out_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +static int usbh_ch34x_disconnect(struct usbh_hubport *hport, uint8_t intf) { - int ret; - struct usbh_urb *urb = &ch34x_class->bulkout_urb; + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; - usbh_bulk_urb_fill(urb, ch34x_class->hport, ch34x_class->bulkout, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; + if (serial) { + usbh_serial_remove(serial); } - return ret; -} -__WEAK void usbh_ch34x_run(struct usbh_ch34x *ch34x_class) -{ - (void)ch34x_class; -} - -__WEAK void usbh_ch34x_stop(struct usbh_ch34x *ch34x_class) -{ - (void)ch34x_class; + return 0; } static const uint16_t ch34x_id_table[][2] = { - { 0x1A86, 0x7523 }, + { 0x1A86, 0x7523 }, /* ch340 chip */ + { 0x1A86, 0x7522 }, /* ch340k chip */ + { 0x1A86, 0x5523 }, /* ch341 chip */ + { 0x1A86, 0xe523 }, /* ch330 chip */ + { 0x4348, 0x5523 }, /* ch340 custom chip */ { 0, 0 }, }; diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h b/components/drivers/usb/cherryusb/class/serial/usbh_ch34x.h similarity index 48% rename from components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h rename to components/drivers/usb/cherryusb/class/serial/usbh_ch34x.h index c90bf9bda6..21e481012c 100644 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h +++ b/components/drivers/usb/cherryusb/class/serial/usbh_ch34x.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024, sakumisu + * Copyright (c) 2024 ~ 2025, sakumisu * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,6 +28,11 @@ #define CH341_CTI_DC 0x08 #define CH341_CTI_ST 0x0f +#define CH341_CTT_M BIT(3) +#define CH341_CTT_F (BIT(2) | BIT(6)) +#define CH341_CTT_P BIT(2) +#define CH341_CTT_O BIT(1) + #define CH341_L_ER 0x80 #define CH341_L_ET 0x40 #define CH341_L_PS 0x38 @@ -40,35 +45,10 @@ #define CH341_L_D6 0x01 #define CH341_L_D5 0x00 -struct usbh_ch34x { - struct usbh_hubport *hport; - struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ - struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ - struct usbh_urb bulkout_urb; - struct usbh_urb bulkin_urb; - - struct cdc_line_coding line_coding; - - uint8_t intf; - uint8_t minor; - - void *user_data; -}; - #ifdef __cplusplus extern "C" { #endif -int usbh_ch34x_set_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding); -int usbh_ch34x_get_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding); -int usbh_ch34x_set_line_state(struct usbh_ch34x *ch34x_class, bool dtr, bool rts); - -int usbh_ch34x_bulk_in_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); -int usbh_ch34x_bulk_out_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); - -void usbh_ch34x_run(struct usbh_ch34x *ch34x_class); -void usbh_ch34x_stop(struct usbh_ch34x *ch34x_class); - #ifdef __cplusplus } #endif diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_cp210x.c b/components/drivers/usb/cherryusb/class/serial/usbh_cp210x.c new file mode 100644 index 0000000000..7b240e2c33 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_cp210x.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_cp210x.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cp210x" +#include "usb_log.h" + +struct usbh_cp210x { + uint8_t partnum; + uint32_t fw_version; + uint32_t min_speed; + uint32_t max_speed; + bool use_actual_rate; + bool no_flow_control; + bool no_event_mode; +}; + +struct cp210x_rate { + uint32_t rate; + uint32_t high; +}; + +static const struct cp210x_rate cp210x_an205_table1[] = { + { 300, 300 }, + { 600, 600 }, + { 1200, 1200 }, + { 1800, 1800 }, + { 2400, 2400 }, + { 4000, 4000 }, + { 4800, 4803 }, + { 7200, 7207 }, + { 9600, 9612 }, + { 14400, 14428 }, + { 16000, 16062 }, + { 19200, 19250 }, + { 28800, 28912 }, + { 38400, 38601 }, + { 51200, 51558 }, + { 56000, 56280 }, + { 57600, 58053 }, + { 64000, 64111 }, + { 76800, 77608 }, + { 115200, 117028 }, + { 128000, 129347 }, + { 153600, 156868 }, + { 230400, 237832 }, + { 250000, 254234 }, + { 256000, 273066 }, + { 460800, 491520 }, + { 500000, 567138 }, + { 576000, 670254 }, + { 921600, 0xffffffff } +}; + +/* + * Quantises the baud rate as per AN205 Table 1 + */ +static uint32_t cp210x_get_an205_rate(uint32_t baud) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cp210x_an205_table1); ++i) { + if (baud <= cp210x_an205_table1[i].high) + break; + } + + return cp210x_an205_table1[i].rate; +} + +static uint32_t cp210x_get_actual_rate(uint32_t baud) +{ + unsigned int prescale = 1; + unsigned int div; + + if (baud <= 365) + prescale = 4; + + div = DIV_ROUND_CLOSEST(48000000, 2 * prescale * baud); + baud = 48000000 / (2 * prescale * div); + + return baud; +} + +static void usbh_cp210x_init_max_speed(struct usbh_serial *serial) +{ + struct usbh_cp210x *cp210x_class; + + if (!serial || !serial->hport || !serial->priv) { + return; + } + + cp210x_class = (struct usbh_cp210x *)serial->priv; + + bool use_actual_rate = false; + uint32_t min = 300; + uint32_t max; + + switch (cp210x_class->partnum) { + case CP210X_PARTNUM_CP2101: + max = 921600; + break; + case CP210X_PARTNUM_CP2102: + case CP210X_PARTNUM_CP2103: + max = 1000000; + break; + case CP210X_PARTNUM_CP2104: + use_actual_rate = true; + max = 2000000; + break; + case CP210X_PARTNUM_CP2108: + max = 2000000; + break; + case CP210X_PARTNUM_CP2105: + if (serial->intf == 0) { + use_actual_rate = true; + max = 2000000; /* ECI */ + } else { + min = 2400; + max = 921600; /* SCI */ + } + break; + case CP210X_PARTNUM_CP2102N_QFN28: + case CP210X_PARTNUM_CP2102N_QFN24: + case CP210X_PARTNUM_CP2102N_QFN20: + use_actual_rate = true; + max = 3000000; + break; + default: + max = 2000000; + break; + } + + cp210x_class->min_speed = min; + cp210x_class->max_speed = max; + cp210x_class->use_actual_rate = use_actual_rate; +} + +static int usbh_cp210x_control_out(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t *data, uint16_t size) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = size; + + if (data && size) { + memcpy(serial->iobuffer, data, size); + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); + } else { + return usbh_control_transfer(serial->hport, setup, NULL); + } +} + +static int usbh_cp210x_control_in(struct usbh_serial *serial, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint8_t *data, uint16_t size) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = bRequest; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = size; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(data, serial->iobuffer, size); + + return ret; +} + +static int usbh_cp210x_get_partnum(struct usbh_serial *serial) +{ + uint8_t version[3]; + struct usbh_cp210x *cp210x_class; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + cp210x_class = (struct usbh_cp210x *)serial->priv; + + ret = usbh_cp210x_control_in(serial, CP210X_VENDOR_SPECIFIC, CP210X_GET_PARTNUM, serial->intf, (uint8_t *)&cp210x_class->partnum, 1); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("chip partnum: 0x%02x\r\n", cp210x_class->partnum); + + switch (cp210x_class->partnum) { + case CP210X_PARTNUM_CP2102: + break; + case CP210X_PARTNUM_CP2105: + case CP210X_PARTNUM_CP2108: + ret = usbh_cp210x_control_in(serial, CP210X_VENDOR_SPECIFIC, CP210X_GET_FW_VER_2N, serial->intf, version, 3); + if (ret < 0) { + return ret; + } + cp210x_class->fw_version = version[0] << 16 | version[1] << 8 | version[2]; + break; + case CP210X_PARTNUM_CP2102N_QFN28: + case CP210X_PARTNUM_CP2102N_QFN24: + case CP210X_PARTNUM_CP2102N_QFN20: + ret = usbh_cp210x_control_in(serial, CP210X_VENDOR_SPECIFIC, CP210X_GET_FW_VER_2N, serial->intf, version, 3); + if (ret < 0) { + return ret; + } + cp210x_class->fw_version = version[0] << 16 | version[1] << 8 | version[2]; + if (cp210x_class->fw_version <= 0x10004) + cp210x_class->no_flow_control = true; + break; + default: + break; + } + return ret; +} + +static int usbh_cp210x_enable(struct usbh_serial *serial) +{ + return usbh_cp210x_control_out(serial, CP210X_IFC_ENABLE, 1, serial->intf, NULL, 0); +} + +static int usbh_cp210x_set_chars(struct usbh_serial *serial) +{ + struct cp210x_special_chars chars = { 0 }; + + return usbh_cp210x_control_out(serial, CP210X_SET_CHARS, 0, serial->intf, (uint8_t *)&chars, sizeof(struct cp210x_special_chars)); +} + +// static int usbh_cp210x_get_common_status(struct usbh_serial *serial, struct cp210x_comm_status *status) +// { +// return usbh_cp210x_control_in(serial, CP210X_GET_COMM_STATUS, 0, serial->intf, (uint8_t *)status, sizeof(struct cp210x_comm_status)); +// } + +static int usbh_cp210x_set_baudrate(struct usbh_serial *serial, uint32_t baudrate) +{ + struct usb_setup_packet *setup; + struct usbh_cp210x *cp210x_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + cp210x_class = (struct usbh_cp210x *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_BAUDRATE; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 4; + + if (cp210x_class->use_actual_rate) + baudrate = cp210x_get_actual_rate(baudrate); + else if (baudrate < 1000000) + baudrate = cp210x_get_an205_rate(baudrate); + + memcpy(serial->iobuffer, (uint8_t *)&baudrate, 4); + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); +} + +static int usbh_cp210x_set_data_format(struct usbh_serial *serial, uint8_t databits, uint8_t parity, uint8_t stopbits) +{ + struct usb_setup_packet *setup; + uint16_t value; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + value = ((databits & 0x0F) << 8) | ((parity & 0x0f) << 4) | ((stopbits & 0x03) << 0); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_LINE_CTL; + setup->wValue = value; + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_cp210x_attach(struct usbh_serial *serial) +{ + int ret; + + struct usbh_cp210x *cp210x_class = usb_osal_malloc(sizeof(struct usbh_cp210x)); + if (!cp210x_class) { + return -USB_ERR_NOMEM; + } + memset(cp210x_class, 0, sizeof(struct usbh_cp210x)); + serial->priv = cp210x_class; + + ret = usbh_cp210x_get_partnum(serial); + usbh_cp210x_init_max_speed(serial); + ret |= usbh_cp210x_enable(serial); + ret |= usbh_cp210x_set_chars(serial); + if (ret < 0) { + goto errout; + } + return 0; +errout: + serial->priv = NULL; + usb_osal_free(cp210x_class); + return ret; +} + +static void usbh_cp210x_detach(struct usbh_serial *serial) +{ + if (serial && serial->priv) { + serial->priv = NULL; + usb_osal_free(serial->priv); + } +} + +int usbh_cp210x_set_flow_ctrl(struct usbh_serial *serial, bool enable) +{ + struct cp210x_flow_ctl flow_ctl = { 0 }; + uint32_t flow_repl; + uint32_t ctl_hs; + int ret; + + ret = usbh_cp210x_control_in(serial, CP210X_GET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); + if (ret < 0) { + return ret; + } + + ctl_hs = flow_ctl.lControlHandshake; + flow_repl = flow_ctl.lFlowReplace; + + ctl_hs &= ~CP210X_SERIAL_DSR_HANDSHAKE; + ctl_hs &= ~CP210X_SERIAL_DCD_HANDSHAKE; + ctl_hs &= ~CP210X_SERIAL_DSR_SENSITIVITY; + ctl_hs &= ~CP210X_SERIAL_DTR_MASK; + ctl_hs |= CP210X_SERIAL_DTR_INACTIVE; + + flow_repl &= ~CP210X_SERIAL_RTS_MASK; + flow_repl &= ~CP210X_SERIAL_AUTO_RECEIVE; + flow_repl &= ~CP210X_SERIAL_AUTO_TRANSMIT; + flow_repl |= CP210X_SERIAL_RTS_INACTIVE; + + flow_repl &= ~CP210X_SERIAL_RTS_MASK; + if (enable) { + ctl_hs |= CP210X_SERIAL_CTS_HANDSHAKE; + } else { + ctl_hs &= ~CP210X_SERIAL_CTS_HANDSHAKE; + } + flow_ctl.lControlHandshake = ctl_hs; + flow_ctl.lFlowReplace = flow_repl; + + return usbh_cp210x_control_out(serial, CP210X_SET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); +} + +int usbh_cp210x_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + int ret; + + ret = usbh_cp210x_set_baudrate(serial, line_coding->dwDTERate); + if (ret < 0) { + return ret; + } + return usbh_cp210x_set_data_format(serial, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat); +} + +int usbh_cp210x_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct cp210x_flow_ctl flow_ctl = { 0 }; + uint32_t flow_repl; + uint32_t ctl_hs; + uint16_t control = 0; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + if (serial->rtscts) { + ret = usbh_cp210x_control_in(serial, CP210X_GET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); + if (ret < 0) { + return ret; + } + ctl_hs = flow_ctl.lControlHandshake; + flow_repl = flow_ctl.lFlowReplace; + + ctl_hs &= ~CP210X_SERIAL_DTR_MASK; + if (dtr) + ctl_hs |= CP210X_SERIAL_DTR_ACTIVE; + else + ctl_hs |= CP210X_SERIAL_DTR_INACTIVE; + + flow_repl &= ~CP210X_SERIAL_RTS_MASK; + if (rts) + flow_repl |= CP210X_SERIAL_RTS_FLOW_CTL; + else + flow_repl |= CP210X_SERIAL_RTS_INACTIVE; + + flow_ctl.lControlHandshake = ctl_hs; + flow_ctl.lFlowReplace = flow_repl; + + return usbh_cp210x_control_out(serial, CP210X_SET_FLOW, 0, serial->intf, (uint8_t *)&flow_ctl, sizeof(struct cp210x_flow_ctl)); + } else { + if (dtr) { + control |= CP210X_CONTROL_DTR; + } + if (rts) { + control |= CP210X_CONTROL_RTS; + } + control |= CP210X_CONTROL_WRITE_DTR; + control |= CP210X_CONTROL_WRITE_RTS; + return usbh_cp210x_control_out(serial, CP210X_SET_MHS, control, serial->intf, NULL, 0); + } +} + +static int usbh_cp210x_get_modem_status(struct usbh_serial *serial) +{ + int ret; + uint8_t control; + uint16_t status; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + + ret = usbh_cp210x_control_in(serial, CP210X_GET_MDMSTS, 0, serial->intf, (uint8_t *)&control, 1); + if (ret < 0) { + return ret; + } + + status = ((control & CP210X_CONTROL_DTR) ? USBH_SERIAL_TIOCM_DTR : 0) | + ((control & CP210X_CONTROL_RTS) ? USBH_SERIAL_TIOCM_RTS : 0) | + ((control & CP210X_CONTROL_CTS) ? USBH_SERIAL_TIOCM_CTS : 0) | + ((control & CP210X_CONTROL_DSR) ? USBH_SERIAL_TIOCM_DSR : 0) | + ((control & CP210X_CONTROL_RING) ? USBH_SERIAL_TIOCM_RI : 0) | + ((control & CP210X_CONTROL_DCD) ? USBH_SERIAL_TIOCM_CD : 0); + + return status; +} + +static const struct usbh_serial_driver cp210x_driver = { + .driver_name = "cp210x", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_cp210x_attach, + .detach = usbh_cp210x_detach, + .set_flow_control = usbh_cp210x_set_flow_ctrl, + .set_line_coding = usbh_cp210x_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_cp210x_set_line_state, + .get_modem_status = usbh_cp210x_get_modem_status, +}; + +static int usbh_cp210x_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &cp210x_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_cp210x_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +static const uint16_t cp210x_id_table[][2] = { + { 0x10C4, 0xEA60 }, + { 0, 0 }, +}; + +const struct usbh_class_driver cp210x_class_driver = { + .driver_name = "cp210x", + .connect = usbh_cp210x_connect, + .disconnect = usbh_cp210x_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cp210x_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = cp210x_id_table, + .class_driver = &cp210x_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_cp210x.h b/components/drivers/usb/cherryusb/class/serial/usbh_cp210x.h new file mode 100644 index 0000000000..6bd0206772 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_cp210x.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CP210X_H +#define USBH_CP210X_H + +#include "usb_cdc.h" + +/* Requests */ +#define CP210X_IFC_ENABLE 0x00 +#define CP210X_SET_BAUDDIV 0x01 +#define CP210X_GET_BAUDDIV 0x02 +#define CP210X_SET_LINE_CTL 0x03 // Set parity, data bits, stop bits +#define CP210X_GET_LINE_CTL 0x04 +#define CP210X_SET_BREAK 0x05 +#define CP210X_IMM_CHAR 0x06 +#define CP210X_SET_MHS 0x07 // Set DTR, RTS +#define CP210X_GET_MDMSTS 0x08 +#define CP210X_SET_XON 0x09 +#define CP210X_SET_XOFF 0x0A +#define CP210X_SET_EVENTMASK 0x0B +#define CP210X_GET_EVENTMASK 0x0C +#define CP210X_SET_CHAR 0x0D +#define CP210X_GET_CHARS 0x0E +#define CP210X_GET_PROPS 0x0F +#define CP210X_GET_COMM_STATUS 0x10 +#define CP210X_RESET 0x11 +#define CP210X_PURGE 0x12 +#define CP210X_SET_FLOW 0x13 +#define CP210X_GET_FLOW 0x14 +#define CP210X_EMBED_EVENTS 0x15 +#define CP210X_GET_EVENTSTATE 0x16 +#define CP210X_SET_CHARS 0x19 +#define CP210X_GET_BAUDRATE 0x1D +#define CP210X_SET_BAUDRATE 0x1E // Set baudrate +#define CP210X_VENDOR_SPECIFIC 0xFF + +/* CP210X_VENDOR_SPECIFIC values */ +#define CP210X_GET_FW_VER 0x000E +#define CP210X_READ_2NCONFIG 0x000E +#define CP210X_GET_FW_VER_2N 0x0010 +#define CP210X_READ_LATCH 0x00C2 +#define CP210X_GET_PARTNUM 0x370B +#define CP210X_GET_PORTCONFIG 0x370C +#define CP210X_GET_DEVICEMODE 0x3711 +#define CP210X_WRITE_LATCH 0x37E1 + +/* CP210X_IFC_ENABLE */ +#define CP210X_UART_ENABLE 0x0001 +#define CP210X_UART_DISABLE 0x0000 + +/* CP210X_(SET|GET)_BAUDDIV */ +#define CP210X_BAUD_RATE_GEN_FREQ 0x384000 + +/* CP210X_(SET|GET)_LINE_CTL */ +#define CP210X_BITS_DATA_MASK 0X0f00 +#define CP210X_BITS_DATA_5 0X0500 +#define CP210X_BITS_DATA_6 0X0600 +#define CP210X_BITS_DATA_7 0X0700 +#define CP210X_BITS_DATA_8 0X0800 +#define CP210X_BITS_DATA_9 0X0900 + +#define CP210X_BITS_PARITY_MASK 0x00f0 +#define CP210X_BITS_PARITY_NONE 0x0000 +#define CP210X_BITS_PARITY_ODD 0x0010 +#define CP210X_BITS_PARITY_EVEN 0x0020 +#define CP210X_BITS_PARITY_MARK 0x0030 +#define CP210X_BITS_PARITY_SPACE 0x0040 + +#define CP210X_BITS_STOP_MASK 0x000f +#define CP210X_BITS_STOP_1 0x0000 +#define CP210X_BITS_STOP_1_5 0x0001 +#define CP210X_BITS_STOP_2 0x0002 + +/* CP210X_SET_BREAK */ +#define CP210X_BREAK_ON 0x0001 +#define CP210X_BREAK_OFF 0x0000 + +/* CP210X_(SET_MHS|GET_MDMSTS) */ +#define CP210X_CONTROL_DTR 0x0001 +#define CP210X_CONTROL_RTS 0x0002 +#define CP210X_CONTROL_CTS 0x0010 +#define CP210X_CONTROL_DSR 0x0020 +#define CP210X_CONTROL_RING 0x0040 +#define CP210X_CONTROL_DCD 0x0080 +#define CP210X_CONTROL_WRITE_DTR 0x0100 +#define CP210X_CONTROL_WRITE_RTS 0x0200 + +/* CP210X_(GET|SET)_CHARS */ +struct cp210x_special_chars { + uint8_t bEofChar; + uint8_t bErrorChar; + uint8_t bBreakChar; + uint8_t bEventChar; + uint8_t bXonChar; + uint8_t bXoffChar; +}; + +/* CP210X_GET_COMM_STATUS returns these 0x13 bytes */ +struct cp210x_comm_status { + uint32_t ulErrors; + uint32_t ulHoldReasons; + uint32_t ulAmountInInQueue; + uint32_t ulAmountInOutQueue; + uint8_t bEofReceived; + uint8_t bWaitForImmediate; + uint8_t bReserved; +} __PACKED; + +/* + * CP210X_PURGE - 16 bits passed in wValue of USB request. + * SiLabs app note AN571 gives a strange description of the 4 bits: + * bit 0 or bit 2 clears the transmit queue and 1 or 3 receive. + * writing 1 to all, however, purges cp2108 well enough to avoid the hang. + */ +#define PURGE_ALL 0x000f + +/* CP210X_EMBED_EVENTS */ +#define CP210X_ESCCHAR 0xec + +#define CP210X_LSR_OVERRUN BIT(1) +#define CP210X_LSR_PARITY BIT(2) +#define CP210X_LSR_FRAME BIT(3) +#define CP210X_LSR_BREAK BIT(4) + +/* CP210X_GET_FLOW/CP210X_SET_FLOW read/write these 0x10 bytes */ +struct cp210x_flow_ctl { + uint32_t lControlHandshake; + uint32_t lFlowReplace; + uint32_t lXonLimit; + uint32_t lXoffLimit; +}; + +/* cp210x_flow_ctl::ulControlHandshake */ +#define CP210X_SERIAL_DTR_MASK (0x03 << 0) +#define CP210X_SERIAL_DTR_INACTIVE (0 << 0) +#define CP210X_SERIAL_DTR_ACTIVE (1 << 0) +#define CP210X_SERIAL_DTR_FLOW_CTL (2 << 0) +#define CP210X_SERIAL_CTS_HANDSHAKE BIT(3) +#define CP210X_SERIAL_DSR_HANDSHAKE BIT(4) +#define CP210X_SERIAL_DCD_HANDSHAKE BIT(5) +#define CP210X_SERIAL_DSR_SENSITIVITY BIT(6) + +/* cp210x_flow_ctl::ulFlowReplace */ +#define CP210X_SERIAL_AUTO_TRANSMIT BIT(0) +#define CP210X_SERIAL_AUTO_RECEIVE BIT(1) +#define CP210X_SERIAL_ERROR_CHAR BIT(2) +#define CP210X_SERIAL_NULL_STRIPPING BIT(3) +#define CP210X_SERIAL_BREAK_CHAR BIT(4) +#define CP210X_SERIAL_RTS_MASK (0x03 << 6) +#define CP210X_SERIAL_RTS_INACTIVE (0 << 6) +#define CP210X_SERIAL_RTS_ACTIVE (1 << 6) +#define CP210X_SERIAL_RTS_FLOW_CTL (2 << 6) +#define CP210X_SERIAL_XOFF_CONTINUE BIT(31) + +/* CP210X_VENDOR_SPECIFIC, CP210X_GET_DEVICEMODE call reads these 0x2 bytes. */ +struct cp210x_pin_mode { + uint8_t eci; + uint8_t sci; +}; + +#define CP210X_PIN_MODE_MODEM 0 +#define CP210X_PIN_MODE_GPIO BIT(0) + +/* Part number definitions */ +#define CP210X_PARTNUM_CP2101 0x01 +#define CP210X_PARTNUM_CP2102 0x02 +#define CP210X_PARTNUM_CP2103 0x03 +#define CP210X_PARTNUM_CP2104 0x04 +#define CP210X_PARTNUM_CP2105 0x05 +#define CP210X_PARTNUM_CP2108 0x08 +#define CP210X_PARTNUM_CP2102N_QFN28 0x20 +#define CP210X_PARTNUM_CP2102N_QFN24 0x21 +#define CP210X_PARTNUM_CP2102N_QFN20 0x22 +#define CP210X_PARTNUM_UNKNOWN 0xFF + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CP210X_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c b/components/drivers/usb/cherryusb/class/serial/usbh_ftdi.c similarity index 38% rename from components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c rename to components/drivers/usb/cherryusb/class/serial/usbh_ftdi.c index 4bc7f81b01..16debf37f1 100644 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c +++ b/components/drivers/usb/cherryusb/class/serial/usbh_ftdi.c @@ -1,19 +1,34 @@ /* - * Copyright (c) 2024, sakumisu + * Copyright (c) 2024 ~ 2025, sakumisu * * SPDX-License-Identifier: Apache-2.0 */ #include "usbh_core.h" +#include "usbh_serial.h" #include "usbh_ftdi.h" -#define DEV_FORMAT "/dev/ttyUSB%d" - -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_ftdi_buf[USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; - -#define CONFIG_USBHOST_MAX_FTDI_CLASS 1 - -static struct usbh_ftdi g_ftdi_class[CONFIG_USBHOST_MAX_FTDI_CLASS]; -static uint32_t g_devinuse = 0; +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_ftdi" +#include "usb_log.h" + +enum ftdi_chip_type { + SIO, + FT232A, + FT232B, + FT2232C, + FT232R, + FT232H, + FT2232H, + FT4232H, + FT4232HA, + FT232HP, + FT233HP, + FT2232HP, + FT2233HP, + FT4232HP, + FT4233HP, + FTX, +}; static const char *ftdi_chip_name[] = { [SIO] = "SIO", /* the serial part of FT8U100AX */ @@ -34,47 +49,9 @@ static const char *ftdi_chip_name[] = { [FTX] = "FT-X", }; -static struct usbh_ftdi *usbh_ftdi_class_alloc(void) -{ - uint8_t devno; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_FTDI_CLASS; devno++) { - if ((g_devinuse & (1U << devno)) == 0) { - g_devinuse |= (1U << devno); - memset(&g_ftdi_class[devno], 0, sizeof(struct usbh_ftdi)); - g_ftdi_class[devno].minor = devno; - return &g_ftdi_class[devno]; - } - } - return NULL; -} - -static void usbh_ftdi_class_free(struct usbh_ftdi *ftdi_class) -{ - uint8_t devno = ftdi_class->minor; - - if (devno < 32) { - g_devinuse &= ~(1U << devno); - } - memset(ftdi_class, 0, sizeof(struct usbh_ftdi)); -} - -/* - * Divide positive or negative dividend by positive or negative divisor - * and round to closest integer. Result is undefined for negative - * divisors if the dividend variable type is unsigned and for negative - * dividends if the divisor variable type is unsigned. - */ -#define DIV_ROUND_CLOSEST(x, divisor) ( \ - { \ - typeof(x) __x = x; \ - typeof(divisor) __d = divisor; \ - (((typeof(x))-1) > 0 || \ - ((typeof(divisor))-1) > 0 || \ - (((__x) > 0) == ((__d) > 0))) ? \ - (((__x) + ((__d) / 2)) / (__d)) : \ - (((__x) - ((__d) / 2)) / (__d)); \ - }) +struct usbh_ftdi { + enum ftdi_chip_type chip_type; +}; static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, int base) { @@ -114,10 +91,10 @@ static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, int base) else if (divisor == 0x4001) /* 1.5 */ divisor = 1; /* - * Set this bit to turn off a divide by 2.5 on baud rate generator - * This enables baud rates up to 12Mbaud but cannot reach below 1200 - * baud with this bit set - */ + * Set this bit to turn off a divide by 2.5 on baud rate generator + * This enables baud rates up to 12Mbaud but cannot reach below 1200 + * baud with this bit set + */ divisor |= 0x00020000; return divisor; } @@ -127,53 +104,37 @@ static uint32_t ftdi_2232h_baud_to_divisor(uint32_t baud) return ftdi_2232h_baud_base_to_divisor(baud, 120000000); } -int usbh_ftdi_reset(struct usbh_ftdi *ftdi_class) +int usbh_ftdi_reset(struct usbh_serial *serial) { struct usb_setup_packet *setup; - if (!ftdi_class || !ftdi_class->hport) { + if (!serial || !serial->hport) { return -USB_ERR_INVAL; } - setup = ftdi_class->hport->setup; + setup = serial->hport->setup; setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_RESET_REQUEST; + setup->bRequest = FTDI_SIO_RESET; setup->wValue = 0; - setup->wIndex = ftdi_class->intf; + setup->wIndex = serial->intf; setup->wLength = 0; - return usbh_control_transfer(ftdi_class->hport, setup, NULL); + return usbh_control_transfer(serial->hport, setup, NULL); } -static int usbh_ftdi_set_modem(struct usbh_ftdi *ftdi_class, uint16_t value) -{ - struct usb_setup_packet *setup; - - if (!ftdi_class || !ftdi_class->hport) { - return -USB_ERR_INVAL; - } - setup = ftdi_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_SET_MODEM_CTRL_REQUEST; - setup->wValue = value; - setup->wIndex = ftdi_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(ftdi_class->hport, setup, NULL); -} - -static int usbh_ftdi_set_baudrate(struct usbh_ftdi *ftdi_class, uint32_t baudrate) +static int usbh_ftdi_set_baudrate(struct usbh_serial *serial, uint32_t baudrate) { struct usb_setup_packet *setup; + struct usbh_ftdi *ftdi_class; uint32_t div_value; uint16_t value; uint8_t baudrate_high; - if (!ftdi_class || !ftdi_class->hport) { + if (!serial || !serial->hport || !serial->priv) { return -USB_ERR_INVAL; } - setup = ftdi_class->hport->setup; + setup = serial->hport->setup; + ftdi_class = (struct usbh_ftdi *)serial->priv; switch (ftdi_class->chip_type) { case FT232B: @@ -187,6 +148,8 @@ static int usbh_ftdi_set_baudrate(struct usbh_ftdi *ftdi_class, uint32_t baudrat default: if ((baudrate <= 12000000) && (baudrate >= 1200)) { div_value = ftdi_2232h_baud_to_divisor(baudrate); + } else if (baudrate < 1200) { + div_value = ftdi_232bm_baud_to_divisor(baudrate); } else { return -USB_ERR_INVAL; } @@ -197,15 +160,15 @@ static int usbh_ftdi_set_baudrate(struct usbh_ftdi *ftdi_class, uint32_t baudrat baudrate_high = (div_value >> 16) & 0xff; setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_SET_BAUDRATE_REQUEST; + setup->bRequest = FTDI_SIO_SET_BAUDRATE; setup->wValue = value; - setup->wIndex = (baudrate_high << 8) | ftdi_class->intf; + setup->wIndex = (baudrate_high << 8) | serial->intf; setup->wLength = 0; - return usbh_control_transfer(ftdi_class->hport, setup, NULL); + return usbh_control_transfer(serial->hport, setup, NULL); } -static int usbh_ftdi_set_data_format(struct usbh_ftdi *ftdi_class, uint8_t databits, uint8_t parity, uint8_t stopbits, uint8_t isbreak) +static int usbh_ftdi_set_data_format(struct usbh_serial *serial, uint8_t databits, uint8_t parity, uint8_t stopbits, uint8_t isbreak) { /** * D0-D7 databits BITS_7=7, BITS_8=8 @@ -216,281 +179,215 @@ static int usbh_ftdi_set_data_format(struct usbh_ftdi *ftdi_class, uint8_t datab struct usb_setup_packet *setup; uint16_t value; - if (!ftdi_class || !ftdi_class->hport) { + if (!serial || !serial->hport) { return -USB_ERR_INVAL; } - setup = ftdi_class->hport->setup; + setup = serial->hport->setup; value = ((isbreak & 0x01) << 14) | ((stopbits & 0x03) << 11) | ((parity & 0x0f) << 8) | (databits & 0x0f); setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_SET_DATA_REQUEST; + setup->bRequest = FTDI_SIO_SET_DATA; setup->wValue = value; - setup->wIndex = ftdi_class->intf; + setup->wIndex = serial->intf; setup->wLength = 0; - return usbh_control_transfer(ftdi_class->hport, setup, NULL); + return usbh_control_transfer(serial->hport, setup, NULL); } -static int usbh_ftdi_set_latency_timer(struct usbh_ftdi *ftdi_class, uint16_t value) +static int usbh_ftdi_set_latency_timer(struct usbh_serial *serial, uint16_t value) { struct usb_setup_packet *setup; - if (!ftdi_class || !ftdi_class->hport) { + if (!serial || !serial->hport) { return -USB_ERR_INVAL; } - setup = ftdi_class->hport->setup; + setup = serial->hport->setup; setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_SET_LATENCY_TIMER_REQUEST; + setup->bRequest = FTDI_SIO_SET_LATENCY_TIMER; setup->wValue = value; - setup->wIndex = ftdi_class->intf; + setup->wIndex = serial->intf; setup->wLength = 0; - return usbh_control_transfer(ftdi_class->hport, setup, NULL); + return usbh_control_transfer(serial->hport, setup, NULL); } -static int usbh_ftdi_set_flow_ctrl(struct usbh_ftdi *ftdi_class, uint16_t value) +static int usbh_ftdi_attach(struct usbh_serial *serial) { - struct usb_setup_packet *setup; - - if (!ftdi_class || !ftdi_class->hport) { - return -USB_ERR_INVAL; - } - setup = ftdi_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_SET_FLOW_CTRL_REQUEST; - setup->wValue = value; - setup->wIndex = ftdi_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(ftdi_class->hport, setup, NULL); -} - -static int usbh_ftdi_read_modem_status(struct usbh_ftdi *ftdi_class) -{ - struct usb_setup_packet *setup; - int ret; - - if (!ftdi_class || !ftdi_class->hport) { - return -USB_ERR_INVAL; - } - setup = ftdi_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; - setup->bRequest = SIO_POLL_MODEM_STATUS_REQUEST; - setup->wValue = 0x0000; - setup->wIndex = ftdi_class->intf; - setup->wLength = 2; - - ret = usbh_control_transfer(ftdi_class->hport, setup, g_ftdi_buf); - if (ret < 0) { - return ret; - } - memcpy(ftdi_class->modem_status, g_ftdi_buf, 2); - return ret; -} - -int usbh_ftdi_set_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding) -{ - memcpy((uint8_t *)&ftdi_class->line_coding, line_coding, sizeof(struct cdc_line_coding)); - - int ret = usbh_ftdi_set_baudrate(ftdi_class, line_coding->dwDTERate); - if (ret < 0) { - return ret; - } - return usbh_ftdi_set_data_format(ftdi_class, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat, 0); -} - -int usbh_ftdi_get_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding) -{ - memcpy(line_coding, (uint8_t *)&ftdi_class->line_coding, sizeof(struct cdc_line_coding)); - return 0; -} - -int usbh_ftdi_set_line_state(struct usbh_ftdi *ftdi_class, bool dtr, bool rts) -{ - int ret; - - if (dtr) { - usbh_ftdi_set_modem(ftdi_class, SIO_SET_DTR_HIGH); - } else { - usbh_ftdi_set_modem(ftdi_class, SIO_SET_DTR_LOW); - } - - if (rts) { - ret = usbh_ftdi_set_modem(ftdi_class, SIO_SET_RTS_HIGH); - } else { - ret = usbh_ftdi_set_modem(ftdi_class, SIO_SET_RTS_LOW); - } - - return ret; -} - -static int usbh_ftdi_connect(struct usbh_hubport *hport, uint8_t intf) -{ - struct usb_endpoint_descriptor *ep_desc; - int ret = 0; uint16_t version; + uint8_t chip_type; + int ret; - struct usbh_ftdi *ftdi_class = usbh_ftdi_class_alloc(); - if (ftdi_class == NULL) { - USB_LOG_ERR("Fail to alloc ftdi_class\r\n"); - return -USB_ERR_NOMEM; - } - - ftdi_class->hport = hport; - ftdi_class->intf = intf; - - hport->config.intf[intf].priv = ftdi_class; - - version = hport->device_desc.bcdDevice; + version = serial->hport->device_desc.bcdDevice; switch (version) { case 0x400: - ftdi_class->chip_type = FT232B; + chip_type = FT232B; break; case 0x500: - ftdi_class->chip_type = FT2232C; + chip_type = FT2232C; break; case 0x600: - ftdi_class->chip_type = FT232R; + chip_type = FT232R; break; case 0x700: - ftdi_class->chip_type = FT2232H; - break; - case 0x800: - ftdi_class->chip_type = FT4232H; + chip_type = FT2232H; break; case 0x900: - ftdi_class->chip_type = FT232H; + chip_type = FT232H; break; default: - USB_LOG_ERR("Unknown FTDI chip version:%04x\r\n", version); + USB_LOG_ERR("Unsupported FTDI chip version: 0x%04x\r\n", version); return -USB_ERR_NOTSUPP; } - USB_LOG_INFO("FTDI chip name:%s\r\n", ftdi_chip_name[ftdi_class->chip_type]); + USB_LOG_INFO("chip name: %s\r\n", ftdi_chip_name[chip_type]); - usbh_ftdi_reset(ftdi_class); - usbh_ftdi_set_flow_ctrl(ftdi_class, SIO_DISABLE_FLOW_CTRL); - usbh_ftdi_set_latency_timer(ftdi_class, 0x10); - usbh_ftdi_read_modem_status(ftdi_class); - USB_LOG_INFO("modem status:%02x:%02x\r\n", ftdi_class->modem_status[0], ftdi_class->modem_status[1]); - - for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { - ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + struct usbh_ftdi *ftdi_class = usb_osal_malloc(sizeof(struct usbh_ftdi)); + if (!ftdi_class) { + USB_LOG_ERR("No memory for ftdi_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(ftdi_class, 0, sizeof(struct usbh_ftdi)); + serial->priv = ftdi_class; - if (ep_desc->bEndpointAddress & 0x80) { - USBH_EP_INIT(ftdi_class->bulkin, ep_desc); - } else { - USBH_EP_INIT(ftdi_class->bulkout, ep_desc); - } + ftdi_class->chip_type = chip_type; + ret = usbh_ftdi_set_latency_timer(serial, 0x10); + if (ret < 0) { + goto errout; } + return 0; +errout: + serial->priv = NULL; + usb_osal_free(ftdi_class); + return ret; +} - snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, ftdi_class->minor); +static void usbh_ftdi_detach(struct usbh_serial *serial) +{ + if (serial && serial->priv) { + serial->priv = NULL; + usb_osal_free(serial->priv); + } +} - USB_LOG_INFO("Register FTDI Class:%s\r\n", hport->config.intf[intf].devname); +static int usbh_ftdi_set_flow_ctrl(struct usbh_serial *serial, bool hardctrl) +{ + struct usb_setup_packet *setup; -#if 0 - USB_LOG_INFO("Test ftdi rx and tx and rx for 5 times, baudrate is 115200\r\n"); + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; - struct cdc_line_coding linecoding; - uint8_t count = 5; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_FLOW_CTRL; + setup->wValue = hardctrl ? FTDI_SIO_RTS_CTS_HS : FTDI_SIO_DISABLE_FLOW_CTRL; + setup->wIndex = serial->intf; + setup->wLength = 0; - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_ftdi_set_line_coding(ftdi_class, &linecoding); - usbh_ftdi_set_line_state(ftdi_class, true, false); + return usbh_control_transfer(serial->hport, setup, NULL); +} - memset(g_ftdi_buf, 'a', sizeof(g_ftdi_buf)); - ret = usbh_ftdi_bulk_out_transfer(ftdi_class, g_ftdi_buf, sizeof(g_ftdi_buf), 0xfffffff); - USB_LOG_RAW("out ret:%d\r\n", ret); - while (count--) { - ret = usbh_ftdi_bulk_in_transfer(ftdi_class, g_ftdi_buf, sizeof(g_ftdi_buf), 0xfffffff); - USB_LOG_RAW("in ret:%d\r\n", ret); - if (ret > 0) { - for (uint32_t i = 0; i < ret; i++) { - USB_LOG_RAW("%02x ", g_ftdi_buf[i]); - } - } - USB_LOG_RAW("\r\n"); +static int usbh_ftdi_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + int ret = usbh_ftdi_set_baudrate(serial, line_coding->dwDTERate); + if (ret < 0) { + return ret; } -#endif - usbh_ftdi_run(ftdi_class); - return ret; + return usbh_ftdi_set_data_format(serial, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat, 0); } -static int usbh_ftdi_disconnect(struct usbh_hubport *hport, uint8_t intf) +static int usbh_ftdi_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) { - int ret = 0; - - struct usbh_ftdi *ftdi_class = (struct usbh_ftdi *)hport->config.intf[intf].priv; - - if (ftdi_class) { - if (ftdi_class->bulkin) { - usbh_kill_urb(&ftdi_class->bulkin_urb); - } + struct usb_setup_packet *setup; + uint16_t value = 0; - if (ftdi_class->bulkout) { - usbh_kill_urb(&ftdi_class->bulkout_urb); - } + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; - if (hport->config.intf[intf].devname[0] != '\0') { - usb_osal_thread_schedule_other(); - USB_LOG_INFO("Unregister FTDI Class:%s\r\n", hport->config.intf[intf].devname); - usbh_ftdi_stop(ftdi_class); - } + value = ((dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | (rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); - usbh_ftdi_class_free(ftdi_class); - } + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_SET_MODEM_CTRL; + setup->wValue = value; + setup->wIndex = serial->intf; + setup->wLength = 0; - return ret; + return usbh_control_transfer(serial->hport, setup, NULL); } -int usbh_ftdi_bulk_in_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +static int usbh_ftdi_get_modem_status(struct usbh_serial *serial) { + struct usb_setup_packet *setup; + uint16_t status = 0; int ret; - struct usbh_urb *urb = &ftdi_class->bulkin_urb; - usbh_bulk_urb_fill(urb, ftdi_class->hport, ftdi_class->bulkin, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; } - return ret; -} -int usbh_ftdi_bulk_out_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &ftdi_class->bulkout_urb; + setup = serial->hport->setup; - usbh_bulk_urb_fill(urb, ftdi_class->hport, ftdi_class->bulkout, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = FTDI_SIO_GET_MODEM_STATUS; + setup->wValue = 0x0000; + setup->wIndex = serial->intf; + setup->wLength = 2; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return 0; } - return ret; + + status = (serial->iobuffer[0] & FTDI_SIO_DSR_MASK ? USBH_SERIAL_TIOCM_DSR : 0) | + (serial->iobuffer[0] & FTDI_SIO_CTS_MASK ? USBH_SERIAL_TIOCM_CTS : 0) | + (serial->iobuffer[0] & FTDI_SIO_RI_MASK ? USBH_SERIAL_TIOCM_RI : 0) | + (serial->iobuffer[0] & FTDI_SIO_RLSD_MASK ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + return status; } -__WEAK void usbh_ftdi_run(struct usbh_ftdi *ftdi_class) +static const struct usbh_serial_driver ftdi_driver = { + .driver_name = "ftdi", + + .ignore_rx_header = 2, + .ignore_tx_header = 0, + + .attach = usbh_ftdi_attach, + .detach = usbh_ftdi_detach, + .set_flow_control = usbh_ftdi_set_flow_ctrl, + .set_line_coding = usbh_ftdi_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_ftdi_set_line_state, + .get_modem_status = usbh_ftdi_get_modem_status, +}; + +static int usbh_ftdi_connect(struct usbh_hubport *hport, uint8_t intf) { - (void)ftdi_class; + return usbh_serial_probe(hport, intf, &ftdi_driver) ? 0 : -USB_ERR_NOMEM; } -__WEAK void usbh_ftdi_stop(struct usbh_ftdi *ftdi_class) +static int usbh_ftdi_disconnect(struct usbh_hubport *hport, uint8_t intf) { - (void)ftdi_class; + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; } static const uint16_t ftdi_id_table[][2] = { { 0x0403, 0x6001 }, { 0x0403, 0x6010 }, + { 0x0403, 0x6014 }, { 0, 0 }, }; diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_ftdi.h b/components/drivers/usb/cherryusb/class/serial/usbh_ftdi.h new file mode 100644 index 0000000000..0d176299ee --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_ftdi.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_FTDI_H +#define USBH_FTDI_H + +#include "usb_cdc.h" + +#define FTDI_VID 0x0403 /* Vendor Id */ + +/* FTDI device PIDs */ +#define FTDI_8U232AM_PID 0x6001 /* Similar device to SIO above */ +#define FTDI_8U232AM_ALT_PID 0x6006 /* FTDI's alternate PID for above */ +#define FTDI_8U2232C_PID 0x6010 /* Dual channel device */ +#define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */ +#define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */ +#define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */ +#define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */ +#define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */ +#define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */ +#define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */ +#define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */ +#define FTDI_FT232HP_PID 0x6045 /* Dual channel hi-speed device with PD */ +#define FTDI_FT4232HA_PID 0x6048 /* Quad channel automotive grade hi-speed device */ +#define FTDI_SIO_PID 0x8372 /* Product Id SIO application of 8U100AX */ +#define FTDI_232RL_PID 0xFBFA /* Product ID for FT232RL */ + +/* Requests */ +#define FTDI_SIO_RESET 0x00 /* Reset the port */ +#define FTDI_SIO_SET_MODEM_CTRL 0x01 /* Set the modem control register */ +#define FTDI_SIO_SET_FLOW_CTRL 0x02 /* Set flow control register */ +#define FTDI_SIO_SET_BAUDRATE 0x03 /* Set baud rate */ +#define FTDI_SIO_SET_DATA 0x04 /* Set the data characteristics of the port */ +#define FTDI_SIO_GET_MODEM_STATUS 0x05 +#define FTDI_SIO_SET_EVENT_CHAR 0x06 +#define FTDI_SIO_SET_ERROR_CHAR 0x07 +#define FTDI_SIO_SET_LATENCY_TIMER 0x09 +#define FTDI_SIO_GET_LATENCY_TIMER 0x0A +#define FTDI_SIO_SET_BITMODE 0x0B +#define FTDI_SIO_READ_PINS 0x0C +#define FTDI_SIO_READ_EEPROM 0x90 +#define FTDI_SIO_WRITE_EEPROM 0x91 +#define FTDI_SIO_ERASE_EEPROM 0x92 + +/* Channel indices for FT2232, FT2232H and FT4232H devices */ +#define FTDI_SIO_CHANNEL_A 1 +#define FTDI_SIO_CHANNEL_B 2 +#define FTDI_SIO_CHANNEL_C 3 +#define FTDI_SIO_CHANNEL_D 4 + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_RESET + * wValue: Control Value + * 0 = Reset SIO + * 1 = Purge RX buffer + * 2 = Purge TX buffer + * wIndex: Port + * wLength: 0 + * Data: None + * + * The Reset SIO command has this effect: + * + * Sets flow control set to 'none' + * Event char = $0D + * Event trigger = disabled + * Purge RX buffer + * Purge TX buffer + * Clear DTR + * Clear RTS + * baud and data format not reset + * + * The Purge RX and TX buffer commands affect nothing except the buffers + * + */ + +#define FTDI_SIO_RESET_SIO 0 +#define FTDI_SIO_RESET_PURGE_RX 1 +#define FTDI_SIO_RESET_PURGE_TX 2 + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_BAUDRATE + * wValue: BaudDivisor value - see below + * wIndex: Port + * wLength: 0 + * Data: None + * The BaudDivisor values are calculated as follows: + * - BaseClock is either 12000000 or 48000000 depending on the device. + * FIXME: I wish I knew how to detect old chips to select proper base clock! + * - BaudDivisor is a fixed point number encoded in a funny way. + * (--WRONG WAY OF THINKING--) + * BaudDivisor is a fixed point number encoded with following bit weighs: + * (-2)(-1)(13..0). It is a radical with a denominator of 4, so values + * end with 0.0 (00...), 0.25 (10...), 0.5 (01...), and 0.75 (11...). + * (--THE REALITY--) + * The both-bits-set has quite different meaning from 0.75 - the chip + * designers have decided it to mean 0.125 instead of 0.75. + * This info looked up in FTDI application note "FT8U232 DEVICES \ Data Rates + * and Flow Control Consideration for USB to RS232". + * - BaudDivisor = (BaseClock / 16) / BaudRate, where the (=) operation should + * automagically re-encode the resulting value to take fractions into + * consideration. + * As all values are integers, some bit twiddling is in order: + * BaudDivisor = (BaseClock / 16 / BaudRate) | + * (((BaseClock / 2 / BaudRate) & 4) ? 0x4000 // 0.5 + * : ((BaseClock / 2 / BaudRate) & 2) ? 0x8000 // 0.25 + * : ((BaseClock / 2 / BaudRate) & 1) ? 0xc000 // 0.125 + * : 0) + * + * For the FT232BM, a 17th divisor bit was introduced to encode the multiples + * of 0.125 missing from the FT8U232AM. Bits 16 to 14 are coded as follows + * (the first four codes are the same as for the FT8U232AM, where bit 16 is + * always 0): + * 000 - add .000 to divisor + * 001 - add .500 to divisor + * 010 - add .250 to divisor + * 011 - add .125 to divisor + * 100 - add .375 to divisor + * 101 - add .625 to divisor + * 110 - add .750 to divisor + * 111 - add .875 to divisor + * Bits 15 to 0 of the 17-bit divisor are placed in the urb value. Bit 16 is + * placed in bit 0 of the urb index. + * + * Note that there are a couple of special cases to support the highest baud + * rates. If the calculated divisor value is 1, this needs to be replaced with + * 0. Additionally for the FT232BM, if the calculated divisor value is 0x4001 + * (1.5), this needs to be replaced with 0x0001 (1) (but this divisor value is + * not supported by the FT8U232AM). + */ + +enum ftdi_sio_baudrate { + ftdi_sio_b300 = 0, + ftdi_sio_b600 = 1, + ftdi_sio_b1200 = 2, + ftdi_sio_b2400 = 3, + ftdi_sio_b4800 = 4, + ftdi_sio_b9600 = 5, + ftdi_sio_b19200 = 6, + ftdi_sio_b38400 = 7, + ftdi_sio_b57600 = 8, + ftdi_sio_b115200 = 9 +}; + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_SET_DATA + * wValue: Data characteristics (see below) + * wIndex: Port + * wLength: 0 + * Data: No + * + * Data characteristics + * + * B0..7 Number of data bits + * B8..10 Parity + * 0 = None + * 1 = Odd + * 2 = Even + * 3 = Mark + * 4 = Space + * B11..13 Stop Bits + * 0 = 1 + * 1 = 1.5 + * 2 = 2 + * B14 + * 1 = TX ON (break) + * 0 = TX OFF (normal state) + * B15 Reserved + * + */ + +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) + +/* + * BmRequestType: 0100 0000B + * bRequest: FTDI_SIO_MODEM_CTRL + * wValue: ControlValue (see below) + * wIndex: Port + * wLength: 0 + * Data: None + * + * NOTE: If the device is in RTS/CTS flow control, the RTS set by this + * command will be IGNORED without an error being returned + * Also - you can not set DTR and RTS with one control message + * + * ControlValue + * B0 DTR state + * 0 = reset + * 1 = set + * B1 RTS state + * 0 = reset + * 1 = set + * B2..7 Reserved + * B8 DTR state enable + * 0 = ignore + * 1 = use DTR state + * B9 RTS state enable + * 0 = ignore + * 1 = use RTS state + * B10..15 Reserved + * + */ + +#define FTDI_SIO_SET_DTR_MASK 0x1 +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) +#define FTDI_SIO_SET_RTS_MASK 0x2 +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) + +/* + * BmRequestType: 0100 0000b + * bRequest: FTDI_SIO_SET_FLOW_CTRL + * wValue: Xoff/Xon + * wIndex: Protocol/Port - hIndex is protocol / lIndex is port + * wLength: 0 + * Data: None + * + * hIndex protocol is: + * B0 Output handshaking using RTS/CTS + * 0 = disabled + * 1 = enabled + * B1 Output handshaking using DTR/DSR + * 0 = disabled + * 1 = enabled + * B2 Xon/Xoff handshaking + * 0 = disabled + * 1 = enabled + * + * A value of zero in the hIndex field disables handshaking + * + * If Xon/Xoff handshaking is specified, the hValue field should contain the + * XOFF character and the lValue field contains the XON character. + */ + +#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 +#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) +#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) +#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) + +/* + * BmRequestType: 1100 0000b + * bRequest: FTDI_SIO_GET_MODEM_STATUS + * wValue: zero + * wIndex: Port + * wLength: 1 + * Data: Status + * + * One byte of data is returned + * B0..3 0 + * B4 CTS + * 0 = inactive + * 1 = active + * B5 DSR + * 0 = inactive + * 1 = active + * B6 Ring Indicator (RI) + * 0 = inactive + * 1 = active + * B7 Receive Line Signal Detect (RLSD) + * 0 = inactive + * 1 = active + */ + +#define FTDI_SIO_CTS_MASK 0x10 +#define FTDI_SIO_DSR_MASK 0x20 +#define FTDI_SIO_RI_MASK 0x40 +#define FTDI_SIO_RLSD_MASK 0x80 + +/* Possible bitmodes for FTDI_SIO_SET_BITMODE_REQUEST */ +#define FTDI_SIO_BITMODE_RESET 0x00 +#define FTDI_SIO_BITMODE_CBUS 0x20 + +/* + * IN Endpoint + * + * The device reserves the first two bytes of data on this endpoint to contain + * the current values of the modem and line status registers. In the absence of + * data, the device generates a message consisting of these two status bytes + * every 40 ms + * + * Byte 0: Modem Status + * + * Offset Description + * B0 Reserved - must be 1 + * B1 Reserved - must be 0 + * B2 Reserved - must be 0 + * B3 Reserved - must be 0 + * B4 Clear to Send (CTS) + * B5 Data Set Ready (DSR) + * B6 Ring Indicator (RI) + * B7 Receive Line Signal Detect (RLSD) + * + * Byte 1: Line Status + * + * Offset Description + * B0 Data Ready (DR) + * B1 Overrun Error (OE) + * B2 Parity Error (PE) + * B3 Framing Error (FE) + * B4 Break Interrupt (BI) + * B5 Transmitter Holding Register (THRE) + * B6 Transmitter Empty (TEMT) + * B7 Error in RCVR FIFO + * + */ +#define FTDI_RS0_CTS (1 << 4) +#define FTDI_RS0_DSR (1 << 5) +#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RLSD (1 << 7) + +#define FTDI_RS_DR 1 +#define FTDI_RS_OE (1 << 1) +#define FTDI_RS_PE (1 << 2) +#define FTDI_RS_FE (1 << 3) +#define FTDI_RS_BI (1 << 4) +#define FTDI_RS_THRE (1 << 5) +#define FTDI_RS_TEMT (1 << 6) +#define FTDI_RS_FIFO (1 << 7) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_FTDI_H */ diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_gsm.c b/components/drivers/usb/cherryusb/class/serial/usbh_gsm.c new file mode 100644 index 0000000000..6341873660 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_gsm.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_gsm" +#include "usb_log.h" + +struct usbh_gsm { + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +static int usbh_gsm_attach(struct usbh_serial *serial) +{ + struct usb_endpoint_descriptor *ep_desc; + + struct usbh_gsm *gsm_class = usb_osal_malloc(sizeof(struct usbh_gsm)); + if (!gsm_class) { + USB_LOG_ERR("No memory for gsm_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(gsm_class, 0, sizeof(struct usbh_gsm)); + serial->priv = gsm_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(gsm_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!gsm_class->intin) { + USB_LOG_WRN("Do not find interrupt endpoint, so disable modem status monitor\r\n"); + } + return 0; +} + +static void usbh_gsm_detach(struct usbh_serial *serial) +{ + struct usbh_gsm *gsm_class; + + if (!serial || !serial->priv) { + return; + } + + gsm_class = (struct usbh_gsm *)serial->priv; + if (gsm_class->intin) { + usbh_kill_urb(&gsm_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(gsm_class); +} + +static int usbh_gsm_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + return 0; +} + +static int usbh_gsm_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + return 0; +} + +static const struct usbh_serial_driver gsm_driver = { + .driver_name = "gsm", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_gsm_attach, + .detach = usbh_gsm_detach, + .set_flow_control = NULL, + .set_line_coding = usbh_gsm_set_line_coding, + .get_line_coding = NULL, + .set_line_state = usbh_gsm_set_line_state, + .get_modem_status = NULL, +}; + +static int usbh_gsm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &gsm_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_gsm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + return 0; +} + +const struct usbh_class_driver gsm_class_driver = { + .driver_name = "gsm", + .connect = usbh_gsm_connect, + .disconnect = usbh_gsm_disconnect +}; + +static const uint16_t gsm_id_table[][2] = { + { 0x2C7C, 0x0120 }, /* Quectel EC20 */ + { 0x2C7C, 0x0121 }, /* Quectel EC21 */ + { 0x2C7C, 0x0125 }, /* Quectel EC25 */ + { 0x2C7C, 0x0191 }, /* Quectel EG91 */ + { 0x2C7C, 0x0195 }, /* Quectel EG95 */ + { 0x2C7C, 0x6002 }, /* Quectel EC200/EC600/EC800/EG91x */ + { 0x1E0E, 0x9001 }, /* SIMCOM SIM7600 */ + { 0x2ECC, 0x3012 }, /* Chinamobile ML307R */ + { 0, 0 }, +}; + +CLASS_INFO_DEFINE const struct usbh_class_info gsm_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = gsm_id_table, + .class_driver = &gsm_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_pl2303.c b/components/drivers/usb/cherryusb/class/serial/usbh_pl2303.c new file mode 100644 index 0000000000..062f8128fd --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_pl2303.c @@ -0,0 +1,726 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * Copyright (c) 2024, Derek Konigsberg + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" +#include "usbh_pl2303.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_pl2303" +#include "usb_log.h" + +#define UART_STATE_INDEX 8 +#define UART_STATE_MSR_MASK 0x8b +#define UART_STATE_TRANSIENT_MASK 0x74 +#define UART_DCD 0x01 +#define UART_DSR 0x02 +#define UART_BREAK_ERROR 0x04 +#define UART_RING 0x08 +#define UART_FRAME_ERROR 0x10 +#define UART_PARITY_ERROR 0x20 +#define UART_OVERRUN_ERROR 0x40 +#define UART_CTS 0x80 + +struct pl2303_type_data { + const char *name; + uint32_t max_baud_rate; + unsigned long quirks; + unsigned int no_autoxonxoff : 1; + unsigned int no_divisors : 1; + unsigned int alt_divisors : 1; +}; + +enum pl2303_type { + TYPE_H, + TYPE_HX, + TYPE_TA, + TYPE_TB, + TYPE_HXD, + TYPE_HXN, + TYPE_COUNT +}; + +struct usbh_pl2303 { + enum pl2303_type chip_type; + uint32_t quirks; + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + struct usb_osal_timer *modem_timer; + uint16_t modem_status; +}; + +static const struct pl2303_type_data pl2303_type_data[TYPE_COUNT] = { + [TYPE_H] = { + .name = "PL2303H", + .max_baud_rate = 1228800, + .quirks = PL2303_QUIRK_LEGACY, + .no_autoxonxoff = true, + }, + [TYPE_HX] = { + .name = "PL2303HX", + .max_baud_rate = 6000000, + }, + [TYPE_TA] = { + .name = "PL2303TA", + .max_baud_rate = 6000000, + .alt_divisors = true, + }, + [TYPE_TB] = { + .name = "PL2303TB", + .max_baud_rate = 12000000, + .alt_divisors = true, + }, + [TYPE_HXD] = { + .name = "PL2303HXD", + .max_baud_rate = 12000000, + }, + [TYPE_HXN] = { + .name = "PL2303G", + .max_baud_rate = 12000000, + .no_divisors = true, + }, +}; + +/* + * Returns the nearest supported baud rate that can be set directly without + * using divisors. + */ +static uint32_t pl2303_get_supported_baud_rate(uint32_t baud) +{ + static const uint32_t baud_sup[] = { + 75, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, + 14400, 19200, 28800, 38400, 57600, 115200, 230400, 460800, + 614400, 921600, 1228800, 2457600, 3000000, 6000000 + }; + + unsigned i; + + for (i = 0; i < ARRAY_SIZE(baud_sup); ++i) { + if (baud_sup[i] > baud) + break; + } + + if (i == ARRAY_SIZE(baud_sup)) + baud = baud_sup[i - 1]; + else if (i > 0 && (baud_sup[i] - baud) > (baud - baud_sup[i - 1])) + baud = baud_sup[i - 1]; + else + baud = baud_sup[i]; + + return baud; +} + +/* + * NOTE: If unsupported baud rates are set directly, the PL2303 seems to + * use 9600 baud. + */ +static uint32_t pl2303_encode_baud_rate_direct(unsigned char buf[4], + uint32_t baud) +{ + memcpy(buf, &baud, 4); + + return baud; +} + +static uint32_t pl2303_encode_baud_rate_divisor_alt(unsigned char buf[4], + uint32_t baud) +{ + unsigned int baseline, mantissa, exponent; + + /* + * Apparently, for the TA version the formula is: + * baudrate = 12M * 32 / (mantissa * 2^exponent) + * where + * mantissa = buf[10:0] + * exponent = buf[15:13 16] + */ + baseline = 12000000 * 32; + mantissa = baseline / baud; + if (mantissa == 0) + mantissa = 1; /* Avoid dividing by zero if baud > 32*12M. */ + exponent = 0; + while (mantissa >= 2048) { + if (exponent < 15) { + mantissa >>= 1; /* divide by 2 */ + exponent++; + } else { + /* Exponent is maxed. Trim mantissa and leave. */ + mantissa = 2047; + break; + } + } + + buf[3] = 0x80; + buf[2] = exponent & 0x01; + buf[1] = (exponent & ~0x01) << 4 | mantissa >> 8; + buf[0] = mantissa & 0xff; + + /* Calculate and return the exact baud rate. */ + baud = (baseline / mantissa) >> exponent; + + return baud; +} + +static uint32_t pl2303_encode_baud_rate_divisor(unsigned char buf[4], + uint32_t baud) +{ + unsigned int baseline, mantissa, exponent; + + /* + * Apparently the formula is: + * baudrate = 12M * 32 / (mantissa * 4^exponent) + * where + * mantissa = buf[8:0] + * exponent = buf[11:9] + */ + baseline = 12000000 * 32; + mantissa = baseline / baud; + if (mantissa == 0) + mantissa = 1; /* Avoid dividing by zero if baud > 32*12M. */ + exponent = 0; + while (mantissa >= 512) { + if (exponent < 7) { + mantissa >>= 2; /* divide by 4 */ + exponent++; + } else { + /* Exponent is maxed. Trim mantissa and leave. */ + mantissa = 511; + break; + } + } + + buf[3] = 0x80; + buf[2] = 0; + buf[1] = exponent << 1 | mantissa >> 8; + buf[0] = mantissa & 0xff; + + /* Calculate and return the exact baud rate. */ + baud = (baseline / mantissa) >> (exponent << 1); + + return baud; +} + +static int pl2303_vendor_write(struct usbh_serial *serial, uint16_t wValue, uint16_t wIndex) +{ + struct usb_setup_packet *setup; + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = pl2303_class->chip_type == TYPE_HXN ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; + setup->wValue = wValue; + setup->wIndex = wIndex; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int pl2303_vendor_read(struct usbh_serial *serial, uint16_t wValue, uint8_t *data) +{ + struct usb_setup_packet *setup; + struct usbh_pl2303 *pl2303_class; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = pl2303_class->chip_type == TYPE_HXN ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; + setup->wValue = wValue; + setup->wIndex = 0; + setup->wLength = 1; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(data, serial->iobuffer, 1); + + return ret; +} + +static bool pl2303_supports_hx_status(struct usbh_serial *serial) +{ + int ret; + uint8_t buf; + + ret = pl2303_vendor_read(serial, PL2303_READ_TYPE_HX_STATUS, &buf); + if (ret < 0) { + return false; + } + + return true; +} + +static bool pl2303_is_hxd_clone(struct usbh_serial *serial) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 7; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return false; + } + return true; +} + +static int pl2303_update_reg(struct usbh_serial *serial, uint8_t reg, uint8_t mask, uint8_t val) +{ + int ret; + uint8_t buf[1]; + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + if (pl2303_class->chip_type == TYPE_HXN) + ret = pl2303_vendor_read(serial, reg, buf); + else + ret = pl2303_vendor_read(serial, reg | 0x80, buf); + + if (ret < 0) { + return ret; + } + + *buf &= ~mask; + *buf |= val & mask; + + return pl2303_vendor_write(serial, reg, *buf); +} + +static int usbh_pl2303_get_chiptype(struct usbh_serial *serial) +{ + if (serial->hport->device_desc.bDeviceClass == 0x02) { + return TYPE_H; /* variant 0 */ + } + + if (serial->hport->device_desc.bMaxPacketSize0 != 0x40) { + if (serial->hport->device_desc.bDeviceClass == 0x00 || serial->hport->device_desc.bDeviceClass == 0xff) + return TYPE_H; /* variant 1 */ + + return TYPE_H; /* variant 0 */ + } + + switch (serial->hport->device_desc.bcdUSB) { + case 0x101: + /* USB 1.0.1? Let's assume they meant 1.1... */ + case 0x110: + switch (serial->hport->device_desc.bcdDevice) { + case 0x300: + return TYPE_HX; + case 0x400: + return TYPE_HXD; + default: + return TYPE_HX; + } + break; + case 0x200: + switch (serial->hport->device_desc.bcdDevice) { + case 0x100: /* GC */ + case 0x105: + return TYPE_HXN; + case 0x300: /* GT / TA */ + if (pl2303_supports_hx_status(serial)) + return TYPE_TA; + __attribute__((fallthrough)); + case 0x305: + case 0x400: /* GL */ + case 0x405: + return TYPE_HXN; + case 0x500: /* GE / TB */ + if (pl2303_supports_hx_status(serial)) + return TYPE_TB; + __attribute__((fallthrough)); + case 0x505: + case 0x600: /* GS */ + case 0x605: + case 0x700: /* GR */ + case 0x705: + case 0x905: /* GT-2AB */ + case 0x1005: /* GC-Q20 */ + return TYPE_HXN; + } + break; + } + + USB_LOG_ERR("Unsupported PL2303 Device\r\n"); + return -USB_ERR_NOTSUPP; +} + +static int usbh_pl2303_attach(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + struct usb_endpoint_descriptor *ep_desc; + uint8_t type; + int ret; + + ret = usbh_pl2303_get_chiptype(serial); + if (ret < 0) { + return ret; + } + + pl2303_class = usb_osal_malloc(sizeof(struct usbh_pl2303)); + if (pl2303_class == NULL) { + USB_LOG_ERR("Fail to alloc pl2303_class\r\n"); + return -USB_ERR_NOMEM; + } + memset(pl2303_class, 0, sizeof(struct usbh_pl2303)); + serial->priv = pl2303_class; + + for (uint8_t i = 0; i < serial->hport->config.intf[serial->intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &serial->hport->config.intf[serial->intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(pl2303_class->intin, ep_desc); + break; + } else { + } + } + } + + if (!pl2303_class->intin) { + USB_LOG_ERR("Failed to find interrupt endpoint\r\n"); + ret = -USB_ERR_NODEV; + goto errout; + } + + type = (uint8_t)ret; + pl2303_class->chip_type = type; + pl2303_class->quirks = pl2303_type_data[pl2303_class->chip_type].quirks; + + USB_LOG_INFO("chip type: %s\r\n", pl2303_type_data[pl2303_class->chip_type].name); + + if (type == TYPE_HXD && pl2303_is_hxd_clone(serial)) { + pl2303_class->quirks |= PL2303_QUIRK_NO_BREAK_GETLINE; + } + + if (type != TYPE_HXN) { + uint8_t buf[1]; + ret = pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_write(serial, 0x0404, 0); + ret |= pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_read(serial, 0x8383, buf); + ret |= pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_write(serial, 0x0404, 1); + ret |= pl2303_vendor_read(serial, 0x8484, buf); + ret |= pl2303_vendor_read(serial, 0x8383, buf); + ret |= pl2303_vendor_write(serial, 0, 1); + ret |= pl2303_vendor_write(serial, 1, 0); + if (pl2303_class->quirks & PL2303_QUIRK_LEGACY) + ret |= pl2303_vendor_write(serial, 2, 0x24); + else + ret |= pl2303_vendor_write(serial, 2, 0x44); + } else { + ret = 0; + } + + if (ret < 0) { + USB_LOG_ERR("pl2303 init failed\r\n"); + goto errout; + } + + return 0; +errout: + serial->priv = NULL; + usb_osal_free(pl2303_class); + return ret; +} + +static void usbh_pl2303_detach(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->priv) { + return; + } + + pl2303_class = (struct usbh_pl2303 *)serial->priv; + if (pl2303_class->intin) { + usbh_kill_urb(&pl2303_class->intin_urb); + } + serial->priv = NULL; + usb_osal_free(pl2303_class); +} + +static int usbh_pl2303_set_flow_ctrl(struct usbh_serial *serial, bool hardctrl) +{ + struct usbh_pl2303 *pl2303_class; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + if (hardctrl) { + if (pl2303_class->quirks & PL2303_QUIRK_LEGACY) { + return pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0x40); + } else if (pl2303_class->chip_type == TYPE_HXN) { + return pl2303_update_reg(serial, PL2303_HXN_FLOWCTRL_REG, + PL2303_HXN_FLOWCTRL_MASK, + PL2303_HXN_FLOWCTRL_RTS_CTS); + } else { + return pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0x60); + } + } else { + if (pl2303_class->chip_type == TYPE_HXN) { + return pl2303_update_reg(serial, PL2303_HXN_FLOWCTRL_REG, + PL2303_HXN_FLOWCTRL_MASK, + PL2303_HXN_FLOWCTRL_NONE); + } else { + return pl2303_update_reg(serial, 0, PL2303_FLOWCTRL_MASK, 0); + } + } +} + +static int usbh_pl2303_set_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + struct usbh_pl2303 *pl2303_class; + uint32_t baud; + uint32_t baud_sup; + uint8_t buf[7]; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + setup = serial->hport->setup; + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + baud = line_coding->dwDTERate; + if (pl2303_type_data[pl2303_class->chip_type].max_baud_rate) { + baud = MIN(baud, pl2303_type_data[pl2303_class->chip_type].max_baud_rate); + } + /* + * Use direct method for supported baud rates, otherwise use divisors. + * Newer chip types do not support divisor encoding. + */ + if (pl2303_type_data[pl2303_class->chip_type].no_divisors) + baud_sup = baud; + else + baud_sup = pl2303_get_supported_baud_rate(baud); + + if (baud == baud_sup) + baud = pl2303_encode_baud_rate_direct(buf, baud); + else if (pl2303_type_data[pl2303_class->chip_type].alt_divisors) + baud = pl2303_encode_baud_rate_divisor_alt(buf, baud); + else + baud = pl2303_encode_baud_rate_divisor(buf, baud); + + buf[4] = line_coding->bCharFormat; + buf[5] = line_coding->bParityType; + buf[6] = line_coding->bDataBits; + + memcpy(serial->iobuffer, buf, sizeof(struct cdc_line_coding)); + + return usbh_control_transfer(serial->hport, setup, serial->iobuffer); +} + +static int usbh_pl2303_get_line_coding(struct usbh_serial *serial, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup; + int ret; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = serial->intf; + setup->wLength = 7; + + ret = usbh_control_transfer(serial->hport, setup, serial->iobuffer); + if (ret < 0) { + return ret; + } + memcpy(line_coding, serial->iobuffer, sizeof(struct cdc_line_coding)); + return ret; +} + +static int usbh_pl2303_set_line_state(struct usbh_serial *serial, bool dtr, bool rts) +{ + struct usb_setup_packet *setup; + + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + setup = serial->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; + setup->wValue = (dtr << 0) | (rts << 1); + setup->wIndex = serial->intf; + setup->wLength = 0; + + return usbh_control_transfer(serial->hport, setup, NULL); +} + +static int usbh_pl2303_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + uintptr_t flags; + uint16_t status; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + status = (pl2303_class->modem_status & UART_DSR ? USBH_SERIAL_TIOCM_DSR : 0) | + (pl2303_class->modem_status & UART_CTS ? USBH_SERIAL_TIOCM_CTS : 0) | + (pl2303_class->modem_status & UART_RING ? USBH_SERIAL_TIOCM_RI : 0) | + (pl2303_class->modem_status & UART_DCD ? USBH_SERIAL_TIOCM_CD : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_DTR ? USBH_SERIAL_TIOCM_DTR : 0) | + (serial->line_state & USBH_SERIAL_TIOCM_RTS ? USBH_SERIAL_TIOCM_RTS : 0); + + usb_osal_leave_critical_section(flags); + + return status; +} + +#ifdef CONFIG_USBH_SERIAL_GET_MODEM_STATUS +static int __usbh_pl2303_get_modem_status(struct usbh_serial *serial) +{ + struct usbh_pl2303 *pl2303_class; + uint8_t status = 0; + uint16_t difference; + uintptr_t flags; + int ret; + + if (!serial || !serial->hport || !serial->priv) { + return -USB_ERR_INVAL; + } + pl2303_class = (struct usbh_pl2303 *)serial->priv; + + usbh_int_urb_fill(&pl2303_class->intin_urb, serial->hport, pl2303_class->intin, &serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET], pl2303_class->intin->wMaxPacketSize, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(&pl2303_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (ret < 1) { + return -USB_ERR_INVAL; + } + + flags = usb_osal_enter_critical_section(); + + status = serial->iobuffer[USBH_SERIAL_INT_NOCACHE_OFFSET]; + difference = pl2303_class->modem_status ^ status; + pl2303_class->modem_status = status; + + if (status & UART_BREAK_ERROR) + serial->iocount.brk++; + + if (difference & UART_STATE_MSR_MASK) { + if (difference & UART_CTS) + serial->iocount.cts++; + if (difference & UART_DSR) + serial->iocount.dsr++; + if (difference & UART_RING) + serial->iocount.rng++; + if (difference & UART_DCD) { + serial->iocount.dcd++; + } + } + + usb_osal_leave_critical_section(flags); + + return ret; +} +#endif + +static const struct usbh_serial_driver pl2303_driver = { + .driver_name = "pl2303", + + .ignore_rx_header = 0, + .ignore_tx_header = 0, + + .attach = usbh_pl2303_attach, + .detach = usbh_pl2303_detach, + .set_flow_control = usbh_pl2303_set_flow_ctrl, + .set_line_coding = usbh_pl2303_set_line_coding, + .get_line_coding = usbh_pl2303_get_line_coding, + .set_line_state = usbh_pl2303_set_line_state, + .get_modem_status = usbh_pl2303_get_modem_status, +}; + +static int usbh_pl2303_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return usbh_serial_probe(hport, intf, &pl2303_driver) ? 0 : -USB_ERR_NOMEM; +} + +static int usbh_pl2303_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_serial *serial = (struct usbh_serial *)hport->config.intf[intf].priv; + + if (serial) { + usbh_serial_remove(serial); + } + + return 0; +} + +static const uint16_t pl2303_id_table[][2] = { + { 0x067B, 0x2303 }, // PL2303 Serial (ATEN/IOGEAR UC232A) + { 0x067B, 0x2304 }, // PL2303HXN Serial, type TB + { 0x067B, 0x23A3 }, // PL2303HXN Serial, type GC + { 0x067B, 0x23B3 }, // PL2303HXN Serial, type GB + { 0x067B, 0x23C3 }, // PL2303HXN Serial, type GT + { 0x067B, 0x23D3 }, // PL2303HXN Serial, type GL + { 0x067B, 0x23E3 }, // PL2303HXN Serial, type GE + { 0x067B, 0x23F3 }, // PL2303HXN Serial, type GS + { 0, 0 }, +}; + +const struct usbh_class_driver pl2303_class_driver = { + .driver_name = "pl2303", + .connect = usbh_pl2303_connect, + .disconnect = usbh_pl2303_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info pl2303_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = 0xff, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = pl2303_id_table, + .class_driver = &pl2303_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_pl2303.h b/components/drivers/usb/cherryusb/class/serial/usbh_pl2303.h new file mode 100644 index 0000000000..83391c1649 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_pl2303.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 ~ 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_PL2303_H +#define USBH_PL2303_H + +#include "usb_cdc.h" + +#define PL2303_VENDOR_WRITE_REQUEST 0x01 +#define PL2303_VENDOR_WRITE_NREQUEST 0x80 +#define PL2303_VENDOR_READ_REQUEST 0x01 +#define PL2303_VENDOR_READ_NREQUEST 0x81 + +#define PL2303_FLOWCTRL_MASK 0xf0 + +#define PL2303_READ_TYPE_HX_STATUS 0x8080 + +#define PL2303_HXN_RESET_REG 0x07 +#define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02 +#define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01 + +#define PL2303_HXN_FLOWCTRL_REG 0x0a +#define PL2303_HXN_FLOWCTRL_MASK 0x1c +#define PL2303_HXN_FLOWCTRL_NONE 0x1c +#define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18 +#define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c + +#define PL2303_QUIRK_UART_STATE_IDX0 BIT(0) +#define PL2303_QUIRK_LEGACY BIT(1) +#define PL2303_QUIRK_ENDPOINT_HACK BIT(2) +#define PL2303_QUIRK_NO_BREAK_GETLINE BIT(3) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_PL2303_H */ diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_serial.c b/components/drivers/usb/cherryusb/class/serial/usbh_serial.c new file mode 100644 index 0000000000..d6361b211a --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_serial.c @@ -0,0 +1,743 @@ +/* + * Copyright (c) 2025, sakumisu + * Copyright (c) 2025, MDLZCOOL + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_serial.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_serial" +#include "usb_log.h" + +#define DEV_FORMAT_VENDOR "/dev/ttyUSB%d" +#define DEV_FORMAT_CDC_ACM "/dev/ttyACM%d" + +#define CONFIG_USBHOST_MAX_SERIAL_CLASS 4 + +static struct usbh_serial g_serial_class[CONFIG_USBHOST_MAX_SERIAL_CLASS]; + +static uint32_t g_devinuse = 0; +static uint32_t g_cdcacm_devinuse = 0; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_serial_iobuffer[CONFIG_USBHOST_MAX_SERIAL_CLASS][USB_ALIGN_UP((USBH_SERIAL_RX2_NOCACHE_OFFSET + USBH_SERIAL_RX2_NOCACHE_SIZE), CONFIG_USB_ALIGN_SIZE)]; + +/* refer to cherryrb */ +static int usbh_serial_ringbuffer_init(usbh_serial_ringbuf_t *rb, void *pool, uint32_t size) +{ + if (NULL == rb) { + return -1; + } + + if (NULL == pool) { + return -1; + } + + if ((size < 2) || (size & (size - 1))) { + return -1; + } + + rb->in = 0; + rb->out = 0; + rb->mask = size - 1; + rb->pool = pool; + + return 0; +} + +static void usbh_serial_ringbuffer_reset(usbh_serial_ringbuf_t *rb) +{ + rb->in = 0; + rb->out = 0; +} + +static uint32_t usbh_serial_ringbuffer_get_used(usbh_serial_ringbuf_t *rb) +{ + return rb->in - rb->out; +} + +static uint32_t usbh_serial_ringbuffer_write(usbh_serial_ringbuf_t *rb, void *data, uint32_t size) +{ + uint32_t unused; + uint32_t offset; + uint32_t remain; + + unused = (rb->mask + 1) - (rb->in - rb->out); + + if (size > unused) { + size = unused; + } + + offset = rb->in & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > size ? size : remain; + + memcpy(((uint8_t *)(rb->pool)) + offset, data, remain); + memcpy(rb->pool, (uint8_t *)data + remain, size - remain); + + rb->in += size; + + return size; +} + +static uint32_t usbh_serial_ringbuffer_peek(usbh_serial_ringbuf_t *rb, void *data, uint32_t size) +{ + uint32_t used; + uint32_t offset; + uint32_t remain; + + used = rb->in - rb->out; + if (size > used) { + size = used; + } + + offset = rb->out & rb->mask; + + remain = rb->mask + 1 - offset; + remain = remain > size ? size : remain; + + memcpy(data, ((uint8_t *)(rb->pool)) + offset, remain); + memcpy((uint8_t *)data + remain, rb->pool, size - remain); + + return size; +} + +static uint32_t usbh_serial_ringbuffer_read(usbh_serial_ringbuf_t *rb, void *data, uint32_t size) +{ + size = usbh_serial_ringbuffer_peek(rb, data, size); + rb->out += size; + return size; +} + +static struct usbh_serial *usbh_serial_alloc(bool is_cdcacm) +{ + uint8_t devno; + uint8_t devno2; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_SERIAL_CLASS; devno++) { + if ((g_devinuse & (1U << devno)) == 0) { + g_devinuse |= (1U << devno); + memset(&g_serial_class[devno], 0, sizeof(struct usbh_serial)); + g_serial_class[devno].minor = devno; + g_serial_class[devno].cdc_minor = -1; + g_serial_class[devno].iobuffer = g_serial_iobuffer[devno]; + g_serial_class[devno].rx_complete_sem = usb_osal_sem_create(0); + + if (is_cdcacm) { + for (devno2 = 0; devno2 < CONFIG_USBHOST_MAX_SERIAL_CLASS; devno2++) { + if ((g_cdcacm_devinuse & (1U << devno2)) == 0) { + g_cdcacm_devinuse |= (1U << devno2); + g_serial_class[devno].cdc_minor = devno2; + return &g_serial_class[devno]; + } + } + + g_devinuse &= ~(1U << devno); + return NULL; + } else { + return &g_serial_class[devno]; + } + } + } + return NULL; +} + +static void usbh_serial_free(struct usbh_serial *serial) +{ + uint8_t devno = serial->minor; + if (devno < 32) { + g_devinuse &= ~(1U << devno); + } + + if (serial->cdc_minor >= 0) { + g_cdcacm_devinuse &= ~(1U << serial->cdc_minor); + } + + if (g_serial_class[devno].rx_complete_sem) { + usb_osal_sem_delete(g_serial_class[devno].rx_complete_sem); + } +} + +static void usbh_serial_callback(void *arg, int nbytes) +{ + struct usbh_serial *serial = (struct usbh_serial *)arg; + int ret; + + if (nbytes < 0) { + if (nbytes != -USB_ERR_SHUTDOWN) { + USB_LOG_ERR("serial transfer error: %d\n", nbytes); + } + serial->rx_errorcode = nbytes; + usb_osal_sem_give(serial->rx_complete_sem); + return; + } + + if (nbytes < serial->driver->ignore_rx_header) { + USB_LOG_ERR("serial rx short packet: %d\n", nbytes); + serial->rx_errorcode = -USB_ERR_IO; + usb_osal_sem_give(serial->rx_complete_sem); + return; + } + + if (nbytes >= serial->driver->ignore_rx_header) { + /* resubmit the read urb */ + usbh_bulk_urb_fill(&serial->bulkin_urb, serial->hport, serial->bulkin, &serial->iobuffer[serial->rx_buf_index ? USBH_SERIAL_RX_NOCACHE_OFFSET : USBH_SERIAL_RX2_NOCACHE_OFFSET], serial->bulkin->wMaxPacketSize, + 0, usbh_serial_callback, serial); + ret = usbh_submit_urb(&serial->bulkin_urb); + if (ret < 0) { + USB_LOG_ERR("serial submit failed: %d\n", ret); + serial->rx_errorcode = ret; + usb_osal_sem_give(serial->rx_complete_sem); + return; + } + + usbh_serial_ringbuffer_write(&serial->rx_rb, + &serial->iobuffer[(serial->rx_buf_index ? USBH_SERIAL_RX2_NOCACHE_OFFSET : USBH_SERIAL_RX_NOCACHE_OFFSET) + serial->driver->ignore_rx_header], + (nbytes - serial->driver->ignore_rx_header)); + + if (serial->rx_complete_callback) { + serial->rx_complete_callback(serial, nbytes - serial->driver->ignore_rx_header); + } + serial->rx_buf_index ^= 1; + serial->rx_errorcode = 0; + usb_osal_sem_give(serial->rx_complete_sem); + } +} + +struct usbh_serial *usbh_serial_probe(struct usbh_hubport *hport, uint8_t intf, + const struct usbh_serial_driver *driver) +{ + struct usb_endpoint_descriptor *ep_desc; + struct usbh_serial *serial; + bool is_cdcacm = false; + int ret; + + if (strcmp(driver->driver_name, "cdc_acm") == 0) { + is_cdcacm = true; + } + + serial = usbh_serial_alloc(is_cdcacm); + if (serial == NULL) { + USB_LOG_ERR("Fail to alloc serial class\r\n"); + return NULL; + } + + serial->hport = hport; + serial->intf = intf; + serial->driver = driver; + + if (driver->attach) { + ret = driver->attach(serial); + if (ret < 0) { + USB_LOG_ERR("Serial attach failed: %d\r\n", ret); + usbh_serial_free(serial); + return NULL; + } + } + + if (is_cdcacm) { + intf = intf + 1; /* data interface */ + } + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_BULK) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(serial->bulkin, ep_desc); + } else { + USBH_EP_INIT(serial->bulkout, ep_desc); + } + } + } + + if (is_cdcacm) { + intf = intf - 1; /* data interface */ + } + + if (!serial->bulkin || !serial->bulkout) { + USB_LOG_ERR("Serial bulk in/out endpoint not found\r\n"); + usbh_serial_free(serial); + return NULL; + } + + if (is_cdcacm) { + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT_CDC_ACM, serial->cdc_minor); + } else { + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT_VENDOR, serial->minor); + } + + hport->config.intf[intf].priv = serial; + USB_LOG_INFO("Register Serial Class: %s (%s)\r\n", hport->config.intf[intf].devname, driver->driver_name); + + usbh_serial_run(serial); + + return serial; +} + +void usbh_serial_remove(struct usbh_serial *serial) +{ + if (!serial || !serial->hport) + return; + + usbh_serial_close(serial); + + if (serial->driver && serial->driver->detach) { + serial->driver->detach(serial); + } + + if (serial->hport->config.intf[serial->intf].priv) { + usb_osal_thread_schedule_other(); + USB_LOG_INFO("Unregister Serial Class: %s (%s)\r\n", serial->hport->config.intf[serial->intf].devname, serial->driver->driver_name); + usbh_serial_stop(serial); + } + + usbh_serial_free(serial); +} + +struct usbh_serial *usbh_serial_open(const char *devname, uint32_t open_flags) +{ + struct usbh_serial *serial; + int ret; + + serial = usbh_find_class_instance(devname); + if (!serial) { + return NULL; + } + + if (serial->ref_count != 0) { + USB_LOG_ERR("Device busy: %s\r\n", devname); + return NULL; + } + + if (serial && serial->driver && serial->driver->open) { + ret = serial->driver->open(serial); + if (ret < 0) { + return NULL; + } + } + + usbh_serial_ringbuffer_init(&serial->rx_rb, serial->rx_rb_pool, CONFIG_USBHOST_SERIAL_RX_SIZE); + + serial->ref_count++; + serial->open_flags = open_flags; + + return serial; +} + +int usbh_serial_close(struct usbh_serial *serial) +{ + if (!serial || !serial->hport) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return 0; + } + + if (serial->bulkin) { + usbh_kill_urb(&serial->bulkin_urb); + } + if (serial->bulkout) { + usbh_kill_urb(&serial->bulkout_urb); + } + + if (serial && serial->driver && serial->driver->set_flow_control && serial->rtscts) { + serial->driver->set_flow_control(serial, false); + } + + if (serial && serial->driver && serial->driver->close) { + serial->driver->close(serial); + } + + serial->ref_count--; + serial->rtscts = false; + + return 0; +} + +static int usbh_serial_tiocmset(struct usbh_serial *serial, uint32_t set, uint32_t clear) +{ + int ret; + uint16_t line_state; + bool dtr; + bool rts; + + if (!serial || !serial->hport || !serial->hport->connected) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + line_state = serial->line_state; + clear &= ~set; /* 'set' takes precedence over 'clear' */ + + if (set & USBH_SERIAL_TIOCM_DTR) { + line_state |= USBH_SERIAL_TIOCM_DTR; + } + if (set & USBH_SERIAL_TIOCM_RTS) { + line_state |= USBH_SERIAL_TIOCM_RTS; + } + if (clear & USBH_SERIAL_TIOCM_DTR) { + line_state &= ~USBH_SERIAL_TIOCM_DTR; + } + if (clear & USBH_SERIAL_TIOCM_RTS) { + line_state &= ~USBH_SERIAL_TIOCM_RTS; + } + + dtr = (line_state & USBH_SERIAL_TIOCM_DTR) ? true : false; + rts = (line_state & USBH_SERIAL_TIOCM_RTS) ? true : false; + + if (serial && serial->driver && serial->driver->set_line_state) { + ret = serial->driver->set_line_state(serial, dtr, rts); + } else { + return -USB_ERR_NOTSUPP; + } + serial->line_state = line_state; + + return ret; +} + +int usbh_serial_control(struct usbh_serial *serial, int cmd, void *arg) +{ + int ret; + + if (!serial || !serial->hport || !serial->hport->connected) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + switch (cmd) { + case USBH_SERIAL_CMD_SET_ATTR: { + struct usbh_serial_termios *termios = (struct usbh_serial_termios *)arg; + struct cdc_line_coding line_coding; + + line_coding.dwDTERate = termios->baudrate; + line_coding.bCharFormat = termios->stopbits; + line_coding.bParityType = termios->parity; + line_coding.bDataBits = termios->databits; + + if (serial->bulkin) { + usbh_kill_urb(&serial->bulkin_urb); + } + if (serial->bulkout) { + usbh_kill_urb(&serial->bulkout_urb); + } + + if (serial && serial->driver && serial->driver->set_line_coding) { + ret = serial->driver->set_line_coding(serial, &line_coding); + if (ret < 0) { + return ret; + } + } else { + return -USB_ERR_NOTSUPP; + } + + memcpy(&serial->line_coding, &line_coding, sizeof(struct cdc_line_coding)); + + if (serial && serial->driver && serial->driver->set_flow_control) { + ret = serial->driver->set_flow_control(serial, termios->rtscts); + } + + serial->rtscts = termios->rtscts; + serial->rx_timeout_ms = termios->rx_timeout; + + ret = usbh_serial_tiocmset(serial, USBH_SERIAL_TIOCM_DTR | USBH_SERIAL_TIOCM_RTS, 0); + if (ret < 0) { + return ret; + } + + usbh_serial_ringbuffer_reset(&serial->rx_rb); + usb_osal_sem_reset(serial->rx_complete_sem); + serial->rx_buf_index = 0; + usbh_bulk_urb_fill(&serial->bulkin_urb, serial->hport, serial->bulkin, &serial->iobuffer[serial->rx_buf_index ? USBH_SERIAL_RX2_NOCACHE_OFFSET : USBH_SERIAL_RX_NOCACHE_OFFSET], serial->bulkin->wMaxPacketSize, + 0, usbh_serial_callback, serial); + ret = usbh_submit_urb(&serial->bulkin_urb); + + return ret; + } break; + case USBH_SERIAL_CMD_GET_ATTR: { + struct usbh_serial_termios *termios = (struct usbh_serial_termios *)arg; + struct cdc_line_coding line_coding; + + if (serial && serial->driver && serial->driver->get_line_coding) { + return serial->driver->get_line_coding(serial, &line_coding); + } else { + memcpy(&line_coding, &serial->line_coding, sizeof(struct cdc_line_coding)); + } + + termios->baudrate = line_coding.dwDTERate; + termios->stopbits = line_coding.bCharFormat; + termios->parity = line_coding.bParityType; + termios->databits = line_coding.bDataBits; + termios->rtscts = serial->rtscts; + termios->rx_timeout = serial->rx_timeout_ms; + return 0; + } break; + case USBH_SERIAL_CMD_IOCMBIS: { + uint32_t flags = *(uint32_t *)arg; + + return usbh_serial_tiocmset(serial, flags, 0); + } break; + case USBH_SERIAL_CMD_IOCMBIC: { + uint32_t flags = *(uint32_t *)arg; + + return usbh_serial_tiocmset(serial, 0, flags); + } break; + case USBH_SERIAL_CMD_TIOCMSET: { + uint32_t flags = *(uint32_t *)arg; + + uint32_t set = 0; + uint32_t clear = 0; + + set |= (flags & USBH_SERIAL_TIOCM_DTR) ? USBH_SERIAL_TIOCM_DTR : 0; + set |= (flags & USBH_SERIAL_TIOCM_RTS) ? USBH_SERIAL_TIOCM_RTS : 0; + clear |= !(flags & USBH_SERIAL_TIOCM_DTR) ? USBH_SERIAL_TIOCM_DTR : 0; + clear |= !(flags & USBH_SERIAL_TIOCM_RTS) ? USBH_SERIAL_TIOCM_RTS : 0; + + return usbh_serial_tiocmset(serial, set, clear); + } break; + case USBH_SERIAL_CMD_TIOCMGET: { + uint32_t *flags = (uint32_t *)arg; + int status; + + if (serial && serial->driver && serial->driver->get_modem_status) { + status = serial->driver->get_modem_status(serial); + if (status < 0) { + return status; + } + } else { + return -USB_ERR_NOTSUPP; + } + *flags = status; + } break; + default: + break; + } + + return -USB_ERR_NOTSUPP; +} + +int usbh_serial_write(struct usbh_serial *serial, const void *buffer, uint32_t buflen) +{ + int ret; + struct usbh_urb *urb; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkout) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + urb = &serial->bulkout_urb; + + usbh_bulk_urb_fill(urb, serial->hport, serial->bulkout, (uint8_t *)buffer, buflen, 0xffffffff, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_serial_read(struct usbh_serial *serial, void *buffer, uint32_t buflen) +{ + int ret; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkin || !serial->line_coding.dwDTERate) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + if (serial->open_flags & USBH_SERIAL_O_NONBLOCK) { + return usbh_serial_ringbuffer_read(&serial->rx_rb, buffer, buflen); + } else { + if (usbh_serial_ringbuffer_get_used(&serial->rx_rb) == 0) { + ret = usb_osal_sem_take(serial->rx_complete_sem, serial->rx_timeout_ms == 0 ? USB_OSAL_WAITING_FOREVER : serial->rx_timeout_ms); + if (ret < 0) { + return ret; + } + if (serial->rx_errorcode < 0) { + return serial->rx_errorcode; + } + } + return usbh_serial_ringbuffer_read(&serial->rx_rb, buffer, buflen); + } +} + +int usbh_serial_cdc_write_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg) +{ + struct usbh_urb *urb; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkout || !complete || serial->line_coding.dwDTERate) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + urb = &serial->bulkout_urb; + + usbh_bulk_urb_fill(urb, serial->hport, serial->bulkout, buffer, buflen, + 0, complete, serial); + return usbh_submit_urb(urb); +} + +int usbh_serial_cdc_read_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg) +{ + struct usbh_urb *urb; + + if (!serial || !serial->hport || !serial->hport->connected || !serial->bulkin || !complete || serial->line_coding.dwDTERate) { + return -USB_ERR_INVAL; + } + + if (serial->ref_count == 0) { + return -USB_ERR_NODEV; + } + + if (buflen % serial->bulkin->wMaxPacketSize) { + return -USB_ERR_INVAL; + } + + urb = &serial->bulkin_urb; + + usbh_bulk_urb_fill(urb, serial->hport, serial->bulkin, buffer, MIN(buflen, serial->bulkin->wMaxPacketSize), + 0, complete, serial); + return usbh_submit_urb(urb); +} + +void usbh_serial_help(void) +{ + USB_LOG_RAW("USB host serial test\r\n" + "Usage: usbh_serial [options]...\r\n" + "\r\n" + "-b set serial baudrate\r\n" + "-t set rts and dtr\r\n" + "-w string write string\r\n" + "-r read data and dump\r\n" + "-x close serial device\r\n" + "\r\n"); +} + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_serial_testbuffer[512]; + +int usbh_serial(int argc, char **argv) +{ + static struct usbh_serial *serial; + int ret; + + if (argc < 3) { + usbh_serial_help(); + return 0; + } + + if (serial) { + if (!serial->hport || !serial->hport->connected) { + serial = NULL; + } + } + + if (!serial) { + serial = usbh_serial_open(argv[1], USBH_SERIAL_O_RDWR | USBH_SERIAL_O_NONBLOCK); + if (!serial) { + USB_LOG_ERR("Fail to open serial device: %s\r\n", argv[1]); + return -USB_ERR_INVAL; + } + } + + if (strncmp(argv[2], "-b", 2) == 0 && argc >= 4) { + struct usbh_serial_termios termios; + + memset(&termios, 0, sizeof(termios)); + termios.baudrate = atoi(argv[3]); + termios.stopbits = 0; + termios.parity = 0; + termios.databits = 8; + termios.rtscts = false; + termios.rx_timeout = 0; + usbh_serial_control(serial, USBH_SERIAL_CMD_SET_ATTR, &termios); + } else if (strncmp(argv[2], "-t", 2) == 0 && argc >= 5) { + uint32_t flags; + + flags = atoi(argv[3]) ? USBH_SERIAL_TIOCM_DTR : 0; + flags |= atoi(argv[4]) ? USBH_SERIAL_TIOCM_RTS : 0; + + usbh_serial_control(serial, USBH_SERIAL_CMD_TIOCMSET, &flags); + USB_LOG_INFO("Set DTR: %d, RTS: %d\r\n", atoi(argv[3]), atoi(argv[4])); + } else if (strncmp(argv[2], "-w", 2) == 0 && argc >= 4) { + memcpy(g_serial_testbuffer, argv[3], MIN(strlen(argv[3]), sizeof(g_serial_testbuffer))); + uint32_t len = snprintf((char *)g_serial_testbuffer, sizeof(g_serial_testbuffer), "%s\r\n", argv[3]); + ret = usbh_serial_write(serial, g_serial_testbuffer, len); + if (ret >= 0) { + USB_LOG_INFO("Write %d bytes\r\n", ret); + } else { + USB_LOG_ERR("Write failed: %d\r\n", ret); + } + } else if (strncmp(argv[2], "-r", 2) == 0) { + ret = usbh_serial_read(serial, g_serial_testbuffer, sizeof(g_serial_testbuffer)); + if (ret >= 0) { + usb_hexdump(g_serial_testbuffer, ret); + USB_LOG_INFO("Read %d bytes\r\n", ret); + } else { + USB_LOG_ERR("Read failed: %d\r\n", ret); + } + } else if (strncmp(argv[2], "-x", 2) == 0) { + usbh_serial_close(serial); + serial = NULL; + } else { + usbh_serial_help(); + } + + return 0; +} + +__WEAK void usbh_serial_run(struct usbh_serial *serial) +{ + (void)serial; +} + +__WEAK void usbh_serial_stop(struct usbh_serial *serial) +{ + (void)serial; +} + +static int usbh_cdc_data_connect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +static int usbh_cdc_data_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + (void)hport; + (void)intf; + return 0; +} + +const struct usbh_class_driver cdc_data_class_driver = { + .driver_name = "cdc_data", + .connect = usbh_cdc_data_connect, + .disconnect = usbh_cdc_data_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_data_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .bInterfaceClass = USB_DEVICE_CLASS_CDC_DATA, + .bInterfaceSubClass = 0x00, + .bInterfaceProtocol = 0x00, + .id_table = NULL, + .class_driver = &cdc_data_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/serial/usbh_serial.h b/components/drivers/usb/cherryusb/class/serial/usbh_serial.h new file mode 100644 index 0000000000..033ab705ed --- /dev/null +++ b/components/drivers/usb/cherryusb/class/serial/usbh_serial.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2025, sakumisu + * Copyright (c) 2025, MDLZCOOL + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_SERIAL_H +#define USBH_SERIAL_H + +#include "usb_cdc.h" + +#define USBH_SERIAL_CTRL_NOCACHE_OFFSET 0 +#define USBH_SERIAL_CTRL_NOCACHE_SIZE 32 +#define USBH_SERIAL_INT_NOCACHE_OFFSET USB_ALIGN_UP(USBH_SERIAL_CTRL_NOCACHE_SIZE, CONFIG_USB_ALIGN_SIZE) +#define USBH_SERIAL_INT_NOCACHE_SIZE 32 +#define USBH_SERIAL_RX_NOCACHE_OFFSET USB_ALIGN_UP((USBH_SERIAL_INT_NOCACHE_OFFSET + USBH_SERIAL_INT_NOCACHE_SIZE), CONFIG_USB_ALIGN_SIZE) +#define USBH_SERIAL_RX_NOCACHE_SIZE 512 +#define USBH_SERIAL_RX2_NOCACHE_OFFSET USB_ALIGN_UP((USBH_SERIAL_RX_NOCACHE_OFFSET + USBH_SERIAL_RX_NOCACHE_SIZE), CONFIG_USB_ALIGN_SIZE) +#define USBH_SERIAL_RX2_NOCACHE_SIZE 512 + +#define USBH_SERIAL_DATABITS_5 5 +#define USBH_SERIAL_DATABITS_6 6 +#define USBH_SERIAL_DATABITS_7 7 +#define USBH_SERIAL_DATABITS_8 8 + +#define USBH_SERIAL_PARITY_NONE 0 +#define USBH_SERIAL_PARITY_ODD 1 +#define USBH_SERIAL_PARITY_EVEN 2 +#define USBH_SERIAL_PARITY_MARK 3 +#define USBH_SERIAL_PARITY_SPACE 4 + +#define USBH_SERIAL_STOPBITS_1 0 +#define USBH_SERIAL_STOPBITS_1_5 1 +#define USBH_SERIAL_STOPBITS_2 2 + +/* modem lines */ +#define USBH_SERIAL_TIOCM_LE 0x001 /* line enable */ +#define USBH_SERIAL_TIOCM_DTR 0x002 /* data terminal ready */ +#define USBH_SERIAL_TIOCM_RTS 0x004 /* request to send */ +#define USBH_SERIAL_TIOCM_ST 0x010 /* secondary transmit */ +#define USBH_SERIAL_TIOCM_SR 0x020 /* secondary receive */ +#define USBH_SERIAL_TIOCM_CTS 0x040 /* clear to send */ +#define USBH_SERIAL_TIOCM_CAR 0x100 /* carrier detect */ +#define USBH_SERIAL_TIOCM_CD USBH_SERIAL_TIOCM_CAR +#define USBH_SERIAL_TIOCM_RNG 0x200 /* ring */ +#define USBH_SERIAL_TIOCM_RI USBH_SERIAL_TIOCM_RNG +#define USBH_SERIAL_TIOCM_DSR 0x400 /* data set ready */ +#define USBH_SERIAL_TIOCM_OUT1 0x2000 +#define USBH_SERIAL_TIOCM_OUT2 0x4000 +#define USBH_SERIAL_TIOCM_LOOP 0x8000 + +#define USBH_SERIAL_O_RDONLY 0x0000 /* open for reading only */ +#define USBH_SERIAL_O_WRONLY 0x0001 /* open for writing only */ +#define USBH_SERIAL_O_RDWR 0x0002 /* open for reading and writing */ + +#define USBH_SERIAL_O_ACCMODE 0x0003 /* mask for above modes, from 4.4BSD https://minnie.tuhs.org/cgi-bin/utree.pl?file=4.4BSD/usr/include/sys/fcntl.h */ +#define USBH_SERIAL_O_NONBLOCK 0x0004 /* non-blocking I/O, from BSD apple https://opensource.apple.com/source/xnu/xnu-1228.0.2/bsd/sys/fcntl.h */ + +#define USBH_SERIAL_CMD_SET_ATTR 0 +#define USBH_SERIAL_CMD_GET_ATTR 1 +#define USBH_SERIAL_CMD_IOCMBIS 2 +#define USBH_SERIAL_CMD_IOCMBIC 3 +#define USBH_SERIAL_CMD_TIOCMSET 4 +#define USBH_SERIAL_CMD_TIOCMGET 5 + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t in; /*!< Define the write pointer. */ + uint32_t out; /*!< Define the read pointer. */ + uint32_t mask; /*!< Define the write and read pointer mask. */ + void *pool; /*!< Define the memory pointer. */ +} usbh_serial_ringbuf_t; + +/* + * Counters of the input lines (CTS, DSR, RI, CD) interrupts + */ + +struct usbh_serial_async_icount { + uint32_t cts, dsr, rng, dcd, tx, rx; + uint32_t frame, parity, overrun, brk; + uint32_t buf_overrun; +}; + +struct usbh_serial_termios { + uint32_t baudrate; + uint8_t databits; + uint8_t parity; + uint8_t stopbits; + bool rtscts; /* hardware flow control */ + uint32_t rx_timeout; +}; + +struct usbh_serial; + +typedef void (*usbh_serial_rx_complete_callback_t)(struct usbh_serial *serial, int nbytes); + +/** + * @brief Serial Driver Operations + */ +struct usbh_serial_driver { + const char *driver_name; + + uint8_t ignore_tx_header; + uint8_t ignore_rx_header; + + int (*attach)(struct usbh_serial *serial); + void (*detach)(struct usbh_serial *serial); + + int (*open)(struct usbh_serial *serial); + void (*close)(struct usbh_serial *serial); + int (*set_flow_control)(struct usbh_serial *serial, bool enable); + int (*set_line_coding)(struct usbh_serial *serial, struct cdc_line_coding *line_coding); + int (*get_line_coding)(struct usbh_serial *serial, struct cdc_line_coding *line_coding); + int (*set_line_state)(struct usbh_serial *serial, bool dtr, bool rts); + int (*get_modem_status)(struct usbh_serial *serial); +}; + +/** + * @brief Serial Instance + */ +struct usbh_serial { + struct usbh_hubport *hport; + uint8_t intf; /* Interface Number */ + int minor; /* Serial Port Number (/dev/ttyUSBx or /dev/ttyACMx) */ + int cdc_minor; /* Serial Port Number (/dev/ttyACMx) */ + uint8_t *iobuffer; /* I/O buffer for serial transfers */ + uint8_t ref_count; /* Reference Count */ + uint32_t open_flags; + uint32_t rx_timeout_ms; + + struct cdc_line_coding line_coding; + uint16_t line_state; + bool rtscts; /* hardware flow control */ + struct usbh_serial_async_icount iocount; + + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + const struct usbh_serial_driver *driver; + + usbh_serial_ringbuf_t rx_rb; + uint8_t rx_rb_pool[CONFIG_USBHOST_SERIAL_RX_SIZE]; + usb_osal_sem_t rx_complete_sem; + uint8_t rx_buf_index; + int rx_errorcode; + usbh_serial_rx_complete_callback_t rx_complete_callback; + + void *priv; /* Private Data */ + void *user_data; /* User Data */ +}; + +/* internal api */ +struct usbh_serial *usbh_serial_probe(struct usbh_hubport *hport, uint8_t intf, const struct usbh_serial_driver *driver); +void usbh_serial_remove(struct usbh_serial *serial); + +/* public api */ +struct usbh_serial *usbh_serial_open(const char *devname, uint32_t open_flags); +int usbh_serial_close(struct usbh_serial *serial); +int usbh_serial_control(struct usbh_serial *serial, int cmd, void *arg); +int usbh_serial_write(struct usbh_serial *serial, const void *buffer, uint32_t buflen); +int usbh_serial_read(struct usbh_serial *serial, void *buffer, uint32_t buflen); + +/* cdc only api */ +int usbh_serial_cdc_write_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg); +int usbh_serial_cdc_read_async(struct usbh_serial *serial, uint8_t *buffer, uint32_t buflen, usbh_complete_callback_t complete, void *arg); + +/* public weak api */ +void usbh_serial_run(struct usbh_serial *serial); +void usbh_serial_stop(struct usbh_serial *serial); + +int usbh_serial(int argc, char **argv); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_SERIAL_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c b/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c index 981c506799..ffa1ed500b 100644 --- a/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c +++ b/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c @@ -795,16 +795,6 @@ int usbh_asix_eth_output(uint32_t buflen) return usbh_submit_urb(&g_asix_class.bulkout_urb); } -__WEAK void usbh_asix_run(struct usbh_asix *asix_class) -{ - (void)asix_class; -} - -__WEAK void usbh_asix_stop(struct usbh_asix *asix_class) -{ - (void)asix_class; -} - static const uint16_t asix_id_table[][2] = { { 0x0B95, 0x772B }, { 0x0B95, 0x7720 }, diff --git a/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c b/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c index 39b597662a..50269f26d3 100644 --- a/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c +++ b/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c @@ -1034,17 +1034,17 @@ static int generic_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t si static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data, uint16_t type) { - int ret; + int ret = -USB_ERR_INVAL; uint16_t byteen_start, byteen_end, byen; uint16_t limit = 512; uint8_t *buf = data; /* both size and indix must be 4 bytes align */ if ((size & 3) || !size || (index & 3) || !buf) - return -USB_ERR_INVAL; + return ret; if ((uint32_t)index + (uint32_t)size > 0xffff) - return -USB_ERR_INVAL; + return ret; byteen_start = byteen & BYTE_EN_START_MASK; byteen_end = byteen & BYTE_EN_END_MASK; @@ -1596,8 +1596,8 @@ static void r8153_teredo_off(struct usbh_rtl8152 *tp) case RTL_VER_15: default: /* The bit 0 ~ 7 are relative with teredo settings. They are - * W1C (write 1 to clear), so set all 1 to disable it. - */ + * W1C (write 1 to clear), so set all 1 to disable it. + */ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); break; } @@ -2251,16 +2251,6 @@ int usbh_rtl8152_eth_output(uint32_t buflen) return usbh_submit_urb(&g_rtl8152_class.bulkout_urb); } -__WEAK void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class) -{ - (void)rtl8152_class; -} - -__WEAK void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class) -{ - (void)rtl8152_class; -} - static const uint16_t rtl_id_table[][2] = { { 0x0BDA, 0x8152 }, { 0, 0 }, diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c deleted file mode 100644 index f58350e6f8..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "usbh_core.h" -#include "usbh_cp210x.h" - -#define DEV_FORMAT "/dev/ttyUSB%d" - -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cp210x_buf[USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; - -#define CONFIG_USBHOST_MAX_CP210X_CLASS 1 - -static struct usbh_cp210x g_cp210x_class[CONFIG_USBHOST_MAX_CP210X_CLASS]; -static uint32_t g_devinuse = 0; - -static struct usbh_cp210x *usbh_cp210x_class_alloc(void) -{ - uint8_t devno; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_CP210X_CLASS; devno++) { - if ((g_devinuse & (1U << devno)) == 0) { - g_devinuse |= (1U << devno); - memset(&g_cp210x_class[devno], 0, sizeof(struct usbh_cp210x)); - g_cp210x_class[devno].minor = devno; - return &g_cp210x_class[devno]; - } - } - return NULL; -} - -static void usbh_cp210x_class_free(struct usbh_cp210x *cp210x_class) -{ - uint8_t devno = cp210x_class->minor; - - if (devno < 32) { - g_devinuse &= ~(1U << devno); - } - memset(cp210x_class, 0, sizeof(struct usbh_cp210x)); -} - -static int usbh_cp210x_enable(struct usbh_cp210x *cp210x_class) -{ - struct usb_setup_packet *setup; - - if (!cp210x_class || !cp210x_class->hport) { - return -USB_ERR_INVAL; - } - setup = cp210x_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CP210X_IFC_ENABLE; - setup->wValue = 1; - setup->wIndex = cp210x_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(cp210x_class->hport, setup, NULL); -} - -static int usbh_cp210x_set_flow(struct usbh_cp210x *cp210x_class) -{ - struct usb_setup_packet *setup; - - if (!cp210x_class || !cp210x_class->hport) { - return -USB_ERR_INVAL; - } - setup = cp210x_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CP210X_SET_FLOW; - setup->wValue = 0; - setup->wIndex = cp210x_class->intf; - setup->wLength = 16; - - memset(g_cp210x_buf, 0, 16); - g_cp210x_buf[13] = 0x20; - return usbh_control_transfer(cp210x_class->hport, setup, g_cp210x_buf); -} - -static int usbh_cp210x_set_chars(struct usbh_cp210x *cp210x_class) -{ - struct usb_setup_packet *setup; - - if (!cp210x_class || !cp210x_class->hport) { - return -USB_ERR_INVAL; - } - setup = cp210x_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CP210X_SET_CHARS; - setup->wValue = 0; - setup->wIndex = cp210x_class->intf; - setup->wLength = 6; - - memset(g_cp210x_buf, 0, 6); - g_cp210x_buf[0] = 0x80; - g_cp210x_buf[4] = 0x88; - g_cp210x_buf[5] = 0x28; - return usbh_control_transfer(cp210x_class->hport, setup, g_cp210x_buf); -} - -static int usbh_cp210x_set_baudrate(struct usbh_cp210x *cp210x_class, uint32_t baudrate) -{ - struct usb_setup_packet *setup; - - if (!cp210x_class || !cp210x_class->hport) { - return -USB_ERR_INVAL; - } - setup = cp210x_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CP210X_SET_BAUDRATE; - setup->wValue = 0; - setup->wIndex = cp210x_class->intf; - setup->wLength = 4; - - memcpy(g_cp210x_buf, (uint8_t *)&baudrate, 4); - return usbh_control_transfer(cp210x_class->hport, setup, g_cp210x_buf); -} - -static int usbh_cp210x_set_data_format(struct usbh_cp210x *cp210x_class, uint8_t databits, uint8_t parity, uint8_t stopbits) -{ - struct usb_setup_packet *setup; - uint16_t value; - - if (!cp210x_class || !cp210x_class->hport) { - return -USB_ERR_INVAL; - } - setup = cp210x_class->hport->setup; - - value = ((databits & 0x0F) << 8) | ((parity & 0x0f) << 4) | ((stopbits & 0x03) << 0); - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CP210X_SET_LINE_CTL; - setup->wValue = value; - setup->wIndex = cp210x_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(cp210x_class->hport, setup, NULL); -} - -static int usbh_cp210x_set_mhs(struct usbh_cp210x *cp210x_class, uint8_t dtr, uint8_t rts, uint8_t dtr_mask, uint8_t rts_mask) -{ - struct usb_setup_packet *setup; - uint16_t value; - - if (!cp210x_class || !cp210x_class->hport) { - return -USB_ERR_INVAL; - } - setup = cp210x_class->hport->setup; - - value = ((dtr & 0x01) << 0) | ((rts & 0x01) << 1) | ((dtr_mask & 0x01) << 8) | ((rts_mask & 0x01) << 9); - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CP210X_SET_MHS; - setup->wValue = value; - setup->wIndex = cp210x_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(cp210x_class->hport, setup, NULL); -} - -int usbh_cp210x_set_line_coding(struct usbh_cp210x *cp210x_class, struct cdc_line_coding *line_coding) -{ - memcpy((uint8_t *)&cp210x_class->line_coding, line_coding, sizeof(struct cdc_line_coding)); - usbh_cp210x_set_baudrate(cp210x_class, line_coding->dwDTERate); - return usbh_cp210x_set_data_format(cp210x_class, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat); -} - -int usbh_cp210x_get_line_coding(struct usbh_cp210x *cp210x_class, struct cdc_line_coding *line_coding) -{ - memcpy(line_coding, (uint8_t *)&cp210x_class->line_coding, sizeof(struct cdc_line_coding)); - return 0; -} - -int usbh_cp210x_set_line_state(struct usbh_cp210x *cp210x_class, bool dtr, bool rts) -{ - return usbh_cp210x_set_mhs(cp210x_class, dtr, rts, 1, 1); -} - -static int usbh_cp210x_connect(struct usbh_hubport *hport, uint8_t intf) -{ - struct usb_endpoint_descriptor *ep_desc; - int ret = 0; - - struct usbh_cp210x *cp210x_class = usbh_cp210x_class_alloc(); - if (cp210x_class == NULL) { - USB_LOG_ERR("Fail to alloc cp210x_class\r\n"); - return -USB_ERR_NOMEM; - } - - cp210x_class->hport = hport; - cp210x_class->intf = intf; - - hport->config.intf[intf].priv = cp210x_class; - - usbh_cp210x_enable(cp210x_class); - usbh_cp210x_set_flow(cp210x_class); - usbh_cp210x_set_chars(cp210x_class); - - for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { - ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; - - if (ep_desc->bEndpointAddress & 0x80) { - USBH_EP_INIT(cp210x_class->bulkin, ep_desc); - } else { - USBH_EP_INIT(cp210x_class->bulkout, ep_desc); - } - } - - snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, cp210x_class->minor); - - USB_LOG_INFO("Register CP210X Class:%s\r\n", hport->config.intf[intf].devname); - -#if 0 - USB_LOG_INFO("Test cp2102 rx and tx and rx for 5 times, baudrate is 115200\r\n"); - - struct cdc_line_coding linecoding; - uint8_t count = 5; - - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_cp210x_set_line_coding(cp210x_class, &linecoding); - usbh_cp210x_set_line_state(cp210x_class, true, false); - - memset(g_cp210x_buf, 'a', sizeof(g_cp210x_buf)); - ret = usbh_cp210x_bulk_out_transfer(cp210x_class, g_cp210x_buf, sizeof(g_cp210x_buf), 0xfffffff); - USB_LOG_RAW("out ret:%d\r\n", ret); - while (count--) { - ret = usbh_cp210x_bulk_in_transfer(cp210x_class, g_cp210x_buf, sizeof(g_cp210x_buf), 0xfffffff); - USB_LOG_RAW("in ret:%d\r\n", ret); - if (ret > 0) { - for (uint32_t i = 0; i < ret; i++) { - USB_LOG_RAW("%02x ", g_cp210x_buf[i]); - } - USB_LOG_RAW("\r\n"); - } - } -#endif - usbh_cp210x_run(cp210x_class); - return ret; -} - -static int usbh_cp210x_disconnect(struct usbh_hubport *hport, uint8_t intf) -{ - int ret = 0; - - struct usbh_cp210x *cp210x_class = (struct usbh_cp210x *)hport->config.intf[intf].priv; - - if (cp210x_class) { - if (cp210x_class->bulkin) { - usbh_kill_urb(&cp210x_class->bulkin_urb); - } - - if (cp210x_class->bulkout) { - usbh_kill_urb(&cp210x_class->bulkout_urb); - } - - if (hport->config.intf[intf].devname[0] != '\0') { - usb_osal_thread_schedule_other(); - USB_LOG_INFO("Unregister CP210X Class:%s\r\n", hport->config.intf[intf].devname); - usbh_cp210x_stop(cp210x_class); - } - - usbh_cp210x_class_free(cp210x_class); - } - - return ret; -} - -int usbh_cp210x_bulk_in_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &cp210x_class->bulkin_urb; - - usbh_bulk_urb_fill(urb, cp210x_class->hport, cp210x_class->bulkin, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -int usbh_cp210x_bulk_out_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &cp210x_class->bulkout_urb; - - usbh_bulk_urb_fill(urb, cp210x_class->hport, cp210x_class->bulkout, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -__WEAK void usbh_cp210x_run(struct usbh_cp210x *cp210x_class) -{ - (void)cp210x_class; -} - -__WEAK void usbh_cp210x_stop(struct usbh_cp210x *cp210x_class) -{ - (void)cp210x_class; -} - -static const uint16_t cp210x_id_table[][2] = { - { 0x10C4, 0xEA60 }, - { 0, 0 }, -}; - -const struct usbh_class_driver cp210x_class_driver = { - .driver_name = "cp210x", - .connect = usbh_cp210x_connect, - .disconnect = usbh_cp210x_disconnect -}; - -CLASS_INFO_DEFINE const struct usbh_class_info cp210x_class_info = { - .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .bInterfaceClass = 0xff, - .bInterfaceSubClass = 0x00, - .bInterfaceProtocol = 0x00, - .id_table = cp210x_id_table, - .class_driver = &cp210x_class_driver -}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h deleted file mode 100644 index d380c36c58..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef USBH_CP210X_H -#define USBH_CP210X_H - -#include "usb_cdc.h" - -/* Requests */ -#define CP210X_IFC_ENABLE 0x00 -#define CP210X_SET_BAUDDIV 0x01 -#define CP210X_GET_BAUDDIV 0x02 -#define CP210X_SET_LINE_CTL 0x03 // Set parity, data bits, stop bits -#define CP210X_GET_LINE_CTL 0x04 -#define CP210X_SET_BREAK 0x05 -#define CP210X_IMM_CHAR 0x06 -#define CP210X_SET_MHS 0x07 // Set DTR, RTS -#define CP210X_GET_MDMSTS 0x08 -#define CP210X_SET_XON 0x09 -#define CP210X_SET_XOFF 0x0A -#define CP210X_SET_EVENTMASK 0x0B -#define CP210X_GET_EVENTMASK 0x0C -#define CP210X_SET_CHAR 0x0D -#define CP210X_GET_CHARS 0x0E -#define CP210X_GET_PROPS 0x0F -#define CP210X_GET_COMM_STATUS 0x10 -#define CP210X_RESET 0x11 -#define CP210X_PURGE 0x12 -#define CP210X_SET_FLOW 0x13 -#define CP210X_GET_FLOW 0x14 -#define CP210X_EMBED_EVENTS 0x15 -#define CP210X_GET_EVENTSTATE 0x16 -#define CP210X_SET_CHARS 0x19 -#define CP210X_GET_BAUDRATE 0x1D -#define CP210X_SET_BAUDRATE 0x1E // Set baudrate -#define CP210X_VENDOR_SPECIFIC 0xFF - -struct usbh_cp210x { - struct usbh_hubport *hport; - struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ - struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ - struct usbh_urb bulkout_urb; - struct usbh_urb bulkin_urb; - - struct cdc_line_coding line_coding; - - uint8_t intf; - uint8_t minor; - - void *user_data; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -int usbh_cp210x_set_line_coding(struct usbh_cp210x *ftdi_class, struct cdc_line_coding *line_coding); -int usbh_cp210x_get_line_coding(struct usbh_cp210x *ftdi_class, struct cdc_line_coding *line_coding); -int usbh_cp210x_set_line_state(struct usbh_cp210x *ftdi_class, bool dtr, bool rts); - -int usbh_cp210x_bulk_in_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); -int usbh_cp210x_bulk_out_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); - -void usbh_cp210x_run(struct usbh_cp210x *cp210x_class); -void usbh_cp210x_stop(struct usbh_cp210x *cp210x_class); - -#ifdef __cplusplus -} -#endif - -#endif /* USBH_CP210X_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h deleted file mode 100644 index 855db8d6c6..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef USBH_FTDI_H -#define USBH_FTDI_H - -#include "usb_cdc.h" - -/* Requests */ -#define SIO_RESET_REQUEST 0x00 /* Reset the port */ -#define SIO_SET_MODEM_CTRL_REQUEST 0x01 /* Set the modem control register */ -#define SIO_SET_FLOW_CTRL_REQUEST 0x02 /* Set flow control register */ -#define SIO_SET_BAUDRATE_REQUEST 0x03 /* Set baud rate */ -#define SIO_SET_DATA_REQUEST 0x04 /* Set the data characteristics of the port */ -#define SIO_POLL_MODEM_STATUS_REQUEST 0x05 -#define SIO_SET_EVENT_CHAR_REQUEST 0x06 -#define SIO_SET_ERROR_CHAR_REQUEST 0x07 -#define SIO_SET_LATENCY_TIMER_REQUEST 0x09 -#define SIO_GET_LATENCY_TIMER_REQUEST 0x0A -#define SIO_SET_BITMODE_REQUEST 0x0B -#define SIO_READ_PINS_REQUEST 0x0C -#define SIO_READ_EEPROM_REQUEST 0x90 -#define SIO_WRITE_EEPROM_REQUEST 0x91 -#define SIO_ERASE_EEPROM_REQUEST 0x92 - -#define SIO_DISABLE_FLOW_CTRL 0x0 -#define SIO_RTS_CTS_HS (0x1 << 8) -#define SIO_DTR_DSR_HS (0x2 << 8) -#define SIO_XON_XOFF_HS (0x4 << 8) - -#define SIO_SET_DTR_MASK 0x1 -#define SIO_SET_DTR_HIGH (1 | (SIO_SET_DTR_MASK << 8)) -#define SIO_SET_DTR_LOW (0 | (SIO_SET_DTR_MASK << 8)) -#define SIO_SET_RTS_MASK 0x2 -#define SIO_SET_RTS_HIGH (2 | (SIO_SET_RTS_MASK << 8)) -#define SIO_SET_RTS_LOW (0 | (SIO_SET_RTS_MASK << 8)) - -#define SIO_RTS_CTS_HS (0x1 << 8) - -enum ftdi_chip_type { - SIO, - FT232A, - FT232B, - FT2232C, - FT232R, - FT232H, - FT2232H, - FT4232H, - FT4232HA, - FT232HP, - FT233HP, - FT2232HP, - FT2233HP, - FT4232HP, - FT4233HP, - FTX, -}; - -struct usbh_ftdi { - struct usbh_hubport *hport; - struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ - struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ - struct usbh_urb bulkout_urb; - struct usbh_urb bulkin_urb; - - struct cdc_line_coding line_coding; - - uint8_t intf; - uint8_t minor; - uint8_t modem_status[2]; - enum ftdi_chip_type chip_type; - - void *user_data; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -int usbh_ftdi_set_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding); -int usbh_ftdi_get_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding); -int usbh_ftdi_set_line_state(struct usbh_ftdi *ftdi_class, bool dtr, bool rts); - -int usbh_ftdi_bulk_in_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); -int usbh_ftdi_bulk_out_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); - -void usbh_ftdi_run(struct usbh_ftdi *ftdi_class); -void usbh_ftdi_stop(struct usbh_ftdi *ftdi_class); - -#ifdef __cplusplus -} -#endif - -#endif /* USBH_FTDI_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c deleted file mode 100644 index ece3253881..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * Copyright (c) 2024, Derek Konigsberg - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "usbh_core.h" -#include "usbh_pl2303.h" - -#undef USB_DBG_TAG -#define USB_DBG_TAG "usbh_pl2303" -#include "usb_log.h" - -#define DEV_FORMAT "/dev/ttyUSB%d" - -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_pl2303_buf[USB_ALIGN_UP(64, CONFIG_USB_ALIGN_SIZE)]; - -#define CONFIG_USBHOST_MAX_PL2303_CLASS 1 - -#define UT_WRITE_VENDOR_DEVICE (USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE) -#define UT_READ_VENDOR_DEVICE (USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE) - -static struct usbh_pl2303 g_pl2303_class[CONFIG_USBHOST_MAX_PL2303_CLASS]; -static uint32_t g_devinuse = 0; - -static struct usbh_pl2303 *usbh_pl2303_class_alloc(void) -{ - uint8_t devno; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_PL2303_CLASS; devno++) { - if ((g_devinuse & (1U << devno)) == 0) { - g_devinuse |= (1U << devno); - memset(&g_pl2303_class[devno], 0, sizeof(struct usbh_pl2303)); - g_pl2303_class[devno].minor = devno; - return &g_pl2303_class[devno]; - } - } - return NULL; -} - -static void usbh_pl2303_class_free(struct usbh_pl2303 *pl2303_class) -{ - uint8_t devno = pl2303_class->minor; - - if (devno < 32) { - g_devinuse &= ~(1U << devno); - } - memset(pl2303_class, 0, sizeof(struct usbh_pl2303)); -} - -static int usbh_pl2303_get_chiptype(struct usbh_pl2303 *pl2303_class) -{ - int ret = 0; - - switch (pl2303_class->hport->device_desc.bcdDevice) { - case 0x0300: - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HX; - /* or TA, that is HX with external crystal */ - break; - case 0x0400: - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HXD; - /* or EA, that is HXD with ESD protection */ - /* or RA, that has internal voltage level converter that works only up to 1Mbaud (!) */ - break; - case 0x0500: - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HXD; - /* in fact it's TB, that is HXD with external crystal */ - break; - default: - /* NOTE: I have no info about the bcdDevice for the base PL2303 (up to 1.2Mbaud, - only fixed rates) and for PL2303SA (8-pin chip, up to 115200 baud */ - /* Determine the chip type. This algorithm is taken from Linux. */ - if (pl2303_class->hport->device_desc.bDeviceClass == 0x02) { - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303; - } else if (pl2303_class->hport->device_desc.bMaxPacketSize0 == 0x40) { - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HX; - } else { - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303; - } - break; - } - - /* - * The new chip revision PL2303HXN is only compatible with the new - * PLCOM_SET_REQUEST_PL2303HXN command. Issuing the old command - * PLCOM_SET_REQUEST to the new chip raises an error. Thus, PL2303HX - * and PL2303HXN can be distinguished by issuing an old-style request - * (on a status register) to the new chip and checking the error. - */ - if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HX) { - struct usb_setup_packet *setup = pl2303_class->hport->setup; - - setup->bmRequestType = UT_READ_VENDOR_DEVICE; - setup->bRequest = PL2303_SET_REQUEST; - setup->wValue = PL2303_STATUS_REG_PL2303HX; - setup->wIndex = 0; - setup->wLength = 1; - - ret = usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); - if (ret == -USB_ERR_STALL) { - pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HXN; - ret = 0; - } else if (ret < 0) { - USB_LOG_WRN("Error checking chip type: %d\r\n", ret); - return ret; - } - } - - switch (pl2303_class->chiptype) { - case USBH_PL2303_TYPE_PL2303: - USB_LOG_INFO("chiptype = 2303\r\n"); - break; - case USBH_PL2303_TYPE_PL2303HX: - USB_LOG_INFO("chiptype = 2303HX/TA\r\n"); - break; - case USBH_PL2303_TYPE_PL2303HXN: - USB_LOG_INFO("chiptype = 2303HXN\r\n"); - break; - case USBH_PL2303_TYPE_PL2303HXD: - USB_LOG_INFO("chiptype = 2303HXD/TB/RA/EA\r\n"); - break; - default: - USB_LOG_INFO("chiptype = [%d]\r\n", pl2303_class->chiptype); - break; - } - - return ret; -} - -static int usbh_pl2303_do(struct usbh_pl2303 *pl2303_class, - uint8_t req_type, uint8_t request, uint16_t value, uint16_t index, - uint16_t length) -{ - struct usb_setup_packet *setup; - - if (!pl2303_class || !pl2303_class->hport) { - return -USB_ERR_INVAL; - } - setup = pl2303_class->hport->setup; - - setup->bmRequestType = req_type; - setup->bRequest = request; - setup->wValue = value; - setup->wIndex = index; - setup->wLength = length; - - return usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); -} - -int usbh_pl2303_set_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding) -{ - struct usb_setup_packet *setup; - - if (!pl2303_class || !pl2303_class->hport) { - return -USB_ERR_INVAL; - } - setup = pl2303_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CDC_REQUEST_SET_LINE_CODING; - setup->wValue = 0; - setup->wIndex = pl2303_class->intf; - setup->wLength = 7; - - memcpy(g_pl2303_buf, line_coding, sizeof(struct cdc_line_coding)); - - return usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); -} - -int usbh_pl2303_get_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding) -{ - struct usb_setup_packet *setup; - int ret; - - if (!pl2303_class || !pl2303_class->hport) { - return -USB_ERR_INVAL; - } - setup = pl2303_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CDC_REQUEST_GET_LINE_CODING; - setup->wValue = 0; - setup->wIndex = pl2303_class->intf; - setup->wLength = 7; - - ret = usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); - if (ret < 0) { - return ret; - } - memcpy(line_coding, g_pl2303_buf, sizeof(struct cdc_line_coding)); - return ret; -} - -int usbh_pl2303_set_line_state(struct usbh_pl2303 *pl2303_class, bool dtr, bool rts) -{ - struct usb_setup_packet *setup; - - if (!pl2303_class || !pl2303_class->hport) { - return -USB_ERR_INVAL; - } - setup = pl2303_class->hport->setup; - - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; - setup->wValue = (dtr << 0) | (rts << 1); - setup->wIndex = pl2303_class->intf; - setup->wLength = 0; - - return usbh_control_transfer(pl2303_class->hport, setup, NULL); -} - -static int usbh_pl2303_connect(struct usbh_hubport *hport, uint8_t intf) -{ - struct usb_endpoint_descriptor *ep_desc; - int ret = 0; - - struct usbh_pl2303 *pl2303_class = usbh_pl2303_class_alloc(); - if (pl2303_class == NULL) { - USB_LOG_ERR("Fail to alloc pl2303_class\r\n"); - return -USB_ERR_NOMEM; - } - - pl2303_class->hport = hport; - pl2303_class->intf = intf; - - hport->config.intf[intf].priv = pl2303_class; - - do { - ret = usbh_pl2303_get_chiptype(pl2303_class); - if (ret < 0) { - break; - } - - /* Startup reset sequence, if necessary for the chip type */ - if (pl2303_class->chiptype != USBH_PL2303_TYPE_PL2303HXN) { - struct usb_setup_packet *setup = pl2303_class->hport->setup; - - setup->bmRequestType = UT_WRITE_VENDOR_DEVICE; - setup->bRequest = PL2303_SET_REQUEST; - setup->wValue = 0; - setup->wIndex = pl2303_class->intf; - setup->wLength = 0; - - ret = usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); - if (ret < 0) { - USB_LOG_WRN("Initialization reset failed: %d\r\n", ret); - break; - } - } - - if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303) { - /* HX variants seem to lock up after a clear stall request. */ - /* - * The FreeBSD code sets the stall flags on the in and out pipes - * here. Have no idea exactly how to do this, or if it is necessary. - * May just leave this code unwritten until test hardware is available. - */ - } else if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HX || pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HXD) { - /* Reset upstream data pipes */ - ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 8, 0, 0); - if (ret < 0) { - USB_LOG_WRN("Could not reset upstream data pipes (8,0): %d\r\n", ret); - break; - } - ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 9, 0, 0); - if (ret < 0) { - USB_LOG_WRN("Could not reset upstream data pipes (9,0): %d\r\n", ret); - break; - } - } else if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HXN) { - /* Reset upstream data pipes */ - ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST_PL2303HXN, 0x07, 0x03, 0); - if (ret < 0) { - USB_LOG_WRN("Could not reset upstream data pipes (7,3): %d\r\n", ret); - break; - } - } - - /* Final device initialization, if necessary for the chip type */ - if (pl2303_class->chiptype != USBH_PL2303_TYPE_PL2303HXN) { - if (usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || - usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x0404, 0, 0) < 0 || - usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || - usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8383, 0, 1) < 0 || - usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || - usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x0404, 1, 0) < 0 || - usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || - usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8383, 0, 1) < 0 || - usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 0, 1, 0) < 0 || - usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 1, 0, 0) < 0) { - USB_LOG_WRN("Could not complete init sequence\r\n"); - ret = -USB_ERR_INVAL; - break; - } - - if (pl2303_class->chiptype != USBH_PL2303_TYPE_PL2303) { - ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 2, 0x44, 0); - } else { - ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 2, 0x24, 0); - } - if (ret < 0) { - USB_LOG_WRN("Could not complete final init request: %d\r\n", ret); - break; - } - } - } while (0); - - if (ret < 0) { - USB_LOG_ERR("Failed to initialize PL2303 device: %d\r\n", ret); - return ret; - } - - for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { - ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; - if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { - continue; - } else { - if (ep_desc->bEndpointAddress & 0x80) { - USBH_EP_INIT(pl2303_class->bulkin, ep_desc); - } else { - USBH_EP_INIT(pl2303_class->bulkout, ep_desc); - } - } - } - - snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, pl2303_class->minor); - - USB_LOG_INFO("Register PL2303 Class:%s\r\n", hport->config.intf[intf].devname); - -#if 0 - USB_LOG_INFO("Test pl2303 rx and tx and rx for 5 times, baudrate is 115200\r\n"); - - struct cdc_line_coding linecoding; - uint8_t count = 5; - - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_pl2303_set_line_coding(pl2303_class, &linecoding); - usbh_pl2303_set_line_state(pl2303_class, true, false); - - memset(g_pl2303_buf, 'a', sizeof(g_pl2303_buf)); - ret = usbh_pl2303_bulk_out_transfer(pl2303_class, g_pl2303_buf, sizeof(g_pl2303_buf), 0xfffffff); - USB_LOG_RAW("out ret:%d\r\n", ret); - while (count--) { - ret = usbh_pl2303_bulk_in_transfer(pl2303_class, g_pl2303_buf, sizeof(g_pl2303_buf), 0xfffffff); - USB_LOG_RAW("in ret:%d\r\n", ret); - if (ret > 0) { - for (uint32_t i = 0; i < ret; i++) { - USB_LOG_RAW("%02x ", g_pl2303_buf[i]); - } - } - USB_LOG_RAW("\r\n"); - } -#endif - - usbh_pl2303_run(pl2303_class); - return ret; -} - -static int usbh_pl2303_disconnect(struct usbh_hubport *hport, uint8_t intf) -{ - int ret = 0; - - struct usbh_pl2303 *pl2303_class = (struct usbh_pl2303 *)hport->config.intf[intf].priv; - - if (pl2303_class) { - if (pl2303_class->bulkin) { - usbh_kill_urb(&pl2303_class->bulkin_urb); - } - - if (pl2303_class->bulkout) { - usbh_kill_urb(&pl2303_class->bulkout_urb); - } - - if (hport->config.intf[intf].devname[0] != '\0') { - usb_osal_thread_schedule_other(); - USB_LOG_INFO("Unregister PL2303 Class:%s\r\n", hport->config.intf[intf].devname); - usbh_pl2303_stop(pl2303_class); - } - - usbh_pl2303_class_free(pl2303_class); - } - - return ret; -} - -int usbh_pl2303_bulk_in_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &pl2303_class->bulkin_urb; - - usbh_bulk_urb_fill(urb, pl2303_class->hport, pl2303_class->bulkin, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -int usbh_pl2303_bulk_out_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &pl2303_class->bulkout_urb; - - usbh_bulk_urb_fill(urb, pl2303_class->hport, pl2303_class->bulkout, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -__WEAK void usbh_pl2303_run(struct usbh_pl2303 *pl2303_class) -{ - (void)pl2303_class; -} - -__WEAK void usbh_pl2303_stop(struct usbh_pl2303 *pl2303_class) -{ - (void)pl2303_class; -} - -static const uint16_t pl2303_id_table[][2] = { - { 0x067B, 0x2303 }, // PL2303 Serial (ATEN/IOGEAR UC232A) - { 0x067B, 0x23A3 }, // PL2303HXN Serial, type GC - { 0x067B, 0x23B3 }, // PL2303HXN Serial, type GB - { 0x067B, 0x23C3 }, // PL2303HXN Serial, type GT - { 0x067B, 0x23D3 }, // PL2303HXN Serial, type GL - { 0x067B, 0x23E3 }, // PL2303HXN Serial, type GE - { 0x067B, 0x23F3 }, // PL2303HXN Serial, type GS - { 0, 0 }, -}; - -const struct usbh_class_driver pl2303_class_driver = { - .driver_name = "pl2303", - .connect = usbh_pl2303_connect, - .disconnect = usbh_pl2303_disconnect -}; - -CLASS_INFO_DEFINE const struct usbh_class_info pl2303_class_info = { - .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .bInterfaceClass = 0xff, - .bInterfaceSubClass = 0x00, - .bInterfaceProtocol = 0x00, - .id_table = pl2303_id_table, - .class_driver = &pl2303_class_driver -}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h deleted file mode 100644 index 2b3d05f9e2..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef USBH_PL2303_H -#define USBH_PL2303_H - -#include "usb_cdc.h" - -#define PL2303_SET_REQUEST 0x01 -#define PL2303_SET_REQUEST_PL2303HXN 0x80 -#define PL2303_SET_CRTSCTS 0x41 -#define PL2303_SET_CRTSCTS_PL2303X 0x61 -#define PL2303_SET_CRTSCTS_PL2303HXN 0xFA -#define PL2303_CLEAR_CRTSCTS_PL2303HXN 0xFF -#define PL2303_CRTSCTS_REG_PL2303HXN 0x0A -#define PL2303_STATUS_REG_PL2303HX 0x8080 - -/* Different PL2303 IC types */ -#define USBH_PL2303_TYPE_UNKNOWN 0 -#define USBH_PL2303_TYPE_PL2303 1 -#define USBH_PL2303_TYPE_PL2303HX 2 -#define USBH_PL2303_TYPE_PL2303HXD 3 -#define USBH_PL2303_TYPE_PL2303HXN 4 - -struct usbh_pl2303 { - struct usbh_hubport *hport; - struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ - struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ - - struct usbh_urb bulkout_urb; - struct usbh_urb bulkin_urb; - - struct cdc_line_coding linecoding; - - uint8_t intf; - uint8_t minor; - uint8_t chiptype; - - void *user_data; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -int usbh_pl2303_set_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding); -int usbh_pl2303_get_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding); -int usbh_pl2303_set_line_state(struct usbh_pl2303 *pl2303_class, bool dtr, bool rts); - -int usbh_pl2303_bulk_in_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); -int usbh_pl2303_bulk_out_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); - -void usbh_pl2303_run(struct usbh_pl2303 *pl2303_class); -void usbh_pl2303_stop(struct usbh_pl2303 *pl2303_class); - -#ifdef __cplusplus -} -#endif - -#endif /* USBH_PL2303_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/wifi/.gitkeep b/components/drivers/usb/cherryusb/class/vendor/wifi/.gitkeep new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/drivers/usb/cherryusb/class/vendor/wifi/README.md b/components/drivers/usb/cherryusb/class/vendor/wifi/README.md deleted file mode 100644 index 18384f65d5..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/wifi/README.md +++ /dev/null @@ -1,6 +0,0 @@ -# BL616 USB WIFI - -Usbwifi firmware please contact bouffalolab. You can purchase a module in the following ways: - -- https://iot.mi.com/moduleBrowser.html -- https://docs.ai-thinker.com/ai_m61 \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c b/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c deleted file mode 100644 index e44df5bd77..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "usbh_core.h" -#include "usbh_bl616.h" - -#undef USB_DBG_TAG -#define USB_DBG_TAG "usbh_bl616" -#include "usb_log.h" - -#define DEV_FORMAT "/dev/wifi/bl616" - -#define MAC_FMT "%02X:%02X:%02X:%02X:%02X:%02X" -#define ARR_ELE_6(e) (e)[0], (e)[1], (e)[2], (e)[3], (e)[4], (e)[5] - -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bl616_tx_buffer[2048 + 512]; -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bl616_rx_buffer[2048 + 512]; - -static struct usbh_bl616 g_bl616_class; - -static const char *auth_to_str(uint8_t auth) -{ - const char *table[RNM_WIFI_AUTH_MAX] = { - [RNM_WIFI_AUTH_UNKNOWN] = "UNKNOWN", - [RNM_WIFI_AUTH_OPEN] = "OPEN", - [RNM_WIFI_AUTH_WEP] = "WEP", - [RNM_WIFI_AUTH_WPA_PSK] = "WPA-PSK", - [RNM_WIFI_AUTH_WPA2_PSK] = "WPA2-PSK", - [RNM_WIFI_AUTH_WPA_WPA2_PSK] = "WPA2-PSK/WPA-PSK", - [RNM_WIFI_AUTH_WPA_ENTERPRISE] = "WPA-ENT", - [RNM_WIFI_AUTH_WPA3_SAE] = "WPA3-SAE", - [RNM_WIFI_AUTH_WPA2_PSK_WPA3_SAE] = "WPA2-PSK/WPA3-SAE", - }; - if (auth < RNM_WIFI_AUTH_MAX) - return table[auth]; - else - return table[RNM_WIFI_AUTH_UNKNOWN]; -} - -static const char *cipher_to_str(uint8_t cipher) -{ - const char *table[RNM_WIFI_CIPHER_MAX] = { - [RNM_WIFI_CIPHER_UNKNOWN] = "UNKNOWN", - [RNM_WIFI_CIPHER_NONE] = "NONE", - [RNM_WIFI_CIPHER_WEP] = "WEP", - [RNM_WIFI_CIPHER_AES] = "AES", - [RNM_WIFI_CIPHER_TKIP] = "TKIP", - [RNM_WIFI_CIPHER_TKIP_AES] = "TKIP/AES", - }; - if (cipher < RNM_WIFI_CIPHER_MAX) - return table[cipher]; - else - return table[RNM_WIFI_CIPHER_UNKNOWN]; -} - -static int parse_get_mac_rsp_msg(struct usbh_bl616 *bl616_class, void *buf, int buf_len) -{ - usb_data_t *usb_hdr = buf; - rnm_mac_addr_ind_msg_t *rsp = buf + sizeof(usb_data_t); - - if (buf_len != sizeof(usb_data_t) + sizeof(rnm_mac_addr_ind_msg_t)) { - return -1; - } - if (usb_hdr->type != USBWIFI_DATA_TYPE_CMD || usb_hdr->length != sizeof(rnm_mac_addr_ind_msg_t)) { - return -1; - } - if (rsp->hdr.cmd != BFLB_CMD_GET_MAC_ADDR || !(rsp->hdr.flags & RNM_MSG_FLAG_ACK)) { - return -1; - } - memcpy(bl616_class->sta_mac, rsp->sta_mac, 6); - memcpy(bl616_class->ap_mac, rsp->ap_mac, 6); - - return 0; -} - -static int usbh_bl616_bulk_in_transfer(struct usbh_bl616 *bl616_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &bl616_class->bulkin_urb; - - usbh_bulk_urb_fill(urb, bl616_class->hport, bl616_class->bulkin, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -static int usbh_bl616_bulk_out_transfer(struct usbh_bl616 *bl616_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) -{ - int ret; - struct usbh_urb *urb = &bl616_class->bulkout_urb; - - usbh_bulk_urb_fill(urb, bl616_class->hport, bl616_class->bulkout, buffer, buflen, timeout, NULL, NULL); - ret = usbh_submit_urb(urb); - if (ret == 0) { - ret = urb->actual_length; - } - return ret; -} - -static int usbh_bl616_get_wifi_mac(struct usbh_bl616 *bl616_class) -{ - int ret; - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_base_msg_t *rnm_msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(rnm_msg, 0, sizeof(rnm_base_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_base_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - rnm_msg->cmd = BFLB_CMD_GET_MAC_ADDR; - - msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); - - ret = usbh_bl616_bulk_out_transfer(bl616_class, g_bl616_tx_buffer, msg_len, 500); - if (ret < 0) { - return ret; - } - ret = usbh_bl616_bulk_in_transfer(bl616_class, g_bl616_rx_buffer, sizeof(g_bl616_rx_buffer), 500); - if (ret < 0) { - return ret; - } - - ret = parse_get_mac_rsp_msg(bl616_class, g_bl616_rx_buffer, ret); - return ret; -} - -static int usbh_bl616_wifi_open(struct usbh_bl616 *bl616_class) -{ - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(msg, 0, sizeof(rnm_base_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_base_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - msg->cmd = BFLB_CMD_HELLO; - - msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); - - return usbh_bl616_bulk_out_transfer(bl616_class, g_bl616_tx_buffer, msg_len, 500); -} - -static int usbh_bl616_wifi_close(struct usbh_bl616 *bl616_class) -{ - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(msg, 0, sizeof(rnm_base_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_base_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - msg->cmd = BFLB_CMD_UNLOAD_DRV; - - msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); - - return usbh_bl616_bulk_out_transfer(bl616_class, g_bl616_tx_buffer, msg_len, 500); -} - -int usbh_bl616_wifi_sta_connect(const char *ssid, - const int ssid_len, - const char *password, - const int pwd_len) -{ - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_sta_connect_msg_t *msg = (rnm_sta_connect_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(msg, 0, sizeof(rnm_sta_connect_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_sta_connect_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - msg->hdr.cmd = BFLB_CMD_STA_CONNECT; - msg->hdr.msg_id = 0x0001; - msg->hdr.session_id = 0x0002; - msg->ssid_len = ssid_len; - memcpy(msg->ssid, ssid, ssid_len); - if (password) { - memcpy(msg->password, password, pwd_len); - } - - msg_len = sizeof(usb_data_t) + sizeof(rnm_sta_connect_msg_t); - - return usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); -} - -int usbh_bl616_wifi_sta_disconnect(void) -{ - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(msg, 0, sizeof(rnm_base_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_base_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - msg->cmd = BFLB_CMD_STA_DISCONNECT; - - msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); - - return usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); -} - -int usbh_bl616_get_wifi_scan_result(void) -{ - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(msg, 0, sizeof(rnm_base_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_base_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - msg->cmd = BFLB_CMD_SCAN_RESULTS; - - msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); - - return usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); -} - -int usbh_bl616_wifi_scan(void) -{ - int ret; - uint32_t msg_len; - usb_data_t *usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - rnm_base_msg_t *msg = (rnm_base_msg_t *)(g_bl616_tx_buffer + sizeof(usb_data_t)); - - memset(usb_hdr, 0, sizeof(usb_data_t)); - memset(msg, 0, sizeof(rnm_base_msg_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_CMD; - usb_hdr->length = sizeof(rnm_base_msg_t); - usb_hdr->payload_offset = sizeof(usb_data_t); - - msg->cmd = BFLB_CMD_SCAN; - - msg_len = sizeof(usb_data_t) + sizeof(rnm_base_msg_t); - - ret = usbh_bl616_bulk_out_transfer(&g_bl616_class, g_bl616_tx_buffer, msg_len, 500); - if (ret < 0) { - return ret; - } - - usb_osal_msleep(500); - return usbh_bl616_get_wifi_scan_result(); -} - -static int usbh_bl616_connect(struct usbh_hubport *hport, uint8_t intf) -{ - struct usb_endpoint_descriptor *ep_desc; - int ret = 0; - - struct usbh_bl616 *bl616_class = &g_bl616_class; - - memset(bl616_class, 0, sizeof(struct usbh_bl616)); - - bl616_class->hport = hport; - bl616_class->intf = intf; - - hport->config.intf[intf].priv = bl616_class; - - for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { - ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; - - if (ep_desc->bEndpointAddress & 0x80) { - USBH_EP_INIT(bl616_class->bulkin, ep_desc); - } else { - USBH_EP_INIT(bl616_class->bulkout, ep_desc); - } - } - - usbh_bl616_get_wifi_mac(bl616_class); - usbh_bl616_wifi_close(bl616_class); - usbh_bl616_wifi_open(bl616_class); - - USB_LOG_INFO("BL616 WIFI STA MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", - bl616_class->sta_mac[0], - bl616_class->sta_mac[1], - bl616_class->sta_mac[2], - bl616_class->sta_mac[3], - bl616_class->sta_mac[4], - bl616_class->sta_mac[5]); - - USB_LOG_INFO("BL616 WIFI AP MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", - bl616_class->ap_mac[0], - bl616_class->ap_mac[1], - bl616_class->ap_mac[2], - bl616_class->ap_mac[3], - bl616_class->ap_mac[4], - bl616_class->ap_mac[5]); - - strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); - - USB_LOG_INFO("Register BL616 WIFI Class:%s\r\n", hport->config.intf[intf].devname); - - usbh_bl616_run(bl616_class); - return ret; -} - -static int usbh_bl616_disconnect(struct usbh_hubport *hport, uint8_t intf) -{ - int ret = 0; - - struct usbh_bl616 *bl616_class = (struct usbh_bl616 *)hport->config.intf[intf].priv; - - if (bl616_class) { - if (bl616_class->bulkin) { - usbh_kill_urb(&bl616_class->bulkin_urb); - } - - if (bl616_class->bulkout) { - usbh_kill_urb(&bl616_class->bulkout_urb); - } - - if (hport->config.intf[intf].devname[0] != '\0') { - usb_osal_thread_schedule_other(); - USB_LOG_INFO("Unregister BL616 WIFI Class:%s\r\n", hport->config.intf[intf].devname); - usbh_bl616_stop(bl616_class); - } - - memset(bl616_class, 0, sizeof(struct usbh_bl616)); - } - - return ret; -} - -void usbh_bl616_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) -{ - int ret; - usb_data_t *usb_hdr; - rnm_base_msg_t *msg; - rnm_sta_ip_update_ind_msg_t *ipmsg; - rnm_scan_ind_msg_t *scanmsg; - uint8_t *data; - - (void)CONFIG_USB_OSAL_THREAD_GET_ARGV; - USB_LOG_INFO("Create bl616 wifi rx thread\r\n"); - - while (1) { - ret = usbh_bl616_bulk_in_transfer(&g_bl616_class, g_bl616_rx_buffer, sizeof(g_bl616_rx_buffer), USB_OSAL_WAITING_FOREVER); - if (ret < 0) { - break; - } - - usb_hdr = (usb_data_t *)g_bl616_rx_buffer; - - if (usb_hdr->type == USBWIFI_DATA_TYPE_CMD) { - msg = (rnm_base_msg_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); - - switch (msg->cmd) { - case BFLB_CMD_STA_CONNECTED_IND: - USB_LOG_INFO("AP connected\n"); - g_bl616_class.connect_status = true; - usbh_bl616_sta_connect_callback(); - - break; - case BFLB_CMD_STA_DISCONNECTED_IND: - if (g_bl616_class.connect_status == true) { - g_bl616_class.connect_status = false; - USB_LOG_INFO("AP disconnected\n"); - usbh_bl616_sta_disconnect_callback(); - } - break; - case BFLB_CMD_STA_IP_UPDATE_IND: - ipmsg = (rnm_sta_ip_update_ind_msg_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); - - USB_LOG_INFO("WIFI IP update\r\n"); - USB_LOG_INFO("WIFI IPv4 Address : %d:%d:%d:%d\r\n", - ipmsg->ip4_addr[0], - ipmsg->ip4_addr[1], - ipmsg->ip4_addr[2], - ipmsg->ip4_addr[3]); - USB_LOG_INFO("WIFI IPv4 Mask : %d:%d:%d:%d\r\n", - ipmsg->ip4_mask[0], - ipmsg->ip4_mask[1], - ipmsg->ip4_mask[2], - ipmsg->ip4_mask[3]); - USB_LOG_INFO("WIFI IPv4 Gateway : %d:%d:%d:%d\r\n\r\n", - ipmsg->ip4_gw[0], - ipmsg->ip4_gw[1], - ipmsg->ip4_gw[2], - ipmsg->ip4_gw[3]); - - g_bl616_class.mode = BL_MODE_STA; - usbh_bl616_sta_update_ip(ipmsg->ip4_addr, ipmsg->ip4_mask, ipmsg->ip4_gw); - break; - case BFLB_CMD_SCAN_RESULTS: - scanmsg = (rnm_scan_ind_msg_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); - USB_LOG_INFO("WIFI scan result:\r\n"); - for (uint32_t i = 0; i < scanmsg->num; ++i) { - struct bf1b_wifi_scan_record *r = &scanmsg->records[i]; - USB_LOG_INFO("BSSID " MAC_FMT ", channel %u, rssi %d, auth %s, cipher %s, SSID %s\r\n", - ARR_ELE_6(r->bssid), r->channel, r->rssi, - auth_to_str(r->auth_mode), cipher_to_str(r->cipher), r->ssid); - } - break; - default: - break; - } - } else if (usb_hdr->type == USBWIFI_DATA_TYPE_PKT) { - data = (uint8_t *)(g_bl616_rx_buffer + usb_hdr->payload_offset); - usbh_bl616_eth_input(data, usb_hdr->length); - } else { - } - } - - USB_LOG_INFO("Delete bl616 wifi rx thread\r\n"); - usb_osal_thread_delete(NULL); -} - -uint8_t *usbh_bl616_get_eth_txbuf(void) -{ - return (g_bl616_tx_buffer + sizeof(usb_data_t)); -} - -int usbh_bl616_eth_output(uint32_t buflen) -{ - usb_data_t *usb_hdr; - uint32_t txlen; - - if (g_bl616_class.connect_status == false) { - return -USB_ERR_NOTCONN; - } - - usb_hdr = (usb_data_t *)g_bl616_tx_buffer; - memset(usb_hdr, 0, sizeof(usb_data_t)); - - usb_hdr->type = USBWIFI_DATA_TYPE_PKT; - usb_hdr->length = buflen; - usb_hdr->payload_offset = sizeof(usb_data_t); - - txlen = buflen + sizeof(usb_data_t); - if (!(txlen % USB_GET_MAXPACKETSIZE(g_bl616_class.bulkout->wMaxPacketSize))) { - txlen += 1; - } - USB_LOG_DBG("txlen:%d\r\n", txlen); - - usbh_bulk_urb_fill(&g_bl616_class.bulkout_urb, g_bl616_class.hport, g_bl616_class.bulkout, g_bl616_tx_buffer, txlen, USB_OSAL_WAITING_FOREVER, NULL, NULL); - return usbh_submit_urb(&g_bl616_class.bulkout_urb); -} - -int wifi_sta_connect(int argc, char **argv) -{ - if (argc < 3) { - USB_LOG_ERR("Usage: %s \r\n", argv[0]); - return -1; - } - usbh_bl616_wifi_sta_connect(argv[1], strlen(argv[1]), argv[2], strlen(argv[2])); - return 0; -} - -int wifi_scan(int argc, char **argv) -{ - (void)argc; - (void)argv; - - usbh_bl616_wifi_scan(); - return 0; -} - -__WEAK void usbh_bl616_run(struct usbh_bl616 *bl616_class) -{ - (void)bl616_class; -} - -__WEAK void usbh_bl616_stop(struct usbh_bl616 *bl616_class) -{ - (void)bl616_class; -} - -static const uint16_t bl616_id_table[][2] = { - { 0x349b, 0x616f }, - { 0, 0 }, -}; - -static const struct usbh_class_driver bl616_class_driver = { - .driver_name = "bl616_wifi", - .connect = usbh_bl616_connect, - .disconnect = usbh_bl616_disconnect -}; - -CLASS_INFO_DEFINE const struct usbh_class_info bl616_class_info = { - .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, - .bInterfaceClass = 0xff, - .bInterfaceSubClass = 0x00, - .bInterfaceProtocol = 0x00, - .id_table = bl616_id_table, - .class_driver = &bl616_class_driver -}; diff --git a/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h b/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h deleted file mode 100644 index 2d247ae2ea..0000000000 --- a/components/drivers/usb/cherryusb/class/vendor/wifi/usbh_bl616.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef USBH_BL616_H -#define USBH_BL616_H - -#define USBWIFI_DATA_TYPE_CMD 0xA55A -#define USBWIFI_DATA_TYPE_PKT 0x6996 - -#define USB_DATA_FLAG_AP_PKT (1u << 0) - -typedef enum { - BFLB_CMD_REBOOT = 0, - BFLB_CMD_RESET, - BFLB_CMD_HELLO, - BFLB_CMD_PING, - - BFLB_CMD_GET_MAC_ADDR, - - // Scan - BFLB_CMD_SCAN, - BFLB_CMD_SCAN_RESULTS, - - // STA - BFLB_CMD_STA_CONNECT, - BFLB_CMD_STA_DISCONNECT, - BFLB_CMD_STA_CONNECTED_IND, - BFLB_CMD_STA_DISCONNECTED_IND, - BFLB_CMD_STA_IP_UPDATE_IND, - BFLB_CMD_STA_SET_AUTO_RECONNECT, - BFLB_CMD_STA_GET_LINK_STATUS, - - // AP - BFLB_CMD_AP_START, - BFLB_CMD_AP_STOP, - BFLB_CMD_AP_STARTED_IND, - BFLB_CMD_AP_STOPPED_IND, - BFLB_CMD_AP_GET_STA_LIST, - - // Monitor - BFLB_CMD_MONITOR_START, - BFLB_CMD_MONITOR_STOP, - BFLB_CMD_MONITOR_SET_CHANNEL, - BFLB_CMD_MONITOR_GET_CHANNEL, - - BFLB_CMD_SET_LPM_MODE, - - // OTA - BFLB_CMD_GET_DEV_VERSION, - BFLB_CMD_OTA, - - BFLB_CMD_EXT, - - BFLB_CMD_USER_EXT, - BFLB_CMD_UNLOAD_DRV, - - BFLB_CMD_MAX, -} bflb_cmd_t; - -typedef enum { - STATUS_OK, - STATUS_NOMEM = 128, - STATUS_INVALID_INPUT, - STATUS_INVALID_MODE, - STATUS_ERR_UNSPECIFIED, - STATUS_NOT_IMPLEMENTED, -} cmd_status_t; - -typedef enum { - RNM_WIFI_AUTH_UNKNOWN = 0, - RNM_WIFI_AUTH_OPEN, - RNM_WIFI_AUTH_WEP, - RNM_WIFI_AUTH_WPA_PSK, - RNM_WIFI_AUTH_WPA2_PSK, - RNM_WIFI_AUTH_WPA_WPA2_PSK, - RNM_WIFI_AUTH_WPA_ENTERPRISE, - RNM_WIFI_AUTH_WPA3_SAE, - RNM_WIFI_AUTH_WPA2_PSK_WPA3_SAE, - RNM_WIFI_AUTH_MAX, -} rnm_wifi_auth_mode_t; - -typedef enum { - RNM_WIFI_CIPHER_UNKNOWN = 0, - RNM_WIFI_CIPHER_NONE, - RNM_WIFI_CIPHER_WEP, - RNM_WIFI_CIPHER_AES, - RNM_WIFI_CIPHER_TKIP, - RNM_WIFI_CIPHER_TKIP_AES, - RNM_WIFI_CIPHER_MAX, -} rnm_wifi_cipher_t; - -/* common header */ -typedef struct { - uint16_t cmd; - // flag ACK is used by server to indicate a response to client -#define RNM_MSG_FLAG_ACK (1 << 0) - // flag TRANSPARENT is never transfered to peer but used locally -#define RNM_MSG_FLAG_TRANSPARENT (1 << 1) - // flag ASYNC is used by server to notify client events such as STA_CONNECTED -#define RNM_MSG_FLAG_ASYNC (1 << 2) - uint16_t flags; - uint16_t status; - uint16_t msg_id; - uint16_t session_id; - uint16_t msg_id_replying; -} rnm_base_msg_t; - -typedef struct { - rnm_base_msg_t hdr; -} rnm_ack_msg_t; - -typedef struct { - rnm_base_msg_t hdr; - uint8_t sta_mac[6]; - uint8_t ap_mac[6]; -} rnm_mac_addr_ind_msg_t; - -typedef struct { - rnm_base_msg_t hdr; - uint16_t ssid_len; - uint8_t ssid[32]; - uint8_t password[64]; -} rnm_sta_connect_msg_t; - -typedef struct { - rnm_base_msg_t hdr; - uint8_t ip4_addr[4]; - uint8_t ip4_mask[4]; - uint8_t ip4_gw[4]; - uint8_t ip4_dns1[4]; - uint8_t ip4_dns2[4]; - uint8_t gw_mac[6]; -} rnm_sta_ip_update_ind_msg_t; - -struct bf1b_wifi_scan_record { - uint8_t bssid[6]; - // TODO use compressed SSID encoding to save room - uint8_t ssid[32 + 1]; - uint16_t channel; - int8_t rssi; - uint8_t auth_mode; - uint8_t cipher; -} __PACKED; - -typedef struct { - rnm_base_msg_t hdr; - uint16_t num; - struct bf1b_wifi_scan_record records[]; -} rnm_scan_ind_msg_t; - -typedef enum { - BL_MODE_NONE, - BL_MODE_STA, // card is STA - BL_MODE_AP, // card is AP - BL_MODE_STA_AP, // card is STA&AP - BL_MODE_SNIFFER, // card is sniffer - BL_MODE_MAX, -} bl_wifi_mode_t; - -typedef struct { - uint16_t type; - uint16_t length; - uint16_t flags; - uint16_t payload_offset; - uint32_t rsvd[8]; - uint8_t payload[]; -} __attribute__((aligned(4))) usb_data_t; - -struct usbh_bl616 { - struct usbh_hubport *hport; - struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ - struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ - - struct usbh_urb bulkout_urb; - struct usbh_urb bulkin_urb; - - uint8_t intf; - - uint8_t sta_mac[6]; - uint8_t ap_mac[6]; - uint8_t mode; - bool connect_status; - - void *user_data; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -int usbh_bl616_wifi_sta_connect(const char *ssid, - const int ssid_len, - const char *password, - const int pwd_len); - -int usbh_bl616_wifi_sta_disconnect(void); -int usbh_bl616_wifi_scan(void); - -void usbh_bl616_sta_connect_callback(void); -void usbh_bl616_sta_disconnect_callback(void); -void usbh_bl616_sta_update_ip(uint8_t ip4_addr[4], uint8_t ip4_mask[4], uint8_t ip4_gw[4]); - -uint8_t *usbh_bl616_get_eth_txbuf(void); -int usbh_bl616_eth_output(uint32_t buflen); -void usbh_bl616_eth_input(uint8_t *buf, uint32_t buflen); -void usbh_bl616_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV); - -void usbh_bl616_run(struct usbh_bl616 *bl616_class); -void usbh_bl616_stop(struct usbh_bl616 *bl616_class); - -int wifi_sta_connect(int argc, char **argv); -int wifi_scan(int argc, char **argv); - -#ifdef __cplusplus -} -#endif - -#endif /* USBH_BL616_H */ diff --git a/components/drivers/usb/cherryusb/class/video/usbh_video.c b/components/drivers/usb/cherryusb/class/video/usbh_video.c index 077b6bb915..18acbda37a 100644 --- a/components/drivers/usb/cherryusb/class/video/usbh_video.c +++ b/components/drivers/usb/cherryusb/class/video/usbh_video.c @@ -122,12 +122,12 @@ int usbh_videostreaming_get_cur_probe(struct usbh_video *video_class) return usbh_video_get(video_class, VIDEO_REQUEST_GET_CUR, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, (uint8_t *)&video_class->probe, 26); } -int usbh_videostreaming_set_cur_probe(struct usbh_video *video_class, uint8_t formatindex, uint8_t frameindex) +int usbh_videostreaming_set_cur_probe(struct usbh_video *video_class, uint8_t formatindex, uint8_t frameindex, uint32_t dwFrameInterval) { video_class->probe.bFormatIndex = formatindex; video_class->probe.bFrameIndex = frameindex; video_class->probe.dwMaxPayloadTransferSize = 0; - video_class->probe.dwFrameInterval = 333333; + video_class->probe.dwFrameInterval = dwFrameInterval; return usbh_video_set(video_class, VIDEO_REQUEST_SET_CUR, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, (uint8_t *)&video_class->probe, 26); } @@ -136,7 +136,6 @@ int usbh_videostreaming_set_cur_commit(struct usbh_video *video_class, uint8_t f memcpy(&video_class->commit, &video_class->probe, sizeof(struct video_probe_and_commit_controls)); video_class->commit.bFormatIndex = formatindex; video_class->commit.bFrameIndex = frameindex; - video_class->commit.dwFrameInterval = 333333; return usbh_video_set(video_class, VIDEO_REQUEST_SET_CUR, video_class->data_intf, 0x00, VIDEO_VS_COMMIT_CONTROL, (uint8_t *)&video_class->commit, 26); } @@ -154,6 +153,7 @@ int usbh_video_open(struct usbh_video *video_class, bool found = false; uint8_t formatidx = 0; uint8_t frameidx = 0; + uint32_t dwDefaultFrameInterval = 0; uint8_t step; if (!video_class || !video_class->hport) { @@ -172,6 +172,7 @@ int usbh_video_open(struct usbh_video *video_class, if ((wWidth == video_class->format[i].frame[j].wWidth) && (wHeight == video_class->format[i].frame[j].wHeight)) { frameidx = j + 1; + dwDefaultFrameInterval = video_class->format[i].frame[j].dwDefaultFrameInterval; found = true; break; } @@ -204,7 +205,7 @@ int usbh_video_open(struct usbh_video *video_class, } step = 1; - ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx); + ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx, dwDefaultFrameInterval); if (ret < 0) { goto errout; } @@ -228,7 +229,7 @@ int usbh_video_open(struct usbh_video *video_class, } step = 5; - ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx); + ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx, dwDefaultFrameInterval); if (ret < 0) { goto errout; } @@ -246,26 +247,30 @@ int usbh_video_open(struct usbh_video *video_class, } step = 8; - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = USB_REQUEST_SET_INTERFACE; - setup->wValue = altsetting; - setup->wIndex = video_class->data_intf; - setup->wLength = 0; - - ret = usbh_control_transfer(video_class->hport, setup, NULL); - if (ret < 0) { - goto errout; - } + if (!video_class->is_bulk) { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = video_class->data_intf; + setup->wLength = 0; + + ret = usbh_control_transfer(video_class->hport, setup, NULL); + if (ret < 0) { + goto errout; + } - ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[altsetting].ep[0].ep_desc; - mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; - mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; - if (ep_desc->bEndpointAddress & 0x80) { - video_class->isoin_mps = mps * (mult + 1); - USBH_EP_INIT(video_class->isoin, ep_desc); + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[altsetting].ep[0].ep_desc; + mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + if (ep_desc->bEndpointAddress & 0x80) { + video_class->isoin_mps = mps * (mult + 1); + USBH_EP_INIT(video_class->isoin, ep_desc); + } else { + return -USB_ERR_NODEV; + } } else { - video_class->isoout_mps = mps * (mult + 1); - USBH_EP_INIT(video_class->isoout, ep_desc); + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(video_class->bulkin, ep_desc); } USB_LOG_INFO("Open video and select formatidx:%u, frameidx:%u, altsetting:%u\r\n", formatidx, frameidx, altsetting); @@ -292,54 +297,62 @@ int usbh_video_close(struct usbh_video *video_class) video_class->is_opened = false; - if (video_class->isoin) { - video_class->isoin = NULL; - } - - if (video_class->isoout) { - video_class->isoout = NULL; + if (video_class->is_bulk) { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_ENDPOINT; + setup->bRequest = USB_REQUEST_CLEAR_FEATURE; + setup->wValue = USB_FEATURE_ENDPOINT_HALT; + setup->wIndex = video_class->bulkin->bEndpointAddress; + setup->wLength = 0; + } else { + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = 0; + setup->wIndex = video_class->data_intf; + setup->wLength = 0; } - setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; - setup->bRequest = USB_REQUEST_SET_INTERFACE; - setup->wValue = 0; - setup->wIndex = video_class->data_intf; - setup->wLength = 0; - ret = usbh_control_transfer(video_class->hport, setup, NULL); if (ret < 0) { return ret; } + return ret; } void usbh_video_list_info(struct usbh_video *video_class) { struct usb_endpoint_descriptor *ep_desc; - uint8_t mult; - uint16_t mps; USB_LOG_INFO("============= Video device information ===================\r\n"); USB_LOG_RAW("bcdVDC:%04x\r\n", video_class->bcdVDC); - USB_LOG_RAW("Num of altsettings:%u\r\n", video_class->num_of_intf_altsettings); - - for (uint8_t i = 0; i < video_class->num_of_intf_altsettings; i++) { - if (i == 0) { - USB_LOG_RAW("Ingore altsetting 0\r\n"); - continue; + USB_LOG_RAW("Num of altsettings:%u (%s mode)\r\n", video_class->num_of_intf_altsettings, video_class->num_of_intf_altsettings == 1 ? "bulk" : "iso"); + + video_class->is_bulk = video_class->num_of_intf_altsettings == 1 ? true : false; + + if (video_class->is_bulk) { + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[0].ep[0].ep_desc; + USB_LOG_RAW("Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize), + ep_desc->bInterval, + USB_GET_MULT(ep_desc->wMaxPacketSize)); + } else { + for (uint8_t i = 0; i < video_class->num_of_intf_altsettings; i++) { + if (i == 0) { + USB_LOG_RAW("Ingore altsetting 0\r\n"); + continue; + } + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[i].ep[0].ep_desc; + + USB_LOG_RAW("Altsetting:%u, Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + i, + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize), + ep_desc->bInterval, + USB_GET_MULT(ep_desc->wMaxPacketSize)); } - ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[i].ep[0].ep_desc; - - mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; - mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; - - USB_LOG_RAW("Altsetting:%u, Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", - i, - ep_desc->bEndpointAddress, - ep_desc->bmAttributes, - mps, - ep_desc->bInterval, - mult); } USB_LOG_RAW("bNumFormats:%u\r\n", video_class->num_of_formats); @@ -350,9 +363,10 @@ void usbh_video_list_info(struct usbh_video *video_class) USB_LOG_RAW(" Resolution:\r\n"); for (uint8_t j = 0; j < video_class->format[i].num_of_frames; j++) { USB_LOG_RAW(" FrameIndex:%u\r\n", j + 1); - USB_LOG_RAW(" wWidth: %d, wHeight: %d\r\n", - video_class->format[i].frame[j].wWidth, - video_class->format[i].frame[j].wHeight); + USB_LOG_RAW(" wWidth: %d, wHeight: %d, fps: %d\r\n", + video_class->format[i].frame[j].wWidth, + video_class->format[i].frame[j].wHeight, + (1000 / (video_class->format[i].frame[j].dwDefaultFrameInterval / 10000))); } } @@ -438,12 +452,14 @@ static int usbh_video_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) video_class->format[format_index - 1].frame[frame_index - 1].wWidth = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->wWidth; video_class->format[format_index - 1].frame[frame_index - 1].wHeight = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->wHeight; + video_class->format[format_index - 1].frame[frame_index - 1].dwDefaultFrameInterval = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->dwDefaultFrameInterval; break; case VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE: frame_index = p[DESC_bFrameIndex]; video_class->format[format_index - 1].frame[frame_index - 1].wWidth = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->wWidth; video_class->format[format_index - 1].frame[frame_index - 1].wHeight = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->wHeight; + video_class->format[format_index - 1].frame[frame_index - 1].dwDefaultFrameInterval = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->dwDefaultFrameInterval; break; default: break; @@ -476,12 +492,6 @@ static int usbh_video_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) struct usbh_video *video_class = (struct usbh_video *)hport->config.intf[intf].priv; if (video_class) { - if (video_class->isoin) { - } - - if (video_class->isoout) { - } - if (hport->config.intf[intf].devname[0] != '\0') { usb_osal_thread_schedule_other(); USB_LOG_INFO("Unregister Video Class:%s\r\n", hport->config.intf[intf].devname); diff --git a/components/drivers/usb/cherryusb/class/video/usbh_video.h b/components/drivers/usb/cherryusb/class/video/usbh_video.h index dac5792c14..9edce49b93 100644 --- a/components/drivers/usb/cherryusb/class/video/usbh_video.h +++ b/components/drivers/usb/cherryusb/class/video/usbh_video.h @@ -14,6 +14,7 @@ struct usbh_video_resolution { uint16_t wWidth; uint16_t wHeight; + uint32_t dwDefaultFrameInterval; }; struct usbh_video_format { @@ -40,7 +41,7 @@ struct usbh_videostreaming { struct usbh_video { struct usbh_hubport *hport; struct usb_endpoint_descriptor *isoin; /* ISO IN endpoint */ - struct usb_endpoint_descriptor *isoout; /* ISO OUT endpoint */ + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ uint8_t ctrl_intf; /* interface number */ uint8_t data_intf; /* interface number */ @@ -48,9 +49,9 @@ struct usbh_video { struct video_probe_and_commit_controls probe; struct video_probe_and_commit_controls commit; uint16_t isoin_mps; - uint16_t isoout_mps; bool is_opened; uint8_t current_format; + bool is_bulk; uint16_t bcdVDC; uint8_t num_of_intf_altsettings; uint8_t num_of_formats; diff --git a/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c b/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c index cb00651faa..709630cbe3 100644 --- a/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c +++ b/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c @@ -578,16 +578,6 @@ int usbh_rndis_eth_output(uint32_t buflen) return usbh_submit_urb(&g_rndis_class.bulkout_urb); } -__WEAK void usbh_rndis_run(struct usbh_rndis *rndis_class) -{ - (void)rndis_class; -} - -__WEAK void usbh_rndis_stop(struct usbh_rndis *rndis_class) -{ - (void)rndis_class; -} - static const struct usbh_class_driver rndis_class_driver = { .driver_name = "rndis", .connect = usbh_rndis_connect, @@ -602,3 +592,12 @@ CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { .id_table = NULL, .class_driver = &rndis_class_driver }; + +CLASS_INFO_DEFINE const struct usbh_class_info rndis_cdcacm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .bInterfaceClass = USB_DEVICE_CLASS_CDC, + .bInterfaceSubClass = CDC_ABSTRACT_CONTROL_MODEL, + .bInterfaceProtocol = 0xff, + .id_table = NULL, + .class_driver = &rndis_class_driver +}; diff --git a/components/drivers/usb/cherryusb/common/usb_def.h b/components/drivers/usb/cherryusb/common/usb_def.h index 27b4d82155..be5ab06103 100644 --- a/components/drivers/usb/cherryusb/common/usb_def.h +++ b/components/drivers/usb/cherryusb/common/usb_def.h @@ -318,24 +318,24 @@ /* Setup packet definition used to read raw data from USB line */ struct usb_setup_packet { /** Request type. Bits 0:4 determine recipient, see - * \ref usb_request_recipient. Bits 5:6 determine type, see - * \ref usb_request_type. Bit 7 determines data transfer direction, see - * \ref usb_endpoint_direction. - */ + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ uint8_t bmRequestType; /** Request. If the type bits of bmRequestType are equal to - * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD - * "USB_REQUEST_TYPE_STANDARD" then this field refers to - * \ref usb_standard_request. For other cases, use of this field is - * application-specific. */ + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ uint8_t bRequest; /** Value. Varies according to request */ uint16_t wValue; /** Index. Varies according to request, typically used to pass an index - * or offset */ + * or offset */ uint16_t wIndex; /** Number of bytes to transfer */ @@ -556,7 +556,7 @@ struct usb_bos_header_descriptor { } __PACKED; /* BOS Capability platform Descriptor */ -struct usb_bos_capability_platform_descriptor { +struct usb_bos_capability_platform_common_descriptor { uint8_t bLength; uint8_t bDescriptorType; uint8_t bDevCapabilityType; @@ -564,16 +564,26 @@ struct usb_bos_capability_platform_descriptor { uint8_t PlatformCapabilityUUID[16]; } __PACKED; -/* BOS Capability MS OS Descriptors version 2 */ -struct usb_bos_capability_msosv2_descriptor { +/* Microsoft OS 2.0 Platform Capability Descriptor +* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ +* microsoft-defined-usb-descriptors +* Adapted from the source: +* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c +* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c +*/ +struct usb_bos_capability_platform_winusb_descriptor { + struct usb_bos_capability_platform_common_descriptor common; uint32_t dwWindowsVersion; uint16_t wMSOSDescriptorSetTotalLength; uint8_t bVendorCode; uint8_t bAltEnumCode; } __PACKED; -/* BOS Capability webusb */ -struct usb_bos_capability_webusb_descriptor { +/* WebUSB Platform Capability Descriptor: +* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor +*/ +struct usb_bos_capability_platform_webusb_descriptor { + struct usb_bos_capability_platform_common_descriptor common; uint16_t bcdVersion; uint8_t bVendorCode; uint8_t iLandingPage; @@ -587,26 +597,6 @@ struct usb_bos_capability_extension_descriptor { uint32_t bmAttributes; } __PACKED; -/* Microsoft OS 2.0 Platform Capability Descriptor -* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ -* microsoft-defined-usb-descriptors -* Adapted from the source: -* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c -* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c -*/ -struct usb_bos_capability_platform_msosv2_descriptor { - struct usb_bos_capability_platform_descriptor platform_msos; - struct usb_bos_capability_msosv2_descriptor data_msosv2; -} __PACKED; - -/* WebUSB Platform Capability Descriptor: -* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor -*/ -struct usb_bos_capability_platform_webusb_descriptor { - struct usb_bos_capability_platform_descriptor platform_webusb; - struct usb_bos_capability_webusb_descriptor data_webusb; -} __PACKED; - struct usb_webusb_url_descriptor { uint8_t bLength; uint8_t bDescriptorType; @@ -625,18 +615,12 @@ struct usb_bos_descriptor { uint32_t string_len; }; -/* USB Device Capability Descriptor */ -struct usb_device_capability_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; -} __PACKED; - /** USB descriptor header */ struct usb_desc_header { uint8_t bLength; /**< descriptor length */ uint8_t bDescriptorType; /**< descriptor type */ }; + // clang-format off #define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \ 0x12, /* bLength */ \ @@ -705,7 +689,7 @@ struct usb_desc_header { WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ bInterval /* bInterval */ -#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ +#define USB_IAD_DESCRIPTOR_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ 0x08, /* bLength */ \ USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ bFirstInterface, /* bFirstInterface */ \ @@ -716,9 +700,145 @@ struct usb_desc_header { 0x00 /* iFunction */ #define USB_LANGID_INIT(id) \ - 0x04, /* bLength */ \ + 0x04, /* bLength */ \ USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ WBVAL(id) /* wLangID0 */ + +#define USB_BOS_HEADER_DESCRIPTOR_INIT(wTotalLength, bNumDeviceCaps) \ + 0x05, /* bLength */ \ + USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE, /* bDescriptorType */\ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumDeviceCaps /* bNumDeviceCaps */ + +#define USB_BOS_CAP_PLATFORM_WEBUSB_DESCRIPTOR_INIT(bVendorCode, iLandingPage) \ + 0x18, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY, /* bDescriptorType */ \ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ \ + 0x00, /* bReserved */ \ + 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, /* PlatformCapabilityUUID */ \ + 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65, \ + WBVAL(0x0100), /* bcdVersion */ \ + bVendorCode, /* bVendorCode */ \ + iLandingPage /* iLandingPage */ + +#define USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_INIT(bVendorCode, wMSOSDescriptorSetTotalLength) \ + 0x1C, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY, /* bDescriptorType */ \ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ \ + 0x00, /* bReserved */ \ + 0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, /* PlatformCapabilityUUID */ \ + 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F, \ + DBVAL(0x06030000), /* dwWindowsVersion */ \ + WBVAL(wMSOSDescriptorSetTotalLength), /* wMSOSDescriptorSetTotalLength */ \ + bVendorCode, /* bVendorCode */ \ + 0x00 /* bAltEnumCode */ + +#define USB_BOS_CAP_PLATFORM_WEBUSB_DESCRIPTOR_LEN 24 +#define USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_LEN 28 + +#define USB_MSOSV1_STRING_DESCRIPTOR_INIT(vendor_code) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + 'M', 0, /* bString[0] */ \ + 'S', 0, /* bString[1] */ \ + 'F', 0, /* bString[2] */ \ + 'T', 0, /* bString[3] */ \ + '1', 0, /* bString[4] */ \ + '0', 0, /* bString[5] */ \ + '0', 0, /* bString[6] */ \ + vendor_code, /* bMS_VendorCode */ \ + 0x00 /* bPad */ + +#define USB_MSOSV1_COMP_ID_HEADER_DESCRIPTOR_INIT(bCount) \ + DBVAL((sizeof(struct usb_msosv1_compat_id_header_descriptor) + sizeof(struct usb_msosv1_comp_id_function_descriptor) * bCount)), /* dwLength */ \ + WBVAL(0x0100), /* bcdVersion */ \ + WBVAL(0x0004), /* wIndex */ \ + bCount, /* bCount */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved[7] */ + +#define USB_MSOSV1_COMP_ID_FUNCTION_WINUSB_DESCRIPTOR_INIT(bFirstInterfaceNumber) \ + bFirstInterfaceNumber, /* bFirstInterfaceNumber */\ + 0x01, /* reserved1 */ \ + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* compatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* subCompatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved2[6] */ + +#define USB_MSOSV1_COMP_ID_FUNCTION_MTP_DESCRIPTOR_INIT(bFirstInterfaceNumber)\ + bFirstInterfaceNumber, /* bFirstInterfaceNumber */\ + 0x01, /* reserved1 */ \ + 'M', 'T', 'P', 'U', 'S', 'B', 0x00, 0x00, /* compatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* subCompatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved2[6] */ + +#define USB_MSOSV1_COMP_ID_FUNCTION_ADB_DESCRIPTOR_INIT(bFirstInterfaceNumber)\ + bFirstInterfaceNumber, * bFirstInterfaceNumber */\ + 0x01, /* reserved1 */ \ + 'A', 'D', 'B', 0x00, 0x00, 0x00, 0x00, 0x00, /* compatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* subCompatibleID[8] */ \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* reserved2[6] */ + +#define USB_MSOSV1_COMP_ID_DESCRIPTOR_LEN(bCount) \ + (sizeof(struct usb_msosv1_compat_id_header_descriptor) + sizeof(struct usb_msosv1_comp_id_function_descriptor) * (bCount)) + +#define USB_MSOSV2_COMP_ID_SET_HEADER_DESCRIPTOR_INIT(wDescriptorSetTotalLength) \ + WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ \ + WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ \ + DBVAL(0x06030000), /* dwWindowsVersion */ \ + WBVAL(wDescriptorSetTotalLength) /* wDescriptorSetTotalLength */ + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_SINGLE_DESCRIPTOR_INIT() \ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ \ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ \ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ \ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ \ + WBVAL(132), /* wLength */ \ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ \ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_SZ), /* wPropertyDataType */ \ + WBVAL(42), /* wPropertyNameLength bPropertyName: "DeviceInterfaceGUID" */ \ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, \ + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, \ + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, \ + WBVAL(80), /* wPropertyDataLength */ \ + '{', 0, \ + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, \ + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, \ + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, \ + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', \ + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, \ + '}', 0, 0, 0, 0, 0 + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_SINGLE_DESCRIPTOR_LEN \ + (WINUSB_FEATURE_COMPATIBLE_ID_SIZE + 132) + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT(bFirstInterfaceNumber) \ + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ \ + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ \ + bFirstInterfaceNumber, /* bFirstInterface*/ \ + 0, /* bReserved */ \ + WBVAL((WINUSB_FUNCTION_SUBSET_HEADER_SIZE + WINUSB_FEATURE_COMPATIBLE_ID_SIZE + 132)), /* wSubsetLength */\ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ \ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ \ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ \ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ \ + WBVAL(132), /* wLength */ \ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ \ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ \ + WBVAL(42), /* wPropertyNameLength bPropertyName: "DeviceInterfaceGUID" */ \ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, \ + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, \ + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, \ + WBVAL(80), /* wPropertyDataLength */ \ + '{', 0, \ + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, \ + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, \ + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, \ + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', \ + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, \ + '}', 0, 0, 0, 0, 0 + +#define USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_LEN \ + (WINUSB_FUNCTION_SUBSET_HEADER_SIZE + WINUSB_FEATURE_COMPATIBLE_ID_SIZE + 132) + // clang-format on #endif /* USB_DEF_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_otg.h b/components/drivers/usb/cherryusb/common/usb_otg.h new file mode 100644 index 0000000000..032d2e9f74 --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_otg.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OTG_H +#define USB_OTG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define USBOTG_MODE_HOST 0 +#define USBOTG_MODE_DEVICE 1 +#define USBOTG_MODE_OTG 2 + +/** + * @brief usb otg controller hardware or gpio id simulator init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_otg_init(uint8_t busid); +/** + * @brief usb otg controller hardware or gpio id simulator deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_otg_deinit(uint8_t busid); + +/* called by user */ +void USBOTG_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_OTG_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/common/usb_util.h b/components/drivers/usb/cherryusb/common/usb_util.h index 96a14d374c..521bf27f56 100644 --- a/components/drivers/usb/cherryusb/common/usb_util.h +++ b/components/drivers/usb/cherryusb/common/usb_util.h @@ -185,8 +185,8 @@ (field)[3] = (uint8_t)((value) >> 0); \ } while (0) -#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF) -#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF) +#define WBVAL(x) ((x) & 0xFF), (((x) >> 8) & 0xFF) +#define DBVAL(x) ((x) & 0xFF), (((x) >> 8) & 0xFF), (((x) >> 16) & 0xFF), (((x) >> 24) & 0xFF) #define PP_NARG(...) \ PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) @@ -209,6 +209,23 @@ 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 +/* + * Divide positive or negative dividend by positive or negative divisor + * and round to closest integer. Result is undefined for negative + * divisors if the dividend variable type is unsigned and for negative + * dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || \ + (((__x) > 0) == ((__d) > 0))) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ + }) + #define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) #define USB_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1)) diff --git a/components/drivers/usb/cherryusb/common/usb_version.h b/components/drivers/usb/cherryusb/common/usb_version.h index 2d70bb4c5a..3e4c2aa395 100644 --- a/components/drivers/usb/cherryusb/common/usb_version.h +++ b/components/drivers/usb/cherryusb/common/usb_version.h @@ -15,7 +15,7 @@ #undef CHERRYUSB_VERSION_STR #endif -#define CHERRYUSB_VERSION 0x010502 -#define CHERRYUSB_VERSION_STR "v1.5.2" +#define CHERRYUSB_VERSION 0x010600 +#define CHERRYUSB_VERSION_STR "v1.6.0" #endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/core/usbd_core.c b/components/drivers/usb/cherryusb/core/usbd_core.c index 66ec4dc60c..bdbcfd07f7 100644 --- a/components/drivers/usb/cherryusb/core/usbd_core.c +++ b/components/drivers/usb/cherryusb/core/usbd_core.c @@ -48,16 +48,10 @@ USB_NOCACHE_RAM_SECTION struct usbd_core_priv { uint32_t ep0_data_buf_len; /** Zero length packet flag of control transfer */ bool zlp_flag; + /** Pointer to registered descriptors */ -#ifdef CONFIG_USBDEV_ADVANCE_DESC const struct usb_descriptor *descriptors; -#else - const uint8_t *descriptors; - struct usb_msosv1_descriptor *msosv1_desc; - struct usb_msosv2_descriptor *msosv2_desc; - struct usb_bos_descriptor *bos_desc; - struct usb_webusb_descriptor *webusb_url_desc; -#endif + /* Buffer used for storing standard, class and vendor request data */ USB_MEM_ALIGNX uint8_t req_data[USB_ALIGN_UP(CONFIG_USBDEV_REQUEST_BUFFER_LEN, CONFIG_USB_ALIGN_SIZE)]; @@ -69,9 +63,7 @@ USB_NOCACHE_RAM_SECTION struct usbd_core_priv { bool remote_wakeup_support; bool remote_wakeup_enabled; bool is_suspend; -#ifdef CONFIG_USBDEV_ADVANCE_DESC uint8_t speed; -#endif #ifdef CONFIG_USBDEV_TEST_MODE bool test_req; #endif @@ -180,7 +172,6 @@ static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descrip * * @return true if the descriptor was found, false otherwise */ -#ifdef CONFIG_USBDEV_ADVANCE_DESC static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) { uint8_t type = 0U; @@ -326,93 +317,6 @@ static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **da } return found; } -#else -static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) -{ - uint8_t type = 0U; - uint8_t index = 0U; - uint8_t *p = NULL; - uint32_t cur_index = 0U; - bool found = false; - - type = HI_BYTE(type_index); - index = LO_BYTE(type_index); - - if ((type == USB_DESCRIPTOR_TYPE_STRING) && (index == USB_OSDESC_STRING_DESC_INDEX)) { - if (!g_usbd_core[busid].msosv1_desc) { - return false; - } - - *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->string; - //memcpy(*data, (uint8_t *)g_usbd_core[busid].msosv1_desc->string, g_usbd_core[busid].msosv1_desc->string[0]); - *len = g_usbd_core[busid].msosv1_desc->string[0]; - - return true; - } else if (type == USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE) { - if (!g_usbd_core[busid].bos_desc) { - return false; - } - - *data = (uint8_t *)g_usbd_core[busid].bos_desc->string; - //memcpy(*data, (uint8_t *)g_usbd_core[busid].bos_desc->string, g_usbd_core[busid].bos_desc->string_len); - *len = g_usbd_core[busid].bos_desc->string_len; - return true; - } - /* - * Invalid types of descriptors, - * see USB Spec. Revision 2.0, 9.4.3 Get Descriptor - */ - else if ((type == USB_DESCRIPTOR_TYPE_INTERFACE) || (type == USB_DESCRIPTOR_TYPE_ENDPOINT) || -#ifndef CONFIG_USB_HS - (type > USB_DESCRIPTOR_TYPE_ENDPOINT)) { -#else - (type > USB_DESCRIPTOR_TYPE_OTHER_SPEED)) { -#endif - return false; - } - - p = (uint8_t *)g_usbd_core[busid].descriptors; - - cur_index = 0U; - - while (p[DESC_bLength] != 0U) { - if (p[DESC_bDescriptorType] == type) { - if (cur_index == index) { - found = true; - break; - } - - cur_index++; - } - - /* skip to next descriptor */ - p += p[DESC_bLength]; - } - - if (found) { - if ((type == USB_DESCRIPTOR_TYPE_CONFIGURATION) || ((type == USB_DESCRIPTOR_TYPE_OTHER_SPEED))) { - /* configuration or other speed descriptor is an - * exception, length is at offset 2 and 3 - */ - *len = (p[CONF_DESC_wTotalLength]) | - (p[CONF_DESC_wTotalLength + 1] << 8); - - g_usbd_core[busid].self_powered = (p[7] & USB_CONFIG_POWERED_MASK) ? true : false; - g_usbd_core[busid].remote_wakeup_support = (p[7] & USB_CONFIG_REMOTE_WAKEUP) ? true : false; - } else { - /* normally length is at offset 0 */ - *len = p[DESC_bLength]; - } - *data = p; - //memcpy(*data, p, *len); - } else { - /* nothing found */ - USB_LOG_ERR("descriptor not found!\r\n", type, index); - } - - return found; -} -#endif /** * @brief set USB configuration @@ -436,11 +340,8 @@ static bool usbd_set_configuration(uint8_t busid, uint8_t config_index, uint8_t uint32_t desc_len = 0; uint32_t current_desc_len = 0; -#ifdef CONFIG_USBDEV_ADVANCE_DESC p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); -#else - p = (uint8_t *)g_usbd_core[busid].descriptors; -#endif + /* configure endpoints for this configuration/altsetting */ while (p[DESC_bLength] != 0U) { switch (p[DESC_bDescriptorType]) { @@ -508,11 +409,8 @@ static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting uint32_t desc_len = 0; uint32_t current_desc_len = 0; -#ifdef CONFIG_USBDEV_ADVANCE_DESC p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); -#else - p = (uint8_t *)g_usbd_core[busid].descriptors; -#endif + USB_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting); while (p[DESC_bLength] != 0U) { @@ -683,11 +581,7 @@ static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packe uint32_t current_desc_len = 0; uint8_t cur_iface = 0xFF; -#ifdef CONFIG_USBDEV_ADVANCE_DESC p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); -#else - p = (uint8_t *)g_usbd_core[busid].descriptors; -#endif /* Only when device is configured, then interface requests can be valid. */ if (!is_device_configured(busid)) { @@ -925,7 +819,7 @@ static int usbd_class_request_handler(uint8_t busid, struct usb_setup_packet *se static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) { uint32_t desclen; -#ifdef CONFIG_USBDEV_ADVANCE_DESC + if (g_usbd_core[busid].descriptors->msosv1_descriptor) { if (setup->bRequest == g_usbd_core[busid].descriptors->msosv1_descriptor->vendor_code) { switch (setup->wIndex) { @@ -982,61 +876,7 @@ static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *s } } } -#else - if (g_usbd_core[busid].msosv1_desc) { - if (setup->bRequest == g_usbd_core[busid].msosv1_desc->vendor_code) { - switch (setup->wIndex) { - case 0x04: - *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->compat_id; - desclen = g_usbd_core[busid].msosv1_desc->compat_id[0] + - (g_usbd_core[busid].msosv1_desc->compat_id[1] << 8) + - (g_usbd_core[busid].msosv1_desc->compat_id[2] << 16) + - (g_usbd_core[busid].msosv1_desc->compat_id[3] << 24); - //memcpy(*data, g_usbd_core[busid].msosv1_desc->compat_id, desclen); - *len = desclen; - return 0; - case 0x05: - *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue]; - desclen = g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][0] + - (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][1] << 8) + - (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][2] << 16) + - (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][3] << 24); - //memcpy(*data, g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue], desclen); - *len = desclen; - return 0; - default: - return -1; - } - } - } else if (g_usbd_core[busid].msosv2_desc) { - if (setup->bRequest == g_usbd_core[busid].msosv2_desc->vendor_code) { - switch (setup->wIndex) { - case WINUSB_REQUEST_GET_DESCRIPTOR_SET: - *data = (uint8_t *)g_usbd_core[busid].msosv2_desc->compat_id; - //memcpy(*data, g_usbd_core[busid].msosv2_desc->compat_id, g_usbd_core[busid].msosv2_desc->compat_id_len); - *len = g_usbd_core[busid].msosv2_desc->compat_id_len; - return 0; - default: - return -1; - } - } - } - if (g_usbd_core[busid].webusb_url_desc) { - if (setup->bRequest == g_usbd_core[busid].webusb_url_desc->vendor_code) { - switch (setup->wIndex) { - case WEBUSB_REQUEST_GET_URL: - desclen = g_usbd_core[busid].webusb_url_desc->string_len; - *data = (uint8_t *)g_usbd_core[busid].webusb_url_desc->string; - //memcpy(*data, g_usbd_core[busid].webusb_url_desc->string, desclen); - *len = desclen; - return 0; - default: - return -1; - } - } - } -#endif for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { struct usbd_interface *intf = g_usbd_core[busid].intf[i]; @@ -1145,18 +985,22 @@ void usbd_event_suspend_handler(uint8_t busid) void usbd_event_reset_handler(uint8_t busid) { + struct usb_endpoint_descriptor ep0; + usbd_set_address(busid, 0); g_usbd_core[busid].device_address = 0; g_usbd_core[busid].configuration = 0; g_usbd_core[busid].ep0_next_state = USBD_EP0_STATE_SETUP; -#ifdef CONFIG_USBDEV_ADVANCE_DESC g_usbd_core[busid].speed = USB_SPEED_UNKNOWN; -#endif - struct usb_endpoint_descriptor ep0; + + USB_ASSERT_MSG(g_usbd_core[busid].descriptors->device_descriptor_callback != NULL, + "device_descriptor_callback is NULL\r\n"); + + struct usb_device_descriptor *device_desc = (struct usb_device_descriptor *)g_usbd_core[busid].descriptors->device_descriptor_callback(g_usbd_core[busid].speed); + ep0.wMaxPacketSize = device_desc->bMaxPacketSize0; ep0.bLength = 7; ep0.bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; - ep0.wMaxPacketSize = USB_CTRL_EP_MPS; ep0.bmAttributes = USB_ENDPOINT_TYPE_CONTROL; ep0.bEndpointAddress = USB_CONTROL_IN_EP0; ep0.bInterval = 0; @@ -1369,7 +1213,6 @@ void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbyt } } -#ifdef CONFIG_USBDEV_ADVANCE_DESC void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc) { memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); @@ -1382,42 +1225,6 @@ void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc) g_usbd_core[busid].rx_msg[0].ep = 0x00; g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; } -#else -void usbd_desc_register(uint8_t busid, const uint8_t *desc) -{ - memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); - - g_usbd_core[busid].descriptors = desc; - g_usbd_core[busid].intf_offset = 0; - - g_usbd_core[busid].tx_msg[0].ep = 0x80; - g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; - g_usbd_core[busid].rx_msg[0].ep = 0x00; - g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; -} - -/* Register MS OS Descriptors version 1 */ -void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc) -{ - g_usbd_core[busid].msosv1_desc = desc; -} - -/* Register MS OS Descriptors version 2 */ -void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc) -{ - g_usbd_core[busid].msosv2_desc = desc; -} - -void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc) -{ - g_usbd_core[busid].bos_desc = desc; -} - -void usbd_webusb_desc_register(uint8_t busid, struct usb_webusb_descriptor *desc) -{ - g_usbd_core[busid].webusb_url_desc = desc; -} -#endif void usbd_add_interface(uint8_t busid, struct usbd_interface *intf) { @@ -1536,11 +1343,7 @@ int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uin int ret; struct usbd_bus *bus; - if (busid >= CONFIG_USBDEV_MAX_BUS) { - USB_LOG_ERR("bus overflow\r\n"); - while (1) { - } - } + USB_ASSERT_MSG(busid < CONFIG_USBDEV_MAX_BUS, "bus overflow\r\n"); bus = &g_usbdev_bus[busid]; bus->reg_base = reg_base; @@ -1569,23 +1372,18 @@ int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uin int usbd_deinitialize(uint8_t busid) { - if (busid >= CONFIG_USBDEV_MAX_BUS) { - USB_LOG_ERR("bus overflow\r\n"); - while (1) { - } - } + USB_ASSERT_MSG(busid < CONFIG_USBDEV_MAX_BUS, "bus overflow\r\n"); g_usbd_core[busid].event_handler(busid, USBD_EVENT_DEINIT); usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); usb_dc_deinit(busid); - g_usbd_core[busid].intf_offset = 0; #ifdef CONFIG_USBDEV_EP0_THREAD - if (g_usbd_core[busid].usbd_ep0_mq) { - usb_osal_mq_delete(g_usbd_core[busid].usbd_ep0_mq); - } if (g_usbd_core[busid].usbd_ep0_thread) { usb_osal_thread_delete(g_usbd_core[busid].usbd_ep0_thread); } + if (g_usbd_core[busid].usbd_ep0_mq) { + usb_osal_mq_delete(g_usbd_core[busid].usbd_ep0_mq); + } #endif return 0; diff --git a/components/drivers/usb/cherryusb/core/usbd_core.h b/components/drivers/usb/cherryusb/core/usbd_core.h index 585668267c..314ccbec71 100644 --- a/components/drivers/usb/cherryusb/core/usbd_core.h +++ b/components/drivers/usb/cherryusb/core/usbd_core.h @@ -56,6 +56,7 @@ enum usbd_event_type { typedef int (*usbd_request_handler)(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len); typedef void (*usbd_endpoint_callback)(uint8_t busid, uint8_t ep, uint32_t nbytes); typedef void (*usbd_notify_handler)(uint8_t busid, uint8_t event, void *arg); +typedef void (*usbd_event_handler_t)(uint8_t busid, uint8_t event); struct usbd_endpoint { uint8_t ep_addr; @@ -95,15 +96,7 @@ extern struct usbd_bus g_usbdev_bus[]; #error USBD_IRQHandler is obsolete, please call USBD_IRQHandler(xxx) in your irq #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc); -#else -void usbd_desc_register(uint8_t busid, const uint8_t *desc); -void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc); -void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc); -void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc); -void usbd_webusb_desc_register(uint8_t busid, struct usb_webusb_descriptor *desc); -#endif void usbd_add_interface(uint8_t busid, struct usbd_interface *intf); void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep); @@ -115,7 +108,7 @@ bool usb_device_is_suspend(uint8_t busid); int usbd_send_remote_wakeup(uint8_t busid); uint8_t usbd_get_ep0_next_state(uint8_t busid); -int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)); +int usbd_initialize(uint8_t busid, uintptr_t reg_base, usbd_event_handler_t event_handler); int usbd_deinitialize(uint8_t busid); #ifdef __cplusplus diff --git a/components/drivers/usb/cherryusb/core/usbh_core.c b/components/drivers/usb/cherryusb/core/usbh_core.c index dc292e1375..43bba3e888 100644 --- a/components/drivers/usb/cherryusb/core/usbh_core.c +++ b/components/drivers/usb/cherryusb/core/usbh_core.c @@ -31,31 +31,38 @@ struct usbh_bus g_usbhost_bus[CONFIG_USBHOST_MAX_BUS]; #define USB_DEV_ADDR_MARK_OFFSET 5 #define USB_DEV_ADDR_MARK_MASK 0x1f +static void dummy_event_handler(uint8_t busid, uint8_t hub_index, uint8_t hub_port, uint8_t intf, uint8_t event) +{ + (void)busid; + (void)hub_index; + (void)hub_port; + (void)intf; + (void)event; +} + static int usbh_allocate_devaddr(struct usbh_devaddr_map *devgen) { - uint8_t startaddr = devgen->next; - uint8_t devaddr; + uint8_t lastaddr = devgen->last; + uint8_t devaddr = lastaddr; int index; int bitno; for (;;) { - devaddr = devgen->next; - if (devgen->next >= 0x7f) { - devgen->next = 2; - } else { - devgen->next++; + devaddr++; + if (devaddr > 0x7f) { + devaddr = 2; + } + if (devaddr == lastaddr) { + return -USB_ERR_NOMEM; } index = devaddr >> 5; bitno = devaddr & 0x1f; - if ((devgen->alloctab[index] & (1 << bitno)) == 0) { - devgen->alloctab[index] |= (1 << bitno); + if ((devgen->alloctab[index] & (1ul << bitno)) == 0) { + devgen->alloctab[index] |= (1ul << bitno); + devgen->last = devaddr; return (int)devaddr; } - - if (startaddr == devaddr) { - return -USB_ERR_NOMEM; - } } } @@ -69,15 +76,11 @@ static int __usbh_free_devaddr(struct usbh_devaddr_map *devgen, uint8_t devaddr) bitno = devaddr & USB_DEV_ADDR_MARK_MASK; /* Free the address */ - if ((devgen->alloctab[index] |= (1 << bitno)) != 0) { - devgen->alloctab[index] &= ~(1 << bitno); + if ((devgen->alloctab[index] & (1ul << bitno)) != 0) { + devgen->alloctab[index] &= ~(1ul << bitno); } else { return -1; } - - if (devaddr < devgen->next) { - devgen->next = devaddr; - } } return 0; @@ -91,7 +94,7 @@ static int usbh_free_devaddr(struct usbh_hubport *hport) return 0; } -static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uint8_t subclass, uint8_t protocol, +static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uint8_t subclass, uint8_t protocol, uint8_t intf, uint16_t vid, uint16_t pid) { struct usbh_class_info *index = NULL; @@ -106,6 +109,9 @@ static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uin if ((index->match_flags & USB_CLASS_MATCH_INTF_PROTOCOL) && !(index->bInterfaceProtocol == protocol)) { continue; } + if ((index->match_flags & USB_CLASS_MATCH_INTF_NUM) && !(index->bInterfaceNumber == intf)) { + continue; + } if (index->match_flags & USB_CLASS_MATCH_VID_PID && index->id_table) { /* scan id table */ uint32_t i; @@ -275,60 +281,6 @@ static int parse_config_descriptor(struct usbh_hubport *hport, struct usb_config return 0; } -static void usbh_print_hubport_info(struct usbh_hubport *hport) -{ - USB_LOG_RAW("Device Descriptor:\r\n"); - USB_LOG_RAW("bLength: 0x%02x \r\n", hport->device_desc.bLength); - USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->device_desc.bDescriptorType); - USB_LOG_RAW("bcdUSB: 0x%04x \r\n", hport->device_desc.bcdUSB); - USB_LOG_RAW("bDeviceClass: 0x%02x \r\n", hport->device_desc.bDeviceClass); - USB_LOG_RAW("bDeviceSubClass: 0x%02x \r\n", hport->device_desc.bDeviceSubClass); - USB_LOG_RAW("bDeviceProtocol: 0x%02x \r\n", hport->device_desc.bDeviceProtocol); - USB_LOG_RAW("bMaxPacketSize0: 0x%02x \r\n", hport->device_desc.bMaxPacketSize0); - USB_LOG_RAW("idVendor: 0x%04x \r\n", hport->device_desc.idVendor); - USB_LOG_RAW("idProduct: 0x%04x \r\n", hport->device_desc.idProduct); - USB_LOG_RAW("bcdDevice: 0x%04x \r\n", hport->device_desc.bcdDevice); - USB_LOG_RAW("iManufacturer: 0x%02x \r\n", hport->device_desc.iManufacturer); - USB_LOG_RAW("iProduct: 0x%02x \r\n", hport->device_desc.iProduct); - USB_LOG_RAW("iSerialNumber: 0x%02x \r\n", hport->device_desc.iSerialNumber); - USB_LOG_RAW("bNumConfigurations: 0x%02x\r\n", hport->device_desc.bNumConfigurations); - - USB_LOG_RAW("Config Descriptor:\r\n"); - USB_LOG_RAW("bLength: 0x%02x \r\n", hport->config.config_desc.bLength); - USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->config.config_desc.bDescriptorType); - USB_LOG_RAW("wTotalLength: 0x%04x \r\n", hport->config.config_desc.wTotalLength); - USB_LOG_RAW("bNumInterfaces: 0x%02x \r\n", hport->config.config_desc.bNumInterfaces); - USB_LOG_RAW("bConfigurationValue: 0x%02x \r\n", hport->config.config_desc.bConfigurationValue); - USB_LOG_RAW("iConfiguration: 0x%02x \r\n", hport->config.config_desc.iConfiguration); - USB_LOG_RAW("bmAttributes: 0x%02x \r\n", hport->config.config_desc.bmAttributes); - USB_LOG_RAW("bMaxPower: 0x%02x \r\n", hport->config.config_desc.bMaxPower); - - for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { - for (uint8_t j = 0; j < hport->config.intf[i].altsetting_num; j++) { - USB_LOG_RAW("\tInterface Descriptor:\r\n"); - USB_LOG_RAW("\tbLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bLength); - USB_LOG_RAW("\tbDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bDescriptorType); - USB_LOG_RAW("\tbInterfaceNumber: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceNumber); - USB_LOG_RAW("\tbAlternateSetting: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bAlternateSetting); - USB_LOG_RAW("\tbNumEndpoints: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints); - USB_LOG_RAW("\tbInterfaceClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceClass); - USB_LOG_RAW("\tbInterfaceSubClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceSubClass); - USB_LOG_RAW("\tbInterfaceProtocol: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceProtocol); - USB_LOG_RAW("\tiInterface: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.iInterface); - - for (uint8_t k = 0; k < hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints; k++) { - USB_LOG_RAW("\t\tEndpoint Descriptor:\r\n"); - USB_LOG_RAW("\t\tbLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bLength); - USB_LOG_RAW("\t\tbDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bDescriptorType); - USB_LOG_RAW("\t\tbEndpointAddress: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bEndpointAddress); - USB_LOG_RAW("\t\tbmAttributes: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bmAttributes); - USB_LOG_RAW("\t\twMaxPacketSize: 0x%04x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.wMaxPacketSize); - USB_LOG_RAW("\t\tbInterval: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bInterval); - } - } - } -} - static void usbh_print_setup(struct usb_setup_packet *setup) { (void)setup; @@ -466,7 +418,7 @@ int usbh_enumerate(struct usbh_hubport *hport) USB_LOG_INFO("The device has %d bNumConfigurations\r\n", ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->bNumConfigurations); - config_index = 0; + config_index = usbh_get_hport_active_config_index(hport); USB_LOG_DBG("The device selects config %d\r\n", config_index); /* Read the first 9 bytes of the config descriptor */ @@ -599,23 +551,35 @@ int usbh_enumerate(struct usbh_hubport *hport) } #endif USB_LOG_INFO("Enumeration success, start loading class driver\r\n"); + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_CONFIGURED); /*search supported class driver*/ for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { intf_desc = &hport->config.intf[i].altsetting[0].intf_desc; - struct usbh_class_driver *class_driver = (struct usbh_class_driver *)usbh_find_class_driver(intf_desc->bInterfaceClass, intf_desc->bInterfaceSubClass, intf_desc->bInterfaceProtocol, hport->device_desc.idVendor, hport->device_desc.idProduct); + USB_ASSERT_MSG(intf_desc->bInterfaceNumber == i, "Interface number mismatch, do not support non-standard device\r\n"); + + struct usbh_class_driver *class_driver = (struct usbh_class_driver *)usbh_find_class_driver(intf_desc->bInterfaceClass, + intf_desc->bInterfaceSubClass, + intf_desc->bInterfaceProtocol, + intf_desc->bInterfaceNumber, + hport->device_desc.idVendor, + hport->device_desc.idProduct); if (class_driver == NULL) { - USB_LOG_ERR("do not support Class:0x%02x,Subclass:0x%02x,Protocl:0x%02x\r\n", + USB_LOG_ERR("Do not support Class:0x%02x, Subclass:0x%02x, Protocl:0x%02x on interface %u\r\n", intf_desc->bInterfaceClass, intf_desc->bInterfaceSubClass, - intf_desc->bInterfaceProtocol); - + intf_desc->bInterfaceProtocol, + i); + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, i, USBH_EVENT_INTERFACE_UNSUPPORTED); continue; } hport->config.intf[i].class_driver = class_driver; - USB_LOG_INFO("Loading %s class driver\r\n", class_driver->driver_name); + USB_LOG_INFO("Loading %s class driver on interface %u\r\n", class_driver->driver_name, i); ret = CLASS_CONNECT(hport, i); + if (ret >= 0) { + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, i, USBH_EVENT_INTERFACE_START); + } } errout: @@ -630,17 +594,20 @@ void usbh_hubport_release(struct usbh_hubport *hport) { if (hport->connected) { hport->connected = false; + usbh_kill_urb(&hport->ep0_urb); usbh_free_devaddr(hport); for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { if (hport->config.intf[i].class_driver && hport->config.intf[i].class_driver->disconnect) { CLASS_DISCONNECT(hport, i); } + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, i, USBH_EVENT_INTERFACE_STOP); } hport->config.config_desc.bNumInterfaces = 0; - usbh_kill_urb(&hport->ep0_urb); if (hport->mutex) { usb_osal_mutex_delete(hport->mutex); } + USB_LOG_INFO("Device on Bus %u, Hub %u, Port %u disconnected\r\n", hport->bus->busid, hport->parent->index, hport->port); + hport->bus->event_handler(hport->bus->busid, hport->parent->index, hport->port, USB_INTERFACE_ANY, USBH_EVENT_DEVICE_DISCONNECTED); } } @@ -652,25 +619,27 @@ static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uintptr_t reg_bas bus->hcd.reg_base = reg_base; /* devaddr 1 is for roothub */ - bus->devgen.next = 2; + bus->devgen.last = 0x7f; usb_slist_add_tail(&g_bus_head, &bus->list); } -int usbh_initialize(uint8_t busid, uintptr_t reg_base) +int usbh_initialize(uint8_t busid, uintptr_t reg_base, usbh_event_handler_t event_handler) { struct usbh_bus *bus; - if (busid >= CONFIG_USBHOST_MAX_BUS) { - USB_LOG_ERR("bus overflow\r\n"); - while (1) { - } - } + USB_ASSERT_MSG(busid < CONFIG_USBHOST_MAX_BUS, "bus overflow\r\n"); bus = &g_usbhost_bus[busid]; usbh_bus_init(bus, busid, reg_base); + if (event_handler) { + bus->event_handler = event_handler; + } else { + bus->event_handler = dummy_event_handler; + } + #ifdef __ARMCC_VERSION /* ARM C Compiler */ extern const int usbh_class_info$$Base; extern const int usbh_class_info$$Limit; @@ -693,14 +662,12 @@ int usbh_deinitialize(uint8_t busid) { struct usbh_bus *bus; - if (busid >= CONFIG_USBHOST_MAX_BUS) { - USB_LOG_ERR("bus overflow\r\n"); - while (1) { - } - } + USB_ASSERT_MSG(busid < CONFIG_USBHOST_MAX_BUS, "bus overflow\r\n"); bus = &g_usbhost_bus[busid]; + bus->event_handler(bus->busid, USB_HUB_INDEX_ANY, USB_HUB_PORT_ANY, USB_INTERFACE_ANY, USBH_EVENT_DEINIT); + usbh_hub_deinitialize(bus); usb_slist_remove(&g_bus_head, &bus->list); @@ -711,6 +678,7 @@ int usbh_deinitialize(uint8_t busid) int usbh_control_transfer(struct usbh_hubport *hport, struct usb_setup_packet *setup, uint8_t *buffer) { struct usbh_urb *urb; + volatile uint8_t retry = 3; int ret; if (!hport || !setup) { @@ -723,12 +691,21 @@ int usbh_control_transfer(struct usbh_hubport *hport, struct usb_setup_packet *s usbh_print_setup(setup); +resubmit: usbh_control_urb_fill(urb, hport, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); ret = usbh_submit_urb(urb); if (ret == 0) { ret = urb->actual_length; } + if (ret < 0 && (ret != -USB_ERR_TIMEOUT)) { + retry--; + if (retry > 0) { + USB_LOG_WRN("Control transfer failed, errorcode %d, retrying...\r\n", ret); + goto resubmit; + } + } + usb_osal_mutex_give(hport->mutex); return ret; } @@ -816,73 +793,6 @@ static void *usbh_list_all_interface_name(struct usbh_hub *hub, const char *devn return NULL; } -static void usbh_list_all_interface_driver(struct usbh_hub *hub) -{ - struct usbh_hubport *hport; - struct usbh_hub *hub_next; - const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" }; - - for (uint8_t port = 0; port < hub->nports; port++) { - hport = &hub->child[port]; - if (hport->connected) { - for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { - if (hport->config.intf[itf].class_driver && hport->config.intf[itf].class_driver->driver_name) { - for (uint8_t j = 0; j < hub->index; j++) { - USB_LOG_RAW("\t"); - } - - USB_LOG_RAW("|__Port %u, dev addr:0x%02x, If %u, ClassDriver=%s, %s\r\n", - hport->port, - hport->dev_addr, - itf, - hport->config.intf[itf].class_driver->driver_name, - speed_table[hport->speed]); - - if (strcmp(hport->config.intf[itf].class_driver->driver_name, "hub") == 0) { - hub_next = hport->config.intf[itf].priv; - - if (hub_next && hub_next->connected) { - usbh_list_all_interface_driver(hub_next); - } - } - } - } - } - } -} - -static void usbh_list_all_interface_desc(struct usbh_bus *bus, struct usbh_hub *hub) -{ - struct usbh_hubport *hport; - struct usbh_hub *hub_next; - - for (uint8_t port = 0; port < hub->nports; port++) { - hport = &hub->child[port]; - if (hport->connected) { - USB_LOG_RAW("\r\nBus %u, Hub %u, Port %u, dev addr:0x%02x, VID:PID 0x%04x:0x%04x\r\n", - bus->busid, - hub->index, - hport->port, - hport->dev_addr, - hport->device_desc.idVendor, - hport->device_desc.idProduct); - usbh_print_hubport_info(hport); - - for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { - if (hport->config.intf[itf].class_driver && hport->config.intf[itf].class_driver->driver_name) { - if (strcmp(hport->config.intf[itf].class_driver->driver_name, "hub") == 0) { - hub_next = hport->config.intf[itf].priv; - - if (hub_next && hub_next->connected) { - usbh_list_all_interface_desc(bus, hub_next); - } - } - } - } - } - } -} - static struct usbh_hubport *usbh_list_all_hubport(struct usbh_hub *hub, uint8_t hub_index, uint8_t hub_port) { struct usbh_hubport *hport; @@ -960,64 +870,348 @@ struct usbh_hubport *usbh_find_hubport(uint8_t busid, uint8_t hub_index, uint8_t return hport; } +static void usbh_print_hubport_info(struct usbh_hubport *hport) +{ + USB_LOG_RAW("Device Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->device_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->device_desc.bDescriptorType); + USB_LOG_RAW(" bcdUSB: 0x%04x \r\n", hport->device_desc.bcdUSB); + USB_LOG_RAW(" bDeviceClass: 0x%02x \r\n", hport->device_desc.bDeviceClass); + USB_LOG_RAW(" bDeviceSubClass: 0x%02x \r\n", hport->device_desc.bDeviceSubClass); + USB_LOG_RAW(" bDeviceProtocol: 0x%02x \r\n", hport->device_desc.bDeviceProtocol); + USB_LOG_RAW(" bMaxPacketSize0: 0x%02x \r\n", hport->device_desc.bMaxPacketSize0); + USB_LOG_RAW(" idVendor: 0x%04x \r\n", hport->device_desc.idVendor); + USB_LOG_RAW(" idProduct: 0x%04x \r\n", hport->device_desc.idProduct); + USB_LOG_RAW(" bcdDevice: 0x%04x \r\n", hport->device_desc.bcdDevice); + USB_LOG_RAW(" iManufacturer: 0x%02x \r\n", hport->device_desc.iManufacturer); + USB_LOG_RAW(" iProduct: 0x%02x \r\n", hport->device_desc.iProduct); + USB_LOG_RAW(" iSerialNumber: 0x%02x \r\n", hport->device_desc.iSerialNumber); + USB_LOG_RAW(" bNumConfigurations: 0x%02x\r\n", hport->device_desc.bNumConfigurations); + + USB_LOG_RAW(" Config Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->config.config_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->config.config_desc.bDescriptorType); + USB_LOG_RAW(" wTotalLength: 0x%04x \r\n", hport->config.config_desc.wTotalLength); + USB_LOG_RAW(" bNumInterfaces: 0x%02x \r\n", hport->config.config_desc.bNumInterfaces); + USB_LOG_RAW(" bConfigurationValue: 0x%02x \r\n", hport->config.config_desc.bConfigurationValue); + USB_LOG_RAW(" iConfiguration: 0x%02x \r\n", hport->config.config_desc.iConfiguration); + USB_LOG_RAW(" bmAttributes: 0x%02x \r\n", hport->config.config_desc.bmAttributes); + USB_LOG_RAW(" bMaxPower: 0x%02x \r\n", hport->config.config_desc.bMaxPower); + + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + for (uint8_t j = 0; j < hport->config.intf[i].altsetting_num; j++) { + USB_LOG_RAW(" Interface Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bDescriptorType); + USB_LOG_RAW(" bInterfaceNumber: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceNumber); + USB_LOG_RAW(" bAlternateSetting: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bAlternateSetting); + USB_LOG_RAW(" bNumEndpoints: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints); + USB_LOG_RAW(" bInterfaceClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceClass); + USB_LOG_RAW(" bInterfaceSubClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceSubClass); + USB_LOG_RAW(" bInterfaceProtocol: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceProtocol); + USB_LOG_RAW(" iInterface: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.iInterface); + + for (uint8_t k = 0; k < hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints; k++) { + USB_LOG_RAW(" Endpoint Descriptor:\r\n"); + USB_LOG_RAW(" bLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bLength); + USB_LOG_RAW(" bDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bDescriptorType); + USB_LOG_RAW(" bEndpointAddress: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bEndpointAddress); + USB_LOG_RAW(" bmAttributes: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bmAttributes); + USB_LOG_RAW(" wMaxPacketSize: 0x%04x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.wMaxPacketSize); + USB_LOG_RAW(" bInterval: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bInterval); + } + } + } +} + +static void usbh_list_device(struct usbh_hub *hub, bool astree, bool verbose, int dev_addr, int vid, int pid) +{ + static const char *speed_table[] = { + "UNKNOWN", + "low-speed", + "full-speed", + "high-speed", + "wireless", + "super-speed", + "super-speed-plus", + }; + + static const char *root_speed_table[] = { + "UNKNOWN", + "1.1", + "1.1", + "2.0", + "2.5", + "3.0", + "3.0", + }; + + static const uint16_t speed_baud[] = { + 0, + 12, + 12, + 480, + 480, + 5000, + 10000, + }; + + struct usbh_bus *bus; + struct usbh_hubport *hport; + struct usbh_hub *hub_next; + + uint8_t imbuf[64]; + uint8_t ipbuf[64]; + + const char *pimstr; + const char *pipstr; + + bool imvalid = false; + bool ipvalid = false; + + int ret; + + bus = hub->bus; + + (void)speed_table; + + if (hub->is_roothub) { + if (astree) { + USB_LOG_RAW("/: Bus %02u.Port 1: Dev %u, Class=root_hub, Driver=hcd, %uM\r\n", + bus->busid, hub->hub_addr, speed_baud[hub->speed]); + + } else { + if ((dev_addr < 0) || (hub->hub_addr == dev_addr)) { + if (((vid < 0) || (vid == 0xffff)) && ((pid < 0) || (pid == 0xffff))) { + USB_LOG_RAW("Bus %03u Device %03u: ID %04x:%04x %s %s root hub\r\n", + bus->busid, hub->hub_addr, 0xffff, 0xffff, + "Cherry-Embedded", root_speed_table[hub->speed]); + } + } + } + } + + for (uint8_t port = 0; port < hub->nports; port++) { + hport = &hub->child[port]; + if (hport->connected) { + ret = 0; + if (hport->device_desc.iManufacturer) { + memset(imbuf, 0, sizeof(imbuf)); + ret = usbh_get_string_desc(hport, hport->device_desc.iManufacturer, imbuf, sizeof(imbuf)); + if (ret == 0) { + imvalid = true; + } + } + + if (hport->device_desc.iProduct) { + memset(ipbuf, 0, sizeof(ipbuf)); + ret = usbh_get_string_desc(hport, hport->device_desc.iProduct, ipbuf, sizeof(ipbuf)); + if (ret == 0) { + ipvalid = true; + } + } + + if (imvalid) { + pimstr = (const char *)imbuf; + } else { + pimstr = "Not specified Manufacturer"; + } + + if (ipvalid) { + pipstr = (const char *)ipbuf; + } else { + pipstr = "Not specified Product"; + } + + if (!astree) { + if ((dev_addr < 0) || (hport->dev_addr == dev_addr)) { + if (((vid < 0) || (vid == hport->device_desc.idVendor)) && ((pid < 0) || (pid == hport->device_desc.idProduct))) { + USB_LOG_RAW("Bus %03u Device %03u: ID %04x:%04x %s %s\r\n", + bus->busid, hport->dev_addr, hport->device_desc.idVendor, hport->device_desc.idProduct, + pimstr, pipstr); + + if (verbose) { + usbh_print_hubport_info(hport); + } + } + } + } + + for (uint8_t intf = 0; intf < hport->config.config_desc.bNumInterfaces; intf++) { + if (hport->config.intf[intf].class_driver && hport->config.intf[intf].class_driver->driver_name) { + if (astree) { + for (uint8_t j = 0; j < hub->index; j++) { + USB_LOG_RAW(" "); + } + + USB_LOG_RAW("|__ Port %u: Dev %u, If %u, ClassDriver=%s, %uM\r\n", + hport->port, hport->dev_addr, intf, hport->config.intf[intf].class_driver->driver_name, speed_baud[hport->speed]); + } + + if (!strcmp(hport->config.intf[intf].class_driver->driver_name, "hub")) { + hub_next = hport->config.intf[intf].priv; + + if (hub_next && hub_next->connected) { + usbh_list_device(hub_next, astree, verbose, dev_addr, vid, pid); + } + } + } else if (astree) { + for (uint8_t j = 0; j < hub->index; j++) { + USB_LOG_RAW(" "); + } + + USB_LOG_RAW("|__ Port %u: Dev %u, If 0 ClassDriver=none, %uM\r\n", + hport->port, hport->dev_addr, speed_baud[hport->speed]); + } + } + } + } +} + +void lsusb_help(void) +{ + USB_LOG_RAW("List USB Devices\r\n" + "Usage: lsusb [options]...\r\n" + "\r\n" + "-v, --verbose\r\n" + " - increase verbosity (show descriptors)\r\n" + "-s [[bus]:][dev_addr]\r\n" + " - show only devices with specified device and/or\r\n" + " bus numbers (in decimal)\r\n" + "-d vendor:[product]\r\n" + " - show only devices with the specified vendor and\r\n" + " product ID numbers (in hexadecimal)\r\n" + "-t, --tree\r\n" + " - dump the physical USB device hierarchy as a tree\r\n" + "-V, --version\r\n" + " - show version of the cherryusb\r\n" + "-h, --help\r\n" + " - show usage and help information\r\n"); +} + int lsusb(int argc, char **argv) { usb_slist_t *bus_list; - struct usbh_hub *hub; struct usbh_bus *bus; - size_t flags; + + int busid = -1; + int dev_addr = -1; + int vid = -1; + int pid = -1; + bool astree = false; + bool verbose = false; if (argc < 2) { - USB_LOG_RAW("Usage: lsusb [options]...\r\n"); - USB_LOG_RAW("List USB devices\r\n"); - USB_LOG_RAW(" -v, --verbose\r\n"); - USB_LOG_RAW(" Increase verbosity (show descriptors)\r\n"); - // USB_LOG_RAW(" -s [[bus]:[devnum]]\r\n"); - // USB_LOG_RAW(" Show only devices with specified device and/or bus numbers (in decimal)\r\n"); - // USB_LOG_RAW(" -d vendor:[product]\r\n"); - // USB_LOG_RAW(" Show only devices with the specified vendor and product ID numbers (in hexadecimal)\r\n"); - USB_LOG_RAW(" -t, --tree\r\n"); - USB_LOG_RAW(" Dump the physical USB device hierachy as a tree\r\n"); - USB_LOG_RAW(" -V, --version\r\n"); - USB_LOG_RAW(" Show version of program\r\n"); - USB_LOG_RAW(" -h, --help\r\n"); - USB_LOG_RAW(" Show usage and help\r\n"); - return 0; - } - if (argc > 3) { + lsusb_help(); return 0; } - flags = usb_osal_enter_critical_section(); + while (argc > 1) { + argc--; + argv++; - if (strcmp(argv[1], "-V") == 0) { - USB_LOG_RAW("CherryUSB Version %s\r\n", CHERRYUSB_VERSION_STR); - } + if (!strcmp(*argv, "-V") || !strcmp(*argv, "--version")) { + USB_LOG_RAW("CherryUSB version %s\r\n", CHERRYUSB_VERSION_STR); + return 0; + } else if (!strcmp(*argv, "-h") || !strcmp(*argv, "--help")) { + lsusb_help(); + return 0; + } else if (!strcmp(*argv, "-v") || !strcmp(*argv, "--verbose")) { + verbose = true; + } else if (!strcmp(*argv, "-t") || !strcmp(*argv, "--tree")) { + astree = true; + } else if (!strcmp(*argv, "-s")) { + if (argc > 1) { + argc--; + argv++; + + if (*argv[0] == '-') { + continue; + } - if (strcmp(argv[1], "-t") == 0) { - usb_slist_for_each(bus_list, &g_bus_head) - { - bus = usb_slist_entry(bus_list, struct usbh_bus, list); - hub = &bus->hcd.roothub; + char *endptr; + const char *colon = strchr(*argv, ':'); + (void)endptr; - USB_LOG_RAW("/: Bus %u, Hub %u, ports=%u, is roothub\r\n", - bus->busid, - hub->index, - hub->nports); - usbh_list_all_interface_driver(hub); + if (colon != NULL) { + const char *str; + if (colon > *argv) { + busid = strtol(*argv, &endptr, 10); + } + str = colon + 1; + if (*str != '\0') { + dev_addr = strtol(str, &endptr, 10); + if (dev_addr <= 0 || dev_addr >= 128) { + dev_addr = -1; + } + } + } else { + dev_addr = strtol(*argv, &endptr, 10); + if (dev_addr <= 0 || dev_addr >= 128) { + dev_addr = -1; + } + } + } + } else if (!strcmp(*argv, "-d")) { + if (argc > 1) { + argc--; + argv++; + + if (*argv[0] == '-') { + continue; + } + + char *endptr; + const char *colon = strchr(*argv, ':'); + (void)endptr; + + if (colon == NULL) { + continue; + } + const char *str; + + vid = strtol(*argv, &endptr, 16); + if (vid < 0 || vid > 0xffff) { + vid = -1; + continue; + } + str = colon + 1; + if (*str != '\0') { + pid = strtol(str, &endptr, 16); + if (pid < 0 || pid > 0xffff) { + pid = -1; + } + } + } } } - if (strcmp(argv[1], "-v") == 0) { - usb_slist_for_each(bus_list, &g_bus_head) - { - bus = usb_slist_entry(bus_list, struct usbh_bus, list); - hub = &bus->hcd.roothub; + if (astree) { + busid = -1; + dev_addr = -1; + vid = -1; + pid = -1; + verbose = false; + } - usbh_list_all_interface_desc(bus, hub); + usb_slist_for_each(bus_list, &g_bus_head) + { + bus = usb_slist_entry(bus_list, struct usbh_bus, list); + if (busid >= 0) { + if (bus->busid != busid) { + continue; + } } + + usbh_list_device(&bus->hcd.roothub, astree, verbose, dev_addr, vid, pid); } - usb_osal_leave_critical_section(flags); return 0; } + +__WEAK uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport) +{ + ARG_UNUSED(hport); + + return 0; // Default to configuration index 0 +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/core/usbh_core.h b/components/drivers/usb/cherryusb/core/usbh_core.h index 060c402ef6..903ce14fdb 100644 --- a/components/drivers/usb/cherryusb/core/usbh_core.h +++ b/components/drivers/usb/cherryusb/core/usbh_core.h @@ -28,11 +28,41 @@ extern "C" { #endif +enum usbh_event_type { + /* USB HCD IRQ */ + USBH_EVENT_ERROR, + USBH_EVENT_SOF, + + /* USB DEVICE STATUS */ + USBH_EVENT_DEVICE_RESET, + USBH_EVENT_DEVICE_CONNECTED, + USBH_EVENT_DEVICE_DISCONNECTED, + USBH_EVENT_DEVICE_CONFIGURED, + USBH_EVENT_DEVICE_WAKEUP, + USBH_EVENT_DEVICE_SUSPEND, + USBH_EVENT_DEVICE_RESUME, + + /* USB DEVICE INTERFACE STATUS */ + USBH_EVENT_INTERFACE_UNSUPPORTED, + USBH_EVENT_INTERFACE_START, + USBH_EVENT_INTERFACE_STOP, + + /* USB FRAMEWORK STATUS */ + USBH_EVENT_INIT, + USBH_EVENT_DEINIT, + USBH_EVENT_UNKNOWN, +}; + +#define USB_HUB_PORT_ANY 0 +#define USB_HUB_INDEX_ANY 0 +#define USB_INTERFACE_ANY 0xff + #define USB_CLASS_MATCH_VENDOR 0x0001 #define USB_CLASS_MATCH_PRODUCT 0x0002 #define USB_CLASS_MATCH_INTF_CLASS 0x0004 #define USB_CLASS_MATCH_INTF_SUBCLASS 0x0008 #define USB_CLASS_MATCH_INTF_PROTOCOL 0x0010 +#define USB_CLASS_MATCH_INTF_NUM 0x0020 #define USB_CLASS_MATCH_VID_PID (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT) #define CLASS_CONNECT(hport, i) ((hport)->config.intf[i].class_driver->connect(hport, i)) @@ -60,11 +90,14 @@ extern "C" { USB_GET_MULT(ep_desc->wMaxPacketSize)); \ } while (0) +typedef void (*usbh_event_handler_t)(uint8_t busid, uint8_t hub_index, uint8_t hub_port, uint8_t intf, uint8_t event); + struct usbh_class_info { uint8_t match_flags; /* Used for product specific matches; range is inclusive */ uint8_t bInterfaceClass; /* Base device class code */ uint8_t bInterfaceSubClass; /* Sub-class, depends on base class. Eg. */ uint8_t bInterfaceProtocol; /* Protocol, depends on base class. Eg. */ + uint8_t bInterfaceNumber; /* Interface number */ const uint16_t (*id_table)[2]; /* List of Vendor/Product ID pairs */ const struct usbh_class_driver *class_driver; }; @@ -131,7 +164,7 @@ struct usbh_hub { uint8_t powerdelay; uint8_t tt_think; bool ismtt; - struct usb_hub_descriptor hub_desc; /* USB 2.0 only */ + struct usb_hub_descriptor hub_desc; /* USB 2.0 only */ struct usb_hub_ss_descriptor hub_ss_desc; /* USB 3.0 only */ struct usbh_hubport child[CONFIG_USBHOST_MAX_EHPORTS]; struct usbh_hubport *parent; @@ -150,7 +183,7 @@ struct usbh_devaddr_map { * alloctab[3]:addr from 96~127 * */ - uint8_t next; /* Next device address */ + uint8_t last; /* Last device address */ uint32_t alloctab[4]; /* Bit allocation table */ }; @@ -168,6 +201,8 @@ struct usbh_bus { struct usbh_devaddr_map devgen; usb_osal_thread_t hub_thread; usb_osal_mq_t hub_mq; + usb_osal_mutex_t mutex; + usbh_event_handler_t event_handler; }; static inline void usbh_control_urb_fill(struct usbh_urb *urb, @@ -274,10 +309,11 @@ int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *out */ int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting); -int usbh_initialize(uint8_t busid, uintptr_t reg_base); +int usbh_initialize(uint8_t busid, uintptr_t reg_base, usbh_event_handler_t event_handler); int usbh_deinitialize(uint8_t busid); void *usbh_find_class_instance(const char *devname); struct usbh_hubport *usbh_find_hubport(uint8_t busid, uint8_t hub_index, uint8_t hub_port); +uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport); int lsusb(int argc, char **argv); diff --git a/components/drivers/usb/cherryusb/core/usbotg_core.c b/components/drivers/usb/cherryusb/core/usbotg_core.c new file mode 100644 index 0000000000..99b0cc8a6b --- /dev/null +++ b/components/drivers/usb/cherryusb/core/usbotg_core.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbotg_core.h" + +#ifdef CONFIG_USB_OTG_ENABLE +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbotg_core" +#include "usb_log.h" + +#define CONFIG_USB_OTG_MAX_BUS CONFIG_USBHOST_MAX_BUS + +struct usbotg_core_priv { + uint8_t busid; + uint32_t reg_base; + bool usbh_initialized; + bool usbd_initialized; + usbd_event_handler_t device_event_callback; + usbh_event_handler_t host_event_callback; + uint8_t request_mode; + usb_osal_sem_t change_sem; + usb_osal_thread_t change_thread; +} g_usbotg_core[CONFIG_USB_OTG_MAX_BUS]; + +static void usbotg_host_initialize(uint8_t busid) +{ + if (g_usbotg_core[busid].usbh_initialized) { + return; + } + + if (g_usbotg_core[busid].usbd_initialized) { + usbd_deinitialize(busid); + g_usbotg_core[busid].usbd_initialized = false; + } + + USB_LOG_INFO("Switch to HOST mode\r\n"); + + g_usbotg_core[busid].usbh_initialized = true; + usbh_initialize(busid, g_usbotg_core[busid].reg_base); +} + +static void usbotg_device_initialize(uint8_t busid) +{ + if (g_usbotg_core[busid].usbd_initialized) { + return; + } + + if (g_usbotg_core[busid].usbh_initialized) { + usbh_deinitialize(busid); + g_usbotg_core[busid].usbh_initialized = false; + } + + USB_LOG_INFO("Switch to DEVICE mode\r\n"); + + g_usbotg_core[busid].usbd_initialized = true; + usbd_initialize(g_usbotg_core[busid].busid, g_usbotg_core[busid].reg_base, g_usbotg_core[busid].device_event_callback); +} + +static void usbotg_rolechange_thread(void *argument) +{ + uint8_t busid = (uint8_t)(uintptr_t)argument; + + usb_otg_init(busid); + + while (1) { + if (usb_osal_sem_take(g_usbotg_core[busid].change_sem, USB_OSAL_WAITING_FOREVER) == 0) { + if (g_usbotg_core[busid].request_mode == USBOTG_MODE_HOST) { + usbotg_host_initialize(busid); + } else if (g_usbotg_core[busid].request_mode == USBOTG_MODE_DEVICE) { + usbotg_device_initialize(busid); + } + } + } +} + +int usbotg_initialize(uint8_t busid, uint32_t reg_base, usbd_event_handler_t device_event_callback, usbh_event_handler_t host_event_callback, uint8_t default_role) +{ + char thread_name[32] = { 0 }; + + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + g_usbotg_core[busid].busid = busid; + g_usbotg_core[busid].reg_base = reg_base; + g_usbotg_core[busid].device_event_callback = device_event_callback; + g_usbotg_core[busid].host_event_callback = host_event_callback; + + g_usbotg_core[busid].change_sem = usb_osal_sem_create(0); + if (g_usbotg_core[busid].change_sem == NULL) { + USB_LOG_ERR("Failed to create change_sem\r\n"); + while (1) { + } + } + + snprintf(thread_name, 32, "usbotg%u", busid); + g_usbotg_core[busid].change_thread = usb_osal_thread_create(thread_name, 2048, 10, usbotg_rolechange_thread, (void *)(uintptr_t)busid); + if (g_usbotg_core[busid].change_thread == NULL) { + USB_LOG_ERR("Failed to create usbotg thread\r\n"); + while (1) { + } + } + + usbotg_trigger_role_change(busid, default_role); + return 0; +} + +int usbotg_deinitialize(uint8_t busid) +{ + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + if (g_usbotg_core[busid].usbd_initialized) { + usbd_deinitialize(busid); + g_usbotg_core[busid].usbd_initialized = false; + } + + if (g_usbotg_core[busid].usbh_initialized) { + usbh_deinitialize(busid); + g_usbotg_core[busid].usbh_initialized = false; + } + + if (g_usbotg_core[busid].change_thread) { + usb_osal_thread_delete(g_usbotg_core[busid].change_thread); + } + + if (g_usbotg_core[busid].change_sem) { + usb_otg_deinit(busid); + usb_osal_sem_delete(g_usbotg_core[busid].change_sem); + } + + return 0; +} + +void usbotg_trigger_role_change(uint8_t busid, uint8_t mode) +{ + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + g_usbotg_core[busid].request_mode = mode; + + if (g_usbotg_core[busid].change_sem) { + usb_osal_sem_give(g_usbotg_core[busid].change_sem); + } +} + +void USBOTG_IRQHandler(uint8_t busid) +{ + USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n"); + + if (g_usbotg_core[busid].usbh_initialized) { + USBH_IRQHandler(busid); + } else if (g_usbotg_core[busid].usbd_initialized) { + USBD_IRQHandler(busid); + } +} +#endif /* CONFIG_USB_OTG_ENABLE */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/core/usbotg_core.h b/components/drivers/usb/cherryusb/core/usbotg_core.h new file mode 100644 index 0000000000..7eadb878ca --- /dev/null +++ b/components/drivers/usb/cherryusb/core/usbotg_core.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBOTG_CORE_H +#define USBOTG_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_otg.h" + +int usbotg_initialize(uint8_t busid, uint32_t reg_base, usbd_event_handler_t device_event_callback, usbh_event_handler_t host_event_callback, uint8_t default_role); +int usbotg_deinitialize(uint8_t busid); + +/* called by user */ +void usbotg_trigger_role_change(uint8_t busid, uint8_t mode); + +#ifdef __cplusplus +} +#endif + +#endif /* USBOTG_CORE_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c b/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c index 24f6d7acb5..9f77e73d04 100644 --- a/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c +++ b/components/drivers/usb/cherryusb/demo/adb/usbd_adb_template.c @@ -108,7 +108,6 @@ struct usb_msosv1_descriptor msosv1_desc = { .comp_id_property = WINUSB_IFx_WCIDProperties, }; -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -171,80 +170,6 @@ const struct usb_descriptor adb_descriptor = { .string_descriptor_callback = string_descriptor_callback, .msosv1_descriptor = &msosv1_desc }; -#else -/*!< global descriptor */ -static const uint8_t adb_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - ADB_DESCRIPTOR_INIT(ADB_INTF_NUM, WINUSB_IN_EP, WINUSB_OUT_EP, WINUSB_MAX_MPS), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'A', 0x00, /* wcChar6 */ - 'D', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x1C, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'A', 0x00, /* wcChar6 */ - 'D', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - '2', 0x00, /* wcChar9 */ - '0', 0x00, /* wcChar10 */ - '2', 0x00, /* wcChar11 */ - '4', 0x00, /* wcChar12 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static void usbd_event_handler(uint8_t busid, uint8_t event) { @@ -288,20 +213,15 @@ void cherryadb_init(uint8_t busid, uint32_t reg_base) /* shell_init() must be called in-task */ if (0 != shell_init(false)) { /* shell failed to be initialized */ - printf("Failed to initialize shell\r\n"); + USB_LOG_RAW("Failed to initialize shell\r\n"); for (;;) { ; } } #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC + usbd_desc_register(busid, &adb_descriptor); -#else - usbd_desc_register(busid, adb_descriptor); -#endif -#ifndef CONFIG_USBDEV_ADVANCE_DESC - usbd_msosv1_desc_register(busid, &msosv1_desc); -#endif + usbd_add_interface(busid, usbd_adb_init_intf(busid, &intf0, WINUSB_IN_EP, WINUSB_OUT_EP)); usbd_initialize(busid, reg_base, usbd_event_handler); -} +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c index 94ca950c96..aad917abbf 100644 --- a/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c +++ b/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c @@ -21,14 +21,15 @@ #define AUDIO_IN_FU_ID 0x02 -/* AUDIO Class Config */ -#define AUDIO_FREQ 16000U +#define AUDIO_MIC_FREQ 16000U +#define AUDIO_MIC_FRAME_SIZE_BYTE 2u +#define AUDIO_MIC_RESOLUTION_BIT 16u -#define IN_CHANNEL_NUM 1 +#define IN_CHANNEL_NUM 2 #if IN_CHANNEL_NUM == 1 #define INPUT_CTRL 0x03, 0x03 -#define INPUT_CH_ENABLE 0x0000 +#define INPUT_CH_ENABLE 0x0001 #elif IN_CHANNEL_NUM == 2 #define INPUT_CTRL 0x03, 0x03, 0x03 #define INPUT_CH_ENABLE 0x0003 @@ -54,32 +55,31 @@ /* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 1) */ /* 16bit(2 Bytes) 单声道(Mono:1) */ -#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_FREQ * 2 * IN_CHANNEL_NUM) / 1000)) +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_MIC_FREQ * 2 * IN_CHANNEL_NUM) / 1000)) -#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \ - AUDIO_AC_DESCRIPTOR_INIT_LEN(1) + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ - AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_AS_DESCRIPTOR_INIT_LEN(1)) +#define USB_CONFIG_SIZE (unsigned long)(9 + \ + AUDIO_AC_DESCRIPTOR_LEN(1) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_AS_DESCRIPTOR_LEN(1)) #define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(1) + \ AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC) -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, 0x00, 0x01), AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, IN_CHANNEL_NUM, INPUT_CH_ENABLE), AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_IN_FU_ID, 0x01, 0x01, INPUT_CTRL), AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, AUDIO_IN_FU_ID), - AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, 2, 16, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_FREQ)) + AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)) }; static const uint8_t device_quality_descriptor[] = { @@ -134,89 +134,6 @@ const struct usb_descriptor audio_v1_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t audio_v1_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, 0x00, 0x01), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, IN_CHANNEL_NUM, INPUT_CH_ENABLE), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_IN_FU_ID, 0x01, 0x01, INPUT_CTRL), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, AUDIO_IN_FU_ID), - AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, 2, 16, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_FREQ)), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'A', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '0' + IN_CHANNEL_NUM, 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif volatile bool tx_flag = 0; volatile bool ep_tx_busy_flag = false; @@ -301,13 +218,12 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_IN_EP }, }; +// In windows, audio driver cannot remove auto, so when you modify any descriptor information, please modify string descriptors too. + void audio_v1_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &audio_v1_descriptor); -#else - usbd_desc_register(busid, audio_v1_descriptor); -#endif + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0100, audio_entity_table, 1)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0100, audio_entity_table, 1)); usbd_add_endpoint(busid, &audio_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c index c764ee9323..872a6cde70 100644 --- a/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c +++ b/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c @@ -21,13 +21,69 @@ #define FEEDBACK_ENDP_PACKET_SIZE 0x03 #endif -#define AUDIO_IN_EP 0x81 -#define AUDIO_OUT_EP 0x02 +#define AUDIO_IN_EP 0x81 +#define AUDIO_OUT_EP 0x02 #define AUDIO_OUT_FEEDBACK_EP 0x83 #define AUDIO_IN_FU_ID 0x02 #define AUDIO_OUT_FU_ID 0x05 +#define IN_CHANNEL_NUM 2 + +#if IN_CHANNEL_NUM == 1 +#define INPUT_CTRL 0x03, 0x03 +#define INPUT_CH_ENABLE 0x0001 +#elif IN_CHANNEL_NUM == 2 +#define INPUT_CTRL 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x0003 +#elif IN_CHANNEL_NUM == 3 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x0007 +#elif IN_CHANNEL_NUM == 4 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x000f +#elif IN_CHANNEL_NUM == 5 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x001f +#elif IN_CHANNEL_NUM == 6 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x003F +#elif IN_CHANNEL_NUM == 7 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x007f +#elif IN_CHANNEL_NUM == 8 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x00ff +#endif + +#define OUT_CHANNEL_NUM 2 + +#if OUT_CHANNEL_NUM == 1 +#define OUTPUT_CTRL 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x0001 +#elif OUT_CHANNEL_NUM == 2 +#define OUTPUT_CTRL 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x0003 +#elif OUT_CHANNEL_NUM == 3 +#define OUTPUT_CTRL 0x03, 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x0007 +#elif OUT_CHANNEL_NUM == 4 +#define OUTPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x000f +#elif OUT_CHANNEL_NUM == 5 +#define OUTPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x001f +#elif OUT_CHANNEL_NUM == 6 +#define OUTPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x003F +#elif OUT_CHANNEL_NUM == 7 +#define OUTPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x007f +#elif OUT_CHANNEL_NUM == 8 +#define OUTPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define OUTPUT_CH_ENABLE 0x00ff +#endif + /* AUDIO Class Config */ #define AUDIO_SPEAKER_FREQ 16000U #define AUDIO_SPEAKER_FRAME_SIZE_BYTE 2u @@ -44,60 +100,59 @@ #define AUDIO_IN_PACKET ((uint32_t)((AUDIO_MIC_FREQ * AUDIO_MIC_FRAME_SIZE_BYTE * 2) / 1000)) #if USING_FEEDBACK == 0 -#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \ - AUDIO_AC_DESCRIPTOR_INIT_LEN(2) + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ - AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ - AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_AS_DESCRIPTOR_INIT_LEN(1) + \ - AUDIO_AS_DESCRIPTOR_INIT_LEN(1)) +#define USB_CONFIG_SIZE (unsigned long)(9 + \ + AUDIO_AC_DESCRIPTOR_LEN(2) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_AS_DESCRIPTOR_LEN(1) + \ + AUDIO_AS_DESCRIPTOR_LEN(1)) #else -#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \ - AUDIO_AC_DESCRIPTOR_INIT_LEN(2) + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ - AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ - AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_AS_DESCRIPTOR_INIT_LEN(1) + \ - AUDIO_AS_FEEDBACK_DESCRIPTOR_INIT_LEN(1)) +#define USB_CONFIG_SIZE (unsigned long)(9 + \ + AUDIO_AC_DESCRIPTOR_LEN(2) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_AS_DESCRIPTOR_LEN(1) + \ + AUDIO_AS_FEEDBACK_DESCRIPTOR_LEN(1)) #endif -#define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(2) + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ - AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ +#define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(2) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM, 1) + \ AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC) -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x03, AUDIO_AC_SIZ, 0x00, 0x01, 0x02), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, 0x02, 0x0003), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x02, 0x01, 0x01, 0x03, 0x00, 0x00), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, 0x02), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x02, 0x0003), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x05, 0x04, 0x01, 0x03, 0x00, 0x00), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_OUTTERM_SPEAKER, 0x05), + AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, IN_CHANNEL_NUM, INPUT_CH_ENABLE), + AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_IN_FU_ID, 0x01, 0x01, INPUT_CTRL), + AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, AUDIO_IN_FU_ID), + AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE), + AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_OUT_FU_ID, 0x04, 0x01, OUTPUT_CTRL), + AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_OUTTERM_SPEAKER, AUDIO_OUT_FU_ID), + AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, + EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)), #if USING_FEEDBACK == 0 - AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, + AUDIO_AS_DESCRIPTOR_INIT(0x02, 0x04, OUT_CHANNEL_NUM, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), #else - AUDIO_AS_FEEDBACK_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, AUDIO_OUT_PACKET, - EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), + AUDIO_AS_FEEDBACK_DESCRIPTOR_INIT(0x02, 0x04, OUT_CHANNEL_NUM, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, AUDIO_OUT_PACKET, + EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), #endif - AUDIO_AS_DESCRIPTOR_INIT(0x02, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, - EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)) }; static const uint8_t device_quality_descriptor[] = { @@ -152,104 +207,6 @@ const struct usb_descriptor audio_v1_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t audio_v1_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x03, AUDIO_AC_SIZ, 0x00, 0x01, 0x02), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, 0x02, 0x0003), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x02, 0x01, 0x01, 0x03, 0x00, 0x00), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, 0x02), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x02, 0x0003), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x05, 0x04, 0x01, 0x03, 0x00, 0x00), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_OUTTERM_SPEAKER, 0x05), -#if USING_FEEDBACK == 0 - AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, - EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), -#else - AUDIO_AS_FEEDBACK_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, AUDIO_OUT_PACKET, - EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), -#endif - AUDIO_AS_DESCRIPTOR_INIT(0x02, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, - EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'A', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ -#if USING_FEEDBACK == 0 - '1', 0x00, /* wcChar9 */ -#else - '2', 0x00, /* wcChar9 */ -#endif -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[AUDIO_OUT_PACKET]; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET]; @@ -297,11 +254,11 @@ void usbd_audio_open(uint8_t busid, uint8_t intf) AUDIO_FEEDBACK_TO_BUF_FS(s_speaker_feedback_buffer, feedback_value); /* uac1 can only use 10.14 */ usbd_ep_start_write(busid, AUDIO_OUT_FEEDBACK_EP, s_speaker_feedback_buffer, FEEDBACK_ENDP_PACKET_SIZE); #endif - printf("OPEN1\r\n"); + USB_LOG_INFO("OPEN1\r\n"); } else { tx_flag = 1; ep_tx_busy_flag = false; - printf("OPEN2\r\n"); + USB_LOG_INFO("OPEN2\r\n"); } } @@ -309,11 +266,11 @@ void usbd_audio_close(uint8_t busid, uint8_t intf) { if (intf == 1) { rx_flag = 0; - printf("CLOSE1\r\n"); + USB_LOG_INFO("CLOSE1\r\n"); } else { tx_flag = 0; ep_tx_busy_flag = false; - printf("CLOSE2\r\n"); + USB_LOG_INFO("CLOSE2\r\n"); } } @@ -393,13 +350,12 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_OUT_EP }, }; +// In windows, audio driver cannot remove auto, so when you modify any descriptor information, please modify string descriptors too. + void audio_v1_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &audio_v1_descriptor); -#else - usbd_desc_register(busid, audio_v1_descriptor); -#endif + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0100, audio_entity_table, 2)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0100, audio_entity_table, 2)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf2, 0x0100, audio_entity_table, 2)); diff --git a/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c index cd6e9b151a..c904455049 100644 --- a/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c +++ b/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c @@ -22,17 +22,17 @@ #define AUDIO_IN_CLOCK_ID 0x01 #define AUDIO_IN_FU_ID 0x03 -#define AUDIO_IN_MAX_FREQ 16000 -#define HALF_WORD_BYTES 2 //2 half word (one channel) -#define SAMPLE_BITS 16 //16 bit per channel +#define AUDIO_IN_MAX_FREQ 96000 +#define AUDIO_MIC_FRAME_SIZE_BYTE 2u +#define AUDIO_MIC_RESOLUTION_BIT 16u -#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME) +#define BMCONTROL (AUDIO_V2_CONTROL_MUTE | AUDIO_V2_CONTROL_VOLUME) #define IN_CHANNEL_NUM 2 #if IN_CHANNEL_NUM == 1 #define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) -#define INPUT_CH_ENABLE 0x00000000 +#define INPUT_CH_ENABLE 0x00000001 #elif IN_CHANNEL_NUM == 2 #define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) #define INPUT_CH_ENABLE 0x00000003 @@ -56,15 +56,15 @@ #define INPUT_CH_ENABLE 0x000000ff #endif -#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_IN_MAX_FREQ * HALF_WORD_BYTES * IN_CHANNEL_NUM) / 1000)) +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_IN_MAX_FREQ * AUDIO_MIC_FRAME_SIZE_BYTE * IN_CHANNEL_NUM) / 1000)) -#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ - AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) +#define USB_CONFIG_SIZE (9 + \ + AUDIO_V2_AC_DESCRIPTOR_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_DESCRIPTOR_LEN) #define AUDIO_AC_SIZ (AUDIO_V2_SIZEOF_AC_HEADER_DESC + \ AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ @@ -72,19 +72,18 @@ AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC) -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, AUDIO_CATEGORY_MICROPHONE, 0x00, 0x00), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x01, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_INTERM_MIC, 0x01, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, INPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x03, 0x01, 0x0000), - AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x04, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL) + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(AUDIO_IN_CLOCK_ID, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_INTERM_MIC, AUDIO_IN_CLOCK_ID, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_IN_FU_ID, 0x02, INPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, AUDIO_IN_FU_ID, AUDIO_IN_CLOCK_ID, 0x0000), + AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x04, IN_CHANNEL_NUM, INPUT_CH_ENABLE, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL) }; static const uint8_t device_quality_descriptor[] = { @@ -139,96 +138,24 @@ const struct usb_descriptor audio_v2_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t audio_v2_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, AUDIO_CATEGORY_MICROPHONE, 0x00, 0x00), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x01, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_INTERM_MIC, 0x01, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, INPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x03, 0x01, 0x0000), - AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x04, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'A', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '4', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static const uint8_t mic_default_sampling_freq_table[] = { - AUDIO_SAMPLE_FREQ_NUM(1), + AUDIO_SAMPLE_FREQ_NUM(5), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(0x00), AUDIO_SAMPLE_FREQ_4B(16000), AUDIO_SAMPLE_FREQ_4B(16000), - AUDIO_SAMPLE_FREQ_4B(0x00) + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(0x00), }; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET]; @@ -323,13 +250,12 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_IN_EP }, }; +// In windows, audio driver cannot remove auto, so when you modify any descriptor information, please modify string descriptors too. + void audio_v2_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &audio_v2_descriptor); -#else - usbd_desc_register(busid, audio_v2_descriptor); -#endif + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 2)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0200, audio_entity_table, 2)); usbd_add_endpoint(busid, &audio_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c index ce77c30268..38c1dbbe01 100644 --- a/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c +++ b/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c @@ -30,19 +30,21 @@ #define AUDIO_IN_CLOCK_ID 0x05 #define AUDIO_IN_FU_ID 0x07 -#define AUDIO_OUT_MAX_FREQ 96000 -#define AUDIO_IN_MAX_FREQ 16000 +#define AUDIO_OUT_MAX_FREQ 96000 +#define AUDIO_SPEAKER_FRAME_SIZE_BYTE 2u +#define AUDIO_SPEAKER_RESOLUTION_BIT 16u -#define HALF_WORD_BYTES 2 //2 half word (one channel) -#define SAMPLE_BITS 16 //16 bit per channel +#define AUDIO_IN_MAX_FREQ 96000 +#define AUDIO_MIC_FRAME_SIZE_BYTE 2u +#define AUDIO_MIC_RESOLUTION_BIT 16u -#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME) +#define BMCONTROL (AUDIO_V2_CONTROL_MUTE | AUDIO_V2_CONTROL_VOLUME) #define IN_CHANNEL_NUM 2 #if IN_CHANNEL_NUM == 1 #define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) -#define INPUT_CH_ENABLE 0x00000000 +#define INPUT_CH_ENABLE 0x00000001 #elif IN_CHANNEL_NUM == 2 #define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) #define INPUT_CH_ENABLE 0x00000003 @@ -70,7 +72,7 @@ #if OUT_CHANNEL_NUM == 1 #define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) -#define OUTPUT_CH_ENABLE 0x00000000 +#define OUTPUT_CH_ENABLE 0x00000001 #elif OUT_CHANNEL_NUM == 2 #define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) #define OUTPUT_CH_ENABLE 0x00000003 @@ -95,35 +97,35 @@ #endif /* AudioFreq * DataSize (2 bytes) * NumChannels */ -#define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_OUT_MAX_FREQ * HALF_WORD_BYTES * OUT_CHANNEL_NUM) / 1000)) -#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_IN_MAX_FREQ * HALF_WORD_BYTES * IN_CHANNEL_NUM) / 1000)) +#define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_OUT_MAX_FREQ * AUDIO_SPEAKER_FRAME_SIZE_BYTE * OUT_CHANNEL_NUM) / 1000)) +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_IN_MAX_FREQ * AUDIO_MIC_FRAME_SIZE_BYTE * IN_CHANNEL_NUM) / 1000)) #if USING_FEEDBACK == 0 -#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ - AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) +#define USB_CONFIG_SIZE (9 + \ + AUDIO_V2_AC_DESCRIPTOR_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_DESCRIPTOR_LEN + \ + AUDIO_V2_AS_DESCRIPTOR_LEN) #else -#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ - AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) +#define USB_CONFIG_SIZE (9 + \ + AUDIO_V2_AC_DESCRIPTOR_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_LEN + \ + AUDIO_V2_AS_DESCRIPTOR_LEN) #endif #define AUDIO_AC_SIZ (AUDIO_V2_SIZEOF_AC_HEADER_DESC + \ @@ -136,28 +138,27 @@ AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC) -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x03, AUDIO_AC_SIZ, AUDIO_CATEGORY_UNDEF, 0x00, 0x00), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x01, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, OUTPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x05, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_INTERM_MIC, 0x05, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x07, 0x06, INPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x08, AUDIO_TERMINAL_STREAMING, 0x07, 0x05, 0x0000), + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(AUDIO_OUT_CLOCK_ID, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, AUDIO_OUT_CLOCK_ID, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_OUT_FU_ID, 0x02, OUTPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, AUDIO_OUT_FU_ID, AUDIO_OUT_CLOCK_ID, 0x0000), + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(AUDIO_IN_CLOCK_ID, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_INTERM_MIC, AUDIO_IN_CLOCK_ID, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_IN_FU_ID, 0x06, INPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x08, AUDIO_TERMINAL_STREAMING, AUDIO_IN_FU_ID, AUDIO_IN_CLOCK_ID, 0x0000), #if USING_FEEDBACK == 0 - AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), + AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), #else - AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP), + AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP), #endif - AUDIO_V2_AS_DESCRIPTOR_INIT(0x02, 0x08, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL) + AUDIO_V2_AS_DESCRIPTOR_INIT(0x02, 0x08, IN_CHANNEL_NUM, INPUT_CH_ENABLE, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL) }; static const uint8_t device_quality_descriptor[] = { @@ -212,103 +213,6 @@ const struct usb_descriptor audio_v2_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -uint8_t audio_v2_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x03, AUDIO_AC_SIZ, AUDIO_CATEGORY_UNDEF, 0x00, 0x00), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x01, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, OUTPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x05, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_INTERM_MIC, 0x05, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x07, 0x06, INPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x08, AUDIO_TERMINAL_STREAMING, 0x07, 0x05, 0x0000), -#if USING_FEEDBACK == 0 - AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), -#else - AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP), -#endif - AUDIO_V2_AS_DESCRIPTOR_INIT(0x02, 0x08, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'A', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ -#if USING_FEEDBACK == 0 - '3', 0x00, /* wcChar9 */ -#else - '4', 0x00, /* wcChar9 */ -#endif -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static const uint8_t speaker_default_sampling_freq_table[] = { AUDIO_SAMPLE_FREQ_NUM(5), @@ -330,9 +234,21 @@ static const uint8_t speaker_default_sampling_freq_table[] = { }; static const uint8_t mic_default_sampling_freq_table[] = { - AUDIO_SAMPLE_FREQ_NUM(1), + AUDIO_SAMPLE_FREQ_NUM(5), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(0x00), AUDIO_SAMPLE_FREQ_4B(16000), AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(96000), AUDIO_SAMPLE_FREQ_4B(0x00) }; @@ -501,13 +417,12 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_IN_EP }, }; +// In windows, audio driver cannot remove auto, so when you modify any descriptor information, please modify string descriptors too. + void audio_v2_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &audio_v2_descriptor); -#else - usbd_desc_register(busid, audio_v2_descriptor); -#endif + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 4)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0200, audio_entity_table, 4)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf2, 0x0200, audio_entity_table, 4)); diff --git a/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c index e89c880810..5420619275 100644 --- a/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c +++ b/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c @@ -31,13 +31,13 @@ #define HALF_WORD_BYTES 2 //2 half word (one channel) #define SAMPLE_BITS 16 //16 bit per channel -#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME) +#define BMCONTROL (AUDIO_V2_CONTROL_MUTE | AUDIO_V2_CONTROL_VOLUME) #define OUT_CHANNEL_NUM 2 #if OUT_CHANNEL_NUM == 1 #define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) -#define OUTPUT_CH_ENABLE 0x00000000 +#define OUTPUT_CH_ENABLE 0x00000001 #elif OUT_CHANNEL_NUM == 2 #define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) #define OUTPUT_CH_ENABLE 0x00000003 @@ -64,21 +64,21 @@ #define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_OUT_MAX_FREQ * HALF_WORD_BYTES * OUT_CHANNEL_NUM) / 1000)) #if USING_FEEDBACK == 0 -#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ - AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) +#define USB_CONFIG_SIZE (9 + \ + AUDIO_V2_AC_DESCRIPTOR_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_DESCRIPTOR_LEN) #else -#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ - AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ - AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ - AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ - AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ - AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN) +#define USB_CONFIG_SIZE (9 + \ + AUDIO_V2_AC_DESCRIPTOR_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_LEN) #endif #define AUDIO_AC_SIZ (AUDIO_V2_SIZEOF_AC_HEADER_DESC + \ @@ -87,18 +87,17 @@ AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC) -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, AUDIO_CATEGORY_SPEAKER, 0x00, 0x00), AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(AUDIO_OUT_CLOCK_ID, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, AUDIO_OUT_CLOCK_ID, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_OUT_FU_ID, 0x02, OUTPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, AUDIO_OUT_FU_ID, AUDIO_OUT_CLOCK_ID, 0x0000), #if USING_FEEDBACK == 0 AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), #else @@ -158,98 +157,6 @@ const struct usb_descriptor audio_v2_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t audio_v2_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, AUDIO_CATEGORY_SPEAKER, 0x00, 0x00), - AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(AUDIO_OUT_CLOCK_ID, 0x03, 0x03), - AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), - AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_OUT_FU_ID, 0x02, OUTPUT_CTRL), - AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000), -#if USING_FEEDBACK == 0 - AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), -#else - AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, AUDIO_OUT_PACKET, EP_INTERVAL, AUDIO_OUT_FEEDBACK_EP), -#endif - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'A', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ -#if USING_FEEDBACK == 0 - '3', 0x00, /* wcChar9 */ -#else - '4', 0x00, /* wcChar9 */ -#endif -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static const uint8_t default_sampling_freq_table[] = { AUDIO_SAMPLE_FREQ_NUM(5), @@ -397,13 +304,12 @@ struct audio_entity_info audio_entity_table[] = { .ep = AUDIO_OUT_EP }, }; +// In windows, audio driver cannot remove auto, so when you modify any descriptor information, please modify string descriptors too. + void audio_v2_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &audio_v2_descriptor); -#else - usbd_desc_register(busid, audio_v2_descriptor); -#endif + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 2)); usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0200, audio_entity_table, 2)); usbd_add_endpoint(busid, &audio_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/bootuf2/msc_bootuf2_template.c b/components/drivers/usb/cherryusb/demo/bootuf2/msc_bootuf2_template.c index 158866057e..2584d3ae76 100644 --- a/components/drivers/usb/cherryusb/demo/bootuf2/msc_bootuf2_template.c +++ b/components/drivers/usb/cherryusb/demo/bootuf2/msc_bootuf2_template.c @@ -23,7 +23,6 @@ #define MSC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01) }; @@ -85,85 +84,6 @@ const struct usb_descriptor msc_bootuf2_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t msc_bootuf2_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - MSC_DESCRIPTOR_INIT(0x00, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'F', 0x00, /* wcChar11 */ - '2', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static void usbd_event_handler(uint8_t busid, uint8_t event) { @@ -215,11 +135,9 @@ static struct usbd_interface intf0; void msc_bootuf2_init(uint8_t busid, uintptr_t reg_base) { boot2uf2_flash_init(); -#ifdef CONFIG_USBDEV_ADVANCE_DESC + usbd_desc_register(busid, &msc_bootuf2_descriptor); -#else - usbd_desc_register(busid, msc_bootuf2_descriptor); -#endif + usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf0, MSC_OUT_EP, MSC_IN_EP)); usbd_initialize(busid, reg_base, usbd_event_handler); diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c index 0851cf89d2..016e9808e3 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c @@ -43,7 +43,6 @@ #define MSC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01) }; @@ -52,37 +51,7 @@ static const uint8_t config_descriptor[] = { USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x04, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), MSC_DESCRIPTOR_INIT(0x02, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x03, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + HID_MOUSE_DESCRIPTOR_INIT(0x03, 0x01, HID_MOUSE_REPORT_DESC_SIZE, HID_INT_EP, HID_INT_EP_SIZE, HID_INT_EP_INTERVAL), }; static const uint8_t device_quality_descriptor[] = { @@ -137,117 +106,6 @@ const struct usb_descriptor cdc_acm_hid_msc_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t cdc_acm_hid_msc_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x04, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - MSC_DESCRIPTOR_INIT(0x02, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x03, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - 'M', 0x00, /* wcChar11 */ - 'H', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif /*!< hid mouse report descriptor */ static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { @@ -399,11 +257,8 @@ struct usbd_interface intf3; void cdc_acm_hid_msc_descriptor_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_acm_hid_msc_descriptor); -#else - usbd_desc_register(busid, cdc_acm_hid_msc_descriptor); -#endif + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); usbd_add_endpoint(busid, &cdc_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_mavlink_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_mavlink_template.c index 0a8bc3b66c..c941b35074 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_acm_mavlink_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_mavlink_template.c @@ -27,7 +27,6 @@ #define CDC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -89,86 +88,6 @@ const struct usb_descriptor cdc_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif chry_ringbuffer_t usb_rx_rb; uint8_t usb_rx_buffer[2048]; @@ -243,11 +162,9 @@ static struct usbd_interface intf1; void cdc_acm_mavlink_init(uint8_t busid, uintptr_t reg_base) { chry_ringbuffer_init(&usb_rx_rb, usb_rx_buffer, sizeof(usb_rx_buffer)); -#ifdef CONFIG_USBDEV_ADVANCE_DESC + usbd_desc_register(busid, &cdc_descriptor); -#else - usbd_desc_register(busid, cdc_descriptor); -#endif + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); usbd_add_endpoint(busid, &cdc_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c index e889cbc8c8..4c805835ee 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c @@ -35,7 +35,6 @@ #define MSC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -98,87 +97,6 @@ const struct usb_descriptor cdc_msc_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_msc_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - MSC_DESCRIPTOR_INIT(0x02, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x00), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - '-', 0x00, /* wcChar11 */ - 'M', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; /* 2048 is only for test speed , please use CDC_MAX_MPS for common*/ USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; @@ -249,11 +167,8 @@ struct usbd_interface intf2; void cdc_acm_msc_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_msc_descriptor); -#else - usbd_desc_register(busid, cdc_msc_descriptor); -#endif + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); usbd_add_endpoint(busid, &cdc_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c index 80b40b0206..753e81729b 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c @@ -37,7 +37,6 @@ #define CDC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -102,89 +101,6 @@ const struct usb_descriptor cdc_multi_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_multi_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x08, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - CDC_ACM_DESCRIPTOR_INIT(0x02, CDC_INT_EP2, CDC_OUT_EP2, CDC_IN_EP2, CDC_MAX_MPS, 0x02), - CDC_ACM_DESCRIPTOR_INIT(0x04, CDC_INT_EP3, CDC_OUT_EP3, CDC_IN_EP3, CDC_MAX_MPS, 0x02), - CDC_ACM_DESCRIPTOR_INIT(0x06, CDC_INT_EP4, CDC_OUT_EP4, CDC_IN_EP4, CDC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[4][2048]; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[4][2048]; @@ -292,11 +208,8 @@ struct usbd_interface intf7; void cdc_acm_multi_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_multi_descriptor); -#else - usbd_desc_register(busid, cdc_multi_descriptor); -#endif + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); usbd_add_endpoint(busid, &cdc_out_ep1); diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_rttchardev_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_rttchardev_template.c index f5fec3f0ea..2fed1cfc50 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_acm_rttchardev_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_rttchardev_template.c @@ -25,7 +25,6 @@ #define CDC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -87,86 +86,6 @@ const struct usb_descriptor cdc_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static void usbd_event_handler(uint8_t busid, uint8_t event) { @@ -198,11 +117,32 @@ extern void usbd_cdc_acm_serial_init(uint8_t busid, uint8_t in_ep, uint8_t out_e void cdc_acm_chardev_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_descriptor); -#else - usbd_desc_register(busid, cdc_descriptor); -#endif + usbd_cdc_acm_serial_init(busid, CDC_IN_EP, CDC_OUT_EP); usbd_initialize(busid, reg_base, usbd_event_handler); -} \ No newline at end of file +} + +static int cdc_acm_enter(int argc, char **argv) +{ + (void)argc; + (void)argv; + + finsh_set_device("usb-acm0"); + rt_console_set_device("usb-acm0"); + + return 0; +} +MSH_CMD_EXPORT(cdc_acm_enter, cdc_acm_enter); + +static int cdc_acm_exit(int argc, char **argv) +{ + (void)argc; + (void)argv; + + finsh_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + return 0; +} +MSH_CMD_EXPORT(cdc_acm_exit, cdc_acm_exit); \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_template.c index 3ff8ae2ab6..e98287c94c 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_acm_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_template.c @@ -25,7 +25,6 @@ #define CDC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -87,86 +86,6 @@ const struct usb_descriptor cdc_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; /* 2048 is only for test speed , please use CDC_MAX_MPS for common*/ USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; @@ -245,11 +164,8 @@ void cdc_acm_init(uint8_t busid, uintptr_t reg_base) memcpy(&write_buffer[0], data, 10); memset(&write_buffer[10], 'a', 2038); -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_descriptor); -#else - usbd_desc_register(busid, cdc_descriptor); -#endif + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); usbd_add_endpoint(busid, &cdc_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c b/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c index b259e75319..528ed9f63e 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c @@ -29,22 +29,16 @@ #define CDC_MAX_MPS 64 #endif -#define CDC_ECM_ETH_STATISTICS_BITMAP 0x00000000 - /* str idx = 4 is for mac address: aa:bb:cc:dd:ee:ff*/ #define CDC_ECM_MAC_STRING_INDEX 4 -/* Ethernet Maximum Segment size, typically 1514 bytes */ -#define CONFIG_CDC_ECM_ETH_MAX_SEGSZE 1514U - -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; static const uint8_t config_descriptor[] = { USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ECM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, CDC_ECM_ETH_STATISTICS_BITMAP, CONFIG_CDC_ECM_ETH_MAX_SEGSZE, 0, 0, CDC_ECM_MAC_STRING_INDEX) + CDC_ECM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, CDC_ECM_MAC_STRING_INDEX) }; static const uint8_t device_quality_descriptor[] = { @@ -68,6 +62,7 @@ static const char *string_descriptors[] = { "CherryUSB", /* Manufacturer */ "CherryUSB CDC ECM DEMO", /* Product */ "2022123456", /* Serial Number */ + "aabbccddeeff", /* ecm mac address */ }; static const uint8_t *device_descriptor_callback(uint8_t speed) @@ -87,7 +82,7 @@ static const uint8_t *device_quality_descriptor_callback(uint8_t speed) static const char *string_descriptor_callback(uint8_t speed, uint8_t index) { - if (index > 3) { + if (index > 4) { return NULL; } return string_descriptors[index]; @@ -99,107 +94,6 @@ const struct usb_descriptor cdc_ecm_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_ecm_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_ECM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, CDC_ECM_ETH_STATISTICS_BITMAP, CONFIG_CDC_ECM_ETH_MAX_SEGSZE, 0, 0, CDC_ECM_MAC_STRING_INDEX), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x2E, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'C', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'E', 0x00, /* wcChar14 */ - 'C', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - ' ', 0x00, /* wcChar17 */ - 'D', 0x00, /* wcChar18 */ - 'E', 0x00, /* wcChar19 */ - 'M', 0x00, /* wcChar20 */ - 'O', 0x00, /* wcChar21 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ - /////////////////////////////////////// - /// string4 descriptor - /////////////////////////////////////// - 0x1A, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'a', 0x00, /* wcChar0 */ - 'a', 0x00, /* wcChar1 */ - 'b', 0x00, /* wcChar2 */ - 'b', 0x00, /* wcChar3 */ - 'c', 0x00, /* wcChar4 */ - 'c', 0x00, /* wcChar5 */ - 'd', 0x00, /* wcChar6 */ - 'd', 0x00, /* wcChar7 */ - 'e', 0x00, /* wcChar8 */ - 'e', 0x00, /* wcChar9 */ - 'f', 0x00, /* wcChar10 */ - 'f', 0x00, /* wcChar11 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif const uint8_t mac[6] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; @@ -463,12 +357,9 @@ void cdc_ecm_init(uint8_t busid, uintptr_t reg_base) { cdc_ecm_lwip_init(); -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_ecm_descriptor); -#else - usbd_desc_register(busid, cdc_ecm_descriptor); -#endif + usbd_add_interface(busid, usbd_cdc_ecm_init_intf(&intf0, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP)); usbd_add_interface(busid, usbd_cdc_ecm_init_intf(&intf1, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP)); usbd_initialize(busid, reg_base, usbd_event_handler); -} +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c b/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c index c7bda9316b..1b5874934d 100644 --- a/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c +++ b/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c @@ -29,7 +29,6 @@ #define CDC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -91,88 +90,6 @@ const struct usb_descriptor cdc_rndis_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t cdc_rndis_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - CDC_RNDIS_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x2A, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'R', 0x00, /* wcChar10 */ - 'N', 0x00, /* wcChar11 */ - 'D', 0x00, /* wcChar12 */ - 'I', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - ' ', 0x00, /* wcChar15 */ - 'D', 0x00, /* wcChar16 */ - 'E', 0x00, /* wcChar17 */ - 'M', 0x00, /* wcChar18 */ - 'O', 0x00, /* wcChar19 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif const uint8_t mac[6] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; @@ -438,11 +355,8 @@ void cdc_rndis_init(uint8_t busid, uintptr_t reg_base) { rndis_lwip_init(); -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &cdc_rndis_descriptor); -#else - usbd_desc_register(busid, cdc_rndis_descriptor); -#endif + usbd_add_interface(busid, usbd_rndis_init_intf(&intf0, CDC_OUT_EP, CDC_IN_EP, CDC_INT_EP, (uint8_t *)mac)); usbd_add_interface(busid, usbd_rndis_init_intf(&intf1, CDC_OUT_EP, CDC_IN_EP, CDC_INT_EP, (uint8_t *)mac)); usbd_initialize(busid, reg_base, usbd_event_handler); diff --git a/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c b/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c index 9c36433a08..0127c58ae8 100644 --- a/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c +++ b/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c @@ -15,7 +15,6 @@ #define USB_CONFIG_SIZE (9 + 9 + 9) -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01) }; @@ -77,134 +76,6 @@ const struct usb_descriptor dfu_flash_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t dfu_flash_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - DFU_DESCRIPTOR_INIT(), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x1e, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'D', 0x00, /* wcChar0 */ - 'F', 0x00, /* wcChar1 */ - 'U', 0x00, /* wcChar2 */ - 'W', 0x00, /* wcChar3 */ - 'i', 0x00, /* wcChar4 */ - 't', 0x00, /* wcChar5 */ - 'h', 0x00, /* wcChar6 */ - 's', 0x00, /* wcChar7 */ - 't', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 't', 0x00, /* wcChar10 */ - 'o', 0x00, /* wcChar11 */ - 'o', 0x00, /* wcChar12 */ - 'l', 0x00, /* wcChar13 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ - /////////////////////////////////////// - /// string4 descriptor - /////////////////////////////////////// - 0x60, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '@', 0x00, /* wcChar0 */ - 'I', 0x00, /* wcChar1 */ - 'n', 0x00, /* wcChar2 */ - 't', 0x00, /* wcChar3 */ - 'e', 0x00, /* wcChar4 */ - 'r', 0x00, /* wcChar5 */ - 'n', 0x00, /* wcChar6 */ - 'a', 0x00, /* wcChar7 */ - 'l', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'F', 0x00, /* wcChar10 */ - 'l', 0x00, /* wcChar11*/ - 'a', 0x00, /* wcChar12 */ - 's', 0x00, /* wcChar13 */ - 'h', 0x00, /* wcChar14 */ - ' ', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - ' ', 0x00, /* wcChar17 */ - '/', 0x00, /* wcChar18 */ - '0', 0x00, /* wcChar19 */ - 'x', 0x00, /* wcChar20 */ - '0', 0x00, /* wcChar21*/ - '8', 0x00, /* wcChar22 */ - '0', 0x00, /* wcChar23 */ - '0', 0x00, /* wcChar24 */ - '0', 0x00, /* wcChar25 */ - '0', 0x00, /* wcChar26 */ - '0', 0x00, /* wcChar27 */ - '0', 0x00, /* wcChar28 */ - '/', 0x00, /* wcChar29 */ - '1', 0x00, /* wcChar30 */ - '6', 0x00, /* wcChar31*/ - '*', 0x00, /* wcChar32 */ - '0', 0x00, /* wcChar33 */ - '0', 0x00, /* wcChar34 */ - '1', 0x00, /* wcChar35 */ - 'K', 0x00, /* wcChar36 */ - 'a', 0x00, /* wcChar37 */ - ',', 0x00, /* wcChar38 */ - '1', 0x00, /* wcChar39 */ - '1', 0x00, /* wcChar40 */ - '2', 0x00, /* wcChar41*/ - '*', 0x00, /* wcChar42 */ - '0', 0x00, /* wcChar43 */ - '1', 0x00, /* wcChar44 */ - 'K', 0x00, /* wcChar45 */ - 'g', 0x00, /* wcChar46 */ - -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static void usbd_event_handler(uint8_t busid, uint8_t event) { @@ -235,11 +106,8 @@ struct usbd_interface intf0; void dfu_flash_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &dfu_flash_descriptor); -#else - usbd_desc_register(busid, dfu_flash_descriptor); -#endif + usbd_add_interface(busid, usbd_dfu_init_intf(&intf0)); usbd_initialize(busid, reg_base, usbd_event_handler); } diff --git a/components/drivers/usb/cherryusb/demo/gamepad_template.c b/components/drivers/usb/cherryusb/demo/gamepad_template.c new file mode 100644 index 0000000000..2decbc7c08 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/gamepad_template.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_gamepad.h" + +#define GAMEPAD_IN_EP 0x81 +#define GAMEPAD_OUT_EP 0x02 + +#define USBD_MAX_POWER 500 + +static const uint8_t xinput_device_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, XINPUT_VID, XINPUT_PID, XINPUT_BCD_DEVICE, 0x01) +}; + +static const uint8_t switch_device_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, SWITCH_VID, SWITCH_PID, SWITCH_BCD_DEVICE, 0x01) +}; + +static const uint8_t xinput_config_descriptor[] = { + USB_CONFIG_DESCRIPTOR_INIT((9 + XINPUT_DESCRIPTOR_LEN), 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + XINPUT_DESCRIPTOR_INIT(0x00, GAMEPAD_OUT_EP, GAMEPAD_IN_EP) +}; + +static const uint8_t switch_config_descriptor[] = { + USB_CONFIG_DESCRIPTOR_INIT((9 + SWITCH_DESCRIPTOR_LEN), 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + SWITCH_DESCRIPTOR_INIT(0x00, GAMEPAD_OUT_EP, GAMEPAD_IN_EP) +}; + +static const char *xinput_string_descriptors[] = { + (const char[]){ 0x09, 0x04 }, /* Langid */ + "Microsoft", /* Manufacturer */ + "XInput STANDARD GAMEPAD", /* Product */ + "1.0", /* Serial Number */ +}; + +static const char *switch_string_descriptors[] = { + (const char[]){ 0x09, 0x04 }, /* Langid */ + "HORI", /* Manufacturer */ + "Switch Pro Controller", /* Product */ + "1.0", /* Serial Number */ +}; + +uint8_t gamepad_mode = USBD_GAMEPAD_MODE_XINPUT; +bool gamepad_init_flag = false; + +static const uint8_t *device_descriptor_callback(uint8_t speed) +{ + switch (gamepad_mode) { + case USBD_GAMEPAD_MODE_XINPUT: + return xinput_device_descriptor; + case USBD_GAMEPAD_MODE_SWITCH: + return switch_device_descriptor; + case USBD_GAMEPAD_MODE_XBOXONE: + break; + case USBD_GAMEPAD_MODE_PS4: + break; + + default: + break; + } + return NULL; +} + +static const uint8_t *config_descriptor_callback(uint8_t speed) +{ + switch (gamepad_mode) { + case USBD_GAMEPAD_MODE_XINPUT: + return xinput_config_descriptor; + case USBD_GAMEPAD_MODE_SWITCH: + return switch_config_descriptor; + case USBD_GAMEPAD_MODE_XBOXONE: + break; + case USBD_GAMEPAD_MODE_PS4: + break; + + default: + break; + } + return NULL; +} + +static const uint8_t *device_quality_descriptor_callback(uint8_t speed) +{ + return NULL; +} + +static const char *string_descriptor_callback(uint8_t speed, uint8_t index) +{ + if (index > 3) { + return NULL; + } + + switch (gamepad_mode) { + case USBD_GAMEPAD_MODE_XINPUT: + return xinput_string_descriptors[index]; + case USBD_GAMEPAD_MODE_SWITCH: + return switch_string_descriptors[index]; + case USBD_GAMEPAD_MODE_XBOXONE: + break; + case USBD_GAMEPAD_MODE_PS4: + break; + + default: + break; + } + return NULL; +} + +const struct usb_descriptor gamepad_descriptor = { + .device_descriptor_callback = device_descriptor_callback, + .config_descriptor_callback = config_descriptor_callback, + .device_quality_descriptor_callback = device_quality_descriptor_callback, + .string_descriptor_callback = string_descriptor_callback +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t gamepad_read_buffer[64]; +struct usb_gamepad_report gamepad_report; + +#define GAMEPAD_STATE_IDLE 0 +#define GAMEPAD_STATE_BUSY 1 + +volatile uint8_t gamepad_state = GAMEPAD_STATE_IDLE; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + usbd_ep_start_read(busid, GAMEPAD_OUT_EP, gamepad_read_buffer, usbd_get_ep_mps(busid, GAMEPAD_OUT_EP)); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +static void usbd_gamepad_int_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + gamepad_state = GAMEPAD_STATE_IDLE; +} + +void usbd_gamepad_int_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + usbd_ep_start_read(busid, GAMEPAD_OUT_EP, gamepad_read_buffer, usbd_get_ep_mps(busid, GAMEPAD_OUT_EP)); +} + +/*!< endpoint call back */ +static struct usbd_endpoint gamepad_in_ep = { + .ep_cb = usbd_gamepad_int_in_callback, + .ep_addr = GAMEPAD_IN_EP +}; + +static struct usbd_endpoint gamepad_out_ep = { + .ep_cb = usbd_gamepad_int_out_callback, + .ep_addr = GAMEPAD_OUT_EP +}; + +static struct usbd_interface intf0; + +void gamepad_init(uint8_t busid, uintptr_t reg_base) +{ + if (gamepad_init_flag) { + return; + } + + gamepad_init_flag = true; + + usbd_desc_register(busid, &gamepad_descriptor); + + switch (gamepad_mode) { + case USBD_GAMEPAD_MODE_XINPUT: + usbd_add_interface(busid, usbd_gamepad_xinput_init_intf(&intf0)); + break; + case USBD_GAMEPAD_MODE_SWITCH: + usbd_add_interface(busid, usbd_gamepad_switch_init_intf(&intf0)); + break; + case USBD_GAMEPAD_MODE_XBOXONE: + break; + case USBD_GAMEPAD_MODE_PS4: + break; + + default: + break; + } + + usbd_add_endpoint(busid, &gamepad_in_ep); + usbd_add_endpoint(busid, &gamepad_out_ep); + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +void gamepad_change_mode(uint8_t mode, uintptr_t reg_base) +{ + gamepad_mode = mode; + + if (gamepad_init_flag) { + usbd_deinitialize(0); + } + gamepad_init_flag = false; + gamepad_init(0, reg_base); +} + +void gamepad_test(uint8_t busid) +{ + static uint32_t test_counter = 0; + + if (usb_device_is_configured(busid) == false) { + return; + } + + gamepad_state = GAMEPAD_STATE_BUSY; + memset(&gamepad_report, 0, sizeof(gamepad_report)); + + gamepad_report.buttons = (1 << (test_counter % 18)); + + switch (gamepad_mode) { + case USBD_GAMEPAD_MODE_XINPUT: + usbd_gamepad_xinput_send_report(GAMEPAD_IN_EP, &gamepad_report); + break; + case USBD_GAMEPAD_MODE_SWITCH: + usbd_gamepad_switch_send_report(GAMEPAD_IN_EP, &gamepad_report); + break; + case USBD_GAMEPAD_MODE_XBOXONE: + break; + case USBD_GAMEPAD_MODE_PS4: + break; + + default: + break; + } + + test_counter++; + while (gamepad_state == GAMEPAD_STATE_BUSY) { + } +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c b/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c index 419fee2dc8..8a43d0a5fb 100644 --- a/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c +++ b/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c @@ -8,25 +8,8 @@ #include "usbd_core.h" #include "usbd_hid.h" - -/*!< hidraw in endpoint */ -#define HIDRAW_IN_EP 0x81 -#ifdef CONFIG_USB_HS -#define HIDRAW_IN_EP_SIZE 1024 -#define HIDRAW_IN_INTERVAL 4 -#else -#define HIDRAW_IN_EP_SIZE 64 -#define HIDRAW_IN_INTERVAL 10 -#endif -/*!< hidraw out endpoint */ -#define HIDRAW_OUT_EP 0x02 -#ifdef CONFIG_USB_HS -#define HIDRAW_OUT_EP_SIZE 1024 -#define HIDRAW_OUT_EP_INTERVAL 4 -#else -#define HIDRAW_OUT_EP_SIZE 64 -#define HIDRAW_OUT_EP_INTERVAL 10 -#endif +#define HIDRAW_IN_EP 0x81 +#define HIDRAW_OUT_EP 0x02 #define USBD_VID 0xffff #define USBD_PID 0xffff @@ -34,53 +17,26 @@ #define USBD_LANGID_STRING 1033 /*!< config descriptor size */ -#define USB_HID_CONFIG_DESC_SIZ (9 + 9 + 9 + 7 + 7) +#define USB_CONFIG_SIZE (9 + 9 + 9 + 7 + 7) /*!< custom hid report descriptor size */ #define HID_CUSTOM_REPORT_DESC_SIZE 38 -#ifdef CONFIG_USBDEV_ADVANCE_DESC +#ifdef CONFIG_USB_HS +#define HID_MAX_MPS 1024 +#define HIDRAW_IN_INTERVAL 1 +#else +#define HID_MAX_MPS 64 +#define HIDRAW_IN_INTERVAL 1 +#endif + static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /************** Descriptor of Custom interface *****************/ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Custom HID ********************/ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Custom in endpoint ********************/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HIDRAW_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - WBVAL(HIDRAW_IN_EP_SIZE), /* wMaxPacketSize: 4 Byte max */ - HIDRAW_IN_INTERVAL, /* bInterval: Polling Interval */ - /******************** Descriptor of Custom out endpoint ********************/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HIDRAW_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - WBVAL(HIDRAW_OUT_EP_SIZE), /* wMaxPacketSize: 4 Byte max */ - HIDRAW_OUT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 73 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + HID_CUSTOM_INOUT_DESCRIPTOR_INIT(0x00, 0x01, HID_CUSTOM_REPORT_DESC_SIZE, HIDRAW_OUT_EP, HIDRAW_IN_EP, HID_MAX_MPS, HIDRAW_IN_INTERVAL), }; static const uint8_t device_quality_descriptor[] = { @@ -135,120 +91,6 @@ const struct usb_descriptor hid_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -static const uint8_t hid_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /************** Descriptor of Custom interface *****************/ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Custom HID ********************/ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Custom in endpoint ********************/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HIDRAW_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - WBVAL(HIDRAW_IN_EP_SIZE), /* wMaxPacketSize: 4 Byte max */ - HIDRAW_IN_INTERVAL, /* bInterval: Polling Interval */ - /******************** Descriptor of Custom out endpoint ********************/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HIDRAW_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - WBVAL(HIDRAW_OUT_EP_SIZE), /* wMaxPacketSize: 4 Byte max */ - HIDRAW_OUT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 73 */ - /* - * string0 descriptor - */ - USB_LANGID_INIT(USBD_LANGID_STRING), - /* - * string1 descriptor - */ - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /* - * string2 descriptor - */ - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'H', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'D', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /* - * string3 descriptor - */ - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /* - * device qualifier descriptor - */ - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif /*!< custom hid report descriptor */ static const uint8_t hid_custom_report_desc[HID_CUSTOM_REPORT_DESC_SIZE] = { @@ -261,16 +103,16 @@ static const uint8_t hid_custom_report_desc[HID_CUSTOM_REPORT_DESC_SIZE] = { 0x09, 0x02, /* USAGE (Vendor Usage 1) */ 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ 0x25, 0xff, /*LOGICAL_MAXIMUM (255) */ - 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ 0x96, 0xff, 0x03, /* REPORT_COUNT (63) */ 0x81, 0x02, /* INPUT (Data,Var,Abs) */ /* <___________________________________________________> */ 0x85, 0x01, /* REPORT ID (0x01) */ 0x09, 0x03, /* USAGE (Vendor Usage 1) */ 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ - 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ 0x75, 0x08, /* REPORT_SIZE (8) */ - 0x96, 0xff, 0x03, /* REPORT_COUNT (63) */ + 0x96, 0xff, 0x03, /* REPORT_COUNT (63) */ 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */ /* USER CODE END 0 */ 0xC0 /* END_COLLECTION */ @@ -299,8 +141,8 @@ static const uint8_t hid_custom_report_desc[HID_CUSTOM_REPORT_DESC_SIZE] = { #endif }; -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[HIDRAW_OUT_EP_SIZE]; -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t send_buffer[HIDRAW_IN_EP_SIZE]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[HID_MAX_MPS]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t send_buffer[HID_MAX_MPS]; #define HID_STATE_IDLE 0 #define HID_STATE_BUSY 1 @@ -311,27 +153,27 @@ static volatile uint8_t custom_state; static void usbd_event_handler(uint8_t busid, uint8_t event) { switch (event) { - case USBD_EVENT_RESET: - break; - case USBD_EVENT_CONNECTED: - break; - case USBD_EVENT_DISCONNECTED: - break; - case USBD_EVENT_RESUME: - break; - case USBD_EVENT_SUSPEND: - break; - case USBD_EVENT_CONFIGURED: - /* setup first out ep read transfer */ - usbd_ep_start_read(busid, HIDRAW_OUT_EP, read_buffer, HIDRAW_OUT_EP_SIZE); - break; - case USBD_EVENT_SET_REMOTE_WAKEUP: - break; - case USBD_EVENT_CLR_REMOTE_WAKEUP: - break; - - default: - break; + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, HIDRAW_OUT_EP, read_buffer, HID_MAX_MPS); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; } } @@ -346,7 +188,7 @@ static void usbd_hid_custom_in_callback(uint8_t busid, uint8_t ep, uint32_t nbyt static void usbd_hid_custom_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { USB_LOG_RAW("actual out len:%d\r\n", (unsigned int)nbytes); - usbd_ep_start_read(busid, ep, read_buffer, HIDRAW_IN_EP_SIZE); + usbd_ep_start_read(busid, ep, read_buffer, HID_MAX_MPS); read_buffer[0] = 0x02; /* IN: report id */ usbd_ep_start_write(busid, HIDRAW_IN_EP, read_buffer, nbytes); } @@ -372,11 +214,8 @@ struct usbd_interface intf0; void hid_custom_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &hid_descriptor); -#else - usbd_desc_register(busid, hid_descriptor); -#endif + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_custom_report_desc, HID_CUSTOM_REPORT_DESC_SIZE)); usbd_add_endpoint(busid, &custom_in_ep); usbd_add_endpoint(busid, &custom_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c b/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c index 9fabba60dd..843a726729 100644 --- a/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c +++ b/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c @@ -15,49 +15,16 @@ #define HID_INT_EP_SIZE 8 #define HID_INT_EP_INTERVAL 10 -#define USB_HID_CONFIG_DESC_SIZ 34 +#define USB_CONFIG_SIZE 34 #define HID_KEYBOARD_REPORT_DESC_SIZE 63 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + HID_KEYBOARD_DESCRIPTOR_INIT(0x00, 0x01, HID_KEYBOARD_REPORT_DESC_SIZE, HID_INT_EP, HID_INT_EP_SIZE, HID_INT_EP_INTERVAL), }; static const uint8_t device_quality_descriptor[] = { @@ -112,117 +79,6 @@ const struct usb_descriptor hid_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -static const uint8_t hid_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'H', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'D', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif /* USB HID device Configuration Descriptor */ static uint8_t hid_desc[9] __ALIGN_END = { @@ -319,11 +175,8 @@ struct usbd_interface intf0; void hid_keyboard_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &hid_descriptor); -#else - usbd_desc_register(busid, hid_descriptor); -#endif + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_keyboard_report_desc, HID_KEYBOARD_REPORT_DESC_SIZE)); usbd_add_endpoint(busid, &hid_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/hid_mouse_template.c b/components/drivers/usb/cherryusb/demo/hid_mouse_template.c index bcd03e1d17..24d32f90df 100644 --- a/components/drivers/usb/cherryusb/demo/hid_mouse_template.c +++ b/components/drivers/usb/cherryusb/demo/hid_mouse_template.c @@ -17,50 +17,17 @@ #define USBD_LANGID_STRING 1033 /*!< config descriptor size */ -#define USB_HID_CONFIG_DESC_SIZ 34 +#define USB_CONFIG_SIZE 34 /*!< report descriptor size */ #define HID_MOUSE_REPORT_DESC_SIZE 74 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + HID_MOUSE_DESCRIPTOR_INIT(0x00, 0x01, HID_MOUSE_REPORT_DESC_SIZE, HID_INT_EP, HID_INT_EP_SIZE, HID_INT_EP_INTERVAL), }; static const uint8_t device_quality_descriptor[] = { @@ -115,118 +82,6 @@ const struct usb_descriptor hid_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -const uint8_t hid_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'H', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'D', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif /*!< hid mouse report descriptor */ static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { @@ -337,11 +192,8 @@ struct usbd_interface intf0; void hid_mouse_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &hid_descriptor); -#else - usbd_desc_register(busid, hid_descriptor); -#endif + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); usbd_add_endpoint(busid, &hid_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c b/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c index fa4381191d..c2c61305e6 100644 --- a/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c +++ b/components/drivers/usb/cherryusb/demo/hid_remote_wakeup_template.c @@ -17,50 +17,17 @@ #define USBD_LANGID_STRING 1033 /*!< config descriptor size */ -#define USB_HID_CONFIG_DESC_SIZ 34 +#define USB_CONFIG_SIZE 34 /*!< report descriptor size */ #define HID_MOUSE_REPORT_DESC_SIZE 74 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_REMOTE_WAKEUP | USB_CONFIG_SELF_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_REMOTE_WAKEUP | USB_CONFIG_SELF_POWERED, USBD_MAX_POWER), + HID_MOUSE_DESCRIPTOR_INIT(0x00, 0x01, HID_MOUSE_REPORT_DESC_SIZE, HID_INT_EP, HID_INT_EP_SIZE, HID_INT_EP_INTERVAL), }; static const uint8_t device_quality_descriptor[] = { @@ -115,118 +82,6 @@ const struct usb_descriptor hid_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -/*!< global descriptor */ -const uint8_t hid_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_REMOTE_WAKEUP | USB_CONFIG_SELF_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'H', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'D', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif /*!< hid mouse report descriptor */ static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { @@ -337,11 +192,8 @@ static struct usbd_interface intf0; void hid_mouse_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &hid_descriptor); -#else - usbd_desc_register(busid, hid_descriptor); -#endif + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); usbd_add_endpoint(busid, &hid_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/midi_template.c b/components/drivers/usb/cherryusb/demo/midi_template.c index 0203c74445..f0e66c4be9 100644 --- a/components/drivers/usb/cherryusb/demo/midi_template.c +++ b/components/drivers/usb/cherryusb/demo/midi_template.c @@ -14,7 +14,13 @@ #define USBD_MAX_POWER 100 #define USBD_LANGID_STRING 1033 -#define USB_CONFIG_SIZE (9 + 9 + 9 + 9 + 7 + MIDI_SIZEOF_JACK_DESC + 9 + 5 + 9 + 5) +#define AUDIO_AC_SIZ AUDIO_SIZEOF_AC_HEADER_DESC(1) +#define AUDIO_MS_SIZ (7 + MIDI_SIZEOF_JACK_DESC + 9 + 5 + 9 + 5) + +#define USB_CONFIG_SIZE (unsigned long)(9 + \ + AUDIO_AC_DESCRIPTOR_LEN(1) + \ + MIDI_STANDARD_DESCRIPTOR_LEN + \ + AUDIO_MS_SIZ) #ifdef CONFIG_USB_HS #define MIDI_EP_MPS 512 @@ -22,55 +28,15 @@ #define MIDI_EP_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01) }; static const uint8_t config_descriptor[] = { USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - // Standard AC Interface Descriptor - 0x09, - 0x04, - 0x00, - 0x00, - 0x00, - 0x01, - 0x01, - 0x00, - 0x00, - // Class-specific AC Interface Descriptor - 0x09, - 0x24, - 0x01, - 0x00, - 0x01, - 0x09, - 0x00, - 0x01, - 0x01, - // MIDIStreaming Interface Descriptors - 0x09, - 0x04, - 0x01, - 0x00, - 0x02, - 0x01, - 0x03, - 0x00, - 0x00, - // Class-Specific MS Interface Header Descriptor - 0x07, - 0x24, - 0x01, - 0x00, - 0x01, - WBVAL(65), - - // MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, 0x01), - // MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, 0x02), - // MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, 0x03, 0x02), - // MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, 0x04, 0x01), + AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, 0x00, 0x01), + MIDI_STANDARD_DESCRIPTOR_INIT(0x01, 0x02), + MIDI_CS_HEADER_DESCRIPTOR_INIT(AUDIO_MS_SIZ), MIDI_JACK_DESCRIPTOR_INIT(0x01), // OUT endpoint descriptor 0x09, 0x05, MIDI_OUT_EP, 0x02, WBVAL(MIDI_EP_MPS), 0x00, 0x00, 0x00, @@ -133,136 +99,6 @@ const struct usb_descriptor midi_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t midi_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - // Standard AC Interface Descriptor - 0x09, - 0x04, - 0x00, - 0x00, - 0x00, - 0x01, - 0x01, - 0x00, - 0x00, - // Class-specific AC Interface Descriptor - 0x09, - 0x24, - 0x01, - 0x00, - 0x01, - 0x09, - 0x00, - 0x01, - 0x01, - // MIDIStreaming Interface Descriptors - 0x09, - 0x04, - 0x01, - 0x00, - 0x02, - 0x01, - 0x03, - 0x00, - 0x00, - // Class-Specific MS Interface Header Descriptor - 0x07, - 0x24, - 0x01, - 0x00, - 0x01, - WBVAL(65), - - // MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, 0x01), - // MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, 0x02), - // MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, 0x03, 0x02), - // MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, 0x04, 0x01), - MIDI_JACK_DESCRIPTOR_INIT(0x01), - // OUT endpoint descriptor - 0x09, 0x05, MIDI_OUT_EP, 0x02, WBVAL(MIDI_EP_MPS), 0x00, 0x00, 0x00, - 0x05, 0x25, 0x01, 0x01, 0x01, - - // IN endpoint descriptor - 0x09, 0x05, MIDI_IN_EP, 0x02, WBVAL(MIDI_EP_MPS), 0x00, 0x00, 0x00, - 0x05, 0x25, 0x01, 0x01, 0x03, - - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x28, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'M', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'D', 0x00, /* wcChar12 */ - 'I', 0x00, /* wcChar13 */ - ' ', 0x00, /* wcChar14 */ - 'D', 0x00, /* wcChar15 */ - 'E', 0x00, /* wcChar16 */ - 'M', 0x00, /* wcChar17 */ - 'O', 0x00, /* wcChar18 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[MIDI_EP_MPS]; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[MIDI_EP_MPS]; @@ -317,11 +153,8 @@ struct usbd_endpoint midi_in_ep = { void midi_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &midi_descriptor); -#else - usbd_desc_register(busid, midi_descriptor); -#endif + usbd_add_interface(busid, &intf0); usbd_add_interface(busid, &intf1); usbd_add_endpoint(busid, &midi_out_ep); diff --git a/components/drivers/usb/cherryusb/demo/msc_ram_template.c b/components/drivers/usb/cherryusb/demo/msc_ram_template.c index ac7d9dbd08..cd8f646463 100644 --- a/components/drivers/usb/cherryusb/demo/msc_ram_template.c +++ b/components/drivers/usb/cherryusb/demo/msc_ram_template.c @@ -22,7 +22,6 @@ #define MSC_MAX_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01) }; @@ -84,85 +83,6 @@ const struct usb_descriptor msc_ram_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t msc_ram_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - MSC_DESCRIPTOR_INIT(0x00, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'M', 0x00, /* wcChar10 */ - 'S', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static void usbd_event_handler(uint8_t busid, uint8_t event) { @@ -267,11 +187,8 @@ void msc_ram_init(uint8_t busid, uintptr_t reg_base) res = rt_device_open(blk_dev, RT_DEVICE_OFLAG_RDWR); RT_ASSERT(res == RT_EOK); #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &msc_ram_descriptor); -#else - usbd_desc_register(busid, msc_ram_descriptor); -#endif + usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf0, MSC_OUT_EP, MSC_IN_EP)); usbd_initialize(busid, reg_base, usbd_event_handler); diff --git a/components/drivers/usb/cherryusb/demo/usb_host.c b/components/drivers/usb/cherryusb/demo/usb_host.c index 0863970eda..5f6e6e9267 100644 --- a/components/drivers/usb/cherryusb/demo/usb_host.c +++ b/components/drivers/usb/cherryusb/demo/usb_host.c @@ -4,79 +4,73 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "usbh_core.h" -#include "usbh_cdc_acm.h" +#include "usbh_serial.h" #include "usbh_hid.h" #include "usbh_msc.h" -#include "usbh_video.h" -#include "usbh_audio.h" -#ifndef CONFIG_TEST_USBH_CDC_ACM -#define CONFIG_TEST_USBH_CDC_ACM 1 -#endif -#ifndef TEST_USBH_CDC_SPEED -#define TEST_USBH_CDC_SPEED 0 -#endif -#ifndef CONFIG_TEST_USBH_HID -#define CONFIG_TEST_USBH_HID 1 -#endif -#ifndef CONFIG_TEST_USBH_MSC -#define CONFIG_TEST_USBH_MSC 1 -#endif -#ifndef TEST_USBH_MSC_FATFS -#define TEST_USBH_MSC_FATFS 0 -#endif -#ifndef TEST_USBH_MSC_FATFS_SPEED -#define TEST_USBH_MSC_FATFS_SPEED 0 -#endif -#ifndef CONFIG_TEST_USBH_AUDIO -#define CONFIG_TEST_USBH_AUDIO 0 -#endif -#ifndef CONFIG_TEST_USBH_VIDEO -#define CONFIG_TEST_USBH_VIDEO 0 -#endif +// net class demos use socket api -#if defined(TEST_USBH_CDC_ECM) || defined(TEST_USBH_CDC_RNDIS) || defined(TEST_USBH_ASIX) || defined(TEST_USBH_RTL8152) -#error we have move those class implements into platform/none/usbh_lwip.c, and you should call tcpip_init(NULL, NULL) in your app +#ifdef CONFIG_TEST_USBH_SERIAL +#define SERIAL_TEST_LEN (1 * 1024) + +#if SERIAL_TEST_LEN >= CONFIG_USBHOST_SERIAL_RX_SIZE +#error SERIAL_TEST_LEN is larger than CONFIG_USBHOST_SERIAL_RX_SIZE, please reduce SERIAL_TEST_LEN or increase CONFIG_USBHOST_SERIAL_RX_SIZE #endif -#if CONFIG_TEST_USBH_CDC_ACM -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t cdc_buffer[4096]; +volatile uint32_t serial_tx_bytes = 0; +volatile uint32_t serial_rx_bytes = 0; +volatile bool serial_is_opened = false; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t serial_tx_buffer[SERIAL_TEST_LEN]; +uint8_t serial_rx_data[SERIAL_TEST_LEN]; -#if TEST_USBH_CDC_SPEED +#ifdef CONFIG_TEST_USBH_CDC_SPEED #define TEST_LEN (16 * 1024) #define TEST_COUNT (10240) -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t cdc_speed_buffer[TEST_LEN]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t serial_speed_buffer[TEST_LEN]; #endif -void usbh_cdc_acm_callback(void *arg, int nbytes) +static void usbh_serial_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) { - //struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)arg; - - if (nbytes > 0) { - for (size_t i = 0; i < nbytes; i++) { - USB_LOG_RAW("0x%02x ", cdc_buffer[i]); + int ret; + struct usbh_serial *serial; + bool serial_test_success = false; + + serial = usbh_serial_open("/dev/ttyACM0", USBH_SERIAL_O_RDWR | USBH_SERIAL_O_NONBLOCK); + if (serial == NULL) { + serial = usbh_serial_open("/dev/ttyUSB0", USBH_SERIAL_O_RDWR | USBH_SERIAL_O_NONBLOCK); + if (serial == NULL) { + USB_LOG_RAW("no serial device found\r\n"); + goto delete; } - USB_LOG_RAW("nbytes:%d\r\n", (unsigned int)nbytes); } -} -static void usbh_cdc_acm_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) -{ - int ret; - struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)CONFIG_USB_OSAL_THREAD_GET_ARGV; + struct usbh_serial_termios termios; + + memset(&termios, 0, sizeof(termios)); + termios.baudrate = 115200; + termios.stopbits = 0; + termios.parity = 0; + termios.databits = 8; + termios.rtscts = false; + termios.rx_timeout = 0; + ret = usbh_serial_control(serial, USBH_SERIAL_CMD_SET_ATTR, &termios); + if (ret < 0) { + USB_LOG_RAW("set serial attr error, ret:%d\r\n", ret); + goto delete_with_close; + } /* test with only one buffer, if you have more cdc acm class, modify by yourself */ -#if TEST_USBH_CDC_SPEED +#ifdef CONFIG_TEST_USBH_CDC_SPEED const uint32_t test_len[] = { 512, 1 * 1024, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024 }; - memset(cdc_speed_buffer, 0xAA, TEST_LEN); + memset(serial_speed_buffer, 0xAA, TEST_LEN); for (uint8_t j = 0; j < 6; j++) { uint32_t start_time = (uint32_t)xTaskGetTickCount(); for (uint32_t i = 0; i < TEST_COUNT; i++) { - usbh_bulk_urb_fill(&cdc_acm_class->bulkout_urb, cdc_acm_class->hport, cdc_acm_class->bulkout, cdc_speed_buffer, test_len[j], 0XFFFFFFF, NULL, NULL); - ret = usbh_submit_urb(&cdc_acm_class->bulkout_urb); + usbh_serial_write(serial, serial_speed_buffer, test_len[j]); if (ret < 0) { USB_LOG_RAW("bulk out error,ret:%d\r\n", ret); while (1) { @@ -87,35 +81,75 @@ static void usbh_cdc_acm_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) uint32_t time_ms = xTaskGetTickCount() - start_time; USB_LOG_RAW("per packet len:%d, out speed:%f MB/S\r\n", (unsigned int)test_len[j], (test_len[j] * TEST_COUNT / 1024 / 1024) * 1000 / ((float)time_ms)); } + usbh_serial_close(serial); + goto delete; #endif - memset(cdc_buffer, 0x55, 4096); + memset(serial_tx_buffer, 0xA5, sizeof(serial_tx_buffer)); + USB_LOG_RAW("start serial loopback test, len: %d\r\n", SERIAL_TEST_LEN); + + serial_tx_bytes = 0; + while (1) { + ret = usbh_serial_write(serial, serial_tx_buffer, sizeof(serial_tx_buffer)); + if (ret < 0) { + USB_LOG_RAW("serial write error, ret:%d\r\n", ret); + goto delete_with_close; + } else { + serial_tx_bytes += ret; - /* for common, we use timeout with 0xffffffff, this is just a test */ - usbh_bulk_urb_fill(&cdc_acm_class->bulkout_urb, cdc_acm_class->hport, cdc_acm_class->bulkout, cdc_buffer, sizeof(cdc_buffer), 3000, NULL, NULL); - ret = usbh_submit_urb(&cdc_acm_class->bulkout_urb); - if (ret < 0) { - USB_LOG_RAW("bulk out error,ret:%d\r\n", ret); - goto delete; - } else { - USB_LOG_RAW("send over:%d\r\n", (unsigned int)cdc_acm_class->bulkout_urb.actual_length); + if (serial_tx_bytes == SERIAL_TEST_LEN) { + USB_LOG_RAW("send over\r\n"); + break; + } + } } - /* we can change cdc_acm_class->bulkin->wMaxPacketSize with 4096 for testing zlp, default is ep mps */ - usbh_bulk_urb_fill(&cdc_acm_class->bulkin_urb, cdc_acm_class->hport, cdc_acm_class->bulkin, cdc_buffer, cdc_acm_class->bulkin->wMaxPacketSize, 0xffffffff, usbh_cdc_acm_callback, cdc_acm_class); - ret = usbh_submit_urb(&cdc_acm_class->bulkin_urb); - if (ret < 0) { - USB_LOG_RAW("bulk in error,ret:%d\r\n", ret); - goto delete; - } else { + volatile uint32_t wait_timeout = 0; + serial_rx_bytes = 0; + while (1) { + ret = usbh_serial_read(serial, &serial_rx_data[serial_rx_bytes], SERIAL_TEST_LEN - serial_rx_bytes); + if (ret < 0) { + USB_LOG_RAW("serial read error, ret:%d\r\n", ret); + goto delete_with_close; + } else { + serial_rx_bytes += ret; + + if (serial_rx_bytes == SERIAL_TEST_LEN) { + USB_LOG_RAW("receive over\r\n"); + for (uint32_t i = 0; i < SERIAL_TEST_LEN; i++) { + if (serial_rx_data[i] != 0xa5) { + USB_LOG_RAW("serial loopback data error at index %d, data: 0x%02x\r\n", (unsigned int)i, serial_rx_data[i]); + goto delete_with_close; + } + } + serial_test_success = true; + break; + } + } + wait_timeout++; + + if (wait_timeout > 500) { // 5s + USB_LOG_RAW("serial read timeout\r\n"); + goto delete_with_close; + } + + usb_osal_msleep(10); } + // clang-format off +delete_with_close: + if (serial_test_success) { + USB_LOG_RAW("serial loopback test success\r\n"); + } else { + USB_LOG_RAW("serial loopback test failed\r\n"); + } + usbh_serial_close(serial); delete: usb_osal_thread_delete(NULL); // clang-format on } #endif -#if CONFIG_TEST_USBH_HID +#ifdef CONFIG_TEST_USBH_HID USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t hid_buffer[128]; void usbh_hid_callback(void *arg, int nbytes) @@ -140,7 +174,6 @@ static void usbh_hid_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) { int ret; struct usbh_hid *hid_class = (struct usbh_hid *)CONFIG_USB_OSAL_THREAD_GET_ARGV; - ; /* test with only one buffer, if you have more hid class, modify by yourself */ @@ -157,15 +190,15 @@ delete: } #endif -#if CONFIG_TEST_USBH_MSC +#ifdef CONFIG_TEST_USBH_MSC -#if TEST_USBH_MSC_FATFS +#ifdef CONFIG_TEST_USBH_MSC_FATFS #include "ff.h" -#if TEST_USBH_MSC_FATFS_SPEED +#ifdef CONFIG_TEST_USBH_MSC_FATFS_SPEED #define WRITE_SIZE_MB (128UL) -#define WRITE_SIZE (1024UL * 1024UL * WRITE_SIZE_MB) -#define BUF_SIZE (1024UL * 128UL) +#define WRITE_SIZE (1024UL * 1024UL * WRITE_SIZE_MB) +#define BUF_SIZE (1024UL * 128UL) USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_write_buffer[BUF_SIZE]; #else USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_write_buffer[25 * 100]; @@ -223,7 +256,7 @@ int usb_msc_fatfs_test() goto unmount; } -#if TEST_USBH_MSC_FATFS_SPEED +#ifdef CONFIG_TEST_USBH_MSC_FATFS_SPEED for (uint32_t i = 0; i < BUF_SIZE; i++) { read_write_buffer[i] = i % 256; } @@ -234,9 +267,9 @@ int usb_msc_fatfs_test() uint32_t write_size = WRITE_SIZE; uint32_t start_time = (uint32_t)xTaskGetTickCount(); while (write_size > 0) { - res_sd = f_write(&fnew, read_write_buffer, BUF_SIZE, (UINT*)&fnum); + res_sd = f_write(&fnew, read_write_buffer, BUF_SIZE, (UINT *)&fnum); if (res_sd != FR_OK) { - printf("Write file failed, cause: %s\n", res_sd); + USB_LOG_RAW("Write file failed, cause: %s\n", res_sd); goto unmount; } write_size -= BUF_SIZE; @@ -260,9 +293,9 @@ int usb_msc_fatfs_test() uint32_t write_size = WRITE_SIZE; uint32_t start_time = (uint32_t)xTaskGetTickCount(); while (write_size > 0) { - res_sd = f_read(&fnew, read_write_buffer, BUF_SIZE, (UINT*)&fnum); + res_sd = f_read(&fnew, read_write_buffer, BUF_SIZE, (UINT *)&fnum); if (res_sd != FR_OK) { - printf("Read file failed, cause: %s\n", res_sd); + USB_LOG_RAW("Read file failed, cause: %s\n", res_sd); goto unmount; } write_size -= BUF_SIZE; @@ -295,8 +328,10 @@ static void usbh_msc_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) int ret; struct usbh_msc *msc_class = (struct usbh_msc *)CONFIG_USB_OSAL_THREAD_GET_ARGV; + (void)msc_class; + /* test with only one buffer, if you have more msc class, modify by yourself */ -#if TEST_USBH_MSC_FATFS == 0 +#ifndef TEST_USBH_MSC_FATFS ret = usbh_msc_scsi_init(msc_class); if (ret < 0) { USB_LOG_RAW("scsi_init error,ret:%d\r\n", ret); @@ -326,18 +361,23 @@ delete: } #endif -#if CONFIG_TEST_USBH_CDC_ACM -void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) +#ifdef CONFIG_TEST_USBH_SERIAL +void usbh_serial_run(struct usbh_serial *serial) { - usb_osal_thread_create("usbh_cdc", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_acm_thread, cdc_acm_class); + if (serial_is_opened) { + return; + } + serial_is_opened = true; + usb_osal_thread_create("usbh_serial", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_serial_thread, serial); } -void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) +void usbh_serial_stop(struct usbh_serial *serial) { + serial_is_opened = false; } #endif -#if CONFIG_TEST_USBH_HID +#ifdef CONFIG_TEST_USBH_HID void usbh_hid_run(struct usbh_hid *hid_class) { usb_osal_thread_create("usbh_hid", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_hid_thread, hid_class); @@ -348,7 +388,7 @@ void usbh_hid_stop(struct usbh_hid *hid_class) } #endif -#if CONFIG_TEST_USBH_MSC +#ifdef CONFIG_TEST_USBH_MSC void usbh_msc_run(struct usbh_msc *msc_class) { usb_osal_thread_create("usbh_msc", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_msc_thread, msc_class); @@ -359,14 +399,6 @@ void usbh_msc_stop(struct usbh_msc *msc_class) } #endif -#if CONFIG_TEST_USBH_AUDIO -#error "commercial charge" -#endif - -#if CONFIG_TEST_USBH_VIDEO -#error "commercial charge" -#endif - #if 0 #include "usbh_aoa.h" diff --git a/components/drivers/usb/cherryusb/demo/usbh_bl616_wifi_cli.c b/components/drivers/usb/cherryusb/demo/usbh_bl616_wifi_cli.c new file mode 100644 index 0000000000..125a26394d --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/usbh_bl616_wifi_cli.c @@ -0,0 +1,182 @@ +#include "usbh_core.h" +#include "usbh_cdc_acm.h" +#include "shell.h" + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t cdc_buffer[8 * 1024]; + +int wifi_scan(int argc, char **argv) +{ + struct usbh_cdc_acm *cdc_acm_class = usbh_find_class_instance("/dev/ttyACM0"); + uint32_t len; + int ret; + + if (cdc_acm_class == NULL) { + printf("cdc acm class not found\r\n"); + return -1; + } + + len = snprintf((char *)cdc_buffer, sizeof(cdc_buffer), "ap_scan\r\n"); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, cdc_buffer, len, 3000); + if (ret < 0) { + printf("wifi scan failed1, ret:%d\r\n", ret); + return -1; + } + + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, cdc_buffer, sizeof(cdc_buffer), 3000); + if (ret < 0) { + printf("wifi scan failed2, ret:%d\r\n", ret); + return -1; + } + cdc_buffer[ret] = '\0'; + printf("%s\r\n", cdc_buffer); + return 0; +} +CSH_CMD_EXPORT(wifi_scan, wifi_scan); + +int wifi_scan_result(int argc, char **argv) +{ + struct usbh_cdc_acm *cdc_acm_class = usbh_find_class_instance("/dev/ttyACM0"); + uint32_t len; + int ret; + + if (cdc_acm_class == NULL) { + printf("cdc acm class not found\r\n"); + return -1; + } + + len = snprintf((char *)cdc_buffer, sizeof(cdc_buffer), "ap_scan_result {\"offset\":0, \"count\":0}\r\n"); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, cdc_buffer, len, 3000); + if (ret < 0) { + printf("wifi scan failed1, ret:%d\r\n", ret); + return -1; + } + + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, cdc_buffer, sizeof(cdc_buffer), 3000); + if (ret < 0) { + printf("wifi scan failed2, ret:%d\r\n", ret); + return -1; + } + cdc_buffer[ret] = '\0'; + printf("%s\r\n", cdc_buffer); + return 0; +} +CSH_CMD_EXPORT(wifi_scan_result, wifi_scan_result); + +int wifi_connect(int argc, char **argv) +{ + struct usbh_cdc_acm *cdc_acm_class = usbh_find_class_instance("/dev/ttyACM0"); + uint32_t len; + int ret; + + if (cdc_acm_class == NULL) { + printf("cdc acm class not found\r\n"); + return -1; + } + + if (argc < 3) { + printf("please input correct command: wifi_connect ssid password\r\n"); + return -1; + } + + len = snprintf((char *)cdc_buffer, sizeof(cdc_buffer), "ap_connect {\"ssid\":\"%s\", \"password\":\"%s\"}\r\n", argv[1], argv[2]); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, cdc_buffer, len, 3000); + if (ret < 0) { + printf("wifi connect failed1, ret:%d\r\n", ret); + return -1; + } + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, cdc_buffer, sizeof(cdc_buffer), 3000); + if (ret < 0) { + printf("wifi connect failed2, ret:%d\r\n", ret); + return -1; + } + cdc_buffer[ret] = '\0'; + printf("%s\r\n", cdc_buffer); + return 0; +} +CSH_CMD_EXPORT(wifi_connect, wifi_connect); + +int wifi_disconnect(int argc, char **argv) +{ + struct usbh_cdc_acm *cdc_acm_class = usbh_find_class_instance("/dev/ttyACM0"); + uint32_t len; + int ret; + + if (cdc_acm_class == NULL) { + printf("cdc acm class not found\r\n"); + return -1; + } + + len = snprintf((char *)cdc_buffer, sizeof(cdc_buffer), "ap_disconnect\r\n"); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, cdc_buffer, len, 3000); + if (ret < 0) { + printf("wifi disconnect failed1, ret:%d\r\n", ret); + return -1; + } + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, cdc_buffer, sizeof(cdc_buffer), 3000); + if (ret < 0) { + printf("wifi disconnect failed2, ret:%d\r\n", ret); + return -1; + } + cdc_buffer[ret] = '\0'; + printf("%s\r\n", cdc_buffer); + return 0; +} +CSH_CMD_EXPORT(wifi_disconnect, wifi_disconnect); + +int wifi_status(int argc, char **argv) +{ + struct usbh_cdc_acm *cdc_acm_class = usbh_find_class_instance("/dev/ttyACM0"); + uint32_t len; + int ret; + + if (cdc_acm_class == NULL) { + printf("cdc acm class not found\r\n"); + return -1; + } + + len = snprintf((char *)cdc_buffer, sizeof(cdc_buffer), "ap_status\r\n"); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, cdc_buffer, len, 3000); + if (ret < 0) { + printf("wifi status failed1, ret:%d\r\n", ret); + return -1; + } + + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, cdc_buffer, sizeof(cdc_buffer), 3000); + if (ret < 0) { + printf("wifi status failed2, ret:%d\r\n", ret); + return -1; + } + cdc_buffer[ret] = '\0'; + printf("%s\r\n", cdc_buffer); + return 0; +} +CSH_CMD_EXPORT(wifi_status, wifi_status); + +int wifi_version(int argc, char **argv) +{ + struct usbh_cdc_acm *cdc_acm_class = usbh_find_class_instance("/dev/ttyACM0"); + uint32_t len; + int ret; + + if (cdc_acm_class == NULL) { + printf("cdc acm class not found\r\n"); + return -1; + } + + len = snprintf((char *)cdc_buffer, sizeof(cdc_buffer), "sys_version\r\n"); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, cdc_buffer, len, 3000); + if (ret < 0) { + printf("wifi status failed1, ret:%d\r\n", ret); + return -1; + } + + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, cdc_buffer, sizeof(cdc_buffer), 3000); + if (ret < 0) { + printf("wifi status failed2, ret:%d\r\n", ret); + return -1; + } + cdc_buffer[ret] = '\0'; + printf("%s\r\n", cdc_buffer); + return 0; +} +CSH_CMD_EXPORT(wifi_version, wifi_version); \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c b/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c index 99df89b995..fab4044fe1 100644 --- a/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c +++ b/components/drivers/usb/cherryusb/demo/video_audiov1_hid_template.c @@ -46,15 +46,15 @@ VS_HEADER_SIZ + \ 9 + \ 7 + \ - AUDIO_AC_DESCRIPTOR_INIT_LEN(2) + \ + AUDIO_AC_DESCRIPTOR_LEN(2) + \ AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ - AUDIO_AS_DESCRIPTOR_INIT_LEN(1) + \ - AUDIO_AS_DESCRIPTOR_INIT_LEN(1) + \ + AUDIO_AS_DESCRIPTOR_LEN(1) + \ + AUDIO_AS_DESCRIPTOR_LEN(1) + \ 25) #define USBD_VID 0xffff @@ -103,7 +103,6 @@ #define HID_KEYBOARD_REPORT_DESC_SIZE 63 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01) }; @@ -130,38 +129,7 @@ static const uint8_t config_descriptor[] = { EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), AUDIO_AS_DESCRIPTOR_INIT(0x04, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)), - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x05, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ + HID_KEYBOARD_DESCRIPTOR_INIT(0x05, 0x01, HID_KEYBOARD_REPORT_DESC_SIZE, HID_INT_EP, HID_INT_EP_SIZE, HID_INT_EP_INTERVAL), }; static const uint8_t device_quality_descriptor[] = { @@ -216,136 +184,6 @@ const struct usb_descriptor video_audio_hid_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t video_audio_hid_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x06, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - //VIDEO_VC_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VC_NOEP_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), - VIDEO_VS_INPUT_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 0x00), - VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(0x01, 0x01), - VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, MAX_FRAME_SIZE, DBVAL(INTERVAL), 0x01, DBVAL(INTERVAL)), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), - /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ - USB_ENDPOINT_DESCRIPTOR_INIT(VIDEO_IN_EP, 0x05, VIDEO_PACKET_SIZE, 0x01), - AUDIO_AC_DESCRIPTOR_INIT(0x02, 0x03, AUDIO_AC_SIZ, 0x00, 0x03, 0x04), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, 0x02, 0x0003), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x02, 0x01, 0x01, 0x03, 0x00, 0x00), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, 0x02), - AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x02, 0x0003), - AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x05, 0x04, 0x01, 0x03, 0x00, 0x00), - AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_OUTTERM_SPEAKER, 0x05), - AUDIO_AS_DESCRIPTOR_INIT(0x03, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, - EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), - AUDIO_AS_DESCRIPTOR_INIT(0x04, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, - EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)), - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x05, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'A', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '4', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif static const uint8_t hid_keyboard_report_desc[HID_KEYBOARD_REPORT_DESC_SIZE] = { 0x05, 0x01, // USAGE_PAGE (Generic Desktop) @@ -469,11 +307,11 @@ void usbd_audio_open(uint8_t busid, uint8_t intf) audio_rx_flag = 1; /* setup first out ep read transfer */ usbd_ep_start_read(busid, AUDIO_OUT_EP, audio_read_buffer, AUDIO_OUT_PACKET); - printf("OPEN1\r\n"); + USB_LOG_RAW("OPEN1\r\n"); } else if (intf == 4) { audio_tx_flag = 1; audio_iso_tx_busy = false; - printf("OPEN2\r\n"); + USB_LOG_RAW("OPEN2\r\n"); } } @@ -481,11 +319,11 @@ void usbd_audio_close(uint8_t busid, uint8_t intf) { if (intf == 3) { audio_rx_flag = 0; - printf("CLOSE1\r\n"); + USB_LOG_RAW("CLOSE1\r\n"); } else if (intf == 4) { audio_tx_flag = 0; audio_iso_tx_busy = false; - printf("CLOSE2\r\n"); + USB_LOG_RAW("CLOSE2\r\n"); } } @@ -541,11 +379,8 @@ struct audio_entity_info audio_entity_table[] = { void composite_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &video_audio_hid_descriptor); -#else - usbd_desc_register(busid, video_audio_hid_descriptor); -#endif + usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf1, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_endpoint(busid, &video_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/video_static_h264_template.c b/components/drivers/usb/cherryusb/demo/video_static_h264_template.c index 7337f5f7ed..a45566f6c4 100644 --- a/components/drivers/usb/cherryusb/demo/video_static_h264_template.c +++ b/components/drivers/usb/cherryusb/demo/video_static_h264_template.c @@ -48,7 +48,6 @@ #define USBD_MAX_POWER 100 #define USBD_LANGID_STRING 1033 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01) }; @@ -118,94 +117,6 @@ const struct usb_descriptor video_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t video_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - //VIDEO_VC_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VC_NOEP_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), - VIDEO_VS_INPUT_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 0x00), - VIDEO_VS_FORMAT_H264_DESCRIPTOR_INIT(0x01, 0x01), - VIDEO_VS_FRAME_H264_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, DBVAL(INTERVAL), 0x01, DBVAL(INTERVAL)), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), - /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ - USB_ENDPOINT_DESCRIPTOR_INIT(VIDEO_IN_EP, 0x05, VIDEO_PACKET_SIZE, 0x01), - - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'V', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif volatile bool tx_flag = 0; volatile bool iso_tx_busy = false; @@ -272,11 +183,8 @@ struct usbd_interface intf1; void video_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &video_descriptor); -#else - usbd_desc_register(busid, video_descriptor); -#endif + usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf1, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_endpoint(busid, &video_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c b/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c index 3fc923f8d8..0f1bcef6ef 100644 --- a/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c +++ b/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c @@ -48,7 +48,6 @@ #define USBD_MAX_POWER 100 #define USBD_LANGID_STRING 1033 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01) }; @@ -118,94 +117,6 @@ const struct usb_descriptor video_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t video_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - //VIDEO_VC_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VC_NOEP_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), - VIDEO_VS_INPUT_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 0x00), - VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(0x01, 0x01), - VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, MAX_FRAME_SIZE, DBVAL(INTERVAL), 0x01, DBVAL(INTERVAL)), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), - /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ - USB_ENDPOINT_DESCRIPTOR_INIT(VIDEO_IN_EP, 0x05, VIDEO_PACKET_SIZE, 0x01), - - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'V', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif volatile bool tx_flag = 0; volatile bool iso_tx_busy = false; @@ -272,11 +183,8 @@ struct usbd_interface intf1; void video_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &video_descriptor); -#else - usbd_desc_register(busid, video_descriptor); -#endif + usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf1, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_endpoint(busid, &video_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c b/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c index 7c7d178992..1d51d8dbbc 100644 --- a/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c +++ b/components/drivers/usb/cherryusb/demo/video_static_yuyv_template.c @@ -49,7 +49,6 @@ #define USBD_MAX_POWER 100 #define USBD_LANGID_STRING 1033 -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01) }; @@ -121,95 +120,6 @@ const struct usb_descriptor video_descriptor = { .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback }; -#else -const uint8_t video_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - //VIDEO_VC_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VC_NOEP_DESCRIPTOR_INIT(0x00, VIDEO_INT_EP, 0x0100, VIDEO_VC_TERMINAL_LEN, 48000000, 0x02), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), - VIDEO_VS_INPUT_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 0x00), - VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_INIT(0x01, 0x01, VIDEO_GUID_YUY2), - VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, MAX_FRAME_SIZE, DBVAL(INTERVAL), 0x01, DBVAL(INTERVAL)), - VIDEO_VS_COLOR_MATCHING_DESCRIPTOR_INIT(), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), - /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ - USB_ENDPOINT_DESCRIPTOR_INIT(VIDEO_IN_EP, 0x05, VIDEO_PACKET_SIZE, 0x01), - - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x26, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'U', 0x00, /* wcChar10 */ - 'V', 0x00, /* wcChar11 */ - 'C', 0x00, /* wcChar12 */ - ' ', 0x00, /* wcChar13 */ - 'D', 0x00, /* wcChar14 */ - 'E', 0x00, /* wcChar15 */ - 'M', 0x00, /* wcChar16 */ - 'O', 0x00, /* wcChar17 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif volatile bool tx_flag = 0; volatile bool iso_tx_busy = false; @@ -276,11 +186,8 @@ struct usbd_interface intf1; void video_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &video_descriptor); -#else - usbd_desc_register(busid, video_descriptor); -#endif + usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_interface(busid, usbd_video_init_intf(busid, &intf1, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); usbd_add_endpoint(busid, &video_in_ep); diff --git a/components/drivers/usb/cherryusb/demo/webusb_hid_template.c b/components/drivers/usb/cherryusb/demo/webusb_hid_template.c index 1019e0541c..ffb2498b81 100644 --- a/components/drivers/usb/cherryusb/demo/webusb_hid_template.c +++ b/components/drivers/usb/cherryusb/demo/webusb_hid_template.c @@ -6,76 +6,17 @@ #include "usbd_core.h" #include "usbd_hid.h" -#define USBD_VID 0xffff -#define USBD_PID 0xffff -#define USBD_MAX_POWER 100 -#define USBD_LANGID_STRING 1033 - -#define HID_INT_EP 0x81 -#define HID_INT_EP_SIZE 8 -#define HID_INT_EP_INTERVAL 10 - -#define USB_HID_CONFIG_DESC_SIZ (34 + 9) -#define HID_KEYBOARD_REPORT_DESC_SIZE 63 - -#define USBD_WEBUSB_VENDOR_CODE (0x22) -#define USBD_WINUSB_VENDOR_CODE (0x21) +#define WEBUSB_VENDOR_CODE (0x22) +#define WINUSB_VENDOR_CODE (0x21) -#define USBD_WINUSB_DESC_SET_LEN (0xB2) #define URL_DESCRIPTOR_LENGTH (3 + 36) -#define USBD_WEBUSB_INTF_NUM 0x01 +#define WEBUSB_INTF_NUM 0x01 #define WEBUSB_URL_STRINGS \ 'g', 'i', 't', 'h', 'u', 'b', '.', 'c', 'o', 'm', '/', \ 'c', 'h', 'e', 'r', 'r', 'y', '-', 'e', 'm', 'b', 'e', 'd', 'd', 'e', 'd', '/', 'C', 'h', 'e', 'r', 'r', 'y', 'U', 'S', 'B', -const uint8_t USBD_WinUSBDescriptorSetDescriptor[USBD_WINUSB_DESC_SET_LEN] = { - // Microsoft OS 2.0 描述符集标头 - 0x0A, 0x00, // Descriptor size (10 bytes) - 0x00, 0x00, // MS OS 2.0 descriptor set header - 0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000) - USBD_WINUSB_DESC_SET_LEN, 0x00, // Size, MS OS 2.0 descriptor set - - // Microsoft OS 2.0 配置子集标头 - 0x08, 0x00, // wLength - 0x01, 0x00, // wDescriptorType - 0x00, // 适用于配置 1 - 0x00, // bReserved - 0XA8, 0X00, // Size, MS OS 2.0 configuration subset - - // Microsoft OS 2.0 功能子集头 - 0x08, 0x00, // Descriptor size (8 bytes) - 0x02, 0x00, // MS OS 2.0 function subset header - USBD_WEBUSB_INTF_NUM, // bFirstInterface - 0x00, // 必须设置为 0 - 0xA0, 0x00, - - // Microsoft OS 2.0 兼容 ID 描述符 - // 兼容 ID 描述符告诉 Windows 此设备与 WinUSB 驱动程序兼容 - 0x14, 0x00, // wLength 20 - 0x03, 0x00, // MS_OS_20_FEATURE_COMPATIBLE_ID - 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - // Microsoft OS 2.0 注册表属性描述符 - // 注册表属性分配设备接口 GUID - 0x84, 0x00, //wLength: 132 - 0x04, 0x00, // wDescriptorType: MS_OS_20_FEATURE_REG_PROPERTY: 0x04 (Table 9) - 0x07, 0x00, //wPropertyDataType: REG_MULTI_SZ (Table 15) - 0x2a, 0x00, //wPropertyNameLength: - //bPropertyName: “DeviceInterfaceGUID” - 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, - 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, - 0x00, 0x00, - 0x50, 0x00, // wPropertyDataLength - //bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. - '{', 0x00, '9', 0x00, 'd', 0x00, '7', 0x00, 'd', 0x00, 'e', 0x00, 'b', 0x00, 'b', 0x00, 'c', 0x00, '-', 0x00, - 'c', 0x00, '8', 0x00, '5', 0x00, 'd', 0x00, '-', 0x00, '1', 0x00, '1', 0x00, 'd', 0x00, '1', 0x00, '-', 0x00, - '9', 0x00, 'e', 0x00, 'b', 0x00, '4', 0x00, '-', 0x00, '0', 0x00, '0', 0x00, '6', 0x00, '0', 0x00, '0', 0x00, - '8', 0x00, 'c', 0x00, '3', 0x00, 'a', 0x00, '1', 0x00, '9', 0x00, 'a', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00 -}; - const uint8_t USBD_WebUSBURLDescriptor[URL_DESCRIPTOR_LENGTH] = { URL_DESCRIPTOR_LENGTH, WEBUSB_URL_TYPE, @@ -83,113 +24,54 @@ const uint8_t USBD_WebUSBURLDescriptor[URL_DESCRIPTOR_LENGTH] = { WEBUSB_URL_STRINGS }; -#define USBD_BOS_WTOTALLENGTH 0x39 - -#define LANDING_PAGE 0x01 -uint8_t USBD_BinaryObjectStoreDescriptor[USBD_BOS_WTOTALLENGTH] = { - // BOS描述符 - 0x05, // bLength 固长为5 - 0x0F, // bDescriptorType 固定为15 - USBD_BOS_WTOTALLENGTH, 0x00, // wTotalLength BOS描述符的总大小 - 0x02, // bNumDeviceCaps BOS描述符中独立设备功能特性描述符的数量 - - // WebUSB 平台功能描述符 - 0x18, // Descriptor size (24 bytes) - 0x10, // Descriptor type (Device Capability) 设备功能描述符 - 0x05, // Capability type (Platform) 平台描述符 - 0x00, // Reserved - - // WebUSB Platform Capability ID (3408b638-09a9-47a0-8bfd-a0768815b665) - // 平台功能 UUID 将此标识为WebUSB 平台功能描述符，它提供有关设备的基本信息 - 0x38, 0xB6, 0x08, 0x34, - 0xA9, 0x09, - 0xA0, 0x47, - 0x8B, 0xFD, - 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65, - - 0x00, 0x01, // WebUSB version 1.0 - USBD_WEBUSB_VENDOR_CODE, // Vendor-assigned WebUSB request code - LANDING_PAGE, // Landing page - - // Microsoft 平台功能描述符 - // 标头 - 0x1C, // Descriptor size (28 bytes) - 0x10, // Descriptor type (Device Capability) - 0x05, // Capability type (Platform) - 0x00, // Reserved - - 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ - 0x89, 0x45, 0xC7, 0x4C, - 0x9C, 0xD2, 0x65, 0x9D, - 0x9E, 0x64, 0x8A, 0x9F, - - // 描述符集信息结构 - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 * dwWindowsVersion 最低兼容 Windows 版本 */ - - USBD_WINUSB_DESC_SET_LEN, 0X00, /* wDescriptorSetTotalLength */ - - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0X00 /* bAltEnumCode */ +const uint8_t WINUSB_WCIDDescriptor[] = { + USB_MSOSV2_COMP_ID_SET_HEADER_DESCRIPTOR_INIT(10 + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_LEN), + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT(WEBUSB_INTF_NUM), +}; + +__ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { + USB_BOS_HEADER_DESCRIPTOR_INIT(5 + USB_BOS_CAP_PLATFORM_WEBUSB_DESCRIPTOR_LEN + USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_LEN, 2), + USB_BOS_CAP_PLATFORM_WEBUSB_DESCRIPTOR_INIT(WEBUSB_VENDOR_CODE, 0x01), + USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_INIT(WINUSB_VENDOR_CODE, sizeof(WINUSB_WCIDDescriptor)), }; struct usb_webusb_descriptor webusb_url_desc = { - .vendor_code = USBD_WEBUSB_VENDOR_CODE, + .vendor_code = WEBUSB_VENDOR_CODE, .string = USBD_WebUSBURLDescriptor, .string_len = URL_DESCRIPTOR_LENGTH }; struct usb_msosv2_descriptor msosv2_desc = { - .vendor_code = USBD_WINUSB_VENDOR_CODE, - .compat_id = USBD_WinUSBDescriptorSetDescriptor, - .compat_id_len = USBD_WINUSB_DESC_SET_LEN, + .vendor_code = WINUSB_VENDOR_CODE, + .compat_id = WINUSB_WCIDDescriptor, + .compat_id_len = sizeof(WINUSB_WCIDDescriptor), }; struct usb_bos_descriptor bos_desc = { .string = USBD_BinaryObjectStoreDescriptor, - .string_len = USBD_BOS_WTOTALLENGTH + .string_len = sizeof(USBD_BinaryObjectStoreDescriptor) }; -#ifdef CONFIG_USBDEV_ADVANCE_DESC +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define HID_INT_EP 0x81 +#define HID_INT_EP_SIZE 8 +#define HID_INT_EP_INTERVAL 10 + +#define USB_CONFIG_SIZE (34 + 9) +#define HID_KEYBOARD_REPORT_DESC_SIZE 63 + static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01) }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ - USB_INTERFACE_DESCRIPTOR_INIT(USBD_WEBUSB_INTF_NUM, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00) + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + HID_KEYBOARD_DESCRIPTOR_INIT(0x00, 0x01, HID_KEYBOARD_REPORT_DESC_SIZE, HID_INT_EP, HID_INT_EP_SIZE, HID_INT_EP_INTERVAL), + USB_INTERFACE_DESCRIPTOR_INIT(WEBUSB_INTF_NUM, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00) }; static const uint8_t device_quality_descriptor[] = { @@ -247,121 +129,6 @@ const struct usb_descriptor webusb_hid_descriptor = { .webusb_url_descriptor = &webusb_url_desc, .bos_descriptor = &bos_desc }; -#else -static const uint8_t webusb_hid_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* 34 */ - USB_INTERFACE_DESCRIPTOR_INIT(USBD_WEBUSB_INTF_NUM, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00), - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x2C, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'W', 0x00, /* wcChar10 */ - 'E', 0x00, /* wcChar11 */ - 'B', 0x00, /* wcChar12 */ - 'U', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - 'B', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - 'D', 0x00, /* wcChar17 */ - 'E', 0x00, /* wcChar18 */ - 'M', 0x00, /* wcChar19 */ - 'O', 0x00, /* wcChar20 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif /* USB HID device Configuration Descriptor */ static uint8_t hid_desc[9] __ALIGN_END = { @@ -458,16 +225,8 @@ static struct usbd_interface intf0; void webusb_hid_keyboard_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC usbd_desc_register(busid, &webusb_hid_descriptor); -#else - usbd_desc_register(busid, webusb_hid_descriptor); -#endif -#ifndef CONFIG_USBDEV_ADVANCE_DESC - usbd_bos_desc_register(busid, &bos_desc); - usbd_msosv2_desc_register(busid, &msosv2_desc); - usbd_webusb_desc_register(busid, &webusb_url_desc); -#endif + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_keyboard_report_desc, HID_KEYBOARD_REPORT_DESC_SIZE)); usbd_add_endpoint(busid, &hid_in_ep); @@ -480,7 +239,7 @@ void hid_keyboard_test(uint8_t busid) { const uint8_t sendbuffer[8] = { 0x00, 0x00, HID_KBD_USAGE_A, 0x00, 0x00, 0x00, 0x00, 0x00 }; - if(usb_device_is_configured(busid) == false) { + if (usb_device_is_configured(busid) == false) { return; } diff --git a/components/drivers/usb/cherryusb/demo/winusb1.0_template.c b/components/drivers/usb/cherryusb/demo/winusb1.0_template.c index c8fd406a25..f203f2109e 100644 --- a/components/drivers/usb/cherryusb/demo/winusb1.0_template.c +++ b/components/drivers/usb/cherryusb/demo/winusb1.0_template.c @@ -4,161 +4,106 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "usbd_core.h" -#include "usbd_cdc_acm.h" -#define WCID_VENDOR_CODE 0x17 +#define WINUSB_VENDOR_CODE 0x17 -#define DOUBLE_WINUSB 0 +#define WINUSB_NUM 1 -__ALIGN_BEGIN const uint8_t WCID_StringDescriptor_MSOS[18] __ALIGN_END = { - /////////////////////////////////////// - /// MS OS string descriptor - /////////////////////////////////////// - 0x12, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - /* MSFT100 */ - 'M', 0x00, 'S', 0x00, 'F', 0x00, 'T', 0x00, /* wcChar_7 */ - '1', 0x00, '0', 0x00, '0', 0x00, /* wcChar_7 */ - WCID_VENDOR_CODE, /* bVendorCode */ - 0x00, /* bReserved */ +const uint8_t WCID_StringDescriptor_MSOS[18] = { + USB_MSOSV1_STRING_DESCRIPTOR_INIT(WINUSB_VENDOR_CODE) }; -#if DOUBLE_WINUSB == 0 -__ALIGN_BEGIN const uint8_t WINUSB_WCIDDescriptor[40] __ALIGN_END = { +const uint8_t WINUSB_WCIDDescriptor[] = { + USB_MSOSV1_COMP_ID_HEADER_DESCRIPTOR_INIT(WINUSB_NUM), + USB_MSOSV1_COMP_ID_FUNCTION_WINUSB_DESCRIPTOR_INIT(0), +#if WINUSB_NUM == 2 + USB_MSOSV1_COMP_ID_FUNCTION_WINUSB_DESCRIPTOR_INIT(1), +#endif +}; + +const uint8_t WINUSB_IF0_WCIDProperties[142] = { /////////////////////////////////////// - /// WCID descriptor + /// WCID property descriptor /////////////////////////////////////// - 0x28, 0x00, 0x00, 0x00, /* dwLength */ - 0x00, 0x01, /* bcdVersion */ - 0x04, 0x00, /* wIndex */ - 0x01, /* bCount */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_7 */ + 0x8e, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x05, 0x00, /* wIndex */ + 0x01, 0x00, /* wCount */ /////////////////////////////////////// - /// WCID function descriptor + /// registry propter descriptor /////////////////////////////////////// - 0x00, /* bFirstInterfaceNumber */ - 0x01, /* bReserved */ - /* WINUSB */ - 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8 */ - /* */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ + 0x84, 0x00, 0x00, 0x00, /* dwSize */ + 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ + 0x28, 0x00, /* wPropertyNameLength */ + /* DeviceInterfaceGUID */ + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ + 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ + 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ + 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ + 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ + 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ + /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ + '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ + 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ + '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ + '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ + '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ + 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ + '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ + 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ + 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ + '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ }; -#else -__ALIGN_BEGIN const uint8_t WINUSB_WCIDDescriptor[64] __ALIGN_END = { - /////////////////////////////////////// - /// WCID descriptor - /////////////////////////////////////// - 0x40, 0x00, 0x00, 0x00, /* dwLength */ - 0x00, 0x01, /* bcdVersion */ - 0x04, 0x00, /* wIndex */ - 0x02, /* bCount */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_7 */ +#if WINUSB_NUM == 2 +#define WINUSB_IF1_WCID_PROPERTIES_SIZE (142) +const uint8_t WINUSB_IF1_WCIDProperties[142] = { /////////////////////////////////////// - /// WCID function descriptor + /// WCID property descriptor /////////////////////////////////////// - 0x00, /* bFirstInterfaceNumber */ - 0x01, /* bReserved */ - /* WINUSB */ - 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8 */ - /* */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ + 0x8e, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x05, 0x00, /* wIndex */ + 0x01, 0x00, /* wCount */ /////////////////////////////////////// - /// WCID function descriptor + /// registry propter descriptor /////////////////////////////////////// - 0x01, /* bFirstInterfaceNumber */ - 0x01, /* bReserved */ - /* WINUSB */ - 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8 */ - /* */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ + 0x84, 0x00, 0x00, 0x00, /* dwSize */ + 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ + 0x28, 0x00, /* wPropertyNameLength */ + /* DeviceInterfaceGUID */ + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ + 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ + 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ + 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ + 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ + 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ + /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ + '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ + 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ + '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ + '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ + '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ + 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ + '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ + 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ + 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ + '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ }; #endif -__ALIGN_BEGIN const uint8_t WINUSB_IF0_WCIDProperties [142] __ALIGN_END = { - /////////////////////////////////////// - /// WCID property descriptor - /////////////////////////////////////// - 0x8e, 0x00, 0x00, 0x00, /* dwLength */ - 0x00, 0x01, /* bcdVersion */ - 0x05, 0x00, /* wIndex */ - 0x01, 0x00, /* wCount */ - - /////////////////////////////////////// - /// registry propter descriptor - /////////////////////////////////////// - 0x84, 0x00, 0x00, 0x00, /* dwSize */ - 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ - 0x28, 0x00, /* wPropertyNameLength */ - /* DeviceInterfaceGUID */ - 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ - 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ - 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ - 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ - 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ - 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ - /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ - '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ - 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ - '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ - '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ - '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ - 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ - '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ - 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ - 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ - '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ -}; -#define WINUSB_IF1_WCID_PROPERTIES_SIZE (142) -__ALIGN_BEGIN const uint8_t WINUSB_IF1_WCIDProperties [142] __ALIGN_END = { - /////////////////////////////////////// - /// WCID property descriptor - /////////////////////////////////////// - 0x8e, 0x00, 0x00, 0x00, /* dwLength */ - 0x00, 0x01, /* bcdVersion */ - 0x05, 0x00, /* wIndex */ - 0x01, 0x00, /* wCount */ - - /////////////////////////////////////// - /// registry propter descriptor - /////////////////////////////////////// - 0x84, 0x00, 0x00, 0x00, /* dwSize */ - 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ - 0x28, 0x00, /* wPropertyNameLength */ - /* DeviceInterfaceGUID */ - 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ - 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ - 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ - 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ - 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ - 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ - /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ - '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ - 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ - '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ - '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ - '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ - 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ - '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ - 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ - 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ - '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ -}; const uint8_t *WINUSB_IFx_WCIDProperties[] = { WINUSB_IF0_WCIDProperties, -#if DOUBLE_WINUSB == 1 +#if WINUSB_NUM == 2 WINUSB_IF1_WCIDProperties, #endif }; struct usb_msosv1_descriptor msosv1_desc = { .string = WCID_StringDescriptor_MSOS, - .vendor_code = WCID_VENDOR_CODE, + .vendor_code = WINUSB_VENDOR_CODE, .compat_id = WINUSB_WCIDDescriptor, .comp_id_property = WINUSB_IFx_WCIDProperties, }; @@ -166,20 +111,20 @@ struct usb_msosv1_descriptor msosv1_desc = { #define WINUSB_IN_EP 0x81 #define WINUSB_OUT_EP 0x02 -#define USBD_VID 0xefff +#define USBD_VID 0xFFFE #define USBD_PID 0xffff #define USBD_MAX_POWER 100 #define USBD_LANGID_STRING 1033 -#if DOUBLE_WINUSB == 0 +#if WINUSB_NUM == 1 #define USB_CONFIG_SIZE (9 + 9 + 7 + 7) -#define INTF_NUM 1 +#define INTF_NUM 1 #else #define WINUSB_IN_EP2 0x83 #define WINUSB_OUT_EP2 0x04 #define USB_CONFIG_SIZE (9 + 9 + 7 + 7 + 9 + 7 + 7) -#define INTF_NUM 2 +#define INTF_NUM 2 #endif #ifdef CONFIG_USB_HS @@ -188,7 +133,6 @@ struct usb_msosv1_descriptor msosv1_desc = { #define WINUSB_EP_MPS 64 #endif -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01) }; @@ -198,7 +142,7 @@ static const uint8_t config_descriptor[] = { USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xff, 0xff, 0x00, 0x04), USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, 0x02, WINUSB_EP_MPS, 0x00), USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, 0x02, WINUSB_EP_MPS, 0x00), -#if DOUBLE_WINUSB == 1 +#if WINUSB_NUM == 2 USB_INTERFACE_DESCRIPTOR_INIT(0x01, 0x00, 0x02, 0xff, 0xff, 0x00, 0x05), USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP2, 0x02, WINUSB_EP_MPS, 0x00), USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP2, 0x02, WINUSB_EP_MPS, 0x00), @@ -253,158 +197,13 @@ static const char *string_descriptor_callback(uint8_t speed, uint8_t index) return string_descriptors[index]; } -const struct usb_descriptor winusb_descriptor = { +const struct usb_descriptor winusbv1_descriptor = { .device_descriptor_callback = device_descriptor_callback, .config_descriptor_callback = config_descriptor_callback, .device_quality_descriptor_callback = device_quality_descriptor_callback, .string_descriptor_callback = string_descriptor_callback, .msosv1_descriptor = &msosv1_desc }; -#else -const uint8_t winusb_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xff, 0xff, 0x00, 0x04), - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, 0x02, WINUSB_EP_MPS, 0x00), - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, 0x02, WINUSB_EP_MPS, 0x00), -#if DOUBLE_WINUSB == 1 - USB_INTERFACE_DESCRIPTOR_INIT(0x01, 0x00, 0x02, 0xff, 0xff, 0x00, 0x05), - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP2, 0x02, WINUSB_EP_MPS, 0x00), - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP2, 0x02, WINUSB_EP_MPS, 0x00), -#endif - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x2C, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'W', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'N', 0x00, /* wcChar12 */ - 'U', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - 'B', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - 'D', 0x00, /* wcChar17 */ - 'E', 0x00, /* wcChar18 */ - 'M', 0x00, /* wcChar19 */ - 'O', 0x00, /* wcChar20 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ - /////////////////////////////////////// - /// string4 descriptor - /////////////////////////////////////// - 0x30, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'W', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'N', 0x00, /* wcChar12 */ - 'U', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - 'B', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - 'D', 0x00, /* wcChar17 */ - 'E', 0x00, /* wcChar18 */ - 'M', 0x00, /* wcChar19 */ - 'O', 0x00, /* wcChar20 */ - ' ', 0x00, /* wcChar16 */ - '1', 0x00, /* wcChar21 */ - /////////////////////////////////////// - /// string5 descriptor - /////////////////////////////////////// - 0x30, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'W', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'N', 0x00, /* wcChar12 */ - 'U', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - 'B', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - 'D', 0x00, /* wcChar17 */ - 'E', 0x00, /* wcChar18 */ - 'M', 0x00, /* wcChar19 */ - 'O', 0x00, /* wcChar20 */ - ' ', 0x00, /* wcChar16 */ - '2', 0x00, /* wcChar21 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; @@ -428,7 +227,7 @@ static void usbd_event_handler(uint8_t busid, uint8_t event) ep_tx_busy_flag = false; /* setup first out ep read transfer */ usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); -#if DOUBLE_WINUSB == 1 +#if WINUSB_NUM == 2 usbd_ep_start_read(busid, WINUSB_OUT_EP2, read_buffer, 2048); #endif break; @@ -478,7 +277,7 @@ struct usbd_endpoint winusb_in_ep1 = { struct usbd_interface intf0; -#if DOUBLE_WINUSB == 1 +#if WINUSB_NUM == 2 void usbd_winusb_out2(uint8_t busid, uint8_t ep, uint32_t nbytes) { @@ -518,20 +317,14 @@ struct usbd_interface intf1; #endif -void winusb_init(uint8_t busid, uintptr_t reg_base) +void winusbv1_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC - usbd_desc_register(busid, &winusb_descriptor); -#else - usbd_desc_register(busid, winusb_descriptor); -#endif -#ifndef CONFIG_USBDEV_ADVANCE_DESC - usbd_msosv1_desc_register(busid, &msosv1_desc); -#endif + usbd_desc_register(busid, &winusbv1_descriptor); + usbd_add_interface(busid, &intf0); usbd_add_endpoint(busid, &winusb_out_ep1); usbd_add_endpoint(busid, &winusb_in_ep1); -#if DOUBLE_WINUSB == 1 +#if WINUSB_NUM == 2 usbd_add_interface(busid, &intf1); usbd_add_endpoint(busid, &winusb_out_ep2); usbd_add_endpoint(busid, &winusb_in_ep2); diff --git a/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c b/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c index 3ccafe324d..13d6eb07da 100644 --- a/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c +++ b/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c @@ -6,6 +6,29 @@ #include "usbd_core.h" #include "usbd_cdc_acm.h" +#define WINUSB_VENDOR_CODE 0x17 + +const uint8_t WINUSB_WCIDDescriptor[] = { + USB_MSOSV2_COMP_ID_SET_HEADER_DESCRIPTOR_INIT(10 + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_LEN), + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT(0x00), +}; + +__ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { + USB_BOS_HEADER_DESCRIPTOR_INIT(5 + USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_LEN, 1), + USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_INIT(WINUSB_VENDOR_CODE, sizeof(WINUSB_WCIDDescriptor)), +}; + +const struct usb_msosv2_descriptor msosv2_desc = { + .vendor_code = WINUSB_VENDOR_CODE, + .compat_id = WINUSB_WCIDDescriptor, + .compat_id_len = sizeof(WINUSB_WCIDDescriptor), +}; + +const struct usb_bos_descriptor bos_desc = { + .string = USBD_BinaryObjectStoreDescriptor, + .string_len = sizeof(USBD_BinaryObjectStoreDescriptor), +}; + #define WINUSB_IN_EP 0x81 #define WINUSB_OUT_EP 0x02 @@ -27,136 +50,6 @@ #define WINUSB_EP_MPS 64 #endif -#define USBD_WINUSB_VENDOR_CODE 0x20 - -#define USBD_WEBUSB_ENABLE 0 -#define USBD_BULK_ENABLE 1 -#define USBD_WINUSB_ENABLE 1 - -/* WinUSB Microsoft OS 2.0 descriptor sizes */ -#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 -#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 -#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 - -#define FUNCTION_SUBSET_LEN 160 -#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 - -#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN) - -__ALIGN_BEGIN const uint8_t USBD_WinUSBDescriptorSetDescriptor[] = { - WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ - WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ - WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ -#if (USBD_WEBUSB_ENABLE) - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), // wLength - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), // wDescriptorType - 0, // bFirstInterface USBD_WINUSB_IF_NUM - 0, // bReserved - WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType - 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId - 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), // wLength - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType - WBVAL(42), // wPropertyNameLength - 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, - 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, - 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, - WBVAL(80), // wPropertyDataLength - '{', 0, - '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, - '9', 0, 'C', 0, '7', 0, '7', 0, '-', 0, - '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, - '9', 0, '3', 0, '3', 0, 'B', 0, '-', - 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'A', 0, 'A', 0, '3', 0, 'B', 0, '9', 0, - '}', 0, 0, 0, 0, 0 -#endif -#if USBD_BULK_ENABLE - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ - 0, /* bFirstInterface USBD_BULK_IF_NUM*/ - 0, /* bReserved */ - WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ - 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ - 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ - WBVAL(42), /* wPropertyNameLength */ - 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, - 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, - 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, - WBVAL(80), /* wPropertyDataLength */ - '{', 0, - 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, - '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, - '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, - 'A', 0, 'A', 0, '3', 0, '6', 0, '-', - 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, - '}', 0, 0, 0, 0, 0 -#endif -}; - -#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE) - -#define USBD_WEBUSB_DESC_LEN 24 -#define USBD_WINUSB_DESC_LEN 28 - -#define USBD_BOS_WTOTALLENGTH (0x05 + \ - USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ - USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) - -__ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { - 0x05, /* bLength */ - 0x0f, /* bDescriptorType */ - WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ - USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */ -#if (USBD_WEBUSB_ENABLE) - USBD_WEBUSB_DESC_LEN, /* bLength */ - 0x10, /* bDescriptorType */ - USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ - 0x00, /* bReserved */ - 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */ - 0xA9, 0x09, 0xA0, 0x47, - 0x8B, 0xFD, 0xA0, 0x76, - 0x88, 0x15, 0xB6, 0x65, - WBVAL(0x0100), /* 1.00 */ /* bcdVersion */ - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0, /* iLandingPage */ -#endif -#if (USBD_WINUSB_ENABLE) - USBD_WINUSB_DESC_LEN, /* bLength */ - 0x10, /* bDescriptorType */ - USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ - 0x00, /* bReserved */ - 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ - 0x89, 0x45, 0xC7, 0x4C, - 0x9C, 0xD2, 0x65, 0x9D, - 0x9E, 0x64, 0x8A, 0x9F, - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ - WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0, /* bAltEnumCode */ -#endif -}; - -struct usb_msosv2_descriptor msosv2_desc = { - .vendor_code = USBD_WINUSB_VENDOR_CODE, - .compat_id = USBD_WinUSBDescriptorSetDescriptor, - .compat_id_len = USBD_WINUSB_DESC_SET_LEN, -}; - -struct usb_bos_descriptor bos_desc = { - .string = USBD_BinaryObjectStoreDescriptor, - .string_len = USBD_BOS_WTOTALLENGTH -}; - -#ifdef CONFIG_USBDEV_ADVANCE_DESC static const uint8_t device_descriptor[] = { USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) }; @@ -219,7 +112,7 @@ static const char *string_descriptor_callback(uint8_t speed, uint8_t index) return string_descriptors[index]; } -const struct usb_descriptor winusbv2_descriptor = { +const struct usb_descriptor winusbv2_cdc_descriptor = { .device_descriptor_callback = device_descriptor_callback, .config_descriptor_callback = config_descriptor_callback, .device_quality_descriptor_callback = device_quality_descriptor_callback, @@ -227,90 +120,6 @@ const struct usb_descriptor winusbv2_descriptor = { .msosv2_descriptor = &msosv2_desc, .bos_descriptor = &bos_desc }; -#else -const uint8_t winusbv2_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - /* Configuration 0 */ - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /* Interface 0 */ - USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), - /* Endpoint OUT 2 */ - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), - /* Endpoint IN 1 */ - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), - CDC_ACM_DESCRIPTOR_INIT(0x01, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, WINUSB_EP_MPS, 0x00), - /* String 0 (LANGID) */ - USB_LANGID_INIT(USBD_LANGID_STRING), - /* String 1 (Manufacturer) */ - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x2C, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'W', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'N', 0x00, /* wcChar12 */ - 'U', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - 'B', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - 'D', 0x00, /* wcChar17 */ - 'E', 0x00, /* wcChar18 */ - 'M', 0x00, /* wcChar19 */ - 'O', 0x00, /* wcChar20 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /* Device Qualifier */ - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x10, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - /* End */ - 0x00 -}; -#endif USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; @@ -418,17 +227,10 @@ struct usbd_interface winusb_intf; struct usbd_interface intf1; struct usbd_interface intf2; -void winusbv2_init(uint8_t busid, uintptr_t reg_base) +void winusbv2_cdc_init(uint8_t busid, uintptr_t reg_base) { -#ifdef CONFIG_USBDEV_ADVANCE_DESC - usbd_desc_register(busid, &winusbv2_descriptor); -#else - usbd_desc_register(busid, winusbv2_descriptor); -#endif -#ifndef CONFIG_USBDEV_ADVANCE_DESC - usbd_bos_desc_register(busid, &bos_desc); - usbd_msosv2_desc_register(busid, &msosv2_desc); -#endif + usbd_desc_register(busid, &winusbv2_cdc_descriptor); + /*!< winusb */ usbd_add_interface(busid, &winusb_intf); usbd_add_endpoint(busid, &winusb_out_ep1); diff --git a/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c b/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c deleted file mode 100644 index d0c1774afa..0000000000 --- a/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (c) 2024, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "usbd_core.h" -#include "usbd_hid.h" - -#define WINUSB_IN_EP 0x81 -#define WINUSB_OUT_EP 0x02 - -/*!< endpoint address */ -#define HID_INT_EP 0x83 -#define HID_INT_EP_SIZE 4 -#define HID_INT_EP_INTERVAL 10 - -#define USBD_VID 0xFFFE -#define USBD_PID 0xFFFF -#define USBD_MAX_POWER 500 -#define USBD_LANGID_STRING 1033 - -#define USB_CONFIG_SIZE (9 + 9 + 7 + 7 + 9 + 9 + 7) -#define INTF_NUM 2 - -/*!< config descriptor size */ -#define USB_HID_CONFIG_DESC_SIZ 34 -/*!< report descriptor size */ -#define HID_MOUSE_REPORT_DESC_SIZE 74 - -#ifdef CONFIG_USB_HS -#define WINUSB_EP_MPS 512 -#else -#define WINUSB_EP_MPS 64 -#endif - -#define USBD_WINUSB_VENDOR_CODE 0x20 - -#define USBD_WEBUSB_ENABLE 0 -#define USBD_BULK_ENABLE 1 -#define USBD_WINUSB_ENABLE 1 - -/* WinUSB Microsoft OS 2.0 descriptor sizes */ -#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 -#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 -#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 - -#define FUNCTION_SUBSET_LEN 160 -#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 - -#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN) - -__ALIGN_BEGIN const uint8_t USBD_WinUSBDescriptorSetDescriptor[] = { - WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ - WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ - WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ -#if (USBD_WEBUSB_ENABLE) - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), // wLength - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), // wDescriptorType - 0, // bFirstInterface USBD_WINUSB_IF_NUM - 0, // bReserved - WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType - 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId - 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), // wLength - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType - WBVAL(42), // wPropertyNameLength - 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, - 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, - 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, - WBVAL(80), // wPropertyDataLength - '{', 0, - '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, - '9', 0, 'C', 0, '7', 0, '7', 0, '-', 0, - '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, - '9', 0, '3', 0, '3', 0, 'B', 0, '-', - 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'A', 0, 'A', 0, '3', 0, 'B', 0, '9', 0, - '}', 0, 0, 0, 0, 0 -#endif -#if USBD_BULK_ENABLE - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ - 0, /* bFirstInterface USBD_BULK_IF_NUM*/ - 0, /* bReserved */ - WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ - 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ - 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ - WBVAL(42), /* wPropertyNameLength */ - 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, - 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, - 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, - WBVAL(80), /* wPropertyDataLength */ - '{', 0, - 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, - '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, - '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, - 'A', 0, 'A', 0, '3', 0, '6', 0, '-', - 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, - '}', 0, 0, 0, 0, 0 -#endif -}; - -#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE) - -#define USBD_WEBUSB_DESC_LEN 24 -#define USBD_WINUSB_DESC_LEN 28 - -#define USBD_BOS_WTOTALLENGTH (0x05 + \ - USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ - USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) - -__ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { - 0x05, /* bLength */ - 0x0f, /* bDescriptorType */ - WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ - USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */ -#if (USBD_WEBUSB_ENABLE) - USBD_WEBUSB_DESC_LEN, /* bLength */ - 0x10, /* bDescriptorType */ - USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ - 0x00, /* bReserved */ - 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */ - 0xA9, 0x09, 0xA0, 0x47, - 0x8B, 0xFD, 0xA0, 0x76, - 0x88, 0x15, 0xB6, 0x65, - WBVAL(0x0100), /* 1.00 */ /* bcdVersion */ - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0, /* iLandingPage */ -#endif -#if (USBD_WINUSB_ENABLE) - USBD_WINUSB_DESC_LEN, /* bLength */ - 0x10, /* bDescriptorType */ - USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ - 0x00, /* bReserved */ - 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ - 0x89, 0x45, 0xC7, 0x4C, - 0x9C, 0xD2, 0x65, 0x9D, - 0x9E, 0x64, 0x8A, 0x9F, - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ - WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0, /* bAltEnumCode */ -#endif -}; - -struct usb_msosv2_descriptor msosv2_desc = { - .vendor_code = USBD_WINUSB_VENDOR_CODE, - .compat_id = USBD_WinUSBDescriptorSetDescriptor, - .compat_id_len = USBD_WINUSB_DESC_SET_LEN, -}; - -struct usb_bos_descriptor bos_desc = { - .string = USBD_BinaryObjectStoreDescriptor, - .string_len = USBD_BOS_WTOTALLENGTH -}; - -#ifdef CONFIG_USBDEV_ADVANCE_DESC -static const uint8_t device_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) -}; - -static const uint8_t config_descriptor[] = { - /* Configuration 0 */ - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /* Interface 0 */ - USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), - /* Endpoint OUT 2 */ - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), - /* Endpoint IN 1 */ - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ -}; - -static const uint8_t device_quality_descriptor[] = { - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x10, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -}; - -static const char *string_descriptors[] = { - (const char[]){ 0x09, 0x04 }, /* Langid */ - "CherryUSB", /* Manufacturer */ - "CherryUSB WINUSB DEMO", /* Product */ - "2022123456", /* Serial Number */ -}; - -static const uint8_t *device_descriptor_callback(uint8_t speed) -{ - return device_descriptor; -} - -static const uint8_t *config_descriptor_callback(uint8_t speed) -{ - return config_descriptor; -} - -static const uint8_t *device_quality_descriptor_callback(uint8_t speed) -{ - return device_quality_descriptor; -} - -static const char *string_descriptor_callback(uint8_t speed, uint8_t index) -{ - if (index > 3) { - return NULL; - } - return string_descriptors[index]; -} - -const struct usb_descriptor winusbv2_descriptor = { - .device_descriptor_callback = device_descriptor_callback, - .config_descriptor_callback = config_descriptor_callback, - .device_quality_descriptor_callback = device_quality_descriptor_callback, - .string_descriptor_callback = string_descriptor_callback, - .msosv2_descriptor = &msosv2_desc, - .bos_descriptor = &bos_desc -}; -#else -const uint8_t winusbv2_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), - /* Configuration 0 */ - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /* Interface 0 */ - USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), - /* Endpoint OUT 2 */ - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), - /* Endpoint IN 1 */ - USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints */ - 0x03, /* bInterfaceClass: HID */ - 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ - 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ - 0, /* iInterface: Index of string descriptor */ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /* bLength: HID Descriptor size */ - HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ - 0x11, /* bcdHID: HID Class Spec release number */ - 0x01, - 0x00, /* bCountryCode: Hardware target country */ - 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ - 0x22, /* bDescriptorType */ - HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ - 0x03, /* bmAttributes: Interrupt endpoint */ - HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ - 0x00, - HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ - /* String 0 (LANGID) */ - USB_LANGID_INIT(USBD_LANGID_STRING), - /* String 1 (Manufacturer) */ - 0x14, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x2C, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'C', 0x00, /* wcChar0 */ - 'h', 0x00, /* wcChar1 */ - 'e', 0x00, /* wcChar2 */ - 'r', 0x00, /* wcChar3 */ - 'r', 0x00, /* wcChar4 */ - 'y', 0x00, /* wcChar5 */ - 'U', 0x00, /* wcChar6 */ - 'S', 0x00, /* wcChar7 */ - 'B', 0x00, /* wcChar8 */ - ' ', 0x00, /* wcChar9 */ - 'W', 0x00, /* wcChar10 */ - 'I', 0x00, /* wcChar11 */ - 'N', 0x00, /* wcChar12 */ - 'U', 0x00, /* wcChar13 */ - 'S', 0x00, /* wcChar14 */ - 'B', 0x00, /* wcChar15 */ - ' ', 0x00, /* wcChar16 */ - 'D', 0x00, /* wcChar17 */ - 'E', 0x00, /* wcChar18 */ - 'M', 0x00, /* wcChar19 */ - 'O', 0x00, /* wcChar20 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '2', 0x00, /* wcChar3 */ - '1', 0x00, /* wcChar4 */ - '2', 0x00, /* wcChar5 */ - '3', 0x00, /* wcChar6 */ - '4', 0x00, /* wcChar7 */ - '5', 0x00, /* wcChar8 */ - '6', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /* Device Qualifier */ - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x10, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x00, - 0x00, -#endif - /* End */ - 0x00 -}; -#endif - -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; -USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; - -volatile bool ep_tx_busy_flag = false; - -static void usbd_event_handler(uint8_t busid, uint8_t event) -{ - switch (event) { - case USBD_EVENT_RESET: - break; - case USBD_EVENT_CONNECTED: - break; - case USBD_EVENT_DISCONNECTED: - break; - case USBD_EVENT_RESUME: - break; - case USBD_EVENT_SUSPEND: - break; - case USBD_EVENT_CONFIGURED: - ep_tx_busy_flag = false; - /* setup first out ep read transfer */ - usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); - break; - case USBD_EVENT_SET_REMOTE_WAKEUP: - break; - case USBD_EVENT_CLR_REMOTE_WAKEUP: - break; - - default: - break; - } -} - -void usbd_winusb_out(uint8_t busid, uint8_t ep, uint32_t nbytes) -{ - USB_LOG_RAW("actual out len:%d\r\n", (unsigned int)nbytes); - // for (int i = 0; i < 100; i++) { - // printf("%02x ", read_buffer[i]); - // } - // printf("\r\n"); - usbd_ep_start_write(busid, WINUSB_IN_EP, read_buffer, nbytes); - /* setup next out ep read transfer */ - usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); -} - -void usbd_winusb_in(uint8_t busid, uint8_t ep, uint32_t nbytes) -{ - USB_LOG_RAW("actual in len:%d\r\n", (unsigned int)nbytes); - - if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { - /* send zlp */ - usbd_ep_start_write(busid, WINUSB_IN_EP, NULL, 0); - } else { - ep_tx_busy_flag = false; - } -} - -struct usbd_endpoint winusb_out_ep1 = { - .ep_addr = WINUSB_OUT_EP, - .ep_cb = usbd_winusb_out -}; - -struct usbd_endpoint winusb_in_ep1 = { - .ep_addr = WINUSB_IN_EP, - .ep_cb = usbd_winusb_in -}; - -/*!< hid mouse report descriptor */ -static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { - 0x05, 0x01, // USAGE_PAGE (Generic Desktop) - 0x09, 0x02, // USAGE (Mouse) - 0xA1, 0x01, // COLLECTION (Application) - 0x09, 0x01, // USAGE (Pointer) - - 0xA1, 0x00, // COLLECTION (Physical) - 0x05, 0x09, // USAGE_PAGE (Button) - 0x19, 0x01, // USAGE_MINIMUM (Button 1) - 0x29, 0x03, // USAGE_MAXIMUM (Button 3) - - 0x15, 0x00, // LOGICAL_MINIMUM (0) - 0x25, 0x01, // LOGICAL_MAXIMUM (1) - 0x95, 0x03, // REPORT_COUNT (3) - 0x75, 0x01, // REPORT_SIZE (1) - - 0x81, 0x02, // INPUT (Data,Var,Abs) - 0x95, 0x01, // REPORT_COUNT (1) - 0x75, 0x05, // REPORT_SIZE (5) - 0x81, 0x01, // INPUT (Cnst,Var,Abs) - - 0x05, 0x01, // USAGE_PAGE (Generic Desktop) - 0x09, 0x30, // USAGE (X) - 0x09, 0x31, // USAGE (Y) - 0x09, 0x38, - - 0x15, 0x81, // LOGICAL_MINIMUM (-127) - 0x25, 0x7F, // LOGICAL_MAXIMUM (127) - 0x75, 0x08, // REPORT_SIZE (8) - 0x95, 0x03, // REPORT_COUNT (2) - - 0x81, 0x06, // INPUT (Data,Var,Rel) - 0xC0, 0x09, - 0x3c, 0x05, - 0xff, 0x09, - - 0x01, 0x15, - 0x00, 0x25, - 0x01, 0x75, - 0x01, 0x95, - - 0x02, 0xb1, - 0x22, 0x75, - 0x06, 0x95, - 0x01, 0xb1, - - 0x01, 0xc0 // END_COLLECTION -}; - -/*!< mouse report struct */ -struct hid_mouse { - uint8_t buttons; - int8_t x; - int8_t y; - int8_t wheel; -}; - -/*!< mouse report */ -static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX struct hid_mouse mouse_cfg; - -#define HID_STATE_IDLE 0 -#define HID_STATE_BUSY 1 - -/*!< hid state ! Data can be sent only when state is idle */ -static volatile uint8_t hid_state = HID_STATE_IDLE; - -/* function ------------------------------------------------------------------*/ -static void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) -{ - hid_state = HID_STATE_IDLE; -} - -/*!< endpoint call back */ -static struct usbd_endpoint hid_in_ep = { - .ep_cb = usbd_hid_int_callback, - .ep_addr = HID_INT_EP -}; - -struct usbd_interface winusb_intf; -struct usbd_interface intf1; - -void winusbv2_init(uint8_t busid, uintptr_t reg_base) -{ -#ifdef CONFIG_USBDEV_ADVANCE_DESC - usbd_desc_register(busid, &winusbv2_descriptor); -#else - usbd_desc_register(busid, winusbv2_descriptor); -#endif -#ifndef CONFIG_USBDEV_ADVANCE_DESC - usbd_bos_desc_register(busid, &bos_desc); - usbd_msosv2_desc_register(busid, &msosv2_desc); -#endif - /*!< winusb */ - usbd_add_interface(busid, &winusb_intf); - usbd_add_endpoint(busid, &winusb_out_ep1); - usbd_add_endpoint(busid, &winusb_in_ep1); - - usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf1, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); - usbd_add_endpoint(busid, &hid_in_ep); - - usbd_initialize(busid, reg_base, usbd_event_handler); -} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/winusb2.0_template.c b/components/drivers/usb/cherryusb/demo/winusb2.0_template.c new file mode 100644 index 0000000000..0530d0d1ec --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/winusb2.0_template.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +#define WINUSB_VENDOR_CODE 0x17 + +#define WINUSB_NUM 1 + +// note that if device is composite device, you should use USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT +const uint8_t WINUSB_WCIDDescriptor[] = { +#if WINUSB_NUM == 1 + USB_MSOSV2_COMP_ID_SET_HEADER_DESCRIPTOR_INIT(10 + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_SINGLE_DESCRIPTOR_LEN), + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_SINGLE_DESCRIPTOR_INIT(), +#else + USB_MSOSV2_COMP_ID_SET_HEADER_DESCRIPTOR_INIT(10 + WINUSB_NUM * USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_LEN), + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT(0x00), + USB_MSOSV2_COMP_ID_FUNCTION_WINUSB_MULTI_DESCRIPTOR_INIT(0x01), +#endif +}; + +const uint8_t USBD_BinaryObjectStoreDescriptor[] = { + USB_BOS_HEADER_DESCRIPTOR_INIT(5 + USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_LEN, 1), + USB_BOS_CAP_PLATFORM_WINUSB_DESCRIPTOR_INIT(WINUSB_VENDOR_CODE, sizeof(WINUSB_WCIDDescriptor)), +}; + +const struct usb_msosv2_descriptor msosv2_desc = { + .vendor_code = WINUSB_VENDOR_CODE, + .compat_id = WINUSB_WCIDDescriptor, + .compat_id_len = sizeof(WINUSB_WCIDDescriptor), +}; + +const struct usb_bos_descriptor bos_desc = { + .string = USBD_BinaryObjectStoreDescriptor, + .string_len = sizeof(USBD_BinaryObjectStoreDescriptor), +}; + +#define WINUSB_IN_EP 0x81 +#define WINUSB_OUT_EP 0x02 + +#define USBD_VID 0xFFFE +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#if WINUSB_NUM == 1 +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7) +#define INTF_NUM 1 +#else +#define WINUSB_IN_EP2 0x83 +#define WINUSB_OUT_EP2 0x04 + +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7 + 9 + 7 + 7) +#define INTF_NUM 2 +#endif + +#ifdef CONFIG_USB_HS +#define WINUSB_EP_MPS 512 +#else +#define WINUSB_EP_MPS 64 +#endif + +static const uint8_t device_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01) +}; + +static const uint8_t config_descriptor[] = { + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xff, 0xff, 0x00, 0x04), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, 0x02, WINUSB_EP_MPS, 0x00), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, 0x02, WINUSB_EP_MPS, 0x00), +#if WINUSB_NUM == 2 + USB_INTERFACE_DESCRIPTOR_INIT(0x01, 0x00, 0x02, 0xff, 0xff, 0x00, 0x05), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP2, 0x02, WINUSB_EP_MPS, 0x00), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP2, 0x02, WINUSB_EP_MPS, 0x00), +#endif +}; + +static const uint8_t device_quality_descriptor[] = { + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, +}; + +static const char *string_descriptors[] = { + (const char[]){ 0x09, 0x04 }, /* Langid */ + "CherryUSB", /* Manufacturer */ + "CherryUSB WINUSB DEMO", /* Product */ + "2022123456", /* Serial Number */ + "CherryUSB WINUSB DEMO 1", /* STRING4 */ + "CherryUSB WINUSB DEMO 2", /* STRING5 */ +}; + +static const uint8_t *device_descriptor_callback(uint8_t speed) +{ + return device_descriptor; +} + +static const uint8_t *config_descriptor_callback(uint8_t speed) +{ + return config_descriptor; +} + +static const uint8_t *device_quality_descriptor_callback(uint8_t speed) +{ + return device_quality_descriptor; +} + +static const char *string_descriptor_callback(uint8_t speed, uint8_t index) +{ + if (index > 5) { + return NULL; + } + return string_descriptors[index]; +} + +const struct usb_descriptor winusbv2_descriptor = { + .device_descriptor_callback = device_descriptor_callback, + .config_descriptor_callback = config_descriptor_callback, + .device_quality_descriptor_callback = device_quality_descriptor_callback, + .string_descriptor_callback = string_descriptor_callback, + .msosv2_descriptor = &msosv2_desc, + .bos_descriptor = &bos_desc, +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); +#if WINUSB_NUM == 2 + usbd_ep_start_read(busid, WINUSB_OUT_EP2, read_buffer, 2048); +#endif + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_winusb_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", (unsigned int)nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + usbd_ep_start_write(busid, WINUSB_IN_EP, read_buffer, nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); +} + +void usbd_winusb_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", (unsigned int)nbytes); + + if ((nbytes % WINUSB_EP_MPS) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, WINUSB_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint winusb_out_ep1 = { + .ep_addr = WINUSB_OUT_EP, + .ep_cb = usbd_winusb_out +}; + +struct usbd_endpoint winusb_in_ep1 = { + .ep_addr = WINUSB_IN_EP, + .ep_cb = usbd_winusb_in +}; + +struct usbd_interface intf0; + +#if WINUSB_NUM == 2 + +void usbd_winusb_out2(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", (unsigned int)nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + usbd_ep_start_write(busid, WINUSB_IN_EP2, read_buffer, nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP2, read_buffer, 2048); +} + +void usbd_winusb_in2(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", (unsigned int)nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, WINUSB_IN_EP2, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint winusb_out_ep2 = { + .ep_addr = WINUSB_OUT_EP2, + .ep_cb = usbd_winusb_out2 +}; + +struct usbd_endpoint winusb_in_ep2 = { + .ep_addr = WINUSB_IN_EP2, + .ep_cb = usbd_winusb_in2 +}; + +struct usbd_interface intf1; + +#endif + +void winusbv2_init(uint8_t busid, uintptr_t reg_base) +{ + usbd_desc_register(busid, &winusbv2_descriptor); + + usbd_add_interface(busid, &intf0); + usbd_add_endpoint(busid, &winusb_out_ep1); + usbd_add_endpoint(busid, &winusb_in_ep1); +#if WINUSB_NUM == 2 + usbd_add_interface(busid, &intf1); + usbd_add_endpoint(busid, &winusb_out_ep2); + usbd_add_endpoint(busid, &winusb_in_ep2); +#endif + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/idf_component.yml b/components/drivers/usb/cherryusb/idf_component.yml index 9cfebea729..bcae2d659f 100644 --- a/components/drivers/usb/cherryusb/idf_component.yml +++ b/components/drivers/usb/cherryusb/idf_component.yml @@ -1,4 +1,4 @@ -version: "1.5.2" +version: "1.6.0" description: CherryUSB is a tiny and portable USB Stack (device & host) for embedded system with USB IP tags: - usb diff --git a/components/drivers/usb/cherryusb/platform/daplink/dap_main.c b/components/drivers/usb/cherryusb/platform/daplink/dap_main.c index f977cffd3d..27e0355b16 100644 --- a/components/drivers/usb/cherryusb/platform/daplink/dap_main.c +++ b/components/drivers/usb/cherryusb/platform/daplink/dap_main.c @@ -5,175 +5,313 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "dap_main.h" -#include "DAP_config.h" -#include "DAP.h" -#define USB_CONFIG_SIZE (9 + CMSIS_DAP_INTERFACE_SIZE + CDC_ACM_DESCRIPTOR_LEN + CONFIG_MSC_DESCRIPTOR_LEN) -#define INTF_NUM (2 + 1 + CONFIG_MSC_INTF_NUM) +#define CMSIS_DAP_INTERFACE_SIZE (9 + 7 + 7) +#define CUSTOM_HID_LEN (9 + 9 + 7 + 7) + +#define HIDRAW_INTERVAL 4 + +#define HID_CUSTOM_REPORT_DESC_SIZE 53 + +#define USBD_WINUSB_VENDOR_CODE 0x20 +#define USBD_WEBUSB_VENDOR_CODE 0x21 + +#define USBD_WEBUSB_ENABLE 1 +#define USBD_BULK_ENABLE 1 +#define USBD_WINUSB_ENABLE 1 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +#define FUNCTION_SUBSET_LEN 160 +#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 + +#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN) + +#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE) + +#define USBD_WEBUSB_DESC_LEN 24 +#define USBD_WINUSB_DESC_LEN 28 + +#define USBD_BOS_WTOTALLENGTH (0x05 + \ + USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ + USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) + +#define USB_CONFIG_SIZE (9 + CMSIS_DAP_INTERFACE_SIZE + CDC_ACM_DESCRIPTOR_LEN + \ + CONFIG_CHERRYDAP_USE_CUSTOM_HID * CUSTOM_HID_LEN + \ + CONFIG_CHERRYDAP_USE_MSC * MSC_DESCRIPTOR_LEN + USBD_WEBUSB_ENABLE * 9) + +#define INTF_NUM (1 + 2 + CONFIG_CHERRYDAP_USE_CUSTOM_HID + CONFIG_CHERRYDAP_USE_MSC + USBD_WEBUSB_ENABLE) + +#define MSC_INTF_NUM (3 + CONFIG_CHERRYDAP_USE_CUSTOM_HID) + +#define WEBUSB_INTF_NUM (3 + CONFIG_CHERRYDAP_USE_CUSTOM_HID + CONFIG_CHERRYDAP_USE_MSC) + +#define WEBUSB_URL_STRINGS \ + 'c', 'h', 'e', 'r', 'r', 'y', 'd', 'a', 'p', '.', 'c', 'h', 'e', 'r', 'r', 'y', '-', 'e', 'm', 'b', 'e', 'd', 'd', 'e', 'd', '.', 'o', 'r', 'g', __ALIGN_BEGIN const uint8_t USBD_WinUSBDescriptorSetDescriptor[] = { - WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ - WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ - WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ + WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ #if (USBD_WEBUSB_ENABLE) - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), // wLength - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), // wDescriptorType - 0, // bFirstInterface USBD_WINUSB_IF_NUM - 0, // bReserved - WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType - 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId - 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), // wLength - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType - WBVAL(42), // wPropertyNameLength - 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, - 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, - 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, - WBVAL(80), // wPropertyDataLength - '{', 0, - '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, - '9', 0, 'C', 0, '7', 0, '7', 0, '-', 0, - '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, - '9', 0, '3', 0, '3', 0, 'B', 0, '-', - 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'A', 0, 'A', 0, '3', 0, 'B', 0, '9', 0, - '}', 0, 0, 0, 0, 0 + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), // wLength + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), // wDescriptorType + WEBUSB_INTF_NUM, // bFirstInterface USBD_WINUSB_IF_NUM + 0, // bReserved + WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId + 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), // wLength + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType + WBVAL(42), // wPropertyNameLength + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), // wPropertyDataLength + '{', 0, + '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, + '9', 0, 'C', 0, '7', 0, '7', 0, '-', 0, + '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, + '9', 0, '3', 0, '3', 0, 'B', 0, '-', + 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'A', 0, 'A', 0, '3', 0, 'B', 0, '9', 0, + '}', 0, 0, 0, 0, 0, #endif #if USBD_BULK_ENABLE - WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ - WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ - 0, /* bFirstInterface USBD_BULK_IF_NUM*/ - 0, /* bReserved */ - WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ - WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ - 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ - 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ - WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ - WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ - WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ - WBVAL(42), /* wPropertyNameLength */ - 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, - 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, - 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, - WBVAL(80), /* wPropertyDataLength */ - '{', 0, - 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, - '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, - '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, - 'A', 0, 'A', 0, '3', 0, '6', 0, '-', - 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, - '}', 0, 0, 0, 0, 0 + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ + 0, /* bFirstInterface USBD_BULK_IF_NUM*/ + 0, /* bReserved */ + WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ + WBVAL(42), /* wPropertyNameLength */ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), /* wPropertyDataLength */ + '{', 0, + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, + '}', 0, 0, 0, 0, 0 #endif }; __ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { - 0x05, /* bLength */ - 0x0f, /* bDescriptorType */ - WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ - USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */ + 0x05, /* bLength */ + 0x0f, /* bDescriptorType */ + WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ + USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */ #if (USBD_WEBUSB_ENABLE) - USBD_WEBUSB_DESC_LEN, /* bLength */ - 0x10, /* bDescriptorType */ - USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ - 0x00, /* bReserved */ - 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */ - 0xA9, 0x09, 0xA0, 0x47, - 0x8B, 0xFD, 0xA0, 0x76, - 0x88, 0x15, 0xB6, 0x65, - WBVAL(0x0100), /* 1.00 */ /* bcdVersion */ - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0, /* iLandingPage */ + USBD_WEBUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */ + 0xA9, 0x09, 0xA0, 0x47, + 0x8B, 0xFD, 0xA0, 0x76, + 0x88, 0x15, 0xB6, 0x65, + WBVAL(0x0100), /* 1.00 */ /* bcdVersion */ + USBD_WEBUSB_VENDOR_CODE, /* bVendorCode */ + 1, /* iLandingPage */ #endif #if (USBD_WINUSB_ENABLE) - USBD_WINUSB_DESC_LEN, /* bLength */ - 0x10, /* bDescriptorType */ - USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ - 0x00, /* bReserved */ - 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ - 0x89, 0x45, 0xC7, 0x4C, - 0x9C, 0xD2, 0x65, 0x9D, - 0x9E, 0x64, 0x8A, 0x9F, - 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ - WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ - USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ - 0, /* bAltEnumCode */ + USBD_WINUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ + 0x89, 0x45, 0xC7, 0x4C, + 0x9C, 0xD2, 0x65, 0x9D, + 0x9E, 0x64, 0x8A, 0x9F, + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0, /* bAltEnumCode */ #endif }; +#define URL_DESCRIPTOR_LENGTH (3 + 29) + +const uint8_t USBD_WebUSBURLDescriptor[URL_DESCRIPTOR_LENGTH] = { + URL_DESCRIPTOR_LENGTH, + WEBUSB_URL_TYPE, + WEBUSB_URL_SCHEME_HTTPS, + WEBUSB_URL_STRINGS +}; + +// clang-format off +#define HID_DESC() \ + /************** Descriptor of Custom interface *****************/ \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + 0X03, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x02, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of Custom HID ********************/ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ \ + 0x00, /******************** Descriptor of Custom in endpoint ********************/ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(HID_PACKET_SIZE), /* wMaxPacketSize: 4 Byte max */ \ + HIDRAW_INTERVAL, /* bInterval: Polling Interval */ /******************** Descriptor of Custom out endpoint ********************/ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(HID_PACKET_SIZE), /* wMaxPacketSize: 4 Byte max */ \ + HIDRAW_INTERVAL /* bInterval: Polling Interval */ +// clang-format on + static const uint8_t device_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), }; static const uint8_t config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /* Interface 0 */ - USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), - /* Endpoint OUT 2 */ - USB_ENDPOINT_DESCRIPTOR_INIT(DAP_OUT_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), - /* Endpoint IN 1 */ - USB_ENDPOINT_DESCRIPTOR_INIT(DAP_IN_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), - CDC_ACM_DESCRIPTOR_INIT(0x01, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, DAP_PACKET_SIZE, 0x00), -#ifdef CONFIG_CHERRYDAP_USE_MSC - MSC_DESCRIPTOR_INIT(MSC_INTF_NUM, MSC_OUT_EP, MSC_IN_EP, DAP_PACKET_SIZE, 0x00), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + /* Interface 0 */ + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), + /* Endpoint OUT 2 */ + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_OUT_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), + /* Endpoint IN 1 */ + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_IN_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), + CDC_ACM_DESCRIPTOR_INIT(0x01, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, DAP_PACKET_SIZE, 0x00), +#if CONFIG_CHERRYDAP_USE_CUSTOM_HID + HID_DESC(), +#endif +#if CONFIG_CHERRYDAP_USE_MSC + MSC_DESCRIPTOR_INIT(MSC_INTF_NUM, MSC_OUT_EP, MSC_IN_EP, DAP_PACKET_SIZE, 0x00), +#endif +#if USBD_WEBUSB_ENABLE + USB_INTERFACE_DESCRIPTOR_INIT(WEBUSB_INTF_NUM, 0x00, 0x00, 0xff, 0x00, 0x00, 0x04), #endif }; static const uint8_t other_speed_config_descriptor[] = { - USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - /* Interface 0 */ - USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), - /* Endpoint OUT 2 */ - USB_ENDPOINT_DESCRIPTOR_INIT(DAP_OUT_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), - /* Endpoint IN 1 */ - USB_ENDPOINT_DESCRIPTOR_INIT(DAP_IN_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), - CDC_ACM_DESCRIPTOR_INIT(0x01, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, DAP_PACKET_SIZE, 0x00), -#ifdef CONFIG_CHERRYDAP_USE_MSC - MSC_DESCRIPTOR_INIT(MSC_INTF_NUM, MSC_OUT_EP, MSC_IN_EP, DAP_PACKET_SIZE, 0x00), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + /* Interface 0 */ + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), + /* Endpoint OUT 2 */ + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_OUT_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), + /* Endpoint IN 1 */ + USB_ENDPOINT_DESCRIPTOR_INIT(DAP_IN_EP, USB_ENDPOINT_TYPE_BULK, DAP_PACKET_SIZE, 0x00), + CDC_ACM_DESCRIPTOR_INIT(0x01, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, DAP_PACKET_SIZE, 0x00), +#if CONFIG_CHERRYDAP_USE_CUSTOM_HID + HID_DESC(), +#endif +#if CONFIG_CHERRYDAP_USE_MSC + MSC_DESCRIPTOR_INIT(0x04, MSC_OUT_EP, MSC_IN_EP, DAP_PACKET_SIZE, 0x00), +#endif +#if USBD_WEBUSB_ENABLE + USB_INTERFACE_DESCRIPTOR_INIT(WEBUSB_INTF_NUM, 0x00, 0x00, 0xff, 0x00, 0x00, 0x04), #endif }; +/*!< custom hid report descriptor */ +const uint8_t hid_custom_report_desc[HID_CUSTOM_REPORT_DESC_SIZE] = { + /* USER CODE BEGIN 0 */ + 0x06, 0x00, 0xff, /* USAGE_PAGE (Vendor Defined Page 1) */ + 0x09, 0x01, /* USAGE (Vendor Usage 1) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x85, 0x02, /* REPORT ID (0x02) */ + 0x09, 0x02, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /*LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0xff, 0x03, /* REPORT_COUNT (1023) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + /* <___________________________________________________> */ + 0x85, 0x01, /* REPORT ID (0x01) */ + 0x09, 0x03, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0xff, 0x03, /* REPORT_COUNT (1023) */ + 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */ + + /* <___________________________________________________> */ + 0x85, 0x03, /* REPORT ID (0x03) */ + 0x09, 0x04, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0xff, 0x03, /* REPORT_COUNT (1023) */ + 0xb1, 0x02, /* FEATURE (Data,Var,Abs) */ + /* USER CODE END 0 */ + 0xC0 /* END_COLLECTION */ +}; + +char serial_number_dynamic[36] = "00000000000000000123456789ABCDEF"; // Dynamic serial number + char *string_descriptors[] = { - (char[]) {0x09, 0x04}, /* Langid */ - "CherryUSB", /* Manufacturer */ - "CherryUSB CMSIS-DAP", /* Product */ - "00000000000000000123456789ABCDEF", /* Serial Number */ + (char[]){ 0x09, 0x04 }, /* Langid */ + "CherryUSB", /* Manufacturer */ + "CherryUSB CMSIS-DAP", /* Product */ + "00000000000000000123456789ABCDEF", /* Serial Number */ + "CherryUSB WebUSB", }; static const uint8_t device_quality_descriptor[] = { - USB_DEVICE_QUALIFIER_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, 0x01), + USB_DEVICE_QUALIFIER_DESCRIPTOR_INIT(USB_2_1, 0x00, 0x00, 0x00, 0x01), }; __WEAK const uint8_t *device_descriptor_callback(uint8_t speed) { - (void) speed; + (void)speed; return device_descriptor; } __WEAK const uint8_t *config_descriptor_callback(uint8_t speed) { - (void) speed; + (void)speed; return config_descriptor; } __WEAK const uint8_t *device_quality_descriptor_callback(uint8_t speed) { - (void) speed; + (void)speed; return device_quality_descriptor; } __WEAK const uint8_t *other_speed_config_descriptor_callback(uint8_t speed) { - (void) speed; + (void)speed; return other_speed_config_descriptor; } __WEAK const char *string_descriptor_callback(uint8_t speed, uint8_t index) { - (void) speed; + (void)speed; + + if (index == 3) { + return serial_number_dynamic; + } if (index >= (sizeof(string_descriptors) / sizeof(char *))) { return NULL; @@ -214,7 +352,7 @@ USB_NOCACHE_RAM_SECTION chry_ringbuffer_t g_usbrx; void usbd_event_handler(uint8_t busid, uint8_t event) { - (void) busid; + (void)busid; switch (event) { case USBD_EVENT_RESET: usbrx_idle_flag = 0; @@ -250,7 +388,7 @@ void usbd_event_handler(uint8_t busid, uint8_t event) void dap_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { - (void) busid; + (void)busid; if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) { DAP_TransferAbort = 1U; } else { @@ -262,7 +400,7 @@ void dap_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) } // Start reception of next request packet - if ((uint16_t) (USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { + if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { usbd_ep_start_read(0, DAP_OUT_EP, USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); } else { USB_RequestIdle = 1U; @@ -271,7 +409,7 @@ void dap_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) void dap_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) { - (void) busid; + (void)busid; if (USB_ResponseCountI != USB_ResponseCountO) { // Load data from response buffer to be sent back usbd_ep_start_write(0, DAP_IN_EP, USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]); @@ -287,7 +425,7 @@ void dap_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) { - (void) busid; + (void)busid; chry_ringbuffer_write(&g_usbrx, usb_tmpbuffer, nbytes); if (chry_ringbuffer_get_free(&g_usbrx) >= DAP_PACKET_SIZE) { usbd_ep_start_read(0, CDC_OUT_EP, usb_tmpbuffer, DAP_PACKET_SIZE); @@ -298,7 +436,7 @@ void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) { - (void) busid; + (void)busid; uint32_t size; uint8_t *buffer; @@ -317,52 +455,110 @@ void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) } struct usbd_endpoint dap_out_ep = { - .ep_addr = DAP_OUT_EP, - .ep_cb = dap_out_callback + .ep_addr = DAP_OUT_EP, + .ep_cb = dap_out_callback }; struct usbd_endpoint dap_in_ep = { - .ep_addr = DAP_IN_EP, - .ep_cb = dap_in_callback + .ep_addr = DAP_IN_EP, + .ep_cb = dap_in_callback }; struct usbd_endpoint cdc_out_ep = { - .ep_addr = CDC_OUT_EP, - .ep_cb = usbd_cdc_acm_bulk_out + .ep_addr = CDC_OUT_EP, + .ep_cb = usbd_cdc_acm_bulk_out }; struct usbd_endpoint cdc_in_ep = { - .ep_addr = CDC_IN_EP, - .ep_cb = usbd_cdc_acm_bulk_in + .ep_addr = CDC_IN_EP, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +#if CONFIG_CHERRYDAP_USE_CUSTOM_HID +struct usbd_endpoint hid_custom_in_ep = { + .ep_addr = HID_IN_EP, + .ep_cb = usbd_hid_custom_in_callback, +}; + +struct usbd_endpoint hid_custom_out_ep = { + .ep_addr = HID_OUT_EP, + .ep_cb = usbd_hid_custom_out_callback, }; +#endif struct usbd_interface dap_intf; struct usbd_interface intf1; struct usbd_interface intf2; -struct usbd_interface intf3; +#if CONFIG_CHERRYDAP_USE_CUSTOM_HID struct usbd_interface hid_intf; +#endif + +#if CONFIG_CHERRYDAP_USE_MSC +struct usbd_interface intf3; +#endif struct usb_msosv2_descriptor msosv2_desc = { - .vendor_code = USBD_WINUSB_VENDOR_CODE, - .compat_id = USBD_WinUSBDescriptorSetDescriptor, - .compat_id_len = USBD_WINUSB_DESC_SET_LEN, + .vendor_code = USBD_WINUSB_VENDOR_CODE, + .compat_id = USBD_WinUSBDescriptorSetDescriptor, + .compat_id_len = USBD_WINUSB_DESC_SET_LEN, }; struct usb_bos_descriptor bos_desc = { - .string = USBD_BinaryObjectStoreDescriptor, - .string_len = USBD_BOS_WTOTALLENGTH + .string = USBD_BinaryObjectStoreDescriptor, + .string_len = USBD_BOS_WTOTALLENGTH +}; + +struct usb_webusb_descriptor webusb_url_desc = { + .vendor_code = USBD_WEBUSB_VENDOR_CODE, + .string = USBD_WebUSBURLDescriptor, + .string_len = URL_DESCRIPTOR_LENGTH }; const struct usb_descriptor cmsisdap_descriptor = { - .device_descriptor_callback = device_descriptor_callback, - .config_descriptor_callback = config_descriptor_callback, - .device_quality_descriptor_callback = device_quality_descriptor_callback, - .other_speed_descriptor_callback = other_speed_config_descriptor_callback, - .string_descriptor_callback = string_descriptor_callback, - .bos_descriptor = &bos_desc, - .msosv2_descriptor = &msosv2_desc, + .device_descriptor_callback = device_descriptor_callback, + .config_descriptor_callback = config_descriptor_callback, + .device_quality_descriptor_callback = device_quality_descriptor_callback, + .other_speed_descriptor_callback = other_speed_config_descriptor_callback, + .string_descriptor_callback = string_descriptor_callback, + .bos_descriptor = &bos_desc, + .msosv2_descriptor = &msosv2_desc, + .webusb_url_descriptor = &webusb_url_desc }; +void chry_dap_init(uint8_t busid, uint32_t reg_base) +{ + chry_ringbuffer_init(&g_uartrx, uartrx_ringbuffer, CONFIG_UARTRX_RINGBUF_SIZE); + chry_ringbuffer_init(&g_usbrx, usbrx_ringbuffer, CONFIG_USBRX_RINGBUF_SIZE); + + DAP_Setup(); + + usbd_desc_register(0, &cmsisdap_descriptor); + + /*!< winusb */ + usbd_add_interface(0, &dap_intf); + usbd_add_endpoint(0, &dap_out_ep); + usbd_add_endpoint(0, &dap_in_ep); + + /*!< cdc acm */ + usbd_add_interface(0, usbd_cdc_acm_init_intf(0, &intf1)); + usbd_add_interface(0, usbd_cdc_acm_init_intf(0, &intf2)); + usbd_add_endpoint(0, &cdc_out_ep); + usbd_add_endpoint(0, &cdc_in_ep); + +#if CONFIG_CHERRYDAP_USE_CUSTOM_HID + /*!< hid */ + usbd_add_interface(0, usbd_hid_init_intf(0, &hid_intf, hid_custom_report_desc, HID_CUSTOM_REPORT_DESC_SIZE)); + hid_intf.notify_handler = hid_custom_notify_handler; + usbd_add_endpoint(0, &hid_custom_in_ep); + usbd_add_endpoint(0, &hid_custom_out_ep); +#endif + +#if CONFIG_CHERRYDAP_USE_MSC + usbd_add_interface(0, usbd_msc_init_intf(0, &intf3, MSC_OUT_EP, MSC_IN_EP)); +#endif + usbd_initialize(busid, reg_base, usbd_event_handler); +} + void chry_dap_handle(void) { uint32_t n; @@ -387,7 +583,7 @@ void chry_dap_handle(void) // Execute DAP Command (process request and prepare response) USB_RespSize[USB_ResponseIndexI] = - (uint16_t) DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]); + (uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]); // Update Request Index and Count USB_RequestIndexO++; @@ -397,7 +593,7 @@ void chry_dap_handle(void) USB_RequestCountO++; if (USB_RequestIdle) { - if ((uint16_t) (USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { + if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) { USB_RequestIdle = 0U; usbd_ep_start_read(0, DAP_OUT_EP, USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE); } @@ -427,9 +623,9 @@ void chry_dap_handle(void) void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) { - (void) busid; - if (memcmp(line_coding, (uint8_t *) &g_cdc_lincoding, sizeof(struct cdc_line_coding)) != 0) { - memcpy((uint8_t *) &g_cdc_lincoding, line_coding, sizeof(struct cdc_line_coding)); + (void)busid; + if (memcmp(line_coding, (uint8_t *)&g_cdc_lincoding, sizeof(struct cdc_line_coding)) != 0) { + memcpy((uint8_t *)&g_cdc_lincoding, line_coding, sizeof(struct cdc_line_coding)); config_uart = 1; config_uart_transfer = 0; } @@ -437,8 +633,8 @@ void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_c void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) { - (void) busid; - memcpy(line_coding, (uint8_t *) &g_cdc_lincoding, sizeof(struct cdc_line_coding)); + (void)busid; + memcpy(line_coding, (uint8_t *)&g_cdc_lincoding, sizeof(struct cdc_line_coding)); } void chry_dap_usb2uart_handle(void) @@ -450,7 +646,7 @@ void chry_dap_usb2uart_handle(void) /* disable irq here */ config_uart = 0; /* config uart here */ - chry_dap_usb2uart_uart_config_callback((struct cdc_line_coding *) &g_cdc_lincoding); + chry_dap_usb2uart_uart_config_callback((struct cdc_line_coding *)&g_cdc_lincoding); usbtx_idle_flag = 1; uarttx_idle_flag = 1; config_uart_transfer = 1; @@ -521,7 +717,7 @@ __WEAK void chry_dap_usb2uart_uart_send_bydma(uint8_t *data, uint16_t len) { } -#ifdef CONFIG_CHERRYDAP_USE_MSC +#if CONFIG_CHERRYDAP_USE_MSC #define BLOCK_SIZE 512 #define BLOCK_COUNT 10 diff --git a/components/drivers/usb/cherryusb/platform/daplink/dap_main.h b/components/drivers/usb/cherryusb/platform/daplink/dap_main.h index 082cb996e7..596f7a47e1 100644 --- a/components/drivers/usb/cherryusb/platform/daplink/dap_main.h +++ b/components/drivers/usb/cherryusb/platform/daplink/dap_main.h @@ -10,6 +10,7 @@ #include "usbd_core.h" #include "usbd_cdc.h" #include "usbd_msc.h" +#include "usbd_hid.h" #include "chry_ringbuffer.h" #include "DAP_config.h" #include "DAP.h" @@ -24,23 +25,14 @@ #define MSC_IN_EP 0x86 #define MSC_OUT_EP 0x07 +#define HID_IN_EP 0x88 +#define HID_OUT_EP 0x09 + #define USBD_VID 0x0D28 #define USBD_PID 0x0204 #define USBD_MAX_POWER 500 #define USBD_LANGID_STRING 1033 -#define CMSIS_DAP_INTERFACE_SIZE (9 + 7 + 7) - -#ifdef CONFIG_CHERRYDAP_USE_MSC -#define CONFIG_MSC_DESCRIPTOR_LEN CDC_ACM_DESCRIPTOR_LEN -#define CONFIG_MSC_INTF_NUM 1 -#define MSC_INTF_NUM (0x02 + 1) -#else -#define CONFIG_MSC_DESCRIPTOR_LEN 0 -#define CONFIG_MSC_INTF_NUM 0 -#define MSC_INTF_NUM (0x02) -#endif - #ifdef CONFIG_USB_HS #if DAP_PACKET_SIZE != 512 #error "DAP_PACKET_SIZE must be 512 in hs" @@ -51,99 +43,57 @@ #endif #endif -#define USBD_WINUSB_VENDOR_CODE 0x20 - -#define USBD_WEBUSB_ENABLE 0 -#define USBD_BULK_ENABLE 1 -#define USBD_WINUSB_ENABLE 1 - -/* WinUSB Microsoft OS 2.0 descriptor sizes */ -#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 -#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 -#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 - -#define FUNCTION_SUBSET_LEN 160 -#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 - -#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN) - -#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE) - -#define USBD_WEBUSB_DESC_LEN 24 -#define USBD_WINUSB_DESC_LEN 28 - -#define USBD_BOS_WTOTALLENGTH (0x05 + \ - USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ - USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) +#ifdef CONFIG_USB_HS +#define HID_PACKET_SIZE 1024 +#else +#define HID_PACKET_SIZE 64 +#endif #define CONFIG_UARTRX_RINGBUF_SIZE (8 * 1024) #define CONFIG_USBRX_RINGBUF_SIZE (8 * 1024) -#ifdef __cplusplus -extern "C" -{ +#ifndef CONFIG_CHERRYDAP_USE_MSC +#define CONFIG_CHERRYDAP_USE_MSC 0 #endif -extern USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t uartrx_ringbuffer[CONFIG_UARTRX_RINGBUF_SIZE]; -extern USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t usbrx_ringbuffer[CONFIG_USBRX_RINGBUF_SIZE]; -extern USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t usb_tmpbuffer[DAP_PACKET_SIZE]; +#ifndef CONFIG_CHERRYDAP_USE_CUSTOM_HID +#define CONFIG_CHERRYDAP_USE_CUSTOM_HID 0 +#endif -extern const struct usb_descriptor cmsisdap_descriptor; -extern __ALIGN_BEGIN const uint8_t USBD_WinUSBDescriptorSetDescriptor[]; -extern __ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[]; -extern char *string_descriptors[]; +#ifdef __cplusplus +extern "C" { +#endif -extern struct usbd_interface dap_intf; -extern struct usbd_interface intf1; -extern struct usbd_interface intf2; -extern struct usbd_interface intf3; -extern struct usbd_interface hid_intf; +extern char serial_number_dynamic[36]; -extern struct usbd_endpoint dap_out_ep; -extern struct usbd_endpoint dap_in_ep; -extern struct usbd_endpoint cdc_out_ep; -extern struct usbd_endpoint cdc_in_ep; +extern struct usbd_interface hid_intf; extern chry_ringbuffer_t g_uartrx; extern chry_ringbuffer_t g_usbrx; -__STATIC_INLINE void chry_dap_init(uint8_t busid, uint32_t reg_base) -{ - chry_ringbuffer_init(&g_uartrx, uartrx_ringbuffer, CONFIG_UARTRX_RINGBUF_SIZE); - chry_ringbuffer_init(&g_usbrx, usbrx_ringbuffer, CONFIG_USBRX_RINGBUF_SIZE); - - DAP_Setup(); - - usbd_desc_register(0, &cmsisdap_descriptor); - - /*!< winusb */ - usbd_add_interface(0, &dap_intf); - usbd_add_endpoint(0, &dap_out_ep); - usbd_add_endpoint(0, &dap_in_ep); - - /*!< cdc acm */ - usbd_add_interface(0, usbd_cdc_acm_init_intf(0, &intf1)); - usbd_add_interface(0, usbd_cdc_acm_init_intf(0, &intf2)); - usbd_add_endpoint(0, &cdc_out_ep); - usbd_add_endpoint(0, &cdc_in_ep); - -#ifdef CONFIG_CHERRYDAP_USE_MSC - usbd_add_interface(0, usbd_msc_init_intf(0, &intf3, MSC_OUT_EP, MSC_IN_EP)); -#endif - extern void usbd_event_handler(uint8_t busid, uint8_t event); - usbd_initialize(busid, reg_base, usbd_event_handler); -} +void chry_dap_init(uint8_t busid, uint32_t reg_base); void chry_dap_handle(void); void chry_dap_usb2uart_handle(void); -void chry_dap_usb2uart_uart_config_callback(struct cdc_line_coding *line_coding); +/* implment by user */ +extern void chry_dap_usb2uart_uart_config_callback(struct cdc_line_coding *line_coding); -void chry_dap_usb2uart_uart_send_bydma(uint8_t *data, uint16_t len); +/* implment by user */ +extern void chry_dap_usb2uart_uart_send_bydma(uint8_t *data, uint16_t len); void chry_dap_usb2uart_uart_send_complete(uint32_t size); +/* implment by user */ +extern void hid_custom_notify_handler(uint8_t busid, uint8_t event, void *arg); + +/* implment by user */ +extern void usbd_hid_custom_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes); + +/* implment by user */ +extern void usbd_hid_custom_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes); + #ifdef __cplusplus } #endif diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c b/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c index 4a5fb8c329..154d89f0b6 100644 --- a/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c +++ b/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c @@ -17,8 +17,11 @@ #endif #endif -#if defined(ARCH_ARM_CORTEX_M7) || \ - defined(SOC_HPM6000) || defined(SOC_HPM6E00) || defined(SOC_HPM6P00) || \ +#if defined(ARCH_ARM_CORTEX_M7) || \ + defined(ARCH_ARM_CORTEX_A) || \ + defined(ARCH_RISCV64) || \ + defined(SOC_HPM6200) || defined(SOC_HPM6300) || defined(SOC_HPM6700) || defined(SOC_HPM6800) || \ + defined(SOC_HPM6E00) || defined(SOC_HPM6P00) || \ defined(BSP_USING_BL61X) || defined(BSP_USING_BL808) #ifndef RT_USING_CACHE #error RT_USING_CACHE must be enabled in this chip @@ -27,6 +30,6 @@ #ifdef RT_USING_CACHE #ifndef CONFIG_USB_DCACHE_ENABLE -#warning CONFIG_USB_DCACHE_ENABLE must be enabled if you do not config nocache ram +#error CONFIG_USB_DCACHE_ENABLE must be enabled if you do not config nocache ram #endif #endif diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c b/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c index a153ed053d..8dd6116407 100644 --- a/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c +++ b/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c @@ -21,7 +21,7 @@ int usbh_init(int argc, char **argv) busid = atoi(argv[1]); reg_base = strtoll(argv[2], NULL, 16); - usbh_initialize(busid, reg_base); + usbh_initialize(busid, reg_base, NULL); return 0; } @@ -44,4 +44,10 @@ int usbh_deinit(int argc, char **argv) MSH_CMD_EXPORT(usbh_init, init usb host); MSH_CMD_EXPORT(usbh_deinit, deinit usb host); MSH_CMD_EXPORT(lsusb, ls usb devices); + +#ifdef CONFIG_USBHOST_SERIAL +#include "usbh_serial.h" +MSH_CMD_EXPORT(usbh_serial, usbh_serial test); +#endif + #endif diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usbd_serial.c b/components/drivers/usb/cherryusb/platform/rtthread/usbd_serial.c index aeb53a9bf1..2f6d484bca 100644 --- a/components/drivers/usb/cherryusb/platform/rtthread/usbd_serial.c +++ b/components/drivers/usb/cherryusb/platform/rtthread/usbd_serial.c @@ -76,9 +76,8 @@ static rt_err_t usbd_serial_open(struct rt_device *dev, rt_uint16_t oflag) serial = (struct usbd_serial *)dev; - if (!usb_device_is_configured(serial->busid)) { - USB_LOG_ERR("USB device is not configured\n"); - return -RT_EPERM; + while(!usb_device_is_configured(serial->busid)) { + rt_thread_mdelay(10); } usbd_ep_start_read(serial->busid, serial->out_ep, @@ -123,9 +122,8 @@ static rt_ssize_t usbd_serial_write(struct rt_device *dev, } align_buf = (rt_uint8_t *)buffer; -#ifdef CONFIG_USB_DCACHE_ENABLE if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { - align_buf = rt_malloc_align(size, CONFIG_USB_ALIGN_SIZE); + align_buf = rt_malloc_align(USB_ALIGN_UP(size, CONFIG_USB_ALIGN_SIZE), CONFIG_USB_ALIGN_SIZE); if (!align_buf) { USB_LOG_ERR("serial get align buf failed\n"); return 0; @@ -133,7 +131,7 @@ static rt_ssize_t usbd_serial_write(struct rt_device *dev, usb_memcpy(align_buf, buffer, size); } -#endif + usb_osal_sem_reset(serial->tx_done); usbd_ep_start_write(serial->busid, serial->in_ep, align_buf, size); ret = usb_osal_sem_take(serial->tx_done, 3000); @@ -144,11 +142,9 @@ static rt_ssize_t usbd_serial_write(struct rt_device *dev, ret = size; } -#ifdef CONFIG_USB_DCACHE_ENABLE if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { rt_free_align(align_buf); } -#endif return ret; } diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c b/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c index 1344f53926..7784666526 100644 --- a/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c +++ b/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c @@ -38,7 +38,7 @@ static rt_ssize_t rt_udisk_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_uint8_t *align_buf; align_buf = (rt_uint8_t *)buffer; -#ifdef CONFIG_USB_DCACHE_ENABLE + if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { align_buf = rt_malloc_align(size * msc_class->blocksize, CONFIG_USB_ALIGN_SIZE); if (!align_buf) { @@ -47,18 +47,18 @@ static rt_ssize_t rt_udisk_read(rt_device_t dev, rt_off_t pos, void *buffer, } } else { } -#endif + ret = usbh_msc_scsi_read10(msc_class, pos, (uint8_t *)align_buf, size); if (ret < 0) { rt_kprintf("usb mass_storage read failed\n"); return 0; } -#ifdef CONFIG_USB_DCACHE_ENABLE + if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { usb_memcpy(buffer, align_buf, size * msc_class->blocksize); rt_free_align(align_buf); } -#endif + return size; } @@ -70,7 +70,7 @@ static rt_ssize_t rt_udisk_write(rt_device_t dev, rt_off_t pos, const void *buff rt_uint8_t *align_buf; align_buf = (rt_uint8_t *)buffer; -#ifdef CONFIG_USB_DCACHE_ENABLE + if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { align_buf = rt_malloc_align(size * msc_class->blocksize, CONFIG_USB_ALIGN_SIZE); if (!align_buf) { @@ -80,17 +80,16 @@ static rt_ssize_t rt_udisk_write(rt_device_t dev, rt_off_t pos, const void *buff usb_memcpy(align_buf, buffer, size * msc_class->blocksize); } -#endif + ret = usbh_msc_scsi_write10(msc_class, pos, (uint8_t *)align_buf, size); if (ret < 0) { rt_kprintf("usb mass_storage write failed\n"); return 0; } -#ifdef CONFIG_USB_DCACHE_ENABLE + if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { rt_free_align(align_buf); } -#endif return size; } diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c b/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c index 34dc385075..292e5e3c88 100644 --- a/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c +++ b/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c @@ -25,7 +25,7 @@ #endif #ifndef LWIP_NO_RX_THREAD -#error must enable LWIP_NO_RX_THREAD, we do not use rtthread eth rx thread +#warning suggest you to enable LWIP_NO_RX_THREAD, we do not use rtthread eth rx thread #endif #ifndef LWIP_NO_TX_THREAD @@ -33,7 +33,7 @@ #endif #if LWIP_TCPIP_CORE_LOCKING_INPUT != 1 -#warning suggest you to set LWIP_TCPIP_CORE_LOCKING_INPUT to 1, usb handles eth input with own thread +#warning suggest you to set LWIP_TCPIP_CORE_LOCKING_INPUT to 1 for better performance, usb handles eth input with own thread #endif #if LWIP_TCPIP_CORE_LOCKING != 1 @@ -48,6 +48,14 @@ #error RT_LWIP_TCPTHREAD_STACKSIZE must be >= 2048 #endif +#if !defined(CONFIG_USBHOST_PLATFORM_CDC_ECM) && \ + !defined(CONFIG_USBHOST_PLATFORM_CDC_RNDIS) && \ + !defined(CONFIG_USBHOST_PLATFORM_CDC_NCM) && \ + !defined(CONFIG_USBHOST_PLATFORM_ASIX) && \ + !defined(CONFIG_USBHOST_PLATFORM_RTL8152) +#error "Please enable at least one USB Ethernet platform in usb_config.h or Kconfig" +#endif + // #define CONFIG_USBHOST_PLATFORM_CDC_ECM // #define CONFIG_USBHOST_PLATFORM_CDC_RNDIS // #define CONFIG_USBHOST_PLATFORM_CDC_NCM diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usbh_serial.c b/components/drivers/usb/cherryusb/platform/rtthread/usbh_serial.c deleted file mode 100644 index cbfbc49e4d..0000000000 --- a/components/drivers/usb/cherryusb/platform/rtthread/usbh_serial.c +++ /dev/null @@ -1,914 +0,0 @@ -/* - * Copyright (c) 2025, sakumisu - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include - -#include "usbh_core.h" -#include "usbh_cdc_acm.h" -#include "usbh_ftdi.h" -#include "usbh_cp210x.h" -#include "usbh_ch34x.h" -#include "usbh_pl2303.h" - -#define DEV_FORMAT_VENDOR "ttyUSB%d" -#define DEV_FORMAT_CDC_ACM "ttyACM%d" - -#define USBH_RX_MAX_SIZE 2048 - -#ifndef CONFIG_USBHOST_MAX_VENDOR_SERIAL_CLASS -#define CONFIG_USBHOST_MAX_VENDOR_SERIAL_CLASS (4) -#endif - -#ifndef CONFIG_USBHOST_SERIAL_RX_BUFSIZE -#define CONFIG_USBHOST_SERIAL_RX_BUFSIZE (USBH_RX_MAX_SIZE * 2) -#endif - -enum usbh_serial_type { - USBH_SERIAL_TYPE_CDC_ACM = 0, - USBH_SERIAL_TYPE_FTDI, - USBH_SERIAL_TYPE_CP210X, - USBH_SERIAL_TYPE_CH34X, - USBH_SERIAL_TYPE_PL2303, -}; - -struct usbh_serial { - struct rt_device parent; - enum usbh_serial_type type; - uint8_t minor; - char name[CONFIG_USBHOST_DEV_NAMELEN]; - struct rt_ringbuffer rx_rb; - rt_uint8_t rx_rb_buffer[CONFIG_USBHOST_SERIAL_RX_BUFSIZE]; -}; - -static uint32_t g_devinuse_vendor = 0; -static uint32_t g_devinuse_cdc_acm = 0; - -static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_usbh_serial_vendor_rx_buf[CONFIG_USBHOST_MAX_VENDOR_SERIAL_CLASS][USB_ALIGN_UP(USBH_RX_MAX_SIZE, CONFIG_USB_ALIGN_SIZE)]; -static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_usbh_serial_cdc_acm_rx_buf[CONFIG_USBHOST_MAX_CDC_ACM_CLASS][USB_ALIGN_UP(USBH_RX_MAX_SIZE, CONFIG_USB_ALIGN_SIZE)]; - -static struct usbh_serial *usbh_serial_alloc(uint8_t type) -{ - uint8_t devno; - struct usbh_serial *serial; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_VENDOR_SERIAL_CLASS; devno++) { - if ((g_devinuse_vendor & (1U << devno)) == 0) { - g_devinuse_vendor |= (1U << devno); - - serial = rt_malloc(sizeof(struct usbh_serial)); - memset(serial, 0, sizeof(struct usbh_serial)); - serial->type = type; - serial->minor = devno; - snprintf(serial->name, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT_VENDOR, serial->minor); - return serial; - } - } - return NULL; -} - -static void usbh_serial_free(struct usbh_serial *serial) -{ - uint8_t devno = serial->minor; - - if (devno < 32) { - g_devinuse_vendor &= ~(1U << devno); - } - memset(serial, 0, sizeof(struct usbh_serial)); - rt_free(serial); -} - -static struct usbh_serial *usbh_serial_cdc_acm_alloc(uint8_t type) -{ - uint8_t devno; - struct usbh_serial *serial; - - for (devno = 0; devno < CONFIG_USBHOST_MAX_CDC_ACM_CLASS; devno++) { - if ((g_devinuse_cdc_acm & (1U << devno)) == 0) { - g_devinuse_cdc_acm |= (1U << devno); - - serial = rt_malloc(sizeof(struct usbh_serial)); - memset(serial, 0, sizeof(struct usbh_serial)); - serial->type = type; - serial->minor = devno; - snprintf(serial->name, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT_CDC_ACM, serial->minor); - return serial; - } - } - return NULL; -} - -static void usbh_serial_cdc_acm_free(struct usbh_serial *serial) -{ - uint8_t devno = serial->minor; - - if (devno < 32) { - g_devinuse_cdc_acm &= ~(1U << devno); - } - memset(serial, 0, sizeof(struct usbh_serial)); - rt_free(serial); -} - -static rt_err_t usbh_serial_open(struct rt_device *dev, rt_uint16_t oflag) -{ - struct usbh_serial *serial; - - RT_ASSERT(dev != RT_NULL); - - serial = (struct usbh_serial *)dev; - - switch (serial->type) { - case USBH_SERIAL_TYPE_CDC_ACM: - break; - case USBH_SERIAL_TYPE_FTDI: - break; - case USBH_SERIAL_TYPE_CP210X: - break; - case USBH_SERIAL_TYPE_CH34X: - break; - case USBH_SERIAL_TYPE_PL2303: - break; - - default: - break; - } - - return RT_EOK; -} - -static rt_err_t usbh_serial_close(struct rt_device *dev) -{ - struct usbh_serial *serial; - - RT_ASSERT(dev != RT_NULL); - - serial = (struct usbh_serial *)dev; - - switch (serial->type) { - case USBH_SERIAL_TYPE_CDC_ACM: - break; - case USBH_SERIAL_TYPE_FTDI: - break; - case USBH_SERIAL_TYPE_CP210X: - break; - case USBH_SERIAL_TYPE_CH34X: - break; - case USBH_SERIAL_TYPE_PL2303: - break; - - default: - break; - } - - return RT_EOK; -} - -static rt_ssize_t usbh_serial_read(struct rt_device *dev, - rt_off_t pos, - void *buffer, - rt_size_t size) -{ - struct usbh_serial *serial; - - RT_ASSERT(dev != RT_NULL); - - serial = (struct usbh_serial *)dev; - - return rt_ringbuffer_get(&serial->rx_rb, (rt_uint8_t *)buffer, size); -} - -static rt_ssize_t usbh_serial_write(struct rt_device *dev, - rt_off_t pos, - const void *buffer, - rt_size_t size) -{ - struct usbh_serial *serial; - int ret = 0; - rt_uint8_t *align_buf; - - RT_ASSERT(dev != RT_NULL); - - serial = (struct usbh_serial *)dev; - - align_buf = (rt_uint8_t *)buffer; -#ifdef CONFIG_USB_DCACHE_ENABLE - if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { - align_buf = rt_malloc_align(size, CONFIG_USB_ALIGN_SIZE); - if (!align_buf) { - USB_LOG_ERR("serial get align buf failed\n"); - return 0; - } - - usb_memcpy(align_buf, buffer, size); - } -#endif - - switch (serial->type) { -#if defined(PKG_CHERRYUSB_HOST_CDC_ACM) || defined(RT_CHERRYUSB_HOST_CDC_ACM) - case USBH_SERIAL_TYPE_CDC_ACM: - ret = usbh_cdc_acm_bulk_out_transfer((struct usbh_cdc_acm *)dev->user_data, (uint8_t *)align_buf, size, RT_WAITING_FOREVER); - if (ret < 0) { - USB_LOG_ERR("usbh_cdc_acm_bulk_out_transfer failed: %d\n", ret); -#ifdef CONFIG_USB_DCACHE_ENABLE - rt_free_align(align_buf); -#endif - return 0; - } - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_FTDI) || defined(RT_CHERRYUSB_HOST_FTDI) - case USBH_SERIAL_TYPE_FTDI: - ret = usbh_ftdi_bulk_out_transfer((struct usbh_ftdi *)dev->user_data, (uint8_t *)align_buf, size, RT_WAITING_FOREVER); - if (ret < 0) { - USB_LOG_ERR("usbh_ftdi_bulk_out_transfer failed: %d\n", ret); -#ifdef CONFIG_USB_DCACHE_ENABLE - rt_free_align(align_buf); -#endif - return 0; - } - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_CH34X) || defined(RT_CHERRYUSB_HOST_CH34X) - case USBH_SERIAL_TYPE_CH34X: - ret = usbh_ch34x_bulk_out_transfer((struct usbh_ch34x *)dev->user_data, (uint8_t *)align_buf, size, RT_WAITING_FOREVER); - if (ret < 0) { - USB_LOG_ERR("usbh_ch34x_bulk_out_transfer failed: %d\n", ret); -#ifdef CONFIG_USB_DCACHE_ENABLE - rt_free_align(align_buf); -#endif - return 0; - } - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_PL2303) || defined(RT_CHERRYUSB_HOST_PL2303) - case USBH_SERIAL_TYPE_PL2303: - ret = usbh_pl2303_bulk_out_transfer((struct usbh_pl2303 *)dev->user_data, (uint8_t *)align_buf, size, RT_WAITING_FOREVER); - if (ret < 0) { - USB_LOG_ERR("usbh_pl2303_bulk_out_transfer failed: %d\n", ret); -#ifdef CONFIG_USB_DCACHE_ENABLE - rt_free_align(align_buf); -#endif - return 0; - } - break; -#endif - default: - break; - } - -#ifdef CONFIG_USB_DCACHE_ENABLE - if ((uint32_t)buffer & (CONFIG_USB_ALIGN_SIZE - 1)) { - rt_free_align(align_buf); - } -#endif - - return ret; -} - -static rt_err_t usbh_serial_control(struct rt_device *dev, - int cmd, - void *args) -{ - struct usbh_serial *serial; - struct serial_configure *config; - struct cdc_line_coding line_coding; - int ret = -RT_EINVAL; - - RT_ASSERT(dev != RT_NULL); - - serial = (struct usbh_serial *)dev; - - switch (serial->type) { -#if defined(PKG_CHERRYUSB_HOST_CDC_ACM) || defined(RT_CHERRYUSB_HOST_CDC_ACM) - case USBH_SERIAL_TYPE_CDC_ACM: - if (cmd == RT_DEVICE_CTRL_CONFIG) { - struct usbh_cdc_acm *cdc_acm_class; - cdc_acm_class = (struct usbh_cdc_acm *)dev->user_data; - - config = (struct serial_configure *)args; - - line_coding.dwDTERate = config->baud_rate; - line_coding.bDataBits = config->data_bits; - line_coding.bCharFormat = 0; // STOP_BITS_1 - line_coding.bParityType = config->parity; - - usbh_cdc_acm_set_line_coding(cdc_acm_class, &line_coding); - } - - ret = RT_EOK; - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_FTDI) || defined(RT_CHERRYUSB_HOST_FTDI) - case USBH_SERIAL_TYPE_FTDI: - if (cmd == RT_DEVICE_CTRL_CONFIG) { - struct usbh_ftdi *ftdi_class; - ftdi_class = (struct usbh_ftdi *)dev->user_data; - - config = (struct serial_configure *)args; - - line_coding.dwDTERate = config->baud_rate; - line_coding.bDataBits = config->data_bits; - line_coding.bCharFormat = 0; // STOP_BITS_1 - line_coding.bParityType = config->parity; - - usbh_ftdi_set_line_coding(ftdi_class, &line_coding); - } - - ret = RT_EOK; - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_CP210X) || defined(RT_CHERRYUSB_HOST_CP210X) - case USBH_SERIAL_TYPE_CP210X: - if (cmd == RT_DEVICE_CTRL_CONFIG) { - struct usbh_cp210x *cp210x_class; - cp210x_class = (struct usbh_cp210x *)dev->user_data; - - config = (struct serial_configure *)args; - - line_coding.dwDTERate = config->baud_rate; - line_coding.bDataBits = config->data_bits; - line_coding.bCharFormat = 0; // STOP_BITS_1 - line_coding.bParityType = config->parity; - - usbh_cp210x_set_line_coding(cp210x_class, &line_coding); - } - - ret = RT_EOK; - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_CH34X) || defined(RT_CHERRYUSB_HOST_CH34X) - case USBH_SERIAL_TYPE_CH34X: - if (cmd == RT_DEVICE_CTRL_CONFIG) { - struct usbh_ch34x *ch34x_class; - ch34x_class = (struct usbh_ch34x *)dev->user_data; - - config = (struct serial_configure *)args; - - line_coding.dwDTERate = config->baud_rate; - line_coding.bDataBits = config->data_bits; - line_coding.bCharFormat = 0; // STOP_BITS_1 - line_coding.bParityType = config->parity; - - usbh_ch34x_set_line_coding(ch34x_class, &line_coding); - } - - ret = RT_EOK; - break; -#endif -#if defined(PKG_CHERRYUSB_HOST_PL2303) || defined(RT_CHERRYUSB_HOST_PL2303) - case USBH_SERIAL_TYPE_PL2303: - if (cmd == RT_DEVICE_CTRL_CONFIG) { - struct usbh_pl2303 *pl2303_class; - pl2303_class = (struct usbh_pl2303 *)dev->user_data; - - config = (struct serial_configure *)args; - - line_coding.dwDTERate = config->baud_rate; - line_coding.bDataBits = config->data_bits; - line_coding.bCharFormat = 0; // STOP_BITS_1 - line_coding.bParityType = config->parity; - - usbh_pl2303_set_line_coding(pl2303_class, &line_coding); - } - - ret = RT_EOK; - break; -#endif - default: - break; - } - - return ret; -} - -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops usbh_serial_ops = { - NULL, - usbh_serial_open, - usbh_serial_close, - usbh_serial_read, - usbh_serial_write, - usbh_serial_control -}; -#endif - -#ifdef RT_USING_POSIX_DEVIO -#include -#include -#include -#include -#include - -#ifdef RT_USING_POSIX_TERMIOS -#include -#endif - -static rt_err_t usbh_serial_fops_rx_ind(rt_device_t dev, rt_size_t size) -{ - rt_wqueue_wakeup(&(dev->wait_queue), (void*)POLLIN); - - return RT_EOK; -} - -/* fops for serial */ -static int usbh_serial_fops_open(struct dfs_file *fd) -{ - rt_err_t ret = 0; - rt_uint16_t flags = 0; - rt_device_t device; - - device = (rt_device_t)fd->vnode->data; - RT_ASSERT(device != RT_NULL); - - switch (fd->flags & O_ACCMODE) - { - case O_RDONLY: - USB_LOG_DBG("fops open: O_RDONLY!"); - flags = RT_DEVICE_FLAG_RDONLY; - break; - case O_WRONLY: - USB_LOG_DBG("fops open: O_WRONLY!"); - flags = RT_DEVICE_FLAG_WRONLY; - break; - case O_RDWR: - USB_LOG_DBG("fops open: O_RDWR!"); - flags = RT_DEVICE_FLAG_RDWR; - break; - default: - USB_LOG_ERR("fops open: unknown mode - %d!", fd->flags & O_ACCMODE); - break; - } - - if ((fd->flags & O_ACCMODE) != O_WRONLY) - rt_device_set_rx_indicate(device, usbh_serial_fops_rx_ind); - ret = rt_device_open(device, flags); - if (ret == RT_EOK) return 0; - - return ret; -} - -static int usbh_serial_fops_close(struct dfs_file *fd) -{ - rt_device_t device; - - device = (rt_device_t)fd->vnode->data; - - rt_device_set_rx_indicate(device, RT_NULL); - rt_device_close(device); - - return 0; -} - -static int usbh_serial_fops_ioctl(struct dfs_file *fd, int cmd, void *args) -{ - rt_device_t device; - int flags = (int)(rt_base_t)args; - int mask = O_NONBLOCK | O_APPEND; - - device = (rt_device_t)fd->vnode->data; - switch (cmd) - { - case FIONREAD: - break; - case FIONWRITE: - break; - case F_SETFL: - flags &= mask; - fd->flags &= ~mask; - fd->flags |= flags; - break; - } - - return rt_device_control(device, cmd, args); -} - -static int usbh_serial_fops_read(struct dfs_file *fd, void *buf, size_t count) -{ - int size = 0; - rt_device_t device; - - device = (rt_device_t)fd->vnode->data; - - do - { - size = rt_device_read(device, -1, buf, count); - if (size <= 0) - { - if (fd->flags & O_NONBLOCK) - { - size = -EAGAIN; - break; - } - - rt_wqueue_wait(&(device->wait_queue), 0, RT_WAITING_FOREVER); - } - }while (size <= 0); - - return size; -} - -static int usbh_serial_fops_write(struct dfs_file *fd, const void *buf, size_t count) -{ - rt_device_t device; - - device = (rt_device_t)fd->vnode->data; - return rt_device_write(device, -1, buf, count); -} - -static int usbh_serial_fops_poll(struct dfs_file *fd, struct rt_pollreq *req) -{ - int mask = 0; - int flags = 0; - rt_device_t device; - struct usbh_serial *serial; - - device = (rt_device_t)fd->vnode->data; - RT_ASSERT(device != RT_NULL); - - serial = (struct usbh_serial *)device; - - /* only support POLLIN */ - flags = fd->flags & O_ACCMODE; - if (flags == O_RDONLY || flags == O_RDWR) - { - rt_base_t level; - - rt_poll_add(&(device->wait_queue), req); - - level = rt_hw_interrupt_disable(); - - if (rt_ringbuffer_data_len(&serial->rx_rb)) - mask |= POLLIN; - rt_hw_interrupt_enable(level); - } - // mask|=POLLOUT; - return mask; -} - -const static struct dfs_file_ops usbh_serial_fops = -{ - usbh_serial_fops_open, - usbh_serial_fops_close, - usbh_serial_fops_ioctl, - usbh_serial_fops_read, - usbh_serial_fops_write, - RT_NULL, /* flush */ - RT_NULL, /* lseek */ - RT_NULL, /* getdents */ - usbh_serial_fops_poll, -}; -#endif /* RT_USING_POSIX_DEVIO */ - -rt_err_t usbh_serial_register(struct usbh_serial *serial, - void *data) -{ - rt_err_t ret; - struct rt_device *device; - RT_ASSERT(serial != RT_NULL); - - device = &(serial->parent); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - -#ifdef RT_USING_DEVICE_OPS - device->ops = &usbh_serial_ops; -#else - device->init = NULL; - device->open = usbh_serial_open; - device->close = usbh_serial_close; - device->read = usbh_serial_read; - device->write = usbh_serial_write; - device->control = usbh_serial_control; -#endif - device->user_data = data; - - /* register a character device */ - ret = rt_device_register(device, serial->name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_REMOVABLE); - -#ifdef RT_USING_POSIX_DEVIO - /* set fops */ - device->fops = &usbh_serial_fops; -#endif - rt_ringbuffer_init(&serial->rx_rb, serial->rx_rb_buffer, sizeof(serial->rx_rb_buffer)); - - return ret; -} - -void usbh_serial_unregister(struct usbh_serial *serial) -{ - RT_ASSERT(serial != NULL); - - rt_device_unregister(&serial->parent); - - if (serial->type == USBH_SERIAL_TYPE_CDC_ACM) { - usbh_serial_cdc_acm_free(serial); - } else { - usbh_serial_free(serial); - } -} - -#if defined(PKG_CHERRYUSB_HOST_CDC_ACM) || defined(RT_CHERRYUSB_HOST_CDC_ACM) -void usbh_cdc_acm_callback(void *arg, int nbytes) -{ - struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)arg; - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &cdc_acm_class->bulkin_urb; - - if (nbytes > 0) { - serial = (struct usbh_serial *)cdc_acm_class->user_data; - rt_ringbuffer_put(&serial->rx_rb, g_usbh_serial_cdc_acm_rx_buf[serial->minor], nbytes); - - if (serial->parent.rx_indicate) { - serial->parent.rx_indicate(&serial->parent, nbytes); - } - - usbh_bulk_urb_fill(urb, cdc_acm_class->hport, cdc_acm_class->bulkin, g_usbh_serial_cdc_acm_rx_buf[serial->minor], sizeof(g_usbh_serial_cdc_acm_rx_buf[serial->minor]), 0, usbh_cdc_acm_callback, cdc_acm_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - } - } -} - -void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) -{ - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &cdc_acm_class->bulkin_urb; - - serial = usbh_serial_cdc_acm_alloc(USBH_SERIAL_TYPE_CDC_ACM); - cdc_acm_class->user_data = serial; - - usbh_serial_register(serial, cdc_acm_class); - - struct cdc_line_coding linecoding; - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_cdc_acm_set_line_coding(cdc_acm_class, &linecoding); - - usbh_bulk_urb_fill(urb, cdc_acm_class->hport, cdc_acm_class->bulkin, g_usbh_serial_cdc_acm_rx_buf[serial->minor], sizeof(g_usbh_serial_cdc_acm_rx_buf[serial->minor]), 0, usbh_cdc_acm_callback, cdc_acm_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - usbh_serial_unregister(serial); - return; - } -} - -void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) -{ - struct usbh_serial *serial; - - serial = (struct usbh_serial *)cdc_acm_class->user_data; - usbh_serial_unregister(serial); -} -#endif - -#if defined(PKG_CHERRYUSB_HOST_FTDI) || defined(RT_CHERRYUSB_HOST_FTDI) -void usbh_ftdi_callback(void *arg, int nbytes) -{ - struct usbh_ftdi *ftdi_class = (struct usbh_ftdi *)arg; - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &ftdi_class->bulkin_urb; - - if (nbytes >= 2) { - serial = (struct usbh_serial *)ftdi_class->user_data; - - nbytes -= 2; // Skip the first two bytes (header) - rt_ringbuffer_put(&serial->rx_rb, &g_usbh_serial_vendor_rx_buf[serial->minor][2], nbytes); - - if (serial->parent.rx_indicate && nbytes) { - serial->parent.rx_indicate(&serial->parent, nbytes); - } - - usbh_bulk_urb_fill(urb, ftdi_class->hport, ftdi_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_ftdi_callback, ftdi_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - } - } -} - -void usbh_ftdi_run(struct usbh_ftdi *ftdi_class) -{ - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &ftdi_class->bulkin_urb; - - serial = usbh_serial_alloc(USBH_SERIAL_TYPE_FTDI); - ftdi_class->user_data = serial; - - usbh_serial_register(serial, ftdi_class); - - struct cdc_line_coding linecoding; - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_ftdi_set_line_coding(ftdi_class, &linecoding); - - usbh_bulk_urb_fill(urb, ftdi_class->hport, ftdi_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_ftdi_callback, ftdi_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - usbh_serial_unregister(serial); - return; - } -} - -void usbh_ftdi_stop(struct usbh_ftdi *ftdi_class) -{ - struct usbh_serial *serial; - - serial = (struct usbh_serial *)ftdi_class->user_data; - usbh_serial_unregister(serial); -} -#endif - -#if defined(PKG_CHERRYUSB_HOST_CH34X) || defined(RT_CHERRYUSB_HOST_CH34X) -void usbh_ch34x_callback(void *arg, int nbytes) -{ - struct usbh_ch34x *ch34x_class = (struct usbh_ch34x *)arg; - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &ch34x_class->bulkin_urb; - - if (nbytes > 0) { - serial = (struct usbh_serial *)ch34x_class->user_data; - rt_ringbuffer_put(&serial->rx_rb, g_usbh_serial_vendor_rx_buf[serial->minor], nbytes); - - if (serial->parent.rx_indicate) { - serial->parent.rx_indicate(&serial->parent, nbytes); - } - - usbh_bulk_urb_fill(urb, ch34x_class->hport, ch34x_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_ch34x_callback, ch34x_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - } - } -} - -void usbh_ch34x_run(struct usbh_ch34x *ch34x_class) -{ - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &ch34x_class->bulkin_urb; - - serial = usbh_serial_alloc(USBH_SERIAL_TYPE_CH34X); - ch34x_class->user_data = serial; - - usbh_serial_register(serial, ch34x_class); - - struct cdc_line_coding linecoding; - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_ch34x_set_line_coding(ch34x_class, &linecoding); - - usbh_bulk_urb_fill(urb, ch34x_class->hport, ch34x_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_ch34x_callback, ch34x_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - usbh_serial_unregister(serial); - return; - } -} - -void usbh_ch34x_stop(struct usbh_ch34x *ch34x_class) -{ - struct usbh_serial *serial; - - serial = (struct usbh_serial *)ch34x_class->user_data; - usbh_serial_unregister(serial); -} -#endif - -#if defined(PKG_CHERRYUSB_HOST_CP210X) || defined(RT_CHERRYUSB_HOST_CP210X) -void usbh_cp210x_callback(void *arg, int nbytes) -{ - struct usbh_cp210x *cp210x_class = (struct usbh_cp210x *)arg; - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &cp210x_class->bulkin_urb; - - if (nbytes > 0) { - serial = (struct usbh_serial *)cp210x_class->user_data; - rt_ringbuffer_put(&serial->rx_rb, g_usbh_serial_vendor_rx_buf[serial->minor], nbytes); - - if (serial->parent.rx_indicate) { - serial->parent.rx_indicate(&serial->parent, nbytes); - } - - usbh_bulk_urb_fill(urb, cp210x_class->hport, cp210x_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_cp210x_callback, cp210x_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - } - } -} - -void usbh_cp210x_run(struct usbh_cp210x *cp210x_class) -{ - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &cp210x_class->bulkin_urb; - - serial = usbh_serial_alloc(USBH_SERIAL_TYPE_CP210X); - cp210x_class->user_data = serial; - - usbh_serial_register(serial, cp210x_class); - - struct cdc_line_coding linecoding; - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_cp210x_set_line_coding(cp210x_class, &linecoding); - - usbh_bulk_urb_fill(urb, cp210x_class->hport, cp210x_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_cp210x_callback, cp210x_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - usbh_serial_unregister(serial); - return; - } -} - -void usbh_cp210x_stop(struct usbh_cp210x *cp210x_class) -{ - struct usbh_serial *serial; - - serial = (struct usbh_serial *)cp210x_class->user_data; - usbh_serial_unregister(serial); -} -#endif - -#if defined(PKG_CHERRYUSB_HOST_PL2303) || defined(RT_CHERRYUSB_HOST_PL2303) -void usbh_pl2303_callback(void *arg, int nbytes) -{ - struct usbh_pl2303 *pl2303_class = (struct usbh_pl2303 *)arg; - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &pl2303_class->bulkin_urb; - - if (nbytes > 0) { - serial = (struct usbh_serial *)pl2303_class->user_data; - rt_ringbuffer_put(&serial->rx_rb, g_usbh_serial_vendor_rx_buf[serial->minor], nbytes); - - if (serial->parent.rx_indicate) { - serial->parent.rx_indicate(&serial->parent, nbytes); - } - - usbh_bulk_urb_fill(urb, pl2303_class->hport, pl2303_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_pl2303_callback, pl2303_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - } - } -} - -void usbh_pl2303_run(struct usbh_pl2303 *pl2303_class) -{ - struct usbh_serial *serial; - int ret; - struct usbh_urb *urb = &pl2303_class->bulkin_urb; - - serial = usbh_serial_alloc(USBH_SERIAL_TYPE_PL2303); - pl2303_class->user_data = serial; - - usbh_serial_register(serial, pl2303_class); - - struct cdc_line_coding linecoding; - linecoding.dwDTERate = 115200; - linecoding.bDataBits = 8; - linecoding.bParityType = 0; - linecoding.bCharFormat = 0; - usbh_pl2303_set_line_coding(pl2303_class, &linecoding); - - usbh_bulk_urb_fill(urb, pl2303_class->hport, pl2303_class->bulkin, g_usbh_serial_vendor_rx_buf[serial->minor], sizeof(g_usbh_serial_vendor_rx_buf[serial->minor]), 0, usbh_pl2303_callback, pl2303_class); - ret = usbh_submit_urb(urb); - if (ret < 0) { - USB_LOG_ERR("usbh_submit_urb failed: %d\n", ret); - usbh_serial_unregister(serial); - return; - } -} - -void usbh_pl2303_stop(struct usbh_pl2303 *pl2303_class) -{ - struct usbh_serial *serial; - - serial = (struct usbh_serial *)pl2303_class->user_data; - usbh_serial_unregister(serial); -} -#endif diff --git a/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c b/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c index 106f8af535..ddead2b9db 100644 --- a/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c +++ b/components/drivers/usb/cherryusb/port/chipidea/usb_dc_chipidea.c @@ -594,10 +594,15 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui return -2; } +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + g_chipidea_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; g_chipidea_udc[busid].in_ep[ep_idx].xfer_len = data_len; g_chipidea_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + usb_dcache_clean((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); chipidea_start_xfer(busid, ep, (uint8_t *)data, data_len); return 0; @@ -614,10 +619,15 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t return -2; } +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + g_chipidea_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; g_chipidea_udc[busid].out_ep[ep_idx].xfer_len = data_len; g_chipidea_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + usb_dcache_invalidate((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); chipidea_start_xfer(busid, ep, data, data_len); return 0; @@ -649,7 +659,7 @@ void USBD_IRQHandler(uint8_t busid) memset(g_chipidea_udc[busid].in_ep, 0, sizeof(struct chipidea_ep_state) * CONFIG_USBDEV_EP_NUM); memset(g_chipidea_udc[busid].out_ep, 0, sizeof(struct chipidea_ep_state) * CONFIG_USBDEV_EP_NUM); usbd_event_reset_handler(busid); - chipidea_bus_reset(busid, 64); + chipidea_bus_reset(busid, g_chipidea_udc[busid].in_ep[0].ep_mps); } if (int_status & intr_suspend) { @@ -712,6 +722,7 @@ void USBD_IRQHandler(uint8_t busid) if (ep_addr & 0x80) { usbd_event_ep_in_complete_handler(busid, ep_addr, transfer_len); } else { + usb_dcache_invalidate((uintptr_t)g_chipidea_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(transfer_len, CONFIG_USB_ALIGN_SIZE)); usbd_event_ep_out_complete_handler(busid, ep_addr, transfer_len); } } diff --git a/components/drivers/usb/cherryusb/port/dwc2/README.md b/components/drivers/usb/cherryusb/port/dwc2/README.md index 2861cde737..db82c6cfb2 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/README.md +++ b/components/drivers/usb/cherryusb/port/dwc2/README.md @@ -48,4 +48,8 @@ Please note that host must support dma mode. ### Nationstech -- N32H4X \ No newline at end of file +- N32H4X + +### Infineon + +- PSOC Edge E8X \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c b/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c index a5de3f29d7..31be0d55db 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c @@ -7,51 +7,6 @@ #include "usb_dwc2_reg.h" #include "usb_dwc2_param.h" -// clang-format off -#if defined ( __CC_ARM ) -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#elif defined ( __GNUC__ ) -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#endif -// clang-format on - #define USBD_BASE (g_usbdev_bus[busid].reg_base) #define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(USBD_BASE)) @@ -61,8 +16,6 @@ #define USB_OTG_OUTEP(i) ((DWC2_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE))) #define USB_OTG_FIFO(i) *(__IO uint32_t *)(USBD_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE)) -extern uint32_t SystemCoreClock; - /* Endpoint state */ struct dwc2_ep_state { uint16_t ep_mps; /* Endpoint max packet size */ @@ -328,12 +281,11 @@ static uint8_t dwc2_get_devspeed(uint8_t busid) static void dwc2_ep0_start_read_setup(uint8_t busid, uint8_t *psetup) { - USB_OTG_OUTEP(0U)->DOEPTSIZ = 0U; - USB_OTG_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USB_OTG_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); - USB_OTG_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + USB_OTG_OUTEP(0U)->DOEPTSIZ = (1U * 8U) | (1U << 19) | (1U << 29); if (g_dwc2_udc[busid].user_params.device_dma_enable) { + usb_dcache_invalidate((uintptr_t)&g_dwc2_udc[busid].setup, USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE)); + USB_OTG_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; /* EP enable */ USB_OTG_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; @@ -342,25 +294,61 @@ static void dwc2_ep0_start_read_setup(uint8_t busid, uint8_t *psetup) void dwc2_ep_write(uint8_t busid, uint8_t ep_idx, uint8_t *src, uint16_t len) { - uint32_t *pSrc = (uint32_t *)src; - uint32_t count32b, i; + uint32_t *p32; + uint8_t *p8; + uint32_t val; + uint8_t remain; + + p32 = (uint32_t *)src; + for (uint32_t i = 0U; i < (len / 4); i++) { + USB_OTG_FIFO((uint32_t)ep_idx) = *p32++; + } - count32b = ((uint32_t)len + 3U) / 4U; - for (i = 0U; i < count32b; i++) { - USB_OTG_FIFO((uint32_t)ep_idx) = __UNALIGNED_UINT32_READ(pSrc); - pSrc++; + remain = len % 4; + + if (remain) { + p8 = (uint8_t *)p32; + val = (uint32_t)(*p8++); + + if (remain > 1) { + val |= (uint32_t)((*p8++) << 8); + } + + if (remain > 2) { + val |= (uint32_t)((*p8++) << 16); + } + + USB_OTG_FIFO((uint32_t)ep_idx) = val; } } void dwc2_ep_read(uint8_t busid, uint8_t *dest, uint16_t len) { - uint32_t *pDest = (uint32_t *)dest; - uint32_t i; - uint32_t count32b = ((uint32_t)len + 3U) / 4U; + uint32_t *p32; + uint8_t *p8; + uint32_t val; + uint8_t remain; + + p32 = (uint32_t *)dest; + for (uint32_t i = 0U; i < (len / 4); i++) { + *p32++ = USB_OTG_FIFO(0U); + } + + remain = len % 4; + + if (remain) { + p8 = (uint8_t *)p32; + val = USB_OTG_FIFO(0U); + + *p8++ = (uint8_t)(val & 0xFFU); - for (i = 0U; i < count32b; i++) { - __UNALIGNED_UINT32_WRITE(pDest, USB_OTG_FIFO(0U)); - pDest++; + if (remain > 1) { + *p8++ = (uint8_t)((val >> 8) & 0xFFU); + } + + if (remain > 2) { + *p8++ = (uint8_t)((val >> 16) & 0xFFU); + } } } @@ -530,6 +518,19 @@ int usb_dc_init(uint8_t busid) /* Force Device Mode*/ dwc2_set_mode(busid, USB_OTG_MODE_DEVICE); + USB_ASSERT_MSG((USB_OTG_GLB->GRXFSIZ & 0xffff) >= g_dwc2_udc[busid].user_params.device_rx_fifo_size, + "device_rx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->GRXFSIZ & 0xffff)); + for (uint8_t i = 0; i < (g_dwc2_udc[busid].hw_params.num_dev_ep + 1); i++) { + uint16_t reset_txfifo_size; + if (i == 0) { + reset_txfifo_size = USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16 & 0xffff; + } else { + reset_txfifo_size = USB_OTG_GLB->DIEPTXF[i - 1] >> 16 & 0xffff; + } + USB_ASSERT_MSG(reset_txfifo_size >= g_dwc2_udc[busid].user_params.device_tx_fifo_size[i], + "device_tx_fifo_size[%u] cannot be larger than power_on_value %u", i, reset_txfifo_size); + } + if (g_dwc2_udc[busid].user_params.b_session_valid_override) { /* B-peripheral session valid override enable */ USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; @@ -675,6 +676,7 @@ uint8_t usbd_get_port_speed(uint8_t busid) int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) { uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint16_t ep_mps; USB_ASSERT_MSG(ep_idx < (g_dwc2_udc[busid].hw_params.num_dev_ep + 1), "Ep addr %02x overflow", ep->bEndpointAddress); @@ -682,14 +684,34 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) g_dwc2_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); g_dwc2_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); - USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx)); + ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + if (ep_idx == 0) { + switch (ep_mps) { + case 64: + ep_mps = EP_MPS_64; + break; + case 32: + ep_mps = EP_MPS_32; + break; + case 16: + ep_mps = EP_MPS_16; + break; + case 8: + ep_mps = EP_MPS_8; + break; - if ((USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP) == 0) { - USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) & USB_OTG_DOEPCTL_MPSIZ) | - ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DOEPCTL_USBAEP; + default: + ep_mps = EP_MPS_64; + break; + } } + + USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx)); + + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (ep_mps & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; } else { uint16_t fifo_size; if (ep_idx == 0) { @@ -703,14 +725,34 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) g_dwc2_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); g_dwc2_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); - USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx); + ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + if (ep_idx == 0) { + switch (ep_mps) { + case 64: + ep_mps = EP_MPS_64; + break; + case 32: + ep_mps = EP_MPS_32; + break; + case 16: + ep_mps = EP_MPS_16; + break; + case 8: + ep_mps = EP_MPS_8; + break; - if ((USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0) { - USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) & USB_OTG_DIEPCTL_MPSIZ) | - ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | (ep_idx << 22) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_USBAEP; + default: + ep_mps = EP_MPS_64; + break; + } } + + USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx); + + USB_OTG_INEP(ep_idx)->DIEPCTL |= (ep_mps & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | (ep_idx << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; dwc2_flush_txfifo(busid, ep_idx); } return 0; @@ -782,7 +824,6 @@ int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) } if ((ep_idx == 0) && g_dwc2_udc[busid].user_params.device_dma_enable) { - usb_dcache_invalidate((uintptr_t)&g_dwc2_udc[busid].setup, USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE)); dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } @@ -1046,7 +1087,7 @@ void USBD_IRQHandler(uint8_t busid) usbd_event_ep_out_complete_handler(busid, ep_idx, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len); } } - // clang-format off + // clang-format off process_setup: // clang-format on if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { @@ -1132,14 +1173,15 @@ process_setup: memset(g_dwc2_udc[busid].in_ep, 0, sizeof(struct dwc2_ep_state) * 16); memset(g_dwc2_udc[busid].out_ep, 0, sizeof(struct dwc2_ep_state) * 16); usbd_event_reset_handler(busid); - /* Start reading setup */ - dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } if (gint_status & USB_OTG_GINTSTS_ENUMDNE) { USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; - dwc2_set_turnaroundtime(busid, SystemCoreClock, dwc2_get_devspeed(busid)); + dwc2_set_turnaroundtime(busid, usbd_dwc2_get_system_clock(), dwc2_get_devspeed(busid)); USB_OTG_DEV->DCTL |= USB_OTG_DCTL_CGINAK; + + /* Start reading setup */ + dwc2_ep0_start_read_setup(busid, (uint8_t *)&g_dwc2_udc[busid].setup); } if (gint_status & USB_OTG_GINTSTS_PXFR_INCOMPISOOUT) { USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_PXFR_INCOMPISOOUT; diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h b/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h index 599d4ea58f..69b0960032 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h @@ -1733,4 +1733,6 @@ typedef struct void usb_dc_low_level_init(uint8_t busid); void usb_dc_low_level_deinit(uint8_t busid); void usbd_dwc2_delay_ms(uint8_t ms); +uint32_t usbd_dwc2_get_system_clock(void); + #endif diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c index 17dec47f3d..5fcb8151f1 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c @@ -9,8 +9,6 @@ extern unsigned int system_core_clock; -uint32_t SystemCoreClock; - const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, @@ -80,8 +78,6 @@ const struct dwc2_user_params param_pb14_pb15 = { #ifndef CONFIG_USB_DWC2_CUSTOM_PARAM void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) { - SystemCoreClock = system_core_clock; - #if __has_include("at32f402_405.h") if (reg_base == OTGHS_BASE) { memcpy(params, ¶m_pb14_pb15, sizeof(struct dwc2_user_params)); @@ -106,8 +102,13 @@ void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) void usbd_dwc2_delay_ms(uint8_t ms) { - uint32_t count = SystemCoreClock / 1000 * ms; + uint32_t count = system_core_clock / 1000 * ms; while (count--) { __asm volatile("nop"); } } + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return system_core_clock; +} diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c index 03110fb8ce..6023129289 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c @@ -151,7 +151,7 @@ void usb_dc_low_level_init(uint8_t busid) }; phy_config.target = GET_USB_PHY_TARGET(reg_base); phy_config.otg_speed = GET_USB_PHY_SPEED(reg_base); - + ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]); if (ret != ESP_OK) { USB_LOG_ERR("USB Phy Init Failed!\r\n"); @@ -262,6 +262,11 @@ void usbd_dwc2_delay_ms(uint8_t ms) vTaskDelay(pdMS_TO_TICKS(ms)); } +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + #ifdef CONFIG_USB_DCACHE_ENABLE #include "esp_cache.h" diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c index 15ba5d69a9..38e065ab13 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_hc.c @@ -1,30 +1,297 @@ /* - * Copyright (c) 2024, sakumisu + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-08-08 CDT first version */ -#include "usb_config.h" -#include "usb_dwc2_reg.h" -/* When using [GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC);], there is no need to configure GOTGCTL */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" + +#include "board_config.h" + +#if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) + #if defined(HC32F460) || defined(HC32F472) + #error "Only one USB role can be selected!" + #endif +#endif + +const struct dwc2_user_params param_fs_core = +{ + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE, + .device_tx_fifo_size = { + [0] = CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE, +#if defined(HC32F4A0) || defined(HC32F4A8) + [6] = CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE, + [10] = CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE, + [11] = CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE, + [12] = CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE, + [13] = CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE, + [14] = CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE, + [15] = CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE +#elif defined(HC32F460) || defined(HC32F472) + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 +#endif + }, + .total_fifo_size = CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE, -#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base)) + .host_dma_desc_enable = false, + .host_rx_fifo_size = CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE, + .host_nperio_tx_fifo_size = CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE, + .host_perio_tx_fifo_size = CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE, + .device_gccfg = 0, + .host_gccfg = 0, +#if defined(HC32F4A0) || defined(HC32F4A8) || defined(HC32F460) + .b_session_valid_override = false, +#elif defined(HC32F472) + .b_session_valid_override = true, +#endif +}; -uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +#if defined(HC32F4A0) || defined(HC32F4A8) +const struct dwc2_user_params param_hs_core = { +#ifdef CONFIG_USB_HS + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#else + .phy_type = DWC2_PHY_TYPE_PARAM_FS, +#endif +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE, + .device_tx_fifo_size = { + [0] = CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE, + [6] = CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE, + [10] = CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE, + [11] = CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE, + [12] = CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE, + [13] = CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE, + [14] = CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE, + [15] = CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE + }, + .total_fifo_size = CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE, + .host_nperio_tx_fifo_size = CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE, + .host_perio_tx_fifo_size = CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE, + .device_gccfg = 0, + .host_gccfg = 0, + .b_session_valid_override = false, +}; +#endif - USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - return 0; +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ +#if defined(HC32F4A0) || defined(HC32F4A8) + if (reg_base == CM_USBHS_BASE) + { + memcpy(params, ¶m_hs_core, sizeof(struct dwc2_user_params)); + } + else +#endif + { + memcpy(params, ¶m_fs_core, sizeof(struct dwc2_user_params)); + } +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) + { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif } +#endif -uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +#define BOARD_INIT_USB_HOST_MODE (0U) +#define BOARD_INIT_USB_DEVICE_MODE (1U) +extern rt_err_t rt_hw_usbfs_board_init(uint8_t devmode); +static uint8_t g_usb_fs_busid = 0U; +#if defined(HC32F4A0) || defined(HC32F4A8) + extern rt_err_t rt_hw_usbhs_board_init(uint8_t devmode); + static uint8_t g_usb_hs_busid = 0U; +#endif + +#if defined(RT_CHERRYUSB_HOST) +static void usbh_fs_irq_handler(void) { - USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; - USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; - return 0; + USBH_IRQHandler(g_usb_fs_busid); } +#if defined(HC32F4A0) || defined(HC32F4A8) +static void usbh_hs_irq_handler(void) +{ + USBH_IRQHandler(g_usb_hs_busid); +} +#endif + +#if defined(HC32F472) +void USBFS_Handler(void) +{ + usbh_fs_irq_handler(); +} +#endif + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + struct hc32_irq_config irq_config; + +#if defined(HC32F4A0) || defined(HC32F4A8) + if (bus->hcd.reg_base == CM_USBHS_BASE) + { + g_usb_hs_busid = bus->hcd.hcd_id; + + rt_hw_usbhs_board_init(BOARD_INIT_USB_HOST_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE); +#ifndef CONFIG_USB_HS + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; +#endif + + irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBHS_GLB; + irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbh_hs_irq_handler, + RT_TRUE); + } + else +#endif + { + g_usb_fs_busid = bus->hcd.hcd_id; + + rt_hw_usbfs_board_init(BOARD_INIT_USB_HOST_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBFS_GLB; + irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbh_fs_irq_handler, + RT_TRUE); + } + +} +#endif + +#if defined(RT_CHERRYUSB_DEVICE) +static void usbd_fs_irq_handler(void) +{ + USBD_IRQHandler(g_usb_fs_busid); +} + +#if defined(HC32F4A0) || defined(HC32F4A8) +static void usbd_hs_irq_handler(void) +{ + USBD_IRQHandler(g_usb_hs_busid); +} +#endif + +#if defined(HC32F472) +void USBFS_Handler(void) +{ + usbd_fs_irq_handler(); +} +#endif + +void usb_dc_low_level_init(uint8_t busid) +{ + struct hc32_irq_config irq_config; + +#if defined(HC32F4A0) || defined(HC32F4A8) + if (g_usbdev_bus[busid].reg_base == CM_USBHS_BASE) + { + g_usb_hs_busid = busid; + + rt_hw_usbhs_board_init(BOARD_INIT_USB_DEVICE_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE); + +#ifndef CONFIG_USB_HS + /* enable the embedded PHY in USBHS mode */ + CM_PERIC->USB_SYCTLREG |= PERIC_USB_SYCTLREG_USBHS_FSPHYE; +#endif + + irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBHS_GLB; + irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbd_hs_irq_handler, + RT_TRUE); + } + else +#endif + { + g_usb_fs_busid = busid; + + rt_hw_usbfs_board_init(BOARD_INIT_USB_DEVICE_MODE); + FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE); + + irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM; + irq_config.int_src = INT_SRC_USBFS_GLB; + irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO; + /* register interrupt */ + hc32_install_irq_handler(&irq_config, + usbd_fs_irq_handler, + RT_TRUE); + } +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + (void)busid; + /* reserved */ +} + +#endif + extern uint32_t SystemCoreClock; void usbd_dwc2_delay_ms(uint8_t ms) @@ -34,3 +301,8 @@ void usbd_dwc2_delay_ms(uint8_t ms) __asm volatile("nop"); } } + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c new file mode 100644 index 0000000000..19239ec891 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2026, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_dwc2_param.h" +#include "rtthread.h" +#include "cybsp.h" + +#if defined (COMPONENT_CM55) + +#if defined(CONFIG_USB_DWC2_DMA_ENABLE) && !defined(CONFIG_USB_DCACHE_ENABLE) +#error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" when using DMA" +#endif + +#else +#define CONFIG_USB_DWC2_DMA_ENABLE +#endif + +const struct dwc2_user_params param_common = { + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + .device_dma_enable = true, +#else + .device_dma_enable = false, +#endif + .device_dma_desc_enable = false, + .device_rx_fifo_size = 0x21F, + .device_tx_fifo_size = { + [0] = 16, // 64 byte + [1] = 0x300, // 1024 byte, tripple buffer + [2] = 0x300, // 1024 byte, tripple buffer + [3] = 0x300, // 1024 byte, tripple buffer + [4] = 0x300, // 1024 byte, tripple buffer + [5] = 0x300, // 1024 byte, tripple buffer + [6] = 0x300, // 1024 byte, tripple buffer + [7] = 0x300, // 1024 byte, tripple buffer + [8] = 0x300, // 1024 byte, tripple buffer + [9] = 0, + [10] = 0, + [11] = 0, + [12] = 0, + [13] = 0, + [14] = 0, + [15] = 0 }, + + .host_dma_desc_enable = false, + .host_rx_fifo_size = 0x21F, + .host_nperio_tx_fifo_size = 0x100, // 512 byte, double buffer + .host_perio_tx_fifo_size = 0x400, // 1024 byte, four buffer + + .device_gccfg = 0, + .host_gccfg = 0 +}; + +#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM +void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) +{ + memcpy(params, ¶m_common, sizeof(struct dwc2_user_params)); +#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO + struct usb_dwc2_user_fifo_config s_dwc2_fifo_config; + + dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config); + + params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size; + for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) { + params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i]; + } +#endif +} +#endif + +void USBHS_DEVICE_IRQHandler(void) +{ + USBD_IRQHandler(0); +} + +void usb_dc_low_level_init(uint8_t busid) +{ + USBHS_SS->SUBSYSTEM_CTL = (1 << USBHS_SS_SUBSYSTEM_CTL_AHB_MASTER_SYNC_Pos) | USBHS_SS_SUBSYSTEM_CTL_SS_ENABLE_Msk; + USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); + USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); + + cy_stc_sysint_t usb_int_cfg = { + .intrSrc = usbhs_interrupt_usbhsctrl_IRQn, + .intrPriority = 3 + }; + + /* Install the interrupt service routine */ + Cy_SysInt_Init(&usb_int_cfg, USBHS_DEVICE_IRQHandler); + + NVIC_EnableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +void usb_dc_low_level_deinit(uint8_t busid) +{ + NVIC_DisableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +void usbd_dwc2_delay_ms(uint8_t ms) +{ + rt_thread_mdelay(ms); +} + +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + +void USBHS_HOST_IRQHandler(void) +{ + USBH_IRQHandler(0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + USBHS_SS->SUBSYSTEM_CTL = (1 << USBHS_SS_SUBSYSTEM_CTL_AHB_MASTER_SYNC_Pos) | USBHS_SS_SUBSYSTEM_CTL_USB_MODE_Msk | USBHS_SS_SUBSYSTEM_CTL_SS_ENABLE_Msk; + USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); + USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); + + cy_stc_sysint_t usb_int_cfg = { + .intrSrc = usbhs_interrupt_usbhsctrl_IRQn, + .intrPriority = 3 + }; + + /* Install the interrupt service routine */ + Cy_SysInt_Init(&usb_int_cfg, USBHS_HOST_IRQHandler); + + NVIC_EnableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + NVIC_DisableIRQ(usbhs_interrupt_usbhsctrl_IRQn); +} + +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + SCB_CleanDCache_by_Addr((void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + SCB_InvalidateDCache_by_Addr((void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + SCB_CleanInvalidateDCache_by_Addr((void *)addr, size); +} +#endif diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c index 36c7791eeb..4e111ddb95 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_kendryte.c @@ -50,11 +50,7 @@ const uintptr_t usb_dev_addr[2] = { 0x91500000UL, 0x91540000UL }; const struct dwc2_user_params param_common = { .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, -#ifdef CONFIG_USB_DWC2_DMA_ENABLE .device_dma_enable = true, -#else - .device_dma_enable = false, -#endif .device_dma_desc_enable = false, .device_rx_fifo_size = (3016 - 16 - 256 * 8), .device_tx_fifo_size = { @@ -204,6 +200,11 @@ void usbd_dwc2_delay_ms(uint8_t ms) rt_thread_mdelay(ms); } +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + #ifdef CONFIG_USB_DCACHE_ENABLE void usb_dcache_clean(uintptr_t addr, size_t size) { diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c index 5e6391fc2c..b766ca4b5d 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c @@ -16,10 +16,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -50,10 +50,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -124,10 +124,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -212,10 +212,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -380,10 +380,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -446,10 +446,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -481,10 +481,10 @@ const struct dwc2_user_params param_pa11_pa12 = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, .device_dma_enable = false, .device_dma_desc_enable = false, - .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16), + .device_rx_fifo_size = (320 - 16 - 64 - 16 - 16), .device_tx_fifo_size = { [0] = 16, // 64 byte - [1] = 16, // 64 byte + [1] = 64, // 256 byte [2] = 16, // 64 byte [3] = 16, // 64 byte [4] = 0, @@ -722,6 +722,11 @@ void usbd_dwc2_delay_ms(uint8_t ms) } } +uint32_t usbd_dwc2_get_system_clock(void) +{ + return SystemCoreClock; +} + void OTG_FS_IRQHandler(void) { g_usb_dwc2_irq[0](g_usb_dwc2_busid[0]); diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c b/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c index df706eda16..bf0adae571 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c @@ -339,22 +339,6 @@ static inline void dwc2_chan_enable_csplit(struct usbh_bus *bus, uint8_t ch_num, } } -static inline void dwc2_chan_reenable(struct usbh_bus *bus, uint8_t ch_num) -{ - __IO uint32_t tmpreg; - uint8_t is_oddframe; - - is_oddframe = (((uint32_t)USB_OTG_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; - USB_OTG_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USB_OTG_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; - - /* Set host channel enable */ - tmpreg = USB_OTG_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USB_OTG_HC(ch_num)->HCCHAR = tmpreg; -} - static void dwc2_halt(struct usbh_bus *bus, uint8_t ch_num) { volatile uint32_t ChannelEna = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; @@ -731,6 +715,13 @@ int usb_hc_init(struct usbh_bus *bus) /* Force Host Mode*/ dwc2_set_mode(bus, USB_OTG_MODE_HOST); + USB_ASSERT_MSG((USB_OTG_GLB->GRXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size, + "host_rx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->GRXFSIZ & 0xffff)); + USB_ASSERT_MSG((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size, + "host_nperio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ & 0xffff)); + USB_ASSERT_MSG((USB_OTG_GLB->HPTXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size, + "host_perio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->HPTXFSIZ & 0xffff)); + /* B-peripheral session valid override enable */ USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; @@ -745,13 +736,15 @@ int usb_hc_init(struct usbh_bus *bus) USB_OTG_HOST->HCFG &= ~USB_OTG_HCFG_FSLSPCS; if (g_dwc2_hcd[bus->hcd.hcd_id].user_params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { + bus->hcd.roothub.speed = USB_SPEED_FULL; USB_OTG_HOST->HCFG |= USB_OTG_HCFG_FSLSPCLKSEL_48_MHZ; } else { + bus->hcd.roothub.speed = USB_SPEED_HIGH; USB_OTG_HOST->HCFG |= USB_OTG_HCFG_FSLSPCLKSEL_30_60_MHZ; } if (g_dwc2_hcd[bus->hcd.hcd_id].hw_params.snpsid > 0x4F54292AU) { - USB_OTG_HOST->HCFG |= USB_OTG_HFIR_RELOAD_CTRL; + USB_OTG_HOST->HFIR |= USB_OTG_HFIR_RELOAD_CTRL; } /* Clear all pending HC Interrupts */ @@ -766,7 +759,7 @@ int usb_hc_init(struct usbh_bus *bus) /* Clear any pending interrupts */ USB_OTG_GLB->GINTSTS = 0xFFFFFFFFU; - /* set Rx FIFO size */ + /* set FIFO size */ USB_OTG_GLB->GRXFSIZ = g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size; USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size << 16) & USB_OTG_NPTXFD) | g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size); @@ -794,36 +787,14 @@ int usb_hc_init(struct usbh_bus *bus) int usb_hc_deinit(struct usbh_bus *bus) { - volatile uint32_t count = 0U; - uint32_t value; - USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; dwc2_flush_txfifo(bus, 0x10U); dwc2_flush_rxfifo(bus); /* Flush out any leftover queued requests. */ - for (uint32_t i = 0U; i < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; i++) { - value = USB_OTG_HC(i)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USB_OTG_HC(i)->HCCHAR = value; - } - - /* Halt all channels to put them into a known state. */ - for (uint32_t i = 0U; i < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; i++) { - value = USB_OTG_HC(i)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USB_OTG_HC(i)->HCCHAR = value; - - do { - if (++count > 1000U) { - return -USB_ERR_TIMEOUT; - } - } while ((USB_OTG_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + for (uint8_t chidx = 0; chidx < g_dwc2_hcd[bus->hcd.hcd_id].hw_params.host_channels; chidx++) { + dwc2_halt(bus, chidx); } /* Disable all interrupts. */ @@ -1235,12 +1206,15 @@ static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) /* restart ssplit transfer */ switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { case USB_ENDPOINT_TYPE_CONTROL: + chan->do_csplit = 0; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; case USB_ENDPOINT_TYPE_BULK: chan->do_csplit = 0; - dwc2_chan_enable_csplit(bus, ch_num, false); - dwc2_chan_reenable(bus, ch_num); + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); break; case USB_ENDPOINT_TYPE_INTERRUPT: + chan->do_csplit = 0; dwc2_chan_enable_csplit(bus, ch_num, false); urb->errorcode = -USB_ERR_NAK; dwc2_urb_waitup(urb); @@ -1255,17 +1229,39 @@ static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) } } else if (chan_intstatus & USB_OTG_HCINT_ACK) { if (chan->do_ssplit) { - /* start ssplit transfer */ + /* start csplit transfer */ chan->do_csplit = 1; chan->ssplit_frame = dwc2_get_full_frame_num(bus); - dwc2_chan_enable_csplit(bus, ch_num, true); - dwc2_chan_reenable(bus, ch_num); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } } } else if (chan_intstatus & USB_OTG_HCINT_NYET) { if (chan->do_ssplit) { /* restart csplit transfer */ - dwc2_chan_enable_csplit(bus, ch_num, true); - dwc2_chan_reenable(bus, ch_num); + chan->do_csplit = 1; + chan->ssplit_frame = dwc2_get_full_frame_num(bus); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } } else { urb->errorcode = -USB_ERR_NAK; dwc2_urb_waitup(urb); @@ -1372,12 +1368,15 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) /* restart ssplit transfer */ switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { case USB_ENDPOINT_TYPE_CONTROL: + chan->do_csplit = 0; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; case USB_ENDPOINT_TYPE_BULK: chan->do_csplit = 0; - dwc2_chan_enable_csplit(bus, ch_num, false); - dwc2_chan_reenable(bus, ch_num); + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); break; case USB_ENDPOINT_TYPE_INTERRUPT: + chan->do_csplit = 0; dwc2_chan_enable_csplit(bus, ch_num, false); urb->errorcode = -USB_ERR_NAK; dwc2_urb_waitup(urb); @@ -1392,17 +1391,39 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) } } else if (chan_intstatus & USB_OTG_HCINT_ACK) { if (chan->do_ssplit) { - /* start ssplit transfer */ + /* start csplit transfer */ chan->do_csplit = 1; chan->ssplit_frame = dwc2_get_full_frame_num(bus); - dwc2_chan_enable_csplit(bus, ch_num, true); - dwc2_chan_reenable(bus, ch_num); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } } } else if (chan_intstatus & USB_OTG_HCINT_NYET) { if (chan->do_ssplit) { /* restart csplit transfer */ - dwc2_chan_enable_csplit(bus, ch_num, true); - dwc2_chan_reenable(bus, ch_num); + chan->do_csplit = 1; + chan->ssplit_frame = dwc2_get_full_frame_num(bus); + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length); + break; + + default: + break; + } } else { urb->errorcode = -USB_ERR_NAK; dwc2_urb_waitup(urb); diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c index 500bc02a40..2db67bc573 100644 --- a/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c @@ -1,4 +1,4 @@ -/* +/* * Copyright (c) 2022, Artinchip Technology Co., Ltd * * SPDX-License-Identifier: Apache-2.0 @@ -46,37 +46,31 @@ typedef struct aic_ehci_config { uint32_t phy_clk_id; uint32_t phy_rst_id; uint32_t irq_num; -}aic_ehci_config_t; +} aic_ehci_config_t; aic_ehci_config_t config[] = { #ifdef AIC_USING_USB0_HOST - { - USB_HOST0_BASE, - CLK_USBH0, - RESET_USBH0, - CLK_USB_PHY0, - RESET_USBPHY0, - USB_HOST0_EHCI_IRQn - }, + { USB_HOST0_BASE, + CLK_USBH0, + RESET_USBH0, + CLK_USB_PHY0, + RESET_USBPHY0, + USB_HOST0_EHCI_IRQn }, #else - { - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF - }, + { 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF }, #endif #ifdef AIC_USING_USB1_HOST - { - USB_HOST1_BASE, - CLK_USBH1, - RESET_USBH1, - CLK_USB_PHY1, - RESET_USBPHY1, - USB_HOST1_EHCI_IRQn - } + { USB_HOST1_BASE, + CLK_USBH1, + RESET_USBH1, + CLK_USB_PHY1, + RESET_USBPHY1, + USB_HOST1_EHCI_IRQn } #endif }; @@ -85,12 +79,12 @@ void usb_hc_low_level_init(struct usbh_bus *bus) uint32_t val; int i = 0; - for (i=0; ihcd.reg_base == config[i].base_addr) break; } - if (i == sizeof(config)/sizeof(aic_ehci_config_t)) + if (i == sizeof(config) / sizeof(aic_ehci_config_t)) return; /* set usb0 phy switch: Host/Device */ @@ -109,20 +103,20 @@ void usb_hc_low_level_init(struct usbh_bus *bus) aicos_udelay(300); /* set phy type: UTMI/ULPI */ - val = readl((volatile void *)(unsigned long)(config[i].base_addr+0x800)); + val = readl((volatile void *)(unsigned long)(config[i].base_addr + 0x800)); #ifdef FPGA_BOARD_ARTINCHIP /* fpga phy type = ULPI */ - writel((val & ~0x1U), (volatile void *)(unsigned long)(config[i].base_addr+0x800)); + writel((val & ~0x1U), (volatile void *)(unsigned long)(config[i].base_addr + 0x800)); #else /* board phy type = UTMI */ - writel((val | 0x1), (volatile void *)(unsigned long)(config[i].base_addr+0x800)); + writel((val | 0x1), (volatile void *)(unsigned long)(config[i].base_addr + 0x800)); #endif /* Set AHB2STBUS_INSREG01 Set EHCI packet buffer IN/OUT threshold (in DWORDs) Must increase the OUT threshold to avoid underrun. (FIFO size - 4) */ - writel((32 | (127 << 16)), (volatile void *)(unsigned long)(config[i].base_addr+0x94)); + writel((32 | (127 << 16)), (volatile void *)(unsigned long)(config[i].base_addr + 0x94)); /* register interrupt callback */ aicos_request_irq(config[i].irq_num, (irq_handler_t)aic_ehci_isr, @@ -160,12 +154,12 @@ int __usbh_init(void) #endif #ifdef AIC_USING_USB0_HOST - usbh_initialize(bus_id, USB_HOST0_BASE); + usbh_initialize(bus_id, USB_HOST0_BASE, NULL); bus_id++; #endif #ifdef AIC_USING_USB1_HOST - usbh_initialize(bus_id, USB_HOST1_BASE); + usbh_initialize(bus_id, USB_HOST1_BASE, NULL); bus_id++; #endif return 0; diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_t113.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_t113.c index 0c99897fd5..ec46dea61d 100644 --- a/components/drivers/usb/cherryusb/port/ehci/usb_glue_t113.c +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_t113.c @@ -1,18 +1,27 @@ /* - * Copyright (c) 2025, YC113 + * Copyright (c) 2026, HakumenJean * * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-06 HakumenJean first version */ + +#include +#include +#include +#include + #include "usbh_core.h" #include "usb_hc_ehci.h" - #ifdef CONFIG_USB_EHCI_WITH_OHCI #include "usb_hc_ohci.h" #endif +#include "hal_clk.h" +#include "hal_reset.h" #include "interrupt.h" -#include "drv_reg_base.h" -#include "drv_clock.h" #if CONFIG_USBHOST_MAX_BUS != 2 #error "t113 has 2 usb host controller" @@ -34,6 +43,13 @@ #error "t113 usb ehci no iso register" #endif +#define USB0_OTG_BASE_ADDR (0x04100000U) +#define USB0_PHY_BASE_ADDR (0x04100400U) +#define USB0_EHCI_BASE_ADDR (0x04101000U) + +#define USB1_EHCI_BASE_ADDR (0x04200000U) +#define USB1_PHY_BASE_ADDR (0x04200800U) + void usb_select_phyTohci(void) { *(volatile rt_uint32_t *)(USB0_OTG_BASE_ADDR + 0x420) &= ~(1 << 0); @@ -41,55 +57,52 @@ void usb_select_phyTohci(void) void usb_gate_open(rt_uint8_t busid) { - rt_uint32_t addr; - - addr = (rt_uint32_t)&CCU->usb0_clk + busid * 4; - - if(busid == 0) { + if (busid == 0) { /* otg gate open*/ - CCU->usb_bgr |= 1 << 8; + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OTG)); /* otg bus reset */ - CCU->usb_bgr &= ~(1 << 24); - sdelay(10); - CCU->usb_bgr |= (1 << 24); - sdelay(10); - } + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OTG)); + + /* ehci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_EHCI0)); + + /* ehci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_EHCI0)); + + /* ohci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OHCI0)); - /* ehci gate open */ - CCU->usb_bgr |= (1 << 4) << busid; + /* ohci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OHCI0)); - /* ehci bus reset */ - CCU->usb_bgr &= ~((1 << 20) << busid); - sdelay(10); - CCU->usb_bgr |= (1 << 20) << busid; - sdelay(10); + /* clock enable */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_USB_OHCI0)); - /* ohci gate open */ - CCU->usb_bgr |= 1 << busid; + /* reset phy */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_USB_PHY0)); - /* ohci bus reset */ - CCU->usb_bgr &= ~((1 << 16) << busid); - sdelay(10); - CCU->usb_bgr |= (1 << 16) << busid; - sdelay(10); + /* otg phy select */ + usb_select_phyTohci(); + } else { + /* ehci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_EHCI1)); - sdelay(10); + /* ehci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_EHCI1)); - /* clock enable */ - *(volatile rt_uint32_t *)addr &= ~(3 << 24); - *(volatile rt_uint32_t *)addr |= (1 << 31) | (1 << 24); + /* ohci gate open */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OHCI1)); - /* reset phy */ - *(volatile rt_uint32_t *)addr &= ~(1 << 30); - sdelay(10); - *(volatile rt_uint32_t *)addr |= 1 << 30; - sdelay(10); + /* ohci bus reset */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OHCI1)); - /* otg phy select */ - if(busid == 0) usb_select_phyTohci(); + /* clock enable */ + hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_USB_OHCI1)); - USB_LOG_DBG("usb%d gate : %X, clock : %X\n", busid, CCU->usb_bgr, *(volatile rt_uint32_t *)addr); + /* reset phy */ + hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_USB_PHY1)); + } } void usb_clean_siddp(struct usbh_bus *bus) @@ -109,10 +122,10 @@ void usb_hci_set_passby(struct usbh_bus *bus) void t113_ehci_isr(int vector, void *arg) { - rt_interrupt_enter(); - struct usbh_bus *bus = (struct usbh_bus *)arg; + rt_interrupt_enter(); + USB_LOG_DBG("t113_ehci_isr"); extern void USBH_IRQHandler(uint8_t busid); @@ -125,10 +138,10 @@ void t113_ehci_isr(int vector, void *arg) void t113_ohci_isr(int vector, void *arg) { - rt_interrupt_enter(); - struct usbh_bus *bus = (struct usbh_bus *)arg; + rt_interrupt_enter(); + USB_LOG_DBG("t113_ohci_isr"); extern void OHCI_IRQHandler(uint8_t busid); @@ -149,8 +162,9 @@ void usb_hc_low_level_init(struct usbh_bus *bus) usb_hci_set_passby(bus); /* register EHCI interrupt callback */ - vector = T113_IRQ_USB0_EHCI + (bus->busid > 0 ? 3 : 0); + vector = SUNXI_IRQ_USB0_EHCI + (bus->busid > 0 ? 3 : 0); rt_hw_interrupt_install(vector, t113_ehci_isr, bus, RT_NULL); + rt_hw_interrupt_set_priority(vector, 11 << 4); rt_hw_interrupt_umask(vector); /* register OHCI interrupt callback */ @@ -183,12 +197,12 @@ int __usbh_init(void) { #ifdef T113_USING_USB0_HOST /* USB0 MSC test OK */ - usbh_initialize(0, USB0_BASE_ADDR); + usbh_initialize(0, USB0_EHCI_BASE_ADDR, NULL); #endif #ifdef T113_USING_USB1_HOST /* USB1 MSC test OK */ - usbh_initialize(1, USB1_BASE_ADDR); + usbh_initialize(1, USB1_EHCI_BASE_ADDR, NULL); #endif return 0; } @@ -196,8 +210,26 @@ int __usbh_init(void) #ifdef PKG_CHERRYUSB_HOST #include +#include #include INIT_ENV_EXPORT(__usbh_init); +#ifdef CONFIG_USB_DCACHE_ENABLE +void usb_dcache_clean(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)addr, size); +} + +void usb_dcache_invalidate(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)addr, size); +} + +void usb_dcache_flush(uintptr_t addr, size_t size) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)addr, size); +} +#endif + #endif diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c b/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c index 2ebe11347c..fd72907f89 100644 --- a/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c +++ b/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c @@ -774,6 +774,8 @@ int usb_hc_init(struct usbh_bus *bus) volatile uint32_t timeout = 0; uint32_t regval; + bus->hcd.roothub.speed = USB_SPEED_HIGH; + memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd)); memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM); memset(ehci_qtd_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qtd_hw) * CONFIG_USB_EHCI_QTD_NUM); @@ -1337,6 +1339,7 @@ int usbh_kill_urb(struct usbh_urb *urb) EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); qh = (struct ehci_qh_hw *)urb->hcpriv; + qh->remove_in_iaad = 0; urb->errorcode = -USB_ERR_SHUTDOWN; if (urb->timeout) { @@ -1347,6 +1350,7 @@ int usbh_kill_urb(struct usbh_urb *urb) if (remove_in_iaad) { volatile uint32_t timeout = 0; + EHCI_HCOR->usbsts = EHCI_USBSTS_IAA; EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD; while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) { timeout++; diff --git a/components/drivers/usb/cherryusb/port/hpmicro/usb_dc_hpm.c b/components/drivers/usb/cherryusb/port/hpmicro/usb_dc_hpm.c index 09896549ab..a3a9fdc10d 100644 --- a/components/drivers/usb/cherryusb/port/hpmicro/usb_dc_hpm.c +++ b/components/drivers/usb/cherryusb/port/hpmicro/usb_dc_hpm.c @@ -102,7 +102,9 @@ int usb_dc_init(uint8_t busid) #endif usb_device_init(g_hpm_udc[busid].handle, int_mask); - +#ifdef CONFIG_USB_OTG_ENABLE + usb_otgsc_enable_id_chg_int(g_hpm_udc[busid].handle->regs); +#endif usb_dc_isr_connect(busid); return 0; @@ -240,10 +242,15 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui return -2; } +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + g_hpm_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; g_hpm_udc[busid].in_ep[ep_idx].xfer_len = data_len; g_hpm_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + usb_dcache_clean((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); usb_device_edpt_xfer(handle, ep, (uint8_t *)data, data_len); return 0; @@ -261,10 +268,15 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t return -2; } +#ifdef CONFIG_USB_DCACHE_ENABLE + USB_ASSERT_MSG(!((uintptr_t)data % CONFIG_USB_ALIGN_SIZE), "data is not aligned %d", CONFIG_USB_ALIGN_SIZE); +#endif + g_hpm_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; g_hpm_udc[busid].out_ep[ep_idx].xfer_len = data_len; g_hpm_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + usb_dcache_invalidate((uintptr_t)data, USB_ALIGN_UP(data_len, CONFIG_USB_ALIGN_SIZE)); usb_device_edpt_xfer(handle, ep, data, data_len); return 0; @@ -297,7 +309,7 @@ void USBD_IRQHandler(uint8_t busid) memset(g_hpm_udc[busid].in_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); memset(g_hpm_udc[busid].out_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); usbd_event_reset_handler(busid); - usb_device_bus_reset(handle, 64); + usb_device_bus_reset(handle, g_hpm_udc[busid].in_ep[0].ep_mps); } if (int_status & intr_suspend) { @@ -362,6 +374,7 @@ void USBD_IRQHandler(uint8_t busid) if (ep_addr & 0x80) { usbd_event_ep_in_complete_handler(busid, ep_addr, transfer_len); } else { + usb_dcache_invalidate((uintptr_t)g_hpm_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(transfer_len, CONFIG_USB_ALIGN_SIZE)); usbd_event_ep_out_complete_handler(busid, ep_addr, transfer_len); } } diff --git a/components/drivers/usb/cherryusb/port/hpmicro/usb_glue_hpm.c b/components/drivers/usb/cherryusb/port/hpmicro/usb_glue_hpm.c index 51aa9aa452..aa5f9cec66 100644 --- a/components/drivers/usb/cherryusb/port/hpmicro/usb_glue_hpm.c +++ b/components/drivers/usb/cherryusb/port/hpmicro/usb_glue_hpm.c @@ -7,11 +7,73 @@ #include "hpm_common.h" #include "hpm_soc.h" #include "hpm_l1c_drv.h" +#include "hpm_usb_drv.h" #include "usb_config.h" void (*g_usb_hpm_irq[2])(uint8_t busid); uint8_t g_usb_hpm_busid[2]; +#ifndef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +SDK_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#ifdef HPM_USB1_BASE +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, hpm_isr_usb1) +#endif +#endif + +#ifdef CONFIG_USB_OTG_ENABLE +#include "usbotg_core.h" +int usb_otg_init(uint8_t busid) +{ + (void)busid; + + return 0; +} + +int usb_otg_deinit(uint8_t busid) +{ + (void)busid; + + return 0; +} + +void hpm_isr_usb0(void) +{ + if (usb_otgsc_get_id_chg_flag(HPM_USB0)) { + usb_otgsc_clear_id_chg_flag(HPM_USB0); + usbotg_trigger_role_change(g_usb_hpm_busid[0], usb_otgsc_get_id_status(HPM_USB0) ? USBOTG_MODE_DEVICE : USBOTG_MODE_HOST); + } + + USBOTG_IRQHandler(g_usb_hpm_busid[0]); +} + +#ifdef HPM_USB1_BASE +void hpm_isr_usb1(void) +{ + if (usb_otgsc_get_id_chg_flag(HPM_USB1)) { + usb_otgsc_clear_id_chg_flag(HPM_USB1); + usbotg_trigger_role_change(g_usb_hpm_busid[1], usb_otgsc_get_id_status(HPM_USB1) ? USBOTG_MODE_DEVICE : USBOTG_MODE_HOST); + } + + USBOTG_IRQHandler(g_usb_hpm_busid[1]); +} +#endif + +#else + +void hpm_isr_usb0(void) +{ + g_usb_hpm_irq[0](g_usb_hpm_busid[0]); +} + +#ifdef HPM_USB1_BASE +void hpm_isr_usb1(void) +{ + g_usb_hpm_irq[1](g_usb_hpm_busid[1]); +} +#endif + +#endif + ATTR_WEAK void hpm_usb_isr_enable(uint32_t base) { if (base == HPM_USB0_BASE) { @@ -34,24 +96,6 @@ ATTR_WEAK void hpm_usb_isr_disable(uint32_t base) } } -#ifndef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER -SDK_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) -#endif -void hpm_isr_usb0(void) -{ - g_usb_hpm_irq[0](g_usb_hpm_busid[0]); -} - -#ifdef HPM_USB1_BASE -#ifndef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER -SDK_DECLARE_EXT_ISR_M(IRQn_USB1, hpm_isr_usb1) -#endif -void hpm_isr_usb1(void) -{ - g_usb_hpm_irq[1](g_usb_hpm_busid[1]); -} -#endif - #ifdef CONFIG_USB_DCACHE_ENABLE void usb_dcache_clean(uintptr_t addr, size_t size) { @@ -67,4 +111,4 @@ void usb_dcache_flush(uintptr_t addr, size_t size) { l1c_dc_flush(addr, size); } -#endif \ No newline at end of file +#endif diff --git a/components/drivers/usb/cherryusb/port/hpmicro/usb_hc_hpm.c b/components/drivers/usb/cherryusb/port/hpmicro/usb_hc_hpm.c index 9ee515008b..2c340573ca 100644 --- a/components/drivers/usb/cherryusb/port/hpmicro/usb_hc_hpm.c +++ b/components/drivers/usb/cherryusb/port/hpmicro/usb_hc_hpm.c @@ -57,31 +57,29 @@ void usb_hc_low_level2_init(struct usbh_bus *bus) if (bus->hcd.reg_base == HPM_USB0_BASE) { g_usb_hpm_busid[0] = bus->hcd.hcd_id; g_usb_hpm_irq[0] = USBH_IRQHandler; - - hpm_usb_isr_enable(HPM_USB0_BASE); } else { #ifdef HPM_USB1_BASE g_usb_hpm_busid[1] = bus->hcd.hcd_id; g_usb_hpm_irq[1] = USBH_IRQHandler; - - hpm_usb_isr_enable(HPM_USB1_BASE); #endif } + +#ifdef CONFIG_USB_OTG_ENABLE + usb_otgsc_enable_id_chg_int((USB_Type *)(bus->hcd.reg_base)); +#endif + hpm_usb_isr_enable(bus->hcd.reg_base); } void usb_hc_low_level_deinit(struct usbh_bus *bus) { usb_phy_deinit((USB_Type *)(bus->hcd.reg_base)); + hpm_usb_isr_disable(bus->hcd.reg_base); if (bus->hcd.reg_base == HPM_USB0_BASE) { - hpm_usb_isr_disable(HPM_USB0_BASE); - g_usb_hpm_busid[0] = 0; g_usb_hpm_irq[0] = NULL; } else { #ifdef HPM_USB1_BASE - hpm_usb_isr_disable(HPM_USB1_BASE); - g_usb_hpm_busid[1] = 0; g_usb_hpm_irq[1] = NULL; #endif diff --git a/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c b/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c index 4ae73f1ca0..b3d767a0a4 100644 --- a/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c +++ b/components/drivers/usb/cherryusb/port/kinetis/usb_glue_mcx.c @@ -86,8 +86,8 @@ void usbd_kinetis_delay_ms(uint8_t ms) rt_thread_mdelay(ms); #else for (uint32_t i = 0; i < ms; i++) - { - for (volatile uint32_t j = 0; j < 10000; j++); + { + for (volatile uint32_t j = 0; j < 10000; j++); } #endif } \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/musb/usb_glue_sifli.c b/components/drivers/usb/cherryusb/port/musb/usb_glue_sifli.c index 106dc3a706..0019482055 100644 --- a/components/drivers/usb/cherryusb/port/musb/usb_glue_sifli.c +++ b/components/drivers/usb/cherryusb/port/musb/usb_glue_sifli.c @@ -17,7 +17,7 @@ #undef USB_POWER_RESUME #ifndef CONFIG_USB_MUSB_SIFLI -#error must define CONFIG_USB_MUSB_SIFLI when use sunxi chips +#error must define CONFIG_USB_MUSB_SIFLI when use sifli chips #endif #include "bf0_hal.h" diff --git a/components/drivers/usb/cherryusb/port/musb/usb_glue_ti.c b/components/drivers/usb/cherryusb/port/musb/usb_glue_ti.c new file mode 100644 index 0000000000..576a517f62 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/musb/usb_glue_ti.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2026, sakumisu + * Copyright (c) 2026, MDLZCOOL + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_musb_reg.h" + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ints.h" +#include "inc/hw_gpio.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_usb.h" +#include "driverlib/sysctl.h" +#include "driverlib/gpio.h" +#include "driverlib/interrupt.h" +#include "driverlib/pin_map.h" +#include "driverlib/rom.h" + +#define TM4C_MUSB_RAM_SIZE 4096 + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 256, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 128, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 64, }, +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 256, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 128, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 64, }, +}; +// clang-format on + +static void (*g_usb_irq_handler)(uint8_t busid) = NULL; + +extern void USBH_IRQHandler(uint8_t busid); +extern void USBD_IRQHandler(uint8_t busid); + +__WEAK void USBD_IRQHandler(uint8_t busid) +{ + (void)busid; +} + +__WEAK void USBH_IRQHandler(uint8_t busid) +{ + (void)busid; +} + +void USB0_Handler(void) +{ + if (g_usb_irq_handler) { + g_usb_irq_handler(0); + } +} + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return TM4C_MUSB_RAM_SIZE; +} + +void usbd_musb_delay_ms(uint8_t ms) +{ + /* implement later */ +} + +void usb_dc_low_level_init(void) +{ + SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_USB0)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOD)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOB)) + ; + + SysCtlPeripheralReset(SYSCTL_PERIPH_USB0); + for (volatile int i = 0; i < 1000; i++) + ; + + GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); + GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + HWREGB(USB0_BASE + USB_O_GPCS) = USB_GPCS_DEVMOD; + SysCtlUSBPLLEnable(); + + g_usb_irq_handler = USBD_IRQHandler; + + IntPrioritySet(INT_USB0, (6 << 5)); + IntEnable(INT_USB0); +} + +void usb_dc_low_level_deinit(void) +{ + IntDisable(INT_USB0); + g_usb_irq_handler = NULL; + SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_USB0)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOD)) + ; + while (!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOB)) + ; + + SysCtlPeripheralReset(SYSCTL_PERIPH_USB0); + for (volatile int i = 0; i < 1000; i++) + ; + + GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); + GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + HWREGB(USB0_BASE + USB_O_GPCS) &= ~(USB_GPCS_DEVMOD); + SysCtlUSBPLLEnable(); + + g_usb_irq_handler = USBH_IRQHandler; + + IntPrioritySet(INT_USB0, (6 << 5)); + IntEnable(INT_USB0); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + IntDisable(INT_USB0); + g_usb_irq_handler = NULL; + SysCtlPeripheralDisable(SYSCTL_PERIPH_USB0); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c b/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c index eea625cc73..26d2ce74ca 100644 --- a/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c +++ b/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c @@ -328,10 +328,16 @@ void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb speed = USB_TYPE0_SPEED_LOW; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + /* Without multipoint, use FADDR for host target addressing and do not access Hub/FuncAddr regs */ + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = speed; +#else HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_TXTYPE_BASE(chidx)) = speed; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif musb_write_packet(bus, chidx, (uint8_t *)setup, 8); HWREGB(USB_TXCSRL_BASE(chidx)) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; @@ -360,12 +366,19 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; +#else HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; +#endif HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; @@ -376,12 +389,19 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; +#else HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); @@ -419,12 +439,19 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; +#else HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; +#endif HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; @@ -435,12 +462,19 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; +#else HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); @@ -490,31 +524,36 @@ static uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) return speed; } -#if 0 -static int musb_pipe_alloc(void) +static int musb_pipe_alloc(struct usbh_bus *bus) { int chidx; + uintptr_t flags; + flags = usb_osal_enter_critical_section(); for (chidx = 1; chidx < CONFIG_USB_MUSB_PIPE_NUM; chidx++) { if (!g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse) { g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse = true; + usb_osal_leave_critical_section(flags); return chidx; } } + usb_osal_leave_critical_section(flags); return -1; } -#endif static void musb_pipe_free(struct musb_pipe *pipe) { + uintptr_t flags; + + flags = usb_osal_enter_critical_section(); if (pipe->urb) { pipe->urb->hcpriv = NULL; pipe->urb = NULL; } -#if 0 + pipe->inuse = false; -#endif + usb_osal_leave_critical_section(flags); } __WEAK void usb_hc_low_level_init(struct usbh_bus *bus) @@ -730,10 +769,9 @@ int usbh_submit_urb(struct usbh_urb *urb) if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { chidx = 0; } else { - chidx = (urb->ep->bEndpointAddress & 0x0f); - - if (chidx > (CONFIG_USB_MUSB_PIPE_NUM - 1)) { - return -USB_ERR_RANGE; + chidx = musb_pipe_alloc(bus); + if (chidx == -1) { + return -USB_ERR_NOMEM; } } @@ -839,8 +877,6 @@ static void musb_urb_waitup(struct usbh_urb *urb) struct musb_pipe *pipe; pipe = (struct musb_pipe *)urb->hcpriv; - pipe->urb = NULL; - urb->hcpriv = NULL; if (urb->timeout) { usb_osal_sem_give(pipe->waitsem); @@ -987,9 +1023,11 @@ void USBH_IRQHandler(uint8_t busid) bus = &g_usbhost_bus[busid]; +#if 0 if (!(HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_HOST)) { return; } +#endif is = HWREGB(USB_BASE + MUSB_IS_OFFSET); txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET); diff --git a/components/drivers/usb/cherryusb/tools/audacity/url b/components/drivers/usb/cherryusb/tools/audacity/url new file mode 100644 index 0000000000..4f690e4064 --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/audacity/url @@ -0,0 +1 @@ +https://audacity.onl/ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/tools/chryusb_configurator/url b/components/drivers/usb/cherryusb/tools/chryusb_configurator/url new file mode 100644 index 0000000000..ed063b5167 --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/chryusb_configurator/url @@ -0,0 +1 @@ +https://github.com/Egahp/chryusb_configurator/releases/tag/1.0.0 \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/tools/packet capture/url b/components/drivers/usb/cherryusb/tools/packet capture/url new file mode 100644 index 0000000000..a5fba08e60 --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/packet capture/url @@ -0,0 +1,3 @@ +QQ群内获取 + +Get it after joining the qq chat \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/tools/stm32_dfuse/url b/components/drivers/usb/cherryusb/tools/stm32_dfuse/url new file mode 100644 index 0000000000..808c6f7386 --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/stm32_dfuse/url @@ -0,0 +1 @@ +http://www.st.com/en/development-tools/stsw-stm32080.html \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/tools/test_srcipts/test_cdc_speed.py b/components/drivers/usb/cherryusb/tools/test_srcipts/test_cdc_speed.py new file mode 100644 index 0000000000..f11b70a4a2 --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/test_srcipts/test_cdc_speed.py @@ -0,0 +1,49 @@ +import serial +import time +try: + from serial.tools.list_ports import comports +except ImportError: + raise serial.serialutil.SerialException + + +test_comx = 'COM66' +test_baudrate = 2000000 +test_maxsize = 10*1024*1024 + +test_data = '0xAA' * 4096 + +test_serial = serial.Serial(test_comx, test_baudrate, timeout = 1) + +def test_cdc_out(): + send_count = 0 + begin = time.time() + + while True: + if send_count < test_maxsize: + txdatalen = test_serial.write(test_data.encode("utf-8")) + send_count += txdatalen + else: + print("cdc out speed %f MB/s" %(send_count//1024//1024/(time.time() - begin))) + break + +def test_cdc_in(): + read_count = 0 + begin = time.time() + + while True: + if read_count < test_maxsize: + data = test_serial.read(test_maxsize).decode(encoding='utf-8',errors='ignore') + read_count += len(data) + else: + print("cdc in speed %f MB/s" %(read_count//1024//1024/(time.time() - begin))) + break + +if __name__ == '__main__': + print('test cdc out speed') + + test_serial.setDTR(0) + test_cdc_out() + + print('test cdc in speed') + test_serial.setDTR(1) + test_cdc_in() \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/tools/test_srcipts/test_hid_inout.py b/components/drivers/usb/cherryusb/tools/test_srcipts/test_hid_inout.py new file mode 100644 index 0000000000..df512d24ef --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/test_srcipts/test_hid_inout.py @@ -0,0 +1,68 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import pywinusb.hid as hid +import os +import time +import sys +import operator + +# VID and PID customization changes here... + +VID = 0xFFFF +PID = 0xFFFF + +# Send buffer +buffer = [0xff]*64 + +# Const +TIMEOUT = -1 +PASS = 0 +FAIL = 1 + +# Result +result = TIMEOUT + +def search_dev(): + filter = hid.HidDeviceFilter(vendor_id = VID, product_id = PID) + hid_device = filter.get_devices() + return hid_device + +def recv_data(data): + print("<=================== USB HID Read ========================>") + for i in range(0, len(data)): + print("0x{0:02x}" .format(data[i]), end=" ") + print("\n") + + global result + result = (PASS if (operator.eq(data[1:-1], buffer[1:-1]) == True) else FAIL) + + return None + +def send_data(report): + print("<=================== USB HID Write ========================>") + buffer[0] = report[0].report_id + print("0x{0:02x}" .format(buffer[0]), end=" ") + + for i in range(1,64): + buffer[i] = i % 256 + print("0x{0:02x}" .format(buffer[i]), end=" ") + print("\n") + + report[0].set_raw_data(buffer) + report[0].send() + return None + +if __name__ == '__main__': + device = search_dev()[0] + device.open() + device.set_raw_data_handler(recv_data) + send_data(device.find_output_reports()) + time.sleep(1) + + if result == PASS: + print("USB hid echo passed!") + elif result == FAIL: + print("USB HID echo failed!") + else: + print("USB HID echo timed out!") \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/tools/uf2/uf2conv.py b/components/drivers/usb/cherryusb/tools/uf2/uf2conv.py new file mode 100644 index 0000000000..53c5e8bc6d --- /dev/null +++ b/components/drivers/usb/cherryusb/tools/uf2/uf2conv.py @@ -0,0 +1,361 @@ +#!/usr/bin/env python3 +import sys +import struct +import subprocess +import re +import os +import os.path +import argparse +import json +from time import sleep + + +UF2_MAGIC_START0 = 0x0A324655 # "UF2\n" +UF2_MAGIC_START1 = 0x9E5D5157 # Randomly selected +UF2_MAGIC_END = 0x0AB16F30 # Ditto + +INFO_FILE = "/INFO_UF2.TXT" + +appstartaddr = 0x2000 +familyid = 0x0 + + +def is_uf2(buf): + w = struct.unpack(" 476: + assert False, "Invalid UF2 data size at " + ptr + newaddr = hd[3] + if (hd[2] & 0x2000) and (currfamilyid == None): + currfamilyid = hd[7] + if curraddr == None or ((hd[2] & 0x2000) and hd[7] != currfamilyid): + currfamilyid = hd[7] + curraddr = newaddr + if familyid == 0x0 or familyid == hd[7]: + appstartaddr = newaddr + padding = newaddr - curraddr + if padding < 0: + assert False, "Block out of order at " + ptr + if padding > 10*1024*1024: + assert False, "More than 10M of padding needed at " + ptr + if padding % 4 != 0: + assert False, "Non-word padding size at " + ptr + while padding > 0: + padding -= 4 + outp.append(b"\x00\x00\x00\x00") + if familyid == 0x0 or ((hd[2] & 0x2000) and familyid == hd[7]): + outp.append(block[32 : 32 + datalen]) + curraddr = newaddr + datalen + if hd[2] & 0x2000: + if hd[7] in families_found.keys(): + if families_found[hd[7]] > newaddr: + families_found[hd[7]] = newaddr + else: + families_found[hd[7]] = newaddr + if prev_flag == None: + prev_flag = hd[2] + if prev_flag != hd[2]: + all_flags_same = False + if blockno == (numblocks - 1): + print("--- UF2 File Header Info ---") + families = load_families() + for family_hex in families_found.keys(): + family_short_name = "" + for name, value in families.items(): + if value == family_hex: + family_short_name = name + print("Family ID is {:s}, hex value is 0x{:08x}".format(family_short_name,family_hex)) + print("Target Address is 0x{:08x}".format(families_found[family_hex])) + if all_flags_same: + print("All block flag values consistent, 0x{:04x}".format(hd[2])) + else: + print("Flags were not all the same") + print("----------------------------") + if len(families_found) > 1 and familyid == 0x0: + outp = [] + appstartaddr = 0x0 + return b"".join(outp) + +def convert_to_carray(file_content): + outp = "const unsigned long bindata_len = %d;\n" % len(file_content) + outp += "const unsigned char bindata[] __attribute__((aligned(16))) = {" + for i in range(len(file_content)): + if i % 16 == 0: + outp += "\n" + outp += "0x%02x, " % file_content[i] + outp += "\n};\n" + return bytes(outp, "utf-8") + +def convert_to_uf2(file_content): + global familyid + datapadding = b"" + while len(datapadding) < 512 - 256 - 32 - 4: + datapadding += b"\x00\x00\x00\x00" + numblocks = (len(file_content) + 255) // 256 + outp = [] + for blockno in range(numblocks): + ptr = 256 * blockno + chunk = file_content[ptr:ptr + 256] + flags = 0x0 + if familyid: + flags |= 0x2000 + hd = struct.pack(b"= 3 and words[1] == "2" and words[2] == "FAT": + drives.append(words[0]) + else: + searchpaths = ["/media"] + if sys.platform == "darwin": + searchpaths = ["/Volumes"] + elif sys.platform == "linux": + searchpaths += ["/media/" + os.environ["USER"], '/run/media/' + os.environ["USER"]] + + for rootpath in searchpaths: + if os.path.isdir(rootpath): + for d in os.listdir(rootpath): + if os.path.isdir(rootpath): + drives.append(os.path.join(rootpath, d)) + + + def has_info(d): + try: + return os.path.isfile(d + INFO_FILE) + except: + return False + + return list(filter(has_info, drives)) + + +def board_id(path): + with open(path + INFO_FILE, mode='r') as file: + file_content = file.read() + return re.search(r"Board-ID: ([^\r\n]*)", file_content).group(1) + + +def list_drives(): + for d in get_drives(): + print(d, board_id(d)) + + +def write_file(name, buf): + with open(name, "wb") as f: + f.write(buf) + print("Wrote %d bytes to %s" % (len(buf), name)) + + +def load_families(): + # The expectation is that the `uf2families.json` file is in the same + # directory as this script. Make a path that works using `__file__` + # which contains the full path to this script. + filename = "uf2families.json" + pathname = os.path.join(os.path.dirname(os.path.abspath(__file__)), filename) + with open(pathname) as f: + raw_families = json.load(f) + + families = {} + for family in raw_families: + families[family["short_name"]] = int(family["id"], 0) + + return families + + +def main(): + global appstartaddr, familyid + def error(msg): + print(msg, file=sys.stderr) + sys.exit(1) + parser = argparse.ArgumentParser(description='Convert to UF2 or flash directly.') + parser.add_argument('input', metavar='INPUT', type=str, nargs='?', + help='input file (HEX, BIN or UF2)') + parser.add_argument('-b', '--base', dest='base', type=str, + default="0x2000", + help='set base address of application for BIN format (default: 0x2000)') + parser.add_argument('-f', '--family', dest='family', type=str, + default="0x0", + help='specify familyID - number or name (default: 0x0)') + parser.add_argument('-o', '--output', metavar="FILE", dest='output', type=str, + help='write output to named file; defaults to "flash.uf2" or "flash.bin" where sensible') + parser.add_argument('-d', '--device', dest="device_path", + help='select a device path to flash') + parser.add_argument('-l', '--list', action='store_true', + help='list connected devices') + parser.add_argument('-c', '--convert', action='store_true', + help='do not flash, just convert') + parser.add_argument('-D', '--deploy', action='store_true', + help='just flash, do not convert') + parser.add_argument('-w', '--wait', action='store_true', + help='wait for device to flash') + parser.add_argument('-C', '--carray', action='store_true', + help='convert binary file to a C array, not UF2') + parser.add_argument('-i', '--info', action='store_true', + help='display header information from UF2, do not convert') + args = parser.parse_args() + appstartaddr = int(args.base, 0) + + families = load_families() + + if args.family.upper() in families: + familyid = families[args.family.upper()] + else: + try: + familyid = int(args.family, 0) + except ValueError: + error("Family ID needs to be a number or one of: " + ", ".join(families.keys())) + + if args.list: + list_drives() + else: + if not args.input: + error("Need input file") + with open(args.input, mode='rb') as f: + inpbuf = f.read() + from_uf2 = is_uf2(inpbuf) + ext = "uf2" + if args.deploy: + outbuf = inpbuf + elif from_uf2 and not args.info: + outbuf = convert_from_uf2(inpbuf) + ext = "bin" + elif from_uf2 and args.info: + outbuf = "" + convert_from_uf2(inpbuf) + elif is_hex(inpbuf): + outbuf = convert_from_hex_to_uf2(inpbuf.decode("utf-8")) + elif args.carray: + outbuf = convert_to_carray(inpbuf) + ext = "h" + else: + outbuf = convert_to_uf2(inpbuf) + if not args.deploy and not args.info: + print("Converted to %s, output size: %d, start address: 0x%x" % + (ext, len(outbuf), appstartaddr)) + if args.convert or ext != "uf2": + if args.output == None: + args.output = "flash." + ext + if args.output: + write_file(args.output, outbuf) + if ext == "uf2" and not args.convert and not args.info: + drives = get_drives() + if len(drives) == 0: + if args.wait: + print("Waiting for drive to deploy...") + while len(drives) == 0: + sleep(0.1) + drives = get_drives() + elif not args.output: + error("No drive to deploy.") + for d in drives: + print("Flashing %s (%s)" % (d, board_id(d))) + write_file(d + "/NEW.UF2", outbuf) + + +if __name__ == "__main__": + main() \ No newline at end of file -- Gitee From 3e2d924e9dcc12aaeb44c97c5218fb67acc8c5ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=E2=80=86b=E2=80=86b666?= <64397326+Rbb666@users.noreply.github.com> Date: Wed, 28 Jan 2026 10:54:30 +0800 Subject: [PATCH 16/45] [driver/usb]Update dwc2/usb_glue_infineon.c to add the missing header file. (#11158) --- .../drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c index 19239ec891..c0956674c7 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c @@ -8,13 +8,13 @@ #include "usb_dwc2_param.h" #include "rtthread.h" #include "cybsp.h" +#include "cy_device.h" #if defined (COMPONENT_CM55) -#if defined(CONFIG_USB_DWC2_DMA_ENABLE) && !defined(CONFIG_USB_DCACHE_ENABLE) +#if !defined(CONFIG_USB_DCACHE_ENABLE) #error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" when using DMA" #endif - #else #define CONFIG_USB_DWC2_DMA_ENABLE #endif @@ -83,6 +83,8 @@ void usb_dc_low_level_init(uint8_t busid) USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); + rt_thread_mdelay(200); /* Wait for PHY stable */ + cy_stc_sysint_t usb_int_cfg = { .intrSrc = usbhs_interrupt_usbhsctrl_IRQn, .intrPriority = 3 @@ -120,6 +122,8 @@ void usb_hc_low_level_init(struct usbh_bus *bus) USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); + rt_thread_mdelay(200); /* Wait for PHY stable */ + cy_stc_sysint_t usb_int_cfg = { .intrSrc = usbhs_interrupt_usbhsctrl_IRQn, .intrPriority = 3 -- Gitee From c374aa2b19c1c52fdc7e497a3c196551362365c2 Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Tue, 27 Jan 2026 15:15:30 +0800 Subject: [PATCH 17/45] [bsp][nxp]:fix mcxa346 ci err --- .../.ci/attachconfig/ci.attachconfig.yml | 10 +- .../.cl/attachconfig/RTduino.attach | 14 -- bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig | 159 +++++++++--------- 3 files changed, 84 insertions(+), 99 deletions(-) delete mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml index a37fda0654..cac6fcae98 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.ci/attachconfig/ci.attachconfig.yml @@ -5,5 +5,11 @@ scons.args: &scons # ------ component CI ------ component.can: kconfig: - - CONFIG_BSP_USING_CAN - - CONFIG_BSP_USING_CAN0 + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN0=y + +# ------ Peripheral CI ------ +Peripheral.arduino: + kconfig: + - CONFIG_BSP_USING_ARDUINO=y + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach b/bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach deleted file mode 100644 index b546b5f2c7..0000000000 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/.cl/attachconfig/RTduino.attach +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_PKG_USING_RTDUINO=y -CONFIG_PKG_RTDUINO_PATH="/packages/arduino/RTduino" -CONFIG_RTDUINO_THREAD_SIZE=2048 -CONFIG_RTDUINO_THREAD_PRIO=30 -CONFIG_RTDUINO_SUPPORT_HIGH_PRECISION_MICROS=y -CONFIG_PKG_USING_RTDUINO_LATEST_VERSION=y -CONFIG_PKG_RTDUINO_VER="latest" -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C3=y -CONFIG_BSP_USING_SPI=y -CONFIG_BSP_USING_SPI1=y -CONFIG_BSP_USING_ADC=y -CONFIG_BSP_USING_PWM=y -CONFIG_BSP_USING_ARDUINO=y \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig index 5e2569c132..0820121fc5 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig @@ -20,55 +20,51 @@ menu "On-chip Peripheral Drivers" default y menuconfig BSP_USING_UART - config BSP_USING_UART - bool "Enable UART" - select RT_USING_UART - default y + bool "Enable UART" + select RT_USING_UART + default y - if BSP_USING_UART - config BSP_USING_UART2 - bool "Enable LPUART2 as defalt UART" - default y + if BSP_USING_UART + config BSP_USING_UART2 + bool "Enable LPUART2 as defalt UART" + default y - endif + endif menuconfig BSP_USING_I2C - config BSP_USING_I2C - bool "Enable I2C" - select RT_USING_I2C - default y + bool "Enable I2C" + select RT_USING_I2C + default y - if BSP_USING_I2C - config BSP_USING_I2C3 - bool "Enable Flexcomm3 I2C" - default y - endif + if BSP_USING_I2C + config BSP_USING_I2C3 + bool "Enable Flexcomm3 I2C" + default y + endif menuconfig BSP_USING_SPI - config BSP_USING_SPI - bool "Enable SPI" - select RT_USING_SPI - default y + bool "Enable SPI" + select RT_USING_SPI + default y - if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable LPSPI1" - default n - endif + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable LPSPI1" + default n + endif menuconfig BSP_USING_ADC - config BSP_USING_ADC - bool "Enable ADC Channel" - select RT_USING_ADC - default y + bool "Enable ADC Channel" + select RT_USING_ADC + default y - if BSP_USING_ADC - config BSP_USING_ADC0_CH22 - bool "Enable ADC0 Channel22" - default n + if BSP_USING_ADC + config BSP_USING_ADC0_CH22 + bool "Enable ADC0 Channel22" + default n - endif + endif config BSP_USING_RTC bool "Enable RTC" @@ -81,61 +77,58 @@ menu "On-chip Peripheral Drivers" default n menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER - bool "Enable Timer" - select RT_USING_HWTIMER - default y + bool "Enable Timer" + select RT_USING_HWTIMER + default y - if BSP_USING_HWTIMER - config BSP_USING_CTIMER0 - bool "Enable CIMER0" - default y + if BSP_USING_HWTIMER + config BSP_USING_CTIMER0 + bool "Enable CIMER0" + default y - config BSP_USING_CTIMER1 - bool "Enable CIMER1" - default n + config BSP_USING_CTIMER1 + bool "Enable CIMER1" + default n - config BSP_USING_CTIMER3 - bool "Enable CIMER3" - default n + config BSP_USING_CTIMER3 + bool "Enable CIMER3" + default n - config BSP_USING_CTIMER4 - bool "Enable CIMER4" - default n - endif + config BSP_USING_CTIMER4 + bool "Enable CIMER4" + default n + endif menuconfig BSP_USING_PWM - config BSP_USING_PWM - bool "Enable PWM" - select RT_USING_PWM - default n - - if BSP_USING_PWM - config BSP_USING_PWM0 - bool "Enable eFlex PWM0" - default n - config BSP_USING_PWM1 - bool "Enable eFlex PWM1" - default n - config BSP_USING_PWM2 - bool "Enable eFlex PWM2" - default n - endif + bool "Enable PWM" + select RT_USING_PWM + default n + + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable eFlex PWM0" + default n + config BSP_USING_PWM1 + bool "Enable eFlex PWM1" + default n + config BSP_USING_PWM2 + bool "Enable eFlex PWM2" + default n + endif menuconfig BSP_USING_CAN - config BSP_USING_CAN - bool "Enable CAN" - select RT_USING_CAN - default n - if BSP_USING_CAN - config BSP_USING_CAN0 - bool "Enable CAN0" - default n - - config BSP_USING_CAN1 - bool "Enable CAN1" - default n - endif + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + endif endmenu -- Gitee From f2a646cff4947bef7554ddbf443765e63d888d96 Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Thu, 29 Jan 2026 14:18:22 +0800 Subject: [PATCH 18/45] fix(cherryusb): fix dwc2 host size check Signed-off-by: sakumisu <1203593632@qq.com> --- .../drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c | 3 ++- components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c | 8 ++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c index c0956674c7..485b36c269 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c @@ -13,8 +13,9 @@ #if defined (COMPONENT_CM55) #if !defined(CONFIG_USB_DCACHE_ENABLE) -#error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" when using DMA" +#error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" for CM55" #endif + #else #define CONFIG_USB_DWC2_DMA_ENABLE #endif diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c b/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c index bf0adae571..92a7f3e027 100644 --- a/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c @@ -717,10 +717,10 @@ int usb_hc_init(struct usbh_bus *bus) USB_ASSERT_MSG((USB_OTG_GLB->GRXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_rx_fifo_size, "host_rx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->GRXFSIZ & 0xffff)); - USB_ASSERT_MSG((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size, - "host_nperio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ & 0xffff)); - USB_ASSERT_MSG((USB_OTG_GLB->HPTXFSIZ & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size, - "host_perio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)(USB_OTG_GLB->HPTXFSIZ & 0xffff)); + USB_ASSERT_MSG(((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16) & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_nperio_tx_fifo_size, + "host_nperio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)((USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16) & 0xffff)); + USB_ASSERT_MSG(((USB_OTG_GLB->HPTXFSIZ >> 16) & 0xffff) >= g_dwc2_hcd[bus->hcd.hcd_id].user_params.host_perio_tx_fifo_size, + "host_perio_tx_fifo_size cannot be larger than power_on_value %u", (unsigned int)((USB_OTG_GLB->HPTXFSIZ >> 16) & 0xffff)); /* B-peripheral session valid override enable */ USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; -- Gitee From 743b614875fc33257be47ab53b6c5e040ec27893 Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Sat, 31 Jan 2026 17:44:27 +0800 Subject: [PATCH 19/45] [components][clock_time] Refactor time subsystem around clock_time (#11111) * [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue --- bsp/ESP32_C3/README.md | 2 +- bsp/ESP32_C3/README_ZH.md | 2 +- bsp/ESP32_C3/drivers/Kconfig | 10 +- bsp/ESP32_C3/drivers/SConscript | 4 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 76 +-- .../drivers/{drv_hwtimer.h => drv_timer.h} | 10 +- bsp/Infineon/libraries/HAL_Drivers/SConscript | 2 +- .../{drv_hwtimer.c => drv_timer.c} | 76 +-- .../{drv_hwtimer.h => drv_timer.h} | 8 +- .../libraries/templates/PSOC62/board/Kconfig | 2 +- .../psoc6-cy8ckit-062-BLE/board/Kconfig | 2 +- .../psoc6-cy8ckit-062-WIFI-BT/board/Kconfig | 2 +- .../psoc6-cy8ckit-062S2-43012/board/Kconfig | 2 +- .../psoc6-cy8ckit-062s4/board/Kconfig | 2 +- .../psoc6-cy8cproto-062S3-4343W/board/Kconfig | 2 +- .../psoc6-evaluationkit-062S2/board/Kconfig | 2 +- bsp/Vango/v85xx/Kconfig | 40 +- bsp/Vango/v85xx/README.md | 2 +- bsp/Vango/v85xx/drivers/SConscript | 4 +- bsp/Vango/v85xx/drivers/drv_comm.h | 2 +- bsp/Vango/v85xxp/Kconfig | 24 +- bsp/Vango/v85xxp/README.md | 2 +- bsp/Vango/v85xxp/drivers/SConscript | 4 +- bsp/Vango/v85xxp/drivers/drv_comm.h | 2 +- bsp/acm32/acm32f0x0-nucleo/drivers/Kconfig | 14 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 60 +-- .../acm32f0x0-nucleo/drivers/tim_config.h | 2 +- bsp/acm32/acm32f0x0-nucleo/project.ewp | 4 +- bsp/acm32/acm32f0x0-nucleo/project.uvprojx | 8 +- bsp/acm32/acm32f4xx-nucleo/drivers/Kconfig | 20 +- .../air105/libraries/HAL_Driver/Inc/app_inc.h | 2 +- .../{core_hwtimer.h => core_clock_timer.h} | 4 +- .../libraries/HAL_Driver/Inc/resource_map.h | 2 +- .../{core_hwtimer.c => core_clock_timer.c} | 8 +- bsp/airm2m/air32f103/board/Kconfig | 2 +- bsp/airm2m/air32f103/board/board.c | 28 +- bsp/airm2m/air32f103/board/board.h | 2 +- bsp/airm2m/air32f103/libraries/SConscript | 2 +- .../rt_drivers/{drv_hwtimer.c => drv_timer.c} | 178 +++---- .../rt_drivers/{drv_hwtimer.h => drv_timer.h} | 20 +- bsp/allwinner/d1s/board/board.c | 5 + bsp/apm32/apm32e103ze-evalboard/board/Kconfig | 2 +- bsp/apm32/apm32e103ze-evalboard/board/board.h | 2 +- bsp/apm32/apm32e103ze-tinyboard/board/Kconfig | 2 +- bsp/apm32/apm32e103ze-tinyboard/board/board.h | 2 +- bsp/apm32/apm32f030r8-miniboard/board/Kconfig | 2 +- bsp/apm32/apm32f030r8-miniboard/board/board.h | 2 +- bsp/apm32/apm32f051r8-evalboard/board/Kconfig | 2 +- bsp/apm32/apm32f051r8-evalboard/board/board.h | 2 +- bsp/apm32/apm32f072vb-miniboard/board/Kconfig | 2 +- bsp/apm32/apm32f072vb-miniboard/board/board.h | 2 +- bsp/apm32/apm32f091vc-miniboard/board/Kconfig | 2 +- bsp/apm32/apm32f091vc-miniboard/board/board.h | 2 +- bsp/apm32/apm32f103vb-miniboard/board/Kconfig | 2 +- bsp/apm32/apm32f103vb-miniboard/board/board.h | 2 +- .../apm32f103xe-minibroard/board/Kconfig | 2 +- .../apm32f103xe-minibroard/board/board.h | 2 +- bsp/apm32/apm32f107vc-evalboard/board/Kconfig | 2 +- bsp/apm32/apm32f107vc-evalboard/board/board.h | 2 +- .../apm32f407ig-minibroard/board/Kconfig | 2 +- .../apm32f407ig-minibroard/board/board.h | 2 +- bsp/apm32/apm32f407zg-evalboard/board/Kconfig | 2 +- bsp/apm32/apm32f407zg-evalboard/board/board.h | 2 +- bsp/apm32/apm32s103vb-miniboard/board/Kconfig | 2 +- bsp/apm32/apm32s103vb-miniboard/board/board.h | 2 +- .../libraries/APM32E10x_Library/SConscript | 2 +- .../libraries/APM32F0xx_Library/SConscript | 2 +- .../libraries/APM32F10x_Library/SConscript | 2 +- .../libraries/APM32F4xx_Library/SConscript | 2 +- .../libraries/APM32S10x_Library/SConscript | 2 +- bsp/apm32/libraries/Drivers/SConscript | 4 +- .../Drivers/{drv_hwtimer.c => drv_timer.c} | 100 ++-- bsp/at32/at32a403a-start/README.md | 2 +- bsp/at32/at32a403a-start/board/Kconfig | 8 +- bsp/at32/at32a403a-start/board/src/at32_msp.c | 2 +- bsp/at32/at32a423-start/README.md | 2 +- bsp/at32/at32a423-start/board/Kconfig | 8 +- bsp/at32/at32a423-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f402-start/README.md | 2 +- bsp/at32/at32f402-start/board/Kconfig | 8 +- bsp/at32/at32f402-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f403a-start/README.md | 2 +- bsp/at32/at32f403a-start/board/Kconfig | 8 +- bsp/at32/at32f403a-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f405-start/README.md | 2 +- bsp/at32/at32f405-start/board/Kconfig | 8 +- bsp/at32/at32f405-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f407-start/README.md | 2 +- bsp/at32/at32f407-start/board/Kconfig | 8 +- bsp/at32/at32f407-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f413-start/README.md | 2 +- bsp/at32/at32f413-start/board/Kconfig | 8 +- bsp/at32/at32f413-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f415-start/README.md | 2 +- bsp/at32/at32f415-start/board/Kconfig | 8 +- bsp/at32/at32f415-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f421-start/README.md | 2 +- bsp/at32/at32f421-start/board/Kconfig | 8 +- bsp/at32/at32f421-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f423-start/README.md | 2 +- bsp/at32/at32f423-start/board/Kconfig | 8 +- bsp/at32/at32f423-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f425-start/README.md | 2 +- bsp/at32/at32f425-start/board/Kconfig | 8 +- bsp/at32/at32f425-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f435-start/README.md | 2 +- bsp/at32/at32f435-start/board/Kconfig | 8 +- bsp/at32/at32f435-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f437-start/README.md | 2 +- bsp/at32/at32f437-start/board/Kconfig | 8 +- bsp/at32/at32f437-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f455-start/README.md | 2 +- bsp/at32/at32f455-start/board/Kconfig | 8 +- bsp/at32/at32f455-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f456-start/README.md | 2 +- bsp/at32/at32f456-start/board/Kconfig | 8 +- bsp/at32/at32f456-start/board/src/at32_msp.c | 2 +- bsp/at32/at32f457-start/README.md | 2 +- bsp/at32/at32f457-start/board/Kconfig | 8 +- bsp/at32/at32f457-start/board/src/at32_msp.c | 2 +- bsp/at32/at32m412-start/README.md | 2 +- bsp/at32/at32m412-start/board/Kconfig | 8 +- bsp/at32/at32m412-start/board/src/at32_msp.c | 2 +- bsp/at32/at32m416-start/README.md | 2 +- bsp/at32/at32m416-start/board/Kconfig | 8 +- bsp/at32/at32m416-start/board/src/at32_msp.c | 2 +- bsp/at32/libraries/rt_drivers/SConscript | 4 +- .../rt_drivers/{drv_hwtimer.c => drv_timer.c} | 62 +-- .../rt_drivers/{drv_hwtimer.h => drv_timer.h} | 4 +- bsp/at91/at91sam9g45/project.ewp | 16 +- bsp/at91/at91sam9g45/project.uvproj | 16 +- bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig | 2 +- bsp/bluetrum/libraries/hal_drivers/SConscript | 4 +- .../libraries/hal_drivers/config/tim_config.h | 2 +- .../{drv_hwtimer.c => drv_timer.c} | 88 ++-- bsp/bouffalo_lab/README.md | 2 +- bsp/bouffalo_lab/README_en.md | 2 +- bsp/bouffalo_lab/libraries/Kconfig | 8 +- .../libraries/rt_drivers/SConscript | 6 +- .../rt_drivers/{drv_hwtimer.c => drv_timer.c} | 70 +-- .../rt_drivers/{drv_hwtimer.h => drv_timer.h} | 8 +- ...{hwtimer_sample.c => clock_timer_sample.c} | 36 +- bsp/cvitek/c906_little/board/Kconfig | 2 +- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 2 +- bsp/cvitek/drivers/drv_timer.c | 44 +- bsp/essemi/es32f0654/drivers/ES/Kconfig | 32 +- .../drivers/ES/es_conf_info_clock_timer.h} | 90 ++-- bsp/essemi/es32f0654/drivers/Kconfig | 4 +- bsp/essemi/es32f0654/drivers/SConscript | 22 +- bsp/essemi/es32f0654/drivers/drv_hwtimer.c | 453 ------------------ bsp/essemi/es32f0654/drivers/drv_timer.c | 453 ++++++++++++++++++ .../drivers/drv_timer.h} | 8 +- bsp/essemi/es32f365x/drivers/ES/Kconfig | 62 +-- .../drivers/ES/es_conf_info_clock_timer.h} | 90 ++-- bsp/essemi/es32f365x/drivers/Kconfig | 4 +- bsp/essemi/es32f365x/drivers/SConscript | 16 +- .../drivers/drv_timer.h} | 8 +- bsp/essemi/es32f369x/drivers/ES/Kconfig | 62 +-- .../drivers/ES/es_conf_info_clock_timer.h} | 90 ++-- bsp/essemi/es32f369x/drivers/Kconfig | 4 +- bsp/essemi/es32f369x/drivers/SConscript | 16 +- bsp/essemi/es32f369x/drivers/drv_hwtimer.c | 448 ----------------- bsp/essemi/es32f369x/drivers/drv_timer.c | 448 +++++++++++++++++ .../drivers/drv_timer.h} | 8 +- bsp/essemi/es32vf2264/drivers/ES/Kconfig | 40 +- .../drivers/ES/es_conf_info_clock_timer.h} | 90 ++-- bsp/essemi/es32vf2264/drivers/SConscript | 18 +- bsp/essemi/es32vf2264/drivers/board.h | 2 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 256 +++++----- .../drivers/drv_timer.h} | 8 +- .../libraries/FM33LC0xx_FL_Driver/SConscript | 2 +- .../libraries/HAL_Drivers/SConscript | 4 +- bsp/ft2004/libraries/SConscript | 2 +- bsp/gd32/arm/gd32103c-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32105c-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32105r-start/board/Kconfig | 2 +- bsp/gd32/arm/gd32107c-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32205r-start/board/Kconfig | 2 +- bsp/gd32/arm/gd32207i-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32303e-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32305r-start/board/Kconfig | 2 +- bsp/gd32/arm/gd32307e-start/board/Kconfig | 2 +- bsp/gd32/arm/gd32407v-lckfb/board/Kconfig | 2 +- bsp/gd32/arm/gd32407v-start/board/Kconfig | 2 +- bsp/gd32/arm/gd32450z-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32470i-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32470z-lckfb/board/Kconfig | 2 +- bsp/gd32/arm/gd32527I-eval/board/Kconfig | 2 +- bsp/gd32/arm/gd32e230-lckfb/board/Kconfig | 2 +- bsp/gd32/arm/gd32e503v-eval/board/Kconfig | 2 +- .../arm/libraries/gd32_drivers/SConscript | 4 +- .../{drv_hwtimer.c => drv_timer.c} | 178 +++---- .../risc-v/gd32vf103r-start/board/Kconfig | 2 +- bsp/gd32/risc-v/gd32vf103v-eval/board/Kconfig | 2 +- .../GD32VF103_Firmware_Library/SConscript | 2 +- .../risc-v/libraries/gd32_drivers/SConscript | 4 +- bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig | 6 +- .../ev_hc32f334_lqfp64/bsp_compile_ci.bat | 2 +- bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig | 8 +- .../ev_hc32f448_lqfp80/bsp_compile_ci.bat | 2 +- bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig | 6 +- .../ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat | 2 +- bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig | 8 +- .../ev_hc32f472_lqfp100/bsp_compile_ci.bat | 2 +- bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig | 6 +- .../ev_hc32f4a0_lqfp176/bsp_compile_ci.bat | 2 +- bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig | 6 +- .../ev_hc32f4a8_lqfp176/bsp_compile_ci.bat | 2 +- bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig | 6 +- bsp/hc32/libraries/hc32_drivers/SConscript | 4 +- .../{drv_hwtimer.c => drv_timer.c} | 140 +++--- bsp/hc32/tests/SConscript | 4 +- .../{test_hwtimer.c => test_clock_timer.c} | 46 +- bsp/hk32/hk32f030c8-mini/README.md | 2 +- bsp/hk32/hk32f030c8-mini/board/Kconfig | 8 +- bsp/hk32/libraries/rt_drivers/SConscript | 4 +- bsp/hpmicro/hpm5300evk/board/Kconfig | 2 +- bsp/hpmicro/hpm5300evk/board/board.c | 11 +- bsp/hpmicro/hpm5301evklite/board/Kconfig | 2 +- bsp/hpmicro/hpm5301evklite/board/board.c | 10 +- bsp/hpmicro/hpm5e00evk/board/Kconfig | 2 +- bsp/hpmicro/hpm5e00evk/board/board.c | 10 +- bsp/hpmicro/hpm6200evk/board/Kconfig | 2 +- bsp/hpmicro/hpm6200evk/board/board.c | 9 +- bsp/hpmicro/hpm6300evk/board/Kconfig | 2 +- bsp/hpmicro/hpm6300evk/board/board.c | 10 +- bsp/hpmicro/hpm6750evk/board/Kconfig | 2 +- bsp/hpmicro/hpm6750evk/board/board.c | 10 +- bsp/hpmicro/hpm6750evk2/board/Kconfig | 2 +- bsp/hpmicro/hpm6750evk2/board/board.c | 10 +- bsp/hpmicro/hpm6750evkmini/board/Kconfig | 2 +- bsp/hpmicro/hpm6750evkmini/board/board.c | 10 +- bsp/hpmicro/hpm6800evk/board/Kconfig | 2 +- bsp/hpmicro/hpm6800evk/board/board.c | 10 +- bsp/hpmicro/hpm6e00evk/board/Kconfig | 2 +- bsp/hpmicro/hpm6e00evk/board/board.c | 10 +- bsp/hpmicro/hpm6p00evk/board/Kconfig | 2 +- bsp/hpmicro/hpm6p00evk/board/board.c | 9 +- bsp/hpmicro/libraries/drivers/SConscript | 3 +- bsp/hpmicro/libraries/drivers/drv_delay.c | 14 + .../drivers/{drv_hwtimer.c => drv_timer.c} | 64 +-- .../drivers/{drv_hwtimer.h => drv_timer.h} | 8 +- bsp/k210/drivers/SConscript | 5 +- bsp/k230/board/Kconfig | 2 +- .../{hwtimer => clock_timer}/SConscript | 0 .../{hwtimer => clock_timer}/drv_timer.c | 62 +-- .../{hwtimer => clock_timer}/drv_timer.h | 4 +- bsp/k230/drivers/utest/test_timer.c | 32 +- bsp/mm32/libraries/MM32F3270_HAL/SConscript | 2 +- .../N32G43x_Firmware_Library/SConscript | 2 +- .../N32G45x_Firmware_Library/SConscript | 2 +- .../N32G4FR_Firmware_Library/SConscript | 2 +- .../N32L40x_Firmware_Library/SConscript | 2 +- .../N32L43x_Firmware_Library/SConscript | 2 +- .../N32WB452_Firmware_Library/SConscript | 2 +- bsp/n32/libraries/n32_drivers/SConscript | 4 +- .../{drv_hwtimer.c => drv_timer.c} | 196 ++++---- .../{drv_hwtimer.h => drv_timer.h} | 16 +- bsp/n32/n32g43xcl-stb/README.md | 2 +- bsp/n32/n32g43xcl-stb/board/Kconfig | 44 +- bsp/n32/n32g43xcl-stb/project.ewp | 4 +- bsp/n32/n32g43xcl-stb/project.uvprojx | 8 +- bsp/n32/n32g457qel-stb/README.md | 2 +- bsp/n32/n32g457qel-stb/board/Kconfig | 40 +- bsp/n32/n32g457qel-stb/project.ewp | 4 +- bsp/n32/n32g457qel-stb/project.uvprojx | 8 +- bsp/n32/n32g45xcl-stb/README.md | 2 +- bsp/n32/n32g45xcl-stb/board/Kconfig | 40 +- bsp/n32/n32g45xcl-stb/project.ewp | 4 +- bsp/n32/n32g45xcl-stb/project.uvprojx | 8 +- bsp/n32/n32g45xml-stb/README.md | 2 +- bsp/n32/n32g45xml-stb/board/Kconfig | 40 +- bsp/n32/n32g45xml-stb/project.ewp | 4 +- bsp/n32/n32g45xml-stb/project.uvprojx | 8 +- bsp/n32/n32g45xrl-stb/README.md | 2 +- bsp/n32/n32g45xrl-stb/board/Kconfig | 40 +- bsp/n32/n32g45xrl-stb/project.ewp | 4 +- bsp/n32/n32g45xrl-stb/project.uvprojx | 8 +- bsp/n32/n32g45xvl-stb/README.md | 2 +- bsp/n32/n32g45xvl-stb/board/Kconfig | 40 +- bsp/n32/n32g45xvl-stb/project.ewp | 4 +- bsp/n32/n32g45xvl-stb/project.uvprojx | 8 +- bsp/n32/n32g4frml-stb/board/Kconfig | 40 +- bsp/n32/n32g4frml-stb/project.ewp | 4 +- bsp/n32/n32g4frml-stb/project.uvprojx | 8 +- bsp/n32/n32l40xcl-stb/README.md | 2 +- bsp/n32/n32l40xcl-stb/board/Kconfig | 44 +- bsp/n32/n32l40xcl-stb/project.ewp | 4 +- bsp/n32/n32l40xcl-stb/project.uvprojx | 8 +- bsp/n32/n32l436-evb/README.md | 2 +- bsp/n32/n32l436-evb/board/Kconfig | 44 +- bsp/n32/n32l436-evb/project.ewp | 4 +- bsp/n32/n32l436-evb/project.uvprojx | 8 +- bsp/n32/n32l43xml-stb/README.md | 2 +- bsp/n32/n32l43xml-stb/board/Kconfig | 44 +- bsp/n32/n32l43xml-stb/project.ewp | 4 +- bsp/n32/n32l43xml-stb/project.uvprojx | 8 +- bsp/n32/n32l43xrl-stb/README.md | 2 +- bsp/n32/n32l43xrl-stb/board/Kconfig | 44 +- bsp/n32/n32l43xrl-stb/project.ewp | 4 +- bsp/n32/n32l43xrl-stb/project.uvprojx | 8 +- bsp/n32/n32wb45xl-evb/README.md | 2 +- bsp/n32/n32wb45xl-evb/board/Kconfig | 40 +- bsp/n32/n32wb45xl-evb/project.ewp | 4 +- bsp/n32/n32wb45xl-evb/project.uvprojx | 8 +- bsp/n32g452xx/Libraries/rt_drivers/SConscript | 4 +- .../rt_drivers/{drv_hwtimer.c => drv_timer.c} | 66 +-- .../rt_drivers/{drv_hwtimer.h => drv_timer.h} | 4 +- bsp/n32g452xx/n32g452xx-mini-system/README.md | 2 +- .../n32g452xx-mini-system/board/Kconfig | 8 +- .../n32g452xx-mini-system/board/msp/n32_msp.c | 26 +- bsp/nrf5x/libraries/drivers/SConscript | 2 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 54 +-- bsp/nrf5x/nrf52832/board/Kconfig | 2 +- bsp/nrf5x/nrf52840/board/Kconfig | 2 +- bsp/nrf5x/nrf5340/board/Kconfig | 2 +- bsp/nuclei/gd32vf103_rvstar/README.md | 4 +- bsp/nuclei/gd32vf103_rvstar/board/Kconfig | 20 +- bsp/nuclei/gd32vf103_rvstar/board/board.c | 8 +- .../gd32vf103/HAL_Drivers/SConscript | 4 +- .../{drv_hwtimer.c => drv_timer.c} | 156 +++--- .../{drv_hwtimer.h => drv_timer.h} | 12 +- bsp/nuvoton/libraries/m031/rtt_port/Kconfig | 8 +- .../libraries/m031/rtt_port/drv_timer.c | 58 +-- bsp/nuvoton/libraries/m2354/rtt_port/Kconfig | 12 +- .../libraries/m2354/rtt_port/drv_timer.c | 66 +-- bsp/nuvoton/libraries/m460/rtt_port/Kconfig | 8 +- .../libraries/m460/rtt_port/drv_timer.c | 48 +- bsp/nuvoton/libraries/m480/rtt_port/Kconfig | 8 +- .../libraries/m480/rtt_port/drv_timer.c | 58 +-- bsp/nuvoton/libraries/ma35/rtt_port/Kconfig | 24 +- .../libraries/ma35/rtt_port/drv_timer.c | 48 +- bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig | 16 +- .../libraries/n9h30/rtt_port/drv_etimer.c | 48 +- .../libraries/n9h30/rtt_port/drv_timer.c | 48 +- bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig | 10 +- .../libraries/nuc980/rtt_port/drv_etimer.c | 48 +- bsp/nuvoton/nk-980iot/config_lvgl | 5 +- bsp/nuvoton/nk-980iot/project.uvopt | 12 +- bsp/nuvoton/nk-980iot/project.uvoptx | 12 +- bsp/nuvoton/nk-980iot/project.uvproj | 12 +- bsp/nuvoton/nk-980iot/project.uvprojx | 12 +- bsp/nuvoton/nk-980iot/spinor.config | 5 +- bsp/nuvoton/nk-n9h30/project.uvopt | 4 +- bsp/nuvoton/nk-n9h30/project.uvproj | 4 +- bsp/nuvoton/nk-rtu980/project.uvopt | 12 +- bsp/nuvoton/nk-rtu980/project.uvproj | 12 +- bsp/nuvoton/numaker-iot-m467/config_lvgl | 3 +- bsp/nuvoton/numaker-iot-m467/project.ewp | 2 +- bsp/nuvoton/numaker-iot-m467/project.uvoptx | 4 +- bsp/nuvoton/numaker-iot-m467/project.uvprojx | 4 +- bsp/nuvoton/numaker-iot-m487/config_lvgl | 3 +- bsp/nuvoton/numaker-iot-m487/project.ewp | 2 +- bsp/nuvoton/numaker-iot-m487/project.uvoptx | 4 +- bsp/nuvoton/numaker-iot-m487/project.uvproj | 4 +- bsp/nuvoton/numaker-iot-m487/project.uvprojx | 4 +- bsp/nuvoton/numaker-m032ki/config_lvgl | 3 +- bsp/nuvoton/numaker-m032ki/project.ewp | 2 +- bsp/nuvoton/numaker-m032ki/project.uvoptx | 4 +- bsp/nuvoton/numaker-m032ki/project.uvprojx | 4 +- bsp/nuvoton/numaker-m2354/config_lvgl | 5 +- bsp/nuvoton/numaker-m2354/project.ewp | 2 +- bsp/nuvoton/numaker-m2354/project.uvoptx | 4 +- bsp/nuvoton/numaker-m2354/project.uvprojx | 4 +- bsp/nuvoton/numaker-m467hj/config_lvgl | 3 +- bsp/nuvoton/numaker-m467hj/project.ewp | 2 +- bsp/nuvoton/numaker-m467hj/project.uvoptx | 4 +- bsp/nuvoton/numaker-m467hj/project.uvprojx | 4 +- bsp/nuvoton/numaker-pfm-m487/config_lvgl | 3 +- bsp/nuvoton/numaker-pfm-m487/project.ewp | 2 +- bsp/nuvoton/numaker-pfm-m487/project.uvoptx | 4 +- bsp/nuvoton/numaker-pfm-m487/project.uvproj | 4 +- bsp/nuvoton/numaker-pfm-m487/project.uvprojx | 4 +- .../imx/imxrt/imxrt1021-nxp-evk/board/Kconfig | 8 +- .../imxrt/imxrt1052-fire-pro/board/Kconfig | 8 +- .../imx/imxrt/imxrt1052-fire-pro/project.ewt | 2 +- .../imx/imxrt/libraries/drivers/SConscript | 4 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 122 ++--- .../drivers/{drv_hwtimer.h => drv_timer.h} | 4 +- .../templates/imxrt1050xxx/board/Kconfig | 8 +- .../templates/imxrt1050xxx/project.ewp | 2 +- .../templates/imxrt1050xxx/project.uvoptx | 4 +- .../templates/imxrt1050xxx/project.uvprojx | 4 +- .../templates/imxrt1064xxx/project.ewp | 2 +- .../templates/imxrt1064xxx/project.uvoptx | 4 +- .../templates/imxrt1064xxx/project.uvprojx | 4 +- bsp/nxp/lpc/lpc178x/rtconfig.py | 2 +- bsp/nxp/lpc/lpc408x/drivers/Kconfig | 4 +- bsp/nxp/lpc/lpc408x/drivers/SConscript | 4 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 36 +- .../drivers/{drv_hwtimer.h => drv_timer.h} | 8 +- bsp/nxp/lpc/lpc408x/project.uvproj | 16 +- bsp/nxp/lpc/lpc408x/project.uvprojx | 16 +- .../lpc/lpc54608-LPCXpresso/project.uvprojx | 16 +- .../lpc/lpc55sxx/Libraries/drivers/SConscript | 4 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 110 ++--- .../drivers/{drv_hwtimer.h => drv_timer.h} | 8 +- .../template/lpc55s6xxxx/board/Kconfig | 8 +- .../template/lpc55s6xxxx/project.ewp | 4 +- .../template/lpc55s6xxxx/project.uvoptx | 8 +- .../template/lpc55s6xxxx/project.uvprojx | 8 +- .../lpc55sxx/lpc55s06_nxp_evk/board/Kconfig | 8 +- .../lpc55sxx/lpc55s16_nxp_evk/board/Kconfig | 8 +- .../lpc55sxx/lpc55s28_nxp_evk/board/Kconfig | 8 +- .../lpc55sxx/lpc55s36_nxp_evk/board/Kconfig | 8 +- .../lpc55sxx/lpc55s69_nxp_evk/board/Kconfig | 8 +- bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript | 4 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 108 ++--- bsp/nxp/mcx/mcxa/frdm-mcxa153/board/Kconfig | 8 +- bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx | 4 +- bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig | 8 +- bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx | 4 +- bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx | 4 +- bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig | 6 +- bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvoptx | 4 +- bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvprojx | 4 +- bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript | 3 - bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig | 6 +- bsp/nxp/mcx/mcxc/frdm-mcxc444/project.ewp | 2 +- bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx | 4 +- bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript | 3 - bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig | 8 +- bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx | 4 +- bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx | 4 +- bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript | 4 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 80 ++-- .../drivers/{drv_hwtimer.h => drv_timer.h} | 8 +- bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig | 6 +- bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewp | 2 +- bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvoptx | 4 +- bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx | 4 +- bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig | 6 +- bsp/nxp/mcx/mcxn/frdm-mcxn947/project.ewp | 2 +- bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx | 4 +- bsp/qemu-virt64-riscv/driver/board.c | 6 +- .../raspi3-32/applications/test_device.c | 26 +- bsp/raspberry-pi/raspi3-32/driver/Kconfig | 2 +- bsp/raspberry-pi/raspi3-32/driver/drv_timer.c | 50 +- bsp/raspberry-pi/raspi3-64/driver/Kconfig | 1 + bsp/raspberry-pi/raspi3-64/driver/drv_timer.c | 50 +- bsp/raspberry-pico/Drivers/SConscript | 4 +- .../Drivers/{drv_hwtimer.c => drv_timer.c} | 76 +-- .../Drivers/{drv_hwtimer.h => drv_timer.h} | 8 +- bsp/raspberry-pico/RP2040/board/Kconfig | 16 +- bsp/raspberry-pico/RP2350/board/Kconfig | 16 +- .../docs/Introduction_to_RA_Series_Drives.md | 2 +- .../libraries/HAL_Drivers/drivers/SConscript | 2 +- .../drivers/config/ra6e2/timer_config.h | 2 +- .../drivers/config/ra6m3/timer_config.h | 2 +- .../drivers/config/ra8/timer_config.h | 2 +- .../drivers/config/rzt/timer_config.h | 2 +- .../drivers/{drv_hwtimer.c => drv_timer.c} | 92 ++-- .../drivers/{drv_hwtimer.h => drv_timer.h} | 6 +- bsp/renesas/ra4m1-ek/board/Kconfig | 2 +- bsp/renesas/ra6m3-ek/board/Kconfig | 2 +- bsp/renesas/ra8p1-titan-board/README.md | 2 +- bsp/renesas/ra8p1-titan-board/README_zh.md | 2 +- bsp/renesas/ra8p1-titan-board/board/Kconfig | 2 +- bsp/renesas/rzn2l_etherkit/board/Kconfig | 2 +- bsp/renesas/rzn2l_rsk/board/Kconfig | 2 +- bsp/renesas/rzt2m_rsk/board/Kconfig | 2 +- bsp/rockchip/dm/hwtimer/Kconfig | 4 +- bsp/rockchip/dm/hwtimer/SConscript | 4 +- ...p_timer.c => clock_timer-rockchip_timer.c} | 155 ++++-- bsp/rockchip/rk3500/.config | 17 +- bsp/rockchip/rk3500/driver/board.c | 16 + bsp/rockchip/rk3500/rtconfig.h | 12 +- .../drivers/config/f0/tim_config.h | 2 +- .../drivers/config/f1/tim_config.h | 2 +- .../drivers/config/f2/tim_config.h | 2 +- .../drivers/config/f3/tim_config.h | 2 +- .../drivers/config/f4/tim_config.h | 2 +- .../drivers/config/f7/tim_config.h | 2 +- .../drivers/config/g0/tim_config.h | 2 +- .../drivers/config/g4/tim_config.h | 2 +- .../drivers/config/h7/lptim_config.h | 2 +- .../drivers/config/h7/tim_config.h | 2 +- .../drivers/config/l1/tim_config.h | 2 +- .../drivers/config/l4/tim_config.h | 2 +- .../drivers/config/l5/tim_config.h | 2 +- .../drivers/config/mp1/tim_config.h | 2 +- .../drivers/config/u5/tim_config.h | 2 +- .../drivers/config/wb/tim_config.h | 2 +- .../drivers/config/wl/tim_config.h | 4 +- .../libraries/HAL_Drivers/drivers/drv_lptim.c | 22 +- .../libraries/HAL_Drivers/drivers/drv_lptim.h | 2 +- .../libraries/HAL_Drivers/drivers/drv_pm.c | 2 +- .../libraries/HAL_Drivers/drivers/drv_tim.c | 104 ++-- bsp/stm32/libraries/STM32L1xx_HAL/SConscript | 2 +- .../templates/stm32f3xx/project.uvoptx | 8 +- .../templates/stm32l1xx/board/Kconfig | 2 +- .../templates/stm32wbxx/board/Kconfig | 2 +- .../libraries/templates/stm32xx_board_Kconfig | 2 +- bsp/stm32/stm32f072-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32f091-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32f103-100ask-pro/board/Kconfig | 2 +- bsp/stm32/stm32f103-atk-nano/board/Kconfig | 2 +- .../stm32f103-atk-warshipv3/board/Kconfig | 2 +- .../stm32f103-fire-arbitrary/board/Kconfig | 2 +- .../arduino_pinout/pins_arduino.h | 2 +- bsp/stm32/stm32f401-st-nucleo/board/Kconfig | 2 +- .../stm32f405zg-mini-template/board/Kconfig | 2 +- bsp/stm32/stm32f407-armfly-v5/board/Kconfig | 2 +- .../stm32f407-atk-explorer/board/Kconfig | 2 +- .../stm32f407-fk407m2-zgt6/board/Kconfig | 2 +- .../stm32f407-lckfb-skystar/board/Kconfig | 2 +- bsp/stm32/stm32f407-micu/board/Kconfig | 2 +- bsp/stm32/stm32f407-rt-spark/board/Kconfig | 2 +- bsp/stm32/stm32f411-atk-nano/board/Kconfig | 2 +- .../arduino_pinout/pins_arduino.h | 2 +- bsp/stm32/stm32f411-st-nucleo/board/Kconfig | 2 +- .../stm32f411-weact-blackpill/board/Kconfig | 2 +- .../arduino_pinout/pins_arduino.h | 2 +- bsp/stm32/stm32f412-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32f413-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32f429-armfly-v6/board/Kconfig | 2 +- bsp/stm32/stm32f429-atk-apollo/board/Kconfig | 2 +- .../stm32f429-fire-challenger/board/Kconfig | 2 +- .../arduino_pinout/pins_arduino.h | 2 +- bsp/stm32/stm32f469-st-disco/board/Kconfig | 2 +- bsp/stm32/stm32f723-st-disco/project.ewp | 2 +- bsp/stm32/stm32f723-st-disco/project.uvprojx | 4 +- bsp/stm32/stm32f746-st-disco/board/Kconfig | 2 +- bsp/stm32/stm32f746-st-disco/project.ewp | 2 +- bsp/stm32/stm32f746-st-disco/project.uvprojx | 4 +- bsp/stm32/stm32f746-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32f767-atk-apollo/board/Kconfig | 2 +- bsp/stm32/stm32g070-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32g071-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32g491-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32h743-openmv-h7plus/project.ewp | 2 +- .../stm32h743-openmv-h7plus/project.uvprojx | 4 +- bsp/stm32/stm32h750-artpi/board/Kconfig | 2 +- .../stm32l433-ali-startkit/board/Kconfig | 2 +- .../arduino_pinout/pins_arduino.h | 2 +- bsp/stm32/stm32l475-atk-pandora/board/Kconfig | 2 +- .../arduino_pinout/pins_arduino.h | 2 +- bsp/stm32/stm32l476-st-nucleo/board/Kconfig | 2 +- .../stm32l496-ali-developer/board/Kconfig | 2 +- .../.ci/attachconfig/ci.attachconfig.yml | 1 + bsp/stm32/stm32l496-st-nucleo/board/Kconfig | 2 +- bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig | 2 +- .../stm32mp157a-st-discovery/board/Kconfig | 2 +- .../board/ports/timer_sample.c | 32 +- bsp/stm32/stm32mp157a-st-ev1/board/Kconfig | 2 +- .../board/ports/timer_sample.c | 32 +- bsp/stm32/stm32wb55-st-nucleo/board/Kconfig | 2 +- .../libraries/SWM320_drivers/SConscript | 4 +- .../{drv_hwtimer.c => drv_timer.c} | 114 ++--- .../{drv_hwtimer.h => drv_timer.h} | 6 +- .../libraries/SWM341_drivers/SConscript | 4 +- .../{drv_hwtimer.c => drv_timer.c} | 136 +++--- .../{drv_hwtimer.h => drv_timer.h} | 6 +- bsp/synwit/swm320-mini/applications/main.c | 30 +- bsp/synwit/swm320-mini/board/Kconfig | 4 +- bsp/synwit/swm341-mini/applications/main.c | 24 +- bsp/synwit/swm341-mini/board/Kconfig | 4 +- bsp/tae32f5300/Libraries/SConscript | 2 +- bsp/tae32f5300/drivers/Kconfig | 2 +- bsp/tkm32F499/drivers/Kconfig | 2 +- bsp/tm4c123bsp/board/Kconfig | 2 +- bsp/tm4c123bsp/libraries/Drivers/SConscript | 4 +- .../libraries/TivaWare_C_series/SConscript | 2 +- bsp/ultrarisc/ur_dp1000_evb/board/board.c | 7 +- bsp/w60x/drivers/Kconfig | 8 +- bsp/w60x/drivers/SConscript | 2 +- bsp/w60x/drivers/drv_hw_timer.c | 54 +-- bsp/w60x/drivers/drv_hw_timer.h | 4 +- bsp/w60x/project.ewp | 2 +- bsp/w60x/project.uvprojx | 4 +- bsp/wch/arm/Libraries/ch32_drivers/SConscript | 8 +- ...wtimer_ch32f10x.c => drv_timer_ch32f10x.c} | 214 ++++----- ...wtimer_ch32f20x.c => drv_timer_ch32f20x.c} | 370 +++++++------- bsp/wch/arm/ch32f103c8-core/board/Kconfig | 44 +- bsp/wch/arm/ch32f103c8-core/board/board.c | 28 +- bsp/wch/arm/ch32f103c8-core/board/board.h | 4 +- bsp/wch/arm/ch32f10x_port_cn.md | 20 +- bsp/wch/arm/ch32f203r-evt/README.md | 2 +- bsp/wch/arm/ch32f203r-evt/board/Kconfig | 96 ++-- bsp/wch/arm/ch32f203r-evt/board/board.c | 68 +-- bsp/wch/arm/ch32f203r-evt/board/board.h | 4 +- bsp/wch/arm/ch32f203r-evt/project.uvprojx | 8 +- .../risc-v/Libraries/ch32_drivers/SConscript | 4 +- .../risc-v/Libraries/ch32_drivers/drv_pwm.h | 2 +- .../{drv_hwtimer.c => drv_timer.c} | 100 ++-- .../{drv_hwtimer.h => drv_timer.h} | 16 +- .../risc-v/Libraries/ch56x_drivers/SConscript | 2 +- .../Libraries/ch56x_drivers/ch56x_timer.c | 154 +++--- bsp/wch/risc-v/ch32v208w-r0/board/Kconfig | 104 ++-- bsp/wch/risc-v/ch32v307v-r1/board/Kconfig | 98 ++-- bsp/wch/risc-v/ch569w-evt/applications/test.c | 30 +- bsp/wch/risc-v/ch569w-evt/board/Kconfig | 2 +- bsp/wch/risc-v/yd-ch32v307vct6/board/Kconfig | 96 ++-- bsp/xuantie/virt64/c906/board/board.c | 6 +- bsp/zynqmp-r5-axu4ev/rtconfig.h | 6 +- components/drivers/Kconfig | 4 +- components/drivers/clock_time/Kconfig | 18 + components/drivers/clock_time/README.md | 39 ++ components/drivers/clock_time/README_zh.md | 28 ++ components/drivers/clock_time/SConscript | 42 ++ .../clock_time/arch/aarch64/cputimer.c | 59 +++ .../clock_time/arch/risc-v/virt64/cputimer.c | 63 +++ .../clock_boottime.c} | 52 +- .../hrtimer.c => clock_time/clock_hrtimer.c} | 221 ++++++--- .../clock_time_arm_arch.c} | 0 .../drivers/clock_time/clock_time_core.c | 232 +++++++++ .../hwtimer.c => clock_time/clock_timer.c} | 232 ++++++--- components/drivers/cputime/Kconfig | 34 -- components/drivers/cputime/SConscript | 18 - components/drivers/cputime/cputime.c | 116 ----- components/drivers/cputime/cputime_cortexm.c | 69 --- components/drivers/cputime/cputime_riscv.c | 37 -- components/drivers/cputime/cputimer.c | 339 ------------- components/drivers/hwtimer/Kconfig | 14 - components/drivers/hwtimer/SConscript | 18 - .../drivers/include/drivers/clock_time.h | 184 +++++++ .../drivers/include/drivers/core/master_id.h | 2 +- components/drivers/include/drivers/cputime.h | 38 -- components/drivers/include/drivers/cputimer.h | 48 -- components/drivers/include/drivers/hwtimer.h | 89 ---- components/drivers/include/rtdevice.h | 10 +- components/drivers/input/Kconfig | 2 +- components/drivers/input/input_uapi.c | 4 +- components/drivers/ktime/Kconfig | 3 - components/drivers/ktime/README.md | 63 --- components/drivers/ktime/SConscript | 24 - components/drivers/ktime/inc/ktime.h | 169 ------- .../drivers/ktime/src/aarch64/cputimer.c | 34 -- components/drivers/ktime/src/cputimer.c | 31 -- .../ktime/src/risc-v/virt64/cputimer.c | 35 -- components/drivers/pic/Kconfig | 2 +- components/drivers/pic/pic.c | 6 +- components/drivers/rtc/dev_soft_rtc.c | 22 +- components/libc/compilers/common/ctime.c | 76 +-- components/libc/posix/Kconfig | 4 +- .../lwp/arch/aarch64/common/vdso_data.c | 6 +- components/lwp/arch/risc-v/common/vdso_data.c | 6 +- .../6.components/device-driver/INDEX.md | 2 +- .../device-driver/clock_time/README.md | 89 ++++ .../device-driver/clock_time/README_zh.md | 78 +++ .../clock_time/clock_boottime.md | 87 ++++ .../clock_time/clock_boottime_zh.md | 78 +++ .../device-driver/clock_time/clock_hrtimer.md | 223 +++++++++ .../clock_time/clock_hrtimer_zh.md | 208 ++++++++ .../clock_time/clock_time_core.md | 274 +++++++++++ .../clock_time/clock_time_core_zh.md | 256 ++++++++++ .../hwtimer.md => clock_time/clock_timer.md} | 219 +++++++-- .../clock_time/clock_timer_zh.md | 370 ++++++++++++++ .../clock_time/figures/clock_time_arch.svg | 96 ++++ .../{hwtimer_test.c => clock_timer_test.c} | 24 +- libcpu/Kconfig | 2 +- libcpu/aarch64/common/SConscript | 2 +- libcpu/aarch64/common/gtimer.c | 8 +- libcpu/aarch64/common/setup.c | 24 +- libcpu/risc-v/common64/tick.c | 51 +- src/Kconfig | 2 +- src/utest/perf/Kconfig | 6 +- src/utest/perf/irq_latency_tc.c | 11 +- src/utest/perf/perf_tc.c | 20 +- src/utest/perf/perf_tc.h | 2 +- 660 files changed, 8461 insertions(+), 6713 deletions(-) rename bsp/ESP32_C3/drivers/{drv_hwtimer.c => drv_timer.c} (53%) rename bsp/ESP32_C3/drivers/{drv_hwtimer.h => drv_timer.h} (61%) rename bsp/Infineon/libraries/HAL_Drivers/{drv_hwtimer.c => drv_timer.c} (74%) rename bsp/Infineon/libraries/HAL_Drivers/{drv_hwtimer.h => drv_timer.h} (89%) rename bsp/acm32/acm32f0x0-nucleo/drivers/{drv_hwtimer.c => drv_timer.c} (77%) rename bsp/airm2m/air105/libraries/HAL_Driver/Inc/{core_hwtimer.h => core_clock_timer.h} (98%) rename bsp/airm2m/air105/libraries/HAL_Driver/Src/{core_hwtimer.c => core_clock_timer.c} (98%) rename bsp/airm2m/air32f103/libraries/rt_drivers/{drv_hwtimer.c => drv_timer.c} (37%) rename bsp/airm2m/air32f103/libraries/rt_drivers/{drv_hwtimer.h => drv_timer.h} (67%) rename bsp/apm32/libraries/Drivers/{drv_hwtimer.c => drv_timer.c} (84%) rename bsp/at32/libraries/rt_drivers/{drv_hwtimer.c => drv_timer.c} (80%) rename bsp/at32/libraries/rt_drivers/{drv_hwtimer.h => drv_timer.h} (95%) rename bsp/bluetrum/libraries/hal_drivers/{drv_hwtimer.c => drv_timer.c} (60%) rename bsp/bouffalo_lab/libraries/rt_drivers/{drv_hwtimer.c => drv_timer.c} (66%) rename bsp/bouffalo_lab/libraries/rt_drivers/{drv_hwtimer.h => drv_timer.h} (71%) rename bsp/bouffalo_lab/libraries/rt_drivers/sample/{hwtimer_sample.c => clock_timer_sample.c} (65%) rename bsp/essemi/{es32vf2264/drivers/ES/es_conf_info_hwtimer.h => es32f0654/drivers/ES/es_conf_info_clock_timer.h} (30%) delete mode 100644 bsp/essemi/es32f0654/drivers/drv_hwtimer.c create mode 100644 bsp/essemi/es32f0654/drivers/drv_timer.c rename bsp/essemi/{es32f365x/drivers/drv_hwtimer.h => es32f0654/drivers/drv_timer.h} (86%) rename bsp/essemi/{es32f369x/drivers/ES/es_conf_info_hwtimer.h => es32f365x/drivers/ES/es_conf_info_clock_timer.h} (30%) rename bsp/essemi/{es32f369x/drivers/drv_hwtimer.h => es32f365x/drivers/drv_timer.h} (86%) rename bsp/essemi/{es32f365x/drivers/ES/es_conf_info_hwtimer.h => es32f369x/drivers/ES/es_conf_info_clock_timer.h} (30%) delete mode 100644 bsp/essemi/es32f369x/drivers/drv_hwtimer.c create mode 100644 bsp/essemi/es32f369x/drivers/drv_timer.c rename bsp/essemi/{es32vf2264/drivers/drv_hwtimer.h => es32f369x/drivers/drv_timer.h} (86%) rename bsp/essemi/{es32f0654/drivers/ES/es_conf_info_hwtimer.h => es32vf2264/drivers/ES/es_conf_info_clock_timer.h} (30%) rename bsp/essemi/es32vf2264/drivers/{drv_hwtimer.c => drv_timer.c} (32%) rename bsp/essemi/{es32f0654/drivers/drv_hwtimer.h => es32vf2264/drivers/drv_timer.h} (86%) rename bsp/gd32/arm/libraries/gd32_drivers/{drv_hwtimer.c => drv_timer.c} (63%) rename bsp/hc32/libraries/hc32_drivers/{drv_hwtimer.c => drv_timer.c} (58%) rename bsp/hc32/tests/{test_hwtimer.c => test_clock_timer.c} (75%) create mode 100644 bsp/hpmicro/libraries/drivers/drv_delay.c rename bsp/hpmicro/libraries/drivers/{drv_hwtimer.c => drv_timer.c} (79%) rename bsp/hpmicro/libraries/drivers/{drv_hwtimer.h => drv_timer.h} (42%) rename bsp/k230/drivers/interdrv/{hwtimer => clock_timer}/SConscript (100%) rename bsp/k230/drivers/interdrv/{hwtimer => clock_timer}/drv_timer.c (84%) rename bsp/k230/drivers/interdrv/{hwtimer => clock_timer}/drv_timer.h (98%) rename bsp/n32/libraries/n32_drivers/{drv_hwtimer.c => drv_timer.c} (66%) rename bsp/n32/libraries/n32_drivers/{drv_hwtimer.h => drv_timer.h} (64%) rename bsp/n32g452xx/Libraries/rt_drivers/{drv_hwtimer.c => drv_timer.c} (77%) rename bsp/n32g452xx/Libraries/rt_drivers/{drv_hwtimer.h => drv_timer.h} (96%) rename bsp/nrf5x/libraries/drivers/{drv_hwtimer.c => drv_timer.c} (80%) rename bsp/nuclei/libraries/gd32vf103/HAL_Drivers/{drv_hwtimer.c => drv_timer.c} (46%) rename bsp/nuclei/libraries/gd32vf103/HAL_Drivers/{drv_hwtimer.h => drv_timer.h} (68%) rename bsp/nxp/imx/imxrt/libraries/drivers/{drv_hwtimer.c => drv_timer.c} (58%) rename bsp/nxp/imx/imxrt/libraries/drivers/{drv_hwtimer.h => drv_timer.h} (83%) rename bsp/nxp/lpc/lpc408x/drivers/{drv_hwtimer.c => drv_timer.c} (70%) rename bsp/nxp/lpc/lpc408x/drivers/{drv_hwtimer.h => drv_timer.h} (63%) rename bsp/nxp/lpc/lpc55sxx/Libraries/drivers/{drv_hwtimer.c => drv_timer.c} (52%) rename bsp/nxp/lpc/lpc55sxx/Libraries/drivers/{drv_hwtimer.h => drv_timer.h} (91%) rename bsp/nxp/mcx/mcxa/Libraries/drivers/{drv_hwtimer.c => drv_timer.c} (59%) rename bsp/nxp/mcx/mcxn/Libraries/drivers/{drv_hwtimer.c => drv_timer.c} (50%) rename bsp/nxp/mcx/mcxn/Libraries/drivers/{drv_hwtimer.h => drv_timer.h} (66%) rename bsp/raspberry-pico/Drivers/{drv_hwtimer.c => drv_timer.c} (57%) rename bsp/raspberry-pico/Drivers/{drv_hwtimer.h => drv_timer.h} (67%) rename bsp/renesas/libraries/HAL_Drivers/drivers/{drv_hwtimer.c => drv_timer.c} (69%) rename bsp/renesas/libraries/HAL_Drivers/drivers/{drv_hwtimer.h => drv_timer.h} (85%) rename bsp/rockchip/dm/hwtimer/{hwtimer-rockchip_timer.c => clock_timer-rockchip_timer.c} (62%) mode change 100755 => 100644 rename bsp/synwit/libraries/SWM320_drivers/{drv_hwtimer.c => drv_timer.c} (59%) rename bsp/synwit/libraries/SWM320_drivers/{drv_hwtimer.h => drv_timer.h} (75%) rename bsp/synwit/libraries/SWM341_drivers/{drv_hwtimer.c => drv_timer.c} (70%) rename bsp/synwit/libraries/SWM341_drivers/{drv_hwtimer.h => drv_timer.h} (72%) rename bsp/wch/arm/Libraries/ch32_drivers/{drv_hwtimer_ch32f10x.c => drv_timer_ch32f10x.c} (36%) rename bsp/wch/arm/Libraries/ch32_drivers/{drv_hwtimer_ch32f20x.c => drv_timer_ch32f20x.c} (32%) rename bsp/wch/risc-v/Libraries/ch32_drivers/{drv_hwtimer.c => drv_timer.c} (76%) rename bsp/wch/risc-v/Libraries/ch32_drivers/{drv_hwtimer.h => drv_timer.h} (94%) create mode 100644 components/drivers/clock_time/Kconfig create mode 100644 components/drivers/clock_time/README.md create mode 100644 components/drivers/clock_time/README_zh.md create mode 100644 components/drivers/clock_time/SConscript create mode 100644 components/drivers/clock_time/arch/aarch64/cputimer.c create mode 100644 components/drivers/clock_time/arch/risc-v/virt64/cputimer.c rename components/drivers/{ktime/src/boottime.c => clock_time/clock_boottime.c} (33%) rename components/drivers/{ktime/src/hrtimer.c => clock_time/clock_hrtimer.c} (57%) rename components/drivers/{hwtimer/hwtimer-arm_arch.c => clock_time/clock_time_arm_arch.c} (100%) create mode 100644 components/drivers/clock_time/clock_time_core.c rename components/drivers/{hwtimer/hwtimer.c => clock_time/clock_timer.c} (52%) delete mode 100644 components/drivers/cputime/Kconfig delete mode 100644 components/drivers/cputime/SConscript delete mode 100644 components/drivers/cputime/cputime.c delete mode 100644 components/drivers/cputime/cputime_cortexm.c delete mode 100644 components/drivers/cputime/cputime_riscv.c delete mode 100644 components/drivers/cputime/cputimer.c delete mode 100644 components/drivers/hwtimer/Kconfig delete mode 100644 components/drivers/hwtimer/SConscript create mode 100644 components/drivers/include/drivers/clock_time.h delete mode 100644 components/drivers/include/drivers/cputime.h delete mode 100644 components/drivers/include/drivers/cputimer.h delete mode 100644 components/drivers/include/drivers/hwtimer.h delete mode 100644 components/drivers/ktime/Kconfig delete mode 100644 components/drivers/ktime/README.md delete mode 100644 components/drivers/ktime/SConscript delete mode 100644 components/drivers/ktime/inc/ktime.h delete mode 100644 components/drivers/ktime/src/aarch64/cputimer.c delete mode 100644 components/drivers/ktime/src/cputimer.c delete mode 100644 components/drivers/ktime/src/risc-v/virt64/cputimer.c create mode 100644 documentation/6.components/device-driver/clock_time/README.md create mode 100644 documentation/6.components/device-driver/clock_time/README_zh.md create mode 100644 documentation/6.components/device-driver/clock_time/clock_boottime.md create mode 100644 documentation/6.components/device-driver/clock_time/clock_boottime_zh.md create mode 100644 documentation/6.components/device-driver/clock_time/clock_hrtimer.md create mode 100644 documentation/6.components/device-driver/clock_time/clock_hrtimer_zh.md create mode 100644 documentation/6.components/device-driver/clock_time/clock_time_core.md create mode 100644 documentation/6.components/device-driver/clock_time/clock_time_core_zh.md rename documentation/6.components/device-driver/{hwtimer/hwtimer.md => clock_time/clock_timer.md} (64%) create mode 100644 documentation/6.components/device-driver/clock_time/clock_timer_zh.md create mode 100644 documentation/6.components/device-driver/clock_time/figures/clock_time_arch.svg rename examples/test/{hwtimer_test.c => clock_timer_test.c} (80%) diff --git a/bsp/ESP32_C3/README.md b/bsp/ESP32_C3/README.md index 474f5da46b..5f61eff7d4 100644 --- a/bsp/ESP32_C3/README.md +++ b/bsp/ESP32_C3/README.md @@ -47,7 +47,7 @@ Each peripheral supporting condition for this BSP is as follows: | WIFI | Partial support | There are currently some problems, such as `rt_mq_recive` cannot be used in ISR, etc. | | BLE | Partially supported | There are currently some problems, such as `NimBLE` running errors after starting for a while | | GDBStub | Support | You can use the GDB provided by ESP-IDF by turning on the `BSP_ENABLE_GDBSTUB` switch, which will enter GDB mode after a chip error | -| HWTIMER | Support | +| CLOCK_TIMER | Support | Note: 1. WIFI and BLE cannot be enabled at the same time. When using the BLE driver, be sure to turn off the `RT_USING_WIFI` and `LWIP` switches in `menuconfig`. In addition, due to limited capabilities and lack of debugging equipment, there are problems with WIFI and BLE driver operation. If it can be solved, please contact [timwcx@qq.com](mailto:timwcx@qq.com). diff --git a/bsp/ESP32_C3/README_ZH.md b/bsp/ESP32_C3/README_ZH.md index 967d82baa3..c0014ac86f 100644 --- a/bsp/ESP32_C3/README_ZH.md +++ b/bsp/ESP32_C3/README_ZH.md @@ -54,7 +54,7 @@ | WIFI | 部分支持 | 目前存在一些问题，例如不能在ISR中使用`rt_mq_recive`等 | | BLE | 部分支持 | 目前存在一些问题，例如`NimBLE`启动一段时间后运行错误 | | GDBStub | 支持 | 通过开启`BSP_ENABLE_GDBSTUB`开关即可使用ESP-IDF所提供的GDB，其会在芯片出错后进入GDB模式 | -| HWTIMER | 支持 | +| CLOCK_TIMER | 支持 | 注： 1、WIFI和BLE不能同时启用，在使用BLE驱动时注意在`menuconfig`中关闭`RT_USING_WIFI`和`LWIP`开关。另外由于能力有限且缺乏调试设备，WIFI和BLE驱动运行都有问题，如果可以解决联系[timwcx@qq.com](mailto:timwcx@qq.com)。 diff --git a/bsp/ESP32_C3/drivers/Kconfig b/bsp/ESP32_C3/drivers/Kconfig index 2d6c4326e9..b7cb8f1275 100644 --- a/bsp/ESP32_C3/drivers/Kconfig +++ b/bsp/ESP32_C3/drivers/Kconfig @@ -115,13 +115,13 @@ menu "On-chip Peripheral Drivers" bool "Enable BLE" default n - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" - select RT_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_TIMER0 - bool "Enable HWTIMER0" + bool "Enable CLOCK_TIMER0" default n endif diff --git a/bsp/ESP32_C3/drivers/SConscript b/bsp/ESP32_C3/drivers/SConscript index 55e9a09d1d..74d91cca65 100644 --- a/bsp/ESP32_C3/drivers/SConscript +++ b/bsp/ESP32_C3/drivers/SConscript @@ -24,8 +24,8 @@ if GetDepend('BSP_USING_SW_I2C'): if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend('BSP_USING_WIFI'): src += ['drv_wifi.c'] diff --git a/bsp/ESP32_C3/drivers/drv_hwtimer.c b/bsp/ESP32_C3/drivers/drv_timer.c similarity index 53% rename from bsp/ESP32_C3/drivers/drv_hwtimer.c rename to bsp/ESP32_C3/drivers/drv_timer.c index 63d33d9a91..7c0766e609 100644 --- a/bsp/ESP32_C3/drivers/drv_hwtimer.c +++ b/bsp/ESP32_C3/drivers/drv_timer.c @@ -8,24 +8,24 @@ * 2023-11-15 BetMul first version */ -#include "drv_hwtimer.h" +#include "drv_timer.h" #include #include #include "driver/gptimer.h" #include "sdkconfig.h" -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME /** - * handle interrupt for hwtimer. + * handle interrupt for clock_timer. */ -static bool mcu_hwtimer_intr_handler(gptimer_handle_t gptimer, const gptimer_alarm_event_data_t *edata, void *user_ctx) +static bool mcu_clock_timer_intr_handler(gptimer_handle_t gptimer, const gptimer_alarm_event_data_t *edata, void *user_ctx) { rt_interrupt_enter(); - rt_hwtimer_t *hwtimer = (rt_hwtimer_t *)user_ctx; - rt_device_hwtimer_isr(hwtimer); + rt_clock_timer_t *clock_timer = (rt_clock_timer_t *)user_ctx; + rt_clock_timer_isr(clock_timer); rt_interrupt_leave(); @@ -33,9 +33,9 @@ static bool mcu_hwtimer_intr_handler(gptimer_handle_t gptimer, const gptimer_ala } /** - * init the hwtimer + * init the clock_timer */ -static void mcu_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void mcu_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; @@ -44,15 +44,15 @@ static void mcu_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) } /** - * start the hwtimer, change status into running + * start the clock_timer, change status into running */ -static rt_err_t mcu_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t mcu_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; gptimer_alarm_config_t alarm_config = { .alarm_count = cnt, }; - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { } @@ -68,9 +68,9 @@ static rt_err_t mcu_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim } /** - * stop the hwtimer, change the status from running into enable + * stop the clock_timer, change the status from running into enable */ -static void mcu_hwtimer_stop(rt_hwtimer_t *timer) +static void mcu_clock_timer_stop(rt_clock_timer_t *timer) { gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; @@ -80,7 +80,7 @@ static void mcu_hwtimer_stop(rt_hwtimer_t *timer) /** * get count */ -static rt_uint32_t mcu_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t mcu_clock_timer_count_get(rt_clock_timer_t *timer) { gptimer_handle_t gptimer = (gptimer_handle_t)timer->parent.user_data; // get count number @@ -90,53 +90,53 @@ static rt_uint32_t mcu_hwtimer_count_get(rt_hwtimer_t *timer) } /** - * control the hwtimer + * control the clock_timer */ -static rt_err_t mcu_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t mcu_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: err = -RT_ERROR; break; - case HWTIMER_CTRL_INFO_GET: + case CLOCK_TIMER_CTRL_INFO_GET: err = -RT_ERROR; break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: timer->mode = *(rt_uint32_t *)args; break; - case HWTIMER_CTRL_STOP: - mcu_hwtimer_stop(timer); + case CLOCK_TIMER_CTRL_STOP: + mcu_clock_timer_stop(timer); break; } return err; } -static struct rt_hwtimer_device _hwtimer; -static const struct rt_hwtimer_ops _hwtimer_ops = +static struct rt_clock_timer_device _clock_timer; +static const struct rt_clock_timer_ops _clock_timer_ops = { - .init = mcu_hwtimer_init, - .start = mcu_hwtimer_start, - .stop = mcu_hwtimer_stop, - .count_get = mcu_hwtimer_count_get, - .control = mcu_hwtimer_control}; + .init = mcu_clock_timer_init, + .start = mcu_clock_timer_start, + .stop = mcu_clock_timer_stop, + .count_get = mcu_clock_timer_count_get, + .control = mcu_clock_timer_control}; -static const struct rt_hwtimer_info _hwtimer_info = +static const struct rt_clock_timer_info _clock_timer_info = { // TODO:what is the true max and min? .maxfreq = 1000000UL, .minfreq = 1000000UL, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_MODE_ONESHOT}; + .cntmode = CLOCK_TIMER_MODE_ONESHOT}; -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { char *name = "timer0"; @@ -149,18 +149,18 @@ int rt_hw_hwtimer_init(void) }; gptimer_event_callbacks_t cbs = { - .on_alarm = mcu_hwtimer_intr_handler, + .on_alarm = mcu_clock_timer_intr_handler, }; ESP_ERROR_CHECK(gptimer_new_timer(&timer_config, &gptimer)); - ESP_ERROR_CHECK(gptimer_register_event_callbacks(gptimer, &cbs, &_hwtimer)); + ESP_ERROR_CHECK(gptimer_register_event_callbacks(gptimer, &cbs, &_clock_timer)); - _hwtimer.info = &_hwtimer_info; - _hwtimer.ops = &_hwtimer_ops; + _clock_timer.info = &_clock_timer_info; + _clock_timer.ops = &_clock_timer_ops; - return rt_device_hwtimer_register(&_hwtimer, name, (void *)gptimer); + return rt_clock_timer_register(&_clock_timer, name, (void *)gptimer); } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); -#endif /* RT_USING_HWTIMER */ +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/ESP32_C3/drivers/drv_hwtimer.h b/bsp/ESP32_C3/drivers/drv_timer.h similarity index 61% rename from bsp/ESP32_C3/drivers/drv_hwtimer.h rename to bsp/ESP32_C3/drivers/drv_timer.h index a5a62fe003..87a1ee495c 100644 --- a/bsp/ESP32_C3/drivers/drv_hwtimer.h +++ b/bsp/ESP32_C3/drivers/drv_timer.h @@ -7,14 +7,14 @@ * Date Author Notes * 2023-11-15 BetMul first version */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include -#ifdef RT_USING_HWTIMER -int rt_hw_hwtimer_init(void); +#ifdef RT_USING_CLOCK_TIME +int rt_hw_clock_timer_init(void); #endif -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/Infineon/libraries/HAL_Drivers/SConscript b/bsp/Infineon/libraries/HAL_Drivers/SConscript index 2b7bb6f2e7..017b3cb4d7 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/SConscript +++ b/bsp/Infineon/libraries/HAL_Drivers/SConscript @@ -57,7 +57,7 @@ if GetDepend(['RT_USING_DAC']): src += ['drv_dac.c'] if GetDepend(['BSP_USING_TIM']): - src += ['drv_hwtimer.c'] + src += ['drv_timer.c'] if GetDepend(['BSP_USING_ETH']): src += ['drv_eth.c'] diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/Infineon/libraries/HAL_Drivers/drv_timer.c similarity index 74% rename from bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.c rename to bsp/Infineon/libraries/HAL_Drivers/drv_timer.c index 722c420cc5..946885686f 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.c +++ b/bsp/Infineon/libraries/HAL_Drivers/drv_timer.c @@ -8,18 +8,18 @@ * 2022-07-29 rtthread qiu first version */ #include "drv_common.h" -#include "drv_hwtimer.h" +#include "drv_timer.h" #include #ifdef BSP_USING_TIM /*#define DRV_DEBUG*/ -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include static void isr_timer(void *callback_arg, cyhal_timer_event_t event); -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME enum { #ifdef BSP_USING_TIM1 @@ -30,15 +30,15 @@ enum #endif }; -struct cyp_hwtimer +struct cyp_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; cyhal_timer_t tim_handle; IRQn_Type tim_irqn; char *name; }; -static struct cyp_hwtimer cyp_hwtimer_obj[] = +static struct cyp_clock_timer cyp_clock_timer_obj[] = { #ifdef BSP_USING_TIM1 TIM1_CONFIG, @@ -48,7 +48,7 @@ static struct cyp_hwtimer cyp_hwtimer_obj[] = #endif }; -static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { RT_ASSERT(timer != RT_NULL); @@ -98,7 +98,7 @@ static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { RT_ASSERT(timer != RT_NULL); RT_ASSERT(opmode != RT_NULL); @@ -122,7 +122,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ duration */ cyhal_timer_configure(tim, &init_timer_cfg); - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ cyhal_timer_stop(tim); @@ -148,7 +148,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ return result; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -160,7 +160,7 @@ static void timer_stop(rt_hwtimer_t *timer) cyhal_timer_stop(tim); } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { cyhal_timer_t *tim = RT_NULL; @@ -175,7 +175,7 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) return count; } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { RT_ASSERT(timer != RT_NULL); RT_ASSERT(arg != RT_NULL); @@ -188,7 +188,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint16_t val; @@ -213,9 +213,9 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -232,79 +232,79 @@ static void isr_timer(void *callback_arg, cyhal_timer_event_t event) (void)callback_arg; (void)event; #ifdef BSP_USING_TIM1 - rt_device_hwtimer_isr(&cyp_hwtimer_obj[TIM1_INDEX].time_device); + rt_clock_timer_isr(&cyp_clock_timer_obj[TIM1_INDEX].time_device); #endif #ifdef BSP_USING_TIM2 - rt_device_hwtimer_isr(&cyp_hwtimer_obj[TIM2_INDEX].time_device); + rt_clock_timer_isr(&cyp_clock_timer_obj[TIM2_INDEX].time_device); #endif /* leave interrupt */ rt_interrupt_leave(); } -int cyp_hwtimer_init(void) +int cyp_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(cyp_hwtimer_obj) / sizeof(cyp_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(cyp_clock_timer_obj) / sizeof(cyp_clock_timer_obj[0]); i++) { - cyp_hwtimer_obj[i].time_device.info = &_info; - cyp_hwtimer_obj[i].time_device.ops = &_ops; - if (rt_device_hwtimer_register(&cyp_hwtimer_obj[i].time_device, cyp_hwtimer_obj[i].name, &cyp_hwtimer_obj[i].tim_handle) != RT_EOK) + cyp_clock_timer_obj[i].time_device.info = &_info; + cyp_clock_timer_obj[i].time_device.ops = &_ops; + if (rt_clock_timer_register(&cyp_clock_timer_obj[i].time_device, cyp_clock_timer_obj[i].name, &cyp_clock_timer_obj[i].tim_handle) != RT_EOK) { - LOG_E("%s register failed", cyp_hwtimer_obj[i].name); + LOG_E("%s register failed", cyp_clock_timer_obj[i].name); result = -RT_ERROR; } } return result; } -INIT_BOARD_EXPORT(cyp_hwtimer_init); +INIT_BOARD_EXPORT(cyp_clock_timer_init); -#endif /*RT_USING_HWTIMER*/ +#endif /*RT_USING_CLOCK_TIME*/ #endif /*BSP_USING_TIM*/ -/* this is a hwtimer test demo*/ +/* this is a clock_timer test demo*/ #include #include -#define HWTIMER_DEV_NAME "time2" /* device name */ +#define CLOCK_TIMER_DEV_NAME "time2" /* device name */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback fucntion!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -int hwtimer_sample() +int clock_timer_sample() { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; rt_uint32_t freq = 10000; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } rt_device_set_rx_indicate(hw_dev, timeout_cb); - rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq); - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -329,4 +329,4 @@ int hwtimer_sample() } return ret; } -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); diff --git a/bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.h b/bsp/Infineon/libraries/HAL_Drivers/drv_timer.h similarity index 89% rename from bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.h rename to bsp/Infineon/libraries/HAL_Drivers/drv_timer.h index a94447bdc9..68016814e7 100644 --- a/bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.h +++ b/bsp/Infineon/libraries/HAL_Drivers/drv_timer.h @@ -8,8 +8,8 @@ * 2022-07-29 rtthread qiu first version */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include @@ -24,7 +24,7 @@ .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ @@ -48,4 +48,4 @@ #endif /*TIM2_CONFIG*/ #endif /* BSP_USING_TIM2 */ -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig b/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig index a8951998f0..07a230d796 100644 --- a/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig +++ b/bsp/Infineon/libraries/templates/PSOC62/board/Kconfig @@ -239,7 +239,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Infineon/psoc6-cy8ckit-062-BLE/board/Kconfig b/bsp/Infineon/psoc6-cy8ckit-062-BLE/board/Kconfig index 90781dde3a..77a4380e4a 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-BLE/board/Kconfig +++ b/bsp/Infineon/psoc6-cy8ckit-062-BLE/board/Kconfig @@ -239,7 +239,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/board/Kconfig b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/board/Kconfig index 21baa70b2c..6b19951456 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/board/Kconfig +++ b/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/board/Kconfig @@ -247,7 +247,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig index 1fa9c5dcc6..0a5cec3667 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig +++ b/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/Kconfig @@ -251,7 +251,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Infineon/psoc6-cy8ckit-062s4/board/Kconfig b/bsp/Infineon/psoc6-cy8ckit-062s4/board/Kconfig index baf6aa1bc1..bfe1fd8b86 100644 --- a/bsp/Infineon/psoc6-cy8ckit-062s4/board/Kconfig +++ b/bsp/Infineon/psoc6-cy8ckit-062s4/board/Kconfig @@ -239,7 +239,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/Kconfig b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/Kconfig index 34f66f7e84..6006e7e97d 100644 --- a/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/Kconfig +++ b/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/Kconfig @@ -251,7 +251,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Infineon/psoc6-evaluationkit-062S2/board/Kconfig b/bsp/Infineon/psoc6-evaluationkit-062S2/board/Kconfig index f528ce3769..ef00b67eba 100644 --- a/bsp/Infineon/psoc6-evaluationkit-062S2/board/Kconfig +++ b/bsp/Infineon/psoc6-evaluationkit-062S2/board/Kconfig @@ -295,7 +295,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/Vango/v85xx/Kconfig b/bsp/Vango/v85xx/Kconfig index a479feb3d5..2f98c8961e 100644 --- a/bsp/Vango/v85xx/Kconfig +++ b/bsp/Vango/v85xx/Kconfig @@ -57,34 +57,34 @@ menu "On-chip Peripheral Drivers" bool "using adc1" default n endif - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER0 - bool "using hwtimer0" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER0 + bool "using clock_timer0" default n - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n endif config BSP_USING_WDT diff --git a/bsp/Vango/v85xx/README.md b/bsp/Vango/v85xx/README.md index 6790ed6af4..8d2840776c 100644 --- a/bsp/Vango/v85xx/README.md +++ b/bsp/Vango/v85xx/README.md @@ -51,7 +51,7 @@ msh /> | UART | 支持 | UART0~4 | | GPIO | 支持 | GPIOB~F | | ADC | 未支持 | ADC0~7 | -| HWTIMER | 未支持 | TIMER0~3 | +| CLOCK_TIMER | 未支持 | TIMER0~3 | | RTC | 未支持 | RTC | | WDT | 未支持 | Free watchdog timer | | IIC | 未支持 | I2C0 | diff --git a/bsp/Vango/v85xx/drivers/SConscript b/bsp/Vango/v85xx/drivers/SConscript index c6cf664e49..1b26f5d785 100644 --- a/bsp/Vango/v85xx/drivers/SConscript +++ b/bsp/Vango/v85xx/drivers/SConscript @@ -21,8 +21,8 @@ if GetDepend('RT_USING_PIN'): if GetDepend('RT_USING_ADC'): src += ['drv_adc.c'] -if GetDepend('RT_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('RT_USING_CLOCK_TIME'): + src += ['drv_timer.c'] if GetDepend('RT_USING_RTC'): src += ['drv_rtc.c'] diff --git a/bsp/Vango/v85xx/drivers/drv_comm.h b/bsp/Vango/v85xx/drivers/drv_comm.h index 78724c7e18..ea6bb51f2a 100644 --- a/bsp/Vango/v85xx/drivers/drv_comm.h +++ b/bsp/Vango/v85xx/drivers/drv_comm.h @@ -23,5 +23,5 @@ extern "C" { } #endif -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/Vango/v85xxp/Kconfig b/bsp/Vango/v85xxp/Kconfig index 0c9ea2319a..509ec78063 100644 --- a/bsp/Vango/v85xxp/Kconfig +++ b/bsp/Vango/v85xxp/Kconfig @@ -57,22 +57,22 @@ menu "On-chip Peripheral Drivers" bool "using adc0" default n endif - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER0 - bool "using hwtimer0" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER0 + bool "using clock_timer0" default n - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n endif config BSP_USING_WDT diff --git a/bsp/Vango/v85xxp/README.md b/bsp/Vango/v85xxp/README.md index f22b7e4f42..996b7ac8e2 100644 --- a/bsp/Vango/v85xxp/README.md +++ b/bsp/Vango/v85xxp/README.md @@ -51,7 +51,7 @@ msh /> | UART | 支持 | UART0~5 | | GPIO | 支持 | GPIOA~F | | ADC | 未支持 | ADC0~7 | -| HWTIMER | 未支持 | TIMER0~3 | +| CLOCK_TIMER | 未支持 | TIMER0~3 | | RTC | 未支持 | RTC | | WDT | 未支持 | Free watchdog timer | | IIC | 未支持 | I2C0 | diff --git a/bsp/Vango/v85xxp/drivers/SConscript b/bsp/Vango/v85xxp/drivers/SConscript index 30a1a338d0..4979b8969e 100644 --- a/bsp/Vango/v85xxp/drivers/SConscript +++ b/bsp/Vango/v85xxp/drivers/SConscript @@ -21,8 +21,8 @@ if GetDepend('RT_USING_PIN'): if GetDepend('RT_USING_ADC'): src += ['drv_adc.c'] -if GetDepend('RT_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('RT_USING_CLOCK_TIME'): + src += ['drv_timer.c'] if GetDepend('RT_USING_RTC'): src += ['drv_rtc.c'] diff --git a/bsp/Vango/v85xxp/drivers/drv_comm.h b/bsp/Vango/v85xxp/drivers/drv_comm.h index 78724c7e18..ea6bb51f2a 100644 --- a/bsp/Vango/v85xxp/drivers/drv_comm.h +++ b/bsp/Vango/v85xxp/drivers/drv_comm.h @@ -23,5 +23,5 @@ extern "C" { } #endif -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/Kconfig b/bsp/acm32/acm32f0x0-nucleo/drivers/Kconfig index 2b263f5e32..e112183e2b 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/Kconfig +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/Kconfig @@ -139,31 +139,31 @@ menu "On-chip Peripheral Drivers" config BSP_USING_TIM1 bool "Enable Timer1" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM3 bool "Enable Timer3" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM6 bool "Enable Timer6" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM14 bool "Enable Timer14" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM15 bool "Enable Timer15" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM16 bool "Enable Timer16" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM17 bool "Enable Timer17" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME endmenu menu "Hardware WDT" diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_hwtimer.c b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_timer.c similarity index 77% rename from bsp/acm32/acm32f0x0-nucleo/drivers/drv_hwtimer.c rename to bsp/acm32/acm32f0x0-nucleo/drivers/drv_timer.c index 9b34ef869b..0060b5f795 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_hwtimer.c +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_timer.c @@ -12,7 +12,7 @@ #include #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME #include "tim_config.h" enum @@ -40,15 +40,15 @@ enum #endif }; -struct acm32_hwtimer +struct acm32_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; TIM_HandleTypeDef tim_handle; IRQn_Type tim_irqn; char *name; }; -static struct acm32_hwtimer acm32_hwtimer_obj[] = +static struct acm32_clock_timer acm32_clock_timer_obj[] = { #ifdef BSP_USING_TIM1 TIM1_CONFIG, @@ -79,7 +79,7 @@ static struct acm32_hwtimer acm32_hwtimer_obj[] = #endif }; -static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { rt_uint32_t timer_clock = 0; TIM_HandleTypeDef *tim = RT_NULL; @@ -100,7 +100,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) tim->Init.Prescaler = (timer_clock / timer->freq) - 1 ; tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { tim->Init.CounterMode = TIM_COUNTERMODE_UP; } @@ -116,7 +116,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { TIM_HandleTypeDef *tim = RT_NULL; @@ -129,7 +129,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ /* set tim arr */ tim->Instance->ARR = t - 1; - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ SET_BIT(tim->Instance->CR1, BIT3); @@ -149,7 +149,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ return RT_EOK; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { TIM_HandleTypeDef *tim = RT_NULL; @@ -161,7 +161,7 @@ static void timer_stop(rt_hwtimer_t *timer) HAL_TIMER_Base_Stop(tim->Instance); } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { TIM_HandleTypeDef *tim = RT_NULL; rt_err_t result = RT_EOK; @@ -173,7 +173,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint32_t timer_clock; @@ -206,16 +206,16 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); return ((TIM_HandleTypeDef *)timer->parent.user_data)->Instance->CNT; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -233,7 +233,7 @@ void TIM1_BRK_UP_TRG_COM_IRQHandler(void) /* interrupt service routine */ if (TIM1->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM1_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM1_INDEX].time_device); } TIM1->SR = 0; /* write 0 to clear hardware flag */ @@ -251,7 +251,7 @@ void TIM3_IRQHandler(void) if (TIM3->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM3_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM3_INDEX].time_device); } TIM3->SR = 0; /* write 0 to clear hardware flag */ @@ -269,7 +269,7 @@ void TIM6_IRQHandler(void) /* interrupt service routine */ if (TIM6->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM6_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM6_INDEX].time_device); } TIM6->SR = 0; /* write 0 to clear hardware flag */ @@ -285,7 +285,7 @@ void TIM14_IRQHandler(void) /* interrupt service routine */ if (TIM14->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM14_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM14_INDEX].time_device); } TIM14->SR = 0; /* write 0 to clear hardware flag */ /* leave interrupt */ @@ -300,7 +300,7 @@ void TIM15_IRQHandler(void) /* interrupt service routine */ if (TIM15->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM15_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM15_INDEX].time_device); } TIM15->SR = 0; /* write 0 to clear hardware flag */ /* leave interrupt */ @@ -314,7 +314,7 @@ void TIM16_IRQHandler(void) rt_interrupt_enter(); if (TIM16->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM16_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM16_INDEX].time_device); } TIM16->SR = 0; /* write 0 to clear hardware flag */ /* leave interrupt */ @@ -328,7 +328,7 @@ void TIM17_IRQHandler(void) rt_interrupt_enter(); if (TIM17->SR & TIMER_SR_UIF) { - rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM17_INDEX].time_device); + rt_clock_timer_isr(&acm32_clock_timer_obj[TIM17_INDEX].time_device); } TIM17->SR = 0; /* write 0 to clear hardware flag */ /* leave interrupt */ @@ -336,18 +336,18 @@ void TIM17_IRQHandler(void) } #endif -static int acm32_hwtimer_init(void) +static int acm32_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(acm32_hwtimer_obj) / sizeof(acm32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(acm32_clock_timer_obj) / sizeof(acm32_clock_timer_obj[0]); i++) { - acm32_hwtimer_obj[i].time_device.info = &_info; - acm32_hwtimer_obj[i].time_device.ops = &_ops; - result = rt_device_hwtimer_register(&acm32_hwtimer_obj[i].time_device, - acm32_hwtimer_obj[i].name, - &acm32_hwtimer_obj[i].tim_handle); + acm32_clock_timer_obj[i].time_device.info = &_info; + acm32_clock_timer_obj[i].time_device.ops = &_ops; + result = rt_clock_timer_register(&acm32_clock_timer_obj[i].time_device, + acm32_clock_timer_obj[i].name, + &acm32_clock_timer_obj[i].tim_handle); if (result != RT_EOK) { result = -RT_ERROR; @@ -357,7 +357,7 @@ static int acm32_hwtimer_init(void) return result; } -INIT_BOARD_EXPORT(acm32_hwtimer_init); +INIT_BOARD_EXPORT(acm32_clock_timer_init); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/tim_config.h b/bsp/acm32/acm32f0x0-nucleo/drivers/tim_config.h index c22487df59..14f12fa68b 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/tim_config.h +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/acm32/acm32f0x0-nucleo/project.ewp b/bsp/acm32/acm32f0x0-nucleo/project.ewp index 598abdb63c..76200b3b3b 100644 --- a/bsp/acm32/acm32f0x0-nucleo/project.ewp +++ b/bsp/acm32/acm32f0x0-nucleo/project.ewp @@ -2229,7 +2229,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c @@ -2298,7 +2298,7 @@ $PROJ_DIR$\drivers\drv_pm.c - $PROJ_DIR$\drivers\drv_hwtimer.c + $PROJ_DIR$\drivers\drv_timer.c $PROJ_DIR$\drivers\drv_i2c.c diff --git a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx index 516695465c..83290ed87a 100644 --- a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx +++ b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx @@ -570,9 +570,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -853,9 +853,9 @@ - drv_hwtimer.c + drv_timer.c 1 - drivers\drv_hwtimer.c + drivers\drv_timer.c diff --git a/bsp/acm32/acm32f4xx-nucleo/drivers/Kconfig b/bsp/acm32/acm32f4xx-nucleo/drivers/Kconfig index a760743f7b..837134e99f 100644 --- a/bsp/acm32/acm32f4xx-nucleo/drivers/Kconfig +++ b/bsp/acm32/acm32f4xx-nucleo/drivers/Kconfig @@ -219,43 +219,43 @@ menu "On-chip Peripheral Drivers" config BSP_USING_TIM1 bool "Enable Timer1" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM2 bool "Enable Timer2" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM3 bool "Enable Timer3" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM4 bool "Enable Timer4" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM6 bool "Enable Timer6" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM7 bool "Enable Timer7" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM14 bool "Enable Timer14" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM15 bool "Enable Timer15" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM16 bool "Enable Timer16" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME config BSP_USING_TIM17 bool "Enable Timer17" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME endmenu menu "Hardware WDT" diff --git a/bsp/airm2m/air105/libraries/HAL_Driver/Inc/app_inc.h b/bsp/airm2m/air105/libraries/HAL_Driver/Inc/app_inc.h index 6edd151571..b5e4c5d37d 100644 --- a/bsp/airm2m/air105/libraries/HAL_Driver/Inc/app_inc.h +++ b/bsp/airm2m/air105/libraries/HAL_Driver/Inc/app_inc.h @@ -23,7 +23,7 @@ #define __APP_INC_H__ #include "bl_inc.h" -#include "core_hwtimer.h" +#include "core_clock_timer.h" #include "core_spi.h" #include "core_adc.h" #include "core_dac.h" diff --git a/bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_hwtimer.h b/bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_clock_timer.h similarity index 98% rename from bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_hwtimer.h rename to bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_clock_timer.h index 1261da425c..5226965367 100644 --- a/bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_hwtimer.h +++ b/bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_clock_timer.h @@ -19,8 +19,8 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#ifndef __CORE_HWTIMER_H__ -#define __CORE_HWTIMER_H__ +#ifndef __CORE_CLOCK_TIMER_H__ +#define __CORE_CLOCK_TIMER_H__ /** diff --git a/bsp/airm2m/air105/libraries/HAL_Driver/Inc/resource_map.h b/bsp/airm2m/air105/libraries/HAL_Driver/Inc/resource_map.h index 21fc95e68f..18fde16974 100644 --- a/bsp/airm2m/air105/libraries/HAL_Driver/Inc/resource_map.h +++ b/bsp/airm2m/air105/libraries/HAL_Driver/Inc/resource_map.h @@ -28,7 +28,7 @@ #define CORE_TICK_1MS (48000) #define CORE_TICK_1S (48000000) #define CORE_TICK_IRQ_LEVEL 1 -#define HWTIMER_IRQ_LEVEL 0 +#define CLOCK_TIMER_IRQ_LEVEL 0 #define SYS_TIMER_TIM 6 #define SYS_TIMER_IRQ TIM0_6_IRQn diff --git a/bsp/airm2m/air105/libraries/HAL_Driver/Src/core_hwtimer.c b/bsp/airm2m/air105/libraries/HAL_Driver/Src/core_clock_timer.c similarity index 98% rename from bsp/airm2m/air105/libraries/HAL_Driver/Src/core_hwtimer.c rename to bsp/airm2m/air105/libraries/HAL_Driver/Src/core_clock_timer.c index 1383d1cf94..da63318e25 100644 --- a/bsp/airm2m/air105/libraries/HAL_Driver/Src/core_hwtimer.c +++ b/bsp/airm2m/air105/libraries/HAL_Driver/Src/core_clock_timer.c @@ -142,7 +142,7 @@ static void __FUNC_IN_RAM__ prvHWTimer_StartOperationQueue(uint8_t HWTimerID, HW break; case OP_QUEUE_CMD_ONE_TIME_DELAY: HWTimer->ContinueDelay = 0; - goto START_HWTIMER; + goto START_CLOCK_TIMER; break; case OP_QUEUE_CMD_REPEAT_DELAY: HWTimer->CurCount++; @@ -166,7 +166,7 @@ static void __FUNC_IN_RAM__ prvHWTimer_StartOperationQueue(uint8_t HWTimerID, HW break; case OP_QUEUE_CMD_CONTINUE_DELAY: HWTimer->ContinueDelay = 1; - goto START_HWTIMER; + goto START_CLOCK_TIMER; break; case OP_QUEUE_CMD_SET_GPIO_DIR_OUT: @@ -235,7 +235,7 @@ static void __FUNC_IN_RAM__ prvHWTimer_StartOperationQueue(uint8_t HWTimerID, HW } } return ; -START_HWTIMER: +START_CLOCK_TIMER: TIMM0->TIM[HWTimerID].ControlReg = 0; Period = HWTimer->Cmd[HWTimer->CurCount].uArg.Time; Period = Period * SYS_TIMER_1US + HWTimer->Cmd[HWTimer->CurCount].Arg1; @@ -404,7 +404,7 @@ void HWTimer_StartOperationQueue(uint8_t HWTimerID) HWTimer_Stop(HWTimerID); } ISR_SetHandler(prvHWTimer[HWTimerID].IrqLine, prvHWTimer_IrqHandlerOperationQueue, HWTimerID); - ISR_SetPriority(prvHWTimer[HWTimerID].IrqLine, HWTIMER_IRQ_LEVEL); + ISR_SetPriority(prvHWTimer[HWTimerID].IrqLine, CLOCK_TIMER_IRQ_LEVEL); prvHWTimer[HWTimerID].Cmd[prvHWTimer[HWTimerID].CmdQueuePos].Operation = OP_QUEUE_CMD_END; HWTimer_ResetOperationQueue(HWTimerID); diff --git a/bsp/airm2m/air32f103/board/Kconfig b/bsp/airm2m/air32f103/board/Kconfig index dd74fdd571..65f1c9b152 100644 --- a/bsp/airm2m/air32f103/board/Kconfig +++ b/bsp/airm2m/air32f103/board/Kconfig @@ -105,7 +105,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/airm2m/air32f103/board/board.c b/bsp/airm2m/air32f103/board/board.c index 38e7c702a3..611082ce42 100644 --- a/bsp/airm2m/air32f103/board/board.c +++ b/bsp/airm2m/air32f103/board/board.c @@ -175,61 +175,61 @@ rt_uint32_t air32_tim_clock_get(TIM_TypeDef *timx) return RCC_Clocks.HCLK_Frequency; } -struct rt_hwtimer_info hwtimer_info1 = +struct rt_clock_timer_info clock_timer_info1 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info2 = +struct rt_clock_timer_info clock_timer_info2 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info3 = +struct rt_clock_timer_info clock_timer_info3 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info4 = +struct rt_clock_timer_info clock_timer_info4 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info *air32_hwtimer_info_config_get(TIM_TypeDef *timx) +struct rt_clock_timer_info *air32_clock_timer_info_config_get(TIM_TypeDef *timx) { - struct rt_hwtimer_info *info = RT_NULL; + struct rt_clock_timer_info *info = RT_NULL; if (timx == TIM1) { - info = &hwtimer_info1; + info = &clock_timer_info1; } else if (timx == TIM2) { - info = &hwtimer_info2; + info = &clock_timer_info2; } else if (timx == TIM3) { - info = &hwtimer_info3; + info = &clock_timer_info3; } else if (timx == TIM4) { - info = &hwtimer_info4; + info = &clock_timer_info4; } return info; diff --git a/bsp/airm2m/air32f103/board/board.h b/bsp/airm2m/air32f103/board/board.h index e21f907aa6..74aa58d0e5 100644 --- a/bsp/airm2m/air32f103/board/board.h +++ b/bsp/airm2m/air32f103/board/board.h @@ -58,7 +58,7 @@ rt_uint32_t air32_tim_clock_get(TIM_TypeDef *timx); #endif #ifdef BSP_USING_TIM -struct rt_hwtimer_info* air32_hwtimer_info_config_get(TIM_TypeDef *timx); +struct rt_clock_timer_info* air32_clock_timer_info_config_get(TIM_TypeDef *timx); #endif #ifdef BSP_USING_PWM diff --git a/bsp/airm2m/air32f103/libraries/SConscript b/bsp/airm2m/air32f103/libraries/SConscript index b0c12a0453..8848f19239 100644 --- a/bsp/airm2m/air32f103/libraries/SConscript +++ b/bsp/airm2m/air32f103/libraries/SConscript @@ -64,7 +64,7 @@ if GetDepend('BSP_USING_PWM'): src += ['rt_drivers/drv_pwm.c'] if GetDepend('BSP_USING_TIM'): - src += ['rt_drivers/drv_hwtimer.c'] + src += ['rt_drivers/drv_timer.c'] if GetDepend('BSP_USING_WDT'): src += ['rt_drivers/drv_wdt.c'] diff --git a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_timer.c similarity index 37% rename from bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c rename to bsp/airm2m/air32f103/libraries/rt_drivers/drv_timer.c index 8f7415fd5a..f1b4e7d655 100644 --- a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_timer.c @@ -11,17 +11,17 @@ #include #include #include -#include "drv_hwtimer.h" +#include "drv_timer.h" #ifdef BSP_USING_TIM -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -static void air32_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t state) +static void air32_clock_timer_init(struct rt_clock_timer_device *device, rt_uint32_t state) { - struct hwtimer_device *hwtimer_dev; - struct rt_hwtimer_info *hwtimer_info; + struct clock_timer_device *clock_timer_dev; + struct rt_clock_timer_info *clock_timer_info; rt_uint32_t clk = 0; rt_uint16_t prescaler_value = 0; @@ -30,34 +30,34 @@ static void air32_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t sta RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; if (state) { - air32_tim_clock_init(hwtimer_dev->periph); + air32_tim_clock_init(clock_timer_dev->periph); - hwtimer_info = air32_hwtimer_info_config_get(hwtimer_dev->periph); + clock_timer_info = air32_clock_timer_info_config_get(clock_timer_dev->periph); - clk = air32_tim_clock_get(hwtimer_dev->periph); + clk = air32_tim_clock_get(clock_timer_dev->periph); - prescaler_value = (rt_uint16_t)(clk / hwtimer_info->minfreq) - 1; + prescaler_value = (rt_uint16_t)(clk / clock_timer_info->minfreq) - 1; /* * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) ) */ - TIM_TimeBaseInitType.TIM_Period = hwtimer_info->maxcnt - 1; + TIM_TimeBaseInitType.TIM_Period = clock_timer_info->maxcnt - 1; TIM_TimeBaseInitType.TIM_Prescaler = prescaler_value; TIM_TimeBaseInitType.TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseInitType.TIM_RepetitionCounter = 0; - if (hwtimer_info == RT_NULL) + if (clock_timer_info == RT_NULL) { TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up; } else { - if (hwtimer_info->cntmode == HWTIMER_CNTMODE_UP) + if (clock_timer_info->cntmode == CLOCK_TIMER_CNTMODE_UP) { TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up; } @@ -67,89 +67,89 @@ static void air32_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t sta } } - TIM_TimeBaseInit(hwtimer_dev->periph, &TIM_TimeBaseInitType); + TIM_TimeBaseInit(clock_timer_dev->periph, &TIM_TimeBaseInitType); - NVIC_InitStructure.NVIC_IRQChannel = hwtimer_dev->irqn; + NVIC_InitStructure.NVIC_IRQChannel = clock_timer_dev->irqn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - TIM_ITConfig(hwtimer_dev->periph, TIM_IT_Update, ENABLE); - TIM_ClearITPendingBit(hwtimer_dev->periph, TIM_IT_Update); + TIM_ITConfig(clock_timer_dev->periph, TIM_IT_Update, ENABLE); + TIM_ClearITPendingBit(clock_timer_dev->periph, TIM_IT_Update); - LOG_D("%s init success", hwtimer_dev->name); + LOG_D("%s init success", clock_timer_dev->name); } } -static rt_err_t air32_hwtimer_start(struct rt_hwtimer_device *device, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t air32_clock_timer_start(struct rt_clock_timer_device *device, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; /* * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) ) */ - TIM_SetCounter(hwtimer_dev->periph, 0); - TIM_SetAutoreload(hwtimer_dev->periph, cnt - 1); + TIM_SetCounter(clock_timer_dev->periph, 0); + TIM_SetAutoreload(clock_timer_dev->periph, cnt - 1); - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { - TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Single); + TIM_SelectOnePulseMode(clock_timer_dev->periph, TIM_OPMode_Single); } else { - TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Repetitive); + TIM_SelectOnePulseMode(clock_timer_dev->periph, TIM_OPMode_Repetitive); } - TIM_Cmd(hwtimer_dev->periph, ENABLE); + TIM_Cmd(clock_timer_dev->periph, ENABLE); - LOG_D("%s start, cnt = %d", hwtimer_dev->name, cnt); + LOG_D("%s start, cnt = %d", clock_timer_dev->name, cnt); return RT_EOK; } -static void air32_hwtimer_stop(struct rt_hwtimer_device *device) +static void air32_clock_timer_stop(struct rt_clock_timer_device *device) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; - TIM_Cmd(hwtimer_dev->periph, DISABLE); + TIM_Cmd(clock_timer_dev->periph, DISABLE); - TIM_SetCounter(hwtimer_dev->periph, 0); + TIM_SetCounter(clock_timer_dev->periph, 0); } -static rt_uint32_t air32_hwtimer_counter_get(struct rt_hwtimer_device *device) +static rt_uint32_t air32_clock_timer_counter_get(struct rt_clock_timer_device *device) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; - return hwtimer_dev->periph->CNT; + return clock_timer_dev->periph->CNT; } -static rt_err_t air32_hwtimer_control(struct rt_hwtimer_device *device, rt_uint32_t cmd, void *arg) +static rt_err_t air32_clock_timer_control(struct rt_clock_timer_device *device, rt_uint32_t cmd, void *arg) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; rt_err_t result = RT_EOK; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq = 0; rt_uint32_t clk = 0; @@ -163,11 +163,11 @@ static rt_err_t air32_hwtimer_control(struct rt_hwtimer_device *device, rt_uint3 freq = *((rt_uint32_t *)arg); - clk = air32_tim_clock_get(hwtimer_dev->periph); + clk = air32_tim_clock_get(clock_timer_dev->periph); prescaler_value = (rt_uint16_t)(clk / freq) - 1; - TIM_PrescalerConfig(hwtimer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate); + TIM_PrescalerConfig(clock_timer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate); } else { @@ -184,83 +184,83 @@ static rt_err_t air32_hwtimer_control(struct rt_hwtimer_device *device, rt_uint3 return result; } -static const struct rt_hwtimer_ops hwtimer_ops = +static const struct rt_clock_timer_ops clock_timer_ops = { - .init = air32_hwtimer_init, - .start = air32_hwtimer_start, - .stop = air32_hwtimer_stop, - .count_get = air32_hwtimer_counter_get, - .control = air32_hwtimer_control, + .init = air32_clock_timer_init, + .start = air32_clock_timer_start, + .stop = air32_clock_timer_stop, + .count_get = air32_clock_timer_counter_get, + .control = air32_clock_timer_control, }; -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { rt_err_t ret; - struct rt_hwtimer_info *hwtimer_info; + struct rt_clock_timer_info *clock_timer_info; #ifdef BSP_USING_TIM1 - hwtimer_info = air32_hwtimer_info_config_get(hwtimer_device1.periph); - hwtimer_device1.parent.info = hwtimer_info; - hwtimer_device1.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device1.parent, hwtimer_device1.name, RT_NULL); + clock_timer_info = air32_clock_timer_info_config_get(clock_timer_device1.periph); + clock_timer_device1.parent.info = clock_timer_info; + clock_timer_device1.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device1.parent, clock_timer_device1.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device1.name); + LOG_D("clock_timer: %s register success.", clock_timer_device1.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device1.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device1.name); } #endif #ifdef BSP_USING_TIM2 - hwtimer_info = air32_hwtimer_info_config_get(hwtimer_device2.periph); - hwtimer_device2.parent.info = hwtimer_info; - hwtimer_device2.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device2.parent, hwtimer_device2.name, RT_NULL); + clock_timer_info = air32_clock_timer_info_config_get(clock_timer_device2.periph); + clock_timer_device2.parent.info = clock_timer_info; + clock_timer_device2.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device2.parent, clock_timer_device2.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device2.name); + LOG_D("clock_timer: %s register success.", clock_timer_device2.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device2.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device2.name); } #endif #ifdef BSP_USING_TIM3 - hwtimer_info = air32_hwtimer_info_config_get(hwtimer_device3.periph); - hwtimer_device3.parent.info = hwtimer_info; - hwtimer_device3.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device3.parent, hwtimer_device3.name, RT_NULL); + clock_timer_info = air32_clock_timer_info_config_get(clock_timer_device3.periph); + clock_timer_device3.parent.info = clock_timer_info; + clock_timer_device3.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device3.parent, clock_timer_device3.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device3.name); + LOG_D("clock_timer: %s register success.", clock_timer_device3.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device3.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device3.name); } #endif #ifdef BSP_USING_TIM4 - hwtimer_info = air32_hwtimer_info_config_get(hwtimer_device4.periph); - hwtimer_device4.parent.info = hwtimer_info; - hwtimer_device4.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device4.parent, hwtimer_device4.name, RT_NULL); + clock_timer_info = air32_clock_timer_info_config_get(clock_timer_device4.periph); + clock_timer_device4.parent.info = clock_timer_info; + clock_timer_device4.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device4.parent, clock_timer_device4.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device4.name); + LOG_D("clock_timer: %s register success.", clock_timer_device4.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device4.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device4.name); } #endif return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); #ifdef BSP_USING_TIM1 void TIM1_UP_IRQHandler(void) @@ -268,10 +268,10 @@ void TIM1_UP_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device1.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device1.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device1.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device1.parent); + TIM_ClearITPendingBit(clock_timer_device1.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device1.parent); } /* leave interrupt */ rt_interrupt_leave(); @@ -284,10 +284,10 @@ void TIM2_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device2.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device2.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device2.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device2.parent); + TIM_ClearITPendingBit(clock_timer_device2.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device2.parent); } /* leave interrupt */ rt_interrupt_leave(); @@ -300,10 +300,10 @@ void TIM3_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device3.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device3.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device3.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device3.parent); + TIM_ClearITPendingBit(clock_timer_device3.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device3.parent); } /* leave interrupt */ rt_interrupt_leave(); @@ -316,14 +316,14 @@ void TIM4_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device4.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device4.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device4.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device4.parent); + TIM_ClearITPendingBit(clock_timer_device4.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device4.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.h b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_timer.h similarity index 67% rename from bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.h rename to bsp/airm2m/air32f103/libraries/rt_drivers/drv_timer.h index a3457ee3db..d7de7c915e 100644 --- a/bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.h +++ b/bsp/airm2m/air32f103/libraries/rt_drivers/drv_timer.h @@ -8,24 +8,24 @@ * 2022-02-22 airm2m first version */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include #ifdef BSP_USING_TIM #include -struct hwtimer_device +struct clock_timer_device { - struct rt_hwtimer_device parent; + struct rt_clock_timer_device parent; TIM_TypeDef *periph; IRQn_Type irqn; char *name; }; #ifdef BSP_USING_TIM1 -struct hwtimer_device hwtimer_device1 = +struct clock_timer_device clock_timer_device1 = { .periph = TIM1, .irqn = TIM1_UP_IRQn, @@ -33,7 +33,7 @@ struct hwtimer_device hwtimer_device1 = #endif #ifdef BSP_USING_TIM2 -struct hwtimer_device hwtimer_device2 = +struct clock_timer_device clock_timer_device2 = { .periph = TIM2, .irqn = TIM2_IRQn, @@ -41,7 +41,7 @@ struct hwtimer_device hwtimer_device2 = #endif #ifdef BSP_USING_TIM3 -struct hwtimer_device hwtimer_device3 = +struct clock_timer_device clock_timer_device3 = { .periph = TIM3, .irqn = TIM3_IRQn, @@ -49,12 +49,12 @@ struct hwtimer_device hwtimer_device3 = #endif #ifdef BSP_USING_TIM4 -struct hwtimer_device hwtimer_device4 = +struct clock_timer_device clock_timer_device4 = { .periph = TIM4, .irqn = TIM4_IRQn, .name = "timer4"}; #endif -#endif /* BSP_USING_HWTIMER */ -#endif /* __DRV_HWTIMER_H__ */ +#endif /* BSP_USING_CLOCK_TIMER */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/allwinner/d1s/board/board.c b/bsp/allwinner/d1s/board/board.c index 33470e5cb7..6063739db3 100644 --- a/bsp/allwinner/d1s/board/board.c +++ b/bsp/allwinner/d1s/board/board.c @@ -52,6 +52,11 @@ struct mem_desc platform_mem_desc[] = { #endif /* RT_USING_SMART */ +rt_uint64_t rt_hw_get_clock_timer_freq(void) +{ + return 24000000ULL; +} + // 初始化BSS节区 void init_bss(void) { diff --git a/bsp/apm32/apm32e103ze-evalboard/board/Kconfig b/bsp/apm32/apm32e103ze-evalboard/board/Kconfig index 5be25544e8..c8c59dee47 100644 --- a/bsp/apm32/apm32e103ze-evalboard/board/Kconfig +++ b/bsp/apm32/apm32e103ze-evalboard/board/Kconfig @@ -175,7 +175,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32e103ze-evalboard/board/board.h b/bsp/apm32/apm32e103ze-evalboard/board/board.h index 2274bb453b..7cee8931a7 100644 --- a/bsp/apm32/apm32e103ze-evalboard/board/board.h +++ b/bsp/apm32/apm32e103ze-evalboard/board/board.h @@ -35,7 +35,7 @@ #if defined(RT_USING_SPI) #include "apm32e10x_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32e10x_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32e103ze-tinyboard/board/Kconfig b/bsp/apm32/apm32e103ze-tinyboard/board/Kconfig index a76b738cef..4ff30f548e 100644 --- a/bsp/apm32/apm32e103ze-tinyboard/board/Kconfig +++ b/bsp/apm32/apm32e103ze-tinyboard/board/Kconfig @@ -156,7 +156,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32e103ze-tinyboard/board/board.h b/bsp/apm32/apm32e103ze-tinyboard/board/board.h index 2274bb453b..7cee8931a7 100644 --- a/bsp/apm32/apm32e103ze-tinyboard/board/board.h +++ b/bsp/apm32/apm32e103ze-tinyboard/board/board.h @@ -35,7 +35,7 @@ #if defined(RT_USING_SPI) #include "apm32e10x_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32e10x_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f030r8-miniboard/board/Kconfig b/bsp/apm32/apm32f030r8-miniboard/board/Kconfig index 7d0f93b3e4..c583254b83 100644 --- a/bsp/apm32/apm32f030r8-miniboard/board/Kconfig +++ b/bsp/apm32/apm32f030r8-miniboard/board/Kconfig @@ -120,7 +120,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f030r8-miniboard/board/board.h b/bsp/apm32/apm32f030r8-miniboard/board/board.h index 3435a9478b..c431a210bc 100644 --- a/bsp/apm32/apm32f030r8-miniboard/board/board.h +++ b/bsp/apm32/apm32f030r8-miniboard/board/board.h @@ -34,7 +34,7 @@ #if defined(RT_USING_SPI) #include "apm32f0xx_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f0xx_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f051r8-evalboard/board/Kconfig b/bsp/apm32/apm32f051r8-evalboard/board/Kconfig index 66b9f17f4e..aef90aa40b 100644 --- a/bsp/apm32/apm32f051r8-evalboard/board/Kconfig +++ b/bsp/apm32/apm32f051r8-evalboard/board/Kconfig @@ -132,7 +132,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f051r8-evalboard/board/board.h b/bsp/apm32/apm32f051r8-evalboard/board/board.h index 5ec31a3c81..2c43d2079b 100644 --- a/bsp/apm32/apm32f051r8-evalboard/board/board.h +++ b/bsp/apm32/apm32f051r8-evalboard/board/board.h @@ -34,7 +34,7 @@ #if defined(RT_USING_SPI) #include "apm32f0xx_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f0xx_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f072vb-miniboard/board/Kconfig b/bsp/apm32/apm32f072vb-miniboard/board/Kconfig index 528e873194..cae05eae10 100644 --- a/bsp/apm32/apm32f072vb-miniboard/board/Kconfig +++ b/bsp/apm32/apm32f072vb-miniboard/board/Kconfig @@ -133,7 +133,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f072vb-miniboard/board/board.h b/bsp/apm32/apm32f072vb-miniboard/board/board.h index 70aab08c05..200f529e70 100644 --- a/bsp/apm32/apm32f072vb-miniboard/board/board.h +++ b/bsp/apm32/apm32f072vb-miniboard/board/board.h @@ -34,7 +34,7 @@ #if defined(RT_USING_SPI) #include "apm32f0xx_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f0xx_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f091vc-miniboard/board/Kconfig b/bsp/apm32/apm32f091vc-miniboard/board/Kconfig index b8a7b84f15..757ecc8b85 100644 --- a/bsp/apm32/apm32f091vc-miniboard/board/Kconfig +++ b/bsp/apm32/apm32f091vc-miniboard/board/Kconfig @@ -133,7 +133,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f091vc-miniboard/board/board.h b/bsp/apm32/apm32f091vc-miniboard/board/board.h index d741eb2237..90df8c8250 100644 --- a/bsp/apm32/apm32f091vc-miniboard/board/board.h +++ b/bsp/apm32/apm32f091vc-miniboard/board/board.h @@ -34,7 +34,7 @@ #if defined(RT_USING_SPI) #include "apm32f0xx_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f0xx_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f103vb-miniboard/board/Kconfig b/bsp/apm32/apm32f103vb-miniboard/board/Kconfig index 5fd8985607..6abbc34415 100644 --- a/bsp/apm32/apm32f103vb-miniboard/board/Kconfig +++ b/bsp/apm32/apm32f103vb-miniboard/board/Kconfig @@ -126,7 +126,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f103vb-miniboard/board/board.h b/bsp/apm32/apm32f103vb-miniboard/board/board.h index 4e69fcf5f4..54f663e877 100644 --- a/bsp/apm32/apm32f103vb-miniboard/board/board.h +++ b/bsp/apm32/apm32f103vb-miniboard/board/board.h @@ -34,7 +34,7 @@ #if defined(RT_USING_SPI) #include "apm32f10x_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f10x_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig index beace4e596..12182a2c48 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/Kconfig +++ b/bsp/apm32/apm32f103xe-minibroard/board/Kconfig @@ -119,7 +119,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f103xe-minibroard/board/board.h b/bsp/apm32/apm32f103xe-minibroard/board/board.h index 8e75b5b643..e2f2029723 100644 --- a/bsp/apm32/apm32f103xe-minibroard/board/board.h +++ b/bsp/apm32/apm32f103xe-minibroard/board/board.h @@ -36,7 +36,7 @@ #if defined(RT_USING_SPI) #include "apm32f10x_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f10x_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f107vc-evalboard/board/Kconfig b/bsp/apm32/apm32f107vc-evalboard/board/Kconfig index bc4840e39e..31d7d7113a 100644 --- a/bsp/apm32/apm32f107vc-evalboard/board/Kconfig +++ b/bsp/apm32/apm32f107vc-evalboard/board/Kconfig @@ -156,7 +156,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f107vc-evalboard/board/board.h b/bsp/apm32/apm32f107vc-evalboard/board/board.h index a57504c15e..88d86b5949 100644 --- a/bsp/apm32/apm32f107vc-evalboard/board/board.h +++ b/bsp/apm32/apm32f107vc-evalboard/board/board.h @@ -34,7 +34,7 @@ #if defined(RT_USING_SPI) #include "apm32f10x_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f10x_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f407ig-minibroard/board/Kconfig b/bsp/apm32/apm32f407ig-minibroard/board/Kconfig index b8eac74c77..d14dafe814 100644 --- a/bsp/apm32/apm32f407ig-minibroard/board/Kconfig +++ b/bsp/apm32/apm32f407ig-minibroard/board/Kconfig @@ -108,7 +108,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f407ig-minibroard/board/board.h b/bsp/apm32/apm32f407ig-minibroard/board/board.h index 15d8abcd5c..242b27bf43 100644 --- a/bsp/apm32/apm32f407ig-minibroard/board/board.h +++ b/bsp/apm32/apm32f407ig-minibroard/board/board.h @@ -35,7 +35,7 @@ #if defined(RT_USING_SPI) #include "apm32f4xx_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f4xx_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32f407zg-evalboard/board/Kconfig b/bsp/apm32/apm32f407zg-evalboard/board/Kconfig index d7cc13ec8a..3d933499a0 100644 --- a/bsp/apm32/apm32f407zg-evalboard/board/Kconfig +++ b/bsp/apm32/apm32f407zg-evalboard/board/Kconfig @@ -168,7 +168,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32f407zg-evalboard/board/board.h b/bsp/apm32/apm32f407zg-evalboard/board/board.h index c9f49f9c18..5d5e23a34c 100644 --- a/bsp/apm32/apm32f407zg-evalboard/board/board.h +++ b/bsp/apm32/apm32f407zg-evalboard/board/board.h @@ -36,7 +36,7 @@ #if defined(RT_USING_SPI) #include "apm32f4xx_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32f4xx_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/apm32s103vb-miniboard/board/Kconfig b/bsp/apm32/apm32s103vb-miniboard/board/Kconfig index 8f19663d00..af6d754f8d 100644 --- a/bsp/apm32/apm32s103vb-miniboard/board/Kconfig +++ b/bsp/apm32/apm32s103vb-miniboard/board/Kconfig @@ -140,7 +140,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TMR bool "Enable Timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TMR config BSP_USING_TMR1 bool "Enable TMR1" diff --git a/bsp/apm32/apm32s103vb-miniboard/board/board.h b/bsp/apm32/apm32s103vb-miniboard/board/board.h index d1906e7189..e7683ccf98 100644 --- a/bsp/apm32/apm32s103vb-miniboard/board/board.h +++ b/bsp/apm32/apm32s103vb-miniboard/board/board.h @@ -35,7 +35,7 @@ #if defined(RT_USING_SPI) #include "apm32s10x_spi.h" #endif -#if defined(RT_USING_HWTIMER) || defined(RT_USING_PWM) +#if defined(RT_USING_CLOCK_TIME) || defined(RT_USING_PWM) #include "apm32s10x_tmr.h" #endif #if defined(RT_USING_WDT) diff --git a/bsp/apm32/libraries/APM32E10x_Library/SConscript b/bsp/apm32/libraries/APM32E10x_Library/SConscript index c8c453079e..87eba829cd 100644 --- a/bsp/apm32/libraries/APM32E10x_Library/SConscript +++ b/bsp/apm32/libraries/APM32E10x_Library/SConscript @@ -29,7 +29,7 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_SPI']): src += ['APM32E10x_StdPeriphDriver/src/apm32e10x_spi.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['APM32E10x_StdPeriphDriver/src/apm32e10x_tmr.c'] if GetDepend(['RT_USING_WDT']): diff --git a/bsp/apm32/libraries/APM32F0xx_Library/SConscript b/bsp/apm32/libraries/APM32F0xx_Library/SConscript index a1e0d9b76e..994a67d834 100644 --- a/bsp/apm32/libraries/APM32F0xx_Library/SConscript +++ b/bsp/apm32/libraries/APM32F0xx_Library/SConscript @@ -29,7 +29,7 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_SPI']): src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_spi.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['APM32F0xx_StdPeriphDriver/src/apm32f0xx_tmr.c'] if GetDepend(['RT_USING_WDT']): diff --git a/bsp/apm32/libraries/APM32F10x_Library/SConscript b/bsp/apm32/libraries/APM32F10x_Library/SConscript index 7bfa61779e..060b2c74f8 100644 --- a/bsp/apm32/libraries/APM32F10x_Library/SConscript +++ b/bsp/apm32/libraries/APM32F10x_Library/SConscript @@ -29,7 +29,7 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_SPI']): src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c'] if GetDepend(['RT_USING_WDT']): diff --git a/bsp/apm32/libraries/APM32F4xx_Library/SConscript b/bsp/apm32/libraries/APM32F4xx_Library/SConscript index 0e6ef2a487..dfdbb2aa30 100644 --- a/bsp/apm32/libraries/APM32F4xx_Library/SConscript +++ b/bsp/apm32/libraries/APM32F4xx_Library/SConscript @@ -30,7 +30,7 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_SPI']): src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_spi.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['APM32F4xx_StdPeriphDriver/src/apm32f4xx_tmr.c'] if GetDepend(['RT_USING_WDT']): diff --git a/bsp/apm32/libraries/APM32S10x_Library/SConscript b/bsp/apm32/libraries/APM32S10x_Library/SConscript index edc3a8e280..7ca9ceff32 100644 --- a/bsp/apm32/libraries/APM32S10x_Library/SConscript +++ b/bsp/apm32/libraries/APM32S10x_Library/SConscript @@ -29,7 +29,7 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_SPI']): src += ['APM32S10x_StdPeriphDriver/src/apm32s10x_spi.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['APM32S10x_StdPeriphDriver/src/apm32s10x_tmr.c'] if GetDepend(['RT_USING_WDT']): diff --git a/bsp/apm32/libraries/Drivers/SConscript b/bsp/apm32/libraries/Drivers/SConscript index 30015b3240..a5d05ad815 100644 --- a/bsp/apm32/libraries/Drivers/SConscript +++ b/bsp/apm32/libraries/Drivers/SConscript @@ -33,8 +33,8 @@ if GetDepend(['RT_USING_I2C']): if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] diff --git a/bsp/apm32/libraries/Drivers/drv_hwtimer.c b/bsp/apm32/libraries/Drivers/drv_timer.c similarity index 84% rename from bsp/apm32/libraries/Drivers/drv_hwtimer.c rename to bsp/apm32/libraries/Drivers/drv_timer.c index e9f4561bfd..c13377db83 100644 --- a/bsp/apm32/libraries/Drivers/drv_hwtimer.c +++ b/bsp/apm32/libraries/Drivers/drv_timer.c @@ -13,18 +13,18 @@ #include -#define DBG_TAG "drv.hwtimer" +#define DBG_TAG "drv.clock_timer" #define DBG_LVL DBG_INFO #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME -static const struct rt_hwtimer_info apm32_timer_info = +static const struct rt_clock_timer_info apm32_timer_info = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; /* apm32 config class */ @@ -33,7 +33,7 @@ struct apm32_timer char *name; TMR_T *tmr; IRQn_Type irqn; - rt_hwtimer_t device; + rt_clock_timer_t device; }; enum @@ -234,7 +234,7 @@ static struct apm32_timer tmr_config[] = #endif }; -static rt_uint32_t apm32_hwtimer_clock_get(TMR_T *tmr) +static rt_uint32_t apm32_clock_timer_clock_get(TMR_T *tmr) { #if defined(SOC_SERIES_APM32F0) uint32_t pclk1; @@ -265,7 +265,7 @@ static rt_uint32_t apm32_hwtimer_clock_get(TMR_T *tmr) #endif } -static void apm32_hwtimer_enable_clock(void) +static void apm32_clock_timer_enable_clock(void) { #ifdef BSP_USING_TMR1 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_TMR1); @@ -320,7 +320,7 @@ static void apm32_hwtimer_enable_clock(void) #endif } -static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void apm32_clock_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { #if defined(SOC_SERIES_APM32F0) TMR_TimeBase_T base_config; @@ -337,15 +337,15 @@ static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t stat { timer_config = (struct apm32_timer *)timer->parent.user_data; - apm32_hwtimer_enable_clock(); + apm32_clock_timer_enable_clock(); - prescaler = (uint32_t)(apm32_hwtimer_clock_get(timer_config->tmr) / 10000) - 1; + prescaler = (uint32_t)(apm32_clock_timer_clock_get(timer_config->tmr) / 10000) - 1; base_config.period = 10000 - 1; #if defined(SOC_SERIES_APM32F0) base_config.div = prescaler; base_config.clockDivision = TMR_CKD_DIV1; - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { base_config.counterMode = TMR_COUNTER_MODE_UP; } @@ -357,7 +357,7 @@ static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t stat || defined(SOC_SERIES_APM32F4) base_config.division = prescaler; base_config.clockDivision = TMR_CLOCK_DIV_1; - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { base_config.countMode = TMR_COUNTER_MODE_UP; } @@ -391,7 +391,7 @@ static void apm32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t stat } } -static rt_err_t apm32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t apm32_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; struct apm32_timer *timer_config = RT_NULL; @@ -405,7 +405,7 @@ static rt_err_t apm32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtim /* set timer_config autoReload */ timer_config->tmr->AUTORLD = t - 1; - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ timer_config->tmr->CTRL1_B.SPMEN = 1; @@ -442,7 +442,7 @@ static rt_err_t apm32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtim return result; } -static void apm32_hwtimer_stop(rt_hwtimer_t *timer) +static void apm32_clock_timer_stop(rt_clock_timer_t *timer) { struct apm32_timer *timer_config = RT_NULL; RT_ASSERT(timer != RT_NULL); @@ -453,7 +453,7 @@ static void apm32_hwtimer_stop(rt_hwtimer_t *timer) timer_config->tmr->CNT = 0; } -static rt_err_t apm32_hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t apm32_clock_timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { struct apm32_timer *timer_config = RT_NULL; rt_err_t result = RT_EOK; @@ -467,11 +467,11 @@ static rt_err_t apm32_hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *a switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: /* set timer frequence */ freq = *((rt_uint32_t *)arg); - val = apm32_hwtimer_clock_get(timer_config->tmr) / freq; + val = apm32_clock_timer_clock_get(timer_config->tmr) / freq; /* Configures the timer prescaler */ timer_config->tmr->PSC_B.PSC = val - 1; @@ -485,7 +485,7 @@ static rt_err_t apm32_hwtimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *a return result; } -static rt_uint32_t apm32_hwtimer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t apm32_clock_timer_counter_get(rt_clock_timer_t *timer) { struct apm32_timer *timer_config = RT_NULL; RT_ASSERT(timer != RT_NULL); @@ -494,13 +494,13 @@ static rt_uint32_t apm32_hwtimer_counter_get(rt_hwtimer_t *timer) return timer_config->tmr->CNT; } -static const struct rt_hwtimer_ops apm32_hwtimer_ops = +static const struct rt_clock_timer_ops apm32_clock_timer_ops = { - .init = apm32_hwtimer_init, - .start = apm32_hwtimer_start, - .stop = apm32_hwtimer_stop, - .count_get = apm32_hwtimer_counter_get, - .control = apm32_hwtimer_ctrl, + .init = apm32_clock_timer_init, + .start = apm32_clock_timer_start, + .stop = apm32_clock_timer_stop, + .count_get = apm32_clock_timer_counter_get, + .control = apm32_clock_timer_ctrl, }; @@ -509,7 +509,7 @@ static const struct rt_hwtimer_ops apm32_hwtimer_ops = void TMR1_BRK_UP_TRG_COM_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR1_INDEX].device); TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -519,7 +519,7 @@ void TMR1_BRK_UP_TRG_COM_IRQHandler(void) void TMR1_UP_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR1_INDEX].device); TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -531,12 +531,12 @@ void TMR1_UP_TMR10_IRQHandler(void) rt_interrupt_enter(); if (TMR_ReadIntFlag(TMR1, TMR_INT_UPDATE)) { - rt_device_hwtimer_isr(&tmr_config[TMR1_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR1_INDEX].device); TMR_ClearIntFlag(TMR1, TMR_INT_UPDATE); } if (TMR_ReadIntFlag(TMR10, TMR_INT_UPDATE)) { - rt_device_hwtimer_isr(&tmr_config[TMR10_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR10_INDEX].device); TMR_ClearIntFlag(TMR10, TMR_INT_UPDATE); } rt_interrupt_leave(); @@ -548,7 +548,7 @@ void TMR1_UP_TMR10_IRQHandler(void) void TMR2_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR2_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR2_INDEX].device); TMR_ClearIntFlag(TMR2, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -558,7 +558,7 @@ void TMR2_IRQHandler(void) void TMR3_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR3_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR3_INDEX].device); TMR_ClearIntFlag(TMR3, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -568,7 +568,7 @@ void TMR3_IRQHandler(void) void TMR4_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR4_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR4_INDEX].device); TMR_ClearIntFlag(TMR4, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -578,7 +578,7 @@ void TMR4_IRQHandler(void) void TMR5_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR5_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR5_INDEX].device); TMR_ClearIntFlag(TMR5, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -594,7 +594,7 @@ void TMR5_IRQHandler(void) #endif { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR6_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR6_INDEX].device); TMR_ClearIntFlag(TMR6, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -604,7 +604,7 @@ void TMR5_IRQHandler(void) void TMR7_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR7_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR7_INDEX].device); TMR_ClearIntFlag(TMR7, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -615,7 +615,7 @@ void TMR7_IRQHandler(void) void TMR8_UP_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR8_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR8_INDEX].device); TMR_ClearIntFlag(TMR8, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -627,12 +627,12 @@ void TMR8_UP_TMR13_IRQHandler(void) rt_interrupt_enter(); if (TMR_ReadIntFlag(TMR8, TMR_INT_UPDATE)) { - rt_device_hwtimer_isr(&tmr_config[TMR8_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR8_INDEX].device); TMR_ClearIntFlag(TMR8, TMR_INT_UPDATE); } if (TMR_ReadIntFlag(TMR13, TMR_INT_UPDATE)) { - rt_device_hwtimer_isr(&tmr_config[TMR13_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR13_INDEX].device); TMR_ClearIntFlag(TMR13, TMR_INT_UPDATE); } rt_interrupt_leave(); @@ -644,7 +644,7 @@ void TMR8_UP_TMR13_IRQHandler(void) void TMR1_BRK_TMR9_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR9_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR9_INDEX].device); TMR_ClearIntFlag(TMR9, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -654,7 +654,7 @@ void TMR1_BRK_TMR9_IRQHandler(void) void TMR1_TRG_COM_TMR11_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR11_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR11_INDEX].device); TMR_ClearIntFlag(TMR11, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -664,7 +664,7 @@ void TMR1_TRG_COM_TMR11_IRQHandler(void) void TMR8_BRK_TMR12_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR12_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR12_INDEX].device); TMR_ClearIntFlag(TMR12, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -678,7 +678,7 @@ void TMR8_BRK_TMR12_IRQHandler(void) #endif { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR14_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR14_INDEX].device); TMR_ClearIntFlag(TMR14, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -688,7 +688,7 @@ void TMR8_BRK_TMR12_IRQHandler(void) void TMR15_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR15_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR15_INDEX].device); TMR_ClearIntFlag(TMR15, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -698,7 +698,7 @@ void TMR15_IRQHandler(void) void TMR16_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR16_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR16_INDEX].device); TMR_ClearIntFlag(TMR16, TMR_INT_UPDATE); rt_interrupt_leave(); } @@ -708,13 +708,13 @@ void TMR16_IRQHandler(void) void TMR17_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&tmr_config[TMR17_INDEX].device); + rt_clock_timer_isr(&tmr_config[TMR17_INDEX].device); TMR_ClearIntFlag(TMR17, TMR_INT_UPDATE); rt_interrupt_leave(); } #endif -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { int i = 0; int result = RT_EOK; @@ -722,8 +722,8 @@ static int rt_hw_hwtimer_init(void) for (i = 0; i < sizeof(tmr_config) / sizeof(tmr_config[0]); i++) { tmr_config[i].device.info = &apm32_timer_info; - tmr_config[i].device.ops = &apm32_hwtimer_ops; - if (rt_device_hwtimer_register(&tmr_config[i].device, tmr_config[i].name, &tmr_config[i]) == RT_EOK) + tmr_config[i].device.ops = &apm32_clock_timer_ops; + if (rt_clock_timer_register(&tmr_config[i].device, tmr_config[i].name, &tmr_config[i]) == RT_EOK) { LOG_D("%s register success", tmr_config[i].name); } @@ -736,6 +736,6 @@ static int rt_hw_hwtimer_init(void) return result; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/at32/at32a403a-start/README.md b/bsp/at32/at32a403a-start/README.md index 1ada75f085..bfa6a2d013 100644 --- a/bsp/at32/at32a403a-start/README.md +++ b/bsp/at32/at32a403a-start/README.md @@ -46,7 +46,7 @@ AT32A403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | WDT | 支持 | | diff --git a/bsp/at32/at32a403a-start/board/Kconfig b/bsp/at32/at32a403a-start/board/Kconfig index bae96053cc..b7d8486d27 100644 --- a/bsp/at32/at32a403a-start/board/Kconfig +++ b/bsp/at32/at32a403a-start/board/Kconfig @@ -186,11 +186,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32a403a-start/board/src/at32_msp.c b/bsp/at32/at32a403a-start/board/src/at32_msp.c index 7011c578d2..2876eebdba 100644 --- a/bsp/at32/at32a403a-start/board/src/at32_msp.c +++ b/bsp/at32/at32a403a-start/board/src/at32_msp.c @@ -290,7 +290,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32a423-start/README.md b/bsp/at32/at32a423-start/README.md index ba2f349bd4..6f378267a9 100644 --- a/bsp/at32/at32a423-start/README.md +++ b/bsp/at32/at32a423-start/README.md @@ -46,7 +46,7 @@ AT32A423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3 | +| CLOCK_TIMER | 支持 | TMR3 | | CAN | 支持 | CAN1/2 | | WDT | 支持 | | | RTC | 支持 | | diff --git a/bsp/at32/at32a423-start/board/Kconfig b/bsp/at32/at32a423-start/board/Kconfig index 29d5188758..6da7a57f63 100644 --- a/bsp/at32/at32a423-start/board/Kconfig +++ b/bsp/at32/at32a423-start/board/Kconfig @@ -201,11 +201,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32a423-start/board/src/at32_msp.c b/bsp/at32/at32a423-start/board/src/at32_msp.c index 3a81f5585c..8e6ce1ae49 100644 --- a/bsp/at32/at32a423-start/board/src/at32_msp.c +++ b/bsp/at32/at32a423-start/board/src/at32_msp.c @@ -268,7 +268,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f402-start/README.md b/bsp/at32/at32f402-start/README.md index af52939a66..caf42a77f0 100644 --- a/bsp/at32/at32f402-start/README.md +++ b/bsp/at32/at32f402-start/README.md @@ -45,7 +45,7 @@ AT32F402-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4 | +| CLOCK_TIMER | 支持 | TMR3/4 | | CAN | 支持 | CAN1 | | QSPI | 支持 | QSPI1/2 | | WDT | 支持 | | diff --git a/bsp/at32/at32f402-start/board/Kconfig b/bsp/at32/at32f402-start/board/Kconfig index ae21e7e68e..58d9aa1a64 100644 --- a/bsp/at32/at32f402-start/board/Kconfig +++ b/bsp/at32/at32f402-start/board/Kconfig @@ -212,11 +212,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f402-start/board/src/at32_msp.c b/bsp/at32/at32f402-start/board/src/at32_msp.c index 9afbb74cfc..9f22f260bf 100644 --- a/bsp/at32/at32f402-start/board/src/at32_msp.c +++ b/bsp/at32/at32f402-start/board/src/at32_msp.c @@ -261,7 +261,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f403a-start/README.md b/bsp/at32/at32f403a-start/README.md index 2b9504a6f5..53d307caa0 100644 --- a/bsp/at32/at32f403a-start/README.md +++ b/bsp/at32/at32f403a-start/README.md @@ -46,7 +46,7 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | WDT | 支持 | | diff --git a/bsp/at32/at32f403a-start/board/Kconfig b/bsp/at32/at32f403a-start/board/Kconfig index b905e52b7c..a12ff97a97 100644 --- a/bsp/at32/at32f403a-start/board/Kconfig +++ b/bsp/at32/at32f403a-start/board/Kconfig @@ -186,11 +186,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f403a-start/board/src/at32_msp.c b/bsp/at32/at32f403a-start/board/src/at32_msp.c index 848ff32cdd..e947bcdcab 100644 --- a/bsp/at32/at32f403a-start/board/src/at32_msp.c +++ b/bsp/at32/at32f403a-start/board/src/at32_msp.c @@ -290,7 +290,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f405-start/README.md b/bsp/at32/at32f405-start/README.md index 533158aa2c..45beb431f7 100644 --- a/bsp/at32/at32f405-start/README.md +++ b/bsp/at32/at32f405-start/README.md @@ -45,7 +45,7 @@ AT32F405-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4 | +| CLOCK_TIMER | 支持 | TMR3/4 | | CAN | 支持 | CAN1 | | QSPI | 支持 | QSPI1/2 | | WDT | 支持 | | diff --git a/bsp/at32/at32f405-start/board/Kconfig b/bsp/at32/at32f405-start/board/Kconfig index edd92e9320..50f523cd4c 100644 --- a/bsp/at32/at32f405-start/board/Kconfig +++ b/bsp/at32/at32f405-start/board/Kconfig @@ -231,11 +231,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f405-start/board/src/at32_msp.c b/bsp/at32/at32f405-start/board/src/at32_msp.c index da12e07a50..b9ee677888 100644 --- a/bsp/at32/at32f405-start/board/src/at32_msp.c +++ b/bsp/at32/at32f405-start/board/src/at32_msp.c @@ -261,7 +261,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f407-start/README.md b/bsp/at32/at32f407-start/README.md index 9a1eb58965..cf03582eb3 100644 --- a/bsp/at32/at32f407-start/README.md +++ b/bsp/at32/at32f407-start/README.md @@ -46,7 +46,7 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | WDT | 支持 | | diff --git a/bsp/at32/at32f407-start/board/Kconfig b/bsp/at32/at32f407-start/board/Kconfig index 037d736049..c4c7e65048 100644 --- a/bsp/at32/at32f407-start/board/Kconfig +++ b/bsp/at32/at32f407-start/board/Kconfig @@ -209,11 +209,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f407-start/board/src/at32_msp.c b/bsp/at32/at32f407-start/board/src/at32_msp.c index 63ef0c2dee..58a90aa37d 100644 --- a/bsp/at32/at32f407-start/board/src/at32_msp.c +++ b/bsp/at32/at32f407-start/board/src/at32_msp.c @@ -292,7 +292,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f413-start/README.md b/bsp/at32/at32f413-start/README.md index 4eee25d488..437eb51c73 100644 --- a/bsp/at32/at32f413-start/README.md +++ b/bsp/at32/at32f413-start/README.md @@ -45,7 +45,7 @@ AT32F413-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1/2 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | WDT | 支持 | | diff --git a/bsp/at32/at32f413-start/board/Kconfig b/bsp/at32/at32f413-start/board/Kconfig index eb784abc99..b809dd5702 100644 --- a/bsp/at32/at32f413-start/board/Kconfig +++ b/bsp/at32/at32f413-start/board/Kconfig @@ -186,11 +186,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f413-start/board/src/at32_msp.c b/bsp/at32/at32f413-start/board/src/at32_msp.c index fc0498c408..fa6276028d 100644 --- a/bsp/at32/at32f413-start/board/src/at32_msp.c +++ b/bsp/at32/at32f413-start/board/src/at32_msp.c @@ -274,7 +274,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f415-start/README.md b/bsp/at32/at32f415-start/README.md index 7863aeba8f..9f42d4637e 100644 --- a/bsp/at32/at32f415-start/README.md +++ b/bsp/at32/at32f415-start/README.md @@ -45,7 +45,7 @@ AT32F415-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1 | | WDT | 支持 | | diff --git a/bsp/at32/at32f415-start/board/Kconfig b/bsp/at32/at32f415-start/board/Kconfig index b6f1375c83..fd29cc332e 100644 --- a/bsp/at32/at32f415-start/board/Kconfig +++ b/bsp/at32/at32f415-start/board/Kconfig @@ -201,11 +201,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f415-start/board/src/at32_msp.c b/bsp/at32/at32f415-start/board/src/at32_msp.c index 64db65da7a..8522820931 100644 --- a/bsp/at32/at32f415-start/board/src/at32_msp.c +++ b/bsp/at32/at32f415-start/board/src/at32_msp.c @@ -260,7 +260,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f421-start/README.md b/bsp/at32/at32f421-start/README.md index e7abaf68b2..7407728e9e 100644 --- a/bsp/at32/at32f421-start/README.md +++ b/bsp/at32/at32f421-start/README.md @@ -45,7 +45,7 @@ AT32F421-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1 | -| HWTIMER | 支持 | TMR3 | +| CLOCK_TIMER | 支持 | TMR3 | | WDT | 支持 | | | RTC | 支持 | | | FLASH | 支持 | | diff --git a/bsp/at32/at32f421-start/board/Kconfig b/bsp/at32/at32f421-start/board/Kconfig index 982750fdbd..a3e4f931c2 100644 --- a/bsp/at32/at32f421-start/board/Kconfig +++ b/bsp/at32/at32f421-start/board/Kconfig @@ -135,11 +135,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f421-start/board/src/at32_msp.c b/bsp/at32/at32f421-start/board/src/at32_msp.c index a5221a799d..2b0b1b299d 100644 --- a/bsp/at32/at32f421-start/board/src/at32_msp.c +++ b/bsp/at32/at32f421-start/board/src/at32_msp.c @@ -213,7 +213,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f423-start/README.md b/bsp/at32/at32f423-start/README.md index 281074e5f8..4f9698fd76 100644 --- a/bsp/at32/at32f423-start/README.md +++ b/bsp/at32/at32f423-start/README.md @@ -46,7 +46,7 @@ AT32F423-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3 | +| CLOCK_TIMER | 支持 | TMR3 | | CAN | 支持 | CAN1/2 | | WDT | 支持 | | | RTC | 支持 | | diff --git a/bsp/at32/at32f423-start/board/Kconfig b/bsp/at32/at32f423-start/board/Kconfig index a272271c69..51da2462ab 100644 --- a/bsp/at32/at32f423-start/board/Kconfig +++ b/bsp/at32/at32f423-start/board/Kconfig @@ -201,11 +201,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f423-start/board/src/at32_msp.c b/bsp/at32/at32f423-start/board/src/at32_msp.c index 396e8622e8..9216209e3c 100644 --- a/bsp/at32/at32f423-start/board/src/at32_msp.c +++ b/bsp/at32/at32f423-start/board/src/at32_msp.c @@ -269,7 +269,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f425-start/README.md b/bsp/at32/at32f425-start/README.md index 51e063ec2b..aa08bdec06 100644 --- a/bsp/at32/at32f425-start/README.md +++ b/bsp/at32/at32f425-start/README.md @@ -45,7 +45,7 @@ AT32F425-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | SPI | 支持 | SPI1/2 | | ADC | 支持 | ADC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3 | +| CLOCK_TIMER | 支持 | TMR3 | | CAN | 支持 | CAN1 | | WDT | 支持 | | | RTC | 支持 | | diff --git a/bsp/at32/at32f425-start/board/Kconfig b/bsp/at32/at32f425-start/board/Kconfig index 2aa0bd4430..cc47c54329 100644 --- a/bsp/at32/at32f425-start/board/Kconfig +++ b/bsp/at32/at32f425-start/board/Kconfig @@ -201,11 +201,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f425-start/board/src/at32_msp.c b/bsp/at32/at32f425-start/board/src/at32_msp.c index 4f0ba76955..b9ad73631f 100644 --- a/bsp/at32/at32f425-start/board/src/at32_msp.c +++ b/bsp/at32/at32f425-start/board/src/at32_msp.c @@ -250,7 +250,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f435-start/README.md b/bsp/at32/at32f435-start/README.md index c9d2261fef..a9e64eb3e9 100644 --- a/bsp/at32/at32f435-start/README.md +++ b/bsp/at32/at32f435-start/README.md @@ -46,7 +46,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | QSPI | 支持 | QSPI1/2 | diff --git a/bsp/at32/at32f435-start/board/Kconfig b/bsp/at32/at32f435-start/board/Kconfig index 25a75ce530..f00c2718f4 100644 --- a/bsp/at32/at32f435-start/board/Kconfig +++ b/bsp/at32/at32f435-start/board/Kconfig @@ -235,11 +235,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f435-start/board/src/at32_msp.c b/bsp/at32/at32f435-start/board/src/at32_msp.c index dcd558ae8c..acd87d52bb 100644 --- a/bsp/at32/at32f435-start/board/src/at32_msp.c +++ b/bsp/at32/at32f435-start/board/src/at32_msp.c @@ -310,7 +310,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f437-start/README.md b/bsp/at32/at32f437-start/README.md index 9e6b73b89f..c8f7a83a01 100644 --- a/bsp/at32/at32f437-start/README.md +++ b/bsp/at32/at32f437-start/README.md @@ -46,7 +46,7 @@ AT32F437-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | QSPI | 支持 | QSPI1/2 | diff --git a/bsp/at32/at32f437-start/board/Kconfig b/bsp/at32/at32f437-start/board/Kconfig index 5e215329fc..da90f3c231 100644 --- a/bsp/at32/at32f437-start/board/Kconfig +++ b/bsp/at32/at32f437-start/board/Kconfig @@ -258,11 +258,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f437-start/board/src/at32_msp.c b/bsp/at32/at32f437-start/board/src/at32_msp.c index 1a22f367f1..29a4cc9baf 100644 --- a/bsp/at32/at32f437-start/board/src/at32_msp.c +++ b/bsp/at32/at32f437-start/board/src/at32_msp.c @@ -311,7 +311,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f455-start/README.md b/bsp/at32/at32f455-start/README.md index 0770b763d6..6e02fe3b64 100644 --- a/bsp/at32/at32f455-start/README.md +++ b/bsp/at32/at32f455-start/README.md @@ -46,7 +46,7 @@ AT32F455-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | QSPI | 支持 | QSPI1 | diff --git a/bsp/at32/at32f455-start/board/Kconfig b/bsp/at32/at32f455-start/board/Kconfig index 83202f14fe..c8f39b0b80 100644 --- a/bsp/at32/at32f455-start/board/Kconfig +++ b/bsp/at32/at32f455-start/board/Kconfig @@ -221,11 +221,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f455-start/board/src/at32_msp.c b/bsp/at32/at32f455-start/board/src/at32_msp.c index fe9d78816f..b61a2c93f3 100644 --- a/bsp/at32/at32f455-start/board/src/at32_msp.c +++ b/bsp/at32/at32f455-start/board/src/at32_msp.c @@ -310,7 +310,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f456-start/README.md b/bsp/at32/at32f456-start/README.md index 6679f455d3..c9c46312a8 100644 --- a/bsp/at32/at32f456-start/README.md +++ b/bsp/at32/at32f456-start/README.md @@ -46,7 +46,7 @@ AT32F456-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | QSPI | 支持 | QSPI1 | diff --git a/bsp/at32/at32f456-start/board/Kconfig b/bsp/at32/at32f456-start/board/Kconfig index 2bbbca1d38..b474dba771 100644 --- a/bsp/at32/at32f456-start/board/Kconfig +++ b/bsp/at32/at32f456-start/board/Kconfig @@ -221,11 +221,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f456-start/board/src/at32_msp.c b/bsp/at32/at32f456-start/board/src/at32_msp.c index fe9d78816f..b61a2c93f3 100644 --- a/bsp/at32/at32f456-start/board/src/at32_msp.c +++ b/bsp/at32/at32f456-start/board/src/at32_msp.c @@ -310,7 +310,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32f457-start/README.md b/bsp/at32/at32f457-start/README.md index d230bc6127..5e9742b639 100644 --- a/bsp/at32/at32f457-start/README.md +++ b/bsp/at32/at32f457-start/README.md @@ -46,7 +46,7 @@ AT32F457-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3/4/5 | +| CLOCK_TIMER | 支持 | TMR3/4/5 | | SDIO | 支持 | SDIO1 | | CAN | 支持 | CAN1/2 | | QSPI | 支持 | QSPI1 | diff --git a/bsp/at32/at32f457-start/board/Kconfig b/bsp/at32/at32f457-start/board/Kconfig index 73334123df..2fce389a82 100644 --- a/bsp/at32/at32f457-start/board/Kconfig +++ b/bsp/at32/at32f457-start/board/Kconfig @@ -221,11 +221,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32f457-start/board/src/at32_msp.c b/bsp/at32/at32f457-start/board/src/at32_msp.c index f37fac2f43..d665681eda 100644 --- a/bsp/at32/at32f457-start/board/src/at32_msp.c +++ b/bsp/at32/at32f457-start/board/src/at32_msp.c @@ -310,7 +310,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32m412-start/README.md b/bsp/at32/at32m412-start/README.md index 094e639404..9b17cc05e6 100644 --- a/bsp/at32/at32m412-start/README.md +++ b/bsp/at32/at32m412-start/README.md @@ -46,7 +46,7 @@ AT32M412-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1/2 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3 | +| CLOCK_TIMER | 支持 | TMR3 | | CAN | 支持 | CAN1 | | WDT | 支持 | | | RTC | 支持 | | diff --git a/bsp/at32/at32m412-start/board/Kconfig b/bsp/at32/at32m412-start/board/Kconfig index 4bb310d92b..dd541b0145 100644 --- a/bsp/at32/at32m412-start/board/Kconfig +++ b/bsp/at32/at32m412-start/board/Kconfig @@ -135,11 +135,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32m412-start/board/src/at32_msp.c b/bsp/at32/at32m412-start/board/src/at32_msp.c index 30e70be4ac..51d3e07c8c 100644 --- a/bsp/at32/at32m412-start/board/src/at32_msp.c +++ b/bsp/at32/at32m412-start/board/src/at32_msp.c @@ -208,7 +208,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/at32m416-start/README.md b/bsp/at32/at32m416-start/README.md index 9f0243f69c..fd5f19d16f 100644 --- a/bsp/at32/at32m416-start/README.md +++ b/bsp/at32/at32m416-start/README.md @@ -46,7 +46,7 @@ AT32M416-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以 | ADC | 支持 | ADC1/2 | | DAC | 支持 | DAC1/2 | | PWM | 支持 | TMR1/2 | -| HWTIMER | 支持 | TMR3 | +| CLOCK_TIMER | 支持 | TMR3 | | CAN | 支持 | CAN1 | | WDT | 支持 | | | RTC | 支持 | | diff --git a/bsp/at32/at32m416-start/board/Kconfig b/bsp/at32/at32m416-start/board/Kconfig index 1601313f4a..8414740adf 100644 --- a/bsp/at32/at32m416-start/board/Kconfig +++ b/bsp/at32/at32m416-start/board/Kconfig @@ -135,11 +135,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTMR3 bool "Enable hardware timer3" default n diff --git a/bsp/at32/at32m416-start/board/src/at32_msp.c b/bsp/at32/at32m416-start/board/src/at32_msp.c index 30e70be4ac..51d3e07c8c 100644 --- a/bsp/at32/at32m416-start/board/src/at32_msp.c +++ b/bsp/at32/at32m416-start/board/src/at32_msp.c @@ -208,7 +208,7 @@ void at32_msp_adc_init(void *instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void at32_msp_hwtmr_init(void *instance) { tmr_type *tmr_x = (tmr_type *)instance; diff --git a/bsp/at32/libraries/rt_drivers/SConscript b/bsp/at32/libraries/rt_drivers/SConscript index 1a0d17c1ae..090fde5feb 100644 --- a/bsp/at32/libraries/rt_drivers/SConscript +++ b/bsp/at32/libraries/rt_drivers/SConscript @@ -25,8 +25,8 @@ if GetDepend(['RT_USING_SERIAL']): if GetDepend(['BSP_USING_PWM']): src += ['drv_pwm.c'] -if GetDepend(['BSP_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['BSP_USING_CLOCK_TIMER']): + src += ['drv_timer.c'] if GetDepend(['BSP_USING_SPI']): src += ['drv_spi.c'] diff --git a/bsp/at32/libraries/rt_drivers/drv_hwtimer.c b/bsp/at32/libraries/rt_drivers/drv_timer.c similarity index 80% rename from bsp/at32/libraries/rt_drivers/drv_hwtimer.c rename to bsp/at32/libraries/rt_drivers/drv_timer.c index 345638a322..55ff0ed5d0 100644 --- a/bsp/at32/libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/at32/libraries/rt_drivers/drv_timer.c @@ -9,13 +9,13 @@ */ #include "board.h" -#include "drv_hwtimer.h" +#include "drv_timer.h" //#define DRV_DEBUG -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER enum { @@ -80,15 +80,15 @@ enum #endif }; -struct at32_hwtimer +struct at32_clock_timer { - rt_hwtimer_t tmr_device; + rt_clock_timer_t tmr_device; tmr_type* tmr_x; IRQn_Type tmr_irqn; char *name; }; -static struct at32_hwtimer at32_hwtimer_obj[] = +static struct at32_clock_timer at32_clock_timer_obj[] = { #ifdef BSP_USING_HWTMR1 TMR1_CONFIG, @@ -171,19 +171,19 @@ static void tmr_pclk_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler) } } -static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void at32_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { crm_clocks_freq_type clocks_struct; rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0; rt_uint32_t prescaler_value = 0, tmr_clock = 0; tmr_type *tmr_x = RT_NULL; - struct at32_hwtimer *tmr_device = RT_NULL; + struct at32_clock_timer *tmr_device = RT_NULL; RT_ASSERT(timer != RT_NULL); if (state) { tmr_x = (tmr_type *)timer->parent.user_data; - tmr_device = (struct at32_hwtimer *)timer; + tmr_device = (struct at32_clock_timer *)timer; /* timer clock enable */ at32_msp_hwtmr_init(tmr_x); @@ -222,7 +222,7 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) tmr_clock_source_div_set(tmr_x, TMR_CLOCK_DIV1); tmr_repetition_counter_set(tmr_x, 0); - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { tmr_cnt_dir_set(tmr_x, TMR_COUNT_UP); } @@ -241,7 +241,7 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode_t opmode) +static rt_err_t at32_timer_start(rt_clock_timer_t *timer, rt_uint32_t pr, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; tmr_type *tmr_x = RT_NULL; @@ -254,7 +254,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer /* set tmr_x period register */ tmr_period_value_set(tmr_x, pr - 1); - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to one cycle mode */ tmr_one_cycle_mode_enable(tmr_x, TRUE); @@ -271,7 +271,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer return result; } -static void at32_timer_stop(rt_hwtimer_t *timer) +static void at32_timer_stop(rt_clock_timer_t *timer) { tmr_type *tmr_x = RT_NULL; @@ -285,7 +285,7 @@ static void at32_timer_stop(rt_hwtimer_t *timer) tmr_counter_value_set(tmr_x, 0); } -static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t at32_timer_counter_get(rt_clock_timer_t *timer) { tmr_type *tmr_x = RT_NULL; @@ -296,7 +296,7 @@ static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer) return tmr_counter_value_get(tmr_x); } -static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t at32_timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { crm_clocks_freq_type clocks_struct; tmr_type *tmr_x = RT_NULL; @@ -310,7 +310,7 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch(cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint16_t val; @@ -362,8 +362,8 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_info _info = TMR_DEV_INFO_CONFIG; +static const struct rt_clock_timer_ops _ops = { .init = at32_timer_init, .start = at32_timer_start, @@ -380,7 +380,7 @@ void TMR2_GLOBAL_IRQHandler(void) if(tmr_flag_get(TMR2, TMR_OVF_FLAG) == SET) { - rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].tmr_device); + rt_clock_timer_isr(&at32_clock_timer_obj[TMR2_INDEX].tmr_device); tmr_flag_clear(TMR2, TMR_OVF_FLAG); } /* leave interrupt */ @@ -396,7 +396,7 @@ void TMR3_GLOBAL_IRQHandler(void) if(tmr_flag_get(TMR3, TMR_OVF_FLAG) == SET) { - rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].tmr_device); + rt_clock_timer_isr(&at32_clock_timer_obj[TMR3_INDEX].tmr_device); tmr_flag_clear(TMR3, TMR_OVF_FLAG); } /* leave interrupt */ @@ -412,7 +412,7 @@ void TMR4_GLOBAL_IRQHandler(void) if(tmr_flag_get(TMR4, TMR_OVF_FLAG) == SET) { - rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].tmr_device); + rt_clock_timer_isr(&at32_clock_timer_obj[TMR4_INDEX].tmr_device); tmr_flag_clear(TMR4, TMR_OVF_FLAG); } /* leave interrupt */ @@ -428,7 +428,7 @@ void TMR5_GLOBAL_IRQHandler(void) if(tmr_flag_get(TMR5, TMR_OVF_FLAG) == SET) { - rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].tmr_device); + rt_clock_timer_isr(&at32_clock_timer_obj[TMR5_INDEX].tmr_device); tmr_flag_clear(TMR5, TMR_OVF_FLAG); } /* leave interrupt */ @@ -436,22 +436,22 @@ void TMR5_GLOBAL_IRQHandler(void) } #endif -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(at32_hwtimer_obj) / sizeof(at32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(at32_clock_timer_obj) / sizeof(at32_clock_timer_obj[0]); i++) { - at32_hwtimer_obj[i].tmr_device.info = &_info; - at32_hwtimer_obj[i].tmr_device.ops = &_ops; - if (rt_device_hwtimer_register(&at32_hwtimer_obj[i].tmr_device, at32_hwtimer_obj[i].name, at32_hwtimer_obj[i].tmr_x) == RT_EOK) + at32_clock_timer_obj[i].tmr_device.info = &_info; + at32_clock_timer_obj[i].tmr_device.ops = &_ops; + if (rt_clock_timer_register(&at32_clock_timer_obj[i].tmr_device, at32_clock_timer_obj[i].name, at32_clock_timer_obj[i].tmr_x) == RT_EOK) { - LOG_D("%s register success", at32_hwtimer_obj[i].name); + LOG_D("%s register success", at32_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", at32_hwtimer_obj[i].name); + LOG_E("%s register failed", at32_clock_timer_obj[i].name); result = -RT_ERROR; } } @@ -459,6 +459,6 @@ static int rt_hw_hwtimer_init(void) return result; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/at32/libraries/rt_drivers/drv_hwtimer.h b/bsp/at32/libraries/rt_drivers/drv_timer.h similarity index 95% rename from bsp/at32/libraries/rt_drivers/drv_hwtimer.h rename to bsp/at32/libraries/rt_drivers/drv_timer.h index 624437f559..fac966bf24 100644 --- a/bsp/at32/libraries/rt_drivers/drv_hwtimer.h +++ b/bsp/at32/libraries/rt_drivers/drv_timer.h @@ -12,7 +12,7 @@ #define __TMR_CONFIG_H__ #include -#include +#include #ifdef __cplusplus extern "C" { @@ -24,7 +24,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 4000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/at91/at91sam9g45/project.ewp b/bsp/at91/at91sam9g45/project.ewp index a3b12ade7f..6282b32b53 100644 --- a/bsp/at91/at91sam9g45/project.ewp +++ b/bsp/at91/at91sam9g45/project.ewp @@ -329,7 +329,7 @@ $PROJ_DIR$\..\..\..\components\drivers\include $PROJ_DIR$\drivers $PROJ_DIR$\..\..\..\components\libc\compilers\common\extension - $PROJ_DIR$\..\..\..\components\drivers\ktime + $PROJ_DIR$\..\..\..\components\drivers\clock_time $PROJ_DIR$\. $PROJ_DIR$\..\..\..\include $PROJ_DIR$\..\..\..\components\libc\posix\delay @@ -340,7 +340,7 @@ $PROJ_DIR$\..\..\..\components\drivers\phy $PROJ_DIR$\..\..\..\components\dfs\dfs_v1\filesystems\devfs $PROJ_DIR$\..\..\..\components\dfs\dfs_v1\include - $PROJ_DIR$\..\..\..\components\drivers\ktime\inc + $PROJ_DIR$\..\..\..\components\drivers\clock_time\inc - ktime + clock_time - $PROJ_DIR$\..\..\..\components\drivers\ktime\src\cputimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_time_core.c - $PROJ_DIR$\..\..\..\components\drivers\ktime\src\boottime.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_boottime.c - $PROJ_DIR$\..\..\..\components\drivers\ktime\src\hrtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_hrtimer.c diff --git a/bsp/at91/at91sam9g45/project.uvproj b/bsp/at91/at91sam9g45/project.uvproj index 7f2d693077..7368f3098b 100644 --- a/bsp/at91/at91sam9g45/project.uvproj +++ b/bsp/at91/at91sam9g45/project.uvproj @@ -359,7 +359,7 @@ __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS - ..\..\..\components\libc\posix\io\poll;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\ktime\inc;..\..\..\libcpu\arm\arm926;applications;..\..\..\components\libc\posix\tls;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\drivers\phy;.;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\cplusplus;platform;..\..\..\components\libc\posix\pthreads;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\components\drivers\ktime;..\..\..\components\drivers\smp_call;drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\delay + ..\..\..\components\libc\posix\io\poll;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\clock_time\inc;..\..\..\libcpu\arm\arm926;applications;..\..\..\components\libc\posix\tls;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\drivers\phy;.;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\cplusplus;platform;..\..\..\components\libc\posix\pthreads;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\components\drivers\clock_time;..\..\..\components\drivers\smp_call;drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\delay @@ -1222,12 +1222,12 @@ - ktime + clock_time - boottime.c + clock_boottime.c 1 - ..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\components\drivers\clock_time\clock_boottime.c @@ -1244,9 +1244,9 @@ - cputimer.c + clock_time_core.c 1 - ..\..\..\components\drivers\ktime\src\cputimer.c + ..\..\..\components\drivers\clock_time\clock_time_core.c @@ -1263,9 +1263,9 @@ - hrtimer.c + clock_hrtimer.c 1 - ..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\components\drivers\clock_time\clock_hrtimer.c diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig index fec93e4e68..670a59980c 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig @@ -178,7 +178,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/bluetrum/libraries/hal_drivers/SConscript b/bsp/bluetrum/libraries/hal_drivers/SConscript index b35a6e89cc..0a6dd7e0cd 100644 --- a/bsp/bluetrum/libraries/hal_drivers/SConscript +++ b/bsp/bluetrum/libraries/hal_drivers/SConscript @@ -23,8 +23,8 @@ if GetDepend('RT_USING_I2C'): if GetDepend('RT_USING_WDT'): src += ['drv_wdt.c'] -if GetDepend('RT_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('RT_USING_CLOCK_TIME'): + src += ['drv_timer.c'] if GetDepend('RT_USING_PWM'): src += ['drv_pwm.c'] diff --git a/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h b/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h index b1c29ae1e8..ae67d24172 100644 --- a/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h +++ b/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c b/bsp/bluetrum/libraries/hal_drivers/drv_timer.c similarity index 60% rename from bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c rename to bsp/bluetrum/libraries/hal_drivers/drv_timer.c index ef925fa037..b79116a238 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_timer.c @@ -13,10 +13,10 @@ #include "tim_config.h" //#define DRV_DEBUG -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME enum { @@ -37,15 +37,15 @@ enum #endif }; -struct ab32_hwtimer +struct ab32_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; hal_sfr_t tim_handle; char *name; irq_type tim_irqn; }; -static struct ab32_hwtimer ab32_hwtimer_obj[] = +static struct ab32_clock_timer ab32_clock_timer_obj[] = { #ifdef BSP_USING_TIM1 TIM1_CONFIG, @@ -69,7 +69,7 @@ static struct ab32_hwtimer ab32_hwtimer_obj[] = }; rt_section(".irq.timer") -static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer) +static void _rt_clock_timer_isr(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -84,7 +84,7 @@ static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer) { timer->cycles = timer->reload; - if (timer->mode == HWTIMER_MODE_ONESHOT) + if (timer->mode == CLOCK_TIMER_MODE_ONESHOT) { if (timer->ops->stop != RT_NULL) { @@ -94,27 +94,27 @@ static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer) if (timer->parent.rx_indicate != RT_NULL) { - timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval)); + timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_clock_timerval)); } } } -static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { rt_uint32_t prescaler_value = 0; hal_sfr_t tim = RT_NULL; - struct ab32_hwtimer *tim_device = RT_NULL; + struct ab32_clock_timer *tim_device = RT_NULL; RT_ASSERT(timer != RT_NULL); tim = (hal_sfr_t)timer->parent.user_data; if (state) { - tim_device = (struct ab32_hwtimer *)timer; + tim_device = (struct ab32_clock_timer *)timer; - if (timer->info->cntmode != HWTIMER_CNTMODE_UP) + if (timer->info->cntmode != CLOCK_TIMER_CNTMODE_UP) { - LOG_E("Only support HWTIMER_CNTMODE_UP!"); + LOG_E("Only support CLOCK_TIMER_CNTMODE_UP!"); } /* set tim int */ @@ -127,7 +127,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; hal_sfr_t tim = RT_NULL; @@ -140,9 +140,9 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ tim[TMRxCNT] = 0; tim[TMRxPR] = t * (get_sysclk_nhz() / timer->freq) - 1; - if (opmode != HWTIMER_MODE_PERIOD) + if (opmode != CLOCK_TIMER_MODE_PERIOD) { - LOG_E("Opmode only support HWTIMER_MODE_PERIOD!"); + LOG_E("Opmode only support CLOCK_TIMER_MODE_PERIOD!"); return -RT_EINVAL; } @@ -152,7 +152,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ return result; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { hal_sfr_t tim = RT_NULL; @@ -167,7 +167,7 @@ static void timer_stop(rt_hwtimer_t *timer) tim[TMRxCNT] = 0; } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { hal_sfr_t tim = RT_NULL; rt_err_t result = RT_EOK; @@ -179,7 +179,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { } break; @@ -193,7 +193,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { hal_sfr_t tim = RT_NULL; @@ -204,9 +204,9 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) return tim[TMRxCNT] / (get_sysclk_nhz() / timer->freq); } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -221,21 +221,21 @@ void timer2_4_5_isr(int vector, void *param) { rt_interrupt_enter(); #ifdef BSP_USING_TIM2 - if (ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) { - ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9); - _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device); + if (ab32_clock_timer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) { + ab32_clock_timer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9); + _rt_clock_timer_isr(&ab32_clock_timer_obj[TIM2_INDEX].time_device); } #endif #ifdef BSP_USING_TIM4 - if (ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) { - ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9); - _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device); + if (ab32_clock_timer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) { + ab32_clock_timer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9); + _rt_clock_timer_isr(&ab32_clock_timer_obj[TIM4_INDEX].time_device); } #endif #ifdef BSP_USING_TIM5 - if (ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) { - ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9); - _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device); + if (ab32_clock_timer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) { + ab32_clock_timer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9); + _rt_clock_timer_isr(&ab32_clock_timer_obj[TIM5_INDEX].time_device); } #endif rt_interrupt_leave(); @@ -247,8 +247,8 @@ rt_section(".irq.timer") void timer3_isr(int vector, void *param) { rt_interrupt_enter(); - ab32_hwtimer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9); - _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device); + ab32_clock_timer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9); + _rt_clock_timer_isr(&ab32_clock_timer_obj[TIM3_INDEX].time_device); rt_interrupt_leave(); } #endif @@ -258,28 +258,28 @@ rt_section(".irq.timer") void timer1_isr(int vector, void *param) { rt_interrupt_enter(); - ab32_hwtimer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9); - _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device); + ab32_clock_timer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9); + _rt_clock_timer_isr(&ab32_clock_timer_obj[TIM1_INDEX].time_device); rt_interrupt_leave(); } #endif -static int ab32_hwtimer_init(void) +static int ab32_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(ab32_hwtimer_obj) / sizeof(ab32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(ab32_clock_timer_obj) / sizeof(ab32_clock_timer_obj[0]); i++) { - ab32_hwtimer_obj[i].time_device.info = &_info; - ab32_hwtimer_obj[i].time_device.ops = &_ops; - if (rt_device_hwtimer_register(&ab32_hwtimer_obj[i].time_device, ab32_hwtimer_obj[i].name, (void *)ab32_hwtimer_obj[i].tim_handle) == RT_EOK) + ab32_clock_timer_obj[i].time_device.info = &_info; + ab32_clock_timer_obj[i].time_device.ops = &_ops; + if (rt_clock_timer_register(&ab32_clock_timer_obj[i].time_device, ab32_clock_timer_obj[i].name, (void *)ab32_clock_timer_obj[i].tim_handle) == RT_EOK) { - LOG_D("%s register success", ab32_hwtimer_obj[i].name); + LOG_D("%s register success", ab32_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", ab32_hwtimer_obj[i].name); + LOG_E("%s register failed", ab32_clock_timer_obj[i].name); result = -RT_ERROR; } } @@ -296,7 +296,7 @@ static int ab32_hwtimer_init(void) return result; } -INIT_BOARD_EXPORT(ab32_hwtimer_init); +INIT_BOARD_EXPORT(ab32_clock_timer_init); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ #endif /* BSP_USING_TIM */ diff --git a/bsp/bouffalo_lab/README.md b/bsp/bouffalo_lab/README.md index 2628406a66..c22fa5fabe 100755 --- a/bsp/bouffalo_lab/README.md +++ b/bsp/bouffalo_lab/README.md @@ -198,7 +198,7 @@ Windows下推荐使用[env工具][1]，在console下进入bsp/bouffalo_lab/bl61x | ADC | 支持 | | | RTC | 支持 | | | WDT | 支持 | | -| HWTIMER | 支持 | | +| CLOCK_TIMER | 支持 | | | FLASH | 支持 | | | SDCARD | 支持 | | | Wi-Fi | 支持 | 仅 BL808 支持 | diff --git a/bsp/bouffalo_lab/README_en.md b/bsp/bouffalo_lab/README_en.md index bb73ed8bf7..6aa5e9bc6a 100644 --- a/bsp/bouffalo_lab/README_en.md +++ b/bsp/bouffalo_lab/README_en.md @@ -180,7 +180,7 @@ If the compilation and flashing are successful, when you reset the device, you w | ADC | Supported | | | RTC | Supported | | | WDT | Supported | | -| HWTIMER | Supported | | +| CLOCK_TIMER | Supported | | | FLASH | Supported | | | SDCARD | Supported | | diff --git a/bsp/bouffalo_lab/libraries/Kconfig b/bsp/bouffalo_lab/libraries/Kconfig index 62737d7920..c12477ca80 100755 --- a/bsp/bouffalo_lab/libraries/Kconfig +++ b/bsp/bouffalo_lab/libraries/Kconfig @@ -791,11 +791,11 @@ menu "General Drivers Configuration" default n endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TIMER0 bool "Enable TIMER0" default n diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/SConscript b/bsp/bouffalo_lab/libraries/rt_drivers/SConscript index c3b16c8dea..39396ad7a7 100755 --- a/bsp/bouffalo_lab/libraries/rt_drivers/SConscript +++ b/bsp/bouffalo_lab/libraries/rt_drivers/SConscript @@ -29,9 +29,9 @@ if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] src += ['sample/wdt_sample.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] - src += ['sample/hwtimer_sample.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] + src += ['sample/clock_timer_sample.c'] if GetDepend('BSP_USING_SPI'): src += ['drv_spi.c'] diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_hwtimer.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_timer.c similarity index 66% rename from bsp/bouffalo_lab/libraries/rt_drivers/drv_hwtimer.c rename to bsp/bouffalo_lab/libraries/rt_drivers/drv_timer.c index 8256e226bd..c2ed973f69 100644 --- a/bsp/bouffalo_lab/libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_timer.c @@ -8,45 +8,45 @@ * 2023-04-01 wcx1024979076 first version */ -#include "drv_hwtimer.h" +#include "drv_timer.h" #include #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER #define DBG_LEVEL DBG_LOG #include -#define LOG_TAG "DRV.HWTIMER" +#define LOG_TAG "DRV.CLOCK_TIMER" typedef struct _gptimer { const char *name; - rt_hwtimer_t timer; + rt_clock_timer_t timer; struct bflb_device_s *bflb_timer; } _gptimer_t; -static void _hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode); -static void _hwtimer_stop(rt_hwtimer_t *timer); -static rt_uint32_t _hwtimer_count_get(rt_hwtimer_t *timer); -static rt_err_t _hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void _clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t _clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode); +static void _clock_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t _clock_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t _clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); static void _hwtmr_isr(_gptimer_t *gptmr); -static const struct rt_hwtimer_ops _hwtimer_ops = { - .init = _hwtimer_init, - .start = _hwtimer_start, - .stop = _hwtimer_stop, - .count_get = _hwtimer_count_get, - .control = _hwtimer_control +static const struct rt_clock_timer_ops _clock_timer_ops = { + .init = _clock_timer_init, + .start = _clock_timer_start, + .stop = _clock_timer_stop, + .count_get = _clock_timer_count_get, + .control = _clock_timer_control }; -static const struct rt_hwtimer_info _hwtimer_info = { +static const struct rt_clock_timer_info _clock_timer_info = { .maxfreq = 1000000UL, .minfreq = 1000000UL, .maxcnt = 0xFFFFFFFFUL, - .cntmode = HWTIMER_MODE_PERIOD + .cntmode = CLOCK_TIMER_MODE_PERIOD }; #ifdef BSP_USING_TIMER0 @@ -84,12 +84,12 @@ static void _hwtmr_isr(_gptimer_t *timer) bool hwtmr_stat = bflb_timer_get_compint_status(timer->bflb_timer, TIMER_COMP_ID_0); if (hwtmr_stat) { - rt_device_hwtimer_isr(&timer->timer); + rt_clock_timer_isr(&timer->timer); bflb_timer_compint_clear(timer->bflb_timer, TIMER_COMP_ID_0); } } -static void _hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void _clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { _gptimer_t *_gptmr = (_gptimer_t*)timer->parent.user_data; @@ -106,12 +106,12 @@ static void _hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) bflb_timer_init(_gptmr->bflb_timer, &cfg); } -static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t _clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { _gptimer_t *_gptmr = (_gptimer_t*) timer->parent.user_data; struct bflb_timer_config_s cfg; - if(mode == HWTIMER_MODE_ONESHOT) + if(mode == CLOCK_TIMER_MODE_ONESHOT) cfg.counter_mode = TIMER_COUNTER_MODE_UP; else cfg.counter_mode = TIMER_COUNTER_MODE_PROLOAD; @@ -130,13 +130,13 @@ static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ return RT_EOK; } -static void _hwtimer_stop(rt_hwtimer_t *timer) +static void _clock_timer_stop(rt_clock_timer_t *timer) { _gptimer_t *_gptmr = (_gptimer_t*)timer->parent.user_data; bflb_timer_stop(_gptmr->bflb_timer); } -static rt_uint32_t _hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t _clock_timer_count_get(rt_clock_timer_t *timer) { _gptimer_t *_gptmr = (_gptimer_t*)timer->parent.user_data; @@ -145,22 +145,22 @@ static rt_uint32_t _hwtimer_count_get(rt_hwtimer_t *timer) return current_cnt; } -static rt_err_t _hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t _clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; _gptimer_t *_gptmr = (_gptimer_t*) timer->parent.user_data; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: err = -RT_ERROR; break; - case HWTIMER_CTRL_INFO_GET: - *(rt_hwtimer_t*)args = _gptmr->timer; + case CLOCK_TIMER_CTRL_INFO_GET: + *(rt_clock_timer_t*)args = _gptmr->timer; break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: _gptmr->timer.mode = *(rt_uint32_t*)args; break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: bflb_timer_stop(_gptmr->bflb_timer); break; } @@ -169,15 +169,15 @@ static rt_err_t _hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { int ret = RT_EOK; for (uint32_t i = 0; i < sizeof(s_gptimers) / sizeof(s_gptimers[0]); i++) { - s_gptimers[i]->timer.info = &_hwtimer_info; - s_gptimers[i]->timer.ops = &_hwtimer_ops; + s_gptimers[i]->timer.info = &_clock_timer_info; + s_gptimers[i]->timer.ops = &_clock_timer_ops; s_gptimers[i]->bflb_timer = bflb_device_get_by_name(s_gptimers[i]->name); - ret = rt_device_hwtimer_register(&s_gptimers[i]->timer, s_gptimers[i]->name, s_gptimers[i]); + ret = rt_clock_timer_register(&s_gptimers[i]->timer, s_gptimers[i]->name, s_gptimers[i]); if (ret != RT_EOK) { LOG_E("%s register failed", s_gptimers[i]->name); @@ -195,5 +195,5 @@ int rt_hw_hwtimer_init(void) return ret; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); -#endif /* BSP_USING_HWTIMER */ +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_hwtimer.h b/bsp/bouffalo_lab/libraries/rt_drivers/drv_timer.h similarity index 71% rename from bsp/bouffalo_lab/libraries/rt_drivers/drv_hwtimer.h rename to bsp/bouffalo_lab/libraries/rt_drivers/drv_timer.h index 6f3cfbc7ae..05a6ec1812 100644 --- a/bsp/bouffalo_lab/libraries/rt_drivers/drv_hwtimer.h +++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_timer.h @@ -8,12 +8,12 @@ * 2023-04-01 wcx1024979076 first version */ -#ifndef DRV_HWTIMER_H -#define DRV_HWTIMER_H +#ifndef DRV_CLOCK_TIMER_H +#define DRV_CLOCK_TIMER_H #include "bflb_timer.h" #include "bflb_mtimer.h" #include "board.h" -int rt_hw_hwtimer_init(void); +int rt_hw_clock_timer_init(void); -#endif /* DRV_HWTIMER_H */ +#endif /* DRV_CLOCK_TIMER_H */ diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/sample/hwtimer_sample.c b/bsp/bouffalo_lab/libraries/rt_drivers/sample/clock_timer_sample.c similarity index 65% rename from bsp/bouffalo_lab/libraries/rt_drivers/sample/hwtimer_sample.c rename to bsp/bouffalo_lab/libraries/rt_drivers/sample/clock_timer_sample.c index e2f6e3abb2..3aeaeefbca 100755 --- a/bsp/bouffalo_lab/libraries/rt_drivers/sample/hwtimer_sample.c +++ b/bsp/bouffalo_lab/libraries/rt_drivers/sample/clock_timer_sample.c @@ -8,41 +8,41 @@ * 2023-04-01 wcx1024979076 first version. */ /* - * 程序清单：这是一个 hwtimer 设备使用例程 - * 例程导出了 hwtimer_sample 命令到控制终端 - * 命令调用格式：hwtimer_sample + * 程序清单：这是一个 clock_timer 设备使用例程 + * 例程导出了 clock_timer_sample 命令到控制终端 + * 命令调用格式：clock_timer_sample * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。 */ #include #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* 定时器名称 */ /* 定时器超时回调函数 */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback fucntion!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; /* 定时器超时值 */ + rt_clock_timerval_t timeout_s; /* 定时器超时值 */ rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ - rt_hwtimer_mode_t mode; /* 定时器模式 */ + rt_clock_timer_mode_t mode; /* 定时器模式 */ rt_uint32_t freq = 10000; /* 计数频率 */ /* 查找定时器设备 */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } @@ -50,7 +50,7 @@ static int hwtimer_sample(int argc, char *argv[]) ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } @@ -58,10 +58,10 @@ static int hwtimer_sample(int argc, char *argv[]) rt_device_set_rx_indicate(hw_dev, timeout_cb); /* 设置计数频率(若未设置该项，默认为1Mhz 或 支持的最小计数频率) */ - rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq); - /* 设置模式为周期性定时器（若未设置，默认是HWTIMER_MODE_ONESHOT）*/ - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq); + /* 设置模式为周期性定时器（若未设置，默认是CLOCK_TIMER_MODE_ONESHOT）*/ + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -87,6 +87,6 @@ static int hwtimer_sample(int argc, char *argv[]) return ret; } /* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 49c046748b..104648aa69 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -298,7 +298,7 @@ menu "General Drivers Configuration" menuconfig BSP_USING_TIMER bool "Enable TIMER" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIMER config BSP_USING_TIMER4 bool "Enable TIMER4" diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index f971b18e2c..d0cb78020e 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -298,7 +298,7 @@ menu "General Drivers Configuration" menuconfig BSP_USING_TIMER bool "Enable TIMER" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIMER config BSP_USING_TIMER0 bool "Enable TIMER0" diff --git a/bsp/cvitek/drivers/drv_timer.c b/bsp/cvitek/drivers/drv_timer.c index 4028b77d17..024282ad85 100644 --- a/bsp/cvitek/drivers/drv_timer.c +++ b/bsp/cvitek/drivers/drv_timer.c @@ -135,16 +135,16 @@ typedef struct _timer char *name; dw_timer_regs_t *base; rt_uint32_t irqno; - rt_hwtimer_t timer; + rt_clock_timer_t timer; }_timer_t; -static void _timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t _timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode); -static void _timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t _timer_count_get(rt_hwtimer_t *timer); -static rt_err_t _timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void _timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t _timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode); +static void _timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t _timer_count_get(rt_clock_timer_t *timer); +static rt_err_t _timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); -static const struct rt_hwtimer_ops _timer_ops = { +static const struct rt_clock_timer_ops _timer_ops = { .init = _timer_init, .start = _timer_start, .stop = _timer_stop, @@ -152,11 +152,11 @@ static const struct rt_hwtimer_ops _timer_ops = { .control = _timer_control }; -static const struct rt_hwtimer_info _timer_info = { +static const struct rt_clock_timer_info _timer_info = { .maxfreq = 25000000UL, .minfreq = 25000000UL, .maxcnt = 0xFFFFFFFF, - .cntmode = HWTIMER_MODE_PERIOD + .cntmode = CLOCK_TIMER_MODE_PERIOD }; static _timer_t _timer_obj[] = @@ -333,8 +333,8 @@ static void rt_hw_hwtmr_isr(int irqno, void *param) hal_timer_clear_irq(timer_base); hal_timer_set_disable(timer_base); - rt_device_hwtimer_isr(&_tmr->timer); - if(_tmr->timer.mode == HWTIMER_MODE_PERIOD) + rt_clock_timer_isr(&_tmr->timer); + if(_tmr->timer.mode == CLOCK_TIMER_MODE_PERIOD) { hal_timer_set_enable(timer_base); hal_timer_set_unmask(timer_base); @@ -342,7 +342,7 @@ static void rt_hw_hwtmr_isr(int irqno, void *param) } } -static void _timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void _timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); @@ -353,7 +353,7 @@ static void _timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t _timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t _timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); uint32_t tmp_load = cnt; @@ -375,7 +375,7 @@ static rt_err_t _timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mo return RT_EOK; } -static void _timer_stop(rt_hwtimer_t *timer) +static void _timer_stop(rt_clock_timer_t *timer) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); @@ -383,7 +383,7 @@ static void _timer_stop(rt_hwtimer_t *timer) hal_timer_set_disable(_tmr->base); } -static rt_uint32_t _timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t _timer_count_get(rt_clock_timer_t *timer) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); rt_uint32_t cnt = hal_timer_get_current(_tmr->base); @@ -391,23 +391,23 @@ static rt_uint32_t _timer_count_get(rt_hwtimer_t *timer) return cnt; } -static rt_err_t _timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t _timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: err = -RT_ERROR; break; - case HWTIMER_CTRL_INFO_GET: - *(rt_hwtimer_t*)args = _tmr->timer; + case CLOCK_TIMER_CTRL_INFO_GET: + *(rt_clock_timer_t*)args = _tmr->timer; break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: _tmr->timer.mode = *(rt_uint32_t*)args; break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: _timer_stop(timer); break; default: @@ -428,7 +428,7 @@ int rt_hw_timer_init(void) _timer_obj[i].timer.info = &_timer_info; _timer_obj[i].timer.ops = &_timer_ops; - ret = rt_device_hwtimer_register(&_timer_obj[i].timer, _timer_obj[i].name, &_timer_obj[i]); + ret = rt_clock_timer_register(&_timer_obj[i].timer, _timer_obj[i].name, &_timer_obj[i]); if (ret != RT_EOK) { LOG_E("%s register failed", _timer_obj[i].name); diff --git a/bsp/essemi/es32f0654/drivers/ES/Kconfig b/bsp/essemi/es32f0654/drivers/ES/Kconfig index 6c8b9ba197..7780e9e477 100644 --- a/bsp/essemi/es32f0654/drivers/ES/Kconfig +++ b/bsp/essemi/es32f0654/drivers/ES/Kconfig @@ -89,50 +89,50 @@ menu "PWM Drivers" endmenu menu "HWtimer Drivers" - config BSP_USING_AD16C4T0_HWTIMER + config BSP_USING_AD16C4T0_CLOCK_TIMER bool "Register timer0" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n depends on !BSP_USING_AD16C4T0_PWM - config BSP_USING_GP16C4T0_HWTIMER + config BSP_USING_GP16C4T0_CLOCK_TIMER bool "Register timer1" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n depends on !BSP_USING_GP16C4T0_PWM - config BSP_USING_GP16C2T0_HWTIMER + config BSP_USING_GP16C2T0_CLOCK_TIMER bool "Register timer2" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n depends on !BSP_USING_GP16C2T0_PWM - config BSP_USING_GP16C2T1_HWTIMER + config BSP_USING_GP16C2T1_CLOCK_TIMER bool "Register timer3" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n depends on !BSP_USING_GP16C2T1_PWM - config BSP_USING_BS16T0_HWTIMER + config BSP_USING_BS16T0_CLOCK_TIMER bool "Register timer4" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n - config BSP_USING_BS16T1_HWTIMER + config BSP_USING_BS16T1_CLOCK_TIMER bool "Register timer5" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n depends on !BSP_USING_UART2 - config BSP_USING_BS16T2_HWTIMER + config BSP_USING_BS16T2_CLOCK_TIMER bool "Register timer6" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n depends on !BSP_USING_UART3 - config BSP_USING_BS16T3_HWTIMER + config BSP_USING_BS16T3_CLOCK_TIMER bool "Register timer7" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n endmenu diff --git a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_clock_timer.h similarity index 30% rename from bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h rename to bsp/essemi/es32f0654/drivers/ES/es_conf_info_clock_timer.h index f712810bcb..c4ec5a21e4 100644 --- a/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_hwtimer.h +++ b/bsp/essemi/es32f0654/drivers/ES/es_conf_info_clock_timer.h @@ -21,82 +21,82 @@ * */ -#ifndef __ES_CONF_INFO_HWTIMER_H__ -#define __ES_CONF_INFO_HWTIMER_H__ +#ifndef __ES_CONF_INFO_CLOCK_TIMER_H__ +#define __ES_CONF_INFO_CLOCK_TIMER_H__ #include #include -#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP -#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW +#define ES_C_CLOCK_TIMER_MODE_UP CLOCK_TIMER_CNTMODE_UP +#define ES_C_CLOCK_TIMER_MODE_DOWN CLOCK_TIMER_CNTMODE_DW -/* HWTIMER 配置 */ +/* CLOCK_TIMER 配置 */ /* codes_main */ -#ifndef ES_AD16C4T0_HWTIMER_MODE -#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_AD16C4T0_CLOCK_TIMER_MODE +#define ES_AD16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T0_HWTIMER_MODE -#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T0_CLOCK_TIMER_MODE +#define ES_GP16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T1_HWTIMER_MODE -#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C2T0_CLOCK_TIMER_MODE +#define ES_GP16C2T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T2_HWTIMER_MODE -#define ES_GP16C4T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP1624T1_CLOCK_TIMER_MODE +#define ES_GP16C2T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T0_HWTIMER_MODE -#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T0_CLOCK_TIMER_MODE +#define ES_BS16T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T1_HWTIMER_MODE -#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T1_CLOCK_TIMER_MODE +#define ES_BS16T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T2_HWTIMER_MODE -#define ES_BS16T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T2_CLOCK_TIMER_MODE +#define ES_BS16T2_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T3_HWTIMER_MODE -#define ES_BS16T3_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T3_CLOCK_TIMER_MODE +#define ES_BS16T3_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#define ES_AD16C4T0_HWTIMER_PRES 1 -#define ES_GP16C4T0_HWTIMER_PRES 1 -#define ES_GP16C2T0_HWTIMER_PRES 1 -#define ES_GP16C2T1_HWTIMER_PRES 1 -#define ES_BS16T0_HWTIMER_PRES 1 -#define ES_BS16T1_HWTIMER_PRES 1 -#define ES_BS16T2_HWTIMER_PRES 1 -#define ES_BS16T3_HWTIMER_PRES 1 +#define ES_AD16C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C2T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C2T1_CLOCK_TIMER_PRES 1 +#define ES_BS16T0_CLOCK_TIMER_PRES 1 +#define ES_BS16T1_CLOCK_TIMER_PRES 1 +#define ES_BS16T2_CLOCK_TIMER_PRES 1 +#define ES_BS16T3_CLOCK_TIMER_PRES 1 -#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER -#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#ifndef ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER "timer0" #endif -#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER -#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer1" +#ifndef ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER "timer1" #endif -#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER -#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer2" +#ifndef ES_DEVICE_NAME_GP16C2T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C2T0_CLOCK_TIMER "timer2" #endif -#ifndef ES_DEVICE_NAME_GP16C4T2_HWTIMER -#define ES_DEVICE_NAME_GP16C4T2_HWTIMER "timer3" +#ifndef ES_DEVICE_NAME_GP16C2T1_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C2T1_CLOCK_TIMER "timer3" #endif -#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER -#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer4" +#ifndef ES_DEVICE_NAME_BS16T0_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T0_CLOCK_TIMER "timer4" #endif -#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER -#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer5" +#ifndef ES_DEVICE_NAME_BS16T1_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T1_CLOCK_TIMER "timer5" #endif -#ifndef ES_DEVICE_NAME_BS16T2_HWTIMER -#define ES_DEVICE_NAME_BS16T2_HWTIMER "timer6" +#ifndef ES_DEVICE_NAME_BS16T2_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T2_CLOCK_TIMER "timer6" #endif -#ifndef ES_DEVICE_NAME_BS16T3_HWTIMER -#define ES_DEVICE_NAME_BS16T3_HWTIMER "timer7" +#ifndef ES_DEVICE_NAME_BS16T3_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T3_CLOCK_TIMER "timer7" #endif diff --git a/bsp/essemi/es32f0654/drivers/Kconfig b/bsp/essemi/es32f0654/drivers/Kconfig index 30e2756e40..863ed91bdc 100644 --- a/bsp/essemi/es32f0654/drivers/Kconfig +++ b/bsp/essemi/es32f0654/drivers/Kconfig @@ -43,8 +43,8 @@ endif bool "BSP_USING_EXAMPLE_ADC_VOL" default n - config BSP_USING_EXAMPLE_HWTIMER - bool "BSP_USING_EXAMPLE_HWTIMER" + config BSP_USING_EXAMPLE_CLOCK_TIMER + bool "BSP_USING_EXAMPLE_CLOCK_TIMER" default n config BSP_USING_EXAMPLE_I2C diff --git a/bsp/essemi/es32f0654/drivers/SConscript b/bsp/essemi/es32f0654/drivers/SConscript index 0e34f50b2f..832f91ae8c 100644 --- a/bsp/essemi/es32f0654/drivers/SConscript +++ b/bsp/essemi/es32f0654/drivers/SConscript @@ -45,15 +45,15 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend('BSP_USING_SPI_FLASH'): src += ['drv_spiflash.c'] -# add hwtimer driver code -if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \ - GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'): - src += ['drv_hwtimer.c'] +# add clock_timer driver code +if GetDepend('BSP_USING_AD16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_AD16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP32C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP32C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C2T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C2T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_BS16T0_CLOCK_TIMER') or GetDepend('BSP_USING_BS16T1_CLOCK_TIMERIMER') or \ + GetDepend('BSP_USING_BS16T2_CLOCK_TIMER') or GetDepend('BSP_USING_BS16T3_CLOCK_TIMER'): + src += ['drv_timer.c'] # add pwm driver code if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ @@ -77,8 +77,8 @@ include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] -if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): - src += ['bsp_driver_example/hwtimer_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_CLOCK_TIMER'): + src += ['bsp_driver_example/clock_timer_sample.c'] if GetDepend('BSP_USING_EXAMPLE_I2C'): src += ['bsp_driver_example/i2c_sample.c'] diff --git a/bsp/essemi/es32f0654/drivers/drv_hwtimer.c b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c deleted file mode 100644 index 498d6c3a46..0000000000 --- a/bsp/essemi/es32f0654/drivers/drv_hwtimer.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Change Logs: - * Date Author Notes - * 2019-3-19 wangyq the first version - * 2019-11-01 wangyq update libraries - * 2021-04-20 liuhy the second version - */ - -#include -#include -#include -#include -#include - - -#ifdef RT_USING_HWTIMER - -struct es32f0_hwtimer_dev -{ - rt_hwtimer_t parent; - timer_handle_t *hwtimer_periph; - IRQn_Type IRQn; -}; - -#ifdef BSP_USING_AD16C4T0_HWTIMER -static struct es32f0_hwtimer_dev ad16c4t0_hwtimer; - -static struct rt_hwtimer_info ad16c4t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_AD16C4T0_HWTIMER_MODE -}; - -void AD16C4T0_BRK_UP_TRIG_COM_Handler(void) -{ - ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_GP16C4T0_HWTIMER - -static struct es32f0_hwtimer_dev gp16c4t0_hwtimer; - -static struct rt_hwtimer_info gp16c4t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_GP16C4T0_HWTIMER_MODE -}; - -void GP16C4T0_LCD_Handler(void) -{ - ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_GP16C2T0_HWTIMER - -static struct es32f0_hwtimer_dev gp16c2t0_hwtimer; - -static struct rt_hwtimer_info gp16c2t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_GP16C2T0_HWTIMER_MODE -}; - -void GP16C2T0_Handler(void) -{ - ald_timer_clear_flag_status(gp16c2t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c2t0_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_GP16C2T1_HWTIMER - -static struct es32f0_hwtimer_dev gp16c2t1_hwtimer; - -static struct rt_hwtimer_info gp16c2t1_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_GP16C2T1_HWTIMER_MODE -}; - -void GP16C2T1_Handler(void) -{ - ald_timer_clear_flag_status(gp16c2t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c2t1_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_BS16T0_HWTIMER - -static struct es32f0_hwtimer_dev bs16t0_hwtimer; - -static struct rt_hwtimer_info bs16t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_BS16T0_HWTIMER_MODE -}; - -void BS16T0_Handler(void) -{ - ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_BS16T1_HWTIMER - -static struct es32f0_hwtimer_dev bs16t1_hwtimer; - -static struct rt_hwtimer_info bs16t1_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_BS16T1_HWTIMER_MODE -}; - -void BS16T1_UART2_Handler(void) -{ - ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_BS16T2_HWTIMER - -static struct es32f0_hwtimer_dev bs16t2_hwtimer; - -static struct rt_hwtimer_info bs16t2_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_BS16T2_HWTIMER_MODE -}; - -void BS16T2_UART3_Handler(void) -{ - ald_timer_clear_flag_status(bs16t2_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t2_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_BS16T3_HWTIMER - -static struct es32f0_hwtimer_dev bs16t3_hwtimer; - -static struct rt_hwtimer_info bs16t3_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_BS16T3_HWTIMER_MODE -}; - -void BS16T3_DAC0_Handler(void) -{ - ald_timer_clear_flag_status(bs16t3_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t3_hwtimer.parent); -} - -#endif - -static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; - - - RT_ASSERT(hwtimer != RT_NULL); - - if (1 == state) - { - ald_timer_base_init(hwtimer->hwtimer_periph); - ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); - NVIC_EnableIRQ(hwtimer->IRQn); - } - - hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); - hwtimer_info->maxfreq = hwtimer->parent.freq; - hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; -} - -static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, - rt_uint32_t cnt, - rt_hwtimer_mode_t mode) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); - ald_timer_base_start(hwtimer->hwtimer_periph); - - return RT_EOK; -} - -static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - ald_timer_base_stop(hwtimer->hwtimer_periph); -} - -static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - uint32_t hwtimer_count = 0; - - RT_ASSERT(hwtimer != RT_NULL); - - hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT); - - return hwtimer_count; -} - -static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, - rt_uint32_t cmd, - void *args) -{ - rt_err_t ret = RT_EOK; - rt_uint32_t freq = 0; - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - switch (cmd) - { - case HWTIMER_CTRL_FREQ_SET: - freq = *(rt_uint32_t *)args; - - ret = -RT_ERROR; - - if(freq) - { - double temp,target; - temp = (double)ald_cmu_get_pclk1_clock(); - target = temp/freq; - - if(target < 0x10001) /*最大分频 = max(PRES)+1*/ - { - temp = target - (int)(target); - - if((temp > 0.998)&&(target < 0x10000)) - { - hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; - ret = RT_EOK; - } - if((temp < 0.002)&&(target >= 0x1)) - { - hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; - ret = RT_EOK; - } - - } - - if(ret == RT_EOK) /*更新信息*/ - hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); - - } - - break; - - case HWTIMER_CTRL_STOP: - ald_timer_base_stop(hwtimer->hwtimer_periph); - break; - - default: - ret = -RT_EINVAL; - break; - } - - return ret; -} - -static struct rt_hwtimer_ops es32f0_hwtimer_ops = -{ - es32f0_hwtimer_init, - es32f0_hwtimer_start, - es32f0_hwtimer_stop, - es32f0_hwtimer_count_get, - es32f0_hwtimer_control -}; - -int rt_hw_hwtimer_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_AD16C4T0_HWTIMER - static timer_handle_t ad16c4t0_hwtimer_periph; - - ad16c4t0_hwtimer_periph.perh = AD16C4T0; - ad16c4t0_hwtimer.IRQn = AD16C4T0_BRK_UP_TRIG_COM_IRQn; - - ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; - ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; - - ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; - ad16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); -#endif - -#ifdef BSP_USING_GP16C4T0_HWTIMER - static timer_handle_t gp16c4t0_hwtimer_periph; - - gp16c4t0_hwtimer_periph.perh = GP16C4T0; - gp16c4t0_hwtimer.IRQn = GP16C4T0_LCD_IRQn; - - gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; - gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; - - gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; - gp16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); -#endif - -#ifdef BSP_USING_GP16C2T0_HWTIMER - static timer_handle_t gp16c2t0_hwtimer_periph; - - gp16c2t0_hwtimer_periph.perh = GP16C2T0; - gp16c2t0_hwtimer.IRQn = GP16C2T0_IRQn; - - gp16c2t0_hwtimer_periph.init.prescaler = ES_GP16C2T0_HWTIMER_PRES - 1; - gp16c2t0_hwtimer_periph.init.mode = ( ES_GP16C2T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c2t0_hwtimer.hwtimer_periph = &gp16c2t0_hwtimer_periph; - - gp16c2t0_hwtimer.parent.info = &gp16c2t0_info; - gp16c2t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c2t0_hwtimer.parent, ES_DEVICE_NAME_GP16C2T0_HWTIMER, &gp16c2t0_hwtimer); -#endif - -#ifdef BSP_USING_GP16C2T1_HWTIMER - static timer_handle_t gp16c2t1_hwtimer_periph; - - gp16c2t1_hwtimer_periph.perh = GP16C2T1; - gp16c2t1_hwtimer.IRQn = GP16C2T1_IRQn; - - gp16c2t1_hwtimer_periph.init.prescaler = ES_GP16C2T1_HWTIMER_PRES - 1; - gp16c2t1_hwtimer_periph.init.mode = ( ES_GP16C2T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c2t1_hwtimer.hwtimer_periph = &gp16c2t1_hwtimer_periph; - - gp16c2t1_hwtimer.parent.info = &gp16c2t1_info; - gp16c2t1_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c2t1_hwtimer.parent, ES_DEVICE_NAME_GP16C2T1_HWTIMER, &gp16c2t1_hwtimer); -#endif - -#ifdef BSP_USING_BS16T0_HWTIMER - static timer_handle_t bs16t0_hwtimer_periph; - - bs16t0_hwtimer_periph.perh = BS16T0; - bs16t0_hwtimer.IRQn = BS16T0_IRQn; - - bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; - bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; - - bs16t0_hwtimer.parent.info = &bs16t0_info; - bs16t0_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); -#endif - -#ifdef BSP_USING_BS16T1_HWTIMER - static timer_handle_t bs16t1_hwtimer_periph; - - bs16t1_hwtimer_periph.perh = BS16T1; - bs16t1_hwtimer.IRQn = BS16T1_UART2_IRQn; - - bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; - bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; - - bs16t1_hwtimer.parent.info = &bs16t1_info; - bs16t1_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); -#endif - -#ifdef BSP_USING_BS16T2_HWTIMER - static timer_handle_t bs16t2_hwtimer_periph; - - bs16t2_hwtimer_periph.perh = BS16T2; - bs16t2_hwtimer.IRQn = BS16T2_UART3_IRQn; - - bs16t2_hwtimer_periph.init.prescaler = ES_BS16T2_HWTIMER_PRES - 1; - bs16t2_hwtimer_periph.init.mode = ( ES_BS16T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t2_hwtimer.hwtimer_periph = &bs16t2_hwtimer_periph; - - bs16t2_hwtimer.parent.info = &bs16t2_info; - bs16t2_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t2_hwtimer.parent, ES_DEVICE_NAME_BS16T2_HWTIMER, &bs16t2_hwtimer); -#endif - -#ifdef BSP_USING_BS16T3_HWTIMER - static timer_handle_t bs16t3_hwtimer_periph; - - bs16t3_hwtimer_periph.perh = BS16T3; - bs16t3_hwtimer.IRQn = BS16T3_DAC0_IRQn; - - bs16t3_hwtimer_periph.init.prescaler = ES_BS16T3_HWTIMER_PRES - 1; - bs16t3_hwtimer_periph.init.mode = ( ES_BS16T3_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t3_hwtimer.hwtimer_periph = &bs16t3_hwtimer_periph; - - bs16t3_hwtimer.parent.info = &bs16t3_info; - bs16t3_hwtimer.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t3_hwtimer.parent, ES_DEVICE_NAME_BS16T3_HWTIMER, &bs16t3_hwtimer); -#endif - - - return ret; -} -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); - -#endif diff --git a/bsp/essemi/es32f0654/drivers/drv_timer.c b/bsp/essemi/es32f0654/drivers/drv_timer.c new file mode 100644 index 0000000000..4ae26c0c78 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_timer.c @@ -0,0 +1,453 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-3-19 wangyq the first version + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include +#include + + +#ifdef RT_USING_CLOCK_TIME + +struct es32f0_clock_timer_dev +{ + rt_clock_timer_t parent; + timer_handle_t *clock_timer_periph; + IRQn_Type IRQn; +}; + +#ifdef BSP_USING_AD16C4T0_CLOCK_TIMER +static struct es32f0_clock_timer_dev ad16c4t0_clock_timer; + +static struct rt_clock_timer_info ad16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_CLOCK_TIMER_MODE +}; + +void AD16C4T0_BRK_UP_TRIG_COM_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&ad16c4t0_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C4T0_CLOCK_TIMER + +static struct es32f0_clock_timer_dev gp16c4t0_clock_timer; + +static struct rt_clock_timer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_CLOCK_TIMER_MODE +}; + +void GP16C4T0_LCD_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c4t0_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C2T0_CLOCK_TIMER + +static struct es32f0_clock_timer_dev gp16c2t0_clock_timer; + +static struct rt_clock_timer_info gp16c2t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C2T0_CLOCK_TIMER_MODE +}; + +void GP16C2T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c2t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c2t0_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_GP16C2T1_CLOCK_TIMER + +static struct es32f0_clock_timer_dev gp16c2t1_clock_timer; + +static struct rt_clock_timer_info gp16c2t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C2T1_CLOCK_TIMER_MODE +}; + +void GP16C2T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c2t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c2t1_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_BS16T0_CLOCK_TIMER + +static struct es32f0_clock_timer_dev bs16t0_clock_timer; + +static struct rt_clock_timer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_CLOCK_TIMER_MODE +}; + +void BS16T0_Handler(void) +{ + ald_timer_clear_flag_status(bs16t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t0_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_BS16T1_CLOCK_TIMER + +static struct es32f0_clock_timer_dev bs16t1_clock_timer; + +static struct rt_clock_timer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_CLOCK_TIMER_MODE +}; + +void BS16T1_UART2_Handler(void) +{ + ald_timer_clear_flag_status(bs16t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t1_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_BS16T2_CLOCK_TIMER + +static struct es32f0_clock_timer_dev bs16t2_clock_timer; + +static struct rt_clock_timer_info bs16t2_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T2_CLOCK_TIMER_MODE +}; + +void BS16T2_UART3_Handler(void) +{ + ald_timer_clear_flag_status(bs16t2_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t2_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_BS16T3_CLOCK_TIMER + +static struct es32f0_clock_timer_dev bs16t3_clock_timer; + +static struct rt_clock_timer_info bs16t3_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T3_CLOCK_TIMER_MODE +}; + +void BS16T3_DAC0_Handler(void) +{ + ald_timer_clear_flag_status(bs16t3_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t3_clock_timer.parent); +} + +#endif + +static void es32f0_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) +{ + struct es32f0_clock_timer_dev *clock_timer = (struct es32f0_clock_timer_dev *)timer->parent.user_data; + + struct rt_clock_timer_info *clock_timer_info = (struct rt_clock_timer_info *)timer->info; + + + RT_ASSERT(clock_timer != RT_NULL); + + if (1 == state) + { + ald_timer_base_init(clock_timer->clock_timer_periph); + ald_timer_interrupt_config(clock_timer->clock_timer_periph, TIMER_IT_UPDATE, ENABLE); + NVIC_EnableIRQ(clock_timer->IRQn); + } + + clock_timer->parent.freq = ald_cmu_get_pclk1_clock()/((clock_timer->clock_timer_periph->perh->PRES & 0xFFFF)+1); + clock_timer_info->maxfreq = clock_timer->parent.freq; + clock_timer_info->minfreq = (clock_timer->parent.freq)/0xFFFF; +} + +static rt_err_t es32f0_clock_timer_start(rt_clock_timer_t *timer, + rt_uint32_t cnt, + rt_clock_timer_mode_t mode) +{ + struct es32f0_clock_timer_dev *clock_timer = (struct es32f0_clock_timer_dev *)timer->parent.user_data; + + RT_ASSERT(clock_timer != RT_NULL); + + WRITE_REG(clock_timer->clock_timer_periph->perh->AR, cnt); + ald_timer_base_start(clock_timer->clock_timer_periph); + + return RT_EOK; +} + +static void es32f0_clock_timer_stop(rt_clock_timer_t *timer) +{ + struct es32f0_clock_timer_dev *clock_timer = (struct es32f0_clock_timer_dev *)timer->parent.user_data; + + RT_ASSERT(clock_timer != RT_NULL); + + ald_timer_base_stop(clock_timer->clock_timer_periph); +} + +static rt_uint32_t es32f0_clock_timer_count_get(rt_clock_timer_t *timer) +{ + struct es32f0_clock_timer_dev *clock_timer = (struct es32f0_clock_timer_dev *)timer->parent.user_data; + uint32_t clock_timer_count = 0; + + RT_ASSERT(clock_timer != RT_NULL); + + clock_timer_count = READ_REG(clock_timer->clock_timer_periph->perh->COUNT); + + return clock_timer_count; +} + +static rt_err_t es32f0_clock_timer_control(rt_clock_timer_t *timer, + rt_uint32_t cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t freq = 0; + struct es32f0_clock_timer_dev *clock_timer = (struct es32f0_clock_timer_dev *)timer->parent.user_data; + + RT_ASSERT(clock_timer != RT_NULL); + + switch (cmd) + { + case CLOCK_TIMER_CTRL_FREQ_SET: + freq = *(rt_uint32_t *)args; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*最大分频 = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + clock_timer->clock_timer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + clock_timer->clock_timer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*更新信息*/ + clock_timer->parent.freq = ald_cmu_get_pclk1_clock()/((clock_timer->clock_timer_periph->perh->PRES & 0xFFFF)+1); + + } + + break; + + case CLOCK_TIMER_CTRL_STOP: + ald_timer_base_stop(clock_timer->clock_timer_periph); + break; + + default: + ret = -RT_EINVAL; + break; + } + + return ret; +} + +static struct rt_clock_timer_ops es32f0_clock_timer_ops = +{ + es32f0_clock_timer_init, + es32f0_clock_timer_start, + es32f0_clock_timer_stop, + es32f0_clock_timer_count_get, + es32f0_clock_timer_control +}; + +int rt_hw_clock_timer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_AD16C4T0_CLOCK_TIMER + static timer_handle_t ad16c4t0_clock_timer_periph; + + ad16c4t0_clock_timer_periph.perh = AD16C4T0; + ad16c4t0_clock_timer.IRQn = AD16C4T0_BRK_UP_TRIG_COM_IRQn; + + ad16c4t0_clock_timer_periph.init.prescaler = ES_AD16C4T0_CLOCK_TIMER_PRES - 1; + ad16c4t0_clock_timer_periph.init.mode = ( ES_AD16C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_clock_timer.clock_timer_periph = &ad16c4t0_clock_timer_periph; + + ad16c4t0_clock_timer.parent.info = &ad16c4t0_info; + ad16c4t0_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&ad16c4t0_clock_timer.parent, ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER, &ad16c4t0_clock_timer); +#endif + +#ifdef BSP_USING_GP16C4T0_CLOCK_TIMER + static timer_handle_t gp16c4t0_clock_timer_periph; + + gp16c4t0_clock_timer_periph.perh = GP16C4T0; + gp16c4t0_clock_timer.IRQn = GP16C4T0_LCD_IRQn; + + gp16c4t0_clock_timer_periph.init.prescaler = ES_GP16C4T0_CLOCK_TIMER_PRES - 1; + gp16c4t0_clock_timer_periph.init.mode = ( ES_GP16C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_clock_timer.clock_timer_periph = &gp16c4t0_clock_timer_periph; + + gp16c4t0_clock_timer.parent.info = &gp16c4t0_info; + gp16c4t0_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c4t0_clock_timer.parent, ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER, &gp16c4t0_clock_timer); +#endif + +#ifdef BSP_USING_GP16C2T0_CLOCK_TIMER + static timer_handle_t gp16c2t0_clock_timer_periph; + + gp16c2t0_clock_timer_periph.perh = GP16C2T0; + gp16c2t0_clock_timer.IRQn = GP16C2T0_IRQn; + + gp16c2t0_clock_timer_periph.init.prescaler = ES_GP16C2T0_CLOCK_TIMER_PRES - 1; + gp16c2t0_clock_timer_periph.init.mode = ( ES_GP16C2T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c2t0_clock_timer.clock_timer_periph = &gp16c2t0_clock_timer_periph; + + gp16c2t0_clock_timer.parent.info = &gp16c2t0_info; + gp16c2t0_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c2t0_clock_timer.parent, ES_DEVICE_NAME_GP16C2T0_CLOCK_TIMER, &gp16c2t0_clock_timer); +#endif + +#ifdef BSP_USING_GP16C2T1_CLOCK_TIMER + static timer_handle_t gp16c2t1_clock_timer_periph; + + gp16c2t1_clock_timer_periph.perh = GP16C2T1; + gp16c2t1_clock_timer.IRQn = GP16C2T1_IRQn; + + gp16c2t1_clock_timer_periph.init.prescaler = ES_GP16C2T1_CLOCK_TIMER_PRES - 1; + gp16c2t1_clock_timer_periph.init.mode = ( ES_GP16C2T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c2t1_clock_timer.clock_timer_periph = &gp16c2t1_clock_timer_periph; + + gp16c2t1_clock_timer.parent.info = &gp16c2t1_info; + gp16c2t1_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c2t1_clock_timer.parent, ES_DEVICE_NAME_GP16C2T1_CLOCK_TIMER, &gp16c2t1_clock_timer); +#endif + +#ifdef BSP_USING_BS16T0_CLOCK_TIMER + static timer_handle_t bs16t0_clock_timer_periph; + + bs16t0_clock_timer_periph.perh = BS16T0; + bs16t0_clock_timer.IRQn = BS16T0_IRQn; + + bs16t0_clock_timer_periph.init.prescaler = ES_BS16T0_CLOCK_TIMER_PRES - 1; + bs16t0_clock_timer_periph.init.mode = ( ES_BS16T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_clock_timer.clock_timer_periph = &bs16t0_clock_timer_periph; + + bs16t0_clock_timer.parent.info = &bs16t0_info; + bs16t0_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t0_clock_timer.parent, ES_DEVICE_NAME_BS16T0_CLOCK_TIMER, &bs16t0_clock_timer); +#endif + +#ifdef BSP_USING_BS16T1_CLOCK_TIMER + static timer_handle_t bs16t1_clock_timer_periph; + + bs16t1_clock_timer_periph.perh = BS16T1; + bs16t1_clock_timer.IRQn = BS16T1_UART2_IRQn; + + bs16t1_clock_timer_periph.init.prescaler = ES_BS16T1_CLOCK_TIMER_PRES - 1; + bs16t1_clock_timer_periph.init.mode = ( ES_BS16T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_clock_timer.clock_timer_periph = &bs16t1_clock_timer_periph; + + bs16t1_clock_timer.parent.info = &bs16t1_info; + bs16t1_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t1_clock_timer.parent, ES_DEVICE_NAME_BS16T1_CLOCK_TIMER, &bs16t1_clock_timer); +#endif + +#ifdef BSP_USING_BS16T2_CLOCK_TIMER + static timer_handle_t bs16t2_clock_timer_periph; + + bs16t2_clock_timer_periph.perh = BS16T2; + bs16t2_clock_timer.IRQn = BS16T2_UART3_IRQn; + + bs16t2_clock_timer_periph.init.prescaler = ES_BS16T2_CLOCK_TIMER_PRES - 1; + bs16t2_clock_timer_periph.init.mode = ( ES_BS16T2_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t2_clock_timer.clock_timer_periph = &bs16t2_clock_timer_periph; + + bs16t2_clock_timer.parent.info = &bs16t2_info; + bs16t2_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t2_clock_timer.parent, ES_DEVICE_NAME_BS16T2_CLOCK_TIMER, &bs16t2_clock_timer); +#endif + +#ifdef BSP_USING_BS16T3_CLOCK_TIMER + static timer_handle_t bs16t3_clock_timer_periph; + + bs16t3_clock_timer_periph.perh = BS16T3; + bs16t3_clock_timer.IRQn = BS16T3_DAC0_IRQn; + + bs16t3_clock_timer_periph.init.prescaler = ES_BS16T3_CLOCK_TIMER_PRES - 1; + bs16t3_clock_timer_periph.init.mode = ( ES_BS16T3_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t3_clock_timer.clock_timer_periph = &bs16t3_clock_timer_periph; + + bs16t3_clock_timer.parent.info = &bs16t3_info; + bs16t3_clock_timer.parent.ops = &es32f0_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t3_clock_timer.parent, ES_DEVICE_NAME_BS16T3_CLOCK_TIMER, &bs16t3_clock_timer); +#endif + + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); + +#endif diff --git a/bsp/essemi/es32f365x/drivers/drv_hwtimer.h b/bsp/essemi/es32f0654/drivers/drv_timer.h similarity index 86% rename from bsp/essemi/es32f365x/drivers/drv_hwtimer.h rename to bsp/essemi/es32f0654/drivers/drv_timer.h index bbf51a4771..676ebb2358 100644 --- a/bsp/essemi/es32f365x/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f0654/drivers/drv_timer.h @@ -21,10 +21,10 @@ * 2021-04-20 liuhy the second version */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ -#include "es_conf_info_hwtimer.h" -int rt_hw_hwtimer_init(void); +#include "es_conf_info_clock_timer.h" +int rt_hw_clock_timer_init(void); #endif diff --git a/bsp/essemi/es32f365x/drivers/ES/Kconfig b/bsp/essemi/es32f365x/drivers/ES/Kconfig index cf90fe65c7..21ff44d666 100644 --- a/bsp/essemi/es32f365x/drivers/ES/Kconfig +++ b/bsp/essemi/es32f365x/drivers/ES/Kconfig @@ -166,46 +166,46 @@ menu "RTC Drivers" endmenu -menu "HWTIMER Drivers" +menu "CLOCK_TIMER Drivers" - config BSP_USING_AD16C4T0_HWTIMER - bool "Register HWTIMER0 " - select RT_USING_HWTIMER + config BSP_USING_AD16C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER0 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_AD16C4T1_HWTIMER - bool "Register HWTIMER1 " - select RT_USING_HWTIMER + config BSP_USING_AD16C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER1 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP32C4T0_HWTIMER - bool "Register HWTIMER2 " - select RT_USING_HWTIMER + config BSP_USING_GP32C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER2 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP32C4T1_HWTIMER - bool "Register HWTIMER3 " - select RT_USING_HWTIMER + config BSP_USING_GP32C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER3 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T0_HWTIMER - bool "Register HWTIMER4 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER4 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T1_HWTIMER - bool "Register HWTIMER5 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER5 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_BS16T0_HWTIMER - bool "Register HWTIMER6 " - select RT_USING_HWTIMER + config BSP_USING_BS16T0_CLOCK_TIMER + bool "Register CLOCK_TIMER6 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_BS16T1_HWTIMER - bool "Register HWTIMER7 " - select RT_USING_HWTIMER + config BSP_USING_BS16T1_CLOCK_TIMER + bool "Register CLOCK_TIMER7 " + select RT_USING_CLOCK_TIME default n endmenu @@ -216,37 +216,37 @@ menu "PWM Drivers" bool "Register PWM0 " select RT_USING_PWM default n - depends on !BSP_USING_AD16C4T0_HWTIMER + depends on !BSP_USING_AD16C4T0_CLOCK_TIMER config BSP_USING_AD16C4T1_PWM bool "Register PWM1 " select RT_USING_PWM default n - depends on !BSP_USING_AD16C4T1_HWTIMER + depends on !BSP_USING_AD16C4T1_CLOCK_TIMER config BSP_USING_GP32C4T0_PWM bool "Register PWM2 " select RT_USING_PWM default n - depends on !BSP_USING_GP32C4T0_HWTIMER + depends on !BSP_USING_GP32C4T0_CLOCK_TIMER config BSP_USING_GP32C4T1_PWM bool "Register PWM3 " select RT_USING_PWM default n - depends on !BSP_USING_GP32C4T1_HWTIMER + depends on !BSP_USING_GP32C4T1_CLOCK_TIMER config BSP_USING_GP16C4T0_PWM bool "Register PWM4 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T0_HWTIMER + depends on !BSP_USING_GP16C4T0_CLOCK_TIMER config BSP_USING_GP16C4T1_PWM bool "Register PWM5 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T1_HWTIMER + depends on !BSP_USING_GP16C4T1_CLOCK_TIMER endmenu diff --git a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_clock_timer.h similarity index 30% rename from bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h rename to bsp/essemi/es32f365x/drivers/ES/es_conf_info_clock_timer.h index 18f2ff8aa0..369875a0d6 100644 --- a/bsp/essemi/es32f369x/drivers/ES/es_conf_info_hwtimer.h +++ b/bsp/essemi/es32f365x/drivers/ES/es_conf_info_clock_timer.h @@ -21,81 +21,81 @@ * */ -#ifndef __ES_CONF_INFO_HWTIMER_H__ -#define __ES_CONF_INFO_HWTIMER_H__ +#ifndef __ES_CONF_INFO_CLOCK_TIMER_H__ +#define __ES_CONF_INFO_CLOCK_TIMER_H__ #include #include -#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP -#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW +#define ES_C_CLOCK_TIMER_MODE_UP CLOCK_TIMER_CNTMODE_UP +#define ES_C_CLOCK_TIMER_MODE_DOWN CLOCK_TIMER_CNTMODE_DW -/* HWTIMER 配置 */ +/* CLOCK_TIMER 配置 */ /* codes_main */ -#ifndef ES_AD16C4T0_HWTIMER_MODE -#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_AD16C4T0_CLOCK_TIMER_MODE +#define ES_AD16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_AD16C4T1_HWTIMER_MODE -#define ES_AD16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_AD16C4T1_CLOCK_TIMER_MODE +#define ES_AD16C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP32C4T0_HWTIMER_MODE -#define ES_GP32C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP32C4T0_CLOCK_TIMER_MODE +#define ES_GP32C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP32C4T1_HWTIMER_MODE -#define ES_GP32C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP32C4T1_CLOCK_TIMER_MODE +#define ES_GP32C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T0_HWTIMER_MODE -#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T0_CLOCK_TIMER_MODE +#define ES_GP16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T1_HWTIMER_MODE -#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T1_CLOCK_TIMER_MODE +#define ES_GP16C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T0_HWTIMER_MODE -#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T0_CLOCK_TIMER_MODE +#define ES_BS16T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T1_HWTIMER_MODE -#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T1_CLOCK_TIMER_MODE +#define ES_BS16T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#define ES_AD16C4T0_HWTIMER_PRES 1 -#define ES_AD16C4T1_HWTIMER_PRES 1 -#define ES_GP16C4T0_HWTIMER_PRES 1 -#define ES_GP16C4T1_HWTIMER_PRES 1 -#define ES_GP32C4T0_HWTIMER_PRES 1 -#define ES_GP32C4T1_HWTIMER_PRES 1 -#define ES_BS16T0_HWTIMER_PRES 1 -#define ES_BS16T1_HWTIMER_PRES 1 +#define ES_AD16C4T0_CLOCK_TIMER_PRES 1 +#define ES_AD16C4T1_CLOCK_TIMER_PRES 1 +#define ES_GP16C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C4T1_CLOCK_TIMER_PRES 1 +#define ES_GP32C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP32C4T1_CLOCK_TIMER_PRES 1 +#define ES_BS16T0_CLOCK_TIMER_PRES 1 +#define ES_BS16T1_CLOCK_TIMER_PRES 1 -#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER -#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#ifndef ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER "timer0" #endif -#ifndef ES_DEVICE_NAME_AD16C4T1_HWTIMER -#define ES_DEVICE_NAME_AD16C4T1_HWTIMER "timer1" +#ifndef ES_DEVICE_NAME_AD16C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_AD16C4T1_CLOCK_TIMER "timer1" #endif -#ifndef ES_DEVICE_NAME_GP32C4T0_HWTIMER -#define ES_DEVICE_NAME_GP32C4T0_HWTIMER "timer2" +#ifndef ES_DEVICE_NAME_GP32C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP32C4T0_CLOCK_TIMER "timer2" #endif -#ifndef ES_DEVICE_NAME_GP32C4T1_HWTIMER -#define ES_DEVICE_NAME_GP32C4T1_HWTIMER "timer3" +#ifndef ES_DEVICE_NAME_GP32C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_GP32C4T1_CLOCK_TIMER "timer3" #endif -#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER -#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer4" +#ifndef ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER "timer4" #endif -#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER -#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer5" +#ifndef ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER "timer5" #endif -#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER -#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer6" +#ifndef ES_DEVICE_NAME_BS16T0_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T0_CLOCK_TIMER "timer6" #endif -#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER -#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer7" +#ifndef ES_DEVICE_NAME_BS16T1_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T1_CLOCK_TIMER "timer7" #endif diff --git a/bsp/essemi/es32f365x/drivers/Kconfig b/bsp/essemi/es32f365x/drivers/Kconfig index 81ef72b911..ad4ad5968d 100644 --- a/bsp/essemi/es32f365x/drivers/Kconfig +++ b/bsp/essemi/es32f365x/drivers/Kconfig @@ -45,8 +45,8 @@ endif bool "BSP_USING_EXAMPLE_ADC_VOL" default n - config BSP_USING_EXAMPLE_HWTIMER - bool "BSP_USING_EXAMPLE_HWTIMER" + config BSP_USING_EXAMPLE_CLOCK_TIMER + bool "BSP_USING_EXAMPLE_CLOCK_TIMER" default n config BSP_USING_EXAMPLE_I2C diff --git a/bsp/essemi/es32f365x/drivers/SConscript b/bsp/essemi/es32f365x/drivers/SConscript index 9b38fc3661..843e04de67 100644 --- a/bsp/essemi/es32f365x/drivers/SConscript +++ b/bsp/essemi/es32f365x/drivers/SConscript @@ -48,12 +48,12 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend('BSP_USING_SPI_FLASH'): src += [ES32F36XX_DRV_ROOT+'/drv_spiflash.c'] -# add hwtimer driver code -if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMER'): - src += [ES32F36XX_DRV_ROOT+'/drv_hwtimer.c'] +# add clock_timer driver code +if GetDepend('BSP_USING_AD16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_AD16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP32C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP32C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_BS16T0_CLOCK_TIMER') or GetDepend('BSP_USING_BS16T1_CLOCK_TIMER'): + src += [ES32F36XX_DRV_ROOT+'/drv_timer.c'] # add pwm driver code if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ @@ -76,8 +76,8 @@ include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/adc_vol_sample.c'] -if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): - src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/hwtimer_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_CLOCK_TIMER'): + src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/clock_timer_sample.c'] if GetDepend('BSP_USING_EXAMPLE_I2C'): src += [ES32F36XX_DRV_ROOT+'/bsp_driver_example/i2c_sample.c'] diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h b/bsp/essemi/es32f365x/drivers/drv_timer.h similarity index 86% rename from bsp/essemi/es32f369x/drivers/drv_hwtimer.h rename to bsp/essemi/es32f365x/drivers/drv_timer.h index bbf51a4771..676ebb2358 100644 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f365x/drivers/drv_timer.h @@ -21,10 +21,10 @@ * 2021-04-20 liuhy the second version */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ -#include "es_conf_info_hwtimer.h" -int rt_hw_hwtimer_init(void); +#include "es_conf_info_clock_timer.h" +int rt_hw_clock_timer_init(void); #endif diff --git a/bsp/essemi/es32f369x/drivers/ES/Kconfig b/bsp/essemi/es32f369x/drivers/ES/Kconfig index cf90fe65c7..21ff44d666 100644 --- a/bsp/essemi/es32f369x/drivers/ES/Kconfig +++ b/bsp/essemi/es32f369x/drivers/ES/Kconfig @@ -166,46 +166,46 @@ menu "RTC Drivers" endmenu -menu "HWTIMER Drivers" +menu "CLOCK_TIMER Drivers" - config BSP_USING_AD16C4T0_HWTIMER - bool "Register HWTIMER0 " - select RT_USING_HWTIMER + config BSP_USING_AD16C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER0 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_AD16C4T1_HWTIMER - bool "Register HWTIMER1 " - select RT_USING_HWTIMER + config BSP_USING_AD16C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER1 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP32C4T0_HWTIMER - bool "Register HWTIMER2 " - select RT_USING_HWTIMER + config BSP_USING_GP32C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER2 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP32C4T1_HWTIMER - bool "Register HWTIMER3 " - select RT_USING_HWTIMER + config BSP_USING_GP32C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER3 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T0_HWTIMER - bool "Register HWTIMER4 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER4 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T1_HWTIMER - bool "Register HWTIMER5 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER5 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_BS16T0_HWTIMER - bool "Register HWTIMER6 " - select RT_USING_HWTIMER + config BSP_USING_BS16T0_CLOCK_TIMER + bool "Register CLOCK_TIMER6 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_BS16T1_HWTIMER - bool "Register HWTIMER7 " - select RT_USING_HWTIMER + config BSP_USING_BS16T1_CLOCK_TIMER + bool "Register CLOCK_TIMER7 " + select RT_USING_CLOCK_TIME default n endmenu @@ -216,37 +216,37 @@ menu "PWM Drivers" bool "Register PWM0 " select RT_USING_PWM default n - depends on !BSP_USING_AD16C4T0_HWTIMER + depends on !BSP_USING_AD16C4T0_CLOCK_TIMER config BSP_USING_AD16C4T1_PWM bool "Register PWM1 " select RT_USING_PWM default n - depends on !BSP_USING_AD16C4T1_HWTIMER + depends on !BSP_USING_AD16C4T1_CLOCK_TIMER config BSP_USING_GP32C4T0_PWM bool "Register PWM2 " select RT_USING_PWM default n - depends on !BSP_USING_GP32C4T0_HWTIMER + depends on !BSP_USING_GP32C4T0_CLOCK_TIMER config BSP_USING_GP32C4T1_PWM bool "Register PWM3 " select RT_USING_PWM default n - depends on !BSP_USING_GP32C4T1_HWTIMER + depends on !BSP_USING_GP32C4T1_CLOCK_TIMER config BSP_USING_GP16C4T0_PWM bool "Register PWM4 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T0_HWTIMER + depends on !BSP_USING_GP16C4T0_CLOCK_TIMER config BSP_USING_GP16C4T1_PWM bool "Register PWM5 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T1_HWTIMER + depends on !BSP_USING_GP16C4T1_CLOCK_TIMER endmenu diff --git a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_clock_timer.h similarity index 30% rename from bsp/essemi/es32f365x/drivers/ES/es_conf_info_hwtimer.h rename to bsp/essemi/es32f369x/drivers/ES/es_conf_info_clock_timer.h index 18f2ff8aa0..369875a0d6 100644 --- a/bsp/essemi/es32f365x/drivers/ES/es_conf_info_hwtimer.h +++ b/bsp/essemi/es32f369x/drivers/ES/es_conf_info_clock_timer.h @@ -21,81 +21,81 @@ * */ -#ifndef __ES_CONF_INFO_HWTIMER_H__ -#define __ES_CONF_INFO_HWTIMER_H__ +#ifndef __ES_CONF_INFO_CLOCK_TIMER_H__ +#define __ES_CONF_INFO_CLOCK_TIMER_H__ #include #include -#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP -#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW +#define ES_C_CLOCK_TIMER_MODE_UP CLOCK_TIMER_CNTMODE_UP +#define ES_C_CLOCK_TIMER_MODE_DOWN CLOCK_TIMER_CNTMODE_DW -/* HWTIMER 配置 */ +/* CLOCK_TIMER 配置 */ /* codes_main */ -#ifndef ES_AD16C4T0_HWTIMER_MODE -#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_AD16C4T0_CLOCK_TIMER_MODE +#define ES_AD16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_AD16C4T1_HWTIMER_MODE -#define ES_AD16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_AD16C4T1_CLOCK_TIMER_MODE +#define ES_AD16C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP32C4T0_HWTIMER_MODE -#define ES_GP32C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP32C4T0_CLOCK_TIMER_MODE +#define ES_GP32C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP32C4T1_HWTIMER_MODE -#define ES_GP32C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP32C4T1_CLOCK_TIMER_MODE +#define ES_GP32C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T0_HWTIMER_MODE -#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T0_CLOCK_TIMER_MODE +#define ES_GP16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T1_HWTIMER_MODE -#define ES_GP16C4T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T1_CLOCK_TIMER_MODE +#define ES_GP16C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T0_HWTIMER_MODE -#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T0_CLOCK_TIMER_MODE +#define ES_BS16T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T1_HWTIMER_MODE -#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T1_CLOCK_TIMER_MODE +#define ES_BS16T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#define ES_AD16C4T0_HWTIMER_PRES 1 -#define ES_AD16C4T1_HWTIMER_PRES 1 -#define ES_GP16C4T0_HWTIMER_PRES 1 -#define ES_GP16C4T1_HWTIMER_PRES 1 -#define ES_GP32C4T0_HWTIMER_PRES 1 -#define ES_GP32C4T1_HWTIMER_PRES 1 -#define ES_BS16T0_HWTIMER_PRES 1 -#define ES_BS16T1_HWTIMER_PRES 1 +#define ES_AD16C4T0_CLOCK_TIMER_PRES 1 +#define ES_AD16C4T1_CLOCK_TIMER_PRES 1 +#define ES_GP16C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C4T1_CLOCK_TIMER_PRES 1 +#define ES_GP32C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP32C4T1_CLOCK_TIMER_PRES 1 +#define ES_BS16T0_CLOCK_TIMER_PRES 1 +#define ES_BS16T1_CLOCK_TIMER_PRES 1 -#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER -#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#ifndef ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER "timer0" #endif -#ifndef ES_DEVICE_NAME_AD16C4T1_HWTIMER -#define ES_DEVICE_NAME_AD16C4T1_HWTIMER "timer1" +#ifndef ES_DEVICE_NAME_AD16C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_AD16C4T1_CLOCK_TIMER "timer1" #endif -#ifndef ES_DEVICE_NAME_GP32C4T0_HWTIMER -#define ES_DEVICE_NAME_GP32C4T0_HWTIMER "timer2" +#ifndef ES_DEVICE_NAME_GP32C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP32C4T0_CLOCK_TIMER "timer2" #endif -#ifndef ES_DEVICE_NAME_GP32C4T1_HWTIMER -#define ES_DEVICE_NAME_GP32C4T1_HWTIMER "timer3" +#ifndef ES_DEVICE_NAME_GP32C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_GP32C4T1_CLOCK_TIMER "timer3" #endif -#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER -#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer4" +#ifndef ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER "timer4" #endif -#ifndef ES_DEVICE_NAME_GP16C4T1_HWTIMER -#define ES_DEVICE_NAME_GP16C4T1_HWTIMER "timer5" +#ifndef ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER "timer5" #endif -#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER -#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer6" +#ifndef ES_DEVICE_NAME_BS16T0_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T0_CLOCK_TIMER "timer6" #endif -#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER -#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer7" +#ifndef ES_DEVICE_NAME_BS16T1_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T1_CLOCK_TIMER "timer7" #endif diff --git a/bsp/essemi/es32f369x/drivers/Kconfig b/bsp/essemi/es32f369x/drivers/Kconfig index 8eade9ab28..c25b38fab1 100644 --- a/bsp/essemi/es32f369x/drivers/Kconfig +++ b/bsp/essemi/es32f369x/drivers/Kconfig @@ -57,8 +57,8 @@ endif bool "BSP_USING_EXAMPLE_ADC_VOL" default n - config BSP_USING_EXAMPLE_HWTIMER - bool "BSP_USING_EXAMPLE_HWTIMER" + config BSP_USING_EXAMPLE_CLOCK_TIMER + bool "BSP_USING_EXAMPLE_CLOCK_TIMER" default n config BSP_USING_EXAMPLE_I2C diff --git a/bsp/essemi/es32f369x/drivers/SConscript b/bsp/essemi/es32f369x/drivers/SConscript index 950f8c70e9..369c09ad66 100644 --- a/bsp/essemi/es32f369x/drivers/SConscript +++ b/bsp/essemi/es32f369x/drivers/SConscript @@ -44,12 +44,12 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend('BSP_USING_SPI_FLASH'): src += ['drv_spiflash.c'] -# add hwtimer driver code -if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMER'): - src += ['drv_hwtimer.c'] +# add clock_timer driver code +if GetDepend('BSP_USING_AD16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_AD16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP32C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP32C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_BS16T0_CLOCK_TIMER') or GetDepend('BSP_USING_BS16T1_CLOCK_TIMER'): + src += ['drv_timer.c'] # add pwm driver code if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ @@ -72,8 +72,8 @@ include_path = [cwd + '/ES'] if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): src += ['bsp_driver_example/adc_vol_sample.c'] -if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): - src += ['bsp_driver_example/hwtimer_sample.c'] +if GetDepend('BSP_USING_EXAMPLE_CLOCK_TIMER'): + src += ['bsp_driver_example/clock_timer_sample.c'] if GetDepend('BSP_USING_EXAMPLE_I2C'): src += ['bsp_driver_example/i2c_sample.c'] diff --git a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c b/bsp/essemi/es32f369x/drivers/drv_hwtimer.c deleted file mode 100644 index 5b26407252..0000000000 --- a/bsp/essemi/es32f369x/drivers/drv_hwtimer.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Change Logs: - * Date Author Notes - * 2019-3-19 wangyq the first version - * 2019-11-01 wangyq update libraries - * 2021-04-20 liuhy the second version - */ - -#include -#include -#include -#include -#include - - -#ifdef RT_USING_HWTIMER - -struct es32f3_hwtimer_dev -{ - rt_hwtimer_t parent; - timer_handle_t *hwtimer_periph; - IRQn_Type IRQn; -}; - -#ifdef BSP_USING_AD16C4T0_HWTIMER -static struct es32f3_hwtimer_dev ad16c4t0_hwtimer; - -static struct rt_hwtimer_info ad16c4t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_AD16C4T0_HWTIMER_MODE -}; - -void AD16C4T0_UP_Handler(void) -{ - ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); -} - -#endif - -#ifdef BSP_USING_AD16C4T1_HWTIMER - -static struct es32f3_hwtimer_dev ad16c4t1_hwtimer; - -static struct rt_hwtimer_info ad16c4t1_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_AD16C4T1_HWTIMER_MODE -}; - -void AD16C4T1_UP_Handler(void) -{ - ald_timer_clear_flag_status(ad16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&ad16c4t1_hwtimer.parent); -} - -#endif -#ifdef BSP_USING_GP32C4T0_HWTIMER - -static struct es32f3_hwtimer_dev gp32c4t0_hwtimer; - -static struct rt_hwtimer_info gp32c4t0_info = -{ - - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV , /* maximum count frequency */ - ( ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ - 0xFFFFFFFF, /* counter maximum value */ - ES_GP32C4T0_HWTIMER_MODE -}; - -void GP32C4T0_Handler(void) -{ - ald_timer_clear_flag_status(gp32c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp32c4t0_hwtimer.parent); -} - -#endif -#ifdef BSP_USING_GP32C4T1_HWTIMER - -static struct es32f3_hwtimer_dev gp32c4t1_hwtimer; - -static struct rt_hwtimer_info gp32c4t1_info = -{ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV ), /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ - 0xFFFFFFFF, /* counter maximum value */ - ES_GP32C4T1_HWTIMER_MODE -}; - -void GP32C4T1_Handler(void) -{ - ald_timer_clear_flag_status(gp32c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp32c4t1_hwtimer.parent); -} - -#endif -#ifdef BSP_USING_GP16C4T0_HWTIMER - -static struct es32f3_hwtimer_dev gp16c4t0_hwtimer; - -static struct rt_hwtimer_info gp16c4t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_GP16C4T0_HWTIMER_MODE -}; - -void GP16C4T0_Handler(void) -{ - ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); -} - -#endif -#ifdef BSP_USING_GP16C4T1_HWTIMER - -static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; - -static struct rt_hwtimer_info gp16c4t1_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_GP16C4T1_HWTIMER_MODE -}; - -void GP16C4T1_Handler(void) -{ - ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); -} - -#endif -#ifdef BSP_USING_BS16T0_HWTIMER - -static struct es32f3_hwtimer_dev bs16t0_hwtimer; - -static struct rt_hwtimer_info bs16t0_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_BS16T0_HWTIMER_MODE -}; - -void BS16T0_Handler(void) -{ - ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); -} - -#endif -#ifdef BSP_USING_BS16T1_HWTIMER - -static struct es32f3_hwtimer_dev bs16t1_hwtimer; - -static struct rt_hwtimer_info bs16t1_info = -{ - ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ - (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ - 0xFFFF, /* counter maximum value */ - ES_BS16T1_HWTIMER_MODE -}; - -void BS16T1_Handler(void) -{ - ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t1_hwtimer.parent); -} - -#endif - -static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) -{ - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; - - struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; - - - RT_ASSERT(hwtimer != RT_NULL); - - if (1 == state) - { - ald_timer_base_init(hwtimer->hwtimer_periph); - ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); - NVIC_EnableIRQ(hwtimer->IRQn); - } - - hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); - hwtimer_info->maxfreq = hwtimer->parent.freq; - hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; - -} - -static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer, - rt_uint32_t cnt, - rt_hwtimer_mode_t mode) -{ - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); - ald_timer_base_start(hwtimer->hwtimer_periph); - - return RT_EOK; -} - -static void es32f3_hwtimer_stop(rt_hwtimer_t *timer) -{ - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - ald_timer_base_stop(hwtimer->hwtimer_periph); -} - -static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer) -{ - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; - uint32_t hwtimer_count = 0; - - RT_ASSERT(hwtimer != RT_NULL); - - hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT); - - return hwtimer_count; -} - -static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, - rt_uint32_t cmd, - void *args) -{ - rt_err_t ret = RT_EOK; - rt_uint32_t freq = 0; - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - switch (cmd) - { - case HWTIMER_CTRL_FREQ_SET: - freq = *(rt_uint32_t *)args; - - ret = -RT_ERROR; - - if(freq) - { - double temp,target; - temp = (double)ald_cmu_get_pclk1_clock(); - target = temp/freq; - - if(target < 0x10001) /*最大分频 = max(PRES)+1*/ - { - temp = target - (int)(target); - - if((temp > 0.998)&&(target < 0x10000)) - { - hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; - ret = RT_EOK; - } - if((temp < 0.002)&&(target >= 0x1)) - { - hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; - ret = RT_EOK; - } - - } - - if(ret == RT_EOK) /*更新信息*/ - hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); - - } - - break; - - case HWTIMER_CTRL_STOP: - ald_timer_base_stop(hwtimer->hwtimer_periph); - break; - - default: - ret = -RT_EINVAL; - break; - } - - return ret; -} - -static struct rt_hwtimer_ops es32f3_hwtimer_ops = -{ - es32f3_hwtimer_init, - es32f3_hwtimer_start, - es32f3_hwtimer_stop, - es32f3_hwtimer_count_get, - es32f3_hwtimer_control -}; - -int rt_hw_hwtimer_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_AD16C4T0_HWTIMER - static timer_handle_t ad16c4t0_hwtimer_periph; - - ad16c4t0_hwtimer_periph.perh = AD16C4T0; - ad16c4t0_hwtimer.IRQn = AD16C4T0_UP_IRQn; - - ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; - ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; - - ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; - ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); -#endif - -#ifdef BSP_USING_AD16C4T1_HWTIMER - static timer_handle_t ad16c4t1_hwtimer_periph; - - ad16c4t1_hwtimer_periph.perh = AD16C4T1; - ad16c4t1_hwtimer.IRQn = AD16C4T1_UP_IRQn; - - ad16c4t1_hwtimer_periph.init.prescaler = ES_AD16C4T1_HWTIMER_PRES - 1; - ad16c4t1_hwtimer_periph.init.mode = ( ES_AD16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - ad16c4t1_hwtimer.hwtimer_periph = &ad16c4t1_hwtimer_periph; - - ad16c4t1_hwtimer.parent.info = &ad16c4t1_info; - ad16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&ad16c4t1_hwtimer.parent, ES_DEVICE_NAME_AD16C4T1_HWTIMER, &ad16c4t1_hwtimer); -#endif - -#ifdef BSP_USING_GP32C4T0_HWTIMER - static timer_handle_t gp32c4t0_hwtimer_periph; - - gp32c4t0_hwtimer_periph.perh = GP32C4T0; - gp32c4t0_hwtimer.IRQn = GP32C4T0_IRQn; - - gp32c4t0_hwtimer_periph.init.prescaler = ES_GP32C4T0_HWTIMER_PRES - 1; - gp32c4t0_hwtimer_periph.init.mode = ( ES_GP32C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp32c4t0_hwtimer.hwtimer_periph = &gp32c4t0_hwtimer_periph; - - gp32c4t0_hwtimer.parent.info = &gp32c4t0_info; - gp32c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp32c4t0_hwtimer.parent, ES_DEVICE_NAME_GP32C4T0_HWTIMER, &gp32c4t0_hwtimer); -#endif - -#ifdef BSP_USING_GP32C4T1_HWTIMER - static timer_handle_t gp32c4t1_hwtimer_periph; - - gp32c4t1_hwtimer_periph.perh = GP32C4T1; - gp32c4t1_hwtimer.IRQn = GP32C4T1_IRQn; - - gp32c4t1_hwtimer_periph.init.prescaler = ES_GP32C4T1_HWTIMER_PRES - 1; - gp32c4t1_hwtimer_periph.init.mode = ( ES_GP32C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp32c4t1_hwtimer.hwtimer_periph = &gp32c4t1_hwtimer_periph; - - gp32c4t1_hwtimer.parent.info = &gp32c4t1_info; - gp32c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp32c4t1_hwtimer.parent, ES_DEVICE_NAME_GP32C4T1_HWTIMER, &gp32c4t1_hwtimer); -#endif - -#ifdef BSP_USING_GP16C4T0_HWTIMER - static timer_handle_t gp16c4t0_hwtimer_periph; - - gp16c4t0_hwtimer_periph.perh = GP16C4T0; - gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn; - - gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; - gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; - - gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; - gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); -#endif - -#ifdef BSP_USING_GP16C4T1_HWTIMER - static timer_handle_t gp16c4t1_hwtimer_periph; - - gp16c4t1_hwtimer_periph.perh = GP16C4T1; - gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn; - - gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1; - gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph; - - gp16c4t1_hwtimer.parent.info = &gp16c4t1_info; - gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer); -#endif - -#ifdef BSP_USING_BS16T0_HWTIMER - static timer_handle_t bs16t0_hwtimer_periph; - - bs16t0_hwtimer_periph.perh = BS16T0; - bs16t0_hwtimer.IRQn = BS16T0_IRQn; - - bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; - bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; - - bs16t0_hwtimer.parent.info = &bs16t0_info; - bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); -#endif - -#ifdef BSP_USING_BS16T1_HWTIMER - static timer_handle_t bs16t1_hwtimer_periph; - - bs16t1_hwtimer_periph.perh = BS16T1; - bs16t1_hwtimer.IRQn = BS16T1_IRQn; - - bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1; - bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph; - - bs16t1_hwtimer.parent.info = &bs16t1_info; - bs16t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer); -#endif - - return ret; -} -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); - -#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_timer.c b/bsp/essemi/es32f369x/drivers/drv_timer.c new file mode 100644 index 0000000000..16adf7ebcd --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_timer.c @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Change Logs: + * Date Author Notes + * 2019-3-19 wangyq the first version + * 2019-11-01 wangyq update libraries + * 2021-04-20 liuhy the second version + */ + +#include +#include +#include +#include +#include + + +#ifdef RT_USING_CLOCK_TIME + +struct es32f3_clock_timer_dev +{ + rt_clock_timer_t parent; + timer_handle_t *clock_timer_periph; + IRQn_Type IRQn; +}; + +#ifdef BSP_USING_AD16C4T0_CLOCK_TIMER +static struct es32f3_clock_timer_dev ad16c4t0_clock_timer; + +static struct rt_clock_timer_info ad16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T0_CLOCK_TIMER_MODE +}; + +void AD16C4T0_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&ad16c4t0_clock_timer.parent); +} + +#endif + +#ifdef BSP_USING_AD16C4T1_CLOCK_TIMER + +static struct es32f3_clock_timer_dev ad16c4t1_clock_timer; + +static struct rt_clock_timer_info ad16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_AD16C4T1_CLOCK_TIMER_MODE +}; + +void AD16C4T1_UP_Handler(void) +{ + ald_timer_clear_flag_status(ad16c4t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&ad16c4t1_clock_timer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T0_CLOCK_TIMER + +static struct es32f3_clock_timer_dev gp32c4t0_clock_timer; + +static struct rt_clock_timer_info gp32c4t0_info = +{ + + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV , /* maximum count frequency */ + ( ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T0_CLOCK_TIMER_MODE +}; + +void GP32C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp32c4t0_clock_timer.parent); +} + +#endif +#ifdef BSP_USING_GP32C4T1_CLOCK_TIMER + +static struct es32f3_clock_timer_dev gp32c4t1_clock_timer; + +static struct rt_clock_timer_info gp32c4t1_info = +{ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV ), /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV )/(1U<<16), /* minimum count frequency */ + 0xFFFFFFFF, /* counter maximum value */ + ES_GP32C4T1_CLOCK_TIMER_MODE +}; + +void GP32C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp32c4t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp32c4t1_clock_timer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T0_CLOCK_TIMER + +static struct es32f3_clock_timer_dev gp16c4t0_clock_timer; + +static struct rt_clock_timer_info gp16c4t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T0_CLOCK_TIMER_MODE +}; + +void GP16C4T0_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c4t0_clock_timer.parent); +} + +#endif +#ifdef BSP_USING_GP16C4T1_CLOCK_TIMER + +static struct es32f3_clock_timer_dev gp16c4t1_clock_timer; + +static struct rt_clock_timer_info gp16c4t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_GP16C4T1_CLOCK_TIMER_MODE +}; + +void GP16C4T1_Handler(void) +{ + ald_timer_clear_flag_status(gp16c4t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c4t1_clock_timer.parent); +} + +#endif +#ifdef BSP_USING_BS16T0_CLOCK_TIMER + +static struct es32f3_clock_timer_dev bs16t0_clock_timer; + +static struct rt_clock_timer_info bs16t0_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T0_CLOCK_TIMER_MODE +}; + +void BS16T0_Handler(void) +{ + ald_timer_clear_flag_status(bs16t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t0_clock_timer.parent); +} + +#endif +#ifdef BSP_USING_BS16T1_CLOCK_TIMER + +static struct es32f3_clock_timer_dev bs16t1_clock_timer; + +static struct rt_clock_timer_info bs16t1_info = +{ + ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */ + (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16), /* minimum count frequency */ + 0xFFFF, /* counter maximum value */ + ES_BS16T1_CLOCK_TIMER_MODE +}; + +void BS16T1_Handler(void) +{ + ald_timer_clear_flag_status(bs16t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t1_clock_timer.parent); +} + +#endif + +static void es32f3_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) +{ + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; + + struct rt_clock_timer_info *clock_timer_info = (struct rt_clock_timer_info *)timer->info; + + + RT_ASSERT(clock_timer != RT_NULL); + + if (1 == state) + { + ald_timer_base_init(clock_timer->clock_timer_periph); + ald_timer_interrupt_config(clock_timer->clock_timer_periph, TIMER_IT_UPDATE, ENABLE); + NVIC_EnableIRQ(clock_timer->IRQn); + } + + clock_timer->parent.freq = ald_cmu_get_pclk1_clock()/((clock_timer->clock_timer_periph->perh->PRES & 0xFFFF)+1); + clock_timer_info->maxfreq = clock_timer->parent.freq; + clock_timer_info->minfreq = (clock_timer->parent.freq)/0xFFFF; + +} + +static rt_err_t es32f3_clock_timer_start(rt_clock_timer_t *timer, + rt_uint32_t cnt, + rt_clock_timer_mode_t mode) +{ + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; + + RT_ASSERT(clock_timer != RT_NULL); + + WRITE_REG(clock_timer->clock_timer_periph->perh->AR, cnt); + ald_timer_base_start(clock_timer->clock_timer_periph); + + return RT_EOK; +} + +static void es32f3_clock_timer_stop(rt_clock_timer_t *timer) +{ + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; + + RT_ASSERT(clock_timer != RT_NULL); + + ald_timer_base_stop(clock_timer->clock_timer_periph); +} + +static rt_uint32_t es32f3_clock_timer_count_get(rt_clock_timer_t *timer) +{ + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; + uint32_t clock_timer_count = 0; + + RT_ASSERT(clock_timer != RT_NULL); + + clock_timer_count = READ_REG(clock_timer->clock_timer_periph->perh->COUNT); + + return clock_timer_count; +} + +static rt_err_t es32f3_clock_timer_control(rt_clock_timer_t *timer, + rt_uint32_t cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t freq = 0; + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; + + RT_ASSERT(clock_timer != RT_NULL); + + switch (cmd) + { + case CLOCK_TIMER_CTRL_FREQ_SET: + freq = *(rt_uint32_t *)args; + + ret = -RT_ERROR; + + if(freq) + { + double temp,target; + temp = (double)ald_cmu_get_pclk1_clock(); + target = temp/freq; + + if(target < 0x10001) /*最大分频 = max(PRES)+1*/ + { + temp = target - (int)(target); + + if((temp > 0.998)&&(target < 0x10000)) + { + clock_timer->clock_timer_periph->perh->PRES = (uint32_t)target; + ret = RT_EOK; + } + if((temp < 0.002)&&(target >= 0x1)) + { + clock_timer->clock_timer_periph->perh->PRES = (uint32_t)target - 1; + ret = RT_EOK; + } + + } + + if(ret == RT_EOK) /*更新信息*/ + clock_timer->parent.freq = ald_cmu_get_pclk1_clock()/((clock_timer->clock_timer_periph->perh->PRES & 0xFFFF)+1); + + } + + break; + + case CLOCK_TIMER_CTRL_STOP: + ald_timer_base_stop(clock_timer->clock_timer_periph); + break; + + default: + ret = -RT_EINVAL; + break; + } + + return ret; +} + +static struct rt_clock_timer_ops es32f3_clock_timer_ops = +{ + es32f3_clock_timer_init, + es32f3_clock_timer_start, + es32f3_clock_timer_stop, + es32f3_clock_timer_count_get, + es32f3_clock_timer_control +}; + +int rt_hw_clock_timer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_AD16C4T0_CLOCK_TIMER + static timer_handle_t ad16c4t0_clock_timer_periph; + + ad16c4t0_clock_timer_periph.perh = AD16C4T0; + ad16c4t0_clock_timer.IRQn = AD16C4T0_UP_IRQn; + + ad16c4t0_clock_timer_periph.init.prescaler = ES_AD16C4T0_CLOCK_TIMER_PRES - 1; + ad16c4t0_clock_timer_periph.init.mode = ( ES_AD16C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t0_clock_timer.clock_timer_periph = &ad16c4t0_clock_timer_periph; + + ad16c4t0_clock_timer.parent.info = &ad16c4t0_info; + ad16c4t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&ad16c4t0_clock_timer.parent, ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER, &ad16c4t0_clock_timer); +#endif + +#ifdef BSP_USING_AD16C4T1_CLOCK_TIMER + static timer_handle_t ad16c4t1_clock_timer_periph; + + ad16c4t1_clock_timer_periph.perh = AD16C4T1; + ad16c4t1_clock_timer.IRQn = AD16C4T1_UP_IRQn; + + ad16c4t1_clock_timer_periph.init.prescaler = ES_AD16C4T1_CLOCK_TIMER_PRES - 1; + ad16c4t1_clock_timer_periph.init.mode = ( ES_AD16C4T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + ad16c4t1_clock_timer.clock_timer_periph = &ad16c4t1_clock_timer_periph; + + ad16c4t1_clock_timer.parent.info = &ad16c4t1_info; + ad16c4t1_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&ad16c4t1_clock_timer.parent, ES_DEVICE_NAME_AD16C4T1_CLOCK_TIMER, &ad16c4t1_clock_timer); +#endif + +#ifdef BSP_USING_GP32C4T0_CLOCK_TIMER + static timer_handle_t gp32c4t0_clock_timer_periph; + + gp32c4t0_clock_timer_periph.perh = GP32C4T0; + gp32c4t0_clock_timer.IRQn = GP32C4T0_IRQn; + + gp32c4t0_clock_timer_periph.init.prescaler = ES_GP32C4T0_CLOCK_TIMER_PRES - 1; + gp32c4t0_clock_timer_periph.init.mode = ( ES_GP32C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t0_clock_timer.clock_timer_periph = &gp32c4t0_clock_timer_periph; + + gp32c4t0_clock_timer.parent.info = &gp32c4t0_info; + gp32c4t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp32c4t0_clock_timer.parent, ES_DEVICE_NAME_GP32C4T0_CLOCK_TIMER, &gp32c4t0_clock_timer); +#endif + +#ifdef BSP_USING_GP32C4T1_CLOCK_TIMER + static timer_handle_t gp32c4t1_clock_timer_periph; + + gp32c4t1_clock_timer_periph.perh = GP32C4T1; + gp32c4t1_clock_timer.IRQn = GP32C4T1_IRQn; + + gp32c4t1_clock_timer_periph.init.prescaler = ES_GP32C4T1_CLOCK_TIMER_PRES - 1; + gp32c4t1_clock_timer_periph.init.mode = ( ES_GP32C4T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp32c4t1_clock_timer.clock_timer_periph = &gp32c4t1_clock_timer_periph; + + gp32c4t1_clock_timer.parent.info = &gp32c4t1_info; + gp32c4t1_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp32c4t1_clock_timer.parent, ES_DEVICE_NAME_GP32C4T1_CLOCK_TIMER, &gp32c4t1_clock_timer); +#endif + +#ifdef BSP_USING_GP16C4T0_CLOCK_TIMER + static timer_handle_t gp16c4t0_clock_timer_periph; + + gp16c4t0_clock_timer_periph.perh = GP16C4T0; + gp16c4t0_clock_timer.IRQn = GP16C4T0_IRQn; + + gp16c4t0_clock_timer_periph.init.prescaler = ES_GP16C4T0_CLOCK_TIMER_PRES - 1; + gp16c4t0_clock_timer_periph.init.mode = ( ES_GP16C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_clock_timer.clock_timer_periph = &gp16c4t0_clock_timer_periph; + + gp16c4t0_clock_timer.parent.info = &gp16c4t0_info; + gp16c4t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c4t0_clock_timer.parent, ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER, &gp16c4t0_clock_timer); +#endif + +#ifdef BSP_USING_GP16C4T1_CLOCK_TIMER + static timer_handle_t gp16c4t1_clock_timer_periph; + + gp16c4t1_clock_timer_periph.perh = GP16C4T1; + gp16c4t1_clock_timer.IRQn = GP16C4T1_IRQn; + + gp16c4t1_clock_timer_periph.init.prescaler = ES_GP16C4T1_CLOCK_TIMER_PRES - 1; + gp16c4t1_clock_timer_periph.init.mode = ( ES_GP16C4T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t1_clock_timer.clock_timer_periph = &gp16c4t1_clock_timer_periph; + + gp16c4t1_clock_timer.parent.info = &gp16c4t1_info; + gp16c4t1_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c4t1_clock_timer.parent, ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER, &gp16c4t1_clock_timer); +#endif + +#ifdef BSP_USING_BS16T0_CLOCK_TIMER + static timer_handle_t bs16t0_clock_timer_periph; + + bs16t0_clock_timer_periph.perh = BS16T0; + bs16t0_clock_timer.IRQn = BS16T0_IRQn; + + bs16t0_clock_timer_periph.init.prescaler = ES_BS16T0_CLOCK_TIMER_PRES - 1; + bs16t0_clock_timer_periph.init.mode = ( ES_BS16T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_clock_timer.clock_timer_periph = &bs16t0_clock_timer_periph; + + bs16t0_clock_timer.parent.info = &bs16t0_info; + bs16t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t0_clock_timer.parent, ES_DEVICE_NAME_BS16T0_CLOCK_TIMER, &bs16t0_clock_timer); +#endif + +#ifdef BSP_USING_BS16T1_CLOCK_TIMER + static timer_handle_t bs16t1_clock_timer_periph; + + bs16t1_clock_timer_periph.perh = BS16T1; + bs16t1_clock_timer.IRQn = BS16T1_IRQn; + + bs16t1_clock_timer_periph.init.prescaler = ES_BS16T1_CLOCK_TIMER_PRES - 1; + bs16t1_clock_timer_periph.init.mode = ( ES_BS16T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t1_clock_timer.clock_timer_periph = &bs16t1_clock_timer_periph; + + bs16t1_clock_timer.parent.info = &bs16t1_info; + bs16t1_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t1_clock_timer.parent, ES_DEVICE_NAME_BS16T1_CLOCK_TIMER, &bs16t1_clock_timer); +#endif + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); + +#endif diff --git a/bsp/essemi/es32vf2264/drivers/drv_hwtimer.h b/bsp/essemi/es32f369x/drivers/drv_timer.h similarity index 86% rename from bsp/essemi/es32vf2264/drivers/drv_hwtimer.h rename to bsp/essemi/es32f369x/drivers/drv_timer.h index bbf51a4771..676ebb2358 100644 --- a/bsp/essemi/es32vf2264/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32f369x/drivers/drv_timer.h @@ -21,10 +21,10 @@ * 2021-04-20 liuhy the second version */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ -#include "es_conf_info_hwtimer.h" -int rt_hw_hwtimer_init(void); +#include "es_conf_info_clock_timer.h" +int rt_hw_clock_timer_init(void); #endif diff --git a/bsp/essemi/es32vf2264/drivers/ES/Kconfig b/bsp/essemi/es32vf2264/drivers/ES/Kconfig index 8c2fffd7b4..bea93ab873 100644 --- a/bsp/essemi/es32vf2264/drivers/ES/Kconfig +++ b/bsp/essemi/es32vf2264/drivers/ES/Kconfig @@ -121,31 +121,31 @@ menu "ADC Drivers" endmenu -menu "HWTIMER Drivers" +menu "CLOCK_TIMER Drivers" - config BSP_USING_AD16C4T0_HWTIMER - bool "Register HWTIMER0 " - select RT_USING_HWTIMER + config BSP_USING_AD16C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER0 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T0_HWTIMER - bool "Register HWTIMER1 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T0_CLOCK_TIMER + bool "Register CLOCK_TIMER1 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T1_HWTIMER - bool "Register HWTIMER2 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T1_CLOCK_TIMER + bool "Register CLOCK_TIMER2 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_GP16C4T2_HWTIMER - bool "Register HWTIMER3 " - select RT_USING_HWTIMER + config BSP_USING_GP16C4T2_CLOCK_TIMER + bool "Register CLOCK_TIMER3 " + select RT_USING_CLOCK_TIME default n - config BSP_USING_BS16T0_HWTIMER - bool "Register HWTIMER4 " - select RT_USING_HWTIMER + config BSP_USING_BS16T0_CLOCK_TIMER + bool "Register CLOCK_TIMER4 " + select RT_USING_CLOCK_TIME default n endmenu @@ -156,25 +156,25 @@ menu "PWM Drivers" bool "Register PWM0 " select RT_USING_PWM default n - depends on !BSP_USING_AD16C4T0_HWTIMER + depends on !BSP_USING_AD16C4T0_CLOCK_TIMER config BSP_USING_GP16C4T0_PWM bool "Register PWM1 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T0_HWTIMER + depends on !BSP_USING_GP16C4T0_CLOCK_TIMER config BSP_USING_GP16C4T1_PWM bool "Register PWM2 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T1_HWTIMER + depends on !BSP_USING_GP16C4T1_CLOCK_TIMER config BSP_USING_GP16C4T2_PWM bool "Register PWM3 " select RT_USING_PWM default n - depends on !BSP_USING_GP16C4T1_HWTIMER + depends on !BSP_USING_GP16C4T1_CLOCK_TIMER endmenu diff --git a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_clock_timer.h similarity index 30% rename from bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h rename to bsp/essemi/es32vf2264/drivers/ES/es_conf_info_clock_timer.h index 100b2e626b..8f7f65b43e 100644 --- a/bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h +++ b/bsp/essemi/es32vf2264/drivers/ES/es_conf_info_clock_timer.h @@ -21,82 +21,82 @@ * */ -#ifndef __ES_CONF_INFO_HWTIMER_H__ -#define __ES_CONF_INFO_HWTIMER_H__ +#ifndef __ES_CONF_INFO_CLOCK_TIMER_H__ +#define __ES_CONF_INFO_CLOCK_TIMER_H__ #include #include -#define ES_C_HWTIMER_MODE_UP HWTIMER_CNTMODE_UP -#define ES_C_HWTIMER_MODE_DOWN HWTIMER_CNTMODE_DW +#define ES_C_CLOCK_TIMER_MODE_UP CLOCK_TIMER_CNTMODE_UP +#define ES_C_CLOCK_TIMER_MODE_DOWN CLOCK_TIMER_CNTMODE_DW -/* HWTIMER 配置 */ +/* CLOCK_TIMER 配置 */ /* codes_main */ -#ifndef ES_AD16C4T0_HWTIMER_MODE -#define ES_AD16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_AD16C4T0_CLOCK_TIMER_MODE +#define ES_AD16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C4T0_HWTIMER_MODE -#define ES_GP16C4T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T0_CLOCK_TIMER_MODE +#define ES_GP16C4T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP16C2T0_HWTIMER_MODE -#define ES_GP16C2T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T1_CLOCK_TIMER_MODE +#define ES_GP16C4T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_GP1624T1_HWTIMER_MODE -#define ES_GP16C2T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_GP16C4T2_CLOCK_TIMER_MODE +#define ES_GP16C4T2_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T0_HWTIMER_MODE -#define ES_BS16T0_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T0_CLOCK_TIMER_MODE +#define ES_BS16T0_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T1_HWTIMER_MODE -#define ES_BS16T1_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T1_CLOCK_TIMER_MODE +#define ES_BS16T1_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T2_HWTIMER_MODE -#define ES_BS16T2_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T2_CLOCK_TIMER_MODE +#define ES_BS16T2_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#ifndef ES_BS16T3_HWTIMER_MODE -#define ES_BS16T3_HWTIMER_MODE ES_C_HWTIMER_MODE_UP +#ifndef ES_BS16T3_CLOCK_TIMER_MODE +#define ES_BS16T3_CLOCK_TIMER_MODE ES_C_CLOCK_TIMER_MODE_UP #endif -#define ES_AD16C4T0_HWTIMER_PRES 1 -#define ES_GP16C4T0_HWTIMER_PRES 1 -#define ES_GP16C2T0_HWTIMER_PRES 1 -#define ES_GP16C2T1_HWTIMER_PRES 1 -#define ES_BS16T0_HWTIMER_PRES 1 -#define ES_BS16T1_HWTIMER_PRES 1 -#define ES_BS16T2_HWTIMER_PRES 1 -#define ES_BS16T3_HWTIMER_PRES 1 +#define ES_AD16C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C4T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C2T0_CLOCK_TIMER_PRES 1 +#define ES_GP16C2T1_CLOCK_TIMER_PRES 1 +#define ES_BS16T0_CLOCK_TIMER_PRES 1 +#define ES_BS16T1_CLOCK_TIMER_PRES 1 +#define ES_BS16T2_CLOCK_TIMER_PRES 1 +#define ES_BS16T3_CLOCK_TIMER_PRES 1 -#ifndef ES_DEVICE_NAME_AD16C4T0_HWTIMER -#define ES_DEVICE_NAME_AD16C4T0_HWTIMER "timer0" +#ifndef ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER "timer0" #endif -#ifndef ES_DEVICE_NAME_GP16C4T0_HWTIMER -#define ES_DEVICE_NAME_GP16C4T0_HWTIMER "timer1" +#ifndef ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER "timer1" #endif -#ifndef ES_DEVICE_NAME_GP16C2T0_HWTIMER -#define ES_DEVICE_NAME_GP16C2T0_HWTIMER "timer2" +#ifndef ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER "timer2" #endif -#ifndef ES_DEVICE_NAME_GP16C2T1_HWTIMER -#define ES_DEVICE_NAME_GP16C2T1_HWTIMER "timer3" +#ifndef ES_DEVICE_NAME_GP16C4T2_CLOCK_TIMER +#define ES_DEVICE_NAME_GP16C4T2_CLOCK_TIMER "timer3" #endif -#ifndef ES_DEVICE_NAME_BS16T0_HWTIMER -#define ES_DEVICE_NAME_BS16T0_HWTIMER "timer4" +#ifndef ES_DEVICE_NAME_BS16T0_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T0_CLOCK_TIMER "timer4" #endif -#ifndef ES_DEVICE_NAME_BS16T1_HWTIMER -#define ES_DEVICE_NAME_BS16T1_HWTIMER "timer5" +#ifndef ES_DEVICE_NAME_BS16T1_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T1_CLOCK_TIMER "timer5" #endif -#ifndef ES_DEVICE_NAME_BS16T2_HWTIMER -#define ES_DEVICE_NAME_BS16T2_HWTIMER "timer6" +#ifndef ES_DEVICE_NAME_BS16T2_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T2_CLOCK_TIMER "timer6" #endif -#ifndef ES_DEVICE_NAME_BS16T3_HWTIMER -#define ES_DEVICE_NAME_BS16T3_HWTIMER "timer7" +#ifndef ES_DEVICE_NAME_BS16T3_CLOCK_TIMER +#define ES_DEVICE_NAME_BS16T3_CLOCK_TIMER "timer7" #endif diff --git a/bsp/essemi/es32vf2264/drivers/SConscript b/bsp/essemi/es32vf2264/drivers/SConscript index d5a224afc4..24861f45ea 100644 --- a/bsp/essemi/es32vf2264/drivers/SConscript +++ b/bsp/essemi/es32vf2264/drivers/SConscript @@ -46,15 +46,15 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend('BSP_USING_SPI_FLASH'): src += ['drv_spiflash.c'] -# add hwtimer driver code -if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or GetDepend('BSP_USING_GP16C4T2_HWTIMER') or \ - GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \ - GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \ - GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \ - GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'): - src += ['drv_hwtimer.c'] +# add clock_timer driver code +if GetDepend('BSP_USING_AD16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_AD16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP32C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP32C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T1_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T2_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C2T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C2T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_GP16C4T0_CLOCK_TIMER') or GetDepend('BSP_USING_GP16C4T1_CLOCK_TIMER') or \ + GetDepend('BSP_USING_BS16T0_CLOCK_TIMER') or GetDepend('BSP_USING_BS16T1_CLOCK_TIMERIMER') or \ + GetDepend('BSP_USING_BS16T2_CLOCK_TIMER') or GetDepend('BSP_USING_BS16T3_CLOCK_TIMER'): + src += ['drv_timer.c'] # add pwm driver code if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \ diff --git a/bsp/essemi/es32vf2264/drivers/board.h b/bsp/essemi/es32vf2264/drivers/board.h index a230d97a39..3f5cb6a081 100644 --- a/bsp/essemi/es32vf2264/drivers/board.h +++ b/bsp/essemi/es32vf2264/drivers/board.h @@ -36,7 +36,7 @@ #include "es_conf_info_map.h" #include "es_conf_info_gpio.h" #include "es_conf_info_adc.h" -#include "es_conf_info_hwtimer.h" +#include "es_conf_info_clock_timer.h" #include "es_conf_info_pwm.h" #include "es_conf_info_uart.h" #include "es_conf_info_spi.h" diff --git a/bsp/essemi/es32vf2264/drivers/drv_hwtimer.c b/bsp/essemi/es32vf2264/drivers/drv_timer.c similarity index 32% rename from bsp/essemi/es32vf2264/drivers/drv_hwtimer.c rename to bsp/essemi/es32vf2264/drivers/drv_timer.c index e42819af09..b2078975b0 100644 --- a/bsp/essemi/es32vf2264/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32vf2264/drivers/drv_timer.c @@ -25,194 +25,194 @@ #include #include #include -#include +#include #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME -struct es32f3_hwtimer_dev +struct es32f3_clock_timer_dev { - rt_hwtimer_t parent; - ald_timer_handle_t *hwtimer_periph; + rt_clock_timer_t parent; + ald_timer_handle_t *clock_timer_periph; IRQn_Type IRQn; }; -#ifdef BSP_USING_AD16C4T0_HWTIMER -static struct es32f3_hwtimer_dev ad16c4t0_hwtimer; +#ifdef BSP_USING_AD16C4T0_CLOCK_TIMER +static struct es32f3_clock_timer_dev ad16c4t0_clock_timer; -static struct rt_hwtimer_info ad16c4t0_info = +static struct rt_clock_timer_info ad16c4t0_info = { ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ 0xFFFF, /* counter maximum value */ - ES_AD16C4T0_HWTIMER_MODE + ES_AD16C4T0_CLOCK_TIMER_MODE }; void __attribute__((interrupt)) AD16C4T_Handler(void) { rt_interrupt_enter(); - ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, ALD_TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent); + ald_timer_clear_flag_status(ad16c4t0_clock_timer.clock_timer_periph, ALD_TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&ad16c4t0_clock_timer.parent); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_GP16C4T0_HWTIMER +#ifdef BSP_USING_GP16C4T0_CLOCK_TIMER -static struct es32f3_hwtimer_dev gp16c4t0_hwtimer; +static struct es32f3_clock_timer_dev gp16c4t0_clock_timer; -static struct rt_hwtimer_info gp16c4t0_info = +static struct rt_clock_timer_info gp16c4t0_info = { ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ 0xFFFF, /* counter maximum value */ - ES_GP16C4T0_HWTIMER_MODE + ES_GP16C4T0_CLOCK_TIMER_MODE }; void __attribute__((interrupt)) GPTIMB0_Handler(void) { rt_interrupt_enter(); - ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent); + ald_timer_clear_flag_status(gp16c4t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c4t0_clock_timer.parent); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_GP16C4T1_HWTIMER +#ifdef BSP_USING_GP16C4T1_CLOCK_TIMER -static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; +static struct es32f3_clock_timer_dev gp16c4t1_clock_timer; -static struct rt_hwtimer_info gp16c4t1_info = +static struct rt_clock_timer_info gp16c4t1_info = { ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ 0xFFFF, /* counter maximum value */ - ES_GP16C4T1_HWTIMER_MODE + ES_GP16C4T1_CLOCK_TIMER_MODE }; void __attribute__((interrupt)) GPTIMB1_Handler(void) { rt_interrupt_enter(); - ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); + ald_timer_clear_flag_status(gp16c4t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c4t1_clock_timer.parent); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_GP16C4T1_HWTIMER +#ifdef BSP_USING_GP16C4T1_CLOCK_TIMER -static struct es32f3_hwtimer_dev gp16c4t1_hwtimer; +static struct es32f3_clock_timer_dev gp16c4t1_clock_timer; -static struct rt_hwtimer_info gp16c4t1_info = +static struct rt_clock_timer_info gp16c4t1_info = { ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ 0xFFFF, /* counter maximum value */ - ES_GP16C4T1_HWTIMER_MODE + ES_GP16C4T1_CLOCK_TIMER_MODE }; void __attribute__((interrupt)) GPTIMB2_Handler(void) { rt_interrupt_enter(); - ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent); + ald_timer_clear_flag_status(gp16c4t1_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&gp16c4t1_clock_timer.parent); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_BS16T0_HWTIMER +#ifdef BSP_USING_BS16T0_CLOCK_TIMER -static struct es32f3_hwtimer_dev bs16t0_hwtimer; +static struct es32f3_clock_timer_dev bs16t0_clock_timer; -static struct rt_hwtimer_info bs16t0_info = +static struct rt_clock_timer_info bs16t0_info = { ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */ (ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */ 0xFFFF, /* counter maximum value */ - ES_BS16T0_HWTIMER_MODE + ES_BS16T0_CLOCK_TIMER_MODE }; void __attribute__((interrupt)) BSTIM0_Handler(void) { rt_interrupt_enter(); - ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&bs16t0_hwtimer.parent); + ald_timer_clear_flag_status(bs16t0_clock_timer.clock_timer_periph, TIMER_FLAG_UPDATE); + rt_clock_timer_isr(&bs16t0_clock_timer.parent); rt_interrupt_leave(); } #endif -static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void es32f3_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; - struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info; + struct rt_clock_timer_info *clock_timer_info = (struct rt_clock_timer_info *)timer->info; - RT_ASSERT(hwtimer != RT_NULL); + RT_ASSERT(clock_timer != RT_NULL); if (1 == state) { - ald_timer_base_init(hwtimer->hwtimer_periph); - ald_timer_interrupt_config(hwtimer->hwtimer_periph, ALD_TIMER_IT_UPDATE, ENABLE); - csi_vic_enable_sirq(hwtimer->IRQn); + ald_timer_base_init(clock_timer->clock_timer_periph); + ald_timer_interrupt_config(clock_timer->clock_timer_periph, ALD_TIMER_IT_UPDATE, ENABLE); + csi_vic_enable_sirq(clock_timer->IRQn); } - hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); - hwtimer_info->maxfreq = hwtimer->parent.freq; - hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF; + clock_timer->parent.freq = ald_cmu_get_pclk_clock()/((clock_timer->clock_timer_periph->perh->PRES & 0xFFFF)+1); + clock_timer_info->maxfreq = clock_timer->parent.freq; + clock_timer_info->minfreq = (clock_timer->parent.freq)/0xFFFF; } -static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer, +static rt_err_t es32f3_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, - rt_hwtimer_mode_t mode) + rt_clock_timer_mode_t mode) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; - RT_ASSERT(hwtimer != RT_NULL); + RT_ASSERT(clock_timer != RT_NULL); - WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); - ald_timer_base_start(hwtimer->hwtimer_periph); + WRITE_REG(clock_timer->clock_timer_periph->perh->AR, cnt); + ald_timer_base_start(clock_timer->clock_timer_periph); return RT_EOK; } -static void es32f3_hwtimer_stop(rt_hwtimer_t *timer) +static void es32f3_clock_timer_stop(rt_clock_timer_t *timer) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; - RT_ASSERT(hwtimer != RT_NULL); + RT_ASSERT(clock_timer != RT_NULL); - ald_timer_base_stop(hwtimer->hwtimer_periph); + ald_timer_base_stop(clock_timer->clock_timer_periph); } -static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t es32f3_clock_timer_count_get(rt_clock_timer_t *timer) { - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; - uint32_t hwtimer_count = 0; + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; + uint32_t clock_timer_count = 0; - RT_ASSERT(hwtimer != RT_NULL); + RT_ASSERT(clock_timer != RT_NULL); - hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT); + clock_timer_count = READ_REG(clock_timer->clock_timer_periph->perh->COUNT); - return hwtimer_count; + return clock_timer_count; } -static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, +static rt_err_t es32f3_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; rt_uint32_t freq = 0; - struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data; + struct es32f3_clock_timer_dev *clock_timer = (struct es32f3_clock_timer_dev *)timer->parent.user_data; - RT_ASSERT(hwtimer != RT_NULL); + RT_ASSERT(clock_timer != RT_NULL); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; ret = -RT_ERROR; @@ -229,26 +229,26 @@ static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, if((temp > 0.998)&&(target < 0x10000)) { - hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target; + clock_timer->clock_timer_periph->perh->PRES = (uint32_t)target; ret = RT_EOK; } if((temp < 0.002)&&(target >= 0x1)) { - hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1; + clock_timer->clock_timer_periph->perh->PRES = (uint32_t)target - 1; ret = RT_EOK; } } if(ret == RT_EOK) /*更新信息*/ - hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1); + clock_timer->parent.freq = ald_cmu_get_pclk_clock()/((clock_timer->clock_timer_periph->perh->PRES & 0xFFFF)+1); } break; - case HWTIMER_CTRL_STOP: - ald_timer_base_stop(hwtimer->hwtimer_periph); + case CLOCK_TIMER_CTRL_STOP: + ald_timer_base_stop(clock_timer->clock_timer_periph); break; default: @@ -259,96 +259,96 @@ static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer, return ret; } -static struct rt_hwtimer_ops es32f3_hwtimer_ops = +static struct rt_clock_timer_ops es32f3_clock_timer_ops = { - es32f3_hwtimer_init, - es32f3_hwtimer_start, - es32f3_hwtimer_stop, - es32f3_hwtimer_count_get, - es32f3_hwtimer_control + es32f3_clock_timer_init, + es32f3_clock_timer_start, + es32f3_clock_timer_stop, + es32f3_clock_timer_count_get, + es32f3_clock_timer_control }; -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { rt_err_t ret = RT_EOK; -#ifdef BSP_USING_AD16C4T0_HWTIMER - static ald_timer_handle_t ad16c4t0_hwtimer_periph; +#ifdef BSP_USING_AD16C4T0_CLOCK_TIMER + static ald_timer_handle_t ad16c4t0_clock_timer_periph; - ad16c4t0_hwtimer_periph.perh = AD16C4T; - ad16c4t0_hwtimer.IRQn = AD16C4T_IRQn; + ad16c4t0_clock_timer_periph.perh = AD16C4T; + ad16c4t0_clock_timer.IRQn = AD16C4T_IRQn; - ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1; - ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? ALD_TIMER_CNT_MODE_UP : ALD_TIMER_CNT_MODE_DOWN; - ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph; + ad16c4t0_clock_timer_periph.init.prescaler = ES_AD16C4T0_CLOCK_TIMER_PRES - 1; + ad16c4t0_clock_timer_periph.init.mode = ( ES_AD16C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? ALD_TIMER_CNT_MODE_UP : ALD_TIMER_CNT_MODE_DOWN; + ad16c4t0_clock_timer.clock_timer_periph = &ad16c4t0_clock_timer_periph; - ad16c4t0_hwtimer.parent.info = &ad16c4t0_info; - ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer); + ad16c4t0_clock_timer.parent.info = &ad16c4t0_info; + ad16c4t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&ad16c4t0_clock_timer.parent, ES_DEVICE_NAME_AD16C4T0_CLOCK_TIMER, &ad16c4t0_clock_timer); #endif -#ifdef BSP_USING_GP16C4T0_HWTIMER - static timer_handle_t gp16c4t0_hwtimer_periph; +#ifdef BSP_USING_GP16C4T0_CLOCK_TIMER + static timer_handle_t gp16c4t0_clock_timer_periph; - gp16c4t0_hwtimer_periph.perh = GP16C4T0; - gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn; + gp16c4t0_clock_timer_periph.perh = GP16C4T0; + gp16c4t0_clock_timer.IRQn = GP16C4T0_IRQn; - gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1; - gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph; + gp16c4t0_clock_timer_periph.init.prescaler = ES_GP16C4T0_CLOCK_TIMER_PRES - 1; + gp16c4t0_clock_timer_periph.init.mode = ( ES_GP16C4T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t0_clock_timer.clock_timer_periph = &gp16c4t0_clock_timer_periph; - gp16c4t0_hwtimer.parent.info = &gp16c4t0_info; - gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer); + gp16c4t0_clock_timer.parent.info = &gp16c4t0_info; + gp16c4t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c4t0_clock_timer.parent, ES_DEVICE_NAME_GP16C4T0_CLOCK_TIMER, &gp16c4t0_clock_timer); #endif -#ifdef BSP_USING_GP16C4T1_HWTIMER - static timer_handle_t gp16c4t1_hwtimer_periph; +#ifdef BSP_USING_GP16C4T1_CLOCK_TIMER + static timer_handle_t gp16c4t1_clock_timer_periph; - gp16c4t1_hwtimer_periph.perh = GP16C4T1; - gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn; + gp16c4t1_clock_timer_periph.perh = GP16C4T1; + gp16c4t1_clock_timer.IRQn = GP16C4T1_IRQn; - gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1; - gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph; + gp16c4t1_clock_timer_periph.init.prescaler = ES_GP16C4T1_CLOCK_TIMER_PRES - 1; + gp16c4t1_clock_timer_periph.init.mode = ( ES_GP16C4T1_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t1_clock_timer.clock_timer_periph = &gp16c4t1_clock_timer_periph; - gp16c4t1_hwtimer.parent.info = &gp16c4t1_info; - gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer); + gp16c4t1_clock_timer.parent.info = &gp16c4t1_info; + gp16c4t1_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c4t1_clock_timer.parent, ES_DEVICE_NAME_GP16C4T1_CLOCK_TIMER, &gp16c4t1_clock_timer); #endif -#ifdef BSP_USING_GP16C4T2_HWTIMER - static timer_handle_t gp16c4t2_hwtimer_periph; +#ifdef BSP_USING_GP16C4T2_CLOCK_TIMER + static timer_handle_t gp16c4t2_clock_timer_periph; - gp16c4t2_hwtimer_periph.perh = GP16C4T2; - gp16c4t2_hwtimer.IRQn = GP16C4T2_IRQn; + gp16c4t2_clock_timer_periph.perh = GP16C4T2; + gp16c4t2_clock_timer.IRQn = GP16C4T2_IRQn; - gp16c4t2_hwtimer_periph.init.prescaler = ES_GP16C4T2_HWTIMER_PRES - 1; - gp16c4t2_hwtimer_periph.init.mode = ( ES_GP16C4T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - gp16c4t2_hwtimer.hwtimer_periph = &gp16c4t2_hwtimer_periph; + gp16c4t2_clock_timer_periph.init.prescaler = ES_GP16C4T2_CLOCK_TIMER_PRES - 1; + gp16c4t2_clock_timer_periph.init.mode = ( ES_GP16C4T2_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + gp16c4t2_clock_timer.clock_timer_periph = &gp16c4t2_clock_timer_periph; - gp16c4t2_hwtimer.parent.info = &gp16c4t2_info; - gp16c4t2_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&gp16c4t2_hwtimer.parent, ES_DEVICE_NAME_GP16C4T2_HWTIMER, &gp16c4t2_hwtimer); + gp16c4t2_clock_timer.parent.info = &gp16c4t2_info; + gp16c4t2_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&gp16c4t2_clock_timer.parent, ES_DEVICE_NAME_GP16C4T2_CLOCK_TIMER, &gp16c4t2_clock_timer); #endif -#ifdef BSP_USING_BS16T0_HWTIMER - static timer_handle_t bs16t0_hwtimer_periph; +#ifdef BSP_USING_BS16T0_CLOCK_TIMER + static timer_handle_t bs16t0_clock_timer_periph; - bs16t0_hwtimer_periph.perh = BS16T0; - bs16t0_hwtimer.IRQn = BS16T0_IRQn; + bs16t0_clock_timer_periph.perh = BS16T0; + bs16t0_clock_timer.IRQn = BS16T0_IRQn; - bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1; - bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; - bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph; + bs16t0_clock_timer_periph.init.prescaler = ES_BS16T0_CLOCK_TIMER_PRES - 1; + bs16t0_clock_timer_periph.init.mode = ( ES_BS16T0_CLOCK_TIMER_MODE == CLOCK_TIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN; + bs16t0_clock_timer.clock_timer_periph = &bs16t0_clock_timer_periph; - bs16t0_hwtimer.parent.info = &bs16t0_info; - bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops; - ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer); + bs16t0_clock_timer.parent.info = &bs16t0_info; + bs16t0_clock_timer.parent.ops = &es32f3_clock_timer_ops; + ret = rt_clock_timer_register(&bs16t0_clock_timer.parent, ES_DEVICE_NAME_BS16T0_CLOCK_TIMER, &bs16t0_clock_timer); #endif return ret; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_hwtimer.h b/bsp/essemi/es32vf2264/drivers/drv_timer.h similarity index 86% rename from bsp/essemi/es32f0654/drivers/drv_hwtimer.h rename to bsp/essemi/es32vf2264/drivers/drv_timer.h index bbf51a4771..676ebb2358 100644 --- a/bsp/essemi/es32f0654/drivers/drv_hwtimer.h +++ b/bsp/essemi/es32vf2264/drivers/drv_timer.h @@ -21,10 +21,10 @@ * 2021-04-20 liuhy the second version */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ -#include "es_conf_info_hwtimer.h" -int rt_hw_hwtimer_init(void); +#include "es_conf_info_clock_timer.h" +int rt_hw_clock_timer_init(void); #endif diff --git a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript index 46d626df1e..14fbf4f1ca 100644 --- a/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript +++ b/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/SConscript @@ -27,7 +27,7 @@ if GetDepend(['RT_USING_I2C']): if GetDepend(['RT_USING_SPI']): src += ['Src/fm33lc0xx_fl_spi.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['Src/fm33lc0xx_fl_atim.c'] src += ['Src/fm33lc0xx_fl_bstim32.c'] diff --git a/bsp/fm33lc026/libraries/HAL_Drivers/SConscript b/bsp/fm33lc026/libraries/HAL_Drivers/SConscript index b95ebbf240..704e728356 100644 --- a/bsp/fm33lc026/libraries/HAL_Drivers/SConscript +++ b/bsp/fm33lc026/libraries/HAL_Drivers/SConscript @@ -14,8 +14,8 @@ if GetDepend(['RT_USING_PIN']): if GetDepend(['RT_USING_SERIAL']): src += ['drv_usart.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] diff --git a/bsp/ft2004/libraries/SConscript b/bsp/ft2004/libraries/SConscript index 2f023e6b9f..7447ac3822 100644 --- a/bsp/ft2004/libraries/SConscript +++ b/bsp/ft2004/libraries/SConscript @@ -61,7 +61,7 @@ if GetDepend(['BSP_USE_CAN']): None -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): None if GetDepend(['RT_USING_ADC']): diff --git a/bsp/gd32/arm/gd32103c-eval/board/Kconfig b/bsp/gd32/arm/gd32103c-eval/board/Kconfig index 46de28e360..2a5ef718bb 100644 --- a/bsp/gd32/arm/gd32103c-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32103c-eval/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32105c-eval/board/Kconfig b/bsp/gd32/arm/gd32105c-eval/board/Kconfig index c2c937003e..bbe77fe170 100644 --- a/bsp/gd32/arm/gd32105c-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32105c-eval/board/Kconfig @@ -258,7 +258,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32105r-start/board/Kconfig b/bsp/gd32/arm/gd32105r-start/board/Kconfig index 6147acac5d..a4edaa9cc3 100644 --- a/bsp/gd32/arm/gd32105r-start/board/Kconfig +++ b/bsp/gd32/arm/gd32105r-start/board/Kconfig @@ -266,7 +266,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32107c-eval/board/Kconfig b/bsp/gd32/arm/gd32107c-eval/board/Kconfig index e3538ec93d..deeddd4234 100644 --- a/bsp/gd32/arm/gd32107c-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32107c-eval/board/Kconfig @@ -258,7 +258,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32205r-start/board/Kconfig b/bsp/gd32/arm/gd32205r-start/board/Kconfig index 895e03a723..29bcf9d8e5 100644 --- a/bsp/gd32/arm/gd32205r-start/board/Kconfig +++ b/bsp/gd32/arm/gd32205r-start/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32207i-eval/board/Kconfig b/bsp/gd32/arm/gd32207i-eval/board/Kconfig index a0d39cf53c..0d05371f60 100644 --- a/bsp/gd32/arm/gd32207i-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32207i-eval/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32303e-eval/board/Kconfig b/bsp/gd32/arm/gd32303e-eval/board/Kconfig index f46897be95..940d34687e 100644 --- a/bsp/gd32/arm/gd32303e-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32303e-eval/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32305r-start/board/Kconfig b/bsp/gd32/arm/gd32305r-start/board/Kconfig index ce44b26f8f..e52d1dae40 100644 --- a/bsp/gd32/arm/gd32305r-start/board/Kconfig +++ b/bsp/gd32/arm/gd32305r-start/board/Kconfig @@ -258,7 +258,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32307e-start/board/Kconfig b/bsp/gd32/arm/gd32307e-start/board/Kconfig index d04e13d66b..0e06786c0b 100644 --- a/bsp/gd32/arm/gd32307e-start/board/Kconfig +++ b/bsp/gd32/arm/gd32307e-start/board/Kconfig @@ -258,7 +258,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32407v-lckfb/board/Kconfig b/bsp/gd32/arm/gd32407v-lckfb/board/Kconfig index b9281dffeb..2a54c9aa12 100644 --- a/bsp/gd32/arm/gd32407v-lckfb/board/Kconfig +++ b/bsp/gd32/arm/gd32407v-lckfb/board/Kconfig @@ -282,7 +282,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32407v-start/board/Kconfig b/bsp/gd32/arm/gd32407v-start/board/Kconfig index bf19a90c80..d6cb2c6fd7 100644 --- a/bsp/gd32/arm/gd32407v-start/board/Kconfig +++ b/bsp/gd32/arm/gd32407v-start/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32450z-eval/board/Kconfig b/bsp/gd32/arm/gd32450z-eval/board/Kconfig index c0a86c5def..64bfd3ca4e 100644 --- a/bsp/gd32/arm/gd32450z-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32450z-eval/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32470i-eval/board/Kconfig b/bsp/gd32/arm/gd32470i-eval/board/Kconfig index 5ab121f7dd..3fc8296d76 100644 --- a/bsp/gd32/arm/gd32470i-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32470i-eval/board/Kconfig @@ -255,7 +255,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig b/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig index 806989c9ab..9d73815115 100644 --- a/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig +++ b/bsp/gd32/arm/gd32470z-lckfb/board/Kconfig @@ -332,7 +332,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32527I-eval/board/Kconfig b/bsp/gd32/arm/gd32527I-eval/board/Kconfig index 80604dcb9d..1bdb2c1de2 100644 --- a/bsp/gd32/arm/gd32527I-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32527I-eval/board/Kconfig @@ -272,7 +272,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/gd32e230-lckfb/board/Kconfig b/bsp/gd32/arm/gd32e230-lckfb/board/Kconfig index 81ab374ea0..89f0da097b 100644 --- a/bsp/gd32/arm/gd32e230-lckfb/board/Kconfig +++ b/bsp/gd32/arm/gd32e230-lckfb/board/Kconfig @@ -314,7 +314,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable Hardware Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_TIM config BSP_USING_TIM2 diff --git a/bsp/gd32/arm/gd32e503v-eval/board/Kconfig b/bsp/gd32/arm/gd32e503v-eval/board/Kconfig index 57a6518e9a..121af8c225 100644 --- a/bsp/gd32/arm/gd32e503v-eval/board/Kconfig +++ b/bsp/gd32/arm/gd32e503v-eval/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/arm/libraries/gd32_drivers/SConscript b/bsp/gd32/arm/libraries/gd32_drivers/SConscript index 31a8d4458d..d10212978d 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/SConscript +++ b/bsp/gd32/arm/libraries/gd32_drivers/SConscript @@ -41,8 +41,8 @@ if GetDepend('RT_USING_RTC'): src += ['drv_rtc.c'] # add timer drivers. -if GetDepend('RT_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('RT_USING_CLOCK_TIME'): + src += ['drv_timer.c'] # add adc drivers. if GetDepend('RT_USING_ADC'): diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c similarity index 63% rename from bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c rename to bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c index 1c22b10467..be459ffcf6 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_hwtimer.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c @@ -10,64 +10,64 @@ #include #include -#include +#include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER typedef struct { uint32_t reg_base; IRQn_Type irqn; rcu_periph_enum rcu; -} gd32_hwtimer_data; +} gd32_clock_timer_data; typedef struct { char dev_name[RT_NAME_MAX]; - const gd32_hwtimer_data hw_data; - rt_hwtimer_t hwtimer_dev; - const struct rt_hwtimer_info hwtimer_info; -} gd32_hwtimer_device; + const gd32_clock_timer_data hw_data; + rt_clock_timer_t clock_timer_dev; + const struct rt_clock_timer_info clock_timer_info; +} gd32_clock_timer_device; enum timer_index_E { -#ifdef BSP_USING_HWTIMER0 +#ifdef BSP_USING_CLOCK_TIMER0 TIM0_INDEX, #endif -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 TIM1_INDEX, #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 TIM2_INDEX, #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 TIM3_INDEX, #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 TIM4_INDEX, #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 TIM5_INDEX, #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 TIM6_INDEX, #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 TIM7_INDEX, #endif -#ifdef BSP_USING_HWTIMER8 +#ifdef BSP_USING_CLOCK_TIMER8 TIM8_INDEX, #endif -#ifdef BSP_USING_HWTIMER9 +#ifdef BSP_USING_CLOCK_TIMER9 TIM9_INDEX, #endif -#ifdef BSP_USING_HWTIMER10 +#ifdef BSP_USING_CLOCK_TIMER10 TIM10_INDEX, #endif -#ifdef BSP_USING_HWTIMER11 +#ifdef BSP_USING_CLOCK_TIMER11 TIM11_INDEX, #endif -#ifdef BSP_USING_HWTIMER12 +#ifdef BSP_USING_CLOCK_TIMER12 TIM12_INDEX, #endif -#ifdef BSP_USING_HWTIMER13 +#ifdef BSP_USING_CLOCK_TIMER13 TIM13_INDEX, #endif }; @@ -111,7 +111,7 @@ static void __set_timerx_freq(uint32_t timerx, uint32_t freq) timer_prescaler_config(timerx, prescaler, TIMER_PSC_RELOAD_NOW); } -static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void gd32_clock_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { uint32_t timer_base = (uint32_t)timer->parent.user_data; timer_parameter_struct initpara; @@ -126,16 +126,16 @@ static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state } } -static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \ - rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t gd32_clock_timer_start(struct rt_clock_timer_device *timer, \ + rt_uint32_t cnt, rt_clock_timer_mode_t mode) { uint32_t timer_base = (uint32_t)timer->parent.user_data; - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_SINGLE); } - else if (mode == HWTIMER_MODE_PERIOD) + else if (mode == CLOCK_TIMER_MODE_PERIOD) { timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_REPETITIVE); } @@ -147,14 +147,14 @@ static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \ return 0; } -static void gd32_hwtimer_stop(struct rt_hwtimer_device *timer) +static void gd32_clock_timer_stop(struct rt_clock_timer_device *timer) { uint32_t timer_base = (uint32_t)timer->parent.user_data; timer_disable(timer_base); } -static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer) +static rt_uint32_t gd32_clock_timer_count_get(struct rt_clock_timer_device *timer) { uint32_t timer_base = (uint32_t)timer->parent.user_data; rt_uint32_t count; @@ -164,16 +164,16 @@ static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer) return count; } -static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_t cmd, \ +static rt_err_t gd32_clock_timer_control(struct rt_clock_timer_device *timer, rt_uint32_t cmd, \ void *args) { int ret = RT_EOK; rt_int32_t freq; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; __set_timerx_freq((uint32_t)timer->parent.user_data, freq); break; @@ -186,16 +186,16 @@ static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ return ret; } -static const struct rt_hwtimer_ops g_gd32_hwtimer_ops = { - gd32_hwtimer_init, - gd32_hwtimer_start, - gd32_hwtimer_stop, - gd32_hwtimer_count_get, - gd32_hwtimer_control, +static const struct rt_clock_timer_ops g_gd32_clock_timer_ops = { + gd32_clock_timer_init, + gd32_clock_timer_start, + gd32_clock_timer_stop, + gd32_clock_timer_count_get, + gd32_clock_timer_control, }; -static gd32_hwtimer_device g_gd32_hwtimer[] = { -#ifdef BSP_USING_HWTIMER0 +static gd32_clock_timer_device g_gd32_clock_timer[] = { +#ifdef BSP_USING_CLOCK_TIMER0 { "timer0", { @@ -212,7 +212,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 { "timer1", { @@ -229,7 +229,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 { "timer2", { @@ -246,7 +246,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 { "timer3", { @@ -263,7 +263,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 { "timer4", { @@ -280,7 +280,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 { "timer5", { @@ -297,7 +297,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 { "timer6", { @@ -314,7 +314,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 { "timer7", { @@ -331,7 +331,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER8 +#ifdef BSP_USING_CLOCK_TIMER8 { "timer8", { @@ -348,7 +348,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER9 +#ifdef BSP_USING_CLOCK_TIMER9 { "timer9", { @@ -365,7 +365,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER10 +#ifdef BSP_USING_CLOCK_TIMER10 { "timer10", { @@ -382,7 +382,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER11 +#ifdef BSP_USING_CLOCK_TIMER11 { "timer11", { @@ -399,7 +399,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER12 +#ifdef BSP_USING_CLOCK_TIMER12 { "timer12", { @@ -416,7 +416,7 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { } }, #endif -#ifdef BSP_USING_HWTIMER13 +#ifdef BSP_USING_CLOCK_TIMER13 { "timer13", { @@ -435,112 +435,112 @@ static gd32_hwtimer_device g_gd32_hwtimer[] = { #endif }; -#ifdef BSP_USING_HWTIMER0 +#ifdef BSP_USING_CLOCK_TIMER0 void TIMER0_UP_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM0_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM0_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 void TIMER1_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM1_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM1_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 void TIMER2_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM2_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM2_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 void TIMER3_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM3_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM3_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 void TIMER4_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM4_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM4_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 void TIMER5_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM5_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM5_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 void TIMER6_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM6_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM6_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 void TIMER7_UP_IRQHandler(void) { rt_interrupt_enter(); - rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev); - timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \ + rt_clock_timer_isr(&g_gd32_clock_timer[TIM7_INDEX].clock_timer_dev); + timer_flag_clear((uint32_t)g_gd32_clock_timer[TIM7_INDEX].clock_timer_dev.parent.user_data, \ TIMER_INT_UP); rt_interrupt_leave(); } #endif -static int rt_hwtimer_init(void) +static int rt_clock_timer_init(void) { int ret = 0, i = 0; - for (; i < sizeof(g_gd32_hwtimer) / sizeof(g_gd32_hwtimer[0]); i++) + for (; i < sizeof(g_gd32_clock_timer) / sizeof(g_gd32_clock_timer[0]); i++) { - g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops; - g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info; - - rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu); - NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0); - NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn); - timer_interrupt_enable(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UP); - ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \ - g_gd32_hwtimer[i].dev_name, (void *)g_gd32_hwtimer[i].hw_data.reg_base); + g_gd32_clock_timer[i].clock_timer_dev.ops = &g_gd32_clock_timer_ops; + g_gd32_clock_timer[i].clock_timer_dev.info = &g_gd32_clock_timer[i].clock_timer_info; + + rcu_periph_clock_enable(g_gd32_clock_timer[i].hw_data.rcu); + NVIC_SetPriority(g_gd32_clock_timer[i].hw_data.irqn, 0); + NVIC_EnableIRQ(g_gd32_clock_timer[i].hw_data.irqn); + timer_interrupt_enable(g_gd32_clock_timer[i].hw_data.reg_base, TIMER_INT_UP); + ret = rt_clock_timer_register(&g_gd32_clock_timer[i].clock_timer_dev, \ + g_gd32_clock_timer[i].dev_name, (void *)g_gd32_clock_timer[i].hw_data.reg_base); if (RT_EOK != ret) { - rt_kprintf("failed register %s, err=%d\n", g_gd32_hwtimer[i].dev_name, \ + rt_kprintf("failed register %s, err=%d\n", g_gd32_clock_timer[i].dev_name, \ ret); break; } @@ -548,5 +548,5 @@ static int rt_hwtimer_init(void) return ret; } -INIT_BOARD_EXPORT(rt_hwtimer_init); +INIT_BOARD_EXPORT(rt_clock_timer_init); #endif diff --git a/bsp/gd32/risc-v/gd32vf103r-start/board/Kconfig b/bsp/gd32/risc-v/gd32vf103r-start/board/Kconfig index 57ac5297c3..abd9f94bc6 100644 --- a/bsp/gd32/risc-v/gd32vf103r-start/board/Kconfig +++ b/bsp/gd32/risc-v/gd32vf103r-start/board/Kconfig @@ -134,7 +134,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/risc-v/gd32vf103v-eval/board/Kconfig b/bsp/gd32/risc-v/gd32vf103v-eval/board/Kconfig index 63127807cf..421d2da24f 100644 --- a/bsp/gd32/risc-v/gd32vf103v-eval/board/Kconfig +++ b/bsp/gd32/risc-v/gd32vf103v-eval/board/Kconfig @@ -137,7 +137,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/SConscript b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/SConscript index 2c2cb02900..7cc4a1b523 100644 --- a/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/SConscript +++ b/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/SConscript @@ -40,7 +40,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['GD32VF103_standard_peripheral/Source/gd32vf103_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['GD32VF103_standard_peripheral/Source/gd32vf103_timer.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript b/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript index df963f3b78..9148ed9816 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript @@ -38,8 +38,8 @@ if GetDepend('RT_USING_RTC'): src += ['drv_rtc.c'] # add timer drivers. -if GetDepend('RT_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('RT_USING_CLOCK_TIME'): + src += ['drv_timer.c'] # add adc drivers. if GetDepend('RT_USING_ADC'): diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig index a2bf2035bf..a036748740 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig @@ -527,11 +527,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n diff --git a/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat index f35553ed5a..d1b6de173a 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat +++ b/bsp/hc32/ev_hc32f334_lqfp64/bsp_compile_ci.bat @@ -18,7 +18,7 @@ scons --attach=devices.gpio scons -j4 scons --attach=default -scons --attach=devices.hwtimer +scons --attach=devices.clock_timer scons -j4 scons --attach=default diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig index 5859ec06f4..7694080495 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig @@ -640,11 +640,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n @@ -681,7 +681,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_SENSOR bool "Enable SENSOR" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_SENSOR config BSP_USING_TMR0_2B bool "Use KEYSCAN" diff --git a/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat index 12d5baf278..801b91cb7f 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat +++ b/bsp/hc32/ev_hc32f448_lqfp80/bsp_compile_ci.bat @@ -18,7 +18,7 @@ scons --attach=devices.gpio scons -j4 scons --attach=default -scons --attach=devices.hwtimer +scons --attach=devices.clock_timer scons -j4 scons --attach=default diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig index 23155b14f4..b2fab38d89 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig @@ -636,11 +636,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat index 5ae6c2aa69..f1d04b01aa 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/bsp_compile_ci.bat @@ -18,7 +18,7 @@ scons --attach=devices.gpio scons -j4 scons --attach=default -scons --attach=devices.hwtimer +scons --attach=devices.clock_timer scons -j4 scons --attach=default diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig index 0867ee6929..0c31a20cd0 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig @@ -703,11 +703,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n @@ -731,7 +731,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_SENSOR bool "Enable SENSOR" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_SENSOR config BSP_USING_TMR0_2B bool "Use KEYSCAN" diff --git a/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat index be8ad07538..997f3ec2e1 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat +++ b/bsp/hc32/ev_hc32f472_lqfp100/bsp_compile_ci.bat @@ -22,7 +22,7 @@ scons --attach=devices.gpio scons -j4 scons --attach=default -scons --attach=devices.hwtimer +scons --attach=devices.clock_timer scons -j4 scons --attach=default diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig index dd6cf3734e..79cb785cbc 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig @@ -963,11 +963,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat index 7a3904105d..c0cd921b13 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/bsp_compile_ci.bat @@ -22,7 +22,7 @@ scons --attach=devices.gpio scons -j4 scons --attach=default -scons --attach=devices.hwtimer +scons --attach=devices.clock_timer scons -j4 scons --attach=default diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig index cae9576d06..9d0e00a67c 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig @@ -961,11 +961,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat index b5b3bbe746..fd4ec1d3ac 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/bsp_compile_ci.bat @@ -22,7 +22,7 @@ scons --attach=devices.gpio scons -j4 scons --attach=default -scons --attach=devices.hwtimer +scons --attach=devices.clock_timer scons -j4 scons --attach=default diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig index d5e9a6bbaa..6c91f7e660 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig @@ -909,11 +909,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Hw Timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 bool "Use Timer_a1 As The Hw Timer" default n diff --git a/bsp/hc32/libraries/hc32_drivers/SConscript b/bsp/hc32/libraries/hc32_drivers/SConscript index 449e1356a2..3edb6bc1c8 100644 --- a/bsp/hc32/libraries/hc32_drivers/SConscript +++ b/bsp/hc32/libraries/hc32_drivers/SConscript @@ -50,8 +50,8 @@ if GetDepend(['RT_USING_RTC']): if GetDepend(['RT_USING_WDT']): src += ['drv_wdt.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_PULSE_ENCODER']): src += ['drv_pulse_encoder.c'] diff --git a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c b/bsp/hc32/libraries/hc32_drivers/drv_timer.c similarity index 58% rename from bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c rename to bsp/hc32/libraries/hc32_drivers/drv_timer.c index 2cac51d01f..2db13325c7 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_timer.c @@ -14,10 +14,10 @@ #include "drv_config.h" // #define DRV_DEBUG -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER #include "drv_irq.h" @@ -61,9 +61,9 @@ enum #endif }; -struct hc32_hwtimer +struct hc32_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; CM_TMRA_TypeDef *tmr_handle; rt_uint32_t clock_source; rt_uint32_t clock; @@ -80,7 +80,7 @@ struct hc32_hwtimer char *name; }; -static struct hc32_hwtimer hc32_hwtimer_obj[] = +static struct hc32_clock_timer hc32_clock_timer_obj[] = { #ifdef BSP_USING_TMRA_1 TMRA_1_CONFIG, @@ -120,11 +120,11 @@ static struct hc32_hwtimer hc32_hwtimer_obj[] = #endif }; -static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void _timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { stc_tmra_init_t stcTmraInit; struct hc32_irq_config irq_config; - struct hc32_hwtimer *tmr_device = (struct hc32_hwtimer *)timer; + struct hc32_clock_timer *tmr_device = (struct hc32_clock_timer *)timer; RT_ASSERT(timer != RT_NULL); @@ -166,14 +166,14 @@ static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t _timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t _timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; - struct hc32_hwtimer *tmr_device = RT_NULL; + struct hc32_clock_timer *tmr_device = RT_NULL; RT_ASSERT(timer != RT_NULL); - tmr_device = (struct hc32_hwtimer *)timer; + tmr_device = (struct hc32_clock_timer *)timer; /* set timer arr */ TMRA_SetPeriodValue(tmr_device->tmr_handle, t - 1U); @@ -183,13 +183,13 @@ static rt_err_t _timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode return result; } -static void _timer_stop(rt_hwtimer_t *timer) +static void _timer_stop(rt_clock_timer_t *timer) { - struct hc32_hwtimer *tmr_device = RT_NULL; + struct hc32_clock_timer *tmr_device = RT_NULL; RT_ASSERT(timer != RT_NULL); - tmr_device = (struct hc32_hwtimer *)timer; + tmr_device = (struct hc32_clock_timer *)timer; /* stop timer */ TMRA_Stop(tmr_device->tmr_handle); @@ -197,7 +197,7 @@ static void _timer_stop(rt_hwtimer_t *timer) TMRA_SetCountValue(tmr_device->tmr_handle, 0U); } -static rt_err_t _timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t _timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { rt_err_t result = -RT_ERROR; uint32_t freq = *(uint32_t *)arg; @@ -207,7 +207,7 @@ static rt_err_t _timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { if (freq != timer->freq) { @@ -230,14 +230,14 @@ static rt_err_t _timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static rt_uint32_t _timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t _timer_counter_get(rt_clock_timer_t *timer) { - struct hc32_hwtimer *tmr_device = RT_NULL; + struct hc32_clock_timer *tmr_device = RT_NULL; rt_uint32_t Counter; RT_ASSERT(timer != RT_NULL); - tmr_device = (struct hc32_hwtimer *)timer; + tmr_device = (struct hc32_clock_timer *)timer; Counter = TMRA_GetCountValue(tmr_device->tmr_handle); @@ -247,8 +247,8 @@ static rt_uint32_t _timer_counter_get(rt_hwtimer_t *timer) #ifdef BSP_USING_TMRA_1 static void TMRA_1_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_1_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_1_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_1_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_1_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_1_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_1_INDEX].time_device); } #if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -262,8 +262,8 @@ void TMRA_1_Ovf_Udf_Handler(void) #ifdef BSP_USING_TMRA_2 static void TMRA_2_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_2_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_2_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_2_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_2_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_2_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_2_INDEX].time_device); } #if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -277,8 +277,8 @@ void TMRA_2_Ovf_Udf_Handler(void) #ifdef BSP_USING_TMRA_3 static void TMRA_3_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_3_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_3_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_3_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_3_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_3_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_3_INDEX].time_device); } #if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -292,8 +292,8 @@ void TMRA_3_Ovf_Udf_Handler(void) #ifdef BSP_USING_TMRA_4 static void TMRA_4_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_4_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_4_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_4_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_4_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_4_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_4_INDEX].time_device); } #if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -307,8 +307,8 @@ void TMRA_4_Ovf_Udf_Handler(void) #ifdef BSP_USING_TMRA_5 static void TMRA_5_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_5_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_5_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_5_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_5_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_5_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_5_INDEX].time_device); } #if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) @@ -322,8 +322,8 @@ void TMRA_5_Ovf_Udf_Handler(void) #ifdef BSP_USING_TMRA_6 static void TMRA_6_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_6_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_6_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_6_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_6_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_6_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_6_INDEX].time_device); } #if defined (HC32F472) @@ -337,105 +337,105 @@ void TMRA_6_Ovf_Udf_Handler(void) #ifdef BSP_USING_TMRA_7 static void TMRA_7_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_7_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_7_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_7_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_7_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_7_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_7_INDEX].time_device); } #endif /* BSP_USING_TMRA_7 */ #ifdef BSP_USING_TMRA_8 static void TMRA_8_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_8_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_8_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_8_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_8_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_8_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_8_INDEX].time_device); } #endif /* BSP_USING_TMRA_8 */ #ifdef BSP_USING_TMRA_9 static void TMRA_9_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_9_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_9_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_9_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_9_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_9_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_9_INDEX].time_device); } #endif /* BSP_USING_TMRA_9 */ #ifdef BSP_USING_TMRA_10 static void TMRA_10_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_10_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_10_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_10_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_10_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_10_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_10_INDEX].time_device); } #endif /* BSP_USING_TMRA_10 */ #ifdef BSP_USING_TMRA_11 static void TMRA_11_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_11_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_11_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_11_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_11_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_11_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_11_INDEX].time_device); } #endif /* BSP_USING_TMRA_11 */ #ifdef BSP_USING_TMRA_12 static void TMRA_12_callback(void) { - TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_12_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_12_INDEX].flag); - rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_12_INDEX].time_device); + TMRA_ClearStatus(hc32_clock_timer_obj[TMRA_12_INDEX].tmr_handle, hc32_clock_timer_obj[TMRA_12_INDEX].flag); + rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_12_INDEX].time_device); } #endif /* BSP_USING_TMRA_12 */ -static struct rt_hwtimer_info _info[sizeof(hc32_hwtimer_obj) / sizeof(hc32_hwtimer_obj[0])]; +static struct rt_clock_timer_info _info[sizeof(hc32_clock_timer_obj) / sizeof(hc32_clock_timer_obj[0])]; void tmra_get_info_callback(void) { /* Div = 32 */ for (rt_uint8_t i = 0; i < sizeof(_info) / sizeof(_info[0]); i++) { - _info[i].maxcnt = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U / 1000U; /* Period = 1ms */ - _info[i].maxfreq = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U; - _info[i].minfreq = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U / _info[i].maxcnt; - _info[i].cntmode = HWTIMER_CNTMODE_UP; + _info[i].maxcnt = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U / 1000U; /* Period = 1ms */ + _info[i].maxfreq = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U; + _info[i].minfreq = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U / _info[i].maxcnt; + _info[i].cntmode = CLOCK_TIMER_CNTMODE_UP; } #if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) #ifdef BSP_USING_TMRA_1 - hc32_hwtimer_obj[TMRA_1_INDEX].isr.irq_callback = TMRA_1_callback; + hc32_clock_timer_obj[TMRA_1_INDEX].isr.irq_callback = TMRA_1_callback; #endif #ifdef BSP_USING_TMRA_2 - hc32_hwtimer_obj[TMRA_2_INDEX].isr.irq_callback = TMRA_2_callback; + hc32_clock_timer_obj[TMRA_2_INDEX].isr.irq_callback = TMRA_2_callback; #endif #ifdef BSP_USING_TMRA_3 - hc32_hwtimer_obj[TMRA_3_INDEX].isr.irq_callback = TMRA_3_callback; + hc32_clock_timer_obj[TMRA_3_INDEX].isr.irq_callback = TMRA_3_callback; #endif #ifdef BSP_USING_TMRA_4 - hc32_hwtimer_obj[TMRA_4_INDEX].isr.irq_callback = TMRA_4_callback; + hc32_clock_timer_obj[TMRA_4_INDEX].isr.irq_callback = TMRA_4_callback; #endif #ifdef BSP_USING_TMRA_5 - hc32_hwtimer_obj[TMRA_5_INDEX].isr.irq_callback = TMRA_5_callback; + hc32_clock_timer_obj[TMRA_5_INDEX].isr.irq_callback = TMRA_5_callback; #endif #ifdef BSP_USING_TMRA_6 - hc32_hwtimer_obj[TMRA_6_INDEX].isr.irq_callback = TMRA_6_callback; + hc32_clock_timer_obj[TMRA_6_INDEX].isr.irq_callback = TMRA_6_callback; #endif #ifdef BSP_USING_TMRA_7 - hc32_hwtimer_obj[TMRA_7_INDEX].isr.irq_callback = TMRA_7_callback; + hc32_clock_timer_obj[TMRA_7_INDEX].isr.irq_callback = TMRA_7_callback; #endif #ifdef BSP_USING_TMRA_8 - hc32_hwtimer_obj[TMRA_8_INDEX].isr.irq_callback = TMRA_8_callback; + hc32_clock_timer_obj[TMRA_8_INDEX].isr.irq_callback = TMRA_8_callback; #endif #ifdef BSP_USING_TMRA_9 - hc32_hwtimer_obj[TMRA_9_INDEX].isr.irq_callback = TMRA_9_callback; + hc32_clock_timer_obj[TMRA_9_INDEX].isr.irq_callback = TMRA_9_callback; #endif #ifdef BSP_USING_TMRA_10 - hc32_hwtimer_obj[TMRA_10_INDEX].isr.irq_callback = TMRA_10_callback; + hc32_clock_timer_obj[TMRA_10_INDEX].isr.irq_callback = TMRA_10_callback; #endif #ifdef BSP_USING_TMRA_11 - hc32_hwtimer_obj[TMRA_11_INDEX].isr.irq_callback = TMRA_11_callback; + hc32_clock_timer_obj[TMRA_11_INDEX].isr.irq_callback = TMRA_11_callback; #endif #ifdef BSP_USING_TMRA_12 - hc32_hwtimer_obj[TMRA_12_INDEX].isr.irq_callback = TMRA_12_callback; + hc32_clock_timer_obj[TMRA_12_INDEX].isr.irq_callback = TMRA_12_callback; #endif #endif } -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = _timer_init, .start = _timer_start, @@ -444,30 +444,30 @@ static const struct rt_hwtimer_ops _ops = .control = _timer_ctrl, }; -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { int i; int result = RT_EOK; tmra_get_info_callback(); - for (i = 0; i < sizeof(hc32_hwtimer_obj) / sizeof(hc32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(hc32_clock_timer_obj) / sizeof(hc32_clock_timer_obj[0]); i++) { - hc32_hwtimer_obj[i].time_device.info = &_info[i]; - hc32_hwtimer_obj[i].time_device.ops = &_ops; - if (rt_device_hwtimer_register(&hc32_hwtimer_obj[i].time_device, - hc32_hwtimer_obj[i].name, &hc32_hwtimer_obj[i].tmr_handle) == RT_EOK) + hc32_clock_timer_obj[i].time_device.info = &_info[i]; + hc32_clock_timer_obj[i].time_device.ops = &_ops; + if (rt_clock_timer_register(&hc32_clock_timer_obj[i].time_device, + hc32_clock_timer_obj[i].name, &hc32_clock_timer_obj[i].tmr_handle) == RT_EOK) { - LOG_D("%s register success", hc32_hwtimer_obj[i].name); + LOG_D("%s register success", hc32_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", hc32_hwtimer_obj[i].name); + LOG_E("%s register failed", hc32_clock_timer_obj[i].name); result = -RT_ERROR; } } return result; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/hc32/tests/SConscript b/bsp/hc32/tests/SConscript index fd00268e78..3733761301 100644 --- a/bsp/hc32/tests/SConscript +++ b/bsp/hc32/tests/SConscript @@ -52,8 +52,8 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend(['BSP_USING_WDT']) or GetDepend(['BSP_USING_SWDT']): src += ['test_wdt.c'] -if GetDepend(['BSP_USING_HWTIMER']): - src += ['test_hwtimer.c'] +if GetDepend(['BSP_USING_CLOCK_TIMER']): + src += ['test_clock_timer.c'] if GetDepend(['BSP_USING_PULSE_ENCODER']): src += ['test_pulse_encoder.c'] diff --git a/bsp/hc32/tests/test_hwtimer.c b/bsp/hc32/tests/test_clock_timer.c similarity index 75% rename from bsp/hc32/tests/test_hwtimer.c rename to bsp/hc32/tests/test_clock_timer.c index 3bb8d7738c..b5536b9bed 100644 --- a/bsp/hc32/tests/test_hwtimer.c +++ b/bsp/hc32/tests/test_clock_timer.c @@ -9,13 +9,13 @@ */ /* - * 程序清单：这是一个 hwtimer 设备使用例程 - * 例程导出了 hwtimer_sample 命令到控制终端 - * 命令调用格式：hwtimer_sample hwtimer_sample [option1] [option2] [option3] + * 程序清单：这是一个 clock_timer 设备使用例程 + * 例程导出了 clock_timer_sample 命令到控制终端 + * 命令调用格式：clock_timer_sample clock_timer_sample [option1] [option2] [option3] * option1: [tmra_1/2/3..] 定时器单元 * option2: [oneshot/period] 定时模式 * option3: 超时时间，单位毫秒 - * eg:hwtimer_sample tmra_1 period 1000 + * eg:clock_timer_sample tmra_1 period 1000 * 程序功能：每隔一秒打印一次定时器运行时间值，在定时器超时回调函数中打印总tick值 * 可以使用逻辑分析进一步查看测试管脚PA0定时时间是否准确 */ @@ -25,7 +25,7 @@ #include #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER /* IO用于定时时间测试 */ #define TIMEOUT_TEST_PIN GET_PIN(A, 0) @@ -33,13 +33,13 @@ static rt_uint32_t tick; static rt_bool_t cb_run = RT_FALSE; -static void _hwtimer_cmd_print_usage(void) +static void _clock_timer_cmd_print_usage(void) { - rt_kprintf("hwtimer_sample [option1] [option2] [option3]\n"); + rt_kprintf("clock_timer_sample [option1] [option2] [option3]\n"); rt_kprintf(" option1: [tmra_1/2/3..] tmra uint\n"); rt_kprintf(" option2: [oneshot/period] timing mode set\n"); rt_kprintf(" option3: timeout unit:ms\n"); - rt_kprintf(" e.g. MSH >hwtimer_sample tmra_1 period 1000\n"); + rt_kprintf(" e.g. MSH >clock_timer_sample tmra_1 period 1000\n"); } /* 定时器超时回调函数 */ @@ -55,22 +55,22 @@ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { rt_uint8_t i; rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; /* 定时器超时值 */ - rt_hwtimer_mode_t mode = HWTIMER_MODE_ONESHOT; /* 定时器模式 */ + rt_clock_timerval_t timeout_s; /* 定时器超时值 */ + rt_clock_timer_mode_t mode = CLOCK_TIMER_MODE_ONESHOT; /* 定时器模式 */ rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ - rt_hwtimer_t *hwtimer; + rt_clock_timer_t *clock_timer; float t; rt_uint8_t loop_cnt; /* 循环打印次数 */ - rt_hwtimerval_t overflow_tv; /* 定时器超时值 */ + rt_clock_timerval_t overflow_tv; /* 定时器超时值 */ rt_uint32_t timer_out_s; if ((argc != 4) || (rt_strcmp("oneshot", argv[2]) && rt_strcmp("period", argv[2]))) { - _hwtimer_cmd_print_usage(); + _clock_timer_cmd_print_usage(); return -RT_ERROR; } @@ -78,12 +78,12 @@ static int hwtimer_sample(int argc, char *argv[]) hw_dev = rt_device_find(argv[1]); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", argv[1]); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", argv[1]); return -RT_ERROR; } else { - hwtimer = (rt_hwtimer_t *)hw_dev; + clock_timer = (rt_clock_timer_t *)hw_dev; } /* 以读写方式打开设备 */ @@ -97,15 +97,15 @@ static int hwtimer_sample(int argc, char *argv[]) /* 设置模式 */ if (0 == rt_strcmp(argv[2], "oneshot")) { - mode = HWTIMER_MODE_ONESHOT; + mode = CLOCK_TIMER_MODE_ONESHOT; loop_cnt = 1; } else if (0 == rt_strcmp(argv[2], "period")) { - mode = HWTIMER_MODE_PERIOD; + mode = CLOCK_TIMER_MODE_PERIOD; loop_cnt = 5; } - rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); /* 设置超时回调函数 */ rt_device_set_rx_indicate(hw_dev, timeout_cb); @@ -132,15 +132,15 @@ static int hwtimer_sample(int argc, char *argv[]) rt_thread_mdelay(1000); /* 读取定时器当前值 */ - if (mode == HWTIMER_MODE_PERIOD) + if (mode == CLOCK_TIMER_MODE_PERIOD) { rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); } - else if (mode == HWTIMER_MODE_ONESHOT) + else if (mode == CLOCK_TIMER_MODE_ONESHOT) { rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); - t = hwtimer->overflow * hwtimer->period_sec; + t = clock_timer->overflow * clock_timer->period_sec; overflow_tv.sec = (rt_int32_t)t; overflow_tv.usec = (rt_int32_t)((t - overflow_tv.sec) * 1000000); @@ -160,5 +160,5 @@ static int hwtimer_sample(int argc, char *argv[]) return ret; } /* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample: devname [oneshot | period] timeout); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample: devname [oneshot | period] timeout); #endif diff --git a/bsp/hk32/hk32f030c8-mini/README.md b/bsp/hk32/hk32f030c8-mini/README.md index 14fc745b89..22d62e433b 100644 --- a/bsp/hk32/hk32f030c8-mini/README.md +++ b/bsp/hk32/hk32f030c8-mini/README.md @@ -49,7 +49,7 @@ HK32F030C8T6-MINI板级包支持MDK5开发环境和GCC编译器，以下是具 | SPI | 支持 | SPI1 | | ADC | 不支持 | | | PWM | 不支持 | | -| HWTIMER | 不支持 | | +| CLOCK_TIMER | 不支持 | | | WDT | 不支持 | | | RTC | 不支持 | | | FLASH | 不支持 | | diff --git a/bsp/hk32/hk32f030c8-mini/board/Kconfig b/bsp/hk32/hk32f030c8-mini/board/Kconfig index 2479bdc2ec..e3e8e27c2f 100644 --- a/bsp/hk32/hk32f030c8-mini/board/Kconfig +++ b/bsp/hk32/hk32f030c8-mini/board/Kconfig @@ -78,11 +78,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTIM3 bool "Enable hardware timer3" default n diff --git a/bsp/hk32/libraries/rt_drivers/SConscript b/bsp/hk32/libraries/rt_drivers/SConscript index b810f026e9..c816e2c8fb 100644 --- a/bsp/hk32/libraries/rt_drivers/SConscript +++ b/bsp/hk32/libraries/rt_drivers/SConscript @@ -18,8 +18,8 @@ if GetDepend(['RT_USING_SERIAL']): if GetDepend(['BSP_USING_PWM']): src += ['drv_pwm.c'] -if GetDepend(['BSP_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['BSP_USING_CLOCK_TIMER']): + src += ['drv_timer.c'] if GetDepend(['BSP_USING_SPI']): src += ['drv_spi.c'] diff --git a/bsp/hpmicro/hpm5300evk/board/Kconfig b/bsp/hpmicro/hpm5300evk/board/Kconfig index b02bba277d..2abc17f7fb 100644 --- a/bsp/hpmicro/hpm5300evk/board/Kconfig +++ b/bsp/hpmicro/hpm5300evk/board/Kconfig @@ -342,7 +342,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm5300evk/board/board.c b/bsp/hpmicro/hpm5300evk/board/board.c index f967e2deb7..323a3974ba 100644 --- a/bsp/hpmicro/hpm5300evk/board/board.c +++ b/bsp/hpmicro/hpm5300evk/board/board.c @@ -14,8 +14,7 @@ #include "hpm_i2c_drv.h" #include "hpm_pcfg_drv.h" #include - - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -231,12 +230,15 @@ void board_init_clock(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -624,4 +626,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm5301evklite/board/Kconfig b/bsp/hpmicro/hpm5301evklite/board/Kconfig index 63888530c2..41f1d35f17 100644 --- a/bsp/hpmicro/hpm5301evklite/board/Kconfig +++ b/bsp/hpmicro/hpm5301evklite/board/Kconfig @@ -266,7 +266,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm5301evklite/board/board.c b/bsp/hpmicro/hpm5301evklite/board/board.c index 6d2339c1d4..961b7d9fcb 100644 --- a/bsp/hpmicro/hpm5301evklite/board/board.c +++ b/bsp/hpmicro/hpm5301evklite/board/board.c @@ -14,7 +14,7 @@ #include "hpm_i2c_drv.h" #include "hpm_pcfg_drv.h" #include - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -233,12 +233,15 @@ void board_init_clock(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -504,4 +507,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm5e00evk/board/Kconfig b/bsp/hpmicro/hpm5e00evk/board/Kconfig index 6e8a2b2341..a6813786a2 100644 --- a/bsp/hpmicro/hpm5e00evk/board/Kconfig +++ b/bsp/hpmicro/hpm5e00evk/board/Kconfig @@ -401,7 +401,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm5e00evk/board/board.c b/bsp/hpmicro/hpm5e00evk/board/board.c index 14b9f61a8c..41137ba6f0 100644 --- a/bsp/hpmicro/hpm5e00evk/board/board.c +++ b/bsp/hpmicro/hpm5e00evk/board/board.c @@ -18,6 +18,8 @@ #include "hpm_enet_drv.h" #include "hpm_usb_drv.h" #include "hpm_pcfg_drv.h" +#include +#include /** * @brief FLASH configuration option definitions: @@ -178,12 +180,15 @@ void board_init(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -713,4 +718,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6200evk/board/Kconfig b/bsp/hpmicro/hpm6200evk/board/Kconfig index 43fbd1d4ba..0b5373e534 100644 --- a/bsp/hpmicro/hpm6200evk/board/Kconfig +++ b/bsp/hpmicro/hpm6200evk/board/Kconfig @@ -130,7 +130,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR1 bool "Enable GPTMR1" diff --git a/bsp/hpmicro/hpm6200evk/board/board.c b/bsp/hpmicro/hpm6200evk/board/board.c index 5025badde5..87b28b838b 100644 --- a/bsp/hpmicro/hpm6200evk/board/board.c +++ b/bsp/hpmicro/hpm6200evk/board/board.c @@ -20,6 +20,7 @@ #include "hpm_pllctlv2_drv.h" #include "hpm_pcfg_drv.h" #include +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -190,12 +191,15 @@ void board_init_core1(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -729,4 +733,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6300evk/board/Kconfig b/bsp/hpmicro/hpm6300evk/board/Kconfig index 7a1ea26dbf..accf154bcc 100644 --- a/bsp/hpmicro/hpm6300evk/board/Kconfig +++ b/bsp/hpmicro/hpm6300evk/board/Kconfig @@ -468,7 +468,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm6300evk/board/board.c b/bsp/hpmicro/hpm6300evk/board/board.c index 8e9a744078..8aef75b62e 100644 --- a/bsp/hpmicro/hpm6300evk/board/board.c +++ b/bsp/hpmicro/hpm6300evk/board/board.c @@ -24,7 +24,7 @@ #include "hpm_debug_console.h" #include - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -193,12 +193,15 @@ uint32_t board_init_femc_clock(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -820,4 +823,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6750evk/board/Kconfig b/bsp/hpmicro/hpm6750evk/board/Kconfig index 975ec75bc8..386d29bd17 100644 --- a/bsp/hpmicro/hpm6750evk/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk/board/Kconfig @@ -279,7 +279,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR1 bool "Enable GPTMR1" diff --git a/bsp/hpmicro/hpm6750evk/board/board.c b/bsp/hpmicro/hpm6750evk/board/board.c index daa8d8b45f..f9bbc614c2 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.c +++ b/bsp/hpmicro/hpm6750evk/board/board.c @@ -24,8 +24,10 @@ #include "hpm_enet_drv.h" #include "hpm_pcfg_drv.h" #include + #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT #include "hpm_enet_phy_common.h" +#include #endif /** @@ -311,12 +313,15 @@ void board_panel_para_to_lcdc(lcdc_config_t *config) void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -1270,4 +1275,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6750evk2/board/Kconfig b/bsp/hpmicro/hpm6750evk2/board/Kconfig index 9f97bd4a7d..893320d8c8 100644 --- a/bsp/hpmicro/hpm6750evk2/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk2/board/Kconfig @@ -785,7 +785,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm6750evk2/board/board.c b/bsp/hpmicro/hpm6750evk2/board/board.c index 73fdf9f866..fc162f6475 100644 --- a/bsp/hpmicro/hpm6750evk2/board/board.c +++ b/bsp/hpmicro/hpm6750evk2/board/board.c @@ -24,8 +24,10 @@ #include "hpm_enet_drv.h" #include "hpm_pcfg_drv.h" #include + #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT #include "hpm_enet_phy_common.h" +#include #endif /** @@ -311,12 +313,15 @@ void board_panel_para_to_lcdc(lcdc_config_t *config) void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -1267,4 +1272,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6750evkmini/board/Kconfig b/bsp/hpmicro/hpm6750evkmini/board/Kconfig index 29c636386e..f495435be7 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/Kconfig +++ b/bsp/hpmicro/hpm6750evkmini/board/Kconfig @@ -791,7 +791,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.c b/bsp/hpmicro/hpm6750evkmini/board/board.c index 17a6df6a56..be841cd44f 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/board.c @@ -24,7 +24,7 @@ #include "hpm_pcfg_drv.h" #include "hpm_enet_drv.h" #include - +#include static bool invert_led_level; /** @@ -369,12 +369,15 @@ void board_panel_para_to_lcdc(lcdc_config_t *config) void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -1210,4 +1213,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6800evk/board/Kconfig b/bsp/hpmicro/hpm6800evk/board/Kconfig index 9e8d58ad4e..d23696e854 100644 --- a/bsp/hpmicro/hpm6800evk/board/Kconfig +++ b/bsp/hpmicro/hpm6800evk/board/Kconfig @@ -567,7 +567,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm6800evk/board/board.c b/bsp/hpmicro/hpm6800evk/board/board.c index 52da53c800..8200bb9c8e 100644 --- a/bsp/hpmicro/hpm6800evk/board/board.c +++ b/bsp/hpmicro/hpm6800evk/board/board.c @@ -27,7 +27,7 @@ #include "hpm_mipi_dsi_drv.h" #include "hpm_mipi_dsi_phy_drv.h" #include - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -191,12 +191,15 @@ void board_init(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -1469,4 +1472,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6e00evk/board/Kconfig b/bsp/hpmicro/hpm6e00evk/board/Kconfig index 795107e16c..6ba06a28d8 100644 --- a/bsp/hpmicro/hpm6e00evk/board/Kconfig +++ b/bsp/hpmicro/hpm6e00evk/board/Kconfig @@ -753,7 +753,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm6e00evk/board/board.c b/bsp/hpmicro/hpm6e00evk/board/board.c index e786fe8e75..0cbf04d134 100644 --- a/bsp/hpmicro/hpm6e00evk/board/board.c +++ b/bsp/hpmicro/hpm6e00evk/board/board.c @@ -23,7 +23,7 @@ #include "hpm_esc_drv.h" #include "hpm_tsw_drv.h" #include - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -219,12 +219,15 @@ uint32_t board_init_femc_clock(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT @@ -1075,4 +1078,3 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) } return freq; } - diff --git a/bsp/hpmicro/hpm6p00evk/board/Kconfig b/bsp/hpmicro/hpm6p00evk/board/Kconfig index beaf5b3a9e..ad13b7dab8 100644 --- a/bsp/hpmicro/hpm6p00evk/board/Kconfig +++ b/bsp/hpmicro/hpm6p00evk/board/Kconfig @@ -401,7 +401,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n - select RT_USING_HWTIMER if BSP_USING_GPTMR + select RT_USING_CLOCK_TIME if BSP_USING_GPTMR if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" diff --git a/bsp/hpmicro/hpm6p00evk/board/board.c b/bsp/hpmicro/hpm6p00evk/board/board.c index 1c2f11ea06..eaef898dbf 100644 --- a/bsp/hpmicro/hpm6p00evk/board/board.c +++ b/bsp/hpmicro/hpm6p00evk/board/board.c @@ -20,7 +20,7 @@ #include "hpm_usb_drv.h" #include "hpm_femc_drv.h" #include - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -202,12 +202,15 @@ uint32_t board_init_femc_clock(void) void board_delay_us(uint32_t us) { - clock_cpu_delay_us(us); + rt_hw_us_delay(us); } void board_delay_ms(uint32_t ms) { - clock_cpu_delay_ms(ms); + while (ms--) + { + rt_hw_us_delay(1000); + } } #if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT diff --git a/bsp/hpmicro/libraries/drivers/SConscript b/bsp/hpmicro/libraries/drivers/SConscript index d558ae6e9b..4f5fa25d84 100644 --- a/bsp/hpmicro/libraries/drivers/SConscript +++ b/bsp/hpmicro/libraries/drivers/SConscript @@ -3,6 +3,7 @@ from building import * cwd = GetCurrentDir() src = [] +src += ['drv_delay.c'] if GetDepend('BSP_USING_GPIO'): src += ['drv_gpio.c'] @@ -33,7 +34,7 @@ if GetDepend('BSP_USING_PWM') or GetDepend('BSP_USING_PWMV2'): src += ['drv_pwm.c'] if GetDepend('BSP_USING_GPTMR'): - src += ['drv_hwtimer.c'] + src += ['drv_timer.c'] if GetDepend('BSP_USING_CAN'): src += ['drv_can.c'] diff --git a/bsp/hpmicro/libraries/drivers/drv_delay.c b/bsp/hpmicro/libraries/drivers/drv_delay.c new file mode 100644 index 0000000000..f14b45a29e --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_delay.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_clock_drv.h" + +void rt_hw_us_delay(rt_uint32_t us) +{ + clock_cpu_delay_us(us); +} diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c b/bsp/hpmicro/libraries/drivers/drv_timer.c similarity index 79% rename from bsp/hpmicro/libraries/drivers/drv_hwtimer.c rename to bsp/hpmicro/libraries/drivers/drv_timer.c index 7b29c99b51..3c3a37c4f4 100644 --- a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c +++ b/bsp/hpmicro/libraries/drivers/drv_timer.c @@ -8,9 +8,9 @@ #include #include #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME -#include "drv_hwtimer.h" +#include "drv_timer.h" #include "board.h" #include "hpm_gptmr_drv.h" @@ -20,34 +20,34 @@ typedef struct _hpm_gptimer { GPTMR_Type *base; const char *name; - rt_hwtimer_t timer; + rt_clock_timer_t timer; uint32_t channel; clock_name_t clock_name; int32_t irq_num; uint8_t irq_priority; } hpm_gptimer_t; -static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode); -static void hpm_hwtimer_stop(rt_hwtimer_t *timer); -static rt_uint32_t hpm_hwtimer_count_get(rt_hwtimer_t *timer); -static rt_err_t hpm_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void hpm_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t hpm_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode); +static void hpm_clock_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t hpm_clock_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t hpm_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); static void hpm_hwtmr_isr(hpm_gptimer_t *gptmr); -static const struct rt_hwtimer_ops hpm_hwtimer_ops = { - .init = hpm_hwtimer_init, - .start = hpm_hwtimer_start, - .stop = hpm_hwtimer_stop, - .count_get = hpm_hwtimer_count_get, - .control = hpm_hwtimer_control +static const struct rt_clock_timer_ops hpm_clock_timer_ops = { + .init = hpm_clock_timer_init, + .start = hpm_clock_timer_start, + .stop = hpm_clock_timer_stop, + .count_get = hpm_clock_timer_count_get, + .control = hpm_clock_timer_control }; -static const struct rt_hwtimer_info hpm_hwtimer_info = { +static const struct rt_clock_timer_info hpm_clock_timer_info = { .maxfreq = 100000000UL, .minfreq = 93750UL, .maxcnt = 0xFFFFFFFFUL, - .cntmode = HWTIMER_CNTMODE_UP + .cntmode = CLOCK_TIMER_CNTMODE_UP }; @@ -262,12 +262,12 @@ static void hpm_hwtmr_isr(hpm_gptimer_t *timer) uint32_t hwtmr_stat = gptmr_get_status(timer->base); if ((hwtmr_stat & GPTMR_CH_RLD_STAT_MASK(timer->channel)) != 0U) { - rt_device_hwtimer_isr(&timer->timer); + rt_clock_timer_isr(&timer->timer); gptmr_clear_status(timer->base, GPTMR_CH_RLD_STAT_MASK(timer->channel)); } } -static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void hpm_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*)timer->parent.user_data; GPTMR_Type *base = hpm_gptmr->base; @@ -282,7 +282,7 @@ static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t hpm_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*) timer->parent.user_data; GPTMR_Type *base = hpm_gptmr->base; @@ -307,7 +307,7 @@ static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim return RT_EOK; } -static void hpm_hwtimer_stop(rt_hwtimer_t *timer) +static void hpm_clock_timer_stop(rt_clock_timer_t *timer) { hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*)timer->parent.user_data; GPTMR_Type *base = hpm_gptmr->base; @@ -315,7 +315,7 @@ static void hpm_hwtimer_stop(rt_hwtimer_t *timer) gptmr_stop_counter(base, hpm_gptmr->channel); } -static rt_uint32_t hpm_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t hpm_clock_timer_count_get(rt_clock_timer_t *timer) { hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*)timer->parent.user_data; GPTMR_Type *base = hpm_gptmr->base; @@ -325,7 +325,7 @@ static rt_uint32_t hpm_hwtimer_count_get(rt_hwtimer_t *timer) return current_cnt; } -static rt_err_t hpm_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t hpm_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*) timer->parent.user_data; @@ -333,16 +333,16 @@ static rt_err_t hpm_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void * switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: err = -RT_ERROR; break; - case HWTIMER_CTRL_INFO_GET: - *(rt_hwtimer_t*)args = hpm_gptmr->timer; + case CLOCK_TIMER_CTRL_INFO_GET: + *(rt_clock_timer_t*)args = hpm_gptmr->timer; break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: hpm_gptmr->timer.mode = *(rt_uint32_t*)args; break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: gptmr_stop_counter(base, hpm_gptmr->channel); break; } @@ -351,15 +351,15 @@ static rt_err_t hpm_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void * } -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { int ret = RT_EOK; for (uint32_t i = 0; i < ARRAY_SIZE(s_gptimers); i++) { - s_gptimers[i]->timer.info = &hpm_hwtimer_info; - s_gptimers[i]->timer.ops = &hpm_hwtimer_ops; - ret = rt_device_hwtimer_register(&s_gptimers[i]->timer, s_gptimers[i]->name, s_gptimers[i]); + s_gptimers[i]->timer.info = &hpm_clock_timer_info; + s_gptimers[i]->timer.ops = &hpm_clock_timer_ops; + ret = rt_clock_timer_register(&s_gptimers[i]->timer, s_gptimers[i]->name, s_gptimers[i]); if (ret != RT_EOK) { LOG_E("%s register failed\n", s_gptimers[i]->name); @@ -369,6 +369,6 @@ int rt_hw_hwtimer_init(void) return ret; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); #endif /* BSP_USING_GPTMR */ diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.h b/bsp/hpmicro/libraries/drivers/drv_timer.h similarity index 42% rename from bsp/hpmicro/libraries/drivers/drv_hwtimer.h rename to bsp/hpmicro/libraries/drivers/drv_timer.h index 29739f0640..3a6e615c0a 100644 --- a/bsp/hpmicro/libraries/drivers/drv_hwtimer.h +++ b/bsp/hpmicro/libraries/drivers/drv_timer.h @@ -5,10 +5,10 @@ * */ -#ifndef DRV_HWTIMER_H -#define DRV_HWTIMER_H +#ifndef DRV_CLOCK_TIMER_H +#define DRV_CLOCK_TIMER_H -int rt_hw_hwtimer_init(void); +int rt_hw_clock_timer_init(void); -#endif /* DRV_HWTIMER_H */ +#endif /* DRV_CLOCK_TIMER_H */ diff --git a/bsp/k210/drivers/SConscript b/bsp/k210/drivers/SConscript index cc4dc0e26d..71b5179595 100644 --- a/bsp/k210/drivers/SConscript +++ b/bsp/k210/drivers/SConscript @@ -18,12 +18,9 @@ if GetDepend('BSP_USING_LCD'): src += ['drv_mpylcd.c'] src += ['test/lcd_test.c'] -if GetDepend('RT_USING_HWTIMER'): +if GetDepend('RT_USING_CLOCK_TIME') and os.path.exists(os.path.join(cwd, 'drv_hw_timer.c')): src += ['drv_hw_timer.c'] -if GetDepend('RT_USING_CPUTIME'): - src += ['drv_cputime.c'] - if GetDepend('RT_USING_I2C'): src += ['drv_i2c.c'] diff --git a/bsp/k230/board/Kconfig b/bsp/k230/board/Kconfig index 92c7866560..11d7e6aae0 100644 --- a/bsp/k230/board/Kconfig +++ b/bsp/k230/board/Kconfig @@ -165,7 +165,7 @@ menu "Drivers Configuration" menuconfig BSP_USING_TIMERS bool "Enable Hardware Timers" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_TIMERS diff --git a/bsp/k230/drivers/interdrv/hwtimer/SConscript b/bsp/k230/drivers/interdrv/clock_timer/SConscript similarity index 100% rename from bsp/k230/drivers/interdrv/hwtimer/SConscript rename to bsp/k230/drivers/interdrv/clock_timer/SConscript diff --git a/bsp/k230/drivers/interdrv/hwtimer/drv_timer.c b/bsp/k230/drivers/interdrv/clock_timer/drv_timer.c similarity index 84% rename from bsp/k230/drivers/interdrv/hwtimer/drv_timer.c rename to bsp/k230/drivers/interdrv/clock_timer/drv_timer.c index 4ec803739c..8bc6c50fc2 100644 --- a/bsp/k230/drivers/interdrv/hwtimer/drv_timer.c +++ b/bsp/k230/drivers/interdrv/clock_timer/drv_timer.c @@ -52,8 +52,8 @@ #include "drv_timer.h" #include -static void k230_timer_stop(rt_hwtimer_t *timer); -static void k230_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void k230_timer_stop(rt_clock_timer_t *timer); +static void k230_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { struct k230_timer *kd_timer = rt_container_of(timer, struct k230_timer, device); @@ -76,7 +76,7 @@ static void k230_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t k230_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t k230_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { struct k230_timer *kd_timer = rt_container_of(timer, struct k230_timer, device); uint8_t id = kd_timer->id; @@ -87,7 +87,7 @@ static rt_err_t k230_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtime return RT_EOK; } -static void k230_timer_stop(rt_hwtimer_t *timer) +static void k230_timer_stop(rt_clock_timer_t *timer) { struct k230_timer *kd_timer = rt_container_of(timer, struct k230_timer, device); uint8_t id = kd_timer->id; @@ -96,7 +96,7 @@ static void k230_timer_stop(rt_hwtimer_t *timer) reg->channel[id].control |= TIMER_CR_INTERRUPT_MASK; } -static rt_uint32_t k230_timer_get(rt_hwtimer_t *timer) +static rt_uint32_t k230_timer_get(rt_clock_timer_t *timer) { struct k230_timer *kd_timer = rt_container_of(timer, struct k230_timer, device); uint8_t id = kd_timer->id; @@ -104,13 +104,13 @@ static rt_uint32_t k230_timer_get(rt_hwtimer_t *timer) return reg->channel[id].current_value; } -static rt_err_t k230_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t k230_timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { struct k230_timer *kd_timer = rt_container_of(timer, struct k230_timer, device); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: timer->freq = *((rt_uint32_t*)arg); sysctl_clk_set_leaf_parent(kd_timer->clk, kd_timer->clk_src); if (timer->freq == timer->info->minfreq) @@ -122,32 +122,32 @@ static rt_err_t k230_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) if (timer->freq == 25*MHz) sysctl_clk_set_leaf_div(kd_timer->clk_src, 1, 4); break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: k230_timer_stop(timer); break; - case HWTIMER_CTRL_INFO_GET: + case CLOCK_TIMER_CTRL_INFO_GET: if (arg == RT_NULL) { - LOG_E("HWTIMER_CTRL_INFO_GET arg is NULL"); + LOG_E("CLOCK_TIMER_CTRL_INFO_GET arg is NULL"); return -RT_ERROR; } - *(struct rt_hwtimer_info *)arg = *(kd_timer->device.info); + *(struct rt_clock_timer_info *)arg = *(kd_timer->device.info); break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: if (arg == RT_NULL) { - LOG_E("HWTIMER_CTRL_MODE_SET arg is NULL"); + LOG_E("CLOCK_TIMER_CTRL_MODE_SET arg is NULL"); return -RT_ERROR; } - timer->mode = *(rt_hwtimer_mode_t *)arg; - if (timer->mode != HWTIMER_MODE_ONESHOT) + timer->mode = *(rt_clock_timer_mode_t *)arg; + if (timer->mode != CLOCK_TIMER_MODE_ONESHOT) { LOG_E("mode is invalid/unsupported, only ONESHOT is supported"); return -RT_ERROR; } break; default: - LOG_E("HWTIMER_CTRL cmd is invalid"); + LOG_E("CLOCK_TIMER_CTRL cmd is invalid"); return -RT_ERROR; } return RT_EOK; @@ -165,15 +165,15 @@ static int k230_timer_fops_close(struct dfs_file* fd) return rt_device_close(device); } -static const struct rt_hwtimer_info k230_timer_info = +static const struct rt_clock_timer_info k230_timer_info = { 100000000, /* the maximum count frequency can be set */ 12500000, /* the minimum count frequency can be set */ 0xFFFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_DW, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_DW, /* Increment or Decreasing count mode */ }; -static const struct rt_hwtimer_ops k230_timer_ops = +static const struct rt_clock_timer_ops k230_timer_ops = { .init = k230_timer_init, .start = k230_timer_start, @@ -187,20 +187,20 @@ static const struct dfs_file_ops k230_timer_fops = { k230_timer_fops_close, }; -void k230_hwtimer_isr(int vector, void *param) +void k230_clock_timer_isr(int vector, void *param) { uint32_t ret; struct k230_timer *kd_timer = (struct k230_timer *)param; - rt_hwtimer_t *hwtimer = (rt_hwtimer_t *)&(kd_timer->device); + rt_clock_timer_t *clock_timer = (rt_clock_timer_t *)&(kd_timer->device); - RT_ASSERT(kd_timer != RT_NULL && hwtimer != RT_NULL); + RT_ASSERT(kd_timer != RT_NULL && clock_timer != RT_NULL); int id = kd_timer->id; k230_timer_regs_t* reg = (k230_timer_regs_t *)kd_timer->base; ret = (reg->channel[id].eoi); - rt_device_hwtimer_isr(hwtimer); + rt_clock_timer_isr(clock_timer); } static struct k230_timer timer_devices[] = @@ -211,7 +211,7 @@ static struct k230_timer timer_devices[] = .device.ops = &k230_timer_ops, .device.parent.fops = &k230_timer_fops, - .name = "hwtimer0", + .name = "clock_timer0", .id = 0, .clk = SYSCTL_CLK_TIMER0, .clk_src = SYSCTL_CLK_TIMER0_SRC, @@ -225,7 +225,7 @@ static struct k230_timer timer_devices[] = .device.ops = &k230_timer_ops, .device.parent.fops = &k230_timer_fops, - .name = "hwtimer1", + .name = "clock_timer1", .id = 1, .clk = SYSCTL_CLK_TIMER1, .clk_src = SYSCTL_CLK_TIMER1_SRC, @@ -239,7 +239,7 @@ static struct k230_timer timer_devices[] = .device.ops = &k230_timer_ops, .device.parent.fops = &k230_timer_fops, - .name = "hwtimer2", + .name = "clock_timer2", .id = 2, .clk = SYSCTL_CLK_TIMER2, .clk_src = SYSCTL_CLK_TIMER2_SRC, @@ -253,7 +253,7 @@ static struct k230_timer timer_devices[] = .device.ops = &k230_timer_ops, .device.parent.fops = &k230_timer_fops, - .name = "hwtimer3", + .name = "clock_timer3", .id = 3, .clk = SYSCTL_CLK_TIMER3, .clk_src = SYSCTL_CLK_TIMER3_SRC, @@ -267,7 +267,7 @@ static struct k230_timer timer_devices[] = .device.ops = &k230_timer_ops, .device.parent.fops = &k230_timer_fops, - .name = "hwtimer4", + .name = "clock_timer4", .id = 4, .clk = SYSCTL_CLK_TIMER4, .clk_src = SYSCTL_CLK_TIMER4_SRC, @@ -281,7 +281,7 @@ static struct k230_timer timer_devices[] = .device.ops = &k230_timer_ops, .device.parent.fops = &k230_timer_fops, - .name = "hwtimer5", + .name = "clock_timer5", .id = 5, .clk = SYSCTL_CLK_TIMER5, .clk_src = SYSCTL_CLK_TIMER5_SRC, @@ -315,7 +315,7 @@ int rt_hw_timer_init(void) { timer_devices[i].base = (rt_ubase_t)base; - if (rt_device_hwtimer_register(&timer_devices[i].device, timer_devices[i].name, RT_NULL) != RT_EOK) + if (rt_clock_timer_register(&timer_devices[i].device, timer_devices[i].name, RT_NULL) != RT_EOK) { LOG_E("%s register failed!", timer_devices[i].name); return -RT_ERROR; @@ -323,7 +323,7 @@ int rt_hw_timer_init(void) LOG_D("%s register OK!", timer_devices[i].name); rt_hw_interrupt_install(timer_devices[i].irq_num, - k230_hwtimer_isr, + k230_clock_timer_isr, &timer_devices[i], timer_devices[i].name); rt_hw_interrupt_umask(timer_devices[i].irq_num); diff --git a/bsp/k230/drivers/interdrv/hwtimer/drv_timer.h b/bsp/k230/drivers/interdrv/clock_timer/drv_timer.h similarity index 98% rename from bsp/k230/drivers/interdrv/hwtimer/drv_timer.h rename to bsp/k230/drivers/interdrv/clock_timer/drv_timer.h index 71392243bc..e0d127bc43 100644 --- a/bsp/k230/drivers/interdrv/hwtimer/drv_timer.h +++ b/bsp/k230/drivers/interdrv/clock_timer/drv_timer.h @@ -32,7 +32,7 @@ #ifndef DRV_TIMER_H__ #define DRV_TIMER_H__ #include -#include +#include #include "sysctl_clk.h" #include "board.h" @@ -85,7 +85,7 @@ typedef struct _k230_timer_regs } __attribute__((packed, aligned(4))) k230_timer_regs_t; struct k230_timer { - struct rt_hwtimer_device device; + struct rt_clock_timer_device device; const char *name; rt_ubase_t base; uint32_t id; diff --git a/bsp/k230/drivers/utest/test_timer.c b/bsp/k230/drivers/utest/test_timer.c index 50a5578a70..ddcffbacbd 100644 --- a/bsp/k230/drivers/utest/test_timer.c +++ b/bsp/k230/drivers/utest/test_timer.c @@ -30,9 +30,9 @@ */ #include -#include +#include -#include "../interdrv/hwtimer/drv_timer.h" +#include "../interdrv/clock_timer/drv_timer.h" #include "utest.h" /* @@ -46,8 +46,8 @@ * 6. Trigger the interrupt callback when the timer times out and print a message. */ -#define DEVICE_NAME0 "hwtimer0" -#define DEVICE_NAME1 "hwtimer1" +#define DEVICE_NAME0 "clock_timer0" +#define DEVICE_NAME1 "clock_timer1" static rt_device_t tmr_dev_0; static rt_device_t tmr_dev_1; @@ -59,24 +59,24 @@ static rt_device_t tmr_dev_1; static rt_err_t tmr_timeout_cb(rt_device_t dev, rt_size_t size) { - struct rt_hwtimer_device *rt_timer = rt_container_of(dev, struct rt_hwtimer_device, parent); + struct rt_clock_timer_device *rt_timer = rt_container_of(dev, struct rt_clock_timer_device, parent); struct k230_timer *kd_timer = rt_container_of(rt_timer, struct k230_timer, device); LOG_I("---> [%s] timeout callback fucntion!\n", kd_timer->name); return RT_EOK; } -static void test_hwtimer(void) +static void test_clock_timer(void) { - rt_hwtimerval_t timerval; - rt_hwtimer_mode_t mode; + rt_clock_timerval_t timerval; + rt_clock_timer_mode_t mode; rt_size_t tsize; rt_uint32_t freq = 25000000; /* Frequency options: 12.5M 25M 50M 100M */ rt_err_t ret; rt_ssize_t size; int loop_count = 0; - LOG_I("test_hwtimer start"); + LOG_I("test_clock_timer start"); tmr_dev_0 = rt_device_find(DEVICE_NAME0); uassert_not_null(tmr_dev_0); @@ -88,7 +88,7 @@ static void test_hwtimer(void) ret = rt_device_open(tmr_dev_1, RT_DEVICE_OFLAG_RDWR); uassert_int_equal(ret, RT_EOK); - ret = rt_device_control(tmr_dev_0, HWTIMER_CTRL_FREQ_SET, &freq); + ret = rt_device_control(tmr_dev_0, CLOCK_TIMER_CTRL_FREQ_SET, &freq); uassert_int_equal(ret, RT_EOK); ret = rt_device_set_rx_indicate(tmr_dev_0, tmr_timeout_cb); @@ -99,8 +99,8 @@ static void test_hwtimer(void) timerval.sec = TIMEOUT_SEC_0; timerval.usec = 0; tsize = sizeof(timerval); - mode = HWTIMER_MODE_ONESHOT; - ret = rt_device_control(tmr_dev_0, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_ONESHOT; + ret = rt_device_control(tmr_dev_0, CLOCK_TIMER_CTRL_MODE_SET, &mode); uassert_int_equal(ret, RT_EOK); size = rt_device_write(tmr_dev_0, 0, &timerval, tsize); uassert_int_equal(size, tsize); @@ -109,8 +109,8 @@ static void test_hwtimer(void) timerval.sec = TIMEOUT_SEC_1; timerval.usec = 0; tsize = sizeof(timerval); - mode = HWTIMER_MODE_ONESHOT; - ret = rt_device_control(tmr_dev_1, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_ONESHOT; + ret = rt_device_control(tmr_dev_1, CLOCK_TIMER_CTRL_MODE_SET, &mode); uassert_int_equal(ret, RT_EOK); size = rt_device_write(tmr_dev_1, 0, &timerval, tsize); uassert_int_equal(size, tsize); @@ -133,12 +133,12 @@ static void test_hwtimer(void) uassert_int_equal(ret, RT_EOK); ret = rt_device_close(tmr_dev_1); uassert_int_equal(ret, RT_EOK); - LOG_I("test_hwtimer end"); + LOG_I("test_clock_timer end"); } static void hw_timer_testcase(void) { - UTEST_UNIT_RUN(test_hwtimer); + UTEST_UNIT_RUN(test_clock_timer); } static rt_err_t utest_tc_init(void) diff --git a/bsp/mm32/libraries/MM32F3270_HAL/SConscript b/bsp/mm32/libraries/MM32F3270_HAL/SConscript index dd7e019ef4..2ca9f25edd 100644 --- a/bsp/mm32/libraries/MM32F3270_HAL/SConscript +++ b/bsp/mm32/libraries/MM32F3270_HAL/SConscript @@ -29,7 +29,7 @@ if GetDepend(['RT_USING_SPI']): if GetDepend(['RT_USING_USB']): src += ['MM32F3270_HAL_Driver/Src/hal_usb.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']): src += ['MM32F3270_HAL_Driver/Src/hal_tim_16b.c'] src += ['MM32F3270_HAL_Driver/Src/hal_tim_32b.c'] src += ['MM32F3270_HAL_Driver/Src/hal_tim_adv.c'] diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript b/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript index 24b530897e..b935a5a6b6 100644 --- a/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript @@ -33,7 +33,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['n32g43x_std_periph_driver/src/n32g43x_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['n32g43x_std_periph_driver/src/n32g43x_tim.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript b/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript index fc0934459f..3b0502c2c4 100644 --- a/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript @@ -38,7 +38,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['n32g45x_std_periph_driver/src/n32g45x_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['n32g45x_std_periph_driver/src/n32g45x_tim.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/SConscript b/bsp/n32/libraries/N32G4FR_Firmware_Library/SConscript index d10b610de1..7d39f87d20 100644 --- a/bsp/n32/libraries/N32G4FR_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32G4FR_Firmware_Library/SConscript @@ -32,7 +32,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['n32g4fr_std_periph_driver/src/n32g4fr_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['n32g4fr_std_periph_driver/src/n32g4fr_tim.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript b/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript index 49b8b0a13b..05abfbd596 100644 --- a/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript @@ -33,7 +33,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['n32l40x_std_periph_driver/src/n32l40x_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['n32l40x_std_periph_driver/src/n32l40x_tim.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript b/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript index f8180cfb79..ad89d20dd6 100644 --- a/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript @@ -33,7 +33,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['n32l43x_std_periph_driver/src/n32l43x_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['n32l43x_std_periph_driver/src/n32l43x_tim.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript b/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript index ec1ac4502a..a8862b66ef 100644 --- a/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript +++ b/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript @@ -33,7 +33,7 @@ if GetDepend(['RT_USING_ADC']): if GetDepend(['RT_USING_DAC']): src += ['n32wb452_std_periph_driver/src/n32wb452_dac.c'] -if GetDepend(['RT_USING_HWTIMER']): +if GetDepend(['RT_USING_CLOCK_TIME']): src += ['n32wb452_std_periph_driver/src/n32wb452_tim.c'] if GetDepend(['RT_USING_RTC']): diff --git a/bsp/n32/libraries/n32_drivers/SConscript b/bsp/n32/libraries/n32_drivers/SConscript index 107e4d1b33..b97376e388 100644 --- a/bsp/n32/libraries/n32_drivers/SConscript +++ b/bsp/n32/libraries/n32_drivers/SConscript @@ -17,8 +17,8 @@ if GetDepend(['RT_USING_SERIAL']): else: src += ['drv_usart.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] diff --git a/bsp/n32/libraries/n32_drivers/drv_hwtimer.c b/bsp/n32/libraries/n32_drivers/drv_timer.c similarity index 66% rename from bsp/n32/libraries/n32_drivers/drv_hwtimer.c rename to bsp/n32/libraries/n32_drivers/drv_timer.c index 575f994490..890fd9cd78 100644 --- a/bsp/n32/libraries/n32_drivers/drv_hwtimer.c +++ b/bsp/n32/libraries/n32_drivers/drv_timer.c @@ -8,17 +8,17 @@ * 2022-10-19 Nations first version */ -#include "drv_hwtimer.h" +#include "drv_timer.h" -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME -#if defined(BSP_USING_HWTIMER1) || defined(BSP_USING_HWTIMER2) || defined(BSP_USING_HWTIMER3) || \ - defined(BSP_USING_HWTIMER4) || defined(BSP_USING_HWTIMER5) || defined(BSP_USING_HWTIMER6) || \ - defined(BSP_USING_HWTIMER7) || defined(BSP_USING_HWTIMER8) || defined(BSP_USING_HWTIMER9) +#if defined(BSP_USING_CLOCK_TIMER1) || defined(BSP_USING_CLOCK_TIMER2) || defined(BSP_USING_CLOCK_TIMER3) || \ + defined(BSP_USING_CLOCK_TIMER4) || defined(BSP_USING_CLOCK_TIMER5) || defined(BSP_USING_CLOCK_TIMER6) || \ + defined(BSP_USING_CLOCK_TIMER7) || defined(BSP_USING_CLOCK_TIMER8) || defined(BSP_USING_CLOCK_TIMER9) -static struct n32_hwtimer_config hwtimer_config[] = +static struct n32_clock_timer_config clock_timer_config[] = { -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 { "timer1", TIM1, @@ -26,7 +26,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 { "timer2", TIM2, @@ -34,7 +34,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 { "timer3", TIM3, @@ -42,7 +42,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 { "timer4", TIM4, @@ -50,7 +50,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 { "timer5", TIM5, @@ -58,7 +58,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 { "timer6", TIM6, @@ -66,7 +66,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 { "timer7", TIM7, @@ -74,7 +74,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER8 +#ifdef BSP_USING_CLOCK_TIMER8 { "timer8", TIM8, @@ -82,7 +82,7 @@ static struct n32_hwtimer_config hwtimer_config[] = }, #endif -#ifdef BSP_USING_HWTIMER9 +#ifdef BSP_USING_CLOCK_TIMER9 { "timer9", TIM9, @@ -100,47 +100,47 @@ static void caculate_tim_count() { uint8_t count = 0; -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 tim1_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 tim2_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 tim3_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 tim4_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 tim5_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 tim6_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 tim7_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER8 +#ifdef BSP_USING_CLOCK_TIMER8 tim8_count = count; count++; #endif -#ifdef BSP_USING_HWTIMER9 +#ifdef BSP_USING_CLOCK_TIMER9 tim9_count = count; count++; #endif @@ -149,22 +149,22 @@ static void caculate_tim_count() #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) -static struct n32_hwtimer hwtimer_obj[sizeof(hwtimer_config) / sizeof(hwtimer_config[0])] = {0}; +static struct n32_clock_timer clock_timer_obj[sizeof(clock_timer_config) / sizeof(clock_timer_config[0])] = {0}; -static rt_err_t n32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t n32_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; - struct n32_hwtimer_config *config; + struct n32_clock_timer_config *config; RCC_ClocksType RCC_ClockFreq; RT_ASSERT(timer != RT_NULL); - config = (struct n32_hwtimer_config *)timer->parent.user_data; + config = (struct n32_clock_timer_config *)timer->parent.user_data; RCC_GetClocksFreqValue(&RCC_ClockFreq); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint8_t clkpre; @@ -188,7 +188,7 @@ static rt_err_t n32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void * config->timer_periph->EVTGEN |= TIM_EVTGEN_UDGN; } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIM_Enable(config->timer_periph, DISABLE); break; default: @@ -198,13 +198,13 @@ static rt_err_t n32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void * return err; } -static rt_uint32_t n32_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t n32_clock_timer_count_get(rt_clock_timer_t *timer) { rt_uint32_t CurrentTimer_Count; - struct n32_hwtimer_config *config; + struct n32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct n32_hwtimer_config *)timer->parent.user_data; + config = (struct n32_clock_timer_config *)timer->parent.user_data; CurrentTimer_Count = TIM_GetCnt(config->timer_periph); @@ -232,13 +232,13 @@ void TIM_NVIC_Config(IRQn_Type IRQn, uint8_t PreemptionPriority, uint8_t SubPrio } -static void n32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void n32_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { - struct n32_hwtimer_config *config; + struct n32_clock_timer_config *config; TIM_TimeBaseInitType TIM_TimeBaseStructure; RCC_ClocksType RCC_ClockFreq; RT_ASSERT(timer != RT_NULL); - config = (struct n32_hwtimer_config *)timer->parent.user_data; + config = (struct n32_clock_timer_config *)timer->parent.user_data; if (state == 1) { @@ -272,7 +272,7 @@ static void n32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; TIM_TimeBaseStructure.RepetCnt = 0; - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; } @@ -294,18 +294,18 @@ static void n32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t n32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t n32_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - struct n32_hwtimer_config *config; + struct n32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct n32_hwtimer_config *)timer->parent.user_data; + config = (struct n32_clock_timer_config *)timer->parent.user_data; /* set tim cnt */ TIM_SetCnt(config->timer_periph, 0); /* set tim arr */ TIM_SetAutoReload(config->timer_periph, cnt - 1); - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { TIM_SelectOnePulseMode(config->timer_periph, TIM_OPMODE_SINGLE); } @@ -324,32 +324,32 @@ static rt_err_t n32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim return RT_EOK; } -static void n32_hwtimer_stop(rt_hwtimer_t *timer) +static void n32_clock_timer_stop(rt_clock_timer_t *timer) { - struct n32_hwtimer_config *config; + struct n32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct n32_hwtimer_config *)timer->parent.user_data; + config = (struct n32_clock_timer_config *)timer->parent.user_data; TIM_Enable(config->timer_periph, DISABLE); TIM_NVIC_Config(config->irqn, 3, 0, DISABLE); } -static const struct rt_hwtimer_ops n32_hwtimer_ops = +static const struct rt_clock_timer_ops n32_clock_timer_ops = { - .init = n32_hwtimer_init, - .start = n32_hwtimer_start, - .stop = n32_hwtimer_stop, - .count_get = n32_hwtimer_count_get, - .control = n32_hwtimer_control, + .init = n32_clock_timer_init, + .start = n32_clock_timer_start, + .stop = n32_clock_timer_stop, + .count_get = n32_clock_timer_count_get, + .control = n32_clock_timer_control, }; -static const struct rt_hwtimer_info n32_hwtimer_info = +static const struct rt_clock_timer_info n32_clock_timer_info = { 1000000, /* the maximum count frequency can be set */ 2000, /* the minimum count frequency can be set */ 0xFFFF, - HWTIMER_CNTMODE_UP, + CLOCK_TIMER_CNTMODE_UP, }; /** @@ -425,187 +425,187 @@ void TIM_IRQHandler(TIM_Module* timer_periph) } } -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 void TIM1_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim1_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim1_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim1_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim1_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 void TIM2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim2_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim2_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim2_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim2_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 void TIM3_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim3_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim3_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim3_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim3_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 void TIM4_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim4_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim4_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim4_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim4_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 void TIM5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim5_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim5_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim5_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim5_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 void TIM6_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim6_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim6_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim6_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim6_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 void TIM7_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim7_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim7_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim7_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim7_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER8 +#ifdef BSP_USING_CLOCK_TIMER8 void TIM8_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim8_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim8_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim8_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim8_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_HWTIMER9 +#ifdef BSP_USING_CLOCK_TIMER9 void TIM9_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - TIM_ClrIntPendingBit(hwtimer_obj[tim9_count].config->timer_periph, TIM_INT_UPDATE); - rt_device_hwtimer_isr(&hwtimer_obj[tim9_count].time_device); + TIM_ClrIntPendingBit(clock_timer_obj[tim9_count].config->timer_periph, TIM_INT_UPDATE); + rt_clock_timer_isr(&clock_timer_obj[tim9_count].time_device); /* leave interrupt */ rt_interrupt_leave(); } #endif -int rt_hwtimer_init(void) +int rt_clock_timer_init(void) { int i = 0; int result = RT_EOK; -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE); #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE); #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE); #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM4, ENABLE); #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM5, ENABLE); #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM6, ENABLE); #endif -#ifdef BSP_USING_HWTIMER7 +#ifdef BSP_USING_CLOCK_TIMER7 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM7, ENABLE); #endif -#ifdef BSP_USING_HWTIMER8 +#ifdef BSP_USING_CLOCK_TIMER8 RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM8, ENABLE); #endif -#ifdef BSP_USING_HWTIMER9 +#ifdef BSP_USING_CLOCK_TIMER9 RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM9, ENABLE); #endif caculate_tim_count(); - for (i = 0; i < sizeof(hwtimer_obj) / sizeof(hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(clock_timer_obj) / sizeof(clock_timer_obj[0]); i++) { - hwtimer_obj[i].time_device.info = &n32_hwtimer_info; - hwtimer_obj[i].time_device.ops = &n32_hwtimer_ops; - hwtimer_obj[i].config = &hwtimer_config[i]; - rt_device_hwtimer_register(&hwtimer_obj[i].time_device, \ - hwtimer_obj[i].config->name, hwtimer_obj[i].config); + clock_timer_obj[i].time_device.info = &n32_clock_timer_info; + clock_timer_obj[i].time_device.ops = &n32_clock_timer_ops; + clock_timer_obj[i].config = &clock_timer_config[i]; + rt_clock_timer_register(&clock_timer_obj[i].time_device, \ + clock_timer_obj[i].config->name, clock_timer_obj[i].config); } return result; } -INIT_DEVICE_EXPORT(rt_hwtimer_init); +INIT_DEVICE_EXPORT(rt_clock_timer_init); -#endif /* defined(BSP_USING_HWTIMERx) */ -#endif /* RT_USING_HWTIMER */ +#endif /* defined(BSP_USING_CLOCK_TIMERx) */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/n32/libraries/n32_drivers/drv_hwtimer.h b/bsp/n32/libraries/n32_drivers/drv_timer.h similarity index 64% rename from bsp/n32/libraries/n32_drivers/drv_hwtimer.h rename to bsp/n32/libraries/n32_drivers/drv_timer.h index ee1368ae36..c0cf897682 100644 --- a/bsp/n32/libraries/n32_drivers/drv_hwtimer.h +++ b/bsp/n32/libraries/n32_drivers/drv_timer.h @@ -8,8 +8,8 @@ * 2022-10-19 Nations first version */ -#ifndef __DRV_HWTIMER__ -#define __DRV_HWTIMER__ +#ifndef __DRV_CLOCK_TIMER__ +#define __DRV_CLOCK_TIMER__ #include #include @@ -21,23 +21,23 @@ extern "C" { #endif /* n32 config class */ -struct n32_hwtimer_config +struct n32_clock_timer_config { const char *name; TIM_Module* timer_periph; IRQn_Type irqn; }; -struct n32_hwtimer +struct n32_clock_timer { - rt_hwtimer_t time_device; - struct n32_hwtimer_config *config; + rt_clock_timer_t time_device; + struct n32_clock_timer_config *config; }; -int rt_hwtimer_init(void); +int rt_clock_timer_init(void); #ifdef __cplusplus } #endif -#endif /* __DRV_HWTIMER__ */ +#endif /* __DRV_CLOCK_TIMER__ */ diff --git a/bsp/n32/n32g43xcl-stb/README.md b/bsp/n32/n32g43xcl-stb/README.md index ba8b0db849..9e389606a2 100644 --- a/bsp/n32/n32g43xcl-stb/README.md +++ b/bsp/n32/n32g43xcl-stb/README.md @@ -45,7 +45,7 @@ N32G43XCL_STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC | | CAN | 支持 | CAN | | DAC | 支持 | DAC | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32g43xcl-stb/board/Kconfig b/bsp/n32/n32g43xcl-stb/board/Kconfig index a5bfedd61c..cf2a42fedd 100644 --- a/bsp/n32/n32g43xcl-stb/board/Kconfig +++ b/bsp/n32/n32g43xcl-stb/board/Kconfig @@ -107,45 +107,45 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n - config BSP_USING_HWTIMER9 - bool "using hwtimer9" + config BSP_USING_CLOCK_TIMER9 + bool "using clock_timer9" default n endif diff --git a/bsp/n32/n32g43xcl-stb/project.ewp b/bsp/n32/n32g43xcl-stb/project.ewp index 84925d44d1..9a4a86e020 100644 --- a/bsp/n32/n32g43xcl-stb/project.ewp +++ b/bsp/n32/n32g43xcl-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g43xcl-stb/project.uvprojx b/bsp/n32/n32g43xcl-stb/project.uvprojx index 8d75374a6f..8c33d032b7 100644 --- a/bsp/n32/n32g43xcl-stb/project.uvprojx +++ b/bsp/n32/n32g43xcl-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32g457qel-stb/README.md b/bsp/n32/n32g457qel-stb/README.md index f6e0822793..a64e39d489 100644 --- a/bsp/n32/n32g457qel-stb/README.md +++ b/bsp/n32/n32g457qel-stb/README.md @@ -45,7 +45,7 @@ N32G457QEL-STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC1/2/3/4 | | CAN | 支持 | CAN1/2 | | DAC | 支持 | DAC2, DAC1由于与音频芯片直连，工作会受到影响 | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32g457qel-stb/board/Kconfig b/bsp/n32/n32g457qel-stb/board/Kconfig index 2e186f1a74..ea112b3c23 100644 --- a/bsp/n32/n32g457qel-stb/board/Kconfig +++ b/bsp/n32/n32g457qel-stb/board/Kconfig @@ -114,34 +114,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32g457qel-stb/project.ewp b/bsp/n32/n32g457qel-stb/project.ewp index bd8690c050..8f1108bf10 100644 --- a/bsp/n32/n32g457qel-stb/project.ewp +++ b/bsp/n32/n32g457qel-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g457qel-stb/project.uvprojx b/bsp/n32/n32g457qel-stb/project.uvprojx index b994bc1107..6075cab541 100644 --- a/bsp/n32/n32g457qel-stb/project.uvprojx +++ b/bsp/n32/n32g457qel-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32g45xcl-stb/README.md b/bsp/n32/n32g45xcl-stb/README.md index ca50472b84..6138e07cb5 100644 --- a/bsp/n32/n32g45xcl-stb/README.md +++ b/bsp/n32/n32g45xcl-stb/README.md @@ -45,7 +45,7 @@ N32G45XCL-STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC1/2/3/4 | | CAN | 支持 | CAN1/2 | | DAC | 支持 | DAC1/2 | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32g45xcl-stb/board/Kconfig b/bsp/n32/n32g45xcl-stb/board/Kconfig index ac08b2c594..b7034deff0 100644 --- a/bsp/n32/n32g45xcl-stb/board/Kconfig +++ b/bsp/n32/n32g45xcl-stb/board/Kconfig @@ -114,34 +114,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32g45xcl-stb/project.ewp b/bsp/n32/n32g45xcl-stb/project.ewp index c6ed49af2a..8e9be79e66 100644 --- a/bsp/n32/n32g45xcl-stb/project.ewp +++ b/bsp/n32/n32g45xcl-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g45xcl-stb/project.uvprojx b/bsp/n32/n32g45xcl-stb/project.uvprojx index 2f9e8d6359..7d8841a62e 100644 --- a/bsp/n32/n32g45xcl-stb/project.uvprojx +++ b/bsp/n32/n32g45xcl-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32g45xml-stb/README.md b/bsp/n32/n32g45xml-stb/README.md index 50409930a8..a05199f0b4 100644 --- a/bsp/n32/n32g45xml-stb/README.md +++ b/bsp/n32/n32g45xml-stb/README.md @@ -45,7 +45,7 @@ N32G45XML-STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC1/2/3/4 | | CAN | 支持 | CAN1/2 | | DAC | 支持 | DAC1/2 | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32g45xml-stb/board/Kconfig b/bsp/n32/n32g45xml-stb/board/Kconfig index 2e186f1a74..ea112b3c23 100644 --- a/bsp/n32/n32g45xml-stb/board/Kconfig +++ b/bsp/n32/n32g45xml-stb/board/Kconfig @@ -114,34 +114,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32g45xml-stb/project.ewp b/bsp/n32/n32g45xml-stb/project.ewp index e78f902eaa..6f05d12e06 100644 --- a/bsp/n32/n32g45xml-stb/project.ewp +++ b/bsp/n32/n32g45xml-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g45xml-stb/project.uvprojx b/bsp/n32/n32g45xml-stb/project.uvprojx index 7db04a3fce..4bbb30d611 100644 --- a/bsp/n32/n32g45xml-stb/project.uvprojx +++ b/bsp/n32/n32g45xml-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32g45xrl-stb/README.md b/bsp/n32/n32g45xrl-stb/README.md index 1c1f77eef0..831d609496 100644 --- a/bsp/n32/n32g45xrl-stb/README.md +++ b/bsp/n32/n32g45xrl-stb/README.md @@ -45,7 +45,7 @@ N32G45XRL-STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC1/2/3/4 | | CAN | 支持 | CAN1/2 | | DAC | 支持 | DAC1/2 | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32g45xrl-stb/board/Kconfig b/bsp/n32/n32g45xrl-stb/board/Kconfig index 2e186f1a74..ea112b3c23 100644 --- a/bsp/n32/n32g45xrl-stb/board/Kconfig +++ b/bsp/n32/n32g45xrl-stb/board/Kconfig @@ -114,34 +114,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32g45xrl-stb/project.ewp b/bsp/n32/n32g45xrl-stb/project.ewp index df8713d347..1a898830f0 100644 --- a/bsp/n32/n32g45xrl-stb/project.ewp +++ b/bsp/n32/n32g45xrl-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g45xrl-stb/project.uvprojx b/bsp/n32/n32g45xrl-stb/project.uvprojx index d2d6148d78..33efa7b75e 100644 --- a/bsp/n32/n32g45xrl-stb/project.uvprojx +++ b/bsp/n32/n32g45xrl-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32g45xvl-stb/README.md b/bsp/n32/n32g45xvl-stb/README.md index d588ffe423..f481a953cd 100644 --- a/bsp/n32/n32g45xvl-stb/README.md +++ b/bsp/n32/n32g45xvl-stb/README.md @@ -45,7 +45,7 @@ N32G45XVL-STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC1/2/3/4 | | CAN | 支持 | CAN1/2 | | DAC | 支持 | DAC1/2 | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | | WDT | 支持 | IWDG | ### IO在板级支持包中的映射情况 diff --git a/bsp/n32/n32g45xvl-stb/board/Kconfig b/bsp/n32/n32g45xvl-stb/board/Kconfig index 5df1f9fc3a..51047d9b4b 100644 --- a/bsp/n32/n32g45xvl-stb/board/Kconfig +++ b/bsp/n32/n32g45xvl-stb/board/Kconfig @@ -447,34 +447,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32g45xvl-stb/project.ewp b/bsp/n32/n32g45xvl-stb/project.ewp index 137f9ff1c6..60d65cbb1e 100644 --- a/bsp/n32/n32g45xvl-stb/project.ewp +++ b/bsp/n32/n32g45xvl-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g45xvl-stb/project.uvprojx b/bsp/n32/n32g45xvl-stb/project.uvprojx index b4310ee0ae..3d12e6f4b9 100644 --- a/bsp/n32/n32g45xvl-stb/project.uvprojx +++ b/bsp/n32/n32g45xvl-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32g4frml-stb/board/Kconfig b/bsp/n32/n32g4frml-stb/board/Kconfig index 16351ea7e1..f2c09867d6 100644 --- a/bsp/n32/n32g4frml-stb/board/Kconfig +++ b/bsp/n32/n32g4frml-stb/board/Kconfig @@ -114,34 +114,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32g4frml-stb/project.ewp b/bsp/n32/n32g4frml-stb/project.ewp index 3b515c59cc..96ebc11b67 100644 --- a/bsp/n32/n32g4frml-stb/project.ewp +++ b/bsp/n32/n32g4frml-stb/project.ewp @@ -2213,7 +2213,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2297,7 +2297,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32g4frml-stb/project.uvprojx b/bsp/n32/n32g4frml-stb/project.uvprojx index 6008458b4a..f116d801f8 100644 --- a/bsp/n32/n32g4frml-stb/project.uvprojx +++ b/bsp/n32/n32g4frml-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32l40xcl-stb/README.md b/bsp/n32/n32l40xcl-stb/README.md index c25ba9b192..f1155c24e0 100644 --- a/bsp/n32/n32l40xcl-stb/README.md +++ b/bsp/n32/n32l40xcl-stb/README.md @@ -45,7 +45,7 @@ N32L40XCL_STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC | | CAN | 支持 | CAN | | DAC | 支持 | DAC | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32l40xcl-stb/board/Kconfig b/bsp/n32/n32l40xcl-stb/board/Kconfig index 4303b8e4ad..be6846a115 100644 --- a/bsp/n32/n32l40xcl-stb/board/Kconfig +++ b/bsp/n32/n32l40xcl-stb/board/Kconfig @@ -107,45 +107,45 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n - config BSP_USING_HWTIMER9 - bool "using hwtimer9" + config BSP_USING_CLOCK_TIMER9 + bool "using clock_timer9" default n endif diff --git a/bsp/n32/n32l40xcl-stb/project.ewp b/bsp/n32/n32l40xcl-stb/project.ewp index 8343f097f3..74de3b8931 100644 --- a/bsp/n32/n32l40xcl-stb/project.ewp +++ b/bsp/n32/n32l40xcl-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32l40xcl-stb/project.uvprojx b/bsp/n32/n32l40xcl-stb/project.uvprojx index 82add6e608..b984ba461b 100644 --- a/bsp/n32/n32l40xcl-stb/project.uvprojx +++ b/bsp/n32/n32l40xcl-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32l436-evb/README.md b/bsp/n32/n32l436-evb/README.md index 2b08341298..24e33e568b 100644 --- a/bsp/n32/n32l436-evb/README.md +++ b/bsp/n32/n32l436-evb/README.md @@ -45,7 +45,7 @@ N32L436_EVB 板级包支持MDK5开发环境和GCC编译器，以下是具体版 | ADC | 支持 | ADC | | CAN | 支持 | CAN | | DAC | 支持 | DAC | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32l436-evb/board/Kconfig b/bsp/n32/n32l436-evb/board/Kconfig index 5e3fe2a39e..312cd4e7df 100644 --- a/bsp/n32/n32l436-evb/board/Kconfig +++ b/bsp/n32/n32l436-evb/board/Kconfig @@ -107,45 +107,45 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n - config BSP_USING_HWTIMER9 - bool "using hwtimer9" + config BSP_USING_CLOCK_TIMER9 + bool "using clock_timer9" default n endif diff --git a/bsp/n32/n32l436-evb/project.ewp b/bsp/n32/n32l436-evb/project.ewp index b53987f97e..b364f0ffdc 100644 --- a/bsp/n32/n32l436-evb/project.ewp +++ b/bsp/n32/n32l436-evb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32l436-evb/project.uvprojx b/bsp/n32/n32l436-evb/project.uvprojx index 81d22ed3a0..31d96d5ffb 100644 --- a/bsp/n32/n32l436-evb/project.uvprojx +++ b/bsp/n32/n32l436-evb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32l43xml-stb/README.md b/bsp/n32/n32l43xml-stb/README.md index 72a277aca9..66d8571946 100644 --- a/bsp/n32/n32l43xml-stb/README.md +++ b/bsp/n32/n32l43xml-stb/README.md @@ -45,7 +45,7 @@ N32L43XML_STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC | | CAN | 支持 | CAN | | DAC | 支持 | DAC | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32l43xml-stb/board/Kconfig b/bsp/n32/n32l43xml-stb/board/Kconfig index 5e3fe2a39e..312cd4e7df 100644 --- a/bsp/n32/n32l43xml-stb/board/Kconfig +++ b/bsp/n32/n32l43xml-stb/board/Kconfig @@ -107,45 +107,45 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n - config BSP_USING_HWTIMER9 - bool "using hwtimer9" + config BSP_USING_CLOCK_TIMER9 + bool "using clock_timer9" default n endif diff --git a/bsp/n32/n32l43xml-stb/project.ewp b/bsp/n32/n32l43xml-stb/project.ewp index 7cd39f1f14..6b37926739 100644 --- a/bsp/n32/n32l43xml-stb/project.ewp +++ b/bsp/n32/n32l43xml-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32l43xml-stb/project.uvprojx b/bsp/n32/n32l43xml-stb/project.uvprojx index d378a75008..cbb0d71431 100644 --- a/bsp/n32/n32l43xml-stb/project.uvprojx +++ b/bsp/n32/n32l43xml-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32l43xrl-stb/README.md b/bsp/n32/n32l43xrl-stb/README.md index 798096604f..0faccdd241 100644 --- a/bsp/n32/n32l43xrl-stb/README.md +++ b/bsp/n32/n32l43xrl-stb/README.md @@ -45,7 +45,7 @@ N32L43XRL_STB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC | | CAN | 支持 | CAN | | DAC | 支持 | DAC | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8/9 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32l43xrl-stb/board/Kconfig b/bsp/n32/n32l43xrl-stb/board/Kconfig index 5e3fe2a39e..312cd4e7df 100644 --- a/bsp/n32/n32l43xrl-stb/board/Kconfig +++ b/bsp/n32/n32l43xrl-stb/board/Kconfig @@ -107,45 +107,45 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n - config BSP_USING_HWTIMER9 - bool "using hwtimer9" + config BSP_USING_CLOCK_TIMER9 + bool "using clock_timer9" default n endif diff --git a/bsp/n32/n32l43xrl-stb/project.ewp b/bsp/n32/n32l43xrl-stb/project.ewp index 7404ec4b8c..c0cb073932 100644 --- a/bsp/n32/n32l43xrl-stb/project.ewp +++ b/bsp/n32/n32l43xrl-stb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32l43xrl-stb/project.uvprojx b/bsp/n32/n32l43xrl-stb/project.uvprojx index 2a9cd0823c..3b5c38167a 100644 --- a/bsp/n32/n32l43xrl-stb/project.uvprojx +++ b/bsp/n32/n32l43xrl-stb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32/n32wb45xl-evb/README.md b/bsp/n32/n32wb45xl-evb/README.md index 3f490f08d4..e549e50999 100644 --- a/bsp/n32/n32wb45xl-evb/README.md +++ b/bsp/n32/n32wb45xl-evb/README.md @@ -45,7 +45,7 @@ N32WB45XL_EVB 板级包支持MDK5开发环境和GCC编译器，以下是具体 | ADC | 支持 | ADC1/2 | | CAN | 支持 | CAN1/2 | | DAC | 支持 | DAC1/2 | -| HWTIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | +| CLOCK_TIMER | 支持 | TIMER1/2/3/4/5/6/7/8 | | WDT | 支持 | IWDG | | RTC | 支持 | 时钟源支持LSE/LSI/HSE | diff --git a/bsp/n32/n32wb45xl-evb/board/Kconfig b/bsp/n32/n32wb45xl-evb/board/Kconfig index 0610640dc4..5da0bd4a40 100644 --- a/bsp/n32/n32wb45xl-evb/board/Kconfig +++ b/bsp/n32/n32wb45xl-evb/board/Kconfig @@ -114,34 +114,34 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - bool "Enable hwtimer" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable clock_timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER1 - bool "using hwtimer1" + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER1 + bool "using clock_timer1" default n - config BSP_USING_HWTIMER2 - bool "using hwtimer2" + config BSP_USING_CLOCK_TIMER2 + bool "using clock_timer2" default n - config BSP_USING_HWTIMER3 - bool "using hwtimer3" + config BSP_USING_CLOCK_TIMER3 + bool "using clock_timer3" default n - config BSP_USING_HWTIMER4 - bool "using hwtimer4" + config BSP_USING_CLOCK_TIMER4 + bool "using clock_timer4" default n - config BSP_USING_HWTIMER5 - bool "using hwtimer5" + config BSP_USING_CLOCK_TIMER5 + bool "using clock_timer5" default n - config BSP_USING_HWTIMER6 - bool "using hwtimer6" + config BSP_USING_CLOCK_TIMER6 + bool "using clock_timer6" default n - config BSP_USING_HWTIMER7 - bool "using hwtimer7" + config BSP_USING_CLOCK_TIMER7 + bool "using clock_timer7" default n - config BSP_USING_HWTIMER8 - bool "using hwtimer8" + config BSP_USING_CLOCK_TIMER8 + bool "using clock_timer8" default n endif diff --git a/bsp/n32/n32wb45xl-evb/project.ewp b/bsp/n32/n32wb45xl-evb/project.ewp index da3f4ce8db..cf5e798397 100644 --- a/bsp/n32/n32wb45xl-evb/project.ewp +++ b/bsp/n32/n32wb45xl-evb/project.ewp @@ -2237,7 +2237,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -2321,7 +2321,7 @@ $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - $PROJ_DIR$\..\libraries\n32_drivers\drv_hwtimer.c + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c diff --git a/bsp/n32/n32wb45xl-evb/project.uvprojx b/bsp/n32/n32wb45xl-evb/project.uvprojx index 61d4ee2eb9..e1ba0c9ebf 100644 --- a/bsp/n32/n32wb45xl-evb/project.uvprojx +++ b/bsp/n32/n32wb45xl-evb/project.uvprojx @@ -488,9 +488,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c @@ -932,9 +932,9 @@ - drv_hwtimer.c + drv_timer.c 1 - ..\libraries\n32_drivers\drv_hwtimer.c + ..\libraries\n32_drivers\drv_timer.c diff --git a/bsp/n32g452xx/Libraries/rt_drivers/SConscript b/bsp/n32g452xx/Libraries/rt_drivers/SConscript index b082134ed4..cf9e595798 100755 --- a/bsp/n32g452xx/Libraries/rt_drivers/SConscript +++ b/bsp/n32g452xx/Libraries/rt_drivers/SConscript @@ -24,8 +24,8 @@ if GetDepend(['BSP_USING_UART']): if GetDepend(['BSP_USING_PWM']): src += ['drv_pwm.c'] -if GetDepend(['BSP_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['BSP_USING_CLOCK_TIMER']): + src += ['drv_timer.c'] if GetDepend(['BSP_USING_SPI']): src += ['drv_spi.c'] diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_timer.c similarity index 77% rename from bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c rename to bsp/n32g452xx/Libraries/rt_drivers/drv_timer.c index 65c05ce702..67bc044625 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_timer.c @@ -9,13 +9,13 @@ */ #include -#include "drv_hwtimer.h" +#include "drv_timer.h" #define DRV_DEBUG -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER enum { #ifdef BSP_USING_HWTIM1 @@ -51,15 +51,15 @@ enum #endif }; -struct n32_hwtimer +struct n32_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; TIM_Module *tim_handle; IRQn_Type tim_irqn; char *name; }; -static struct n32_hwtimer n32_hwtimer_obj[] = +static struct n32_clock_timer n32_clock_timer_obj[] = { #ifdef BSP_USING_HWTIM1 TIM1_CONFIG, @@ -94,7 +94,7 @@ static struct n32_hwtimer n32_hwtimer_obj[] = #endif }; -static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void n32_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { RCC_ClocksType RCC_ClockStruct; TIM_TimeBaseInitType TIM_TimeBaseStructure; @@ -103,13 +103,13 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) uint32_t input_clock; uint32_t prescaler_value = 0; TIM_Module *tim = RT_NULL; - struct n32_hwtimer *tim_device = RT_NULL; + struct n32_clock_timer *tim_device = RT_NULL; RT_ASSERT(timer != RT_NULL); if (state) { tim = (TIM_Module *)timer->parent.user_data; - tim_device = (struct n32_hwtimer *)timer; + tim_device = (struct n32_clock_timer *)timer; RT_ASSERT((tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM6) || (tim == TIM7)); @@ -130,7 +130,7 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; TIM_TimeBaseStructure.RepetCnt = 0; - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { TIM_TimeBaseStructure.CntMode = TIM_CNT_MODE_UP; } @@ -155,7 +155,7 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t n32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t n32_timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; TIM_Module *tim = RT_NULL; @@ -168,7 +168,7 @@ static rt_err_t n32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_m TIM_SetCnt(tim, 0); /* set tim arr */ TIM_SetAutoReload(tim, t - 1); - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ TIM_SelectOnePulseMode(tim, TIM_OPMODE_SINGLE); @@ -184,7 +184,7 @@ static rt_err_t n32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_m return result; } -static void n32_timer_stop(rt_hwtimer_t *timer) +static void n32_timer_stop(rt_clock_timer_t *timer) { TIM_Module *tim = RT_NULL; @@ -198,7 +198,7 @@ static void n32_timer_stop(rt_hwtimer_t *timer) TIM_SetCnt(tim, 0); } -static rt_uint32_t n32_timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t n32_timer_counter_get(rt_clock_timer_t *timer) { TIM_Module *tim = RT_NULL; @@ -209,7 +209,7 @@ static rt_uint32_t n32_timer_counter_get(rt_hwtimer_t *timer) return tim->CNT; } -static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t n32_timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { RCC_ClocksType RCC_ClockStruct; TIM_Module *tim = RT_NULL; @@ -222,7 +222,7 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t input_clock; rt_uint32_t freq; @@ -251,8 +251,8 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_ops _ops = { .init = n32_timer_init, .start = n32_timer_start, @@ -270,7 +270,7 @@ void TIM2_IRQHandler(void) if (TIM_GetIntStatus(TIM2, TIM_INT_UPDATE) == SET) { - rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM2_INDEX].time_device); + rt_clock_timer_isr(&n32_clock_timer_obj[TIM2_INDEX].time_device); TIM_ClrIntPendingBit(TIM2, TIM_INT_UPDATE); } @@ -288,7 +288,7 @@ void TIM3_IRQHandler(void) if (TIM_GetIntStatus(TIM3, TIM_INT_UPDATE) == SET) { - rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM3_INDEX].time_device); + rt_clock_timer_isr(&n32_clock_timer_obj[TIM3_INDEX].time_device); TIM_ClrIntPendingBit(TIM3, TIM_INT_UPDATE); } @@ -306,7 +306,7 @@ void TIM4_IRQHandler(void) if (TIM_GetIntStatus(TIM4, TIM_INT_UPDATE) == SET) { - rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM4_INDEX].time_device); + rt_clock_timer_isr(&n32_clock_timer_obj[TIM4_INDEX].time_device); TIM_ClrIntPendingBit(TIM4, TIM_INT_UPDATE); } @@ -324,7 +324,7 @@ void TIM5_IRQHandler(void) if (TIM_GetIntStatus(TIM5, TIM_INT_UPDATE) == SET) { - rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM5_INDEX].time_device); + rt_clock_timer_isr(&n32_clock_timer_obj[TIM5_INDEX].time_device); TIM_ClrIntPendingBit(TIM5, TIM_INT_UPDATE); } @@ -342,7 +342,7 @@ void TIM6_IRQHandler(void) if (TIM_GetIntStatus(TIM6, TIM_INT_UPDATE) == SET) { - rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM6_INDEX].time_device); + rt_clock_timer_isr(&n32_clock_timer_obj[TIM6_INDEX].time_device); TIM_ClrIntPendingBit(TIM6, TIM_INT_UPDATE); } @@ -360,7 +360,7 @@ void TIM7_IRQHandler(void) if (TIM_GetIntStatus(TIM7, TIM_INT_UPDATE) == SET) { - rt_device_hwtimer_isr(&n32_hwtimer_obj[TIM7_INDEX].time_device); + rt_clock_timer_isr(&n32_clock_timer_obj[TIM7_INDEX].time_device); TIM_ClrIntPendingBit(TIM7, TIM_INT_UPDATE); } @@ -369,31 +369,31 @@ void TIM7_IRQHandler(void) } #endif -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(n32_hwtimer_obj) / sizeof(n32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(n32_clock_timer_obj) / sizeof(n32_clock_timer_obj[0]); i++) { - n32_hwtimer_obj[i].time_device.info = &_info; - n32_hwtimer_obj[i].time_device.ops = &_ops; - if (rt_device_hwtimer_register(&n32_hwtimer_obj[i].time_device, n32_hwtimer_obj[i].name, n32_hwtimer_obj[i].tim_handle) == RT_EOK) + n32_clock_timer_obj[i].time_device.info = &_info; + n32_clock_timer_obj[i].time_device.ops = &_ops; + if (rt_clock_timer_register(&n32_clock_timer_obj[i].time_device, n32_clock_timer_obj[i].name, n32_clock_timer_obj[i].tim_handle) == RT_EOK) { - LOG_D("%s register success", n32_hwtimer_obj[i].name); + LOG_D("%s register success", n32_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", n32_hwtimer_obj[i].name); + LOG_E("%s register failed", n32_clock_timer_obj[i].name); result = -RT_ERROR; } } return result; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_timer.h similarity index 96% rename from bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h rename to bsp/n32g452xx/Libraries/rt_drivers/drv_timer.h index 73647845e0..9258eec010 100644 --- a/bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h +++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_timer.h @@ -12,7 +12,7 @@ #define __TIM_CONFIG_H__ #include -#include +#include #ifdef __cplusplus extern "C" { @@ -24,7 +24,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 1000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/n32g452xx/n32g452xx-mini-system/README.md b/bsp/n32g452xx/n32g452xx-mini-system/README.md index 68bd5b3d7e..e1063e1a1b 100644 --- a/bsp/n32g452xx/n32g452xx-mini-system/README.md +++ b/bsp/n32g452xx/n32g452xx-mini-system/README.md @@ -37,7 +37,7 @@ N32G452 MINI-SYSTEM 板级包支持MDK5开发环境和GCC编译器，以下是 | GPIO | 支持(已移植，已测试) | PA0...PF7 | | ADC | 支持(已移植，已测试) | ADC1/2 | | PWM | 支持(已移植，已测试) | TMR1/2 | -| HWTIMER | 支持(已移植，已测试) | TMR6/7 | +| CLOCK_TIMER | 支持(已移植，已测试) | TMR6/7 | ### IO在板级支持包中的映射情况 diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig index 0f3cfab5e5..373a7d69e2 100755 --- a/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig @@ -304,11 +304,11 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_HWTIM3 bool "Enable hardware timer3" default n diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c index 35f17b6b41..56fe68cea7 100644 --- a/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c +++ b/bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c @@ -670,7 +670,7 @@ void n32_msp_adc_init(void *Instance) } #endif /* BSP_USING_ADC */ -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void n32_msp_hwtim_init(void *Instance) { TIM_Module *TIMx = (TIM_Module *)Instance; @@ -881,25 +881,25 @@ static int adc_vol_sample(int argc, char *argv[]) MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); #endif -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback fucntion!\n"); rt_kprintf("timer name is :%s.\n", dev->parent.name); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_init(const char *name) +static int clock_timer_init(const char *name) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; hw_dev = rt_device_find(name); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", name); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", name); return -RT_ERROR; } ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); @@ -909,8 +909,8 @@ static int hwtimer_init(const char *name) return ret; } rt_device_set_rx_indicate(hw_dev, timeout_cb); - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -932,17 +932,17 @@ static int hwtimer_init(const char *name) return ret; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { #ifdef BSP_USING_HWTIM6 - hwtimer_init("timer6"); + clock_timer_init("timer6"); #endif #ifdef BSP_USING_HWTIM7 - hwtimer_init("timer7"); + clock_timer_init("timer7"); #endif return RT_EOK; } -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); #endif #endif diff --git a/bsp/nrf5x/libraries/drivers/SConscript b/bsp/nrf5x/libraries/drivers/SConscript index 53987e54c8..f065f4994a 100644 --- a/bsp/nrf5x/libraries/drivers/SConscript +++ b/bsp/nrf5x/libraries/drivers/SConscript @@ -41,7 +41,7 @@ if GetDepend(['BSP_USING_ONCHIP_RTC']): src += ['drv_rtc.c'] if GetDepend(['BSP_USING_TIM']): - src += ['drv_hwtimer.c'] + src += ['drv_timer.c'] path = [cwd] diff --git a/bsp/nrf5x/libraries/drivers/drv_hwtimer.c b/bsp/nrf5x/libraries/drivers/drv_timer.c similarity index 80% rename from bsp/nrf5x/libraries/drivers/drv_hwtimer.c rename to bsp/nrf5x/libraries/drivers/drv_timer.c index 1e8d83f550..358cd4a13a 100644 --- a/bsp/nrf5x/libraries/drivers/drv_hwtimer.c +++ b/bsp/nrf5x/libraries/drivers/drv_timer.c @@ -20,11 +20,11 @@ #ifdef BSP_USING_TIM -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #define DBG_LVL DBG_INFO #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME #ifndef TIM_DEV_INFO_CONFIG /* maxfreq and minfreq unit is HZ */ @@ -33,7 +33,7 @@ .maxfreq = 16000000, \ .minfreq = 31250, \ .maxcnt = 0xFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif @@ -44,14 +44,14 @@ typedef struct nrf_timer_cc_channel_t cc_channel; }nrf5x_timer_info_t; -struct nrf5x_hwtimer +struct nrf5x_clock_timer { - rt_hwtimer_t timer_device; + rt_clock_timer_t timer_device; nrf5x_timer_info_t timer_info; char *name; }; -static struct nrf5x_hwtimer nrf5x_hwtimer_obj[] = +static struct nrf5x_clock_timer nrf5x_clock_timer_obj[] = { #ifdef BSP_USING_TIM0 { @@ -101,15 +101,15 @@ static struct nrf5x_hwtimer nrf5x_hwtimer_obj[] = static void timer_callback(nrf_timer_event_t event_type, void* p_context) { - rt_hwtimer_t *timer_device = (struct rt_hwtimer_device *)p_context; + rt_clock_timer_t *timer_device = (struct rt_clock_timer_device *)p_context; - /* no matter what event_type is(NRF_TIMER_EVENT_COMPARE0 or others), call same function "rt_device_hwtimer_isr" */ + /* no matter what event_type is(NRF_TIMER_EVENT_COMPARE0 or others), call same function "rt_clock_timer_isr" */ LOG_D("timer_callback event_type = %d, inst_id = %d, cc conunt = %d\r\n", event_type, timer_info->timer_inst.instance_id, timer_info->timer_inst.cc_channel_count); - rt_device_hwtimer_isr(timer_device); + rt_clock_timer_isr(timer_device); } -static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { nrf5x_timer_info_t *timer_info = RT_NULL; nrfx_timer_config_t *timer_cfg = RT_NULL; @@ -126,7 +126,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { nrf5x_timer_info_t *timer_info = RT_NULL; nrf_timer_short_mask_t mask = NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK; @@ -135,7 +135,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ timer_info = (nrf5x_timer_info_t *)timer->parent.user_data; - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* means TIMER_SHORTS_COMPARE0_STOP_Msk or TIMER_SHORTS_COMPARE1_STOP_Msk ..., according to cc_channel. */ mask = (nrf_timer_short_mask_t)(1 << (timer_info->cc_channel + 8)); @@ -151,7 +151,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ return RT_EOK; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { nrf5x_timer_info_t *timer_info = RT_NULL; @@ -233,7 +233,7 @@ static nrf_timer_frequency_t frequency_convert(rt_uint32_t freq) return frequency; } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { rt_err_t result = RT_EOK; nrf5x_timer_info_t *timer_info = RT_NULL; @@ -247,7 +247,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; /* set timer frequence */ @@ -267,7 +267,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { rt_uint32_t count = 0; nrf5x_timer_info_t *timer_info = RT_NULL; @@ -282,8 +282,8 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) return count; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -292,30 +292,30 @@ static const struct rt_hwtimer_ops _ops = .control = timer_ctrl, }; -static int nrf5x_hwtimer_init(void) +static int nrf5x_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(nrf5x_hwtimer_obj) / sizeof(nrf5x_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(nrf5x_clock_timer_obj) / sizeof(nrf5x_clock_timer_obj[0]); i++) { - nrf5x_hwtimer_obj[i].timer_device.info = &_info; - nrf5x_hwtimer_obj[i].timer_device.ops = &_ops; - if (rt_device_hwtimer_register(&nrf5x_hwtimer_obj[i].timer_device, nrf5x_hwtimer_obj[i].name, &nrf5x_hwtimer_obj[i].timer_info) == RT_EOK) + nrf5x_clock_timer_obj[i].timer_device.info = &_info; + nrf5x_clock_timer_obj[i].timer_device.ops = &_ops; + if (rt_clock_timer_register(&nrf5x_clock_timer_obj[i].timer_device, nrf5x_clock_timer_obj[i].name, &nrf5x_clock_timer_obj[i].timer_info) == RT_EOK) { - LOG_D("%s register success", nrf5x_hwtimer_obj[i].name); + LOG_D("%s register success", nrf5x_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", nrf5x_hwtimer_obj[i].name); + LOG_E("%s register failed", nrf5x_clock_timer_obj[i].name); result = -RT_ERROR; } } return result; } -INIT_BOARD_EXPORT(nrf5x_hwtimer_init); +INIT_BOARD_EXPORT(nrf5x_clock_timer_init); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ #endif /* BSP_USING_TIM */ diff --git a/bsp/nrf5x/nrf52832/board/Kconfig b/bsp/nrf5x/nrf52832/board/Kconfig index 261c5ff997..9b0e1dadfa 100644 --- a/bsp/nrf5x/nrf52832/board/Kconfig +++ b/bsp/nrf5x/nrf52832/board/Kconfig @@ -421,7 +421,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_TIM bool "Enable TIMER" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_TIM config NRFX_TIMER_ENABLED diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index 924db34a5e..9118680155 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -511,7 +511,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_TIM bool "Enable TIMER" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_TIM config NRFX_TIMER_ENABLED diff --git a/bsp/nrf5x/nrf5340/board/Kconfig b/bsp/nrf5x/nrf5340/board/Kconfig index eaf696c8ea..079395abe4 100644 --- a/bsp/nrf5x/nrf5340/board/Kconfig +++ b/bsp/nrf5x/nrf5340/board/Kconfig @@ -513,7 +513,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_TIM bool "Enable TIMER" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_TIM config NRFX_TIMER_ENABLED diff --git a/bsp/nuclei/gd32vf103_rvstar/README.md b/bsp/nuclei/gd32vf103_rvstar/README.md index 6e265d6729..545fae5c72 100644 --- a/bsp/nuclei/gd32vf103_rvstar/README.md +++ b/bsp/nuclei/gd32vf103_rvstar/README.md @@ -256,7 +256,7 @@ Breakpoint 1, irq_entry () at D:\workspace\Sourcecode\rt-thread\libcpu\risc-v\nu | GPIO | 支持 | 默认使能，支持中断控制 | | SPI | 支持 | 默认关闭 | | I2C | 支持 | 默认关闭 | -| HWTIMER | 支持 | 默认关闭 | +| CLOCK_TIMER | 支持 | 默认关闭 | | PWM | 支持 | 默认关闭 | | WDT | 支持 | 默认关闭 | | RTC | 支持 | 默认关闭 | @@ -300,7 +300,7 @@ gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); - 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。 - 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。 - GD32VF103的驱动适配开关在 `menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers` 可以找到。 -- HWTIMER和PWM都是采用的TIMER模块进行功能实现，所以在使用驱动时，请务必注意不要重叠使用相同模块。 +- CLOCK_TIMER和PWM都是采用的TIMER模块进行功能实现，所以在使用驱动时，请务必注意不要重叠使用相同模块。 ## 联系人信息 diff --git a/bsp/nuclei/gd32vf103_rvstar/board/Kconfig b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig index 2e90c8d681..4005486bbd 100644 --- a/bsp/nuclei/gd32vf103_rvstar/board/Kconfig +++ b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig @@ -68,30 +68,30 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER0 + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER0 bool "Enable TIMER0" default n - config BSP_USING_HWTIMER1 + config BSP_USING_CLOCK_TIMER1 bool "Enable TIMER1" default n - config BSP_USING_HWTIMER2 + config BSP_USING_CLOCK_TIMER2 bool "Enable TIMER2" default n - config BSP_USING_HWTIMER3 + config BSP_USING_CLOCK_TIMER3 bool "Enable TIMER3" default n - config BSP_USING_HWTIMER4 + config BSP_USING_CLOCK_TIMER4 bool "Enable TIMER4" default n - config BSP_USING_HWTIMER5 + config BSP_USING_CLOCK_TIMER5 bool "Enable TIMER5" default n - config BSP_USING_HWTIMER6 + config BSP_USING_CLOCK_TIMER6 bool "Enable TIMER6" default n endif diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.c b/bsp/nuclei/gd32vf103_rvstar/board/board.c index 3c0aaad171..054206bffd 100644 --- a/bsp/nuclei/gd32vf103_rvstar/board/board.c +++ b/bsp/nuclei/gd32vf103_rvstar/board/board.c @@ -37,7 +37,7 @@ extern void _init(void); /* * - Check MCU pin assignment here https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html * - If you changed menuconfig to use different peripherals such as SPI, ADC, GPIO, - * HWTIMER, I2C, PWM, UART, WDT, RTC, please add or change related pinmux configuration + * CLOCK_TIMER, I2C, PWM, UART, WDT, RTC, please add or change related pinmux configuration * code in functions(rt_hw_*_drvinit) below */ @@ -62,7 +62,7 @@ void rt_hw_gpio_drvinit(void) rcu_periph_clock_enable(RCU_AF); } -void rt_hw_hwtimer_drvinit(void) +void rt_hw_clock_timer_drvinit(void) { } @@ -116,8 +116,8 @@ void rt_hw_drivers_init(void) #ifdef BSP_USING_RTC rt_hw_rtc_drvinit(); #endif -#ifdef BSP_USING_HWTIMER - rt_hw_hwtimer_drvinit(); +#ifdef BSP_USING_CLOCK_TIMER + rt_hw_clock_timer_drvinit(); #endif #ifdef BSP_USING_PWM rt_hw_pwm_drvinit(); diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript index b9cdd5b795..ee3e2a3ea8 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript @@ -20,8 +20,8 @@ if GetDepend(['RT_USING_I2C']): if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_ADC']): src += ['drv_adc.c'] diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_timer.c similarity index 46% rename from bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.c rename to bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_timer.c index dd351ee146..1beb899437 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.c +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_timer.c @@ -8,61 +8,61 @@ * 2020-05-12 hqfang first version */ -#include "drv_hwtimer.h" +#include "drv_timer.h" -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#if !defined(BSP_USING_HWTIMER0) && !defined(BSP_USING_HWTIMER1) && !defined(BSP_USING_HWTIMER2) \ - && !defined(BSP_USING_HWTIMER3) && !defined(BSP_USING_HWTIMER4) - #error "Please define at least one BSP_USING_HWTIMERx" - /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable HWTIMER */ +#if !defined(BSP_USING_CLOCK_TIMER0) && !defined(BSP_USING_CLOCK_TIMER1) && !defined(BSP_USING_CLOCK_TIMER2) \ + && !defined(BSP_USING_CLOCK_TIMER3) && !defined(BSP_USING_CLOCK_TIMER4) + #error "Please define at least one BSP_USING_CLOCK_TIMERx" + /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable CLOCK_TIMER */ #endif -static struct gd32_hwtimer_config hwtimer_config[] = +static struct gd32_clock_timer_config clock_timer_config[] = { -#ifdef BSP_USING_HWTIMER0 +#ifdef BSP_USING_CLOCK_TIMER0 { "timer0", TIMER0, TIMER0_UP_IRQn, }, #endif -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 { "timer1", TIMER1, TIMER1_IRQn, }, #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 { "timer2", TIMER2, TIMER2_IRQn, }, #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 { "timer3", TIMER3, TIMER3_IRQn, }, #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 { "timer4", TIMER4, TIMER4_IRQn, }, #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 { "timer5", TIMER5, TIMER5_IRQn, }, #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 { "timer6", TIMER6, @@ -71,19 +71,19 @@ static struct gd32_hwtimer_config hwtimer_config[] = #endif }; -static struct gd32_hwtimer hwtimer_obj[sizeof(hwtimer_config) / sizeof(hwtimer_config[0])] = {0}; +static struct gd32_clock_timer clock_timer_obj[sizeof(clock_timer_config) / sizeof(clock_timer_config[0])] = {0}; -static rt_err_t gd32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t gd32_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; - struct gd32_hwtimer_config *config; + struct gd32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct gd32_hwtimer_config *)timer->parent.user_data; + config = (struct gd32_clock_timer_config *)timer->parent.user_data; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint8_t clkpre; @@ -106,7 +106,7 @@ static rt_err_t gd32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void TIMER_PSC(config->timer_periph) = (uint32_t)pre; } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: timer_disable(config->timer_periph); break; default: @@ -116,25 +116,25 @@ static rt_err_t gd32_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void return err; } -static rt_uint32_t gd32_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t gd32_clock_timer_count_get(rt_clock_timer_t *timer) { rt_uint32_t CurrentTimer_Count; - struct gd32_hwtimer_config *config; + struct gd32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct gd32_hwtimer_config *)timer->parent.user_data; + config = (struct gd32_clock_timer_config *)timer->parent.user_data; CurrentTimer_Count = timer_counter_read(config->timer_periph); return CurrentTimer_Count; } -static void gd32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void gd32_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { - struct gd32_hwtimer_config *config; + struct gd32_clock_timer_config *config; timer_parameter_struct initpara; RT_ASSERT(timer != RT_NULL); - config = (struct gd32_hwtimer_config *)timer->parent.user_data; + config = (struct gd32_clock_timer_config *)timer->parent.user_data; if (state == 1) { @@ -150,13 +150,13 @@ static void gd32_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t gd32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t gd32_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - struct gd32_hwtimer_config *config; + struct gd32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct gd32_hwtimer_config *)timer->parent.user_data; + config = (struct gd32_clock_timer_config *)timer->parent.user_data; - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { timer_single_pulse_mode_config(config->timer_periph, TIMER_SP_MODE_SINGLE); } @@ -173,143 +173,143 @@ static rt_err_t gd32_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwti return RT_EOK; } -static void gd32_hwtimer_stop(rt_hwtimer_t *timer) +static void gd32_clock_timer_stop(rt_clock_timer_t *timer) { - struct gd32_hwtimer_config *config; + struct gd32_clock_timer_config *config; RT_ASSERT(timer != RT_NULL); - config = (struct gd32_hwtimer_config *)timer->parent.user_data; + config = (struct gd32_clock_timer_config *)timer->parent.user_data; timer_disable(config->timer_periph); ECLIC_DisableIRQ(config->irqn); } -static const struct rt_hwtimer_ops gd32_hwtimer_ops = +static const struct rt_clock_timer_ops gd32_clock_timer_ops = { - .init = gd32_hwtimer_init, - .start = gd32_hwtimer_start, - .stop = gd32_hwtimer_stop, - .count_get = gd32_hwtimer_count_get, - .control = gd32_hwtimer_control, + .init = gd32_clock_timer_init, + .start = gd32_clock_timer_start, + .stop = gd32_clock_timer_stop, + .count_get = gd32_clock_timer_count_get, + .control = gd32_clock_timer_control, }; -static const struct rt_hwtimer_info gd32_hwtimer_info = +static const struct rt_clock_timer_info gd32_clock_timer_info = { 54000000, /* the maximum count frequency can be set */ 1000, /* the minimum count frequency can be set */ 0xFFFF, - HWTIMER_CNTMODE_UP, + CLOCK_TIMER_CNTMODE_UP, }; -#ifdef BSP_USING_HWTIMER0 +#ifdef BSP_USING_CLOCK_TIMER0 void TIMER0_UP_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[0].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[0].time_device); + timer_interrupt_flag_clear(clock_timer_obj[0].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[0].time_device); } #endif -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 void TIMER1_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[1].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[1].time_device); + timer_interrupt_flag_clear(clock_timer_obj[1].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[1].time_device); } #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 void TIMER2_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[2].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[2].time_device); + timer_interrupt_flag_clear(clock_timer_obj[2].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[2].time_device); } #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 void TIMER3_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[3].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[3].time_device); + timer_interrupt_flag_clear(clock_timer_obj[3].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[3].time_device); } #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 void TIMER4_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[4].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[4].time_device); + timer_interrupt_flag_clear(clock_timer_obj[4].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[4].time_device); } #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 void TIMER5_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[5].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[5].time_device); + timer_interrupt_flag_clear(clock_timer_obj[5].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[5].time_device); } #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 void TIMER6_IRQHandler(void) { - timer_interrupt_flag_clear(hwtimer_obj[6].config->timer_periph, TIMER_INT_FLAG_UP); - rt_device_hwtimer_isr(&hwtimer_obj[6].time_device); + timer_interrupt_flag_clear(clock_timer_obj[6].config->timer_periph, TIMER_INT_FLAG_UP); + rt_clock_timer_isr(&clock_timer_obj[6].time_device); } #endif -static int rt_hwtimer_init(void) +static int rt_clock_timer_init(void) { int i = 0; int result = RT_EOK; -#ifdef BSP_USING_HWTIMER0 +#ifdef BSP_USING_CLOCK_TIMER0 rcu_periph_clock_enable(RCU_TIMER0); #endif -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 rcu_periph_clock_enable(RCU_TIMER1); #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 rcu_periph_clock_enable(RCU_TIMER2); #endif -#ifdef BSP_USING_HWTIMER3 +#ifdef BSP_USING_CLOCK_TIMER3 rcu_periph_clock_enable(RCU_TIMER3); #endif -#ifdef BSP_USING_HWTIMER4 +#ifdef BSP_USING_CLOCK_TIMER4 rcu_periph_clock_enable(RCU_TIMER4); #endif -#ifdef BSP_USING_HWTIMER5 +#ifdef BSP_USING_CLOCK_TIMER5 rcu_periph_clock_enable(RCU_TIMER5); #endif -#ifdef BSP_USING_HWTIMER6 +#ifdef BSP_USING_CLOCK_TIMER6 rcu_periph_clock_enable(RCU_TIMER6); #endif - for (i = 0; i < sizeof(hwtimer_obj) / sizeof(hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(clock_timer_obj) / sizeof(clock_timer_obj[0]); i++) { - hwtimer_obj[i].time_device.info = &gd32_hwtimer_info; - hwtimer_obj[i].time_device.ops = &gd32_hwtimer_ops; - hwtimer_obj[i].config = &hwtimer_config[i]; - rt_device_hwtimer_register(&hwtimer_obj[i].time_device, \ - hwtimer_obj[i].config->name, hwtimer_obj[i].config); + clock_timer_obj[i].time_device.info = &gd32_clock_timer_info; + clock_timer_obj[i].time_device.ops = &gd32_clock_timer_ops; + clock_timer_obj[i].config = &clock_timer_config[i]; + rt_clock_timer_register(&clock_timer_obj[i].time_device, \ + clock_timer_obj[i].config->name, clock_timer_obj[i].config); } return result; } -INIT_DEVICE_EXPORT(rt_hwtimer_init); +INIT_DEVICE_EXPORT(rt_clock_timer_init); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_timer.h similarity index 68% rename from bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.h rename to bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_timer.h index f4664c9d38..53b2e1e45e 100644 --- a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.h +++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_timer.h @@ -8,8 +8,8 @@ * 2029-05-06 hqfang first implementation. */ -#ifndef __DRV_HWTIMER__ -#define __DRV_HWTIMER__ +#ifndef __DRV_CLOCK_TIMER__ +#define __DRV_CLOCK_TIMER__ #include #include @@ -17,17 +17,17 @@ #include /* gd32 config class */ -struct gd32_hwtimer_config +struct gd32_clock_timer_config { const char *name; rt_uint32_t timer_periph; IRQn_Type irqn; }; -struct gd32_hwtimer +struct gd32_clock_timer { - rt_hwtimer_t time_device; - struct gd32_hwtimer_config *config; + rt_clock_timer_t time_device; + struct gd32_clock_timer_config *config; }; #endif diff --git a/bsp/nuvoton/libraries/m031/rtt_port/Kconfig b/bsp/nuvoton/libraries/m031/rtt_port/Kconfig index ea590078a7..6a640a1978 100644 --- a/bsp/nuvoton/libraries/m031/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m031/rtt_port/Kconfig @@ -92,7 +92,7 @@ config SOC_SERIES_M032 config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -117,7 +117,7 @@ config SOC_SERIES_M032 config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -141,7 +141,7 @@ config SOC_SERIES_M032 config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -165,7 +165,7 @@ config SOC_SERIES_M032 config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/m031/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m031/rtt_port/drv_timer.c index 02b5a1ea94..403889ec46 100644 --- a/bsp/nuvoton/libraries/m031/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/m031/rtt_port/drv_timer.c @@ -12,7 +12,7 @@ #include -#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) #include #include "NuMicro.h" @@ -24,17 +24,17 @@ /* Private typedef --------------------------------------------------------------*/ typedef struct nu_timer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; TIMER_T *timer_periph; IRQn_Type IRQn; } nu_timer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -56,15 +56,15 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg static nu_timer_t nu_timer3; #endif -static struct rt_hwtimer_info nu_timer_info = +static struct rt_clock_timer_info nu_timer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_timer_ops = +static struct rt_clock_timer_ops nu_timer_ops = { nu_timer_init, nu_timer_start, @@ -74,7 +74,7 @@ static struct rt_hwtimer_ops nu_timer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { RT_ASSERT(timer != RT_NULL); @@ -85,7 +85,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_timer_info; + struct rt_clock_timer_info *info = &nu_timer_info; timer_clk = TIMER_GetModuleClock(nu_timer->timer_periph); info->maxfreq = timer_clk; @@ -102,7 +102,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t err = RT_EOK; RT_ASSERT(timer != RT_NULL); @@ -121,11 +121,11 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ err = -RT_ERROR; } - if (HWTIMER_MODE_PERIOD == opmode) + if (CLOCK_TIMER_MODE_PERIOD == opmode) { TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_PERIODIC_MODE); } - else if (HWTIMER_MODE_ONESHOT == opmode) + else if (CLOCK_TIMER_MODE_ONESHOT == opmode) { TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_ONESHOT_MODE); } @@ -140,7 +140,7 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ return err; } -static void nu_timer_stop(rt_hwtimer_t *timer) +static void nu_timer_stop(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -151,7 +151,7 @@ static void nu_timer_stop(rt_hwtimer_t *timer) TIMER_Stop(nu_timer->timer_periph); } -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -162,7 +162,7 @@ static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) return TIMER_GetCounter(nu_timer->timer_periph); } -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; @@ -174,7 +174,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -186,7 +186,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIMER_Stop(nu_timer->timer_periph); break; @@ -207,7 +207,7 @@ int rt_hw_timer_init(void) nu_timer0.parent.info = &nu_timer_info; nu_timer0.parent.ops = &nu_timer_ops; nu_timer0.IRQn = TMR0_IRQn; - ret = rt_device_hwtimer_register(&nu_timer0.parent, "timer0", &nu_timer0); + ret = rt_clock_timer_register(&nu_timer0.parent, "timer0", &nu_timer0); if (ret != RT_EOK) { rt_kprintf("timer0 register failed\n"); @@ -221,7 +221,7 @@ int rt_hw_timer_init(void) nu_timer1.parent.info = &nu_timer_info; nu_timer1.parent.ops = &nu_timer_ops; nu_timer1.IRQn = TMR1_IRQn; - ret = rt_device_hwtimer_register(&nu_timer1.parent, "timer1", &nu_timer1); + ret = rt_clock_timer_register(&nu_timer1.parent, "timer1", &nu_timer1); if (ret != RT_EOK) { rt_kprintf("timer1 register failed\n"); @@ -235,7 +235,7 @@ int rt_hw_timer_init(void) nu_timer2.parent.info = &nu_timer_info; nu_timer2.parent.ops = &nu_timer_ops; nu_timer2.IRQn = TMR2_IRQn; - ret = rt_device_hwtimer_register(&nu_timer2.parent, "timer2", &nu_timer2); + ret = rt_clock_timer_register(&nu_timer2.parent, "timer2", &nu_timer2); if (ret != RT_EOK) { rt_kprintf("timer2 register failed\n"); @@ -249,7 +249,7 @@ int rt_hw_timer_init(void) nu_timer3.parent.info = &nu_timer_info; nu_timer3.parent.ops = &nu_timer_ops; nu_timer3.IRQn = TMR3_IRQn; - ret = rt_device_hwtimer_register(&nu_timer3.parent, "timer3", &nu_timer3); + ret = rt_clock_timer_register(&nu_timer3.parent, "timer3", &nu_timer3); if (ret != RT_EOK) { rt_kprintf("timer3 register failed\n"); @@ -271,7 +271,7 @@ void TMR0_IRQHandler(void) if (TIMER_GetIntFlag(TIMER0)) { TIMER_ClearIntFlag(TIMER0); - rt_device_hwtimer_isr(&nu_timer0.parent); + rt_clock_timer_isr(&nu_timer0.parent); } rt_interrupt_leave(); @@ -286,7 +286,7 @@ void TMR1_IRQHandler(void) if (TIMER_GetIntFlag(TIMER1)) { TIMER_ClearIntFlag(TIMER1); - rt_device_hwtimer_isr(&nu_timer1.parent); + rt_clock_timer_isr(&nu_timer1.parent); } rt_interrupt_leave(); @@ -301,7 +301,7 @@ void TMR2_IRQHandler(void) if (TIMER_GetIntFlag(TIMER2)) { TIMER_ClearIntFlag(TIMER2); - rt_device_hwtimer_isr(&nu_timer2.parent); + rt_clock_timer_isr(&nu_timer2.parent); } rt_interrupt_leave(); @@ -316,11 +316,11 @@ void TMR3_IRQHandler(void) if (TIMER_GetIntFlag(TIMER3)) { TIMER_ClearIntFlag(TIMER3); - rt_device_hwtimer_isr(&nu_timer3.parent); + rt_clock_timer_isr(&nu_timer3.parent); } rt_interrupt_leave(); } #endif -#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig b/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig index e37055919f..67632a4754 100644 --- a/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig @@ -97,7 +97,7 @@ config SOC_SERIES_M2354 config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -129,7 +129,7 @@ config SOC_SERIES_M2354 config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -160,7 +160,7 @@ config SOC_SERIES_M2354 config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -191,7 +191,7 @@ config SOC_SERIES_M2354 config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -222,7 +222,7 @@ config SOC_SERIES_M2354 config BSP_USING_TIMER4 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -253,7 +253,7 @@ config SOC_SERIES_M2354 config BSP_USING_TIMER5 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c index 1a27a5dc09..3ca6aab454 100644 --- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c @@ -12,7 +12,7 @@ #include -#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) #include #include "NuMicro.h" @@ -23,17 +23,17 @@ /* Private typedef --------------------------------------------------------------*/ typedef struct nu_timer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; TIMER_T *timer_periph; IRQn_Type IRQn; } nu_timer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -63,15 +63,15 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg static nu_timer_t nu_timer5; #endif -static struct rt_hwtimer_info nu_timer_info = +static struct rt_clock_timer_info nu_timer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_timer_ops = +static struct rt_clock_timer_ops nu_timer_ops = { nu_timer_init, nu_timer_start, @@ -81,7 +81,7 @@ static struct rt_hwtimer_ops nu_timer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { RT_ASSERT(timer != RT_NULL); @@ -92,7 +92,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_timer_info; + struct rt_clock_timer_info *info = &nu_timer_info; timer_clk = TIMER_GetModuleClock(nu_timer->timer_periph); info->maxfreq = timer_clk; @@ -109,7 +109,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t err = RT_EOK; RT_ASSERT(timer != RT_NULL); @@ -128,11 +128,11 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ err = -RT_ERROR; } - if (HWTIMER_MODE_PERIOD == opmode) + if (CLOCK_TIMER_MODE_PERIOD == opmode) { TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_PERIODIC_MODE); } - else if (HWTIMER_MODE_ONESHOT == opmode) + else if (CLOCK_TIMER_MODE_ONESHOT == opmode) { TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_ONESHOT_MODE); } @@ -147,7 +147,7 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ return err; } -static void nu_timer_stop(rt_hwtimer_t *timer) +static void nu_timer_stop(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -158,7 +158,7 @@ static void nu_timer_stop(rt_hwtimer_t *timer) TIMER_Stop(nu_timer->timer_periph); } -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -169,7 +169,7 @@ static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) return TIMER_GetCounter(nu_timer->timer_periph); } -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; @@ -181,7 +181,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -193,7 +193,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIMER_Stop(nu_timer->timer_periph); break; @@ -214,7 +214,7 @@ int rt_hw_timer_init(void) nu_timer0.parent.info = &nu_timer_info; nu_timer0.parent.ops = &nu_timer_ops; nu_timer0.IRQn = TMR0_IRQn; - ret = rt_device_hwtimer_register(&nu_timer0.parent, "timer0", &nu_timer0); + ret = rt_clock_timer_register(&nu_timer0.parent, "timer0", &nu_timer0); if (ret != RT_EOK) { rt_kprintf("timer0 register failed\n"); @@ -228,7 +228,7 @@ int rt_hw_timer_init(void) nu_timer1.parent.info = &nu_timer_info; nu_timer1.parent.ops = &nu_timer_ops; nu_timer1.IRQn = TMR1_IRQn; - ret = rt_device_hwtimer_register(&nu_timer1.parent, "timer1", &nu_timer1); + ret = rt_clock_timer_register(&nu_timer1.parent, "timer1", &nu_timer1); if (ret != RT_EOK) { rt_kprintf("timer1 register failed\n"); @@ -242,7 +242,7 @@ int rt_hw_timer_init(void) nu_timer2.parent.info = &nu_timer_info; nu_timer2.parent.ops = &nu_timer_ops; nu_timer2.IRQn = TMR2_IRQn; - ret = rt_device_hwtimer_register(&nu_timer2.parent, "timer2", &nu_timer2); + ret = rt_clock_timer_register(&nu_timer2.parent, "timer2", &nu_timer2); if (ret != RT_EOK) { rt_kprintf("timer2 register failed\n"); @@ -256,7 +256,7 @@ int rt_hw_timer_init(void) nu_timer3.parent.info = &nu_timer_info; nu_timer3.parent.ops = &nu_timer_ops; nu_timer3.IRQn = TMR3_IRQn; - ret = rt_device_hwtimer_register(&nu_timer3.parent, "timer3", &nu_timer3); + ret = rt_clock_timer_register(&nu_timer3.parent, "timer3", &nu_timer3); if (ret != RT_EOK) { rt_kprintf("timer3 register failed\n"); @@ -270,7 +270,7 @@ int rt_hw_timer_init(void) nu_timer4.parent.info = &nu_timer_info; nu_timer4.parent.ops = &nu_timer_ops; nu_timer4.IRQn = TMR4_IRQn; - ret = rt_device_hwtimer_register(&nu_timer4.parent, "timer4", &nu_timer4); + ret = rt_clock_timer_register(&nu_timer4.parent, "timer4", &nu_timer4); if (ret != RT_EOK) { rt_kprintf("timer4 register failed\n"); @@ -284,7 +284,7 @@ int rt_hw_timer_init(void) nu_timer5.parent.info = &nu_timer_info; nu_timer5.parent.ops = &nu_timer_ops; nu_timer5.IRQn = TMR5_IRQn; - ret = rt_device_hwtimer_register(&nu_timer5.parent, "timer5", &nu_timer5); + ret = rt_clock_timer_register(&nu_timer5.parent, "timer5", &nu_timer5); if (ret != RT_EOK) { rt_kprintf("timer5 register failed\n"); @@ -306,7 +306,7 @@ void TMR0_IRQHandler(void) if (TIMER_GetIntFlag(TIMER0)) { TIMER_ClearIntFlag(TIMER0); - rt_device_hwtimer_isr(&nu_timer0.parent); + rt_clock_timer_isr(&nu_timer0.parent); } rt_interrupt_leave(); @@ -321,7 +321,7 @@ void TMR1_IRQHandler(void) if (TIMER_GetIntFlag(TIMER1)) { TIMER_ClearIntFlag(TIMER1); - rt_device_hwtimer_isr(&nu_timer1.parent); + rt_clock_timer_isr(&nu_timer1.parent); } rt_interrupt_leave(); @@ -336,7 +336,7 @@ void TMR2_IRQHandler(void) if (TIMER_GetIntFlag(TIMER2)) { TIMER_ClearIntFlag(TIMER2); - rt_device_hwtimer_isr(&nu_timer2.parent); + rt_clock_timer_isr(&nu_timer2.parent); } rt_interrupt_leave(); @@ -351,7 +351,7 @@ void TMR3_IRQHandler(void) if (TIMER_GetIntFlag(TIMER3)) { TIMER_ClearIntFlag(TIMER3); - rt_device_hwtimer_isr(&nu_timer3.parent); + rt_clock_timer_isr(&nu_timer3.parent); } rt_interrupt_leave(); @@ -366,7 +366,7 @@ void TMR4_IRQHandler(void) if (TIMER_GetIntFlag(TIMER4)) { TIMER_ClearIntFlag(TIMER4); - rt_device_hwtimer_isr(&nu_timer4.parent); + rt_clock_timer_isr(&nu_timer4.parent); } rt_interrupt_leave(); @@ -381,11 +381,11 @@ void TMR5_IRQHandler(void) if (TIMER_GetIntFlag(TIMER5)) { TIMER_ClearIntFlag(TIMER5); - rt_device_hwtimer_isr(&nu_timer5.parent); + rt_clock_timer_isr(&nu_timer5.parent); } rt_interrupt_leave(); } #endif -#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) diff --git a/bsp/nuvoton/libraries/m460/rtt_port/Kconfig b/bsp/nuvoton/libraries/m460/rtt_port/Kconfig index e13519e10e..e4a2ec8b7d 100644 --- a/bsp/nuvoton/libraries/m460/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m460/rtt_port/Kconfig @@ -113,7 +113,7 @@ config SOC_SERIES_M460 config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -144,7 +144,7 @@ config SOC_SERIES_M460 config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -174,7 +174,7 @@ config SOC_SERIES_M460 config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -204,7 +204,7 @@ config SOC_SERIES_M460 config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/m460/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m460/rtt_port/drv_timer.c index b9f4c7bbea..3d9172c540 100644 --- a/bsp/nuvoton/libraries/m460/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/m460/rtt_port/drv_timer.c @@ -12,7 +12,7 @@ #include -#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) #include #include "NuMicro.h" @@ -41,7 +41,7 @@ enum /* Private typedef --------------------------------------------------------------*/ struct nu_timer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; char *name; TIMER_T *base; IRQn_Type irqn; @@ -51,11 +51,11 @@ struct nu_timer typedef struct nu_timer *nu_timer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -77,15 +77,15 @@ static struct nu_timer nu_timer_arr [] = #endif }; -static struct rt_hwtimer_info nu_timer_info = +static struct rt_clock_timer_info nu_timer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_timer_ops = +static struct rt_clock_timer_ops nu_timer_ops = { nu_timer_init, nu_timer_start, @@ -95,7 +95,7 @@ static struct rt_hwtimer_ops nu_timer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -103,7 +103,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_timer_info; + struct rt_clock_timer_info *info = &nu_timer_info; timer_clk = TIMER_GetModuleClock(psNuTmr->base); info->maxfreq = timer_clk; @@ -120,7 +120,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t ret = -RT_EINVAL; rt_uint32_t u32OpMode; @@ -135,11 +135,11 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ switch (opmode) { - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: u32OpMode = TIMER_PERIODIC_MODE; break; - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: u32OpMode = TIMER_ONESHOT_MODE; break; @@ -161,7 +161,7 @@ exit_nu_timer_start: return -(ret); } -static void nu_timer_stop(rt_hwtimer_t *timer) +static void nu_timer_stop(rt_clock_timer_t *timer) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -172,7 +172,7 @@ static void nu_timer_stop(rt_hwtimer_t *timer) TIMER_ResetCounter(psNuTmr->base); } -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -180,7 +180,7 @@ static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) return TIMER_GetCounter(psNuTmr->base); } -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); @@ -188,7 +188,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -200,7 +200,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIMER_Stop(psNuTmr->base); break; @@ -222,7 +222,7 @@ static void nu_timer_isr(nu_timer_t psNuTmr) if (TIMER_GetIntFlag(psNuTmr->base)) { TIMER_ClearIntFlag(psNuTmr->base); - rt_device_hwtimer_isr(&psNuTmr->parent); + rt_clock_timer_isr(&psNuTmr->parent); } } @@ -242,8 +242,8 @@ int rt_hw_timer_init(void) /* Register Timer operation. */ nu_timer_arr[i].parent.ops = &nu_timer_ops; - /* Register RT hwtimer device. */ - ret = rt_device_hwtimer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); + /* Register RT clock_timer device. */ + ret = rt_clock_timer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); RT_ASSERT(ret == RT_EOK); } return 0; @@ -295,4 +295,4 @@ void TMR3_IRQHandler(void) } #endif -#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) diff --git a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig index cc9de1b570..87a82cf98b 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/m480/rtt_port/Kconfig @@ -115,7 +115,7 @@ config SOC_SERIES_M480 config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -147,7 +147,7 @@ config SOC_SERIES_M480 config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -178,7 +178,7 @@ config SOC_SERIES_M480 config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -209,7 +209,7 @@ config SOC_SERIES_M480 config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c index 59509c3dbc..3052e5e7b6 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c @@ -12,7 +12,7 @@ #include -#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) #include #include "NuMicro.h" @@ -23,17 +23,17 @@ /* Private typedef --------------------------------------------------------------*/ typedef struct nu_timer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; TIMER_T *timer_periph; IRQn_Type IRQn; } nu_timer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -55,15 +55,15 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg static nu_timer_t nu_timer3; #endif -static struct rt_hwtimer_info nu_timer_info = +static struct rt_clock_timer_info nu_timer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_timer_ops = +static struct rt_clock_timer_ops nu_timer_ops = { nu_timer_init, nu_timer_start, @@ -73,7 +73,7 @@ static struct rt_hwtimer_ops nu_timer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { RT_ASSERT(timer != RT_NULL); @@ -84,7 +84,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_timer_info; + struct rt_clock_timer_info *info = &nu_timer_info; timer_clk = TIMER_GetModuleClock(nu_timer->timer_periph); info->maxfreq = timer_clk; @@ -101,7 +101,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t err = RT_EOK; RT_ASSERT(timer != RT_NULL); @@ -120,11 +120,11 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ err = -RT_ERROR; } - if (HWTIMER_MODE_PERIOD == opmode) + if (CLOCK_TIMER_MODE_PERIOD == opmode) { TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_PERIODIC_MODE); } - else if (HWTIMER_MODE_ONESHOT == opmode) + else if (CLOCK_TIMER_MODE_ONESHOT == opmode) { TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_ONESHOT_MODE); } @@ -139,7 +139,7 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ return err; } -static void nu_timer_stop(rt_hwtimer_t *timer) +static void nu_timer_stop(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -150,7 +150,7 @@ static void nu_timer_stop(rt_hwtimer_t *timer) TIMER_Stop(nu_timer->timer_periph); } -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer) { RT_ASSERT(timer != RT_NULL); @@ -161,7 +161,7 @@ static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) return TIMER_GetCounter(nu_timer->timer_periph); } -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; @@ -173,7 +173,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -185,7 +185,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIMER_Stop(nu_timer->timer_periph); break; @@ -206,7 +206,7 @@ int rt_hw_timer_init(void) nu_timer0.parent.info = &nu_timer_info; nu_timer0.parent.ops = &nu_timer_ops; nu_timer0.IRQn = TMR0_IRQn; - ret = rt_device_hwtimer_register(&nu_timer0.parent, "timer0", &nu_timer0); + ret = rt_clock_timer_register(&nu_timer0.parent, "timer0", &nu_timer0); if (ret != RT_EOK) { rt_kprintf("timer0 register failed\n"); @@ -220,7 +220,7 @@ int rt_hw_timer_init(void) nu_timer1.parent.info = &nu_timer_info; nu_timer1.parent.ops = &nu_timer_ops; nu_timer1.IRQn = TMR1_IRQn; - ret = rt_device_hwtimer_register(&nu_timer1.parent, "timer1", &nu_timer1); + ret = rt_clock_timer_register(&nu_timer1.parent, "timer1", &nu_timer1); if (ret != RT_EOK) { rt_kprintf("timer1 register failed\n"); @@ -234,7 +234,7 @@ int rt_hw_timer_init(void) nu_timer2.parent.info = &nu_timer_info; nu_timer2.parent.ops = &nu_timer_ops; nu_timer2.IRQn = TMR2_IRQn; - ret = rt_device_hwtimer_register(&nu_timer2.parent, "timer2", &nu_timer2); + ret = rt_clock_timer_register(&nu_timer2.parent, "timer2", &nu_timer2); if (ret != RT_EOK) { rt_kprintf("timer2 register failed\n"); @@ -248,7 +248,7 @@ int rt_hw_timer_init(void) nu_timer3.parent.info = &nu_timer_info; nu_timer3.parent.ops = &nu_timer_ops; nu_timer3.IRQn = TMR3_IRQn; - ret = rt_device_hwtimer_register(&nu_timer3.parent, "timer3", &nu_timer3); + ret = rt_clock_timer_register(&nu_timer3.parent, "timer3", &nu_timer3); if (ret != RT_EOK) { rt_kprintf("timer3 register failed\n"); @@ -270,7 +270,7 @@ void TMR0_IRQHandler(void) if (TIMER_GetIntFlag(TIMER0)) { TIMER_ClearIntFlag(TIMER0); - rt_device_hwtimer_isr(&nu_timer0.parent); + rt_clock_timer_isr(&nu_timer0.parent); } rt_interrupt_leave(); @@ -285,7 +285,7 @@ void TMR1_IRQHandler(void) if (TIMER_GetIntFlag(TIMER1)) { TIMER_ClearIntFlag(TIMER1); - rt_device_hwtimer_isr(&nu_timer1.parent); + rt_clock_timer_isr(&nu_timer1.parent); } rt_interrupt_leave(); @@ -300,7 +300,7 @@ void TMR2_IRQHandler(void) if (TIMER_GetIntFlag(TIMER2)) { TIMER_ClearIntFlag(TIMER2); - rt_device_hwtimer_isr(&nu_timer2.parent); + rt_clock_timer_isr(&nu_timer2.parent); } rt_interrupt_leave(); @@ -315,11 +315,11 @@ void TMR3_IRQHandler(void) if (TIMER_GetIntFlag(TIMER3)) { TIMER_ClearIntFlag(TIMER3); - rt_device_hwtimer_isr(&nu_timer3.parent); + rt_clock_timer_isr(&nu_timer3.parent); } rt_interrupt_leave(); } #endif -#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)) +#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME)) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig b/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig index fb6ca917ca..ef43e5c16d 100644 --- a/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig @@ -173,7 +173,7 @@ config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -198,7 +198,7 @@ config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -222,7 +222,7 @@ config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -246,7 +246,7 @@ config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -270,7 +270,7 @@ config BSP_USING_TIMER4 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -295,7 +295,7 @@ config BSP_USING_TIMER5 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -320,7 +320,7 @@ config BSP_USING_TIMER6 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -346,7 +346,7 @@ config BSP_USING_TIMER7 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -371,7 +371,7 @@ config BSP_USING_TIMER8 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -396,7 +396,7 @@ config BSP_USING_TIMER9 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -421,7 +421,7 @@ config BSP_USING_TIMER10 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. @@ -446,7 +446,7 @@ config BSP_USING_TIMER11 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "Timer" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c index fe590fec3b..58b31f8161 100644 --- a/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c @@ -12,7 +12,7 @@ #include -#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) #include #include "NuMicro.h" @@ -66,7 +66,7 @@ enum /* Private typedef --------------------------------------------------------------*/ struct nu_timer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; char *name; TIMER_T *base; IRQn_Type irqn; @@ -76,11 +76,11 @@ struct nu_timer typedef struct nu_timer *nu_timer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -126,15 +126,15 @@ static struct nu_timer nu_timer_arr [] = #endif }; -static struct rt_hwtimer_info nu_timer_info = +static struct rt_clock_timer_info nu_timer_info = { __HXT, /* maximum count frequency */ (__HXT / 256), /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_timer_ops = +static struct rt_clock_timer_ops nu_timer_ops = { nu_timer_init, nu_timer_start, @@ -144,7 +144,7 @@ static struct rt_hwtimer_ops nu_timer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -152,7 +152,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_timer_info; + struct rt_clock_timer_info *info = &nu_timer_info; timer_clk = TIMER_GetModuleClock(psNuTmr->base); info->maxfreq = timer_clk; @@ -169,7 +169,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t ret = -RT_EINVAL; rt_uint32_t u32OpMode; @@ -184,11 +184,11 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ switch (opmode) { - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: u32OpMode = TIMER_PERIODIC_MODE; break; - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: u32OpMode = TIMER_ONESHOT_MODE; break; @@ -210,7 +210,7 @@ exit_nu_timer_start: return -(ret); } -static void nu_timer_stop(rt_hwtimer_t *timer) +static void nu_timer_stop(rt_clock_timer_t *timer) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -221,7 +221,7 @@ static void nu_timer_stop(rt_hwtimer_t *timer) TIMER_ResetCounter(psNuTmr->base); } -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -229,7 +229,7 @@ static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) return TIMER_GetCounter(psNuTmr->base); } -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); @@ -237,7 +237,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -249,7 +249,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIMER_Stop(psNuTmr->base); break; @@ -272,7 +272,7 @@ static void nu_timer_isr(int vector, void *param) if (TIMER_GetIntFlag(psNuTmr->base)) { TIMER_ClearIntFlag(psNuTmr->base); - rt_device_hwtimer_isr(&psNuTmr->parent); + rt_clock_timer_isr(&psNuTmr->parent); } } @@ -295,8 +295,8 @@ int rt_hw_timer_init(void) /* Register Timer interrupt service routine. */ rt_hw_interrupt_install(nu_timer_arr[i].irqn, nu_timer_isr, &nu_timer_arr[i], nu_timer_arr[i].name); - /* Register RT hwtimer device. */ - ret = rt_device_hwtimer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); + /* Register RT clock_timer device. */ + ret = rt_clock_timer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); RT_ASSERT(ret == RT_EOK); } return 0; @@ -304,4 +304,4 @@ int rt_hw_timer_init(void) INIT_BOARD_EXPORT(rt_hw_timer_init); -#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig b/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig index aab564422e..a05652a923 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig @@ -93,7 +93,7 @@ config SOC_SERIES_N9H30 config BSP_USING_ETIMER0 select BSP_USING_ETIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "ETIMER" help Choose this option if you need TIMER function mode. @@ -118,7 +118,7 @@ config SOC_SERIES_N9H30 config BSP_USING_ETIMER1 select BSP_USING_ETIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "ETIMER" help Choose this option if you need TIMER function mode. @@ -142,7 +142,7 @@ config SOC_SERIES_N9H30 config BSP_USING_ETIMER2 select BSP_USING_ETIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "ETIMER" help Choose this option if you need TIMER function mode. @@ -166,7 +166,7 @@ config SOC_SERIES_N9H30 config BSP_USING_ETIMER3 select BSP_USING_ETIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "ETIMER" help Choose this option if you need TIMER function mode. @@ -197,28 +197,28 @@ config SOC_SERIES_N9H30 config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER0" help Choose this option if you need TIMER function mode. config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER1" help Choose this option if you need TIMER function mode. config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER2" help Choose this option if you need TIMER function mode. config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER3" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_etimer.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_etimer.c index e132600f95..ac75810bfd 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_etimer.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_etimer.c @@ -12,7 +12,7 @@ #include -#if defined(BSP_USING_ETIMER) && defined(RT_USING_HWTIMER) +#if defined(BSP_USING_ETIMER) && defined(RT_USING_CLOCK_TIME) #include #include "NuMicro.h" @@ -42,7 +42,7 @@ enum /* Private typedef --------------------------------------------------------------*/ struct nu_etimer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; char *name; uint32_t idx; IRQn_Type irqn; @@ -52,11 +52,11 @@ struct nu_etimer typedef struct nu_etimer *nu_etimer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_etimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_etimer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_etimer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_etimer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_etimer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_etimer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_etimer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_etimer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -102,15 +102,15 @@ static struct nu_etimer nu_etimer_arr [] = #endif }; -static struct rt_hwtimer_info nu_etimer_info = +static struct rt_clock_timer_info nu_etimer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_etimer_ops = +static struct rt_clock_timer_ops nu_etimer_ops = { nu_etimer_init, nu_etimer_start, @@ -120,7 +120,7 @@ static struct rt_hwtimer_ops nu_etimer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_etimer_init(rt_clock_timer_t *timer, rt_uint32_t state) { nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuETmr != RT_NULL); @@ -128,7 +128,7 @@ static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_etimer_info; + struct rt_clock_timer_info *info = &nu_etimer_info; timer_clk = ETIMER_GetModuleClock(psNuETmr->idx); info->maxfreq = timer_clk; @@ -145,7 +145,7 @@ static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_etimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_etimer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t ret = -RT_EINVAL; rt_uint32_t u32OpMode; @@ -160,11 +160,11 @@ static rt_err_t nu_etimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer switch (opmode) { - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: u32OpMode = ETIMER_PERIODIC_MODE; break; - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: u32OpMode = ETIMER_ONESHOT_MODE; break; @@ -186,7 +186,7 @@ exit_nu_etimer_start: return -(ret); } -static void nu_etimer_stop(rt_hwtimer_t *timer) +static void nu_etimer_stop(rt_clock_timer_t *timer) { nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuETmr != RT_NULL); @@ -197,7 +197,7 @@ static void nu_etimer_stop(rt_hwtimer_t *timer) ETIMER_ClearCounter(psNuETmr->idx); } -static rt_uint32_t nu_etimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_etimer_count_get(rt_clock_timer_t *timer) { nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuETmr != RT_NULL); @@ -205,7 +205,7 @@ static rt_uint32_t nu_etimer_count_get(rt_hwtimer_t *timer) return ETIMER_GetCounter(psNuETmr->idx); } -static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_etimer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); @@ -213,7 +213,7 @@ static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *ar switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -225,7 +225,7 @@ static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *ar } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: ETIMER_Stop(psNuETmr->idx); break; @@ -248,7 +248,7 @@ static void nu_etimer_isr(int vector, void *param) if (ETIMER_GetIntFlag(psNuETmr->idx)) { ETIMER_ClearIntFlag(psNuETmr->idx); - rt_device_hwtimer_isr(&psNuETmr->parent); + rt_clock_timer_isr(&psNuETmr->parent); } } @@ -271,8 +271,8 @@ int rt_hw_etimer_init(void) /* Register Etimer interrupt service routine. */ rt_hw_interrupt_install(nu_etimer_arr[i].irqn, nu_etimer_isr, &nu_etimer_arr[i], nu_etimer_arr[i].name); - /* Register RT hwtimer device. */ - ret = rt_device_hwtimer_register(&nu_etimer_arr[i].parent, nu_etimer_arr[i].name, &nu_etimer_arr[i]); + /* Register RT clock_timer device. */ + ret = rt_clock_timer_register(&nu_etimer_arr[i].parent, nu_etimer_arr[i].name, &nu_etimer_arr[i]); RT_ASSERT(ret == RT_EOK); } return 0; @@ -280,4 +280,4 @@ int rt_hw_etimer_init(void) INIT_BOARD_EXPORT(rt_hw_etimer_init); -#endif //#if defined(BSP_USING_ETIMER) && defined(RT_USING_HWTIMER) +#endif //#if defined(BSP_USING_ETIMER) && defined(RT_USING_CLOCK_TIME) diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_timer.c index 38ea1b9e49..df3d4a1dd2 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_timer.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_timer.c @@ -12,7 +12,7 @@ #include -#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) #include #include "NuMicro.h" @@ -44,7 +44,7 @@ enum /* Private typedef --------------------------------------------------------------*/ struct nu_timer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; char *name; uint32_t idx; IRQn_Type irqn; @@ -54,11 +54,11 @@ struct nu_timer typedef struct nu_timer *nu_timer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_timer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -105,15 +105,15 @@ static struct nu_timer nu_timer_arr [] = /* BSP_USING_TIMER4 is reserved for Systick usage. */ }; -static struct rt_hwtimer_info nu_timer_info = +static struct rt_clock_timer_info nu_timer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_timer_ops = +static struct rt_clock_timer_ops nu_timer_ops = { nu_timer_init, nu_timer_start, @@ -123,7 +123,7 @@ static struct rt_hwtimer_ops nu_timer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -131,7 +131,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_timer_info; + struct rt_clock_timer_info *info = &nu_timer_info; timer_clk = TIMER_GetModuleClock(psNuTmr->idx); info->maxfreq = timer_clk; @@ -148,7 +148,7 @@ static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t ret = -RT_EINVAL; rt_uint32_t u32OpMode; @@ -163,11 +163,11 @@ static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ switch (opmode) { - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: u32OpMode = TIMER_PERIODIC_MODE; break; - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: u32OpMode = TIMER_ONESHOT_MODE; break; @@ -189,7 +189,7 @@ exit_nu_timer_start: return -(ret); } -static void nu_timer_stop(rt_hwtimer_t *timer) +static void nu_timer_stop(rt_clock_timer_t *timer) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -200,7 +200,7 @@ static void nu_timer_stop(rt_hwtimer_t *timer) TIMER_ClearCounter(psNuTmr->idx); } -static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_timer_count_get(rt_clock_timer_t *timer) { nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuTmr != RT_NULL); @@ -208,7 +208,7 @@ static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) return TIMER_GetCounter(psNuTmr->idx); } -static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); @@ -216,7 +216,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -228,7 +228,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: TIMER_Stop(psNuTmr->idx); break; @@ -251,7 +251,7 @@ static void nu_timer_isr(int vector, void *param) if (TIMER_GetIntFlag(psNuTmr->idx)) { TIMER_ClearIntFlag(psNuTmr->idx); - rt_device_hwtimer_isr(&psNuTmr->parent); + rt_clock_timer_isr(&psNuTmr->parent); } } @@ -274,12 +274,12 @@ int rt_hw_timer_init(void) /* Register Etimer interrupt service routine. */ rt_hw_interrupt_install(nu_timer_arr[i].irqn, nu_timer_isr, &nu_timer_arr[i], nu_timer_arr[i].name); - /* Register RT hwtimer device. */ - ret = rt_device_hwtimer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); + /* Register RT clock_timer device. */ + ret = rt_clock_timer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); RT_ASSERT(ret == RT_EOK); } return 0; } INIT_BOARD_EXPORT(rt_hw_timer_init); -#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig index 379c5e84fc..c494564285 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig @@ -103,7 +103,7 @@ config SOC_SERIES_NUC980 config BSP_USING_TIMER0 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -128,7 +128,7 @@ config SOC_SERIES_NUC980 config BSP_USING_TIMER1 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -152,7 +152,7 @@ config SOC_SERIES_NUC980 config BSP_USING_TIMER2 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -176,7 +176,7 @@ config SOC_SERIES_NUC980 config BSP_USING_TIMER3 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. @@ -200,7 +200,7 @@ config SOC_SERIES_NUC980 config BSP_USING_TIMER4 select BSP_USING_TIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME bool "TIMER" help Choose this option if you need TIMER function mode. diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c index 93942edd54..64fcdc1dd4 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c @@ -12,7 +12,7 @@ #include -#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) #include #include "NuMicro.h" @@ -46,7 +46,7 @@ enum /* Private typedef --------------------------------------------------------------*/ struct nu_etimer { - rt_hwtimer_t parent; + rt_clock_timer_t parent; char *name; uint32_t idx; IRQn_Type irqn; @@ -56,11 +56,11 @@ struct nu_etimer typedef struct nu_etimer *nu_etimer_t; /* Private functions ------------------------------------------------------------*/ -static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t nu_etimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); -static void nu_etimer_stop(rt_hwtimer_t *timer); -static rt_uint32_t nu_etimer_count_get(rt_hwtimer_t *timer); -static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void nu_etimer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t nu_etimer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode); +static void nu_etimer_stop(rt_clock_timer_t *timer); +static rt_uint32_t nu_etimer_count_get(rt_clock_timer_t *timer); +static rt_err_t nu_etimer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); /* Public functions -------------------------------------------------------------*/ @@ -116,15 +116,15 @@ static struct nu_etimer nu_etimer_arr [] = /* BSP_USING_TIMER5 is reserved for Systick usage. */ }; -static struct rt_hwtimer_info nu_etimer_info = +static struct rt_clock_timer_info nu_etimer_info = { 12000000, /* maximum count frequency */ 46875, /* minimum count frequency */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ }; -static struct rt_hwtimer_ops nu_etimer_ops = +static struct rt_clock_timer_ops nu_etimer_ops = { nu_etimer_init, nu_etimer_start, @@ -134,7 +134,7 @@ static struct rt_hwtimer_ops nu_etimer_ops = }; /* Functions define ------------------------------------------------------------*/ -static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void nu_etimer_init(rt_clock_timer_t *timer, rt_uint32_t state) { nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuETmr != RT_NULL); @@ -142,7 +142,7 @@ static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { uint32_t timer_clk; - struct rt_hwtimer_info *info = &nu_etimer_info; + struct rt_clock_timer_info *info = &nu_etimer_info; timer_clk = ETIMER_GetModuleClock(psNuETmr->idx); info->maxfreq = timer_clk; @@ -159,7 +159,7 @@ static void nu_etimer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t nu_etimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t nu_etimer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t ret = -RT_EINVAL; rt_uint32_t u32OpMode; @@ -174,11 +174,11 @@ static rt_err_t nu_etimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer switch (opmode) { - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: u32OpMode = ETIMER_PERIODIC_MODE; break; - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: u32OpMode = ETIMER_ONESHOT_MODE; break; @@ -200,7 +200,7 @@ exit_nu_etimer_start: return -(ret); } -static void nu_etimer_stop(rt_hwtimer_t *timer) +static void nu_etimer_stop(rt_clock_timer_t *timer) { nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuETmr != RT_NULL); @@ -211,7 +211,7 @@ static void nu_etimer_stop(rt_hwtimer_t *timer) ETIMER_ClearCounter(psNuETmr->idx); } -static rt_uint32_t nu_etimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t nu_etimer_count_get(rt_clock_timer_t *timer) { nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); RT_ASSERT(psNuETmr != RT_NULL); @@ -219,7 +219,7 @@ static rt_uint32_t nu_etimer_count_get(rt_hwtimer_t *timer) return ETIMER_GetCounter(psNuETmr->idx); } -static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t nu_etimer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; nu_etimer_t psNuETmr = NU_TIMER_DEVICE(timer); @@ -227,7 +227,7 @@ static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *ar switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -239,7 +239,7 @@ static rt_err_t nu_etimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *ar } break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: ETIMER_Stop(psNuETmr->idx); break; @@ -262,7 +262,7 @@ static void nu_etimer_isr(int vector, void *param) if (ETIMER_GetIntFlag(psNuETmr->idx)) { ETIMER_ClearIntFlag(psNuETmr->idx); - rt_device_hwtimer_isr(&psNuETmr->parent); + rt_clock_timer_isr(&psNuETmr->parent); } } @@ -285,8 +285,8 @@ int rt_hw_etimer_init(void) /* Register Etimer interrupt service routine. */ rt_hw_interrupt_install(nu_etimer_arr[i].irqn, nu_etimer_isr, &nu_etimer_arr[i], nu_etimer_arr[i].name); - /* Register RT hwtimer device. */ - ret = rt_device_hwtimer_register(&nu_etimer_arr[i].parent, nu_etimer_arr[i].name, &nu_etimer_arr[i]); + /* Register RT clock_timer device. */ + ret = rt_clock_timer_register(&nu_etimer_arr[i].parent, nu_etimer_arr[i].name, &nu_etimer_arr[i]); RT_ASSERT(ret == RT_EOK); } return 0; @@ -294,4 +294,4 @@ int rt_hw_etimer_init(void) INIT_BOARD_EXPORT(rt_hw_etimer_init); -#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) +#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_CLOCK_TIME) diff --git a/bsp/nuvoton/nk-980iot/config_lvgl b/bsp/nuvoton/nk-980iot/config_lvgl index 8c65963bbb..87d581b321 100644 --- a/bsp/nuvoton/nk-980iot/config_lvgl +++ b/bsp/nuvoton/nk-980iot/config_lvgl @@ -170,9 +170,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=2048 CONFIG_RT_USING_CAN=y CONFIG_RT_CAN_USING_HDR=y # CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_HWTIMER=y -CONFIG_RT_USING_CPUTIME=y -CONFIG_CPUTIME_TIMER_FREQ=0 +CONFIG_RT_USING_CLOCK_TIME=y +CONFIG_CLOCK_TIMER_FREQ=0 CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y diff --git a/bsp/nuvoton/nk-980iot/project.uvopt b/bsp/nuvoton/nk-980iot/project.uvopt index 730a5777d3..baed90281b 100644 --- a/bsp/nuvoton/nk-980iot/project.uvopt +++ b/bsp/nuvoton/nk-980iot/project.uvopt @@ -391,8 +391,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputime.c - cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c + clock_time_core.c 0 0 @@ -403,8 +403,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputimer.c - cputimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 @@ -463,8 +463,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/nk-980iot/project.uvoptx b/bsp/nuvoton/nk-980iot/project.uvoptx index f3c2426a2c..51644e2695 100644 --- a/bsp/nuvoton/nk-980iot/project.uvoptx +++ b/bsp/nuvoton/nk-980iot/project.uvoptx @@ -391,8 +391,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputime.c - cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c + clock_time_core.c 0 0 @@ -403,8 +403,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputimer.c - cputimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 @@ -463,8 +463,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/nk-980iot/project.uvproj b/bsp/nuvoton/nk-980iot/project.uvproj index 32ca527fec..6be5063e78 100644 --- a/bsp/nuvoton/nk-980iot/project.uvproj +++ b/bsp/nuvoton/nk-980iot/project.uvproj @@ -723,9 +723,9 @@ - cputime.c + clock_time_core.c 1 - ..\..\..\components\drivers\cputime\cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c 2 @@ -779,9 +779,9 @@ - cputimer.c + clock_timer.c 1 - ..\..\..\components\drivers\cputime\cputimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 @@ -1059,9 +1059,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/nk-980iot/project.uvprojx b/bsp/nuvoton/nk-980iot/project.uvprojx index 9aec038116..048e023127 100644 --- a/bsp/nuvoton/nk-980iot/project.uvprojx +++ b/bsp/nuvoton/nk-980iot/project.uvprojx @@ -682,9 +682,9 @@ - cputime.c + clock_time_core.c 1 - ..\..\..\components\drivers\cputime\cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c 2 @@ -738,9 +738,9 @@ - cputimer.c + clock_timer.c 1 - ..\..\..\components\drivers\cputime\cputimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 @@ -1018,9 +1018,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/nk-980iot/spinor.config b/bsp/nuvoton/nk-980iot/spinor.config index 73ca797816..6a888d0214 100644 --- a/bsp/nuvoton/nk-980iot/spinor.config +++ b/bsp/nuvoton/nk-980iot/spinor.config @@ -175,9 +175,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=2048 CONFIG_RT_USING_CAN=y CONFIG_RT_CAN_USING_HDR=y # CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_HWTIMER=y -CONFIG_RT_USING_CPUTIME=y -CONFIG_CPUTIME_TIMER_FREQ=0 +CONFIG_RT_USING_CLOCK_TIME=y +CONFIG_CLOCK_TIMER_FREQ=0 CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y diff --git a/bsp/nuvoton/nk-n9h30/project.uvopt b/bsp/nuvoton/nk-n9h30/project.uvopt index 246d751843..81d2f4f59d 100644 --- a/bsp/nuvoton/nk-n9h30/project.uvopt +++ b/bsp/nuvoton/nk-n9h30/project.uvopt @@ -391,8 +391,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/nk-n9h30/project.uvproj b/bsp/nuvoton/nk-n9h30/project.uvproj index edf97f9ebd..04314bbd0b 100644 --- a/bsp/nuvoton/nk-n9h30/project.uvproj +++ b/bsp/nuvoton/nk-n9h30/project.uvproj @@ -723,9 +723,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/nk-rtu980/project.uvopt b/bsp/nuvoton/nk-rtu980/project.uvopt index 05e93fcc1f..ace3ba3106 100644 --- a/bsp/nuvoton/nk-rtu980/project.uvopt +++ b/bsp/nuvoton/nk-rtu980/project.uvopt @@ -367,8 +367,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputime.c - cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c + clock_time_core.c 0 0 @@ -379,8 +379,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputimer.c - cputimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 @@ -439,8 +439,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/nk-rtu980/project.uvproj b/bsp/nuvoton/nk-rtu980/project.uvproj index c0b81bb753..0fd0e92b88 100644 --- a/bsp/nuvoton/nk-rtu980/project.uvproj +++ b/bsp/nuvoton/nk-rtu980/project.uvproj @@ -611,9 +611,9 @@ - cputime.c + clock_time_core.c 1 - ..\..\..\components\drivers\cputime\cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c 2 @@ -667,9 +667,9 @@ - cputimer.c + clock_timer.c 1 - ..\..\..\components\drivers\cputime\cputimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 @@ -947,9 +947,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/numaker-iot-m467/config_lvgl b/bsp/nuvoton/numaker-iot-m467/config_lvgl index 84fce8720a..dbe4cda107 100644 --- a/bsp/nuvoton/numaker-iot-m467/config_lvgl +++ b/bsp/nuvoton/numaker-iot-m467/config_lvgl @@ -165,8 +165,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=512 CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set # CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y diff --git a/bsp/nuvoton/numaker-iot-m467/project.ewp b/bsp/nuvoton/numaker-iot-m467/project.ewp index fc84f282c7..8cc03027b5 100644 --- a/bsp/nuvoton/numaker-iot-m467/project.ewp +++ b/bsp/nuvoton/numaker-iot-m467/project.ewp @@ -1224,7 +1224,7 @@ $PROJ_DIR$\..\..\..\components\drivers\hwcrypto\hwcrypto.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/nuvoton/numaker-iot-m467/project.uvoptx b/bsp/nuvoton/numaker-iot-m467/project.uvoptx index 687323ec13..ff6de66129 100644 --- a/bsp/nuvoton/numaker-iot-m467/project.uvoptx +++ b/bsp/nuvoton/numaker-iot-m467/project.uvoptx @@ -610,8 +610,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/numaker-iot-m467/project.uvprojx b/bsp/nuvoton/numaker-iot-m467/project.uvprojx index 194029c15b..55b50db848 100644 --- a/bsp/nuvoton/numaker-iot-m467/project.uvprojx +++ b/bsp/nuvoton/numaker-iot-m467/project.uvprojx @@ -1336,9 +1336,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/numaker-iot-m487/config_lvgl b/bsp/nuvoton/numaker-iot-m487/config_lvgl index bbeb858b34..02d41f8738 100644 --- a/bsp/nuvoton/numaker-iot-m487/config_lvgl +++ b/bsp/nuvoton/numaker-iot-m487/config_lvgl @@ -158,8 +158,7 @@ CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=2048 CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y diff --git a/bsp/nuvoton/numaker-iot-m487/project.ewp b/bsp/nuvoton/numaker-iot-m487/project.ewp index b5966f89f1..4fb48b1255 100644 --- a/bsp/nuvoton/numaker-iot-m487/project.ewp +++ b/bsp/nuvoton/numaker-iot-m487/project.ewp @@ -1222,7 +1222,7 @@ $PROJ_DIR$\..\..\..\components\drivers\hwcrypto\hwcrypto.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/nuvoton/numaker-iot-m487/project.uvoptx b/bsp/nuvoton/numaker-iot-m487/project.uvoptx index 1512157524..c4768e1d4b 100644 --- a/bsp/nuvoton/numaker-iot-m487/project.uvoptx +++ b/bsp/nuvoton/numaker-iot-m487/project.uvoptx @@ -610,8 +610,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/numaker-iot-m487/project.uvproj b/bsp/nuvoton/numaker-iot-m487/project.uvproj index b7a1f75921..c307afedce 100644 --- a/bsp/nuvoton/numaker-iot-m487/project.uvproj +++ b/bsp/nuvoton/numaker-iot-m487/project.uvproj @@ -788,9 +788,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/nuvoton/numaker-iot-m487/project.uvprojx b/bsp/nuvoton/numaker-iot-m487/project.uvprojx index 6ac30b4f4e..b820f880b2 100644 --- a/bsp/nuvoton/numaker-iot-m487/project.uvprojx +++ b/bsp/nuvoton/numaker-iot-m487/project.uvprojx @@ -1335,9 +1335,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/numaker-m032ki/config_lvgl b/bsp/nuvoton/numaker-m032ki/config_lvgl index 122f5aa244..374031f2bb 100644 --- a/bsp/nuvoton/numaker-m032ki/config_lvgl +++ b/bsp/nuvoton/numaker-m032ki/config_lvgl @@ -135,8 +135,7 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y # CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y diff --git a/bsp/nuvoton/numaker-m032ki/project.ewp b/bsp/nuvoton/numaker-m032ki/project.ewp index 3b83ff3f26..d46d6fa38c 100644 --- a/bsp/nuvoton/numaker-m032ki/project.ewp +++ b/bsp/nuvoton/numaker-m032ki/project.ewp @@ -1159,7 +1159,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c diff --git a/bsp/nuvoton/numaker-m032ki/project.uvoptx b/bsp/nuvoton/numaker-m032ki/project.uvoptx index 850f005e80..06b22ba7fb 100644 --- a/bsp/nuvoton/numaker-m032ki/project.uvoptx +++ b/bsp/nuvoton/numaker-m032ki/project.uvoptx @@ -374,8 +374,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/numaker-m032ki/project.uvprojx b/bsp/nuvoton/numaker-m032ki/project.uvprojx index 24c12cd060..2e4c8e868b 100644 --- a/bsp/nuvoton/numaker-m032ki/project.uvprojx +++ b/bsp/nuvoton/numaker-m032ki/project.uvprojx @@ -522,9 +522,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/numaker-m2354/config_lvgl b/bsp/nuvoton/numaker-m2354/config_lvgl index 6db987d376..57e8f347ba 100644 --- a/bsp/nuvoton/numaker-m2354/config_lvgl +++ b/bsp/nuvoton/numaker-m2354/config_lvgl @@ -172,8 +172,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=2048 CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set # CONFIG_RT_CAN_USING_CANFD is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y @@ -383,7 +382,7 @@ CONFIG_UTEST_THR_PRIORITY=20 # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set -# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_CLOCK_TIME is not set # # RT-Thread Utestcases diff --git a/bsp/nuvoton/numaker-m2354/project.ewp b/bsp/nuvoton/numaker-m2354/project.ewp index aefdd38f51..1955f42c85 100644 --- a/bsp/nuvoton/numaker-m2354/project.ewp +++ b/bsp/nuvoton/numaker-m2354/project.ewp @@ -2325,7 +2325,7 @@ $PROJ_DIR$\..\..\..\components\drivers\hwcrypto\hwcrypto.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/nuvoton/numaker-m2354/project.uvoptx b/bsp/nuvoton/numaker-m2354/project.uvoptx index 1780fbee3c..2e633109e0 100644 --- a/bsp/nuvoton/numaker-m2354/project.uvoptx +++ b/bsp/nuvoton/numaker-m2354/project.uvoptx @@ -654,8 +654,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/numaker-m2354/project.uvprojx b/bsp/nuvoton/numaker-m2354/project.uvprojx index fc79bd4fbf..5294c23efd 100644 --- a/bsp/nuvoton/numaker-m2354/project.uvprojx +++ b/bsp/nuvoton/numaker-m2354/project.uvprojx @@ -1355,9 +1355,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/numaker-m467hj/config_lvgl b/bsp/nuvoton/numaker-m467hj/config_lvgl index e2aae5679c..ff2e60bf01 100644 --- a/bsp/nuvoton/numaker-m467hj/config_lvgl +++ b/bsp/nuvoton/numaker-m467hj/config_lvgl @@ -175,8 +175,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=128 CONFIG_RT_USING_CAN=y # CONFIG_RT_CAN_USING_HDR is not set # CONFIG_RT_CAN_USING_CANFD is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_CLOCK_TIME is not set CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y diff --git a/bsp/nuvoton/numaker-m467hj/project.ewp b/bsp/nuvoton/numaker-m467hj/project.ewp index 596c6a8d77..1d707e5964 100644 --- a/bsp/nuvoton/numaker-m467hj/project.ewp +++ b/bsp/nuvoton/numaker-m467hj/project.ewp @@ -1207,7 +1207,7 @@ $PROJ_DIR$\..\..\..\components\drivers\hwcrypto\hwcrypto.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/nuvoton/numaker-m467hj/project.uvoptx b/bsp/nuvoton/numaker-m467hj/project.uvoptx index 3cdcc75865..67245e901b 100644 --- a/bsp/nuvoton/numaker-m467hj/project.uvoptx +++ b/bsp/nuvoton/numaker-m467hj/project.uvoptx @@ -498,8 +498,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/numaker-m467hj/project.uvprojx b/bsp/nuvoton/numaker-m467hj/project.uvprojx index c02697c63a..68f7852be4 100644 --- a/bsp/nuvoton/numaker-m467hj/project.uvprojx +++ b/bsp/nuvoton/numaker-m467hj/project.uvprojx @@ -1285,9 +1285,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nuvoton/numaker-pfm-m487/config_lvgl b/bsp/nuvoton/numaker-pfm-m487/config_lvgl index 7c6f283972..c6b879ba15 100644 --- a/bsp/nuvoton/numaker-pfm-m487/config_lvgl +++ b/bsp/nuvoton/numaker-pfm-m487/config_lvgl @@ -159,8 +159,7 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=128 # CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y diff --git a/bsp/nuvoton/numaker-pfm-m487/project.ewp b/bsp/nuvoton/numaker-pfm-m487/project.ewp index ff0c072d8a..fc5f7c43f3 100644 --- a/bsp/nuvoton/numaker-pfm-m487/project.ewp +++ b/bsp/nuvoton/numaker-pfm-m487/project.ewp @@ -1205,7 +1205,7 @@ $PROJ_DIR$\..\..\..\components\drivers\hwcrypto\hwcrypto.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/nuvoton/numaker-pfm-m487/project.uvoptx b/bsp/nuvoton/numaker-pfm-m487/project.uvoptx index 4b9bd78d2d..a36f1e28b0 100644 --- a/bsp/nuvoton/numaker-pfm-m487/project.uvoptx +++ b/bsp/nuvoton/numaker-pfm-m487/project.uvoptx @@ -498,8 +498,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nuvoton/numaker-pfm-m487/project.uvproj b/bsp/nuvoton/numaker-pfm-m487/project.uvproj index 002e03a2bf..0ccb2abf44 100644 --- a/bsp/nuvoton/numaker-pfm-m487/project.uvproj +++ b/bsp/nuvoton/numaker-pfm-m487/project.uvproj @@ -757,9 +757,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/nuvoton/numaker-pfm-m487/project.uvprojx b/bsp/nuvoton/numaker-pfm-m487/project.uvprojx index 2f4a6c85a3..d37d5ebbf9 100644 --- a/bsp/nuvoton/numaker-pfm-m487/project.uvprojx +++ b/bsp/nuvoton/numaker-pfm-m487/project.uvprojx @@ -1285,9 +1285,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/board/Kconfig index 4e7ad9aad1..ae3d9590d2 100644 --- a/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1021-nxp-evk/board/Kconfig @@ -69,16 +69,16 @@ menu "On-chip Peripheral Drivers" int "Set LPUART1 TX DMA channel (0-32)" default 1 endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable GPT" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM - config BSP_USING_HWTIMER1 + config BSP_USING_CLOCK_TIMER1 bool "Enable GPT1" default n - config BSP_USING_HWTIMER2 + config BSP_USING_CLOCK_TIMER2 bool "Enable GPT2" default n endif diff --git a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/board/Kconfig index 2e071dbb34..bf6b813713 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/board/Kconfig @@ -92,16 +92,16 @@ menu "On-chip Peripheral Drivers" default 3 endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable GPT" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM - config BSP_USING_HWTIMER1 + config BSP_USING_CLOCK_TIMER1 bool "Enable GPT1" default n - config BSP_USING_HWTIMER2 + config BSP_USING_CLOCK_TIMER2 bool "Enable GPT2" default n endif diff --git a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewt b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewt index f2e841061a..af86848631 100644 --- a/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewt +++ b/bsp/nxp/imx/imxrt/imxrt1052-fire-pro/project.ewt @@ -1215,7 +1215,7 @@ $PROJ_DIR$\..\..\..\components\drivers\src\completion.c - $PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_time_core.c $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript index 233837fc36..9cc4b48ad6 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/SConscript +++ b/bsp/nxp/imx/imxrt/libraries/drivers/SConscript @@ -15,8 +15,8 @@ if GetDepend('BSP_USING_GPIO'): if GetDepend('BSP_USING_LPUART'): src += ['drv_uart.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend('BSP_USING_RTC'): src += ['drv_rtc.c'] diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_hwtimer.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c similarity index 58% rename from bsp/nxp/imx/imxrt/libraries/drivers/drv_hwtimer.c rename to bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c index aae7fa7a18..860c483e92 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_hwtimer.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.c @@ -11,13 +11,13 @@ */ #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include #include -#include "drv_hwtimer.h" +#include "drv_timer.h" #include "fsl_gpt.h" #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL @@ -40,32 +40,32 @@ static void NVIC_Configuration(void) { -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 EnableIRQ(GPT1_IRQn); #endif -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 EnableIRQ(GPT2_IRQn); #endif } -static rt_err_t imxrt_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t imxrt_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; + GPT_Type *clock_timer_dev; + clock_timer_dev = (GPT_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; clk = EXAMPLE_GPT_CLK_FREQ; pre = clk / *((uint32_t *)args) - 1; - GPT_SetClockDivider(hwtimer_dev, pre); + GPT_SetClockDivider(clock_timer_dev, pre); } break; default: @@ -75,36 +75,36 @@ static rt_err_t imxrt_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void return err; } -static rt_uint32_t imxrt_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t imxrt_clock_timer_count_get(rt_clock_timer_t *timer) { rt_uint32_t CurrentTimer_Count; - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; + GPT_Type *clock_timer_dev; + clock_timer_dev = (GPT_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - CurrentTimer_Count = GPT_GetCurrentTimerCount(hwtimer_dev); + CurrentTimer_Count = GPT_GetCurrentTimerCount(clock_timer_dev); return CurrentTimer_Count; } -static void imxrt_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void imxrt_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { - GPT_Type *hwtimer_dev; + GPT_Type *clock_timer_dev; gpt_config_t gptConfig; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; + clock_timer_dev = (GPT_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); if (state == 1) { #ifdef SOC_IMXRT1170_SERIES - #ifdef BSP_USING_HWTIMER1 + #ifdef BSP_USING_CLOCK_TIMER1 /*Clock setting for GPT*/ CLOCK_SetRootClockMux(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt1, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); #endif - #ifdef BSP_USING_HWTIMER2 + #ifdef BSP_USING_CLOCK_TIMER2 /*Clock setting for GPT*/ CLOCK_SetRootClockMux(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_SOURCE_SELECT); CLOCK_SetRootClockDiv(kCLOCK_Root_Gpt2, EXAMPLE_GPT_CLOCK_DIVIDER_SELECT); @@ -117,73 +117,73 @@ static void imxrt_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) /* Initialize GPT module by default config */ GPT_GetDefaultConfig(&gptConfig); - GPT_Init(hwtimer_dev, &gptConfig); + GPT_Init(clock_timer_dev, &gptConfig); } } -static rt_err_t imxrt_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t imxrt_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; + GPT_Type *clock_timer_dev; + clock_timer_dev = (GPT_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - hwtimer_dev->CR |= (mode != HWTIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U; + clock_timer_dev->CR |= (mode != CLOCK_TIMER_MODE_PERIOD) ? GPT_CR_FRR_MASK : 0U; - GPT_SetOutputCompareValue(hwtimer_dev, kGPT_OutputCompare_Channel1, cnt); + GPT_SetOutputCompareValue(clock_timer_dev, kGPT_OutputCompare_Channel1, cnt); - GPT_EnableInterrupts(hwtimer_dev, kGPT_OutputCompare1InterruptEnable); + GPT_EnableInterrupts(clock_timer_dev, kGPT_OutputCompare1InterruptEnable); NVIC_Configuration(); - GPT_StartTimer(hwtimer_dev); + GPT_StartTimer(clock_timer_dev); return RT_EOK; } -static void imxrt_hwtimer_stop(rt_hwtimer_t *timer) +static void imxrt_clock_timer_stop(rt_clock_timer_t *timer) { - GPT_Type *hwtimer_dev; - hwtimer_dev = (GPT_Type *)timer->parent.user_data; + GPT_Type *clock_timer_dev; + clock_timer_dev = (GPT_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - GPT_StopTimer(hwtimer_dev); + GPT_StopTimer(clock_timer_dev); } -static const struct rt_hwtimer_ops imxrt_hwtimer_ops = +static const struct rt_clock_timer_ops imxrt_clock_timer_ops = { - .init = imxrt_hwtimer_init, - .start = imxrt_hwtimer_start, - .stop = imxrt_hwtimer_stop, - .count_get = imxrt_hwtimer_count_get, - .control = imxrt_hwtimer_control, + .init = imxrt_clock_timer_init, + .start = imxrt_clock_timer_start, + .stop = imxrt_clock_timer_stop, + .count_get = imxrt_clock_timer_count_get, + .control = imxrt_clock_timer_control, }; -static const struct rt_hwtimer_info imxrt_hwtimer_info = +static const struct rt_clock_timer_info imxrt_clock_timer_info = { 25000000, /* the maximum count frequency can be set */ 6103, /* the minimum count frequency can be set */ 0xFFFFFFFF, - HWTIMER_CNTMODE_UP, + CLOCK_TIMER_CNTMODE_UP, }; -#ifdef BSP_USING_HWTIMER1 -static rt_hwtimer_t GPT_timer1; -#endif /*BSP_USING_HWTIMER1*/ +#ifdef BSP_USING_CLOCK_TIMER1 +static rt_clock_timer_t GPT_timer1; +#endif /*BSP_USING_CLOCK_TIMER1*/ -#ifdef BSP_USING_HWTIMER2 -static rt_hwtimer_t GPT_timer2; +#ifdef BSP_USING_CLOCK_TIMER2 +static rt_clock_timer_t GPT_timer2; #endif -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { int ret = RT_EOK; -#ifdef BSP_USING_HWTIMER1 - GPT_timer1.info = &imxrt_hwtimer_info; - GPT_timer1.ops = &imxrt_hwtimer_ops; - ret = rt_device_hwtimer_register(&GPT_timer1, "gpt1", GPT1); +#ifdef BSP_USING_CLOCK_TIMER1 + GPT_timer1.info = &imxrt_clock_timer_info; + GPT_timer1.ops = &imxrt_clock_timer_ops; + ret = rt_clock_timer_register(&GPT_timer1, "gpt1", GPT1); if (ret != RT_EOK) { @@ -191,10 +191,10 @@ int rt_hw_hwtimer_init(void) } #endif -#ifdef BSP_USING_HWTIMER2 - GPT_timer2.info = &imxrt_hwtimer_info; - GPT_timer2.ops = &imxrt_hwtimer_ops; - ret = rt_device_hwtimer_register(&GPT_timer2, "gpt2", GPT2); +#ifdef BSP_USING_CLOCK_TIMER2 + GPT_timer2.info = &imxrt_clock_timer_info; + GPT_timer2.ops = &imxrt_clock_timer_ops; + ret = rt_clock_timer_register(&GPT_timer2, "gpt2", GPT2); if (ret != RT_EOK) { @@ -205,14 +205,14 @@ int rt_hw_hwtimer_init(void) return ret; } -#ifdef BSP_USING_HWTIMER1 +#ifdef BSP_USING_CLOCK_TIMER1 void GPT1_IRQHandler(void) { if (GPT_GetStatusFlags(GPT1, kGPT_OutputCompare1Flag) != 0) { GPT_ClearStatusFlags(GPT1, kGPT_OutputCompare1Flag); - rt_device_hwtimer_isr(&GPT_timer1); + rt_clock_timer_isr(&GPT_timer1); } /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping @@ -222,16 +222,16 @@ void GPT1_IRQHandler(void) #endif } -#endif /*BSP_USING_HWTIMER1*/ +#endif /*BSP_USING_CLOCK_TIMER1*/ -#ifdef BSP_USING_HWTIMER2 +#ifdef BSP_USING_CLOCK_TIMER2 void GPT2_IRQHandler(void) { if (GPT_GetStatusFlags(GPT2, kGPT_OutputCompare1Flag) != 0) { GPT_ClearStatusFlags(GPT2, kGPT_OutputCompare1Flag); - rt_device_hwtimer_isr(&GPT_timer2); + rt_clock_timer_isr(&GPT_timer2); } /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M7F Store immediate overlapping @@ -240,8 +240,8 @@ void GPT2_IRQHandler(void) __DSB(); #endif } -#endif /*BSP_USING_HWTIMER2*/ +#endif /*BSP_USING_CLOCK_TIMER2*/ -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_hwtimer.h b/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.h similarity index 83% rename from bsp/nxp/imx/imxrt/libraries/drivers/drv_hwtimer.h rename to bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.h index 22dd018347..dc95a020b6 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_hwtimer.h +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_timer.h @@ -8,8 +8,8 @@ * 2018-04-17 WangBing the first version. */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ #include #include diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/board/Kconfig b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/board/Kconfig index 33e35d2ac5..02b973dfa9 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/board/Kconfig +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/board/Kconfig @@ -53,16 +53,16 @@ menu "On-chip Peripheral Drivers" default 1 endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable GPT" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM - config BSP_USING_HWTIMER1 + config BSP_USING_CLOCK_TIMER1 bool "Enable GPT1" default n - config BSP_USING_HWTIMER2 + config BSP_USING_CLOCK_TIMER2 bool "Enable GPT2" default n endif diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.ewp b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.ewp index f5a716af31..3e1756ee27 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.ewp +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.ewp @@ -1151,7 +1151,7 @@ DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\cputime\cputime.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_time_core.c $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvoptx b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvoptx index c1f392aa34..38789ef884 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvoptx +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvoptx @@ -536,8 +536,8 @@ 0 0 0 - ..\..\..\components\drivers\cputime\cputime.c - cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c + clock_time_core.c 0 0 diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvprojx b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvprojx index e15669351d..e89ac7373d 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvprojx +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1050xxx/project.uvprojx @@ -533,9 +533,9 @@ DeviceDrivers - cputime.c + clock_time_core.c 1 - ..\..\..\components\drivers\cputime\cputime.c + ..\..\..\components\drivers\clock_time\clock_time_core.c pin.c diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.ewp b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.ewp index 2a6b63a8a6..9d417419e3 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.ewp +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.ewp @@ -1167,7 +1167,7 @@ DeviceDrivers - $PROJ_DIR$\..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\cputime\cputime.c + $PROJ_DIR$\..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\clock_time\clock_time_core.c $PROJ_DIR$\..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\misc\pin.c diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvoptx b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvoptx index c4218d5d92..d6fee8bb74 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvoptx +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvoptx @@ -575,8 +575,8 @@ 0 0 0 - ..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\cputime\cputime.c - cputime.c + ..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\clock_time\clock_time_core.c + clock_time_core.c 0 0 diff --git a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvprojx b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvprojx index 9874343b6b..357075c781 100644 --- a/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvprojx +++ b/bsp/nxp/imx/imxrt/libraries/templates/imxrt1064xxx/project.uvprojx @@ -552,9 +552,9 @@ DeviceDrivers - cputime.c + clock_time_core.c 1 - ..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\cputime\cputime.c + ..\..\..\..\..\..\NXP\RTT_BSP\imxrt_bsp\components\drivers\clock_time\clock_time_core.c pin.c diff --git a/bsp/nxp/lpc/lpc178x/rtconfig.py b/bsp/nxp/lpc/lpc178x/rtconfig.py index 3f2d804903..4794f9a35b 100644 --- a/bsp/nxp/lpc/lpc178x/rtconfig.py +++ b/bsp/nxp/lpc/lpc178x/rtconfig.py @@ -3,7 +3,7 @@ import os # toolchains options ARCH='arm' CPU='cortex-m3' -CROSS_TOOL='keil' +CROSS_TOOL='gcc' BOARD_NAME = 'lpc178x' if os.getenv('RTT_CC'): diff --git a/bsp/nxp/lpc/lpc408x/drivers/Kconfig b/bsp/nxp/lpc/lpc408x/drivers/Kconfig index 3e9b19fb81..cc4f6f5212 100644 --- a/bsp/nxp/lpc/lpc408x/drivers/Kconfig +++ b/bsp/nxp/lpc/lpc408x/drivers/Kconfig @@ -7,9 +7,9 @@ menu "Hardware Drivers Config" select RT_USING_LWIP default n - config BSP_USING_HWTIMER0 + config BSP_USING_CLOCK_TIMER0 bool "Using timer0" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n config BSP_USING_ADC diff --git a/bsp/nxp/lpc/lpc408x/drivers/SConscript b/bsp/nxp/lpc/lpc408x/drivers/SConscript index 6557de9c16..70ac821c74 100644 --- a/bsp/nxp/lpc/lpc408x/drivers/SConscript +++ b/bsp/nxp/lpc/lpc408x/drivers/SConscript @@ -11,8 +11,8 @@ board.c if GetDepend(['BSP_USING_EMAC']): src += ['drv_emac.c'] -if GetDepend(['BSP_USING_HWTIMER0']): - src += ['drv_hwtimer.c'] +if GetDepend(['BSP_USING_CLOCK_TIMER0']): + src += ['drv_timer.c'] if GetDepend(['BSP_USING_LED']): src += ['drv_led.c'] diff --git a/bsp/nxp/lpc/lpc408x/drivers/drv_hwtimer.c b/bsp/nxp/lpc/lpc408x/drivers/drv_timer.c similarity index 70% rename from bsp/nxp/lpc/lpc408x/drivers/drv_hwtimer.c rename to bsp/nxp/lpc/lpc408x/drivers/drv_timer.c index 0357c2c1f9..70a64679b8 100644 --- a/bsp/nxp/lpc/lpc408x/drivers/drv_hwtimer.c +++ b/bsp/nxp/lpc/lpc408x/drivers/drv_timer.c @@ -12,16 +12,16 @@ #include #include "lpc_timer.h" #include "lpc_clkpwr.h" -#include "drv_hwtimer.h" +#include "drv_timer.h" -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME static void NVIC_Configuration(void) { NVIC_EnableIRQ(TIMER0_IRQn); } -static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { LPC_TIM_TypeDef *tim; TIM_TIMERCFG_Type cfg; @@ -40,7 +40,7 @@ static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { LPC_TIM_TypeDef *tim; TIM_MATCHCFG_Type match; @@ -50,7 +50,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ match.MatchChannel = 0; match.IntOnMatch = ENABLE; match.ResetOnMatch = ENABLE; - match.StopOnMatch = (opmode == HWTIMER_MODE_ONESHOT) ? ENABLE : DISABLE; + match.StopOnMatch = (opmode == CLOCK_TIMER_MODE_ONESHOT) ? ENABLE : DISABLE; match.ExtMatchOutputType = 0; match.MatchValue = t; @@ -60,7 +60,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ return RT_EOK; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { LPC_TIM_TypeDef *tim; @@ -69,7 +69,7 @@ static void timer_stop(rt_hwtimer_t *timer) TIM_Cmd(tim, DISABLE); } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { LPC_TIM_TypeDef *tim; rt_err_t err = RT_EOK; @@ -78,7 +78,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; @@ -98,7 +98,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return err; } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { LPC_TIM_TypeDef *tim; @@ -107,15 +107,15 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) return tim->TC; } -static const struct rt_hwtimer_info _info = +static const struct rt_clock_timer_info _info = { 1000000, /* the maximum count frequency can be set */ 2000, /* the minimum count frequency can be set */ 0xFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_UP,/* Increment or Decreasing count mode */ }; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { timer_init, timer_start, @@ -124,14 +124,14 @@ static const struct rt_hwtimer_ops _ops = timer_ctrl, }; -static rt_hwtimer_t _timer0; +static rt_clock_timer_t _timer0; -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { _timer0.info = &_info; _timer0.ops = &_ops; - rt_device_hwtimer_register(&_timer0, "timer0", LPC_TIM0); + rt_clock_timer_register(&_timer0, "timer0", LPC_TIM0); return 0; } @@ -141,10 +141,10 @@ void TIMER0_IRQHandler(void) if (TIM_GetIntStatus(LPC_TIM0, TIM_MR0_INT) != RESET) { TIM_ClearIntPending(LPC_TIM0, TIM_MR0_INT); - rt_device_hwtimer_isr(&_timer0); + rt_clock_timer_isr(&_timer0); } } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/nxp/lpc/lpc408x/drivers/drv_hwtimer.h b/bsp/nxp/lpc/lpc408x/drivers/drv_timer.h similarity index 63% rename from bsp/nxp/lpc/lpc408x/drivers/drv_hwtimer.h rename to bsp/nxp/lpc/lpc408x/drivers/drv_timer.h index ca34816a77..bd63fab1ac 100644 --- a/bsp/nxp/lpc/lpc408x/drivers/drv_hwtimer.h +++ b/bsp/nxp/lpc/lpc408x/drivers/drv_timer.h @@ -8,9 +8,9 @@ * 2015-09-02 heyuanjie87 the first version */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ -int rt_hw_hwtimer_init(void); +int rt_hw_clock_timer_init(void); -#endif /* DRV_HWTIMER_H__ */ +#endif /* DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/nxp/lpc/lpc408x/project.uvproj b/bsp/nxp/lpc/lpc408x/project.uvproj index ab66c409a2..45028c721b 100644 --- a/bsp/nxp/lpc/lpc408x/project.uvproj +++ b/bsp/nxp/lpc/lpc408x/project.uvproj @@ -359,7 +359,7 @@ __STDC_LIMIT_MACROS, CORE_M4, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC - ..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\ktime\inc;.;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\drivers\ktime;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\libcpu\arm\common;..\..\..\..\components\finsh;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;drivers;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;Libraries\Drivers\include;..\..\..\..\components\libc\posix\ipc;Libraries\CMSIS\Include;applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\delay;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;Libraries\Device\NXP\LPC407x_8x_177x_8x\Include + ..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\clock_time\inc;.;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\drivers\clock_time;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\libcpu\arm\common;..\..\..\..\components\finsh;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;drivers;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;Libraries\Drivers\include;..\..\..\..\components\libc\posix\ipc;Libraries\CMSIS\Include;applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\delay;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;Libraries\Device\NXP\LPC407x_8x_177x_8x\Include @@ -1064,26 +1064,26 @@ - ktime + clock_time - hrtimer.c + clock_hrtimer.c 1 - ..\..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\..\components\drivers\clock_time\clock_hrtimer.c - boottime.c + clock_boottime.c 1 - ..\..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\..\components\drivers\clock_time\clock_boottime.c - cputimer.c + clock_time_core.c 1 - ..\..\..\..\components\drivers\ktime\src\cputimer.c + ..\..\..\..\components\drivers\clock_time\clock_time_core.c diff --git a/bsp/nxp/lpc/lpc408x/project.uvprojx b/bsp/nxp/lpc/lpc408x/project.uvprojx index f3c2dfa9cf..fa15f6e109 100644 --- a/bsp/nxp/lpc/lpc408x/project.uvprojx +++ b/bsp/nxp/lpc/lpc408x/project.uvprojx @@ -333,7 +333,7 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 __STDC_LIMIT_MACROS, CORE_M4, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC - ..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\ktime\inc;.;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\drivers\ktime;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\libcpu\arm\common;..\..\..\..\components\finsh;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;drivers;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;Libraries\Drivers\include;..\..\..\..\components\libc\posix\ipc;Libraries\CMSIS\Include;applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\delay;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;Libraries\Device\NXP\LPC407x_8x_177x_8x\Include + ..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\clock_time\inc;.;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\drivers\clock_time;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\libcpu\arm\common;..\..\..\..\components\finsh;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;drivers;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\libc\posix\io\eventfd;Libraries\Drivers\include;..\..\..\..\components\libc\posix\ipc;Libraries\CMSIS\Include;applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\delay;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;Libraries\Device\NXP\LPC407x_8x_177x_8x\Include @@ -1039,26 +1039,26 @@ - ktime + clock_time - cputimer.c + clock_time_core.c 1 - ..\..\..\..\components\drivers\ktime\src\cputimer.c + ..\..\..\..\components\drivers\clock_time\clock_time_core.c - boottime.c + clock_boottime.c 1 - ..\..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\..\components\drivers\clock_time\clock_boottime.c - hrtimer.c + clock_hrtimer.c 1 - ..\..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\..\components\drivers\clock_time\clock_hrtimer.c diff --git a/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx b/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx index e091a4f64f..d0bdb76eaf 100644 --- a/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx +++ b/bsp/nxp/lpc/lpc54608-LPCXpresso/project.uvprojx @@ -332,7 +332,7 @@ --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 RT_USING_LIBC, CPU_LPC54608, RT_USING_ARMLIBC, SDK_DEBUGCONSOLE=0, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, CORE_M4, CPU_LPC54608J512ET180=1 - ..\..\..\..\libcpu\arm\cortex-m4;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\net\lwip\lwip-2.0.3\src\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;drivers;..\..\..\..\components\net\sal\include\socket\sys_socket;..\..\..\..\components\libc\posix\pthreads;..\..\..\..\components\net\lwip\lwip-2.0.3\src\include\ipv4;applications;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\drivers\ktime;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\libcpu\arm\common;SDK_2.2_LPCXpresso54608\CMSIS\Include;..\..\..\..\components\net\sal\include\dfs_net;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;..\..\..\..\components\net\sal\include;..\..\..\..\components\net\sal\include\socket;..\..\..\..\components\finsh;.;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\net\netdev\include;..\..\..\..\components\libc\posix\io\eventfd;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\..\..\components\net\lwip\port;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;SDK_2.2_LPCXpresso54608\devices\LPC54608;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\spi;..\..\..\..\components\libc\cplusplus;..\..\..\..\components\net\sal\impl;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\delay;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;..\..\..\..\components\net\lwip\lwip-2.0.3\src\include\netif;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;..\..\..\..\components\drivers\ktime\inc + ..\..\..\..\libcpu\arm\cortex-m4;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\net\lwip\lwip-2.0.3\src\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;drivers;..\..\..\..\components\net\sal\include\socket\sys_socket;..\..\..\..\components\libc\posix\pthreads;..\..\..\..\components\net\lwip\lwip-2.0.3\src\include\ipv4;applications;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\drivers\clock_time;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\libcpu\arm\common;SDK_2.2_LPCXpresso54608\CMSIS\Include;..\..\..\..\components\net\sal\include\dfs_net;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;..\..\..\..\components\net\sal\include;..\..\..\..\components\net\sal\include\socket;..\..\..\..\components\finsh;.;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;..\..\..\..\include;..\..\..\..\components\net\netdev\include;..\..\..\..\components\libc\posix\io\eventfd;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\..\..\components\net\lwip\port;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\drivers\include;SDK_2.2_LPCXpresso54608\devices\LPC54608;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\spi;..\..\..\..\components\libc\cplusplus;..\..\..\..\components\net\sal\impl;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\delay;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;..\..\..\..\components\net\lwip\lwip-2.0.3\src\include\netif;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;..\..\..\..\components\drivers\clock_time\inc @@ -1422,26 +1422,26 @@ - ktime + clock_time - boottime.c + clock_boottime.c 1 - ..\..\..\..\components\drivers\ktime\src\boottime.c + ..\..\..\..\components\drivers\clock_time\clock_boottime.c - cputimer.c + clock_time_core.c 1 - ..\..\..\..\components\drivers\ktime\src\cputimer.c + ..\..\..\..\components\drivers\clock_time\clock_time_core.c - hrtimer.c + clock_hrtimer.c 1 - ..\..\..\..\components\drivers\ktime\src\hrtimer.c + ..\..\..\..\components\drivers\clock_time\clock_hrtimer.c diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/SConscript b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/SConscript index db8bd4d409..772d3452bb 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/SConscript +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/SConscript @@ -28,8 +28,8 @@ if GetDepend('BSP_USING_MMA8562I2C'): if GetDepend('BSP_USING_ADC'): src += ['drv_adc.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_hwtimer.c b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_timer.c similarity index 52% rename from bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_hwtimer.c rename to bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_timer.c index de082d8d15..7c7a75bc57 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_hwtimer.c +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_timer.c @@ -12,13 +12,13 @@ */ #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include #include -#include "drv_hwtimer.h" +#include "drv_timer.h" #include "fsl_ctimer.h" enum @@ -34,15 +34,15 @@ enum #endif }; -struct lpc_hwtimer +struct lpc_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; CTIMER_Type* tim_handle; enum IRQn tim_irqn; char* name; }; -static struct lpc_hwtimer lpc_hwtimer_obj[] = +static struct lpc_clock_timer lpc_clock_timer_obj[] = { #ifdef BSP_USING_CTIMER0 TIM1_CONFIG, @@ -72,27 +72,27 @@ static void NVIC_Configuration(void) #endif } -static rt_err_t lpc_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t lpc_ctimer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; - if(hwtimer_dev == CTIMER0) clk = CLOCK_GetCTimerClkFreq(0U); - if(hwtimer_dev == CTIMER3) clk = CLOCK_GetCTimerClkFreq(3U); - if(hwtimer_dev == CTIMER4) clk = CLOCK_GetCTimerClkFreq(4U); + if(clock_timer_dev == CTIMER0) clk = CLOCK_GetCTimerClkFreq(0U); + if(clock_timer_dev == CTIMER3) clk = CLOCK_GetCTimerClkFreq(3U); + if(clock_timer_dev == CTIMER4) clk = CLOCK_GetCTimerClkFreq(4U); pre = clk / *((uint32_t *)args) - 1; - hwtimer_dev->PR = pre; + clock_timer_dev->PR = pre; } break; default: @@ -102,46 +102,46 @@ static rt_err_t lpc_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *a return err; } -static rt_uint32_t lpc_ctimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t lpc_ctimer_count_get(rt_clock_timer_t *timer) { rt_uint32_t CurrentTimer_Count; - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - CurrentTimer_Count = hwtimer_dev->TC; + CurrentTimer_Count = clock_timer_dev->TC; return CurrentTimer_Count; } -static void lpc_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void lpc_ctimer_init(rt_clock_timer_t *timer, rt_uint32_t state) { - CTIMER_Type *hwtimer_dev; + CTIMER_Type *clock_timer_dev; ctimer_config_t cfg; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); /* Use Main clock for some of the Ctimers */ - if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0); - if(hwtimer_dev == CTIMER3) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER3); - if(hwtimer_dev == CTIMER4) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER4); + if(clock_timer_dev == CTIMER0) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0); + if(clock_timer_dev == CTIMER3) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER3); + if(clock_timer_dev == CTIMER4) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER4); - CTIMER_Deinit(hwtimer_dev); + CTIMER_Deinit(clock_timer_dev); if (state == 1) { NVIC_Configuration(); CTIMER_GetDefaultConfig(&cfg); - CTIMER_Init(hwtimer_dev, &cfg); + CTIMER_Init(clock_timer_dev, &cfg); } } -static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t lpc_ctimer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; /* Match Configuration for Channel 0 */ ctimer_match_config_t matchCfg; @@ -149,32 +149,32 @@ static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtime /* Configuration*/ matchCfg.enableCounterReset = true; - matchCfg.enableCounterStop = (mode == HWTIMER_MODE_ONESHOT) ? true : false;; + matchCfg.enableCounterStop = (mode == CLOCK_TIMER_MODE_ONESHOT) ? true : false;; matchCfg.matchValue = cnt; matchCfg.outControl = kCTIMER_Output_NoAction; matchCfg.outPinInitState = false; matchCfg.enableInterrupt = true; - CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg); + CTIMER_SetupMatch(clock_timer_dev, kCTIMER_Match_1, &matchCfg); NVIC_Configuration(); - CTIMER_StartTimer(hwtimer_dev); + CTIMER_StartTimer(clock_timer_dev); return RT_EOK; } -static void lpc_ctimer_stop(rt_hwtimer_t *timer) +static void lpc_ctimer_stop(rt_clock_timer_t *timer) { - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - CTIMER_StopTimer(hwtimer_dev); + CTIMER_StopTimer(clock_timer_dev); } -static const struct rt_hwtimer_ops lpc_hwtimer_ops = +static const struct rt_clock_timer_ops lpc_clock_timer_ops = { .init = lpc_ctimer_init, .start = lpc_ctimer_start, @@ -183,31 +183,31 @@ static const struct rt_hwtimer_ops lpc_hwtimer_ops = .control = lpc_ctimer_control, }; -static const struct rt_hwtimer_info lpc_hwtimer_info = +static const struct rt_clock_timer_info lpc_clock_timer_info = { 25000000, /* the maximum count frequency can be set */ 6103, /* the minimum count frequency can be set */ 0xFFFFFFFF, - HWTIMER_CNTMODE_UP, + CLOCK_TIMER_CNTMODE_UP, }; -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(lpc_hwtimer_obj) / sizeof(lpc_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(lpc_clock_timer_obj) / sizeof(lpc_clock_timer_obj[0]); i++) { - lpc_hwtimer_obj[i].time_device.info = &lpc_hwtimer_info; - lpc_hwtimer_obj[i].time_device.ops = &lpc_hwtimer_ops; - if (rt_device_hwtimer_register(&lpc_hwtimer_obj[i].time_device, - lpc_hwtimer_obj[i].name, lpc_hwtimer_obj[i].tim_handle) == RT_EOK) + lpc_clock_timer_obj[i].time_device.info = &lpc_clock_timer_info; + lpc_clock_timer_obj[i].time_device.ops = &lpc_clock_timer_ops; + if (rt_clock_timer_register(&lpc_clock_timer_obj[i].time_device, + lpc_clock_timer_obj[i].name, lpc_clock_timer_obj[i].tim_handle) == RT_EOK) { - LOG_D("%s register success", lpc_hwtimer_obj[i].name); + LOG_D("%s register success", lpc_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", lpc_hwtimer_obj[i].name); + LOG_E("%s register failed", lpc_clock_timer_obj[i].name); result = -RT_ERROR; } } @@ -215,7 +215,7 @@ int rt_hw_hwtimer_init(void) return result; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); #ifdef BSP_USING_CTIMER0 void CTIMER0_IRQHandler(void) @@ -225,10 +225,10 @@ void CTIMER0_IRQHandler(void) int_stat = CTIMER_GetStatusFlags(CTIMER0); /* Clear the status flags that were set */ CTIMER_ClearStatusFlags(CTIMER0, int_stat); - rt_device_hwtimer_isr(&lpc_hwtimer_obj[TIM1_INDEX].time_device); + rt_clock_timer_isr(&lpc_clock_timer_obj[TIM1_INDEX].time_device); } -#endif /* BSP_USING_HWTIMER0 */ +#endif /* BSP_USING_CLOCK_TIMER0 */ #ifdef BSP_USING_CTIMER3 void CTIMER3_IRQHandler(void) @@ -238,10 +238,10 @@ void CTIMER3_IRQHandler(void) int_stat = CTIMER_GetStatusFlags(CTIMER3); /* Clear the status flags that were set */ CTIMER_ClearStatusFlags(CTIMER3, int_stat); - rt_device_hwtimer_isr(&lpc_hwtimer_obj[TIM2_INDEX].time_device); + rt_clock_timer_isr(&lpc_clock_timer_obj[TIM2_INDEX].time_device); } -#endif /* BSP_USING_HWTIMER3 */ +#endif /* BSP_USING_CLOCK_TIMER3 */ #ifdef BSP_USING_CTIMER4 void CTIMER4_IRQHandler(void) @@ -251,10 +251,10 @@ void CTIMER4_IRQHandler(void) int_stat = CTIMER_GetStatusFlags(CTIMER4); /* Clear the status flags that were set */ CTIMER_ClearStatusFlags(CTIMER4, int_stat); - rt_device_hwtimer_isr(&lpc_hwtimer_obj[TIM3_INDEX].time_device); + rt_clock_timer_isr(&lpc_clock_timer_obj[TIM3_INDEX].time_device); } -#endif /* BSP_USING_HWTIMER4 */ +#endif /* BSP_USING_CLOCK_TIMER4 */ -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_hwtimer.h b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_timer.h similarity index 91% rename from bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_hwtimer.h rename to bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_timer.h index f73aa0ca46..413bd46f77 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_hwtimer.h +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/drivers/drv_timer.h @@ -8,8 +8,8 @@ * 2018-04-17 WangBing the first version. */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef DRV_CLOCK_TIMER_H__ +#define DRV_CLOCK_TIMER_H__ #include #include @@ -41,7 +41,7 @@ } #endif /* TIM4_CONFIG */ -int rt_hw_hwtimer_init(void); +int rt_hw_clock_timer_init(void); -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig index 3527467baf..c593e8e0d3 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/board/Kconfig @@ -147,13 +147,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default y diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp index bb13acc40f..5c256fabc3 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.ewp @@ -1161,7 +1161,7 @@ $PROJ_DIR$\..\Libraries\drivers\drv_mma8562.c - $PROJ_DIR$\..\Libraries\drivers\drv_hwtimer.c + $PROJ_DIR$\..\Libraries\drivers\drv_timer.c $PROJ_DIR$\..\Libraries\drivers\drv_wdt.c @@ -1221,7 +1221,7 @@ DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx index 47b39900a1..4974afa91f 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvoptx @@ -561,8 +561,8 @@ 0 0 0 - ..\Libraries\drivers\drv_hwtimer.c - drv_hwtimer.c + ..\Libraries\drivers\drv_timer.c + drv_timer.c 0 0 @@ -753,8 +753,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvprojx b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvprojx index 875610e51f..0f3ff2ad97 100644 --- a/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvprojx +++ b/bsp/nxp/lpc/lpc55sxx/Libraries/template/lpc55s6xxxx/project.uvprojx @@ -534,9 +534,9 @@ ..\Libraries\drivers\drv_adc.c - drv_hwtimer.c + drv_timer.c 1 - ..\Libraries\drivers\drv_hwtimer.c + ..\Libraries\drivers\drv_timer.c drv_pwm.c @@ -688,9 +688,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c i2c_core.c diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/board/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/board/Kconfig index 74bdcb8a94..7c47c538fd 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/board/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s06_nxp_evk/board/Kconfig @@ -149,13 +149,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default n diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig index fb85eb0a80..70155de00a 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig @@ -149,13 +149,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default n diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/board/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/board/Kconfig index 4e80e5ec15..0a30acb27c 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/board/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s28_nxp_evk/board/Kconfig @@ -149,13 +149,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default n diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig index 0215acf530..5862fe3217 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s36_nxp_evk/board/Kconfig @@ -149,13 +149,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default n diff --git a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/board/Kconfig b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/board/Kconfig index 1ca764c295..10269eb496 100644 --- a/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/board/Kconfig +++ b/bsp/nxp/lpc/lpc55sxx/lpc55s69_nxp_evk/board/Kconfig @@ -260,13 +260,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default n diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript index da702a27ef..23c9d21d69 100644 --- a/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/SConscript @@ -25,8 +25,8 @@ if GetDepend('BSP_USING_I2C'): if GetDepend('BSP_USING_ADC'): src += ['drv_adc.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] diff --git a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_hwtimer.c b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_timer.c similarity index 59% rename from bsp/nxp/mcx/mcxa/Libraries/drivers/drv_hwtimer.c rename to bsp/nxp/mcx/mcxa/Libraries/drivers/drv_timer.c index 78b1e1e49a..e6d9a70bd4 100644 --- a/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_hwtimer.c +++ b/bsp/nxp/mcx/mcxa/Libraries/drivers/drv_timer.c @@ -10,9 +10,9 @@ */ #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include #include #include "fsl_ctimer.h" @@ -57,15 +57,15 @@ enum } #endif /* TIM2_CONFIG */ -struct mcxa_hwtimer +struct mcxa_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; CTIMER_Type* tim_handle; enum IRQn tim_irqn; char* name; }; -static struct mcxa_hwtimer mcxa_hwtimer_obj[] = +static struct mcxa_clock_timer mcxa_clock_timer_obj[] = { #ifdef BSP_USING_CTIMER0 TIM0_CONFIG, @@ -95,27 +95,27 @@ static void NVIC_Configuration(void) #endif } -static rt_err_t mcxa_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t mcxa_ctimer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { uint32_t clk; uint32_t pre; - if(hwtimer_dev == CTIMER0) clk = CLOCK_GetCTimerClkFreq(0U); - if(hwtimer_dev == CTIMER1) clk = CLOCK_GetCTimerClkFreq(1U); - if(hwtimer_dev == CTIMER2) clk = CLOCK_GetCTimerClkFreq(2U); + if(clock_timer_dev == CTIMER0) clk = CLOCK_GetCTimerClkFreq(0U); + if(clock_timer_dev == CTIMER1) clk = CLOCK_GetCTimerClkFreq(1U); + if(clock_timer_dev == CTIMER2) clk = CLOCK_GetCTimerClkFreq(2U); pre = clk / *((uint32_t *)args) - 1; - hwtimer_dev->PR = pre; + clock_timer_dev->PR = pre; } break; default: @@ -125,46 +125,46 @@ static rt_err_t mcxa_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void * return err; } -static rt_uint32_t mcxa_ctimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t mcxa_ctimer_count_get(rt_clock_timer_t *timer) { rt_uint32_t CurrentTimer_Count; - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - CurrentTimer_Count = hwtimer_dev->TC; + CurrentTimer_Count = clock_timer_dev->TC; return CurrentTimer_Count; } -static void mcxa_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void mcxa_ctimer_init(rt_clock_timer_t *timer, rt_uint32_t state) { - CTIMER_Type *hwtimer_dev; + CTIMER_Type *clock_timer_dev; ctimer_config_t cfg; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); /* Use Main clock for some of the Ctimers */ - if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kFRO_HF_to_CTIMER0); - if(hwtimer_dev == CTIMER1) CLOCK_AttachClk(kFRO_HF_to_CTIMER1); - if(hwtimer_dev == CTIMER2) CLOCK_AttachClk(kFRO_HF_to_CTIMER2); + if(clock_timer_dev == CTIMER0) CLOCK_AttachClk(kFRO_HF_to_CTIMER0); + if(clock_timer_dev == CTIMER1) CLOCK_AttachClk(kFRO_HF_to_CTIMER1); + if(clock_timer_dev == CTIMER2) CLOCK_AttachClk(kFRO_HF_to_CTIMER2); - CTIMER_Init(hwtimer_dev, &cfg); + CTIMER_Init(clock_timer_dev, &cfg); if (state == 1) { NVIC_Configuration(); CTIMER_GetDefaultConfig(&cfg); - CTIMER_Init(hwtimer_dev, &cfg); + CTIMER_Init(clock_timer_dev, &cfg); } } -static rt_err_t mcxa_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t mcxa_ctimer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; /* Match Configuration for Channel 0 */ ctimer_match_config_t matchCfg; @@ -172,32 +172,32 @@ static rt_err_t mcxa_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim /* Configuration*/ matchCfg.enableCounterReset = true; - matchCfg.enableCounterStop = (mode == HWTIMER_MODE_ONESHOT) ? true : false;; + matchCfg.enableCounterStop = (mode == CLOCK_TIMER_MODE_ONESHOT) ? true : false;; matchCfg.matchValue = cnt; matchCfg.outControl = kCTIMER_Output_NoAction; matchCfg.outPinInitState = false; matchCfg.enableInterrupt = true; - CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg); + CTIMER_SetupMatch(clock_timer_dev, kCTIMER_Match_1, &matchCfg); NVIC_Configuration(); - CTIMER_StartTimer(hwtimer_dev); + CTIMER_StartTimer(clock_timer_dev); return RT_EOK; } -static void mcxa_ctimer_stop(rt_hwtimer_t *timer) +static void mcxa_ctimer_stop(rt_clock_timer_t *timer) { - CTIMER_Type *hwtimer_dev; - hwtimer_dev = (CTIMER_Type *)timer->parent.user_data; + CTIMER_Type *clock_timer_dev; + clock_timer_dev = (CTIMER_Type *)timer->parent.user_data; RT_ASSERT(timer != RT_NULL); - CTIMER_StopTimer(hwtimer_dev); + CTIMER_StopTimer(clock_timer_dev); } -static const struct rt_hwtimer_ops mcxa_hwtimer_ops = +static const struct rt_clock_timer_ops mcxa_clock_timer_ops = { .init = mcxa_ctimer_init, .start = mcxa_ctimer_start, @@ -206,31 +206,31 @@ static const struct rt_hwtimer_ops mcxa_hwtimer_ops = .control = mcxa_ctimer_control, }; -static const struct rt_hwtimer_info mcxa_hwtimer_info = +static const struct rt_clock_timer_info mcxa_clock_timer_info = { 96000000, /* the maximum count frequency can be set */ 6103, /* the minimum count frequency can be set */ 0xFFFFFFFF, - HWTIMER_CNTMODE_UP, + CLOCK_TIMER_CNTMODE_UP, }; -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(mcxa_hwtimer_obj) / sizeof(mcxa_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(mcxa_clock_timer_obj) / sizeof(mcxa_clock_timer_obj[0]); i++) { - mcxa_hwtimer_obj[i].time_device.info = &mcxa_hwtimer_info; - mcxa_hwtimer_obj[i].time_device.ops = &mcxa_hwtimer_ops; - if (rt_device_hwtimer_register(&mcxa_hwtimer_obj[i].time_device, - mcxa_hwtimer_obj[i].name, mcxa_hwtimer_obj[i].tim_handle) == RT_EOK) + mcxa_clock_timer_obj[i].time_device.info = &mcxa_clock_timer_info; + mcxa_clock_timer_obj[i].time_device.ops = &mcxa_clock_timer_ops; + if (rt_clock_timer_register(&mcxa_clock_timer_obj[i].time_device, + mcxa_clock_timer_obj[i].name, mcxa_clock_timer_obj[i].tim_handle) == RT_EOK) { - LOG_D("%s register success", mcxa_hwtimer_obj[i].name); + LOG_D("%s register success", mcxa_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", mcxa_hwtimer_obj[i].name); + LOG_E("%s register failed", mcxa_clock_timer_obj[i].name); result = -RT_ERROR; } } @@ -238,7 +238,7 @@ int rt_hw_hwtimer_init(void) return result; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); #ifdef BSP_USING_CTIMER0 void CTIMER0_IRQHandler(void) @@ -249,10 +249,10 @@ void CTIMER0_IRQHandler(void) int_stat = CTIMER_GetStatusFlags(CTIMER0); /* Clear the status flags that were set */ CTIMER_ClearStatusFlags(CTIMER0, int_stat); - rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM0_INDEX].time_device); + rt_clock_timer_isr(&mcxa_clock_timer_obj[TIM0_INDEX].time_device); rt_interrupt_leave(); } -#endif /* BSP_USING_HWTIMER0 */ +#endif /* BSP_USING_CLOCK_TIMER0 */ #ifdef BSP_USING_CTIMER1 void CTIMER1_IRQHandler(void) @@ -263,10 +263,10 @@ void CTIMER1_IRQHandler(void) int_stat = CTIMER_GetStatusFlags(CTIMER1); /* Clear the status flags that were set */ CTIMER_ClearStatusFlags(CTIMER1, int_stat); - rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM1_INDEX].time_device); + rt_clock_timer_isr(&mcxa_clock_timer_obj[TIM1_INDEX].time_device); rt_interrupt_leave(); } -#endif /* BSP_USING_HWTIMER1 */ +#endif /* BSP_USING_CLOCK_TIMER1 */ #ifdef BSP_USING_CTIMER2 void CTIMER2_IRQHandler(void) @@ -277,10 +277,10 @@ void CTIMER2_IRQHandler(void) int_stat = CTIMER_GetStatusFlags(CTIMER2); /* Clear the status flags that were set */ CTIMER_ClearStatusFlags(CTIMER2, int_stat); - rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM2_INDEX].time_device); + rt_clock_timer_isr(&mcxa_clock_timer_obj[TIM2_INDEX].time_device); rt_interrupt_leave(); } -#endif /* BSP_USING_HWTIMER2 */ +#endif /* BSP_USING_CLOCK_TIMER2 */ -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa153/board/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa153/board/Kconfig index bfb840f930..0f2b4d1af6 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa153/board/Kconfig +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa153/board/Kconfig @@ -101,13 +101,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Hardware Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default y diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx b/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx index a5b1108738..314e0b45f2 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa153/project.uvprojx @@ -470,9 +470,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig index bc13fcdb5c..87f3becb62 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig @@ -108,13 +108,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default y diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx index 41ae9542dc..f857145a92 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx @@ -325,8 +325,8 @@ 0 0 0 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx index 4e8d74e129..2f93edb810 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx @@ -496,9 +496,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig index 0820121fc5..2567117783 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/board/Kconfig @@ -76,12 +76,12 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default y diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvoptx b/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvoptx index 56d3a78b4d..181dd9c7ab 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvoptx +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvoptx @@ -342,8 +342,8 @@ 0 0 0 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvprojx b/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvprojx index a4553409c6..4d66d9c031 100644 --- a/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvprojx +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa346/project.uvprojx @@ -501,9 +501,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript index aedc385849..56456e2fec 100644 --- a/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxc/Libraries/drivers/SConscript @@ -28,9 +28,6 @@ if GetDepend('BSP_USING_ADC'): if GetDepend('BSP_USING_DAC'): src += ['drv_dac.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] - if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig index 7800112a42..5a3a20c92b 100644 --- a/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/board/Kconfig @@ -75,10 +75,10 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y menuconfig BSP_USING_PWM diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.ewp b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.ewp index 3d335daa09..9159d37834 100644 --- a/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.ewp +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.ewp @@ -2318,7 +2318,7 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx index ac03bd3d3d..6bde6e67c0 100644 --- a/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx +++ b/bsp/nxp/mcx/mcxc/frdm-mcxc444/project.uvprojx @@ -470,9 +470,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript index 9a9f0979d1..a902674e85 100644 --- a/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxe/Libraries/drivers/SConscript @@ -22,9 +22,6 @@ if GetDepend('BSP_USING_I2C'): if GetDepend('BSP_USING_ADC'): src += ['drv_adc.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] - if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig index 2738f1136a..de3a7a083a 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/board/Kconfig @@ -97,13 +97,13 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config BSP_USING_CTIMER0 bool "Enable CIMER0" default y diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx index d8f793c243..d87e74043c 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvoptx @@ -335,8 +335,8 @@ 0 0 0 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx b/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx index b800d91322..9b1fce77b0 100644 --- a/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx +++ b/bsp/nxp/mcx/mcxe/frdm-mcxe247/project.uvprojx @@ -501,9 +501,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript b/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript index c193f1f106..1dee3db356 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/SConscript @@ -34,8 +34,8 @@ if GetDepend('BSP_USING_DAC'): if GetDepend('BSP_USING_CAN'): src += ['drv_can.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend('BSP_USING_WDT'): src += ['drv_wdt.c'] diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_timer.c similarity index 50% rename from bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c rename to bsp/nxp/mcx/mcxn/Libraries/drivers/drv_timer.c index cd65c534c6..82aa231f4e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_timer.c @@ -8,29 +8,29 @@ * 2024-02-21 Yilin Sun Initial revision. */ -#include "drv_hwtimer.h" +#include "drv_timer.h" -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER #include "fsl_mrt.h" typedef struct { - rt_hwtimer_t timer_device; + rt_clock_timer_t timer_device; mrt_chnl_t channel; char *name; -} mcx_hwtimer_obj_t; +} mcx_clock_timer_obj_t; -static inline rt_err_t mcx_hwtimer_mode_set(mcx_hwtimer_obj_t *handle, rt_hwtimer_mode_t mode) +static inline rt_err_t mcx_clock_timer_mode_set(mcx_clock_timer_obj_t *handle, rt_clock_timer_mode_t mode) { mrt_timer_mode_t mrt_mode; switch (mode) { - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: mrt_mode = kMRT_OneShotMode; break; - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: mrt_mode = kMRT_RepeatMode; break; @@ -43,7 +43,7 @@ static inline rt_err_t mcx_hwtimer_mode_set(mcx_hwtimer_obj_t *handle, rt_hwtime return RT_EOK; } -static void mcx_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void mcx_clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { mrt_config_t mrt_config; MRT_GetDefaultConfig(&mrt_config); @@ -51,15 +51,15 @@ static void mcx_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) MRT_Init(MRT0, &mrt_config); } -static rt_err_t mcx_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t mcx_clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { rt_err_t ret = RT_EOK; - mcx_hwtimer_obj_t *handle = timer->parent.user_data; + mcx_clock_timer_obj_t *handle = timer->parent.user_data; MRT_StopTimer(MRT0, handle->channel); - ret = mcx_hwtimer_mode_set(handle, mode); + ret = mcx_clock_timer_mode_set(handle, mode); if (ret != RT_EOK) { return ret; @@ -71,33 +71,33 @@ static rt_err_t mcx_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim return ret; } -static void mcx_hwtimer_stop(rt_hwtimer_t *timer) +static void mcx_clock_timer_stop(rt_clock_timer_t *timer) { - mcx_hwtimer_obj_t *handle = timer->parent.user_data; + mcx_clock_timer_obj_t *handle = timer->parent.user_data; MRT_StopTimer(MRT0, handle->channel); MRT_DisableInterrupts(MRT0, handle->channel, kMRT_TimerInterruptEnable); } -static rt_uint32_t mcx_hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t mcx_clock_timer_count_get(rt_clock_timer_t *timer) { - mcx_hwtimer_obj_t *handle = timer->parent.user_data; + mcx_clock_timer_obj_t *handle = timer->parent.user_data; return MRT_GetCurrentTimerCount(MRT0, handle->channel); } -static rt_err_t mcx_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t mcx_clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t ret = RT_EOK; - mcx_hwtimer_obj_t *handle = timer->parent.user_data; + mcx_clock_timer_obj_t *handle = timer->parent.user_data; switch (cmd) { - case HWTIMER_CTRL_STOP: - mcx_hwtimer_stop(timer); + case CLOCK_TIMER_CTRL_STOP: + mcx_clock_timer_stop(timer); break; - case HWTIMER_CTRL_MODE_SET: - ret = mcx_hwtimer_mode_set(handle, *(rt_hwtimer_mode_t *)args); + case CLOCK_TIMER_CTRL_MODE_SET: + ret = mcx_clock_timer_mode_set(handle, *(rt_clock_timer_mode_t *)args); if (ret != RT_EOK) { return ret; @@ -111,7 +111,7 @@ static rt_err_t mcx_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void * return RT_EOK; } -static mcx_hwtimer_obj_t mcx_hwtimer_list[] = +static mcx_clock_timer_obj_t mcx_clock_timer_list[] = { { .name = "timer0", .channel = kMRT_Channel_0, }, { .name = "timer1", .channel = kMRT_Channel_1, }, @@ -119,37 +119,37 @@ static mcx_hwtimer_obj_t mcx_hwtimer_list[] = { .name = "timer3", .channel = kMRT_Channel_3, }, }; -static struct rt_hwtimer_info mcx_hwtimer_info = +static struct rt_clock_timer_info mcx_clock_timer_info = { - .cntmode = HWTIMER_CNTMODE_DW, + .cntmode = CLOCK_TIMER_CNTMODE_DW, .maxcnt = 0x00FFFFFF, /* 24bit counter */ .minfreq = 150000000, .maxfreq = 150000000, }; -static const struct rt_hwtimer_ops mcx_hwtimer_ops = +static const struct rt_clock_timer_ops mcx_clock_timer_ops = { - .init = mcx_hwtimer_init, - .control = mcx_hwtimer_control, - .start = mcx_hwtimer_start, - .stop = mcx_hwtimer_stop, - .count_get = mcx_hwtimer_count_get, + .init = mcx_clock_timer_init, + .control = mcx_clock_timer_control, + .start = mcx_clock_timer_start, + .stop = mcx_clock_timer_stop, + .count_get = mcx_clock_timer_count_get, }; -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { /* MRT frequency is fixed to AHB clock */ uint32_t mrt_freq = CLOCK_GetFreq(kCLOCK_BusClk); - mcx_hwtimer_info.minfreq = mrt_freq; - mcx_hwtimer_info.maxfreq = mrt_freq; + mcx_clock_timer_info.minfreq = mrt_freq; + mcx_clock_timer_info.maxfreq = mrt_freq; - for (uint8_t i = 0; i < ARRAY_SIZE(mcx_hwtimer_list); i++) + for (uint8_t i = 0; i < ARRAY_SIZE(mcx_clock_timer_list); i++) { - mcx_hwtimer_list[i].timer_device.info = &mcx_hwtimer_info; - mcx_hwtimer_list[i].timer_device.ops = &mcx_hwtimer_ops; + mcx_clock_timer_list[i].timer_device.info = &mcx_clock_timer_info; + mcx_clock_timer_list[i].timer_device.ops = &mcx_clock_timer_ops; - rt_err_t ret = rt_device_hwtimer_register(&mcx_hwtimer_list[i].timer_device, mcx_hwtimer_list[i].name, &mcx_hwtimer_list[i]); + rt_err_t ret = rt_clock_timer_register(&mcx_clock_timer_list[i].timer_device, mcx_clock_timer_list[i].name, &mcx_clock_timer_list[i]); if (ret != RT_EOK) { return ret; @@ -173,11 +173,11 @@ void MRT0_IRQHandler(void) { if (mrt_flag & (1U << i)) { - rt_device_hwtimer_isr(&mcx_hwtimer_list[i].timer_device); + rt_clock_timer_isr(&mcx_clock_timer_list[i].timer_device); } } } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.h b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_timer.h similarity index 66% rename from bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.h rename to bsp/nxp/mcx/mcxn/Libraries/drivers/drv_timer.h index 5a9c5cbeba..ab1dfb444e 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_hwtimer.h +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_timer.h @@ -8,13 +8,13 @@ * 2024-02-21 Yilin Sun Initial revision. */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include #include -int rt_hw_hwtimer_init(void); +int rt_hw_clock_timer_init(void); -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig index 7a99272d42..95d456e625 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig @@ -187,10 +187,10 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y menuconfig BSP_USING_PWM diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewp b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewp index cebc66c1d8..5b802c5650 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewp +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewp @@ -2296,7 +2296,7 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion_comm.c diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvoptx b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvoptx index 7b158725d5..72917fbb7d 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvoptx +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvoptx @@ -337,8 +337,8 @@ 0 0 0 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx index 95bd03e733..96bf0522ad 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx @@ -552,9 +552,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c 2 diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig index 3457ec51b1..5717cd092f 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/Kconfig @@ -166,10 +166,10 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n - menuconfig BSP_USING_HWTIMER - config BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER bool "Enable Timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default y menuconfig BSP_USING_PWM diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.ewp b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.ewp index 4ae265a7ec..76c5d5b835 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.ewp +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.ewp @@ -2332,7 +2332,7 @@ $PROJ_DIR$\..\..\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\..\..\components\drivers\ipc\completion_comm.c diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx index c06d4f4eac..df92d1e302 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/project.uvprojx @@ -470,9 +470,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/qemu-virt64-riscv/driver/board.c b/bsp/qemu-virt64-riscv/driver/board.c index 092244278e..7250159e30 100644 --- a/bsp/qemu-virt64-riscv/driver/board.c +++ b/bsp/qemu-virt64-riscv/driver/board.c @@ -46,6 +46,11 @@ struct mem_desc platform_mem_desc[] = { #endif +rt_uint64_t rt_hw_get_clock_timer_freq(void) +{ + return 10000000ULL; +} + void primary_cpu_entry(void) { /* disable global interrupt */ @@ -115,4 +120,3 @@ void rt_hw_cpu_reset(void) ; } MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); - diff --git a/bsp/raspberry-pi/raspi3-32/applications/test_device.c b/bsp/raspberry-pi/raspi3-32/applications/test_device.c index 69b6e840fa..a071bf8844 100644 --- a/bsp/raspberry-pi/raspi3-32/applications/test_device.c +++ b/bsp/raspberry-pi/raspi3-32/applications/test_device.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include @@ -237,15 +237,15 @@ static rt_err_t timer_timeout_cb(rt_device_t dev, rt_size_t size) return 0; } #endif -rt_err_t test_hwtimer(void) +rt_err_t test_clock_timer(void) { #ifdef BSP_USING_SYSTIMER rt_kprintf("Hello Test HW Timer!\n"); rt_err_t err; - rt_hwtimerval_t val; + rt_clock_timerval_t val; rt_device_t dev = RT_NULL; rt_tick_t tick; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; int t = 5; if ((dev = rt_device_find(TIMER)) == RT_NULL) @@ -260,8 +260,8 @@ rt_err_t test_hwtimer(void) return -1; } - mode = HWTIMER_MODE_PERIOD; - err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + err = rt_device_control(dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); tick = rt_tick_get(); rt_kprintf("Start Timer> Tick: %d\n", tick); @@ -277,7 +277,7 @@ rt_err_t test_hwtimer(void) rt_kprintf("Sleep %d sec\n", t); rt_thread_delay(t*RT_TICK_PER_SECOND); - err = rt_device_control(dev, HWTIMER_CTRL_STOP, RT_NULL); + err = rt_device_control(dev, CLOCK_TIMER_CTRL_STOP, RT_NULL); rt_kprintf("Timer Stoped\n"); rt_device_read(dev, 0, &val, sizeof(val)); @@ -285,8 +285,8 @@ rt_err_t test_hwtimer(void) rt_device_set_rx_indicate(dev, timer_timeout_cb); - mode = HWTIMER_MODE_PERIOD; - err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + err = rt_device_control(dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); val.sec = t; val.usec = 0; @@ -436,9 +436,9 @@ void test_device(int argc, char**argv) return; } - if (0 == strcmp(argv[1],"hwtimer")) + if (0 == strcmp(argv[1],"clock_timer")) { - test_hwtimer(); + test_clock_timer(); return; } @@ -458,6 +458,6 @@ void test_device(int argc, char**argv) test_hdmi(); return; } - rt_kprintf("param err, please entry test_device \n"); + rt_kprintf("param err, please entry test_device \n"); } -MSH_CMD_EXPORT(test_device, sample: test_device ); +MSH_CMD_EXPORT(test_device, sample: test_device ); diff --git a/bsp/raspberry-pi/raspi3-32/driver/Kconfig b/bsp/raspberry-pi/raspi3-32/driver/Kconfig index c7e7c85597..098082732e 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/Kconfig +++ b/bsp/raspberry-pi/raspi3-32/driver/Kconfig @@ -22,7 +22,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_SYSTIMER bool "Enable SYSTIMER" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_SYSTIMER diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c index 117026e91c..edecb51ed5 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c @@ -12,19 +12,19 @@ #ifdef BSP_USING_SYSTIMER -static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state) +static void raspi_systimer_init(rt_clock_timer_t *clock_timer, rt_uint32_t state) { if (state == 0) - hwtimer->ops->stop(hwtimer); + clock_timer->ops->stop(clock_timer); } -static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t raspi_systimer_start(rt_clock_timer_t *clock_timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { rt_err_t result = RT_EOK; - rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + rt_systimer_t *timer = (rt_systimer_t *)clock_timer->parent.user_data; int timer_id = timer->timer_id; - if (mode == HWTIMER_MODE_PERIOD) + if (mode == CLOCK_TIMER_MODE_PERIOD) timer->cnt = cnt; else timer->cnt = 0; @@ -48,9 +48,9 @@ static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_ return result; } -static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) +static void raspi_systimer_stop(rt_clock_timer_t *clock_timer) { - rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + rt_systimer_t *timer = (rt_systimer_t *)clock_timer->parent.user_data; int timer_id = timer->timer_id; if (timer_id == 1) rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1); @@ -59,10 +59,10 @@ static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) } -static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t raspi_systimer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { /* The frequency value is an immutable value. */ - if (cmd == HWTIMER_CTRL_FREQ_SET) + if (cmd == CLOCK_TIMER_CTRL_FREQ_SET) { return RT_EOK; } @@ -76,8 +76,8 @@ static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void * void rt_device_systimer_isr(int vector, void *param) { - rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param; - rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + rt_clock_timer_t *clock_timer = (rt_clock_timer_t *) param; + rt_systimer_t *timer = (rt_systimer_t *)clock_timer->parent.user_data; RT_ASSERT(timer != RT_NULL); int timer_id = timer->timer_id; @@ -95,16 +95,16 @@ void rt_device_systimer_isr(int vector, void *param) } __sync_synchronize(); - rt_device_hwtimer_isr(hwtimer); + rt_clock_timer_isr(clock_timer); } -static struct rt_hwtimer_device _hwtimer1; -static struct rt_hwtimer_device _hwtimer3; +static struct rt_clock_timer_device _clock_timer1; +static struct rt_clock_timer_device _clock_timer3; static rt_systimer_t _systimer1; static rt_systimer_t _systimer3; -const static struct rt_hwtimer_ops systimer_ops = +const static struct rt_clock_timer_ops systimer_ops = { raspi_systimer_init, raspi_systimer_start, @@ -113,12 +113,12 @@ const static struct rt_hwtimer_ops systimer_ops = raspi_systimer_ctrl }; -static const struct rt_hwtimer_info _info = +static const struct rt_clock_timer_info _info = { 1000000, /* the maxinum count frequency can be set */ 1000000, /* the maxinum count frequency can be set */ 0xFFFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP /* count mode (inc/dec) */ + CLOCK_TIMER_CNTMODE_UP /* count mode (inc/dec) */ }; #endif @@ -130,19 +130,19 @@ int rt_hw_systimer_init(void) #ifdef RT_USING_SYSTIMER1 _systimer1.timer_id =1; - _hwtimer1.ops = &systimer_ops; - _hwtimer1.info = &_info; - rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1); - rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1"); + _clock_timer1.ops = &systimer_ops; + _clock_timer1.info = &_info; + rt_clock_timer_register(&_clock_timer1, "timer1",&_systimer1); + rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_clock_timer1, "systimer1"); rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1); #endif #ifdef RT_USING_SYSTIMER3 _systimer3.timer_id =3; - _hwtimer3.ops = &systimer_ops; - _hwtimer3.info = &_info; - rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3); - rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3"); + _clock_timer3.ops = &systimer_ops; + _clock_timer3.info = &_info; + rt_clock_timer_register(&_clock_timer3, "timer3",&_systimer3); + rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_clock_timer3, "systimer3"); rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3); #endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/Kconfig b/bsp/raspberry-pi/raspi3-64/driver/Kconfig index 6ebead47a2..5632f72462 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/Kconfig +++ b/bsp/raspberry-pi/raspi3-64/driver/Kconfig @@ -27,6 +27,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_SYSTIMER bool "Enable SYSTIMER" + select RT_USING_CLOCK_TIME default n if BSP_USING_SYSTIMER diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c index a8cb5149d4..eff6fe5417 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c @@ -14,19 +14,19 @@ #ifdef BSP_USING_SYSTIMER -static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state) +static void raspi_systimer_init(rt_clock_timer_t *clock_timer, rt_uint32_t state) { if (state == 0) - hwtimer->ops->stop(hwtimer); + clock_timer->ops->stop(clock_timer); } -static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t raspi_systimer_start(rt_clock_timer_t *clock_timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { rt_err_t result = RT_EOK; - rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + rt_systimer_t *timer = (rt_systimer_t *)clock_timer->parent.user_data; int timer_id = timer->timer_id; - if (mode == HWTIMER_MODE_PERIOD) + if (mode == CLOCK_TIMER_MODE_PERIOD) timer->cnt = cnt; else timer->cnt = 0; @@ -50,9 +50,9 @@ static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_ return result; } -static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) +static void raspi_systimer_stop(rt_clock_timer_t *clock_timer) { - rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + rt_systimer_t *timer = (rt_systimer_t *)clock_timer->parent.user_data; int timer_id = timer->timer_id; if (timer_id == 1) rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1); @@ -61,10 +61,10 @@ static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) } -static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t raspi_systimer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { /* The frequency value is an immutable value. */ - if (cmd == HWTIMER_CTRL_FREQ_SET) + if (cmd == CLOCK_TIMER_CTRL_FREQ_SET) { return RT_EOK; } @@ -78,8 +78,8 @@ static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void * void rt_device_systimer_isr(int vector, void *param) { - rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param; - rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + rt_clock_timer_t *clock_timer = (rt_clock_timer_t *) param; + rt_systimer_t *timer = (rt_systimer_t *)clock_timer->parent.user_data; RT_ASSERT(timer != RT_NULL); int timer_id = timer->timer_id; @@ -97,20 +97,20 @@ void rt_device_systimer_isr(int vector, void *param) } __sync_synchronize(); - rt_device_hwtimer_isr(hwtimer); + rt_clock_timer_isr(clock_timer); } #ifdef RT_USING_SYSTIMER1 -static struct rt_hwtimer_device _hwtimer1; +static struct rt_clock_timer_device _clock_timer1; static rt_systimer_t _systimer1; #endif #ifdef RT_USING_SYSTIMER3 -static struct rt_hwtimer_device _hwtimer3; +static struct rt_clock_timer_device _clock_timer3; static rt_systimer_t _systimer3; #endif -const static struct rt_hwtimer_ops systimer_ops = +const static struct rt_clock_timer_ops systimer_ops = { raspi_systimer_init, raspi_systimer_start, @@ -119,12 +119,12 @@ const static struct rt_hwtimer_ops systimer_ops = raspi_systimer_ctrl }; -static const struct rt_hwtimer_info _info = +static const struct rt_clock_timer_info _info = { 1000000, /* the maxinum count frequency can be set */ 1000000, /* the maxinum count frequency can be set */ 0xFFFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_UP /* count mode (inc/dec) */ + CLOCK_TIMER_CNTMODE_UP /* count mode (inc/dec) */ }; #endif @@ -136,19 +136,19 @@ int rt_hw_systimer_init(void) #ifdef RT_USING_SYSTIMER1 _systimer1.timer_id =1; - _hwtimer1.ops = &systimer_ops; - _hwtimer1.info = &_info; - rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1); - rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1"); + _clock_timer1.ops = &systimer_ops; + _clock_timer1.info = &_info; + rt_clock_timer_register(&_clock_timer1, "timer1",&_systimer1); + rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_clock_timer1, "systimer1"); rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1); #endif #ifdef RT_USING_SYSTIMER3 _systimer3.timer_id =3; - _hwtimer3.ops = &systimer_ops; - _hwtimer3.info = &_info; - rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3); - rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3"); + _clock_timer3.ops = &systimer_ops; + _clock_timer3.info = &_info; + rt_clock_timer_register(&_clock_timer3, "timer3",&_systimer3); + rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_clock_timer3, "systimer3"); rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3); #endif diff --git a/bsp/raspberry-pico/Drivers/SConscript b/bsp/raspberry-pico/Drivers/SConscript index dbd1b4f654..5afbe70b28 100644 --- a/bsp/raspberry-pico/Drivers/SConscript +++ b/bsp/raspberry-pico/Drivers/SConscript @@ -34,8 +34,8 @@ if GetDepend('BSP_USING_ON_CHIP_FLASH'): if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] -if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] +if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend('BSP_USING_RTC'): src += ['drv_rtc.c'] diff --git a/bsp/raspberry-pico/Drivers/drv_hwtimer.c b/bsp/raspberry-pico/Drivers/drv_timer.c similarity index 57% rename from bsp/raspberry-pico/Drivers/drv_hwtimer.c rename to bsp/raspberry-pico/Drivers/drv_timer.c index cefacd5477..4fd9d73789 100644 --- a/bsp/raspberry-pico/Drivers/drv_hwtimer.c +++ b/bsp/raspberry-pico/Drivers/drv_timer.c @@ -8,43 +8,43 @@ * 2023-10-30 ChuShicheng first version */ -#include "drv_hwtimer.h" +#include "drv_timer.h" #include "board.h" -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER #define DBG_LEVEL DBG_LOG #include -#define LOG_TAG "DRV.HWTIMER" +#define LOG_TAG "DRV.CLOCK_TIMER" typedef struct _timer { char *name; struct repeating_timer repeat_timer; alarm_id_t alarm_id; - rt_hwtimer_t timer; + rt_clock_timer_t timer; }_timer_t; -static void _hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state); -static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode); -static void _hwtimer_stop(rt_hwtimer_t *timer); -static rt_uint32_t _hwtimer_count_get(rt_hwtimer_t *timer); -static rt_err_t _hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); +static void _clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state); +static rt_err_t _clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode); +static void _clock_timer_stop(rt_clock_timer_t *timer); +static rt_uint32_t _clock_timer_count_get(rt_clock_timer_t *timer); +static rt_err_t _clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args); static int64_t _hwtmr_isr(alarm_id_t id, void *user_data); -static const struct rt_hwtimer_ops _hwtimer_ops = { - .init = _hwtimer_init, - .start = _hwtimer_start, - .stop = _hwtimer_stop, - .count_get = _hwtimer_count_get, - .control = _hwtimer_control +static const struct rt_clock_timer_ops _clock_timer_ops = { + .init = _clock_timer_init, + .start = _clock_timer_start, + .stop = _clock_timer_stop, + .count_get = _clock_timer_count_get, + .control = _clock_timer_control }; -static const struct rt_hwtimer_info _hwtimer_info = { +static const struct rt_clock_timer_info _clock_timer_info = { .maxfreq = 1000000UL, .minfreq = 1000000UL, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_MODE_PERIOD + .cntmode = CLOCK_TIMER_MODE_PERIOD }; #ifdef BSP_USING_TIMER0 @@ -78,26 +78,26 @@ static _timer_t *_timer_obj[] = { static int64_t _hwtmr_isr(alarm_id_t id, void *user_data) { _timer_t *_tmr = rt_container_of(id, _timer_t, alarm_id); - rt_device_hwtimer_isr(&_tmr->timer); + rt_clock_timer_isr(&_tmr->timer); return RT_TRUE; } static bool _repeat_timer_isr(struct repeating_timer *t) { _timer_t *_tmr = rt_container_of(t, _timer_t, repeat_timer); - rt_device_hwtimer_isr(&_tmr->timer); + rt_clock_timer_isr(&_tmr->timer); return RT_TRUE; } -static void _hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void _clock_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { } -static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t _clock_timer_start(rt_clock_timer_t *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); - if(mode == HWTIMER_MODE_ONESHOT) + if(mode == CLOCK_TIMER_MODE_ONESHOT) _tmr->alarm_id = add_alarm_in_us(cnt, _hwtmr_isr, RT_NULL, RT_TRUE); else add_repeating_timer_us(cnt, _repeat_timer_isr, RT_NULL, &_tmr->repeat_timer); @@ -105,55 +105,55 @@ static rt_err_t _hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_ return RT_EOK; } -static void _hwtimer_stop(rt_hwtimer_t *timer) +static void _clock_timer_stop(rt_clock_timer_t *timer) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); - if(timer->mode == HWTIMER_MODE_ONESHOT) + if(timer->mode == CLOCK_TIMER_MODE_ONESHOT) cancel_alarm(_tmr->alarm_id); else cancel_repeating_timer(&_tmr->repeat_timer); } -static rt_uint32_t _hwtimer_count_get(rt_hwtimer_t *timer) +static rt_uint32_t _clock_timer_count_get(rt_clock_timer_t *timer) { _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); return timer_hw->alarm[_tmr->alarm_id]; } -static rt_err_t _hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +static rt_err_t _clock_timer_control(rt_clock_timer_t *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; _timer_t *_tmr = rt_container_of(timer, _timer_t, timer); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: err = -RT_ERROR; break; - case HWTIMER_CTRL_INFO_GET: - *(rt_hwtimer_t*)args = _tmr->timer; + case CLOCK_TIMER_CTRL_INFO_GET: + *(rt_clock_timer_t*)args = _tmr->timer; break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: _tmr->timer.mode = *(rt_uint32_t*)args; break; - case HWTIMER_CTRL_STOP: - _hwtimer_stop(timer); + case CLOCK_TIMER_CTRL_STOP: + _clock_timer_stop(timer); break; } return err; } -int rt_hw_hwtimer_init(void) +int rt_hw_clock_timer_init(void) { int ret = RT_EOK; for (uint32_t i = 0; i < sizeof(_timer_obj) / sizeof(_timer_obj[0]); i++) { - _timer_obj[i]->timer.info = &_hwtimer_info; - _timer_obj[i]->timer.ops = &_hwtimer_ops; - ret = rt_device_hwtimer_register(&_timer_obj[i]->timer, _timer_obj[i]->name, _timer_obj[i]); + _timer_obj[i]->timer.info = &_clock_timer_info; + _timer_obj[i]->timer.ops = &_clock_timer_ops; + ret = rt_clock_timer_register(&_timer_obj[i]->timer, _timer_obj[i]->name, _timer_obj[i]); if (ret != RT_EOK) { LOG_E("%s register failed", _timer_obj[i]->name); @@ -163,5 +163,5 @@ int rt_hw_hwtimer_init(void) return ret; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); -#endif /* BSP_USING_HWTIMER */ +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/raspberry-pico/Drivers/drv_hwtimer.h b/bsp/raspberry-pico/Drivers/drv_timer.h similarity index 67% rename from bsp/raspberry-pico/Drivers/drv_hwtimer.h rename to bsp/raspberry-pico/Drivers/drv_timer.h index e84eb568cf..2b6c0c1c75 100644 --- a/bsp/raspberry-pico/Drivers/drv_hwtimer.h +++ b/bsp/raspberry-pico/Drivers/drv_timer.h @@ -7,11 +7,11 @@ * Date Author Notes * 2023-10-30 ChuShicheng first version */ -#ifndef DRV_HWTIMER_H -#define DRV_HWTIMER_H +#ifndef DRV_CLOCK_TIMER_H +#define DRV_CLOCK_TIMER_H #include -int rt_hw_hwtimer_init(void); +int rt_hw_clock_timer_init(void); -#endif /* DRV_HWTIMER_H */ +#endif /* DRV_CLOCK_TIMER_H */ diff --git a/bsp/raspberry-pico/RP2040/board/Kconfig b/bsp/raspberry-pico/RP2040/board/Kconfig index bffb545386..b1b70a9a38 100644 --- a/bsp/raspberry-pico/RP2040/board/Kconfig +++ b/bsp/raspberry-pico/RP2040/board/Kconfig @@ -659,25 +659,25 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TIMER0 - bool "Enable HWTIMER0" + bool "Enable CLOCK_TIMER0" default n config BSP_USING_TIMER1 - bool "Enable HWTIMER1" + bool "Enable CLOCK_TIMER1" default n config BSP_USING_TIMER2 - bool "Enable HWTIMER2" + bool "Enable CLOCK_TIMER2" default n config BSP_USING_TIMER3 - bool "Enable HWTIMER3" + bool "Enable CLOCK_TIMER3" default n endif diff --git a/bsp/raspberry-pico/RP2350/board/Kconfig b/bsp/raspberry-pico/RP2350/board/Kconfig index bffb545386..b1b70a9a38 100644 --- a/bsp/raspberry-pico/RP2350/board/Kconfig +++ b/bsp/raspberry-pico/RP2350/board/Kconfig @@ -659,25 +659,25 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER config BSP_USING_TIMER0 - bool "Enable HWTIMER0" + bool "Enable CLOCK_TIMER0" default n config BSP_USING_TIMER1 - bool "Enable HWTIMER1" + bool "Enable CLOCK_TIMER1" default n config BSP_USING_TIMER2 - bool "Enable HWTIMER2" + bool "Enable CLOCK_TIMER2" default n config BSP_USING_TIMER3 - bool "Enable HWTIMER3" + bool "Enable CLOCK_TIMER3" default n endif diff --git a/bsp/renesas/docs/Introduction_to_RA_Series_Drives.md b/bsp/renesas/docs/Introduction_to_RA_Series_Drives.md index c35946ddd9..b058af1f08 100644 --- a/bsp/renesas/docs/Introduction_to_RA_Series_Drives.md +++ b/bsp/renesas/docs/Introduction_to_RA_Series_Drives.md @@ -36,7 +36,7 @@ The driver libraries currently provided by RT-Thread already support multiple se | [SPI](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi) | Send and receive data over SPI | | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | Measure the analog data on the pin | | SDIO | Read and write data through SDIO | -| [TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | Use hardware timers to implement the function of measuring time and timing execution callback functions | +| [TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/clock_timer/clock_timer) | Use hardware timers to implement the function of measuring time and timing execution callback functions | | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | Outputs a PWM waveform at a specific pin | | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | Set and read times | | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | Watchdog driver | diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript b/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript index 75e41c133a..128ac93982 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/SConscript @@ -48,7 +48,7 @@ if GetDepend(['BSP_USING_PWM']): src += ['drv_pwm.c'] if GetDepend(['BSP_USING_TIM']): - src += ['drv_hwtimer.c'] + src += ['drv_timer.c'] if GetDepend(['BSP_USING_ETH']): src += ['drv_eth.c'] diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6e2/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6e2/timer_config.h index cf707670d7..2669a521eb 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6e2/timer_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6e2/timer_config.h @@ -37,7 +37,7 @@ extern "C" .maxfreq = 120000000, \ .minfreq = 1875000, \ .maxcnt = 0XFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6m3/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6m3/timer_config.h index cf707670d7..2669a521eb 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6m3/timer_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra6m3/timer_config.h @@ -37,7 +37,7 @@ extern "C" .maxfreq = 120000000, \ .minfreq = 1875000, \ .maxcnt = 0XFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h index 9e2d62b51f..aa946162cc 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/ra8/timer_config.h @@ -38,7 +38,7 @@ extern "C" .maxfreq = 250000000, \ .minfreq = 1562500, \ .maxcnt = 0XFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/config/rzt/timer_config.h b/bsp/renesas/libraries/HAL_Drivers/drivers/config/rzt/timer_config.h index 842a3eba59..090aed5170 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/config/rzt/timer_config.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/config/rzt/timer_config.h @@ -38,7 +38,7 @@ extern "C" .maxfreq = 400000000, \ .minfreq = 1562500, \ .maxcnt = 0XFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.c similarity index 69% rename from bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c rename to bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.c index bf7f2c79a2..8a4e71cd86 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.c +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.c @@ -9,15 +9,15 @@ */ #include "board.h" -#include "drv_hwtimer.h" +#include "drv_timer.h" //#define DRV_DEBUG #define LOG_TAG "drv.timer" #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME -static struct ra_hwtimer ra_hwtimer_obj[BSP_TIMERS_NUM] = +static struct ra_clock_timer ra_clock_timer_obj[BSP_TIMERS_NUM] = { #ifdef BSP_USING_TIM0 [BSP_TIMER0_INDEX] = TIMER_DRV_INITIALIZER(0), @@ -60,12 +60,12 @@ const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] = #endif }; -static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { RT_ASSERT(timer != RT_NULL); - struct ra_hwtimer *tim; - tim = (struct ra_hwtimer *)timer->parent.user_data; + struct ra_clock_timer *tim; + tim = (struct ra_clock_timer *)timer->parent.user_data; if (state) { @@ -80,13 +80,13 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t pr, rt_clock_timer_mode_t opmode) { RT_ASSERT(timer != RT_NULL); RT_ASSERT(opmode != RT_NULL); - struct ra_hwtimer *tim; - tim = (struct ra_hwtimer *)timer->parent.user_data; + struct ra_clock_timer *tim; + tim = (struct ra_clock_timer *)timer->parent.user_data; fsp_err_t err = FSP_SUCCESS; /* set timer count */ @@ -105,12 +105,12 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t pr, rt_hwtimer_mode return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { - struct ra_hwtimer *tim = RT_NULL; + struct ra_clock_timer *tim = RT_NULL; RT_ASSERT(timer != RT_NULL); - tim = (struct ra_hwtimer *)timer->parent.user_data; + tim = (struct ra_clock_timer *)timer->parent.user_data; /* stop timer */ R_GPT_Stop(tim->g_ctrl); @@ -119,13 +119,13 @@ static void timer_stop(rt_hwtimer_t *timer) R_GPT_CounterSet(tim->g_ctrl, 0); } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { - struct ra_hwtimer *tim = RT_NULL; + struct ra_clock_timer *tim = RT_NULL; RT_ASSERT(timer != RT_NULL); - tim = (struct ra_hwtimer *)timer->parent.user_data; + tim = (struct ra_clock_timer *)timer->parent.user_data; #if defined(SOC_SERIES_R7KA8P1) timer_info_t info; @@ -142,19 +142,19 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) #endif } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { rt_err_t result = RT_EOK; - struct ra_hwtimer *tim = RT_NULL; + struct ra_clock_timer *tim = RT_NULL; RT_ASSERT(timer != RT_NULL); RT_ASSERT(arg != RT_NULL); - tim = (struct ra_hwtimer *)timer->parent.user_data; + tim = (struct ra_clock_timer *)timer->parent.user_data; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint8_t index = 0; rt_uint32_t freq = *((rt_uint32_t *)arg); @@ -209,7 +209,7 @@ void timer0_callback(timer_callback_args_t *p_args) if (TIMER_EVENT_CYCLE_END == p_args->event) { - rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER0_INDEX].tmr_device); + rt_clock_timer_isr(&ra_clock_timer_obj[BSP_TIMER0_INDEX].tmr_device); timer_one_shot_check(); } @@ -227,7 +227,7 @@ void timer1_callback(timer_callback_args_t *p_args) if (TIMER_EVENT_CYCLE_END == p_args->event) { - rt_device_hwtimer_isr(&ra_hwtimer_obj[BSP_TIMER1_INDEX].tmr_device); + rt_clock_timer_isr(&ra_clock_timer_obj[BSP_TIMER1_INDEX].tmr_device); timer_one_shot_check(); } @@ -237,7 +237,7 @@ void timer1_callback(timer_callback_args_t *p_args) } #endif -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -246,70 +246,70 @@ static const struct rt_hwtimer_ops _ops = .control = timer_ctrl, }; -static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TMR_DEV_INFO_CONFIG; -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { int result = RT_EOK; - for (int i = 0; i < sizeof(ra_hwtimer_obj) / sizeof(ra_hwtimer_obj[0]); i++) + for (int i = 0; i < sizeof(ra_clock_timer_obj) / sizeof(ra_clock_timer_obj[0]); i++) { - ra_hwtimer_obj[i].tmr_device.info = &_info; - ra_hwtimer_obj[i].tmr_device.ops = &_ops; - if (rt_device_hwtimer_register(&ra_hwtimer_obj[i].tmr_device, ra_hwtimer_obj[i].name, &ra_hwtimer_obj[i]) == RT_EOK) + ra_clock_timer_obj[i].tmr_device.info = &_info; + ra_clock_timer_obj[i].tmr_device.ops = &_ops; + if (rt_clock_timer_register(&ra_clock_timer_obj[i].tmr_device, ra_clock_timer_obj[i].name, &ra_clock_timer_obj[i]) == RT_EOK) { - LOG_D("%s register success", ra_hwtimer_obj[i].name); + LOG_D("%s register success", ra_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", ra_hwtimer_obj[i].name); + LOG_E("%s register failed", ra_clock_timer_obj[i].name); result = -RT_ERROR; } } return result; } -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); +INIT_BOARD_EXPORT(rt_hw_clock_timer_init); -/* This is a hwtimer example */ -#define HWTIMER_DEV_NAME "timer0" /* device name */ +/* This is a clock_timer example */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* device name */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback fucntion!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return RT_EOK; } -int hwtimer_sample(void) +int clock_timer_sample(void) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; rt_uint32_t freq = 1875000; /* 1Mhz */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } rt_device_set_rx_indicate(hw_dev, timeout_cb); - rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq); - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -325,12 +325,12 @@ int hwtimer_sample(void) return -RT_ERROR; } - /* read hwtimer value */ + /* read clock_timer value */ rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); return ret; } -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.h b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.h similarity index 85% rename from bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.h rename to bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.h index 8ef599f11a..6959cf14a2 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drivers/drv_hwtimer.h +++ b/bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.h @@ -12,7 +12,7 @@ #define __TMR_CONFIG_H__ #include -#include +#include #include #include @@ -21,9 +21,9 @@ extern "C" { #endif -struct ra_hwtimer +struct ra_clock_timer { - rt_hwtimer_t tmr_device; + rt_clock_timer_t tmr_device; gpt_instance_ctrl_t *g_ctrl; timer_instance_t const *const g_timer; timer_cfg_t const *const g_cfg; diff --git a/bsp/renesas/ra4m1-ek/board/Kconfig b/bsp/renesas/ra4m1-ek/board/Kconfig index ca3cf60f24..5b4af52dca 100644 --- a/bsp/renesas/ra4m1-ek/board/Kconfig +++ b/bsp/renesas/ra4m1-ek/board/Kconfig @@ -102,7 +102,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/renesas/ra6m3-ek/board/Kconfig b/bsp/renesas/ra6m3-ek/board/Kconfig index 8f521ddd57..e9c001c0ba 100644 --- a/bsp/renesas/ra6m3-ek/board/Kconfig +++ b/bsp/renesas/ra6m3-ek/board/Kconfig @@ -108,7 +108,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/renesas/ra8p1-titan-board/README.md b/bsp/renesas/ra8p1-titan-board/README.md index ac88be7d63..57c3f4cc72 100644 --- a/bsp/renesas/ra8p1-titan-board/README.md +++ b/bsp/renesas/ra8p1-titan-board/README.md @@ -33,7 +33,7 @@ The current peripheral support status in this BSP is as follows: | ---------------------- | ------------------ | --------------------------- | ------------------ | | UART | Supported | LWIP | Supported | | GPIO | Supported | TCP/UDP | Supported | -| HWTIMER | Supported | MQTT | Supported | +| CLOCK_TIMER | Supported | MQTT | Supported | | I2C | Supported | TFTP | Supported | | WDT | Supported | Telnet | Supported | | RTC | Supported | **Multicore Communication** | **Support Status** | diff --git a/bsp/renesas/ra8p1-titan-board/README_zh.md b/bsp/renesas/ra8p1-titan-board/README_zh.md index 10640f7a38..6d718343bb 100644 --- a/bsp/renesas/ra8p1-titan-board/README_zh.md +++ b/bsp/renesas/ra8p1-titan-board/README_zh.md @@ -33,7 +33,7 @@ Titan Board 搭载频率 1GHz Arm® Cortex®-M85 与 250MHz Arm® Cortex®-M33 | ------------ | ------------ | -------- | ------------ | | UART | 支持 | LWIP | 支持 | | GPIO | 支持 | TCP/UDP | 支持 | -| HWTIMER | 支持 | MQTT | 支持 | +| CLOCK_TIMER | 支持 | MQTT | 支持 | | IIC | 支持 | TFTP | 支持 | | WDT | 支持 | Telnet | 支持 | | RTC | 支持 | **多核通信** | **支持情况** | diff --git a/bsp/renesas/ra8p1-titan-board/board/Kconfig b/bsp/renesas/ra8p1-titan-board/board/Kconfig index 0deed2ea17..7d1e754f49 100644 --- a/bsp/renesas/ra8p1-titan-board/board/Kconfig +++ b/bsp/renesas/ra8p1-titan-board/board/Kconfig @@ -638,7 +638,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/renesas/rzn2l_etherkit/board/Kconfig b/bsp/renesas/rzn2l_etherkit/board/Kconfig index c003e8fb1f..e4cff33116 100644 --- a/bsp/renesas/rzn2l_etherkit/board/Kconfig +++ b/bsp/renesas/rzn2l_etherkit/board/Kconfig @@ -497,7 +497,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/renesas/rzn2l_rsk/board/Kconfig b/bsp/renesas/rzn2l_rsk/board/Kconfig index 46693461eb..9060c7c18d 100644 --- a/bsp/renesas/rzn2l_rsk/board/Kconfig +++ b/bsp/renesas/rzn2l_rsk/board/Kconfig @@ -136,7 +136,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/renesas/rzt2m_rsk/board/Kconfig b/bsp/renesas/rzt2m_rsk/board/Kconfig index 89f3b5435f..aa374df16f 100644 --- a/bsp/renesas/rzt2m_rsk/board/Kconfig +++ b/bsp/renesas/rzt2m_rsk/board/Kconfig @@ -84,7 +84,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/rockchip/dm/hwtimer/Kconfig b/bsp/rockchip/dm/hwtimer/Kconfig index ee60464d69..7bfac13baf 100755 --- a/bsp/rockchip/dm/hwtimer/Kconfig +++ b/bsp/rockchip/dm/hwtimer/Kconfig @@ -1,3 +1,5 @@ -config RT_HWTIMER_ROCKCHIP +config RT_CLOCK_TIMER_ROCKCHIP bool "RockChip Timer" + depends on RT_USING_DM + depends on RT_USING_CLOCK_TIME default n diff --git a/bsp/rockchip/dm/hwtimer/SConscript b/bsp/rockchip/dm/hwtimer/SConscript index 999034bf7f..3e9799e775 100755 --- a/bsp/rockchip/dm/hwtimer/SConscript +++ b/bsp/rockchip/dm/hwtimer/SConscript @@ -4,8 +4,8 @@ cwd = GetCurrentDir() src = [] CPPPATH = [cwd + '/../include'] -if GetDepend(['RT_HWTIMER_ROCKCHIP']): - src += ['hwtimer-rockchip_timer.c'] +if GetDepend(['RT_CLOCK_TIMER_ROCKCHIP']): + src += ['clock_timer-rockchip_timer.c'] group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/rockchip/dm/hwtimer/hwtimer-rockchip_timer.c b/bsp/rockchip/dm/hwtimer/clock_timer-rockchip_timer.c old mode 100755 new mode 100644 similarity index 62% rename from bsp/rockchip/dm/hwtimer/hwtimer-rockchip_timer.c rename to bsp/rockchip/dm/hwtimer/clock_timer-rockchip_timer.c index ac77ca1f36..488b48aade --- a/bsp/rockchip/dm/hwtimer/hwtimer-rockchip_timer.c +++ b/bsp/rockchip/dm/hwtimer/clock_timer-rockchip_timer.c @@ -8,17 +8,30 @@ * 2022-12-06 GuEe-GUI first version */ +#define DBG_TAG "drv.rk_timer" +#define DBG_LVL DBG_INFO +#include + #include #include #include -#define TIMER_LOAD_COUNT0 0x00 -#define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CURRENT_VALUE0 0x08 -#define TIMER_CURRENT_VALUE1 0x0c -#define TIMER_CONTROL_REG3288 0x10 -#define TIMER_CONTROL_REG3399 0x1c -#define TIMER_INT_STATUS 0x18 +#ifdef RT_USING_CLOCK_TIME +#include +#endif + +#define HZ 100 +#define KHZ 1000 +#define MHZ 1000000 +#define OSC_HZ (24 * MHZ) + +#define TIMER_LOAD_COUNT0 0x00 +#define TIMER_LOAD_COUNT1 0x04 +#define TIMER_CURRENT_VALUE0 0x08 +#define TIMER_CURRENT_VALUE1 0x0c +#define TIMER_CONTROL_REG3288 0x10 +#define TIMER_CONTROL_REG3399 0x1c +#define TIMER_INT_STATUS 0x18 #define TIMER_DISABLE 0x0 #define TIMER_ENABLE 0x1 @@ -26,11 +39,9 @@ #define TIMER_MODE_USER_DEFINED_COUNT (1 << 1) #define TIMER_INT_UNMASK (1 << 2) -#define HZ 100 - struct rk_timer { - struct rt_hwtimer_device parent; + struct rt_clock_timer_device parent; void *base; void *ctrl; @@ -42,9 +53,21 @@ struct rk_timer rt_uint32_t cycle; rt_bool_t status; - struct rt_hwtimer_info info; + struct rt_clock_timer_info info; }; +#ifdef RT_USING_CLOCK_TIME +struct hrt_timer +{ + struct rk_timer *timer; + uint64_t cnt; + void (*outcb)(void *param); + void *param; +}; +static struct hrt_timer _timer0 = {0}; +static struct rt_spinlock _spinlock; +#endif + #define raw_to_rk_timer(raw) rt_container_of(raw, struct rk_timer, parent) struct rk_timer_data @@ -78,24 +101,24 @@ static void rk_timer_interrupt_clear(struct rk_timer *timer) HWREG32(timer->base + TIMER_INT_STATUS) = 1; } -static void rk_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void rk_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { } -static rt_err_t rk_timer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t rk_timer_start(struct rt_clock_timer_device *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { rt_err_t err = RT_EOK; struct rk_timer *rk_timer = raw_to_rk_timer(timer); switch (mode) { - case HWTIMER_MODE_ONESHOT: + case CLOCK_TIMER_MODE_ONESHOT: rk_timer_disable(rk_timer); rk_timer_update_counter(cnt, rk_timer); rk_timer_enable(rk_timer, TIMER_MODE_USER_DEFINED_COUNT | TIMER_INT_UNMASK); break; - case HWTIMER_MODE_PERIOD: + case CLOCK_TIMER_MODE_PERIOD: rk_timer_disable(rk_timer); rk_timer_update_counter(rk_timer->freq / HZ - 1, rk_timer); rk_timer_enable(rk_timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK); @@ -115,7 +138,7 @@ static rt_err_t rk_timer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, return err; } -static void rk_timer_stop(struct rt_hwtimer_device *timer) +static void rk_timer_stop(struct rt_clock_timer_device *timer) { struct rk_timer *rk_timer = raw_to_rk_timer(timer); @@ -123,29 +146,29 @@ static void rk_timer_stop(struct rt_hwtimer_device *timer) rk_timer_disable(rk_timer); } -static rt_uint32_t rk_timer_count_get(struct rt_hwtimer_device *timer) +static rt_uint32_t rk_timer_count_get(struct rt_clock_timer_device *timer) { struct rk_timer *rk_timer = raw_to_rk_timer(timer); return rk_timer_current_value(rk_timer); } -static rt_err_t rk_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args) +static rt_err_t rk_timer_ctrl(struct rt_clock_timer_device *timer, rt_uint32_t cmd, void *args) { rt_err_t err = RT_EOK; struct rk_timer *rk_timer = raw_to_rk_timer(timer); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: err = -RT_ENOSYS; break; - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: rk_timer_stop(timer); break; - case HWTIMER_CTRL_INFO_GET: + case CLOCK_TIMER_CTRL_INFO_GET: if (args) { rt_memcpy(args, &rk_timer->info, sizeof(rk_timer->info)); @@ -156,8 +179,8 @@ static rt_err_t rk_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, } break; - case HWTIMER_CTRL_MODE_SET: - err = rk_timer_start(timer, rk_timer->cycle, (rt_hwtimer_mode_t)args); + case CLOCK_TIMER_CTRL_MODE_SET: + err = rk_timer_start(timer, rk_timer->cycle, (rt_clock_timer_mode_t)args); break; default: @@ -168,7 +191,7 @@ static rt_err_t rk_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, return err; } -const static struct rt_hwtimer_ops rk_timer_ops = +const static struct rt_clock_timer_ops rk_timer_ops = { .init = rk_timer_init, .start = rk_timer_start, @@ -179,13 +202,25 @@ const static struct rt_hwtimer_ops rk_timer_ops = static void rk_timer_isr(int irqno, void *param) { - struct rk_timer *rk_timer = (struct rk_timer *)param; + struct hrt_timer *timer = &_timer0; + struct rk_timer *time = timer->timer; + + rk_timer_interrupt_clear(time); + + rt_clock_hrtimer_process(); +} - rk_timer_interrupt_clear(rk_timer); +void rt_clock_hrtimer_bind(rt_bitmap_t *affinity) +{ + struct rk_timer *timer = _timer0.timer; - if (rk_timer->status) + if (rt_pic_irq_set_affinity(timer->irq, affinity) == -RT_ENOSYS) { - rt_device_hwtimer_isr(&rk_timer->parent); + LOG_E("timer irq affinity init fail\n"); + } + else + { + LOG_D("timer irq(%d) binding done\n", timer->irq); } } @@ -222,6 +257,11 @@ static rt_err_t rk_timer_probe(struct rt_platform_device *pdev) return -RT_ENOMEM; } +#ifdef RT_USING_CLOCK_TIME + _timer0.timer = timer; + rt_spin_lock_init(&_spinlock); +#endif + if (rt_is_err(timer->pclk = rt_clk_get_by_name(dev, "pclk"))) { err = rt_ptr_err(timer->pclk); @@ -263,14 +303,25 @@ static rt_err_t rk_timer_probe(struct rt_platform_device *pdev) timer->info.maxfreq = timer->freq; timer->info.minfreq = timer->freq; timer->info.maxcnt = 0xffffffff; - timer->info.cntmode = HWTIMER_CNTMODE_UP; + timer->info.cntmode = CLOCK_TIMER_CNTMODE_DW; rt_dm_dev_set_name_auto(&timer->parent.parent, "timer"); dev_name = rt_dm_dev_get_name(&timer->parent.parent); - rt_device_hwtimer_register(&timer->parent, dev_name, RT_NULL); - rt_hw_interrupt_install(timer->irq, rk_timer_isr, timer, dev_name); - rt_hw_interrupt_umask(timer->irq); + rt_clock_timer_register(&timer->parent, dev_name, RT_NULL); + + RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = { 0 }; + rt_bitmap_set_bit(affinity, RT_CPUS_NR - 1); + rt_clock_hrtimer_bind(affinity); + + rt_pic_attach_irq(timer->irq, rk_timer_isr, timer, dev_name, RT_IRQ_F_NONE); + rt_pic_irq_unmask(timer->irq); + +#if KTIMER_BIND_CPU + RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = {0}; + rt_bitmap_set_bit(affinity, 1); + rt_pic_irq_set_affinity(timer->irq, affinity); +#endif return RT_EOK; @@ -306,6 +357,44 @@ static const struct rk_timer_data rk3399_timer_data = .ctrl_reg = TIMER_CONTROL_REG3399, }; +#ifdef RT_USING_CLOCK_TIME + +uint64_t rt_clock_hrtimer_getfrq(void) +{ + return OSC_HZ; +} + +uint64_t rt_clock_hrtimer_getres(void) +{ + return ((1000UL * 1000 * 1000) * RT_CLOCK_TIME_RESMUL) / OSC_HZ; +} + +/** + * @brief set the timeout function for hrtimer framework + * + * @warning application should not call this API directly + * + * @param cnt the count of timer dealy + * @return rt_err_t 0 forever + */ +rt_err_t rt_clock_hrtimer_settimeout(unsigned long cnt) +{ + struct hrt_timer *timer = &_timer0; + struct rk_timer *time = timer->timer; + + timer->cnt = cnt; + + if (cnt) + { + rk_timer_disable(time); + rk_timer_update_counter(cnt, time); + rk_timer_enable(time, TIMER_MODE_USER_DEFINED_COUNT | TIMER_INT_UNMASK); + } + + return 0; +} +#endif + static const struct rt_ofw_node_id rk_timer_ofw_ids[] = { { .compatible = "rockchip,rk3288-timer", .data = &rk3288_timer_data }, @@ -315,7 +404,7 @@ static const struct rt_ofw_node_id rk_timer_ofw_ids[] = static struct rt_platform_driver rk_timer_driver = { - .name = "hwtimer-rockchip", + .name = "clock_timer-rockchip", .ids = rk_timer_ofw_ids, .probe = rk_timer_probe, diff --git a/bsp/rockchip/rk3500/.config b/bsp/rockchip/rk3500/.config index fed7587c00..fc4a8cde21 100644 --- a/bsp/rockchip/rk3500/.config +++ b/bsp/rockchip/rk3500/.config @@ -392,7 +392,8 @@ CONFIG_RT_PIN_ROCKCHIP=y CONFIG_RT_USING_PINCTRL=y # CONFIG_RT_PINCTRL_SINGLE is not set CONFIG_RT_PINCTRL_ROCKCHIP=y -CONFIG_RT_USING_KTIME=y +CONFIG_RT_USING_CLOCK_TIME=y +CONFIG_RT_CLOCK_TIME_ARM_ARCH=y CONFIG_RT_USING_CLK=y CONFIG_RT_CLK_ROCKCHIP_LINK=y CONFIG_RT_CLK_ROCKCHIP=y @@ -400,9 +401,7 @@ CONFIG_RT_CLK_ROCKCHIP=y CONFIG_RT_CLK_ROCKCHIP_RK3568=y # CONFIG_RT_CLK_ROCKCHIP_RK3576 is not set CONFIG_RT_CLK_ROCKCHIP_RK3588=y -CONFIG_RT_USING_HWTIMER=y -CONFIG_RT_HWTIMER_ARM_ARCH=y -CONFIG_RT_HWTIMER_ROCKCHIP=y +CONFIG_RT_CLOCK_TIMER_ROCKCHIP=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -1000,6 +999,7 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set # end of tools packages # @@ -1094,6 +1094,7 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -1250,6 +1251,12 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1298,6 +1305,7 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1768,3 +1776,4 @@ CONFIG_PKG_ZLIB_VER="latest" # end of RT-Thread online packages CONFIG_SOC_RK3500=y +CONFIG_SOC_RK3568=y diff --git a/bsp/rockchip/rk3500/driver/board.c b/bsp/rockchip/rk3500/driver/board.c index c469931882..e2e14a6994 100644 --- a/bsp/rockchip/rk3500/driver/board.c +++ b/bsp/rockchip/rk3500/driver/board.c @@ -9,8 +9,24 @@ */ #include +#include +#include +#include + +static void rk3568_machine_shutdown(void) +{ + psci_system_off(); +} void rt_hw_board_init(void) { rt_hw_common_setup(); + rt_dm_machine_shutdown = rk3568_machine_shutdown; + rt_dm_machine_reset = psci_system_reboot; +} + +void reboot(void) +{ + psci_system_reboot(); } +MSH_CMD_EXPORT(reboot, reboot...); diff --git a/bsp/rockchip/rk3500/rtconfig.h b/bsp/rockchip/rk3500/rtconfig.h index 6897ff3729..0518bc0e16 100644 --- a/bsp/rockchip/rk3500/rtconfig.h +++ b/bsp/rockchip/rk3500/rtconfig.h @@ -247,15 +247,14 @@ #define RT_PIN_ROCKCHIP #define RT_USING_PINCTRL #define RT_PINCTRL_ROCKCHIP -#define RT_USING_KTIME +#define RT_USING_CLOCK_TIME #define RT_USING_CLK #define RT_CLK_ROCKCHIP_LINK #define RT_CLK_ROCKCHIP #define RT_CLK_ROCKCHIP_RK3568 #define RT_CLK_ROCKCHIP_RK3588 -#define RT_USING_HWTIMER -#define RT_HWTIMER_ARM_ARCH -#define RT_HWTIMER_ROCKCHIP +#define RT_CLOCK_TIME_ARM_ARCH +#define RT_CLOCK_TIMER_ROCKCHIP /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -595,6 +594,10 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -677,5 +680,6 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ #define SOC_RK3500 +#define SOC_RK3568 #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/tim_config.h index 82f0a2375f..55abb16237 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/tim_config.h index 735bf7b70d..d3a685ac28 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/tim_config.h index 3e2a606f6e..19347c25f3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/tim_config.h index a80ce58de6..68e0ec2c6a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/tim_config.h index 08646d9af7..c6e1ee581a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/tim_config.h @@ -24,7 +24,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/tim_config.h index 6c397f087b..bf7fd577b8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/tim_config.h index 4c3691353b..200255dfb4 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/tim_config.h @@ -24,7 +24,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/tim_config.h index 856a437d0b..6e450ccde7 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/tim_config.h @@ -24,7 +24,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h index 794289d88a..507bcff446 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/lptim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/tim_config.h index 6c397f087b..bf7fd577b8 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/tim_config.h index 735bf7b70d..d3a685ac28 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/tim_config.h index ed4100a9c7..0024d41823 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/tim_config.h index eca2f6ddde..f049572c2a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/tim_config.h index 2742f70c71..1528817033 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/mp1/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/tim_config.h index eca2f6ddde..f049572c2a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h index 1aa956e255..0e8ae50b6a 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/tim_config.h @@ -23,7 +23,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/tim_config.h index f85bea7b1c..05118d7ac5 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/tim_config.h @@ -24,7 +24,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #else #define TIM_DEV_INFO_CONFIG \ @@ -32,7 +32,7 @@ extern "C" { .maxfreq = 1000000, \ .minfreq = 2000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif #endif /* TIM_DEV_INFO_CONFIG */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c index 192343f5be..cfcf540531 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.c @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2019-05-06 Zero-Free first version - * 2024-07-04 wdfk-prog lptimer is register with hwtimer, only supports pm calls,the timer function is not supported + * 2024-07-04 wdfk-prog lptimer is register with clock_timer, only supports pm calls,the timer function is not supported */ #include @@ -37,7 +37,7 @@ enum struct stm32_hw_lptimer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; LPTIM_HandleTypeDef tim_handle; IRQn_Type tim_irqn; char *name; @@ -56,9 +56,9 @@ static struct stm32_hw_lptimer stm32_hw_lptimer_obj[] = #endif }; -static const struct rt_hwtimer_info _info = LPTIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = LPTIM_DEV_INFO_CONFIG; -static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { if(timer == RT_NULL) { @@ -118,7 +118,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { if(timer == RT_NULL) { @@ -153,7 +153,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ } } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { if(timer == RT_NULL) { @@ -193,13 +193,13 @@ static rt_uint32_t timer_get_freq(LPTIM_HandleTypeDef *tim) } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { LPTIM_HandleTypeDef *tim = (LPTIM_HandleTypeDef *)timer->parent.user_data; return HAL_LPTIM_ReadCounter(tim); } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { if(timer == RT_NULL) { @@ -236,7 +236,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) } case DRV_HW_LPTIMER_CTRL_START: { - timer_start(timer, *(rt_uint32_t *)arg, HWTIMER_MODE_ONESHOT); + timer_start(timer, *(rt_uint32_t *)arg, CLOCK_TIMER_MODE_ONESHOT); break; } case DRV_HW_LPTIMER_CTRL_GET_COUNT: @@ -281,7 +281,7 @@ void LPTIM3_IRQHandler(void) } #endif -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -302,7 +302,7 @@ static int stm32_hw_lptim_init(void) { stm32_hw_lptimer_obj[i].time_device.info = &_info; stm32_hw_lptimer_obj[i].time_device.ops = &_ops; - if (rt_device_hwtimer_register(&stm32_hw_lptimer_obj[i].time_device, stm32_hw_lptimer_obj[i].name, &stm32_hw_lptimer_obj[i].tim_handle) == RT_EOK) + if (rt_clock_timer_register(&stm32_hw_lptimer_obj[i].time_device, stm32_hw_lptimer_obj[i].name, &stm32_hw_lptimer_obj[i].tim_handle) == RT_EOK) { LOG_D("%s register success", stm32_hw_lptimer_obj[i].name); } diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h index 124242abb5..203edba439 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_lptim.h @@ -6,7 +6,7 @@ * Change Logs: * Date Author Notes * 2019-05-06 Zero-Free first version - * 2024-07-04 wdfk-prog lptimer is register with hwtimer, only supports pm calls,the timer function is not supported + * 2024-07-04 wdfk-prog lptimer is register with clock_timer, only supports pm calls,the timer function is not supported */ #ifndef __DRV_PMTIMER_H__ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c index 2b93c30f94..eaf39d8b14 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_pm.c @@ -203,7 +203,7 @@ static void pm_timer_stop(struct rt_pm *pm) RT_ASSERT(pm != RT_NULL); /* Reset pmtimer status */ - rt_device_control(timer, HWTIMER_CTRL_STOP, RT_NULL); + rt_device_control(timer, CLOCK_TIMER_CTRL_STOP, RT_NULL); } /** diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c index 4533df7a64..b236a7ffdd 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_tim.c @@ -298,15 +298,15 @@ enum #endif }; -struct stm32_hwtimer +struct stm32_clock_timer { - rt_hwtimer_t time_device; + rt_clock_timer_t time_device; TIM_HandleTypeDef tim_handle; IRQn_Type tim_irqn; char *name; }; -static struct stm32_hwtimer stm32_hwtimer_obj[] = +static struct stm32_clock_timer stm32_clock_timer_obj[] = { #ifdef BSP_USING_TIM1 TIM1_CONFIG, @@ -377,18 +377,18 @@ static struct stm32_hwtimer stm32_hwtimer_obj[] = #endif }; -static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { uint32_t prescaler_value = 0; uint32_t pclk1_doubler, pclk2_doubler; TIM_HandleTypeDef *tim = RT_NULL; - struct stm32_hwtimer *tim_device = RT_NULL; + struct stm32_clock_timer *tim_device = RT_NULL; RT_ASSERT(timer != RT_NULL); if (state) { tim = (TIM_HandleTypeDef *)timer->parent.user_data; - tim_device = (struct stm32_hwtimer *)timer; + tim_device = (struct stm32_clock_timer *)timer; stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler); @@ -409,7 +409,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) tim->Init.Period = 10000 - 1; tim->Init.Prescaler = prescaler_value; tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; - if (timer->info->cntmode == HWTIMER_CNTMODE_UP) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { tim->Init.CounterMode = TIM_COUNTERMODE_UP; } @@ -436,7 +436,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) } } -static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; TIM_HandleTypeDef *tim = RT_NULL; @@ -450,7 +450,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ /* set tim arr */ __HAL_TIM_SET_AUTORELOAD(tim, t - 1); - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ tim->Instance->CR1 |= TIM_OPMODE_SINGLE; @@ -470,7 +470,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_ return result; } -static void timer_stop(rt_hwtimer_t *timer) +static void timer_stop(rt_clock_timer_t *timer) { TIM_HandleTypeDef *tim = RT_NULL; @@ -485,7 +485,7 @@ static void timer_stop(rt_hwtimer_t *timer) __HAL_TIM_SET_COUNTER(tim, 0); } -static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { TIM_HandleTypeDef *tim = RT_NULL; rt_err_t result = -RT_ERROR; @@ -498,7 +498,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint16_t val=0; @@ -591,7 +591,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) return result; } -static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) +static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) { TIM_HandleTypeDef *tim = RT_NULL; @@ -602,9 +602,9 @@ static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer) return tim->Instance->CNT; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { .init = timer_init, .start = timer_start, @@ -618,7 +618,7 @@ void TIM2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM2_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -630,10 +630,10 @@ void TIM3_TIM4_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); #ifdef BSP_USING_TIM3 - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM3_INDEX].tim_handle); #endif #ifdef BSP_USING_TIM4 - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM4_INDEX].tim_handle); #endif /* leave interrupt */ rt_interrupt_leave(); @@ -645,7 +645,7 @@ void TIM3_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM3_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -655,7 +655,7 @@ void TIM4_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM4_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -666,7 +666,7 @@ void TIM5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM5_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -676,7 +676,7 @@ void TIM6_DAC_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM6_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM6_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -686,7 +686,7 @@ void TIM7_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM7_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM7_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -696,7 +696,7 @@ void TIM8_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM8_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM8_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -706,7 +706,7 @@ void TIM1_TRG_COM_TIM11_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM11_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -716,7 +716,7 @@ void TIM8_UP_TIM13_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM13_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -730,7 +730,7 @@ void TIM8_UP_TIM13_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM14_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -740,7 +740,7 @@ void TIM1_BRK_TIM15_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM15_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -754,7 +754,7 @@ void TIM1_BRK_TIM15_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM16_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -768,7 +768,7 @@ void TIM1_BRK_TIM15_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle); + HAL_TIM_IRQHandler(&stm32_clock_timer_obj[TIM17_INDEX].tim_handle); /* leave interrupt */ rt_interrupt_leave(); } @@ -779,106 +779,106 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) #ifdef BSP_USING_TIM2 if (htim->Instance == TIM2) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM2_INDEX].time_device); } #endif #ifdef BSP_USING_TIM3 if (htim->Instance == TIM3) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM3_INDEX].time_device); } #endif #ifdef BSP_USING_TIM4 if (htim->Instance == TIM4) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM4_INDEX].time_device); } #endif #ifdef BSP_USING_TIM5 if (htim->Instance == TIM5) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM5_INDEX].time_device); } #endif #ifdef BSP_USING_TIM6 if (htim->Instance == TIM6) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM6_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM6_INDEX].time_device); } #endif #ifdef BSP_USING_TIM7 if (htim->Instance == TIM7) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM7_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM7_INDEX].time_device); } #endif #ifdef BSP_USING_TIM8 if (htim->Instance == TIM8) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM8_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM8_INDEX].time_device); } #endif #ifdef BSP_USING_TIM11 if (htim->Instance == TIM11) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM11_INDEX].time_device); } #endif #ifdef BSP_USING_TIM13 if (htim->Instance == TIM13) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM13_INDEX].time_device); } #endif #ifdef BSP_USING_TIM14 if (htim->Instance == TIM14) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM14_INDEX].time_device); } #endif #ifdef BSP_USING_TIM15 if (htim->Instance == TIM15) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM15_INDEX].time_device); } #endif #ifdef BSP_USING_TIM16 if (htim->Instance == TIM16) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM16_INDEX].time_device); } #endif #ifdef BSP_USING_TIM17 if (htim->Instance == TIM17) { - rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device); + rt_clock_timer_isr(&stm32_clock_timer_obj[TIM17_INDEX].time_device); } #endif } -static int stm32_hwtimer_init(void) +static int stm32_clock_timer_init(void) { rt_uint32_t i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(stm32_clock_timer_obj) / sizeof(stm32_clock_timer_obj[0]); i++) { - stm32_hwtimer_obj[i].time_device.info = &_info; - stm32_hwtimer_obj[i].time_device.ops = &_ops; - if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, - stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK) + stm32_clock_timer_obj[i].time_device.info = &_info; + stm32_clock_timer_obj[i].time_device.ops = &_ops; + if (rt_clock_timer_register(&stm32_clock_timer_obj[i].time_device, + stm32_clock_timer_obj[i].name, &stm32_clock_timer_obj[i].tim_handle) == RT_EOK) { - LOG_D("%s register success", stm32_hwtimer_obj[i].name); + LOG_D("%s register success", stm32_clock_timer_obj[i].name); } else { - LOG_E("%s register failed", stm32_hwtimer_obj[i].name); + LOG_E("%s register failed", stm32_clock_timer_obj[i].name); result = -RT_ERROR; } } return result; } -INIT_BOARD_EXPORT(stm32_hwtimer_init); +INIT_BOARD_EXPORT(stm32_clock_timer_init); #endif /* BSP_USING_TIM */ diff --git a/bsp/stm32/libraries/STM32L1xx_HAL/SConscript b/bsp/stm32/libraries/STM32L1xx_HAL/SConscript index 7859bc2332..7c2b1d785d 100644 --- a/bsp/stm32/libraries/STM32L1xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32L1xx_HAL/SConscript @@ -43,7 +43,7 @@ if GetDepend(['RT_USING_USB']): if GetDepend(['RT_USING_CAN']): src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_can.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']): src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_tim.c'] src += ['STM32L1xx_HAL_Driver/Src/stm32L1xx_hal_tim_ex.c'] diff --git a/bsp/stm32/libraries/templates/stm32f3xx/project.uvoptx b/bsp/stm32/libraries/templates/stm32f3xx/project.uvoptx index ccbafccdba..3d774f94f1 100644 --- a/bsp/stm32/libraries/templates/stm32f3xx/project.uvoptx +++ b/bsp/stm32/libraries/templates/stm32f3xx/project.uvoptx @@ -282,8 +282,8 @@ 0 0 0 - ..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 @@ -482,8 +482,8 @@ 0 0 0 - ..\libraries\HAL_Drivers\drv_hwtimer.c - drv_hwtimer.c + ..\libraries\HAL_Drivers\drv_timer.c + drv_timer.c 0 0 diff --git a/bsp/stm32/libraries/templates/stm32l1xx/board/Kconfig b/bsp/stm32/libraries/templates/stm32l1xx/board/Kconfig index 0650b2dbc4..d95f206f82 100644 --- a/bsp/stm32/libraries/templates/stm32l1xx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32l1xx/board/Kconfig @@ -88,7 +88,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/libraries/templates/stm32wbxx/board/Kconfig b/bsp/stm32/libraries/templates/stm32wbxx/board/Kconfig index e20043c172..1287e9a63f 100644 --- a/bsp/stm32/libraries/templates/stm32wbxx/board/Kconfig +++ b/bsp/stm32/libraries/templates/stm32wbxx/board/Kconfig @@ -123,7 +123,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM16 diff --git a/bsp/stm32/libraries/templates/stm32xx_board_Kconfig b/bsp/stm32/libraries/templates/stm32xx_board_Kconfig index 0cc7a077ba..62fe69fab0 100644 --- a/bsp/stm32/libraries/templates/stm32xx_board_Kconfig +++ b/bsp/stm32/libraries/templates/stm32xx_board_Kconfig @@ -116,7 +116,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM15 bool "Enable TIM15" diff --git a/bsp/stm32/stm32f072-st-nucleo/board/Kconfig b/bsp/stm32/stm32f072-st-nucleo/board/Kconfig index 4aa69b91f2..69900f4061 100644 --- a/bsp/stm32/stm32f072-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f072-st-nucleo/board/Kconfig @@ -135,7 +135,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM7 bool "Enable TIM7" diff --git a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig index 0cd4e49603..d5ea59755e 100644 --- a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig @@ -137,7 +137,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM14 bool "Enable TIM14" diff --git a/bsp/stm32/stm32f103-100ask-pro/board/Kconfig b/bsp/stm32/stm32f103-100ask-pro/board/Kconfig index 60b4bd11df..65919379fc 100644 --- a/bsp/stm32/stm32f103-100ask-pro/board/Kconfig +++ b/bsp/stm32/stm32f103-100ask-pro/board/Kconfig @@ -237,7 +237,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig index b30a684c21..282086aecd 100644 --- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig @@ -149,7 +149,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig b/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig index c8d95d40c6..0d7330f082 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig @@ -162,7 +162,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig index 9482489e81..75787559a1 100644 --- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig +++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig @@ -277,7 +277,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/pins_arduino.h index 2b80505e24..1a314d4fc4 100644 --- a/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/pins_arduino.h +++ b/bsp/stm32/stm32f401-st-nucleo/applications/arduino_pinout/pins_arduino.h @@ -50,6 +50,6 @@ #define SS D10 #define RTDUINO_DEFAULT_SPI_BUS_NAME "spi1" -#define RTDUINO_TONE_HWTIMER_DEVICE_NAME "timer9" +#define RTDUINO_TONE_CLOCK_TIMER_DEVICE_NAME "timer9" #endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32f401-st-nucleo/board/Kconfig b/bsp/stm32/stm32f401-st-nucleo/board/Kconfig index e03d2d2814..a4ddfc0c2c 100644 --- a/bsp/stm32/stm32f401-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f401-st-nucleo/board/Kconfig @@ -104,7 +104,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM9 diff --git a/bsp/stm32/stm32f405zg-mini-template/board/Kconfig b/bsp/stm32/stm32f405zg-mini-template/board/Kconfig index 8e3876b026..80bb0b0522 100644 --- a/bsp/stm32/stm32f405zg-mini-template/board/Kconfig +++ b/bsp/stm32/stm32f405zg-mini-template/board/Kconfig @@ -107,7 +107,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM6 bool "Enable TIM6" diff --git a/bsp/stm32/stm32f407-armfly-v5/board/Kconfig b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig index 5055463e32..613d1cfb85 100644 --- a/bsp/stm32/stm32f407-armfly-v5/board/Kconfig +++ b/bsp/stm32/stm32f407-armfly-v5/board/Kconfig @@ -164,7 +164,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index b88d55f8cd..1cd3f3eb67 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -384,7 +384,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f407-fk407m2-zgt6/board/Kconfig b/bsp/stm32/stm32f407-fk407m2-zgt6/board/Kconfig index 6669b21f72..97bf737ac2 100644 --- a/bsp/stm32/stm32f407-fk407m2-zgt6/board/Kconfig +++ b/bsp/stm32/stm32f407-fk407m2-zgt6/board/Kconfig @@ -242,7 +242,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig b/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig index 9b8c3bbb19..606c772551 100644 --- a/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig +++ b/bsp/stm32/stm32f407-lckfb-skystar/board/Kconfig @@ -269,7 +269,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f407-micu/board/Kconfig b/bsp/stm32/stm32f407-micu/board/Kconfig index fc65f2af28..25202dfa2f 100644 --- a/bsp/stm32/stm32f407-micu/board/Kconfig +++ b/bsp/stm32/stm32f407-micu/board/Kconfig @@ -177,7 +177,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f407-rt-spark/board/Kconfig b/bsp/stm32/stm32f407-rt-spark/board/Kconfig index ca3ab2c321..a003330564 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/Kconfig +++ b/bsp/stm32/stm32f407-rt-spark/board/Kconfig @@ -490,7 +490,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f411-atk-nano/board/Kconfig b/bsp/stm32/stm32f411-atk-nano/board/Kconfig index ec936d9025..fbb264b09d 100644 --- a/bsp/stm32/stm32f411-atk-nano/board/Kconfig +++ b/bsp/stm32/stm32f411-atk-nano/board/Kconfig @@ -116,7 +116,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/pins_arduino.h index 4281578659..504b746427 100644 --- a/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/pins_arduino.h +++ b/bsp/stm32/stm32f411-st-nucleo/applications/arduino_pinout/pins_arduino.h @@ -50,6 +50,6 @@ #define SS D10 #define RTDUINO_DEFAULT_SPI_BUS_NAME "spi1" -#define RTDUINO_TONE_HWTIMER_DEVICE_NAME "timer9" +#define RTDUINO_TONE_CLOCK_TIMER_DEVICE_NAME "timer9" #endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32f411-st-nucleo/board/Kconfig b/bsp/stm32/stm32f411-st-nucleo/board/Kconfig index ae4f9ac01e..9c4c0c3466 100644 --- a/bsp/stm32/stm32f411-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f411-st-nucleo/board/Kconfig @@ -210,7 +210,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM9 bool "Enable TIM9" diff --git a/bsp/stm32/stm32f411-weact-blackpill/board/Kconfig b/bsp/stm32/stm32f411-weact-blackpill/board/Kconfig index afdbf51658..691cabbf34 100644 --- a/bsp/stm32/stm32f411-weact-blackpill/board/Kconfig +++ b/bsp/stm32/stm32f411-weact-blackpill/board/Kconfig @@ -211,7 +211,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM10 bool "Enable TIM10" diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/pins_arduino.h index 249f0e7e77..9840fd7f99 100644 --- a/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/pins_arduino.h +++ b/bsp/stm32/stm32f412-st-nucleo/applications/arduino_pinout/pins_arduino.h @@ -53,6 +53,6 @@ #define SS D10 #define RTDUINO_DEFAULT_SPI_BUS_NAME "spi1" -#define RTDUINO_TONE_HWTIMER_DEVICE_NAME "timer6" +#define RTDUINO_TONE_CLOCK_TIMER_DEVICE_NAME "timer6" #endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32f412-st-nucleo/board/Kconfig b/bsp/stm32/stm32f412-st-nucleo/board/Kconfig index 38b77b90f9..28d5f0e198 100644 --- a/bsp/stm32/stm32f412-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f412-st-nucleo/board/Kconfig @@ -183,7 +183,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM6 bool "Enable TIM6" diff --git a/bsp/stm32/stm32f413-st-nucleo/board/Kconfig b/bsp/stm32/stm32f413-st-nucleo/board/Kconfig index c5738e58e5..cd009d2fe2 100644 --- a/bsp/stm32/stm32f413-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f413-st-nucleo/board/Kconfig @@ -136,7 +136,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig index 3373a8fd27..99b09d498d 100644 --- a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig +++ b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig @@ -166,7 +166,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index 0cd7bc4fde..151792707e 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -278,7 +278,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig index bfe8cff519..c56a1b6a85 100644 --- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig +++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig @@ -186,7 +186,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/pins_arduino.h index ad1360cd07..8dd4453fd4 100644 --- a/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/pins_arduino.h +++ b/bsp/stm32/stm32f469-st-disco/applications/arduino_pinout/pins_arduino.h @@ -54,6 +54,6 @@ #define SS D10 #define RTDUINO_DEFAULT_SPI_BUS_NAME "spi2" -#define RTDUINO_TONE_HWTIMER_DEVICE_NAME "timer6" +#define RTDUINO_TONE_CLOCK_TIMER_DEVICE_NAME "timer6" #endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32f469-st-disco/board/Kconfig b/bsp/stm32/stm32f469-st-disco/board/Kconfig index d1c8dbe962..93b561d474 100644 --- a/bsp/stm32/stm32f469-st-disco/board/Kconfig +++ b/bsp/stm32/stm32f469-st-disco/board/Kconfig @@ -183,7 +183,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM6 bool "Enable TIM6" diff --git a/bsp/stm32/stm32f723-st-disco/project.ewp b/bsp/stm32/stm32f723-st-disco/project.ewp index 174f59043d..6aec292827 100644 --- a/bsp/stm32/stm32f723-st-disco/project.ewp +++ b/bsp/stm32/stm32f723-st-disco/project.ewp @@ -2151,7 +2151,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c diff --git a/bsp/stm32/stm32f723-st-disco/project.uvprojx b/bsp/stm32/stm32f723-st-disco/project.uvprojx index 5298f594c0..4b0e3f910f 100644 --- a/bsp/stm32/stm32f723-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f723-st-disco/project.uvprojx @@ -469,9 +469,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/stm32/stm32f746-st-disco/board/Kconfig b/bsp/stm32/stm32f746-st-disco/board/Kconfig index 120807deb2..dd1f0d0bf6 100644 --- a/bsp/stm32/stm32f746-st-disco/board/Kconfig +++ b/bsp/stm32/stm32f746-st-disco/board/Kconfig @@ -111,7 +111,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32f746-st-disco/project.ewp b/bsp/stm32/stm32f746-st-disco/project.ewp index 1b0a508120..1e709e6cea 100644 --- a/bsp/stm32/stm32f746-st-disco/project.ewp +++ b/bsp/stm32/stm32f746-st-disco/project.ewp @@ -2151,7 +2151,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c diff --git a/bsp/stm32/stm32f746-st-disco/project.uvprojx b/bsp/stm32/stm32f746-st-disco/project.uvprojx index 40a682b162..b2bc254a6c 100644 --- a/bsp/stm32/stm32f746-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f746-st-disco/project.uvprojx @@ -468,9 +468,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/stm32/stm32f746-st-nucleo/board/Kconfig b/bsp/stm32/stm32f746-st-nucleo/board/Kconfig index 2d7eacf753..224cd13c3c 100644 --- a/bsp/stm32/stm32f746-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f746-st-nucleo/board/Kconfig @@ -183,7 +183,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index b864a41c2c..0bb7894b0c 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -186,7 +186,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM11 bool "Enable TIM11" diff --git a/bsp/stm32/stm32g070-st-nucleo/board/Kconfig b/bsp/stm32/stm32g070-st-nucleo/board/Kconfig index 8d6190005e..bbf6869bc4 100644 --- a/bsp/stm32/stm32g070-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32g070-st-nucleo/board/Kconfig @@ -129,7 +129,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 diff --git a/bsp/stm32/stm32g071-st-nucleo/board/Kconfig b/bsp/stm32/stm32g071-st-nucleo/board/Kconfig index 2f18269e64..899c308fb4 100644 --- a/bsp/stm32/stm32g071-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32g071-st-nucleo/board/Kconfig @@ -121,7 +121,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 diff --git a/bsp/stm32/stm32g491-st-nucleo/board/Kconfig b/bsp/stm32/stm32g491-st-nucleo/board/Kconfig index c1c027d8d2..9f0dcc5373 100644 --- a/bsp/stm32/stm32g491-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32g491-st-nucleo/board/Kconfig @@ -235,7 +235,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM7 bool "Enable TIM7" diff --git a/bsp/stm32/stm32h743-openmv-h7plus/project.ewp b/bsp/stm32/stm32h743-openmv-h7plus/project.ewp index 2f62b9c880..74475b8ee5 100644 --- a/bsp/stm32/stm32h743-openmv-h7plus/project.ewp +++ b/bsp/stm32/stm32h743-openmv-h7plus/project.ewp @@ -2165,7 +2165,7 @@ $PROJ_DIR$\..\..\..\components\drivers\core\device.c - $PROJ_DIR$\..\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c diff --git a/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx b/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx index 7577c5e144..d6b51695b2 100644 --- a/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx +++ b/bsp/stm32/stm32h743-openmv-h7plus/project.uvprojx @@ -469,9 +469,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/stm32/stm32h750-artpi/board/Kconfig b/bsp/stm32/stm32h750-artpi/board/Kconfig index 54f1c97c05..68b2ed588d 100644 --- a/bsp/stm32/stm32h750-artpi/board/Kconfig +++ b/bsp/stm32/stm32h750-artpi/board/Kconfig @@ -242,7 +242,7 @@ menu "On-chip Peripheral Drivers" bool "Enable lptimer" default n select RT_USING_LPTIMER - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_LPTIM config BSP_USING_LPTIM1 bool "Enable LPTIM1" diff --git a/bsp/stm32/stm32l433-ali-startkit/board/Kconfig b/bsp/stm32/stm32l433-ali-startkit/board/Kconfig index e435fd49a7..d42f7465c5 100644 --- a/bsp/stm32/stm32l433-ali-startkit/board/Kconfig +++ b/bsp/stm32/stm32l433-ali-startkit/board/Kconfig @@ -203,7 +203,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM15 bool "Enable TIM15" diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/pins_arduino.h index 69578f337f..79fe8c6ce4 100644 --- a/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/pins_arduino.h +++ b/bsp/stm32/stm32l475-atk-pandora/applications/arduino_pinout/pins_arduino.h @@ -70,7 +70,7 @@ /* Serial2 - PA2-TX PA3-RX */ #define RTDUINO_SERIAL2_DEVICE_NAME "uart2" -#define RTDUINO_TONE_HWTIMER_DEVICE_NAME "timer7" +#define RTDUINO_TONE_CLOCK_TIMER_DEVICE_NAME "timer7" /* I2C */ #if defined(BSP_USING_ARDUINO_AHT10) diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig index bb300ec0e2..de2fc8ce25 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig +++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig @@ -478,7 +478,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM7 bool "Enable TIM7" diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/pins_arduino.h b/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/pins_arduino.h index e7362a43d0..4c00425203 100644 --- a/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/pins_arduino.h +++ b/bsp/stm32/stm32l476-st-nucleo/applications/arduino_pinout/pins_arduino.h @@ -50,6 +50,6 @@ #define SS D10 #define RTDUINO_DEFAULT_SPI_BUS_NAME "spi1" -#define RTDUINO_TONE_HWTIMER_DEVICE_NAME "timer7" +#define RTDUINO_TONE_CLOCK_TIMER_DEVICE_NAME "timer7" #endif /* Pins_Arduino_h */ diff --git a/bsp/stm32/stm32l476-st-nucleo/board/Kconfig b/bsp/stm32/stm32l476-st-nucleo/board/Kconfig index ebbeebb534..a8e9ee55f3 100644 --- a/bsp/stm32/stm32l476-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32l476-st-nucleo/board/Kconfig @@ -188,7 +188,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM7 bool "Enable TIM7" diff --git a/bsp/stm32/stm32l496-ali-developer/board/Kconfig b/bsp/stm32/stm32l496-ali-developer/board/Kconfig index 7c554b11ae..56643f8cdd 100644 --- a/bsp/stm32/stm32l496-ali-developer/board/Kconfig +++ b/bsp/stm32/stm32l496-ali-developer/board/Kconfig @@ -211,7 +211,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM15 bool "Enable TIM15" diff --git a/bsp/stm32/stm32l496-st-nucleo/.ci/attachconfig/ci.attachconfig.yml b/bsp/stm32/stm32l496-st-nucleo/.ci/attachconfig/ci.attachconfig.yml index 98c22f549d..21dbe5769b 100644 --- a/bsp/stm32/stm32l496-st-nucleo/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/stm32/stm32l496-st-nucleo/.ci/attachconfig/ci.attachconfig.yml @@ -64,6 +64,7 @@ pkg.kernel_en_sample: - CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER=y pkg.peripheral.sample: kconfig: + - CONFIG_RT_USING_CLOCK_TIME=y - CONFIG_PKG_USING_PERIPHERAL_SAMPLES=y - CONFIG_PERIPHERAL_SAMPLES_USING_ADC=y - CONFIG_PERIPHERAL_SAMPLES_USING_HWTIMER=y diff --git a/bsp/stm32/stm32l496-st-nucleo/board/Kconfig b/bsp/stm32/stm32l496-st-nucleo/board/Kconfig index 2787a7174b..f0c35b330a 100644 --- a/bsp/stm32/stm32l496-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32l496-st-nucleo/board/Kconfig @@ -207,7 +207,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM7 bool "Enable TIM7" diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig index 1858c87a37..24bbfa4351 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig @@ -323,7 +323,7 @@ menu "Hardware Drivers Config" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig index 8a564292bf..05c61bf8b9 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig @@ -183,7 +183,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM14 bool "Enable TIM14" diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c index 50c87ad0c8..402902db3f 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c @@ -15,7 +15,7 @@ #include #include -#define HWTIMER_DEV_NAME "timer14" +#define CLOCK_TIMER_DEV_NAME "timer14" #define HWADC_DEV_NAME "adc2" #define REFER_VOLTAGE 330 /* voltage reference */ #define CONVERT_BITS (1 << 12) /* Conversion digit */ @@ -37,22 +37,22 @@ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) return 0; } -static int hwtimer_stop(void) +static int clock_timer_stop(void) { rt_err_t ret = RT_EOK; rt_device_t hw_dev = RT_NULL; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } ret = rt_device_close(hw_dev); if (ret != RT_EOK) { - rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("close %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } @@ -62,18 +62,18 @@ static int hwtimer_stop(void) return ret; } -static int hwtimer_start(void) +static int clock_timer_start(void) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } @@ -81,7 +81,7 @@ static int hwtimer_start(void) adc_dev = (rt_adc_device_t)rt_device_find(HWADC_DEV_NAME); if (adc_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); return -RT_ERROR; } @@ -89,7 +89,7 @@ static int hwtimer_start(void) ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } @@ -97,8 +97,8 @@ static int hwtimer_start(void) rt_device_set_rx_indicate(hw_dev, timeout_cb); /* Set the mode to periodic timer */ - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -132,12 +132,12 @@ static int tim_sample(int argc, char *argv[]) if (!rt_strcmp(argv[1], "start")) { rt_kprintf("tim14 will start\n"); - hwtimer_start(); + clock_timer_start(); return RT_EOK; } else if (!rt_strcmp(argv[1], "stop")) { - hwtimer_stop(); + clock_timer_stop(); rt_kprintf("stop tim14 success!\n"); return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig index 153c1df159..fb4c2cea1e 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-ev1/board/Kconfig @@ -233,7 +233,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM14 bool "Enable TIM14" diff --git a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c index 50c87ad0c8..402902db3f 100644 --- a/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c +++ b/bsp/stm32/stm32mp157a-st-ev1/board/ports/timer_sample.c @@ -15,7 +15,7 @@ #include #include -#define HWTIMER_DEV_NAME "timer14" +#define CLOCK_TIMER_DEV_NAME "timer14" #define HWADC_DEV_NAME "adc2" #define REFER_VOLTAGE 330 /* voltage reference */ #define CONVERT_BITS (1 << 12) /* Conversion digit */ @@ -37,22 +37,22 @@ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) return 0; } -static int hwtimer_stop(void) +static int clock_timer_stop(void) { rt_err_t ret = RT_EOK; rt_device_t hw_dev = RT_NULL; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } ret = rt_device_close(hw_dev); if (ret != RT_EOK) { - rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("close %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } @@ -62,18 +62,18 @@ static int hwtimer_stop(void) return ret; } -static int hwtimer_start(void) +static int clock_timer_start(void) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } @@ -81,7 +81,7 @@ static int hwtimer_start(void) adc_dev = (rt_adc_device_t)rt_device_find(HWADC_DEV_NAME); if (adc_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", HWADC_DEV_NAME); return -RT_ERROR; } @@ -89,7 +89,7 @@ static int hwtimer_start(void) ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } @@ -97,8 +97,8 @@ static int hwtimer_start(void) rt_device_set_rx_indicate(hw_dev, timeout_cb); /* Set the mode to periodic timer */ - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -132,12 +132,12 @@ static int tim_sample(int argc, char *argv[]) if (!rt_strcmp(argv[1], "start")) { rt_kprintf("tim14 will start\n"); - hwtimer_start(); + clock_timer_start(); return RT_EOK; } else if (!rt_strcmp(argv[1], "stop")) { - hwtimer_stop(); + clock_timer_stop(); rt_kprintf("stop tim14 success!\n"); return RT_EOK; } diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/Kconfig b/bsp/stm32/stm32wb55-st-nucleo/board/Kconfig index c57500c423..1351db7061 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32wb55-st-nucleo/board/Kconfig @@ -116,7 +116,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM16 diff --git a/bsp/synwit/libraries/SWM320_drivers/SConscript b/bsp/synwit/libraries/SWM320_drivers/SConscript index 9c20c550a4..c4beaaac5b 100644 --- a/bsp/synwit/libraries/SWM320_drivers/SConscript +++ b/bsp/synwit/libraries/SWM320_drivers/SConscript @@ -12,8 +12,8 @@ if GetDepend(['RT_USING_PIN']): if GetDepend(['RT_USING_ADC']): src += ['drv_adc.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_I2C']): src += ['drv_soft_i2c.c'] diff --git a/bsp/synwit/libraries/SWM320_drivers/drv_hwtimer.c b/bsp/synwit/libraries/SWM320_drivers/drv_timer.c similarity index 59% rename from bsp/synwit/libraries/SWM320_drivers/drv_hwtimer.c rename to bsp/synwit/libraries/SWM320_drivers/drv_timer.c index 2970dc5e16..a1ec811ee0 100644 --- a/bsp/synwit/libraries/SWM320_drivers/drv_hwtimer.c +++ b/bsp/synwit/libraries/SWM320_drivers/drv_timer.c @@ -9,13 +9,13 @@ * 2020-07-10 lik format file */ -#include "drv_hwtimer.h" +#include "drv_timer.h" -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME #ifdef BSP_USING_TIM //#define DRV_DEBUG -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include #if !defined(BSP_USING_TIM0) && !defined(BSP_USING_TIM1) && !defined(BSP_USING_TIM2) && !defined(BSP_USING_TIM3) \ @@ -30,7 +30,7 @@ .maxfreq = 120000000, \ .minfreq = 120000000, \ .maxcnt = 0xFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_DW, \ + .cntmode = CLOCK_TIMER_CNTMODE_DW, \ } #endif /* TIM_DEV_INFO_CONFIG */ @@ -94,16 +94,16 @@ #endif /* TIM5_CFG */ #endif /* BSP_USING_TIM5 */ -struct swm_hwtimer_cfg +struct swm_clock_timer_cfg { char *name; TIMR_TypeDef *TIMRx; }; -struct swm_hwtimer_device +struct swm_clock_timer_device { - struct swm_hwtimer_cfg *hwtimer_cfg; - rt_hwtimer_t time_device; + struct swm_clock_timer_cfg *clock_timer_cfg; + rt_clock_timer_t time_device; }; enum @@ -128,7 +128,7 @@ enum #endif }; -static struct swm_hwtimer_cfg swm_hwtimer_cfg[] = +static struct swm_clock_timer_cfg swm_clock_timer_cfg[] = { #ifdef BSP_USING_TIM0 TIM0_CFG, @@ -150,79 +150,79 @@ static struct swm_hwtimer_cfg swm_hwtimer_cfg[] = #endif }; -static struct swm_hwtimer_device hwtimer_obj[sizeof(swm_hwtimer_cfg) / sizeof(swm_hwtimer_cfg[0])] = {0}; +static struct swm_clock_timer_device clock_timer_obj[sizeof(swm_clock_timer_cfg) / sizeof(swm_clock_timer_cfg[0])] = {0}; -static void swm_timer_configure(struct rt_hwtimer_device *timer_device, rt_uint32_t state) +static void swm_timer_configure(struct rt_clock_timer_device *timer_device, rt_uint32_t state) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); if (state) { - hwtimer_cfg = timer_device->parent.user_data; - TIMR_Init(hwtimer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1); + clock_timer_cfg = timer_device->parent.user_data; + TIMR_Init(clock_timer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1); timer_device->freq = SystemCoreClock; } } -static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t swm_timer_start(rt_clock_timer_t *timer_device, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ - timer_device->mode = HWTIMER_MODE_ONESHOT; + timer_device->mode = CLOCK_TIMER_MODE_ONESHOT; } else { - timer_device->mode = HWTIMER_MODE_PERIOD; + timer_device->mode = CLOCK_TIMER_MODE_PERIOD; } - TIMR_SetPeriod(hwtimer_cfg->TIMRx, cnt); - TIMR_Stop(hwtimer_cfg->TIMRx); - TIMR_Start(hwtimer_cfg->TIMRx); + TIMR_SetPeriod(clock_timer_cfg->TIMRx, cnt); + TIMR_Stop(clock_timer_cfg->TIMRx); + TIMR_Start(clock_timer_cfg->TIMRx); return result; } -static void swm_timer_stop(rt_hwtimer_t *timer_device) +static void swm_timer_stop(rt_clock_timer_t *timer_device) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; /* stop timer */ - TIMR_Stop(hwtimer_cfg->TIMRx); + TIMR_Stop(clock_timer_cfg->TIMRx); } -static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device) +static rt_uint32_t swm_timer_count_get(rt_clock_timer_t *timer_device) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; - return TIMR_GetCurValue(hwtimer_cfg->TIMRx); + return TIMR_GetCurValue(clock_timer_cfg->TIMRx); } -static rt_err_t swm_timer_control(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args) +static rt_err_t swm_timer_control(rt_clock_timer_t *timer_device, rt_uint32_t cmd, void *args) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; rt_err_t result = RT_EOK; RT_ASSERT(timer_device != RT_NULL); RT_ASSERT(args != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; freq = *(rt_uint32_t *)args; - TIMR_Init(hwtimer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1); + TIMR_Init(clock_timer_cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1); } break; default: @@ -235,9 +235,9 @@ static rt_err_t swm_timer_control(rt_hwtimer_t *timer_device, rt_uint32_t cmd, v return result; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops swm_timer_ops = +static const struct rt_clock_timer_ops swm_timer_ops = { .init = swm_timer_configure, .start = swm_timer_start, @@ -245,14 +245,14 @@ static const struct rt_hwtimer_ops swm_timer_ops = .count_get = swm_timer_count_get, .control = swm_timer_control}; -void swm_timer_isr(rt_hwtimer_t *timer_device) +void swm_timer_isr(rt_clock_timer_t *timer_device) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; - TIMR_INTClr(hwtimer_cfg->TIMRx); - rt_device_hwtimer_isr(timer_device); + TIMR_INTClr(clock_timer_cfg->TIMRx); + rt_clock_timer_isr(timer_device); } #ifdef BSP_USING_TIM0 @@ -260,7 +260,7 @@ void TIMR0_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM0_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM0_INDEX].time_device)); /* leave interrupt */ rt_interrupt_leave(); } @@ -271,7 +271,7 @@ void TIMR1_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM1_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM1_INDEX].time_device)); /* leave interrupt */ rt_interrupt_leave(); } @@ -282,7 +282,7 @@ void TIMR2_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM2_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM2_INDEX].time_device)); /* leave interrupt */ rt_interrupt_leave(); } @@ -293,7 +293,7 @@ void TIMR3_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM3_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM3_INDEX].time_device)); /* leave interrupt */ rt_interrupt_leave(); } @@ -304,7 +304,7 @@ void TIMR4_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM4_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM4_INDEX].time_device)); /* leave interrupt */ rt_interrupt_leave(); } @@ -315,7 +315,7 @@ void TIMR5_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM5_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM5_INDEX].time_device)); /* leave interrupt */ rt_interrupt_leave(); } @@ -326,19 +326,19 @@ static int swm_timer_init(void) int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(swm_hwtimer_cfg) / sizeof(swm_hwtimer_cfg[0]); i++) + for (i = 0; i < sizeof(swm_clock_timer_cfg) / sizeof(swm_clock_timer_cfg[0]); i++) { - hwtimer_obj[i].hwtimer_cfg = &swm_hwtimer_cfg[i]; - hwtimer_obj[i].time_device.info = &_info; - hwtimer_obj[i].time_device.ops = &swm_timer_ops; - result = rt_device_hwtimer_register(&hwtimer_obj[i].time_device, hwtimer_obj[i].hwtimer_cfg->name, hwtimer_obj[i].hwtimer_cfg); + clock_timer_obj[i].clock_timer_cfg = &swm_clock_timer_cfg[i]; + clock_timer_obj[i].time_device.info = &_info; + clock_timer_obj[i].time_device.ops = &swm_timer_ops; + result = rt_clock_timer_register(&clock_timer_obj[i].time_device, clock_timer_obj[i].clock_timer_cfg->name, clock_timer_obj[i].clock_timer_cfg); if (result != RT_EOK) { - LOG_E("%s register fail.", hwtimer_obj[i].hwtimer_cfg->name); + LOG_E("%s register fail.", clock_timer_obj[i].clock_timer_cfg->name); } else { - LOG_D("%s register success.", hwtimer_obj[i].hwtimer_cfg->name); + LOG_D("%s register success.", clock_timer_obj[i].clock_timer_cfg->name); } } @@ -347,4 +347,4 @@ static int swm_timer_init(void) INIT_BOARD_EXPORT(swm_timer_init); #endif /* BSP_USING_TIM */ -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/synwit/libraries/SWM320_drivers/drv_hwtimer.h b/bsp/synwit/libraries/SWM320_drivers/drv_timer.h similarity index 75% rename from bsp/synwit/libraries/SWM320_drivers/drv_hwtimer.h rename to bsp/synwit/libraries/SWM320_drivers/drv_timer.h index fa74a2a68f..0d2818ac14 100644 --- a/bsp/synwit/libraries/SWM320_drivers/drv_hwtimer.h +++ b/bsp/synwit/libraries/SWM320_drivers/drv_timer.h @@ -9,11 +9,11 @@ * 2020-07-10 lik rewrite */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include "board.h" int swm_timer_init(void); -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/synwit/libraries/SWM341_drivers/SConscript b/bsp/synwit/libraries/SWM341_drivers/SConscript index 8aacb2087f..26bef4ca2b 100644 --- a/bsp/synwit/libraries/SWM341_drivers/SConscript +++ b/bsp/synwit/libraries/SWM341_drivers/SConscript @@ -18,8 +18,8 @@ if GetDepend(['RT_USING_DAC']): if GetDepend(['RT_USING_CAN']): src += ['drv_can.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_I2C']): src += ['drv_soft_i2c.c'] diff --git a/bsp/synwit/libraries/SWM341_drivers/drv_hwtimer.c b/bsp/synwit/libraries/SWM341_drivers/drv_timer.c similarity index 70% rename from bsp/synwit/libraries/SWM341_drivers/drv_hwtimer.c rename to bsp/synwit/libraries/SWM341_drivers/drv_timer.c index c66836b32f..507190caac 100644 --- a/bsp/synwit/libraries/SWM341_drivers/drv_hwtimer.c +++ b/bsp/synwit/libraries/SWM341_drivers/drv_timer.c @@ -8,13 +8,13 @@ * 2021-07-01 lik first version */ -#include "drv_hwtimer.h" +#include "drv_timer.h" -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME #ifdef BSP_USING_TIM //#define DRV_DEBUG -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include #if !defined(BSP_USING_TIM0) && !defined(BSP_USING_TIM1) && !defined(BSP_USING_TIM2) && !defined(BSP_USING_TIM3) \ @@ -32,7 +32,7 @@ .maxfreq = 1000000, \ .minfreq = 1000000, \ .maxcnt = 0xFFFFFFFF, \ - .cntmode = HWTIMER_CNTMODE_DW, \ + .cntmode = CLOCK_TIMER_CNTMODE_DW, \ } #endif /* TIM_DEV_INFO_CONFIG */ @@ -206,16 +206,16 @@ #endif /* BTIM11_CFG */ #endif /* BSP_USING_BTIM11 */ -struct swm_hwtimer_cfg +struct swm_clock_timer_cfg { char *name; TIMR_TypeDef *TIMRx; }; -struct swm_hwtimer_device +struct swm_clock_timer_device { - struct swm_hwtimer_cfg *hwtimer_cfg; - rt_hwtimer_t time_device; + struct swm_clock_timer_cfg *clock_timer_cfg; + rt_clock_timer_t time_device; }; enum @@ -273,7 +273,7 @@ enum #endif }; -static struct swm_hwtimer_cfg swm_hwtimer_cfg[] = +static struct swm_clock_timer_cfg swm_clock_timer_cfg[] = { #ifdef BSP_USING_TIM0 TIM0_CFG, @@ -328,79 +328,79 @@ static struct swm_hwtimer_cfg swm_hwtimer_cfg[] = #endif }; -static struct swm_hwtimer_device hwtimer_obj[sizeof(swm_hwtimer_cfg) / sizeof(swm_hwtimer_cfg[0])] = {0}; +static struct swm_clock_timer_device clock_timer_obj[sizeof(swm_clock_timer_cfg) / sizeof(swm_clock_timer_cfg[0])] = {0}; -static void swm_timer_configure(struct rt_hwtimer_device *timer_device, rt_uint32_t state) +static void swm_timer_configure(struct rt_clock_timer_device *timer_device, rt_uint32_t state) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); if (state) { - hwtimer_cfg = timer_device->parent.user_data; - TIMR_Init(hwtimer_cfg->TIMRx, TIMR_MODE_TIMER, CyclesPerUs, 1000000, 1); + clock_timer_cfg = timer_device->parent.user_data; + TIMR_Init(clock_timer_cfg->TIMRx, TIMR_MODE_TIMER, CyclesPerUs, 1000000, 1); timer_device->freq = 1000000; } } -static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +static rt_err_t swm_timer_start(rt_clock_timer_t *timer_device, rt_uint32_t cnt, rt_clock_timer_mode_t opmode) { rt_err_t result = RT_EOK; - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; - if (opmode == HWTIMER_MODE_ONESHOT) + if (opmode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ - timer_device->mode = HWTIMER_MODE_ONESHOT; + timer_device->mode = CLOCK_TIMER_MODE_ONESHOT; } else { - timer_device->mode = HWTIMER_MODE_PERIOD; + timer_device->mode = CLOCK_TIMER_MODE_PERIOD; } - hwtimer_cfg->TIMRx->LOAD = cnt - 1; - TIMR_Stop(hwtimer_cfg->TIMRx); - TIMR_Start(hwtimer_cfg->TIMRx); + clock_timer_cfg->TIMRx->LOAD = cnt - 1; + TIMR_Stop(clock_timer_cfg->TIMRx); + TIMR_Start(clock_timer_cfg->TIMRx); return result; } -static void swm_timer_stop(rt_hwtimer_t *timer_device) +static void swm_timer_stop(rt_clock_timer_t *timer_device) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; /* stop timer */ - TIMR_Stop(hwtimer_cfg->TIMRx); + TIMR_Stop(clock_timer_cfg->TIMRx); } -static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device) +static rt_uint32_t swm_timer_count_get(rt_clock_timer_t *timer_device) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; - return TIMR_GetCurValue(hwtimer_cfg->TIMRx); + return TIMR_GetCurValue(clock_timer_cfg->TIMRx); } -static rt_err_t swm_timer_control(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args) +static rt_err_t swm_timer_control(rt_clock_timer_t *timer_device, rt_uint32_t cmd, void *args) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; rt_err_t result = RT_EOK; RT_ASSERT(timer_device != RT_NULL); RT_ASSERT(args != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; freq = *(rt_uint32_t *)args; - TIMR_Init(hwtimer_cfg->TIMRx, TIMR_MODE_TIMER, CyclesPerUs, freq, 1); + TIMR_Init(clock_timer_cfg->TIMRx, TIMR_MODE_TIMER, CyclesPerUs, freq, 1); } break; default: @@ -413,9 +413,9 @@ static rt_err_t swm_timer_control(rt_hwtimer_t *timer_device, rt_uint32_t cmd, v return result; } -static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops swm_timer_ops = +static const struct rt_clock_timer_ops swm_timer_ops = { .init = swm_timer_configure, .start = swm_timer_start, @@ -423,21 +423,21 @@ static const struct rt_hwtimer_ops swm_timer_ops = .count_get = swm_timer_count_get, .control = swm_timer_control}; -void swm_timer_isr(rt_hwtimer_t *timer_device) +void swm_timer_isr(rt_clock_timer_t *timer_device) { - struct swm_hwtimer_cfg *hwtimer_cfg = RT_NULL; + struct swm_clock_timer_cfg *clock_timer_cfg = RT_NULL; RT_ASSERT(timer_device != RT_NULL); - hwtimer_cfg = timer_device->parent.user_data; + clock_timer_cfg = timer_device->parent.user_data; - TIMR_INTClr(hwtimer_cfg->TIMRx); - rt_device_hwtimer_isr(timer_device); + TIMR_INTClr(clock_timer_cfg->TIMRx); + rt_clock_timer_isr(timer_device); } #ifdef BSP_USING_TIM0 void TIMR0_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM0_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM0_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_TIM0 @@ -446,7 +446,7 @@ void TIMR0_Handler(void) void TIMR1_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM1_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM1_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_TIM1 @@ -455,7 +455,7 @@ void TIMR1_Handler(void) void TIMR2_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM2_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM2_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_TIM2 @@ -464,7 +464,7 @@ void TIMR2_Handler(void) void TIMR3_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM3_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM3_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_TIM3 @@ -473,7 +473,7 @@ void TIMR3_Handler(void) void TIMR4_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[TIM4_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[TIM4_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_TIM4 @@ -482,7 +482,7 @@ void TIMR4_Handler(void) void BTIMR0_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM0_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM0_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM0 @@ -491,7 +491,7 @@ void BTIMR0_Handler(void) void BTIMR1_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM1_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM1_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM1 @@ -500,7 +500,7 @@ void BTIMR1_Handler(void) void BTIMR2_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM2_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM2_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM2 @@ -509,7 +509,7 @@ void BTIMR2_Handler(void) void BTIMR3_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM3_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM3_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM3 @@ -518,7 +518,7 @@ void BTIMR3_Handler(void) void BTIMR4_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM4_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM4_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM4 @@ -527,7 +527,7 @@ void BTIMR4_Handler(void) void BTIMR5_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM5_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM5_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM5 @@ -536,7 +536,7 @@ void BTIMR5_Handler(void) void BTIMR6_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM6_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM6_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM6 @@ -545,7 +545,7 @@ void BTIMR6_Handler(void) void BTIMR7_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM7_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM7_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM7 @@ -554,7 +554,7 @@ void BTIMR7_Handler(void) void BTIMR8_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM8_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM8_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM8 @@ -563,7 +563,7 @@ void BTIMR8_Handler(void) void BTIMR9_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM9_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM9_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM9 @@ -572,7 +572,7 @@ void BTIMR9_Handler(void) void BTIMR10_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM10_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM10_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM10 @@ -581,7 +581,7 @@ void BTIMR10_Handler(void) void BTIMR11_Handler(void) { rt_interrupt_enter(); - swm_timer_isr(&(hwtimer_obj[BTIM11_INDEX].time_device)); + swm_timer_isr(&(clock_timer_obj[BTIM11_INDEX].time_device)); rt_interrupt_leave(); } #endif // BSP_USING_BTIM11 @@ -591,19 +591,19 @@ int swm_timer_init(void) int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(swm_hwtimer_cfg) / sizeof(swm_hwtimer_cfg[0]); i++) + for (i = 0; i < sizeof(swm_clock_timer_cfg) / sizeof(swm_clock_timer_cfg[0]); i++) { - hwtimer_obj[i].hwtimer_cfg = &swm_hwtimer_cfg[i]; - hwtimer_obj[i].time_device.info = &_info; - hwtimer_obj[i].time_device.ops = &swm_timer_ops; - result = rt_device_hwtimer_register(&hwtimer_obj[i].time_device, hwtimer_obj[i].hwtimer_cfg->name, hwtimer_obj[i].hwtimer_cfg); + clock_timer_obj[i].clock_timer_cfg = &swm_clock_timer_cfg[i]; + clock_timer_obj[i].time_device.info = &_info; + clock_timer_obj[i].time_device.ops = &swm_timer_ops; + result = rt_clock_timer_register(&clock_timer_obj[i].time_device, clock_timer_obj[i].clock_timer_cfg->name, clock_timer_obj[i].clock_timer_cfg); if (result != RT_EOK) { - LOG_E("%s register fail.", hwtimer_obj[i].hwtimer_cfg->name); + LOG_E("%s register fail.", clock_timer_obj[i].clock_timer_cfg->name); } else { - LOG_D("%s register success.", hwtimer_obj[i].hwtimer_cfg->name); + LOG_D("%s register success.", clock_timer_obj[i].clock_timer_cfg->name); } } @@ -612,4 +612,4 @@ int swm_timer_init(void) INIT_BOARD_EXPORT(swm_timer_init); #endif /* BSP_USING_TIM */ -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/bsp/synwit/libraries/SWM341_drivers/drv_hwtimer.h b/bsp/synwit/libraries/SWM341_drivers/drv_timer.h similarity index 72% rename from bsp/synwit/libraries/SWM341_drivers/drv_hwtimer.h rename to bsp/synwit/libraries/SWM341_drivers/drv_timer.h index 861d447b7b..745b8c74e3 100644 --- a/bsp/synwit/libraries/SWM341_drivers/drv_hwtimer.h +++ b/bsp/synwit/libraries/SWM341_drivers/drv_timer.h @@ -8,11 +8,11 @@ * 2021-07-01 lik first version */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include "board.h" int swm_timer_init(void); -#endif /* __DRV_HWTIMER_H__ */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/synwit/swm320-mini/applications/main.c b/bsp/synwit/swm320-mini/applications/main.c index ee150569ff..4350be85ed 100644 --- a/bsp/synwit/swm320-mini/applications/main.c +++ b/bsp/synwit/swm320-mini/applications/main.c @@ -81,42 +81,42 @@ MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); #endif #ifdef BSP_USING_TIM -#define HWTIMER_DEV_NAME "timer0" +#define CLOCK_TIMER_DEV_NAME "timer0" static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback fucntion!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } rt_device_set_rx_indicate(hw_dev, timeout_cb); - mode = HWTIMER_MODE_PERIOD; - //mode = HWTIMER_MODE_ONESHOT; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + //mode = CLOCK_TIMER_MODE_ONESHOT; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -139,7 +139,7 @@ static int hwtimer_sample(int argc, char *argv[]) return ret; } -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); #endif #ifdef BSP_USING_PWM @@ -553,9 +553,9 @@ static int norflash_sample(int argc, char *argv[]) rt_kprintf("id = %08x!\n", id); // rt_device_set_rx_indicate(hw_dev, timeout_cb); - // mode = HWTIMER_MODE_PERIOD; - // //mode = HWTIMER_MODE_ONESHOT; - // ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + // mode = CLOCK_TIMER_MODE_PERIOD; + // //mode = CLOCK_TIMER_MODE_ONESHOT; + // ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); // if (ret != RT_EOK) // { // rt_kprintf("set mode failed! ret is :%d\n", ret); diff --git a/bsp/synwit/swm320-mini/board/Kconfig b/bsp/synwit/swm320-mini/board/Kconfig index 6dab8a31ef..8a2c6875e1 100644 --- a/bsp/synwit/swm320-mini/board/Kconfig +++ b/bsp/synwit/swm320-mini/board/Kconfig @@ -99,9 +99,9 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_TIM - bool "Enable HWTIMER" + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/synwit/swm341-mini/applications/main.c b/bsp/synwit/swm341-mini/applications/main.c index f46e4395cd..4d32b758e2 100644 --- a/bsp/synwit/swm341-mini/applications/main.c +++ b/bsp/synwit/swm341-mini/applications/main.c @@ -247,42 +247,42 @@ int can_sample(int argc, char *argv[]) MSH_CMD_EXPORT(can_sample, can device sample); #endif #ifdef BSP_USING_TIM -#define HWTIMER_DEV_NAME "timer0" +#define CLOCK_TIMER_DEV_NAME "timer0" static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback fucntion!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; + rt_clock_timerval_t timeout_s; rt_device_t hw_dev = RT_NULL; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } rt_device_set_rx_indicate(hw_dev, timeout_cb); - mode = HWTIMER_MODE_PERIOD; - //mode = HWTIMER_MODE_ONESHOT; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + //mode = CLOCK_TIMER_MODE_ONESHOT; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -305,7 +305,7 @@ static int hwtimer_sample(int argc, char *argv[]) return ret; } -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); #endif #ifdef BSP_USING_PWM diff --git a/bsp/synwit/swm341-mini/board/Kconfig b/bsp/synwit/swm341-mini/board/Kconfig index df36c1a65c..6e6564850d 100644 --- a/bsp/synwit/swm341-mini/board/Kconfig +++ b/bsp/synwit/swm341-mini/board/Kconfig @@ -126,9 +126,9 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_TIM - bool "Enable HWTIMER" + bool "Enable CLOCK_TIMER" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM0 bool "Enable TIM0" diff --git a/bsp/tae32f5300/Libraries/SConscript b/bsp/tae32f5300/Libraries/SConscript index c084d6df4b..730c641e28 100644 --- a/bsp/tae32f5300/Libraries/SConscript +++ b/bsp/tae32f5300/Libraries/SConscript @@ -35,7 +35,7 @@ if GetDepend(['RT_USING_WDT']): src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_wwdg.c'] src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_iwdg.c'] -if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])): +if GetDepend(['RT_USING_CLOCK_TIME']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])): src += ['TAE32F53xx_StdPeriph_Driver/src/tae32f53xx_ll_tmr.c'] #add for startup script diff --git a/bsp/tae32f5300/drivers/Kconfig b/bsp/tae32f5300/drivers/Kconfig index 6d39184c1a..29451af6c7 100644 --- a/bsp/tae32f5300/drivers/Kconfig +++ b/bsp/tae32f5300/drivers/Kconfig @@ -233,7 +233,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIMER bool "Enable TIMER" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIMER config BSP_USING_TIMER5 bool "Enable TIMER5" diff --git a/bsp/tkm32F499/drivers/Kconfig b/bsp/tkm32F499/drivers/Kconfig index 4e7e9a19d6..d856bc73ff 100644 --- a/bsp/tkm32F499/drivers/Kconfig +++ b/bsp/tkm32F499/drivers/Kconfig @@ -87,7 +87,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/tm4c123bsp/board/Kconfig b/bsp/tm4c123bsp/board/Kconfig index b7356b7fad..2387534959 100644 --- a/bsp/tm4c123bsp/board/Kconfig +++ b/bsp/tm4c123bsp/board/Kconfig @@ -262,7 +262,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_TIM bool "Enable timer" default n - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME if BSP_USING_TIM config BSP_USING_TIM2 bool "Enable TIM2" diff --git a/bsp/tm4c123bsp/libraries/Drivers/SConscript b/bsp/tm4c123bsp/libraries/Drivers/SConscript index 94e0d77ba1..99d85cd7f7 100644 --- a/bsp/tm4c123bsp/libraries/Drivers/SConscript +++ b/bsp/tm4c123bsp/libraries/Drivers/SConscript @@ -14,8 +14,8 @@ if GetDepend(['RT_USING_PIN']): if GetDepend(['RT_USING_SERIAL']): src += ['drv_uart.c'] -if GetDepend(['RT_USING_HWTIMER']): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_CLOCK_TIME']): + src += ['drv_timer.c'] if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] diff --git a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript index 6bd89e4889..f638750a74 100644 --- a/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript +++ b/bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript @@ -33,7 +33,7 @@ if GetDepend(['RT_USING_SPI']): #if GetDepend(['RT_USING_CAN']): -#if GetDepend(['RT_USING_HWTIMER']) +#if GetDepend(['RT_USING_CLOCK_TIME']) if GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']): src += ['tm4c123_driverlib/src/pwm.c'] diff --git a/bsp/ultrarisc/ur_dp1000_evb/board/board.c b/bsp/ultrarisc/ur_dp1000_evb/board/board.c index 0a672df343..5f338c4689 100644 --- a/bsp/ultrarisc/ur_dp1000_evb/board/board.c +++ b/bsp/ultrarisc/ur_dp1000_evb/board/board.c @@ -35,6 +35,11 @@ struct mem_desc platform_mem_desc[] = #endif +rt_uint64_t rt_hw_get_clock_timer_freq(void) +{ + return 10000000ULL; +} + void primary_cpu_entry(void) { /* disable global interrupt */ @@ -123,4 +128,4 @@ void rt_hw_cpu_reset(void) while (1) ; } -MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); \ No newline at end of file +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); diff --git a/bsp/w60x/drivers/Kconfig b/bsp/w60x/drivers/Kconfig index 2a10fd89dc..5c2b5c6d82 100644 --- a/bsp/w60x/drivers/Kconfig +++ b/bsp/w60x/drivers/Kconfig @@ -108,12 +108,12 @@ menu "On-chip Peripheral Drivers" endif endif - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" - select RT_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" + select RT_USING_CLOCK_TIME default n - if BSP_USING_HWTIMER + if BSP_USING_CLOCK_TIMER config USING_HW_TIMER1 bool "Enable hw timer1" config USING_HW_TIMER2 diff --git a/bsp/w60x/drivers/SConscript b/bsp/w60x/drivers/SConscript index ef076132c3..44dd0267b3 100644 --- a/bsp/w60x/drivers/SConscript +++ b/bsp/w60x/drivers/SConscript @@ -20,7 +20,7 @@ if GetDepend(['BSP_USING_WIFI']): if GetDepend('BSP_USING_PIN'): src += ['drv_pin.c'] -if GetDepend('BSP_USING_HWTIMER'): +if GetDepend('BSP_USING_CLOCK_TIMER'): src += ['drv_hw_timer.c'] if GetDepend('BSP_USING_SOFT_I2C'): diff --git a/bsp/w60x/drivers/drv_hw_timer.c b/bsp/w60x/drivers/drv_hw_timer.c index d52c9c09a6..0ae3b8bfe9 100644 --- a/bsp/w60x/drivers/drv_hw_timer.c +++ b/bsp/w60x/drivers/drv_hw_timer.c @@ -14,7 +14,7 @@ #include "wm_timer.h" #include "drv_hw_timer.h" -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER struct wm_timer_Type { @@ -22,7 +22,7 @@ struct wm_timer_Type enum tls_timer_id id; }; -static void wm_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +static void wm_timer_init(rt_clock_timer_t *timer, rt_uint32_t state) { struct tls_timer_cfg timer_cfg; struct wm_timer_Type *wm_timer = (struct wm_timer_Type *)timer->parent.user_data; @@ -43,35 +43,35 @@ static void wm_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) } } -static rt_err_t wm_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) +static rt_err_t wm_timer_start(rt_clock_timer_t *timer, rt_uint32_t t, rt_clock_timer_mode_t opmode) { struct wm_timer_Type *wm_timer = (struct wm_timer_Type *)timer->parent.user_data; uint8_t m; tls_timer_change(wm_timer->id, t); - m = (opmode == HWTIMER_MODE_ONESHOT) ? 0 : 1; + m = (opmode == CLOCK_TIMER_MODE_ONESHOT) ? 0 : 1; tls_timer_set_mode(wm_timer->id, m); tls_timer_start(wm_timer->id); return RT_EOK; } -static void wm_timer_stop(rt_hwtimer_t *timer) +static void wm_timer_stop(rt_clock_timer_t *timer) { struct wm_timer_Type *wm_timer = (struct wm_timer_Type *)timer->parent.user_data; tls_timer_stop(wm_timer->id); } -static rt_uint32_t wm_timer_get(rt_hwtimer_t *timer) +static rt_uint32_t wm_timer_get(rt_clock_timer_t *timer) { return 0; } -static rt_err_t wm_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +static rt_err_t wm_timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { /* The frequency value is an immutable value. */ - if (cmd != HWTIMER_CTRL_FREQ_SET) + if (cmd != CLOCK_TIMER_CTRL_FREQ_SET) { return -RT_ENOSYS; } @@ -85,15 +85,15 @@ static rt_err_t wm_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) } } -static const struct rt_hwtimer_info _info = +static const struct rt_clock_timer_info _info = { 1000000, /* the maximum count frequency can be set */ 1000000, /* the minimum count frequency can be set */ 0xFFFFFFFF, /* the maximum counter value */ - HWTIMER_CNTMODE_DW, /* Increment or Decreasing count mode */ + CLOCK_TIMER_CNTMODE_DW, /* Increment or Decreasing count mode */ }; -static const struct rt_hwtimer_ops _ops = +static const struct rt_clock_timer_ops _ops = { wm_timer_init, wm_timer_start, @@ -103,23 +103,23 @@ static const struct rt_hwtimer_ops _ops = }; #ifdef USING_HW_TIMER1 -static rt_hwtimer_t _timer1; +static rt_clock_timer_t _timer1; static struct wm_timer_Type wm_timer1; #endif #ifdef USING_HW_TIMER2 -static rt_hwtimer_t _timer2; +static rt_clock_timer_t _timer2; static struct wm_timer_Type wm_timer2; #endif #ifdef USING_HW_TIMER3 -static rt_hwtimer_t _timer3; +static rt_clock_timer_t _timer3; static struct wm_timer_Type wm_timer3; #endif #ifdef USING_HW_TIMER4 -static rt_hwtimer_t _timer4; +static rt_clock_timer_t _timer4; static struct wm_timer_Type wm_timer4; #endif #ifdef USING_HW_TIMER5 -static rt_hwtimer_t _timer5; +static rt_clock_timer_t _timer5; static struct wm_timer_Type wm_timer5; #endif @@ -132,7 +132,7 @@ int wm_hw_timer_init(void) _timer1.info = &_info; _timer1.ops = &_ops; - rt_device_hwtimer_register(&_timer1, "timer1", &wm_timer1); + rt_clock_timer_register(&_timer1, "timer1", &wm_timer1); #endif #ifdef USING_HW_TIMER2 wm_timer2.id = TLS_TIMER_ID_2; @@ -141,7 +141,7 @@ int wm_hw_timer_init(void) _timer2.info = &_info; _timer2.ops = &_ops; - rt_device_hwtimer_register(&_timer2, "timer2", &wm_timer2); + rt_clock_timer_register(&_timer2, "timer2", &wm_timer2); #endif #ifdef USING_HW_TIMER3 wm_timer3.id = TLS_TIMER_ID_3; @@ -150,7 +150,7 @@ int wm_hw_timer_init(void) _timer3.info = &_info; _timer3.ops = &_ops; - rt_device_hwtimer_register(&_timer3, "timer3", &wm_timer3); + rt_clock_timer_register(&_timer3, "timer3", &wm_timer3); #endif #ifdef USING_HW_TIMER4 wm_timer4.id = TLS_TIMER_ID_4; @@ -159,7 +159,7 @@ int wm_hw_timer_init(void) _timer4.info = &_info; _timer4.ops = &_ops; - rt_device_hwtimer_register(&_timer4, "timer4", &wm_timer4); + rt_clock_timer_register(&_timer4, "timer4", &wm_timer4); #endif #ifdef USING_HW_TIMER5 wm_timer5.id = TLS_TIMER_ID_5; @@ -168,7 +168,7 @@ int wm_hw_timer_init(void) _timer5.info = &_info; _timer5.ops = &_ops; - rt_device_hwtimer_register(&_timer5, "timer5", &wm_timer5); + rt_clock_timer_register(&_timer5, "timer5", &wm_timer5); #endif return 0; } @@ -178,35 +178,35 @@ void TIM1_IRQHandler(void) { timer_clear_irq(1); #ifdef USING_HW_TIMER1 - rt_device_hwtimer_isr(&_timer1); + rt_clock_timer_isr(&_timer1); #endif } void TIM2_IRQHandler(void) { timer_clear_irq(2); #ifdef USING_HW_TIMER2 - rt_device_hwtimer_isr(&_timer2); + rt_clock_timer_isr(&_timer2); #endif } void TIM3_IRQHandler(void) { timer_clear_irq(3); #ifdef USING_HW_TIMER3 - rt_device_hwtimer_isr(&_timer3); + rt_clock_timer_isr(&_timer3); #endif } void TIM4_IRQHandler(void) { timer_clear_irq(4); #ifdef USING_HW_TIMER4 - rt_device_hwtimer_isr(&_timer4); + rt_clock_timer_isr(&_timer4); #endif } void TIM5_IRQHandler(void) { timer_clear_irq(5); #ifdef USING_HW_TIMER5 - rt_device_hwtimer_isr(&_timer5); + rt_clock_timer_isr(&_timer5); #endif } -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/w60x/drivers/drv_hw_timer.h b/bsp/w60x/drivers/drv_hw_timer.h index 2856b5f5e4..61caadc2c2 100644 --- a/bsp/w60x/drivers/drv_hw_timer.h +++ b/bsp/w60x/drivers/drv_hw_timer.h @@ -8,8 +8,8 @@ * 2018-11-19 fanwenl 1st version */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ int wm_hw_timer_init(void); diff --git a/bsp/w60x/project.ewp b/bsp/w60x/project.ewp index 01ab9f59a7..b86d2ce4c2 100644 --- a/bsp/w60x/project.ewp +++ b/bsp/w60x/project.ewp @@ -2194,7 +2194,7 @@ $PROJ_DIR$\..\..\components\drivers\hwcrypto\hwcrypto.c - $PROJ_DIR$\..\..\components\drivers\hwtimer\hwtimer.c + $PROJ_DIR$\..\..\components\drivers\clock_time\clock_timer.c $PROJ_DIR$\..\..\components\drivers\i2c\dev_i2c_bit_ops.c diff --git a/bsp/w60x/project.uvprojx b/bsp/w60x/project.uvprojx index 3bbf457034..4dff2a774b 100644 --- a/bsp/w60x/project.uvprojx +++ b/bsp/w60x/project.uvprojx @@ -582,9 +582,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\components\drivers\hwtimer\hwtimer.c + ..\..\components\drivers\clock_time\clock_timer.c diff --git a/bsp/wch/arm/Libraries/ch32_drivers/SConscript b/bsp/wch/arm/Libraries/ch32_drivers/SConscript index bb4def6cab..fdc304accc 100644 --- a/bsp/wch/arm/Libraries/ch32_drivers/SConscript +++ b/bsp/wch/arm/Libraries/ch32_drivers/SConscript @@ -29,8 +29,8 @@ if GetDepend('SOC_ARM_SERIES_CH32F103'): if GetDepend(['RT_USING_WDT', 'BSP_USING_IWDT']): src += ['drv_iwdt_ch32f10x.c'] - if GetDepend(['RT_USING_HWTIMER', 'BSP_USING_HWTIMER']): - src += ['drv_hwtimer_ch32f10x.c'] + if GetDepend(['RT_USING_CLOCK_TIME', 'BSP_USING_CLOCK_TIMER']): + src += ['drv_timer_ch32f10x.c'] if GetDepend(['RT_USING_PWM', 'BSP_USING_PWM']): src += ['drv_pwm_ch32f10x.c'] @@ -56,8 +56,8 @@ if GetDepend('SOC_ARM_SERIES_CH32F203'): if GetDepend(['RT_USING_WDT', 'BSP_USING_IWDT']): src += ['drv_iwdt_ch32f20x.c'] - if GetDepend(['RT_USING_HWTIMER', 'BSP_USING_HWTIMER']): - src += ['drv_hwtimer_ch32f20x.c'] + if GetDepend(['RT_USING_CLOCK_TIME', 'BSP_USING_CLOCK_TIMER']): + src += ['drv_timer_ch32f20x.c'] if GetDepend(['RT_USING_PWM', 'BSP_USING_PWM']): src += ['drv_pwm_ch32f20x.c'] diff --git a/bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f10x.c b/bsp/wch/arm/Libraries/ch32_drivers/drv_timer_ch32f10x.c similarity index 36% rename from bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f10x.c rename to bsp/wch/arm/Libraries/ch32_drivers/drv_timer_ch32f10x.c index 13ffe679d5..8e88b60fd1 100644 --- a/bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f10x.c +++ b/bsp/wch/arm/Libraries/ch32_drivers/drv_timer_ch32f10x.c @@ -12,55 +12,55 @@ #include #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -struct hwtimer_device +struct clock_timer_device { - struct rt_hwtimer_device parent; + struct rt_clock_timer_device parent; TIM_TypeDef *periph; IRQn_Type irqn; char *name; }; -#ifdef BSP_USING_TIM1_HWTIMER -struct hwtimer_device hwtimer_device1 = +#ifdef BSP_USING_TIM1_CLOCK_TIMER +struct clock_timer_device clock_timer_device1 = { .periph = TIM1, .irqn = TIM1_UP_IRQn, .name = "timer1"}; #endif -#ifdef BSP_USING_TIM2_HWTIMER -struct hwtimer_device hwtimer_device2 = +#ifdef BSP_USING_TIM2_CLOCK_TIMER +struct clock_timer_device clock_timer_device2 = { .periph = TIM2, .irqn = TIM2_IRQn, .name = "timer2"}; #endif -#ifdef BSP_USING_TIM3_HWTIMER -struct hwtimer_device hwtimer_device3 = +#ifdef BSP_USING_TIM3_CLOCK_TIMER +struct clock_timer_device clock_timer_device3 = { .periph = TIM3, .irqn = TIM3_IRQn, .name = "timer3"}; #endif -#ifdef BSP_USING_TIM4_HWTIMER -struct hwtimer_device hwtimer_device4 = +#ifdef BSP_USING_TIM4_CLOCK_TIMER +struct clock_timer_device clock_timer_device4 = { .periph = TIM4, .irqn = TIM4_IRQn, .name = "timer4"}; #endif -static void ch32f1_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t state) +static void ch32f1_clock_timer_init(struct rt_clock_timer_device *device, rt_uint32_t state) { - struct hwtimer_device *hwtimer_dev; - struct rt_hwtimer_info *hwtimer_info; + struct clock_timer_device *clock_timer_dev; + struct rt_clock_timer_info *clock_timer_info; rt_uint32_t clk = 0; rt_uint16_t prescaler_value = 0; @@ -69,34 +69,34 @@ static void ch32f1_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t st RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; if (state) { - ch32f1_tim_clock_init(hwtimer_dev->periph); + ch32f1_tim_clock_init(clock_timer_dev->periph); - hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_dev->periph); + clock_timer_info = ch32f1_clock_timer_info_config_get(clock_timer_dev->periph); - clk = ch32f1_tim_clock_get(hwtimer_dev->periph); + clk = ch32f1_tim_clock_get(clock_timer_dev->periph); - prescaler_value = (rt_uint16_t)(clk / hwtimer_info->minfreq) - 1; + prescaler_value = (rt_uint16_t)(clk / clock_timer_info->minfreq) - 1; /* * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) ) */ - TIM_TimeBaseInitType.TIM_Period = hwtimer_info->maxcnt - 1; + TIM_TimeBaseInitType.TIM_Period = clock_timer_info->maxcnt - 1; TIM_TimeBaseInitType.TIM_Prescaler = prescaler_value; TIM_TimeBaseInitType.TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseInitType.TIM_RepetitionCounter = 0; - if (hwtimer_info == RT_NULL) + if (clock_timer_info == RT_NULL) { TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up; } else { - if (hwtimer_info->cntmode == HWTIMER_CNTMODE_UP) + if (clock_timer_info->cntmode == CLOCK_TIMER_CNTMODE_UP) { TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up; } @@ -106,89 +106,89 @@ static void ch32f1_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t st } } - TIM_TimeBaseInit(hwtimer_dev->periph, &TIM_TimeBaseInitType); + TIM_TimeBaseInit(clock_timer_dev->periph, &TIM_TimeBaseInitType); - NVIC_InitStructure.NVIC_IRQChannel = hwtimer_dev->irqn; + NVIC_InitStructure.NVIC_IRQChannel = clock_timer_dev->irqn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - TIM_ITConfig(hwtimer_dev->periph, TIM_IT_Update, ENABLE); - TIM_ClearITPendingBit(hwtimer_dev->periph, TIM_IT_Update); + TIM_ITConfig(clock_timer_dev->periph, TIM_IT_Update, ENABLE); + TIM_ClearITPendingBit(clock_timer_dev->periph, TIM_IT_Update); - LOG_D("%s init success", hwtimer_dev->name); + LOG_D("%s init success", clock_timer_dev->name); } } -static rt_err_t ch32f1_hwtimer_start(struct rt_hwtimer_device *device, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t ch32f1_clock_timer_start(struct rt_clock_timer_device *device, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; /* * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) ) */ - TIM_SetCounter(hwtimer_dev->periph, 0); - TIM_SetAutoreload(hwtimer_dev->periph, cnt - 1); + TIM_SetCounter(clock_timer_dev->periph, 0); + TIM_SetAutoreload(clock_timer_dev->periph, cnt - 1); - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { - TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Single); + TIM_SelectOnePulseMode(clock_timer_dev->periph, TIM_OPMode_Single); } else { - TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Repetitive); + TIM_SelectOnePulseMode(clock_timer_dev->periph, TIM_OPMode_Repetitive); } - TIM_Cmd(hwtimer_dev->periph, ENABLE); + TIM_Cmd(clock_timer_dev->periph, ENABLE); - LOG_D("%s start, cnt = %d", hwtimer_dev->name, cnt); + LOG_D("%s start, cnt = %d", clock_timer_dev->name, cnt); return RT_EOK; } -static void ch32f1_hwtimer_stop(struct rt_hwtimer_device *device) +static void ch32f1_clock_timer_stop(struct rt_clock_timer_device *device) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; - TIM_Cmd(hwtimer_dev->periph, DISABLE); + TIM_Cmd(clock_timer_dev->periph, DISABLE); - TIM_SetCounter(hwtimer_dev->periph, 0); + TIM_SetCounter(clock_timer_dev->periph, 0); } -static rt_uint32_t ch32f1_hwtimer_counter_get(struct rt_hwtimer_device *device) +static rt_uint32_t ch32f1_clock_timer_counter_get(struct rt_clock_timer_device *device) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; - return hwtimer_dev->periph->CNT; + return clock_timer_dev->periph->CNT; } -static rt_err_t ch32f1_hwtimer_control(struct rt_hwtimer_device *device, rt_uint32_t cmd, void *arg) +static rt_err_t ch32f1_clock_timer_control(struct rt_clock_timer_device *device, rt_uint32_t cmd, void *arg) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; rt_err_t result = RT_EOK; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq = 0; rt_uint32_t clk = 0; @@ -202,11 +202,11 @@ static rt_err_t ch32f1_hwtimer_control(struct rt_hwtimer_device *device, rt_uint freq = *((rt_uint32_t *)arg); - clk = ch32f1_tim_clock_get(hwtimer_dev->periph); + clk = ch32f1_tim_clock_get(clock_timer_dev->periph); prescaler_value = (rt_uint16_t)(clk / freq) - 1; - TIM_PrescalerConfig(hwtimer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate); + TIM_PrescalerConfig(clock_timer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate); } else { @@ -223,146 +223,146 @@ static rt_err_t ch32f1_hwtimer_control(struct rt_hwtimer_device *device, rt_uint return result; } -static const struct rt_hwtimer_ops hwtimer_ops = +static const struct rt_clock_timer_ops clock_timer_ops = { - .init = ch32f1_hwtimer_init, - .start = ch32f1_hwtimer_start, - .stop = ch32f1_hwtimer_stop, - .count_get = ch32f1_hwtimer_counter_get, - .control = ch32f1_hwtimer_control, + .init = ch32f1_clock_timer_init, + .start = ch32f1_clock_timer_start, + .stop = ch32f1_clock_timer_stop, + .count_get = ch32f1_clock_timer_counter_get, + .control = ch32f1_clock_timer_control, }; -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { rt_err_t ret; - struct rt_hwtimer_info *hwtimer_info; + struct rt_clock_timer_info *clock_timer_info; -#ifdef BSP_USING_TIM1_HWTIMER - hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device1.periph); - hwtimer_device1.parent.info = hwtimer_info; - hwtimer_device1.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device1.parent, hwtimer_device1.name, RT_NULL); +#ifdef BSP_USING_TIM1_CLOCK_TIMER + clock_timer_info = ch32f1_clock_timer_info_config_get(clock_timer_device1.periph); + clock_timer_device1.parent.info = clock_timer_info; + clock_timer_device1.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device1.parent, clock_timer_device1.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device1.name); + LOG_D("clock_timer: %s register success.", clock_timer_device1.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device1.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device1.name); } #endif -#ifdef BSP_USING_TIM2_HWTIMER - hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device2.periph); - hwtimer_device2.parent.info = hwtimer_info; - hwtimer_device2.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device2.parent, hwtimer_device2.name, RT_NULL); +#ifdef BSP_USING_TIM2_CLOCK_TIMER + clock_timer_info = ch32f1_clock_timer_info_config_get(clock_timer_device2.periph); + clock_timer_device2.parent.info = clock_timer_info; + clock_timer_device2.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device2.parent, clock_timer_device2.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device2.name); + LOG_D("clock_timer: %s register success.", clock_timer_device2.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device2.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device2.name); } #endif -#ifdef BSP_USING_TIM3_HWTIMER - hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device3.periph); - hwtimer_device3.parent.info = hwtimer_info; - hwtimer_device3.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device3.parent, hwtimer_device3.name, RT_NULL); +#ifdef BSP_USING_TIM3_CLOCK_TIMER + clock_timer_info = ch32f1_clock_timer_info_config_get(clock_timer_device3.periph); + clock_timer_device3.parent.info = clock_timer_info; + clock_timer_device3.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device3.parent, clock_timer_device3.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device3.name); + LOG_D("clock_timer: %s register success.", clock_timer_device3.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device3.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device3.name); } #endif -#ifdef BSP_USING_TIM4_HWTIMER - hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device4.periph); - hwtimer_device4.parent.info = hwtimer_info; - hwtimer_device4.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device4.parent, hwtimer_device4.name, RT_NULL); +#ifdef BSP_USING_TIM4_CLOCK_TIMER + clock_timer_info = ch32f1_clock_timer_info_config_get(clock_timer_device4.periph); + clock_timer_device4.parent.info = clock_timer_info; + clock_timer_device4.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device4.parent, clock_timer_device4.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device4.name); + LOG_D("clock_timer: %s register success.", clock_timer_device4.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device4.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device4.name); } #endif return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); -#ifdef BSP_USING_TIM1_HWTIMER +#ifdef BSP_USING_TIM1_CLOCK_TIMER void TIM1_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device1.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device1.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device1.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device1.parent); + TIM_ClearITPendingBit(clock_timer_device1.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device1.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM2_HWTIMER +#ifdef BSP_USING_TIM2_CLOCK_TIMER void TIM2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device2.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device2.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device2.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device2.parent); + TIM_ClearITPendingBit(clock_timer_device2.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device2.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM3_HWTIMER +#ifdef BSP_USING_TIM3_CLOCK_TIMER void TIM3_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device3.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device3.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device3.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device3.parent); + TIM_ClearITPendingBit(clock_timer_device3.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device3.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM4_HWTIMER +#ifdef BSP_USING_TIM4_CLOCK_TIMER void TIM4_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device4.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device4.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device4.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device4.parent); + TIM_ClearITPendingBit(clock_timer_device4.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device4.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f20x.c b/bsp/wch/arm/Libraries/ch32_drivers/drv_timer_ch32f20x.c similarity index 32% rename from bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f20x.c rename to bsp/wch/arm/Libraries/ch32_drivers/drv_timer_ch32f20x.c index 5bb45e7b36..17c92a80e0 100644 --- a/bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f20x.c +++ b/bsp/wch/arm/Libraries/ch32_drivers/drv_timer_ch32f20x.c @@ -12,103 +12,103 @@ #include #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER -#define LOG_TAG "drv.hwtimer" +#define LOG_TAG "drv.clock_timer" #include -struct hwtimer_device +struct clock_timer_device { - struct rt_hwtimer_device parent; + struct rt_clock_timer_device parent; TIM_TypeDef *periph; IRQn_Type irqn; char *name; }; -#ifdef BSP_USING_TIM1_HWTIMER -struct hwtimer_device hwtimer_device1 = +#ifdef BSP_USING_TIM1_CLOCK_TIMER +struct clock_timer_device clock_timer_device1 = { .periph = TIM1, .irqn = TIM1_UP_IRQn, .name = "timer1"}; #endif -#ifdef BSP_USING_TIM2_HWTIMER -struct hwtimer_device hwtimer_device2 = +#ifdef BSP_USING_TIM2_CLOCK_TIMER +struct clock_timer_device clock_timer_device2 = { .periph = TIM2, .irqn = TIM2_IRQn, .name = "timer2"}; #endif -#ifdef BSP_USING_TIM3_HWTIMER -struct hwtimer_device hwtimer_device3 = +#ifdef BSP_USING_TIM3_CLOCK_TIMER +struct clock_timer_device clock_timer_device3 = { .periph = TIM3, .irqn = TIM3_IRQn, .name = "timer3"}; #endif -#ifdef BSP_USING_TIM4_HWTIMER -struct hwtimer_device hwtimer_device4 = +#ifdef BSP_USING_TIM4_CLOCK_TIMER +struct clock_timer_device clock_timer_device4 = { .periph = TIM4, .irqn = TIM4_IRQn, .name = "timer4"}; #endif -#ifdef BSP_USING_TIM5_HWTIMER -struct hwtimer_device hwtimer_device5 = +#ifdef BSP_USING_TIM5_CLOCK_TIMER +struct clock_timer_device clock_timer_device5 = { .periph = TIM5, .irqn = TIM5_IRQn, .name = "timer5"}; #endif -#ifdef BSP_USING_TIM6_HWTIMER -struct hwtimer_device hwtimer_device6 = +#ifdef BSP_USING_TIM6_CLOCK_TIMER +struct clock_timer_device clock_timer_device6 = { .periph = TIM6, .irqn = TIM6_IRQn, .name = "timer6"}; #endif -#ifdef BSP_USING_TIM7_HWTIMER -struct hwtimer_device hwtimer_device7 = +#ifdef BSP_USING_TIM7_CLOCK_TIMER +struct clock_timer_device clock_timer_device7 = { .periph = TIM7, .irqn = TIM7_IRQn, .name = "timer7"}; #endif -#ifdef BSP_USING_TIM8_HWTIMER -struct hwtimer_device hwtimer_device8 = +#ifdef BSP_USING_TIM8_CLOCK_TIMER +struct clock_timer_device clock_timer_device8 = { .periph = TIM8, .irqn = TIM8_UP_IRQn, .name = "timer8"}; #endif -#ifdef BSP_USING_TIM9_HWTIMER -struct hwtimer_device hwtimer_device9 = +#ifdef BSP_USING_TIM9_CLOCK_TIMER +struct clock_timer_device clock_timer_device9 = { .periph = TIM9, .irqn = TIM9_UP_IRQn, .name = "timer9"}; #endif -#ifdef BSP_USING_TIM10_HWTIMER -struct hwtimer_device hwtimer_device10 = +#ifdef BSP_USING_TIM10_CLOCK_TIMER +struct clock_timer_device clock_timer_device10 = { .periph = TIM10, .irqn = TIM10_UP_IRQn, .name = "timer10"}; #endif -static void ch32f2_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t state) +static void ch32f2_clock_timer_init(struct rt_clock_timer_device *device, rt_uint32_t state) { - struct hwtimer_device *hwtimer_dev; - struct rt_hwtimer_info *hwtimer_info; + struct clock_timer_device *clock_timer_dev; + struct rt_clock_timer_info *clock_timer_info; rt_uint32_t clk = 0; rt_uint16_t prescaler_value = 0; @@ -117,34 +117,34 @@ static void ch32f2_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t st RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; if (state) { - ch32f2_tim_clock_init(hwtimer_dev->periph); + ch32f2_tim_clock_init(clock_timer_dev->periph); - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_dev->periph); + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_dev->periph); - clk = ch32f2_tim_clock_get(hwtimer_dev->periph); + clk = ch32f2_tim_clock_get(clock_timer_dev->periph); - prescaler_value = (rt_uint16_t)(clk / hwtimer_info->minfreq) - 1; + prescaler_value = (rt_uint16_t)(clk / clock_timer_info->minfreq) - 1; /* * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) ) */ - TIM_TimeBaseInitType.TIM_Period = hwtimer_info->maxcnt - 1; + TIM_TimeBaseInitType.TIM_Period = clock_timer_info->maxcnt - 1; TIM_TimeBaseInitType.TIM_Prescaler = prescaler_value; TIM_TimeBaseInitType.TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseInitType.TIM_RepetitionCounter = 0; - if (hwtimer_info == RT_NULL) + if (clock_timer_info == RT_NULL) { TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up; } else { - if (hwtimer_info->cntmode == HWTIMER_CNTMODE_UP) + if (clock_timer_info->cntmode == CLOCK_TIMER_CNTMODE_UP) { TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up; } @@ -154,89 +154,89 @@ static void ch32f2_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t st } } - TIM_TimeBaseInit(hwtimer_dev->periph, &TIM_TimeBaseInitType); + TIM_TimeBaseInit(clock_timer_dev->periph, &TIM_TimeBaseInitType); - NVIC_InitStructure.NVIC_IRQChannel = hwtimer_dev->irqn; + NVIC_InitStructure.NVIC_IRQChannel = clock_timer_dev->irqn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - TIM_ITConfig(hwtimer_dev->periph, TIM_IT_Update, ENABLE); - TIM_ClearITPendingBit(hwtimer_dev->periph, TIM_IT_Update); + TIM_ITConfig(clock_timer_dev->periph, TIM_IT_Update, ENABLE); + TIM_ClearITPendingBit(clock_timer_dev->periph, TIM_IT_Update); - LOG_D("%s init success", hwtimer_dev->name); + LOG_D("%s init success", clock_timer_dev->name); } } -static rt_err_t ch32f2_hwtimer_start(struct rt_hwtimer_device *device, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t ch32f2_clock_timer_start(struct rt_clock_timer_device *device, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; /* * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) ) */ - TIM_SetCounter(hwtimer_dev->periph, 0); - TIM_SetAutoreload(hwtimer_dev->periph, cnt - 1); + TIM_SetCounter(clock_timer_dev->periph, 0); + TIM_SetAutoreload(clock_timer_dev->periph, cnt - 1); - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { - TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Single); + TIM_SelectOnePulseMode(clock_timer_dev->periph, TIM_OPMode_Single); } else { - TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Repetitive); + TIM_SelectOnePulseMode(clock_timer_dev->periph, TIM_OPMode_Repetitive); } - TIM_Cmd(hwtimer_dev->periph, ENABLE); + TIM_Cmd(clock_timer_dev->periph, ENABLE); - LOG_D("%s start, cnt = %d", hwtimer_dev->name, cnt); + LOG_D("%s start, cnt = %d", clock_timer_dev->name, cnt); return RT_EOK; } -static void ch32f2_hwtimer_stop(struct rt_hwtimer_device *device) +static void ch32f2_clock_timer_stop(struct rt_clock_timer_device *device) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; - TIM_Cmd(hwtimer_dev->periph, DISABLE); + TIM_Cmd(clock_timer_dev->periph, DISABLE); - TIM_SetCounter(hwtimer_dev->periph, 0); + TIM_SetCounter(clock_timer_dev->periph, 0); } -static rt_uint32_t ch32f2_hwtimer_counter_get(struct rt_hwtimer_device *device) +static rt_uint32_t ch32f2_clock_timer_counter_get(struct rt_clock_timer_device *device) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; - return hwtimer_dev->periph->CNT; + return clock_timer_dev->periph->CNT; } -static rt_err_t ch32f2_hwtimer_control(struct rt_hwtimer_device *device, rt_uint32_t cmd, void *arg) +static rt_err_t ch32f2_clock_timer_control(struct rt_clock_timer_device *device, rt_uint32_t cmd, void *arg) { - struct hwtimer_device *hwtimer_dev; + struct clock_timer_device *clock_timer_dev; rt_err_t result = RT_EOK; RT_ASSERT(device != RT_NULL); - hwtimer_dev = (struct hwtimer_device *)device; + clock_timer_dev = (struct clock_timer_device *)device; switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq = 0; rt_uint32_t clk = 0; @@ -250,11 +250,11 @@ static rt_err_t ch32f2_hwtimer_control(struct rt_hwtimer_device *device, rt_uint freq = *((rt_uint32_t *)arg); - clk = ch32f2_tim_clock_get(hwtimer_dev->periph); + clk = ch32f2_tim_clock_get(clock_timer_dev->periph); prescaler_value = (rt_uint16_t)(clk / freq) - 1; - TIM_PrescalerConfig(hwtimer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate); + TIM_PrescalerConfig(clock_timer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate); } else { @@ -271,332 +271,332 @@ static rt_err_t ch32f2_hwtimer_control(struct rt_hwtimer_device *device, rt_uint return result; } -static const struct rt_hwtimer_ops hwtimer_ops = +static const struct rt_clock_timer_ops clock_timer_ops = { - .init = ch32f2_hwtimer_init, - .start = ch32f2_hwtimer_start, - .stop = ch32f2_hwtimer_stop, - .count_get = ch32f2_hwtimer_counter_get, - .control = ch32f2_hwtimer_control, + .init = ch32f2_clock_timer_init, + .start = ch32f2_clock_timer_start, + .stop = ch32f2_clock_timer_stop, + .count_get = ch32f2_clock_timer_counter_get, + .control = ch32f2_clock_timer_control, }; -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { rt_err_t ret; - struct rt_hwtimer_info *hwtimer_info; + struct rt_clock_timer_info *clock_timer_info; -#ifdef BSP_USING_TIM1_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device1.periph); - hwtimer_device1.parent.info = hwtimer_info; - hwtimer_device1.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device1.parent, hwtimer_device1.name, RT_NULL); +#ifdef BSP_USING_TIM1_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device1.periph); + clock_timer_device1.parent.info = clock_timer_info; + clock_timer_device1.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device1.parent, clock_timer_device1.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device1.name); + LOG_D("clock_timer: %s register success.", clock_timer_device1.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device1.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device1.name); } #endif -#ifdef BSP_USING_TIM2_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device2.periph); - hwtimer_device2.parent.info = hwtimer_info; - hwtimer_device2.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device2.parent, hwtimer_device2.name, RT_NULL); +#ifdef BSP_USING_TIM2_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device2.periph); + clock_timer_device2.parent.info = clock_timer_info; + clock_timer_device2.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device2.parent, clock_timer_device2.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device2.name); + LOG_D("clock_timer: %s register success.", clock_timer_device2.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device2.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device2.name); } #endif -#ifdef BSP_USING_TIM3_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device3.periph); - hwtimer_device3.parent.info = hwtimer_info; - hwtimer_device3.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device3.parent, hwtimer_device3.name, RT_NULL); +#ifdef BSP_USING_TIM3_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device3.periph); + clock_timer_device3.parent.info = clock_timer_info; + clock_timer_device3.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device3.parent, clock_timer_device3.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device3.name); + LOG_D("clock_timer: %s register success.", clock_timer_device3.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device3.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device3.name); } #endif -#ifdef BSP_USING_TIM4_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device4.periph); - hwtimer_device4.parent.info = hwtimer_info; - hwtimer_device4.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device4.parent, hwtimer_device4.name, RT_NULL); +#ifdef BSP_USING_TIM4_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device4.periph); + clock_timer_device4.parent.info = clock_timer_info; + clock_timer_device4.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device4.parent, clock_timer_device4.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device4.name); + LOG_D("clock_timer: %s register success.", clock_timer_device4.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device4.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device4.name); } #endif -#ifdef BSP_USING_TIM5_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device5.periph); - hwtimer_device5.parent.info = hwtimer_info; - hwtimer_device5.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device5.parent, hwtimer_device5.name, RT_NULL); +#ifdef BSP_USING_TIM5_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device5.periph); + clock_timer_device5.parent.info = clock_timer_info; + clock_timer_device5.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device5.parent, clock_timer_device5.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device5.name); + LOG_D("clock_timer: %s register success.", clock_timer_device5.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device5.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device5.name); } #endif -#ifdef BSP_USING_TIM6_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device6.periph); - hwtimer_device6.parent.info = hwtimer_info; - hwtimer_device6.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device6.parent, hwtimer_device6.name, RT_NULL); +#ifdef BSP_USING_TIM6_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device6.periph); + clock_timer_device6.parent.info = clock_timer_info; + clock_timer_device6.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device6.parent, clock_timer_device6.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device6.name); + LOG_D("clock_timer: %s register success.", clock_timer_device6.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device6.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device6.name); } #endif -#ifdef BSP_USING_TIM7_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device7.periph); - hwtimer_device7.parent.info = hwtimer_info; - hwtimer_device7.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device7.parent, hwtimer_device7.name, RT_NULL); +#ifdef BSP_USING_TIM7_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device7.periph); + clock_timer_device7.parent.info = clock_timer_info; + clock_timer_device7.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device7.parent, clock_timer_device7.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device7.name); + LOG_D("clock_timer: %s register success.", clock_timer_device7.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device7.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device7.name); } #endif -#ifdef BSP_USING_TIM8_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device8.periph); - hwtimer_device8.parent.info = hwtimer_info; - hwtimer_device8.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device8.parent, hwtimer_device8.name, RT_NULL); +#ifdef BSP_USING_TIM8_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device8.periph); + clock_timer_device8.parent.info = clock_timer_info; + clock_timer_device8.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device8.parent, clock_timer_device8.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device8.name); + LOG_D("clock_timer: %s register success.", clock_timer_device8.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device8.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device8.name); } #endif -#ifdef BSP_USING_TIM9_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device9.periph); - hwtimer_device9.parent.info = hwtimer_info; - hwtimer_device9.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device9.parent, hwtimer_device9.name, RT_NULL); +#ifdef BSP_USING_TIM9_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device9.periph); + clock_timer_device9.parent.info = clock_timer_info; + clock_timer_device9.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device9.parent, clock_timer_device9.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device9.name); + LOG_D("clock_timer: %s register success.", clock_timer_device9.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device9.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device9.name); } #endif -#ifdef BSP_USING_TIM10_HWTIMER - hwtimer_info = ch32f2_hwtimer_info_config_get(hwtimer_device10.periph); - hwtimer_device10.parent.info = hwtimer_info; - hwtimer_device10.parent.ops = &hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer_device10.parent, hwtimer_device10.name, RT_NULL); +#ifdef BSP_USING_TIM10_CLOCK_TIMER + clock_timer_info = ch32f2_clock_timer_info_config_get(clock_timer_device10.periph); + clock_timer_device10.parent.info = clock_timer_info; + clock_timer_device10.parent.ops = &clock_timer_ops; + ret = rt_clock_timer_register(&clock_timer_device10.parent, clock_timer_device10.name, RT_NULL); if (ret == RT_EOK) { - LOG_D("hwtimer: %s register success.", hwtimer_device10.name); + LOG_D("clock_timer: %s register success.", clock_timer_device10.name); } else { - LOG_D("hwtimer: %s register failed.", hwtimer_device10.name); + LOG_D("clock_timer: %s register failed.", clock_timer_device10.name); } #endif return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); -#ifdef BSP_USING_TIM1_HWTIMER +#ifdef BSP_USING_TIM1_CLOCK_TIMER void TIM1_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device1.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device1.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device1.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device1.parent); + TIM_ClearITPendingBit(clock_timer_device1.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device1.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM2_HWTIMER +#ifdef BSP_USING_TIM2_CLOCK_TIMER void TIM2_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device2.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device2.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device2.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device2.parent); + TIM_ClearITPendingBit(clock_timer_device2.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device2.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM3_HWTIMER +#ifdef BSP_USING_TIM3_CLOCK_TIMER void TIM3_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device3.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device3.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device3.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device3.parent); + TIM_ClearITPendingBit(clock_timer_device3.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device3.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM4_HWTIMER +#ifdef BSP_USING_TIM4_CLOCK_TIMER void TIM4_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device4.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device4.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device4.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device4.parent); + TIM_ClearITPendingBit(clock_timer_device4.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device4.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM5_HWTIMER +#ifdef BSP_USING_TIM5_CLOCK_TIMER void TIM5_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device5.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device5.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device5.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device5.parent); + TIM_ClearITPendingBit(clock_timer_device5.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device5.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM6_HWTIMER +#ifdef BSP_USING_TIM6_CLOCK_TIMER void TIM6_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device6.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device6.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device6.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device6.parent); + TIM_ClearITPendingBit(clock_timer_device6.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device6.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM7_HWTIMER +#ifdef BSP_USING_TIM7_CLOCK_TIMER void TIM7_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device7.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device7.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device7.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device7.parent); + TIM_ClearITPendingBit(clock_timer_device7.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device7.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM8_HWTIMER +#ifdef BSP_USING_TIM8_CLOCK_TIMER void TIM8_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device8.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device8.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device8.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device8.parent); + TIM_ClearITPendingBit(clock_timer_device8.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device8.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM9_HWTIMER +#ifdef BSP_USING_TIM9_CLOCK_TIMER void TIM9_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device9.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device9.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device9.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device9.parent); + TIM_ClearITPendingBit(clock_timer_device9.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device9.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#ifdef BSP_USING_TIM10_HWTIMER +#ifdef BSP_USING_TIM10_CLOCK_TIMER void TIM10_UP_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - if (TIM_GetITStatus(hwtimer_device10.periph, TIM_IT_Update) == SET) + if (TIM_GetITStatus(clock_timer_device10.periph, TIM_IT_Update) == SET) { - TIM_ClearITPendingBit(hwtimer_device10.periph, TIM_IT_Update); - rt_device_hwtimer_isr(&hwtimer_device10.parent); + TIM_ClearITPendingBit(clock_timer_device10.periph, TIM_IT_Update); + rt_clock_timer_isr(&clock_timer_device10.parent); } /* leave interrupt */ rt_interrupt_leave(); } #endif -#endif /* BSP_USING_HWTIMER */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/wch/arm/ch32f103c8-core/board/Kconfig b/bsp/wch/arm/ch32f103c8-core/board/Kconfig index beac3e7972..1f2345562f 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/Kconfig +++ b/bsp/wch/arm/ch32f103c8-core/board/Kconfig @@ -85,9 +85,9 @@ config BSP_USING_TIM default n if BSP_USING_TIM - config BSP_USING_HWTIMER + config BSP_USING_CLOCK_TIMER bool - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n config BSP_USING_PWM @@ -101,12 +101,12 @@ config BSP_USING_TIM if BSP_USING_TIM1 choice - prompt "using TIM1 as hwtimer or PWM mode" - default BSP_USING_TIM1_HWTIMER + prompt "using TIM1 as clock_timer or PWM mode" + default BSP_USING_TIM1_CLOCK_TIMER - config BSP_USING_TIM1_HWTIMER - bool "using TIM1 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM1_CLOCK_TIMER + bool "using TIM1 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM1_PWM bool "using TIM1 as PWM mode" @@ -139,12 +139,12 @@ config BSP_USING_TIM if BSP_USING_TIM2 choice - prompt "using TIM2 as hwtimer or PWM mode" - default BSP_USING_TIM2_HWTIMER + prompt "using TIM2 as clock_timer or PWM mode" + default BSP_USING_TIM2_CLOCK_TIMER - config BSP_USING_TIM2_HWTIMER - bool "using TIM2 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM2_CLOCK_TIMER + bool "using TIM2 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM2_PWM bool "using TIM2 as PWM mode" @@ -177,12 +177,12 @@ config BSP_USING_TIM if BSP_USING_TIM3 choice - prompt "using TIM3 as hwtimer or PWM mode" - default BSP_USING_TIM3_HWTIMER + prompt "using TIM3 as clock_timer or PWM mode" + default BSP_USING_TIM3_CLOCK_TIMER - config BSP_USING_TIM3_HWTIMER - bool "using TIM3 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM3_CLOCK_TIMER + bool "using TIM3 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM3_PWM bool "using TIM3 as PWM mode" @@ -215,12 +215,12 @@ config BSP_USING_TIM if BSP_USING_TIM4 choice - prompt "using TIM4 as hwtimer or PWM mode" - default BSP_USING_TIM4_HWTIMER + prompt "using TIM4 as clock_timer or PWM mode" + default BSP_USING_TIM4_CLOCK_TIMER - config BSP_USING_TIM4_HWTIMER - bool "using TIM4 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM4_CLOCK_TIMER + bool "using TIM4 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM4_PWM bool "using TIM4 as PWM mode" diff --git a/bsp/wch/arm/ch32f103c8-core/board/board.c b/bsp/wch/arm/ch32f103c8-core/board/board.c index f1d3773fa6..e2a06a3a37 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/board.c +++ b/bsp/wch/arm/ch32f103c8-core/board/board.c @@ -234,61 +234,61 @@ rt_uint32_t ch32f1_tim_clock_get(TIM_TypeDef *timx) return RCC_Clocks.HCLK_Frequency; } -struct rt_hwtimer_info hwtimer_info1 = +struct rt_clock_timer_info clock_timer_info1 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info2 = +struct rt_clock_timer_info clock_timer_info2 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info3 = +struct rt_clock_timer_info clock_timer_info3 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info4 = +struct rt_clock_timer_info clock_timer_info4 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info *ch32f1_hwtimer_info_config_get(TIM_TypeDef *timx) +struct rt_clock_timer_info *ch32f1_clock_timer_info_config_get(TIM_TypeDef *timx) { - struct rt_hwtimer_info *info = RT_NULL; + struct rt_clock_timer_info *info = RT_NULL; if (timx == TIM1) { - info = &hwtimer_info1; + info = &clock_timer_info1; } else if (timx == TIM2) { - info = &hwtimer_info2; + info = &clock_timer_info2; } else if (timx == TIM3) { - info = &hwtimer_info3; + info = &clock_timer_info3; } else if (timx == TIM4) { - info = &hwtimer_info4; + info = &clock_timer_info4; } return info; diff --git a/bsp/wch/arm/ch32f103c8-core/board/board.h b/bsp/wch/arm/ch32f103c8-core/board/board.h index f4073203a7..433895224a 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/board.h +++ b/bsp/wch/arm/ch32f103c8-core/board/board.h @@ -64,8 +64,8 @@ void ch32f1_i2c_config(I2C_TypeDef* i2cx); void ch32f1_tim_clock_init(TIM_TypeDef *timx); rt_uint32_t ch32f1_tim_clock_get(TIM_TypeDef *timx); -#ifdef BSP_USING_HWTIMER -struct rt_hwtimer_info* ch32f1_hwtimer_info_config_get(TIM_TypeDef *timx); +#ifdef BSP_USING_CLOCK_TIMER +struct rt_clock_timer_info* ch32f1_clock_timer_info_config_get(TIM_TypeDef *timx); #endif #ifdef BSP_USING_PWM diff --git a/bsp/wch/arm/ch32f10x_port_cn.md b/bsp/wch/arm/ch32f10x_port_cn.md index ff0f3d9313..577d59d10e 100644 --- a/bsp/wch/arm/ch32f10x_port_cn.md +++ b/bsp/wch/arm/ch32f10x_port_cn.md @@ -49,19 +49,19 @@ void ch32f1_i2c_config(I2C_TypeDef* i2cx); + BSP_USING_RTC + BSP_USING_RTC_LSI + LSI_VALUE -+ HWTIMER 1/2/3/4 - + RT_USING_HWTIMER - + BSP_USING_HWTIMER - + BSP_USING_TIM1_HWTIMER - + BSP_USING_TIM2_HWTIMER - + BSP_USING_TIM3_HWTIMER - + BSP_USING_TIM4_HWTIMER ++ CLOCK_TIMER 1/2/3/4 + + RT_USING_CLOCK_TIME + + BSP_USING_CLOCK_TIMER + + BSP_USING_TIM1_CLOCK_TIMER + + BSP_USING_TIM2_CLOCK_TIMER + + BSP_USING_TIM3_CLOCK_TIMER + + BSP_USING_TIM4_CLOCK_TIMER ~~~c void ch32f1_tim_clock_init(TIM_TypeDef *timx); rt_uint32_t ch32f1_tim_clock_get(TIM_TypeDef *timx); ~~~ ~~~c -struct rt_hwtimer_info* ch32f1_hwtimer_info_config_get(TIM_TypeDef *timx); +struct rt_clock_timer_info* ch32f1_clock_timer_info_config_get(TIM_TypeDef *timx); ~~~ + PWM 4(timer) x 4 (channel) + RT_USING_PWM @@ -189,8 +189,8 @@ void ch32f1_usart_clock_and_io_init(USART_TypeDef* usartx); void ch32f1_tim_clock_init(TIM_TypeDef *timx); rt_uint32_t ch32f1_tim_clock_get(TIM_TypeDef *timx); -#ifdef BSP_USING_HWTIMER -struct rt_hwtimer_info* ch32f1_hwtimer_info_config_get(TIM_TypeDef *timx); +#ifdef BSP_USING_CLOCK_TIMER +struct rt_clock_timer_info* ch32f1_clock_timer_info_config_get(TIM_TypeDef *timx); #endif #ifdef BSP_USING_PWM diff --git a/bsp/wch/arm/ch32f203r-evt/README.md b/bsp/wch/arm/ch32f203r-evt/README.md index 7e2cd04716..af53579eb6 100644 --- a/bsp/wch/arm/ch32f203r-evt/README.md +++ b/bsp/wch/arm/ch32f203r-evt/README.md @@ -31,7 +31,7 @@ | SPI | 支持 | SPI 1~3 | | WDT | 支持 | IWDG | | RTC | 支持 | 外部或内部低速晶振 | -| HWTIMER | 支持 |定时器 1~10 | +| CLOCK_TIMER | 支持 |定时器 1~10 | | PWM | 支持 |定时器 1~5, 8~10(每个定时器包括4个通道) | diff --git a/bsp/wch/arm/ch32f203r-evt/board/Kconfig b/bsp/wch/arm/ch32f203r-evt/board/Kconfig index 74ef7c3dcf..d83f9257b8 100644 --- a/bsp/wch/arm/ch32f203r-evt/board/Kconfig +++ b/bsp/wch/arm/ch32f203r-evt/board/Kconfig @@ -109,9 +109,9 @@ config BSP_USING_TIM default n if BSP_USING_TIM - config BSP_USING_HWTIMER + config BSP_USING_CLOCK_TIMER bool - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n config BSP_USING_PWM @@ -125,12 +125,12 @@ config BSP_USING_TIM if BSP_USING_TIM1 choice - prompt "using TIM1 as hwtimer or PWM mode" - default BSP_USING_TIM1_HWTIMER + prompt "using TIM1 as clock_timer or PWM mode" + default BSP_USING_TIM1_CLOCK_TIMER - config BSP_USING_TIM1_HWTIMER - bool "using TIM1 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM1_CLOCK_TIMER + bool "using TIM1 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM1_PWM bool "using TIM1 as PWM mode" @@ -163,12 +163,12 @@ config BSP_USING_TIM if BSP_USING_TIM2 choice - prompt "using TIM2 as hwtimer or PWM mode" - default BSP_USING_TIM2_HWTIMER + prompt "using TIM2 as clock_timer or PWM mode" + default BSP_USING_TIM2_CLOCK_TIMER - config BSP_USING_TIM2_HWTIMER - bool "using TIM2 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM2_CLOCK_TIMER + bool "using TIM2 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM2_PWM bool "using TIM2 as PWM mode" @@ -201,12 +201,12 @@ config BSP_USING_TIM if BSP_USING_TIM3 choice - prompt "using TIM3 as hwtimer or PWM mode" - default BSP_USING_TIM3_HWTIMER + prompt "using TIM3 as clock_timer or PWM mode" + default BSP_USING_TIM3_CLOCK_TIMER - config BSP_USING_TIM3_HWTIMER - bool "using TIM3 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM3_CLOCK_TIMER + bool "using TIM3 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM3_PWM bool "using TIM3 as PWM mode" @@ -239,12 +239,12 @@ config BSP_USING_TIM if BSP_USING_TIM4 choice - prompt "using TIM4 as hwtimer or PWM mode" - default BSP_USING_TIM4_HWTIMER + prompt "using TIM4 as clock_timer or PWM mode" + default BSP_USING_TIM4_CLOCK_TIMER - config BSP_USING_TIM4_HWTIMER - bool "using TIM4 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM4_CLOCK_TIMER + bool "using TIM4 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM4_PWM bool "using TIM4 as PWM mode" @@ -277,12 +277,12 @@ config BSP_USING_TIM if BSP_USING_TIM4 choice - prompt "using TIM5 as hwtimer or PWM mode" - default BSP_USING_TIM5_HWTIMER + prompt "using TIM5 as clock_timer or PWM mode" + default BSP_USING_TIM5_CLOCK_TIMER - config BSP_USING_TIM5_HWTIMER - bool "using TIM5 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM5_CLOCK_TIMER + bool "using TIM5 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM5_PWM bool "using TIM5 as PWM mode" @@ -315,9 +315,9 @@ config BSP_USING_TIM if BSP_USING_TIM6 - config BSP_USING_TIM6_HWTIMER - bool "using TIM6 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM6_CLOCK_TIMER + bool "using TIM6 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endif @@ -327,9 +327,9 @@ config BSP_USING_TIM if BSP_USING_TIM7 - config BSP_USING_TIM7_HWTIMER - bool "using TIM7 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM7_CLOCK_TIMER + bool "using TIM7 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endif @@ -339,12 +339,12 @@ config BSP_USING_TIM if BSP_USING_TIM8 choice - prompt "using TIM8 as hwtimer or PWM mode" - default BSP_USING_TIM8_HWTIMER + prompt "using TIM8 as clock_timer or PWM mode" + default BSP_USING_TIM8_CLOCK_TIMER - config BSP_USING_TIM8_HWTIMER - bool "using TIM8 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM8_CLOCK_TIMER + bool "using TIM8 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM8_PWM bool "using TIM8 as PWM mode" @@ -377,12 +377,12 @@ config BSP_USING_TIM if BSP_USING_TIM9 choice - prompt "using TIM9 as hwtimer or PWM mode" - default BSP_USING_TIM9_HWTIMER + prompt "using TIM9 as clock_timer or PWM mode" + default BSP_USING_TIM9_CLOCK_TIMER - config BSP_USING_TIM9_HWTIMER - bool "using TIM9 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM9_CLOCK_TIMER + bool "using TIM9 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM9_PWM bool "using TIM9 as PWM mode" @@ -415,12 +415,12 @@ config BSP_USING_TIM if BSP_USING_TIM10 choice - prompt "using TIM10 as hwtimer or PWM mode" - default BSP_USING_TIM10_HWTIMER + prompt "using TIM10 as clock_timer or PWM mode" + default BSP_USING_TIM10_CLOCK_TIMER - config BSP_USING_TIM10_HWTIMER - bool "using TIM10 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM10_CLOCK_TIMER + bool "using TIM10 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM10_PWM bool "using TIM10 as PWM mode" diff --git a/bsp/wch/arm/ch32f203r-evt/board/board.c b/bsp/wch/arm/ch32f203r-evt/board/board.c index 50593beaeb..f9bb1ba249 100644 --- a/bsp/wch/arm/ch32f203r-evt/board/board.c +++ b/bsp/wch/arm/ch32f203r-evt/board/board.c @@ -303,7 +303,7 @@ void ch32f2_i2c_config(I2C_TypeDef *i2cx) } } -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER void ch32f2_tim_clock_init(TIM_TypeDef *timx) { if (timx == TIM1) @@ -379,143 +379,143 @@ rt_uint32_t ch32f2_tim_clock_get(TIM_TypeDef *timx) return ppre1 >= 4 ? RCC_Clocks.PCLK1_Frequency * 2 : RCC_Clocks.PCLK1_Frequency; } -struct rt_hwtimer_info hwtimer_info1 = +struct rt_clock_timer_info clock_timer_info1 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info2 = +struct rt_clock_timer_info clock_timer_info2 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info3 = +struct rt_clock_timer_info clock_timer_info3 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info4 = +struct rt_clock_timer_info clock_timer_info4 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info5 = +struct rt_clock_timer_info clock_timer_info5 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info6 = +struct rt_clock_timer_info clock_timer_info6 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info7 = +struct rt_clock_timer_info clock_timer_info7 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info8 = +struct rt_clock_timer_info clock_timer_info8 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info9 = +struct rt_clock_timer_info clock_timer_info9 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info hwtimer_info10 = +struct rt_clock_timer_info clock_timer_info10 = { .maxfreq = 1000000, .minfreq = 2000, .maxcnt = 0xFFFF, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }; -struct rt_hwtimer_info *ch32f2_hwtimer_info_config_get(TIM_TypeDef *timx) +struct rt_clock_timer_info *ch32f2_clock_timer_info_config_get(TIM_TypeDef *timx) { - struct rt_hwtimer_info *info = RT_NULL; + struct rt_clock_timer_info *info = RT_NULL; if (timx == TIM1) { - info = &hwtimer_info1; + info = &clock_timer_info1; } else if (timx == TIM2) { - info = &hwtimer_info2; + info = &clock_timer_info2; } else if (timx == TIM3) { - info = &hwtimer_info3; + info = &clock_timer_info3; } else if (timx == TIM4) { - info = &hwtimer_info4; + info = &clock_timer_info4; } else if (timx == TIM4) { - info = &hwtimer_info4; + info = &clock_timer_info4; } else if (timx == TIM5) { - info = &hwtimer_info5; + info = &clock_timer_info5; } else if (timx == TIM6) { - info = &hwtimer_info6; + info = &clock_timer_info6; } else if (timx == TIM7) { - info = &hwtimer_info7; + info = &clock_timer_info7; } else if (timx == TIM8) { - info = &hwtimer_info8; + info = &clock_timer_info8; } else if (timx == TIM9) { - info = &hwtimer_info9; + info = &clock_timer_info9; } else if (timx == TIM10) { - info = &hwtimer_info10; + info = &clock_timer_info10; } return info; diff --git a/bsp/wch/arm/ch32f203r-evt/board/board.h b/bsp/wch/arm/ch32f203r-evt/board/board.h index 6a3b8eedfb..c4ae16e4b2 100644 --- a/bsp/wch/arm/ch32f203r-evt/board/board.h +++ b/bsp/wch/arm/ch32f203r-evt/board/board.h @@ -64,8 +64,8 @@ void ch32f2_i2c_config(I2C_TypeDef* i2cx); void ch32f2_tim_clock_init(TIM_TypeDef *timx); rt_uint32_t ch32f2_tim_clock_get(TIM_TypeDef *timx); -#ifdef BSP_USING_HWTIMER -struct rt_hwtimer_info* ch32f2_hwtimer_info_config_get(TIM_TypeDef *timx); +#ifdef BSP_USING_CLOCK_TIMER +struct rt_clock_timer_info* ch32f2_clock_timer_info_config_get(TIM_TypeDef *timx); #endif #ifdef BSP_USING_PWM diff --git a/bsp/wch/arm/ch32f203r-evt/project.uvprojx b/bsp/wch/arm/ch32f203r-evt/project.uvprojx index 3c8b1d23a4..52e072f039 100644 --- a/bsp/wch/arm/ch32f203r-evt/project.uvprojx +++ b/bsp/wch/arm/ch32f203r-evt/project.uvprojx @@ -618,9 +618,9 @@ - hwtimer.c + clock_timer.c 1 - ..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\components\drivers\clock_time\clock_timer.c @@ -1036,9 +1036,9 @@ - drv_hwtimer_ch32f20x.c + drv_timer_ch32f20x.c 1 - ..\Libraries\ch32_drivers\drv_hwtimer_ch32f20x.c + ..\Libraries\ch32_drivers\drv_timer_ch32f20x.c diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript index f87d0b1ea1..537dd03f72 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/SConscript @@ -51,8 +51,8 @@ if GetDepend('SOC_RISCV_FAMILY_CH32'): if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] - if GetDepend('BSP_USING_HWTIMER'): - src += ['drv_hwtimer.c'] + if GetDepend('BSP_USING_CLOCK_TIMER'): + src += ['drv_timer.c'] if GetDepend(['BSP_USING_ON_CHIP_FLASH']): src += ['drv_flash.c'] diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.h index ec8db3aec7..9e73e4b8b1 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.h +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.h @@ -20,7 +20,7 @@ #include "ch32v20x_tim.h" #endif #include -#include +#include #include #define MAX_COUNTER 65535 diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_timer.c similarity index 76% rename from bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c rename to bsp/wch/risc-v/Libraries/ch32_drivers/drv_timer.c index c4f227156b..f58196620b 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_timer.c @@ -11,15 +11,15 @@ #include #include -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER #define DBG_TAG "TIM" #define DBG_LVL DBG_LOG #include -#include "drv_hwtimer.h" +#include "drv_timer.h" #include "board.h" -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME enum { @@ -55,7 +55,7 @@ enum #endif }; -static struct ch32_hwtimer ch32_hwtimer_obj[] = +static struct ch32_clock_timer ch32_clock_timer_obj[] = { #ifdef BSP_USING_TIM1 TIM1_CONFIG, @@ -126,13 +126,13 @@ void ch32_get_pclk_doubler(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_double } } -static void ch32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +static void ch32_clock_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { RT_ASSERT(timer != RT_NULL); TIM_HandleTypeDef *tim = RT_NULL; RCC_ClocksTypeDef RCC_ClockStruct; NVIC_InitTypeDef NVIC_InitStruct; - struct ch32_hwtimer *tim_device = RT_NULL; + struct ch32_clock_timer *tim_device = RT_NULL; rt_uint32_t prescaler_value = 0; rt_uint32_t pclk1_doubler, pclk2_doubler; @@ -142,7 +142,7 @@ static void ch32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state if(state) { tim = (TIM_HandleTypeDef *)timer->parent.user_data; - tim_device = (struct ch32_hwtimer *)timer; + tim_device = (struct ch32_clock_timer *)timer; #if defined (SOC_RISCV_SERIES_CH32V2) if(tim->instance == TIM1) @@ -167,7 +167,7 @@ static void ch32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state tim->init.TIM_Period = 10000 - 1; tim->init.TIM_RepetitionCounter = 0; - if(timer->info->cntmode == HWTIMER_CNTMODE_UP) + if(timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { tim->init.TIM_CounterMode = TIM_CounterMode_Up; } @@ -195,7 +195,7 @@ static void ch32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state } } -static rt_err_t ch32_hwtimer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t ch32_clock_timer_start(struct rt_clock_timer_device *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode) { RT_ASSERT(timer != RT_NULL); TIM_HandleTypeDef *tim = RT_NULL; @@ -207,7 +207,7 @@ static rt_err_t ch32_hwtimer_start(struct rt_hwtimer_device *timer, rt_uint32_t tim->instance->ATRLR = cnt - 1; tim->init.TIM_Period = cnt - 1; - if (mode == HWTIMER_MODE_ONESHOT) + if (mode == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM); @@ -225,7 +225,7 @@ static rt_err_t ch32_hwtimer_start(struct rt_hwtimer_device *timer, rt_uint32_t return RT_EOK; } -static void ch32_hwtimer_stop(struct rt_hwtimer_device *timer) +static void ch32_clock_timer_stop(struct rt_clock_timer_device *timer) { RT_ASSERT(timer != RT_NULL); TIM_HandleTypeDef *tim = RT_NULL; @@ -239,7 +239,7 @@ static void ch32_hwtimer_stop(struct rt_hwtimer_device *timer) tim->instance->CNT = 0; } -static rt_uint32_t ch32_hwtimer_count_get(struct rt_hwtimer_device *timer) +static rt_uint32_t ch32_clock_timer_count_get(struct rt_clock_timer_device *timer) { RT_ASSERT(timer != RT_NULL); TIM_HandleTypeDef *tim = RT_NULL; @@ -248,7 +248,7 @@ static rt_uint32_t ch32_hwtimer_count_get(struct rt_hwtimer_device *timer) return tim->instance->CNT; } -static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args) +static rt_err_t ch32_clock_timer_control(struct rt_clock_timer_device *timer, rt_uint32_t cmd, void *args) { RT_ASSERT(timer != RT_NULL); RT_ASSERT(args != RT_NULL); @@ -261,7 +261,7 @@ static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint16_t val; @@ -297,9 +297,9 @@ static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ break; } - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: { - if (*(rt_hwtimer_mode_t *)args == HWTIMER_MODE_ONESHOT) + if (*(rt_clock_timer_mode_t *)args == CLOCK_TIMER_MODE_ONESHOT) { /* set timer to single mode */ tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM); @@ -313,15 +313,15 @@ static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ break; } - case HWTIMER_CTRL_INFO_GET: + case CLOCK_TIMER_CTRL_INFO_GET: { - *(rt_hwtimer_mode_t *)args = tim->instance->CNT; + *(rt_clock_timer_mode_t *)args = tim->instance->CNT; break; } - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: { - ch32_hwtimer_stop(timer); + ch32_clock_timer_stop(timer); break; } @@ -335,26 +335,26 @@ static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ return result; } -static const struct rt_hwtimer_info ch32_hwtimer_info = TIM_DEV_INFO_CONFIG; -static const struct rt_hwtimer_ops ch32_hwtimer_ops = +static const struct rt_clock_timer_info ch32_clock_timer_info = TIM_DEV_INFO_CONFIG; +static const struct rt_clock_timer_ops ch32_clock_timer_ops = { - ch32_hwtimer_init, - ch32_hwtimer_start, - ch32_hwtimer_stop, - ch32_hwtimer_count_get, - ch32_hwtimer_control + ch32_clock_timer_init, + ch32_clock_timer_start, + ch32_clock_timer_stop, + ch32_clock_timer_count_get, + ch32_clock_timer_control }; -static void ch32_hwtimer_isr(struct rt_hwtimer_device *device) +static void ch32_clock_timer_isr(struct rt_clock_timer_device *device) { RT_ASSERT(device != RT_NULL); - struct ch32_hwtimer *hwtimer = RT_NULL; - hwtimer = rt_container_of(device, struct ch32_hwtimer, device); + struct ch32_clock_timer *clock_timer = RT_NULL; + clock_timer = rt_container_of(device, struct ch32_clock_timer, device); - if(TIM_GetITStatus(hwtimer->handle.instance, TIM_IT_Update) != RESET) + if(TIM_GetITStatus(clock_timer->handle.instance, TIM_IT_Update) != RESET) { - rt_device_hwtimer_isr(device); - TIM_ClearITPendingBit(hwtimer->handle.instance, TIM_IT_Update); + rt_clock_timer_isr(device); + TIM_ClearITPendingBit(clock_timer->handle.instance, TIM_IT_Update); } } @@ -364,7 +364,7 @@ void TIM1_UP_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM1_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM1_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -376,7 +376,7 @@ void TIM2_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM2_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM2_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -388,7 +388,7 @@ void TIM3_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM3_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM3_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -400,7 +400,7 @@ void TIM4_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM4_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM4_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -412,7 +412,7 @@ void TIM5_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM5_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM5_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -424,7 +424,7 @@ void TIM6_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM6_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM6_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -436,7 +436,7 @@ void TIM7_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM7_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM7_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -448,7 +448,7 @@ void TIM8_UP_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM8_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM8_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -460,7 +460,7 @@ void TIM9_UP_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM9_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM9_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -472,7 +472,7 @@ void TIM10_UP_IRQHandler(void) { GET_INT_SP(); rt_interrupt_enter(); - ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM10_INDEX].device)); + ch32_clock_timer_isr(&(ch32_clock_timer_obj[TIM10_INDEX].device)); rt_interrupt_leave(); FREE_INT_SP(); } @@ -483,12 +483,12 @@ static int rt_hw_timer_init(void) int i = 0; int result = RT_EOK; - for (i = 0; i < sizeof(ch32_hwtimer_obj) / sizeof(ch32_hwtimer_obj[0]); i++) + for (i = 0; i < sizeof(ch32_clock_timer_obj) / sizeof(ch32_clock_timer_obj[0]); i++) { - ch32_hwtimer_obj[i].device.info = &ch32_hwtimer_info; - ch32_hwtimer_obj[i].device.ops = &ch32_hwtimer_ops; - result = rt_device_hwtimer_register(&ch32_hwtimer_obj[i].device, - ch32_hwtimer_obj[i].name, (void *)&ch32_hwtimer_obj[i].handle); + ch32_clock_timer_obj[i].device.info = &ch32_clock_timer_info; + ch32_clock_timer_obj[i].device.ops = &ch32_clock_timer_ops; + result = rt_clock_timer_register(&ch32_clock_timer_obj[i].device, + ch32_clock_timer_obj[i].name, (void *)&ch32_clock_timer_obj[i].handle); RT_ASSERT(result == RT_EOK); } @@ -496,5 +496,5 @@ static int rt_hw_timer_init(void) } INIT_BOARD_EXPORT(rt_hw_timer_init); -#endif /* RT_USING_HWTIMER */ -#endif /* BSP_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ +#endif /* BSP_USING_CLOCK_TIMER */ diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_timer.h similarity index 94% rename from bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.h rename to bsp/wch/risc-v/Libraries/ch32_drivers/drv_timer.h index 10ed383746..685b55a87e 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.h +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_timer.h @@ -8,8 +8,8 @@ * 2022-09-10 MXH the first version */ -#ifndef __DRV_HWTIMER_H__ -#define __DRV_HWTIMER_H__ +#ifndef __DRV_CLOCK_TIMER_H__ +#define __DRV_CLOCK_TIMER_H__ #include #if defined(SOC_RISCV_SERIES_CH32V3) @@ -19,7 +19,7 @@ #include "ch32v20x_tim.h" #endif -#ifdef BSP_USING_HWTIMER +#ifdef BSP_USING_CLOCK_TIMER typedef struct { @@ -29,9 +29,9 @@ typedef struct }TIM_HandleTypeDef; -struct ch32_hwtimer +struct ch32_clock_timer { - rt_hwtimer_t device; + rt_clock_timer_t device; TIM_HandleTypeDef handle; IRQn_Type irqn; char *name; @@ -44,7 +44,7 @@ struct ch32_hwtimer .maxfreq = 1000000, \ .minfreq = 3000, \ .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ + .cntmode = CLOCK_TIMER_CNTMODE_UP, \ } #endif /* TIM_DEV_INFO_CONFIG */ @@ -148,5 +148,5 @@ struct ch32_hwtimer } #endif /* BSP_USING_TIM10 */ -#endif /* BSP_USING_HWTIMER */ -#endif /* __DRV_HWTIMER_H__ */ +#endif /* BSP_USING_CLOCK_TIMER */ +#endif /* __DRV_CLOCK_TIMER_H__ */ diff --git a/bsp/wch/risc-v/Libraries/ch56x_drivers/SConscript b/bsp/wch/risc-v/Libraries/ch56x_drivers/SConscript index b92cfcb3db..8c6988aa60 100644 --- a/bsp/wch/risc-v/Libraries/ch56x_drivers/SConscript +++ b/bsp/wch/risc-v/Libraries/ch56x_drivers/SConscript @@ -18,7 +18,7 @@ if GetDepend('RT_USING_USB_DEVICE'): if GetDepend('RT_USING_PWM'): src += ['ch56x_pwm.c'] -if GetDepend('RT_USING_HWTIMER'): +if GetDepend('RT_USING_CLOCK_TIME'): src += ['ch56x_timer.c'] if GetDepend('RT_USING_SPI'): diff --git a/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_timer.c b/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_timer.c index 2c8411d6fd..e59cd04f6f 100644 --- a/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_timer.c +++ b/bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_timer.c @@ -8,7 +8,7 @@ * 2022-07-15 Emuzit first version */ #include -#include +#include #include "ch56x_sys.h" #include "ch56x_timer.h" #include "isr_sp.h" @@ -17,142 +17,142 @@ #error "Please define at least one TMRx" #endif -struct hwtimer_device +struct clock_timer_device { - struct rt_hwtimer_device parent; - struct rt_hwtimer_info hwtimer_info; + struct rt_clock_timer_device parent; + struct rt_clock_timer_info clock_timer_info; volatile struct timer_registers *reg_base; - rt_hwtimer_mode_t tmode; + rt_clock_timer_mode_t tmode; irq_number_t irqn; char *name; }; #ifdef BSP_USING_TMR0 -static struct hwtimer_device hwtimer_device_0 = +static struct clock_timer_device clock_timer_device_0 = { - .hwtimer_info = + .clock_timer_info = { .maxfreq = 80000000, .minfreq = 80000000, .maxcnt = 0x3ffffff, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }, .reg_base = (struct timer_registers *)TMR0_REG_BASE, - .tmode = HWTIMER_MODE_PERIOD, + .tmode = CLOCK_TIMER_MODE_PERIOD, .irqn = TMR0_IRQn, .name = "timer0", }; #endif #ifdef BSP_USING_TMR1 -static struct hwtimer_device hwtimer_device_1 = +static struct clock_timer_device clock_timer_device_1 = { - .hwtimer_info = + .clock_timer_info = { .maxfreq = 80000000, .minfreq = 80000000, .maxcnt = 0x3ffffff, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }, .reg_base = (struct timer_registers *)TMR1_REG_BASE, - .tmode = HWTIMER_MODE_PERIOD, + .tmode = CLOCK_TIMER_MODE_PERIOD, .irqn = TMR1_IRQn, .name = "timer1", }; #endif #ifdef BSP_USING_TMR2 -static struct hwtimer_device hwtimer_device_2 = +static struct clock_timer_device clock_timer_device_2 = { - .hwtimer_info = + .clock_timer_info = { .maxfreq = 80000000, .minfreq = 80000000, .maxcnt = 0x3ffffff, - .cntmode = HWTIMER_CNTMODE_UP, + .cntmode = CLOCK_TIMER_CNTMODE_UP, }, .reg_base = (struct timer_registers *)TMR2_REG_BASE, - .tmode = HWTIMER_MODE_PERIOD, + .tmode = CLOCK_TIMER_MODE_PERIOD, .irqn = TMR2_IRQn, .name = "timer2", }; #endif -static void hwtimer_stop(struct rt_hwtimer_device *timer); +static void clock_timer_stop(struct rt_clock_timer_device *timer); -static void hwtimer_init(struct rt_hwtimer_device *timer, uint32_t state) +static void clock_timer_init(struct rt_clock_timer_device *timer, uint32_t state) { - struct hwtimer_device *hwtimer_device = (void *)timer; + struct clock_timer_device *clock_timer_device = (void *)timer; - RT_ASSERT(hwtimer_device != RT_NULL); + RT_ASSERT(clock_timer_device != RT_NULL); /* no resource processing, `state` ignored */ - hwtimer_stop(timer); + clock_timer_stop(timer); - if (hwtimer_device->irqn != TMR0_IRQn) + if (clock_timer_device->irqn != TMR0_IRQn) { - hwtimer_device->reg_base->CTRL_DMA.reg = 0; + clock_timer_device->reg_base->CTRL_DMA.reg = 0; } } -static rt_err_t hwtimer_start(struct rt_hwtimer_device *timer, uint32_t cnt, rt_hwtimer_mode_t mode) +static rt_err_t clock_timer_start(struct rt_clock_timer_device *timer, uint32_t cnt, rt_clock_timer_mode_t mode) { - struct hwtimer_device *hwtimer_device = (void *)timer; + struct clock_timer_device *clock_timer_device = (void *)timer; volatile struct timer_registers *txreg; - RT_ASSERT(hwtimer_device != RT_NULL); + RT_ASSERT(clock_timer_device != RT_NULL); - /* hwtimer_device->tmode may be different from timer->mode. - * For multi-cycle ONESHOT, tmode is set to PERIOD at hwtimer_start. + /* clock_timer_device->tmode may be different from timer->mode. + * For multi-cycle ONESHOT, tmode is set to PERIOD at clock_timer_start. */ - hwtimer_device->tmode = mode; + clock_timer_device->tmode = mode; - sys_clk_off_by_irqn(hwtimer_device->irqn, SYS_SLP_CLK_ON); - txreg = hwtimer_device->reg_base; + sys_clk_off_by_irqn(clock_timer_device->irqn, SYS_SLP_CLK_ON); + txreg = clock_timer_device->reg_base; txreg->CNT_END = cnt; txreg->CTRL_MOD.reg = RB_TMR_ALL_CLEAR; txreg->CTRL_MOD.reg = RB_TMR_COUNT_EN; txreg->INTER_EN.cyc_end = 1; - rt_hw_interrupt_umask(hwtimer_device->irqn); + rt_hw_interrupt_umask(clock_timer_device->irqn); return RT_EOK; } -static void hwtimer_stop(struct rt_hwtimer_device *timer) +static void clock_timer_stop(struct rt_clock_timer_device *timer) { - struct hwtimer_device *hwtimer_device = (void *)timer; + struct clock_timer_device *clock_timer_device = (void *)timer; volatile struct timer_registers *txreg; - RT_ASSERT(hwtimer_device != RT_NULL); + RT_ASSERT(clock_timer_device != RT_NULL); - rt_hw_interrupt_mask(hwtimer_device->irqn); + rt_hw_interrupt_mask(clock_timer_device->irqn); /* note: RB_TMR_COUNT_EN cleared */ - txreg = hwtimer_device->reg_base; + txreg = clock_timer_device->reg_base; txreg->CTRL_MOD.reg = RB_TMR_ALL_CLEAR; txreg->INTER_EN.reg = 0; - sys_clk_off_by_irqn(hwtimer_device->irqn, SYS_SLP_CLK_OFF); + sys_clk_off_by_irqn(clock_timer_device->irqn, SYS_SLP_CLK_OFF); } -static uint32_t hwtimer_count_get(struct rt_hwtimer_device *timer) +static uint32_t clock_timer_count_get(struct rt_clock_timer_device *timer) { - struct hwtimer_device *hwtimer_device = (void *)timer; + struct clock_timer_device *clock_timer_device = (void *)timer; - RT_ASSERT(hwtimer_device != RT_NULL); + RT_ASSERT(clock_timer_device != RT_NULL); - return hwtimer_device->reg_base->COUNT; + return clock_timer_device->reg_base->COUNT; } -static rt_err_t hwtimer_control( - struct rt_hwtimer_device *timer, uint32_t cmd, void *args) +static rt_err_t clock_timer_control( + struct rt_clock_timer_device *timer, uint32_t cmd, void *args) { - struct hwtimer_device *hwtimer_device = (void *)timer; + struct clock_timer_device *clock_timer_device = (void *)timer; rt_err_t result = RT_EOK; - RT_ASSERT(hwtimer_device != RT_NULL); + RT_ASSERT(clock_timer_device != RT_NULL); switch (cmd) { - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: /* clocking for ch56x timers are fixed to Fsys */ if (args == RT_NULL || *(uint32_t *)args != timer->info->minfreq) { @@ -160,9 +160,9 @@ static rt_err_t hwtimer_control( } break; - case HWTIMER_CTRL_STOP: - case HWTIMER_CTRL_INFO_GET: - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_INFO_GET: + case CLOCK_TIMER_CTRL_MODE_SET: default: result = -RT_ENOSYS; } @@ -170,60 +170,60 @@ static rt_err_t hwtimer_control( return result; } -static const struct rt_hwtimer_ops hwtimer_ops = +static const struct rt_clock_timer_ops clock_timer_ops = { - .init = hwtimer_init, - .start = hwtimer_start, - .stop = hwtimer_stop, - .count_get = hwtimer_count_get, - .control = hwtimer_control, + .init = clock_timer_init, + .start = clock_timer_start, + .stop = clock_timer_stop, + .count_get = clock_timer_count_get, + .control = clock_timer_control, }; -static int rt_hw_hwtimer_init(void) +static int rt_hw_clock_timer_init(void) { - struct hwtimer_device *devices[3]; + struct clock_timer_device *devices[3]; uint32_t Fsys = sys_hclk_get(); int n = 0; #ifdef BSP_USING_TMR2 - devices[n++] = &hwtimer_device_2; + devices[n++] = &clock_timer_device_2; #endif #ifdef BSP_USING_TMR1 - devices[n++] = &hwtimer_device_1; + devices[n++] = &clock_timer_device_1; #endif #ifdef BSP_USING_TMR0 - devices[n++] = &hwtimer_device_0; + devices[n++] = &clock_timer_device_0; #endif while (--n >= 0) { - struct hwtimer_device *hwtimer_device = devices[n]; + struct clock_timer_device *clock_timer_device = devices[n]; /* counting frequency is fixed to Fsys */ - hwtimer_device->hwtimer_info.maxfreq = Fsys; - hwtimer_device->hwtimer_info.minfreq = Fsys; - hwtimer_device->parent.info = &hwtimer_device->hwtimer_info; - hwtimer_device->parent.ops = &hwtimer_ops; - rt_device_hwtimer_register( - &hwtimer_device->parent, hwtimer_device->name, RT_NULL); + clock_timer_device->clock_timer_info.maxfreq = Fsys; + clock_timer_device->clock_timer_info.minfreq = Fsys; + clock_timer_device->parent.info = &clock_timer_device->clock_timer_info; + clock_timer_device->parent.ops = &clock_timer_ops; + rt_clock_timer_register( + &clock_timer_device->parent, clock_timer_device->name, RT_NULL); } return RT_EOK; } -INIT_DEVICE_EXPORT(rt_hw_hwtimer_init); +INIT_DEVICE_EXPORT(rt_hw_clock_timer_init); -static void _hwtimer_isr_common(struct hwtimer_device *hwtimer_device) +static void _clock_timer_isr_common(struct clock_timer_device *clock_timer_device) { - volatile struct timer_registers *txreg = hwtimer_device->reg_base; + volatile struct timer_registers *txreg = clock_timer_device->reg_base; if (txreg->INT_FLAG.cyc_end) { - if (hwtimer_device->tmode == HWTIMER_MODE_ONESHOT) + if (clock_timer_device->tmode == CLOCK_TIMER_MODE_ONESHOT) { /* disable timer to emulate oneshot */ txreg->CTRL_MOD.reg = 0; } - rt_device_hwtimer_isr(&hwtimer_device->parent); + rt_clock_timer_isr(&clock_timer_device->parent); txreg->INT_FLAG.cyc_end = 1; } } @@ -234,7 +234,7 @@ void tmr0_irq_handler(void) { isr_sp_enter(); rt_interrupt_enter(); - _hwtimer_isr_common(&hwtimer_device_0); + _clock_timer_isr_common(&clock_timer_device_0); rt_interrupt_leave(); isr_sp_leave(); } @@ -246,7 +246,7 @@ void tmr1_irq_handler(void) { isr_sp_enter(); rt_interrupt_enter(); - _hwtimer_isr_common(&hwtimer_device_1); + _clock_timer_isr_common(&clock_timer_device_1); rt_interrupt_leave(); isr_sp_leave(); } @@ -258,7 +258,7 @@ void tmr2_irq_handler(void) { isr_sp_enter(); rt_interrupt_enter(); - _hwtimer_isr_common(&hwtimer_device_2); + _clock_timer_isr_common(&clock_timer_device_2); rt_interrupt_leave(); isr_sp_leave(); } diff --git a/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig b/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig index 5134fbd334..1ef09bd521 100644 --- a/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig +++ b/bsp/wch/risc-v/ch32v208w-r0/board/Kconfig @@ -266,9 +266,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM - config BSP_USING_HWTIMER + config BSP_USING_CLOCK_TIMER bool - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n config BSP_USING_PWM @@ -282,12 +282,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM1 choice - prompt "Using TIM1 as hwtimer or PWM mode" - default BSP_USING_TIM1_HWTIMER + prompt "Using TIM1 as clock_timer or PWM mode" + default BSP_USING_TIM1_CLOCK_TIMER - config BSP_USING_TIM1_HWTIMER - bool "Using TIM1 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM1_CLOCK_TIMER + bool "Using TIM1 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM1_PWM bool "Using TIM1 as PWM mode" @@ -318,12 +318,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM2 choice - prompt "Using TIM2 as hwtimer or PWM mode" - default BSP_USING_TIM2_HWTIMER + prompt "Using TIM2 as clock_timer or PWM mode" + default BSP_USING_TIM2_CLOCK_TIMER - config BSP_USING_TIM2_HWTIMER - bool "Using TIM2 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM2_CLOCK_TIMER + bool "Using TIM2 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM2_PWM bool "Using TIM2 as PWM mode" @@ -354,12 +354,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM3 choice - prompt "Using TIM3 as hwtimer or PWM mode" - default BSP_USING_TIM3_HWTIMER + prompt "Using TIM3 as clock_timer or PWM mode" + default BSP_USING_TIM3_CLOCK_TIMER - config BSP_USING_TIM3_HWTIMER - bool "Using TIM3 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM3_CLOCK_TIMER + bool "Using TIM3 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM3_PWM bool "Using TIM3 as PWM mode" @@ -390,12 +390,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM4 choice - prompt "Using TIM4 as hwtimer or PWM mode" - default BSP_USING_TIM4_HWTIMER + prompt "Using TIM4 as clock_timer or PWM mode" + default BSP_USING_TIM4_CLOCK_TIMER - config BSP_USING_TIM4_HWTIMER - bool "Using TIM4 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM4_CLOCK_TIMER + bool "Using TIM4 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM4_PWM bool "Using TIM4 as PWM mode" @@ -426,12 +426,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM5 choice - prompt "Using TIM5 as hwtimer or PWM mode" - default BSP_USING_TIM5_HWTIMER + prompt "Using TIM5 as clock_timer or PWM mode" + default BSP_USING_TIM5_CLOCK_TIMER - config BSP_USING_TIM5_HWTIMER - bool "Using TIM5 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM5_CLOCK_TIMER + bool "Using TIM5 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM5_PWM bool "Using TIM5 as PWM mode" @@ -462,12 +462,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM6 choice - prompt "Using TIM5 as hwtimer (PWM mode not supported)" - default BSP_USING_TIM6_HWTIMER + prompt "Using TIM5 as clock_timer (PWM mode not supported)" + default BSP_USING_TIM6_CLOCK_TIMER - config BSP_USING_TIM6_HWTIMER - bool "Using TIM6 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM6_CLOCK_TIMER + bool "Using TIM6 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endchoice endif @@ -478,12 +478,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM7 choice - prompt "Using TIM7 as hwtimer (PWM mode not supported)" - default BSP_USING_TIM7_HWTIMER + prompt "Using TIM7 as clock_timer (PWM mode not supported)" + default BSP_USING_TIM7_CLOCK_TIMER - config BSP_USING_TIM7_HWTIMER - bool "Using TIM7 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM7_CLOCK_TIMER + bool "Using TIM7 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endchoice endif @@ -494,12 +494,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM8 choice - prompt "Using TIM8 as hwtimer or PWM mode" - default BSP_USING_TIM8_HWTIMER + prompt "Using TIM8 as clock_timer or PWM mode" + default BSP_USING_TIM8_CLOCK_TIMER - config BSP_USING_TIM8_HWTIMER - bool "Using TIM8 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM8_CLOCK_TIMER + bool "Using TIM8 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM8_PWM bool "Using TIM8 as PWM mode" @@ -530,12 +530,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM9 choice - prompt "Using TIM9 as hwtimer or PWM mode" - default BSP_USING_TIM9_HWTIMER + prompt "Using TIM9 as clock_timer or PWM mode" + default BSP_USING_TIM9_CLOCK_TIMER - config BSP_USING_TIM9_HWTIMER - bool "Using TIM9 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM9_CLOCK_TIMER + bool "Using TIM9 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM9_PWM bool "Using TIM9 as PWM mode" @@ -566,12 +566,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM10 choice - prompt "Using TIM10 as hwtimer or PWM mode" - default BSP_USING_TIM10_HWTIMER + prompt "Using TIM10 as clock_timer or PWM mode" + default BSP_USING_TIM10_CLOCK_TIMER - config BSP_USING_TIM10_HWTIMER - bool "Using TIM10 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM10_CLOCK_TIMER + bool "Using TIM10 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM10_PWM bool "Using TIM10 as PWM mode" diff --git a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig index e0af96f539..ececb91344 100644 --- a/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig +++ b/bsp/wch/risc-v/ch32v307v-r1/board/Kconfig @@ -30,7 +30,7 @@ menu "Onboard Peripheral Drivers" select BSP_USING_TIM4_PWM_CH3 select BSP_USING_TIM4_PWM_CH4 select BSP_USING_TIM6 - select BSP_USING_TIM6_HWTIMER + select BSP_USING_TIM6_CLOCK_TIMER select BSP_USING_SOFT_I2C select BSP_USING_I2C1 select RTDUINO_USING_WIRE @@ -538,9 +538,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM - config BSP_USING_HWTIMER + config BSP_USING_CLOCK_TIMER bool - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n config BSP_USING_PWM @@ -553,9 +553,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM1 - config BSP_USING_TIM1_HWTIMER - bool "Using TIM1 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM1_CLOCK_TIMER + bool "Using TIM1 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM1_PWM bool "Using TIM1 as PWM mode" @@ -577,8 +577,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM1 channel 4" endif - if BSP_USING_TIM1_HWTIMER && BSP_USING_TIM1_PWM - comment "BSP_USING_TIM1_HWTIMER and BSP_USING_TIM1_PWM can only be chosen for one!" + if BSP_USING_TIM1_CLOCK_TIMER && BSP_USING_TIM1_PWM + comment "BSP_USING_TIM1_CLOCK_TIMER and BSP_USING_TIM1_PWM can only be chosen for one!" endif endif @@ -588,9 +588,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM2 - config BSP_USING_TIM2_HWTIMER - bool "Using TIM2 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM2_CLOCK_TIMER + bool "Using TIM2 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM2_PWM bool "Using TIM2 as PWM mode" @@ -612,8 +612,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM2 channel 4" endif - if BSP_USING_TIM2_HWTIMER && BSP_USING_TIM2_PWM - comment "BSP_USING_TIM2_HWTIMER and BSP_USING_TIM2_PWM can only be chosen for one!" + if BSP_USING_TIM2_CLOCK_TIMER && BSP_USING_TIM2_PWM + comment "BSP_USING_TIM2_CLOCK_TIMER and BSP_USING_TIM2_PWM can only be chosen for one!" endif endif @@ -623,9 +623,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM3 - config BSP_USING_TIM3_HWTIMER - bool "Using TIM3 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM3_CLOCK_TIMER + bool "Using TIM3 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM3_PWM bool "Using TIM3 as PWM mode" @@ -647,8 +647,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM3 channel 4" endif - if BSP_USING_TIM3_HWTIMER && BSP_USING_TIM3_PWM - comment "BSP_USING_TIM3_HWTIMER and BSP_USING_TIM3_PWM can only be chosen for one!" + if BSP_USING_TIM3_CLOCK_TIMER && BSP_USING_TIM3_PWM + comment "BSP_USING_TIM3_CLOCK_TIMER and BSP_USING_TIM3_PWM can only be chosen for one!" endif endif @@ -658,9 +658,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM4 - config BSP_USING_TIM4_HWTIMER - bool "Using TIM4 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM4_CLOCK_TIMER + bool "Using TIM4 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM4_PWM bool "Using TIM4 as PWM mode" @@ -682,8 +682,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM4 channel 4" endif - if BSP_USING_TIM4_HWTIMER && BSP_USING_TIM4_PWM - comment "BSP_USING_TIM4_HWTIMER and BSP_USING_TIM4_PWM can only be chosen for one!" + if BSP_USING_TIM4_CLOCK_TIMER && BSP_USING_TIM4_PWM + comment "BSP_USING_TIM4_CLOCK_TIMER and BSP_USING_TIM4_PWM can only be chosen for one!" endif endif @@ -693,9 +693,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM5 - config BSP_USING_TIM5_HWTIMER - bool "Using TIM5 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM5_CLOCK_TIMER + bool "Using TIM5 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM5_PWM bool "Using TIM5 as PWM mode" @@ -717,8 +717,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM5 channel 4" endif - if BSP_USING_TIM5_HWTIMER && BSP_USING_TIM5_PWM - comment "BSP_USING_TIM5_HWTIMER and BSP_USING_TIM5_PWM can only be chosen for one!" + if BSP_USING_TIM5_CLOCK_TIMER && BSP_USING_TIM5_PWM + comment "BSP_USING_TIM5_CLOCK_TIMER and BSP_USING_TIM5_PWM can only be chosen for one!" endif endif @@ -728,9 +728,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM6 - config BSP_USING_TIM6_HWTIMER - bool "Using TIM6 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM6_CLOCK_TIMER + bool "Using TIM6 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endif config BSP_USING_TIM7 @@ -738,9 +738,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM7 - config BSP_USING_TIM7_HWTIMER - bool "Using TIM7 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM7_CLOCK_TIMER + bool "Using TIM7 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endif config BSP_USING_TIM8 @@ -748,9 +748,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM8 - config BSP_USING_TIM8_HWTIMER - bool "Using TIM8 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM8_CLOCK_TIMER + bool "Using TIM8 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM8_PWM bool "Using TIM8 as PWM mode" @@ -772,8 +772,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM8 channel 4" endif - if BSP_USING_TIM8_HWTIMER && BSP_USING_TIM8_PWM - comment "BSP_USING_TIM8_HWTIMER and BSP_USING_TIM8_PWM can only be chosen for one!" + if BSP_USING_TIM8_CLOCK_TIMER && BSP_USING_TIM8_PWM + comment "BSP_USING_TIM8_CLOCK_TIMER and BSP_USING_TIM8_PWM can only be chosen for one!" endif endif @@ -783,9 +783,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM9 - config BSP_USING_TIM9_HWTIMER - bool "Using TIM9 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM9_CLOCK_TIMER + bool "Using TIM9 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM9_PWM bool "Using TIM9 as PWM mode" @@ -807,8 +807,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM9 channel 4" endif - if BSP_USING_TIM9_HWTIMER && BSP_USING_TIM9_PWM - comment "BSP_USING_TIM9_HWTIMER and BSP_USING_TIM9_PWM can only be chosen for one!" + if BSP_USING_TIM9_CLOCK_TIMER && BSP_USING_TIM9_PWM + comment "BSP_USING_TIM9_CLOCK_TIMER and BSP_USING_TIM9_PWM can only be chosen for one!" endif endif @@ -818,9 +818,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM10 - config BSP_USING_TIM10_HWTIMER - bool "Using TIM10 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM10_CLOCK_TIMER + bool "Using TIM10 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM10_PWM bool "Using TIM10 as PWM mode" @@ -842,8 +842,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM10 channel 4" endif - if BSP_USING_TIM10_HWTIMER && BSP_USING_TIM10_PWM - comment "BSP_USING_TIM10_HWTIMER and BSP_USING_TIM10_PWM can only be chosen for one!" + if BSP_USING_TIM10_CLOCK_TIMER && BSP_USING_TIM10_PWM + comment "BSP_USING_TIM10_CLOCK_TIMER and BSP_USING_TIM10_PWM can only be chosen for one!" endif endif diff --git a/bsp/wch/risc-v/ch569w-evt/applications/test.c b/bsp/wch/risc-v/ch569w-evt/applications/test.c index f29811f8ca..848189f301 100644 --- a/bsp/wch/risc-v/ch569w-evt/applications/test.c +++ b/bsp/wch/risc-v/ch569w-evt/applications/test.c @@ -7,14 +7,14 @@ * Date Author Notes * 2022-07-15 Emuzit first version * 2022-07-20 Emuzit add watchdog test - * 2022-07-26 Emuzit add hwtimer test + * 2022-07-26 Emuzit add clock_timer test * 2022-07-30 Emuzit add spi master test * 2022-08-04 Emuzit add pwm test */ #include #include #include "drivers/dev_watchdog.h" -#include +#include #include "drivers/dev_spi.h" #include #include "board.h" @@ -154,7 +154,7 @@ static void test_watchdog(uint32_t seconds) #define test_watchdog(tov) do {} while(0) #endif -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME static struct rt_device *tmr_dev_0; static struct rt_device *tmr_dev_1; @@ -164,15 +164,15 @@ static rt_err_t tmr_timeout_cb(rt_device_t dev, rt_size_t size) int tmr = (dev == tmr_dev_1) ? 1 : 0; - rt_kprintf("hwtimer %d timeout callback fucntion @tick %d\n", tmr, tick); + rt_kprintf("clock_timer %d timeout callback fucntion @tick %d\n", tmr, tick); return RT_EOK; } -static void test_hwtimer(void) +static void test_clock_timer(void) { - rt_hwtimerval_t timerval; - rt_hwtimer_mode_t mode; + rt_clock_timerval_t timerval; + rt_clock_timer_mode_t mode; rt_size_t tsize; /* setup two timers, ONESHOT & PERIOD each @@ -181,12 +181,12 @@ static void test_hwtimer(void) tmr_dev_1 = rt_device_find("timer1"); if (tmr_dev_0 == RT_NULL || tmr_dev_1 == RT_NULL) { - rt_kprintf("hwtimer device(s) not found !\n"); + rt_kprintf("clock_timer device(s) not found !\n"); } else if (rt_device_open(tmr_dev_0, RT_DEVICE_OFLAG_RDWR) != RT_EOK || rt_device_open(tmr_dev_1, RT_DEVICE_OFLAG_RDWR) != RT_EOK) { - rt_kprintf("hwtimer device(s) open failed !\n"); + rt_kprintf("clock_timer device(s) open failed !\n"); } else { @@ -196,8 +196,8 @@ static void test_hwtimer(void) timerval.sec = 3; timerval.usec = 500000; tsize = sizeof(timerval); - mode = HWTIMER_MODE_ONESHOT; - if (rt_device_control(tmr_dev_0, HWTIMER_CTRL_MODE_SET, &mode) != RT_EOK) + mode = CLOCK_TIMER_MODE_ONESHOT; + if (rt_device_control(tmr_dev_0, CLOCK_TIMER_CTRL_MODE_SET, &mode) != RT_EOK) { rt_kprintf("timer0 set mode failed !\n"); } @@ -213,8 +213,8 @@ static void test_hwtimer(void) timerval.sec = 5; timerval.usec = 0; tsize = sizeof(timerval); - mode = HWTIMER_MODE_PERIOD; - if (rt_device_control(tmr_dev_1, HWTIMER_CTRL_MODE_SET, &mode) != RT_EOK) + mode = CLOCK_TIMER_MODE_PERIOD; + if (rt_device_control(tmr_dev_1, CLOCK_TIMER_CTRL_MODE_SET, &mode) != RT_EOK) { rt_kprintf("timer1 set mode failed !\n"); } @@ -229,7 +229,7 @@ static void test_hwtimer(void) } } #else - #define test_hwtimer() do {} while(0) + #define test_clock_timer() do {} while(0) #endif #ifdef RT_USING_SPI @@ -414,7 +414,7 @@ void main(void) test_gpio_int(); test_watchdog(wdog_timeout); - test_hwtimer(); + test_clock_timer(); test_spi_master(); test_pwm(); test_usbd(); diff --git a/bsp/wch/risc-v/ch569w-evt/board/Kconfig b/bsp/wch/risc-v/ch569w-evt/board/Kconfig index 2f23098a3c..4cbfc32981 100644 --- a/bsp/wch/risc-v/ch569w-evt/board/Kconfig +++ b/bsp/wch/risc-v/ch569w-evt/board/Kconfig @@ -40,7 +40,7 @@ config BSP_USING_UART config BSP_USING_TIMER bool "using on-chip timer" - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n if BSP_USING_TIMER diff --git a/bsp/wch/risc-v/yd-ch32v307vct6/board/Kconfig b/bsp/wch/risc-v/yd-ch32v307vct6/board/Kconfig index 2ad8cc1336..dccae0c2bb 100644 --- a/bsp/wch/risc-v/yd-ch32v307vct6/board/Kconfig +++ b/bsp/wch/risc-v/yd-ch32v307vct6/board/Kconfig @@ -256,9 +256,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM - config BSP_USING_HWTIMER + config BSP_USING_CLOCK_TIMER bool - select RT_USING_HWTIMER + select RT_USING_CLOCK_TIME default n config BSP_USING_PWM @@ -271,9 +271,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM1 - config BSP_USING_TIM1_HWTIMER - bool "Using TIM1 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM1_CLOCK_TIMER + bool "Using TIM1 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM1_PWM bool "Using TIM1 as PWM mode" @@ -295,8 +295,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM1 channel 4" endif - if BSP_USING_TIM1_HWTIMER && BSP_USING_TIM1_PWM - comment "BSP_USING_TIM1_HWTIMER and BSP_USING_TIM1_PWM can only be chosen for one!" + if BSP_USING_TIM1_CLOCK_TIMER && BSP_USING_TIM1_PWM + comment "BSP_USING_TIM1_CLOCK_TIMER and BSP_USING_TIM1_PWM can only be chosen for one!" endif endif @@ -306,9 +306,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM2 - config BSP_USING_TIM2_HWTIMER - bool "Using TIM2 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM2_CLOCK_TIMER + bool "Using TIM2 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM2_PWM bool "Using TIM2 as PWM mode" @@ -330,8 +330,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM2 channel 4" endif - if BSP_USING_TIM2_HWTIMER && BSP_USING_TIM2_PWM - comment "BSP_USING_TIM2_HWTIMER and BSP_USING_TIM2_PWM can only be chosen for one!" + if BSP_USING_TIM2_CLOCK_TIMER && BSP_USING_TIM2_PWM + comment "BSP_USING_TIM2_CLOCK_TIMER and BSP_USING_TIM2_PWM can only be chosen for one!" endif endif @@ -341,9 +341,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM3 - config BSP_USING_TIM3_HWTIMER - bool "Using TIM3 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM3_CLOCK_TIMER + bool "Using TIM3 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM3_PWM bool "Using TIM3 as PWM mode" @@ -365,8 +365,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM3 channel 4" endif - if BSP_USING_TIM3_HWTIMER && BSP_USING_TIM3_PWM - comment "BSP_USING_TIM3_HWTIMER and BSP_USING_TIM3_PWM can only be chosen for one!" + if BSP_USING_TIM3_CLOCK_TIMER && BSP_USING_TIM3_PWM + comment "BSP_USING_TIM3_CLOCK_TIMER and BSP_USING_TIM3_PWM can only be chosen for one!" endif endif @@ -376,9 +376,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM4 - config BSP_USING_TIM4_HWTIMER - bool "Using TIM4 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM4_CLOCK_TIMER + bool "Using TIM4 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM4_PWM bool "Using TIM4 as PWM mode" @@ -400,8 +400,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM4 channel 4" endif - if BSP_USING_TIM4_HWTIMER && BSP_USING_TIM4_PWM - comment "BSP_USING_TIM4_HWTIMER and BSP_USING_TIM4_PWM can only be chosen for one!" + if BSP_USING_TIM4_CLOCK_TIMER && BSP_USING_TIM4_PWM + comment "BSP_USING_TIM4_CLOCK_TIMER and BSP_USING_TIM4_PWM can only be chosen for one!" endif endif @@ -411,9 +411,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM5 - config BSP_USING_TIM5_HWTIMER - bool "Using TIM5 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM5_CLOCK_TIMER + bool "Using TIM5 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM5_PWM bool "Using TIM5 as PWM mode" @@ -435,8 +435,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM5 channel 4" endif - if BSP_USING_TIM5_HWTIMER && BSP_USING_TIM5_PWM - comment "BSP_USING_TIM5_HWTIMER and BSP_USING_TIM5_PWM can only be chosen for one!" + if BSP_USING_TIM5_CLOCK_TIMER && BSP_USING_TIM5_PWM + comment "BSP_USING_TIM5_CLOCK_TIMER and BSP_USING_TIM5_PWM can only be chosen for one!" endif endif @@ -446,9 +446,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM6 - config BSP_USING_TIM6_HWTIMER - bool "Using TIM6 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM6_CLOCK_TIMER + bool "Using TIM6 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endif config BSP_USING_TIM7 @@ -456,9 +456,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM7 - config BSP_USING_TIM7_HWTIMER - bool "Using TIM7 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM7_CLOCK_TIMER + bool "Using TIM7 as clock_timer mode" + select BSP_USING_CLOCK_TIMER endif config BSP_USING_TIM8 @@ -466,9 +466,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM8 - config BSP_USING_TIM8_HWTIMER - bool "Using TIM8 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM8_CLOCK_TIMER + bool "Using TIM8 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM8_PWM bool "Using TIM8 as PWM mode" @@ -490,8 +490,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM8 channel 4" endif - if BSP_USING_TIM8_HWTIMER && BSP_USING_TIM8_PWM - comment "BSP_USING_TIM8_HWTIMER and BSP_USING_TIM8_PWM can only be chosen for one!" + if BSP_USING_TIM8_CLOCK_TIMER && BSP_USING_TIM8_PWM + comment "BSP_USING_TIM8_CLOCK_TIMER and BSP_USING_TIM8_PWM can only be chosen for one!" endif endif @@ -501,9 +501,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM9 - config BSP_USING_TIM9_HWTIMER - bool "Using TIM9 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM9_CLOCK_TIMER + bool "Using TIM9 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM9_PWM bool "Using TIM9 as PWM mode" @@ -525,8 +525,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM9 channel 4" endif - if BSP_USING_TIM9_HWTIMER && BSP_USING_TIM9_PWM - comment "BSP_USING_TIM9_HWTIMER and BSP_USING_TIM9_PWM can only be chosen for one!" + if BSP_USING_TIM9_CLOCK_TIMER && BSP_USING_TIM9_PWM + comment "BSP_USING_TIM9_CLOCK_TIMER and BSP_USING_TIM9_PWM can only be chosen for one!" endif endif @@ -536,9 +536,9 @@ menu "On-chip Peripheral Drivers" default n if BSP_USING_TIM10 - config BSP_USING_TIM10_HWTIMER - bool "Using TIM10 as hwtimer mode" - select BSP_USING_HWTIMER + config BSP_USING_TIM10_CLOCK_TIMER + bool "Using TIM10 as clock_timer mode" + select BSP_USING_CLOCK_TIMER config BSP_USING_TIM10_PWM bool "Using TIM10 as PWM mode" @@ -560,8 +560,8 @@ menu "On-chip Peripheral Drivers" bool "Using TIM10 channel 4" endif - if BSP_USING_TIM10_HWTIMER && BSP_USING_TIM10_PWM - comment "BSP_USING_TIM10_HWTIMER and BSP_USING_TIM10_PWM can only be chosen for one!" + if BSP_USING_TIM10_CLOCK_TIMER && BSP_USING_TIM10_PWM + comment "BSP_USING_TIM10_CLOCK_TIMER and BSP_USING_TIM10_PWM can only be chosen for one!" endif endif diff --git a/bsp/xuantie/virt64/c906/board/board.c b/bsp/xuantie/virt64/c906/board/board.c index 3a38dab716..7e30de7a57 100644 --- a/bsp/xuantie/virt64/c906/board/board.c +++ b/bsp/xuantie/virt64/c906/board/board.c @@ -42,6 +42,11 @@ struct mem_desc platform_mem_desc[] = { #endif +rt_uint64_t rt_hw_get_clock_timer_freq(void) +{ + return 10000000ULL; +} + void primary_cpu_entry(void) { /* disable global interrupt */ @@ -106,4 +111,3 @@ void rt_hw_cpu_reset(void) ; } MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); - diff --git a/bsp/zynqmp-r5-axu4ev/rtconfig.h b/bsp/zynqmp-r5-axu4ev/rtconfig.h index 7cb23b1b7c..9b296b2f0d 100644 --- a/bsp/zynqmp-r5-axu4ev/rtconfig.h +++ b/bsp/zynqmp-r5-axu4ev/rtconfig.h @@ -105,7 +105,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_CACHE @@ -404,6 +404,10 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index f803469d64..01539009a2 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -5,7 +5,7 @@ rsource "ipc/Kconfig" rsource "serial/Kconfig" rsource "can/Kconfig" -rsource "cputime/Kconfig" +rsource "clock_time/Kconfig" rsource "i2c/Kconfig" rsource "phy/Kconfig" rsource "misc/Kconfig" @@ -46,9 +46,7 @@ rsource "pci/Kconfig" rsource "pic/Kconfig" rsource "pin/Kconfig" rsource "pinctrl/Kconfig" -rsource "ktime/Kconfig" rsource "clk/Kconfig" -rsource "hwtimer/Kconfig" rsource "usb/Kconfig" endmenu diff --git a/components/drivers/clock_time/Kconfig b/components/drivers/clock_time/Kconfig new file mode 100644 index 0000000000..7da12ac849 --- /dev/null +++ b/components/drivers/clock_time/Kconfig @@ -0,0 +1,18 @@ +menuconfig RT_USING_CLOCK_TIME + bool "Clock time subsystem" + default n + +if RT_USING_CLOCK_TIME + config CLOCK_TIMER_FREQ + int "Clock time timer freq" + default 0 + depends on ARCH_RISCV64 + help + Base frequency (Hz) for clock time counter on RISC-V. + + config RT_CLOCK_TIME_ARM_ARCH + bool "ARM ARCH Timer" + depends on RT_USING_DM + depends on ARCH_ARM_CORTEX_A || ARCH_ARMV8 + default n +endif diff --git a/components/drivers/clock_time/README.md b/components/drivers/clock_time/README.md new file mode 100644 index 0000000000..45de9f9f4d --- /dev/null +++ b/components/drivers/clock_time/README.md @@ -0,0 +1,39 @@ +# Clock Time Subsystem + +The clock_time subsystem provides a unified time base and event scheduling for +RT-Thread. It separates timekeeping (a monotonic counter) from event delivery +(a programmable timer interrupt) so platforms can combine different hardware +sources while the kernel sees consistent behavior. + +## Design Principles +- Monotonic time: time readings never go backward. +- Separation of roles: a clock source provides a counter, a clock event triggers + deadlines. +- Scaled integer conversion: counters are converted to nanoseconds with a + resolution scale factor, avoiding floating point. +- Graceful fallback: if a hardware event is unavailable, software timers keep + the system functional. + +## Building Blocks +- Clock source: provides a stable counter and its frequency. +- Clock event: can be programmed to fire at the next deadline. +- Clock timer adapter: exposes a general timer peripheral as a clock source or + event device. +- Clock hrtimer: software scheduler that orders high-resolution timeouts and + programs the next event. +- Clock boottime helpers: translate the monotonic counter into common time + formats for use by higher layers. + +## Time Flow +- Read path: counter -> scaled resolution -> nanoseconds. +- Timeout path: hrtimer queue -> next expiry -> program event -> interrupt -> + dispatch callbacks. + +## BSP Integration Guidance +- Provide a stable counter or a programmable timer. One device can serve both + roles. +- Select a default source and event device to enable accurate timekeeping and + efficient scheduling. +- Keep ISRs minimal; the core handles conversion and scheduling. +- POSIX time APIs are layered on top of this subsystem and reuse its monotonic + base. diff --git a/components/drivers/clock_time/README_zh.md b/components/drivers/clock_time/README_zh.md new file mode 100644 index 0000000000..aed720b8dd --- /dev/null +++ b/components/drivers/clock_time/README_zh.md @@ -0,0 +1,28 @@ +# Clock Time 子系统 + +clock_time 子系统为 RT-Thread 提供统一的时间基准与事件调度能力。它将 +“计时”(单调计数器)与“定时事件”(可编程定时器中断)解耦，允许不同硬件 +组合，同时保证内核行为一致。 + +## 设计原则 +- 单调时间: 时间读数不回退。 +- 角色分离: 时钟源负责计数，时钟事件负责触发超时。 +- 缩放整数换算: 通过分辨率缩放因子把计数转换为纳秒，避免浮点计算。 +- 可降级运行: 缺少硬件事件时由软件定时器维持基本功能。 + +## 组成部分 +- 时钟源: 提供稳定计数器与频率信息。 +- 时钟事件: 可编程下一次超时。 +- 时钟定时器适配层: 将通用定时器外设包装为时钟源或事件设备。 +- 高精度定时器: 软件调度层，排序超时并驱动下一次事件。 +- 启动时间辅助: 将单调计数转换为常见时间格式，供上层使用。 + +## 时间流转 +- 读取路径: 计数 -> 缩放分辨率 -> 纳秒。 +- 超时路径: hrtimer 队列 -> 下一到期 -> 设置事件 -> 中断 -> 回调分发。 + +## BSP 集成要点 +- 提供稳定计数器或可编程定时器，一个设备可兼任两种角色。 +- 选择默认的时钟源与事件设备，以获得准确计时与高效调度。 +- 中断服务保持简短，换算与调度交由核心完成。 +- POSIX 时间接口建立在该子系统之上，复用其单调时间基准。 diff --git a/components/drivers/clock_time/SConscript b/components/drivers/clock_time/SConscript new file mode 100644 index 0000000000..111449276a --- /dev/null +++ b/components/drivers/clock_time/SConscript @@ -0,0 +1,42 @@ +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() + +group = [] +build_clock_time = GetDepend('RT_USING_CLOCK_TIME') + +if not build_clock_time: + Return('group') + +src = [ + 'clock_time_core.c', + 'clock_hrtimer.c', + 'clock_boottime.c', + 'clock_timer.c', +] +if GetDepend('RT_CLOCK_TIME_ARM_ARCH'): + src += ['clock_time_arm_arch.c'] + +arch_dir = os.path.join(cwd, 'arch') +if os.path.isdir(arch_dir): + arch_list = os.listdir(arch_dir) + if rtconfig.ARCH in arch_list: + cpu_dir = os.path.join(arch_dir, rtconfig.ARCH, rtconfig.CPU) + if os.path.exists(cpu_dir): + src += Glob("arch/%s/%s/*.c" % (rtconfig.ARCH, rtconfig.CPU)) + else: + src += Glob("arch/%s/*.c" % rtconfig.ARCH) + +CPPPATH = [cwd, os.path.join(cwd, '..', 'include')] +LOCAL_CCFLAGS = '' +if rtconfig.PLATFORM in ['gcc', 'armclang']: + LOCAL_CCFLAGS += ' -std=gnu99' +elif rtconfig.PLATFORM in ['armcc']: + LOCAL_CCFLAGS += ' --c99 --gnu' + +group = DefineGroup('DeviceDrivers', src, depend=[''], CPPPATH=CPPPATH, LOCAL_CCFLAGS=LOCAL_CCFLAGS) + +Return('group') diff --git a/components/drivers/clock_time/arch/aarch64/cputimer.c b/components/drivers/clock_time/arch/aarch64/cputimer.c new file mode 100644 index 0000000000..58102d226f --- /dev/null +++ b/components/drivers/clock_time/arch/aarch64/cputimer.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-10 xqyjlj The first version. + */ + +#include "gtimer.h" +#include + +static volatile unsigned long _init_cnt = 0; +static rt_bool_t _aarch64_clock_registered = RT_FALSE; +static struct rt_clock_time_device _aarch64_clock_dev; + +static rt_uint64_t _aarch64_clock_get_freq(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return rt_hw_get_gtimer_frq(); +} + +static rt_uint64_t _aarch64_clock_get_counter(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return (rt_uint64_t)(rt_hw_get_cntpct_val() - _init_cnt); +} + +static rt_err_t _aarch64_clock_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta) +{ + RT_UNUSED(dev); + RT_UNUSED(delta); + return -RT_ENOSYS; +} + +static const struct rt_clock_time_ops _aarch64_clock_ops = +{ + _aarch64_clock_get_freq, + _aarch64_clock_get_counter, + _aarch64_clock_set_timeout, +}; + +void rt_clock_time_source_init(void) +{ + _init_cnt = rt_hw_get_cntpct_val(); + + if (!_aarch64_clock_registered) + { + rt_uint8_t caps = RT_CLOCK_TIME_CAP_SOURCE; + + _aarch64_clock_dev.ops = &_aarch64_clock_ops; + _aarch64_clock_dev.res_scale = RT_CLOCK_TIME_RESMUL; + _aarch64_clock_dev.caps = caps; + rt_clock_time_device_register(&_aarch64_clock_dev, "clock_time_gtimer", caps); + rt_clock_time_set_default_source(&_aarch64_clock_dev); + _aarch64_clock_registered = RT_TRUE; + } +} diff --git a/components/drivers/clock_time/arch/risc-v/virt64/cputimer.c b/components/drivers/clock_time/arch/risc-v/virt64/cputimer.c new file mode 100644 index 0000000000..7921716b7f --- /dev/null +++ b/components/drivers/clock_time/arch/risc-v/virt64/cputimer.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-07-10 xqyjlj The first version. + */ + +#include + +static volatile unsigned long _init_cnt = 0; +static rt_bool_t _riscv_clock_registered = RT_FALSE; +static struct rt_clock_time_device _riscv_clock_dev; + +extern rt_uint64_t rt_hw_get_clock_timer_freq(void); + +static rt_uint64_t _riscv_clock_get_freq(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return rt_hw_get_clock_timer_freq(); +} + +static rt_uint64_t _riscv_clock_get_counter(struct rt_clock_time_device *dev) +{ + unsigned long time_elapsed; + + RT_UNUSED(dev); + __asm__ __volatile__("rdtime %0" : "=r"(time_elapsed)); + return (rt_uint64_t)(time_elapsed - _init_cnt); +} + +static rt_err_t _riscv_clock_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta) +{ + RT_UNUSED(dev); + RT_UNUSED(delta); + return -RT_ENOSYS; +} + +static const struct rt_clock_time_ops _riscv_clock_ops = +{ + _riscv_clock_get_freq, + _riscv_clock_get_counter, + _riscv_clock_set_timeout, +}; + +void rt_clock_time_source_init(void) +{ + __asm__ __volatile__("rdtime %0" : "=r"(_init_cnt)); + + if (!_riscv_clock_registered) + { + rt_uint8_t caps = RT_CLOCK_TIME_CAP_SOURCE; + + _riscv_clock_dev.ops = &_riscv_clock_ops; + _riscv_clock_dev.res_scale = RT_CLOCK_TIME_RESMUL; + _riscv_clock_dev.caps = caps; + rt_clock_time_device_register(&_riscv_clock_dev, "clock_time_rdtime", caps); + rt_clock_time_set_default_source(&_riscv_clock_dev); + _riscv_clock_registered = RT_TRUE; + } +} diff --git a/components/drivers/ktime/src/boottime.c b/components/drivers/clock_time/clock_boottime.c similarity index 33% rename from components/drivers/ktime/src/boottime.c rename to components/drivers/clock_time/clock_boottime.c index 8e69141b68..3185a04968 100644 --- a/components/drivers/ktime/src/boottime.c +++ b/components/drivers/clock_time/clock_boottime.c @@ -1,22 +1,31 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2023-07-10 xqyjlj The first version. + * 2025-01-01 RT-Thread Clock time boottime helpers */ -#include "ktime.h" +#include -#define __KTIME_MUL ((1000ULL * 1000 * 1000) / RT_TICK_PER_SECOND) - -rt_weak rt_err_t rt_ktime_boottime_get_us(struct timeval *tv) +rt_err_t rt_clock_boottime_get_us(struct timeval *tv) { + rt_uint64_t cnt; + rt_uint64_t res; + rt_uint64_t ns; + RT_ASSERT(tv != RT_NULL); - rt_uint64_t ns = (rt_ktime_cputimer_getcnt() * rt_ktime_cputimer_getres()) / RT_KTIME_RESMUL; + cnt = rt_clock_time_get_counter(); + res = rt_clock_time_get_res_scaled(); + if (res == 0) + { + return -RT_ERROR; + } + + ns = (cnt * res) / RT_CLOCK_TIME_RESMUL; tv->tv_sec = ns / (1000ULL * 1000 * 1000); tv->tv_usec = (ns % (1000ULL * 1000 * 1000)) / 1000; @@ -24,22 +33,43 @@ rt_weak rt_err_t rt_ktime_boottime_get_us(struct timeval *tv) return RT_EOK; } -rt_weak rt_err_t rt_ktime_boottime_get_s(time_t *t) +rt_err_t rt_clock_boottime_get_s(time_t *t) { + rt_uint64_t cnt; + rt_uint64_t res; + rt_uint64_t ns; + RT_ASSERT(t != RT_NULL); - rt_uint64_t ns = (rt_ktime_cputimer_getcnt() * rt_ktime_cputimer_getres()) / RT_KTIME_RESMUL; + cnt = rt_clock_time_get_counter(); + res = rt_clock_time_get_res_scaled(); + if (res == 0) + { + return -RT_ERROR; + } + ns = (cnt * res) / RT_CLOCK_TIME_RESMUL; *t = ns / (1000ULL * 1000 * 1000); return RT_EOK; } -rt_weak rt_err_t rt_ktime_boottime_get_ns(struct timespec *ts) +rt_err_t rt_clock_boottime_get_ns(struct timespec *ts) { + rt_uint64_t cnt; + rt_uint64_t res; + rt_uint64_t ns; + RT_ASSERT(ts != RT_NULL); - rt_uint64_t ns = (rt_ktime_cputimer_getcnt() * rt_ktime_cputimer_getres()) / RT_KTIME_RESMUL; + cnt = rt_clock_time_get_counter(); + res = rt_clock_time_get_res_scaled(); + if (res == 0) + { + return -RT_ERROR; + } + + ns = (cnt * res) / RT_CLOCK_TIME_RESMUL; ts->tv_sec = ns / (1000ULL * 1000 * 1000); ts->tv_nsec = ns % (1000ULL * 1000 * 1000); diff --git a/components/drivers/ktime/src/hrtimer.c b/components/drivers/clock_time/clock_hrtimer.c similarity index 57% rename from components/drivers/ktime/src/hrtimer.c rename to components/drivers/clock_time/clock_hrtimer.c index ca579a5e98..6fbfcecdea 100644 --- a/components/drivers/ktime/src/hrtimer.c +++ b/components/drivers/clock_time/clock_hrtimer.c @@ -1,23 +1,24 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2023-07-10 xqyjlj The first version. - * 2023-09-15 xqyjlj perf rt_hw_interrupt_disable/enable + * 2025-01-01 RT-Thread Clock time hrtimer */ #include #include #include -#define DBG_SECTION_NAME "drv.ktime" +#include + +#define DBG_SECTION_NAME "drv.clock_time" #define DBG_LEVEL DBG_INFO #include -#include "ktime.h" +#define CLOCK_TIME_NSEC_PER_SEC (1000000000ULL) #ifdef ARCH_CPU_64BIT #define _HRTIMER_MAX_CNT UINT64_MAX @@ -28,36 +29,88 @@ static rt_list_t _timer_list = RT_LIST_OBJECT_INIT(_timer_list); static RT_DEFINE_SPINLOCK(_spinlock); -rt_inline rt_ktime_hrtimer_t _first_hrtimer(void) +rt_inline rt_clock_hrtimer_t _first_hrtimer(void) +{ + return rt_list_isempty(&_timer_list) ? RT_NULL : rt_list_first_entry(&_timer_list, struct rt_clock_hrtimer, node); +} + +rt_inline unsigned long _clock_time_get_cnt(void) +{ + return rt_clock_time_get_counter(); +} + +rt_inline rt_bool_t _cnt_before(unsigned long a, unsigned long b) +{ + return ((rt_base_t)(a - b)) < 0; +} + +rt_inline rt_bool_t _cnt_after(unsigned long a, unsigned long b) { - return rt_list_isempty(&_timer_list) ? RT_NULL : rt_list_first_entry(&_timer_list, struct rt_ktime_hrtimer, node); + return _cnt_before(b, a); } -rt_weak rt_uint64_t rt_ktime_hrtimer_getres(void) +rt_weak rt_uint64_t rt_clock_hrtimer_getres(void) { - return ((1000ULL * 1000 * 1000) * RT_KTIME_RESMUL) / RT_TICK_PER_SECOND; + return rt_clock_time_get_event_res_scaled(); } -rt_weak unsigned long rt_ktime_hrtimer_getfrq(void) +rt_weak unsigned long rt_clock_hrtimer_getfrq(void) { - return RT_TICK_PER_SECOND; + return (unsigned long)rt_clock_time_get_event_freq(); } -rt_weak rt_err_t rt_ktime_hrtimer_settimeout(unsigned long cnt) +static rt_tick_t _hrtimer_cnt_to_tick(unsigned long cnt) +{ + rt_uint64_t res = rt_clock_hrtimer_getres(); + rt_uint64_t ns; + + if (res == 0) + { + return 0; + } + + ns = ((rt_uint64_t)cnt * res) / RT_CLOCK_TIME_RESMUL; + if (ns == 0) + { + return 1; + } + + ns = (ns * RT_TICK_PER_SECOND + CLOCK_TIME_NSEC_PER_SEC - 1) / CLOCK_TIME_NSEC_PER_SEC; + if (ns == 0) + { + return 1; + } + + return (rt_tick_t)ns; +} + +rt_weak rt_err_t rt_clock_hrtimer_settimeout(unsigned long cnt) { static rt_timer_t timer = RT_NULL; static struct rt_timer _sh_rtimer; + rt_tick_t tick; RT_ASSERT(cnt > 0); + if (rt_clock_time_set_timeout(cnt) == RT_EOK) + { + return RT_EOK; + } + + tick = _hrtimer_cnt_to_tick(cnt); + if (tick == 0) + { + return -RT_ERROR; + } + if (timer == RT_NULL) { timer = &_sh_rtimer; - rt_timer_init(timer, "shrtimer", (void (*)(void *))rt_ktime_hrtimer_process, RT_NULL, cnt, RT_TIMER_FLAG_ONE_SHOT); + rt_timer_init(timer, "shrtimer", (void (*)(void *))rt_clock_hrtimer_process, RT_NULL, + tick, RT_TIMER_FLAG_ONE_SHOT); } else { - rt_tick_t tick = cnt; rt_timer_control(timer, RT_TIMER_CTRL_SET_TIME, &tick); rt_timer_control(timer, RT_TIMER_CTRL_SET_PARM, RT_NULL); } @@ -71,36 +124,44 @@ rt_weak rt_err_t rt_ktime_hrtimer_settimeout(unsigned long cnt) return RT_EOK; } -/** - * @brief convert cnt from cputimer cnt to hrtimer cnt - * - * @param cnt - * @return unsigned long - */ static unsigned long _cnt_convert(unsigned long cnt) { - unsigned long rtn = 0; - unsigned long count = cnt - rt_ktime_cputimer_getcnt(); + unsigned long count; + rt_uint64_t src_res; + rt_uint64_t event_res; + rt_uint64_t result; + + count = cnt - _clock_time_get_cnt(); if (count > (_HRTIMER_MAX_CNT / 2)) + { + return 0; + } + + src_res = rt_clock_time_get_res_scaled(); + event_res = rt_clock_hrtimer_getres(); + if (src_res == 0 || event_res == 0) + { return 0; + } + + result = ((rt_uint64_t)count * src_res) / event_res; - rtn = (count * rt_ktime_cputimer_getres()) / rt_ktime_hrtimer_getres(); - return rtn == 0 ? 1 : rtn; /* at least 1 */ + return result == 0 ? 1 : (unsigned long)result; } static void _sleep_timeout(void *parameter) { - struct rt_ktime_hrtimer *timer = parameter; + struct rt_clock_hrtimer *timer = parameter; rt_completion_done(&timer->completion); } -static void _insert_timer_to_list_locked(rt_ktime_hrtimer_t timer) +static void _insert_timer_to_list_locked(rt_clock_hrtimer_t timer) { - rt_ktime_hrtimer_t iter; + rt_clock_hrtimer_t iter; rt_list_for_each_entry(iter, &_timer_list, node) { - if (iter->timeout_cnt > timer->timeout_cnt) + if (_cnt_before(timer->timeout_cnt, iter->timeout_cnt)) { break; } @@ -112,17 +173,22 @@ static void _insert_timer_to_list_locked(rt_ktime_hrtimer_t timer) static void _hrtimer_process_locked(void) { - rt_ktime_hrtimer_t timer; + rt_clock_hrtimer_t timer; - for (timer = _first_hrtimer(); - (timer != RT_NULL) && (timer->timeout_cnt <= rt_ktime_cputimer_getcnt()); - timer = _first_hrtimer()) + while ((timer = _first_hrtimer()) != RT_NULL) { + unsigned long now = _clock_time_get_cnt(); + + if (_cnt_before(now, timer->timeout_cnt)) + { + break; + } + rt_list_remove(&(timer->node)); if (timer->flag & RT_TIMER_FLAG_PERIODIC) { - timer->timeout_cnt = timer->delay_cnt + rt_ktime_cputimer_getcnt(); + timer->timeout_cnt = timer->delay_cnt + now; _insert_timer_to_list_locked(timer); } else @@ -139,8 +205,8 @@ static void _hrtimer_process_locked(void) static void _set_next_timeout_locked(void) { - rt_ktime_hrtimer_t timer; - rt_ubase_t next_timeout_hrtimer_cnt; + rt_clock_hrtimer_t timer; + rt_ubase_t next_timeout_cnt; rt_bool_t find_next; do @@ -148,10 +214,10 @@ static void _set_next_timeout_locked(void) find_next = RT_FALSE; if ((timer = _first_hrtimer()) != RT_NULL) { - next_timeout_hrtimer_cnt = _cnt_convert(timer->timeout_cnt); - if (next_timeout_hrtimer_cnt > 0) + next_timeout_cnt = _cnt_convert(timer->timeout_cnt); + if (next_timeout_cnt > 0) { - rt_ktime_hrtimer_settimeout(next_timeout_hrtimer_cnt); + rt_clock_hrtimer_settimeout(next_timeout_cnt); } else { @@ -163,7 +229,7 @@ static void _set_next_timeout_locked(void) while (find_next); } -void rt_ktime_hrtimer_process(void) +void rt_clock_hrtimer_process(void) { rt_base_t level = rt_spin_lock_irqsave(&_spinlock); @@ -173,17 +239,16 @@ void rt_ktime_hrtimer_process(void) rt_spin_unlock_irqrestore(&_spinlock, level); } -void rt_ktime_hrtimer_init(rt_ktime_hrtimer_t timer, +void rt_clock_hrtimer_init(rt_clock_hrtimer_t timer, const char *name, rt_uint8_t flag, void (*timeout)(void *parameter), void *parameter) { - /* parameter check */ RT_ASSERT(timer != RT_NULL); RT_ASSERT(timeout != RT_NULL); - rt_memset(timer, 0, sizeof(struct rt_ktime_hrtimer)); + rt_memset(timer, 0, sizeof(struct rt_clock_hrtimer)); timer->flag = flag & ~RT_TIMER_FLAG_ACTIVATED; timer->timeout_func = timeout; @@ -193,16 +258,15 @@ void rt_ktime_hrtimer_init(rt_ktime_hrtimer_t timer, rt_completion_init(&timer->completion); } -rt_err_t rt_ktime_hrtimer_start(rt_ktime_hrtimer_t timer, unsigned long delay_cnt) +rt_err_t rt_clock_hrtimer_start(rt_clock_hrtimer_t timer, unsigned long delay_cnt) { rt_base_t level; - /* parameter check */ RT_ASSERT(timer != RT_NULL); RT_ASSERT(delay_cnt < (_HRTIMER_MAX_CNT / 2)); timer->delay_cnt = delay_cnt; - timer->timeout_cnt = timer->delay_cnt + rt_ktime_cputimer_getcnt(); + timer->timeout_cnt = timer->delay_cnt + _clock_time_get_cnt(); level = rt_spin_lock_irqsave(&_spinlock); @@ -220,11 +284,11 @@ rt_err_t rt_ktime_hrtimer_start(rt_ktime_hrtimer_t timer, unsigned long delay_cn return RT_EOK; } -rt_err_t rt_ktime_hrtimer_stop(rt_ktime_hrtimer_t timer) +rt_err_t rt_clock_hrtimer_stop(rt_clock_hrtimer_t timer) { rt_base_t level; - RT_ASSERT(timer != RT_NULL); /* timer check */ + RT_ASSERT(timer != RT_NULL); level = rt_spin_lock_irqsave(&_spinlock); @@ -243,17 +307,15 @@ rt_err_t rt_ktime_hrtimer_stop(rt_ktime_hrtimer_t timer) return RT_EOK; } -rt_err_t rt_ktime_hrtimer_control(rt_ktime_hrtimer_t timer, int cmd, void *arg) +rt_err_t rt_clock_hrtimer_control(rt_clock_hrtimer_t timer, int cmd, void *arg) { rt_base_t level; - /* parameter check */ RT_ASSERT(timer != RT_NULL); level = rt_spin_lock_irqsave(&_spinlock); switch (cmd) { - case RT_TIMER_CTRL_GET_TIME: *(unsigned long *)arg = timer->delay_cnt; break; @@ -261,7 +323,7 @@ rt_err_t rt_ktime_hrtimer_control(rt_ktime_hrtimer_t timer, int cmd, void *arg) case RT_TIMER_CTRL_SET_TIME: RT_ASSERT((*(unsigned long *)arg) < (_HRTIMER_MAX_CNT / 2)); timer->delay_cnt = *(unsigned long *)arg; - timer->timeout_cnt = *(unsigned long *)arg + rt_ktime_cputimer_getcnt(); + timer->timeout_cnt = *(unsigned long *)arg + _clock_time_get_cnt(); break; case RT_TIMER_CTRL_SET_ONESHOT: @@ -275,12 +337,10 @@ rt_err_t rt_ktime_hrtimer_control(rt_ktime_hrtimer_t timer, int cmd, void *arg) case RT_TIMER_CTRL_GET_STATE: if (timer->flag & RT_TIMER_FLAG_ACTIVATED) { - /*timer is start and run*/ *(rt_uint32_t *)arg = RT_TIMER_FLAG_ACTIVATED; } else { - /*timer is stop*/ *(rt_uint32_t *)arg = RT_TIMER_FLAG_DEACTIVATED; } break; @@ -289,7 +349,10 @@ rt_err_t rt_ktime_hrtimer_control(rt_ktime_hrtimer_t timer, int cmd, void *arg) *(unsigned long *)arg = timer->timeout_cnt; break; case RT_TIMER_CTRL_GET_FUNC: - arg = (void *)timer->timeout_func; + if (arg != RT_NULL) + { + *(void **)arg = (void *)timer->timeout_func; + } break; case RT_TIMER_CTRL_SET_FUNC: @@ -312,21 +375,17 @@ rt_err_t rt_ktime_hrtimer_control(rt_ktime_hrtimer_t timer, int cmd, void *arg) return RT_EOK; } -rt_err_t rt_ktime_hrtimer_detach(rt_ktime_hrtimer_t timer) +rt_err_t rt_clock_hrtimer_detach(rt_clock_hrtimer_t timer) { rt_base_t level; - /* parameter check */ RT_ASSERT(timer != RT_NULL); - /* notify the timer stop event */ rt_completion_wakeup_by_errno(&timer->completion, RT_ERROR); level = rt_spin_lock_irqsave(&_spinlock); - /* stop timer */ timer->flag &= ~RT_TIMER_FLAG_ACTIVATED; - /* when interrupted */ if (timer->error == -RT_EINTR || timer->error == RT_EINTR) { rt_list_remove(&timer->node); @@ -338,49 +397,61 @@ rt_err_t rt_ktime_hrtimer_detach(rt_ktime_hrtimer_t timer) return RT_EOK; } -/************************** delay ***************************/ - -void rt_ktime_hrtimer_delay_init(struct rt_ktime_hrtimer *timer) +void rt_clock_hrtimer_delay_init(struct rt_clock_hrtimer *timer) { - rt_ktime_hrtimer_init(timer, "hrtimer_sleep", RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_HARD_TIMER, + rt_clock_hrtimer_init(timer, "hrtimer_sleep", RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_HARD_TIMER, _sleep_timeout, timer); } -void rt_ktime_hrtimer_delay_detach(struct rt_ktime_hrtimer *timer) +void rt_clock_hrtimer_delay_detach(struct rt_clock_hrtimer *timer) { - rt_ktime_hrtimer_detach(timer); + rt_clock_hrtimer_detach(timer); } -rt_err_t rt_ktime_hrtimer_sleep(struct rt_ktime_hrtimer *timer, unsigned long cnt) +rt_err_t rt_clock_hrtimer_sleep(struct rt_clock_hrtimer *timer, unsigned long cnt) { rt_err_t err; if (cnt == 0) + { return -RT_EINVAL; + } - err = rt_ktime_hrtimer_start(timer, cnt); + err = rt_clock_hrtimer_start(timer, cnt); if (err) + { return err; + } err = rt_completion_wait_flags(&(timer->completion), RT_WAITING_FOREVER, RT_INTERRUPTIBLE); - rt_ktime_hrtimer_keep_errno(timer, err); + rt_clock_hrtimer_keep_errno(timer, err); return err; } -rt_err_t rt_ktime_hrtimer_ndelay(struct rt_ktime_hrtimer *timer, unsigned long ns) +rt_err_t rt_clock_hrtimer_ndelay(struct rt_clock_hrtimer *timer, unsigned long ns) +{ + rt_uint64_t res = rt_clock_time_get_res_scaled(); + if (res == 0) + { + return -RT_ERROR; + } + + return rt_clock_hrtimer_sleep(timer, (ns * RT_CLOCK_TIME_RESMUL) / res); +} + +rt_err_t rt_clock_hrtimer_udelay(struct rt_clock_hrtimer *timer, unsigned long us) { - rt_uint64_t res = rt_ktime_cputimer_getres(); - return rt_ktime_hrtimer_sleep(timer, (ns * RT_KTIME_RESMUL) / res); + return rt_clock_hrtimer_ndelay(timer, us * 1000); } -rt_err_t rt_ktime_hrtimer_udelay(struct rt_ktime_hrtimer *timer, unsigned long us) +rt_err_t rt_clock_hrtimer_mdelay(struct rt_clock_hrtimer *timer, unsigned long ms) { - return rt_ktime_hrtimer_ndelay(timer, us * 1000); + return rt_clock_hrtimer_ndelay(timer, ms * 1000000); } -rt_err_t rt_ktime_hrtimer_mdelay(struct rt_ktime_hrtimer *timer, unsigned long ms) +void rt_clock_time_event_isr(void) { - return rt_ktime_hrtimer_ndelay(timer, ms * 1000000); + rt_clock_hrtimer_process(); } diff --git a/components/drivers/hwtimer/hwtimer-arm_arch.c b/components/drivers/clock_time/clock_time_arm_arch.c similarity index 100% rename from components/drivers/hwtimer/hwtimer-arm_arch.c rename to components/drivers/clock_time/clock_time_arm_arch.c diff --git a/components/drivers/clock_time/clock_time_core.c b/components/drivers/clock_time/clock_time_core.c new file mode 100644 index 0000000000..2682270ba3 --- /dev/null +++ b/components/drivers/clock_time/clock_time_core.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-01-01 RT-Thread Clock time core + */ + +#include +#include +#include + +#include + +#define CLOCK_TIME_NSEC_PER_SEC (1000000000ULL) + +static rt_uint64_t _clock_time_tick_get_freq(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return RT_TICK_PER_SECOND; +} + +static rt_uint64_t _clock_time_tick_get_counter(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return (rt_uint64_t)rt_tick_get(); +} + +static rt_err_t _clock_time_tick_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta) +{ + RT_UNUSED(dev); + RT_UNUSED(delta); + return -RT_ENOSYS; +} + +static const struct rt_clock_time_ops _clock_time_tick_ops = +{ + _clock_time_tick_get_freq, + _clock_time_tick_get_counter, + _clock_time_tick_set_timeout, +}; + +static struct rt_clock_time_device _clock_time_tick_dev = +{ + .ops = &_clock_time_tick_ops, + .res_scale = RT_CLOCK_TIME_RESMUL, + .caps = RT_CLOCK_TIME_CAP_SOURCE, +}; + +static struct rt_clock_time_device * _clock_time_default_source = &_clock_time_tick_dev; +static struct rt_clock_time_device * _clock_time_default_event = RT_NULL; + +rt_weak void rt_clock_time_source_init(void) +{ + return; +} + +static rt_uint64_t _clock_time_get_res_scaled(struct rt_clock_time_device *dev) +{ + rt_uint64_t freq; + rt_uint64_t scale; + + if (dev == RT_NULL || dev->ops == RT_NULL || dev->ops->get_freq == RT_NULL) + { + return 0; + } + + freq = dev->ops->get_freq(dev); + if (freq == 0) + { + return 0; + } + + scale = dev->res_scale ? dev->res_scale : RT_CLOCK_TIME_RESMUL; + + return (CLOCK_TIME_NSEC_PER_SEC * scale) / freq; +} + +rt_err_t rt_clock_time_device_register(struct rt_clock_time_device *dev, const char *name, rt_uint8_t caps) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev->ops != RT_NULL); + + dev->caps = caps; + if (dev->res_scale == 0) + { + dev->res_scale = RT_CLOCK_TIME_RESMUL; + } + + if (name != RT_NULL) + { + dev->parent.type = RT_Device_Class_Timer; + result = rt_device_register(&dev->parent, name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + } + + if ((caps & RT_CLOCK_TIME_CAP_SOURCE) && _clock_time_default_source == &_clock_time_tick_dev) + { + _clock_time_default_source = dev; + } + + if ((caps & RT_CLOCK_TIME_CAP_EVENT) && _clock_time_default_event == RT_NULL) + { + _clock_time_default_event = dev; + } + + return result; +} + +void rt_clock_time_set_default_source(struct rt_clock_time_device *dev) +{ + if (dev != RT_NULL) + { + _clock_time_default_source = dev; + } +} + +void rt_clock_time_set_default_event(struct rt_clock_time_device *dev) +{ + if (dev != RT_NULL) + { + _clock_time_default_event = dev; + } +} + +struct rt_clock_time_device *rt_clock_time_get_default_source(void) +{ + return _clock_time_default_source ? _clock_time_default_source : &_clock_time_tick_dev; +} + +struct rt_clock_time_device *rt_clock_time_get_default_event(void) +{ + return _clock_time_default_event; +} + +rt_uint64_t rt_clock_time_get_freq(void) +{ + struct rt_clock_time_device *src = rt_clock_time_get_default_source(); + + if (src == RT_NULL || src->ops == RT_NULL || src->ops->get_freq == RT_NULL) + { + return 0; + } + + return src->ops->get_freq(src); +} + +rt_uint64_t rt_clock_time_get_counter(void) +{ + struct rt_clock_time_device *src = rt_clock_time_get_default_source(); + + if (src == RT_NULL || src->ops == RT_NULL || src->ops->get_counter == RT_NULL) + { + return 0; + } + + return src->ops->get_counter(src); +} + +rt_uint64_t rt_clock_time_get_res_scaled(void) +{ + return _clock_time_get_res_scaled(rt_clock_time_get_default_source()); +} + +rt_uint64_t rt_clock_time_get_event_freq(void) +{ + struct rt_clock_time_device *event = rt_clock_time_get_default_event(); + + if (event == RT_NULL) + { + return rt_clock_time_get_freq(); + } + + if (event->ops == RT_NULL || event->ops->get_freq == RT_NULL) + { + return 0; + } + + return event->ops->get_freq(event); +} + +rt_uint64_t rt_clock_time_get_event_res_scaled(void) +{ + struct rt_clock_time_device *event = rt_clock_time_get_default_event(); + + if (event == RT_NULL) + { + return rt_clock_time_get_res_scaled(); + } + + return _clock_time_get_res_scaled(event); +} + +rt_uint64_t rt_clock_time_counter_to_ns(rt_uint64_t cnt) +{ + rt_uint64_t res = rt_clock_time_get_res_scaled(); + + if (res == 0) + { + return 0; + } + + return (cnt * res) / RT_CLOCK_TIME_RESMUL; +} + +rt_uint64_t rt_clock_time_ns_to_counter(rt_uint64_t ns) +{ + rt_uint64_t res = rt_clock_time_get_res_scaled(); + + if (res == 0) + { + return 0; + } + + return (ns * RT_CLOCK_TIME_RESMUL) / res; +} + +rt_err_t rt_clock_time_set_timeout(rt_uint64_t delta) +{ + struct rt_clock_time_device *event = rt_clock_time_get_default_event(); + + if (event == RT_NULL || event->ops == RT_NULL || event->ops->set_timeout == RT_NULL) + { + return -RT_ENOSYS; + } + + return event->ops->set_timeout(event, delta); +} diff --git a/components/drivers/hwtimer/hwtimer.c b/components/drivers/clock_time/clock_timer.c similarity index 52% rename from components/drivers/hwtimer/hwtimer.c rename to components/drivers/clock_time/clock_timer.c index 1b2792558d..94e06ccb11 100644 --- a/components/drivers/hwtimer/hwtimer.c +++ b/components/drivers/clock_time/clock_timer.c @@ -10,19 +10,20 @@ #include #include +#include -#define DBG_TAG "hwtimer" +#define DBG_TAG "clock_timer" #define DBG_LVL DBG_INFO #include #ifdef RT_USING_DM -void (*rt_device_hwtimer_us_delay)(rt_uint32_t us) = RT_NULL; +void (*rt_clock_timer_us_delay)(rt_uint32_t us) = RT_NULL; -void rt_hw_us_delay(rt_uint32_t us) +rt_weak void rt_hw_us_delay(rt_uint32_t us) { - if (rt_device_hwtimer_us_delay) + if (rt_clock_timer_us_delay) { - rt_device_hwtimer_us_delay(us); + rt_clock_timer_us_delay(us); } else { @@ -33,7 +34,75 @@ void rt_hw_us_delay(rt_uint32_t us) } #endif /* RT_USING_DM */ -rt_inline rt_uint32_t timeout_calc(rt_hwtimer_t *timer, rt_hwtimerval_t *tv) +static struct rt_clock_time_device _clock_timer_clock_dev; +static rt_clock_timer_t *_clock_timer_owner = RT_NULL; + +static rt_uint64_t _clock_timer_clock_get_freq(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + if (_clock_timer_owner == RT_NULL) + { + return 0; + } + + return (rt_uint64_t)_clock_timer_owner->freq; +} + +static rt_uint64_t _clock_timer_clock_get_counter(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + if (_clock_timer_owner == RT_NULL || + _clock_timer_owner->ops == RT_NULL || + _clock_timer_owner->ops->count_get == RT_NULL) + { + return 0; + } + + return (rt_uint64_t)_clock_timer_owner->ops->count_get(_clock_timer_owner); +} + +static rt_err_t _clock_timer_clock_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta) +{ + RT_UNUSED(dev); + if (_clock_timer_owner == RT_NULL || + _clock_timer_owner->ops == RT_NULL || + _clock_timer_owner->ops->start == RT_NULL) + { + return -RT_ENOSYS; + } + + if (delta == 0) + { + if (_clock_timer_owner->ops->stop) + { + _clock_timer_owner->ops->stop(_clock_timer_owner); + } + return RT_EOK; + } + + if (_clock_timer_owner->ops->stop) + { + _clock_timer_owner->ops->stop(_clock_timer_owner); + } + + _clock_timer_owner->mode = CLOCK_TIMER_MODE_ONESHOT; + + if (delta > (rt_uint64_t)RT_UINT32_MAX) + { + delta = RT_UINT32_MAX; + } + + return _clock_timer_owner->ops->start(_clock_timer_owner, (rt_uint32_t)delta, CLOCK_TIMER_MODE_ONESHOT); +} + +static const struct rt_clock_time_ops _clock_timer_clock_ops = +{ + _clock_timer_clock_get_freq, + _clock_timer_clock_get_counter, + _clock_timer_clock_set_timeout, +}; + +rt_inline rt_uint32_t timeout_calc(rt_clock_timer_t *timer, rt_clock_timerval_t *tv) { float overflow; float timeout; @@ -91,12 +160,12 @@ rt_inline rt_uint32_t timeout_calc(rt_hwtimer_t *timer, rt_hwtimerval_t *tv) return counter; } -static rt_err_t rt_hwtimer_init(struct rt_device *dev) +static rt_err_t rt_clock_timer_init(struct rt_device *dev) { rt_err_t result = RT_EOK; - rt_hwtimer_t *timer; + rt_clock_timer_t *timer; - timer = (rt_hwtimer_t *)dev; + timer = (rt_clock_timer_t *)dev; /* try to change to 1MHz */ if ((1000000 <= timer->info->maxfreq) && (1000000 >= timer->info->minfreq)) { @@ -106,7 +175,7 @@ static rt_err_t rt_hwtimer_init(struct rt_device *dev) { timer->freq = timer->info->minfreq; } - timer->mode = HWTIMER_MODE_ONESHOT; + timer->mode = CLOCK_TIMER_MODE_ONESHOT; timer->cycles = 0; timer->overflow = 0; @@ -122,15 +191,15 @@ static rt_err_t rt_hwtimer_init(struct rt_device *dev) return result; } -static rt_err_t rt_hwtimer_open(struct rt_device *dev, rt_uint16_t oflag) +static rt_err_t rt_clock_timer_open(struct rt_device *dev, rt_uint16_t oflag) { rt_err_t result = RT_EOK; - rt_hwtimer_t *timer; + rt_clock_timer_t *timer; - timer = (rt_hwtimer_t *)dev; + timer = (rt_clock_timer_t *)dev; if (timer->ops->control != RT_NULL) { - timer->ops->control(timer, HWTIMER_CTRL_FREQ_SET, &timer->freq); + timer->ops->control(timer, CLOCK_TIMER_CTRL_FREQ_SET, &timer->freq); } else { @@ -140,12 +209,12 @@ static rt_err_t rt_hwtimer_open(struct rt_device *dev, rt_uint16_t oflag) return result; } -static rt_err_t rt_hwtimer_close(struct rt_device *dev) +static rt_err_t rt_clock_timer_close(struct rt_device *dev) { rt_err_t result = RT_EOK; - rt_hwtimer_t *timer; + rt_clock_timer_t *timer; - timer = (rt_hwtimer_t*)dev; + timer = (rt_clock_timer_t*)dev; if (timer->ops->init != RT_NULL) { timer->ops->init(timer, 0); @@ -161,16 +230,16 @@ static rt_err_t rt_hwtimer_close(struct rt_device *dev) return result; } -static rt_ssize_t rt_hwtimer_read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size) +static rt_ssize_t rt_clock_timer_read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size) { - rt_hwtimer_t *timer; - rt_hwtimerval_t tv; + rt_clock_timer_t *timer; + rt_clock_timerval_t tv; rt_uint32_t cnt; rt_base_t level; rt_int32_t overflow; float t; - timer = (rt_hwtimer_t *)dev; + timer = (rt_clock_timer_t *)dev; if (timer->ops->count_get == RT_NULL) return 0; @@ -179,11 +248,11 @@ static rt_ssize_t rt_hwtimer_read(struct rt_device *dev, rt_off_t pos, void *buf overflow = timer->overflow; rt_hw_interrupt_enable(level); - if (timer->info->cntmode == HWTIMER_CNTMODE_DW) + if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_DW) { cnt = (rt_uint32_t)(timer->freq * timer->period_sec) - cnt; } - if (timer->mode == HWTIMER_MODE_ONESHOT) + if (timer->mode == CLOCK_TIMER_MODE_ONESHOT) { overflow = 0; } @@ -197,18 +266,18 @@ static rt_ssize_t rt_hwtimer_read(struct rt_device *dev, rt_off_t pos, void *buf return size; } -static rt_ssize_t rt_hwtimer_write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size) +static rt_ssize_t rt_clock_timer_write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size) { rt_base_t level; rt_uint32_t t; - rt_hwtimer_mode_t opm = HWTIMER_MODE_PERIOD; - rt_hwtimer_t *timer; + rt_clock_timer_mode_t opm = CLOCK_TIMER_MODE_PERIOD; + rt_clock_timer_t *timer; - timer = (rt_hwtimer_t *)dev; + timer = (rt_clock_timer_t *)dev; if ((timer->ops->start == RT_NULL) || (timer->ops->stop == RT_NULL)) return 0; - if (size != sizeof(rt_hwtimerval_t)) + if (size != sizeof(rt_clock_timerval_t)) return 0; timer->ops->stop(timer); @@ -217,10 +286,10 @@ static rt_ssize_t rt_hwtimer_write(struct rt_device *dev, rt_off_t pos, const vo timer->overflow = 0; rt_hw_interrupt_enable(level); - t = timeout_calc(timer, (rt_hwtimerval_t*)buffer); - if ((timer->cycles <= 1) && (timer->mode == HWTIMER_MODE_ONESHOT)) + t = timeout_calc(timer, (rt_clock_timerval_t*)buffer); + if ((timer->cycles <= 1) && (timer->mode == CLOCK_TIMER_MODE_ONESHOT)) { - opm = HWTIMER_MODE_ONESHOT; + opm = CLOCK_TIMER_MODE_ONESHOT; } if (timer->ops->start(timer, t, opm) != RT_EOK) @@ -229,17 +298,17 @@ static rt_ssize_t rt_hwtimer_write(struct rt_device *dev, rt_off_t pos, const vo return size; } -static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) +static rt_err_t rt_clock_timer_control(struct rt_device *dev, int cmd, void *args) { rt_base_t level; rt_err_t result = RT_EOK; - rt_hwtimer_t *timer; + rt_clock_timer_t *timer; - timer = (rt_hwtimer_t *)dev; + timer = (rt_clock_timer_t *)dev; switch (cmd) { - case HWTIMER_CTRL_STOP: + case CLOCK_TIMER_CTRL_STOP: { if (timer->ops->stop != RT_NULL) { @@ -251,7 +320,7 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) } } break; - case HWTIMER_CTRL_FREQ_SET: + case CLOCK_TIMER_CTRL_FREQ_SET: { rt_int32_t *f; @@ -285,7 +354,7 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) } } break; - case HWTIMER_CTRL_INFO_GET: + case CLOCK_TIMER_CTRL_INFO_GET: { if (args == RT_NULL) { @@ -293,12 +362,12 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) break; } - *((struct rt_hwtimer_info*)args) = *timer->info; + *((struct rt_clock_timer_info*)args) = *timer->info; } break; - case HWTIMER_CTRL_MODE_SET: + case CLOCK_TIMER_CTRL_MODE_SET: { - rt_hwtimer_mode_t *m; + rt_clock_timer_mode_t *m; if (args == RT_NULL) { @@ -306,9 +375,9 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) break; } - m = (rt_hwtimer_mode_t*)args; + m = (rt_clock_timer_mode_t*)args; - if ((*m != HWTIMER_MODE_ONESHOT) && (*m != HWTIMER_MODE_PERIOD)) + if ((*m != CLOCK_TIMER_MODE_ONESHOT) && (*m != CLOCK_TIMER_MODE_PERIOD)) { result = -RT_ERROR; break; @@ -335,7 +404,7 @@ static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args) return result; } -void rt_device_hwtimer_isr(rt_hwtimer_t *timer) +void rt_clock_timer_isr(rt_clock_timer_t *timer) { rt_base_t level; @@ -356,7 +425,7 @@ void rt_device_hwtimer_isr(rt_hwtimer_t *timer) rt_hw_interrupt_enable(level); - if (timer->mode == HWTIMER_MODE_ONESHOT) + if (timer->mode == CLOCK_TIMER_MODE_ONESHOT) { if (timer->ops->stop != RT_NULL) { @@ -364,9 +433,14 @@ void rt_device_hwtimer_isr(rt_hwtimer_t *timer) } } + if (timer == _clock_timer_owner) + { + rt_clock_time_event_isr(); + } + if (timer->parent.rx_indicate != RT_NULL) { - timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval)); + timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_clock_timerval)); } } else @@ -376,20 +450,22 @@ void rt_device_hwtimer_isr(rt_hwtimer_t *timer) } #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops hwtimer_ops = +const static struct rt_device_ops clock_timer_ops = { - rt_hwtimer_init, - rt_hwtimer_open, - rt_hwtimer_close, - rt_hwtimer_read, - rt_hwtimer_write, - rt_hwtimer_control + rt_clock_timer_init, + rt_clock_timer_open, + rt_clock_timer_close, + rt_clock_timer_read, + rt_clock_timer_write, + rt_clock_timer_control }; #endif -rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void *user_data) +rt_err_t rt_clock_timer_register(rt_clock_timer_t *timer, const char *name, void *user_data) { struct rt_device *device; + rt_err_t result; + rt_uint8_t caps = 0; RT_ASSERT(timer != RT_NULL); RT_ASSERT(timer->ops != RT_NULL); @@ -402,16 +478,50 @@ rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void device->tx_complete = RT_NULL; #ifdef RT_USING_DEVICE_OPS - device->ops = &hwtimer_ops; + device->ops = &clock_timer_ops; #else - device->init = rt_hwtimer_init; - device->open = rt_hwtimer_open; - device->close = rt_hwtimer_close; - device->read = rt_hwtimer_read; - device->write = rt_hwtimer_write; - device->control = rt_hwtimer_control; + device->init = rt_clock_timer_init; + device->open = rt_clock_timer_open; + device->close = rt_clock_timer_close; + device->read = rt_clock_timer_read; + device->write = rt_clock_timer_write; + device->control = rt_clock_timer_control; #endif device->user_data = user_data; - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + result = rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE); + if (result != RT_EOK) + { + return result; + } + + if (timer->ops->start) + { + caps |= RT_CLOCK_TIME_CAP_EVENT; + } + + if (caps && _clock_timer_owner == RT_NULL) + { + char ct_name[RT_NAME_MAX]; + + _clock_timer_owner = timer; + _clock_timer_clock_dev.ops = &_clock_timer_clock_ops; + _clock_timer_clock_dev.res_scale = RT_CLOCK_TIME_RESMUL; + _clock_timer_clock_dev.caps = caps; + + rt_snprintf(ct_name, sizeof(ct_name), "clock_time_%s", name); + rt_clock_time_device_register(&_clock_timer_clock_dev, ct_name, caps); + + if ((caps & RT_CLOCK_TIME_CAP_EVENT) && rt_clock_time_get_default_event() == RT_NULL) + { + rt_clock_time_set_default_event(&_clock_timer_clock_dev); + if (!(device->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + rt_device_init(device); + rt_device_open(device, RT_DEVICE_OFLAG_RDWR); + } + } + } + + return RT_EOK; } diff --git a/components/drivers/cputime/Kconfig b/components/drivers/cputime/Kconfig deleted file mode 100644 index 97c2c46259..0000000000 --- a/components/drivers/cputime/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -config RT_USING_CPUTIME - bool "Enable CPU time for high resolution clock counter" - default n - help - When enable this option, the BSP should provide a rt_clock_cputime_ops - for CPU time by: - const static struct rt_clock_cputime_ops _ops = {...}; - clock_cpu_setops(&_ops); - - Then user can use high resolution clock counter with: - - ts1 = clock_cpu_gettime(); - ts2 = clock_cpu_gettime(); - - /* and get the ms of delta tick with API: */ - ms_tick = clock_cpu_millisecond(t2 - t1); - us_tick = clock_cpu_microsecond(t2 - t1); - -if RT_USING_CPUTIME - config RT_USING_CPUTIME_CORTEXM - bool "Support Cortex-M CPU" - default y - depends on ARCH_ARM_CORTEX_M0 || ARCH_ARM_CORTEX_M3 || ARCH_ARM_CORTEX_M4 || ARCH_ARM_CORTEX_M7 - select PKG_USING_PERF_COUNTER - config RT_USING_CPUTIME_RISCV - bool "Use rdtime instructions for CPU time" - default y - depends on ARCH_RISCV64 - help - Some RISCV64 MCU Use rdtime instructions read CPU time. - config CPUTIME_TIMER_FREQ - int "CPUTIME timer freq" - default 0 -endif diff --git a/components/drivers/cputime/SConscript b/components/drivers/cputime/SConscript deleted file mode 100644 index 9fec4641e5..0000000000 --- a/components/drivers/cputime/SConscript +++ /dev/null @@ -1,18 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd + '/../include'] -src = Split(''' -cputime.c -cputimer.c -''') - -if GetDepend('RT_USING_CPUTIME_CORTEXM'): - src += ['cputime_cortexm.c'] - -if GetDepend('RT_USING_CPUTIME_RISCV'): - src += ['cputime_riscv.c'] - -group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_CPUTIME'], CPPPATH = CPPPATH) - -Return('group') diff --git a/components/drivers/cputime/cputime.c b/components/drivers/cputime/cputime.c deleted file mode 100644 index 42298ea98c..0000000000 --- a/components/drivers/cputime/cputime.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-12-23 Bernard first version - */ - -#include -#include -#include - -static const struct rt_clock_cputime_ops *_cputime_ops = RT_NULL; - -/** - * The clock_cpu_getres() function shall return the resolution of CPU time, the - * number of nanosecond per tick. - * - * @return the number of nanosecond per tick(x (1000UL * 1000)) - */ -uint64_t clock_cpu_getres(void) -{ - if (_cputime_ops) - return _cputime_ops->cputime_getres(); - - rt_set_errno(ENOSYS); - return 0; -} - -/** - * The clock_cpu_gettime() function shall return the current value of cpu time tick. - * - * @return the cpu tick - */ -uint64_t clock_cpu_gettime(void) -{ - if (_cputime_ops) - return _cputime_ops->cputime_gettime(); - - rt_set_errno(ENOSYS); - return 0; -} - -/** - * The clock_cpu_settimeout() fucntion set timeout time and timeout callback function - * The timeout callback function will be called when the timeout time is reached - * - * @param tick the Timeout tick - * @param timeout the Timeout function - * @param parameter the Parameters of timeout function - * - */ -int clock_cpu_settimeout(uint64_t tick, void (*timeout)(void *param), void *param) -{ - if (_cputime_ops) - return _cputime_ops->cputime_settimeout(tick, timeout, param); - - rt_set_errno(ENOSYS); - return 0; -} - -int clock_cpu_issettimeout(void) -{ - if (_cputime_ops) - return _cputime_ops->cputime_settimeout != RT_NULL; - return RT_FALSE; -} - -/** - * The clock_cpu_microsecond() fucntion shall return the microsecond according to - * cpu_tick parameter. - * - * @param cpu_tick the cpu tick - * - * @return the microsecond - */ -uint64_t clock_cpu_microsecond(uint64_t cpu_tick) -{ - uint64_t unit = clock_cpu_getres(); - - return (uint64_t)(((cpu_tick * unit) / (1000UL * 1000)) / 1000); -} - -/** - * The clock_cpu_microsecond() fucntion shall return the millisecond according to - * cpu_tick parameter. - * - * @param cpu_tick the cpu tick - * - * @return the millisecond - */ -uint64_t clock_cpu_millisecond(uint64_t cpu_tick) -{ - uint64_t unit = clock_cpu_getres(); - - return (uint64_t)(((cpu_tick * unit) / (1000UL * 1000)) / (1000UL * 1000)); -} - -/** - * The clock_cpu_seops() function shall set the ops of cpu time. - * - * @return always return 0. - */ -int clock_cpu_setops(const struct rt_clock_cputime_ops *ops) -{ - _cputime_ops = ops; - if (ops) - { - RT_ASSERT(ops->cputime_getres != RT_NULL); - RT_ASSERT(ops->cputime_gettime != RT_NULL); - } - - return 0; -} diff --git a/components/drivers/cputime/cputime_cortexm.c b/components/drivers/cputime/cputime_cortexm.c deleted file mode 100644 index 100910a9f9..0000000000 --- a/components/drivers/cputime/cputime_cortexm.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-12-23 Bernard first version - * 2022-06-14 Meco Man suuport pref_counter - */ - -#include -#include -#include - -#include -#ifdef PKG_USING_PERF_COUNTER -#include -#endif - -/* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */ -static uint64_t cortexm_cputime_getres(void) -{ - uint64_t ret = 1000UL * 1000 * 1000; - - ret = (ret * (1000UL * 1000)) / SystemCoreClock; - return ret; -} - -static uint64_t cortexm_cputime_gettime(void) -{ -#ifdef PKG_USING_PERF_COUNTER - return get_system_ticks(); -#else - return DWT->CYCCNT; -#endif -} - -const static struct rt_clock_cputime_ops _cortexm_ops = -{ - cortexm_cputime_getres, - cortexm_cputime_gettime -}; - - -int cortexm_cputime_init(void) -{ -#ifdef PKG_USING_PERF_COUNTER - clock_cpu_setops(&_cortexm_ops); -#else - /* check support bit */ - if ((DWT->CTRL & (1UL << DWT_CTRL_NOCYCCNT_Pos)) == 0) - { - /* enable trace*/ - CoreDebug->DEMCR |= (1UL << CoreDebug_DEMCR_TRCENA_Pos); - - /* whether cycle counter not enabled */ - if ((DWT->CTRL & (1UL << DWT_CTRL_CYCCNTENA_Pos)) == 0) - { - /* enable cycle counter */ - DWT->CTRL |= (1UL << DWT_CTRL_CYCCNTENA_Pos); - } - - clock_cpu_setops(&_cortexm_ops); - } -#endif /* PKG_USING_PERF_COUNTER */ - return 0; -} -INIT_BOARD_EXPORT(cortexm_cputime_init); diff --git a/components/drivers/cputime/cputime_riscv.c b/components/drivers/cputime/cputime_riscv.c deleted file mode 100644 index 597157c226..0000000000 --- a/components/drivers/cputime/cputime_riscv.c +++ /dev/null @@ -1,37 +0,0 @@ -#include -#include -#include - -#include - -/* Use Cycle counter of Data Watchpoint and Trace Register for CPU time */ - -static uint64_t riscv_cputime_getres(void) -{ - uint64_t ret = 1000UL * 1000 * 1000; - - ret = (ret * (1000UL * 1000)) / CPUTIME_TIMER_FREQ; - return ret; -} - -static uint64_t riscv_cputime_gettime(void) -{ - uint64_t time_elapsed; - __asm__ __volatile__( - "rdtime %0" - : "=r"(time_elapsed)); - return time_elapsed; -} - -const static struct rt_clock_cputime_ops _riscv_ops = -{ - riscv_cputime_getres, - riscv_cputime_gettime -}; - -int riscv_cputime_init(void) -{ - clock_cpu_setops(&_riscv_ops); - return 0; -} -INIT_BOARD_EXPORT(riscv_cputime_init); diff --git a/components/drivers/cputime/cputimer.c b/components/drivers/cputime/cputimer.c deleted file mode 100644 index 0431833640..0000000000 --- a/components/drivers/cputime/cputimer.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-02-13 zhkag first version - * 2023-04-03 xqyjlj fix cputimer in multithreading - */ - -#include -#include -#include - -static rt_list_t _cputimer_list = RT_LIST_OBJECT_INIT(_cputimer_list); -static struct rt_cputimer *_cputimer_nowtimer = RT_NULL; - -static void _cputime_sleep_timeout(void *parameter) -{ - struct rt_semaphore *sem; - sem = (struct rt_semaphore *)parameter; - rt_sem_release(sem); -} - -static void _cputime_timeout_callback(void *parameter) -{ - struct rt_cputimer *timer; - timer = (struct rt_cputimer *)parameter; - rt_base_t level; - level = rt_hw_interrupt_disable(); - _cputimer_nowtimer = RT_NULL; - rt_list_remove(&(timer->row)); - rt_hw_interrupt_enable(level); - timer->timeout_func(timer->parameter); - - if (&_cputimer_list != _cputimer_list.prev) - { - struct rt_cputimer *t; - t = rt_list_entry(_cputimer_list.next, struct rt_cputimer, row); - clock_cpu_settimeout(t->timeout_tick, _cputime_timeout_callback, t); - } - else - { - clock_cpu_settimeout(RT_NULL, RT_NULL, RT_NULL); - } -} - -static void _set_next_timeout() -{ - struct rt_cputimer *t; - - if (&_cputimer_list != _cputimer_list.prev) - { - t = rt_list_entry((&_cputimer_list)->next, struct rt_cputimer, row); - if (_cputimer_nowtimer != RT_NULL) - { - if (t != _cputimer_nowtimer && t->timeout_tick < _cputimer_nowtimer->timeout_tick) - { - _cputimer_nowtimer = t; - clock_cpu_settimeout(t->timeout_tick, _cputime_timeout_callback, t); - } - } - else - { - _cputimer_nowtimer = t; - clock_cpu_settimeout(t->timeout_tick, _cputime_timeout_callback, t); - } - } - else - { - _cputimer_nowtimer = RT_NULL; - clock_cpu_settimeout(RT_NULL, RT_NULL, RT_NULL); - } -} - -void rt_cputimer_init(rt_cputimer_t timer, - const char *name, - void (*timeout)(void *parameter), - void *parameter, - rt_uint64_t tick, - rt_uint8_t flag) -{ - /* parameter check */ - RT_ASSERT(timer != RT_NULL); - RT_ASSERT(timeout != RT_NULL); - RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE); - - /* set flag */ - timer->parent.flag = flag; - - /* set deactivated */ - timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; - timer->timeout_func = timeout; - timer->parameter = parameter; - timer->timeout_tick = tick + clock_cpu_gettime(); - timer->init_tick = tick; - - rt_list_init(&(timer->row)); - rt_sem_init(&(timer->sem), "cputime", 0, RT_IPC_FLAG_PRIO); -} - -rt_err_t rt_cputimer_delete(rt_cputimer_t timer) -{ - rt_base_t level; - - /* parameter check */ - RT_ASSERT(timer != RT_NULL); - RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE); - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - rt_list_remove(&timer->row); - /* stop timer */ - timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - _set_next_timeout(); - - return RT_EOK; -} - -rt_err_t rt_cputimer_start(rt_cputimer_t timer) -{ - rt_list_t *timer_list; - rt_base_t level; - - /* parameter check */ - RT_ASSERT(timer != RT_NULL); - RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE); - - /* stop timer firstly */ - level = rt_hw_interrupt_disable(); - /* remove timer from list */ - - rt_list_remove(&timer->row); - /* change status of timer */ - timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; - - timer_list = &_cputimer_list; - - for (; timer_list != _cputimer_list.prev; - timer_list = timer_list->next) - { - struct rt_cputimer *t; - rt_list_t *p = timer_list->next; - - t = rt_list_entry(p, struct rt_cputimer, row); - - if ((t->timeout_tick - timer->timeout_tick) == 0) - { - continue; - } - else if ((t->timeout_tick - timer->timeout_tick) < 0x7fffffffffffffff) - { - break; - } - } - - rt_list_insert_after(timer_list, &(timer->row)); - - timer->parent.flag |= RT_TIMER_FLAG_ACTIVATED; - - _set_next_timeout(); - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -rt_err_t rt_cputimer_stop(rt_cputimer_t timer) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - /* timer check */ - RT_ASSERT(timer != RT_NULL); - RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE); - - if (!(timer->parent.flag & RT_TIMER_FLAG_ACTIVATED)) - { - rt_hw_interrupt_enable(level); - return -RT_ERROR; - } - - rt_list_remove(&timer->row); - /* change status */ - timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; - - _set_next_timeout(); - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -rt_err_t rt_cputimer_control(rt_cputimer_t timer, int cmd, void *arg) -{ - rt_base_t level; - - /* parameter check */ - RT_ASSERT(timer != RT_NULL); - RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE); - - level = rt_hw_interrupt_disable(); - switch (cmd) - { - case RT_TIMER_CTRL_GET_TIME: - *(rt_uint64_t *)arg = timer->init_tick; - break; - - case RT_TIMER_CTRL_SET_TIME: - RT_ASSERT((*(rt_uint64_t *)arg) < 0x7fffffffffffffff); - timer->init_tick = *(rt_uint64_t *)arg; - timer->timeout_tick = *(rt_uint64_t *)arg + clock_cpu_gettime(); - break; - - case RT_TIMER_CTRL_SET_ONESHOT: - timer->parent.flag &= ~RT_TIMER_FLAG_PERIODIC; - break; - - case RT_TIMER_CTRL_SET_PERIODIC: - timer->parent.flag |= RT_TIMER_FLAG_PERIODIC; - break; - - case RT_TIMER_CTRL_GET_STATE: - if (timer->parent.flag & RT_TIMER_FLAG_ACTIVATED) - { - /*timer is start and run*/ - *(rt_uint32_t *)arg = RT_TIMER_FLAG_ACTIVATED; - } - else - { - /*timer is stop*/ - *(rt_uint32_t *)arg = RT_TIMER_FLAG_DEACTIVATED; - } - break; - - case RT_TIMER_CTRL_GET_REMAIN_TIME: - *(rt_uint64_t *)arg = timer->timeout_tick; - break; - case RT_TIMER_CTRL_GET_FUNC: - arg = (void *)timer->timeout_func; - break; - - case RT_TIMER_CTRL_SET_FUNC: - timer->timeout_func = (void (*)(void *))arg; - break; - - case RT_TIMER_CTRL_GET_PARM: - *(void **)arg = timer->parameter; - break; - - case RT_TIMER_CTRL_SET_PARM: - timer->parameter = arg; - break; - - default: - break; - } - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -rt_err_t rt_cputimer_detach(rt_cputimer_t timer) -{ - rt_base_t level; - - /* parameter check */ - RT_ASSERT(timer != RT_NULL); - RT_ASSERT(clock_cpu_issettimeout() != RT_FALSE); - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - rt_list_remove(&timer->row); - /* stop timer */ - timer->parent.flag &= ~RT_TIMER_FLAG_ACTIVATED; - - _set_next_timeout(); - /* enable interrupt */ - rt_hw_interrupt_enable(level); - - rt_sem_detach(&(timer->sem)); - - return RT_EOK; -} - -rt_err_t rt_cputime_sleep(rt_uint64_t tick) -{ - rt_base_t level; - struct rt_cputimer cputimer; - - if (!clock_cpu_issettimeout()) - { - rt_int32_t ms = clock_cpu_millisecond(tick); - return rt_thread_delay(rt_tick_from_millisecond(ms)); - } - - if (tick == 0) - { - return -RT_EINVAL; - } - - rt_cputimer_init(&cputimer, "cputime_sleep", _cputime_sleep_timeout, &(cputimer.sem), tick, - RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER); - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - rt_cputimer_start(&cputimer); /* reset the timeout of thread timer and start it */ - rt_hw_interrupt_enable(level); - rt_sem_take_interruptible(&(cputimer.sem), RT_WAITING_FOREVER); - - rt_cputimer_detach(&cputimer); - return RT_EOK; -} - -rt_err_t rt_cputime_ndelay(rt_uint64_t ns) -{ - uint64_t unit = clock_cpu_getres(); - return rt_cputime_sleep(ns * (1000UL * 1000) / unit); -} - -rt_err_t rt_cputime_udelay(rt_uint64_t us) -{ - return rt_cputime_ndelay(us * 1000); -} - -rt_err_t rt_cputime_mdelay(rt_uint64_t ms) -{ - return rt_cputime_ndelay(ms * 1000000); -} diff --git a/components/drivers/hwtimer/Kconfig b/components/drivers/hwtimer/Kconfig deleted file mode 100644 index 0fd1974b89..0000000000 --- a/components/drivers/hwtimer/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -menuconfig RT_USING_HWTIMER - bool "Using Hardware Timer device drivers" - default n - -config RT_HWTIMER_ARM_ARCH - bool "ARM ARCH Timer" - depends on RT_USING_DM - depends on RT_USING_HWTIMER - depends on ARCH_ARM_CORTEX_A || ARCH_ARMV8 - default n - -if RT_USING_DM && RT_USING_HWTIMER - osource "$(SOC_DM_HWTIMER_DIR)/Kconfig" -endif diff --git a/components/drivers/hwtimer/SConscript b/components/drivers/hwtimer/SConscript deleted file mode 100644 index b6ffc580ed..0000000000 --- a/components/drivers/hwtimer/SConscript +++ /dev/null @@ -1,18 +0,0 @@ -from building import * - -group = [] - -if not GetDepend(['RT_USING_HWTIMER']): - Return('group') - -cwd = GetCurrentDir() -CPPPATH = [cwd + '/../include'] - -src = ['hwtimer.c'] - -if GetDepend(['RT_HWTIMER_ARM_ARCH']): - src += ['hwtimer-arm_arch.c'] - -group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/components/drivers/include/drivers/clock_time.h b/components/drivers/include/drivers/clock_time.h new file mode 100644 index 0000000000..7374b97d00 --- /dev/null +++ b/components/drivers/include/drivers/clock_time.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-01-01 RT-Thread Clock time subsystem + */ +#ifndef __CLOCK_TIME_H__ +#define __CLOCK_TIME_H__ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define RT_CLOCK_TIME_RESMUL (1000000ULL) + +#define RT_CLOCK_TIME_CAP_SOURCE (1U << 0) +#define RT_CLOCK_TIME_CAP_EVENT (1U << 1) + +struct rt_clock_time_device; + +struct rt_clock_time_ops +{ + rt_uint64_t (*get_freq)(struct rt_clock_time_device *dev); + rt_uint64_t (*get_counter)(struct rt_clock_time_device *dev); + rt_err_t (*set_timeout)(struct rt_clock_time_device *dev, rt_uint64_t delta); +}; + +struct rt_clock_time_device +{ + struct rt_device parent; + const struct rt_clock_time_ops *ops; + rt_uint64_t res_scale; + rt_uint8_t caps; +}; + +/* Clock time timer device (replacement for legacy hardware timer device) */ +typedef enum +{ + CLOCK_TIMER_CTRL_FREQ_SET = RT_DEVICE_CTRL_BASE(Timer) + 0x01, + CLOCK_TIMER_CTRL_STOP = RT_DEVICE_CTRL_BASE(Timer) + 0x02, + CLOCK_TIMER_CTRL_INFO_GET = RT_DEVICE_CTRL_BASE(Timer) + 0x03, + CLOCK_TIMER_CTRL_MODE_SET = RT_DEVICE_CTRL_BASE(Timer) + 0x04 +} rt_clock_timer_ctrl_t; + +typedef enum +{ + CLOCK_TIMER_MODE_ONESHOT = 0x01, + CLOCK_TIMER_MODE_PERIOD +} rt_clock_timer_mode_t; + +typedef struct rt_clock_timerval +{ + rt_int32_t sec; + rt_int32_t usec; +} rt_clock_timerval_t; + +#define CLOCK_TIMER_CNTMODE_UP 0x01 +#define CLOCK_TIMER_CNTMODE_DW 0x02 + +struct rt_clock_timer_device; + +struct rt_clock_timer_ops +{ + void (*init)(struct rt_clock_timer_device *timer, rt_uint32_t state); + rt_err_t (*start)(struct rt_clock_timer_device *timer, rt_uint32_t cnt, rt_clock_timer_mode_t mode); + void (*stop)(struct rt_clock_timer_device *timer); + rt_uint32_t (*count_get)(struct rt_clock_timer_device *timer); + rt_err_t (*control)(struct rt_clock_timer_device *timer, rt_uint32_t cmd, void *args); +}; + +struct rt_clock_timer_info +{ + rt_int32_t maxfreq; + rt_int32_t minfreq; + rt_uint32_t maxcnt; + rt_uint8_t cntmode; +}; + +typedef struct rt_clock_timer_device +{ + struct rt_device parent; + const struct rt_clock_timer_ops *ops; + const struct rt_clock_timer_info *info; + + rt_int32_t freq; + rt_int32_t overflow; + float period_sec; + rt_int32_t cycles; + rt_int32_t reload; + rt_clock_timer_mode_t mode; + +} rt_clock_timer_t; + +rt_err_t rt_clock_timer_register(rt_clock_timer_t *timer, const char *name, void *user_data); +void rt_clock_timer_isr(rt_clock_timer_t *timer); + +#ifdef RT_USING_DM +extern void (*rt_clock_timer_us_delay)(rt_uint32_t us); +#endif + +struct rt_clock_hrtimer +{ + rt_uint8_t flag; /**< compatible to tick timer's flag */ + char name[RT_NAME_MAX]; + rt_list_t node; + void *parameter; + unsigned long delay_cnt; + unsigned long timeout_cnt; + rt_err_t error; + struct rt_completion completion; + void (*timeout_func)(void *parameter); +}; +typedef struct rt_clock_hrtimer *rt_clock_hrtimer_t; + +rt_err_t rt_clock_time_device_register(struct rt_clock_time_device *dev, const char *name, rt_uint8_t caps); + +void rt_clock_time_set_default_source(struct rt_clock_time_device *dev); +void rt_clock_time_set_default_event(struct rt_clock_time_device *dev); +struct rt_clock_time_device *rt_clock_time_get_default_source(void); +struct rt_clock_time_device *rt_clock_time_get_default_event(void); + +void rt_clock_time_source_init(void); + +rt_uint64_t rt_clock_time_get_freq(void); +rt_uint64_t rt_clock_time_get_counter(void); +rt_uint64_t rt_clock_time_get_res_scaled(void); +rt_uint64_t rt_clock_time_get_event_freq(void); +rt_uint64_t rt_clock_time_get_event_res_scaled(void); + +rt_uint64_t rt_clock_time_counter_to_ns(rt_uint64_t cnt); +rt_uint64_t rt_clock_time_ns_to_counter(rt_uint64_t ns); + +rt_err_t rt_clock_time_set_timeout(rt_uint64_t delta); +void rt_clock_time_event_isr(void); + +rt_err_t rt_clock_boottime_get_us(struct timeval *tv); +rt_err_t rt_clock_boottime_get_s(time_t *t); +rt_err_t rt_clock_boottime_get_ns(struct timespec *ts); + +rt_uint64_t rt_clock_hrtimer_getres(void); +unsigned long rt_clock_hrtimer_getfrq(void); +rt_err_t rt_clock_hrtimer_settimeout(unsigned long cnt); +void rt_clock_hrtimer_process(void); + +void rt_clock_hrtimer_init(rt_clock_hrtimer_t timer, + const char *name, + rt_uint8_t flag, + void (*timeout)(void *parameter), + void *parameter); +rt_err_t rt_clock_hrtimer_start(rt_clock_hrtimer_t timer, unsigned long cnt); +rt_err_t rt_clock_hrtimer_stop(rt_clock_hrtimer_t timer); +rt_err_t rt_clock_hrtimer_control(rt_clock_hrtimer_t timer, int cmd, void *arg); +rt_err_t rt_clock_hrtimer_detach(rt_clock_hrtimer_t timer); + +rt_inline void rt_clock_hrtimer_keep_errno(rt_clock_hrtimer_t timer, rt_err_t err) +{ + RT_ASSERT(timer != RT_NULL); + + timer->error = err; + rt_set_errno(-err); +} + +void rt_clock_hrtimer_delay_init(struct rt_clock_hrtimer *timer); +void rt_clock_hrtimer_delay_detach(struct rt_clock_hrtimer *timer); +void rt_clock_hrtimer_process(void); + +rt_err_t rt_clock_hrtimer_sleep(struct rt_clock_hrtimer *timer, unsigned long cnt); +rt_err_t rt_clock_hrtimer_ndelay(struct rt_clock_hrtimer *timer, unsigned long ns); +rt_err_t rt_clock_hrtimer_udelay(struct rt_clock_hrtimer *timer, unsigned long us); +rt_err_t rt_clock_hrtimer_mdelay(struct rt_clock_hrtimer *timer, unsigned long ms); + +#ifdef __cplusplus +} +#endif + +#endif /* __CLOCK_TIME_H__ */ diff --git a/components/drivers/include/drivers/core/master_id.h b/components/drivers/include/drivers/core/master_id.h index 5bf9e611cb..99b1b09856 100644 --- a/components/drivers/include/drivers/core/master_id.h +++ b/components/drivers/include/drivers/core/master_id.h @@ -26,7 +26,7 @@ #define MASTER_ID_SERIAL 13 /* Clock Timer */ -#define MASTER_ID_HWTIMER 21 +#define MASTER_ID_CLOCK_TIMER 21 #define MASTER_ID_PTP 22 #define MASTER_ID_RTC 23 diff --git a/components/drivers/include/drivers/cputime.h b/components/drivers/include/drivers/cputime.h deleted file mode 100644 index 478ccfd019..0000000000 --- a/components/drivers/include/drivers/cputime.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-12-23 Bernard first version - */ - -#ifndef CPUTIME_H__ -#define CPUTIME_H__ - -#include -#include "cputimer.h" - -struct rt_clock_cputime_ops -{ - uint64_t (*cputime_getres)(void); - uint64_t (*cputime_gettime)(void); - int (*cputime_settimeout)(uint64_t tick, void (*timeout)(void *param), void *param); -}; - -uint64_t clock_cpu_getres(void); -uint64_t clock_cpu_gettime(void); -int clock_cpu_settimeout(uint64_t tick, void (*timeout)(void *param), void *param); -int clock_cpu_issettimeout(void); - -uint64_t clock_cpu_microsecond(uint64_t cpu_tick); -uint64_t clock_cpu_millisecond(uint64_t cpu_tick); - -int clock_cpu_setops(const struct rt_clock_cputime_ops *ops); - -#ifdef RT_USING_CPUTIME_RISCV -int riscv_cputime_init(void); -#endif /* RT_USING_CPUTIME_RISCV */ - -#endif diff --git a/components/drivers/include/drivers/cputimer.h b/components/drivers/include/drivers/cputimer.h deleted file mode 100644 index 371992a41e..0000000000 --- a/components/drivers/include/drivers/cputimer.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-02-13 zhkag first version - */ - -#ifndef CPUTIMER_H__ -#define CPUTIMER_H__ - -#include - -struct rt_cputimer -{ - struct rt_object parent; /**< inherit from rt_object */ - rt_list_t row; - void (*timeout_func)(void *parameter); - void *parameter; - rt_uint64_t init_tick; - rt_uint64_t timeout_tick; - struct rt_semaphore sem; -}; -typedef struct rt_cputimer *rt_cputimer_t; - -rt_err_t rt_cputimer_detach(rt_cputimer_t timer); - -#ifdef RT_USING_HEAP -void rt_cputimer_init(rt_cputimer_t timer, - const char *name, - void (*timeout)(void *parameter), - void *parameter, - rt_uint64_t tick, - rt_uint8_t flag); -rt_err_t rt_cputimer_delete(rt_cputimer_t timer); -#endif - -rt_err_t rt_cputimer_start(rt_cputimer_t timer); -rt_err_t rt_cputimer_stop(rt_cputimer_t timer); -rt_err_t rt_cputimer_control(rt_cputimer_t timer, int cmd, void *arg); -rt_err_t rt_cputime_sleep(rt_uint64_t tick); -rt_err_t rt_cputime_ndelay(rt_uint64_t ns); -rt_err_t rt_cputime_udelay(rt_uint64_t us); -rt_err_t rt_cputime_mdelay(rt_uint64_t ms); - -#endif diff --git a/components/drivers/include/drivers/hwtimer.h b/components/drivers/include/drivers/hwtimer.h deleted file mode 100644 index 6f11ff2c54..0000000000 --- a/components/drivers/include/drivers/hwtimer.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __HWTIMER_H__ -#define __HWTIMER_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Timer Control Command */ -typedef enum -{ - HWTIMER_CTRL_FREQ_SET = RT_DEVICE_CTRL_BASE(Timer) + 0x01, /* set the count frequency */ - HWTIMER_CTRL_STOP = RT_DEVICE_CTRL_BASE(Timer) + 0x02, /* stop timer */ - HWTIMER_CTRL_INFO_GET = RT_DEVICE_CTRL_BASE(Timer) + 0x03, /* get a timer feature information */ - HWTIMER_CTRL_MODE_SET = RT_DEVICE_CTRL_BASE(Timer) + 0x04 /* Setting the timing mode(oneshot/period) */ -} rt_hwtimer_ctrl_t; - -/* Timing Mode */ -typedef enum -{ - HWTIMER_MODE_ONESHOT = 0x01, - HWTIMER_MODE_PERIOD -} rt_hwtimer_mode_t; - -/* Time Value */ -typedef struct rt_hwtimerval -{ - rt_int32_t sec; /* second */ - rt_int32_t usec; /* microsecond */ -} rt_hwtimerval_t; - -#define HWTIMER_CNTMODE_UP 0x01 /* increment count mode */ -#define HWTIMER_CNTMODE_DW 0x02 /* decreasing count mode */ - -struct rt_hwtimer_device; - -struct rt_hwtimer_ops -{ - void (*init)(struct rt_hwtimer_device *timer, rt_uint32_t state); - rt_err_t (*start)(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode); - void (*stop)(struct rt_hwtimer_device *timer); - rt_uint32_t (*count_get)(struct rt_hwtimer_device *timer); - rt_err_t (*control)(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args); -}; - -/* Timer Feature Information */ -struct rt_hwtimer_info -{ - rt_int32_t maxfreq; /* the maximum count frequency timer support */ - rt_int32_t minfreq; /* the minimum count frequency timer support */ - rt_uint32_t maxcnt; /* counter maximum value */ - rt_uint8_t cntmode; /* count mode (inc/dec) */ -}; - -typedef struct rt_hwtimer_device -{ - struct rt_device parent; - const struct rt_hwtimer_ops *ops; - const struct rt_hwtimer_info *info; - - rt_int32_t freq; /* counting frequency set by the user */ - rt_int32_t overflow; /* timer overflows */ - float period_sec; - rt_int32_t cycles; /* how many times will generate a timeout event after overflow */ - rt_int32_t reload; /* reload cycles(using in period mode) */ - rt_hwtimer_mode_t mode; /* timing mode(oneshot/period) */ -} rt_hwtimer_t; - -rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void *user_data); -void rt_device_hwtimer_isr(rt_hwtimer_t *timer); - -#ifdef RT_USING_DM -extern void (*rt_device_hwtimer_us_delay)(rt_uint32_t us); -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 50a97beee5..c3a1277449 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -242,18 +242,14 @@ extern "C" { #include "drivers/dev_can.h" #endif /* RT_USING_CAN */ -#ifdef RT_USING_HWTIMER -#include "drivers/hwtimer.h" -#endif /* RT_USING_HWTIMER */ +#ifdef RT_USING_CLOCK_TIME +#include "drivers/clock_time.h" +#endif /* RT_USING_CLOCK_TIME */ #ifdef RT_USING_AUDIO #include "drivers/dev_audio.h" #endif /* RT_USING_AUDIO */ -#ifdef RT_USING_CPUTIME -#include "drivers/cputime.h" -#endif /* RT_USING_CPUTIME */ - #ifdef RT_USING_ADC #include "drivers/adc.h" #endif /* RT_USING_ADC */ diff --git a/components/drivers/input/Kconfig b/components/drivers/input/Kconfig index 707a7500d9..fc70a67790 100644 --- a/components/drivers/input/Kconfig +++ b/components/drivers/input/Kconfig @@ -13,7 +13,7 @@ config RT_INPUT_POWER config RT_INPUT_UAPI bool "Input event Unix API" depends on RT_USING_INPUT - depends on RT_USING_KTIME + depends on RT_USING_CLOCK_TIME depends on RT_USING_POSIX_DEVIO default n default y if RT_USING_SMART diff --git a/components/drivers/input/input_uapi.c b/components/drivers/input/input_uapi.c index c1ce87efb5..21dca947c7 100644 --- a/components/drivers/input/input_uapi.c +++ b/components/drivers/input/input_uapi.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #define DBG_TAG "input.uapi" @@ -384,7 +384,7 @@ void input_uapi_event(struct rt_input_device *idev, struct rt_input_event *event uapi_event = &uapi->events[w_idx]; - rt_ktime_boottime_get_us(&uapi_event->time); + rt_clock_boottime_get_us(&uapi_event->time); uapi_event->type = event->type; uapi_event->code = event->code; uapi_event->value = event->value; diff --git a/components/drivers/ktime/Kconfig b/components/drivers/ktime/Kconfig deleted file mode 100644 index 170271c222..0000000000 --- a/components/drivers/ktime/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -menuconfig RT_USING_KTIME - bool "Ktime: kernel time" - default n diff --git a/components/drivers/ktime/README.md b/components/drivers/ktime/README.md deleted file mode 100644 index b878f93d4c..0000000000 --- a/components/drivers/ktime/README.md +++ /dev/null @@ -1,63 +0,0 @@ -# ktime - -## 1、介绍 - -ktime 为 kernel time，为内核时间子系统，实现了内核启动时间以及芯片内核 cputimer 时间管理以及一个 ns 精度的高精度定时器， - -## 2、如何打开 ktime - -使用 ktime 需要在 RT-Thread 的 menuconfig 中选择它，具体路径如下： - -``` -RT-Thread Components - [*] Ktime: kernel time -``` - -## 3、使用 ktime - -> 函数的功能以及参数类型已经写在头文件的注释之中，本文不再赘述 - -### 3.1、boottime - -boottime 为系统启动时间，即为系统从上电开始到现在运行的时间，默认的时间基准为芯片内核的 cputimer 的 cnt 值，已经适配了 aarch64 与 riscv64 平台，例如 stm32 等平台需要在自己的 bsp 里面进行适配（boottime 里面函数都为 weak function），需要注意 tick 从中断到设置中间的时延 - -**此值应当为 Readonly** - -### 3.2、cputimer - -cputimer 为芯片内核的 cputimer，也可以认为是 os tick 来源的那个定时器，cputimer 主要是提供了一个统一的接口去获得其分辨率，频率，cnt 值 - -**此值应当为 Readonly** - -### 3.3、hrtimer - -> TODO: hrtimer 目前还是使用优先级链表的方式进行管理，在遇到任务的大规模并发时还是存在部分性能问题，待内核有一个统一的红黑树组件后，再进行优化 - -hrtimer 为高精度定时器，需要重写其 weak 函数（需要对接到硬件定时器，否则默认走的是软件定时器，分辨率只有 os tick 的值）才能正常使用，其主要使用方法： - -#### 3.3.1、延时 - -hrtimer 的延时并不是 while(1)式死等，它会将一个线程挂起，睡眠多少时间后通过硬件定时器将其唤醒（注：延时 ns 并不是真的能准确的延时这么多，而是在保证性能的情况下尽可能的延时） - -- rt_ktime_hrtimer_sleep：单位为 cputimer 的 tick 值 -- rt_ktime_hrtimer_ndelay：单位为 ns -- rt_ktime_hrtimer_udelay：单位为 us -- rt_ktime_hrtimer_mdelay：单位为 ms - -#### 3.3.1、定时器 - -hrtimer 还提供了一套 rt_timer 风格的 api - -- rt_ktime_hrtimer_init -- rt_ktime_hrtimer_delete -- rt_ktime_hrtimer_start -- rt_ktime_hrtimer_stop -- rt_ktime_hrtimer_control -- rt_ktime_hrtimer_detach - -需要注意，此定时器回调函数依旧处于中断之中，不能做一些耗时的任务 - -## 5、联系方式 - -- 维护：xqyjlj -- 主页：https://github.com/xqyjlj diff --git a/components/drivers/ktime/SConscript b/components/drivers/ktime/SConscript deleted file mode 100644 index 20a0295719..0000000000 --- a/components/drivers/ktime/SConscript +++ /dev/null @@ -1,24 +0,0 @@ -import os -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() - -src = Glob('src/*.c') -list = os.listdir(cwd + "/src") -if rtconfig.ARCH in list: - if os.path.exists(cwd + "/src/" + rtconfig.ARCH + "/" + rtconfig.CPU): - src += Glob("src/" + rtconfig.ARCH + "/" + rtconfig.CPU + "/*.c") - else: - src += Glob("src/" + rtconfig.ARCH + "/*.c") -CPPPATH = [cwd, cwd + "/inc"] -LOCAL_CCFLAGS = '' -if rtconfig.PLATFORM in ['gcc', 'armclang']: - LOCAL_CCFLAGS += ' -std=gnu99' -elif rtconfig.PLATFORM in ['armcc']: - LOCAL_CCFLAGS += ' --c99 --gnu' - -group = DefineGroup('DeviceDrivers', src, depend=['RT_USING_KTIME'], CPPPATH=CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS) - -Return('group') diff --git a/components/drivers/ktime/inc/ktime.h b/components/drivers/ktime/inc/ktime.h deleted file mode 100644 index a430f85a17..0000000000 --- a/components/drivers/ktime/inc/ktime.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-07-10 xqyjlj The first version. - * 2024-04-26 Shell Improve ipc performance - */ - -#ifndef __KTIME_H__ -#define __KTIME_H__ - -#include -#include -#include - -#include "rtthread.h" - -#define RT_KTIME_RESMUL (1000000ULL) - -struct rt_ktime_hrtimer -{ - rt_uint8_t flag; /**< compatible to tick timer's flag */ - char name[RT_NAME_MAX]; - rt_list_t node; - void *parameter; - unsigned long delay_cnt; - unsigned long timeout_cnt; - rt_err_t error; - struct rt_completion completion; - void (*timeout_func)(void *parameter); -}; -typedef struct rt_ktime_hrtimer *rt_ktime_hrtimer_t; - -/** - * @brief Get boottime with us precision - * - * @param tv: timeval - * @return rt_err_t - */ -rt_err_t rt_ktime_boottime_get_us(struct timeval *tv); - -/** - * @brief Get boottime with s precision - * - * @param t: time_t - * @return rt_err_t - */ -rt_err_t rt_ktime_boottime_get_s(time_t *t); - -/** - * @brief Get boottime with ns precision - * - * @param ts: timespec - * @return rt_err_t - */ -rt_err_t rt_ktime_boottime_get_ns(struct timespec *ts); - -/** - * @brief Get cputimer resolution - * - * @return (resolution * RT_KTIME_RESMUL) - */ -rt_uint64_t rt_ktime_cputimer_getres(void); - -/** - * @brief Get cputimer frequency - * - * @return frequency - */ -unsigned long rt_ktime_cputimer_getfrq(void); - -/** - * @brief Get cputimer the value of the cnt counter - * - * @return cnt - */ -unsigned long rt_ktime_cputimer_getcnt(void); - -/** - * @brief Init cputimer - * - */ -void rt_ktime_cputimer_init(void); - -/** - * @brief Get hrtimer resolution - * - * @return (resolution * RT_KTIME_RESMUL) - */ -rt_uint64_t rt_ktime_hrtimer_getres(void); - -/** - * @brief Get hrtimer frequency - * - * @return frequency - */ -unsigned long rt_ktime_hrtimer_getfrq(void); - -/** - * @brief set hrtimer interrupt timeout count (cnt), you should re-implemented it in hrtimer device driver - * - * @param cnt: hrtimer requires a timing cnt value - * @return rt_err_t - */ -rt_err_t rt_ktime_hrtimer_settimeout(unsigned long cnt); - -/** - * @brief called in hrtimer device driver isr routinue, it will process the timeouts - */ -void rt_ktime_hrtimer_process(void); - -void rt_ktime_hrtimer_init(rt_ktime_hrtimer_t timer, - const char *name, - rt_uint8_t flag, - void (*timeout)(void *parameter), - void *parameter); -rt_err_t rt_ktime_hrtimer_start(rt_ktime_hrtimer_t timer, unsigned long cnt); -rt_err_t rt_ktime_hrtimer_stop(rt_ktime_hrtimer_t timer); -rt_err_t rt_ktime_hrtimer_control(rt_ktime_hrtimer_t timer, int cmd, void *arg); -rt_err_t rt_ktime_hrtimer_detach(rt_ktime_hrtimer_t timer); - -rt_inline void rt_ktime_hrtimer_keep_errno(rt_ktime_hrtimer_t timer, rt_err_t err) -{ - RT_ASSERT(timer != RT_NULL); - - timer->error = err; - rt_set_errno(-err); -} - -void rt_ktime_hrtimer_delay_init(struct rt_ktime_hrtimer *timer); -void rt_ktime_hrtimer_delay_detach(struct rt_ktime_hrtimer *timer); -void rt_ktime_hrtimer_process(void); - -/** - * @brief sleep by the cputimer cnt value - * - * @param cnt: the cputimer cnt value - * @return rt_err_t - */ -rt_err_t rt_ktime_hrtimer_sleep(struct rt_ktime_hrtimer *timer, unsigned long cnt); - -/** - * @brief sleep by ns - * - * @param ns: ns - * @return rt_err_t - */ -rt_err_t rt_ktime_hrtimer_ndelay(struct rt_ktime_hrtimer *timer, unsigned long ns); - -/** - * @brief sleep by us - * - * @param us: us - * @return rt_err_t - */ -rt_err_t rt_ktime_hrtimer_udelay(struct rt_ktime_hrtimer *timer, unsigned long us); - -/** - * @brief sleep by ms - * - * @param ms: ms - * @return rt_err_t - */ -rt_err_t rt_ktime_hrtimer_mdelay(struct rt_ktime_hrtimer *timer, unsigned long ms); - -#endif diff --git a/components/drivers/ktime/src/aarch64/cputimer.c b/components/drivers/ktime/src/aarch64/cputimer.c deleted file mode 100644 index 005848eccd..0000000000 --- a/components/drivers/ktime/src/aarch64/cputimer.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-07-10 xqyjlj The first version. - */ - -#include "gtimer.h" -#include "ktime.h" - -static volatile unsigned long _init_cnt = 0; - -rt_uint64_t rt_ktime_cputimer_getres(void) -{ - return ((1000ULL * 1000 * 1000) * RT_KTIME_RESMUL) / rt_hw_get_gtimer_frq(); -} - -unsigned long rt_ktime_cputimer_getfrq(void) -{ - return rt_hw_get_gtimer_frq(); -} - -unsigned long rt_ktime_cputimer_getcnt(void) -{ - return rt_hw_get_cntpct_val() - _init_cnt; -} - -void rt_ktime_cputimer_init(void) -{ - _init_cnt = rt_hw_get_cntpct_val(); -} diff --git a/components/drivers/ktime/src/cputimer.c b/components/drivers/ktime/src/cputimer.c deleted file mode 100644 index ee19b236dc..0000000000 --- a/components/drivers/ktime/src/cputimer.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-07-10 xqyjlj The first version. - */ - -#include "ktime.h" - -rt_weak rt_uint64_t rt_ktime_cputimer_getres(void) -{ - return ((1000ULL * 1000 * 1000) * RT_KTIME_RESMUL) / RT_TICK_PER_SECOND; -} - -rt_weak unsigned long rt_ktime_cputimer_getfrq(void) -{ - return RT_TICK_PER_SECOND; -} - -rt_weak unsigned long rt_ktime_cputimer_getcnt(void) -{ - return rt_tick_get(); -} - -rt_weak void rt_ktime_cputimer_init(void) -{ - return; -} diff --git a/components/drivers/ktime/src/risc-v/virt64/cputimer.c b/components/drivers/ktime/src/risc-v/virt64/cputimer.c deleted file mode 100644 index 70c133aa2e..0000000000 --- a/components/drivers/ktime/src/risc-v/virt64/cputimer.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023-07-10 xqyjlj The first version. - */ - -#include "ktime.h" - -static volatile unsigned long _init_cnt = 0; - -rt_uint64_t rt_ktime_cputimer_getres(void) -{ - return ((1000ULL * 1000 * 1000) * RT_KTIME_RESMUL) / CPUTIME_TIMER_FREQ; -} - -unsigned long rt_ktime_cputimer_getfrq(void) -{ - return CPUTIME_TIMER_FREQ; -} - -unsigned long rt_ktime_cputimer_getcnt(void) -{ - unsigned long time_elapsed; - __asm__ __volatile__("rdtime %0" : "=r"(time_elapsed)); - return time_elapsed - _init_cnt; -} - -void rt_ktime_cputimer_init(void) -{ - __asm__ __volatile__("rdtime %0" : "=r"(_init_cnt)); -} diff --git a/components/drivers/pic/Kconfig b/components/drivers/pic/Kconfig index 448818fab7..e2c05685a6 100755 --- a/components/drivers/pic/Kconfig +++ b/components/drivers/pic/Kconfig @@ -8,7 +8,7 @@ menuconfig RT_USING_PIC config RT_USING_PIC_STATISTICS bool "Enable ISR execution time statistics" depends on RT_USING_PIC - depends on RT_USING_KTIME + depends on RT_USING_CLOCK_TIME depends on RT_USING_INTERRUPT_INFO default n diff --git a/components/drivers/pic/pic.c b/components/drivers/pic/pic.c index 423846c6e7..f3850ebd48 100644 --- a/components/drivers/pic/pic.c +++ b/components/drivers/pic/pic.c @@ -17,7 +17,7 @@ #include #ifdef RT_USING_PIC_STATISTICS -#include +#include #endif struct irq_traps @@ -553,7 +553,7 @@ rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq) RT_ASSERT(pirq->pic != RT_NULL); #ifdef RT_USING_PIC_STATISTICS - rt_ktime_boottime_get_ns(&ts); + rt_clock_boottime_get_ns(&ts); current_irq_begin = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec; #endif @@ -614,7 +614,7 @@ rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq) } #ifdef RT_USING_PIC_STATISTICS - rt_ktime_boottime_get_ns(&ts); + rt_clock_boottime_get_ns(&ts); irq_time_ns = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec - current_irq_begin; pirq->stat.sum_irq_time_ns += irq_time_ns; if (irq_time_ns < pirq->stat.min_irq_time_ns || pirq->stat.min_irq_time_ns == 0) diff --git a/components/drivers/rtc/dev_soft_rtc.c b/components/drivers/rtc/dev_soft_rtc.c index 3f85709e56..5f8489158f 100644 --- a/components/drivers/rtc/dev_soft_rtc.c +++ b/components/drivers/rtc/dev_soft_rtc.c @@ -13,8 +13,8 @@ #include #include -#ifdef RT_USING_KTIME -#include +#ifdef RT_USING_CLOCK_TIME +#include #endif #ifdef RT_USING_SOFT_RTC @@ -46,7 +46,7 @@ static struct rt_device soft_rtc_dev; static RT_DEFINE_SPINLOCK(_spinlock); /* RTC time baseline for calculation */ static struct timespec base_ts = { 0 }; -#ifdef RT_USING_KTIME +#ifdef RT_USING_CLOCK_TIME static struct timespec base_ktime_ts = { 0 }; #else static rt_tick_t base_tick; @@ -111,8 +111,8 @@ static void set_rtc_time(struct timespec *ts) rt_base_t level = rt_spin_lock_irqsave(&_spinlock); base_ts.tv_sec = ts->tv_sec; base_ts.tv_nsec = ts->tv_nsec; -#ifdef RT_USING_KTIME - rt_ktime_boottime_get_ns(&base_ktime_ts); +#ifdef RT_USING_CLOCK_TIME + rt_clock_boottime_get_ns(&base_ktime_ts); #else base_tick = rt_tick_get(); #endif @@ -140,9 +140,9 @@ static void get_rtc_time(struct timespec *ts) return; level = rt_spin_lock_irqsave(&_spinlock); -#ifdef RT_USING_KTIME +#ifdef RT_USING_CLOCK_TIME struct timespec current_ts; - rt_ktime_boottime_get_ns(¤t_ts); + rt_clock_boottime_get_ns(¤t_ts); ts->tv_sec = base_ts.tv_sec + (current_ts.tv_sec - base_ktime_ts.tv_sec); ts->tv_nsec = base_ts.tv_nsec + (current_ts.tv_nsec - base_ktime_ts.tv_nsec); @@ -256,8 +256,8 @@ static rt_err_t soft_rtc_control(rt_device_t dev, int cmd, void *args) ts = (struct timespec *)args; level = rt_spin_lock_irqsave(&_spinlock); ts->tv_sec = 0; -#ifdef RT_USING_KTIME - ts->tv_nsec = (rt_ktime_cputimer_getres() / RT_KTIME_RESMUL); +#ifdef RT_USING_CLOCK_TIME + ts->tv_nsec = (rt_clock_time_get_res_scaled() / RT_CLOCK_TIME_RESMUL); #else ts->tv_nsec = (1000UL * 1000 * 1000) / RT_TICK_PER_SECOND; #endif @@ -314,8 +314,8 @@ static int rt_soft_rtc_init(void) RT_TIMER_FLAG_SOFT_TIMER | RT_TIMER_FLAG_ONE_SHOT); #endif -#ifdef RT_USING_KTIME - rt_ktime_boottime_get_ns(&base_ktime_ts); +#ifdef RT_USING_CLOCK_TIME + rt_clock_boottime_get_ns(&base_ktime_ts); #else base_tick = rt_tick_get(); #endif diff --git a/components/libc/compilers/common/ctime.c b/components/libc/compilers/common/ctime.c index bcd19fc8aa..5e89097b27 100644 --- a/components/libc/compilers/common/ctime.c +++ b/components/libc/compilers/common/ctime.c @@ -42,8 +42,8 @@ #ifdef RT_USING_POSIX_DELAY #include #endif -#ifdef RT_USING_KTIME -#include +#ifdef RT_USING_CLOCK_TIME +#include #endif #define DBG_TAG "time" @@ -536,14 +536,14 @@ int settimeofday(const struct timeval *tv, const struct timezone *tz) } RTM_EXPORT(settimeofday); -#if defined(RT_USING_POSIX_DELAY) && defined(RT_USING_KTIME) +#if defined(RT_USING_POSIX_DELAY) && defined(RT_USING_CLOCK_TIME) int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) { struct timespec old_ts = {0}; struct timespec new_ts = {0}; - struct rt_ktime_hrtimer timer; + struct rt_clock_hrtimer timer; - rt_ktime_hrtimer_delay_init(&timer); + rt_clock_hrtimer_delay_init(&timer); if (rqtp == RT_NULL) { @@ -557,14 +557,14 @@ int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) return -1; } unsigned long ns = rqtp->tv_sec * NANOSECOND_PER_SECOND + rqtp->tv_nsec; - rt_ktime_boottime_get_ns(&old_ts); - rt_ktime_hrtimer_ndelay(&timer, ns); + rt_clock_boottime_get_ns(&old_ts); + rt_clock_hrtimer_ndelay(&timer, ns); if (rt_get_errno() == RT_EINTR) { if (rmtp) { rt_base_t rsec, rnsec; - rt_ktime_boottime_get_ns(&new_ts); + rt_clock_boottime_get_ns(&new_ts); rsec = old_ts.tv_sec + rqtp->tv_sec - new_ts.tv_sec; rnsec = old_ts.tv_nsec + rqtp->tv_nsec - new_ts.tv_nsec; @@ -580,18 +580,18 @@ int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) } } - rt_ktime_hrtimer_delay_detach(&timer); + rt_clock_hrtimer_delay_detach(&timer); rt_set_errno(EINTR); return -1; } - rt_ktime_hrtimer_delay_detach(&timer); + rt_clock_hrtimer_delay_detach(&timer); return 0; } RTM_EXPORT(nanosleep); -#endif /* RT_USING_POSIX_DELAY && RT_USING_KTIME */ +#endif /* RT_USING_POSIX_DELAY && RT_USING_CLOCK_TIME */ -#if defined(RT_USING_POSIX_CLOCK) && defined(RT_USING_KTIME) +#if defined(RT_USING_POSIX_CLOCK) && defined(RT_USING_CLOCK_TIME) int clock_getres(clockid_t clockid, struct timespec *res) { @@ -609,14 +609,14 @@ int clock_getres(clockid_t clockid, struct timespec *res) return _control_rtc(RT_DEVICE_CTRL_RTC_GET_TIMERES, res); #endif /* RT_USING_RTC */ - case CLOCK_MONOTONIC: // use cputimer + case CLOCK_MONOTONIC: // use clock_time counter case CLOCK_MONOTONIC_COARSE: case CLOCK_MONOTONIC_RAW: case CLOCK_BOOTTIME: case CLOCK_PROCESS_CPUTIME_ID: case CLOCK_THREAD_CPUTIME_ID: res->tv_sec = 0; - res->tv_nsec = (rt_ktime_cputimer_getres() / RT_KTIME_RESMUL); + res->tv_nsec = (rt_clock_time_get_res_scaled() / RT_CLOCK_TIME_RESMUL); return 0; default: @@ -646,11 +646,11 @@ int clock_gettime(clockid_t clockid, struct timespec *tp) case CLOCK_MONOTONIC_COARSE: case CLOCK_MONOTONIC_RAW: case CLOCK_BOOTTIME: - return rt_ktime_boottime_get_ns(tp); + return rt_clock_boottime_get_ns(tp); case CLOCK_PROCESS_CPUTIME_ID: case CLOCK_THREAD_CPUTIME_ID: - return rt_ktime_boottime_get_ns(tp); // TODO not yet implemented + return rt_clock_boottime_get_ns(tp); // TODO not yet implemented default: tp->tv_sec = 0; @@ -690,7 +690,7 @@ int clock_nanosleep(clockid_t clockid, int flags, const struct timespec *rqtp, s case CLOCK_MONOTONIC: // use boottime case CLOCK_PROCESS_CPUTIME_ID: if (flags & TIMER_ABSTIME) - err = rt_ktime_boottime_get_ns(&ts); + err = rt_clock_boottime_get_ns(&ts); break; default: @@ -790,9 +790,9 @@ int rt_timespec_to_tick(const struct timespec *time) } RTM_EXPORT(rt_timespec_to_tick); -#endif /* RT_USING_POSIX_CLOCK && RT_USING_KTIME */ +#endif /* RT_USING_POSIX_CLOCK && RT_USING_CLOCK_TIME */ -#if defined(RT_USING_POSIX_TIMER) && defined(RT_USING_KTIME) +#if defined(RT_USING_POSIX_TIMER) && defined(RT_USING_CLOCK_TIME) #include @@ -801,7 +801,7 @@ RTM_EXPORT(rt_timespec_to_tick); struct timer_obj { - struct rt_ktime_hrtimer hrtimer; + struct rt_clock_hrtimer hrtimer; void (*sigev_notify_func)(union sigval val); union sigval val; struct timespec interval; /* Reload value */ @@ -896,11 +896,11 @@ static void rtthread_timer_wrapper(void *timerobj) timer->status = NOT_ACTIVE; } - timer->reload = ((timer->interval.tv_sec * NANOSECOND_PER_SECOND + timer->interval.tv_nsec) * RT_KTIME_RESMUL) / - rt_ktime_cputimer_getres(); + timer->reload = ((timer->interval.tv_sec * NANOSECOND_PER_SECOND + timer->interval.tv_nsec) * RT_CLOCK_TIME_RESMUL) / + rt_clock_time_get_res_scaled(); if (timer->reload) { - rt_ktime_hrtimer_start(&timer->hrtimer, timer->reload); + rt_clock_hrtimer_start(&timer->hrtimer, timer->reload); } #ifdef RT_USING_SMART /* this field is named as tid in musl */ @@ -1021,7 +1021,7 @@ int timer_create(clockid_t clockid, struct sigevent *evp, timer_t *timerid) timer->status = NOT_ACTIVE; timer->clockid = clockid; - rt_ktime_hrtimer_init(&timer->hrtimer, timername, RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_HARD_TIMER, + rt_clock_hrtimer_init(&timer->hrtimer, timername, RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_HARD_TIMER, rtthread_timer_wrapper, timer); _timerid = resource_id_get(&id_timer); @@ -1031,7 +1031,7 @@ int timer_create(clockid_t clockid, struct sigevent *evp, timer_t *timerid) rt_free(param); #endif /* RT_USING_SMART */ - rt_ktime_hrtimer_detach(&timer->hrtimer); + rt_clock_hrtimer_detach(&timer->hrtimer); rt_free(timer); rt_set_errno(ENOMEM); return -1; @@ -1083,9 +1083,9 @@ int timer_delete(timer_t timerid) if (timer->status == ACTIVE) { timer->status = NOT_ACTIVE; - rt_ktime_hrtimer_stop(&timer->hrtimer); + rt_clock_hrtimer_stop(&timer->hrtimer); } - rt_ktime_hrtimer_detach(&timer->hrtimer); + rt_clock_hrtimer_detach(&timer->hrtimer); #ifdef RT_USING_SMART if (timer->pid) @@ -1135,8 +1135,8 @@ int timer_gettime(timer_t timerid, struct itimerspec *its) if (timer->status == ACTIVE) { unsigned long remain_cnt; - rt_ktime_hrtimer_control(&timer->hrtimer, RT_TIMER_CTRL_GET_REMAIN_TIME, &remain_cnt); - nanoseconds = ((remain_cnt - rt_ktime_cputimer_getcnt()) * rt_ktime_cputimer_getres()) / RT_KTIME_RESMUL; + rt_clock_hrtimer_control(&timer->hrtimer, RT_TIMER_CTRL_GET_REMAIN_TIME, &remain_cnt); + nanoseconds = ((remain_cnt - rt_clock_time_get_counter()) * rt_clock_time_get_res_scaled()) / RT_CLOCK_TIME_RESMUL; seconds = nanoseconds / NANOSECOND_PER_SECOND; nanoseconds = nanoseconds % NANOSECOND_PER_SECOND; its->it_value.tv_sec = (rt_int32_t)seconds; @@ -1191,7 +1191,7 @@ int timer_settime(timer_t timerid, int flags, const struct itimerspec *value, { if (timer->status == ACTIVE) { - rt_ktime_hrtimer_stop(&timer->hrtimer); + rt_clock_hrtimer_stop(&timer->hrtimer); } timer->status = NOT_ACTIVE; @@ -1213,7 +1213,7 @@ int timer_settime(timer_t timerid, int flags, const struct itimerspec *value, case CLOCK_PROCESS_CPUTIME_ID: case CLOCK_THREAD_CPUTIME_ID: if (flags & TIMER_ABSTIME) - err = rt_ktime_boottime_get_ns(&ts); + err = rt_clock_boottime_get_ns(&ts); break; default: rt_set_errno(EINVAL); @@ -1228,8 +1228,8 @@ int timer_settime(timer_t timerid, int flags, const struct itimerspec *value, if (ns <= 0) return 0; - unsigned long res = rt_ktime_cputimer_getres(); - timer->reload = (ns * RT_KTIME_RESMUL) / res; + unsigned long res = rt_clock_time_get_res_scaled(); + timer->reload = (ns * RT_CLOCK_TIME_RESMUL) / res; timer->interval.tv_sec = value->it_interval.tv_sec; timer->interval.tv_nsec = value->it_interval.tv_nsec; timer->value.tv_sec = value->it_value.tv_sec; @@ -1237,18 +1237,18 @@ int timer_settime(timer_t timerid, int flags, const struct itimerspec *value, if (timer->status == ACTIVE) { - rt_ktime_hrtimer_stop(&timer->hrtimer); + rt_clock_hrtimer_stop(&timer->hrtimer); } timer->status = ACTIVE; if ((value->it_interval.tv_sec == 0) && (value->it_interval.tv_nsec == 0)) - rt_ktime_hrtimer_control(&timer->hrtimer, RT_TIMER_CTRL_SET_ONESHOT, RT_NULL); + rt_clock_hrtimer_control(&timer->hrtimer, RT_TIMER_CTRL_SET_ONESHOT, RT_NULL); else - rt_ktime_hrtimer_control(&timer->hrtimer, RT_TIMER_CTRL_SET_PERIODIC, RT_NULL); + rt_clock_hrtimer_control(&timer->hrtimer, RT_TIMER_CTRL_SET_PERIODIC, RT_NULL); - rt_ktime_hrtimer_start(&timer->hrtimer, timer->reload); + rt_clock_hrtimer_start(&timer->hrtimer, timer->reload); return 0; } RTM_EXPORT(timer_settime); -#endif /* RT_USING_POSIX_TIMER && RT_USING_KTIME */ +#endif /* RT_USING_POSIX_TIMER && RT_USING_CLOCK_TIME */ diff --git a/components/libc/posix/Kconfig b/components/libc/posix/Kconfig index 8a4a3843cb..16f2eee840 100644 --- a/components/libc/posix/Kconfig +++ b/components/libc/posix/Kconfig @@ -79,7 +79,7 @@ if RT_USING_POSIX_FS endif config RT_USING_POSIX_DELAY - select RT_USING_KTIME + select RT_USING_CLOCK_TIME bool "Enable delay APIs, sleep()/usleep()/msleep() etc" default n @@ -89,7 +89,7 @@ config RT_USING_POSIX_CLOCK default n config RT_USING_POSIX_TIMER - select RT_USING_KTIME + select RT_USING_CLOCK_TIME select RT_USING_RESOURCE_ID bool "Enable timer APIs, timer_create()/timer_gettime() etc" default n diff --git a/components/lwp/arch/aarch64/common/vdso_data.c b/components/lwp/arch/aarch64/common/vdso_data.c index 13c055ec56..b33094db9d 100644 --- a/components/lwp/arch/aarch64/common/vdso_data.c +++ b/components/lwp/arch/aarch64/common/vdso_data.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #include #include @@ -23,11 +23,11 @@ void rt_vdso_update_glob_time(void) rt_vdso_write_begin(vdata); vdso_ts = &vdata[CS_HRES_COARSE].basetime[CLOCK_REALTIME]; - rt_ktime_boottime_get_ns(vdso_ts); + rt_clock_boottime_get_ns(vdso_ts); vdso_ts->tv_sec = initdata + vdso_ts->tv_sec; vdso_ts = &vdata[CS_HRES_COARSE].basetime[CLOCK_MONOTONIC]; - rt_ktime_boottime_get_ns(vdso_ts); + rt_clock_boottime_get_ns(vdso_ts); vdata->cycle_last = rt_hw_get_cntpct_val(); rt_vdso_write_end(vdata); diff --git a/components/lwp/arch/risc-v/common/vdso_data.c b/components/lwp/arch/risc-v/common/vdso_data.c index e31305af8f..b457c1f7ee 100644 --- a/components/lwp/arch/risc-v/common/vdso_data.c +++ b/components/lwp/arch/risc-v/common/vdso_data.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include #include @@ -23,11 +23,11 @@ void rt_vdso_update_glob_time(void) rt_vdso_write_begin(vdata); vdso_ts = &vdata[CS_HRES_COARSE].basetime[CLOCK_REALTIME]; - rt_ktime_boottime_get_ns(vdso_ts); + rt_clock_boottime_get_ns(vdso_ts); vdso_ts->tv_sec = initdata + vdso_ts->tv_sec; vdso_ts = &vdata[CS_HRES_COARSE].basetime[CLOCK_MONOTONIC]; - rt_ktime_boottime_get_ns(vdso_ts); + rt_clock_boottime_get_ns(vdso_ts); vdata->cycle_last = rdtime(); rt_vdso_write_end(vdata); diff --git a/documentation/6.components/device-driver/INDEX.md b/documentation/6.components/device-driver/INDEX.md index b8600c9e79..b42844dbc9 100644 --- a/documentation/6.components/device-driver/INDEX.md +++ b/documentation/6.components/device-driver/INDEX.md @@ -8,7 +8,7 @@ - @subpage page_device_spi - @subpage page_device_pwm - @subpage page_device_rtc -- @subpage page_device_hwtimer +- @subpage page_device_clock_time - @subpage page_device_watchdog - @subpage page_device_wlan - @subpage page_device_sensor diff --git a/documentation/6.components/device-driver/clock_time/README.md b/documentation/6.components/device-driver/clock_time/README.md new file mode 100644 index 0000000000..de70570812 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/README.md @@ -0,0 +1,89 @@ +@page page_device_clock_time Clock Time Subsystem + +# Overview + +The clock_time subsystem provides a unified, high-resolution time base and +programmable event scheduling for RT-Thread. It decouples a monotonic counter +(clock source) from deadline delivery (clock event), so platforms can mix +hardware counters and timers while the kernel and libc see consistent behavior. + +# Architecture + +![Clock time architecture](figures/clock_time_arch.svg) + +## Layering and Responsibilities + +- Upper layers: + - POSIX/libc time APIs (clock_gettime, nanosleep) use boottime and hrtimer APIs. + - Soft RTC uses boottime as its monotonic time base for timekeeping. + - Device drivers (input event timestamps, vDSO, PIC statistics) use boottime + for timestamping. +- clock_time subsystem: core APIs, clock source/event devices, the hrtimer + scheduler, boottime helpers, and the clock_timer adapter. +- Lower layers: BSP drivers provide hardware counters and timers, which are + wrapped as clock_time devices or clock_timer devices. + +## Internal Components + +- Core API (clock_time_core.c) + - Registers clock_time devices, manages default source/event selection, and + provides counter <-> nanosecond conversion with fixed-point scaling. +- Clock source device (rt_clock_time_device + RT_CLOCK_TIME_CAP_SOURCE) + - Supplies a free-running counter and frequency for monotonic time reads. +- Clock event device (rt_clock_time_device + RT_CLOCK_TIME_CAP_EVENT) + - Programs the next deadline and calls rt_clock_time_event_isr() on expiry. +- Clock hrtimer (clock_hrtimer.c) + - Schedules high-resolution timeouts, programs the next event, and dispatches + callbacks. Falls back to software timer when no hardware event is available. +- Boottime helpers (clock_boottime.c) + - Converts the monotonic counter into timeval/timespec/seconds for upper + layers. +- Clock timer adapter (clock_timer.c) + - Exposes a unified hardware timer device (rt_clock_timer) and can register + itself as a clock_time event device. +- Architecture sources (arch/* and clock_time_arm_arch.c) + - Provide fast CPU counters or architectural timers and register them as the + default clock source when available. + +## Data Flow + +- Read path + - Clock source counter -> scaled resolution -> nanoseconds -> boottime or + clock_gettime. +- Timeout path + - HRTimer queue -> next expiry -> set_timeout on event device -> event ISR -> + hrtimer processing -> callbacks. + +# Configuration + +Enable the subsystem in menuconfig: + +``` +RT-Thread Components -> + Device Drivers -> + [*] Clock time subsystem (RT_USING_CLOCK_TIME) +``` + +Optional settings: + +- CLOCK_TIMER_FREQ (RISC-V): base counter frequency used by the clock source. +- RT_CLOCK_TIME_ARM_ARCH: enable ARM architected timer integration (DM/OFW). + +# BSP Integration Checklist + +- Provide a clock source: + - Register a rt_clock_time_device with CAP_SOURCE, or use the provided + architecture source (AArch64/RISC-V) via rt_clock_time_source_init(). +- Provide a clock event: + - Register a rt_clock_time_device with CAP_EVENT and call + rt_clock_time_event_isr() in its interrupt handler. + - Or register a rt_clock_timer device; it can become the default event + device automatically. +- Keep event ISRs short; heavy work should run in thread context if needed. + +# Detailed Documents + +- @subpage page_device_clock_time_core +- @subpage page_device_clock_hrtimer +- @subpage page_device_clock_boottime +- @subpage page_device_clock_timer diff --git a/documentation/6.components/device-driver/clock_time/README_zh.md b/documentation/6.components/device-driver/clock_time/README_zh.md new file mode 100644 index 0000000000..d4433f18c2 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/README_zh.md @@ -0,0 +1,78 @@ +# Clock Time 子系统概述 + +clock_time 子系统为 RT-Thread 提供统一的高精度时间基准与事件调度能力。 +它将单调计数（时钟源）与超时事件（时钟事件）解耦，使平台可以组合不同的 +硬件计数器与定时器，同时为内核与 libc 提供一致的时间行为。 + +# 软件架构 + +![Clock time architecture](figures/clock_time_arch.svg) + +## 分层关系与职责 + +- 上层： + - POSIX/libc 时间接口（clock_gettime、nanosleep）使用 boottime 和 hrtimer API。 + - 软 RTC 使用 boottime 作为单调时间基准进行计时。 + - 设备驱动（输入事件时间戳、vDSO、中断控制器统计）使用 boottime 获取时间戳。 +- clock_time 子系统：核心 API、时钟源/事件设备、高精度定时器调度器、 + boottime 辅助函数、clock_timer 适配层。 +- 下层：BSP 驱动提供硬件计数器与定时器，并封装为 clock_time 设备或 + clock_timer 设备。 + +## 内部组成 + +- Core API（clock_time_core.c） + - 负责设备注册、默认源/事件选择，以及计数 <-> 纳秒的缩放换算。 +- 时钟源设备（rt_clock_time_device + RT_CLOCK_TIME_CAP_SOURCE） + - 提供自由运行计数器与频率，作为单调时间基准。 +- 时钟事件设备（rt_clock_time_device + RT_CLOCK_TIME_CAP_EVENT） + - 负责下一次超时编程，并在到期时调用 rt_clock_time_event_isr()。 +- 高精度定时器（clock_hrtimer.c） + - 维护超时队列、设置下一次事件并分发回调。没有硬件事件时退化为软件定时器。 +- Boottime 辅助（clock_boottime.c） + - 将单调计数转换为 timeval/timespec/秒，供上层使用。 +- Clock timer 适配层（clock_timer.c） + - 提供统一的硬件定时器设备（rt_clock_timer），并可注册为事件设备。 +- 架构源（arch/* 与 clock_time_arm_arch.c） + - 提供 CPU 计数器或架构定时器，并在可用时设置为默认时钟源。 + +## 数据流 + +- 读取路径 + - 时钟源计数 -> 缩放分辨率 -> 纳秒 -> boottime 或 clock_gettime。 +- 超时路径 + - hrtimer 队列 -> 下一到期 -> 事件设备 set_timeout -> 事件中断 -> + hrtimer 处理 -> 回调分发。 + +# 配置选项 + +在 menuconfig 中启用： + +``` +RT-Thread Components -> + Device Drivers -> + [*] Clock time subsystem (RT_USING_CLOCK_TIME) +``` + +可选配置： + +- CLOCK_TIMER_FREQ（RISC-V）：时钟源使用的基础计数频率。 +- RT_CLOCK_TIME_ARM_ARCH：启用 ARM 架构定时器集成（DM/OFW）。 + +# BSP 集成要点 + +- 提供时钟源： + - 注册带 CAP_SOURCE 的 rt_clock_time_device，或使用 + rt_clock_time_source_init() 提供的架构源。 +- 提供时钟事件： + - 注册带 CAP_EVENT 的 rt_clock_time_device，并在中断中调用 + rt_clock_time_event_isr()。 + - 或直接注册 rt_clock_timer 设备，自动成为默认事件设备。 +- 事件中断应保持简短，复杂处理建议转到线程上下文。 + +# 详细文档 + +- clock_time_core.md +- clock_hrtimer.md +- clock_boottime.md +- clock_timer.md diff --git a/documentation/6.components/device-driver/clock_time/clock_boottime.md b/documentation/6.components/device-driver/clock_time/clock_boottime.md new file mode 100644 index 0000000000..205c861311 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_boottime.md @@ -0,0 +1,87 @@ +@page page_device_clock_boottime Clock Boottime Helpers + +# Overview + +Boottime helpers convert the clock_time monotonic counter into standard time +formats. The resulting values represent time since boot and do not depend on +RTC or wall-clock settings. + +# API + +```c +rt_err_t rt_clock_boottime_get_us(struct timeval *tv); +rt_err_t rt_clock_boottime_get_s(time_t *t); +rt_err_t rt_clock_boottime_get_ns(struct timespec *ts); +``` + +All functions return RT_EOK on success or -RT_ERROR if the clock source is +unavailable. The returned values are monotonic and suitable for measuring +elapsed time. + +## rt_clock_boottime_get_us + +```c +rt_err_t rt_clock_boottime_get_us(struct timeval *tv); +``` + +- Purpose: get time since boot as seconds + microseconds. +- Parameters: `tv` must be a valid pointer to `struct timeval`. +- Return values: + - RT_EOK: data written to `tv`. + - -RT_ERROR: no valid clock_time source or conversion failed. +- Notes: + - `tv_usec` is derived from the clock_time resolution and may not be exact + microseconds if the underlying counter does not align to 1 us. + +## rt_clock_boottime_get_s + +```c +rt_err_t rt_clock_boottime_get_s(time_t *t); +``` + +- Purpose: get time since boot in whole seconds. +- Parameters: `t` must be a valid pointer to `time_t`. +- Return values: + - RT_EOK: `*t` updated. + - -RT_ERROR: no valid clock_time source or conversion failed. +- Notes: + - Sub-second precision is discarded; use `rt_clock_boottime_get_us()` or + `rt_clock_boottime_get_ns()` if needed. + +## rt_clock_boottime_get_ns + +```c +rt_err_t rt_clock_boottime_get_ns(struct timespec *ts); +``` + +- Purpose: get time since boot as seconds + nanoseconds. +- Parameters: `ts` must be a valid pointer to `struct timespec`. +- Return values: + - RT_EOK: data written to `ts`. + - -RT_ERROR: no valid clock_time source or conversion failed. +- Notes: + - `tv_nsec` reflects the clock_time resolution; it may not be 1 ns granularity + if the counter frequency is lower. + +# Example + +```c +#include + +static void demo_boottime(void) +{ + struct timespec ts; + + if (rt_clock_boottime_get_ns(&ts) == RT_EOK) + { + rt_kprintf("boottime: %ld.%09ld\n", (long)ts.tv_sec, ts.tv_nsec); + } +} +``` + +# Notes + +- The boottime helpers are used by the soft RTC implementation to build a + stable base time. +- If no clock_time source is registered, the subsystem falls back to the tick + counter and the resolution matches RT_TICK_PER_SECOND. diff --git a/documentation/6.components/device-driver/clock_time/clock_boottime_zh.md b/documentation/6.components/device-driver/clock_time/clock_boottime_zh.md new file mode 100644 index 0000000000..d0a577bf2c --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_boottime_zh.md @@ -0,0 +1,78 @@ +# Clock Boottime 辅助 + +boottime 辅助函数将 clock_time 的单调计数转换为常见时间格式，返回值表示 +“系统启动以来的时间”，不受 RTC 或墙上时间设置影响。 + +# API + +```c +rt_err_t rt_clock_boottime_get_us(struct timeval *tv); +rt_err_t rt_clock_boottime_get_s(time_t *t); +rt_err_t rt_clock_boottime_get_ns(struct timespec *ts); +``` + +成功返回 RT_EOK；若时钟源不可用则返回 -RT_ERROR。返回值单调递增，适合用于 +测量耗时。 + +## rt_clock_boottime_get_us + +```c +rt_err_t rt_clock_boottime_get_us(struct timeval *tv); +``` + +- 作用：获取启动以来的时间，格式为秒 + 微秒。 +- 参数：`tv` 需为有效的 `struct timeval` 指针。 +- 返回值： + - RT_EOK：成功写入 `tv`。 + - -RT_ERROR：无有效时钟源或换算失败。 +- 说明： + - `tv_usec` 由 clock_time 分辨率换算而来，不一定严格为 1 us 精度。 + +## rt_clock_boottime_get_s + +```c +rt_err_t rt_clock_boottime_get_s(time_t *t); +``` + +- 作用：获取启动以来的整秒数。 +- 参数：`t` 需为有效的 `time_t` 指针。 +- 返回值： + - RT_EOK：成功写入 `*t`。 + - -RT_ERROR：无有效时钟源或换算失败。 +- 说明： + - 该接口仅返回秒，若需亚秒精度请使用其它接口。 + +## rt_clock_boottime_get_ns + +```c +rt_err_t rt_clock_boottime_get_ns(struct timespec *ts); +``` + +- 作用：获取启动以来的时间，格式为秒 + 纳秒。 +- 参数：`ts` 需为有效的 `struct timespec` 指针。 +- 返回值： + - RT_EOK：成功写入 `ts`。 + - -RT_ERROR：无有效时钟源或换算失败。 +- 说明： + - `tv_nsec` 的精度取决于计数频率，不一定达到 1 ns。 + +# 示例 + +```c +#include + +static void demo_boottime(void) +{ + struct timespec ts; + + if (rt_clock_boottime_get_ns(&ts) == RT_EOK) + { + rt_kprintf("boottime: %ld.%09ld\n", (long)ts.tv_sec, ts.tv_nsec); + } +} +``` + +# 注意事项 + +- 软 RTC 会使用 boottime 作为稳定基准。 +- 未注册时钟源时，系统退化为 tick 计数，分辨率由 RT_TICK_PER_SECOND 决定。 diff --git a/documentation/6.components/device-driver/clock_time/clock_hrtimer.md b/documentation/6.components/device-driver/clock_time/clock_hrtimer.md new file mode 100644 index 0000000000..ff64ab56d4 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_hrtimer.md @@ -0,0 +1,223 @@ +@page page_device_clock_hrtimer Clock HRTimer + +# Overview + +The clock hrtimer layer provides high-resolution timeout scheduling on top of +clock_time. It keeps a sorted timeout list, programs the next deadline, and +runs callbacks when the deadline expires. + +# Key Concepts + +- Time base: delay counts are expressed in the clock source counter units. +- Event programming: the next expiry is converted to event units and sent to + the clock event device. +- Fallback: if no hardware event exists, a software timer triggers processing. + +# API + +```c +void rt_clock_hrtimer_init(rt_clock_hrtimer_t timer, + const char *name, + rt_uint8_t flag, + void (*timeout)(void *parameter), + void *parameter); +rt_err_t rt_clock_hrtimer_start(rt_clock_hrtimer_t timer, unsigned long cnt); +rt_err_t rt_clock_hrtimer_stop(rt_clock_hrtimer_t timer); +rt_err_t rt_clock_hrtimer_control(rt_clock_hrtimer_t timer, int cmd, void *arg); +rt_err_t rt_clock_hrtimer_detach(rt_clock_hrtimer_t timer); + +void rt_clock_hrtimer_delay_init(struct rt_clock_hrtimer *timer); +void rt_clock_hrtimer_delay_detach(struct rt_clock_hrtimer *timer); +rt_err_t rt_clock_hrtimer_sleep(struct rt_clock_hrtimer *timer, unsigned long cnt); +rt_err_t rt_clock_hrtimer_ndelay(struct rt_clock_hrtimer *timer, unsigned long ns); +rt_err_t rt_clock_hrtimer_udelay(struct rt_clock_hrtimer *timer, unsigned long us); +rt_err_t rt_clock_hrtimer_mdelay(struct rt_clock_hrtimer *timer, unsigned long ms); +``` + +Flags reuse RT_TIMER_FLAG_* definitions (one-shot/periodic/hard timer). `cnt` +is a counter delta based on the default clock source. + +## rt_clock_hrtimer_init + +```c +void rt_clock_hrtimer_init(rt_clock_hrtimer_t timer, + const char *name, + rt_uint8_t flag, + void (*timeout)(void *parameter), + void *parameter); +``` + +- Purpose: initialize a high-resolution timer object. +- Parameters: + - `timer`: the hrtimer object to initialize. + - `name`: timer name (truncated to RT_NAME_MAX-1). + - `flag`: RT_TIMER_FLAG_* (one-shot/periodic/hard timer). + - `timeout`: callback function on expiry. + - `parameter`: user parameter passed to the callback. +- Behavior: + - Clears internal state, initializes list node and completion. + - Does not start the timer; call `rt_clock_hrtimer_start()` to arm it. +- Context: thread context. + +## rt_clock_hrtimer_start + +```c +rt_err_t rt_clock_hrtimer_start(rt_clock_hrtimer_t timer, unsigned long cnt); +``` + +- Purpose: arm a timer to expire after `cnt` counter ticks. +- Parameters: + - `cnt`: relative delay in clock source counter units. +- Return values: + - RT_EOK: timer armed. + - -RT_ERROR: timer already active or invalid `cnt`. +- Notes: + - `cnt` must be less than half of the maximum counter range to avoid wrap + ambiguity. + - Starting a timer programs the next clock event if this timer becomes the + earliest deadline. + +## rt_clock_hrtimer_stop + +```c +rt_err_t rt_clock_hrtimer_stop(rt_clock_hrtimer_t timer); +``` + +- Purpose: cancel an active timer. +- Return values: + - RT_EOK: timer stopped. + - -RT_ERROR: timer was not active. +- Notes: stopping a timer may reprogram the next event. + +## rt_clock_hrtimer_control + +```c +rt_err_t rt_clock_hrtimer_control(rt_clock_hrtimer_t timer, int cmd, void *arg); +``` + +- Purpose: query or modify a timer after initialization. +- Common commands (same as RT-Thread timers): + - RT_TIMER_CTRL_GET_TIME: get `delay_cnt` into `*(unsigned long *)arg`. + - RT_TIMER_CTRL_SET_TIME: set `delay_cnt` from `*(unsigned long *)arg`. + - RT_TIMER_CTRL_SET_ONESHOT / RT_TIMER_CTRL_SET_PERIODIC: set mode. + - RT_TIMER_CTRL_GET_STATE: return activated/deactivated state. + - RT_TIMER_CTRL_GET_REMAIN_TIME: get absolute timeout counter. + - RT_TIMER_CTRL_GET_FUNC / RT_TIMER_CTRL_SET_FUNC: get/set callback. + - RT_TIMER_CTRL_GET_PARM / RT_TIMER_CTRL_SET_PARM: get/set parameter. +- Notes: + - Changing time or mode while active updates internal deadline but does not + implicitly restart a stopped timer. + +## rt_clock_hrtimer_detach + +```c +rt_err_t rt_clock_hrtimer_detach(rt_clock_hrtimer_t timer); +``` + +- Purpose: detach a timer and wake any waiters. +- Behavior: + - Marks the timer inactive and wakes `rt_clock_hrtimer_sleep()` waiters with + an error code. + - Removes the timer from the list if needed. +- Use case: cleanup when a timer is no longer valid. + +## rt_clock_hrtimer_delay_init + +```c +void rt_clock_hrtimer_delay_init(struct rt_clock_hrtimer *timer); +``` + +- Purpose: initialize a one-shot hrtimer for blocking delays. +- Behavior: sets a built-in timeout callback that signals a completion. + +## rt_clock_hrtimer_delay_detach + +```c +void rt_clock_hrtimer_delay_detach(struct rt_clock_hrtimer *timer); +``` + +- Purpose: detach a delay timer created by `rt_clock_hrtimer_delay_init()`. +- Notes: safe to call even if the timer has already expired. + +## rt_clock_hrtimer_sleep + +```c +rt_err_t rt_clock_hrtimer_sleep(struct rt_clock_hrtimer *timer, unsigned long cnt); +``` + +- Purpose: block the current thread until the delay expires. +- Parameters: `timer` must be initialized (typically by delay_init). +- Return values: + - RT_EOK: timeout expired normally. + - -RT_EINTR: interrupted by signal or detach. + - -RT_EINVAL: `cnt` is zero. +- Context: thread context only. + +## rt_clock_hrtimer_ndelay / udelay / mdelay + +```c +rt_err_t rt_clock_hrtimer_ndelay(struct rt_clock_hrtimer *timer, unsigned long ns); +rt_err_t rt_clock_hrtimer_udelay(struct rt_clock_hrtimer *timer, unsigned long us); +rt_err_t rt_clock_hrtimer_mdelay(struct rt_clock_hrtimer *timer, unsigned long ms); +``` + +- Purpose: sleep for a duration expressed in nanoseconds, microseconds, or + milliseconds. +- Behavior: + - Converts the time into counter units using the current clock_time + resolution and calls `rt_clock_hrtimer_sleep()`. +- Notes: + - The actual delay is limited by the clock source resolution and event + programming granularity. + +# Typical Flow + +1. Initialize a hrtimer with a callback. +2. Convert a time interval to counter units, or use the ndelay/udelay/mdelay + helpers. +3. Start the timer; the subsystem will program the next event. +4. When the event ISR fires, rt_clock_time_event_isr() runs hrtimer processing + and dispatches callbacks. + +# Example: One-shot Timeout + +```c +#include + +static struct rt_clock_hrtimer demo_timer; + +static void demo_timeout(void *parameter) +{ + RT_UNUSED(parameter); + rt_kprintf("hrtimer timeout\n"); +} + +static void demo_hrtimer_start(void) +{ + rt_uint64_t ns = 5ULL * 1000 * 1000; /* 5 ms */ + unsigned long cnt = (unsigned long)rt_clock_time_ns_to_counter(ns); + + rt_clock_hrtimer_init(&demo_timer, "demo", RT_TIMER_FLAG_ONE_SHOT, + demo_timeout, RT_NULL); + rt_clock_hrtimer_start(&demo_timer, cnt); +} +``` + +# Example: Sleep Helper + +```c +static void demo_hrtimer_sleep(void) +{ + struct rt_clock_hrtimer timer; + + rt_clock_hrtimer_delay_init(&timer); + rt_clock_hrtimer_mdelay(&timer, 10); + rt_clock_hrtimer_delay_detach(&timer); +} +``` + +# Notes + +- Callbacks may run in interrupt context when using a hardware event device. +- rt_clock_hrtimer_sleep() waits on a completion and may return -RT_EINTR if + interrupted. diff --git a/documentation/6.components/device-driver/clock_time/clock_hrtimer_zh.md b/documentation/6.components/device-driver/clock_time/clock_hrtimer_zh.md new file mode 100644 index 0000000000..50462072d1 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_hrtimer_zh.md @@ -0,0 +1,208 @@ +# Clock HRTimer + +clock hrtimer 在 clock_time 之上提供高精度超时调度。它维护按到期时间排序的 +队列，编程下一次事件，并在到期时执行回调。 + +# 关键点 + +- 时间基准：延时 cnt 基于默认时钟源的计数单位。 +- 事件编程：将下一次到期换算为事件单位后调用事件设备。 +- 退化机制：缺少硬件事件时自动使用软件定时器触发处理。 + +# API + +```c +void rt_clock_hrtimer_init(rt_clock_hrtimer_t timer, + const char *name, + rt_uint8_t flag, + void (*timeout)(void *parameter), + void *parameter); +rt_err_t rt_clock_hrtimer_start(rt_clock_hrtimer_t timer, unsigned long cnt); +rt_err_t rt_clock_hrtimer_stop(rt_clock_hrtimer_t timer); +rt_err_t rt_clock_hrtimer_control(rt_clock_hrtimer_t timer, int cmd, void *arg); +rt_err_t rt_clock_hrtimer_detach(rt_clock_hrtimer_t timer); + +void rt_clock_hrtimer_delay_init(struct rt_clock_hrtimer *timer); +void rt_clock_hrtimer_delay_detach(struct rt_clock_hrtimer *timer); +rt_err_t rt_clock_hrtimer_sleep(struct rt_clock_hrtimer *timer, unsigned long cnt); +rt_err_t rt_clock_hrtimer_ndelay(struct rt_clock_hrtimer *timer, unsigned long ns); +rt_err_t rt_clock_hrtimer_udelay(struct rt_clock_hrtimer *timer, unsigned long us); +rt_err_t rt_clock_hrtimer_mdelay(struct rt_clock_hrtimer *timer, unsigned long ms); +``` + +flag 复用 RT_TIMER_FLAG_* 定义（单次/周期/硬定时器）。cnt 为默认时钟源计数 +单位。 + +## rt_clock_hrtimer_init + +```c +void rt_clock_hrtimer_init(rt_clock_hrtimer_t timer, + const char *name, + rt_uint8_t flag, + void (*timeout)(void *parameter), + void *parameter); +``` + +- 作用：初始化一个高精度定时器对象。 +- 参数： + - `timer`：待初始化的 hrtimer 对象。 + - `name`：定时器名称（超过 RT_NAME_MAX-1 会截断）。 + - `flag`：RT_TIMER_FLAG_* 标志（单次/周期/硬定时器）。 + - `timeout`：超时回调函数。 + - `parameter`：回调参数。 +- 行为： + - 清理内部状态，初始化链表节点与 completion。 + - 仅初始化，不会启动，需要调用 `rt_clock_hrtimer_start()`。 +- 上下文：线程上下文。 + +## rt_clock_hrtimer_start + +```c +rt_err_t rt_clock_hrtimer_start(rt_clock_hrtimer_t timer, unsigned long cnt); +``` + +- 作用：启动定时器，在 `cnt` 个计数后到期。 +- 参数： + - `cnt`：相对延时，单位为默认时钟源计数。 +- 返回值： + - RT_EOK：启动成功。 + - -RT_ERROR：定时器已激活或 `cnt` 非法。 +- 说明： + - `cnt` 需小于计数器最大值的一半，以避免回绕歧义。 + - 启动后可能重新编程下一次事件。 + +## rt_clock_hrtimer_stop + +```c +rt_err_t rt_clock_hrtimer_stop(rt_clock_hrtimer_t timer); +``` + +- 作用：停止一个正在运行的定时器。 +- 返回值： + - RT_EOK：停止成功。 + - -RT_ERROR：定时器未激活。 +- 说明：停止定时器可能触发重新编程下一次事件。 + +## rt_clock_hrtimer_control + +```c +rt_err_t rt_clock_hrtimer_control(rt_clock_hrtimer_t timer, int cmd, void *arg); +``` + +- 作用：查询或修改定时器属性。 +- 常用命令（与 RT-Thread 定时器一致）： + - RT_TIMER_CTRL_GET_TIME：读取 `delay_cnt` 到 `*(unsigned long *)arg`。 + - RT_TIMER_CTRL_SET_TIME：用 `*(unsigned long *)arg` 设置 `delay_cnt`。 + - RT_TIMER_CTRL_SET_ONESHOT / RT_TIMER_CTRL_SET_PERIODIC：设置模式。 + - RT_TIMER_CTRL_GET_STATE：查询激活状态。 + - RT_TIMER_CTRL_GET_REMAIN_TIME：获取绝对到期计数值。 + - RT_TIMER_CTRL_GET_FUNC / RT_TIMER_CTRL_SET_FUNC：获取/设置回调。 + - RT_TIMER_CTRL_GET_PARM / RT_TIMER_CTRL_SET_PARM：获取/设置参数。 +- 说明： + - 修改时间或模式不会自动启动已停止的定时器。 + +## rt_clock_hrtimer_detach + +```c +rt_err_t rt_clock_hrtimer_detach(rt_clock_hrtimer_t timer); +``` + +- 作用：分离定时器，并唤醒等待者。 +- 行为： + - 标记定时器为未激活。 + - 唤醒 `rt_clock_hrtimer_sleep()` 的等待线程并返回错误。 +- 适用场景：定时器资源释放或任务退出。 + +## rt_clock_hrtimer_delay_init + +```c +void rt_clock_hrtimer_delay_init(struct rt_clock_hrtimer *timer); +``` + +- 作用：初始化用于阻塞延时的 one-shot hrtimer。 +- 行为：设置内部回调为 completion 触发函数。 + +## rt_clock_hrtimer_delay_detach + +```c +void rt_clock_hrtimer_delay_detach(struct rt_clock_hrtimer *timer); +``` + +- 作用：释放 delay_init 初始化的定时器。 +- 说明：即使已超时也可安全调用。 + +## rt_clock_hrtimer_sleep + +```c +rt_err_t rt_clock_hrtimer_sleep(struct rt_clock_hrtimer *timer, unsigned long cnt); +``` + +- 作用：阻塞当前线程，直到超时。 +- 参数：`timer` 需已初始化（通常通过 delay_init）。 +- 返回值： + - RT_EOK：正常到期。 + - -RT_EINTR：被信号打断或 detach。 + - -RT_EINVAL：`cnt` 为 0。 +- 上下文：仅线程上下文可用。 + +## rt_clock_hrtimer_ndelay / udelay / mdelay + +```c +rt_err_t rt_clock_hrtimer_ndelay(struct rt_clock_hrtimer *timer, unsigned long ns); +rt_err_t rt_clock_hrtimer_udelay(struct rt_clock_hrtimer *timer, unsigned long us); +rt_err_t rt_clock_hrtimer_mdelay(struct rt_clock_hrtimer *timer, unsigned long ms); +``` + +- 作用：按纳秒/微秒/毫秒为单位进行阻塞延时。 +- 行为：根据 clock_time 分辨率换算为计数后调用 `rt_clock_hrtimer_sleep()`。 +- 说明： + - 实际延时受计数频率与事件编程粒度限制。 + +# 典型流程 + +1. 初始化 hrtimer 并设置回调。 +2. 将时间转换为计数值，或使用 ndelay/udelay/mdelay 辅助函数。 +3. 启动定时器，系统会自动编程下一次事件。 +4. 事件中断调用 rt_clock_time_event_isr()，触发 hrtimer 处理与回调分发。 + +# 示例：单次超时 + +```c +#include + +static struct rt_clock_hrtimer demo_timer; + +static void demo_timeout(void *parameter) +{ + RT_UNUSED(parameter); + rt_kprintf("hrtimer timeout\n"); +} + +static void demo_hrtimer_start(void) +{ + rt_uint64_t ns = 5ULL * 1000 * 1000; /* 5 ms */ + unsigned long cnt = (unsigned long)rt_clock_time_ns_to_counter(ns); + + rt_clock_hrtimer_init(&demo_timer, "demo", RT_TIMER_FLAG_ONE_SHOT, + demo_timeout, RT_NULL); + rt_clock_hrtimer_start(&demo_timer, cnt); +} +``` + +# 示例：延时辅助 + +```c +static void demo_hrtimer_sleep(void) +{ + struct rt_clock_hrtimer timer; + + rt_clock_hrtimer_delay_init(&timer); + rt_clock_hrtimer_mdelay(&timer, 10); + rt_clock_hrtimer_delay_detach(&timer); +} +``` + +# 注意事项 + +- 使用硬件事件时，回调可能在中断上下文执行。 +- rt_clock_hrtimer_sleep() 会等待 completion，可能返回 -RT_EINTR。 diff --git a/documentation/6.components/device-driver/clock_time/clock_time_core.md b/documentation/6.components/device-driver/clock_time/clock_time_core.md new file mode 100644 index 0000000000..e7d099eb9d --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_time_core.md @@ -0,0 +1,274 @@ +@page page_device_clock_time_core Clock Time Core + +# Overview + +The clock_time core defines the device model and conversion helpers used by the +subsystem. It manages the default clock source and clock event devices and +provides fixed-point conversion between counters and nanoseconds. + +# Device Model + +## Clock Time Operations + +```c +struct rt_clock_time_ops +{ + rt_uint64_t (*get_freq)(struct rt_clock_time_device *dev); + rt_uint64_t (*get_counter)(struct rt_clock_time_device *dev); + rt_err_t (*set_timeout)(struct rt_clock_time_device *dev, rt_uint64_t delta); +}; +``` + +### get_freq + +- Purpose: return the counter frequency in Hz. +- Requirements: + - Must be stable and match the source used by get_counter. + - Should be non-zero; zero indicates the device is not ready. + +### get_counter + +- Purpose: return a monotonically increasing counter value. +- Requirements: + - Must not go backwards. + - Wrap behavior is allowed but should be consistent with the width of the + counter used by the device. + +### set_timeout + +- Purpose: program the next timeout relative to the current counter value. +- Parameters: `delta` is in the same counter units returned by get_counter. +- Behavior: + - If `delta` is 0 and the hardware supports it, the event can be canceled. + - Return -RT_ENOSYS when the device does not support event programming. + +## Clock Time Device + +```c +struct rt_clock_time_device +{ + struct rt_device parent; + const struct rt_clock_time_ops *ops; + rt_uint64_t res_scale; + rt_uint8_t caps; /* RT_CLOCK_TIME_CAP_SOURCE / RT_CLOCK_TIME_CAP_EVENT */ +}; +``` + +- res_scale provides extra precision in the conversion pipeline. If set to 0, + RT_CLOCK_TIME_RESMUL is used by default. +- caps advertises whether the device can be used as a clock source, a clock + event, or both. + +## Register and Select Devices + +```c +rt_err_t rt_clock_time_device_register(struct rt_clock_time_device *dev, + const char *name, + rt_uint8_t caps); +void rt_clock_time_set_default_source(struct rt_clock_time_device *dev); +void rt_clock_time_set_default_event(struct rt_clock_time_device *dev); +struct rt_clock_time_device *rt_clock_time_get_default_source(void); +struct rt_clock_time_device *rt_clock_time_get_default_event(void); +``` + +### rt_clock_time_device_register + +- Purpose: register a clock_time device and its capabilities. +- Parameters: + - `dev`: device object with ops and res_scale initialized. + - `name`: device name; if NULL, only capability registration is performed. + - `caps`: RT_CLOCK_TIME_CAP_SOURCE and/or RT_CLOCK_TIME_CAP_EVENT. +- Behavior: + - Registers the device under RT_Device_Class_Timer when `name` is provided. + - If this is the first source, it becomes the default source. + - If this is the first event, it becomes the default event. +- Return values: + - RT_EOK on success. + - Negative error code if device registration fails. + +### rt_clock_time_set_default_source / rt_clock_time_set_default_event + +- Purpose: explicitly select the default source or event device. +- Behavior: overrides the auto-selected default. + +### rt_clock_time_get_default_source / rt_clock_time_get_default_event + +- Purpose: query the current default devices. +- Behavior: + - Source defaults to the internal tick-based device if none was registered. + - Event returns NULL if no event device is available. + +### rt_clock_time_source_init + +- Purpose: BSP hook to register an architecture counter or board source. +- Notes: this function is weak and may be overridden by BSP code. + +# Clock Time Query APIs + +```c +rt_uint64_t rt_clock_time_get_freq(void); +rt_uint64_t rt_clock_time_get_counter(void); +rt_uint64_t rt_clock_time_get_event_freq(void); +rt_uint64_t rt_clock_time_get_event_res_scaled(void); +``` + +## rt_clock_time_get_freq + +- Purpose: return the frequency of the default source in Hz. +- Return values: + - Non-zero frequency on success. + - 0 if no valid source is available. + +## rt_clock_time_get_counter + +- Purpose: return the current counter from the default source. +- Return values: + - Monotonic counter value on success. + - 0 if no valid source is available. + +## rt_clock_time_get_event_freq + +- Purpose: return the event device frequency in Hz. +- Behavior: if no event device exists, falls back to the default source. + +## rt_clock_time_get_event_res_scaled + +- Purpose: return the scaled resolution for the event device. +- Behavior: if no event device exists, falls back to the default source. + +# Conversion Helpers + +```c +rt_uint64_t rt_clock_time_get_res_scaled(void); +rt_uint64_t rt_clock_time_counter_to_ns(rt_uint64_t cnt); +rt_uint64_t rt_clock_time_ns_to_counter(rt_uint64_t ns); +``` + +## rt_clock_time_get_res_scaled + +- Purpose: return the scaled resolution for the default source. +- Return values: + - Non-zero scaled resolution when the source is ready. + - 0 when the source is missing or frequency is invalid. + +## rt_clock_time_counter_to_ns + +- Purpose: convert a counter value to nanoseconds based on the default source. +- Notes: returns 0 when resolution is unavailable. + +## rt_clock_time_ns_to_counter + +- Purpose: convert nanoseconds to counter units for the default source. +- Notes: returns 0 when resolution is unavailable. + +Internally, the core computes a scaled resolution: + +``` +res_scaled = (1e9 * res_scale) / freq +``` + +Nanoseconds are then derived using the scale factor RT_CLOCK_TIME_RESMUL to +avoid floating-point math. This keeps precision stable even when freq is not a +power of ten. + +# Event API + +```c +rt_err_t rt_clock_time_set_timeout(rt_uint64_t delta); +void rt_clock_time_event_isr(void); +``` + +## rt_clock_time_set_timeout + +- Purpose: program the next event using the default event device. +- Parameters: `delta` in event counter units (same as event get_counter). +- Return values: + - RT_EOK on success. + - -RT_ENOSYS if no event device exists or set_timeout is unsupported. + +## rt_clock_time_event_isr + +- Purpose: drive the hrtimer scheduler when an event expires. +- Usage: + - Call from the hardware timer ISR after acknowledging the interrupt. + - This function processes expired hrtimers and programs the next event. + +# BSP Integration Example + +## Register a Clock Source + +```c +static rt_uint64_t demo_get_freq(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return 10000000ULL; /* 10 MHz */ +} + +static rt_uint64_t demo_get_counter(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return demo_hw_counter_read(); +} + +static const struct rt_clock_time_ops demo_src_ops = +{ + demo_get_freq, + demo_get_counter, + RT_NULL, +}; + +static struct rt_clock_time_device demo_src_dev = +{ + .ops = &demo_src_ops, + .res_scale = RT_CLOCK_TIME_RESMUL, +}; + +void rt_clock_time_source_init(void) +{ + rt_clock_time_device_register(&demo_src_dev, "clock_time_demo_src", + RT_CLOCK_TIME_CAP_SOURCE); + rt_clock_time_set_default_source(&demo_src_dev); +} +``` + +## Register a Clock Event + +```c +static rt_err_t demo_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta) +{ + RT_UNUSED(dev); + return demo_hw_timer_program(delta); +} + +static const struct rt_clock_time_ops demo_evt_ops = +{ + demo_get_freq, + demo_get_counter, + demo_set_timeout, +}; + +static struct rt_clock_time_device demo_evt_dev = +{ + .ops = &demo_evt_ops, + .res_scale = RT_CLOCK_TIME_RESMUL, +}; + +static void demo_timer_isr(void) +{ + demo_hw_timer_ack(); + rt_clock_time_event_isr(); +} + +void demo_register_event(void) +{ + rt_clock_time_device_register(&demo_evt_dev, "clock_time_demo_evt", + RT_CLOCK_TIME_CAP_EVENT); + rt_clock_time_set_default_event(&demo_evt_dev); +} +``` + +# Notes + +- Event callbacks may run in interrupt context when backed by a hardware event. +- If no event device is available, the hrtimer subsystem falls back to a + software timer. diff --git a/documentation/6.components/device-driver/clock_time/clock_time_core_zh.md b/documentation/6.components/device-driver/clock_time/clock_time_core_zh.md new file mode 100644 index 0000000000..9e81180f32 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_time_core_zh.md @@ -0,0 +1,256 @@ +# Clock Time Core + +clock_time core 定义了子系统的设备模型与换算接口，负责默认时钟源/事件 +选择，并提供计数值与纳秒之间的定点换算。 + +# 设备模型 + +## 时钟操作接口 + +```c +struct rt_clock_time_ops +{ + rt_uint64_t (*get_freq)(struct rt_clock_time_device *dev); + rt_uint64_t (*get_counter)(struct rt_clock_time_device *dev); + rt_err_t (*set_timeout)(struct rt_clock_time_device *dev, rt_uint64_t delta); +}; +``` + +### get_freq + +- 作用：返回计数频率（Hz）。 +- 要求： + - 频率应稳定并与 get_counter 使用的计数源一致。 + - 返回 0 表示设备尚不可用。 + +### get_counter + +- 作用：返回单调递增计数值。 +- 要求： + - 不能回退。 + - 允许回绕，但需与硬件计数位宽一致。 + +### set_timeout + +- 作用：设置相对当前计数的超时事件。 +- 参数：`delta` 为计数单位，与 get_counter 一致。 +- 行为： + - 若 `delta` 为 0 且硬件支持，可取消事件。 + - 不支持时应返回 -RT_ENOSYS。 + +## 时钟设备对象 + +```c +struct rt_clock_time_device +{ + struct rt_device parent; + const struct rt_clock_time_ops *ops; + rt_uint64_t res_scale; + rt_uint8_t caps; /* RT_CLOCK_TIME_CAP_SOURCE / RT_CLOCK_TIME_CAP_EVENT */ +}; +``` + +- res_scale 用于提高换算精度，0 表示使用 RT_CLOCK_TIME_RESMUL 默认值。 +- caps 用于标识设备能力：时钟源或时钟事件。 + +## 注册与默认选择 + +```c +rt_err_t rt_clock_time_device_register(struct rt_clock_time_device *dev, + const char *name, + rt_uint8_t caps); +void rt_clock_time_set_default_source(struct rt_clock_time_device *dev); +void rt_clock_time_set_default_event(struct rt_clock_time_device *dev); +struct rt_clock_time_device *rt_clock_time_get_default_source(void); +struct rt_clock_time_device *rt_clock_time_get_default_event(void); +``` + +### rt_clock_time_device_register + +- 作用：注册 clock_time 设备及其能力。 +- 参数： + - `dev`：设备对象，需初始化 ops 与 res_scale。 + - `name`：设备名；为 NULL 时仅注册能力，不进入设备框架。 + - `caps`：RT_CLOCK_TIME_CAP_SOURCE / RT_CLOCK_TIME_CAP_EVENT。 +- 行为： + - 当 `name` 非空时，以 RT_Device_Class_Timer 注册到设备框架。 + - 首个时钟源/事件默认成为系统默认。 +- 返回值：成功返回 RT_EOK，失败返回负错误码。 + +### rt_clock_time_set_default_source / rt_clock_time_set_default_event + +- 作用：显式设置默认时钟源/事件设备。 +- 说明：会覆盖自动选择结果。 + +### rt_clock_time_get_default_source / rt_clock_time_get_default_event + +- 作用：获取当前默认设备。 +- 行为： + - 若无时钟源，返回内部 tick 源。 + - 若无事件设备，返回 NULL。 + +### rt_clock_time_source_init + +- 作用：BSP 提供时钟源的弱符号入口。 +- 说明：可在 BSP 中重写该函数完成设备注册。 + +# 时钟查询接口 + +```c +rt_uint64_t rt_clock_time_get_freq(void); +rt_uint64_t rt_clock_time_get_counter(void); +rt_uint64_t rt_clock_time_get_event_freq(void); +rt_uint64_t rt_clock_time_get_event_res_scaled(void); +``` + +## rt_clock_time_get_freq + +- 作用：获取默认时钟源频率（Hz）。 +- 返回值：成功返回非 0 频率；无有效时钟源则返回 0。 + +## rt_clock_time_get_counter + +- 作用：获取默认时钟源计数值。 +- 返回值：成功返回计数值；无有效时钟源则返回 0。 + +## rt_clock_time_get_event_freq + +- 作用：获取事件设备频率（Hz）。 +- 行为：若无事件设备则回退使用默认时钟源。 + +## rt_clock_time_get_event_res_scaled + +- 作用：获取事件设备的缩放分辨率。 +- 行为：若无事件设备则回退使用默认时钟源。 + +# 换算接口 + +```c +rt_uint64_t rt_clock_time_get_res_scaled(void); +rt_uint64_t rt_clock_time_counter_to_ns(rt_uint64_t cnt); +rt_uint64_t rt_clock_time_ns_to_counter(rt_uint64_t ns); +``` + +## rt_clock_time_get_res_scaled + +- 作用：获取默认时钟源的缩放分辨率。 +- 返回值：无有效时钟源时返回 0。 + +## rt_clock_time_counter_to_ns + +- 作用：将计数值换算为纳秒。 +- 说明：当分辨率不可用时返回 0。 + +## rt_clock_time_ns_to_counter + +- 作用：将纳秒换算为计数值。 +- 说明：当分辨率不可用时返回 0。 + +核心使用定点缩放换算： + +``` +res_scaled = (1e9 * res_scale) / freq +``` + +然后用 RT_CLOCK_TIME_RESMUL 进行定点缩放，以避免浮点运算带来的精度损失。 + +# 事件接口 + +```c +rt_err_t rt_clock_time_set_timeout(rt_uint64_t delta); +void rt_clock_time_event_isr(void); +``` + +## rt_clock_time_set_timeout + +- 作用：通过默认事件设备设置下一次超时。 +- 参数：`delta` 为事件设备计数单位。 +- 返回值： + - RT_EOK：成功。 + - -RT_ENOSYS：无事件设备或不支持 set_timeout。 + +## rt_clock_time_event_isr + +- 作用：事件到期时驱动 hrtimer 处理。 +- 使用方式： + - 在硬件中断中确认中断后调用该函数。 + - 该函数处理已到期的 hrtimer 并编程下一次事件。 + +# BSP 集成示例 + +## 注册时钟源 + +```c +static rt_uint64_t demo_get_freq(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return 10000000ULL; /* 10 MHz */ +} + +static rt_uint64_t demo_get_counter(struct rt_clock_time_device *dev) +{ + RT_UNUSED(dev); + return demo_hw_counter_read(); +} + +static const struct rt_clock_time_ops demo_src_ops = +{ + demo_get_freq, + demo_get_counter, + RT_NULL, +}; + +static struct rt_clock_time_device demo_src_dev = +{ + .ops = &demo_src_ops, + .res_scale = RT_CLOCK_TIME_RESMUL, +}; + +void rt_clock_time_source_init(void) +{ + rt_clock_time_device_register(&demo_src_dev, "clock_time_demo_src", + RT_CLOCK_TIME_CAP_SOURCE); + rt_clock_time_set_default_source(&demo_src_dev); +} +``` + +## 注册时钟事件 + +```c +static rt_err_t demo_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta) +{ + RT_UNUSED(dev); + return demo_hw_timer_program(delta); +} + +static const struct rt_clock_time_ops demo_evt_ops = +{ + demo_get_freq, + demo_get_counter, + demo_set_timeout, +}; + +static struct rt_clock_time_device demo_evt_dev = +{ + .ops = &demo_evt_ops, + .res_scale = RT_CLOCK_TIME_RESMUL, +}; + +static void demo_timer_isr(void) +{ + demo_hw_timer_ack(); + rt_clock_time_event_isr(); +} + +void demo_register_event(void) +{ + rt_clock_time_device_register(&demo_evt_dev, "clock_time_demo_evt", + RT_CLOCK_TIME_CAP_EVENT); + rt_clock_time_set_default_event(&demo_evt_dev); +} +``` + +# 注意事项 + +- 使用硬件事件时，回调可能运行于中断上下文。 +- 未提供事件设备时，hrtimer 会退化到软件定时器实现。 diff --git a/documentation/6.components/device-driver/hwtimer/hwtimer.md b/documentation/6.components/device-driver/clock_time/clock_timer.md similarity index 64% rename from documentation/6.components/device-driver/hwtimer/hwtimer.md rename to documentation/6.components/device-driver/clock_time/clock_timer.md index 0e2e9767f7..d6c0721bc8 100644 --- a/documentation/6.components/device-driver/hwtimer/hwtimer.md +++ b/documentation/6.components/device-driver/clock_time/clock_timer.md @@ -1,4 +1,6 @@ -@page page_device_hwtimer HWTIMER Device +@page page_device_clock_timer CLOCK_TIMER Device + +> Note: CLOCK_TIMER is the unified hardware timer device in the `clock_time` subsystem. # Introduction to the Timer @@ -10,6 +12,14 @@ Hardware timers generally have two modes of operation, timer mode and counter mo **Counting frequency**：Since the input frequency is usually fixed, the time it takes for the counter to reach its desired count number can be calculated from just the given frequency - `time = count value / count frequency`. For example, if the counting frequency is 1 MHz, the counter counts once every 1 / 1000000 seconds. That is, every 1 microsecond, the counter is incremented by one (or subtracted by one), at this time, the maximum timing capability of the 16-bit counter is 65535 microseconds, or 65.535 milliseconds. +# Relationship to clock_time + +CLOCK_TIMER devices can be used directly by applications through the RT-Thread +device API, and can also act as a clock_time event device. When a clock_timer +is registered with `rt_clock_timer_register()` and selected as the default +event, its ISR calls `rt_clock_time_event_isr()` internally, which drives the +high-resolution timer scheduler. + # Access Hardware Timer Device The application accesses the hardware timer device through the I/O device management interface provided by RT-Thread. The related interfaces are as follows: @@ -42,12 +52,16 @@ rt_device_t rt_device_find(const char* name); In general, the hardware timer device name registered to the system is timer0, timer1, etc. The usage examples are as follows: ```c -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ rt_device_t hw_dev; /* timer device handle */ /* find timer device */ -hw_dev = rt_device_find(HWTIMER_DEV_NAME); +hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); ``` +Details: +- The device name is assigned by the BSP when calling `rt_clock_timer_register()`. +- If multiple timers are registered, each is exposed as a separate device. + ## Open Timer Device With the device handle, the application can open the device. When the device is open, it will detect whether the device has been initialized. If it is not initialized, it will call the initialization interface to initialize the device by default. Open the device with the following function: @@ -67,14 +81,20 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflags); An example of use is as follows: ```c -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ rt_device_t hw_dev; /* timer device handle */ /* find timer device */ -hw_dev = rt_device_find(HWTIMER_DEV_NAME); +hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); /* to open the timer device in read-write mode */ rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); ``` +Details: +- Opening the device ensures the driver is initialized and the working + frequency is applied. +- Call open before using control/read/write APIs; otherwise behavior depends on + the BSP driver and may fail with -RT_ENOSYS or other errors. + ## Set the Timeout Callback Function Set the timer timeout callback function with the following function - this is the function that will be called when the timer reaches its set count value: @@ -93,22 +113,22 @@ rt_err_t rt_device_set_rx_indicate(rt_device_t dev, rt_err_t (*rx_ind)(rt_device An example of use is as follows： ```c -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ rt_device_t hw_dev; /* timer device handle */ /* timer timeout callback function */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback function!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { /* find timer device */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); /* open the device in read and write mode */ rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); /* set the timeout callback function */ @@ -116,6 +136,12 @@ static int hwtimer_sample(int argc, char *argv[]) } ``` +Details: +- The callback runs in the timer interrupt context, so it must be fast and + non-blocking. +- `size` is the size of the timeout data (sizeof(rt_clock_timerval_t)) passed + by the driver; most users can ignore it. + ## Control the Timer Device By sending control words, the application can configure the hardware timer device with the following function: @@ -138,56 +164,70 @@ The command control words available for the hardware timer device are as follows | **Control word** | Description | | ---------------------- | ------------------------ | -| HWTIMER_CTRL_FREQ_SET | set the counting frequency | -| HWTIMER_CTRL_STOP | stop the timer | -| HWTIMER_CTRL_INFO_GET | get timer feature information | -| HWTIMER_CTRL_MODE_SET | set timer mode | +| CLOCK_TIMER_CTRL_FREQ_SET | set the counting frequency | +| CLOCK_TIMER_CTRL_STOP | stop the timer | +| CLOCK_TIMER_CTRL_INFO_GET | get timer feature information | +| CLOCK_TIMER_CTRL_MODE_SET | set timer mode | -Get the timer parameter argument, which is a pointer to the structure struct rt_hwtimer_info, to save the obtained information. +Get the timer parameter argument, which is a pointer to the structure struct rt_clock_timer_info, to save the obtained information. >Setting frequency is valid only when the timer hardware and included driver set the counting frequency. Generally, the default frequency of the driving setting can be used. When setting the timer mode, the parameter argument can take the following values： ```c -HWTIMER_MODE_ONESHOT /* Single timing */ -HWTIMER_MODE_PERIOD /* Periodic timing */ +CLOCK_TIMER_MODE_ONESHOT /* Single timing */ +CLOCK_TIMER_MODE_PERIOD /* Periodic timing */ ``` An example of using the timer count frequency and timing mode is as follows: ```c -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ rt_device_t hw_dev; /* timer device handle */ -rt_hwtimer_mode_t mode; /* timer mode */ -rt_uint32_t freq = 10000; /* couting frequency */ +rt_clock_timer_mode_t mode; /* timer mode */ +rt_uint32_t freq = 10000; /* counting frequency */ /* Timer timeout callback function */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback function!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { /* find timer device */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); /* open the device in read and write mode */ rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); /* Set the timeout callback function */ rt_device_set_rx_indicate(hw_dev, timeout_cb); /* Set the counting frequency (1Mhz or the supported minimum counting frequency by default) */ - rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq); /* Set the mode to periodic timer */ - mode = HWTIMER_MODE_PERIOD; - rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); } ``` +Details: +- CLOCK_TIMER_CTRL_FREQ_SET: + - `arg` points to an integer frequency in Hz. + - The driver checks against `minfreq` and `maxfreq` from rt_clock_timer_info. + - On success, the new frequency is used for subsequent timeouts. +- CLOCK_TIMER_CTRL_STOP: + - Stops the current timer cycle. It does not close the device. +- CLOCK_TIMER_CTRL_INFO_GET: + - `arg` points to `struct rt_clock_timer_info`. + - Returns hardware limits (min/max frequency, max count, count direction). +- CLOCK_TIMER_CTRL_MODE_SET: + - `arg` points to `rt_clock_timer_mode_t`. + - ONESHOT fires once, PERIOD repeats using the calculated reload. + ## Set the Timer Timeout Value The timer timeout value can be set by the following function： @@ -209,41 +249,41 @@ rt_size_t rt_device_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_ The prototype of the timeout structure is shown below : ```c -typedef struct rt_hwtimerval +typedef struct rt_clock_timerval { rt_int32_t sec; /* second */ rt_int32_t usec; /* microsecond */ -} rt_hwtimerval_t; +} rt_clock_timerval_t; ``` An example of using the timer timeout value is as follows: ```c -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ rt_device_t hw_dev; /* timer device handle */ -rt_hwtimer_mode_t mode; /* timer mode */ -rt_hwtimerval_t timeout_s; /* Timer timeout value */ +rt_clock_timer_mode_t mode; /* timer mode */ +rt_clock_timerval_t timeout_s; /* Timer timeout value */ /* Timer timeout callback function */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback function!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { /* find timer device */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); /* open the device in read-write mode */ rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); /* set the timeout callback function */ rt_device_set_rx_indicate(hw_dev, timeout_cb); /* set the mode as periodic timer */ - mode = HWTIMER_MODE_PERIOD; - rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); /* Set the timer timeout value to 5s and start the timer */ timeout_s.sec = 5; /* second */ @@ -252,6 +292,13 @@ static int hwtimer_sample(int argc, char *argv[]) } ``` +Details: +- `size` must match `sizeof(rt_clock_timerval_t)`; otherwise the write fails. +- In periodic mode, the driver may split a long timeout into multiple cycles + based on the hardware `maxcnt` and current frequency. +- For one-shot mode, if the timeout fits in a single cycle, the timer stops + automatically after expiry. + ## Obtain the Current Value of the Timer The current value of the timer can be obtained by the following function： @@ -273,11 +320,17 @@ rt_size_t rt_device_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t An example of use is shown below： ```c -rt_hwtimerval_t timeout_s; /* Used to save the time the timer has elapsed */ +rt_clock_timerval_t timeout_s; /* Used to save the time the timer has elapsed */ /* Read the elapsed time of the timer */ rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); ``` +Details: +- The returned value represents elapsed time since the timer started. +- In periodic mode, the driver accounts for completed cycles plus the current + counter value. +- In one-shot mode, the elapsed time is limited to the active cycle. + ## Close the Timer Device The timer device can be closed with the following function: @@ -299,16 +352,78 @@ When a timer device has been used and is not necessary anymore, it should be clo An example of use is shown below： ```c -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ rt_device_t hw_dev; /* timer device handle */ /* find timer device */ -hw_dev = rt_device_find(HWTIMER_DEV_NAME); +hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); ... ... rt_device_close(hw_dev); ``` +Details: +- Closing the device may stop the timer and deinitialize hardware resources. +- Reopen the device before using it again. + >Timing errors may occur. Assume that the counter has a maximum value of 0xFFFF, a counting frequency of 1Mhz, and a timing time of 1 second and 1 microsecond. Since the timer can only count up to 65535us at a time, the timing requirement for 1000001us can be completed 20 times at 50000us, and the calculation error will be 1us. +# Driver Integration (BSP/Driver Authors) + +To provide a hardware timer as a clock_timer device, implement +`rt_clock_timer_ops`, fill `rt_clock_timer_info`, and register it with +`rt_clock_timer_register()`. The ISR should call `rt_clock_timer_isr()` to +handle overflow, callback dispatch, and (if selected) clock_time event +notification. + +```c +static const struct rt_clock_timer_ops timer_ops = +{ + .init = drv_timer_init, + .start = drv_timer_start, + .stop = drv_timer_stop, + .count_get = drv_timer_count_get, + .control = drv_timer_control, +}; + +static const struct rt_clock_timer_info timer_info = +{ + .maxfreq = 1000000, + .minfreq = 1000, + .maxcnt = 0xFFFFFFFF, + .cntmode = CLOCK_TIMER_CNTMODE_UP, +}; + +static rt_clock_timer_t hw_timer = +{ + .ops = &timer_ops, + .info = &timer_info, +}; + +void drv_timer_register(void) +{ + rt_clock_timer_register(&hw_timer, "timer0", RT_NULL); +} + +void drv_timer_isr(void) +{ + rt_clock_timer_isr(&hw_timer); +} +``` + +If the timer supports one-shot start, it can also serve as the default +clock_time event device (used by hrtimer). + +Details: +- rt_clock_timer_register(): + - Registers the device into the RT-Thread device framework as a timer class. + - If this is the first registered timer with a valid start op, it becomes + the clock_time event device automatically. + - The default event is opened and initialized if not already active. +- rt_clock_timer_isr(): + - Maintains internal overflow/cycle accounting. + - Triggers the user callback via `rx_indicate`. + - If the timer is the clock_time event owner, it calls + `rt_clock_time_event_isr()` to drive hrtimer. + # Hardware Timer Device Usage Example The specific use of the hardware timer device can refer to the following sample code. The main steps of the sample code are as follows: @@ -321,38 +436,38 @@ The specific use of the hardware timer device can refer to the following sample ```c /* - * Program listing: This is an hwtimer device usage routine -  * The routine exports the hwtimer_sample command to the control terminal -  * Command call format: hwtimer_sample + * Program listing: This is a clock_timer device usage routine +  * The routine exports the clock_timer_sample command to the control terminal +  * Command call format: clock_timer_sample   * Program function: The hardware timer timeout callback function periodically prints the current tick value, and the difference between the two tick values is converted to the time equivalent to the timing time value. */ #include #include -#define HWTIMER_DEV_NAME "timer0" /* timer name */ +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ /* Timer timeout callback function */ static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) { - rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("this is clock_timer timeout callback function!\n"); rt_kprintf("tick is :%d !\n", rt_tick_get()); return 0; } -static int hwtimer_sample(int argc, char *argv[]) +static int clock_timer_sample(int argc, char *argv[]) { rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; /* timer timeout value */ + rt_clock_timerval_t timeout_s; /* timer timeout value */ rt_device_t hw_dev = RT_NULL; /* timer device value */ - rt_hwtimer_mode_t mode; /* timer mode */ + rt_clock_timer_mode_t mode; /* timer mode */ /* find timer device */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); return -RT_ERROR; } @@ -360,7 +475,7 @@ static int hwtimer_sample(int argc, char *argv[]) ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); return ret; } @@ -368,8 +483,8 @@ static int hwtimer_sample(int argc, char *argv[]) rt_device_set_rx_indicate(hw_dev, timeout_cb); /* Setting mode is periodic timer */ - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); if (ret != RT_EOK) { rt_kprintf("set mode failed! ret is :%d\n", ret); @@ -396,5 +511,5 @@ static int hwtimer_sample(int argc, char *argv[]) return ret; } /* Export to the msh command list */ -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); ``` diff --git a/documentation/6.components/device-driver/clock_time/clock_timer_zh.md b/documentation/6.components/device-driver/clock_time/clock_timer_zh.md new file mode 100644 index 0000000000..880f604da6 --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/clock_timer_zh.md @@ -0,0 +1,370 @@ +# CLOCK_TIMER 设备 + +> 说明：CLOCK_TIMER 是 `clock_time` 子系统中的统一硬件定时器设备。 + +# 定时器简介 + +硬件定时器通常有两种工作模式：定时模式与计数模式。无论哪种模式，本质都 +是对输入脉冲计数。以下为常用概念： + +**定时模式**：计数内部脉冲信号，常用于定时检测、响应与控制。 + +**计数模式**：计数器可加/减计数。16 位计数器最大计数值为 65535，32 位 +计数器最大值为 4,294,967,295。 + +**计数频率**：在输入频率固定时，可由 `time = count / freq` 计算时间。 +例如频率 1 MHz，计数器每 1 微秒加 1；16 位计数器最大定时能力约为 +65.535 ms。 + +# 与 clock_time 的关系 + +CLOCK_TIMER 设备可直接通过 RT-Thread 设备框架被应用使用，也可以作为 +clock_time 的事件设备。当通过 `rt_clock_timer_register()` 注册并成为默认 +事件设备时，其中断会触发 `rt_clock_time_event_isr()`，驱动高精度定时器 +调度。 + +# 访问硬件定时器设备 + +应用通过 RT-Thread I/O 设备管理接口访问硬件定时器，常用接口如下： + +| **函数** | **描述** | +| -------------------- | ---------------------------------- | +| rt_device_find() | 查找定时器设备 | +| rt_device_open() | 以读写方式打开定时器设备 | +| rt_device_set_rx_indicate() | 设置超时回调函数 | +| rt_device_control() | 控制定时器（模式、频率、停止等） | +| rt_device_write() | 设置超时时间并启动 | +| rt_device_read() | 读取当前计数值 | +| rt_device_close() | 关闭设备 | + +## 查找定时器设备 + +```c +rt_device_t rt_device_find(const char* name); +``` + +| 参数 | 描述 | +| -------- | ---------------------------------- | +| name | 定时器设备名称 | +| **返回** | —— | +| 设备句柄 | 查找成功返回句柄 | +| RT_NULL | 未找到设备 | + +通常设备名为 timer0、timer1 等。 + +```c +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ +rt_device_t hw_dev; /* timer device handle */ + +hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); +``` + +补充说明： +- 设备名由 BSP 在 `rt_clock_timer_register()` 中指定。 +- 系统内注册的每个定时器都会对应一个设备节点。 + +## 打开定时器设备 + +```c +rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflags); +``` + +| 参数 | 描述 | +| ---------- | ------------------------------- | +| dev | 定时器设备句柄 | +| oflags | 打开模式，通常为 RT_DEVICE_OFLAG_RDWR | +| **返回** | —— | +| RT_EOK | 打开成功 | +| 其他错误码 | 打开失败 | + +```c +hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); +rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); +``` + +补充说明： +- 打开设备会确保驱动初始化并应用当前工作频率。 +- 调用 control/read/write 之前应先 open，否则可能返回 -RT_ENOSYS 或失败。 + +## 设置超时回调函数 + +```c +rt_err_t rt_device_set_rx_indicate(rt_device_t dev, + rt_err_t (*rx_ind)(rt_device_t dev, rt_size_t size)) +``` + +| 参数 | 描述 | +| ---------- | ------------------------------- | +| dev | 设备句柄 | +| rx_ind | 超时回调函数 | +| **返回** | —— | +| RT_EOK | 成功 | + +```c +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("this is clock_timer timeout callback function!\n"); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int clock_timer_sample(int argc, char *argv[]) +{ + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); + rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + rt_device_set_rx_indicate(hw_dev, timeout_cb); +} +``` + +补充说明： +- 回调在中断上下文执行，应尽量短小且避免阻塞。 +- `size` 通常为 sizeof(rt_clock_timerval_t)，多数场景可忽略。 + +## 控制定时器设备 + +```c +rt_err_t rt_device_control(rt_device_t dev, rt_uint8_t cmd, void* arg); +``` + +| 参数 | 描述 | +| ---------------- | ------------------------------ | +| dev | 设备句柄 | +| cmd | 控制命令 | +| arg | 参数 | +| **返回** | —— | +| RT_EOK | 成功 | +| -RT_ENOSYS | 失败，设备为空 | +| 其他错误码 | 失败 | + +控制命令： + +| **控制命令** | 描述 | +| ---------------------- | ------------------------ | +| CLOCK_TIMER_CTRL_FREQ_SET | 设置计数频率 | +| CLOCK_TIMER_CTRL_STOP | 停止定时器 | +| CLOCK_TIMER_CTRL_INFO_GET | 获取特性信息 | +| CLOCK_TIMER_CTRL_MODE_SET | 设置模式 | + +模式可选： + +```c +CLOCK_TIMER_MODE_ONESHOT /* 单次定时 */ +CLOCK_TIMER_MODE_PERIOD /* 周期定时 */ +``` + +示例： + +```c +rt_clock_timer_mode_t mode; +rt_uint32_t freq = 10000; /* counting frequency */ + +rt_device_control(hw_dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq); +mode = CLOCK_TIMER_MODE_PERIOD; +rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); +``` + +补充说明： +- CLOCK_TIMER_CTRL_FREQ_SET： + - `arg` 指向频率值（Hz）。 + - 驱动会与 `rt_clock_timer_info` 中的 minfreq/maxfreq 做范围校验。 + - 设置成功后影响后续超时换算。 +- CLOCK_TIMER_CTRL_STOP： + - 仅停止当前定时流程，不会关闭设备。 +- CLOCK_TIMER_CTRL_INFO_GET： + - `arg` 指向 `struct rt_clock_timer_info`，返回硬件能力信息。 +- CLOCK_TIMER_CTRL_MODE_SET： + - `arg` 指向 `rt_clock_timer_mode_t`。 + - ONESHOT 单次触发；PERIOD 周期触发。 + +## 设置超时值 + +```c +rt_size_t rt_device_write(rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size); +``` + +| 参数 | 描述 | +| ---------- | ------------------------------------------ | +| dev | 设备句柄 | +| pos | 偏移，未使用，置 0 | +| buffer | 超时结构体指针 | +| size | 结构体大小 | +| **返回** | —— | +| 实际写入长度 | 成功 | +| 0 | 失败 | + +超时结构体： + +```c +typedef struct rt_clock_timerval +{ + rt_int32_t sec; + rt_int32_t usec; +} rt_clock_timerval_t; +``` + +```c +rt_clock_timerval_t timeout_s; + +timeout_s.sec = 5; +timeout_s.usec = 0; +rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)); +``` + +补充说明： +- `size` 必须等于 `sizeof(rt_clock_timerval_t)`，否则写入失败。 +- 周期模式下，长超时可能被拆分为多个计数周期执行。 +- 单次模式且超时可在一个周期内完成时，到期后自动停止。 + +## 读取当前计数值 + +```c +rt_size_t rt_device_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size); +``` + +```c +rt_clock_timerval_t timeout_s; +rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); +``` + +补充说明： +- 返回值表示自定时启动以来的累计耗时。 +- 周期模式会包含已完成周期的时间。 +- 单次模式下只反映当前周期内的计数进度。 + +## 关闭设备 + +```c +rt_err_t rt_device_close(rt_device_t dev); +``` + +```c +rt_device_close(hw_dev); +``` + +补充说明： +- 关闭设备可能会停止定时器并释放硬件资源。 +- 再次使用前需要重新打开设备。 + +> 定时误差示例：若计数器最大 0xFFFF、频率 1 MHz，定时 1.000001 s 时需拆分 +> 为多次计数，误差约 1 us。 + +# 驱动对接（BSP/驱动作者） + +实现 `rt_clock_timer_ops` 并注册设备；在中断中调用 `rt_clock_timer_isr()`。 + +```c +static const struct rt_clock_timer_ops timer_ops = +{ + .init = drv_timer_init, + .start = drv_timer_start, + .stop = drv_timer_stop, + .count_get = drv_timer_count_get, + .control = drv_timer_control, +}; + +static const struct rt_clock_timer_info timer_info = +{ + .maxfreq = 1000000, + .minfreq = 1000, + .maxcnt = 0xFFFFFFFF, + .cntmode = CLOCK_TIMER_CNTMODE_UP, +}; + +static rt_clock_timer_t hw_timer = +{ + .ops = &timer_ops, + .info = &timer_info, +}; + +void drv_timer_register(void) +{ + rt_clock_timer_register(&hw_timer, "timer0", RT_NULL); +} + +void drv_timer_isr(void) +{ + rt_clock_timer_isr(&hw_timer); +} +``` + +若支持单次启动，clock_timer 设备也可作为 clock_time 默认事件设备。 + +补充说明： +- rt_clock_timer_register(): + - 将设备注册到 RT-Thread 设备框架，类型为 Timer。 + - 首个具备 start 操作的设备会被自动设置为 clock_time 事件设备。 + - 若默认事件尚未激活，注册后会自动初始化并打开。 +- rt_clock_timer_isr(): + - 维护溢出与周期计数。 + - 通过 rx_indicate 回调上层。 + - 若为 clock_time 事件设备，会调用 `rt_clock_time_event_isr()`。 + +# 使用示例 + +以下示例演示完整流程：查找设备、打开、设置回调、周期定时、读取计数等。 + +```c +#include +#include + +#define CLOCK_TIMER_DEV_NAME "timer0" /* timer name */ + +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("this is clock_timer timeout callback function!\n"); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int clock_timer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_clock_timerval_t timeout_s; /* timer timeout value */ + rt_device_t hw_dev = RT_NULL; /* timer device handle */ + rt_clock_timer_mode_t mode; /* timer mode */ + + hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME); + return -RT_ERROR; + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME); + return ret; + } + + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + mode = CLOCK_TIMER_MODE_PERIOD; + ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + timeout_s.sec = 5; + timeout_s.usec = 0; + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return -RT_ERROR; + } + + rt_thread_mdelay(3500); + + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample); +``` diff --git a/documentation/6.components/device-driver/clock_time/figures/clock_time_arch.svg b/documentation/6.components/device-driver/clock_time/figures/clock_time_arch.svg new file mode 100644 index 0000000000..ae0d42192c --- /dev/null +++ b/documentation/6.components/device-driver/clock_time/figures/clock_time_arch.svg @@ -0,0 +1,96 @@ + + + + + + + + + + + POSIX / libc + clock_gettime, nanosleep + + + Soft RTC + timekeeping baseline + + + Device Drivers + input timestamp, vDSO, PIC + + + + Clock Time Subsystem + + + + Core API + register, default source/event + counter ↔ ns conversion + + + Clock Source Device + get_freq / get_counter + monotonic time base + + + Clock Event Device + set_timeout / event ISR + timeout programming + + + + Clock HRTimer + priority queue of timeouts + callback dispatch + + + Boottime Helpers + get_us / get_ns / get_s + timeval / timespec + + + Clock Timer Adapter + rt_clock_timer device API + unified timer interface + + + + BSP Drivers + arch counters, clock_timer drivers, DM/OFW integration + + + + Hardware Counter / Timer + CPU timer, SoC timer peripherals + + + + + + + + + + + + + + + diff --git a/examples/test/hwtimer_test.c b/examples/test/clock_timer_test.c similarity index 80% rename from examples/test/hwtimer_test.c rename to examples/test/clock_timer_test.c index 08b0c5acaf..f231682ffb 100644 --- a/examples/test/hwtimer_test.c +++ b/examples/test/clock_timer_test.c @@ -11,7 +11,7 @@ #include #include -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME #define TIMER "timer0" @@ -22,13 +22,13 @@ static rt_err_t timer_timeout_cb(rt_device_t dev, rt_size_t size) return 0; } -int hwtimer(void) +int clock_timer(void) { rt_err_t err; - rt_hwtimerval_t val; + rt_clock_timerval_t val; rt_device_t dev = RT_NULL; rt_tick_t tick; - rt_hwtimer_mode_t mode; + rt_clock_timer_mode_t mode; int freq = 10000; int t = 5; @@ -46,7 +46,7 @@ int hwtimer(void) /* 时间测量 */ /* 计数时钟设置(默认1Mhz或支持的最小计数频率) */ - err = rt_device_control(dev, HWTIMER_CTRL_FREQ_SET, &freq); + err = rt_device_control(dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq); if (err != RT_EOK) { rt_kprintf("Set Freq=%dhz Fail\n", freq); @@ -54,8 +54,8 @@ int hwtimer(void) } /* 周期模式 */ - mode = HWTIMER_MODE_PERIOD; - err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + err = rt_device_control(dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); tick = rt_tick_get(); rt_kprintf("Start Timer> Tick: %d\n", tick); @@ -72,7 +72,7 @@ int hwtimer(void) rt_thread_delay(t*RT_TICK_PER_SECOND); /* 停止定时器 */ - err = rt_device_control(dev, HWTIMER_CTRL_STOP, RT_NULL); + err = rt_device_control(dev, CLOCK_TIMER_CTRL_STOP, RT_NULL); rt_kprintf("Timer Stoped\n"); /* 读取计数 */ rt_device_read(dev, 0, &val, sizeof(val)); @@ -83,8 +83,8 @@ int hwtimer(void) rt_device_set_rx_indicate(dev, timer_timeout_cb); /* 单次模式 */ - mode = HWTIMER_MODE_PERIOD; - err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode); + mode = CLOCK_TIMER_MODE_PERIOD; + err = rt_device_control(dev, CLOCK_TIMER_CTRL_MODE_SET, &mode); /* 设置定时器超时值并启动定时器 */ val.sec = t; @@ -106,6 +106,6 @@ EXIT: return err; } #ifdef RT_USING_FINSH -MSH_CMD_EXPORT(hwtimer, "Test hardware timer"); +MSH_CMD_EXPORT(clock_timer, "Test clock time timer"); #endif -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ diff --git a/libcpu/Kconfig b/libcpu/Kconfig index b089b61725..22381a42fe 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -264,7 +264,7 @@ if ARCH_RISCV64 config ARCH_USING_RISCV_COMMON64 bool depends on ARCH_RISCV64 - select RT_USING_CPUTIME + select RT_USING_CLOCK_TIME select ARCH_USING_NEW_CTX_SWITCH help Using the common64 implementation under ./libcpu/risc-v diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript index 13e5f2fdb0..99645683b8 100644 --- a/libcpu/aarch64/common/SConscript +++ b/libcpu/aarch64/common/SConscript @@ -21,7 +21,7 @@ if GetDepend('RT_USING_OFW') == False: if GetDepend('RT_USING_PIC') == True: SrcRemove(src, ['gicv3.c', 'gic.c', 'gtimer.c', 'interrupt.c']) -if GetDepend('RT_HWTIMER_ARM_ARCH') == True: +if GetDepend('RT_CLOCK_TIME_ARM_ARCH') == True: SrcRemove(src, ['gtimer.c']) group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) diff --git a/libcpu/aarch64/common/gtimer.c b/libcpu/aarch64/common/gtimer.c index 514ec4e043..46ce287aeb 100644 --- a/libcpu/aarch64/common/gtimer.c +++ b/libcpu/aarch64/common/gtimer.c @@ -13,8 +13,8 @@ #include #include -#ifdef RT_USING_KTIME -#include +#ifdef RT_USING_CLOCK_TIME +#include #endif #define EL1_PHY_TIMER_IRQ_NUM 30 @@ -42,8 +42,8 @@ void rt_hw_gtimer_local_enable(void) rt_hw_gtimer_disable(); rt_hw_set_gtimer_val(timer_step); rt_hw_interrupt_umask(EL1_PHY_TIMER_IRQ_NUM); -#ifdef RT_USING_KTIME - rt_ktime_cputimer_init(); +#ifdef RT_USING_CLOCK_TIME + rt_clock_time_source_init(); #endif rt_hw_gtimer_enable(); } diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index 2109179134..79df36ec5b 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -72,7 +72,7 @@ void rt_hw_fdt_install_early(void *fdt) #endif } -#ifdef RT_USING_HWTIMER +#ifdef RT_USING_CLOCK_TIME static rt_ubase_t loops_per_tick[RT_CPUS_NR]; static rt_ubase_t cpu_get_cycles(void) @@ -132,7 +132,7 @@ static void cpu_us_delay(rt_uint32_t us) rt_hw_cpu_relax(); } } -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME */ rt_weak void rt_hw_idle_wfi(void) { @@ -188,14 +188,14 @@ rt_inline void cpu_info_init(void) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, rt_cpu_mpidr_table, sizeof(rt_cpu_mpidr_table)); -#ifdef RT_USING_HWTIMER +#if defined(RT_USING_CLOCK_TIME) && defined(RT_USING_DM) cpu_loops_per_tick_init(); - if (!rt_device_hwtimer_us_delay) + if (!rt_clock_timer_us_delay) { - rt_device_hwtimer_us_delay = &cpu_us_delay; + rt_clock_timer_us_delay = &cpu_us_delay; } -#endif /* RT_USING_HWTIMER */ +#endif /* RT_USING_CLOCK_TIME && RT_USING_DM */ } rt_inline rt_size_t string_to_size(const char *string, const char *who) @@ -382,10 +382,10 @@ void rt_hw_common_setup(void) rt_hw_uart_init(); #endif -#ifndef RT_HWTIMER_ARM_ARCH +#ifndef RT_CLOCK_TIME_ARM_ARCH /* initialize timer for os tick */ rt_hw_gtimer_init(); -#endif /* !RT_HWTIMER_ARM_ARCH */ +#endif /* !RT_CLOCK_TIME_ARM_ARCH */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); @@ -478,10 +478,10 @@ rt_weak void rt_hw_secondary_cpu_bsp_start(void) #endif /* BSP_USING_GICV3 */ #endif -#ifndef RT_HWTIMER_ARM_ARCH +#ifndef RT_CLOCK_TIME_ARM_ARCH /* initialize timer for os tick */ rt_hw_gtimer_local_enable(); -#endif /* !RT_HWTIMER_ARM_ARCH */ +#endif /* !RT_CLOCK_TIME_ARM_ARCH */ rt_dm_secondary_cpu_init(); @@ -491,8 +491,8 @@ rt_weak void rt_hw_secondary_cpu_bsp_start(void) LOG_I("Call cpu %d on %s", cpu_id, "success"); -#ifdef RT_USING_HWTIMER - if (rt_device_hwtimer_us_delay == &cpu_us_delay) +#if defined(RT_USING_CLOCK_TIME) && defined(RT_USING_DM) + if (rt_clock_timer_us_delay == &cpu_us_delay) { cpu_loops_per_tick_init(); } diff --git a/libcpu/risc-v/common64/tick.c b/libcpu/risc-v/common64/tick.c index 8e8ff86a74..06ede73a54 100644 --- a/libcpu/risc-v/common64/tick.c +++ b/libcpu/risc-v/common64/tick.c @@ -6,49 +6,61 @@ * Change Logs: * Date Author Notes * 2018/10/28 Bernard The unify RISC-V porting code. - * 2024/07/08 Shell Using CPUTIME as tick + * 2024/07/08 Shell Using clock_time as tick */ #include #include -#include #include #include "sbi.h" -#ifdef RT_USING_KTIME -#include +#ifdef RT_USING_CLOCK_TIME +#include #endif static volatile unsigned long tick_cycles = 0; +static rt_uint64_t _clock_timer_freq = 0; + +rt_weak rt_uint64_t rt_hw_get_clock_timer_freq(void) +{ + return CLOCK_TIMER_FREQ; +} + +static rt_uint64_t _riscv_read_time(void) +{ + unsigned long time_elapsed; + + __asm__ __volatile__("rdtime %0" : "=r"(time_elapsed)); + return (rt_uint64_t)time_elapsed; +} int tick_isr(void) { rt_tick_increase(); - sbi_set_timer(clock_cpu_gettime() + tick_cycles); + sbi_set_timer(_riscv_read_time() + tick_cycles); return 0; } -/* BSP should config clockbase frequency */ -RT_STATIC_ASSERT(defined_clockbase_freq, CPUTIME_TIMER_FREQ != 0); - /* Sets and enable the timer interrupt */ int rt_hw_tick_init(void) { + rt_uint64_t freq = rt_hw_get_clock_timer_freq(); + RT_ASSERT(freq != 0); + + _clock_timer_freq = freq; + /* calculate the tick cycles */ - tick_cycles = CPUTIME_TIMER_FREQ / RT_TICK_PER_SECOND; + tick_cycles = freq / RT_TICK_PER_SECOND; /* Clear the Supervisor-Timer bit in SIE */ clear_csr(sie, SIP_STIP); - /* Init riscv timer */ - riscv_cputime_init(); - /* Set timer */ - sbi_set_timer(clock_cpu_gettime() + tick_cycles); + sbi_set_timer(_riscv_read_time() + tick_cycles); -#ifdef RT_USING_KTIME - rt_ktime_cputimer_init(); +#ifdef RT_USING_CLOCK_TIME + rt_clock_time_source_init(); #endif /* Enable the Supervisor-Timer bit in SIE */ set_csr(sie, SIP_STIP); @@ -66,11 +78,14 @@ void rt_hw_us_delay(rt_uint32_t us) unsigned long start_time; unsigned long end_time; unsigned long run_time; + rt_uint64_t freq; - start_time = clock_cpu_gettime(); - end_time = start_time + us * (CPUTIME_TIMER_FREQ / 1000000); + start_time = _riscv_read_time(); + freq = _clock_timer_freq ? _clock_timer_freq : rt_hw_get_clock_timer_freq(); + RT_ASSERT(freq != 0); + end_time = start_time + (rt_uint64_t)us * freq / 1000000ULL; do { - run_time = clock_cpu_gettime(); + run_time = _riscv_read_time(); } while(run_time < end_time); } diff --git a/src/Kconfig b/src/Kconfig index efb21f2752..f57b305ca2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -41,7 +41,7 @@ config RT_USING_SMART select RT_USING_POSIX_CLOCK select RT_USING_POSIX_FS select RT_USING_POSIX_TERMIOS - select RT_USING_KTIME + select RT_USING_CLOCK_TIME select RT_USING_STDC_ATOMIC select RT_USING_SYSTEM_WORKQUEUE select RT_USING_CPU_USAGE_TRACER diff --git a/src/utest/perf/Kconfig b/src/utest/perf/Kconfig index fe6ee640ce..9425c7b456 100644 --- a/src/utest/perf/Kconfig +++ b/src/utest/perf/Kconfig @@ -7,9 +7,9 @@ config RT_UTEST_SYS_PERF_TC_COUNT default 1000 depends on RT_UTEST_SYS_PERF -config RT_UTEST_HWTIMER_DEV_NAME - string "PerfTest: Hardware timer device name" +config RT_UTEST_CLOCK_TIMER_DEV_NAME + string "PerfTest: Clock time timer device name" default "timer0" - depends on RT_USING_HWTIMER && RT_UTEST_SYS_PERF + depends on RT_USING_CLOCK_TIME && RT_UTEST_SYS_PERF help Specify the hardware timer device name used for context switch testing (e.g., timer0). diff --git a/src/utest/perf/irq_latency_tc.c b/src/utest/perf/irq_latency_tc.c index 51eccd3df9..a6b61b1c5f 100644 --- a/src/utest/perf/irq_latency_tc.c +++ b/src/utest/perf/irq_latency_tc.c @@ -50,7 +50,7 @@ static rt_device_t hw_dev = RT_NULL; static rt_sem_t complete_sem = RT_NULL; -static rt_hwtimerval_t timeout = {0}; +static rt_clock_timerval_t timeout = {0}; static rt_perf_t *perf_local = RT_NULL; static void modify_time(rt_perf_t *perf) @@ -79,14 +79,14 @@ rt_err_t rt_perf_irq_latency(rt_perf_t *perf) rt_strcpy(perf->name,"rt_perf_irq_latency"); #endif int ret = RT_EOK; - rt_hwtimer_mode_t mode = HWTIMER_MODE_PERIOD; + rt_clock_timer_mode_t mode = CLOCK_TIMER_MODE_PERIOD; perf_local = perf; - hw_dev = rt_device_find(RT_UTEST_HWTIMER_DEV_NAME); + hw_dev = rt_device_find(RT_UTEST_CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { ret = RT_ERROR; - LOG_E("hwtimer sample run failed! can't find %s device!", RT_UTEST_HWTIMER_DEV_NAME); + LOG_E("clock_timer sample run failed! can't find %s device!", RT_UTEST_CLOCK_TIMER_DEV_NAME); return ret; } @@ -100,7 +100,7 @@ rt_err_t rt_perf_irq_latency(rt_perf_t *perf) rt_mutex_release(perf->lock); rt_device_set_rx_indicate(hw_dev, timer_callback); - rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, (void *)&mode); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, (void *)&mode); rt_perf_start_impl(perf_local, &timeout); @@ -111,4 +111,3 @@ rt_err_t rt_perf_irq_latency(rt_perf_t *perf) return RT_EOK; } - diff --git a/src/utest/perf/perf_tc.c b/src/utest/perf/perf_tc.c index 99f36733b6..65e0fa4673 100644 --- a/src/utest/perf/perf_tc.c +++ b/src/utest/perf/perf_tc.c @@ -47,7 +47,6 @@ * - Test runs via: `utest_run core.perf_test` in msh */ - #include #include #include @@ -62,7 +61,7 @@ #define GET_DECIMALS(num) split_double(num, RET_DECIMALS) static rt_device_t hw_dev = RT_NULL; -static rt_hwtimerval_t timeout_s = { 0 }; +static rt_clock_timerval_t timeout_s = { 0 }; typedef rt_err_t (*testcase_function)(rt_perf_t *perf); testcase_function test_func_ptrs[] = { @@ -77,21 +76,21 @@ testcase_function test_func_ptrs[] = { static rt_uint32_t rt_perf_get_timer_us(void) { - rt_hwtimerval_t timer_val = { 0 }; - if (hw_dev && rt_device_read(hw_dev, 0, &timer_val, sizeof(rt_hwtimerval_t))) + rt_clock_timerval_t timer_val = { 0 }; + if (hw_dev && rt_device_read(hw_dev, 0, &timer_val, sizeof(rt_clock_timerval_t))) { return (rt_uint32_t)(timer_val.sec * 1000000u + timer_val.usec); /* return us */ } return 0; } -void rt_perf_start_impl(rt_perf_t *perf, rt_hwtimerval_t *timeout) +void rt_perf_start_impl(rt_perf_t *perf, rt_clock_timerval_t *timeout) { if (hw_dev) { if (timeout == RT_NULL) timeout = &timeout_s; - rt_device_write(hw_dev, 0, timeout, sizeof(rt_hwtimerval_t)); + rt_device_write(hw_dev, 0, timeout, sizeof(rt_clock_timerval_t)); } perf->begin_time = rt_perf_get_timer_us(); } @@ -116,7 +115,7 @@ void rt_perf_stop(rt_perf_t *perf) perf->tot_time += perf->real_time; if (hw_dev) - rt_device_control(hw_dev, HWTIMER_CTRL_STOP, NULL); + rt_device_control(hw_dev, CLOCK_TIMER_CTRL_STOP, NULL); } static rt_int32_t split_double(double num, rt_uint32_t type) @@ -206,17 +205,17 @@ static rt_err_t utest_tc_init(void) { int ret = RT_EOK; - hw_dev = rt_device_find(RT_UTEST_HWTIMER_DEV_NAME); + hw_dev = rt_device_find(RT_UTEST_CLOCK_TIMER_DEV_NAME); if (hw_dev == RT_NULL) { ret = RT_ERROR; - LOG_E("hwtimer sample run failed! can't find %s device!", RT_UTEST_HWTIMER_DEV_NAME); + LOG_E("clock_timer sample run failed! can't find %s device!", RT_UTEST_CLOCK_TIMER_DEV_NAME); return ret; } ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); if (ret != RT_EOK) { - LOG_E("open %s device failed!", RT_UTEST_HWTIMER_DEV_NAME); + LOG_E("open %s device failed!", RT_UTEST_CLOCK_TIMER_DEV_NAME); return ret; } @@ -239,4 +238,3 @@ static void testcase(void) } UTEST_TC_EXPORT(testcase, "core.perf_test", utest_tc_init, utest_tc_cleanup, 10); - diff --git a/src/utest/perf/perf_tc.h b/src/utest/perf/perf_tc.h index 06aeb5214e..0dc20e0d30 100644 --- a/src/utest/perf/perf_tc.h +++ b/src/utest/perf/perf_tc.h @@ -35,7 +35,7 @@ typedef struct rt_perf rt_bool_t dump_head; } rt_perf_t; -void rt_perf_start_impl(rt_perf_t *perf, rt_hwtimerval_t *timeout); +void rt_perf_start_impl(rt_perf_t *perf, rt_clock_timerval_t *timeout); void rt_perf_stop(rt_perf_t *perf); void rt_perf_dump( rt_perf_t *perf); -- Gitee From 88c1e6c88a99a74ad85eb08652d4e31e960c1f19 Mon Sep 17 00:00:00 2001 From: Damon <99158101+Start-xl-wq@users.noreply.github.com> Date: Sun, 1 Feb 2026 14:02:10 +0800 Subject: [PATCH 20/45] sdio: fix missing card status polling after CMD6 in eMMC DDR mode switch --- .../drivers/include/drivers/dev_mmcsd_core.h | 2 + components/drivers/sdio/dev_mmc.c | 70 ++++++++++++++++++- 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/components/drivers/include/drivers/dev_mmcsd_core.h b/components/drivers/include/drivers/dev_mmcsd_core.h index a541bc2e2d..0e170a6695 100644 --- a/components/drivers/include/drivers/dev_mmcsd_core.h +++ b/components/drivers/include/drivers/dev_mmcsd_core.h @@ -142,6 +142,8 @@ struct rt_mmcsd_req #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ #define R1_APP_CMD (1 << 5) /* sr, c */ +/*the programing is state*/ +#define R1_STATE_PRG 0x07 #define R1_SPI_IDLE (1 << 0) #define R1_SPI_ERASE_RESET (1 << 1) diff --git a/components/drivers/sdio/dev_mmc.c b/components/drivers/sdio/dev_mmc.c index 2012d9e529..8a09aa937d 100644 --- a/components/drivers/sdio/dev_mmc.c +++ b/components/drivers/sdio/dev_mmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2026, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -270,6 +270,64 @@ static int mmc_parse_ext_csd(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) return 0; } +/* + * Send Status. + */ +static int mmc_send_status(struct rt_mmcsd_card *card, rt_uint32_t *status, unsigned retries) +{ + int err; + struct rt_mmcsd_cmd cmd = (struct rt_mmcsd_cmd){ 0 }; + + cmd.busy_timeout = 0; + cmd.cmd_code = SEND_STATUS; + cmd.arg = card->rca << 16; + cmd.flags = RESP_R1 | CMD_AC; + err = mmcsd_send_cmd(card->host, &cmd, retries); + if (err) + return err; + + if (status) + *status = cmd.resp[0]; + + return 0; +} + +/* + * Poll Busy. + */ +static int mmc_poll_for_busy(struct rt_mmcsd_card *card, rt_uint32_t timeout_ms, unsigned retries) +{ + int timeout = rt_tick_from_millisecond(timeout_ms); + int err = 0; + rt_uint32_t status; + rt_tick_t start; + + start = rt_tick_get(); + do + { + rt_bool_t out = (int)(rt_tick_get() - start) >= timeout; + + if (out) + { + LOG_E("wait card busy timeout"); + return -RT_ETIMEOUT; + } + + rt_thread_mdelay(1); + + err = mmc_send_status(card, &status, retries); + if (R1_STATUS(err)) + { + LOG_E("error %d requesting status", err); + return err; + } + } + while (!(status & R1_READY_FOR_DATA) || + (R1_CURRENT_STATE(status) == R1_STATE_PRG)); + + return err; +} + /** * mmc_switch - modify EXT_CSD register * @card: the MMC card associated with the data transfer @@ -295,6 +353,13 @@ static int mmc_switch(struct rt_mmcsd_card *card, rt_uint8_t set, if (err) return err; + /* + * Poll the card status using CMD13 with a timeout of 500ms and a polling interval of 1ms. + */ + err = mmc_poll_for_busy(card, 500, 3); + if (err) + return err; + return 0; } @@ -490,7 +555,7 @@ rt_err_t mmc_send_op_cond(struct rt_mmcsd_host *host, err = -RT_ETIMEOUT; - rt_thread_mdelay(10); //delay 10ms + rt_thread_mdelay(10); /* delay 10ms */ } if (rocr && !controller_is_spi(host)) @@ -815,3 +880,4 @@ err: return err; } + -- Gitee From 2b95c3409c24afd18a061eb03ec96af019798d88 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Mon, 5 Jan 2026 10:34:16 +0800 Subject: [PATCH 21/45] fix[dfs_v1]: prevent vnode ref underflow and double release on close/fd release --- components/dfs/dfs_v1/src/dfs.c | 7 +++++-- components/dfs/dfs_v1/src/dfs_file.c | 7 ++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/components/dfs/dfs_v1/src/dfs.c b/components/dfs/dfs_v1/src/dfs.c index 3783179315..9a7c98cc33 100644 --- a/components/dfs/dfs_v1/src/dfs.c +++ b/components/dfs/dfs_v1/src/dfs.c @@ -414,13 +414,16 @@ void fdt_fd_release(struct dfs_fdtable* fdt, int fd) if (fd_slot->ref_count == 0) { struct dfs_vnode *vnode = fd_slot->vnode; + fd_slot->vnode = RT_NULL; if (vnode) { - vnode->ref_count--; + if (vnode->ref_count > 0) + { + vnode->ref_count--; + } if(vnode->ref_count == 0) { rt_free(vnode); - fd_slot->vnode = RT_NULL; } } rt_free(fd_slot); diff --git a/components/dfs/dfs_v1/src/dfs_file.c b/components/dfs/dfs_v1/src/dfs_file.c index 75bbd219bc..f1c4e7ee4d 100644 --- a/components/dfs/dfs_v1/src/dfs_file.c +++ b/components/dfs/dfs_v1/src/dfs_file.c @@ -337,7 +337,7 @@ int dfs_file_close(struct dfs_file *fd) dfs_fm_lock(); vnode = fd->vnode; - if (vnode->ref_count <= 0) + if (vnode == NULL || vnode->ref_count <= 0) { dfs_fm_unlock(); return -ENXIO; @@ -348,11 +348,12 @@ int dfs_file_close(struct dfs_file *fd) result = vnode->fops->close(fd); } - if (vnode->ref_count == 1) + vnode->ref_count--; + fd->vnode = NULL; + if (vnode->ref_count == 0) { /* remove from hash */ rt_list_remove(&vnode->list); - fd->vnode = NULL; if (vnode->path != vnode->fullpath) { -- Gitee From 1eaa85c581a4bf5d0378084fc418105685273a0e Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Mon, 2 Feb 2026 15:31:45 +0800 Subject: [PATCH 22/45] feat[STM32][CAN]: drain RX FIFO frames in ISR with a bounded limit to reduce overruns - Add CAN_ISR_DRAIN_LIMIT (default 3) to cap ISR work - Drain multiple frames per RX0/RX1 interrupt to reduce FIFO FULL/OVERRUN --- .../libraries/HAL_Drivers/drivers/drv_can.c | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_can.c index 72d89316b2..97c06dadf6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_can.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_can.c @@ -15,6 +15,7 @@ * 2021-8-25 SVCHAO The baud rate is configured according to the different APB1 frequencies. f4-series only. * 2025-09-20 wdfk_prog Implemented sendmsg_nonblocking op to support framework's async TX. + * 2026-02-02 wdfk_prog Drain multiple RX frames per ISR with a bounded limit. */ #include "drv_can.h" @@ -24,6 +25,14 @@ #define LOG_TAG "drv_can" #include +#ifndef CAN_ISR_DRAIN_LIMIT +/* + * bxCAN FIFO depth is 3 (FMP[1:0]=0..3). Draining up to 3 frames can clear the FIFO in one ISR, + * reducing FULL/OVERRUN without letting ISR time grow unbounded. + */ +#define CAN_ISR_DRAIN_LIMIT 3 +#endif + /* attention !!! baud calculation example: Tclk / ((ss + bs1 + bs2) * brp) = 36 / ((1 + 8 + 3) * 3) = 1MHz*/ #if defined (SOC_SERIES_STM32F1)/* APB1 36MHz(max) */ static const struct stm32_baud_rate_tab can_baud_rate_tab[] = @@ -745,10 +754,20 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) switch (fifo) { case CAN_RX_FIFO0: - /* save to user list */ - if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_MSG_PENDING)) + /* save to user list: drain multiple frames per ISR to reduce FULL/OVERRUN */ + if (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_MSG_PENDING)) { - rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + for (rt_uint32_t i = 0; i < CAN_ISR_DRAIN_LIMIT; i++) + { + if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO0) == 0) + { + break; + } + else + { + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + } } /* Check FULL flag for FIFO0 */ if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_FULL)) @@ -766,10 +785,20 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) } break; case CAN_RX_FIFO1: - /* save to user list */ - if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_MSG_PENDING)) + /* save to user list: drain multiple frames per ISR to reduce FULL/OVERRUN */ + if (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_MSG_PENDING)) { - rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + for (rt_uint32_t i = 0; i < CAN_ISR_DRAIN_LIMIT; i++) + { + if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO1) == 0) + { + break; + } + else + { + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + } + } } /* Check FULL flag for FIFO1 */ if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_FULL)) -- Gitee From 06e829b1b3d8bfd39c9e602baf23fe34a669a291 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Mon, 2 Feb 2026 15:32:10 +0800 Subject: [PATCH 23/45] docs(can): improve dev_can.h docs for batched RX example --- components/drivers/include/drivers/dev_can.h | 38 +++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/components/drivers/include/drivers/dev_can.h b/components/drivers/include/drivers/dev_can.h index 9bf0c162cb..4ec5103e7b 100644 --- a/components/drivers/include/drivers/dev_can.h +++ b/components/drivers/include/drivers/dev_can.h @@ -132,22 +132,42 @@ enum CANBAUD * res = rt_device_control(can_dev, RT_CAN_CMD_START, &cmd_arg); * RT_ASSERT(res == RT_EOK); * + * #define CAN_RX_BATCH_SIZE 8 + * * while (1) * { * // Block and wait for the semaphore, which is released by the receive callback. * rt_sem_take(&rx_sem, RT_WAITING_FOREVER); * - * // Read one frame of data from the CAN device's general message queue. - * rx_msg.hdr_index = -1; - * rt_device_read(can_dev, 0, &rx_msg, sizeof(rx_msg)); - * - * // Print the received message's ID and data. - * rt_kprintf("Received a message. ID: 0x%x, Data: ", rx_msg.id); - * for (int i = 0; i < rx_msg.len; i++) + * // Drain all pending frames in batches. + * struct rt_can_msg rx_buf[CAN_RX_BATCH_SIZE]; + * rt_ssize_t read_size; + * rt_size_t count; + * do * { - * rt_kprintf("%02x ", rx_msg.data[i]); + * for (rt_size_t i = 0; i < CAN_RX_BATCH_SIZE; i++) + * { + * rx_buf[i].hdr_index = -1; + * } + * + * read_size = rt_device_read(can_dev, 0, rx_buf, sizeof(rx_buf)); + * if (read_size <= 0) + * { + * break; + * } + * count = (rt_size_t)(read_size / sizeof(rx_buf[0])); + * for (rt_size_t i = 0; i < count; i++) + * { + * // Print the received message's ID and data. + * rt_kprintf("Received a message. ID: 0x%x, Data: ", rx_buf[i].id); + * for (int j = 0; j < rx_buf[i].len; j++) + * { + * rt_kprintf("%02x ", rx_buf[i].data[j]); + * } + * rt_kprintf("\n"); + * } * } - * rt_kprintf("\n"); + * while(count == CAN_RX_BATCH_SIZE); * } * } * -- Gitee From f9de2909915079449aae444eeefd361b66e239f0 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Tue, 3 Feb 2026 14:43:02 +0800 Subject: [PATCH 24/45] fix[STM32][RTC]: Compute tv_usec from SecondFraction/SubSeconds and skip during shift pending Use the generic SecondFraction/SubSeconds formula when SSR/PRER are available. If SHPF is present and a shift is pending, keep tv_usec at 0. Platforms without SSR/PRER (e.g. F1) default to 0. --- .../libraries/HAL_Drivers/drivers/drv_rtc.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c index b86c4ba93b..fcf3494458 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_rtc.c @@ -10,6 +10,7 @@ * 2021-02-05 Meco Man fix the problem of mixing local time and UTC time * 2021-07-05 iysheng implement RTC framework V2.0 * 2025-06-05 RCSN add local time conversion for get timeval and set stamp + * 0206-02-03 wdfk_prog compute tv_usec from SecondFraction/SubSeconds */ #include "board.h" @@ -85,10 +86,30 @@ static rt_err_t stm32_rtc_get_timeval(struct timeval *tv) #else tv->tv_sec = timegm(&tm_new); #endif -#if defined(SOC_SERIES_STM32H7) - tv->tv_usec = (255.0 - RTC_TimeStruct.SubSeconds * 1.0) / 256.0 * 1000.0 * 1000.0; -#endif - + tv->tv_usec = 0U; +/* F1 RTC does not have SSR/PRER */ +#if defined(RTC_SSR_SS) && defined(RTC_PRER_PREDIV_S) + /* + * You can use SubSeconds and SecondFraction (sTime structure fields + * returned) to convert SubSeconds value in second fraction ratio with + * time unit following generic formula: + * Second fraction ratio * time_unit = + * [(SecondFraction - SubSeconds) / (SecondFraction + 1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS + */ +#if defined(RTC_ISR_SHPF) + if (READ_BIT(RTC->ISR, RTC_ISR_SHPF) == 0U) +#endif /* RTC_ISR_SHPF */ + { + uint32_t sf = RTC_TimeStruct.SecondFraction; + uint32_t ss = RTC_TimeStruct.SubSeconds; + if ((sf != 0U) && (ss <= sf)) + { + tv->tv_usec = (uint32_t)(((sf - ss) * 1000000ULL) / (sf + 1U)); + } + } +#endif /* defined(RTC_SSR_SS) && defined(RTC_PRER_PREDIV_S) */ return RT_EOK; } -- Gitee From 1c0926f223e830b28696542b5e92589b39104b83 Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Tue, 27 Jan 2026 14:43:03 +0800 Subject: [PATCH 25/45] [bsp][gd32]:add gd32vw533xx pwm support --- .../.ci/attachconfig/ci.attachconfig.yml | 9 + bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig | 24 + .../risc-v/libraries/gd32_drivers/SConscript | 4 + .../risc-v/libraries/gd32_drivers/drv_pwm.c | 591 ++++++++++++++++++ 4 files changed, 628 insertions(+) create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml create mode 100644 bsp/gd32/risc-v/libraries/gd32_drivers/drv_pwm.c diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml b/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 0000000000..24dc154586 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,9 @@ +scons.args: &scons + scons_arg: + - '--strict' + +# ------ component CI ------ +component.pwm: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM0=y \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig index 6bb5df4137..8d0f34949a 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig @@ -78,6 +78,30 @@ menu "On-chip Peripheral Drivers" default n endif + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0" + default y + config BSP_USING_PWM1 + bool "Enable PWM1" + default n + config BSP_USING_PWM2 + bool "Enable PWM2" + default n + config BSP_USING_PWM15 + bool "Enable PWM15" + default n + config BSP_USING_PWM16 + bool "Enable PWM16" + default n + endif + + + source "$(BSP_DIR)/../libraries/gd32_drivers/Kconfig" endmenu diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript b/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript index 9148ed9816..4dedb95150 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript @@ -45,6 +45,10 @@ if GetDepend('RT_USING_CLOCK_TIME'): if GetDepend('RT_USING_ADC'): src += ['drv_adc.c'] +# add pwm drivers. +if GetDepend(['RT_USING_PWM', 'SOC_GD32VW553H']): + src += ['drv_pwm.c'] + path = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_pwm.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_pwm.c new file mode 100644 index 0000000000..ac941cdefb --- /dev/null +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_pwm.c @@ -0,0 +1,591 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-27 CYFS first version + */ + +#include +#include +#include + +#ifdef RT_USING_PWM + +#define DBG_TAG "drv.pwm" +#define DBG_LVL DBG_LOG + +#include + +#define MAX_PERIOD 65535 +#define MIN_PERIOD 3 +#define MIN_PULSE 2 + + +typedef struct gd32_pwm_pin +{ + rt_uint32_t Port; + rt_uint32_t pin; + rt_uint32_t alt_func_num; + rt_int16_t channel; + rt_int8_t TimerIndex; + +} gd32_pwm_pin_t; + +static gd32_pwm_pin_t gd32_pwm_pin_obj[] = { +#ifdef BSP_USING_PWM0 + { + .Port = GPIOA, + .pin = GPIO_PIN_9, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_1, + .TimerIndex = 0, + }, + { + .Port = GPIOA, + .pin = GPIO_PIN_10, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_2, + .TimerIndex = 0, + }, + { + .Port = GPIOA, + .pin = GPIO_PIN_11, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_3, + .TimerIndex = 0, + }, +#endif + +#ifdef BSP_USING_PWM1 +{ + .Port = GPIOA, + .pin = GPIO_PIN_0, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_0, + .TimerIndex = 1, + }, + { + .Port = GPIOA, + .pin = GPIO_PIN_1, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_1, + .TimerIndex = 1, + }, + { + .Port = GPIOA, + .pin = GPIO_PIN_2, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_2, + .TimerIndex = 1, + }, + { + .Port = GPIOA, + .pin = GPIO_PIN_3, + .alt_func_num = GPIO_AF_1, + .channel = TIMER_CH_3, + .TimerIndex = 1, + }, +#endif + +#ifdef BSP_USING_PWM2 + { + .Port = GPIOA, + .pin = GPIO_PIN_6, + .alt_func_num = GPIO_AF_2, + .channel = TIMER_CH_0, + .TimerIndex = 2, + }, + { + .Port = GPIOA, + .pin = GPIO_PIN_7, + .alt_func_num = GPIO_AF_2, + .channel = TIMER_CH_1, + .TimerIndex = 2, + }, + +#endif + +#ifdef BSP_USING_PWM15 + { + .Port = GPIOB, + .pin = GPIO_PIN_13, + .alt_func_num = GPIO_AF_8, + .channel = TIMER_CH_0, + .TimerIndex = 15, + }, +#endif + +#ifdef BSP_USING_PWM16 + { + .Port = GPIOB, + .pin = GPIO_PIN_0, + .alt_func_num = GPIO_AF_9, + .channel = TIMER_CH_0, + .TimerIndex = 16, + }, +#endif + +}; + +typedef struct gd32_pwm_device +{ + struct rt_device_pwm pwm_device; + rt_int8_t TimerIndex; + char *name; +} gd32_pwm_device_t; + + +static gd32_pwm_device_t gd32_pwm_obj[] = { +#ifdef BSP_USING_PWM0 + { + .name = "pwm0", + .TimerIndex = 0, + }, +#endif +#ifdef BSP_USING_PWM1 + { + .name = "pwm1", + .TimerIndex = 1, + }, +#endif +#ifdef BSP_USING_PWM2 + { + .name = "pwm2", + .TimerIndex = 2, + }, +#endif +#ifdef BSP_USING_PWM15 + { + .name = "pwm15", + .TimerIndex = 15, + }, +#endif +#ifdef BSP_USING_PWM16 + { + .name = "pwm16", + .TimerIndex = 16, + }, +#endif +}; + +typedef struct +{ + rt_uint32_t Port[3]; + rt_int8_t TimerIndex[5]; +} TIMER_PERIPH_LIST_S; + +static TIMER_PERIPH_LIST_S gd32_timer_periph_list = { + .Port = {0, 0, 0}, + .TimerIndex = {-1, -1, -1, -1, -1}, +}; + +/* + * List all used GPIO ports and timers without duplication to avoid repeated initialization later. + */ +static rt_err_t pwm_find_timer_periph(void) +{ + rt_int16_t i, j, k; + + /* find gpio port of defined table */ + for (i = 0; i < sizeof(gd32_pwm_pin_obj) / sizeof(gd32_pwm_pin_obj[0]); ++i) + { + /* find -1 of gd32_periph_list's member of Port */ + for (j = 0; j < sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]); ++j) + { + if (0 == gd32_timer_periph_list.Port[j]) + { + break; + } + } + + if (j >= sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0])) + { + LOG_E("Can not find -1 of gd32_periph_list's member of Port!\n"); + break; + } + + /* find the different of Port */ + for (k = 0; k < j; ++k) + { + if (gd32_pwm_pin_obj[i].Port == gd32_timer_periph_list.Port[k]) + { + break; + } + } + + /* if can not find the same Port */ + if (k == j) + { + gd32_timer_periph_list.Port[j] = gd32_pwm_pin_obj[i].Port; + } + } + + /* find timer periph of defined table */ + for (i = 0; i < sizeof(gd32_pwm_pin_obj) / sizeof(gd32_pwm_pin_obj[0]); ++i) + { + /* find -1 of gd32_periph_list's member of TimerIndex */ + for (j = 0; j < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++j) + { + if (-1 == gd32_timer_periph_list.TimerIndex[j]) + { + break; + } + } + + if (j >= sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0])) + { + LOG_E("Can not find -1 of gd32_periph_list's member of TimerIndex!\n"); + break; + } + + /* find the different of TimerIndex */ + for (k = 0; k < j; ++k) + { + if (gd32_pwm_pin_obj[i].TimerIndex == gd32_timer_periph_list.TimerIndex[k]) + { + break; + } + } + + /* if can not find the same TimerIndex */ + if (k == j) + { + gd32_timer_periph_list.TimerIndex[j] = gd32_pwm_pin_obj[i].TimerIndex; + } + } + + return RT_EOK; +} +static rt_uint32_t index_to_timer(rt_int8_t TimerIndex) +{ + switch (TimerIndex) + { + case 0: + return TIMER0; + case 1: + return TIMER1; + case 2: + return TIMER2; + case 15: + return TIMER15; + case 16: + return TIMER16; + default: + LOG_E("Unsupported timer periph!\n"); + } + return TIMER0; +} + +static void gpio_clock_enable(rt_uint32_t Port) +{ + switch (Port) + { + case GPIOA: + rcu_periph_clock_enable(RCU_GPIOA); + break; + case GPIOB: + rcu_periph_clock_enable(RCU_GPIOB); + break; + case GPIOC: + rcu_periph_clock_enable(RCU_GPIOC); + break; + default: + LOG_E("Unsupported gpio port!\n"); + } +} + +static void timer_clock_enable(rt_int8_t TimerIndex) +{ + switch (TimerIndex) + { + case 0: + rcu_periph_clock_enable(RCU_TIMER0); + break; + case 1: + rcu_periph_clock_enable(RCU_TIMER1); + break; + case 2: + rcu_periph_clock_enable(RCU_TIMER2); + break; + case 15: + rcu_periph_clock_enable(RCU_TIMER15); + break; + case 16: + rcu_periph_clock_enable(RCU_TIMER16); + break; + default: + LOG_E("Unsport timer periph!\n"); + } +} +static void gpio_config(void) +{ + rt_int16_t i; + /* configure GPIO pins in alternate-function mode for TIMER PWM output */ + for (i = 0; i < sizeof(gd32_pwm_pin_obj) / sizeof(gd32_pwm_pin_obj[0]); ++i) + { + /* configure pin as alternate function for the corresponding TIMER channel */ + gpio_mode_set(gd32_pwm_pin_obj[i].Port, GPIO_MODE_AF, GPIO_PUPD_NONE, gd32_pwm_pin_obj[i].pin); + gpio_output_options_set(gd32_pwm_pin_obj[i].Port, GPIO_OTYPE_PP, GPIO_OSPEED_MAX, gd32_pwm_pin_obj[i].pin); + gpio_af_set(gd32_pwm_pin_obj[i].Port, gd32_pwm_pin_obj[i].alt_func_num, gd32_pwm_pin_obj[i].pin); + } +} + +static void rcu_config(void) +{ + rt_int16_t i; + rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL4); + for (i = 0; i < sizeof(gd32_timer_periph_list.Port) / sizeof(gd32_timer_periph_list.Port[0]); ++i) + { + if (0 == gd32_timer_periph_list.Port[i]) + { + break; + } + + /* enable GPIO clock */ + gpio_clock_enable(gd32_timer_periph_list.Port[i]); + } + + for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i) + { + if (-1 == gd32_timer_periph_list.TimerIndex[i]) + { + break; + } + + /* enable timer clock */ + timer_clock_enable(gd32_timer_periph_list.TimerIndex[i]); + timer_deinit(index_to_timer(gd32_timer_periph_list.TimerIndex[i])); + } +} + +static void timer_init_para(timer_parameter_struct *initpara) +{ + rt_int16_t i; + + for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i) + { + /* config timer */ + if (-1 != gd32_timer_periph_list.TimerIndex[i]) + { + timer_init(index_to_timer(gd32_timer_periph_list.TimerIndex[i]), initpara); + } + } +} + +static void channel_output_config(timer_oc_parameter_struct *ocpara) +{ + rt_int16_t i; + rt_uint32_t timer_periph; + + /* config the channel config */ + for (i = 0; i < sizeof(gd32_pwm_pin_obj) / sizeof(gd32_pwm_pin_obj[0]); ++i) + { + + timer_periph = index_to_timer(gd32_pwm_pin_obj[i].TimerIndex); + timer_channel_output_config(timer_periph, gd32_pwm_pin_obj[i].channel, ocpara); + + timer_channel_output_pulse_value_config(timer_periph, gd32_pwm_pin_obj[i].channel, 7999); + timer_channel_output_mode_config(timer_periph, gd32_pwm_pin_obj[i].channel, TIMER_OC_MODE_PWM0); + timer_channel_output_shadow_config(timer_periph, gd32_pwm_pin_obj[i].channel, TIMER_OC_SHADOW_DISABLE); + /* auto-reload preload shadow reg enable */ + /* timer_auto_reload_shadow_enable(timer_periph); */ + timer_channel_output_state_config(timer_periph, gd32_pwm_pin_obj[i].channel, TIMER_CCX_DISABLE); + timer_channel_complementary_output_state_config(timer_periph, gd32_pwm_pin_obj[i].channel, TIMER_CCXN_DISABLE); + } + + /* enable timer */ + for (i = 0; i < sizeof(gd32_timer_periph_list.TimerIndex) / sizeof(gd32_timer_periph_list.TimerIndex[0]); ++i) + { + if (-1 != gd32_timer_periph_list.TimerIndex[i]) + { + timer_periph = index_to_timer(gd32_timer_periph_list.TimerIndex[i]); + if (timer_periph == TIMER0) + { + timer_primary_output_config(timer_periph, ENABLE); + } + timer_enable(timer_periph); + } + } +} + +static void timer_config(void) +{ + timer_oc_parameter_struct timer_ocintpara; + timer_parameter_struct timer_initpara; + + /* TIMER configuration */ + timer_initpara.prescaler = 119; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 15999; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_initpara.repetitioncounter = 0; + timer_init_para(&timer_initpara); + + /* CHX configuration in PWM mode */ + timer_ocintpara.outputstate = TIMER_CCX_ENABLE; + timer_ocintpara.outputnstate = TIMER_CCXN_DISABLE; + timer_ocintpara.ocpolarity = TIMER_OC_POLARITY_HIGH; + timer_ocintpara.ocnpolarity = TIMER_OCN_POLARITY_HIGH; + timer_ocintpara.ocidlestate = TIMER_OC_IDLE_STATE_LOW; + timer_ocintpara.ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; + channel_output_config(&timer_ocintpara); +} + +static rt_err_t gd32_hw_pwm_init(void) +{ + pwm_find_timer_periph(); + rcu_config(); + gpio_config(); + timer_config(); + return RT_EOK; +} + +static rt_err_t drv_pwm_enable(gd32_pwm_device_t *pstTimerMap, + struct rt_pwm_configuration *configuration, + rt_bool_t enable) +{ + uint32_t timer_periph = index_to_timer(pstTimerMap->TimerIndex); + uint32_t channel = configuration->channel; + + if ((channel != TIMER_CH_0) && + (channel != TIMER_CH_1) && + (channel != TIMER_CH_2) && + (channel != TIMER_CH_3)) + { + return -RT_EINVAL; + } + + if (enable) + { + timer_channel_output_state_config(timer_periph, channel, TIMER_CCX_ENABLE); + } + else + { + timer_channel_output_state_config(timer_periph, channel, TIMER_CCX_DISABLE); + } + + return RT_EOK; +} + +static rt_err_t drv_pwm_set(gd32_pwm_device_t *pstTimerMap, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t tim_clock, psc; + tim_clock = rcu_clock_freq_get(CK_SYS); + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL; + psc = period / MAX_PERIOD + 1; + period = period / psc; + + timer_prescaler_config(index_to_timer(pstTimerMap->TimerIndex), psc - 1, TIMER_PSC_RELOAD_NOW); + + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + + timer_autoreload_value_config(index_to_timer(pstTimerMap->TimerIndex), period - 1); + + pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL; + if (pulse < MIN_PULSE) + { + pulse = MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + + timer_channel_output_pulse_value_config(index_to_timer(pstTimerMap->TimerIndex), configuration->channel, pulse); + timer_counter_value_config(index_to_timer(pstTimerMap->TimerIndex), 0); + + /* Update frequency value */ + timer_event_software_generate(index_to_timer(pstTimerMap->TimerIndex), TIMER_EVENT_SRC_UPG); + + return RT_EOK; +} + + +static rt_err_t drv_pwm_get(gd32_pwm_device_t *pstTimerMap, struct rt_pwm_configuration *configuration) +{ + rt_uint64_t tim_clock; + rt_uint16_t psc; + rt_uint32_t chxcv; + + tim_clock = rcu_clock_freq_get(CK_SYS); + + psc = timer_prescaler_read(index_to_timer(pstTimerMap->TimerIndex)); + if (psc == TIMER_CKDIV_DIV2) + { + tim_clock = tim_clock / 2; + } + else if (psc == TIMER_CKDIV_DIV4) + { + tim_clock = tim_clock / 4; + } + + chxcv = timer_channel_capture_value_register_read(index_to_timer(pstTimerMap->TimerIndex), configuration->channel); + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + configuration->period = (TIMER_CAR(index_to_timer(pstTimerMap->TimerIndex)) + 1) * (psc + 1) * 1000UL / tim_clock; + configuration->pulse = (chxcv + 1) * (psc + 1) * 1000UL / tim_clock; + + return RT_EOK; +} + + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + gd32_pwm_device_t *pstTimerMap = (gd32_pwm_device_t *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable(pstTimerMap, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable(pstTimerMap, configuration, RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set(pstTimerMap, configuration); + case PWM_CMD_GET: + return drv_pwm_get(pstTimerMap, configuration); + default: + return -RT_EINVAL; +} +} + +static struct rt_pwm_ops drv_ops = {drv_pwm_control}; + +static int gd32_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + /* pwm init */ + gd32_hw_pwm_init(); + LOG_D("PWM init success"); + + for (i = 0; i < sizeof(gd32_pwm_obj) / sizeof(gd32_pwm_obj[0]); i++) + { + if (rt_device_pwm_register(&gd32_pwm_obj[i].pwm_device, gd32_pwm_obj[i].name, &drv_ops, &gd32_pwm_obj[i]) == RT_EOK) + { + LOG_D("%s register success", gd32_pwm_obj[i].name); + } + else + { + LOG_E("%s register failed", gd32_pwm_obj[i].name); + result = -RT_ERROR; + } + } + return result; +} + +INIT_DEVICE_EXPORT(gd32_pwm_init); + +#endif /* RT_USING_PWM */ \ No newline at end of file -- Gitee From 4d063acc297165c5125163f4a36a2465357781f5 Mon Sep 17 00:00:00 2001 From: Onlyou_tzZ <97173915+OnlyoutzZ@users.noreply.github.com> Date: Tue, 3 Feb 2026 18:56:53 +0800 Subject: [PATCH 26/45] Update Nsing's BSP architecture and add N32H7xx series BSPs. (#11159) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * 更新国民技术BSP架构，添加N32H7xx系列BSP * 修改clang_format-ignore文件,根据反馈修改n32h7xxx/libraries/N32_Drivers/nano/*下的文件格式，修改n32h7xxx/n32/n32hxxx/n32h760zil7-stb/applications/main.c文件，区别处理Nano下头文件包含 * 将N32 BSP的.clang-format-ignore文件放入libraries同级目录 * 忽略库文件格式检查 * 解决N32 BSP project.ewp和project.uvprojx冲突 * 更新RTT最新同步 --- .github/ALL_BSP_COMPILE.json | 25 +- bsp/n32/n32g45xcl-stb/project.uvoptx | 185 - bsp/n32/n32g45xml-stb/project.uvoptx | 185 - bsp/n32/n32g45xrl-stb/Kconfig | 12 - bsp/n32/n32g45xrl-stb/project.uvoptx | 185 - bsp/n32/n32g45xrl-stb/rtconfig.py | 184 - bsp/n32/n32g45xvl-stb/Kconfig | 12 - bsp/n32/n32g45xvl-stb/project.uvoptx | 185 - bsp/n32/n32g45xvl-stb/rtconfig.py | 184 - bsp/n32/n32g4frml-stb/Kconfig | 12 - bsp/n32/n32g4frml-stb/project.ewp | 2474 -- bsp/n32/n32g4frml-stb/rtconfig.py | 184 - bsp/n32/{ => n32gxx_lxx}/.clang-format-ignore | 7 +- bsp/n32/{ => n32gxx_lxx}/libraries/Kconfig | 0 .../CMSIS/core/arm_common_tables.h | 0 .../CMSIS/core/arm_const_structs.h | 0 .../CMSIS/core/arm_math.h | 0 .../CMSIS/core/cmsis_armcc.h | 0 .../CMSIS/core/cmsis_armclang.h | 0 .../CMSIS/core/cmsis_compiler.h | 0 .../CMSIS/core/cmsis_gcc.h | 0 .../CMSIS/core/cmsis_iccarm.h | 0 .../CMSIS/core/cmsis_version.h | 0 .../CMSIS/core/core_cm4.h | 0 .../CMSIS/core/mpu_armv7.h | 0 .../CMSIS/device/n32g43x.h | 0 .../CMSIS/device/n32g43x_conf.h | 0 .../CMSIS/device/n32g43x_flash.ld | 0 .../CMSIS/device/startup/startup_n32g43x.s | 0 .../device/startup/startup_n32g43x_EWARM.s | 0 .../device/startup/startup_n32g43x_gcc.s | 0 .../CMSIS/device/system_n32g43x.c | 0 .../CMSIS/device/system_n32g43x.h | 0 .../N32G43x_Firmware_Library/SConscript | 0 .../n32g43x_algo_lib/inc/n32g43x_aes.h | 0 .../inc/n32g43x_algo_common.h | 0 .../n32g43x_algo_lib/inc/n32g43x_des.h | 0 .../n32g43x_algo_lib/inc/n32g43x_hash.h | 0 .../n32g43x_algo_lib/inc/n32g43x_rng.h | 0 .../n32g43x_std_periph_driver/inc/misc.h | 0 .../inc/n32g43x_adc.h | 0 .../inc/n32g43x_can.h | 0 .../inc/n32g43x_comp.h | 0 .../inc/n32g43x_crc.h | 0 .../inc/n32g43x_dac.h | 0 .../inc/n32g43x_dbg.h | 0 .../inc/n32g43x_dma.h | 0 .../inc/n32g43x_exti.h | 0 .../inc/n32g43x_flash.h | 0 .../inc/n32g43x_gpio.h | 0 .../inc/n32g43x_i2c.h | 0 .../inc/n32g43x_iwdg.h | 0 .../inc/n32g43x_lptim.h | 0 .../inc/n32g43x_lpuart.h | 0 .../inc/n32g43x_opamp.h | 0 .../inc/n32g43x_pwr.h | 0 .../inc/n32g43x_rcc.h | 0 .../inc/n32g43x_rtc.h | 0 .../inc/n32g43x_spi.h | 0 .../inc/n32g43x_tim.h | 0 .../inc/n32g43x_tsc.h | 0 .../inc/n32g43x_usart.h | 0 .../inc/n32g43x_wwdg.h | 0 .../n32g43x_std_periph_driver/src/misc.c | 0 .../src/n32g43x_adc.c | 0 .../src/n32g43x_can.c | 0 .../src/n32g43x_comp.c | 0 .../src/n32g43x_crc.c | 0 .../src/n32g43x_dac.c | 0 .../src/n32g43x_dbg.c | 0 .../src/n32g43x_dma.c | 0 .../src/n32g43x_exti.c | 0 .../src/n32g43x_flash.c | 0 .../src/n32g43x_gpio.c | 0 .../src/n32g43x_i2c.c | 0 .../src/n32g43x_iwdg.c | 0 .../src/n32g43x_lptim.c | 0 .../src/n32g43x_lpuart.c | 0 .../src/n32g43x_opamp.c | 0 .../src/n32g43x_pwr.c | 0 .../src/n32g43x_rcc.c | 0 .../src/n32g43x_rtc.c | 0 .../src/n32g43x_spi.c | 0 .../src/n32g43x_tim.c | 0 .../src/n32g43x_tsc.c | 0 .../src/n32g43x_usart.c | 0 .../src/n32g43x_wwdg.c | 0 .../n32g43x_usbfs_driver/inc/usb_core.h | 0 .../n32g43x_usbfs_driver/inc/usb_def.h | 0 .../n32g43x_usbfs_driver/inc/usb_init.h | 0 .../n32g43x_usbfs_driver/inc/usb_int.h | 0 .../n32g43x_usbfs_driver/inc/usb_lib.h | 0 .../n32g43x_usbfs_driver/inc/usb_mem.h | 0 .../n32g43x_usbfs_driver/inc/usb_regs.h | 0 .../n32g43x_usbfs_driver/inc/usb_sil.h | 0 .../n32g43x_usbfs_driver/inc/usb_type.h | 0 .../n32g43x_usbfs_driver/src/usb_core.c | 0 .../n32g43x_usbfs_driver/src/usb_init.c | 0 .../n32g43x_usbfs_driver/src/usb_int.c | 0 .../n32g43x_usbfs_driver/src/usb_mem.c | 0 .../n32g43x_usbfs_driver/src/usb_regs.c | 0 .../n32g43x_usbfs_driver/src/usb_sil.c | 0 .../CMSIS/core/arm_common_tables.h | 0 .../CMSIS/core/arm_const_structs.h | 0 .../CMSIS/core/arm_math.h | 0 .../CMSIS/core/cmsis_armcc.h | 0 .../CMSIS/core/cmsis_armclang.h | 0 .../CMSIS/core/cmsis_compiler.h | 0 .../CMSIS/core/cmsis_gcc.h | 0 .../CMSIS/core/cmsis_iccarm.h | 0 .../CMSIS/core/cmsis_version.h | 0 .../CMSIS/core/core_cm4.h | 0 .../CMSIS/core/mpu_armv7.h | 0 .../CMSIS/device/n32g45x.h | 0 .../CMSIS/device/n32g45x_conf.h | 0 .../CMSIS/device/n32g45x_flash.ld | 0 .../CMSIS/device/startup/startup_n32g45x.s | 0 .../device/startup/startup_n32g45x_EWARM.s | 0 .../device/startup/startup_n32g45x_gcc.s | 0 .../CMSIS/device/system_n32g45x.c | 0 .../CMSIS/device/system_n32g45x.h | 0 .../N32G45x_Firmware_Library/SConscript | 0 .../n32g45x_algo_lib/inc/n32g45x_aes.h | 0 .../inc/n32g45x_algo_common.h | 0 .../n32g45x_algo_lib/inc/n32g45x_des.h | 0 .../n32g45x_algo_lib/inc/n32g45x_hash.h | 0 .../n32g45x_algo_lib/inc/n32g45x_rng.h | 0 .../n32g45x_std_periph_driver/inc/misc.h | 0 .../inc/n32g45x_adc.h | 0 .../inc/n32g45x_bkp.h | 0 .../inc/n32g45x_can.h | 0 .../inc/n32g45x_comp.h | 0 .../inc/n32g45x_crc.h | 0 .../inc/n32g45x_dac.h | 0 .../inc/n32g45x_dbg.h | 0 .../inc/n32g45x_dma.h | 0 .../inc/n32g45x_dvp.h | 0 .../inc/n32g45x_eth.h | 0 .../inc/n32g45x_exti.h | 0 .../inc/n32g45x_flash.h | 0 .../inc/n32g45x_gpio.h | 0 .../inc/n32g45x_i2c.h | 0 .../inc/n32g45x_iwdg.h | 0 .../inc/n32g45x_opamp.h | 0 .../inc/n32g45x_pwr.h | 0 .../inc/n32g45x_qspi.h | 0 .../inc/n32g45x_rcc.h | 0 .../inc/n32g45x_rtc.h | 0 .../inc/n32g45x_sdio.h | 0 .../inc/n32g45x_spi.h | 0 .../inc/n32g45x_tim.h | 0 .../inc/n32g45x_tsc.h | 0 .../inc/n32g45x_usart.h | 0 .../inc/n32g45x_wwdg.h | 0 .../inc/n32xx_tsc_alg_api.h | 0 .../n32g45x_std_periph_driver/src/misc.c | 0 .../src/n32g45x_adc.c | 0 .../src/n32g45x_bkp.c | 0 .../src/n32g45x_can.c | 0 .../src/n32g45x_comp.c | 0 .../src/n32g45x_crc.c | 0 .../src/n32g45x_dac.c | 0 .../src/n32g45x_dbg.c | 0 .../src/n32g45x_dma.c | 0 .../src/n32g45x_dvp.c | 0 .../src/n32g45x_eth.c | 0 .../src/n32g45x_exti.c | 0 .../src/n32g45x_flash.c | 0 .../src/n32g45x_gpio.c | 0 .../src/n32g45x_i2c.c | 0 .../src/n32g45x_iwdg.c | 0 .../src/n32g45x_opamp.c | 0 .../src/n32g45x_pwr.c | 0 .../src/n32g45x_qspi.c | 0 .../src/n32g45x_rcc.c | 0 .../src/n32g45x_rtc.c | 0 .../src/n32g45x_sdio.c | 0 .../src/n32g45x_spi.c | 0 .../src/n32g45x_tim.c | 0 .../src/n32g45x_tsc.c | 0 .../src/n32g45x_usart.c | 0 .../src/n32g45x_wwdg.c | 0 .../n32g45x_usbfs_driver/inc/usb_core.h | 0 .../n32g45x_usbfs_driver/inc/usb_def.h | 0 .../n32g45x_usbfs_driver/inc/usb_init.h | 0 .../n32g45x_usbfs_driver/inc/usb_int.h | 0 .../n32g45x_usbfs_driver/inc/usb_lib.h | 0 .../n32g45x_usbfs_driver/inc/usb_mem.h | 0 .../n32g45x_usbfs_driver/inc/usb_regs.h | 0 .../n32g45x_usbfs_driver/inc/usb_sil.h | 0 .../n32g45x_usbfs_driver/inc/usb_type.h | 0 .../n32g45x_usbfs_driver/src/usb_core.c | 0 .../n32g45x_usbfs_driver/src/usb_init.c | 0 .../n32g45x_usbfs_driver/src/usb_int.c | 0 .../n32g45x_usbfs_driver/src/usb_mem.c | 0 .../n32g45x_usbfs_driver/src/usb_regs.c | 0 .../n32g45x_usbfs_driver/src/usb_sil.c | 0 .../CMSIS/core/arm_common_tables.h | 0 .../CMSIS/core/arm_const_structs.h | 0 .../CMSIS/core/arm_math.h | 0 .../CMSIS/core/cmsis_armcc.h | 0 .../CMSIS/core/cmsis_armclang.h | 0 .../CMSIS/core/cmsis_compiler.h | 0 .../CMSIS/core/cmsis_gcc.h | 0 .../CMSIS/core/cmsis_iccarm.h | 0 .../CMSIS/core/cmsis_version.h | 0 .../CMSIS/core/core_cm4.h | 0 .../CMSIS/core/mpu_armv7.h | 0 .../CMSIS/device/n32g4fr.h | 0 .../CMSIS/device/n32g4fr_conf.h | 0 .../CMSIS/device/n32g4fr_flash.ld | 0 .../CMSIS/device/startup/startup_n32g4fr.s | 0 .../device/startup/startup_n32g4fr_EWARM.s | 0 .../device/startup/startup_n32g4fr_gcc.s | 0 .../CMSIS/device/system_n32g4fr.c | 0 .../CMSIS/device/system_n32g4fr.h | 0 .../N32G4FR_Firmware_Library/SConscript | 0 .../n32g4fr_algo_lib/inc/n32g4fr_aes.h | 0 .../inc/n32g4fr_algo_common.h | 0 .../n32g4fr_algo_lib/inc/n32g4fr_des.h | 0 .../n32g4fr_algo_lib/inc/n32g4fr_hash.h | 0 .../n32g4fr_algo_lib/inc/n32g4fr_rng.h | 0 .../n32g4fr_std_periph_driver/inc/misc.h | 0 .../inc/n32g4fr_adc.h | 0 .../inc/n32g4fr_bkp.h | 0 .../inc/n32g4fr_can.h | 0 .../inc/n32g4fr_crc.h | 0 .../inc/n32g4fr_dac.h | 0 .../inc/n32g4fr_dbg.h | 0 .../inc/n32g4fr_dma.h | 0 .../inc/n32g4fr_dvp.h | 0 .../inc/n32g4fr_exti.h | 0 .../inc/n32g4fr_flash.h | 0 .../inc/n32g4fr_gpio.h | 0 .../inc/n32g4fr_i2c.h | 0 .../inc/n32g4fr_iwdg.h | 0 .../inc/n32g4fr_pwr.h | 0 .../inc/n32g4fr_qspi.h | 0 .../inc/n32g4fr_rcc.h | 0 .../inc/n32g4fr_rtc.h | 0 .../inc/n32g4fr_sdio.h | 0 .../inc/n32g4fr_spi.h | 0 .../inc/n32g4fr_tim.h | 0 .../inc/n32g4fr_tsc.h | 0 .../inc/n32g4fr_usart.h | 0 .../inc/n32g4fr_wwdg.h | 0 .../inc/n32xx_tsc_alg_api.h | 0 .../n32g4fr_std_periph_driver/src/misc.c | 0 .../src/n32g4fr_adc.c | 0 .../src/n32g4fr_bkp.c | 0 .../src/n32g4fr_can.c | 0 .../src/n32g4fr_crc.c | 0 .../src/n32g4fr_dac.c | 0 .../src/n32g4fr_dbg.c | 0 .../src/n32g4fr_dma.c | 0 .../src/n32g4fr_dvp.c | 0 .../src/n32g4fr_exti.c | 0 .../src/n32g4fr_flash.c | 0 .../src/n32g4fr_gpio.c | 0 .../src/n32g4fr_i2c.c | 0 .../src/n32g4fr_iwdg.c | 0 .../src/n32g4fr_pwr.c | 0 .../src/n32g4fr_qspi.c | 0 .../src/n32g4fr_rcc.c | 0 .../src/n32g4fr_rtc.c | 0 .../src/n32g4fr_sdio.c | 0 .../src/n32g4fr_spi.c | 0 .../src/n32g4fr_tim.c | 0 .../src/n32g4fr_tsc.c | 0 .../src/n32g4fr_usart.c | 0 .../src/n32g4fr_wwdg.c | 0 .../n32g4fr_usbfs_driver/inc/usb_core.h | 0 .../n32g4fr_usbfs_driver/inc/usb_def.h | 0 .../n32g4fr_usbfs_driver/inc/usb_init.h | 0 .../n32g4fr_usbfs_driver/inc/usb_int.h | 0 .../n32g4fr_usbfs_driver/inc/usb_lib.h | 0 .../n32g4fr_usbfs_driver/inc/usb_mem.h | 0 .../n32g4fr_usbfs_driver/inc/usb_regs.h | 0 .../n32g4fr_usbfs_driver/inc/usb_sil.h | 0 .../n32g4fr_usbfs_driver/inc/usb_type.h | 0 .../n32g4fr_usbfs_driver/src/usb_core.c | 0 .../n32g4fr_usbfs_driver/src/usb_init.c | 0 .../n32g4fr_usbfs_driver/src/usb_int.c | 0 .../n32g4fr_usbfs_driver/src/usb_mem.c | 0 .../n32g4fr_usbfs_driver/src/usb_regs.c | 0 .../n32g4fr_usbfs_driver/src/usb_sil.c | 0 .../CMSIS/core/arm_common_tables.h | 0 .../CMSIS/core/arm_const_structs.h | 0 .../CMSIS/core/arm_math.h | 0 .../CMSIS/core/cmsis_armcc.h | 0 .../CMSIS/core/cmsis_armclang.h | 0 .../CMSIS/core/cmsis_compiler.h | 0 .../CMSIS/core/cmsis_gcc.h | 0 .../CMSIS/core/cmsis_iccarm.h | 0 .../CMSIS/core/cmsis_version.h | 0 .../CMSIS/core/core_cm4.h | 0 .../CMSIS/core/mpu_armv7.h | 0 .../CMSIS/device/n32l40x.h | 0 .../CMSIS/device/n32l40x_conf.h | 0 .../CMSIS/device/n32l40x_flash.ld | 0 .../CMSIS/device/startup/startup_n32l40x.s | 0 .../device/startup/startup_n32l40x_EWARM.s | 0 .../device/startup/startup_n32l40x_gcc.s | 0 .../CMSIS/device/system_n32l40x.c | 0 .../CMSIS/device/system_n32l40x.h | 0 .../N32L40x_Firmware_Library/SConscript | 0 .../n32l40x_algo_lib/inc/n32l40x_aes.h | 0 .../inc/n32l40x_algo_common.h | 0 .../n32l40x_algo_lib/inc/n32l40x_des.h | 0 .../n32l40x_algo_lib/inc/n32l40x_hash.h | 0 .../n32l40x_algo_lib/inc/n32l40x_rng.h | 0 .../n32l40x_std_periph_driver/inc/misc.h | 0 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.../Driver/CMSIS/core/core_sc000.h | 1025 + .../Driver/CMSIS/core/core_sc300.h | 1912 ++ .../Cube_Config/Driver/CMSIS/core/mpu_armv7.h | 272 + .../Cube_Config/Driver/CMSIS/core/mpu_armv8.h | 346 + .../Driver/CMSIS/core/tz_context.h | 70 + .../Driver/CMSIS/device/n32h76x_78x.h | 27708 ++++++++++++++++ .../CMSIS/device/startup/startup_n32h76x.s | 892 + .../device/startup/startup_n32h76x_EWARM.s | 1529 + .../device/startup/startup_n32h78x_cm4.s | 897 + .../startup/startup_n32h78x_cm4_EWARM.s | 1543 + .../device/startup/startup_n32h78x_cm7.s | 892 + .../startup/startup_n32h78x_cm7_EWARM.s | 1535 + .../Driver/CMSIS/device/system_n32h76x_78x.c | 233 + .../Driver/CMSIS/device/system_n32h76x_78x.h | 79 + .../inc/n32h76x_78x_Common.h | 273 + .../inc/n32h76x_78x_DES.h | 131 + .../inc/n32h76x_78x_HASH.h | 216 + .../inc/n32h76x_78x_RNG.h | 112 + .../inc/n32h76x_78x_SAC_Common.h | 122 + .../inc/n32h76x_78x_SM4.h | 108 + .../inc/n32h76x_78x_aes.h | 119 + .../n32h76x_78x_periph_app/inc/mmc_host.h | 266 + .../n32h76x_78x_periph_app/inc/sd_host.h | 180 + .../n32h76x_78x_periph_app/inc/sdmmc_spec.h | 548 + .../n32h76x_78x_periph_app/src/mmc_host.c | 1272 + .../n32h76x_78x_periph_app/src/sd_host.c | 873 + .../n32h76x_78x_std_periph_driver/inc/misc.h | 292 + .../inc/n32h76x_78x_adc.h | 733 + .../inc/n32h76x_78x_comp.h | 330 + .../inc/n32h76x_78x_cordic.h | 236 + .../inc/n32h76x_78x_crc.h | 160 + .../inc/n32h76x_78x_dac.h | 346 + .../inc/n32h76x_78x_dbg.h | 161 + .../inc/n32h76x_78x_dcmu.h | 197 + .../inc/n32h76x_78x_dma.h | 448 + .../inc/n32h76x_78x_dmamux.h | 534 + .../inc/n32h76x_78x_dsi.h | 623 + .../inc/n32h76x_78x_dsmu.h | 446 + .../inc/n32h76x_78x_dvp.h | 433 + .../inc/n32h76x_78x_eccmon.h | 170 + .../inc/n32h76x_78x_eth.h | 1490 + .../inc/n32h76x_78x_exti.h | 200 + .../inc/n32h76x_78x_fdcan.h | 1718 + .../inc/n32h76x_78x_femc.h | 372 + .../inc/n32h76x_78x_fmac.h | 189 + .../inc/n32h76x_78x_gpio.h | 912 + .../inc/n32h76x_78x_i2c.h | 430 + .../inc/n32h76x_78x_i2s.h | 272 + .../inc/n32h76x_78x_iwdg.h | 108 + .../inc/n32h76x_78x_jpeg.h | 383 + .../inc/n32h76x_78x_lcdc.h | 335 + .../inc/n32h76x_78x_lptim.h | 284 + .../inc/n32h76x_78x_lpuart.h | 319 + .../inc/n32h76x_78x_mdma.h | 540 + .../inc/n32h76x_78x_mmu.h | 256 + .../inc/n32h76x_78x_otpc.h | 171 + .../inc/n32h76x_78x_pwr.h | 425 + .../inc/n32h76x_78x_rcc.h | 2542 ++ .../inc/n32h76x_78x_rtc.h | 455 + .../inc/n32h76x_78x_sdmmc.h | 851 + .../inc/n32h76x_78x_sdram.h | 233 + .../inc/n32h76x_78x_shrtim.h | 2292 ++ .../inc/n32h76x_78x_smu.h | 93 + .../inc/n32h76x_78x_spi.h | 359 + .../inc/n32h76x_78x_tim.h | 946 + .../inc/n32h76x_78x_usart.h | 366 + .../inc/n32h76x_78x_vrefbuf.h | 111 + .../inc/n32h76x_78x_wwdg.h | 107 + .../inc/n32h76x_78x_xspi.h | 505 + .../n32h76x_78x_std_periph_driver/src/misc.c | 431 + .../src/n32h76x_78x_adc.c | 2669 ++ .../src/n32h76x_78x_comp.c | 785 + .../src/n32h76x_78x_cordic.c | 392 + .../src/n32h76x_78x_crc.c | 469 + .../src/n32h76x_78x_dac.c | 1340 + .../src/n32h76x_78x_dbg.c | 276 + .../src/n32h76x_78x_dcmu.c | 314 + .../src/n32h76x_78x_dma.c | 1266 + .../src/n32h76x_78x_dmamux.c | 1899 ++ .../src/n32h76x_78x_dsi.c | 1620 + .../src/n32h76x_78x_dsmu.c | 1574 + .../src/n32h76x_78x_dvp.c | 1169 + .../src/n32h76x_78x_eccmon.c | 869 + .../src/n32h76x_78x_eth.c | 4988 +++ .../src/n32h76x_78x_exti.c | 702 + .../src/n32h76x_78x_fdcan.c | 4885 +++ .../src/n32h76x_78x_femc.c | 951 + .../src/n32h76x_78x_fmac.c | 712 + .../src/n32h76x_78x_gpio.c | 2390 ++ .../src/n32h76x_78x_i2c.c | 1733 + .../src/n32h76x_78x_i2s.c | 1159 + .../src/n32h76x_78x_iwdg.c | 193 + .../src/n32h76x_78x_jpeg.c | 1617 + .../src/n32h76x_78x_lcdc.c | 1160 + .../src/n32h76x_78x_lptim.c | 1220 + .../src/n32h76x_78x_lpuart.c | 675 + .../src/n32h76x_78x_mdma.c | 1289 + .../src/n32h76x_78x_mmu.c | 598 + .../src/n32h76x_78x_otpc.c | 555 + .../src/n32h76x_78x_pwr.c | 1580 + .../src/n32h76x_78x_rcc.c | 9078 +++++ .../src/n32h76x_78x_rtc.c | 2412 ++ .../src/n32h76x_78x_sdmmc.c | 2879 ++ .../src/n32h76x_78x_sdram.c | 694 + .../src/n32h76x_78x_shrtim.c | 10593 ++++++ .../src/n32h76x_78x_smu.c | 136 + .../src/n32h76x_78x_spi.c | 962 + .../src/n32h76x_78x_tim.c | 6437 ++++ .../src/n32h76x_78x_usart.c | 1850 ++ .../src/n32h76x_78x_vrefbuf.c | 191 + .../src/n32h76x_78x_wwdg.c | 216 + .../src/n32h76x_78x_xspi.c | 1272 + .../device/class/audio/inc/usbd_audio_core.h | 128 + .../class/audio/inc/usbd_audio_out_if.h | 87 + .../device/class/audio/src/usbd_audio_core.c | 548 + .../class/audio/src/usbd_audio_out_if.c | 247 + .../device/class/cdc/inc/usbd_cdc_core.h | 97 + .../class/cdc/inc/usbd_cdc_core_loopback.h | 80 + .../device/class/cdc/src/usbd_cdc_core.c | 695 + .../class/cdc/src/usbd_cdc_core_loopback.c | 511 + .../class/customhid/inc/usbd_customhid_core.h | 97 + .../class/customhid/src/usbd_customhid_core.c | 584 + .../inc/usbd_hid_cdc_composite.h | 63 + .../src/usbd_hid_cdc_composite.c | 402 + .../hid_keyboard/inc/usbd_keyboard_core.h | 79 + .../hid_keyboard/src/usbd_keyboard_core.c | 351 + .../hid_msc_composite/inc/usbd_msc_hid_core.h | 63 + .../hid_msc_composite/src/usbd_msc_hid_core.c | 338 + .../device/class/mouse/inc/usbd_mouse_core.h | 120 + .../device/class/mouse/src/usbd_mouse_core.c | 355 + .../device/class/msc/inc/usbd_msc_bot.h | 127 + .../device/class/msc/inc/usbd_msc_core.h | 70 + .../device/class/msc/inc/usbd_msc_data.h | 73 + .../device/class/msc/inc/usbd_msc_scsi.h | 157 + .../device/class/msc/src/usbd_msc_bot.c | 311 + .../device/class/msc/src/usbd_msc_core.c | 389 + .../device/class/msc/src/usbd_msc_data.c | 90 + .../device/class/msc/src/usbd_msc_scsi.c | 616 + .../inc/usbd_msc_cdc_composite.h | 63 + .../src/usbd_msc_cdc_composite.c | 385 + .../device/class/printer/inc/usbd_printer.h | 90 + .../device/class/printer/src/usbd_printer.c | 400 + .../device/core/inc/usbd_core.h | 78 + .../device/core/inc/usbd_def.h | 124 + .../device/core/inc/usbd_ioreq.h | 78 + .../device/core/inc/usbd_req.h | 73 + .../device/core/src/usbd_core.c | 441 + .../device/core/src/usbd_ioreq.c | 175 + .../device/core/src/usbd_req.c | 758 + .../driver/inc/usbhs_core.h | 344 + .../driver/inc/usbhs_dcd.h | 100 + .../driver/inc/usbhs_dcd_int.h | 84 + .../driver/inc/usbhs_defines.h | 174 + .../driver/inc/usbhs_hcd.h | 75 + .../driver/inc/usbhs_hcd_int.h | 78 + .../driver/inc/usbhs_regs.h | 107 + .../driver/src/usbhs_core.c | 2063 ++ .../driver/src/usbhs_dcd.c | 434 + .../driver/src/usbhs_dcd_int.c | 1002 + .../driver/src/usbhs_hcd.c | 220 + .../driver/src/usbhs_hcd_int.c | 787 + .../host/class/CDC/inc/usbh_cdc_core.h | 164 + .../host/class/CDC/inc/usbh_cdc_funct.h | 294 + .../host/class/CDC/src/usbh_cdc_core.c | 568 + .../host/class/CDC/src/usbh_cdc_funct.c | 151 + .../host/class/HID/inc/usbh_hid_core.h | 212 + .../host/class/HID/inc/usbh_hid_keyboard.h | 81 + .../host/class/HID/inc/usbh_hid_mouse.h | 129 + .../host/class/HID/src/usbh_hid_core.c | 559 + .../host/class/HID/src/usbh_hid_keyboard.c | 291 + .../host/class/HID/src/usbh_hid_mouse.c | 106 + .../host/class/MSC/inc/usbh_msc_bot.h | 236 + .../host/class/MSC/inc/usbh_msc_core.h | 155 + .../host/class/MSC/inc/usbh_msc_scsi.h | 174 + .../host/class/MSC/src/usbh_msc_bot.c | 618 + .../host/class/MSC/src/usbh_msc_core.c | 458 + .../host/class/MSC/src/usbh_msc_fatfs.c | 235 + .../host/class/MSC/src/usbh_msc_scsi.c | 593 + .../host/core/inc/usbh_core.h | 250 + .../host/core/inc/usbh_def.h | 285 + .../host/core/inc/usbh_hcs.h | 80 + .../host/core/inc/usbh_ioreq.h | 85 + .../host/core/inc/usbh_stdreq.h | 96 + .../host/core/src/usbh_core.c | 825 + .../host/core/src/usbh_hcs.c | 200 + .../host/core/src/usbh_ioreq.c | 377 + .../host/core/src/usbh_stdreq.c | 512 + .../Cube_Config/MDK-ARM/Cube_Config.uvoptx} | 20 +- .../Cube_Config/MDK-ARM/Cube_Config.uvprojx | 482 + .../Cube_Config/MDK-ARM/Cube_Config_CM7.sct | 26 + .../Nationstech.N32H76x_DFP.1.1.0.pack | Bin 0 -> 213082 bytes .../board/Cube_Config/SaveProjects.dat | 1 + .../board/Cube_Config/USER/inc/main.h | 26 + .../Cube_Config/USER/inc/n32h76x_78x_cfg.h | 40 + .../Cube_Config/USER/inc/n32h76x_78x_it.h | 22 + .../board/Cube_Config/USER/src/main.c | 35 + .../Cube_Config/USER/src/n32h76x_78x_cfg.c | 233 + .../Cube_Config/USER/src/n32h76x_78x_it.c | 100 + .../board/Cube_Config/data/Clock.dat | 1 + .../board/Cube_Config/data/ConfigModList.dat | 1 + .../board/Cube_Config/data/DMAStates.dat | 1 + .../Cube_Config/data/LastLoadProject.dat | 1 + .../board/Cube_Config/data/NVIC_M4.dat | 1 + .../board/Cube_Config/data/NVIC_M7.dat | 1 + .../board/Cube_Config/data/PinStates.dat | 1 + .../board/Cube_Config/data/SYS.dat | 1 + .../board/Cube_Config/data/USART1.dat | 1 + .../Cube_Config/startup/startup_n32h73x_76x.s | 892 + .../startup/startup_n32h73x_76x_EWARM.s | 1529 + .../startup/startup_n32h73x_76x_gcc.s | 1099 + .../startup/startup_n32h76x_ITCM_gcc.s | 1126 + .../Cube_Config/startup/startup_n32h78x_cm4.s | 897 + .../startup/startup_n32h78x_cm4_EWARM.s | 1543 + .../startup/startup_n32h78x_cm4_gcc.s | 1117 + .../Cube_Config/startup/startup_n32h78x_cm7.s | 892 + .../startup/startup_n32h78x_cm7_EWARM.s | 1535 + .../startup/startup_n32h78x_cm7_gcc.s | 1108 + ...2\347\232\204\347\202\271\346\210\221.txt" | 4 + bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig | 165 + .../n32hxxx/n32h760zil7-stb/board/SConscript | 93 + bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c | 36 + bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h | 55 + .../board/linker_scripts/link.icf | 63 + .../board/linker_scripts/link.lds | 157 + .../board/linker_scripts/link.sct | 25 + .../n32hxxx/n32h760zil7-stb/figures/board.jpg | Bin 0 -> 3188413 bytes .../n32hxxx/n32h760zil7-stb/project.uvoptx | 1064 + .../n32hxxx/n32h760zil7-stb/project.uvprojx | 2150 ++ bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.h | 424 + bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.py | 185 + .../n32h760zil7-stb/template.uvoptx} | 21 +- .../n32hxxx/n32h760zil7-stb/template.uvprojx | 391 + bsp/n32/n32hxxx/tools/sdk_dist.py | 23 + bsp/n32/n32l40xcl-stb/Kconfig | 12 - bsp/n32/n32l40xcl-stb/project.uvoptx | 185 - bsp/n32/n32l40xcl-stb/rtconfig.py | 184 - bsp/n32/n32l436-evb/Kconfig | 12 - bsp/n32/n32l436-evb/project.uvoptx | 185 - bsp/n32/n32l436-evb/rtconfig.py | 184 - bsp/n32/n32l43xml-stb/Kconfig | 12 - bsp/n32/n32l43xml-stb/project.uvoptx | 185 - bsp/n32/n32l43xml-stb/rtconfig.py | 184 - bsp/n32/n32l43xrl-stb/Kconfig | 12 - bsp/n32/n32l43xrl-stb/rtconfig.py | 184 - bsp/n32/n32wb45xl-evb/Kconfig | 12 - bsp/n32/n32wb45xl-evb/project.uvoptx | 180 - bsp/n32/n32wb45xl-evb/rtconfig.py | 184 - 1308 files changed, 248658 insertions(+), 7504 deletions(-) delete mode 100644 bsp/n32/n32g45xcl-stb/project.uvoptx delete mode 100644 bsp/n32/n32g45xml-stb/project.uvoptx delete mode 100644 bsp/n32/n32g45xrl-stb/Kconfig delete mode 100644 bsp/n32/n32g45xrl-stb/project.uvoptx delete mode 100644 bsp/n32/n32g45xrl-stb/rtconfig.py delete mode 100644 bsp/n32/n32g45xvl-stb/Kconfig delete mode 100644 bsp/n32/n32g45xvl-stb/project.uvoptx delete mode 100644 bsp/n32/n32g45xvl-stb/rtconfig.py delete mode 100644 bsp/n32/n32g4frml-stb/Kconfig delete mode 100644 bsp/n32/n32g4frml-stb/project.ewp delete mode 100644 bsp/n32/n32g4frml-stb/rtconfig.py rename bsp/n32/{ => n32gxx_lxx}/.clang-format-ignore (55%) rename bsp/n32/{ => n32gxx_lxx}/libraries/Kconfig (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/SConscript (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_common_tables.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_const_structs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_compiler.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_iccarm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/core_cm4.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_conf.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_flash.ld (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_EWARM.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/SConscript (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_bkp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_can.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_crc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dac.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dma.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dvp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_eth.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_exti.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_flash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_gpio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_i2c.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_opamp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_pwr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rtc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_sdio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_spi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_usart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_bkp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_crc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dac.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dma.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_eth.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_exti.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_gpio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_iwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_pwr.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rcc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_spi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_wwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_core.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_def.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_init.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_lib.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_mem.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_sil.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_type.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_core.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_init.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_mem.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_regs.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_sil.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_common_tables.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_const_structs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armclang.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_compiler.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_gcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_iccarm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/core_cm4.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/core/mpu_armv7.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_conf.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_flash.ld (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_EWARM.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/SConscript (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_aes.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_algo_common.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_des.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_hash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_rng.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/misc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_adc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_bkp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_can.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_crc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dac.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dbg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dma.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dvp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_exti.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_flash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_gpio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_i2c.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_iwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_pwr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_qspi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rtc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_sdio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_spi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tsc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_usart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_wwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32xx_tsc_alg_api.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/misc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_adc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_bkp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_can.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_crc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dac.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dbg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dma.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dvp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_exti.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_flash.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_gpio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_i2c.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_iwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_pwr.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_qspi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rcc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rtc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_sdio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_spi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tsc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_usart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_wwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_core.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_def.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_init.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_lib.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_mem.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_regs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_sil.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_type.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_core.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_init.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_int.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_mem.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_regs.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_sil.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_conf.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_flash.ld (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/SConscript (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_usart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_conf.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_flash.ld (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/SConscript (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_usart.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_conf.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_flash.ld (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/SConscript (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h (100%) rename bsp/n32/{ => n32gxx_lxx}/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h (100%) rename bsp/n32/{ => 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bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dac.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dbg.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dcmu.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dma.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dmamux.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsi.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsmu.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dvp.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eccmon.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eth.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_exti.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fdcan.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_femc.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fmac.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_gpio.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2c.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2s.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_iwdg.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_jpeg.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lcdc.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lptim.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lpuart.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mdma.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mmu.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_otpc.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_pwr.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rcc.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rtc.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdmmc.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdram.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_shrtim.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_smu.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_spi.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_tim.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_usart.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_vrefbuf.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_wwdg.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_xspi.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/misc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_adc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_comp.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_cordic.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_crc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dac.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dbg.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dcmu.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dma.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dmamux.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsi.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsmu.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dvp.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eccmon.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eth.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_exti.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fdcan.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_femc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fmac.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_gpio.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2c.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2s.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_iwdg.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_jpeg.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lcdc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lptim.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lpuart.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mdma.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mmu.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_otpc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_pwr.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rcc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rtc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdmmc.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdram.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_shrtim.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_smu.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_spi.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_tim.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_usart.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_vrefbuf.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_wwdg.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_xspi.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_out_if.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_out_if.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core_loopback.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core_loopback.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/inc/usbd_customhid_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/src/usbd_customhid_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/inc/usbd_hid_cdc_composite.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/src/usbd_hid_cdc_composite.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/inc/usbd_keyboard_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/src/usbd_keyboard_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/inc/usbd_msc_hid_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/src/usbd_msc_hid_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/inc/usbd_mouse_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/src/usbd_mouse_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_bot.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_data.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_scsi.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_bot.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_data.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_scsi.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/inc/usbd_msc_cdc_composite.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/src/usbd_msc_cdc_composite.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/inc/usbd_printer.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/src/usbd_printer.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_def.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_ioreq.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_req.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_ioreq.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_req.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd_int.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_defines.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd_int.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_regs.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd_int.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd_int.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_funct.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_funct.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_keyboard.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_mouse.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_keyboard.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_mouse.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_bot.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_scsi.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_bot.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_fatfs.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_scsi.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_core.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_def.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_hcs.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_ioreq.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_stdreq.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_core.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_hcs.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_ioreq.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_stdreq.c rename bsp/n32/{n32g457qel-stb/project.uvoptx => n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvoptx} (91%) create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvprojx create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config_CM7.sct create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Nationstech.N32H76x_DFP.1.1.0.pack create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/SaveProjects.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/main.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_cfg.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_it.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/main.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_cfg.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_it.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/Clock.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/ConfigModList.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/DMAStates.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/LastLoadProject.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/NVIC_M4.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/NVIC_M7.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/PinStates.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/SYS.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/USART1.dat create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_EWARM.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_gcc.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h76x_ITCM_gcc.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_EWARM.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_gcc.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_EWARM.s create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_gcc.s create mode 100644 "bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/\346\226\260\347\211\210keil_pack\345\214\205\350\243\205\344\270\215\344\270\212\347\232\204\347\202\271\346\210\221.txt" create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/SConscript create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.icf create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.lds create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.sct create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/figures/board.jpg create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.h create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.py rename bsp/n32/{n32g4frml-stb/project.uvoptx => n32hxxx/n32h760zil7-stb/template.uvoptx} (89%) create mode 100644 bsp/n32/n32hxxx/n32h760zil7-stb/template.uvprojx create mode 100644 bsp/n32/n32hxxx/tools/sdk_dist.py delete mode 100644 bsp/n32/n32l40xcl-stb/Kconfig delete mode 100644 bsp/n32/n32l40xcl-stb/project.uvoptx delete mode 100644 bsp/n32/n32l40xcl-stb/rtconfig.py delete mode 100644 bsp/n32/n32l436-evb/Kconfig delete mode 100644 bsp/n32/n32l436-evb/project.uvoptx delete mode 100644 bsp/n32/n32l436-evb/rtconfig.py delete mode 100644 bsp/n32/n32l43xml-stb/Kconfig delete mode 100644 bsp/n32/n32l43xml-stb/project.uvoptx delete mode 100644 bsp/n32/n32l43xml-stb/rtconfig.py delete mode 100644 bsp/n32/n32l43xrl-stb/Kconfig delete mode 100644 bsp/n32/n32l43xrl-stb/rtconfig.py delete mode 100644 bsp/n32/n32wb45xl-evb/Kconfig delete mode 100644 bsp/n32/n32wb45xl-evb/project.uvoptx delete mode 100644 bsp/n32/n32wb45xl-evb/rtconfig.py diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 6d503086dd..de94d69ffb 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -316,18 +316,19 @@ "gd32/arm/gd32e503v-eval", "gd32/arm/gd32527I-eval", "gd32/arm/gd32e230-lckfb", - "n32/n32g43xcl-stb", - "n32/n32g45xcl-stb", - "n32/n32g45xml-stb", - "n32/n32g45xrl-stb", - "n32/n32g45xvl-stb", - "n32/n32g457qel-stb", - "n32/n32g4frml-stb", - "n32/n32l40xcl-stb", - "n32/n32l43xml-stb", - "n32/n32l43xrl-stb", - "n32/n32l436-evb", - "n32/n32wb45xl-evb", + "n32/n32gxx_lxx/n32g43xcl-stb", + "n32/n32gxx_lxx/n32g45xcl-stb", + "n32/n32gxx_lxx/n32g45xml-stb", + "n32/n32gxx_lxx/n32g45xrl-stb", + "n32/n32gxx_lxx/n32g45xvl-stb", + "n32/n32gxx_lxx/n32g457qel-stb", + "n32/n32gxx_lxx/n32g4frml-stb", + "n32/n32gxx_lxx/n32l40xcl-stb", + "n32/n32gxx_lxx/n32l43xml-stb", + "n32/n32gxx_lxx/n32l43xrl-stb", + "n32/n32gxx_lxx/n32l436-evb", + "n32/n32gxx_lxx/n32wb45xl-evb", + "n32/n32hxxx/n32h760zil7-stb", "apm32/apm32f103xe-minibroard", "apm32/apm32f407ig-minibroard", "apm32/apm32f407zg-evalboard", diff --git a/bsp/n32/n32g45xcl-stb/project.uvoptx b/bsp/n32/n32g45xcl-stb/project.uvoptx deleted file mode 100644 index d3d314c823..0000000000 --- a/bsp/n32/n32g45xcl-stb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL040000 -FS08000000 -FP0($$Device:N32G455CCL7$Flash\N32G45x.FLM) - - - 0 - CMSIS_AGDI - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL040000 -FS08000000 -FP0($$Device:N32G455CCL7$Flash\N32G45x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/n32/n32g45xml-stb/project.uvoptx b/bsp/n32/n32g45xml-stb/project.uvoptx deleted file mode 100644 index c992fb01f0..0000000000 --- a/bsp/n32/n32g45xml-stb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457MEL7$Flash\N32G45x.FLM) - - - 0 - CMSIS_AGDI - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457MEL7$Flash\N32G45x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/n32/n32g45xrl-stb/Kconfig b/bsp/n32/n32g45xrl-stb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32g45xrl-stb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32g45xrl-stb/project.uvoptx b/bsp/n32/n32g45xrl-stb/project.uvoptx deleted file mode 100644 index ebb33b1f75..0000000000 --- a/bsp/n32/n32g45xrl-stb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457REL7$Flash\N32G45x.FLM) - - - 0 - CMSIS_AGDI - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457REL7$Flash\N32G45x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/n32/n32g45xrl-stb/rtconfig.py b/bsp/n32/n32g45xrl-stb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32g45xrl-stb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32g45xvl-stb/Kconfig b/bsp/n32/n32g45xvl-stb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32g45xvl-stb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32g45xvl-stb/project.uvoptx b/bsp/n32/n32g45xvl-stb/project.uvoptx deleted file mode 100644 index 4fae3b2177..0000000000 --- a/bsp/n32/n32g45xvl-stb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457VEL7$Flash\N32G45x.FLM) - - - 0 - CMSIS_AGDI - -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0N32G45x.FLM -FS08000000 -FL080000 -FP0($$Device:N32G457VEL7$Flash\N32G45x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/n32/n32g45xvl-stb/rtconfig.py b/bsp/n32/n32g45xvl-stb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32g45xvl-stb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32g4frml-stb/Kconfig b/bsp/n32/n32g4frml-stb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32g4frml-stb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32g4frml-stb/project.ewp b/bsp/n32/n32g4frml-stb/project.ewp deleted file mode 100644 index 96ebc11b67..0000000000 --- a/bsp/n32/n32g4frml-stb/project.ewp +++ /dev/null @@ -1,2474 +0,0 @@ - - 3 - - rt-thread - - ARM - - 1 - - General - 3 - - 33 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 37 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - inputOutputBased - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 25 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - - Release - - ARM - - 0 - - General - 3 - - 33 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 37 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - inputOutputBased - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 25 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - - Applications - - $PROJ_DIR$\applications\main.c - - - - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c - - - - DeviceDrivers - - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c - - - $PROJ_DIR$\..\..\..\components\drivers\core\device.c - - - $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - - - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - - - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c - - - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c - - - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c - - - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c - - - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c - - - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c - - - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c - - - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c - - - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c - - - - Drivers - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\CMSIS\device\startup\startup_n32g4fr_EWARM.s - - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_adc.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_can.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_dac.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_spi.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\n32_drivers\drv_wdt.c - - - - Finsh - - $PROJ_DIR$\..\..\..\components\finsh\cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c - - - $PROJ_DIR$\..\..\..\components\finsh\shell.c - - - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\components.c - - - $PROJ_DIR$\..\..\..\src\cpu_up.c - - - $PROJ_DIR$\..\..\..\src\defunct.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\memheap.c - - - $PROJ_DIR$\..\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\scheduler_comm.c - - - $PROJ_DIR$\..\..\..\src\scheduler_up.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - - - klibc - - $PROJ_DIR$\..\..\..\src\klibc\kstring.c - - - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c - - - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c - - - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c - - - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c - - - - libcpu - - $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c - - - - libraries - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_usart.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_adc.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_rtc.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_exti.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_spi.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_rcc.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_gpio.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_can.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_i2c.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_dac.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_iwdg.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_tim.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\CMSIS\device\system_n32g4fr.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\misc.c - - - $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_wwdg.c - - - - POSIX - - - utc_UTest - - - utestcases - - diff --git a/bsp/n32/n32g4frml-stb/rtconfig.py b/bsp/n32/n32g4frml-stb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32g4frml-stb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/.clang-format-ignore b/bsp/n32/n32gxx_lxx/.clang-format-ignore similarity index 55% rename from bsp/n32/.clang-format-ignore rename to bsp/n32/n32gxx_lxx/.clang-format-ignore index bb5dde5216..b828aa10a8 100644 --- a/bsp/n32/.clang-format-ignore +++ b/bsp/n32/n32gxx_lxx/.clang-format-ignore @@ -4,4 +4,9 @@ # If you need to exclude a file, add the path to the file in file_path. # 从 .ignore_format.yml 迁移的规则 -/libraries/N32G45x_Firmware_Library/ \ No newline at end of file +/libraries/N32G43x_Firmware_Library/ +/libraries/N32G4FR_Firmware_Library/ +/libraries/N32G45x_Firmware_Library/ +/libraries/N32L40x_Firmware_Library/ +/libraries/N32L43x_Firmware_Library/ +/libraries/N32WB452_Firmware_Library/ \ No newline at end of file diff --git a/bsp/n32/libraries/Kconfig b/bsp/n32/n32gxx_lxx/libraries/Kconfig similarity index 100% rename from bsp/n32/libraries/Kconfig rename to bsp/n32/n32gxx_lxx/libraries/Kconfig diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/SConscript b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/SConscript similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/SConscript rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/SConscript diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_can.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rcc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_rtc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_spi.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tim.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_tsc.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_adc.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_can.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_comp.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_crc.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dac.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dbg.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_dma.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_exti.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_flash.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_gpio.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_i2c.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_iwdg.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lptim.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_lpuart.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_opamp.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_pwr.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rcc.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_rtc.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_spi.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tim.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_tsc.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_usart.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/n32g43x_wwdg.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_core.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_def.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_init.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_int.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_lib.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_mem.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_regs.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_sil.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/inc/usb_type.h diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_core.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_init.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_int.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_mem.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_regs.c diff --git a/bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c b/bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c similarity index 100% rename from bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c rename to bsp/n32/n32gxx_lxx/libraries/N32G43x_Firmware_Library/n32g43x_usbfs_driver/src/usb_sil.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_common_tables.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_common_tables.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_common_tables.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_const_structs.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_const_structs.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_const_structs.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/arm_math.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armcc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_armclang.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_compiler.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_compiler.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_compiler.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_gcc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_iccarm.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_iccarm.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_iccarm.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_version.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/cmsis_version.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/core_cm4.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/core_cm4.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/core_cm4.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/core/mpu_armv7.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_conf.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_conf.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_conf.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_conf.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_flash.ld b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_flash.ld similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_flash.ld rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/n32g45x_flash.ld diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x.s b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x.s similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x.s rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x.s diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_EWARM.s b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_EWARM.s similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_EWARM.s rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_EWARM.s diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/startup/startup_n32g45x_gcc.s diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/CMSIS/device/system_n32g45x.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/SConscript b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/SConscript similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/SConscript rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/SConscript diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_aes.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_algo_common.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_des.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_hash.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_algo_lib/inc/n32g45x_rng.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/misc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_adc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_bkp.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_bkp.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_bkp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_bkp.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_can.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_can.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_can.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_can.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_comp.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_crc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_crc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_crc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_crc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dac.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dac.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dac.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dac.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dbg.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dma.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dma.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dma.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dma.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dvp.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dvp.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dvp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_dvp.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_eth.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_eth.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_eth.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_eth.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_exti.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_exti.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_exti.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_exti.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_flash.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_flash.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_gpio.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_gpio.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_gpio.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_i2c.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_i2c.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_i2c.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_iwdg.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_opamp.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_opamp.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_opamp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_opamp.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_pwr.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_pwr.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_pwr.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_pwr.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_qspi.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rcc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rcc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rtc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rtc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rtc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_rtc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_sdio.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_sdio.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_sdio.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_sdio.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_spi.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_spi.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tim.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_tsc.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_usart.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_usart.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_usart.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_usart.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32g45x_wwdg.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/inc/n32xx_tsc_alg_api.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/misc.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_adc.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_bkp.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_bkp.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_bkp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_bkp.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_can.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_comp.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_crc.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_crc.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_crc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_crc.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dac.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dac.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dac.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dac.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dbg.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dma.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dma.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dma.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dma.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_dvp.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_eth.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_eth.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_eth.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_eth.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_exti.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_exti.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_exti.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_exti.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_flash.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_gpio.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_gpio.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_gpio.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_i2c.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_iwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_iwdg.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_iwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_iwdg.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_opamp.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_pwr.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_pwr.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_pwr.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_pwr.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_qspi.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rcc.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rcc.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rcc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rcc.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_rtc.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_sdio.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_spi.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_spi.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_spi.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_spi.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tim.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_tsc.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_usart.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_wwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_wwdg.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_wwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/n32g45x_wwdg.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_core.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_core.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_core.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_core.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_def.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_def.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_def.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_def.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_init.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_init.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_init.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_init.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_int.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_int.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_int.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_lib.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_lib.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_lib.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_lib.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_mem.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_mem.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_regs.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_sil.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_sil.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_sil.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_sil.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_type.h b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_type.h similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_type.h rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/inc/usb_type.h diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_core.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_core.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_core.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_core.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_init.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_init.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_init.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_init.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_int.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_mem.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_mem.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_mem.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_mem.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_regs.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_regs.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_regs.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_regs.c diff --git a/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_sil.c b/bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_sil.c similarity index 100% rename from bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_sil.c rename to bsp/n32/n32gxx_lxx/libraries/N32G45x_Firmware_Library/n32g45x_usbfs_driver/src/usb_sil.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_common_tables.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_common_tables.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_common_tables.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_const_structs.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_const_structs.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_const_structs.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_math.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/arm_math.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armcc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armcc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armclang.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armclang.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_armclang.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_compiler.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_compiler.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_compiler.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_gcc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_gcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_gcc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_iccarm.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_iccarm.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_iccarm.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_version.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/cmsis_version.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/core_cm4.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/core_cm4.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/core_cm4.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/mpu_armv7.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/core/mpu_armv7.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/core/mpu_armv7.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_conf.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_conf.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_conf.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_conf.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_flash.ld b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_flash.ld similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_flash.ld rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/n32g4fr_flash.ld diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr.s b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr.s similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr.s rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr.s diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_EWARM.s b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_EWARM.s similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_EWARM.s rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_EWARM.s diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/system_n32g4fr.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/SConscript b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/SConscript similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/SConscript rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/SConscript diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_aes.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_aes.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_aes.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_aes.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_algo_common.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_algo_common.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_algo_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_algo_common.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_des.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_des.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_des.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_des.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_hash.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_hash.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_hash.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_hash.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_rng.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_rng.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_rng.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_algo_lib/inc/n32g4fr_rng.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/misc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/misc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/misc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/misc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_adc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_adc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_adc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_adc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_bkp.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_bkp.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_bkp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_bkp.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_can.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_can.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_can.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_can.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_crc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_crc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_crc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_crc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dac.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dac.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dac.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dac.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dbg.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dbg.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dbg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dbg.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dma.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dma.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dma.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dma.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dvp.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dvp.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dvp.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_dvp.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_exti.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_exti.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_exti.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_exti.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_flash.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_flash.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_gpio.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_gpio.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_gpio.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_i2c.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_i2c.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_i2c.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_iwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_iwdg.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_iwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_iwdg.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_pwr.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_pwr.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_pwr.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_pwr.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_qspi.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_qspi.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_qspi.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_qspi.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rcc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rcc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rcc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rtc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rtc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rtc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_rtc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_sdio.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_sdio.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_sdio.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_sdio.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_spi.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_spi.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tim.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tim.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tim.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tim.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tsc.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tsc.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tsc.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_tsc.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_usart.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_usart.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_usart.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_usart.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_wwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_wwdg.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_wwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32g4fr_wwdg.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32xx_tsc_alg_api.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32xx_tsc_alg_api.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32xx_tsc_alg_api.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/inc/n32xx_tsc_alg_api.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/misc.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/misc.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/misc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/misc.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_adc.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_adc.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_adc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_adc.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_bkp.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_bkp.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_bkp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_bkp.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_can.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_can.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_can.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_can.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_crc.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_crc.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_crc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_crc.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dac.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dac.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dac.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dac.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dbg.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dbg.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dbg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dbg.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dma.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dma.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dma.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dma.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dvp.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dvp.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dvp.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_dvp.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_exti.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_exti.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_exti.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_exti.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_flash.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_flash.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_gpio.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_gpio.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_gpio.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_i2c.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_i2c.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_i2c.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_iwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_iwdg.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_iwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_iwdg.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_pwr.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_pwr.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_pwr.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_pwr.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_qspi.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_qspi.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_qspi.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_qspi.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rcc.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rcc.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rcc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rcc.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rtc.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rtc.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_rtc.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_sdio.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_sdio.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_sdio.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_sdio.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_spi.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_spi.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_spi.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_spi.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tim.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tim.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tim.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tim.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tsc.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tsc.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tsc.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_tsc.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_usart.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_usart.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_usart.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_usart.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_wwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_wwdg.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_wwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/n32g4fr_wwdg.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_core.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_core.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_core.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_core.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_def.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_def.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_def.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_def.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_init.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_init.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_init.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_init.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_int.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_int.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_int.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_lib.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_lib.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_lib.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_lib.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_mem.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_mem.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_regs.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_regs.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_regs.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_regs.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_sil.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_sil.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_sil.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_sil.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_type.h b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_type.h similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_type.h rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/inc/usb_type.h diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_core.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_core.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_core.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_core.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_init.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_init.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_init.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_init.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_int.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_int.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_int.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_int.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_mem.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_mem.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_mem.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_mem.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_regs.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_regs.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_regs.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_regs.c diff --git a/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_sil.c b/bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_sil.c similarity index 100% rename from bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_sil.c rename to bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/n32g4fr_usbfs_driver/src/usb_sil.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_common_tables.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_const_structs.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/arm_math.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armcc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_armclang.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_compiler.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_gcc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_iccarm.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/cmsis_version.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/core_cm4.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/core/mpu_armv7.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_conf.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_conf.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_conf.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_conf.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_flash.ld b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_flash.ld similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_flash.ld rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/n32l40x_flash.ld diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x.s diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_EWARM.s diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/startup/startup_n32l40x_gcc.s diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/CMSIS/device/system_n32l40x.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/SConscript b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/SConscript similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/SConscript rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/SConscript diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_aes.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_algo_common.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_des.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_hash.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_algo_lib/inc/n32l40x_rng.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/misc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_adc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_can.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_comp.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_crc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dac.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dbg.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_dma.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_exti.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_flash.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_gpio.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_i2c.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_iwdg.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lcd.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lptim.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_lpuart.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_opamp.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_pwr.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rcc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_rtc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_spi.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tim.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_tsc.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_usart.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_usart.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_usart.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_usart.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/n32l40x_wwdg.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/misc.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_adc.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_can.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_comp.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_crc.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dac.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dbg.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_dma.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_exti.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_flash.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_gpio.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_i2c.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_iwdg.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lcd.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lptim.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_lpuart.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_opamp.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_pwr.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rcc.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_rtc.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_spi.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tim.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_tsc.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_usart.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/n32l40x_wwdg.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_core.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_def.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_init.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_int.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_lib.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_mem.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_regs.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_sil.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/inc/usb_type.h diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_core.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_init.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_int.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_mem.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_regs.c diff --git a/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c b/bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c similarity index 100% rename from bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c rename to bsp/n32/n32gxx_lxx/libraries/N32L40x_Firmware_Library/n32l40x_usbfs_driver/src/usb_sil.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_common_tables.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_const_structs.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/arm_math.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armcc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_armclang.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_compiler.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_gcc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/cmsis_version.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/core_cm4.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/core/mpu_armv7.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_conf.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_conf.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_conf.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_conf.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_flash.ld b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_flash.ld similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_flash.ld rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/n32l43x_flash.ld diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x.s diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_EWARM.s diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/startup/startup_n32l43x_gcc.s diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/CMSIS/device/system_n32l43x.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/SConscript b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/SConscript similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/SConscript rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/SConscript diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_aes.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_algo_common.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_des.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_hash.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_algo_lib/inc/n32l43x_rng.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/misc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_adc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_can.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_comp.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_crc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dac.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dbg.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_dma.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_exti.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_flash.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_gpio.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_i2c.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_iwdg.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lcd.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lprcnt.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lptim.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_lpuart.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_opamp.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_pwr.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rcc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_rtc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_spi.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tim.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_tsc.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_usart.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_usart.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_usart.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_usart.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/n32l43x_wwdg.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/misc.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_adc.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_can.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_comp.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_crc.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dac.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dbg.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_dma.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_exti.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_flash.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_gpio.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_i2c.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_iwdg.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lcd.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lprcnt.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lptim.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_lpuart.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_opamp.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_pwr.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rcc.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_rtc.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_spi.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tim.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_tsc.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_usart.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/n32l43x_wwdg.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_core.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_def.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_init.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_int.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_lib.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_mem.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_regs.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_sil.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/inc/usb_type.h diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_core.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_init.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_int.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_mem.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_regs.c diff --git a/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c b/bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c similarity index 100% rename from bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c rename to bsp/n32/n32gxx_lxx/libraries/N32L43x_Firmware_Library/n32l43x_usbfs_driver/src/usb_sil.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_common_tables.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_const_structs.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/arm_math.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armcc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_armclang.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_compiler.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_gcc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_iccarm.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/cmsis_version.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/core_cm4.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/core/mpu_armv7.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_conf.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_conf.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_conf.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_conf.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_flash.ld b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_flash.ld similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_flash.ld rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/n32wb452_flash.ld diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452.s diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_EWARM.s diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/startup/startup_n32wb452_gcc.s diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/CMSIS/device/system_n32wb452.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/SConscript b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/SConscript similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/SConscript rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/SConscript diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_aes.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_algo_common.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_des.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_hash.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_algo_lib/inc/n32wb452_rng.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/att.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/attm_db.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/atts.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ble_arch.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_bt_defines.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_endian.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_error.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_hci.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_list.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_llcp.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_lmp.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_math.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_utils.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/co_version.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gap.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_sig.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapc_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gapm_util.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gatt.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattc_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/gattm_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/h4tl.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/hci_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_env.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_event.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_mem.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_msg.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_queue.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/ke_timer.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_lecb.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_pdu_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_sig.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cc_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/l2cm_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/nvds.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_types.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/prf_utils.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwapp_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwble_hl_error.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwip_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/rwprf_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smp_common.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_api.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_crypto.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpc_util.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/smpm_api.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/n32wb452_ble_api.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_debug.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_flash.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Eif_timer.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/Interface.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_debug.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_flash.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_iom.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_spi.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_timer.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Eif_uart.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Interface.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/Ramcode.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/platform/inc/ble_monitor.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_batt.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_sec.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_task.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/app_user.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/bass_task.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_batt.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_sec.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/app_user.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/bass_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/rwapp_config.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/inc/user_task.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/prf_utils.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/profile/user_task.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/misc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_adc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_bkp.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_can.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_crc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dac.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dbg.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dma.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_dvp.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_exti.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_flash.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_gpio.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_i2c.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_iwdg.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_pwr.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rcc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_rtc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_sdio.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_spi.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tim.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_tsc.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_usart.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_usart.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_usart.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_usart.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32wb452_wwdg.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/inc/n32xx_tsc_alg_api.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/misc.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_adc.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_bkp.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_can.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_crc.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dac.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dbg.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dma.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_dvp.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_exti.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_flash.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_gpio.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_i2c.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_iwdg.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_pwr.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rcc.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_rtc.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_sdio.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_spi.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tim.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_tsc.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_usart.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/n32wb452_wwdg.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_core.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_def.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_init.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_int.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_lib.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_mem.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_regs.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_sil.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/inc/usb_type.h diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_core.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_init.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_int.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_mem.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_regs.c diff --git a/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c b/bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c similarity index 100% rename from bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c rename to bsp/n32/n32gxx_lxx/libraries/N32WB452_Firmware_Library/n32wb452_usbfs_driver/src/usb_sil.c diff --git a/bsp/n32/libraries/n32_drivers/Kconfig b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/Kconfig similarity index 100% rename from bsp/n32/libraries/n32_drivers/Kconfig rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/Kconfig diff --git a/bsp/n32/libraries/n32_drivers/SConscript b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/SConscript similarity index 100% rename from bsp/n32/libraries/n32_drivers/SConscript rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/SConscript diff --git a/bsp/n32/libraries/n32_drivers/drv_adc.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_adc.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_adc.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_adc.c diff --git a/bsp/n32/libraries/n32_drivers/drv_adc.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_adc.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_adc.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_adc.h diff --git a/bsp/n32/libraries/n32_drivers/drv_can.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_can.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_can.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_can.c diff --git a/bsp/n32/libraries/n32_drivers/drv_can.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_can.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_can.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_can.h diff --git a/bsp/n32/libraries/n32_drivers/drv_dac.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_dac.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_dac.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_dac.c diff --git a/bsp/n32/libraries/n32_drivers/drv_dac.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_dac.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_dac.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_dac.h diff --git a/bsp/n32/libraries/n32_drivers/drv_gpio.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_gpio.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_gpio.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_gpio.c diff --git a/bsp/n32/libraries/n32_drivers/drv_gpio.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_gpio.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_gpio.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_gpio.h diff --git a/bsp/n32/libraries/n32_drivers/drv_i2c.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_i2c.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_i2c.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_i2c.c diff --git a/bsp/n32/libraries/n32_drivers/drv_i2c.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_i2c.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_i2c.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_i2c.h diff --git a/bsp/n32/libraries/n32_drivers/drv_rtc.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_rtc.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_rtc.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_rtc.c diff --git a/bsp/n32/libraries/n32_drivers/drv_spi.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_spi.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_spi.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_spi.c diff --git a/bsp/n32/libraries/n32_drivers/drv_spi.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_spi.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_spi.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_spi.h diff --git a/bsp/n32/libraries/n32_drivers/drv_timer.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_timer.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_timer.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_timer.c diff --git a/bsp/n32/libraries/n32_drivers/drv_timer.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_timer.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_timer.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_timer.h diff --git a/bsp/n32/libraries/n32_drivers/drv_usart.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_usart.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart.c diff --git a/bsp/n32/libraries/n32_drivers/drv_usart.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_usart.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart.h diff --git a/bsp/n32/libraries/n32_drivers/drv_usart_v2.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart_v2.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_usart_v2.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart_v2.c diff --git a/bsp/n32/libraries/n32_drivers/drv_usart_v2.h b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart_v2.h similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_usart_v2.h rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_usart_v2.h diff --git a/bsp/n32/libraries/n32_drivers/drv_wdt.c b/bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_wdt.c similarity index 100% rename from bsp/n32/libraries/n32_drivers/drv_wdt.c rename to bsp/n32/n32gxx_lxx/libraries/n32_drivers/drv_wdt.c diff --git a/bsp/n32/n32g43xcl-stb/.config b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/.config similarity index 97% rename from bsp/n32/n32g43xcl-stb/.config rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/.config index 7f129ba8d9..83e11064d0 100644 --- a/bsp/n32/n32g43xcl-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/.config @@ -179,7 +179,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -267,6 +267,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -361,8 +363,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +371,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -572,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -596,6 +598,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -644,6 +647,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -738,6 +744,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -893,7 +900,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -939,9 +962,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1066,6 +1091,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32g45xml-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/Kconfig similarity index 88% rename from bsp/n32/n32g45xml-stb/Kconfig rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/Kconfig index 73238d3a13..07edfefc34 100644 --- a/bsp/n32/n32g45xml-stb/Kconfig +++ b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/Kconfig @@ -2,7 +2,7 @@ mainmenu "RT-Thread Configuration" BSP_DIR := . -RTT_DIR := ../../.. +RTT_DIR := ../../../.. PKGS_DIR := packages diff --git a/bsp/n32/n32g43xcl-stb/README.md b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/README.md similarity index 100% rename from bsp/n32/n32g43xcl-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/README.md diff --git a/bsp/n32/n32g43xcl-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/SConscript similarity index 100% rename from bsp/n32/n32g43xcl-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/SConscript diff --git a/bsp/n32/n32g43xcl-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/SConstruct similarity index 96% rename from bsp/n32/n32g43xcl-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/SConstruct index a72e9bffee..605ee02867 100644 --- a/bsp/n32/n32g43xcl-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g43xcl-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g43xcl-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/applications/SConscript diff --git a/bsp/n32/n32g43xcl-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g43xcl-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/applications/main.c diff --git a/bsp/n32/n32g43xcl-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/Kconfig diff --git a/bsp/n32/n32g43xcl-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/SConscript diff --git a/bsp/n32/n32g43xcl-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/board.c similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/board.c diff --git a/bsp/n32/n32g43xcl-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/board.h similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/board.h diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g43xcl-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g43xcl-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g43xcl-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32g43xcl-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/figures/board.jpg diff --git a/bsp/n32/n32g43xcl-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.ewd similarity index 100% rename from bsp/n32/n32g43xcl-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.ewd diff --git a/bsp/n32/n32g43xcl-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.ewp similarity index 86% rename from bsp/n32/n32g43xcl-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.ewp index 9a4a86e020..4a260e1d3e 100644 --- a/bsp/n32/n32g43xcl-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,142 +2308,169 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c Libraries - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_rcc.c - - - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_dac.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\CMSIS\device\system_n32g43x.c $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_gpio.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\CMSIS\device\system_n32g43x.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_rcc.c $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_exti.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_usart.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_flash.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_usart.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_i2c.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_can.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_spi.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_tim.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_can.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_wwdg.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_adc.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_iwdg.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_dac.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_i2c.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_tim.c $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_rtc.c @@ -2483,14 +2479,14 @@ $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_pwr.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_spi.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_flash.c - $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_adc.c + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_iwdg.c + + + $PROJ_DIR$\..\libraries\N32G43x_Firmware_Library\n32g43x_std_periph_driver\src\n32g43x_wwdg.c - - - POSIX utc_UTest diff --git a/bsp/n32/n32g43xcl-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.eww similarity index 100% rename from bsp/n32/n32g43xcl-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.eww diff --git a/bsp/n32/n32g43xcl-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.uvoptx similarity index 100% rename from bsp/n32/n32g43xcl-stb/project.uvoptx rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.uvoptx diff --git a/bsp/n32/n32g43xcl-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g43xcl-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/project.uvprojx diff --git a/bsp/n32/n32g43xcl-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g43xcl-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/rtconfig.h index 9c8805bc9f..be4dfb4dc4 100644 --- a/bsp/n32/n32g43xcl-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ @@ -155,6 +155,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -327,6 +328,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32g457qel-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/rtconfig.py similarity index 97% rename from bsp/n32/n32g457qel-stb/rtconfig.py rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/rtconfig.py index 2a0371110c..c3765e6f08 100644 --- a/bsp/n32/n32g457qel-stb/rtconfig.py +++ b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g43xcl-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.ewp similarity index 100% rename from bsp/n32/n32g43xcl-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.ewp diff --git a/bsp/n32/n32g43xcl-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.eww similarity index 100% rename from bsp/n32/n32g43xcl-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.eww diff --git a/bsp/n32/n32g43xcl-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g43xcl-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.uvoptx diff --git a/bsp/n32/n32g43xcl-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32g43xcl-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g43xcl-stb/template.uvprojx diff --git a/bsp/n32/n32g45xrl-stb/.config b/bsp/n32/n32gxx_lxx/n32g457qel-stb/.config similarity index 97% rename from bsp/n32/n32g45xrl-stb/.config rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/.config index b8eb0410ff..25021739e8 100644 --- a/bsp/n32/n32g45xrl-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32g457qel-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g457qel-stb/Kconfig similarity index 88% rename from bsp/n32/n32g457qel-stb/Kconfig rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/Kconfig index 73238d3a13..07edfefc34 100644 --- a/bsp/n32/n32g457qel-stb/Kconfig +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/Kconfig @@ -2,7 +2,7 @@ mainmenu "RT-Thread Configuration" BSP_DIR := . -RTT_DIR := ../../.. +RTT_DIR := ../../../.. PKGS_DIR := packages diff --git a/bsp/n32/n32g457qel-stb/README.md b/bsp/n32/n32gxx_lxx/n32g457qel-stb/README.md similarity index 100% rename from bsp/n32/n32g457qel-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/README.md diff --git a/bsp/n32/n32g457qel-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g457qel-stb/SConscript similarity index 100% rename from bsp/n32/n32g457qel-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/SConscript diff --git a/bsp/n32/n32g45xcl-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g457qel-stb/SConstruct similarity index 96% rename from bsp/n32/n32g45xcl-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/SConstruct index bc987cd14d..133a133cba 100644 --- a/bsp/n32/n32g45xcl-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g457qel-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g457qel-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g457qel-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/applications/SConscript diff --git a/bsp/n32/n32g457qel-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g457qel-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g457qel-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/applications/main.c diff --git a/bsp/n32/n32g457qel-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g457qel-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/Kconfig diff --git a/bsp/n32/n32g457qel-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g457qel-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/SConscript diff --git a/bsp/n32/n32g457qel-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/board.c similarity index 100% rename from bsp/n32/n32g457qel-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/board.c diff --git a/bsp/n32/n32g457qel-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/board.h similarity index 100% rename from bsp/n32/n32g457qel-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/board.h diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g457qel-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g457qel-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g457qel-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g457qel-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g457qel-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g457qel-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32g457qel-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32g457qel-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/figures/board.jpg diff --git a/bsp/n32/n32g457qel-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.ewd similarity index 100% rename from bsp/n32/n32g457qel-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/project.ewd diff --git a/bsp/n32/n32g457qel-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.ewp similarity index 86% rename from bsp/n32/n32g457qel-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/project.ewp index 8f1108bf10..51bcc9c6f6 100644 --- a/bsp/n32/n32g457qel-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,162 +2311,186 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - 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$PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - - POSIX - utc_UTest diff --git a/bsp/n32/n32g457qel-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.eww similarity index 100% rename from bsp/n32/n32g457qel-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.uvoptx new file mode 100644 index 0000000000..f188c982c4 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.uvoptx @@ -0,0 +1,1324 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + n32g45x_gpio.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + n32g45x_rcc.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + n32g45x_exti.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + n32g45x_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + n32g45x_dma.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + n32g45x_i2c.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + n32g45x_spi.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + n32g45x_can.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + n32g45x_adc.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + n32g45x_dac.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + n32g45x_tim.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + n32g45x_rtc.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + n32g45x_pwr.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + n32g45x_wwdg.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + n32g45x_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32g457qel-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g457qel-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g457qel-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/project.uvprojx diff --git a/bsp/n32/n32g45xrl-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g457qel-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g45xrl-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/rtconfig.h index e2e0b57871..506672db3f 100644 --- a/bsp/n32/n32g45xrl-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32g43xcl-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g457qel-stb/rtconfig.py similarity index 97% rename from bsp/n32/n32g43xcl-stb/rtconfig.py rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/rtconfig.py index 2a0371110c..c3765e6f08 100644 --- a/bsp/n32/n32g43xcl-stb/rtconfig.py +++ b/bsp/n32/n32gxx_lxx/n32g457qel-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g457qel-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g457qel-stb/template.ewp similarity index 100% rename from bsp/n32/n32g457qel-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/template.ewp diff --git a/bsp/n32/n32g457qel-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g457qel-stb/template.eww similarity index 100% rename from bsp/n32/n32g457qel-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/template.eww diff --git a/bsp/n32/n32g457qel-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g457qel-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g457qel-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/template.uvoptx diff --git a/bsp/n32/n32g457qel-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g457qel-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32g457qel-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g457qel-stb/template.uvprojx diff --git a/bsp/n32/n32g45xcl-stb/.config b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/.config similarity index 97% rename from bsp/n32/n32g45xcl-stb/.config rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/.config index 38a9ebefa7..ec0f05d433 100644 --- a/bsp/n32/n32g45xcl-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32g43xcl-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/Kconfig similarity index 88% rename from bsp/n32/n32g43xcl-stb/Kconfig rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/Kconfig index 73238d3a13..07edfefc34 100644 --- a/bsp/n32/n32g43xcl-stb/Kconfig +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/Kconfig @@ -2,7 +2,7 @@ mainmenu "RT-Thread Configuration" BSP_DIR := . -RTT_DIR := ../../.. +RTT_DIR := ../../../.. PKGS_DIR := packages diff --git a/bsp/n32/n32g45xcl-stb/README.md b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/README.md similarity index 100% rename from bsp/n32/n32g45xcl-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/README.md diff --git a/bsp/n32/n32g45xcl-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/SConscript similarity index 100% rename from bsp/n32/n32g45xcl-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/SConscript diff --git a/bsp/n32/n32g457qel-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/SConstruct similarity index 96% rename from bsp/n32/n32g457qel-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/SConstruct index bc987cd14d..133a133cba 100644 --- a/bsp/n32/n32g457qel-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g45xcl-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g45xcl-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/applications/SConscript diff --git a/bsp/n32/n32g45xcl-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g45xcl-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/applications/main.c diff --git a/bsp/n32/n32g45xcl-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/Kconfig diff --git a/bsp/n32/n32g45xcl-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/SConscript diff --git a/bsp/n32/n32g45xcl-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/board.c similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/board.c diff --git a/bsp/n32/n32g45xcl-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/board.h similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/board.h diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g45xcl-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g45xcl-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g45xcl-stb/figures/board.png b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/figures/board.png similarity index 100% rename from bsp/n32/n32g45xcl-stb/figures/board.png rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/figures/board.png diff --git a/bsp/n32/n32g45xcl-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.ewd similarity index 100% rename from bsp/n32/n32g45xcl-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.ewd diff --git a/bsp/n32/n32g45xcl-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.ewp similarity index 86% rename from bsp/n32/n32g45xcl-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.ewp index 8e9be79e66..525c4bad72 100644 --- a/bsp/n32/n32g45xcl-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,110 +2311,134 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c Libraries - - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c @@ -2450,50 +2446,50 @@ $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - - - POSIX utc_UTest diff --git a/bsp/n32/n32g45xcl-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.eww similarity index 100% rename from bsp/n32/n32g45xcl-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.uvoptx new file mode 100644 index 0000000000..dffdf2bc24 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.uvoptx @@ -0,0 +1,1329 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + system_n32g45x.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + n32g45x_gpio.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + n32g45x_rcc.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + n32g45x_exti.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + n32g45x_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + n32g45x_dma.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + n32g45x_i2c.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + n32g45x_spi.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + n32g45x_can.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + n32g45x_adc.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + n32g45x_dac.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + n32g45x_tim.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + n32g45x_rtc.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + n32g45x_pwr.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + n32g45x_wwdg.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + n32g45x_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32g45xcl-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g45xcl-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/project.uvprojx diff --git a/bsp/n32/n32g45xcl-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g45xcl-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/rtconfig.h index e2e0b57871..506672db3f 100644 --- a/bsp/n32/n32g45xcl-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32g45xcl-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/rtconfig.py similarity index 97% rename from bsp/n32/n32g45xcl-stb/rtconfig.py rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/rtconfig.py index 2a0371110c..c3765e6f08 100644 --- a/bsp/n32/n32g45xcl-stb/rtconfig.py +++ b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g45xcl-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.ewp similarity index 100% rename from bsp/n32/n32g45xcl-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.ewp diff --git a/bsp/n32/n32g45xcl-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.eww similarity index 100% rename from bsp/n32/n32g45xcl-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.eww diff --git a/bsp/n32/n32g45xcl-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g45xcl-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.uvoptx diff --git a/bsp/n32/n32g45xcl-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32g45xcl-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xcl-stb/template.uvprojx diff --git a/bsp/n32/n32g457qel-stb/.config b/bsp/n32/n32gxx_lxx/n32g45xml-stb/.config similarity index 97% rename from bsp/n32/n32g457qel-stb/.config rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/.config index b8eb0410ff..25021739e8 100644 --- a/bsp/n32/n32g457qel-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32g45xcl-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xml-stb/Kconfig similarity index 88% rename from bsp/n32/n32g45xcl-stb/Kconfig rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/Kconfig index 73238d3a13..07edfefc34 100644 --- a/bsp/n32/n32g45xcl-stb/Kconfig +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/Kconfig @@ -2,7 +2,7 @@ mainmenu "RT-Thread Configuration" BSP_DIR := . -RTT_DIR := ../../.. +RTT_DIR := ../../../.. PKGS_DIR := packages diff --git a/bsp/n32/n32g45xml-stb/README.md b/bsp/n32/n32gxx_lxx/n32g45xml-stb/README.md similarity index 100% rename from bsp/n32/n32g45xml-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/README.md diff --git a/bsp/n32/n32g45xml-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g45xml-stb/SConscript similarity index 100% rename from bsp/n32/n32g45xml-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/SConscript diff --git a/bsp/n32/n32g45xml-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g45xml-stb/SConstruct similarity index 96% rename from bsp/n32/n32g45xml-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/SConstruct index d6b0922512..c826a74f7f 100644 --- a/bsp/n32/n32g45xml-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g45xml-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g45xml-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g45xml-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/applications/SConscript diff --git a/bsp/n32/n32g45xml-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g45xml-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g45xml-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/applications/main.c diff --git a/bsp/n32/n32g45xml-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g45xml-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/Kconfig diff --git a/bsp/n32/n32g45xml-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g45xml-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/SConscript diff --git a/bsp/n32/n32g45xml-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/board.c similarity index 100% rename from bsp/n32/n32g45xml-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/board.c diff --git a/bsp/n32/n32g45xml-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/board.h similarity index 100% rename from bsp/n32/n32g45xml-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/board.h diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g45xml-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g45xml-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g45xml-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g45xml-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g45xml-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g45xml-stb/figures/board.png b/bsp/n32/n32gxx_lxx/n32g45xml-stb/figures/board.png similarity index 100% rename from bsp/n32/n32g45xml-stb/figures/board.png rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/figures/board.png diff --git a/bsp/n32/n32g45xml-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.ewd similarity index 100% rename from bsp/n32/n32g45xml-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/project.ewd diff --git a/bsp/n32/n32g45xml-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.ewp similarity index 86% rename from bsp/n32/n32g45xml-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/project.ewp index 6f05d12e06..6e2225de3d 100644 --- a/bsp/n32/n32g45xml-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,128 +2311,152 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - Libraries - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c + + + + Libraries + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c @@ -2468,33 +2464,33 @@ $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - - POSIX - utc_UTest diff --git a/bsp/n32/n32g45xml-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.eww similarity index 100% rename from bsp/n32/n32g45xml-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.uvoptx new file mode 100644 index 0000000000..f6a691da2f --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.uvoptx @@ -0,0 +1,1329 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + system_n32g45x.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + n32g45x_gpio.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + n32g45x_rcc.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + n32g45x_exti.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + n32g45x_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + n32g45x_dma.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + n32g45x_i2c.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + n32g45x_spi.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + n32g45x_can.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + n32g45x_adc.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + n32g45x_dac.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + n32g45x_tim.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + n32g45x_rtc.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + n32g45x_pwr.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + n32g45x_wwdg.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + n32g45x_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32g45xml-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xml-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g45xml-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/project.uvprojx diff --git a/bsp/n32/n32g45xml-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g45xml-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g45xml-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/rtconfig.h index e2e0b57871..506672db3f 100644 --- a/bsp/n32/n32g45xml-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32g45xml-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g45xml-stb/rtconfig.py similarity index 97% rename from bsp/n32/n32g45xml-stb/rtconfig.py rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/rtconfig.py index 2a0371110c..c3765e6f08 100644 --- a/bsp/n32/n32g45xml-stb/rtconfig.py +++ b/bsp/n32/n32gxx_lxx/n32g45xml-stb/rtconfig.py @@ -73,7 +73,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' diff --git a/bsp/n32/n32g45xml-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g45xml-stb/template.ewp similarity index 100% rename from bsp/n32/n32g45xml-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/template.ewp diff --git a/bsp/n32/n32g45xml-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g45xml-stb/template.eww similarity index 100% rename from bsp/n32/n32g45xml-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/template.eww diff --git a/bsp/n32/n32g45xml-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xml-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g45xml-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/template.uvoptx diff --git a/bsp/n32/n32g45xml-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xml-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32g45xml-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xml-stb/template.uvprojx diff --git a/bsp/n32/n32g45xml-stb/.config b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/.config similarity index 97% rename from bsp/n32/n32g45xml-stb/.config rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/.config index b8eb0410ff..25021739e8 100644 --- a/bsp/n32/n32g45xml-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32g45xrl-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32g45xrl-stb/README.md b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/README.md similarity index 100% rename from bsp/n32/n32g45xrl-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/README.md diff --git a/bsp/n32/n32g45xrl-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/SConscript similarity index 100% rename from bsp/n32/n32g45xrl-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/SConscript diff --git a/bsp/n32/n32g45xrl-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/SConstruct similarity index 96% rename from bsp/n32/n32g45xrl-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/SConstruct index bc987cd14d..133a133cba 100644 --- a/bsp/n32/n32g45xrl-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g45xrl-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g45xrl-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/applications/SConscript diff --git a/bsp/n32/n32g45xrl-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g45xrl-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/applications/main.c diff --git a/bsp/n32/n32g45xrl-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/Kconfig diff --git a/bsp/n32/n32g45xrl-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/SConscript diff --git a/bsp/n32/n32g45xrl-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/board.c similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/board.c diff --git a/bsp/n32/n32g45xrl-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/board.h similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/board.h diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g45xrl-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g45xrl-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g45xrl-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32g45xrl-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/figures/board.jpg diff --git a/bsp/n32/n32g45xrl-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.ewd similarity index 100% rename from bsp/n32/n32g45xrl-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.ewd diff --git a/bsp/n32/n32g45xrl-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.ewp similarity index 86% rename from bsp/n32/n32g45xrl-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.ewp index 1a898830f0..060d36f879 100644 --- a/bsp/n32/n32g45xrl-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,109 +2311,139 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c Libraries - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c @@ -2450,37 +2452,37 @@ $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c @@ -2488,12 +2490,6 @@ $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c - - - - POSIX utc_UTest diff --git a/bsp/n32/n32g45xrl-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.eww similarity index 100% rename from bsp/n32/n32g45xrl-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.uvoptx new file mode 100644 index 0000000000..de16f2dbab --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.uvoptx @@ -0,0 +1,1329 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457REL7$Flash\N32G45x.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457REL7$Flash\N32G45x.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 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..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + system_n32g45x.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + n32g45x_gpio.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + n32g45x_rcc.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + n32g45x_exti.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + n32g45x_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + n32g45x_dma.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + n32g45x_i2c.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + n32g45x_spi.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + n32g45x_can.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + n32g45x_adc.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + n32g45x_dac.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + n32g45x_tim.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + n32g45x_rtc.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + n32g45x_pwr.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + n32g45x_wwdg.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + n32g45x_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32g45xrl-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g45xrl-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/project.uvprojx diff --git a/bsp/n32/n32g457qel-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g457qel-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/rtconfig.h index e2e0b57871..506672db3f 100644 --- a/bsp/n32/n32g457qel-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32g45xrl-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32g45xrl-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.ewp similarity index 100% rename from bsp/n32/n32g45xrl-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.ewp diff --git a/bsp/n32/n32g45xrl-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.eww similarity index 100% rename from bsp/n32/n32g45xrl-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.eww diff --git a/bsp/n32/n32g45xrl-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g45xrl-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.uvoptx diff --git a/bsp/n32/n32g45xrl-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32g45xrl-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xrl-stb/template.uvprojx diff --git a/bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml similarity index 100% rename from bsp/n32/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/.ci/attachconfig/ci.attachconfig.yml diff --git a/bsp/n32/n32g45xvl-stb/.config b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/.config similarity index 97% rename from bsp/n32/n32g45xvl-stb/.config rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/.config index cb8bfc253e..972176a480 100644 --- a/bsp/n32/n32g45xvl-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32g45xvl-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32g45xvl-stb/README.md b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/README.md similarity index 100% rename from bsp/n32/n32g45xvl-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/README.md diff --git a/bsp/n32/n32g45xvl-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/SConscript similarity index 100% rename from bsp/n32/n32g45xvl-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/SConscript diff --git a/bsp/n32/n32g45xvl-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/SConstruct similarity index 96% rename from bsp/n32/n32g45xvl-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/SConstruct index bc987cd14d..133a133cba 100644 --- a/bsp/n32/n32g45xvl-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g45xvl-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g45xvl-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/applications/SConscript diff --git a/bsp/n32/n32g45xvl-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g45xvl-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/applications/main.c diff --git a/bsp/n32/n32g45xvl-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/Kconfig diff --git a/bsp/n32/n32g45xvl-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/SConscript diff --git a/bsp/n32/n32g45xvl-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/board.c similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/board.c diff --git a/bsp/n32/n32g45xvl-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/board.h similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/board.h diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g45xvl-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g45xvl-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g45xvl-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32g45xvl-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/figures/board.jpg diff --git a/bsp/n32/n32g45xvl-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.ewd similarity index 100% rename from bsp/n32/n32g45xvl-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.ewd diff --git a/bsp/n32/n32g45xvl-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.ewp similarity index 86% rename from bsp/n32/n32g45xvl-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.ewp index 60d65cbb1e..18d89ec013 100644 --- a/bsp/n32/n32g45xvl-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,161 +2311,185 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - Libraries - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c + + + + Libraries $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c - $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + + + $PROJ_DIR$\..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c - - - POSIX utc_UTest diff --git a/bsp/n32/n32g45xvl-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.eww similarity index 100% rename from bsp/n32/n32g45xvl-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.uvoptx new file mode 100644 index 0000000000..547c4b34a2 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.uvoptx @@ -0,0 +1,1329 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457VEL7$Flash\N32G45x.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0N32G45x.FLM -FS08000000 -FL080000 -FP0($$Device:N32G457VEL7$Flash\N32G45x.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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hwtimer.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + dev_i2c_bit_ops.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_core.c + dev_i2c_core.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_dev.c + dev_i2c_dev.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 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..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 8 + 74 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\CMSIS\device\system_n32g45x.c + system_n32g45x.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_gpio.c + n32g45x_gpio.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rcc.c + n32g45x_rcc.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_exti.c + n32g45x_exti.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_usart.c + n32g45x_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dma.c + n32g45x_dma.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_i2c.c + n32g45x_i2c.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_spi.c + n32g45x_spi.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_can.c + n32g45x_can.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_adc.c + n32g45x_adc.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_dac.c + n32g45x_dac.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_tim.c + n32g45x_tim.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_rtc.c + n32g45x_rtc.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_pwr.c + n32g45x_pwr.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_wwdg.c + n32g45x_wwdg.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\libraries\N32G45x_Firmware_Library\n32g45x_std_periph_driver\src\n32g45x_iwdg.c + n32g45x_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32g45xvl-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g45xvl-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/project.uvprojx diff --git a/bsp/n32/n32g45xvl-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g45xvl-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/rtconfig.h index d9a019d68c..2175a80b37 100644 --- a/bsp/n32/n32g45xvl-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32g45xvl-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32g45xvl-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.ewp similarity index 100% rename from bsp/n32/n32g45xvl-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.ewp diff --git a/bsp/n32/n32g45xvl-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.eww similarity index 100% rename from bsp/n32/n32g45xvl-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.eww diff --git a/bsp/n32/n32g45xvl-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g45xvl-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.uvoptx diff --git a/bsp/n32/n32g45xvl-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32g45xvl-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g45xvl-stb/template.uvprojx diff --git a/bsp/n32/n32g4frml-stb/.config b/bsp/n32/n32gxx_lxx/n32g4frml-stb/.config similarity index 97% rename from bsp/n32/n32g4frml-stb/.config rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/.config index 06c31eee58..fa4247eb2e 100644 --- a/bsp/n32/n32g4frml-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32g4frml-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32g4frml-stb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32g4frml-stb/README.md b/bsp/n32/n32gxx_lxx/n32g4frml-stb/README.md similarity index 100% rename from bsp/n32/n32g4frml-stb/README.md rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/README.md diff --git a/bsp/n32/n32g4frml-stb/SConscript b/bsp/n32/n32gxx_lxx/n32g4frml-stb/SConscript similarity index 100% rename from bsp/n32/n32g4frml-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/SConscript diff --git a/bsp/n32/n32g4frml-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32g4frml-stb/SConstruct similarity index 96% rename from bsp/n32/n32g4frml-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/SConstruct index ef571d5871..9e3b2adbb4 100644 --- a/bsp/n32/n32g4frml-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32g4frml-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32g4frml-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32g4frml-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/applications/SConscript diff --git a/bsp/n32/n32g4frml-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32g4frml-stb/applications/main.c similarity index 100% rename from bsp/n32/n32g4frml-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/applications/main.c diff --git a/bsp/n32/n32g4frml-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32g4frml-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/Kconfig diff --git a/bsp/n32/n32g4frml-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/SConscript similarity index 100% rename from bsp/n32/n32g4frml-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/SConscript diff --git a/bsp/n32/n32g4frml-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/board.c similarity index 100% rename from bsp/n32/n32g4frml-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/board.c diff --git a/bsp/n32/n32g4frml-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/board.h similarity index 100% rename from bsp/n32/n32g4frml-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/board.h diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32g4frml-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32g4frml-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32g4frml-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32g4frml-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32g4frml-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32g4frml-stb/figures/board.png b/bsp/n32/n32gxx_lxx/n32g4frml-stb/figures/board.png similarity index 100% rename from bsp/n32/n32g4frml-stb/figures/board.png rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/figures/board.png diff --git a/bsp/n32/n32g4frml-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.ewd similarity index 100% rename from bsp/n32/n32g4frml-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/project.ewd diff --git a/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.ewp new file mode 100644 index 0000000000..a0c4b8752b --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.ewp @@ -0,0 +1,2496 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + CPU + + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c + + + $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c + + + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c + + + + Drivers + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\CMSIS\device\startup\startup_n32g4fr_EWARM.s + + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_adc.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_can.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_dac.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_timer.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_rtc.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_spi.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\n32_drivers\drv_wdt.c + + + + Finsh + + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\..\src\cpu_up.c + + + $PROJ_DIR$\..\..\..\..\src\defunct.c + + + $PROJ_DIR$\..\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c + + + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c + + + $PROJ_DIR$\..\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\..\src\timer.c + + + + Libc + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c + + + + libraries + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\CMSIS\device\system_n32g4fr.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_gpio.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_rcc.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_exti.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\misc.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_usart.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_i2c.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_spi.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_can.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_adc.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_dac.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_tim.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_rtc.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_wwdg.c + + + $PROJ_DIR$\..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_iwdg.c + + + + utc_UTest + + + utestcases + + diff --git a/bsp/n32/n32g4frml-stb/project.eww b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.eww similarity index 100% rename from bsp/n32/n32g4frml-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.uvoptx new file mode 100644 index 0000000000..c03c7a33f0 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.uvoptx @@ -0,0 +1,1305 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0N32G4FR.FLM -FS08000000 -FL080000 -FP0($$Device:N32G4FRMEL7$Flash\N32G4FR.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G4FR -FL080000 -FS08000000 -FP0($$Device:N32G4FRMEL7$Flash\N32G4FR.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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hwtimer.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + dev_i2c_bit_ops.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_core.c + dev_i2c_core.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_dev.c + dev_i2c_dev.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + 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drv_usart.c + 0 + 0 + + + 4 + 40 + 1 + 0 + 0 + 0 + ..\libraries\n32_drivers\drv_wdt.c + drv_wdt.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 5 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 5 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 6 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\src\defunct.c + defunct.c + 0 + 0 + + + 6 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + 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..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + libraries + 0 + 0 + 0 + 0 + + 8 + 74 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\CMSIS\device\system_n32g4fr.c + system_n32g4fr.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_gpio.c + n32g4fr_gpio.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_rcc.c + n32g4fr_rcc.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_exti.c + n32g4fr_exti.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_usart.c + n32g4fr_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_i2c.c + n32g4fr_i2c.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_spi.c + n32g4fr_spi.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_can.c + n32g4fr_can.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_adc.c + n32g4fr_adc.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_dac.c + n32g4fr_dac.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_tim.c + n32g4fr_tim.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_rtc.c + n32g4fr_rtc.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_wwdg.c + n32g4fr_wwdg.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32G4FR_Firmware_Library\n32g4fr_std_periph_driver\src\n32g4fr_iwdg.c + n32g4fr_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32g4frml-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32g4frml-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32g4frml-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/project.uvprojx diff --git a/bsp/n32/n32g4frml-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32g4frml-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32g4frml-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/rtconfig.h index dd1890c4ce..f173033882 100644 --- a/bsp/n32/n32g4frml-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32g4frml-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32g4frml-stb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32g4frml-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32g4frml-stb/template.ewp similarity index 92% rename from bsp/n32/n32g4frml-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/template.ewp index 8b6420c8a1..b80dc67c93 100644 --- a/bsp/n32/n32g4frml-stb/template.ewp +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/template.ewp @@ -11,13 +11,9 @@ General 3 - 33 + 31 1 1 - + + + + + - - ICCARM 2 - 37 + 36 1 1 + + + @@ -652,9 +672,13 @@ 0 - inputOutputBased + + BICOMP + 0 + + BUILDACTION 1 @@ -667,13 +691,17 @@ ILINK 0 - 25 + 23 1 1 + - - - - - @@ -1042,6 +1050,11 @@ + + BILINK + 0 + + Release @@ -1053,13 +1066,9 @@ General 3 - 33 + 31 1 0 - + + + + + - - ICCARM 2 - 37 + 36 1 0 + + + @@ -1694,9 +1727,13 @@ 0 - inputOutputBased + + BICOMP + 0 + + BUILDACTION 1 @@ -1709,13 +1746,17 @@ ILINK 0 - 25 + 23 1 0 + - - - - - @@ -2084,5 +2105,10 @@ + + BILINK + 0 + + diff --git a/bsp/n32/n32g4frml-stb/template.eww b/bsp/n32/n32gxx_lxx/n32g4frml-stb/template.eww similarity index 100% rename from bsp/n32/n32g4frml-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/template.eww diff --git a/bsp/n32/n32g4frml-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32g4frml-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32g4frml-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/template.uvoptx diff --git a/bsp/n32/n32g4frml-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32g4frml-stb/template.uvprojx similarity index 98% rename from bsp/n32/n32g4frml-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32g4frml-stb/template.uvprojx index 8c3a51f09e..82f674564a 100644 --- a/bsp/n32/n32g4frml-stb/template.uvprojx +++ b/bsp/n32/n32gxx_lxx/n32g4frml-stb/template.uvprojx @@ -16,7 +16,7 @@ N32G4FRMEL7 Nationstech - Nationstech.N32G4FR_DFP.1.0.4 + Nationstech.N32G4FR_DFP.1.1.1 http://www.keil.com/pack/ IRAM(0x20000000,0x24000) IROM(0x08000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -404,11 +404,6 @@ template - - - - - 0 1 diff --git a/bsp/n32/n32l40xcl-stb/.config b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/.config similarity index 97% rename from bsp/n32/n32l40xcl-stb/.config rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/.config index f9070b0e8e..3aa3f33ae4 100644 --- a/bsp/n32/n32l40xcl-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/.config @@ -179,7 +179,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -267,6 +267,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -361,8 +363,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +371,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -572,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -596,6 +598,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -644,6 +647,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -738,6 +744,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -893,7 +900,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -939,9 +962,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1066,6 +1091,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32l40xcl-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32l40xcl-stb/README.md b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/README.md similarity index 100% rename from bsp/n32/n32l40xcl-stb/README.md rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/README.md diff --git a/bsp/n32/n32l40xcl-stb/SConscript b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/SConscript similarity index 100% rename from bsp/n32/n32l40xcl-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/SConscript diff --git a/bsp/n32/n32l40xcl-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/SConstruct similarity index 96% rename from bsp/n32/n32l40xcl-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/SConstruct index 59d77be5c7..cc8121e4a1 100644 --- a/bsp/n32/n32l40xcl-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32l40xcl-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32l40xcl-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/applications/SConscript diff --git a/bsp/n32/n32l40xcl-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/applications/main.c similarity index 100% rename from bsp/n32/n32l40xcl-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/applications/main.c diff --git a/bsp/n32/n32l40xcl-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/Kconfig diff --git a/bsp/n32/n32l40xcl-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/SConscript similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/SConscript diff --git a/bsp/n32/n32l40xcl-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/board.c similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/board.c diff --git a/bsp/n32/n32l40xcl-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/board.h similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/board.h diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32l40xcl-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32l40xcl-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32l40xcl-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32l40xcl-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/figures/board.jpg diff --git a/bsp/n32/n32l40xcl-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.ewd similarity index 100% rename from bsp/n32/n32l40xcl-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.ewd diff --git a/bsp/n32/n32l40xcl-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.ewp similarity index 86% rename from bsp/n32/n32l40xcl-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.ewp index 74de3b8931..5dd4fe22a6 100644 --- a/bsp/n32/n32l40xcl-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,158 +2308,185 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + 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$PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\CMSIS\device\system_n32l40x.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_gpio.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rcc.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_exti.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\misc.c $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_usart.c + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_i2c.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_spi.c + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_can.c + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_adc.c + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_dac.c + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_tim.c + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rtc.c - $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_pwr.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_flash.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_iwdg.c + + + $PROJ_DIR$\..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_wwdg.c - - - POSIX utc_UTest diff --git a/bsp/n32/n32l40xcl-stb/project.eww b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.eww similarity index 100% rename from bsp/n32/n32l40xcl-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.uvoptx new file mode 100644 index 0000000000..f0932d6a46 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.uvoptx @@ -0,0 +1,1317 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_can.c + n32l40x_can.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_adc.c + n32l40x_adc.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_dac.c + n32l40x_dac.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_tim.c + n32l40x_tim.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_rtc.c + n32l40x_rtc.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_pwr.c + n32l40x_pwr.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_flash.c + n32l40x_flash.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_iwdg.c + n32l40x_iwdg.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32L40x_Firmware_Library\n32l40x_std_periph_driver\src\n32l40x_wwdg.c + n32l40x_wwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32l40xcl-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32l40xcl-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/project.uvprojx diff --git a/bsp/n32/n32l40xcl-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32l40xcl-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/rtconfig.h index 236a2cdae7..a05bc5d0c3 100644 --- a/bsp/n32/n32l40xcl-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ @@ -155,6 +155,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -327,6 +328,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32l40xcl-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l40xcl-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.ewp similarity index 100% rename from bsp/n32/n32l40xcl-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.ewp diff --git a/bsp/n32/n32l40xcl-stb/template.eww b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.eww similarity index 100% rename from bsp/n32/n32l40xcl-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.eww diff --git a/bsp/n32/n32l40xcl-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32l40xcl-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.uvoptx diff --git a/bsp/n32/n32l40xcl-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32l40xcl-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32l40xcl-stb/template.uvprojx diff --git a/bsp/n32/n32l436-evb/.config b/bsp/n32/n32gxx_lxx/n32l436-evb/.config similarity index 97% rename from bsp/n32/n32l436-evb/.config rename to bsp/n32/n32gxx_lxx/n32l436-evb/.config index 26c579656c..fef23158b5 100644 --- a/bsp/n32/n32l436-evb/.config +++ b/bsp/n32/n32gxx_lxx/n32l436-evb/.config @@ -179,7 +179,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -267,6 +267,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -361,8 +363,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +371,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -572,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -596,6 +598,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -644,6 +647,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -738,6 +744,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -893,7 +900,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -939,9 +962,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1066,6 +1091,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32l436-evb/Kconfig b/bsp/n32/n32gxx_lxx/n32l436-evb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l436-evb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32l436-evb/README.md b/bsp/n32/n32gxx_lxx/n32l436-evb/README.md similarity index 100% rename from bsp/n32/n32l436-evb/README.md rename to bsp/n32/n32gxx_lxx/n32l436-evb/README.md diff --git a/bsp/n32/n32l436-evb/SConscript b/bsp/n32/n32gxx_lxx/n32l436-evb/SConscript similarity index 100% rename from bsp/n32/n32l436-evb/SConscript rename to bsp/n32/n32gxx_lxx/n32l436-evb/SConscript diff --git a/bsp/n32/n32l436-evb/SConstruct b/bsp/n32/n32gxx_lxx/n32l436-evb/SConstruct similarity index 96% rename from bsp/n32/n32l436-evb/SConstruct rename to bsp/n32/n32gxx_lxx/n32l436-evb/SConstruct index cfa5f35aba..14aafb0a2f 100644 --- a/bsp/n32/n32l436-evb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32l436-evb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32l436-evb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32l436-evb/applications/SConscript similarity index 100% rename from bsp/n32/n32l436-evb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32l436-evb/applications/SConscript diff --git a/bsp/n32/n32l436-evb/applications/main.c b/bsp/n32/n32gxx_lxx/n32l436-evb/applications/main.c similarity index 100% rename from bsp/n32/n32l436-evb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32l436-evb/applications/main.c diff --git a/bsp/n32/n32l436-evb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32l436-evb/board/Kconfig similarity index 100% rename from bsp/n32/n32l436-evb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/Kconfig diff --git a/bsp/n32/n32l436-evb/board/SConscript b/bsp/n32/n32gxx_lxx/n32l436-evb/board/SConscript similarity index 100% rename from bsp/n32/n32l436-evb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/SConscript diff --git a/bsp/n32/n32l436-evb/board/board.c b/bsp/n32/n32gxx_lxx/n32l436-evb/board/board.c similarity index 100% rename from bsp/n32/n32l436-evb/board/board.c rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/board.c diff --git a/bsp/n32/n32l436-evb/board/board.h b/bsp/n32/n32gxx_lxx/n32l436-evb/board/board.h similarity index 100% rename from bsp/n32/n32l436-evb/board/board.h rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/board.h diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32l436-evb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32l436-evb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32l436-evb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32l436-evb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32l436-evb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32l436-evb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32l436-evb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32l436-evb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32l436-evb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32l436-evb/figures/board.jpg similarity index 100% rename from bsp/n32/n32l436-evb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32l436-evb/figures/board.jpg diff --git a/bsp/n32/n32l436-evb/project.ewd b/bsp/n32/n32gxx_lxx/n32l436-evb/project.ewd similarity index 100% rename from bsp/n32/n32l436-evb/project.ewd rename to bsp/n32/n32gxx_lxx/n32l436-evb/project.ewd diff --git a/bsp/n32/n32l436-evb/project.ewp b/bsp/n32/n32gxx_lxx/n32l436-evb/project.ewp similarity index 86% rename from bsp/n32/n32l436-evb/project.ewp rename to bsp/n32/n32gxx_lxx/n32l436-evb/project.ewp index b364f0ffdc..4c5c5570ce 100644 --- a/bsp/n32/n32l436-evb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32l436-evb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,158 +2308,185 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - Libraries - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c + + + + Libraries + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_exti.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_tim.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c - - - POSIX utc_UTest diff --git a/bsp/n32/n32l436-evb/project.eww b/bsp/n32/n32gxx_lxx/n32l436-evb/project.eww similarity index 100% rename from bsp/n32/n32l436-evb/project.eww rename to bsp/n32/n32gxx_lxx/n32l436-evb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32l436-evb/project.uvoptx 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 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cstring.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 8 + 73 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + system_n32l43x.c + 0 + 0 + + + 8 + 74 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + n32l43x_gpio.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c + n32l43x_rcc.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_exti.c + n32l43x_exti.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c + n32l43x_usart.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c + n32l43x_i2c.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c + n32l43x_spi.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + n32l43x_can.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c + n32l43x_adc.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c + n32l43x_dac.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_tim.c + n32l43x_tim.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + n32l43x_rtc.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + n32l43x_pwr.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + n32l43x_flash.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + n32l43x_iwdg.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c + n32l43x_wwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32l436-evb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32l436-evb/project.uvprojx similarity index 100% rename from bsp/n32/n32l436-evb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32l436-evb/project.uvprojx diff --git a/bsp/n32/n32l43xrl-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32l436-evb/rtconfig.h similarity index 98% rename from bsp/n32/n32l43xrl-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32l436-evb/rtconfig.h index a454f9f412..57bcc7aab0 100644 --- a/bsp/n32/n32l43xrl-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32l436-evb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ @@ -155,6 +155,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -327,6 +328,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32l436-evb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32l436-evb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l436-evb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l436-evb/template.ewp b/bsp/n32/n32gxx_lxx/n32l436-evb/template.ewp similarity index 100% rename from bsp/n32/n32l436-evb/template.ewp rename to bsp/n32/n32gxx_lxx/n32l436-evb/template.ewp diff --git a/bsp/n32/n32l436-evb/template.eww b/bsp/n32/n32gxx_lxx/n32l436-evb/template.eww similarity index 100% rename from bsp/n32/n32l436-evb/template.eww rename to bsp/n32/n32gxx_lxx/n32l436-evb/template.eww diff --git a/bsp/n32/n32l436-evb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32l436-evb/template.uvoptx similarity index 100% rename from bsp/n32/n32l436-evb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32l436-evb/template.uvoptx diff --git a/bsp/n32/n32l436-evb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32l436-evb/template.uvprojx similarity index 100% rename from bsp/n32/n32l436-evb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32l436-evb/template.uvprojx diff --git a/bsp/n32/n32l43xml-stb/.config b/bsp/n32/n32gxx_lxx/n32l43xml-stb/.config similarity index 97% rename from bsp/n32/n32l43xml-stb/.config rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/.config index 26c579656c..fef23158b5 100644 --- a/bsp/n32/n32l43xml-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/.config @@ -179,7 +179,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -267,6 +267,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -361,8 +363,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +371,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -572,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -596,6 +598,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -644,6 +647,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -738,6 +744,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -893,7 +900,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -939,9 +962,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1066,6 +1091,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32l43xml-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32l43xml-stb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32l43xml-stb/README.md b/bsp/n32/n32gxx_lxx/n32l43xml-stb/README.md similarity index 100% rename from bsp/n32/n32l43xml-stb/README.md rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/README.md diff --git a/bsp/n32/n32l43xml-stb/SConscript b/bsp/n32/n32gxx_lxx/n32l43xml-stb/SConscript similarity index 100% rename from bsp/n32/n32l43xml-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/SConscript diff --git a/bsp/n32/n32l43xml-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32l43xml-stb/SConstruct similarity index 96% rename from bsp/n32/n32l43xml-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/SConstruct index cfa5f35aba..14aafb0a2f 100644 --- a/bsp/n32/n32l43xml-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32l43xml-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32l43xml-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32l43xml-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/applications/SConscript diff --git a/bsp/n32/n32l43xml-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32l43xml-stb/applications/main.c similarity index 100% rename from bsp/n32/n32l43xml-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/applications/main.c diff --git a/bsp/n32/n32l43xml-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32l43xml-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/Kconfig diff --git a/bsp/n32/n32l43xml-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/SConscript similarity index 100% rename from bsp/n32/n32l43xml-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/SConscript diff --git a/bsp/n32/n32l43xml-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/board.c similarity index 100% rename from bsp/n32/n32l43xml-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/board.c diff --git a/bsp/n32/n32l43xml-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/board.h similarity index 100% rename from bsp/n32/n32l43xml-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/board.h diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32l43xml-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32l43xml-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32l43xml-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32l43xml-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32l43xml-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32l43xml-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32l43xml-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32l43xml-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/figures/board.jpg diff --git a/bsp/n32/n32l43xml-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.ewd similarity index 100% rename from bsp/n32/n32l43xml-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/project.ewd diff --git a/bsp/n32/n32l43xml-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.ewp similarity index 86% rename from bsp/n32/n32l43xml-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/project.ewp index 6b37926739..4c5c5570ce 100644 --- a/bsp/n32/n32l43xml-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,158 +2308,185 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - Libraries - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c + + + + Libraries + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_exti.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_tim.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + + + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c - - - POSIX utc_UTest diff --git a/bsp/n32/n32l43xml-stb/project.eww b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.eww similarity index 100% rename from bsp/n32/n32l43xml-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.uvoptx new file mode 100644 index 0000000000..a8f4dba884 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.uvoptx @@ -0,0 +1,1317 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 4 + 2 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\can\dev_can.c + dev_can.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + dev_i2c_bit_ops.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_core.c + dev_i2c_core.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\i2c\dev_i2c_dev.c + dev_i2c_dev.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 3 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cstring.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 8 + 73 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + system_n32l43x.c + 0 + 0 + + + 8 + 74 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + n32l43x_gpio.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c + n32l43x_rcc.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_exti.c + n32l43x_exti.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c + n32l43x_usart.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c + n32l43x_i2c.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c + n32l43x_spi.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + n32l43x_can.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c + n32l43x_adc.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c + n32l43x_dac.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_tim.c + n32l43x_tim.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + n32l43x_rtc.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + n32l43x_pwr.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + n32l43x_flash.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + n32l43x_iwdg.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c + n32l43x_wwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32l43xml-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32l43xml-stb/project.uvprojx similarity index 100% rename from bsp/n32/n32l43xml-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/project.uvprojx diff --git a/bsp/n32/n32l436-evb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32l43xml-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32l436-evb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/rtconfig.h index a454f9f412..57bcc7aab0 100644 --- a/bsp/n32/n32l436-evb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ @@ -155,6 +155,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -327,6 +328,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32l43xml-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32l43xml-stb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l43xml-stb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l43xml-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32l43xml-stb/template.ewp similarity index 100% rename from bsp/n32/n32l43xml-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/template.ewp diff --git a/bsp/n32/n32l43xml-stb/template.eww b/bsp/n32/n32gxx_lxx/n32l43xml-stb/template.eww similarity index 100% rename from bsp/n32/n32l43xml-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/template.eww diff --git a/bsp/n32/n32l43xml-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32l43xml-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32l43xml-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/template.uvoptx diff --git a/bsp/n32/n32l43xml-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32l43xml-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32l43xml-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32l43xml-stb/template.uvprojx diff --git a/bsp/n32/n32l43xrl-stb/.config b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/.config similarity index 97% rename from bsp/n32/n32l43xrl-stb/.config rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/.config index 26c579656c..fef23158b5 100644 --- a/bsp/n32/n32l43xrl-stb/.config +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/.config @@ -179,7 +179,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -267,6 +267,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -361,8 +363,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -371,6 +371,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -572,6 +573,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -596,6 +598,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -644,6 +647,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -738,6 +744,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -893,7 +900,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -939,9 +962,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1066,6 +1091,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32l43xrl-stb/Kconfig b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32l43xrl-stb/README.md b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/README.md similarity index 100% rename from bsp/n32/n32l43xrl-stb/README.md rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/README.md diff --git a/bsp/n32/n32l43xrl-stb/SConscript b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/SConscript similarity index 100% rename from bsp/n32/n32l43xrl-stb/SConscript rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/SConscript diff --git a/bsp/n32/n32l43xrl-stb/SConstruct b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/SConstruct similarity index 96% rename from bsp/n32/n32l43xrl-stb/SConstruct rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/SConstruct index cfa5f35aba..14aafb0a2f 100644 --- a/bsp/n32/n32l43xrl-stb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32l43xrl-stb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/applications/SConscript similarity index 100% rename from bsp/n32/n32l43xrl-stb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/applications/SConscript diff --git a/bsp/n32/n32l43xrl-stb/applications/main.c b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/applications/main.c similarity index 100% rename from bsp/n32/n32l43xrl-stb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/applications/main.c diff --git a/bsp/n32/n32l43xrl-stb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/Kconfig similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/Kconfig diff --git a/bsp/n32/n32l43xrl-stb/board/SConscript b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/SConscript similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/SConscript diff --git a/bsp/n32/n32l43xrl-stb/board/board.c b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/board.c similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/board.c rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/board.c diff --git a/bsp/n32/n32l43xrl-stb/board/board.h b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/board.h similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/board.h rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/board.h diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32l43xrl-stb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32l43xrl-stb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32l43xrl-stb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/figures/board.jpg similarity index 100% rename from bsp/n32/n32l43xrl-stb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/figures/board.jpg diff --git a/bsp/n32/n32l43xrl-stb/project.ewd b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.ewd similarity index 100% rename from bsp/n32/n32l43xrl-stb/project.ewd rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.ewd diff --git a/bsp/n32/n32l43xrl-stb/project.ewp b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.ewp similarity index 86% rename from bsp/n32/n32l43xrl-stb/project.ewp rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.ewp index c0cb073932..1c3cb1642b 100644 --- a/bsp/n32/n32l43xrl-stb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,130 +2308,160 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c Libraries - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_tim.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_exti.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_exti.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rcc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c @@ -2471,27 +2470,24 @@ $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_tim.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c - $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + $PROJ_DIR$\..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_wwdg.c - - POSIX - utc_UTest diff --git a/bsp/n32/n32l43xrl-stb/project.eww b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.eww similarity index 100% rename from bsp/n32/n32l43xrl-stb/project.eww rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.eww diff --git a/bsp/n32/n32l43xrl-stb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.uvoptx similarity index 100% rename from bsp/n32/n32l43xrl-stb/project.uvoptx rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.uvoptx diff --git a/bsp/n32/n32l43xrl-stb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.uvprojx similarity index 89% rename from bsp/n32/n32l43xrl-stb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.uvprojx index 3b5c38167a..8c874cac0a 100644 --- a/bsp/n32/n32l43xrl-stb/project.uvprojx +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/project.uvprojx @@ -334,9 +334,9 @@ 0 - USE_STDPERIPH_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, RT_USING_ARMLIBC, N32L43X + USE_STDPERIPH_DRIVER, RT_USING_ARMLIBC, N32L43X, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND - ..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\..\..\components\drivers\smp_call;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\libraries\n32_drivers;..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\inc;..\..\..\components\drivers\phy;..\libraries\N32L43x_Firmware_Library\CMSIS\device;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\n32_drivers\config;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;applications;..\..\..\components\finsh;.;..\..\..\libcpu\arm\cortex-m4;..\libraries\N32L43x_Firmware_Library\CMSIS\core;..\..\..\components\drivers\spi + ..\..\..\..\components\drivers\include;.;..\libraries\N32L43x_Firmware_Library\CMSIS\core;..\libraries\N32L43x_Firmware_Library\CMSIS\device;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include;..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\inc;..\..\..\..\include;..\..\..\..\components\libc\compilers\common\include;..\libraries\n32_drivers\config;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\phy;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;board;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;applications;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\libraries\n32_drivers;..\..\..\..\components\net\utest;..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\spi;..\..\..\..\components\drivers\include @@ -388,61 +388,33 @@ - Compiler + CPU - syscall_mem.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c - 1 - ..\..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c + div0.c 1 - ..\..\..\components\libc\compilers\common\cstring.c + ..\..\..\..\libcpu\arm\common\div0.c - ctime.c + showmem.c 1 - ..\..\..\components\libc\compilers\common\ctime.c + ..\..\..\..\libcpu\arm\common\showmem.c - cunistd.c - 1 - ..\..\..\components\libc\compilers\common\cunistd.c + context_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S - cwchar.c + cpuport.c 1 - ..\..\..\components\libc\compilers\common\cwchar.c + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c @@ -452,7 +424,7 @@ dev_can.c 1 - ..\..\..\components\drivers\can\dev_can.c + ..\..\..\..\components\drivers\can\dev_can.c @@ -471,7 +443,7 @@ device.c 1 - ..\..\..\components\drivers\core\device.c + ..\..\..\..\components\drivers\core\device.c @@ -509,7 +481,7 @@ dev_i2c_bit_ops.c 1 - ..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + ..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c @@ -528,7 +500,7 @@ dev_i2c_core.c 1 - ..\..\..\components\drivers\i2c\dev_i2c_core.c + ..\..\..\..\components\drivers\i2c\dev_i2c_core.c @@ -547,7 +519,7 @@ dev_i2c_dev.c 1 - ..\..\..\components\drivers\i2c\dev_i2c_dev.c + ..\..\..\..\components\drivers\i2c\dev_i2c_dev.c @@ -566,7 +538,7 @@ completion_comm.c 1 - ..\..\..\components\drivers\ipc\completion_comm.c + ..\..\..\..\components\drivers\ipc\completion_comm.c @@ -585,7 +557,7 @@ completion_up.c 1 - ..\..\..\components\drivers\ipc\completion_up.c + ..\..\..\..\components\drivers\ipc\completion_up.c @@ -604,7 +576,7 @@ condvar.c 1 - ..\..\..\components\drivers\ipc\condvar.c + ..\..\..\..\components\drivers\ipc\condvar.c @@ -623,7 +595,7 @@ dataqueue.c 1 - ..\..\..\components\drivers\ipc\dataqueue.c + ..\..\..\..\components\drivers\ipc\dataqueue.c @@ -642,7 +614,7 @@ pipe.c 1 - ..\..\..\components\drivers\ipc\pipe.c + ..\..\..\..\components\drivers\ipc\pipe.c @@ -661,7 +633,7 @@ ringblk_buf.c 1 - ..\..\..\components\drivers\ipc\ringblk_buf.c + ..\..\..\..\components\drivers\ipc\ringblk_buf.c @@ -680,7 +652,7 @@ ringbuffer.c 1 - ..\..\..\components\drivers\ipc\ringbuffer.c + ..\..\..\..\components\drivers\ipc\ringbuffer.c @@ -699,7 +671,7 @@ waitqueue.c 1 - ..\..\..\components\drivers\ipc\waitqueue.c + ..\..\..\..\components\drivers\ipc\waitqueue.c @@ -718,7 +690,7 @@ workqueue.c 1 - ..\..\..\components\drivers\ipc\workqueue.c + ..\..\..\..\components\drivers\ipc\workqueue.c @@ -737,7 +709,7 @@ adc.c 1 - ..\..\..\components\drivers\misc\adc.c + ..\..\..\..\components\drivers\misc\adc.c @@ -756,7 +728,7 @@ dac.c 1 - ..\..\..\components\drivers\misc\dac.c + ..\..\..\..\components\drivers\misc\dac.c @@ -775,7 +747,7 @@ dev_pin.c 1 - ..\..\..\components\drivers\pin\dev_pin.c + ..\..\..\..\components\drivers\pin\dev_pin.c @@ -794,7 +766,7 @@ dev_rtc.c 1 - ..\..\..\components\drivers\rtc\dev_rtc.c + ..\..\..\..\components\drivers\rtc\dev_rtc.c @@ -813,7 +785,7 @@ dev_serial.c 1 - ..\..\..\components\drivers\serial\dev_serial.c + ..\..\..\..\components\drivers\serial\dev_serial.c @@ -832,7 +804,7 @@ dev_spi.c 1 - ..\..\..\components\drivers\spi\dev_spi.c + ..\..\..\..\components\drivers\spi\dev_spi.c @@ -851,7 +823,7 @@ dev_spi_core.c 1 - ..\..\..\components\drivers\spi\dev_spi_core.c + ..\..\..\..\components\drivers\spi\dev_spi_core.c @@ -870,7 +842,7 @@ dev_watchdog.c 1 - ..\..\..\components\drivers\watchdog\dev_watchdog.c + ..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -970,30 +942,30 @@ Finsh - cmd.c + shell.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\..\components\finsh\shell.c - shell.c + msh.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\..\components\finsh\msh.c msh_parse.c 1 - ..\..\..\components\finsh\msh_parse.c + ..\..\..\..\components\finsh\msh_parse.c - msh.c + cmd.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\..\components\finsh\cmd.c @@ -1003,7 +975,7 @@ clock.c 1 - ..\..\..\src\clock.c + ..\..\..\..\src\clock.c @@ -1022,7 +994,7 @@ components.c 1 - ..\..\..\src\components.c + ..\..\..\..\src\components.c @@ -1041,7 +1013,7 @@ cpu_up.c 1 - ..\..\..\src\cpu_up.c + ..\..\..\..\src\cpu_up.c @@ -1060,7 +1032,7 @@ defunct.c 1 - ..\..\..\src\defunct.c + ..\..\..\..\src\defunct.c @@ -1079,7 +1051,7 @@ idle.c 1 - ..\..\..\src\idle.c + ..\..\..\..\src\idle.c @@ -1098,7 +1070,7 @@ ipc.c 1 - ..\..\..\src\ipc.c + ..\..\..\..\src\ipc.c @@ -1117,7 +1089,7 @@ irq.c 1 - ..\..\..\src\irq.c + ..\..\..\..\src\irq.c @@ -1136,7 +1108,7 @@ kservice.c 1 - ..\..\..\src\kservice.c + ..\..\..\..\src\kservice.c @@ -1155,7 +1127,7 @@ mem.c 1 - ..\..\..\src\mem.c + ..\..\..\..\src\mem.c @@ -1174,7 +1146,7 @@ memheap.c 1 - ..\..\..\src\memheap.c + ..\..\..\..\src\memheap.c @@ -1193,7 +1165,7 @@ mempool.c 1 - ..\..\..\src\mempool.c + ..\..\..\..\src\mempool.c @@ -1212,7 +1184,7 @@ object.c 1 - ..\..\..\src\object.c + ..\..\..\..\src\object.c @@ -1231,7 +1203,7 @@ scheduler_comm.c 1 - ..\..\..\src\scheduler_comm.c + ..\..\..\..\src\scheduler_comm.c @@ -1250,7 +1222,7 @@ scheduler_up.c 1 - ..\..\..\src\scheduler_up.c + ..\..\..\..\src\scheduler_up.c @@ -1269,7 +1241,7 @@ thread.c 1 - ..\..\..\src\thread.c + ..\..\..\..\src\thread.c @@ -1288,7 +1260,7 @@ timer.c 1 - ..\..\..\src\timer.c + ..\..\..\..\src\timer.c @@ -1305,116 +1277,113 @@ - klibc + Libc - rt_vsnprintf_tiny.c + syscall_mem.c 1 - ..\..\..\src\klibc\rt_vsnprintf_tiny.c + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c - rt_vsscanf.c + syscalls.c 1 - ..\..\..\src\klibc\rt_vsscanf.c + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c - kstring.c + cctype.c 1 - ..\..\..\src\klibc\kstring.c + ..\..\..\..\components\libc\compilers\common\cctype.c - kerrno.c + cstdlib.c 1 - ..\..\..\src\klibc\kerrno.c + ..\..\..\..\components\libc\compilers\common\cstdlib.c - kstdio.c + cstring.c 1 - ..\..\..\src\klibc\kstdio.c + ..\..\..\..\components\libc\compilers\common\cstring.c - - - libcpu - div0.c + ctime.c 1 - ..\..\..\libcpu\arm\common\div0.c + ..\..\..\..\components\libc\compilers\common\ctime.c - showmem.c + cunistd.c 1 - ..\..\..\libcpu\arm\common\showmem.c + ..\..\..\..\components\libc\compilers\common\cunistd.c - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + cwchar.c + 1 + ..\..\..\..\components\libc\compilers\common\cwchar.c - cpuport.c + kerrno.c 1 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c + ..\..\..\..\src\klibc\kerrno.c - - - Libraries - n32l43x_adc.c + kstdio.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c + ..\..\..\..\src\klibc\kstdio.c - n32l43x_can.c + kstring.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + ..\..\..\..\src\klibc\kstring.c - n32l43x_spi.c + rt_vsnprintf_tiny.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c - n32l43x_rtc.c + rt_vsscanf.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + ..\..\..\..\src\klibc\rt_vsscanf.c + + + Libraries - misc.c + system_n32l43x.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c + ..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c - n32l43x_usart.c + n32l43x_gpio.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c @@ -1433,37 +1402,51 @@ - n32l43x_dac.c + misc.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\misc.c - n32l43x_pwr.c + n32l43x_usart.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_usart.c - n32l43x_iwdg.c + n32l43x_i2c.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c - n32l43x_gpio.c + n32l43x_spi.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_gpio.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_spi.c - n32l43x_i2c.c + n32l43x_can.c 1 - ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_i2c.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_can.c + + + + + n32l43x_adc.c + 1 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_adc.c + + + + + n32l43x_dac.c + 1 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_dac.c @@ -1475,9 +1458,16 @@ - system_n32l43x.c + n32l43x_rtc.c 1 - ..\libraries\N32L43x_Firmware_Library\CMSIS\device\system_n32l43x.c + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_rtc.c + + + + + n32l43x_pwr.c + 1 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_pwr.c @@ -1487,6 +1477,13 @@ ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_flash.c + + + n32l43x_iwdg.c + 1 + ..\libraries\N32L43x_Firmware_Library\n32l43x_std_periph_driver\src\n32l43x_iwdg.c + + n32l43x_wwdg.c diff --git a/bsp/n32/n32l43xml-stb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/rtconfig.h similarity index 98% rename from bsp/n32/n32l43xml-stb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/rtconfig.h index a454f9f412..57bcc7aab0 100644 --- a/bsp/n32/n32l43xml-stb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ @@ -155,6 +155,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -327,6 +328,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32l43xrl-stb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l43xrl-stb/template.ewp b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.ewp similarity index 100% rename from bsp/n32/n32l43xrl-stb/template.ewp rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.ewp diff --git a/bsp/n32/n32l43xrl-stb/template.eww b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.eww similarity index 100% rename from bsp/n32/n32l43xrl-stb/template.eww rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.eww diff --git a/bsp/n32/n32l43xrl-stb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.uvoptx similarity index 100% rename from bsp/n32/n32l43xrl-stb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.uvoptx diff --git a/bsp/n32/n32l43xrl-stb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.uvprojx similarity index 100% rename from bsp/n32/n32l43xrl-stb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32l43xrl-stb/template.uvprojx diff --git a/bsp/n32/n32wb45xl-evb/.config b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/.config similarity index 97% rename from bsp/n32/n32wb45xl-evb/.config rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/.config index 03f1cee04e..0a4df74121 100644 --- a/bsp/n32/n32wb45xl-evb/.config +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/.config @@ -180,7 +180,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="usart1" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -274,6 +274,8 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set # CONFIG_RT_USING_SOFT_SPI is not set # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set @@ -368,8 +370,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -378,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -579,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_U8G2 is not set # end of u8g2: a monochrome graphic library +# CONFIG_PKG_USING_NES_SIMULATOR is not set # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -604,6 +606,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # tools packages # +# CONFIG_PKG_USING_VECTOR is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -653,6 +656,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set # end of tools packages # @@ -747,6 +753,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -902,7 +909,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set # end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers # end of HAL & SDK Drivers # @@ -948,9 +971,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT3020 is not set # CONFIG_PKG_USING_MLX90632 is not set # CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1075,6 +1100,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set # CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers diff --git a/bsp/n32/n32gxx_lxx/n32wb45xl-evb/Kconfig b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/Kconfig new file mode 100644 index 0000000000..07edfefc34 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/n32/n32wb45xl-evb/README.md b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/README.md similarity index 100% rename from bsp/n32/n32wb45xl-evb/README.md rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/README.md diff --git a/bsp/n32/n32wb45xl-evb/SConscript b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/SConscript similarity index 100% rename from bsp/n32/n32wb45xl-evb/SConscript rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/SConscript diff --git a/bsp/n32/n32wb45xl-evb/SConstruct b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/SConstruct similarity index 96% rename from bsp/n32/n32wb45xl-evb/SConstruct rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/SConstruct index ab72eba93b..c2c9b82dfc 100644 --- a/bsp/n32/n32wb45xl-evb/SConstruct +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/n32/n32wb45xl-evb/applications/SConscript b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/applications/SConscript similarity index 100% rename from bsp/n32/n32wb45xl-evb/applications/SConscript rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/applications/SConscript diff --git a/bsp/n32/n32wb45xl-evb/applications/main.c b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/applications/main.c similarity index 100% rename from bsp/n32/n32wb45xl-evb/applications/main.c rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/applications/main.c diff --git a/bsp/n32/n32wb45xl-evb/board/Kconfig b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/Kconfig similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/Kconfig rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/Kconfig diff --git a/bsp/n32/n32wb45xl-evb/board/SConscript b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/SConscript similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/SConscript rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/SConscript diff --git a/bsp/n32/n32wb45xl-evb/board/board.c b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/board.c similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/board.c rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/board.c diff --git a/bsp/n32/n32wb45xl-evb/board/board.h b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/board.h similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/board.h rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/board.h diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/linker_scripts/link.icf similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/linker_scripts/link.icf rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/linker_scripts/link.icf diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/linker_scripts/link.lds similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/linker_scripts/link.lds rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/linker_scripts/link.lds diff --git a/bsp/n32/n32wb45xl-evb/board/linker_scripts/link.sct b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/linker_scripts/link.sct similarity index 100% rename from bsp/n32/n32wb45xl-evb/board/linker_scripts/link.sct rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/board/linker_scripts/link.sct diff --git a/bsp/n32/n32wb45xl-evb/figures/board.jpg b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/figures/board.jpg similarity index 100% rename from bsp/n32/n32wb45xl-evb/figures/board.jpg rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/figures/board.jpg diff --git a/bsp/n32/n32wb45xl-evb/project.ewd b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.ewd similarity index 100% rename from bsp/n32/n32wb45xl-evb/project.ewd rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.ewd diff --git a/bsp/n32/n32wb45xl-evb/project.ewp b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.ewp similarity index 86% rename from bsp/n32/n32wb45xl-evb/project.ewp rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.ewp index cf5e798397..5ec12a1a79 100644 --- a/bsp/n32/n32wb45xl-evb/project.ewp +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.ewp @@ -358,29 +358,30 @@ - Compiler - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c - + CPU - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\atomic_arm.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\div0.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\common\showmem.c - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\context_iar.S - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + $PROJ_DIR$\..\..\..\..\libcpu\arm\cortex-m4\cpuport.c DeviceDrivers - $PROJ_DIR$\..\..\..\components\drivers\can\dev_can.c + $PROJ_DIR$\..\..\..\..\components\drivers\can\dev_can.c - $PROJ_DIR$\..\..\..\components\drivers\core\device.c + $PROJ_DIR$\..\..\..\..\components\drivers\core\device.c $PROJ_DIR$\..\..\..\components\drivers\clock_time\clock_timer.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_core.c - $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + $PROJ_DIR$\..\..\..\..\components\drivers\i2c\dev_i2c_dev.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_comm.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\completion_up.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\condvar.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\dataqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\pipe.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringblk_buf.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\ringbuffer.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\waitqueue.c - $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + $PROJ_DIR$\..\..\..\..\components\drivers\ipc\workqueue.c - $PROJ_DIR$\..\..\..\components\drivers\misc\adc.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\adc.c - $PROJ_DIR$\..\..\..\components\drivers\misc\dac.c + $PROJ_DIR$\..\..\..\..\components\drivers\misc\dac.c - $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + $PROJ_DIR$\..\..\..\..\components\drivers\pin\dev_pin.c - $PROJ_DIR$\..\..\..\components\drivers\rtc\dev_rtc.c + $PROJ_DIR$\..\..\..\..\components\drivers\rtc\dev_rtc.c - $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + $PROJ_DIR$\..\..\..\..\components\drivers\serial\dev_serial.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi.c - $PROJ_DIR$\..\..\..\components\drivers\spi\dev_spi_core.c + $PROJ_DIR$\..\..\..\..\components\drivers\spi\dev_spi_core.c - $PROJ_DIR$\..\..\..\components\drivers\watchdog\dev_watchdog.c + $PROJ_DIR$\..\..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -2339,151 +2311,178 @@ Finsh - $PROJ_DIR$\..\..\..\components\finsh\shell.c + $PROJ_DIR$\..\..\..\..\components\finsh\shell.c - $PROJ_DIR$\..\..\..\components\finsh\msh.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh.c - $PROJ_DIR$\..\..\..\components\finsh\cmd.c + $PROJ_DIR$\..\..\..\..\components\finsh\msh_parse.c - $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + $PROJ_DIR$\..\..\..\..\components\finsh\cmd.c Kernel - $PROJ_DIR$\..\..\..\src\clock.c + $PROJ_DIR$\..\..\..\..\src\clock.c - $PROJ_DIR$\..\..\..\src\components.c + $PROJ_DIR$\..\..\..\..\src\components.c - $PROJ_DIR$\..\..\..\src\cpu_up.c + $PROJ_DIR$\..\..\..\..\src\cpu_up.c - $PROJ_DIR$\..\..\..\src\defunct.c + $PROJ_DIR$\..\..\..\..\src\defunct.c - $PROJ_DIR$\..\..\..\src\idle.c + $PROJ_DIR$\..\..\..\..\src\idle.c - $PROJ_DIR$\..\..\..\src\ipc.c + $PROJ_DIR$\..\..\..\..\src\ipc.c - $PROJ_DIR$\..\..\..\src\irq.c + $PROJ_DIR$\..\..\..\..\src\irq.c - $PROJ_DIR$\..\..\..\src\kservice.c + $PROJ_DIR$\..\..\..\..\src\kservice.c - $PROJ_DIR$\..\..\..\src\mem.c + $PROJ_DIR$\..\..\..\..\src\mem.c - $PROJ_DIR$\..\..\..\src\memheap.c + $PROJ_DIR$\..\..\..\..\src\memheap.c - $PROJ_DIR$\..\..\..\src\mempool.c + $PROJ_DIR$\..\..\..\..\src\mempool.c - $PROJ_DIR$\..\..\..\src\object.c + $PROJ_DIR$\..\..\..\..\src\object.c - $PROJ_DIR$\..\..\..\src\scheduler_comm.c + $PROJ_DIR$\..\..\..\..\src\scheduler_comm.c - $PROJ_DIR$\..\..\..\src\scheduler_up.c + $PROJ_DIR$\..\..\..\..\src\scheduler_up.c - $PROJ_DIR$\..\..\..\src\thread.c + $PROJ_DIR$\..\..\..\..\src\thread.c - $PROJ_DIR$\..\..\..\src\timer.c + $PROJ_DIR$\..\..\..\..\src\timer.c - klibc + Libc - $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cctype.c - $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstdlib.c - $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cstring.c - $PROJ_DIR$\..\..\..\src\klibc\kstring.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\ctime.c - $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\environ.c - - - libcpu - $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_close.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_mem.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_open.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\..\src\klibc\rt_vsscanf.c Libraries - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_rcc.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\CMSIS\device\system_n32wb452.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_i2c.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_gpio.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_bkp.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_rcc.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_tim.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_exti.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_adc.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\misc.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_exti.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_usart.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_can.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_i2c.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_dac.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_spi.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_usart.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_can.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_gpio.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_adc.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_spi.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_dac.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_rtc.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_tim.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\CMSIS\device\system_n32wb452.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_rtc.c $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_pwr.c - $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\misc.c + $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_bkp.c $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_wwdg.c @@ -2492,9 +2491,6 @@ $PROJ_DIR$\..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_iwdg.c - - POSIX - utc_UTest diff --git a/bsp/n32/n32wb45xl-evb/project.eww b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.eww similarity index 100% rename from bsp/n32/n32wb45xl-evb/project.eww rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.eww diff --git a/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.uvoptx b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.uvoptx new file mode 100644 index 0000000000..b36a24c17f --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.uvoptx @@ -0,0 +1,1324 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_can.c + n32wb452_can.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_adc.c + n32wb452_adc.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_dac.c + n32wb452_dac.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_tim.c + n32wb452_tim.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_rtc.c + n32wb452_rtc.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_pwr.c + n32wb452_pwr.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_bkp.c + n32wb452_bkp.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_wwdg.c + n32wb452_wwdg.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\libraries\N32WB452_Firmware_Library\n32wb452_std_periph_driver\src\n32wb452_iwdg.c + n32wb452_iwdg.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/n32/n32wb45xl-evb/project.uvprojx b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.uvprojx similarity index 100% rename from bsp/n32/n32wb45xl-evb/project.uvprojx rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/project.uvprojx diff --git a/bsp/n32/n32wb45xl-evb/rtconfig.h b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/rtconfig.h similarity index 98% rename from bsp/n32/n32wb45xl-evb/rtconfig.h rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/rtconfig.h index 7d15dff71c..451940bab2 100644 --- a/bsp/n32/n32wb45xl-evb/rtconfig.h +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/rtconfig.h @@ -104,7 +104,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "usart1" -#define RT_VER_NUM 0x50201 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -160,6 +160,7 @@ #define RT_USING_DAC #define RT_USING_RTC #define RT_USING_SPI +#define RT_USING_SPI_ISR #define RT_USING_WDT #define RT_USING_PIN #define RT_USING_HWTIMER @@ -332,6 +333,14 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/n32/n32gxx_lxx/n32wb45xl-evb/rtconfig.py b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/rtconfig.py new file mode 100644 index 0000000000..c3765e6f08 --- /dev/null +++ b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/rtconfig.py @@ -0,0 +1,184 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32wb45xl-evb/template.ewp b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.ewp similarity index 100% rename from bsp/n32/n32wb45xl-evb/template.ewp rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.ewp diff --git a/bsp/n32/n32wb45xl-evb/template.eww b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.eww similarity index 100% rename from bsp/n32/n32wb45xl-evb/template.eww rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.eww diff --git a/bsp/n32/n32wb45xl-evb/template.uvoptx b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.uvoptx similarity index 100% rename from bsp/n32/n32wb45xl-evb/template.uvoptx rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.uvoptx diff --git a/bsp/n32/n32wb45xl-evb/template.uvprojx b/bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.uvprojx similarity index 100% rename from bsp/n32/n32wb45xl-evb/template.uvprojx rename to bsp/n32/n32gxx_lxx/n32wb45xl-evb/template.uvprojx diff --git a/bsp/n32/tools/sdk_dist.py b/bsp/n32/n32gxx_lxx/tools/sdk_dist.py similarity index 100% rename from bsp/n32/tools/sdk_dist.py rename to bsp/n32/n32gxx_lxx/tools/sdk_dist.py diff --git a/bsp/n32/n32hxxx/.clang-format-ignore b/bsp/n32/n32hxxx/.clang-format-ignore new file mode 100644 index 0000000000..a47789d228 --- /dev/null +++ b/bsp/n32/n32hxxx/.clang-format-ignore @@ -0,0 +1,12 @@ + +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +# 从 .ignore_format.yml 迁移的规则 +/n32h760zil7-stb/board/Cube_Config/ +/n32h760zil7-stb/board/Cube_Config/data/ +/n32h760zil7-stb/board/Cube_Config/Driver/ +/n32h760zil7-stb/board/Cube_Config/MDK-ARM/ +/n32h760zil7-stb/board/Cube_Config/startup/ +/n32h760zil7-stb/board/Cube_Config/USER/ \ No newline at end of file diff --git a/bsp/n32/n32hxxx/libraries/Kconfig b/bsp/n32/n32hxxx/libraries/Kconfig new file mode 100644 index 0000000000..4f00588009 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/Kconfig @@ -0,0 +1,9 @@ +config SOC_FAMILY_N32 + bool + +config SOC_SERIES_N32H7xx + bool + select ARCH_ARM_CORTEX_M7 + select SOC_FAMILY_N32 + + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/SConscript b/bsp/n32/n32hxxx/libraries/N32_Drivers/SConscript new file mode 100644 index 0000000000..430a293f9a --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/SConscript @@ -0,0 +1,18 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import os + +cwd = GetCurrentDir() +group = [] +src = ['drv_common.c'] +path = [cwd] + +if GetDepend(['RT_USING_NANO']): + group = group + SConscript(os.path.join(cwd, 'nano', 'SConscript')) +else: + group = group + SConscript(os.path.join(cwd, 'drivers', 'SConscript')) + +group = group + DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/Kconfig b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/Kconfig new file mode 100644 index 0000000000..ba93a5898c --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/Kconfig @@ -0,0 +1,16 @@ +if BSP_USING_USBD + config BSP_USBD_TYPE_FS + bool + # "USB Full Speed (FS) Core" + config BSP_USBD_TYPE_HS + bool + # "USB High Speed (HS) Core" + + config BSP_USBD_SPEED_HS + bool + # "USB High Speed (HS) Mode" + config BSP_USBD_SPEED_HSINFS + bool + # "USB High Speed (HS) Core in FS mode" +endif + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/SConscript b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/SConscript new file mode 100644 index 0000000000..3dda86ed0c --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/SConscript @@ -0,0 +1,39 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import os + +cwd = GetCurrentDir() +group = [] +src = [] +path = [cwd] + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'): + src += ['drv_soft_i2c.c'] + +if GetDepend(['RT_USING_I2C']): + if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4') or GetDepend('BSP_USING_HARD_I2C5') or GetDepend('BSP_USING_HARD_I2C6') or GetDepend('BSP_USING_HARD_I2C7') or GetDepend('BSP_USING_HARD_I2C8') or GetDepend('BSP_USING_HARD_I2C9') or GetDepend('BSP_USING_HARD_I2C10'): + src += ['drv_hard_i2c.c'] + +if GetDepend('BSP_USING_ONCHIP_RTC'): + src += ['drv_rtc.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['drv_adc.c'] + + +path += [os.path.join(cwd, 'config')] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/adc_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/adc_config.h new file mode 100644 index 0000000000..dca16bf4fe --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/adc_config.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CONFIG +#define ADC1_CONFIG \ + { \ + .ADCx = ADC1, \ + .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \ + .EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \ + .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ + .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ + .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ + .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ + .Init.MultiChEn = DISABLE, \ + .Init.ContinueConvEn = DISABLE, \ + .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ + .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ + .Init.DatAlign = ADC_DAT_ALIGN_R, \ + .Init.ChsNumber = 1U, \ + .Init.Resolution = ADC_DATA_RES_12BIT, \ + .Rank = 1U, \ + .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ + } +#endif /* ADC1_CONFIG */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_CONFIG +#define ADC2_CONFIG \ + { \ + .ADCx = ADC2, \ + .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \ + .EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \ + .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ + .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ + .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ + .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ + .Init.MultiChEn = DISABLE, \ + .Init.ContinueConvEn = DISABLE, \ + .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ + .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ + .Init.DatAlign = ADC_DAT_ALIGN_R, \ + .Init.ChsNumber = 1U, \ + .Init.Resolution = ADC_DATA_RES_12BIT, \ + .Rank = 1U, \ + .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ + } +#endif /* ADC2_CONFIG */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_CONFIG +#define ADC3_CONFIG \ + { \ + .ADCx = ADC3, \ + .AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \ + .EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \ + .ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \ + .Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \ + .RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \ + .Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \ + .Init.MultiChEn = DISABLE, \ + .Init.ContinueConvEn = DISABLE, \ + .Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \ + .Init.DataTransferMode = ADC_REG_DR_TRANSFER, \ + .Init.DatAlign = ADC_DAT_ALIGN_R, \ + .Init.ChsNumber = 1U, \ + .Init.Resolution = ADC_DATA_RES_12BIT, \ + .Rank = 1U, \ + .ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \ + } +#endif /* ADC3_CONFIG */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/dma_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/dma_config.h new file mode 100644 index 0000000000..c9003200d6 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/dma_config.h @@ -0,0 +1,710 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMAMUX1 channel0 / DMA1 channel0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE DMA1 +#define UART1_RX_DMA_IRQHandler DMA1_Channel0_IRQHandler +#define UART1_RX_DMA_IRQ DMA1_Channel0_IRQn +#define UART1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define UART1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define UART1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0 +#define UART1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART1_RX +#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE) +#define UART8_TX_DMA_INSTANCE DMA1 +#define UART8_TX_DMA_IRQHandler DMA1_Channel0_IRQHandler +#define UART8_TX_DMA_IRQ DMA1_Channel0_IRQn +#define UART8_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define UART8_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART8_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define UART8_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0 +#define UART8_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART8_TX +#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) +#define I2C5_TX_DMA_INSTANCE DMA1 +#define I2C5_TX_DMA_IRQHandler DMA1_Channel0_IRQHandler +#define I2C5_TX_DMA_IRQ DMA1_Channel0_IRQn +#define I2C5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define I2C5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define I2C5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define I2C5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_0 +#define I2C5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C5_TX +#endif + +/* DMAMUX1 channel1 / DMA1 channel1 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE DMA1 +#define UART2_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define UART2_RX_DMA_IRQ DMA1_Channel1_IRQn +#define UART2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define UART2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define UART2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1 +#define UART2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART2_RX +#elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA_INSTANCE) +#define UART9_TX_DMA_INSTANCE DMA1 +#define UART9_TX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define UART9_TX_DMA_IRQ DMA1_Channel1_IRQn +#define UART9_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define UART9_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART9_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define UART9_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1 +#define UART9_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART9_TX +#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) +#define I2C6_TX_DMA_INSTANCE DMA1 +#define I2C6_TX_DMA_IRQHandler DMA1_Channel1_IRQHandler +#define I2C6_TX_DMA_IRQ DMA1_Channel1_IRQn +#define I2C6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define I2C6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define I2C6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define I2C6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_1 +#define I2C6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C6_TX +#endif + +/* DMAMUX1 channel2 / DMA1 channel2 */ +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) +#define UART3_RX_DMA_INSTANCE DMA1 +#define UART3_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define UART3_RX_DMA_IRQ DMA1_Channel2_IRQn +#define UART3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define UART3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define UART3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2 +#define UART3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART3_RX +#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE) +#define UART10_TX_DMA_INSTANCE DMA1 +#define UART10_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define UART10_TX_DMA_IRQ DMA1_Channel2_IRQn +#define UART10_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define UART10_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART10_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define UART10_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2 +#define UART10_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART10_TX +#elif defined(BSP_I2C7_TX_USING_DMA) && !defined(I2C7_TX_DMA_INSTANCE) +#define I2C7_TX_DMA_INSTANCE DMA1 +#define I2C7_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler +#define I2C7_TX_DMA_IRQ DMA1_Channel2_IRQn +#define I2C7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define I2C7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define I2C7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define I2C7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_2 +#define I2C7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C7_TX +#endif + +/* DMAMUX1 channel3 / DMA1 channel3 */ +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_RX_DMA_INSTANCE DMA1 +#define UART4_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define UART4_RX_DMA_IRQ DMA1_Channel3_IRQn +#define UART4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define UART4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define UART4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3 +#define UART4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART4_RX +#elif defined(BSP_UART11_TX_USING_DMA) && !defined(UART11_TX_DMA_INSTANCE) +#define UART11_TX_DMA_INSTANCE DMA1 +#define UART11_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define UART11_TX_DMA_IRQ DMA1_Channel3_IRQn +#define UART11_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define UART11_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART11_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define UART11_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3 +#define UART11_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART11_TX +#elif defined(BSP_I2C8_TX_USING_DMA) && !defined(I2C8_TX_DMA_INSTANCE) +#define I2C8_TX_DMA_INSTANCE DMA1 +#define I2C8_TX_DMA_IRQHandler DMA1_Channel3_IRQHandler +#define I2C8_TX_DMA_IRQ DMA1_Channel3_IRQn +#define I2C8_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define I2C8_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define I2C8_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define I2C8_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_3 +#define I2C8_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C8_TX +#endif + +/* DMAMUX1 channel4 / DMA1 channel4 */ +#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) +#define UART5_RX_DMA_INSTANCE DMA1 +#define UART5_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define UART5_RX_DMA_IRQ DMA1_Channel4_IRQn +#define UART5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define UART5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define UART5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4 +#define UART5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART5_RX +#elif defined(BSP_UART12_TX_USING_DMA) && !defined(UART12_TX_DMA_INSTANCE) +#define UART12_TX_DMA_INSTANCE DMA1 +#define UART12_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define UART12_TX_DMA_IRQ DMA1_Channel4_IRQn +#define UART12_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define UART12_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART12_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define UART12_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4 +#define UART12_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART12_TX +#elif defined(BSP_I2C9_TX_USING_DMA) && !defined(I2C9_TX_DMA_INSTANCE) +#define I2C9_TX_DMA_INSTANCE DMA1 +#define I2C9_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler +#define I2C9_TX_DMA_IRQ DMA1_Channel4_IRQn +#define I2C9_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define I2C9_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define I2C9_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define I2C9_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_4 +#define I2C9_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C9_TX +#endif + +/* DMAMUX1 channel5 / DMA1 channel5 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE DMA1 +#define UART6_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define UART6_RX_DMA_IRQ DMA1_Channel5_IRQn +#define UART6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define UART6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define UART6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5 +#define UART6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART6_RX +#elif defined(BSP_UART13_TX_USING_DMA) && !defined(UART13_TX_DMA_INSTANCE) +#define UART13_TX_DMA_INSTANCE DMA1 +#define UART13_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define UART13_TX_DMA_IRQ DMA1_Channel5_IRQn +#define UART13_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define UART13_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART13_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define UART13_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5 +#define UART13_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART13_TX +#elif defined(BSP_I2C10_TX_USING_DMA) && !defined(I2C10_TX_DMA_INSTANCE) +#define I2C10_TX_DMA_INSTANCE DMA1 +#define I2C10_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler +#define I2C10_TX_DMA_IRQ DMA1_Channel5_IRQn +#define I2C10_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define I2C10_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define I2C10_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define I2C10_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_5 +#define I2C10_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C10_TX +#endif + +/* DMAMUX1 channel6 / DMA1 channel6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE DMA1 +#define UART7_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define UART7_RX_DMA_IRQ DMA1_Channel6_IRQn +#define UART7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define UART7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define UART7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6 +#define UART7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART7_RX +#elif defined(BSP_UART14_TX_USING_DMA) && !defined(UART14_TX_DMA_INSTANCE) +#define UART14_TX_DMA_INSTANCE DMA1 +#define UART14_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define UART14_TX_DMA_IRQ DMA1_Channel6_IRQn +#define UART14_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define UART14_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART14_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define UART14_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6 +#define UART14_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART14_TX +#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE DMA1 +#define SPI1_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler +#define SPI1_TX_DMA_IRQ DMA1_Channel6_IRQn +#define SPI1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define SPI1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define SPI1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define SPI1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_6 +#define SPI1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI1_TX +#endif + +/* DMAMUX1 channel7 / DMA1 channel7 */ +#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE) +#define UART8_RX_DMA_INSTANCE DMA1 +#define UART8_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define UART8_RX_DMA_IRQ DMA1_Channel7_IRQn +#define UART8_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define UART8_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART8_RX_DMA_DMA_CHANNEL DMA_CHANNEL_7 +#define UART8_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7 +#define UART8_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART8_RX +#elif defined(BSP_UART15_TX_USING_DMA) && !defined(UART15_TX_DMA_INSTANCE) +#define UART15_TX_DMA_INSTANCE DMA1 +#define UART15_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define UART15_TX_DMA_IRQ DMA1_Channel7_IRQn +#define UART15_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define UART15_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define UART15_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7 +#define UART15_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7 +#define UART15_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART15_TX +#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE DMA1 +#define SPI2_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler +#define SPI2_TX_DMA_IRQ DMA1_Channel7_IRQn +#define SPI2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define SPI2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA1 +#define SPI2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7 +#define SPI2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_7 +#define SPI2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI2_TX +#endif + +/* DMAMUX1 channel8 / DMA2 channel0 */ +#if defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA_INSTANCE) +#define UART9_RX_DMA_INSTANCE DMA2 +#define UART9_RX_DMA_IRQHandler DMA2_Channel0_IRQHandler +#define UART9_RX_DMA_IRQ DMA2_Channel0_IRQn +#define UART9_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define UART9_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART9_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define UART9_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8 +#define UART9_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART9_RX +#elif defined(BSP_LPUART1_TX_USING_DMA) && !defined(LPUART1_TX_DMA_INSTANCE) +#define LPUART1_TX_DMA_INSTANCE DMA2 +#define LPUART1_TX_DMA_IRQHandler DMA2_Channel0_IRQHandler +#define LPUART1_TX_DMA_IRQ DMA2_Channel0_IRQn +#define LPUART1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define LPUART1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define LPUART1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define LPUART1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8 +#define LPUART1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART1_TX +#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE DMA2 +#define SPI3_TX_DMA_IRQHandler DMA2_Channel0_IRQHandler +#define SPI3_TX_DMA_IRQ DMA2_Channel0_IRQn +#define SPI3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define SPI3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_8 +#define SPI3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_TX +#endif + +/* DMAMUX1 channel9 / DMA2 channel1 */ +#if defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE) +#define UART10_RX_DMA_INSTANCE DMA2 +#define UART10_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler +#define UART10_RX_DMA_IRQ DMA2_Channel1_IRQn +#define UART10_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define UART10_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART10_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define UART10_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9 +#define UART10_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART10_RX +#elif defined(BSP_LPUART2_TX_USING_DMA) && !defined(LPUART2_TX_DMA_INSTANCE) +#define LPUART2_TX_DMA_INSTANCE DMA2 +#define LPUART2_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler +#define LPUART2_TX_DMA_IRQ DMA2_Channel1_IRQn +#define LPUART2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define LPUART2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define LPUART2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define LPUART2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9 +#define LPUART2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART2_TX +#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE DMA2 +#define SPI4_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler +#define SPI4_TX_DMA_IRQ DMA2_Channel1_IRQn +#define SPI4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define SPI4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define SPI4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_9 +#define SPI4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI4_TX +#endif + +/* DMAMUX1 channel10 / DMA2 channel2 */ +#if defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE DMA2 +#define I2C1_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler +#define I2C1_RX_DMA_IRQ DMA2_Channel2_IRQn +#define I2C1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define I2C1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define I2C1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define I2C1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10 +#define I2C1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C1_RX +#elif defined(BSP_UART11_RX_USING_DMA) && !defined(UART11_RX_DMA_INSTANCE) +#define UART11_RX_DMA_INSTANCE DMA2 +#define UART11_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler +#define UART11_RX_DMA_IRQ DMA2_Channel2_IRQn +#define UART11_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define UART11_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART11_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define UART11_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10 +#define UART11_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART11_RX +#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_TX_DMA_INSTANCE DMA2 +#define SPI5_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler +#define SPI5_TX_DMA_IRQ DMA2_Channel2_IRQn +#define SPI5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define SPI5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_10 +#define SPI5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI5_TX +#endif + +/* DMAMUX1 channel11 / DMA2 channel3 */ +#if defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE DMA2 +#define I2C2_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler +#define I2C2_RX_DMA_IRQ DMA2_Channel3_IRQn +#define I2C2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define I2C2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define I2C2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define I2C2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11 +#define I2C2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C2_RX +#elif defined(BSP_UART12_RX_USING_DMA) && !defined(UART12_RX_DMA_INSTANCE) +#define UART12_RX_DMA_INSTANCE DMA2 +#define UART12_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler +#define UART12_RX_DMA_IRQ DMA2_Channel3_IRQn +#define UART12_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define UART12_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART12_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define UART12_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11 +#define UART12_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART12_RX +#elif defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_TX_DMA_INSTANCE DMA2 +#define SPI6_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler +#define SPI6_TX_DMA_IRQ DMA2_Channel3_IRQn +#define SPI6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define SPI6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_11 +#define SPI6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI6_TX +#endif + +/* DMAMUX1 channel12 / DMA2 channel4 */ +#if defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_RX_DMA_INSTANCE DMA2 +#define I2C3_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler +#define I2C3_RX_DMA_IRQ DMA2_Channel4_IRQn +#define I2C3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define I2C3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define I2C3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define I2C3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12 +#define I2C3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C3_RX +#elif defined(BSP_UART13_RX_USING_DMA) && !defined(UART13_RX_DMA_INSTANCE) +#define UART13_RX_DMA_INSTANCE DMA2 +#define UART13_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler +#define UART13_RX_DMA_IRQ DMA2_Channel4_IRQn +#define UART13_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define UART13_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART13_RX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define UART13_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12 +#define UART13_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART13_RX +#elif defined(BSP_SPI7_TX_USING_DMA) && !defined(SPI7_TX_DMA_INSTANCE) +#define SPI7_TX_DMA_INSTANCE DMA2 +#define SPI7_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler +#define SPI7_TX_DMA_IRQ DMA2_Channel4_IRQn +#define SPI7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define SPI7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_12 +#define SPI7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI7_TX +#endif + +/* DMAMUX1 channel13 / DMA2 channel5 */ +#if defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) +#define I2C4_RX_DMA_INSTANCE DMA2 +#define I2C4_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler +#define I2C4_RX_DMA_IRQ DMA2_Channel5_IRQn +#define I2C4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define I2C4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define I2C4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define I2C4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13 +#define I2C4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C4_RX +#elif defined(BSP_UART14_RX_USING_DMA) && !defined(UART14_RX_DMA_INSTANCE) +#define UART14_RX_DMA_INSTANCE DMA2 +#define UART14_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler +#define UART14_RX_DMA_IRQ DMA2_Channel5_IRQn +#define UART14_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define UART14_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART14_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define UART14_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13 +#define UART14_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART14_RX +#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE DMA2 +#define SPI1_RX_DMA_IRQHandler DMA2_Channel5_IRQHandler +#define SPI1_RX_DMA_IRQ DMA2_Channel5_IRQn +#define SPI1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define SPI1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_13 +#define SPI1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI1_RX +#endif + +/* DMAMUX1 channel14 / DMA2 channel6 */ +#if defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) +#define I2C5_RX_DMA_INSTANCE DMA2 +#define I2C5_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler +#define I2C5_RX_DMA_IRQ DMA2_Channel6_IRQn +#define I2C5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define I2C5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define I2C5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define I2C5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14 +#define I2C5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C5_RX +#elif defined(BSP_UART15_RX_USING_DMA) && !defined(UART15_RX_DMA_INSTANCE) +#define UART15_RX_DMA_INSTANCE DMA2 +#define UART15_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler +#define UART15_RX_DMA_IRQ DMA2_Channel6_IRQn +#define UART15_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define UART15_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define UART15_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define UART15_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14 +#define UART15_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_UART15_RX +#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE DMA2 +#define SPI2_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler +#define SPI2_RX_DMA_IRQ DMA2_Channel6_IRQn +#define SPI2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define SPI2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define SPI2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_14 +#define SPI2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI2_RX +#endif + +/* DMAMUX1 channel15 / DMA2 channel7 */ +#if defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) +#define I2C6_RX_DMA_INSTANCE DMA2 +#define I2C6_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler +#define I2C6_RX_DMA_IRQ DMA2_Channel7_IRQn +#define I2C6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define I2C6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define I2C6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define I2C6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15 +#define I2C6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C6_RX +#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE) +#define LPUART1_RX_DMA_INSTANCE DMA2 +#define LPUART1_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler +#define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn +#define LPUART1_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define LPUART1_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define LPUART1_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define LPUART1_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15 +#define LPUART1_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART1_RX +#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE DMA2 +#define SPI3_RX_DMA_IRQHandler DMA2_Channel7_IRQHandler +#define SPI3_RX_DMA_IRQ DMA2_Channel7_IRQn +#define SPI3_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define SPI3_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA2 +#define SPI3_RX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI3_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_15 +#define SPI3_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI3_RX +#endif + +/* DMAMUX1 channel16 / DMA3 channel0 */ +#if defined(BSP_I2C7_RX_USING_DMA) && !defined(I2C7_RX_DMA_INSTANCE) +#define I2C7_RX_DMA_INSTANCE DMA3 +#define I2C7_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler +#define I2C7_RX_DMA_IRQ DMA3_Channel0_IRQn +#define I2C7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define I2C7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define I2C7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16 +#define I2C7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C7_RX +#elif defined(BSP_LPUART2_RX_USING_DMA) && !defined(LPUART2_RX_DMA_INSTANCE) +#define LPUART2_RX_DMA_INSTANCE DMA3 +#define LPUART2_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler +#define LPUART2_RX_DMA_IRQ DMA3_Channel0_IRQn +#define LPUART2_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define LPUART2_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define LPUART2_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define LPUART2_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16 +#define LPUART2_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_LPUART2_RX +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE DMA3 +#define SPI4_RX_DMA_IRQHandler DMA3_Channel0_IRQHandler +#define SPI4_RX_DMA_IRQ DMA3_Channel0_IRQn +#define SPI4_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_0 +#define SPI4_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define SPI4_RX_DMA_DMA_CHANNEL DMA_CHANNEL_0 +#define SPI4_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_16 +#define SPI4_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI4_RX +#endif + +/* DMAMUX1 channel17 / DMA3 channel1 */ +#if defined(BSP_I2C8_RX_USING_DMA) && !defined(I2C8_RX_DMA_INSTANCE) +#define I2C8_RX_DMA_INSTANCE DMA3 +#define I2C8_RX_DMA_IRQHandler DMA3_Channel1_IRQHandler +#define I2C8_RX_DMA_IRQ DMA3_Channel1_IRQn +#define I2C8_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define I2C8_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C8_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define I2C8_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17 +#define I2C8_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C8_RX +#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE DMA3 +#define UART1_TX_DMA_IRQHandler DMA3_Channel1_IRQHandler +#define UART1_TX_DMA_IRQ DMA3_Channel1_IRQn +#define UART1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define UART1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define UART1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17 +#define UART1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART1_TX +#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE) +#define SPI5_RX_DMA_INSTANCE DMA3 +#define SPI5_RX_DMA_IRQHandler DMA3_Channel1_IRQHandler +#define SPI5_RX_DMA_IRQ DMA3_Channel1_IRQn +#define SPI5_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_1 +#define SPI5_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define SPI5_RX_DMA_DMA_CHANNEL DMA_CHANNEL_1 +#define SPI5_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_17 +#define SPI5_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI5_RX +#endif + +/* DMAMUX1 channel18 / DMA3 channel2 */ +#if defined(BSP_I2C9_RX_USING_DMA) && !defined(I2C9_RX_DMA_INSTANCE) +#define I2C9_RX_DMA_INSTANCE DMA3 +#define I2C9_RX_DMA_IRQHandler DMA3_Channel2_IRQHandler +#define I2C9_RX_DMA_IRQ DMA3_Channel2_IRQn +#define I2C9_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define I2C9_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C9_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define I2C9_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18 +#define I2C9_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C9_RX +#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE DMA3 +#define UART2_TX_DMA_IRQHandler DMA3_Channel2_IRQHandler +#define UART2_TX_DMA_IRQ DMA3_Channel2_IRQn +#define UART2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define UART2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define UART2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18 +#define UART2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART2_TX +#elif defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE) +#define SPI6_RX_DMA_INSTANCE DMA3 +#define SPI6_RX_DMA_IRQHandler DMA3_Channel2_IRQHandler +#define SPI6_RX_DMA_IRQ DMA3_Channel2_IRQn +#define SPI6_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_2 +#define SPI6_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define SPI6_RX_DMA_DMA_CHANNEL DMA_CHANNEL_2 +#define SPI6_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_18 +#define SPI6_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI6_RX +#endif + +/* DMAMUX1 channel19 / DMA3 channel3 */ +#if defined(BSP_I2C10_RX_USING_DMA) && !defined(I2C10_RX_DMA_INSTANCE) +#define I2C10_RX_DMA_INSTANCE DMA3 +#define I2C10_RX_DMA_IRQHandler DMA3_Channel3_IRQHandler +#define I2C10_RX_DMA_IRQ DMA3_Channel3_IRQn +#define I2C10_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define I2C10_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C10_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define I2C10_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19 +#define I2C10_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C10_RX +#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) +#define UART3_TX_DMA_INSTANCE DMA3 +#define UART3_TX_DMA_IRQHandler DMA3_Channel3_IRQHandler +#define UART3_TX_DMA_IRQ DMA3_Channel3_IRQn +#define UART3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define UART3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define UART3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19 +#define UART3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART3_TX +#elif defined(BSP_SPI7_RX_USING_DMA) && !defined(SPI7_RX_DMA_INSTANCE) +#define SPI7_RX_DMA_INSTANCE DMA3 +#define SPI7_RX_DMA_IRQHandler DMA3_Channel3_IRQHandler +#define SPI7_RX_DMA_IRQ DMA3_Channel3_IRQn +#define SPI7_RX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_3 +#define SPI7_RX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define SPI7_RX_DMA_DMA_CHANNEL DMA_CHANNEL_3 +#define SPI7_RX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_19 +#define SPI7_RX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_SPI7_RX +#endif + +/* DMAMUX1 channel20 / DMA3 channel4 */ +#if defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE DMA3 +#define I2C1_TX_DMA_IRQHandler DMA3_Channel4_IRQHandler +#define I2C1_TX_DMA_IRQ DMA3_Channel4_IRQn +#define I2C1_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define I2C1_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C1_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define I2C1_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_20 +#define I2C1_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C1_TX +#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) +#define UART4_TX_DMA_INSTANCE DMA3 +#define UART4_TX_DMA_IRQHandler DMA3_Channel4_IRQHandler +#define UART4_TX_DMA_IRQ DMA3_Channel4_IRQn +#define UART4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_4 +#define UART4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_4 +#define UART4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_20 +#define UART4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART4_TX +#endif + +/* DMAMUX1 channel21 / DMA3 channel5 */ +#if defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE DMA3 +#define I2C2_TX_DMA_IRQHandler DMA3_Channel5_IRQHandler +#define I2C2_TX_DMA_IRQ DMA3_Channel5_IRQn +#define I2C2_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define I2C2_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C2_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define I2C2_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_21 +#define I2C2_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C2_TX +#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) +#define UART5_TX_DMA_INSTANCE DMA3 +#define UART5_TX_DMA_IRQHandler DMA3_Channel5_IRQHandler +#define UART5_TX_DMA_IRQ DMA3_Channel5_IRQn +#define UART5_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_5 +#define UART5_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART5_TX_DMA_DMA_CHANNEL DMA_CHANNEL_5 +#define UART5_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_21 +#define UART5_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART5_TX +#endif + +/* DMAMUX1 channel22 / DMA3 channel6 */ +#if defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_TX_DMA_INSTANCE DMA3 +#define I2C3_TX_DMA_IRQHandler DMA3_Channel6_IRQHandler +#define I2C3_TX_DMA_IRQ DMA3_Channel6_IRQn +#define I2C3_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define I2C3_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C3_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define I2C3_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_22 +#define I2C3_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C3_TX +#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE DMA3 +#define UART6_TX_DMA_IRQHandler DMA3_Channel6_IRQHandler +#define UART6_TX_DMA_IRQ DMA3_Channel6_IRQn +#define UART6_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_6 +#define UART6_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART6_TX_DMA_DMA_CHANNEL DMA_CHANNEL_6 +#define UART6_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_22 +#define UART6_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART6_TX +#endif + +/* DMAMUX1 channel23 / DMA3 channel7 */ +#if defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) +#define I2C4_TX_DMA_INSTANCE DMA3 +#define I2C4_TX_DMA_IRQHandler DMA3_Channel7_IRQHandler +#define I2C4_TX_DMA_IRQ DMA3_Channel7_IRQn +#define I2C4_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define I2C4_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define I2C4_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7 +#define I2C4_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_23 +#define I2C4_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_I2C4_TX +#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE DMA3 +#define UART7_TX_DMA_IRQHandler DMA3_Channel7_IRQHandler +#define UART7_TX_DMA_IRQ DMA3_Channel7_IRQn +#define UART7_TX_DMA_HANDSHAK DMA_CH_HARDWARE_HANDSHAKING_IF_7 +#define UART7_TX_DMA_DMA_RCC RCC_AHB1_PERIPHEN_M7_DMA3 +#define UART7_TX_DMA_DMA_CHANNEL DMA_CHANNEL_7 +#define UART7_TX_DMA_DMAMUX_CHANNEL DMAMUX_CHANNEL_23 +#define UART7_TX_DMA_DMAMUX_REQUEST DMAMUX1_REQUEST_USART7_TX +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_CONFIG_H__ */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/i2c_hard_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/i2c_hard_config.h new file mode 100644 index 0000000000..085c8f87b8 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/i2c_hard_config.h @@ -0,0 +1,512 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .name = "hwi2c1", \ + .Instance = I2C1, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB1_PERIPHEN_M7_I2C1, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk4, \ + .I2CKerClkSource = RCC_ConfigI2C1KerClkSource, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .HsInterface = I2C1_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C1_RX_DMA_DMA_RCC, \ + .dma_channel = I2C1_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C1_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C1_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .HsInterface = I2C1_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C1_TX_DMA_DMA_RCC, \ + .dma_channel = I2C1_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C1_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C1_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .name = "hwi2c2", \ + .Instance = I2C2, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB1_PERIPHEN_M7_I2C2, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk4, \ + .I2CKerClkSource = RCC_ConfigI2C2KerClkSource, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .HsInterface = I2C2_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C2_RX_DMA_DMA_RCC, \ + .dma_channel = I2C2_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C2_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C2_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .HsInterface = I2C2_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C2_TX_DMA_DMA_RCC, \ + .dma_channel = I2C2_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C2_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C2_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .name = "hwi2c3", \ + .Instance = I2C3, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB1_PERIPHEN_M7_I2C3, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk4, \ + .I2CKerClkSource = RCC_ConfigI2C3KerClkSource, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .HsInterface = I2C3_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C3_RX_DMA_DMA_RCC, \ + .dma_channel = I2C3_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C3_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C3_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .HsInterface = I2C3_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C3_TX_DMA_DMA_RCC, \ + .dma_channel = I2C3_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C3_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C3_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .name = "hwi2c4", \ + .Instance = I2C4, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB2_PERIPHEN_M7_I2C4, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C4KerClkSource, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .HsInterface = I2C4_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C4_RX_DMA_DMA_RCC, \ + .dma_channel = I2C4_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C4_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C4_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .HsInterface = I2C4_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C4_TX_DMA_DMA_RCC, \ + .dma_channel = I2C4_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C4_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C4_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C5 +#ifndef I2C5_BUS_CONFIG +#define I2C5_BUS_CONFIG \ + { \ + .name = "hwi2c5", \ + .Instance = I2C5, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C5_EV_IRQn, \ + .erirq_type = I2C5_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB2_PERIPHEN_M7_I2C5, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C5KerClkSource, \ + } +#endif /* I2C5_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C5 */ +#ifdef BSP_I2C5_RX_USING_DMA +#ifndef I2C5_RX_DMA_CONFIG +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .dma_irq = I2C5_RX_DMA_IRQ, \ + .HsInterface = I2C5_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C5_RX_DMA_DMA_RCC, \ + .dma_channel = I2C5_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C5_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C5_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C5_RX_DMA_CONFIG */ +#endif /* BSP_I2C5_RX_USING_DMA */ +#ifdef BSP_I2C5_TX_USING_DMA +#ifndef I2C5_TX_DMA_CONFIG +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .dma_irq = I2C5_TX_DMA_IRQ, \ + .HsInterface = I2C5_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C5_TX_DMA_DMA_RCC, \ + .dma_channel = I2C5_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C5_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C5_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C5_TX_DMA_CONFIG */ +#endif /* BSP_I2C5_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C6 +#ifndef I2C6_BUS_CONFIG +#define I2C6_BUS_CONFIG \ + { \ + .name = "hwi2c6", \ + .Instance = I2C6, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C6_EV_IRQn, \ + .erirq_type = I2C6_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB2_PERIPHEN_M7_I2C6, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C6KerClkSource, \ + } +#endif /* I2C6_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C6 */ +#ifdef BSP_I2C6_RX_USING_DMA +#ifndef I2C6_RX_DMA_CONFIG +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .dma_irq = I2C6_RX_DMA_IRQ, \ + .HsInterface = I2C6_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C6_RX_DMA_DMA_RCC, \ + .dma_channel = I2C6_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C6_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C6_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C6_RX_DMA_CONFIG */ +#endif /* BSP_I2C6_RX_USING_DMA */ +#ifdef BSP_I2C6_TX_USING_DMA +#ifndef I2C6_TX_DMA_CONFIG +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .dma_irq = I2C6_TX_DMA_IRQ, \ + .HsInterface = I2C6_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C6_TX_DMA_DMA_RCC, \ + .dma_channel = I2C6_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C6_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C6_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C6_TX_DMA_CONFIG */ +#endif /* BSP_I2C6_TX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C7 +#ifndef I2C7_BUS_CONFIG +#define I2C7_BUS_CONFIG \ + { \ + .name = "hwi2c7", \ + .Instance = I2C7, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C7_EV_IRQn, \ + .erirq_type = I2C7_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C7, \ + .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C7KerClkSource, \ + } +#endif /* I2C7_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C7 */ +#ifdef BSP_I2C7_RX_USING_DMA +#ifndef I2C7_RX_DMA_CONFIG +#define I2C7_RX_DMA_CONFIG \ + { \ + .Instance = I2C7_RX_DMA_INSTANCE, \ + .dma_irq = I2C7_RX_DMA_IRQ, \ + .HsInterface = I2C7_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C7_RX_DMA_DMA_RCC, \ + .dma_channel = I2C7_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C7_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C7_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C7_RX_DMA_CONFIG */ +#endif /* BSP_I2C7_RX_USING_DMA */ +#ifdef BSP_I2C7_TX_USING_DMA +#ifndef I2C7_TX_DMA_CONFIG +#define I2C7_TX_DMA_CONFIG \ + { \ + .Instance = I2C7_TX_DMA_INSTANCE, \ + .dma_irq = I2C7_TX_DMA_IRQ, \ + .HsInterface = I2C7_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C7_TX_DMA_DMA_RCC, \ + .dma_channel = I2C7_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C7_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C7_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C7_TX_DMA_CONFIG */ +#endif /* BSP_I2C7_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C8 +#ifndef I2C8_BUS_CONFIG +#define I2C8_BUS_CONFIG \ + { \ + .name = "hwi2c8", \ + .Instance = I2C8, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C8_EV_IRQn, \ + .erirq_type = I2C8_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C8, \ + .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C8KerClkSource, \ + } +#endif /* I2C8_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C8 */ +#ifdef BSP_I2C8_RX_USING_DMA +#ifndef I2C8_RX_DMA_CONFIG +#define I2C8_RX_DMA_CONFIG \ + { \ + .Instance = I2C8_RX_DMA_INSTANCE, \ + .dma_irq = I2C8_RX_DMA_IRQ, \ + .HsInterface = I2C8_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C8_RX_DMA_DMA_RCC, \ + .dma_channel = I2C8_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C8_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C8_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C8_RX_DMA_CONFIG */ +#endif /* BSP_I2C8_RX_USING_DMA */ +#ifdef BSP_I2C8_TX_USING_DMA +#ifndef I2C8_TX_DMA_CONFIG +#define I2C8_TX_DMA_CONFIG \ + { \ + .Instance = I2C8_TX_DMA_INSTANCE, \ + .dma_irq = I2C8_TX_DMA_IRQ, \ + .HsInterface = I2C8_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C8_TX_DMA_DMA_RCC, \ + .dma_channel = I2C8_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C8_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C8_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C8_TX_DMA_CONFIG */ +#endif /* BSP_I2C8_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C9 +#ifndef I2C9_BUS_CONFIG +#define I2C9_BUS_CONFIG \ + { \ + .name = "hwi2c9", \ + .Instance = I2C9, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C9_EV_IRQn, \ + .erirq_type = I2C9_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C9, \ + .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C9KerClkSource, \ + } +#endif /* I2C9_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C9 */ +#ifdef BSP_I2C9_RX_USING_DMA +#ifndef I2C9_RX_DMA_CONFIG +#define I2C9_RX_DMA_CONFIG \ + { \ + .Instance = I2C9_RX_DMA_INSTANCE, \ + .dma_irq = I2C9_RX_DMA_IRQ, \ + .HsInterface = I2C9_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C9_RX_DMA_DMA_RCC, \ + .dma_channel = I2C9_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C9_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C9_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C9_RX_DMA_CONFIG */ +#endif /* BSP_I2C9_RX_USING_DMA */ +#ifdef BSP_I2C9_TX_USING_DMA +#ifndef I2C9_TX_DMA_CONFIG +#define I2C9_TX_DMA_CONFIG \ + { \ + .Instance = I2C9_TX_DMA_INSTANCE, \ + .dma_irq = I2C9_TX_DMA_IRQ, \ + .HsInterface = I2C9_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C9_TX_DMA_DMA_RCC, \ + .dma_channel = I2C9_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C9_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C9_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C9_TX_DMA_CONFIG */ +#endif /* BSP_I2C9_TX_USING_DMA */ + + +#ifdef BSP_USING_HARD_I2C10 +#ifndef I2C10_BUS_CONFIG +#define I2C10_BUS_CONFIG \ + { \ + .name = "hwi2c10", \ + .Instance = I2C10, \ + .timing = 0x50012526, \ + .timeout = 0x1000, \ + .evirq_type = I2C10_EV_IRQn, \ + .erirq_type = I2C10_ER_IRQn, \ + .scl_af_width = 0, \ + .sda_af_width = 0, \ + .df_width = 0, \ + .periph = RCC_APB5_PERIPHEN_M7_I2C10, \ + .EnablePeriphClk = RCC_EnableAPB5PeriphClk2, \ + .I2CKerClkSource = RCC_ConfigI2C10KerClkSource, \ + } +#endif /* I2C10_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C10 */ +#ifdef BSP_I2C10_RX_USING_DMA +#ifndef I2C10_RX_DMA_CONFIG +#define I2C10_RX_DMA_CONFIG \ + { \ + .Instance = I2C10_RX_DMA_INSTANCE, \ + .dma_irq = I2C10_RX_DMA_IRQ, \ + .HsInterface = I2C10_RX_DMA_HANDSHAK, \ + .dma_rcc = I2C10_RX_DMA_DMA_RCC, \ + .dma_channel = I2C10_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C10_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C10_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C10_RX_DMA_CONFIG */ +#endif /* BSP_I2C10_RX_USING_DMA */ +#ifdef BSP_I2C10_TX_USING_DMA +#ifndef I2C10_TX_DMA_CONFIG +#define I2C10_TX_DMA_CONFIG \ + { \ + .Instance = I2C10_TX_DMA_INSTANCE, \ + .dma_irq = I2C10_TX_DMA_IRQ, \ + .HsInterface = I2C10_TX_DMA_HANDSHAK, \ + .dma_rcc = I2C10_TX_DMA_DMA_RCC, \ + .dma_channel = I2C10_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = I2C10_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = I2C10_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* I2C10_TX_DMA_CONFIG */ +#endif /* BSP_I2C10_TX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_HARD_CONFIG_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/spi_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/spi_config.h new file mode 100644 index 0000000000..c583ca5313 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/spi_config.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .SPIx = SPI1, \ + .bus_name = "spi1", \ + .irq_type = SPI1_IRQn, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + .HsInterface = SPI1_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI1_TX_DMA_DMA_RCC, \ + .dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI1_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI1_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + .HsInterface = SPI1_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI1_RX_DMA_DMA_RCC, \ + .dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI1_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI1_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + + + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .SPIx = SPI2, \ + .bus_name = "spi2", \ + .irq_type = SPI2_IRQn, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + .HsInterface = SPI2_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI2_TX_DMA_DMA_RCC, \ + .dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI2_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI2_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + .HsInterface = SPI2_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI2_RX_DMA_DMA_RCC, \ + .dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI2_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI2_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + + + + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .SPIx = SPI3, \ + .bus_name = "spi3", \ + .irq_type = SPI3_IRQn, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .dma_irq = SPI3_TX_DMA_IRQ, \ + .HsInterface = SPI3_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI3_TX_DMA_DMA_RCC, \ + .dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI3_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI3_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .dma_irq = SPI3_RX_DMA_IRQ, \ + .HsInterface = SPI3_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI3_RX_DMA_DMA_RCC, \ + .dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI3_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI3_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + + + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .SPIx = SPI4, \ + .bus_name = "spi4", \ + .irq_type = SPI4_IRQn, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .dma_irq = SPI4_TX_DMA_IRQ, \ + .HsInterface = SPI4_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI4_TX_DMA_DMA_RCC, \ + .dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI4_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI4_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .dma_irq = SPI4_RX_DMA_IRQ, \ + .HsInterface = SPI4_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI4_RX_DMA_DMA_RCC, \ + .dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI4_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI4_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + + + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .SPIx = SPI5, \ + .bus_name = "spi5", \ + .irq_type = SPI5_IRQn, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .dma_irq = SPI5_TX_DMA_IRQ, \ + .HsInterface = SPI5_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI5_TX_DMA_DMA_RCC, \ + .dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI5_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI5_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .dma_irq = SPI5_RX_DMA_IRQ, \ + .HsInterface = SPI5_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI5_RX_DMA_DMA_RCC, \ + .dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI5_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI5_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + + + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .SPIx = SPI6, \ + .bus_name = "spi6", \ + .irq_type = SPI6_IRQn, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .dma_irq = SPI6_TX_DMA_IRQ, \ + .HsInterface = SPI6_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI6_TX_DMA_DMA_RCC, \ + .dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI6_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI6_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .dma_irq = SPI6_RX_DMA_IRQ, \ + .HsInterface = SPI6_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI6_RX_DMA_DMA_RCC, \ + .dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI6_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI6_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef BSP_USING_SPI7 +#ifndef SPI7_BUS_CONFIG +#define SPI7_BUS_CONFIG \ + { \ + .SPIx = SPI7, \ + .bus_name = "spi7", \ + .irq_type = SPI7_IRQn, \ + } +#endif /* SPI7_BUS_CONFIG */ +#endif /* BSP_USING_SPI7 */ +#ifdef BSP_SPI7_TX_USING_DMA +#ifndef SPI7_TX_DMA_CONFIG +#define SPI7_TX_DMA_CONFIG \ + { \ + .Instance = SPI7_TX_DMA_INSTANCE, \ + .dma_irq = SPI7_TX_DMA_IRQ, \ + .HsInterface = SPI7_TX_DMA_HANDSHAK, \ + .dma_rcc = SPI7_TX_DMA_DMA_RCC, \ + .dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI7_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI7_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI7_TX_DMA_CONFIG */ +#endif /* BSP_SPI7_TX_USING_DMA */ +#ifdef BSP_SPI7_RX_USING_DMA +#ifndef SPI7_RX_DMA_CONFIG +#define SPI7_RX_DMA_CONFIG \ + { \ + .Instance = SPI7_RX_DMA_INSTANCE, \ + .dma_irq = SPI7_RX_DMA_IRQ, \ + .HsInterface = SPI7_RX_DMA_HANDSHAK, \ + .dma_rcc = SPI7_RX_DMA_DMA_RCC, \ + .dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = SPI7_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = SPI7_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* SPI7_RX_DMA_CONFIG */ +#endif /* BSP_SPI7_RX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/uart_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/uart_config.h new file mode 100644 index 0000000000..71b499535f --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/uart_config.h @@ -0,0 +1,832 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART1, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ +#if defined(BSP_UART1_RX_USING_DMA) +#if defined(UART1_RX_DMA_INSTANCE) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + .HsInterface = UART1_RX_DMA_HANDSHAK, \ + .dma_rcc = UART1_RX_DMA_DMA_RCC, \ + .dma_channel = UART1_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART1_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART1_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART1_RX_DMA_INSTANCE */ +#endif /* BSP_UART1_RX_USING_DMA */ +#if defined(BSP_UART1_TX_USING_DMA) +#if defined(UART1_TX_DMA_INSTANCE) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + .HsInterface = UART1_TX_DMA_HANDSHAK, \ + .dma_rcc = UART1_TX_DMA_DMA_RCC, \ + .dma_channel = UART1_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART1_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART1_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART1_TX_DMA_INSTANCE */ +#endif /* BSP_UART1_TX_USING_DMA */ + + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART2, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ +#if defined(BSP_UART2_RX_USING_DMA) +#if defined(UART2_RX_DMA_INSTANCE) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + .HsInterface = UART2_RX_DMA_HANDSHAK, \ + .dma_rcc = UART2_RX_DMA_DMA_RCC, \ + .dma_channel = UART2_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART2_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART2_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART2_RX_DMA_INSTANCE */ +#endif /* BSP_UART2_RX_USING_DMA */ +#if defined(BSP_UART2_TX_USING_DMA) +#if defined(UART2_TX_DMA_INSTANCE) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + .HsInterface = UART2_TX_DMA_HANDSHAK, \ + .dma_rcc = UART2_TX_DMA_DMA_RCC, \ + .dma_channel = UART2_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART2_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART2_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART2_TX_DMA_INSTANCE */ +#endif /* BSP_UART2_TX_USING_DMA */ + + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART3, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ +#if defined(BSP_UART3_RX_USING_DMA) +#if defined(UART3_RX_DMA_INSTANCE) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + .HsInterface = UART3_RX_DMA_HANDSHAK, \ + .dma_rcc = UART3_RX_DMA_DMA_RCC, \ + .dma_channel = UART3_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART3_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART3_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART3_RX_DMA_INSTANCE */ +#endif /* BSP_UART3_RX_USING_DMA */ +#if defined(BSP_UART3_TX_USING_DMA) +#if defined(UART3_TX_DMA_INSTANCE) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + .HsInterface = UART3_TX_DMA_HANDSHAK, \ + .dma_rcc = UART3_TX_DMA_DMA_RCC, \ + .dma_channel = UART3_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART3_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART3_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART3_TX_DMA_INSTANCE */ +#endif /* BSP_UART3_TX_USING_DMA */ + + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = USART4, \ + .irq_type = USART4_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_USART4, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ +#if defined(BSP_UART4_RX_USING_DMA) +#if defined(UART4_RX_DMA_INSTANCE) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + .HsInterface = UART4_RX_DMA_HANDSHAK, \ + .dma_rcc = UART4_RX_DMA_DMA_RCC, \ + .dma_channel = UART4_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART4_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART4_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART4_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART4_RX_DMA_INSTANCE */ +#endif /* BSP_UART4_RX_USING_DMA */ +#if defined(BSP_UART4_TX_USING_DMA) +#if defined(UART4_TX_DMA_INSTANCE) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .dma_irq = UART4_TX_DMA_IRQ, \ + .HsInterface = UART4_TX_DMA_HANDSHAK, \ + .dma_rcc = UART4_TX_DMA_DMA_RCC, \ + .dma_channel = UART4_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART4_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART4_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART4_TX_DMA_INSTANCE */ +#endif /* BSP_UART4_TX_USING_DMA */ + + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = USART5, \ + .irq_type = USART5_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART5, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART5_CONFIG */ +#endif /* BSP_USING_UART5 */ +#if defined(BSP_UART5_RX_USING_DMA) +#if defined(UART5_RX_DMA_INSTANCE) +#ifndef UART5_DMA_RX_CONFIG +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .dma_irq = UART5_RX_DMA_IRQ, \ + .HsInterface = UART5_RX_DMA_HANDSHAK, \ + .dma_rcc = UART5_RX_DMA_DMA_RCC, \ + .dma_channel = UART5_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART5_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART5_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART5_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART5_RX_DMA_INSTANCE */ +#endif /* BSP_UART5_RX_USING_DMA */ +#if defined(BSP_UART5_TX_USING_DMA) +#if defined(UART5_TX_DMA_INSTANCE) +#ifndef UART5_DMA_TX_CONFIG +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .dma_irq = UART5_TX_DMA_IRQ, \ + .HsInterface = UART5_TX_DMA_HANDSHAK, \ + .dma_rcc = UART5_TX_DMA_DMA_RCC, \ + .dma_channel = UART5_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART5_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART5_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART5_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART5_TX_DMA_INSTANCE */ +#endif /* BSP_UART5_TX_USING_DMA */ + + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = USART6, \ + .irq_type = USART6_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART6, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART6_CONFIG */ +#endif /* BSP_USING_UART6 */ +#if defined(BSP_UART6_RX_USING_DMA) +#if defined(UART6_RX_DMA_INSTANCE) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .dma_irq = UART6_RX_DMA_IRQ, \ + .HsInterface = UART6_RX_DMA_HANDSHAK, \ + .dma_rcc = UART6_RX_DMA_DMA_RCC, \ + .dma_channel = UART6_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART6_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART6_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART6_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART6_RX_DMA_INSTANCE */ +#endif /* BSP_UART6_RX_USING_DMA */ +#if defined(BSP_UART6_TX_USING_DMA) +#if defined(UART6_TX_DMA_INSTANCE) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .dma_irq = UART6_TX_DMA_IRQ, \ + .HsInterface = UART6_TX_DMA_HANDSHAK, \ + .dma_rcc = UART6_TX_DMA_DMA_RCC, \ + .dma_channel = UART6_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART6_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART6_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART6_TX_DMA_INSTANCE */ +#endif /* BSP_UART6_TX_USING_DMA */ + + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = USART7, \ + .irq_type = USART7_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART7, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART7_CONFIG */ +#endif /* BSP_USING_UART7 */ +#if defined(BSP_UART7_RX_USING_DMA) +#if defined(UART7_RX_DMA_INSTANCE) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .dma_irq = UART7_RX_DMA_IRQ, \ + .HsInterface = UART7_RX_DMA_HANDSHAK, \ + .dma_rcc = UART7_RX_DMA_DMA_RCC, \ + .dma_channel = UART7_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART7_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART7_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART7_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART7_RX_DMA_INSTANCE */ +#endif /* BSP_UART7_RX_USING_DMA */ +#if defined(BSP_UART7_TX_USING_DMA) +#if defined(UART7_TX_DMA_INSTANCE) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .dma_irq = UART7_TX_DMA_IRQ, \ + .HsInterface = UART7_TX_DMA_HANDSHAK, \ + .dma_rcc = UART7_TX_DMA_DMA_RCC, \ + .dma_channel = UART7_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART7_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART7_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART7_TX_DMA_INSTANCE */ +#endif /* BSP_UART7_TX_USING_DMA */ + + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = USART8, \ + .irq_type = USART8_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_USART8, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART8_CONFIG */ +#endif /* BSP_USING_UART8 */ +#if defined(BSP_UART8_RX_USING_DMA) +#if defined(UART8_RX_DMA_INSTANCE) +#ifndef UART8_DMA_RX_CONFIG +#define UART8_DMA_RX_CONFIG \ + { \ + .Instance = UART8_RX_DMA_INSTANCE, \ + .dma_irq = UART8_RX_DMA_IRQ, \ + .HsInterface = UART8_RX_DMA_HANDSHAK, \ + .dma_rcc = UART8_RX_DMA_DMA_RCC, \ + .dma_channel = UART8_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART8_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART8_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART8_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART8_RX_DMA_INSTANCE */ +#endif /* BSP_UART8_RX_USING_DMA */ +#if defined(BSP_UART8_TX_USING_DMA) +#if defined(UART8_TX_DMA_INSTANCE) +#ifndef UART8_DMA_TX_CONFIG +#define UART8_DMA_TX_CONFIG \ + { \ + .Instance = UART8_TX_DMA_INSTANCE, \ + .dma_irq = UART8_TX_DMA_IRQ, \ + .HsInterface = UART8_TX_DMA_HANDSHAK, \ + .dma_rcc = UART8_TX_DMA_DMA_RCC, \ + .dma_channel = UART8_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART8_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART8_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART8_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART8_TX_DMA_INSTANCE */ +#endif /* BSP_UART8_TX_USING_DMA */ + + +#if defined(BSP_USING_UART9) +#ifndef UART9_CONFIG +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = UART9, \ + .irq_type = UART9_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART9, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART9_CONFIG */ +#endif /* BSP_USING_UART9 */ +#if defined(BSP_UART9_RX_USING_DMA) +#if defined(UART9_RX_DMA_INSTANCE) +#ifndef UART9_DMA_RX_CONFIG +#define UART9_DMA_RX_CONFIG \ + { \ + .Instance = UART9_RX_DMA_INSTANCE, \ + .dma_irq = UART9_RX_DMA_IRQ, \ + .HsInterface = UART9_RX_DMA_HANDSHAK, \ + .dma_rcc = UART9_RX_DMA_DMA_RCC, \ + .dma_channel = UART9_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART9_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART9_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART9_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART9_RX_DMA_INSTANCE */ +#endif /* BSP_UART9_RX_USING_DMA */ +#if defined(BSP_UART9_TX_USING_DMA) +#if defined(UART9_TX_DMA_INSTANCE) +#ifndef UART9_DMA_TX_CONFIG +#define UART9_DMA_TX_CONFIG \ + { \ + .Instance = UART9_TX_DMA_INSTANCE, \ + .dma_irq = UART9_TX_DMA_IRQ, \ + .HsInterface = UART9_TX_DMA_HANDSHAK, \ + .dma_rcc = UART9_TX_DMA_DMA_RCC, \ + .dma_channel = UART9_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART9_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART9_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART9_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART9_TX_DMA_INSTANCE */ +#endif /* BSP_UART9_TX_USING_DMA */ + + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = UART10, \ + .irq_type = UART10_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART10, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART10_CONFIG */ +#endif /* BSP_USING_UART10 */ +#if defined(BSP_UART10_RX_USING_DMA) +#if defined(UART10_RX_DMA_INSTANCE) +#ifndef UART10_DMA_RX_CONFIG +#define UART10_DMA_RX_CONFIG \ + { \ + .Instance = UART10_RX_DMA_INSTANCE, \ + .dma_irq = UART10_RX_DMA_IRQ, \ + .HsInterface = UART10_RX_DMA_HANDSHAK, \ + .dma_rcc = UART10_RX_DMA_DMA_RCC, \ + .dma_channel = UART10_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART10_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART10_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART10_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART10_RX_DMA_INSTANCE */ +#endif /* BSP_UART10_RX_USING_DMA */ +#if defined(BSP_UART10_TX_USING_DMA) +#if defined(UART10_TX_DMA_INSTANCE) +#ifndef UART10_DMA_TX_CONFIG +#define UART10_DMA_TX_CONFIG \ + { \ + .Instance = UART10_TX_DMA_INSTANCE, \ + .dma_irq = UART10_TX_DMA_IRQ, \ + .HsInterface = UART10_TX_DMA_HANDSHAK, \ + .dma_rcc = UART10_TX_DMA_DMA_RCC, \ + .dma_channel = UART10_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART10_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART10_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART10_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART10_TX_DMA_INSTANCE */ +#endif /* BSP_UART10_TX_USING_DMA */ + + +#if defined(BSP_USING_UART11) +#ifndef UART11_CONFIG +#define UART11_CONFIG \ + { \ + .name = "uart11", \ + .Instance = UART11, \ + .irq_type = UART11_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART11, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART11_CONFIG */ +#endif /* BSP_USING_UART11 */ +#if defined(BSP_UART11_RX_USING_DMA) +#if defined(UART11_RX_DMA_INSTANCE) +#ifndef UART11_DMA_RX_CONFIG +#define UART11_DMA_RX_CONFIG \ + { \ + .Instance = UART11_RX_DMA_INSTANCE, \ + .dma_irq = UART11_RX_DMA_IRQ, \ + .HsInterface = UART11_RX_DMA_HANDSHAK, \ + .dma_rcc = UART11_RX_DMA_DMA_RCC, \ + .dma_channel = UART11_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART11_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART11_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART11_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART11_RX_DMA_INSTANCE */ +#endif /* BSP_UART11_RX_USING_DMA */ +#if defined(BSP_UART11_TX_USING_DMA) +#if defined(UART11_TX_DMA_INSTANCE) +#ifndef UART11_DMA_TX_CONFIG +#define UART11_DMA_TX_CONFIG \ + { \ + .Instance = UART11_TX_DMA_INSTANCE, \ + .dma_irq = UART11_TX_DMA_IRQ, \ + .HsInterface = UART11_TX_DMA_HANDSHAK, \ + .dma_rcc = UART11_TX_DMA_DMA_RCC, \ + .dma_channel = UART11_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART11_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART11_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART11_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART11_TX_DMA_INSTANCE */ +#endif /* BSP_UART11_TX_USING_DMA */ + + +#if defined(BSP_USING_UART12) +#ifndef UART12_CONFIG +#define UART12_CONFIG \ + { \ + .name = "uart12", \ + .Instance = UART12, \ + .irq_type = UART12_IRQn, \ + .periph = RCC_APB1_PERIPHEN_M7_UART12, \ + .EnablePeriphClk = RCC_EnableAPB1PeriphClk3, \ + } +#endif /* UART12_CONFIG */ +#endif /* BSP_USING_UART12 */ +#if defined(BSP_UART12_RX_USING_DMA) +#if defined(UART12_RX_DMA_INSTANCE) +#ifndef UART12_DMA_RX_CONFIG +#define UART12_DMA_RX_CONFIG \ + { \ + .Instance = UART12_RX_DMA_INSTANCE, \ + .dma_irq = UART12_RX_DMA_IRQ, \ + .HsInterface = UART12_RX_DMA_HANDSHAK, \ + .dma_rcc = UART12_RX_DMA_DMA_RCC, \ + .dma_channel = UART12_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART12_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART12_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART12_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART12_RX_DMA_INSTANCE */ +#endif /* BSP_UART12_RX_USING_DMA */ +#if defined(BSP_UART12_TX_USING_DMA) +#if defined(UART12_TX_DMA_INSTANCE) +#ifndef UART12_DMA_TX_CONFIG +#define UART12_DMA_TX_CONFIG \ + { \ + .Instance = UART12_TX_DMA_INSTANCE, \ + .dma_irq = UART12_TX_DMA_IRQ, \ + .HsInterface = UART12_TX_DMA_HANDSHAK, \ + .dma_rcc = UART12_TX_DMA_DMA_RCC, \ + .dma_channel = UART12_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART12_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART12_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART12_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART12_TX_DMA_INSTANCE */ +#endif /* BSP_UART12_TX_USING_DMA */ + + +#if defined(BSP_USING_UART13) +#ifndef UART13_CONFIG +#define UART13_CONFIG \ + { \ + .name = "uart13", \ + .Instance = UART13, \ + .irq_type = UART13_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_UART13, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART13_CONFIG */ +#endif /* BSP_USING_UART13 */ +#if defined(BSP_UART13_RX_USING_DMA) +#if defined(UART13_RX_DMA_INSTANCE) +#ifndef UART13_DMA_RX_CONFIG +#define UART13_DMA_RX_CONFIG \ + { \ + .Instance = UART13_RX_DMA_INSTANCE, \ + .dma_irq = UART13_RX_DMA_IRQ, \ + .HsInterface = UART13_RX_DMA_HANDSHAK, \ + .dma_rcc = UART13_RX_DMA_DMA_RCC, \ + .dma_channel = UART13_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART13_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART13_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART13_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART13_RX_DMA_INSTANCE */ +#endif /* BSP_UART13_RX_USING_DMA */ +#if defined(BSP_UART13_TX_USING_DMA) +#if defined(UART13_TX_DMA_INSTANCE) +#ifndef UART13_DMA_TX_CONFIG +#define UART13_DMA_TX_CONFIG \ + { \ + .Instance = UART13_TX_DMA_INSTANCE, \ + .dma_irq = UART13_TX_DMA_IRQ, \ + .HsInterface = UART13_TX_DMA_HANDSHAK, \ + .dma_rcc = UART13_TX_DMA_DMA_RCC, \ + .dma_channel = UART13_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART13_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART13_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART13_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART13_TX_DMA_INSTANCE */ +#endif /* BSP_UART13_TX_USING_DMA */ + + +#if defined(BSP_USING_UART14) +#ifndef UART14_CONFIG +#define UART14_CONFIG \ + { \ + .name = "uart14", \ + .Instance = UART14, \ + .irq_type = UART14_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_UART14, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART14_CONFIG */ +#endif /* BSP_USING_UART14 */ +#if defined(BSP_UART14_RX_USING_DMA) +#if defined(UART14_RX_DMA_INSTANCE) +#ifndef UART14_DMA_RX_CONFIG +#define UART14_DMA_RX_CONFIG \ + { \ + .Instance = UART14_RX_DMA_INSTANCE, \ + .dma_irq = UART14_RX_DMA_IRQ, \ + .HsInterface = UART14_RX_DMA_HANDSHAK, \ + .dma_rcc = UART14_RX_DMA_DMA_RCC, \ + .dma_channel = UART14_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART14_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART14_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART14_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART14_RX_DMA_INSTANCE */ +#endif /* BSP_UART14_RX_USING_DMA */ +#if defined(BSP_UART14_TX_USING_DMA) +#if defined(UART14_TX_DMA_INSTANCE) +#ifndef UART14_DMA_TX_CONFIG +#define UART14_DMA_TX_CONFIG \ + { \ + .Instance = UART14_TX_DMA_INSTANCE, \ + .dma_irq = UART14_TX_DMA_IRQ, \ + .HsInterface = UART14_TX_DMA_HANDSHAK, \ + .dma_rcc = UART14_TX_DMA_DMA_RCC, \ + .dma_channel = UART14_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART14_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART14_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART14_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART14_TX_DMA_INSTANCE */ +#endif /* BSP_UART14_TX_USING_DMA */ + + +#if defined(BSP_USING_UART15) +#ifndef UART15_CONFIG +#define UART15_CONFIG \ + { \ + .name = "uart15", \ + .Instance = UART15, \ + .irq_type = UART15_IRQn, \ + .periph = RCC_APB2_PERIPHEN_M7_UART15, \ + .EnablePeriphClk = RCC_EnableAPB2PeriphClk3, \ + } +#endif /* UART15_CONFIG */ +#endif /* BSP_USING_UART15 */ +#if defined(BSP_UART15_RX_USING_DMA) +#if defined(UART15_RX_DMA_INSTANCE) +#ifndef UART15_DMA_RX_CONFIG +#define UART15_DMA_RX_CONFIG \ + { \ + .Instance = UART15_RX_DMA_INSTANCE, \ + .dma_irq = UART15_RX_DMA_IRQ, \ + .HsInterface = UART15_RX_DMA_HANDSHAK, \ + .dma_rcc = UART15_RX_DMA_DMA_RCC, \ + .dma_channel = UART15_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART15_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART15_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART15_DMA_RX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART15_RX_DMA_INSTANCE */ +#endif /* BSP_UART15_RX_USING_DMA */ +#if defined(BSP_UART15_TX_USING_DMA) +#if defined(UART15_TX_DMA_INSTANCE) +#ifndef UART15_DMA_TX_CONFIG +#define UART15_DMA_TX_CONFIG \ + { \ + .Instance = UART15_TX_DMA_INSTANCE, \ + .dma_irq = UART15_TX_DMA_IRQ, \ + .HsInterface = UART15_TX_DMA_HANDSHAK, \ + .dma_rcc = UART15_TX_DMA_DMA_RCC, \ + .dma_channel = UART15_TX_DMA_DMA_CHANNEL, \ + .dmamux_channel = UART15_TX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = UART15_TX_DMA_DMAMUX_REQUEST, \ + } +#endif /* UART15_DMA_TX_CONFIG */ +#else +#error "The DMA resource is not available." +#endif /* UART15_TX_DMA_INSTANCE */ +#endif /* BSP_UART15_TX_USING_DMA */ + + +#if defined(BSP_USING_LPUART1) +#ifndef LPUART1_CONFIG +#define LPUART1_CONFIG \ + { \ + .name = "lpuart1", \ + .Instance = LPUART1, \ + .irq_type = LPUART1_IRQn, \ + .periph = RCC_RD_PERIPHEN_M7_LPUART1, \ + .EnablePeriphClk = RCC_EnableRDPeriphClk1, \ + } +#endif /* LPUART1_CONFIG */ +#endif /* BSP_USING_LPUART1 */ +#if defined(BSP_LPUART1_RX_USING_DMA) +#ifndef LPUART1_DMA_RX_CONFIG +#define LPUART1_DMA_RX_CONFIG \ + { \ + .Instance = LPUART1_RX_DMA_INSTANCE, \ + .dma_irq = LPUART1_RX_DMA_IRQ, \ + .HsInterface = LPUART1_RX_DMA_HANDSHAK, \ + .dma_rcc = LPUART1_RX_DMA_DMA_RCC, \ + .dma_channel = LPUART1_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = LPUART1_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = LPUART1_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* LPUART1_DMA_RX_CONFIG */ +#endif /* BSP_LPUART1_RX_USING_DMA */ + + +#if defined(BSP_USING_LPUART2) +#ifndef LPUART2_CONFIG +#define LPUART2_CONFIG \ + { \ + .name = "lpuart2", \ + .Instance = LPUART2, \ + .irq_type = LPUART2_IRQn, \ + .periph = RCC_RD_PERIPHEN_M7_LPUART2, \ + .EnablePeriphClk = RCC_EnableRDPeriphClk1, \ + } +#endif /* LPUART2_CONFIG */ +#endif /* BSP_USING_LPUART2 */ +#if defined(BSP_LPUART2_RX_USING_DMA) +#ifndef LPUART2_DMA_RX_CONFIG +#define LPUART2_DMA_RX_CONFIG \ + { \ + .Instance = LPUART2_RX_DMA_INSTANCE, \ + .dma_irq = LPUART2_RX_DMA_IRQ, \ + .HsInterface = LPUART2_RX_DMA_HANDSHAK, \ + .dma_rcc = LPUART2_RX_DMA_DMA_RCC, \ + .dma_channel = LPUART2_RX_DMA_DMA_CHANNEL, \ + .dmamux_channel = LPUART2_RX_DMA_DMAMUX_CHANNEL, \ + .dmamux_request = LPUART2_RX_DMA_DMAMUX_REQUEST, \ + } +#endif /* LPUART2_DMA_RX_CONFIG */ +#endif /* BSP_LPUART2_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_CONFIG_H__ */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c new file mode 100644 index 0000000000..cd04672c07 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_adc.c @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include +#include + +#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) +#include "drv_config.h" + +//#define DRV_DEBUG +#define LOG_TAG "drv.adc" +#include + + +typedef struct +{ + ADC_Module *ADCx; + uint32_t AHB_periph; + void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd); + + ADC_CTRL3_CKMOD ADC_ClkMode; + uint32_t Pll_CLK_source; + uint32_t RCC_ADCPrescaler; + + uint32_t Rank; + uint32_t ADC_SampleTime; + + ADC_InitType Init; +} ADC_InitInfo_t; + +static ADC_InitInfo_t adc_config[] = +{ +#ifdef BSP_USING_ADC1 + ADC1_CONFIG, +#endif + +#ifdef BSP_USING_ADC2 + ADC2_CONFIG, +#endif + +#ifdef BSP_USING_ADC3 + ADC3_CONFIG, +#endif +}; + + +struct n32_adc +{ + ADC_InitInfo_t ADC_Info; + struct rt_adc_device n32_adc_device; +}; + + +static struct n32_adc n32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])]; + + +static rt_err_t n32_adc_get_channel(rt_int8_t rt_channel, uint32_t *n32_channel) +{ + switch (rt_channel) + { + case 0: + *n32_channel = ADC_CH_0; + break; + case 1: + *n32_channel = ADC_CH_1; + break; + case 2: + *n32_channel = ADC_CH_2; + break; + case 3: + *n32_channel = ADC_CH_3; + break; + case 4: + *n32_channel = ADC_CH_4; + break; + case 5: + *n32_channel = ADC_CH_5; + break; + case 6: + *n32_channel = ADC_CH_6; + break; + case 7: + *n32_channel = ADC_CH_7; + break; + case 8: + *n32_channel = ADC_CH_8; + break; + case 9: + *n32_channel = ADC_CH_9; + break; + case 10: + *n32_channel = ADC_CH_10; + break; + case 11: + *n32_channel = ADC_CH_11; + break; + case 12: + *n32_channel = ADC_CH_12; + break; + case 13: + *n32_channel = ADC_CH_13; + break; + case 14: + *n32_channel = ADC_CH_14; + break; + case 15: + *n32_channel = ADC_CH_15; + break; + case 16: + *n32_channel = ADC_CH_16; + break; + case 17: + *n32_channel = ADC_CH_17; + break; + case 18: + *n32_channel = ADC_CH_18; + break; + case 19: + *n32_channel = ADC_CH_19; + break; + +#if defined(SOC_SERIES_N32H7xx) +#ifdef ADC3_Channel_19_VREFINT + case RT_ADC_INTERN_CH_VREF: + *n32_channel = ADC3_Channel_19_VREFINT; + break; +#endif /* ADC3_Channel_19_VREFINT */ + +#ifdef ADC3_Channel_17_Battery_DIV4 + case RT_ADC_INTERN_CH_VBAT: + *n32_channel = ADC3_Channel_17_Battery_DIV4; + break; +#endif /* ADC3_Channel_17_Battery_DIV4 */ + +#ifdef ADC3_Channel_18_Temperture_Sensor + case RT_ADC_INTERN_CH_TEMPER: + *n32_channel = ADC3_Channel_18_Temperture_Sensor; + break; +#endif /* ADC3_Channel_18_Temperture_Sensor */ +#endif + + default: + return -RT_EINVAL; + } + + return RT_EOK; +} + + +static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) +{ + volatile uint32_t index = 0; + uint32_t ADC_Channel; + ADC_InitInfo_t *n32_adc_info; + + RT_ASSERT(device != RT_NULL); + n32_adc_info = device->parent.user_data; + + if (enabled) + { + if (n32_adc_get_channel(channel, &ADC_Channel) != RT_EOK) + { + LOG_E("ADC channel illegal: %d", channel); + return -RT_EINVAL; + } + +#if defined(SOC_SERIES_N32H7xx) + + /* */ + if ((channel == RT_ADC_INTERN_CH_VREF) || (channel == RT_ADC_INTERN_CH_VBAT) || (channel == RT_ADC_INTERN_CH_TEMPER)) + { + if (n32_adc_info->ADCx != ADC3) + { + LOG_E("%s not supported", device->parent.parent.name); + return -RT_EINVAL; + } + + if (channel == RT_ADC_INTERN_CH_VREF) + { + /* Enable ADC Vrefint channel */ + ADC_EnableVrefint(ENABLE); + } + else if (channel == RT_ADC_INTERN_CH_TEMPER) + { + /* Enable ADC temperature sensor */ + ADC_EnableTempSensor(ENABLE); + } + else + { + /* Enable ADC battery voltage monitor */ + ADC_EnableBatteryVoltageMonitor(ENABLE); + } + } + + /* Enable ADC */ + ADC_Enable(n32_adc_info->ADCx, ENABLE); + /* Check ADC Ready */ + while (ADC_GetFlagStatus(n32_adc_info->ADCx, ADC_FLAG_RDY) == RESET) + { + } + + /* Start ADC calibration */ + ADC_CalibrationOperation(n32_adc_info->ADCx); + /* Check the end of ADCx calibration */ + while (ADC_GetCalibrationStatus(n32_adc_info->ADCx)) + { + } + + /* Configures ADC regular channel */ + ADC_ConfigRegularChannel(n32_adc_info->ADCx, ADC_Channel, n32_adc_info->Rank, n32_adc_info->ADC_SampleTime); + + for (index = 0U; index < 100U; index++) + { + __NOP(); + } + + /* Enable ADC Regular channel conversion */ + ADC_StartRegularConv(n32_adc_info->ADCx); + + while ((n32_adc_info->ADCx->CTRL3 & ADC_CTRL3_RSTART) != ADC_CTRL3_RSTART) + { + } + + /* Start ADC Software Conversion */ + ADC_EnableSoftwareStartConv(n32_adc_info->ADCx, ENABLE); +#endif + } + else + { +#if defined(SOC_SERIES_N32H7xx) + if (channel == RT_ADC_INTERN_CH_VREF) + { + /* Disable ADC Vrefint channel */ + ADC_EnableVrefint(DISABLE); + } + else if (channel == RT_ADC_INTERN_CH_VBAT) + { + /* Disable ADC battery voltage monitor */ + ADC_EnableBatteryVoltageMonitor(DISABLE); + } + else + { + /* Disable ADC temperature sensor */ + ADC_EnableTempSensor(DISABLE); + } + + /* Disable ADC */ + ADC_Enable(n32_adc_info->ADCx, DISABLE); +#endif + } + + return RT_EOK; +} + + +static rt_err_t n32_adc_get_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) +{ + uint16_t Convert_Value; + ADC_InitInfo_t *n32_adc_info; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + n32_adc_info = device->parent.user_data; + +#if defined(SOC_SERIES_N32H7xx) + /* Wait for the ADC to convert */ + while (ADC_GetFlagStatus(n32_adc_info->ADCx, ADC_FLAG_ENDC) != SET) + { + } + + /* Clear ADC Flag */ + ADC_ClearFlag(n32_adc_info->ADCx, ADC_FLAG_ENDC); + ADC_ClearFlag(n32_adc_info->ADCx, ADC_FLAG_STR); + + /* Get ADC value */ + Convert_Value = ADC_GetDat(n32_adc_info->ADCx); + + if (channel == RT_ADC_INTERN_CH_VBAT) + Convert_Value *= 4U; +#endif + + *value = Convert_Value; + + return RT_EOK; +} + + +static rt_uint8_t n32_adc_get_resolution(struct rt_adc_device *device) +{ + rt_uint8_t Resolution = 0; + ADC_InitInfo_t *n32_adc_info = device->parent.user_data; + + RT_ASSERT(device != RT_NULL); + + switch (n32_adc_info->Init.Resolution) + { +#if defined(SOC_SERIES_N32H7xx) + case ADC_DATA_RES_12BIT: + { + Resolution = 12; + break; + } + + case ADC_DATA_RES_10BIT: + { + Resolution = 10; + break; + } +#endif + default: + break; + } + + return Resolution; +} + + +static rt_int16_t n32_adc_get_vref (struct rt_adc_device *device) +{ + return 3300; +} + + +static const struct rt_adc_ops n32_adc_ops = +{ + .enabled = n32_adc_enabled, + .convert = n32_adc_get_value, + .get_resolution = n32_adc_get_resolution, + .get_vref = n32_adc_get_vref, +}; + + +static int n32_adc_init(void) +{ + int result = RT_EOK; + /* save adc name */ + char name_buf[5] = {'a', 'd', 'c', '0', 0}; + int i = 0; + + for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++) + { + /* ADC init */ + name_buf[3] = '0'; + n32_adc_obj[i].ADC_Info = adc_config[i]; +#if defined(ADC1) + if (n32_adc_obj[i].ADC_Info.ADCx == ADC1) + { + name_buf[3] = '1'; + } +#endif +#if defined(ADC2) + if (n32_adc_obj[i].ADC_Info.ADCx == ADC2) + { + name_buf[3] = '2'; + } +#endif +#if defined(ADC3) + if (n32_adc_obj[i].ADC_Info.ADCx == ADC3) + { + name_buf[3] = '3'; + } +#endif + + ADC_Init(n32_adc_obj[i].ADC_Info.ADCx, &n32_adc_obj[i].ADC_Info.Init); + + /* register ADC device */ + if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device, name_buf, &n32_adc_ops, &n32_adc_obj[i].ADC_Info) == RT_EOK) + { + LOG_D("%s init success", name_buf); + } + else + { + LOG_E("%s register failed", name_buf); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(n32_adc_init); + +#endif /* BSP_USING_ADC */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h new file mode 100644 index 0000000000..10d904f3f8 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_CONFIG_H_ +#define __DRV_CONFIG_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(SOC_SERIES_N32H7xx) +#include "h7/dma_config.h" +#include "h7/uart_config.h" +#include "h7/i2c_hard_config.h" +#include "h7/adc_config.h" +#include "h7/spi_config.h" +#endif /* defined(SOC_SERIES_N32H7xx) */ + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_CONFIG_H_ */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h new file mode 100644 index 0000000000..4ede0efca6 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_DMA_H_ +#define __DRV_DMA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define DMA_BLOCK_SIZE (4095) + +struct dma_config +{ + DMA_Module *Instance; + IRQn_Type dma_irq; + DMA_ChHwHsIfType HsInterface; + rt_uint32_t dma_rcc; + DMA_ChNumType dma_channel; + rt_uint32_t dmamux_channel; + rt_uint32_t dmamux_request; +}; + +#ifdef __cplusplus +} +#endif + +#endif /*__DRV_DMA_H_ */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c new file mode 100644 index 0000000000..ea9fc1aaf0 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c @@ -0,0 +1,628 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include "drv_gpio.h" + +#ifdef BSP_USING_GPIO + +#define PIN_NUM(port, no) (((((port) & 0xFU) << 4U) | ((no) & 0xFU))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4U) & 0xFU)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFU)) + +#define PIN_STPORT(pin) ((GPIO_Module *)(GPIOA_BASE + (0x400U * PIN_PORT(pin)))) +#define PIN_STPIN(pin) ((uint16_t)(1U << PIN_NO(pin))) + +#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) + +static uint32_t pin_irq_enable_mask = 0; + +#if defined(GPIOK) + #define __N32_PORT_MAX 8u +#elif defined(GPIOJ) + #define __N32_PORT_MAX 16u +#elif defined(GPIOI) + #define __N32_PORT_MAX 16u +#elif defined(GPIOH) + #define __N32_PORT_MAX 16u +#elif defined(GPIOG) + #define __N32_PORT_MAX 16u +#elif defined(GPIOF) + #define __N32_PORT_MAX 16u +#elif defined(GPIOE) + #define __N32_PORT_MAX 16u +#elif defined(GPIOD) + #define __N32_PORT_MAX 16u +#elif defined(GPIOC) + #define __N32_PORT_MAX 16u +#elif defined(GPIOB) + #define __N32_PORT_MAX 16u +#elif defined(GPIOA) + #define __N32_PORT_MAX 16u +#else + #define __N32_PORT_MAX 0u + #error Unsupported N32 GPIO peripheral. +#endif + +#define PIN_STPORT_MAX __N32_PORT_MAX + +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI_LINE0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI_LINE1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI_LINE2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI_LINE3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI_LINE4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI_LINE5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI_LINE6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI_LINE7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI_LINE8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI_LINE9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI_LINE10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI_LINE11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI_LINE12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI_LINE13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI_LINE14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI_LINE15, EXTI15_10_IRQn}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +/* e.g. PA.0 */ +static rt_base_t n32_pin_get(const char *name) +{ + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 4U) || (name_len >= 6U)) + { + goto out; + } + if ((name[0] != 'P') || (name[2] != '.')) + { + goto out; + } + + if ((name[1] >= 'A') && (name[1] <= 'Z')) + { + hw_port_num = (int)(name[1] - 'A'); + } + else + { + goto out; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; + +out: + rt_kprintf("Px.y x:A~Z y:0-15, e.g. PA.0\n"); + return -RT_EINVAL; +} + +static void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + GPIO_Module *gpio_port; + uint16_t gpio_pin; + + if (PIN_PORT(pin) < PIN_STPORT_MAX) + { + gpio_port = PIN_STPORT(pin); + gpio_pin = PIN_STPIN(pin); + + if (value != 0) + { + gpio_port->PBSC = gpio_pin; + } + else + { + gpio_port->PBC = gpio_pin; + } + } +} + +static rt_ssize_t n32_pin_read(rt_device_t dev, rt_base_t pin) +{ + GPIO_Module *gpio_port; + uint16_t gpio_pin; + Bit_OperateType state = Bit_RESET; + + if (PIN_PORT(pin) < PIN_STPORT_MAX) + { + gpio_port = PIN_STPORT(pin); + gpio_pin = PIN_STPIN(pin); + + if ((gpio_port->PID & gpio_pin) != Bit_RESET) + { + state = Bit_SET; + } + else + { + state = Bit_RESET; + } + } + else + { + return -RT_EINVAL; + } + + return (state == Bit_RESET) ? PIN_LOW : PIN_HIGH; +} + +static void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + GPIO_InitType GPIO_InitStructure; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return; + } + + GPIO_InitStruct(&GPIO_InitStructure); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.Pin = PIN_STPIN(pin); + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + } + + GPIO_InitPeripheral(PIN_STPORT(pin), &GPIO_InitStructure); +} + +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + rt_int32_t i; + for (i = 0; i < 32; i++) + { + if (((rt_uint32_t)0x01 << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + + +static rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_base_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitType GPIO_InitStructure; + EXTI_InitType EXTI_InitStructure; + + if (PIN_PORT(pin) >= PIN_STPORT_MAX) + { + return -RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(PIN_STPIN(pin)); + if (irqindex < 0 || irqindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + + irqmap = &pin_irq_map[irqindex]; + + /* EXTI Line Config */ + GPIO_ConfigEXTILine(irqmap->exti_line, (PIN_NO(pin) * 11 + PIN_PORT(pin))); + + GPIO_InitStruct(&GPIO_InitStructure); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.Pin = PIN_STPIN(pin); + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_FAST; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_DOWN; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_DOWN; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + } + GPIO_InitPeripheral(PIN_STPORT(pin), &GPIO_InitStructure); + + EXTI_InitStructure.EXTI_Line = irqmap->exti_line; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + + NVIC_SetPriority(irqmap->irqno, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0)); + NVIC_EnableIRQ(irqmap->irqno); + pin_irq_enable_mask |= irqmap->pinbit; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(PIN_STPIN(pin)); + if (irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + pin_irq_enable_mask &= ~irqmap->pinbit; + + if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15)) + { + if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQ(irqmap->irqno); + } + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} + +static const struct rt_pin_ops _n32_pin_ops = +{ + n32_pin_mode, + n32_pin_write, + n32_pin_read, + n32_pin_attach_irq, + n32_pin_dettach_irq, + n32_pin_irq_enable, + n32_pin_get, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void N32_GPIO_EXTI_Callback(uint16_t line_num) +{ + if (pin_irq_hdr_tab[line_num].pin != -1 && EXTI_GetITStatus(line_num) != RESET) + { + /* Clear EXTI line pending bit */ + EXTI_ClrITPendBit(line_num); + + pin_irq_hdr(line_num); + } +} + +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE0); + rt_interrupt_leave(); +} + +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE1); + rt_interrupt_leave(); +} + +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE2); + rt_interrupt_leave(); +} + +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE3); + rt_interrupt_leave(); +} + +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE4); + rt_interrupt_leave(); +} + +void EXTI9_5_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE5); + N32_GPIO_EXTI_Callback(EXTI_LINE6); + N32_GPIO_EXTI_Callback(EXTI_LINE7); + N32_GPIO_EXTI_Callback(EXTI_LINE8); + N32_GPIO_EXTI_Callback(EXTI_LINE9); + rt_interrupt_leave(); +} + +void EXTI15_10_IRQHandler(void) +{ + rt_interrupt_enter(); + N32_GPIO_EXTI_Callback(EXTI_LINE10); + N32_GPIO_EXTI_Callback(EXTI_LINE11); + N32_GPIO_EXTI_Callback(EXTI_LINE12); + N32_GPIO_EXTI_Callback(EXTI_LINE13); + N32_GPIO_EXTI_Callback(EXTI_LINE14); + N32_GPIO_EXTI_Callback(EXTI_LINE15); + rt_interrupt_leave(); +} + +int rt_hw_pin_init(void) +{ +#if defined(SOC_SERIES_N32H7xx) +#if defined(AFIO) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_AFIO, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(EXTI) + RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_EXTI, ENABLE); +#endif + +#if defined(GPIOA) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOA, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOB) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOB, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOC) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOC, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOD) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOD, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOE) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOE, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOF) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOF, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOG) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOG, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOH) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOH, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOI) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOI, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOJ) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOJ, ENABLE); +#endif /* SOC_N32H78X */ +#endif + +#if defined(GPIOK) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE); +#if defined(SOC_N32H78X) + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOK, ENABLE); +#endif /* SOC_N32H78X */ +#endif +#endif /* defined(SOC_SERIES_N32H7xx) */ + + return rt_device_pin_register("pin", &_n32_pin_ops, RT_NULL); +} + +#endif /* BSP_USING_GPIO */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h new file mode 100644 index 0000000000..2b9d4f9abf --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __N32_PORT(port) GPIO##port##_BASE + + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__N32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) + + +struct pin_irq_map +{ + rt_uint16_t pinbit; + rt_uint16_t exti_line; + IRQn_Type irqno; +}; + +int rt_hw_pin_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c new file mode 100644 index 0000000000..a4d7d71950 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c @@ -0,0 +1,1474 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include +#include +#include +#include "drv_hard_i2c.h" +#include "drv_config.h" +#include + +#if defined(BSP_USING_HARD_I2C1) || defined(BSP_USING_HARD_I2C2) || defined(BSP_USING_HARD_I2C3) || defined(BSP_USING_HARD_I2C4) || defined(BSP_USING_HARD_I2C5) || \ + defined(BSP_USING_HARD_I2C6) || defined(BSP_USING_HARD_I2C7) || defined(BSP_USING_HARD_I2C8) || defined(BSP_USING_HARD_I2C9) || defined(BSP_USING_HARD_I2C10) + + +#define I2C_CTRL2_NBYTES_POS (16U) +#define MAX_NBYTE_SIZE (255U) + +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_START_READ (I2C_CTRL2_START | I2C_CTRL2_RWN) +#define I2C_START_WRITE (I2C_CTRL2_START) + +#define I2C_RELOAD_MODE (CTRL2_REFILL_ENABLE) +#define I2C_AUTOEND_MODE (CTRL2_AUTO_STOP) +#define I2C_SOFTEND_MODE (0x00000000U) + +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ +#define I2C_CTRL2_CLEAR (I2C_CTRL2_SADR | I2C_CTRL2_RWN | I2C_CTRL2_START | I2C_CTRL2_STOP | I2C_CTRL2_BYTECNT | I2C_CTRL2_REFILL | I2C_CTRL2_AUTOSTOP) + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c.hw" +#include + +static rt_bool_t first_valid_rx_isr = RT_FALSE; +static void i2c_master_ev_isr_handler_it(struct n32_i2c *drv_i2c); +static void i2c_master_ev_isr_handler_dma(struct n32_i2c *drv_i2c); + +enum +{ +#ifdef BSP_USING_HARD_I2C1 + I2C1_INDEX, +#endif /* BSP_USING_HARD_I2C1 */ +#ifdef BSP_USING_HARD_I2C2 + I2C2_INDEX, +#endif /* BSP_USING_HARD_I2C2 */ +#ifdef BSP_USING_HARD_I2C3 + I2C3_INDEX, +#endif /* BSP_USING_HARD_I2C3 */ +#ifdef BSP_USING_HARD_I2C4 + I2C4_INDEX, +#endif /* BSP_USING_HARD_I2C4 */ +#ifdef BSP_USING_HARD_I2C5 + I2C5_INDEX, +#endif /* BSP_USING_HARD_I2C5 */ +#ifdef BSP_USING_HARD_I2C6 + I2C6_INDEX, +#endif /* BSP_USING_HARD_I2C6 */ +#ifdef BSP_USING_HARD_I2C7 + I2C7_INDEX, +#endif /* BSP_USING_HARD_I2C7 */ +#ifdef BSP_USING_HARD_I2C8 + I2C8_INDEX, +#endif /* BSP_USING_HARD_I2C8 */ +#ifdef BSP_USING_HARD_I2C9 + I2C9_INDEX, +#endif /* BSP_USING_HARD_I2C9 */ +#ifdef BSP_USING_HARD_I2C10 + I2C10_INDEX, +#endif /* BSP_USING_HARD_I2C10 */ +}; + +static struct n32_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_HARD_I2C1 + I2C1_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C1 */ +#ifdef BSP_USING_HARD_I2C2 + I2C2_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C2 */ +#ifdef BSP_USING_HARD_I2C3 + I2C3_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C3 */ +#ifdef BSP_USING_HARD_I2C4 + I2C4_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C4 */ +#ifdef BSP_USING_HARD_I2C5 + I2C5_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C5 */ +#ifdef BSP_USING_HARD_I2C6 + I2C6_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C6 */ +#ifdef BSP_USING_HARD_I2C7 + I2C7_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C7 */ +#ifdef BSP_USING_HARD_I2C8 + I2C8_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C8 */ +#ifdef BSP_USING_HARD_I2C9 + I2C9_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C9 */ +#ifdef BSP_USING_HARD_I2C10 + I2C10_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C10 */ +}; + +static struct n32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; + +static rt_ssize_t n32_iic_transfer_by_dma(struct n32_i2c_config *config, uint8_t *pData, uint16_t Size, rt_bool_t is_rx) +{ + struct dma_config *dma_config; + + RT_ASSERT(config != RT_NULL); + RT_ASSERT(pData != RT_NULL); + + if (is_rx) + { + dma_config = config->dma_rx; + } + else + { + dma_config = config->dma_tx; + } + +#if defined(SOC_SERIES_N32H7xx) + /* Check whether DMA Channel is disable */ + if (DMA_ChannelIsEnabled(dma_config->Instance, dma_config->dma_channel)) + { + /* Disable DMA Channel */ + DMA_ChannelCmd(dma_config->Instance, dma_config->dma_channel, DISABLE); + } + + if (is_rx) + { + /* Sets the destination address of the specified channel */ + DMA_SetChannelDestinationAddress(dma_config->Instance, dma_config->dma_channel, (uint32_t *)pData); + } + else + { + /* Sets the source address of the specified channel */ + DMA_SetChannelSourceAddress(dma_config->Instance, dma_config->dma_channel, (uint32_t *)pData); + } + + /* Sets the block transfer size of the specified channel */ + DMA_SetChannelBlockSize(dma_config->Instance, dma_config->dma_channel, Size); + + /* Clear a DMA channel event status */ + DMA_ClearChannelEventStatus(dma_config->Instance, dma_config->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + + /* Enable transaction complete interrupt event */ + DMA_ChannelEventCmd(dma_config->Instance, dma_config->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE, ENABLE); + + /* Configure DMAMUX */ + DMAMUX_SetRequestID(DMAMUX1_ID, dma_config->dmamux_channel, dma_config->dmamux_request); + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(dma_config->Instance, dma_config->dma_channel, ENABLE); +#endif + + return Size; +} + + +static rt_err_t n32_i2c_dma_init(struct n32_i2c_config *config, rt_bool_t is_rx) +{ + struct dma_config *dma_config; + DMA_ChInitType DMA_ChInitStr; + + RT_ASSERT(config != RT_NULL); + +#if defined(SOC_SERIES_N32H7xx) + /* Enable DMAMUX clock */ + RCC_EnableAHB1PeriphClk1(RCC_AHB1_PERIPHEN_M7_DMAMUX1, ENABLE); + + /* DMA channel struct configuration */ + DMA_ChannelStructInit(&DMA_ChInitStr); + DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + + /* Read by DMA */ + if (is_rx) + { + dma_config = config->dma_rx; + + /* DMA clock enable */ + RCC_EnableAHB1PeriphClk3(dma_config->dma_rcc, ENABLE); + + /* DMA channel struct configuration */ + DMA_ChInitStr.SrcAddr = (uint32_t)&config->Instance->RDR; + DMA_ChInitStr.DstAddr = (uint32_t)RT_NULL; + DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; + DMA_ChInitStr.SrcHsInterface = dma_config->HsInterface; + } + /* Write by DMA */ + else + { + dma_config = config->dma_tx; + + /* DMA clock enable */ + RCC_EnableAHB1PeriphClk3(dma_config->dma_rcc, ENABLE); + + /* DMA channel struct configuration */ + DMA_ChInitStr.SrcAddr = (uint32_t) RT_NULL; + DMA_ChInitStr.DstAddr = (uint32_t)&config->Instance->WDR; + DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; + DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; + DMA_ChInitStr.DstHsInterface = dma_config->HsInterface; + } + + /* DMA controller must be enabled before initializing the channel */ + DMA_ControllerCmd(dma_config->Instance, ENABLE); + + /* Initialize the specified DMA channel */ + if (DMA_ChannelInit(dma_config->Instance, &DMA_ChInitStr, dma_config->dma_channel) != 0) + { + return -RT_ERROR; + } +#endif + + /* enable dma irq */ + NVIC_SetPriority(dma_config->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_EnableIRQ(dma_config->dma_irq); + + return RT_EOK; +} + +static rt_err_t n32_i2c_init(struct n32_i2c *i2c_drv) +{ + rt_err_t ret; + uint32_t BusTim_Reg; + I2C_InitType I2C_InitStructure; + RT_ASSERT(i2c_drv != RT_NULL); + + struct n32_i2c_config *cfg = i2c_drv->config; + + /* Enable I2C Clock */ + cfg->EnablePeriphClk(cfg->periph, ENABLE); + +#if defined(SOC_SERIES_N32H7xx) + /* Call I2C_Configuration() from an external file */ + I2C_Configuration(); + /* Disable IIC */ + I2C_Enable(cfg->Instance, DISABLE); + /* Get IIC BUSTIM Register value */ + BusTim_Reg = cfg->Instance->BUSTIM; + + if (BusTim_Reg == 0U) + { + /* IIC Kernal use default kernal clock */ + RCC_ConfigHse(RCC_HSE_ENABLE); + if (RCC_WaitHseStable() != SUCCESS) + { + return -RT_ERROR; + } + RCC_ConfigPll3(RCC_PLL_SRC_HSE, HSE_VALUE, 480000000, ENABLE); + RCC_ConfigPLL3CDivider(RCC_PLLC_DIV10); + /*Choose I2C1 ker clk source*/ + cfg->I2CKerClkSource(RCC_I2CKERCLK_SRC_PLL3C); + } +#endif + + /* Deinitializes the I2Cx peripheral registers to their default reset values */ + I2C_DeInit(cfg->Instance); + + I2C_InitStruct(&I2C_InitStructure); + I2C_InitStructure.Timing = ((BusTim_Reg != 0) ? BusTim_Reg : cfg->timing); + I2C_InitStructure.OwnAddress1 = 0x0; + I2C_InitStructure.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + I2C_InitStructure.DualAddressMode = I2C_DUALADDRESS_DISABLE; + I2C_InitStructure.OwnAddress2 = 0x0; + I2C_InitStructure.OwnAddress2Masks = I2C_ADDRESS2MASK_NONE; + I2C_InitStructure.GeneralCallMode = I2C_GENERALCALL_DISABLE; + I2C_InitStructure.NoStretchMode = I2C_NOSTRCH_DISABLE; + I2C_Init(cfg->Instance, &I2C_InitStructure); + + I2C_Enable(cfg->Instance, ENABLE); + +#if defined(SOC_SERIES_N32H7xx) + /* Configure Analogue filter */ + I2C_EnableAnalogFilter(cfg->Instance, ENABLE); + I2C_EnableSDAAnalogFilter(cfg->Instance, ENABLE); + I2C_EnableSCLAnalogFilter(cfg->Instance, ENABLE); + I2C_SetSCLAnalogFilterWidth(cfg->Instance, cfg->scl_af_width); + I2C_SetSDAAnalogFilterWidth(cfg->Instance, cfg->sda_af_width); + + /* Configure Digital filter */ + I2C_SetDigitalFilterWidth(cfg->Instance, cfg->df_width); +#endif /* defined(SOC_SERIES_N32H7xx) */ + + /* I2C2 DMA Init */ + if (i2c_drv->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) + { + ret = n32_i2c_dma_init(cfg, RT_TRUE); + RT_ASSERT(ret == RT_EOK); + } + + if (i2c_drv->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) + { + ret = n32_i2c_dma_init(cfg, RT_FALSE); + RT_ASSERT(ret == RT_EOK); + } + + /* Enable Event IRQ */ + NVIC_SetPriority(i2c_drv->config->evirq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 0)); + NVIC_EnableIRQ(i2c_drv->config->evirq_type); + + /* Enable Error IRQ */ + NVIC_SetPriority(i2c_drv->config->erirq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0)); + NVIC_EnableIRQ(i2c_drv->config->erirq_type); + + i2c_drv->transfer.state = I2C_READY; + + return RT_EOK; +} + +static rt_err_t n32_i2c_master_seq_receive_it(struct n32_i2c *i2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t setmask; + uint32_t xfermode; + + if (i2c->transfer.state == I2C_READY) + { + first_valid_rx_isr = RT_FALSE; + /* Set transfer parameters */ + i2c->transfer.state = I2C_BUSY_RX; + i2c->transfer.pBuffPtr = pData; + i2c->transfer.XferCount = Size; + i2c->transfer.XferOptions = XferOptions; + i2c->i2c_isr_callback = i2c_master_ev_isr_handler_it; + + /* If i2c->transfer.XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (Size > MAX_NBYTE_SIZE) + { + i2c->transfer.XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; // Use reload mode + } + else + { + i2c->transfer.XferSize = i2c->transfer.XferCount; + xfermode = i2c->transfer.XferOptions; + } + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)DevAddress & I2C_CTRL2_SADR) | (uint32_t)I2C_START_READ | (((uint32_t)i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)xfermode; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + I2C_ConfigInt(i2c->config->Instance, I2C_INT_ERR | I2C_INT_TFC | I2C_INT_STOP | I2C_INT_NACK | I2C_INT_RDR, ENABLE); + + return RT_EOK; + } + else + { + return -RT_EBUSY; + } +} + +static rt_err_t n32_i2c_master_seq_send_it(struct n32_i2c *i2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t setmask; + uint32_t xfermode; + + if (i2c->transfer.state == I2C_READY) + { + /* Set transfer parameters */ + i2c->transfer.state = I2C_BUSY_TX; + i2c->transfer.pBuffPtr = pData; + i2c->transfer.XferCount = Size; + i2c->transfer.XferOptions = XferOptions; + i2c->i2c_isr_callback = i2c_master_ev_isr_handler_it; + + /* If i2c->transfer.XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (Size > MAX_NBYTE_SIZE) + { + i2c->transfer.XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; // Use reload mode + } + else + { + i2c->transfer.XferSize = i2c->transfer.XferCount; + xfermode = i2c->transfer.XferOptions; + } + + I2C_ConfigInt(i2c->config->Instance, I2C_INT_ERR | I2C_INT_TFC | I2C_INT_STOP | I2C_INT_NACK | I2C_INT_WDR, ENABLE); + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)DevAddress & I2C_CTRL2_SADR) | (uint32_t)I2C_START_WRITE | (((uint32_t)i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)xfermode; + + /* Wait for bus idele */ + while ((i2c->config->Instance->STSINT & I2C_STSINT_BUSY) == I2C_STSINT_BUSY) + { + } + + /* Set IIC CTRL2 Register */ + MODIFY_REG(i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + return RT_EOK; + } + else + { + return -RT_EBUSY; + } +} + +static rt_err_t n32_i2c_master_seq_receive_dma(struct n32_i2c *i2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t setmask; + uint32_t xfermode; + + if (i2c->transfer.state == I2C_READY) + { + first_valid_rx_isr = RT_FALSE; + /* Set transfer parameters */ + i2c->transfer.state = I2C_BUSY_RX; + i2c->transfer.pBuffPtr = pData; + i2c->transfer.XferCount = Size; + i2c->transfer.XferOptions = XferOptions; + i2c->i2c_isr_callback = i2c_master_ev_isr_handler_dma; + + /* If i2c->transfer.XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (Size > MAX_NBYTE_SIZE) + { + i2c->transfer.XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; // Use reload mode + } + else + { + i2c->transfer.XferSize = i2c->transfer.XferCount; + xfermode = i2c->transfer.XferOptions; + } + + if (i2c->transfer.XferSize > 0U) + { + n32_iic_transfer_by_dma(i2c->config, i2c->transfer.pBuffPtr, i2c->transfer.XferSize, RT_TRUE); + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)DevAddress & I2C_CTRL2_SADR) | (uint32_t)I2C_START_READ | (((uint32_t)i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)xfermode; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + /* Update XferCount value */ + i2c->transfer.XferCount -= i2c->transfer.XferSize; + + /* Enable ERR and NACK interrupts */ + i2c->config->Instance->CTRL1 |= (I2C_CTRL1_ERRIE | I2C_CTRL1_NAKIE); + + /* Enable DMA Request */ + i2c->config->Instance->CTRL1 |= I2C_CTRL1_DMARDEN; + } + else + { + i2c->i2c_isr_callback = i2c_master_ev_isr_handler_it; + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)DevAddress & I2C_CTRL2_SADR) | (uint32_t)I2C_START_READ | (((uint32_t)i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)I2C_AUTOEND_MODE; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + i2c->config->Instance->CTRL1 |= (I2C_CTRL1_ERRIE | I2C_CTRL1_TFCIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_WDRIE); + } + + return RT_EOK; + } + else + { + return -RT_EBUSY; + } +} + +static rt_err_t n32_i2c_master_seq_send_dma(struct n32_i2c *i2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t setmask; + uint32_t xfermode; + + if (i2c->transfer.state == I2C_READY) + { + /* Set transfer parameters */ + i2c->transfer.state = I2C_BUSY_TX; + i2c->transfer.pBuffPtr = pData; + i2c->transfer.XferCount = Size; + i2c->transfer.XferOptions = XferOptions; + i2c->i2c_isr_callback = i2c_master_ev_isr_handler_dma; + + /* If i2c->transfer.XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (Size > MAX_NBYTE_SIZE) + { + i2c->transfer.XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; // Use reload mode + } + else + { + i2c->transfer.XferSize = i2c->transfer.XferCount; + xfermode = i2c->transfer.XferOptions; + } + + if (i2c->transfer.XferSize > 0U) + { + n32_iic_transfer_by_dma(i2c->config, i2c->transfer.pBuffPtr, i2c->transfer.XferSize, RT_FALSE); + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)DevAddress & I2C_CTRL2_SADR) | (uint32_t)I2C_START_WRITE | (((uint32_t)i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)xfermode; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + /* Update XferCount value */ + i2c->transfer.XferCount -= i2c->transfer.XferSize; + + /* Enable ERR and NACK interrupts */ + i2c->config->Instance->CTRL1 |= (I2C_CTRL1_ERRIE | I2C_CTRL1_NAKIE); + + /* Enable DMA Request */ + i2c->config->Instance->CTRL1 |= I2C_CTRL1_DMAWREN; + } + else + { + i2c->i2c_isr_callback = i2c_master_ev_isr_handler_it; + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)DevAddress & I2C_CTRL2_SADR) | (uint32_t)I2C_START_WRITE | (((uint32_t)i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)I2C_AUTOEND_MODE; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + i2c->config->Instance->CTRL1 |= (I2C_CTRL1_ERRIE | I2C_CTRL1_TFCIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_WDRIE); + } + + return RT_EOK; + } + else + { + return -RT_EBUSY; + } +} + +static rt_err_t n32_i2c_configure(struct rt_i2c_bus_device *bus) +{ + RT_ASSERT(RT_NULL != bus); + struct n32_i2c *i2c_drv = rt_container_of(bus, struct n32_i2c, i2c_bus); + + return n32_i2c_init(i2c_drv); +} + +static rt_ssize_t n32_i2c_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ +#define DMA_TRANS_MIN_LEN 2 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ +#define TRANS_TIMEOUT_PERSEC 8 /* per ms will trans nums bytes */ + + rt_int32_t i, ret; + struct rt_i2c_msg *msg = msgs; + struct rt_i2c_msg *next_msg = 0; + struct n32_i2c *i2c_obj; + uint32_t mode = 0; + uint8_t next_flag = 0; + struct rt_completion *completion; + rt_uint32_t timeout; + if (num == 0) + { + return 0; + } + RT_ASSERT((msgs != RT_NULL) && (bus != RT_NULL)); + + i2c_obj = rt_container_of(bus, struct n32_i2c, i2c_bus); + completion = &i2c_obj->completion; + + LOG_D("xfer start %d mags", num); + for (i = 0; i < (num - 1); i++) + { + mode = 0; + msg = &msgs[i]; + LOG_D("xfer msgs[%d] addr=0x%2x buf=0x%x len= 0x%x flags= 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); + next_msg = &msgs[i + 1]; + next_flag = next_msg->flags; + + timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; + if (next_flag & RT_I2C_NO_START) + { + if ((next_flag & RT_I2C_RD) == (msg->flags & RT_I2C_RD)) + { + /* The same mode, can use no start */ + mode = I2C_FIRST_AND_NEXT_FRAME; + } + else + { + /* Not allowed to use no start, sending address is required when changing direction, user setting error */ + LOG_W("user set flags error msg[%d] flags RT_I2C_NO_START has canceled", i + 1); + mode = I2C_LAST_FRAME_NO_STOP; + } + } + else + { + mode = I2C_LAST_FRAME_NO_STOP; + } + + if (msg->flags & RT_I2C_RD) + { + LOG_D("xfer rec msgs[%d] i2c mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" + : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : "nuknown mode"); + if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = n32_i2c_master_seq_receive_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + else + { + ret = n32_i2c_master_seq_receive_it(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + if (ret != RT_EOK) + { + LOG_E("[%s:%d]I2C Read error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("receive time out"); + goto out; + + } + } + else + { + LOG_D("xfer trans msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" + : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : "nuknown mode"); + if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = n32_i2c_master_seq_send_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + else + { + ret = n32_i2c_master_seq_send_it(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]I2C Write error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("transmit time out"); + goto out; + } + } + LOG_D("xfer next msgs[%d] addr=0x%2x buf= 0x%x len= 0x%x flags = 0x%x\r\n", i + 1, next_msg->addr, next_msg->buf, next_msg->len, next_msg->flags); + } + + /* last msg */ + msg = &msgs[i]; + timeout = msg->len / TRANS_TIMEOUT_PERSEC + 2; + + if (msg->flags & RT_I2C_NO_STOP) + mode = I2C_LAST_FRAME_NO_STOP; + else + mode = I2C_LAST_FRAME; + + LOG_D("xfer last msgs[%d] addr=0x%2x buf= 0x%x len= 0x%x flags = 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); + if (msg->flags & RT_I2C_RD) + { + LOG_D("xfer rec msgs[%d] hal mode=%s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" + : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : "nuknown mode"); + if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = n32_i2c_master_seq_receive_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + else + { + uint32_t itflags = READ_REG(i2c_obj->config->Instance->STSINT); + ret = n32_i2c_master_seq_receive_it(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]I2C Read error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("receive time out"); + goto out; + } + } + else + { + LOG_D("xfer trans msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" + : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" + : "nuknown mode"); + if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) + { + ret = n32_i2c_master_seq_send_dma(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + else + { + ret = n32_i2c_master_seq_send_it(i2c_obj, (msg->addr << 1), msg->buf, msg->len, mode); + } + if (ret != RT_EOK) + { + LOG_D("[%s:%d]I2C Write error(%d)!\n", __func__, __LINE__, ret); + goto out; + } + if (rt_completion_wait(completion, timeout) != RT_EOK) + { + LOG_D("transmit time out"); + goto out; + + } + } + LOG_D("xfer end %d mags\r\n", num); + return num; + +out: + return (i - 1); +} + + +static const struct rt_i2c_bus_device_ops n32_i2c_ops = +{ + .master_xfer = n32_i2c_master_xfer, + RT_NULL, + RT_NULL +}; + + +static void n32_get_dma_info(void) +{ +#ifdef BSP_I2C1_RX_USING_DMA + i2c_objs[I2C1_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C1_dma_rx = I2C1_RX_DMA_CONFIG; + i2c_config[I2C1_INDEX].dma_rx = &I2C1_dma_rx; +#endif /* BSP_I2C1_RX_USING_DMA */ +#ifdef BSP_I2C1_TX_USING_DMA + i2c_objs[I2C1_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C1_dma_tx = I2C1_TX_DMA_CONFIG; + i2c_config[I2C1_INDEX].dma_tx = &I2C1_dma_tx; +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA + i2c_objs[I2C2_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C2_dma_rx = I2C2_RX_DMA_CONFIG; + i2c_config[I2C2_INDEX].dma_rx = &I2C2_dma_rx; +#endif /* BSP_I2C2_RX_USING_DMA */ +#ifdef BSP_I2C2_TX_USING_DMA + i2c_objs[I2C2_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C2_dma_tx = I2C2_TX_DMA_CONFIG; + i2c_config[I2C2_INDEX].dma_tx = &I2C2_dma_tx; +#endif /* BSP_I2C2_TX_USING_DMA */ +#ifdef BSP_I2C3_RX_USING_DMA + i2c_objs[I2C3_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C3_dma_rx = I2C3_RX_DMA_CONFIG; + i2c_config[I2C3_INDEX].dma_rx = &I2C3_dma_rx; +#endif /* BSP_I2C3_RX_USING_DMA */ +#ifdef BSP_I2C3_TX_USING_DMA + i2c_objs[I2C3_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C3_dma_tx = I2C3_TX_DMA_CONFIG; + i2c_config[I2C3_INDEX].dma_tx = &I2C3_dma_tx; +#endif /* BSP_I2C3_TX_USING_DMA */ +#ifdef BSP_I2C4_RX_USING_DMA + i2c_objs[I2C4_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C4_dma_rx = I2C4_RX_DMA_CONFIG; + i2c_config[I2C4_INDEX].dma_rx = &I2C4_dma_rx; +#endif /* BSP_I2C4_RX_USING_DMA */ +#ifdef BSP_I2C4_TX_USING_DMA + i2c_objs[I2C4_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C4_dma_tx = I2C4_TX_DMA_CONFIG; + i2c_config[I2C4_INDEX].dma_tx = &I2C4_dma_tx; +#endif /* BSP_I2C4_TX_USING_DMA */ +#ifdef BSP_I2C5_RX_USING_DMA + i2c_objs[I2C5_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C5_dma_rx = I2C5_RX_DMA_CONFIG; + i2c_config[I2C5_INDEX].dma_rx = &I2C5_dma_rx; +#endif /* BSP_I2C5_RX_USING_DMA */ +#ifdef BSP_I2C5_TX_USING_DMA + i2c_objs[I2C5_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C5_dma_tx = I2C5_TX_DMA_CONFIG; + i2c_config[I2C5_INDEX].dma_tx = &I2C5_dma_tx; +#endif /* BSP_I2C5_TX_USING_DMA */ +#ifdef BSP_I2C6_RX_USING_DMA + i2c_objs[I2C6_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C6_dma_rx = I2C6_RX_DMA_CONFIG; + i2c_config[I2C6_INDEX].dma_rx = &I2C6_dma_rx; +#endif /* BSP_I2C6_RX_USING_DMA */ +#ifdef BSP_I2C6_TX_USING_DMA + i2c_objs[I2C6_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C6_dma_tx = I2C6_TX_DMA_CONFIG; + i2c_config[I2C6_INDEX].dma_tx = &I2C6_dma_tx; +#endif /* BSP_I2C6_TX_USING_DMA */ +#ifdef BSP_I2C7_RX_USING_DMA + i2c_objs[I2C7_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C7_dma_rx = I2C7_RX_DMA_CONFIG; + i2c_config[I2C7_INDEX].dma_rx = &I2C7_dma_rx; +#endif /* BSP_I2C7_RX_USING_DMA */ +#ifdef BSP_I2C7_TX_USING_DMA + i2c_objs[I2C7_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C7_dma_tx = I2C7_TX_DMA_CONFIG; + i2c_config[I2C7_INDEX].dma_tx = &I2C7_dma_tx; +#endif /* BSP_I2C7_TX_USING_DMA */ +#ifdef BSP_I2C8_RX_USING_DMA + i2c_objs[I2C8_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C8_dma_rx = I2C8_RX_DMA_CONFIG; + i2c_config[I2C8_INDEX].dma_rx = &I2C8_dma_rx; +#endif /* BSP_I2C8_RX_USING_DMA */ +#ifdef BSP_I2C8_TX_USING_DMA + i2c_objs[I2C8_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C8_dma_tx = I2C8_TX_DMA_CONFIG; + i2c_config[I2C8_INDEX].dma_tx = &I2C8_dma_tx; +#endif /* BSP_I2C8_TX_USING_DMA */ +#ifdef BSP_I2C9_RX_USING_DMA + i2c_objs[I2C9_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C9_dma_rx = I2C9_RX_DMA_CONFIG; + i2c_config[I2C9_INDEX].dma_rx = &I2C9_dma_rx; +#endif /* BSP_I2C9_RX_USING_DMA */ +#ifdef BSP_I2C9_TX_USING_DMA + i2c_objs[I2C9_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C9_dma_tx = I2C9_TX_DMA_CONFIG; + i2c_config[I2C9_INDEX].dma_tx = &I2C9_dma_tx; +#endif /* BSP_I2C9_TX_USING_DMA */ +#ifdef BSP_I2C10_RX_USING_DMA + i2c_objs[I2C10_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + static struct dma_config I2C10_dma_rx = I2C10_RX_DMA_CONFIG; + i2c_config[I2C10_INDEX].dma_rx = &I2C10_dma_rx; +#endif /* BSP_I2C10_RX_USING_DMA */ +#ifdef BSP_I2C10_TX_USING_DMA + i2c_objs[I2C10_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + static struct dma_config I2C10_dma_tx = I2C10_TX_DMA_CONFIG; + i2c_config[I2C10_INDEX].dma_tx = &I2C10_dma_tx; +#endif /* BSP_I2C10_TX_USING_DMA */ +} + + +static void i2c_flush_wdr(I2C_Module *Instance) +{ + /* If a pending WRAVL flag is set, Write a dummy data in WDR to clear it */ + if ((((Instance->STSINT) & I2C_STSINT_WRAVL) == I2C_STSINT_WRAVL) ? SET : RESET) + { + Instance->WDR = 0x00U; + } + + /* Flush WDR register if not empty */ + if ((((Instance->STSINT) & I2C_STSINT_WRE) == I2C_STSINT_WRE) ? SET : RESET) + { + Instance->STSINT |= I2C_STSINT_WRE; + } +} + +static void i2c_it_error_handler(struct n32_i2c *drv_i2c, uint32_t itflags) +{ + uint32_t setmask; + I2C_StateTypeDef tmpstate = drv_i2c->transfer.state; + + drv_i2c->transfer.pBuffPtr = RT_NULL; + drv_i2c->transfer.XferCount = 0; + + setmask = I2C_CTRL1_TFCIE | I2C_CTRL1_WDRIE | I2C_CTRL1_RDRIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_ERRIE; + + /* Disable all interrupts */ + drv_i2c->config->Instance->CTRL1 &= (~(setmask)); + + drv_i2c->transfer.state = I2C_READY; + drv_i2c->i2c_isr_callback = RT_NULL; + + /* Abort DMA TX transfer */ + if ((tmpstate == I2C_BUSY_TX) && (drv_i2c->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) == I2C_USING_TX_DMA_FLAG) + { + if ((drv_i2c->config->Instance->CTRL1 & I2C_CTRL1_DMAWREN) == I2C_CTRL1_DMAWREN) + { + drv_i2c->config->Instance->CTRL1 &= ~I2C_CTRL1_DMAWREN; + } + + DMA_ChannelCmd(drv_i2c->config->dma_tx->Instance, drv_i2c->config->dma_tx->dma_channel, DISABLE); + + DMA_ChannelEventCmd(drv_i2c->config->dma_tx->Instance, drv_i2c->config->dma_tx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE, DISABLE); + + DMA_ClearChannelEventStatus(drv_i2c->config->dma_tx->Instance, drv_i2c->config->dma_tx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + + /* Abort DMA RX transfer */ + if ((tmpstate == I2C_BUSY_RX) && (drv_i2c->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) == I2C_USING_RX_DMA_FLAG) + { + if ((drv_i2c->config->Instance->CTRL1 & I2C_CTRL1_DMARDEN) == I2C_CTRL1_DMARDEN) + { + drv_i2c->config->Instance->CTRL1 &= ~I2C_CTRL1_DMARDEN; + } + + DMA_ChannelCmd(drv_i2c->config->dma_rx->Instance, drv_i2c->config->dma_rx->dma_channel, DISABLE); + + DMA_ChannelEventCmd(drv_i2c->config->dma_rx->Instance, drv_i2c->config->dma_rx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE, DISABLE); + + DMA_ClearChannelEventStatus(drv_i2c->config->dma_rx->Instance, drv_i2c->config->dma_rx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + + if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET) || + ((((itflags & I2C_STSINT_BSER) == I2C_STSINT_BSER) ? SET : RESET) != RESET)) + { + /* Send stop signal to prevent bus lock-up */ + LOG_D("I2C NACK Error or BUS Error now stoped"); + drv_i2c->config->Instance->CTRL1 |= I2C_CTRL1_STOPIE; + } +} + +static void i2c_it_master_complete(struct n32_i2c *drv_i2c, uint32_t itflags) +{ + uint32_t setmask; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_STOPCLR; + + /* I2C Write */ + if (drv_i2c->transfer.state == I2C_BUSY_TX) + { + setmask = I2C_CTRL1_TFCIE | I2C_CTRL1_WDRIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_ERRIE; + + /* Disable interrupt */ + drv_i2c->config->Instance->CTRL1 &= (~(setmask)); + } + /* I2C Read */ + if (drv_i2c->transfer.state == I2C_BUSY_RX) + { + setmask = I2C_CTRL1_TFCIE | I2C_CTRL1_RDRIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_ERRIE; + + /* Disable interrupt */ + drv_i2c->config->Instance->CTRL1 &= (~(setmask)); + } + + /* Clear CTRL2 */ + drv_i2c->config->Instance->CTRL2 &= (~(I2C_CTRL2_CLEAR | I2C_CTRL2_HDR10)); + + drv_i2c->i2c_isr_callback = RT_NULL; + + if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET)) + { + /* Clear NACK Flag */ + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_NAKCLR; + } + + /* Fetch Last receive data */ + if (((((itflags & I2C_STSINT_RDAVL) == I2C_STSINT_RDAVL) ? SET : RESET) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)drv_i2c->config->Instance->RDR; + RT_UNUSED(tmpreg); + } + + i2c_flush_wdr(drv_i2c->config->Instance); + + drv_i2c->transfer.state = I2C_READY; + rt_completion_done(&drv_i2c->completion); +} + +static void i2c_it_completion_done(struct n32_i2c *drv_i2c) +{ + uint32_t setmask; + + /* I2C Write */ + if (drv_i2c->transfer.state == I2C_BUSY_TX) + { + drv_i2c->transfer.state = I2C_READY; + drv_i2c->i2c_isr_callback = RT_NULL; + + setmask = I2C_CTRL1_TFCIE | I2C_CTRL1_WDRIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_ERRIE; + + /* Disable interrupt */ + drv_i2c->config->Instance->CTRL1 &= (~(setmask)); + + rt_completion_done(&drv_i2c->completion); + } + /* I2C Read */ + if (drv_i2c->transfer.state == I2C_BUSY_RX) + { + drv_i2c->transfer.state = I2C_READY; + drv_i2c->i2c_isr_callback = RT_NULL; + + setmask = I2C_CTRL1_TFCIE | I2C_CTRL1_RDRIE | I2C_CTRL1_STOPIE | I2C_CTRL1_NAKIE | I2C_CTRL1_ERRIE; + + /* Disable interrupt */ + drv_i2c->config->Instance->CTRL1 &= (~(setmask)); + + rt_completion_done(&drv_i2c->completion); + } +} + +static void i2c_master_ev_isr_handler_it(struct n32_i2c *drv_i2c) +{ + uint16_t devaddress; + uint32_t setmask; + /* Get current IT Flags and IT sources value */ + volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); + volatile uint32_t itsources = READ_REG(drv_i2c->config->Instance->CTRL1); + + /* It takes more than 100 microseconds to clear the TC flag after starting, so wait for the TC flag to clear */ + if (drv_i2c->transfer.state == I2C_BUSY_RX && first_valid_rx_isr != RT_TRUE) + { + if ((itflags & I2C_STSINT_TFC) == I2C_STSINT_TFC) + { + return; + } + else + { + first_valid_rx_isr = RT_TRUE; + } + } + + if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_NAKIE) == I2C_CTRL1_NAKIE) ? SET : RESET) != RESET)) + { + /* Clear Not Acknowledge received flag */ + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_NAKCLR; + + /* Flush WDR register */ + i2c_flush_wdr(drv_i2c->config->Instance); + } + else if (((((itflags & I2C_STSINT_RDAVL) == I2C_STSINT_RDAVL) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_RDRIE) == I2C_CTRL1_RDRIE) ? SET : RESET) != RESET)) + { + /* Remove RDAVL flag as read done */ + itflags &= ~I2C_STSINT_RDAVL; + + /* Read data from RDR */ + *drv_i2c->transfer.pBuffPtr = (uint8_t)drv_i2c->config->Instance->RDR; + + /* Increment Buffer pointer */ + drv_i2c->transfer.pBuffPtr++; + + drv_i2c->transfer.XferSize--; + drv_i2c->transfer.XferCount--; + } + else if (((((itflags & I2C_STSINT_WRAVL) == I2C_STSINT_WRAVL) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_WDRIE) == I2C_CTRL1_WDRIE) ? SET : RESET) != RESET)) + { + /* Write data to WDR */ + drv_i2c->config->Instance->WDR = *drv_i2c->transfer.pBuffPtr; + + /* Increment Buffer pointer */ + drv_i2c->transfer.pBuffPtr++; + + drv_i2c->transfer.XferSize--; + drv_i2c->transfer.XferCount--; + } + else if (((((itflags & I2C_STSINT_TFCR) == I2C_STSINT_TFCR) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_TFCIE) == I2C_CTRL1_TFCIE) ? SET : RESET) != RESET)) + { + if ((drv_i2c->transfer.XferCount != 0U) && (drv_i2c->transfer.XferSize == 0U)) + { + devaddress = (uint16_t)(drv_i2c->config->Instance->CTRL2 & I2C_CTRL2_SADR); + + if (drv_i2c->transfer.XferCount > MAX_NBYTE_SIZE) + { + drv_i2c->transfer.XferSize = MAX_NBYTE_SIZE; + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)devaddress & I2C_CTRL2_SADR) | (uint32_t)I2C_NO_STARTSTOP | (((uint32_t)drv_i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)I2C_RELOAD_MODE; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(drv_i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + } + else + { + drv_i2c->transfer.XferSize = drv_i2c->transfer.XferCount; + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)devaddress & I2C_CTRL2_SADR) | (uint32_t)I2C_NO_STARTSTOP | (((uint32_t)drv_i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)drv_i2c->transfer.XferOptions; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(drv_i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + } + } + else + { + if (((drv_i2c->config->Instance->CTRL2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)) + { + i2c_it_completion_done(drv_i2c); + } + else + { + i2c_it_error_handler(drv_i2c, itflags); + } + } + } + else if (((((itflags & I2C_STSINT_TFC) == I2C_STSINT_TFC) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_TFCIE) == I2C_CTRL1_TFCIE) ? SET : RESET) != RESET)) + { + if (drv_i2c->transfer.XferCount == 0U) + { + if (((drv_i2c->config->Instance->CTRL2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)) + { + i2c_it_completion_done(drv_i2c); + } + } + else + { + i2c_it_error_handler(drv_i2c, itflags); + } + } + else + { + /* Nothing to do */ + } + + if (((((itflags & I2C_STSINT_STOPF) == I2C_STSINT_STOPF) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_STOPIE) == I2C_CTRL1_STOPIE) ? SET : RESET) != RESET)) + { + i2c_it_master_complete(drv_i2c, itflags); + } +} + +static void i2c_master_ev_isr_handler_dma(struct n32_i2c *drv_i2c) +{ + uint16_t devaddress; + uint32_t setmask; + uint32_t xfermode; + /* Get current IT Flags and IT sources value */ + volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); + volatile uint32_t itsources = READ_REG(drv_i2c->config->Instance->CTRL1); + + if (((((itflags & I2C_STSINT_NAKF) == I2C_STSINT_NAKF) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_NAKIE) == I2C_CTRL1_NAKIE) ? SET : RESET) != RESET)) + { + /* Clear Not Acknowledge received flag */ + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_NAKCLR; + + setmask = I2C_CTRL1_TFCIE | I2C_CTRL1_STOPIE; + + /* Enable STOP interrupts */ + drv_i2c->config->Instance->CTRL1 |= setmask; + + /* Flush WDR register */ + i2c_flush_wdr(drv_i2c->config->Instance); + } + else if (((((itflags & I2C_STSINT_TFCR) == I2C_STSINT_TFCR) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_TFCIE) == I2C_CTRL1_TFCIE) ? SET : RESET) != RESET)) + { + /* Disable TC interrupt */ + drv_i2c->config->Instance->CTRL1 &= ~I2C_CTRL1_TFCIE; + + if (drv_i2c->transfer.XferCount != 0U) + { + devaddress = (uint16_t)(drv_i2c->config->Instance->CTRL2 & I2C_CTRL2_SADR); + + /* Prepare the new XferSize to transfer */ + if (drv_i2c->transfer.XferCount > MAX_NBYTE_SIZE) + { + drv_i2c->transfer.XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + drv_i2c->transfer.XferSize = drv_i2c->transfer.XferCount; + xfermode = drv_i2c->transfer.XferOptions; + } + + /* Slave address | Transfer direction | START generation | STOP generation | Number of bytes | NBYTES reload mode | Automatic end mode */ + setmask = ((uint32_t)devaddress & I2C_CTRL2_SADR) | (uint32_t)I2C_NO_STARTSTOP | (((uint32_t)drv_i2c->transfer.XferSize << I2C_CTRL2_NBYTES_POS) & I2C_CTRL2_BYTECNT) | (uint32_t)xfermode; + + /* Set IIC CTRL2 Register */ + MODIFY_REG(drv_i2c->config->Instance->CTRL2, I2C_CTRL2_CLEAR, (uint32_t)setmask); + + /* Update XferCount value */ + drv_i2c->transfer.XferCount -= drv_i2c->transfer.XferSize; + + /* Enable DMA Request */ + if (drv_i2c->transfer.state == I2C_BUSY_TX) + { + drv_i2c->config->Instance->CTRL1 |= I2C_CTRL1_DMAWREN; + } + if (drv_i2c->transfer.state == I2C_BUSY_RX) + { + drv_i2c->config->Instance->CTRL1 |= I2C_CTRL1_DMARDEN; + } + } + else + { + if (((drv_i2c->config->Instance->CTRL2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)) + { + i2c_it_completion_done(drv_i2c); + } + else + { + i2c_it_error_handler(drv_i2c, itflags); + } + } + } + else if (((((itflags & I2C_STSINT_TFC) == I2C_STSINT_TFC) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_TFCIE) == I2C_CTRL1_TFCIE) ? SET : RESET) != RESET)) + { + if (drv_i2c->transfer.XferCount == 0U) + { + if (((drv_i2c->config->Instance->CTRL2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)) + { + i2c_it_completion_done(drv_i2c); + } + } + else + { + i2c_it_error_handler(drv_i2c, itflags); + } + } + else if (((((itflags & I2C_STSINT_STOPF) == I2C_STSINT_STOPF) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_STOPIE) == I2C_CTRL1_STOPIE) ? SET : RESET) != RESET)) + { + i2c_it_master_complete(drv_i2c, itflags); + } + else + { + /* Nothing to do */ + } +} + +static void i2c_master_er_isr_handler(struct n32_i2c *drv_i2c) +{ + uint32_t tmperror = 0; + volatile uint32_t itflags = READ_REG(drv_i2c->config->Instance->STSINT); + volatile uint32_t itsources = READ_REG(drv_i2c->config->Instance->CTRL1); + + /* I2C Bus error interrupt occurred */ + if (((((itflags & I2C_STSINT_BSER) == I2C_STSINT_BSER) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + { + tmperror |= I2C_STSINT_BSER; + + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_BSERCLR; + } + + /* I2C Over-Run/Under-Run interrupt occurred */ + if (((((itflags & I2C_STSINT_OVF) == I2C_STSINT_OVF) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + { + tmperror |= I2C_STSINT_OVF; + + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_OVFCLR; + } + + /* I2C Arbitration Loss error interrupt occurred */ + if (((((itflags & I2C_STSINT_ABLO) == I2C_STSINT_ABLO) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + { + tmperror |= I2C_STSINT_ABLO; + + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_ABLOCLR; + } + + /* I2C PEC error interrupt occurred */ + if (((((itflags & I2C_STSINT_CRCERR) == I2C_STSINT_CRCERR) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + { + tmperror |= I2C_STSINT_CRCERR; + + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_CRCCLR; + } + + /* I2C PEC error interrupt occurred */ + if (((((itflags & I2C_STSINT_TMOUT) == I2C_STSINT_TMOUT) ? SET : RESET) != RESET) && + ((((itsources & I2C_CTRL1_ERRIE) == I2C_CTRL1_ERRIE) ? SET : RESET) != RESET)) + { + tmperror |= I2C_STSINT_TMOUT; + + drv_i2c->config->Instance->INTCLR = I2C_INTCLR_TMOUTCLR; + } + + if ((tmperror & (I2C_STSINT_BSER | I2C_STSINT_OVF | I2C_STSINT_ABLO | I2C_STSINT_CRCERR | I2C_STSINT_TMOUT)) != 0) + { + i2c_it_error_handler(drv_i2c, itflags); + } +} + +static void i2c_master_ev_isr_handler(struct n32_i2c *drv_i2c) +{ + if (drv_i2c->i2c_isr_callback != RT_NULL) + { + drv_i2c->i2c_isr_callback(drv_i2c); + } +} + + +#if defined(BSP_I2C1_RX_USING_DMA) || defined(BSP_I2C2_RX_USING_DMA) || defined(BSP_I2C3_RX_USING_DMA) || defined(BSP_I2C4_RX_USING_DMA) || defined(BSP_I2C5_RX_USING_DMA) || \ + defined(BSP_I2C6_RX_USING_DMA) || defined(BSP_I2C7_RX_USING_DMA) || defined(BSP_I2C8_RX_USING_DMA) || defined(BSP_I2C9_RX_USING_DMA) || defined(BSP_I2C10_RX_USING_DMA) +static void i2c_master_dma_receive_isr_handler(struct n32_i2c *drv_i2c) +{ +#if defined(SOC_SERIES_N32H7xx) + if (DMA_GetCombinedStatus(drv_i2c->config->dma_rx->Instance)) + { + if (DMA_GetChannelIntBlockStatus(drv_i2c->config->dma_rx->Instance, drv_i2c->config->dma_rx->dma_channel) == SET) + { + /* Disable DMA Request */ + drv_i2c->config->Instance->CTRL1 &= (~I2C_CTRL1_DMARDEN); + + /* If last transfer, enable STOP interrupt */ + if (drv_i2c->transfer.XferCount == 0U) + { + /* Enable interrupt */ + drv_i2c->config->Instance->CTRL1 |= (I2C_CTRL1_TFCIE | I2C_CTRL1_STOPIE); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + drv_i2c->transfer.pBuffPtr += drv_i2c->transfer.XferSize; + + /* Set the XferSize to transfer */ + if (drv_i2c->transfer.XferCount > MAX_NBYTE_SIZE) + { + drv_i2c->transfer.XferSize = MAX_NBYTE_SIZE; + } + else + { + drv_i2c->transfer.XferSize = drv_i2c->transfer.XferCount; + } + + n32_iic_transfer_by_dma(drv_i2c->config, drv_i2c->transfer.pBuffPtr, drv_i2c->transfer.XferSize, RT_TRUE); + + /* Enable TC interrupts */ + drv_i2c->config->Instance->CTRL1 |= I2C_CTRL1_TFCIE; + } + + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(drv_i2c->config->dma_rx->Instance, drv_i2c->config->dma_rx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + } +#endif +} +#endif + +#if defined(BSP_I2C1_TX_USING_DMA) || defined(BSP_I2C2_TX_USING_DMA) || defined(BSP_I2C3_TX_USING_DMA) || defined(BSP_I2C4_TX_USING_DMA) || defined(BSP_I2C5_TX_USING_DMA) || \ + defined(BSP_I2C6_TX_USING_DMA) || defined(BSP_I2C7_TX_USING_DMA) || defined(BSP_I2C8_TX_USING_DMA) || defined(BSP_I2C9_TX_USING_DMA) || defined(BSP_I2C10_TX_USING_DMA) +static void i2c_master_dma_send_isr_handler(struct n32_i2c *drv_i2c) +{ +#if defined(SOC_SERIES_N32H7xx) + if (DMA_GetCombinedStatus(drv_i2c->config->dma_tx->Instance)) + { + if (DMA_GetChannelIntBlockStatus(drv_i2c->config->dma_tx->Instance, drv_i2c->config->dma_tx->dma_channel) == SET) + { + /* Disable DMA Request */ + drv_i2c->config->Instance->CTRL1 &= (~I2C_CTRL1_DMAWREN); + + /* If last transfer, enable STOP interrupt */ + if (drv_i2c->transfer.XferCount == 0U) + { + /* Enable interrupt */ + drv_i2c->config->Instance->CTRL1 |= (I2C_CTRL1_TFCIE | I2C_CTRL1_STOPIE); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + drv_i2c->transfer.pBuffPtr += drv_i2c->transfer.XferSize; + + /* Set the XferSize to transfer */ + if (drv_i2c->transfer.XferCount > MAX_NBYTE_SIZE) + { + drv_i2c->transfer.XferSize = MAX_NBYTE_SIZE; + } + else + { + drv_i2c->transfer.XferSize = drv_i2c->transfer.XferCount; + } + + n32_iic_transfer_by_dma(drv_i2c->config, drv_i2c->transfer.pBuffPtr, drv_i2c->transfer.XferSize, RT_TRUE); + + /* Enable TC interrupts */ + drv_i2c->config->Instance->CTRL1 |= I2C_CTRL1_TFCIE; + } + + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(drv_i2c->config->dma_tx->Instance, drv_i2c->config->dma_tx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + } +#endif +} +#endif + +#ifdef BSP_USING_HARD_I2C1 +/** + * @brief This function handles I2C2 event interrupt. + */ +void I2C1_EV_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_master_ev_isr_handler(&i2c_objs[I2C1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +/** + * @brief This function handles I2C2 error interrupt. + */ +void I2C1_ER_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_master_er_isr_handler(&i2c_objs[I2C1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(BSP_I2C1_RX_USING_DMA) && defined(I2C1_RX_DMA_IRQHandler) +void I2C1_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_master_dma_receive_isr_handler(&i2c_objs[I2C1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C1_RX_USING_DMA) && defined(I2C1_RX_DMA_IRQHandler) */ + +#if defined(BSP_I2C1_TX_USING_DMA) && defined(I2C1_TX_DMA_IRQHandler) +void I2C1_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + i2c_master_dma_send_isr_handler(&i2c_objs[I2C1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_I2C1_TX_USING_DMA) && defined(I2C1_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_HARD_I2C1 */ + + +int rt_hw_hw_i2c_init(void) +{ + int ret = -RT_ERROR; + rt_size_t obj_num = sizeof(i2c_objs) / sizeof(i2c_objs[0]); + + n32_get_dma_info(); + + for (int i = 0; i < obj_num; i++) + { + i2c_objs[i].i2c_bus.ops = &n32_i2c_ops; + i2c_objs[i].transfer.state = I2C_RESET; + i2c_objs[i].config = &i2c_config[i]; + i2c_objs[i].i2c_bus.timeout = i2c_config[i].timeout; + + rt_completion_init(&i2c_objs[i].completion); + n32_i2c_configure(&i2c_objs[i].i2c_bus); + ret = rt_i2c_bus_device_register(&i2c_objs[i].i2c_bus, i2c_objs[i].config->name); + RT_ASSERT(ret == RT_EOK); + LOG_D("%s bus init done", i2c_config[i].name); + } + return ret; +} +INIT_CORE_EXPORT(rt_hw_hw_i2c_init); + +#endif diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h new file mode 100644 index 0000000000..2b4a96f569 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_HARD_I2C_H__ +#define __DRV_HARD_I2C_H__ + +#include "drv_config.h" +#include +#include "rtdevice.h" +#include +#include +#include "drv_dma.h" +#include + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define I2C_USING_TX_DMA_FLAG (1U) +#define I2C_USING_RX_DMA_FLAG (1U << 1) + + +typedef enum +{ + I2C_RESET = 0x00U, + I2C_READY = 0x01U, + I2C_BUSY_TX = 0x02U, + I2C_BUSY_RX = 0x03U, +} I2C_StateTypeDef; + +struct n32_i2c_config +{ + const char *name; + I2C_Module *Instance; + rt_uint32_t timing; + rt_uint32_t timeout; + IRQn_Type evirq_type; + IRQn_Type erirq_type; + + rt_uint32_t scl_af_width; /* SCL Analog Filter Width */ + rt_uint32_t sda_af_width; /* SDA Analog Filter Width */ + rt_uint32_t df_width; /* Digital Filter Width */ + + uint32_t periph; + void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd); + void (*I2CKerClkSource)(uint32_t CLK_source); + + struct dma_config *dma_rx, *dma_tx; +}; + +struct hard_i2c_transfer +{ + uint8_t *pBuffPtr; /* Pointer to I2C transfer buffer */ + uint16_t XferSize; /* I2C transfer size */ + __IO uint16_t XferCount; /* I2C transfer counter */ + __IO uint32_t XferOptions; /* I2C sequantial transfer options */ + __IO I2C_StateTypeDef state; /* I2C communication state */ +}; + + +struct n32_i2c +{ + struct hard_i2c_transfer transfer; + + struct n32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; + rt_uint8_t i2c_dma_flag; + struct rt_completion completion; + + void (*i2c_isr_callback)(struct n32_i2c *drv_i2c); +}; + + + +#ifdef __cplusplus +} +#endif + + +#if defined(RT_USING_I2C) && defined(BSP_USING_I2C) + + +#endif /* defined(RT_USING_I2C) && defined(BSP_USING_I2C) */ + + +#endif /* __DRV_HARD_I2C_H__ */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_log.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_log.h new file mode 100644 index 0000000000..48f874b13f --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c new file mode 100644 index 0000000000..0d5b769c61 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_rtc.c @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include "board.h" +#include +#include +#include + +#ifdef BSP_USING_ONCHIP_RTC + +#ifndef RTC_BKP_REG1 + #define RTC_BKP_REG1 1U +#endif + +//#define DRV_DEBUG +#define LOG_TAG "drv.rtc" +#include + + +#define BKUP_REG_DATA 0xA5A5 + +struct rtc_device_object +{ + rt_rtc_dev_t rtc_dev; +#ifdef RT_USING_ALARM + struct rt_rtc_wkalarm wkalarm; +#endif +}; + +#ifdef RT_USING_ALARM +static rt_err_t rtc_alarm_time_set(struct rtc_device_object* p_dev); +static int rt_rtc_alarm_init(void); +static RTC_AlarmType Alarm_InitStruct = { 0 }; +static EXTI_InitType EXTI_InitStructure = { 0 }; +#endif + +static struct rtc_device_object rtc_device; + + +rt_weak uint32_t RTC_BKUP_Read(uint8_t BackupRegister) +{ + return RTC_BKUPRgRead(BackupRegister); +} + +rt_weak void RTC_BKUP_Write(uint8_t BackupRegister, uint32_t Data) +{ + RTC_BKUPRgWrite(BackupRegister, Data); +} + + +static rt_err_t n32_rtc_get_timeval(struct timeval *tv) +{ + uint32_t SubSeconds; + uint32_t Div_Sync; + RTC_TimeType RTC_TimeStruct = {0}; + RTC_DateType RTC_DateStruct = {0}; + struct tm tm_new = {0}; + + RTC_GetTime(RTC_FORMAT_BIN, &RTC_TimeStruct); + RTC_GetDate(RTC_FORMAT_BIN, &RTC_DateStruct); + + tm_new.tm_sec = RTC_TimeStruct.Seconds; + tm_new.tm_min = RTC_TimeStruct.Minutes; + tm_new.tm_hour = RTC_TimeStruct.Hours; + + tm_new.tm_mday = RTC_DateStruct.Date; + tm_new.tm_mon = RTC_DateStruct.Month - 1; + tm_new.tm_year = RTC_DateStruct.Year + 100; + + tv->tv_sec = timegm(&tm_new); + + SubSeconds = (uint32_t)(RTC->SUBS); + Div_Sync = (uint32_t)((RTC->PRE) & 0x00007FFFU); + tv->tv_usec = ((Div_Sync * 1.0) - (SubSeconds * 1.0)) / ((Div_Sync + 1U) * 1.0) * 1000.0 * 1000.0; + + return RT_EOK; +} + + +static rt_err_t set_rtc_time_stamp(time_t time_stamp) +{ + RTC_TimeType RTC_TimeStruct = {0}; + RTC_DateType RTC_DateStruct = {0}; + struct tm tm = {0}; + + gmtime_r(&time_stamp, &tm); + if (tm.tm_year < 100) + { + return -RT_ERROR; + } + + RTC_TimeStruct.Seconds = tm.tm_sec ; + RTC_TimeStruct.Minutes = tm.tm_min ; + RTC_TimeStruct.Hours = tm.tm_hour; + RTC_DateStruct.Date = tm.tm_mday; + RTC_DateStruct.Month = tm.tm_mon + 1 ; + RTC_DateStruct.Year = tm.tm_year - 100; + RTC_DateStruct.WeekDay = tm.tm_wday + 1; + + if (RTC_ConfigTime(RTC_FORMAT_BIN, &RTC_TimeStruct) == ERROR) + { + return -RT_ERROR; + } + if (RTC_SetDate(RTC_FORMAT_BIN, &RTC_DateStruct) == ERROR) + { + return -RT_ERROR; + } + + LOG_D("set rtc time."); + RTC_BKUP_Write(RTC_BKP_REG1, BKUP_REG_DATA); + + return RT_EOK; +} + + +static rt_err_t rt_rtc_config(void) +{ + uint32_t SynchPrediv, AsynchPrediv; + RTC_InitType RTC_InitStructure = { 0 }; + +#if defined(SOC_SERIES_N32H7xx) + /* Enable the PWR clock */ + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_PWR, ENABLE); + /* Allow access to RTC */ + PWR_BackupAccessEnable(ENABLE); + + /* Disable RTC clock */ + RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_M7_RTCPCLK, DISABLE); +#endif + +#if defined(BSP_RTC_USING_LSI) +#if defined(SOC_SERIES_N32H7xx) + /* Enable the LSI OSC */ + RCC_EnableLsi(ENABLE); + if (RCC_WaitLsiStable() == ERROR) + { + return -RT_ERROR; + } + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI, RCC_RTCCLK_HSEDIV63); +#endif + SynchPrediv = 0xF9; + AsynchPrediv = 0x7F; +#elif defined(BSP_RTC_USING_LSE) +#if defined(SOC_SERIES_N32H7xx) + /* Enable the LSI */ + RCC_EnableLsi(ENABLE); + RCC_ConfigLse(RCC_LSE_ENABLE); + + /****Waite LSE Ready *****/ + if (RCC_WaitLseStable() == ERROR) + { + return -RT_ERROR; + } + + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE, RCC_RTCCLK_HSEDIV_MASK); +#endif + SynchPrediv = 0xFF; + AsynchPrediv = 0x7F; +#else +#if defined(SOC_SERIES_N32H7xx) + /* Enable HSE */ + RCC_EnableLsi(ENABLE); + RCC_ConfigHse(RCC_HSE_ENABLE); + if (RCC_WaitHseStable() == ERROR) + { + return -RT_ERROR; + } + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSEDIV, RCC_RTCCLK_HSEDIV50); +#endif + SynchPrediv = 0x1387; + AsynchPrediv = 0x63; +#endif + +#if defined(SOC_SERIES_N32H7xx) + /* Enable the RTC Clock */ + RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_M7_RTCPCLK, ENABLE); + RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_M7_RTCPCLKLP, ENABLE); + RCC_EnableRtcClk(ENABLE); + + if (RTC_WaitForSynchro() == ERROR) + { + return -RT_ERROR; + } +#endif + + if (RTC_BKUP_Read(RTC_BKP_REG1) != BKUP_REG_DATA) + { + LOG_I("RTC hasn't been configured, please use command to config."); + + RTC_InitStructure.RTC_AsynchPrediv = AsynchPrediv; + RTC_InitStructure.RTC_SynchPrediv = SynchPrediv; + RTC_InitStructure.RTC_HourFormat = RTC_24HOUR_FORMAT; + + if (RTC_Init(&RTC_InitStructure) == ERROR) + { + return -RT_ERROR; + } + } + + return RT_EOK; +} + + +static rt_err_t n32_rtc_init(void) +{ + if (rt_rtc_config() != RT_EOK) + { + LOG_E("rtc init failed."); + return -RT_ERROR; + } + + return RT_EOK; +} + + +static rt_err_t n32_rtc_get_secs(time_t *sec) +{ + struct timeval tv; + + n32_rtc_get_timeval(&tv); + *(time_t *) sec = tv.tv_sec; + LOG_D("RTC: get rtc_time %d", *sec); + + return RT_EOK; +} + + +static rt_err_t n32_rtc_set_secs(time_t *sec) +{ + rt_err_t result = RT_EOK; + + if (set_rtc_time_stamp(*sec)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %d", *sec); +#ifdef RT_USING_ALARM + rt_alarm_update(&rtc_device.rtc_dev.parent, 1); +#endif + return result; +} + + +static rt_err_t n32_rtc_get_alarm(struct rt_rtc_wkalarm *alarm) +{ +#ifdef RT_USING_ALARM + *alarm = rtc_device.wkalarm; + LOG_D("GET_ALARM %d:%d:%d", rtc_device.wkalarm.tm_hour, + rtc_device.wkalarm.tm_min, + rtc_device.wkalarm.tm_sec); + return RT_EOK; +#else + return -RT_ERROR; +#endif +} + + +static rt_err_t n32_rtc_set_alarm(struct rt_rtc_wkalarm *alarm) +{ +#ifdef RT_USING_ALARM + LOG_D("RT_DEVICE_CTRL_RTC_SET_ALARM"); + if (alarm != RT_NULL) + { + rtc_device.wkalarm.enable = alarm->enable; + rtc_device.wkalarm.tm_hour = alarm->tm_hour; + rtc_device.wkalarm.tm_min = alarm->tm_min; + rtc_device.wkalarm.tm_sec = alarm->tm_sec; + rtc_device.wkalarm.tm_mday = alarm->tm_mday; + rtc_device.wkalarm.tm_mon = alarm->tm_mon; + rtc_device.wkalarm.tm_year = alarm->tm_year; + rtc_alarm_time_set(&rtc_device); + } + else + { + LOG_E("RT_DEVICE_CTRL_RTC_SET_ALARM error!!"); + return -RT_ERROR; + } + LOG_D("SET_ALARM %d:%d:%d", alarm->tm_hour, + alarm->tm_min, + alarm->tm_sec); + return RT_EOK; +#else + return -RT_ERROR; +#endif +} + + +static const struct rt_rtc_ops n32_rtc_ops = +{ + n32_rtc_init, + n32_rtc_get_secs, + n32_rtc_set_secs, + n32_rtc_get_alarm, + n32_rtc_set_alarm, + n32_rtc_get_timeval, + RT_NULL, +}; + + + +#ifdef RT_USING_ALARM +void rt_rtc_alarm_enable(void) +{ +#if defined(SOC_SERIES_N32H7xx) + /* Enable EXTI clocks */ + RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_EXTI, ENABLE); +#endif + + /* Configure the RTC Alarm A register */ + RTC_SetAlarm(RTC_FORMAT_BIN, RTC_A_ALARM, &Alarm_InitStruct); + /* Enable the RTC Alarm A Interrupt */ + RTC_ConfigInt(RTC_INT_ALRA, ENABLE); + /* Enable the Alarm A */ + RTC_EnableAlarm(RTC_A_ALARM, ENABLE); + + LOG_D("alarm read:%d:%d:%d", Alarm_InitStruct.AlarmTime.Hours, + Alarm_InitStruct.AlarmTime.Minutes, + Alarm_InitStruct.AlarmTime.Seconds); + + + RTC_ClrIntPendingBit(RTC_INT_ALRA); + EXTI_ClrITPendBit(EXTI_LINE17); + + EXTI_InitStruct(&EXTI_InitStructure); + +#if defined(SOC_SERIES_N32H7xx) + EXTI_InitStructure.EXTI_Line = EXTI_LINE17; +#endif + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_InitPeripheral(&EXTI_InitStructure); + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + NVIC_SetPriority(RTC_ALARM_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x02, 0)); + NVIC_EnableIRQ(RTC_ALARM_IRQn); +} + +void rt_rtc_alarm_disable(void) +{ + /* Disable the AlarmX */ + RTC_EnableAlarm(RTC_A_ALARM, DISABLE); + + EXTI_InitStructure.EXTI_LineCmd = DISABLE; +#if defined(SOC_SERIES_N32H7xx) + EXTI_InitStructure.EXTI_Line = EXTI_LINE17; + EXTI_InitPeripheral(&EXTI_InitStructure); + + EXTI_ClrITPendBit(EXTI_LINE17); +#endif + + NVIC_DisableIRQ(RTC_ALARM_IRQn); +} + +static int rt_rtc_alarm_init(void) +{ + return RT_EOK; +} + +static rt_err_t rtc_alarm_time_set(struct rtc_device_object* p_dev) +{ + if (p_dev->wkalarm.enable) + { + /* Disable the AlarmX */ + RTC_EnableAlarm(RTC_A_ALARM, DISABLE); + + Alarm_InitStruct.AlarmTime.Hours = p_dev->wkalarm.tm_hour; + Alarm_InitStruct.AlarmTime.Minutes = p_dev->wkalarm.tm_min; + Alarm_InitStruct.AlarmTime.Seconds = p_dev->wkalarm.tm_sec; + Alarm_InitStruct.DateWeekValue = p_dev->wkalarm.tm_mday; + + Alarm_InitStruct.AlarmTime.H12 = RTC_AM_H12; + Alarm_InitStruct.DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + Alarm_InitStruct.AlarmMask = RTC_ALARMMASK_NONE; + + LOG_D("alarm set:%d:%d:%d", Alarm_InitStruct.AlarmTime.Hours, + Alarm_InitStruct.AlarmTime.Minutes, + Alarm_InitStruct.AlarmTime.Seconds); + rt_rtc_alarm_enable(); + } + + return RT_EOK; +} + + +void RTC_ALARM_IRQHandler(void) +{ + rt_interrupt_enter(); + +#if defined(SOC_SERIES_N32H7xx) + EXTI_ClrITPendBit(EXTI_LINE17); +#endif + + if (RTC_GetITStatus(RTC_INT_ALRA) != RESET) + { + RTC_ClrIntPendingBit(RTC_INT_ALRA); + rt_alarm_update(&rtc_device.rtc_dev.parent, 1); + } + + rt_interrupt_leave(); +} +#endif + + +static int rt_hw_rtc_init(void) +{ + rt_err_t result; + + rtc_device.rtc_dev.ops = &n32_rtc_ops; + result = rt_hw_rtc_register(&rtc_device.rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL); + if (result != RT_EOK) + { + LOG_E("rtc register err code: %d", result); + return result; + } + LOG_D("rtc init success"); + +#ifdef RT_USING_ALARM + rt_rtc_alarm_init(); +#endif + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + + +#endif /* BSP_USING_ONCHIP_RTC */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_soft_i2c.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..5a0a7b911f --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_soft_i2c.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include "drv_soft_i2c.h" +#include "drv_config.h" + +#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c.sw" +#include + +static const struct n32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C5 + I2C5_BUS_CONFIG, +#endif +}; + +static struct n32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + +/** + * This function initializes the i2c pin. + * + * @param n32 i2c dirver class. + */ +static void n32_i2c_gpio_init(struct n32_i2c *i2c) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param n32 config class. + * @param The sda pin state. + */ +static void n32_set_sda(void *data, rt_int32_t state) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param n32 config class. + * @param The scl pin state. + */ +static void n32_set_scl(void *data, rt_int32_t state) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t n32_get_sda(void *data) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t n32_get_scl(void *data) +{ + struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data; + return rt_pin_read(cfg->scl); +} + + +static const struct rt_i2c_bit_ops n32_bit_ops_default = +{ + .data = RT_NULL, + .set_sda = n32_set_sda, + .set_scl = n32_set_scl, + .get_sda = n32_get_sda, + .get_scl = n32_get_scl, + .udelay = rt_hw_us_delay, + .delay_us = 1, + .timeout = 100 +}; + +/** + * if i2c is locked, this function will unlock it + * + * @param n32 config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t n32_i2c_bus_unlock(const struct n32_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + rt_hw_us_delay(100); + rt_pin_write(cfg->scl, PIN_LOW); + rt_hw_us_delay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_err_t result; + + for (rt_size_t i = 0; i < sizeof(i2c_obj) / sizeof(struct n32_i2c); i++) + { + i2c_obj[i].ops = n32_bit_ops_default; + i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; + + n32_i2c_gpio_init(&i2c_obj[i]); + + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + n32_i2c_bus_unlock(&soft_i2c_config[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, + soft_i2c_config[i].sda); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); + +#endif /* defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_soft_i2c.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..2695e5896e --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_soft_i2c.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_SOFT_I2C_H__ +#define __DRV_SOFT_I2C_H__ + +#include +#include +#include + +/* n32 config class */ +struct n32_soft_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; +/* n32 i2c dirver class */ +struct n32_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c_bus; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1", \ + } +#endif + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_I2C2_SCL_PIN, \ + .sda = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2", \ + } +#endif + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .scl = BSP_I2C3_SCL_PIN, \ + .sda = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3", \ + } +#endif + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .scl = BSP_I2C4_SCL_PIN, \ + .sda = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4", \ + } +#endif + +#ifdef BSP_USING_I2C5 +#define I2C5_BUS_CONFIG \ + { \ + .scl = BSP_I2C5_SCL_PIN, \ + .sda = BSP_I2C5_SDA_PIN, \ + .bus_name = "i2c5", \ + } +#endif + +#endif /* __DRV_SOFT_I2C_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c new file mode 100644 index 0000000000..0c0dd3d99b --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.c @@ -0,0 +1,1926 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include +#include +#include "board.h" + +#ifdef BSP_USING_SPI + +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) || defined(BSP_USING_SPI7) + + +#include "drv_spi.h" +#include "drv_config.h" +#include + +//#define DRV_DEBUG +#define LOG_TAG "drv.spi" +#include + +enum +{ +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +#ifdef BSP_USING_SPI2 + SPI2_INDEX, +#endif +#ifdef BSP_USING_SPI3 + SPI3_INDEX, +#endif +#ifdef BSP_USING_SPI4 + SPI4_INDEX, +#endif +#ifdef BSP_USING_SPI5 + SPI5_INDEX, +#endif +#ifdef BSP_USING_SPI6 + SPI6_INDEX, +#endif +#ifdef BSP_USING_SPI7 + SPI7_INDEX, +#endif +}; + + +static struct n32_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI3 + SPI3_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI4 + SPI4_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI5 + SPI5_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI6 + SPI6_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI7 + SPI7_BUS_CONFIG, +#endif +}; + +static struct n32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = { 0 }; + + +static rt_err_t SPI_DMA_TransmitReceive(struct n32_spi *spi_drv, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT((spi_drv->cfg->mode & RT_SPI_3WIRE) != RT_SPI_3WIRE); + + if (spi_drv->dma.DMA_Rx_Init != RT_TRUE || spi_drv->dma.DMA_Tx_Init != RT_TRUE) + { + LOG_E("In full-duplex mode, both TX DMA and RX DMA did not complete initialization."); + return -RT_ERROR; + } + + if (spi_drv->dma.DMA_Rx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + /* SPI RX DMA Receive Data */ + DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(spi_drv->config->dma_rx->Instance)) + DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + + spi_drv->dma.RX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)pRxData; + spi_drv->dma.RX_DMA_ChInitStr.BlkTfrSize = Size; + + DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + if (DMA_ChannelInit(spi_drv->config->dma_rx->Instance, &spi_drv->dma.RX_DMA_ChInitStr, spi_drv->config->dma_rx->dma_channel) == 0U) + { + /* Enable transaction complete interrupt event */ + DMA_ChannelEventCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, ENABLE); + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, ENABLE); + + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_RX, ENABLE); + } +#endif + } + else + { + LOG_E("In full-duplex mode, RX DMA did not complete initialization."); + return -RT_ERROR; + } + + if (spi_drv->dma.DMA_Tx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + /* SPI TX DMA Send Data */ + DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(spi_drv->config->dma_tx->Instance)) + DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + + spi_drv->dma.TX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)pTxData; + spi_drv->dma.TX_DMA_ChInitStr.BlkTfrSize = Size; + + DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + if (DMA_ChannelInit(spi_drv->config->dma_tx->Instance, &spi_drv->dma.TX_DMA_ChInitStr, spi_drv->config->dma_tx->dma_channel) == 0U) + { + /* Enable transaction complete interrupt event */ + DMA_ChannelEventCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, ENABLE); + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, ENABLE); + + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_TX, ENABLE); + } +#endif + } + else + { + LOG_E("In full-duplex mode, TX DMA did not complete initialization."); + return -RT_ERROR; + } + + /* Clear Over Flag */ + SPI_I2S_ReceiveData(spi_drv->config->SPIx); + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + + /* Enable Error Interrupt */ + SPI_I2S_EnableInt(spi_drv->config->SPIx, SPI_I2S_INT_ERR, ENABLE); + + /* Set SPI Direction */ + spi_drv->Direct = SPI_Tx_Rx; + + /* Check if the SPI is already enabled */ + if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + SPI_Enable(spi_drv->config->SPIx, ENABLE); + + return RT_EOK; +} + +static rt_err_t SPI_DMA_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Size) +{ + RT_ASSERT(spi_drv != RT_NULL); + + if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + { + /* Disable the sFLASH_SPI */ + SPI_Enable(spi_drv->config->SPIx, DISABLE); + /* DeInitializes the sFLASH_SPI */ + SPI_I2S_DeInit(spi_drv->config->SPIx); + /* Set the sFLASH_SPI SendOnly*/ + spi_drv->SPI_InitStructure.DataDirection = SPI_DIR_SINGLELINE_TX; + SPI_Init(spi_drv->config->SPIx, &spi_drv->SPI_InitStructure); + } + + if (spi_drv->dma.DMA_Rx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(spi_drv->config->dma_rx->Instance)) + DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + + spi_drv->dma.RX_DMA_ChInitStr.IntEn = 0U; + spi_drv->dma.RX_DMA_ChInitStr.DstAddr = NULL; + spi_drv->dma.RX_DMA_ChInitStr.BlkTfrSize = 0U; + + DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + if (DMA_ChannelInit(spi_drv->config->dma_rx->Instance, &spi_drv->dma.RX_DMA_ChInitStr, spi_drv->config->dma_rx->dma_channel) != 0U) + { + LOG_E("Master DMA Rx channel initialization failed."); + return -RT_ERROR; + } +#endif + } + + if (spi_drv->dma.DMA_Tx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(spi_drv->config->dma_tx->Instance)) + DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + + spi_drv->dma.TX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)pData; + spi_drv->dma.TX_DMA_ChInitStr.BlkTfrSize = Size; + + DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + if (DMA_ChannelInit(spi_drv->config->dma_tx->Instance, &spi_drv->dma.TX_DMA_ChInitStr, spi_drv->config->dma_tx->dma_channel) == 0U) + { + /* Enable transaction complete interrupt event */ + DMA_ChannelEventCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, ENABLE); + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, ENABLE); + + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_TX, ENABLE); + } +#endif + } + else + { + LOG_E("SPI DMA TX Mode, TX DMA did not complete initialization."); + return -RT_ERROR; + } + + /* Set SPI Direction */ + spi_drv->Direct = SPI_Tx; + + /* Check if the SPI is already enabled */ + if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + SPI_Enable(spi_drv->config->SPIx, ENABLE); + + return RT_EOK; +} + +static rt_err_t SPI_DMA_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Size) +{ + RT_ASSERT(spi_drv != RT_NULL); + + if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_FULLDUPLEX && spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER) + { + return SPI_DMA_TransmitReceive(spi_drv, pData, pData, Size); + } + + if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + { + /* Disable the sFLASH_SPI */ + SPI_Enable(spi_drv->config->SPIx, DISABLE); + /* DeInitializes the sFLASH_SPI */ + SPI_I2S_DeInit(spi_drv->config->SPIx); + /* Set the sFLASH_SPI SendOnly*/ + spi_drv->SPI_InitStructure.DataDirection = SPI_DIR_SINGLELINE_RX; + SPI_Init(spi_drv->config->SPIx, &spi_drv->SPI_InitStructure); + } + + if (spi_drv->dma.DMA_Rx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(spi_drv->config->dma_rx->Instance)) + DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + + spi_drv->dma.RX_DMA_ChInitStr.IntEn = 1U; + spi_drv->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)pData; + spi_drv->dma.RX_DMA_ChInitStr.BlkTfrSize = Size; + + DMA_ControllerCmd(spi_drv->config->dma_rx->Instance, ENABLE); + if (DMA_ChannelInit(spi_drv->config->dma_rx->Instance, &spi_drv->dma.RX_DMA_ChInitStr, spi_drv->config->dma_rx->dma_channel) == 0U) + { + /* Enable transaction complete interrupt event */ + DMA_ChannelEventCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, ENABLE); + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, ENABLE); + + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_RX, ENABLE); + } +#endif + } + else + { + LOG_E("SPI DMA RX Mode, RX DMA did not complete initialization."); + return -RT_ERROR; + } + + if (spi_drv->dma.DMA_Tx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(spi_drv->config->dma_tx->Instance)) + DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + + spi_drv->dma.TX_DMA_ChInitStr.IntEn = 0U; + spi_drv->dma.TX_DMA_ChInitStr.SrcAddr = NULL; + spi_drv->dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; + + DMA_ControllerCmd(spi_drv->config->dma_tx->Instance, ENABLE); + if (DMA_ChannelInit(spi_drv->config->dma_tx->Instance, &spi_drv->dma.TX_DMA_ChInitStr, spi_drv->config->dma_tx->dma_channel) != 0U) + { + LOG_E("Master DMA Tx channel initialization failed."); + return -RT_ERROR; + } +#endif + } + + /* Clear Over Flag */ + SPI_I2S_ReceiveData(spi_drv->config->SPIx); + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + + /* Enable Error Interrupt */ + SPI_I2S_EnableInt(spi_drv->config->SPIx, SPI_I2S_INT_ERR, ENABLE); + + /* Set SPI Direction */ + spi_drv->Direct = SPI_Rx; + + /* Check if the SPI is already enabled */ + if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + SPI_Enable(spi_drv->config->SPIx, ENABLE); + + return RT_EOK; +} + +static rt_err_t SPI_Transmit_Receive(struct n32_spi *spi_drv, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint16_t Tx_Size_Const = Size; + uint16_t Tx_Size = Size; + uint16_t Rx_Size = Size; + uint32_t tickstart; + + RT_ASSERT(spi_drv != RT_NULL); + + if (!((spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER) && (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_FULLDUPLEX))) + { + return -RT_EIO; + } + + if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + SPI_Enable(spi_drv->config->SPIx, ENABLE); + + if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_16BITS) + { + if ((spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_SLAVE) || (Tx_Size_Const == 1U)) + { + spi_drv->config->SPIx->DAT = *((const uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + Tx_Size--; + } + + while ((Tx_Size > 0U) || (Rx_Size > 0U)) + { + if (Tx_Size > 0U) + { + tickstart = rt_tick_get(); + /* Loop while DAT register in not emplty */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking TE flag timeout befor send data in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + /* Send byte through the SPI1 peripheral */ + SPI_I2S_TransmitData(spi_drv->config->SPIx, *(const uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + + Tx_Size--; + } + + tickstart = rt_tick_get(); + /* Wait for DATA send has complete */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking TE flag timeout after send data in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + tickstart = rt_tick_get(); + /* Wait for SPI bus idle */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking BUSY flag timeout in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + tickstart = rt_tick_get(); + /* Wait to receive a byte */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking RNE flag timeout after send data in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + /* Return the byte read from the SPI bus */ + *((uint16_t *)pRxData) = (uint16_t)SPI_I2S_ReceiveData(spi_drv->config->SPIx); + pRxData += sizeof(uint16_t); + + Rx_Size--; + } + } + else if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_8BITS) + { + if ((spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_SLAVE) || (Tx_Size_Const == 1U)) + { + spi_drv->config->SPIx->DAT = *((const uint8_t *)pTxData); + pTxData += sizeof(uint8_t); + Tx_Size--; + } + + while ((Tx_Size > 0U) || (Rx_Size > 0U)) + { + if (Tx_Size > 0U) + { + tickstart = rt_tick_get(); + /* Loop while DAT register in not emplty */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking TE flag timeout befor send data in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + /* Send byte through the SPI1 peripheral */ + SPI_I2S_TransmitData(spi_drv->config->SPIx, *(const uint8_t *)pTxData); + pTxData += sizeof(uint8_t); + + Tx_Size--; + } + + tickstart = rt_tick_get(); + /* Wait for DATA send has complete */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking TE flag timeout after send data in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + tickstart = rt_tick_get(); + /* Wait for SPI bus idle */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking BUSY flag timeout in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + tickstart = rt_tick_get(); + /* Wait to receive a byte */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking RNE flag timeout after send data in full-duplex mode."); + return -RT_ETIMEOUT; + } + } + + /*!< Return the byte read from the SPI bus */ + *((uint8_t *)pRxData) = (uint8_t)SPI_I2S_ReceiveData(spi_drv->config->SPIx); + pRxData += sizeof(uint8_t); + + Rx_Size--; + } + } + else + { + return -RT_EINVAL; + } + + if (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) != RESET) + { + volatile uint32_t reg_tmp; + reg_tmp = spi_drv->config->SPIx->DAT; + reg_tmp = spi_drv->config->SPIx->STS; + (void)reg_tmp; + } + + return RT_EOK; +} + +static rt_err_t SPI_Transmit(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t Tx_Size_Const = Size; + uint16_t Transfer_Size = Size; + uint32_t tickstart; + + RT_ASSERT(spi_drv != RT_NULL); + + if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + { + /* Disable the sFLASH_SPI */ + SPI_Enable(spi_drv->config->SPIx, DISABLE); + /* DeInitializes the sFLASH_SPI */ + SPI_I2S_DeInit(spi_drv->config->SPIx); + /* Set the sFLASH_SPI SendOnly*/ + spi_drv->SPI_InitStructure.DataDirection = SPI_DIR_SINGLELINE_TX; + SPI_Init(spi_drv->config->SPIx, &spi_drv->SPI_InitStructure); + } + + if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + SPI_Enable(spi_drv->config->SPIx, ENABLE); + + + if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_16BITS) + { + if ((spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_SLAVE) || (Tx_Size_Const == 1U)) + { + spi_drv->config->SPIx->DAT = *((const uint16_t *)pData); + pData += sizeof(uint16_t); + Transfer_Size--; + } + + while ((Transfer_Size > 0U)) + { + tickstart = rt_tick_get(); + /* Loop while DAT register in not emplty */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking TE flag timeout."); + return -RT_ETIMEOUT; + } + } + + + /* Send byte through the SPI1 peripheral */ + SPI_I2S_TransmitData(spi_drv->config->SPIx, *(const uint16_t *)pData); + pData += sizeof(uint16_t); + + Transfer_Size--; + } + } + else if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_8BITS) + { + if ((spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_SLAVE) || (Tx_Size_Const == 1U)) + { + spi_drv->config->SPIx->DAT = *((const uint8_t *)pData); + pData += sizeof(uint8_t); + Transfer_Size--; + } + + while ((Transfer_Size > 0U)) + { + tickstart = rt_tick_get(); + /* Loop while DAT register in not emplty */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Checking TE flag timeout."); + return -RT_ETIMEOUT; + } + } + + + /* Send byte through the SPI1 peripheral */ + SPI_I2S_TransmitData(spi_drv->config->SPIx, *(const uint8_t *)pData); + pData += sizeof(uint8_t); + + Transfer_Size--; + } + } + else + { + + } + + tickstart = rt_tick_get(); + /* Wait for DATA send has complete */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_TE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("After sending the data, check the TE flag for timeout."); + return -RT_ETIMEOUT; + } + } + + tickstart = rt_tick_get(); + /* Wait for SPI bus idle */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("After sending the data, check the BUSY flag for timeout."); + return -RT_ETIMEOUT; + } + } + + if (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) != RESET) + { + volatile uint32_t reg_tmp; + reg_tmp = spi_drv->config->SPIx->DAT; + reg_tmp = spi_drv->config->SPIx->STS; + (void)reg_tmp; + } + + return RT_EOK; +} + + +static rt_err_t SP_Receive(struct n32_spi *spi_drv, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint16_t Transfer_Size = Size; + uint32_t tickstart; + + RT_ASSERT(spi_drv != RT_NULL); + + tickstart = rt_tick_get(); + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) != RESET || SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) != RESET) + { + volatile uint32_t reg_tmp; + reg_tmp = spi_drv->config->SPIx->DAT; + reg_tmp = spi_drv->config->SPIx->STS; + (void)reg_tmp; + + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("Before receiving data, check the OVER and RNE flags for timeout."); + return -RT_ETIMEOUT; + } + } + + if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_FULLDUPLEX && spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER) + { + return SPI_Transmit_Receive(spi_drv, pData, pData, Size, Timeout); + } + + if (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_TX) + { + /* Disable the sFLASH_SPI */ + SPI_Enable(spi_drv->config->SPIx, DISABLE); + /* DeInitializes the sFLASH_SPI */ + SPI_I2S_DeInit(spi_drv->config->SPIx); + /* Set the sFLASH_SPI SendOnly*/ + spi_drv->SPI_InitStructure.DataDirection = SPI_DIR_SINGLELINE_RX; + SPI_Init(spi_drv->config->SPIx, &spi_drv->SPI_InitStructure); + } + + if ((spi_drv->config->SPIx->CTRL2 & SPI_CTRL2_SPIEN) != SPI_CTRL2_SPIEN) + SPI_Enable(spi_drv->config->SPIx, ENABLE); + + if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_16BITS) + { + while ((Transfer_Size > 0U)) + { + tickstart = rt_tick_get(); + /* Wait to receive a byte */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("During receiving data, check the RNE flags for timeout."); + return -RT_ETIMEOUT; + } + } + + /*!< Return the byte read from the SPI bus */ + *((uint16_t *)pData) = (uint16_t)SPI_I2S_ReceiveData(spi_drv->config->SPIx); + pData += sizeof(uint16_t); + + Transfer_Size--; + } + } + else if (spi_drv->SPI_InitStructure.DataLen == SPI_DATA_SIZE_8BITS) + { + while ((Transfer_Size > 0U)) + { + tickstart = rt_tick_get(); + /* Wait to receive a byte */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("During receiving data, check the RNE flags for timeout."); + return -RT_ETIMEOUT; + } + } + + /*!< Return the byte read from the SPI bus */ + *((uint8_t *)pData) = (uint8_t)SPI_I2S_ReceiveData(spi_drv->config->SPIx); + pData += sizeof(uint8_t); + + Transfer_Size--; + } + } + else + { + + } + + if ((spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_RONLY || + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX) && + spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER) + { + /* Disable the sFLASH_SPI */ + SPI_Enable(spi_drv->config->SPIx, DISABLE); + } + + tickstart = rt_tick_get(); + /* Wait to receive a byte */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) == RESET) + { + spi_drv->config->SPIx->DAT; + + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("After receiving data, check the RNE flags for timeout."); + return -RT_ETIMEOUT; + } + } + + tickstart = rt_tick_get(); + /* Wait for SPI bus idle */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) + { + if ((((rt_tick_get() - tickstart) >= Timeout) && (Timeout != 0xFFFFFFFFU)) || (Timeout == 0U)) + { + LOG_E("After receiving data, check the BUSY flags for timeout."); + return -RT_ETIMEOUT; + } + } + + if (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) != RESET) + { + volatile uint32_t reg_tmp; + reg_tmp = spi_drv->config->SPIx->DAT; + reg_tmp = spi_drv->config->SPIx->STS; + (void)reg_tmp; + } + + return RT_EOK; +} + + +static rt_err_t n32_spi_init(struct n32_spi *spi_drv, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + SPI_InitStruct(&spi_drv->SPI_InitStructure); + + if (cfg->mode & RT_SPI_SLAVE) + { + spi_drv->SPI_InitStructure.SpiMode = SPI_MODE_SLAVE; + } + else + { + spi_drv->SPI_InitStructure.SpiMode = SPI_MODE_MASTER; + } + + if (cfg->mode & RT_SPI_3WIRE) + { + /* Switch TX/RX direction dynamically according to the application */ + spi_drv->SPI_InitStructure.DataDirection = SPI_DIR_SINGLELINE_RX; + } + else + { + spi_drv->SPI_InitStructure.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + } + + if (cfg->data_width == 8) + { + spi_drv->SPI_InitStructure.DataLen = SPI_DATA_SIZE_8BITS; + } + else if (cfg->data_width == 16) + { + spi_drv->SPI_InitStructure.DataLen = SPI_DATA_SIZE_16BITS; + } + else + { + return -RT_EIO; + } + + if (cfg->mode & RT_SPI_CPHA) + { + spi_drv->SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE; + } + else + { + spi_drv->SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE; + } + + if (cfg->mode & RT_SPI_CPOL) + { + spi_drv->SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH; + } + else + { + spi_drv->SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW; + } + + spi_drv->SPI_InitStructure.NSS = SPI_NSS_SOFT; + spi_drv->SPI_InitStructure.CRCPoly = 7; + + uint32_t SPI_CLOCK = 0UL; + +#if defined(SOC_SERIES_N32H7xx) + RCC_ClocksTypeDef RCC_Clocks = { 0 }; + + RCC_GetClocksFreqValue(&RCC_Clocks); + + if ((spi_drv->config->SPIx == SPI1) || (spi_drv->config->SPIx == SPI2)) + { + SPI_CLOCK = RCC_Clocks.APB2ClkFreq; + } + else if (spi_drv->config->SPIx == SPI3) + { + SPI_CLOCK = RCC_Clocks.APB1ClkFreq; + } + else if ((spi_drv->config->SPIx == SPI4) || (spi_drv->config->SPIx == SPI5) || (spi_drv->config->SPIx == SPI6) || (spi_drv->config->SPIx == SPI7)) + { + SPI_CLOCK = RCC_Clocks.APB5ClkFreq; + } + else + { + return -RT_EIO; + } +#endif + + if (cfg->max_hz >= SPI_CLOCK / 2) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_2; + } + else if (cfg->max_hz >= SPI_CLOCK / 4) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_4; + } + else if (cfg->max_hz >= SPI_CLOCK / 8) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_8; + } + else if (cfg->max_hz >= SPI_CLOCK / 16) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_16; + } + else if (cfg->max_hz >= SPI_CLOCK / 32) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_32; + } + else if (cfg->max_hz >= SPI_CLOCK / 64) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_64; + } + else if (cfg->max_hz >= SPI_CLOCK / 128) + { + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_128; + } + else + { + /* min prescaler 256 */ + spi_drv->SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_256; + } + + if (cfg->mode & RT_SPI_MSB) + { + spi_drv->SPI_InitStructure.FirstBit = SPI_FB_MSB; + } + else + { + spi_drv->SPI_InitStructure.FirstBit = SPI_FB_LSB; + } + + /* Initializes the SPIx peripheral */ + SPI_Init(spi_drv->config->SPIx, &spi_drv->SPI_InitStructure); + + /* DMA configuration */ + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + if (cfg->data_width == 8) + { +#if defined(SOC_SERIES_N32H7xx) + spi_drv->dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_drv->dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; +#endif + } + else if (cfg->data_width == 16) + { +#if defined(SOC_SERIES_N32H7xx) + spi_drv->dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_16; + spi_drv->dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_16; +#endif + } + + /* enable dma irq */ + NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq); + } + + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + if (cfg->data_width == 8) + { +#if defined(SOC_SERIES_N32H7xx) + spi_drv->dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_drv->dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; +#endif + } + else if (cfg->data_width == 16) + { +#if defined(SOC_SERIES_N32H7xx) + spi_drv->dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_16; + spi_drv->dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_16; +#endif + } + + /* enable dma irq */ + NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0)); + NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq); + } + + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG || spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + /* enable dma irq */ + NVIC_SetPriority(spi_drv->config->irq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 0)); + NVIC_EnableIRQ(spi_drv->config->irq_type); + } + + LOG_D("%s init done", spi_drv->config->bus_name); + return RT_EOK; +} + + +static rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus); + spi_drv->cfg = configuration; + + return n32_spi_init(spi_drv, configuration); +} + + +static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ +#define DMA_TRANS_MIN_LEN 10 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ + + rt_err_t state = RT_EOK; + uint32_t tickstart; + rt_size_t message_length, already_send_length; + rt_uint16_t send_length; + rt_uint8_t *recv_buf; + const rt_uint8_t *send_buf; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct n32_spi *spi_drv = rt_container_of(device->bus, struct n32_spi, spi_bus); + + if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) + { + if (device->config.mode & RT_SPI_CS_HIGH) + { + rt_pin_write(device->cs_pin, PIN_HIGH); + } + else + { + rt_pin_write(device->cs_pin, PIN_LOW); + } + } + + LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + spi_drv->config->bus_name, + (uint32_t)message->send_buf, + (uint32_t)message->recv_buf, message->length); + + message_length = message->length; + recv_buf = message->recv_buf; + send_buf = message->send_buf; + + while (message_length) + { +#if defined(SOC_SERIES_N32H7xx) + /* DMA uses a single block, with a maximum of 4095 per block */ + if (message_length > 4095) + { + send_length = 4095; + message_length = message_length - 4095; + } + else + { + send_length = message_length; + message_length = 0; + } +#endif + + /* calculate the start address */ + already_send_length = message->length - send_length - message_length; + /* avoid null pointer problems */ + if (message->send_buf) + { + send_buf = (rt_uint8_t *)message->send_buf + already_send_length; + } + if (message->recv_buf) + { + recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length; + } + + rt_uint32_t *dma_aligned_buffer = RT_NULL; + rt_uint32_t *p_txrx_buffer = RT_NULL; + + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) + { +#if defined(SOC_SERIES_N32H7xx) + if (RT_IS_ALIGN((rt_uint32_t)send_buf, 32) && send_buf != RT_NULL) /* aligned with 32 bytes? */ + { + p_txrx_buffer = (rt_uint32_t *)send_buf; /* send_buf aligns with 32 bytes, no more operations */ + } + else + { + /* send_buf doesn't align with 32 bytes, so creat a cache buffer with 32 bytes aligned */ + dma_aligned_buffer = (rt_uint32_t *)rt_malloc_align(send_length, 32); + rt_memcpy(dma_aligned_buffer, send_buf, send_length); + p_txrx_buffer = dma_aligned_buffer; + } + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, dma_aligned_buffer, send_length); +#else + if (RT_IS_ALIGN((rt_uint32_t)send_buf, 4) && send_buf != RT_NULL) /* aligned with 4 bytes? */ + { + p_txrx_buffer = (rt_uint32_t *)send_buf; /* send_buf aligns with 4 bytes, no more operations */ + } + else + { + /* send_buf doesn't align with 4 bytes, so creat a cache buffer with 4 bytes aligned */ + dma_aligned_buffer = (rt_uint32_t *)rt_malloc(send_length); /* aligned with RT_ALIGN_SIZE (8 bytes by default) */ + rt_memcpy(dma_aligned_buffer, send_buf, send_length); + p_txrx_buffer = dma_aligned_buffer; + } +#endif + } + + tickstart = rt_tick_get(); + /* Check the SPI RNE Flag */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_RNE_FLAG) != RESET) + { + /*clear RX buff*/ + spi_drv->config->SPIx->DAT; + + if ((rt_tick_get() - tickstart) > 1000U) + { + state = -RT_ERROR; + LOG_E("Checking the RNE flag timeout before transmission begins!"); + break; + } + } + + tickstart = rt_tick_get(); + /* Check the SPI OVER Flag */ + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) != RESET) + { + /*clear RX buff*/ + spi_drv->config->SPIx->DAT; + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + + if ((rt_tick_get() - tickstart) > 1000U) + { + state = -RT_ERROR; + LOG_E("Checking the OVER flag timeout before transmission begins!"); + break; + } + } + + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) + { + state = SPI_DMA_TransmitReceive(spi_drv, (uint8_t *)p_txrx_buffer, (uint8_t *)p_txrx_buffer, send_length); + } + else if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) + { + state = SPI_DMA_Transmit(spi_drv, (uint8_t *)p_txrx_buffer, send_length); + } + else if ((spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) + { + state = -RT_ERROR; + LOG_E("It shoule be enabled both BSP_SPIx_TX_USING_DMA and BSP_SPIx_TX_USING_DMA flag, if wants to use SPI DMA Rx singly."); + break; + } + else + { + state = SPI_Transmit_Receive(spi_drv, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length, 1000); + } + } + else if (message->send_buf) + { + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) + { + state = SPI_DMA_Transmit(spi_drv, (uint8_t *)p_txrx_buffer, send_length); + } + else + { + state = SPI_Transmit(spi_drv, (uint8_t *)send_buf, send_length, 1000); + } + + if (message->cs_release && (device->config.mode & RT_SPI_3WIRE)) + { + /* release the CS by disable SPI when using 3 wires SPI */ + SPI_Enable(spi_drv->config->SPIx, DISABLE); + } + } + else if (message->recv_buf) + { + rt_memset((uint8_t *)recv_buf, 0xff, send_length); + if ((spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN)) + { + state = SPI_DMA_Receive(spi_drv, (uint8_t *)p_txrx_buffer, send_length); + } + else + { + /* clear the old error flag */ + __IO uint32_t tmpreg = 0x00U; + tmpreg = spi_drv->config->SPIx->DAT; + tmpreg = spi_drv->config->SPIx->STS; + (void)tmpreg; + + state = SP_Receive(spi_drv, (uint8_t *)recv_buf, send_length, 1000); + } + } + else + { + state = -RT_ERROR; + LOG_E("message->send_buf and message->recv_buf are both NULL!"); + } + + if (state != RT_EOK) + { + LOG_E("SPI transfer error: %d", state); + message->length = 0; + break; + } + else + { + LOG_D("%s transfer done", spi_drv->config->bus_name); + } + + /* For simplicity reasons, this example is just waiting till the end of the + transfer, but application may perform other tasks while transfer operation + is ongoing. */ + if ((spi_drv->spi_dma_flag & (SPI_USING_TX_DMA_FLAG | SPI_USING_RX_DMA_FLAG)) && (send_length >= DMA_TRANS_MIN_LEN)) + { + /* blocking the thread,and the other tasks can run */ + if (rt_completion_wait(&spi_drv->cpt, 1000) != RT_EOK) + { + state = -RT_ERROR; + LOG_E("wait for DMA interrupt overtime!"); + break; + } + } + + tickstart = rt_tick_get(); + while (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_BUSY_FLAG) != RESET) + { + if ((rt_tick_get() - tickstart) > 1000U) + { + state = -RT_ERROR; + LOG_E("Wait SPI BUSY Flag Timeout!"); + break; + } + } + + if (dma_aligned_buffer != RT_NULL) /* re-aligned, so need to copy the data to recv_buf */ + { + if (recv_buf != RT_NULL) + { +#if defined(SOC_SERIES_N32H7xx) + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, p_txrx_buffer, send_length); +#endif /* SOC_SERIES_N32H7xx */ + rt_memcpy(recv_buf, p_txrx_buffer, send_length); + } +#if defined(SOC_SERIES_N32H7xx) + rt_free_align(dma_aligned_buffer); +#else + rt_free(dma_aligned_buffer); +#endif /* SOC_SERIES_N32H7xx */ + } + } + + if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) + { + if (device->config.mode & RT_SPI_CS_HIGH) + rt_pin_write(device->cs_pin, PIN_LOW); + else + rt_pin_write(device->cs_pin, PIN_HIGH); + } + + if (state != RT_EOK) + { + return -RT_ERROR; + } + return message->length; +} + +static const struct rt_spi_ops n32_spi_ops = +{ + .configure = spi_configure, + .xfer = spixfer, +}; + + + +static int rt_hw_spi_bus_init(void) +{ + rt_err_t result; + + for (rt_size_t i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++) + { + spi_bus_obj[i].config = &spi_config[i]; + spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; + + + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { +#if defined(SOC_SERIES_N32H7xx) + /* Configure the SPI RX DMA for Transmission process */ + /* Enable DMA clock */ + RCC_EnableAHB1PeriphClk3(spi_bus_obj[i].config->dma_rx->dma_rcc, ENABLE); + /* Enable DMA MUXclock */ + RCC_EnableAHB1PeriphClk1(RCC_AHB1_PERIPHEN_M7_DMAMUX1, ENABLE); + + /* Receive DMA Config */ + DMA_ChannelStructInit(&spi_bus_obj[i].dma.RX_DMA_ChInitStr); + spi_bus_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&spi_bus_obj[i].config->SPIx->DAT; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstAddr = NULL; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherEn = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterEn = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.BlkTfrSize = 0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.pLinkListItem = NULL; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcGatherCount = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterInterval = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstScatterCount = 0x0U; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; + spi_bus_obj[i].dma.RX_DMA_ChInitStr.SrcHsInterface = spi_bus_obj[i].config->dma_rx->HsInterface; + + /* DMA controller must be enabled before initializing the channel */ + DMA_ControllerCmd(spi_bus_obj[i].config->dma_rx->Instance, ENABLE); + + /* Initialize the specified DMA channel and Whether the specified channel was successfully initialized */ + if (DMA_ChannelInit(spi_bus_obj[i].config->dma_rx->Instance, &spi_bus_obj[i].dma.RX_DMA_ChInitStr, spi_bus_obj[i].config->dma_rx->dma_channel) == 0U) + { + /* Configure DMAMUX */ + DMAMUX_SetRequestID(DMAMUX1_ID, spi_bus_obj[i].config->dma_rx->dmamux_channel, spi_bus_obj[i].config->dma_rx->dmamux_request); + + spi_bus_obj[i].dma.DMA_Rx_Init = RT_TRUE; + } + else + { + LOG_E("SPI RX DMA channel initialization failed!"); + return -RT_ERROR; + } +#endif + } + + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { +#if defined(SOC_SERIES_N32H7xx) + /* Configure the SPI TX DMA for Transmission process */ + /* Enable DMA clock */ + RCC_EnableAHB1PeriphClk3(spi_bus_obj[i].config->dma_tx->dma_rcc, ENABLE); + /* Enable DMA MUXclock */ + RCC_EnableAHB1PeriphClk1(RCC_AHB1_PERIPHEN_M7_DMAMUX1, ENABLE); + + /* SPI_MASTER_Tx_DMA_Channel DMA1 Channel1 configuration ---------------------------------------------*/ + DMA_ChannelStructInit(&spi_bus_obj[i].dma.TX_DMA_ChInitStr); + spi_bus_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&spi_bus_obj[i].config->SPIx->DAT; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = NULL; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherEn = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = NULL; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterInterval = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstScatterCount = 0x0U; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; + spi_bus_obj[i].dma.TX_DMA_ChInitStr.DstHsInterface = spi_bus_obj[i].config->dma_tx->HsInterface; + + /* DMA controller must be enabled before initializing the channel */ + DMA_ControllerCmd(spi_bus_obj[i].config->dma_tx->Instance, ENABLE); + + /* Initialize the specified DMA channel and Whether the specified channel was successfully initialized */ + if (DMA_ChannelInit(spi_bus_obj[i].config->dma_tx->Instance, &spi_bus_obj[i].dma.TX_DMA_ChInitStr, spi_bus_obj[i].config->dma_tx->dma_channel) == 0U) + { + /* Configure DMAMUX */ + DMAMUX_SetRequestID(DMAMUX1_ID, spi_bus_obj[i].config->dma_tx->dmamux_channel, spi_bus_obj[i].config->dma_tx->dmamux_request); + + spi_bus_obj[i].dma.DMA_Tx_Init = RT_TRUE; + } + else + { + LOG_E("SPI TX DMA channel initialization failed!"); + return -RT_ERROR; + } +#endif + } + + + /* initialize completion object */ + rt_completion_init(&spi_bus_obj[i].cpt); + + result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &n32_spi_ops); + RT_ASSERT(result == RT_EOK); + + LOG_D("%s bus init done", spi_config[i].bus_name); + } + + return result; +} + + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL); + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + + RT_ASSERT(result == RT_EOK); + + LOG_D("%s attach to %s done", device_name, bus_name); + + return result; +} + + +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI1_TX_USING_DMA) || \ + defined(BSP_SPI2_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || \ + defined(BSP_SPI3_RX_USING_DMA) || defined(BSP_SPI3_TX_USING_DMA) || \ + defined(BSP_SPI4_RX_USING_DMA) || defined(BSP_SPI4_TX_USING_DMA) || \ + defined(BSP_SPI5_RX_USING_DMA) || defined(BSP_SPI5_TX_USING_DMA) || \ + defined(BSP_SPI6_RX_USING_DMA) || defined(BSP_SPI6_TX_USING_DMA) || \ + defined(BSP_SPI7_RX_USING_DMA) || defined(BSP_SPI7_TX_USING_DMA) +static void spi_isr(struct n32_spi *spi_drv) +{ + if (SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG) == SET) + { + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_TX | SPI_I2S_DMA_RX, DISABLE); + + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelEventCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); +#endif + } + + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelEventCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); +#endif + } + + SPI_I2S_EnableInt(spi_drv->config->SPIx, SPI_I2S_INT_ERR, DISABLE); + + SPI_I2S_ReceiveData(spi_drv->config->SPIx); + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + } +} + +#if defined(BSP_SPI1_RX_USING_DMA) || \ + defined(BSP_SPI2_RX_USING_DMA) || \ + defined(BSP_SPI3_RX_USING_DMA) || \ + defined(BSP_SPI4_RX_USING_DMA) || \ + defined(BSP_SPI5_RX_USING_DMA) || \ + defined(BSP_SPI6_RX_USING_DMA) || \ + defined(BSP_SPI7_RX_USING_DMA) +static void spi_rx_dma_isr(struct n32_spi *spi_drv) +{ +#if defined(SOC_SERIES_N32H7xx) + if (DMA_GetCombinedStatus(spi_drv->config->dma_rx->Instance)) + { + if (DMA_GetChannelIntTfrStatus(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel) == SET) + { +#endif + if (spi_drv->Direct == SPI_Tx_Rx) + { + SPI_I2S_EnableInt(spi_drv->config->SPIx, SPI_I2S_INT_ERR, DISABLE); + +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelEventCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); + DMA_ChannelEventCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); +#endif + + if (spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER && spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_FULLDUPLEX) + { + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_TX | SPI_I2S_DMA_RX, DISABLE); + } + + SPI_I2S_ReceiveData(spi_drv->config->SPIx); + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + + spi_drv->Direct = SPI_Idle; + rt_completion_done(&spi_drv->cpt); + } + else if (spi_drv->Direct == SPI_Rx) + { + if (spi_drv->SPI_InitStructure.SpiMode == SPI_MODE_MASTER && (spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_SINGLELINE_RX || + spi_drv->SPI_InitStructure.DataDirection == SPI_DIR_DOUBLELINE_RONLY)) + { + SPI_Enable(spi_drv->config->SPIx, DISABLE); + } + + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_RX, DISABLE); + + SPI_I2S_EnableInt(spi_drv->config->SPIx, SPI_I2S_INT_ERR, DISABLE); + +#if defined(SOC_SERIES_N32H7xx) + DMA_ChannelEventCmd(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); +#endif + + SPI_I2S_ReceiveData(spi_drv->config->SPIx); + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + + spi_drv->Direct = SPI_Idle; + rt_completion_done(&spi_drv->cpt); + } + +#if defined(SOC_SERIES_N32H7xx) + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(spi_drv->config->dma_rx->Instance, spi_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE); +#endif + } + } +} +#endif + +static void spi_tx_dma_isr(struct n32_spi *spi_drv) +{ +#if defined(SOC_SERIES_N32H7xx) + if (DMA_GetCombinedStatus(spi_drv->config->dma_tx->Instance)) + { + if (DMA_GetChannelIntTfrStatus(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel) == SET) + { +#endif + if (spi_drv->Direct == SPI_Tx) + { + DMA_ChannelEventCmd(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); + + SPI_I2S_EnableDma(spi_drv->config->SPIx, SPI_I2S_DMA_TX, DISABLE); + + SPI_I2S_ReceiveData(spi_drv->config->SPIx); + SPI_I2S_GetStatus(spi_drv->config->SPIx, SPI_I2S_OVER_FLAG); + + spi_drv->Direct = SPI_Idle; + rt_completion_done(&spi_drv->cpt); + } + + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(spi_drv->config->dma_tx->Instance, spi_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE); + } + } +} +#endif + +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) +void SPI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) */ +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) +void SPI1_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA) */ +#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) +void SPI1_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA) */ + + +#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) +void SPI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) */ +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) +void SPI2_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA) */ +#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) +void SPI2_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA) */ + + + +#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA) +void SPI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA) */ +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA) +void SPI3_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA) */ +#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA) +void SPI3_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA) */ + + + +#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA) +void SPI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA) */ +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA) +void SPI4_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA) */ +#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA) +void SPI4_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA) */ + + + + +#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA) +void SPI5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA) */ +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA) +void SPI5_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA) */ +#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA) +void SPI5_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA) */ + + + + +#if defined(BSP_SPI6_TX_USING_DMA) || defined(BSP_SPI6_RX_USING_DMA) +void SPI6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI6_TX_USING_DMA) || defined(BSP_SPI6_RX_USING_DMA) */ +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA) +void SPI6_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA) */ +#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA) +void SPI6_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA) */ + + + +#if defined(BSP_SPI7_TX_USING_DMA) || defined(BSP_SPI7_RX_USING_DMA) +void SPI7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_isr(&spi_bus_obj[SPI7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_SPI7_TX_USING_DMA) || defined(BSP_SPI7_RX_USING_DMA) */ +#if defined(BSP_USING_SPI7) && defined(BSP_SPI7_RX_USING_DMA) +void SPI7_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_rx_dma_isr(&spi_bus_obj[SPI7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI7) && defined(BSP_SPI7_RX_USING_DMA) */ +#if defined(BSP_USING_SPI7) && defined(BSP_SPI7_TX_USING_DMA) +void SPI7_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + spi_tx_dma_isr(&spi_bus_obj[SPI7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(BSP_USING_SPI7) && defined(BSP_SPI7_TX_USING_DMA) */ + +static void n32_spi_get_dma_config(void) +{ +#ifdef BSP_USING_SPI1 + spi_bus_obj[SPI1_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI1_RX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; +#endif /* BSP_SPI1_RX_USING_DMA */ +#ifdef BSP_SPI1_TX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; +#endif /* BSP_SPI1_TX_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI2 + spi_bus_obj[SPI2_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI2_RX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; +#endif /* BSP_SPI2_RX_USING_DMA */ +#ifdef BSP_SPI2_TX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; +#endif /* BSP_SPI2_TX_USING_DMA */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_USING_SPI3 + spi_bus_obj[SPI3_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI3_RX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; +#endif /* BSP_SPI3_RX_USING_DMA */ +#ifdef BSP_SPI3_TX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; +#endif /* BSP_SPI3_TX_USING_DMA */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_USING_SPI4 + spi_bus_obj[SPI4_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI4_RX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; +#endif /* BSP_SPI4_RX_USING_DMA */ +#ifdef BSP_SPI4_TX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; +#endif /* BSP_SPI4_TX_USING_DMA */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_USING_SPI5 + spi_bus_obj[SPI5_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI5_RX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; +#endif /* BSP_SPI5_RX_USING_DMA */ +#ifdef BSP_SPI5_TX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; +#endif /* BSP_SPI5_TX_USING_DMA */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_USING_SPI6 + spi_bus_obj[SPI6_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI6_RX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; +#endif /* BSP_SPI6_RX_USING_DMA */ +#ifdef BSP_SPI6_TX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; +#endif /* BSP_SPI6_TX_USING_DMA */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_USING_SPI7 + spi_bus_obj[SPI7_INDEX].spi_dma_flag = 0; +#ifdef BSP_SPI7_RX_USING_DMA + spi_bus_obj[SPI7_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi7_dma_rx = SPI7_RX_DMA_CONFIG; + spi_config[SPI7_INDEX].dma_rx = &spi7_dma_rx; +#endif /* BSP_SPI7_RX_USING_DMA */ +#ifdef BSP_SPI7_TX_USING_DMA + spi_bus_obj[SPI7_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi7_dma_tx = SPI7_TX_DMA_CONFIG; + spi_config[SPI7_INDEX].dma_tx = &spi7_dma_tx; +#endif /* BSP_SPI7_TX_USING_DMA */ +#endif /* BSP_USING_SPI7 */ +} + + +int rt_hw_spi_init(void) +{ + n32_spi_get_dma_config(); + return rt_hw_spi_bus_init(); +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + + +#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 || BSP_USING_SPI6 || BSP_USING_SPI7 */ +#endif /* BSP_USING_SPI */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h new file mode 100644 index 0000000000..d34d610bed --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_spi.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include "rtdevice.h" +#include +#include +#include "drv_dma.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); + +#ifdef __cplusplus +} +#endif + +struct n32_spi_config +{ + SPI_Module *SPIx; + char *bus_name; + IRQn_Type irq_type; + struct dma_config *dma_rx, *dma_tx; +}; + +struct n32_spi_device +{ + rt_uint32_t pin; + char *bus_name; + char *device_name; +}; + + +#define SPI_USING_RX_DMA_FLAG (1<<0) +#define SPI_USING_TX_DMA_FLAG (1<<1) + +typedef enum +{ + SPI_Tx_Rx = 0U, + SPI_Tx, + SPI_Rx, + SPI_Idle, +} SPI_Work_Direct_t; + +/* n32 spi dirver class */ +struct n32_spi +{ + struct n32_spi_config *config; + struct rt_spi_configuration *cfg; + + SPI_InitType SPI_InitStructure; + SPI_Work_Direct_t Direct; + + struct + { + rt_bool_t DMA_Tx_Init; + DMA_ChInitType TX_DMA_ChInitStr; + + rt_bool_t DMA_Rx_Init; + DMA_ChInitType RX_DMA_ChInitStr; + } dma; + + rt_uint8_t spi_dma_flag; + struct rt_spi_bus spi_bus; + + struct rt_completion cpt; +}; + +#endif /*__DRV_SPI_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c new file mode 100644 index 0000000000..a32b9ff8ab --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c @@ -0,0 +1,1699 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + + +#include "board.h" +#include "drv_usart.h" +#include "drv_config.h" + +#ifdef RT_USING_SERIAL + +//#define DRV_DEBUG +#define LOG_TAG "drv.usart" +#include + + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_UART9) && \ + !defined(BSP_USING_UART10) && !defined(BSP_USING_UART11) && !defined(BSP_USING_UART12) && \ + !defined(BSP_USING_UART13) && !defined(BSP_USING_UART14) && !defined(BSP_USING_UART15) && \ + !defined(BSP_USING_LPUART1) && !defined(BSP_USING_LPUART2) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +#ifdef RT_SERIAL_USING_DMA + static rt_err_t UART_DMA_Transmit(struct n32_uart *uart); +#endif + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif +#ifdef BSP_USING_UART8 + UART8_INDEX, +#endif +#ifdef BSP_USING_UART9 + UART9_INDEX, +#endif +#ifdef BSP_USING_UART10 + UART10_INDEX, +#endif +#ifdef BSP_USING_UART11 + UART11_INDEX, +#endif +#ifdef BSP_USING_UART12 + UART12_INDEX, +#endif +#ifdef BSP_USING_UART13 + UART13_INDEX, +#endif +#ifdef BSP_USING_UART14 + UART14_INDEX, +#endif +#ifdef BSP_USING_UART15 + UART15_INDEX, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_INDEX, +#endif +#ifdef BSP_USING_LPUART2 + LPUART2_INDEX, +#endif +}; + +static struct n32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +#ifdef BSP_USING_UART5 + UART5_CONFIG, +#endif +#ifdef BSP_USING_UART6 + UART6_CONFIG, +#endif +#ifdef BSP_USING_UART7 + UART7_CONFIG, +#endif +#ifdef BSP_USING_UART8 + UART8_CONFIG, +#endif +#ifdef BSP_USING_UART9 + UART9_CONFIG, +#endif +#ifdef BSP_USING_UART10 + UART10_CONFIG, +#endif +#ifdef BSP_USING_UART11 + UART11_CONFIG, +#endif +#ifdef BSP_USING_UART12 + UART12_CONFIG, +#endif +#ifdef BSP_USING_UART13 + UART13_CONFIG, +#endif +#ifdef BSP_USING_UART14 + UART14_CONFIG, +#endif +#ifdef BSP_USING_UART15 + UART15_CONFIG, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_CONFIG, +#endif +#ifdef BSP_USING_LPUART2 + LPUART2_CONFIG, +#endif +}; + +static struct n32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = { 0 }; + +#ifdef RT_SERIAL_USING_DMA +static void dma_recv_callback(struct rt_serial_device *serial, rt_uint8_t isr_flag) +{ + struct n32_uart *uart; + rt_base_t level; + rt_size_t recv_len, read_len; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + level = rt_hw_interrupt_disable(); + recv_len = 0; + + read_len = DMA_GetTransferredNumber(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel); + + switch (isr_flag) + { + case UART_RX_DMA_IT_IDLE_FLAG: + { + if (uart->dma.rx_dma.block_has_recv_cnt != 0) + { + recv_len = read_len - uart->dma.rx_dma.block_has_recv_cnt; + } + else + { + recv_len = read_len; + } + uart->dma.rx_dma.block_has_recv_cnt = read_len; + + break; + } + case UART_RX_DMA_IT_BLOCK_TC_FLAG: + { + if (uart->dma.rx_dma.block_has_recv_cnt != 0) + { + recv_len = read_len - uart->dma.rx_dma.block_has_recv_cnt; + uart->dma.rx_dma.block_has_recv_cnt = 0; + } + else + { + recv_len = DMA_BLOCK_SIZE; + } + break; + } + + default: + break; + } + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + rt_hw_interrupt_enable(level); +} + + +#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ + defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || \ + defined(BSP_UART7_RX_USING_DMA) || defined(BSP_UART8_RX_USING_DMA) || defined(BSP_UART9_RX_USING_DMA) || \ + defined(BSP_UART10_RX_USING_DMA) || defined(BSP_UART11_RX_USING_DMA) || defined(BSP_UART12_RX_USING_DMA) || \ + defined(BSP_UART13_RX_USING_DMA) || defined(BSP_UART14_RX_USING_DMA) || defined(BSP_UART15_RX_USING_DMA) + +static void uart_rx_dma_isr(struct n32_uart *uart_drv) +{ +#if defined(SOC_SERIES_N32H7xx) + if (DMA_GetCombinedStatus(uart_drv->config->dma_rx->Instance)) + { + if (DMA_GetChannelIntBlockStatus(uart_drv->config->dma_rx->Instance, uart_drv->config->dma_rx->dma_channel) != RESET) + { + dma_recv_callback(&uart_drv->serial, UART_RX_DMA_IT_BLOCK_TC_FLAG); + + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(uart_drv->config->dma_rx->Instance, uart_drv->config->dma_rx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE); + } + } +#endif +} +#endif + +#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \ + defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART5_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || \ + defined(BSP_UART7_TX_USING_DMA) || defined(BSP_UART8_TX_USING_DMA) || defined(BSP_UART9_TX_USING_DMA) || \ + defined(BSP_UART10_TX_USING_DMA) || defined(BSP_UART11_TX_USING_DMA) || defined(BSP_UART12_TX_USING_DMA) || \ + defined(BSP_UART13_TX_USING_DMA) || defined(BSP_UART14_TX_USING_DMA) || defined(BSP_UART15_TX_USING_DMA) + +static void uart_tx_dma_isr(struct n32_uart *uart_drv) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + +#if defined(SOC_SERIES_N32H7xx) + if (DMA_GetCombinedStatus(uart_drv->config->dma_tx->Instance)) + { + if (DMA_GetChannelIntTfrStatus(uart_drv->config->dma_tx->Instance, uart_drv->config->dma_tx->dma_channel) == SET) + { + DMA_ChannelEventCmd(uart_drv->config->dma_tx->Instance, uart_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, DISABLE); + + USART_EnableDMA(uart_drv->config->Instance, USART_DMAREQ_TX, DISABLE); + + DMA_ChannelCmd(uart_drv->config->dma_tx->Instance, uart_drv->config->dma_tx->dma_channel, DISABLE); + + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(uart_drv->config->dma_tx->Instance, uart_drv->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE); + + if (uart_drv->dma.tx_dma.already_send_length < uart_drv->dma.tx_dma.record_length) + { + UART_DMA_Transmit(uart_drv); + } + else + { + /* DMA TX Complete + * 1. All data has been completely transmitted. + */ + rt_hw_serial_isr(&uart_drv->serial, RT_SERIAL_EVENT_TX_DMADONE); + } + } + } +#endif + + rt_hw_interrupt_enable(level); +} +#endif /* RT_SERIAL_USING_DMA */ + + +static void N32_UART_DMA_Config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + rt_size_t i = 0; + rt_err_t result = RT_EOK; + struct n32_uart *uart; + struct rt_serial_rx_fifo *rx_fifo = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); + uart = rt_container_of(serial, struct n32_uart, serial); + + /* DMA Initialize */ + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + uart->dma.RX_DMA_ChInitStr.DstAddr = (uint32_t)rx_fifo->buffer; + + /* Set LLI control information */ + for (i = 0; i < uart->dma.rx_dma.block_num; i++) + { + uart->dma.rx_dma.Read_LinkList[i].DstAddr = (uint32_t)(((uint8_t *)rx_fifo->buffer) + i * DMA_BLOCK_SIZE); + } + + if (!DMA_ControllerIsEnabled(uart->config->dma_rx->Instance)) + DMA_ControllerCmd(uart->config->dma_rx->Instance, ENABLE); + + /* Initialize the specified DMA channel and Whether the specified channel was successfully initialized */ + if (DMA_ChannelInit(uart->config->dma_rx->Instance, &uart->dma.RX_DMA_ChInitStr, uart->config->dma_rx->dma_channel) == 0U) + { + /* Enable the specified DMA channel interrupt event */ + DMA_ChannelEventCmd(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel, DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE, ENABLE); + + /* Configure DMAMUX */ + DMAMUX_SetRequestID(DMAMUX1_ID, uart->config->dma_rx->dmamux_channel, uart->config->dma_rx->dmamux_request); + + uart->dma.DMA_Rx_Init = RT_TRUE; + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel, ENABLE); + + /* enable dma irq */ + NVIC_SetPriority(uart->config->dma_rx->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_EnableIRQ(uart->config->dma_rx->dma_irq); + } + else + { + LOG_E("%s RX DMA channel initialization failed!", uart->config->name); + result = -RT_ERROR; + } + + RT_ASSERT(result == RT_EOK) + + /* Enable the USART idle interrupts */ + USART_ConfigInt(uart->config->Instance, USART_INT_IDLEF, ENABLE); + + /* Enables the USART's DMA interface */ + USART_EnableDMA(uart->config->Instance, USART_DMAREQ_RX, ENABLE); + } + + /* enable uart irq */ + NVIC_SetPriority(uart->config->irq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0)); + NVIC_EnableIRQ(uart->config->irq_type); +} + +static rt_err_t UART_DMA_Transmit(struct n32_uart *uart) +{ + rt_uint16_t send_length; + rt_size_t already_send_length; + const rt_uint8_t *send_buf = RT_NULL; + + RT_ASSERT(uart != RT_NULL); + + if (uart->dma.DMA_Tx_Init == RT_TRUE) + { +#if defined(SOC_SERIES_N32H7xx) + /* DMA uses a single block, with a maximum of 4095 per block */ + if (uart->dma.tx_dma.total_length > 4095U) + { + send_length = 4095U; + uart->dma.tx_dma.total_length = uart->dma.tx_dma.total_length - 4095U; + } + else + { + send_length = uart->dma.tx_dma.total_length; + uart->dma.tx_dma.total_length = 0; + } + + /* Calculate the length sent after this transmission is complete */ + uart->dma.tx_dma.already_send_length += send_length; + /* calculate the start address */ + already_send_length = uart->dma.tx_dma.record_length - send_length - uart->dma.tx_dma.total_length; + send_buf = uart->dma.tx_dma.buf + already_send_length; + + DMA_ChannelCmd(uart->config->dma_tx->Instance, uart->config->dma_tx->dma_channel, DISABLE); + + if (!DMA_ControllerIsEnabled(uart->config->dma_tx->Instance)) + DMA_ControllerCmd(uart->config->dma_tx->Instance, ENABLE); + + uart->dma.TX_DMA_ChInitStr.IntEn = 1U; + uart->dma.TX_DMA_ChInitStr.SrcAddr = (uint32_t)send_buf; + uart->dma.TX_DMA_ChInitStr.BlkTfrSize = send_length; + + DMA_ControllerCmd(uart->config->dma_tx->Instance, ENABLE); + if (DMA_ChannelInit(uart->config->dma_tx->Instance, &uart->dma.TX_DMA_ChInitStr, uart->config->dma_tx->dma_channel) == 0U) + { + /* Enable transaction complete interrupt event */ + DMA_ChannelEventCmd(uart->config->dma_tx->Instance, uart->config->dma_tx->dma_channel, DMA_CH_EVENT_TRANSFER_COMPLETE, ENABLE); + + /* Enable the specified DMA channel */ + DMA_ChannelCmd(uart->config->dma_tx->Instance, uart->config->dma_tx->dma_channel, ENABLE); + + /* Clears the USARTx's USART_FLAG_TXC flags */ + USART_ClrFlag(uart->config->Instance, USART_FLAG_TXC); + + /* Enables the USART's DMA interface */ + USART_EnableDMA(uart->config->Instance, USART_DMAREQ_TX, ENABLE); + + USART_Enable(uart->config->Instance, ENABLE); + } +#endif + } + else + { + LOG_E("UART TX DMA Mode, TX DMA did not complete initialization."); + return -RT_ERROR; + } + + return RT_EOK; +} +#endif /* RT_SERIAL_USING_DMA */ + + +rt_uint32_t n32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) +{ + rt_uint32_t mask = 0x00FFU; + if (word_length == USART_WL_8B) + { + if (parity == USART_PE_NO) + { + mask = 0x00FFU ; + } + else + { + mask = 0x007FU ; + } + } +#ifdef USART_WL_9B + else if (word_length == USART_WL_9B) + { + if (parity == USART_PE_NO) + { + mask = 0x01FFU ; + } + else + { + mask = 0x00FFU ; + } + } +#endif + return mask; +} + +static rt_err_t n32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct n32_uart *uart; + USART_InitType USART_InitStructure; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct n32_uart, serial); + + /* Enable UART Clock */ + uart->config->EnablePeriphClk(uart->config->periph, ENABLE); + + USART_StructInit(&USART_InitStructure); + USART_InitStructure.BaudRate = cfg->baud_rate; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + +#if defined(SOC_SERIES_N32H7) +#ifdef USART_CTRL1_OSPM +#endif + USART_InitStructure.OverSampling = cfg->baud_rate > 5000000 ? USART_8OVER : USART_16OVER; +#else + USART_InitStructure.OverSampling = USART_16OVER; +#endif /* USART_CTRL1_OSPM */ + + switch (cfg->flowcontrol) + { + case RT_SERIAL_FLOWCONTROL_NONE: + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + break; + case RT_SERIAL_FLOWCONTROL_CTSRTS: + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_RTS_CTS; + break; + default: + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + break; + } + + switch (cfg->data_bits) + { + case DATA_BITS_8: + if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) + USART_InitStructure.WordLength = USART_WL_9B; + else + USART_InitStructure.WordLength = USART_WL_8B; + break; + case DATA_BITS_9: + USART_InitStructure.WordLength = USART_WL_9B; + break; + default: + USART_InitStructure.WordLength = USART_WL_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + USART_InitStructure.StopBits = USART_STPB_1; + break; + case STOP_BITS_2: + USART_InitStructure.StopBits = USART_STPB_2; + break; + default: + USART_InitStructure.StopBits = USART_STPB_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + USART_InitStructure.Parity = USART_PE_NO; + break; + case PARITY_ODD: + USART_InitStructure.Parity = USART_PE_ODD; + break; + case PARITY_EVEN: + USART_InitStructure.Parity = USART_PE_EVEN; + break; + default: + USART_InitStructure.Parity = USART_PE_NO; + break; + } + +#ifdef RT_SERIAL_USING_DMA + if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) + { + uart->dma.rx_dma.block_has_recv_cnt = 0; + } +#endif + + USART_Init(uart->config->Instance, &USART_InitStructure); + + USART_Enable(uart->config->Instance, ENABLE); + + uart->DR_mask = n32_uart_get_mask(USART_InitStructure.WordLength, USART_InitStructure.Parity); + + return RT_EOK; +} + + +static rt_err_t n32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct n32_uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->config->irq_type); + /* disable interrupt */ + USART_ConfigInt(uart->config->Instance, USART_INT_RXDNE, DISABLE); + +#ifdef RT_SERIAL_USING_DMA + /* disable DMA */ + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) + { + NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); + + DMA_ChannelCmd(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel, DISABLE); + + USART_EnableDMA(uart->config->Instance, USART_DMAREQ_RX, DISABLE); + + rt_free(uart->dma.rx_dma.Read_LinkList); + uart->dma.rx_dma.Read_LinkList = RT_NULL; + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) + { + NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); + + DMA_ChannelCmd(uart->config->dma_rx->Instance, uart->config->dma_rx->dma_channel, DISABLE); + + USART_EnableDMA(uart->config->Instance, USART_DMAREQ_TX, DISABLE); + } +#endif + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_SetPriority(uart->config->irq_type, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0)); + NVIC_EnableIRQ(uart->config->irq_type); + /* enable interrupt */ + USART_ConfigInt(uart->config->Instance, USART_INT_RXDNE, ENABLE); + break; + +#ifdef RT_SERIAL_USING_DMA + case RT_DEVICE_CTRL_CONFIG: + N32_UART_DMA_Config(serial, ctrl_arg); + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + USART_DeInit(uart->config->Instance); + /* Enable UART Clock */ + uart->config->EnablePeriphClk(uart->config->periph, DISABLE); + break; + + } + return RT_EOK; +} + +static int n32_putc(struct rt_serial_device *serial, char c) +{ + struct n32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct n32_uart, serial); + + /* Clear transmission complete flag */ + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) != RESET) + USART_ClrFlag(uart->config->Instance, USART_FLAG_TXC); + + /* Send data */ + USART_SendData(uart->config->Instance, c); + + while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) == RESET) + { + } + + return 1; +} + +static int n32_getc(struct rt_serial_device *serial) +{ + int ch; + struct n32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + ch = -1; + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXDNE) != RESET) + { + ch = USART_ReceiveData(uart->config->Instance); + } + return ch; +} + +static rt_ssize_t n32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + struct n32_uart *uart = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + RT_ASSERT(uart != RT_NULL); + if (size == 0) + { + return 0; + } + +#ifdef RT_SERIAL_USING_DMA + if (RT_SERIAL_DMA_TX == direction) + { + uart->dma.tx_dma.record_length = size; + uart->dma.tx_dma.total_length = size; + uart->dma.tx_dma.already_send_length = 0U; + uart->dma.tx_dma.buf = buf; + + /* start once data exchange in DMA mode */ + UART_DMA_Transmit(uart); + } +#endif + + return size; +} + +static void uart_isr(struct rt_serial_device *serial) +{ + struct n32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct n32_uart, serial); + + /* UART in mode Receiver */ + if ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXDNE) != RESET) && + (USART_GetIntStatus(uart->config->Instance, USART_INT_RXDNE) != RESET)) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } +#ifdef RT_SERIAL_USING_DMA + else if ((uart->uart_dma_flag) && + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_IDLEF) != RESET) && + (USART_GetIntStatus(uart->config->Instance, USART_INT_IDLEF) != RESET)) + { + dma_recv_callback(serial, UART_RX_DMA_IT_IDLE_FLAG); + USART_GetFlagStatus(uart->config->Instance, USART_FLAG_IDLEF); + USART_ReceiveData(uart->config->Instance); + } + else if ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXC) != RESET) && + (USART_GetIntStatus(uart->config->Instance, USART_INT_TXC) != RESET)) + { + USART_ClrFlag(uart->config->Instance, USART_FLAG_TXC); + } +#endif + else + { + if ((USART_GetFlagStatus(uart->config->Instance, USART_FLAG_OREF) != RESET) || + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_NEF) != RESET) || + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_FEF) != RESET) || + (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_PEF) != RESET)) + { + USART_GetFlagStatus(uart->config->Instance, USART_FLAG_OREF | USART_FLAG_NEF | USART_FLAG_FEF | USART_FLAG_PEF); + USART_ReceiveData(uart->config->Instance); + } + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_LINBD) != RESET) + { + USART_ClrFlag(uart->config->Instance, USART_FLAG_LINBD); + } + + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_CTSF) != RESET) + { + USART_ClrFlag(uart->config->Instance, USART_FLAG_CTSF); + } + + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXDE) != RESET) + { + USART_ClrFlag(uart->config->Instance, USART_FLAG_CTSF); + } + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXDNE) != RESET) + { + USART_ClrFlag(uart->config->Instance, USART_FLAG_RXDNE); + } + } +} + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART1_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) && defined(UART1_RX_DMA_IRQHandler) +void UART1_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) && defined(UART1_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) && defined(UART1_TX_DMA_IRQHandler) +void UART1_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) && defined(UART1_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART2_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) && defined(UART2_RX_DMA_IRQHandler) +void UART2_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) && defined(UART2_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) && defined(UART2_TX_DMA_IRQHandler) +void UART2_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) && defined(UART2_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART3_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) && defined(UART3_RX_DMA_IRQHandler) +void UART3_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) && defined(UART3_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) && defined(UART3_TX_DMA_IRQHandler) +void UART3_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) && defined(UART3_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +void USART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART4_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) && defined(UART4_RX_DMA_IRQHandler) +void UART4_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) && defined(UART4_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) && defined(UART4_TX_DMA_IRQHandler) +void UART4_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA) && defined(UART4_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +void USART5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART5_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) && defined(UART5_RX_DMA_IRQHandler) +void UART5_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) && defined(UART5_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) && defined(UART5_TX_DMA_IRQHandler) +void UART5_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) && defined(UART5_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +void USART6_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART6_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) && defined(UART6_RX_DMA_IRQHandler) +void UART6_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) && defined(UART6_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) && defined(UART6_TX_DMA_IRQHandler) +void UART6_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) && defined(UART6_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +void USART7_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART7_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) && defined(UART7_RX_DMA_IRQHandler) +void UART7_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) && defined(UART7_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) && defined(UART7_TX_DMA_IRQHandler) +void UART7_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) && defined(UART7_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +void USART8_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART8_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) && defined(UART8_RX_DMA_IRQHandler) +void UART8_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) && defined(UART8_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) && defined(UART8_TX_DMA_IRQHandler) +void UART8_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) && defined(UART8_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +void UART9_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART9_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_RX_USING_DMA) && defined(UART9_RX_DMA_IRQHandler) +void UART9_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_RX_USING_DMA) && defined(UART9_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_TX_USING_DMA) && defined(UART9_TX_DMA_IRQHandler) +void UART9_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART9_TX_USING_DMA) && defined(UART9_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +void UART10_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART10_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_RX_USING_DMA) && defined(UART10_RX_DMA_IRQHandler) +void UART10_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_RX_USING_DMA) && defined(UART10_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_TX_USING_DMA) && defined(UART10_TX_DMA_IRQHandler) +void UART10_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART10_TX_USING_DMA) && defined(UART10_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_UART11) +void UART11_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART11_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART11_RX_USING_DMA) && defined(UART11_RX_DMA_IRQHandler) +void UART11_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART11_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART11_RX_USING_DMA) && defined(UART11_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART11_TX_USING_DMA) && defined(UART11_TX_DMA_IRQHandler) +void UART11_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART11_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART11_TX_USING_DMA) && defined(UART11_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART11 */ + +#if defined(BSP_USING_UART12) +void UART12_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART12_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART12_RX_USING_DMA) && defined(UART12_RX_DMA_IRQHandler) +void UART12_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART12_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART12_RX_USING_DMA) && defined(UART12_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART12_TX_USING_DMA) && defined(UART12_TX_DMA_IRQHandler) +void UART12_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART12_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART12_TX_USING_DMA) && defined(UART12_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART12 */ + +#if defined(BSP_USING_UART13) +void UART13_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART13_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART13_RX_USING_DMA) && defined(UART13_RX_DMA_IRQHandler) +void UART13_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART13_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART13_RX_USING_DMA) && defined(UART13_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART13_TX_USING_DMA) && defined(UART13_TX_DMA_IRQHandler) +void UART13_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART13_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART13_TX_USING_DMA) && defined(UART13_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART13 */ + +#if defined(BSP_USING_UART14) +void UART14_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART14_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART14_RX_USING_DMA) && defined(UART14_RX_DMA_IRQHandler) +void UART14_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART14_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART14_RX_USING_DMA) && defined(UART14_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART14_TX_USING_DMA) && defined(UART14_TX_DMA_IRQHandler) +void UART14_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART14_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART14_TX_USING_DMA) && defined(UART14_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART14 */ + +#if defined(BSP_USING_UART15) +void UART15_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&(uart_obj[UART15_INDEX].serial)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART15_RX_USING_DMA) && defined(UART15_RX_DMA_IRQHandler) +void UART15_RX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_rx_dma_isr(&uart_obj[UART15_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART15_RX_USING_DMA) && defined(UART15_RX_DMA_IRQHandler) */ +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART15_TX_USING_DMA) && defined(UART15_TX_DMA_IRQHandler) +void UART15_TX_DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_tx_dma_isr(&uart_obj[UART15_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART15_TX_USING_DMA) && defined(UART15_TX_DMA_IRQHandler) */ +#endif /* BSP_USING_UART15 */ + +static void n32_uart_get_dma_config(void) +{ +#ifdef BSP_USING_UART1 + uart_obj[UART1_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; + uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; +#endif +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; + uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART2 + uart_obj[UART2_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; + uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; +#endif +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; + uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART3 + uart_obj[UART3_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART3_RX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; + uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx; +#endif +#ifdef BSP_UART3_TX_USING_DMA + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG; + uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART4 + uart_obj[UART4_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART4_RX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; + uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; +#endif +#ifdef BSP_UART4_TX_USING_DMA + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG; + uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART5 + uart_obj[UART5_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif +#ifdef BSP_UART5_TX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; + uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx; +#endif +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG; + uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG; + uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx; +#endif +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG; + uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART8 + uart_obj[UART8_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART8_RX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart8_dma_rx = UART8_DMA_RX_CONFIG; + uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx; +#endif +#ifdef BSP_UART8_TX_USING_DMA + uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart8_dma_tx = UART8_DMA_TX_CONFIG; + uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART9 + uart_obj[UART9_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART9_RX_USING_DMA + uart_obj[UART9_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart9_dma_rx = UART9_DMA_RX_CONFIG; + uart_config[UART9_INDEX].dma_rx = &uart9_dma_rx; +#endif +#ifdef BSP_UART9_TX_USING_DMA + uart_obj[UART9_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart9_dma_tx = UART9_DMA_TX_CONFIG; + uart_config[UART9_INDEX].dma_tx = &uart9_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART10 + uart_obj[UART10_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART10_RX_USING_DMA + uart_obj[UART10_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart10_dma_rx = UART10_DMA_RX_CONFIG; + uart_config[UART10_INDEX].dma_rx = &uart10_dma_rx; +#endif +#ifdef BSP_UART10_TX_USING_DMA + uart_obj[UART10_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart10_dma_tx = UART10_DMA_TX_CONFIG; + uart_config[UART10_INDEX].dma_tx = &uart10_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART11 + uart_obj[UART11_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART11_RX_USING_DMA + uart_obj[UART11_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart11_dma_rx = UART11_DMA_RX_CONFIG; + uart_config[UART11_INDEX].dma_rx = &uart11_dma_rx; +#endif +#ifdef BSP_UART11_TX_USING_DMA + uart_obj[UART11_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart11_dma_tx = UART11_DMA_TX_CONFIG; + uart_config[UART11_INDEX].dma_tx = &uart11_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART12 + uart_obj[UART12_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART12_RX_USING_DMA + uart_obj[UART12_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart12_dma_rx = UART12_DMA_RX_CONFIG; + uart_config[UART12_INDEX].dma_rx = &uart12_dma_rx; +#endif +#ifdef BSP_UART12_TX_USING_DMA + uart_obj[UART12_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart12_dma_tx = UART12_DMA_TX_CONFIG; + uart_config[UART12_INDEX].dma_tx = &uart12_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART13 + uart_obj[UART13_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART13_RX_USING_DMA + uart_obj[UART13_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart13_dma_rx = UART13_DMA_RX_CONFIG; + uart_config[UART13_INDEX].dma_rx = &uart13_dma_rx; +#endif +#ifdef BSP_UART13_TX_USING_DMA + uart_obj[UART13_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart13_dma_tx = UART13_DMA_TX_CONFIG; + uart_config[UART13_INDEX].dma_tx = &uart13_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART14 + uart_obj[UART14_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART14_RX_USING_DMA + uart_obj[UART14_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart14_dma_rx = UART14_DMA_RX_CONFIG; + uart_config[UART14_INDEX].dma_rx = &uart14_dma_rx; +#endif +#ifdef BSP_UART14_TX_USING_DMA + uart_obj[UART14_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart14_dma_tx = UART14_DMA_TX_CONFIG; + uart_config[UART14_INDEX].dma_tx = &uart14_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART15 + uart_obj[UART15_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART15_RX_USING_DMA + uart_obj[UART15_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart15_dma_rx = UART15_DMA_RX_CONFIG; + uart_config[UART15_INDEX].dma_rx = &uart15_dma_rx; +#endif +#ifdef BSP_UART15_TX_USING_DMA + uart_obj[UART15_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart15_dma_tx = UART15_DMA_TX_CONFIG; + uart_config[UART15_INDEX].dma_tx = &uart15_dma_tx; +#endif +#endif +} + + + +static const struct rt_uart_ops n32_uart_ops = +{ + .configure = n32_configure, + .control = n32_control, + .putc = n32_putc, + .getc = n32_getc, + .dma_transmit = n32_dma_transmit +}; + +int rt_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + n32_uart_get_dma_config(); + + for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(struct n32_uart); i++) + { + /* init UART object */ + uart_obj[i].config = &uart_config[i]; + uart_obj[i].serial.ops = &n32_uart_ops; + uart_obj[i].serial.config = config; + +#ifdef RT_SERIAL_USING_DMA + if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { +#if defined(SOC_SERIES_N32H7xx) + /* Configure the UART TX DMA for Transmission process */ + /* Enable DMA clock */ + RCC_EnableAHB1PeriphClk3(uart_obj[i].config->dma_tx->dma_rcc, ENABLE); + /* Enable DMA MUXclock */ + RCC_EnableAHB1PeriphClk1(RCC_AHB1_PERIPHEN_M7_DMAMUX1, ENABLE); + + /* UART TX DMA Channel1 configuration ---------------------------------------------*/ + DMA_ChannelStructInit(&uart_obj[i].dma.TX_DMA_ChInitStr); + uart_obj[i].dma.TX_DMA_ChInitStr.IntEn = 0x1U; + uart_obj[i].dma.TX_DMA_ChInitStr.DstAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddr = NULL; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.TX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.TX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + uart_obj[i].dma.TX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherEn = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterEn = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_M2P_DMA; + uart_obj[i].dma.TX_DMA_ChInitStr.BlkTfrSize = 0U; + uart_obj[i].dma.TX_DMA_ChInitStr.pLinkListItem = NULL; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcGatherCount = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterInterval = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.DstScatterCount = 0x0U; + uart_obj[i].dma.TX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + uart_obj[i].dma.TX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + uart_obj[i].dma.TX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; + uart_obj[i].dma.TX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_HARDWARE; + uart_obj[i].dma.TX_DMA_ChInitStr.DstHsInterface = uart_obj[i].config->dma_tx->HsInterface; + + /* DMA controller must be enabled before initializing the channel */ + DMA_ControllerCmd(uart_obj[i].config->dma_tx->Instance, ENABLE); + + /* Initialize the specified DMA channel and Whether the specified channel was successfully initialized */ + if (DMA_ChannelInit(uart_obj[i].config->dma_tx->Instance, &uart_obj[i].dma.TX_DMA_ChInitStr, uart_obj[i].config->dma_tx->dma_channel) == 0U) + { + /* Configure DMAMUX */ + DMAMUX_SetRequestID(DMAMUX1_ID, uart_obj[i].config->dma_tx->dmamux_channel, uart_obj[i].config->dma_tx->dmamux_request); + + uart_obj[i].dma.DMA_Tx_Init = RT_TRUE; + + /* enable dma irq */ + NVIC_SetPriority(uart_obj[i].config->dma_tx->dma_irq, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); + NVIC_EnableIRQ(uart_obj[i].config->dma_tx->dma_irq); + } + else + { + LOG_E("%s TX DMA channel initialization failed!", uart_obj[i].config->name); + return -RT_ERROR; + } +#endif + } + + if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { +#if defined(SOC_SERIES_N32H7xx) + /* Calculate the number of blocks */ + if ((uart_obj[i].serial.config.bufsz % DMA_BLOCK_SIZE) != 0) + { + uart_obj[i].dma.rx_dma.block_num = uart_obj[i].serial.config.bufsz / DMA_BLOCK_SIZE + 1; + + /* Calculate the remain length */ + uart_obj[i].dma.rx_dma.remain_len = ((uart_obj[i].serial.config.bufsz > DMA_BLOCK_SIZE) ? + (uart_obj[i].serial.config.bufsz - DMA_BLOCK_SIZE * (uart_obj[i].dma.rx_dma.block_num - 1U)) : + uart_obj[i].serial.config.bufsz); + } + else + { + uart_obj[i].dma.rx_dma.block_num = uart_obj[i].serial.config.bufsz / DMA_BLOCK_SIZE; + + /* Calculate the remain length */ + uart_obj[i].dma.rx_dma.remain_len = 0; + } + + /* Request a LinkList address */ + uart_obj[i].dma.rx_dma.Read_LinkList = (DMA_LinkListItemType *)rt_malloc(sizeof(DMA_LinkListItemType) * uart_obj[i].dma.rx_dma.block_num); + if (uart_obj[i].dma.rx_dma.Read_LinkList == RT_NULL) + { + return -RT_ERROR; + } + + /* Configure the UART RX DMA for Transmission process */ + /* Enable DMA clock */ + RCC_EnableAHB1PeriphClk3(uart_obj[i].config->dma_rx->dma_rcc, ENABLE); + /* Enable DMA MUXclock */ + RCC_EnableAHB1PeriphClk1(RCC_AHB1_PERIPHEN_M7_DMAMUX1, ENABLE); + + /* UART RX DMA Channel1 configuration ---------------------------------------------*/ + DMA_ChannelStructInit(&uart_obj[i].dma.RX_DMA_ChInitStr); + uart_obj[i].dma.RX_DMA_ChInitStr.IntEn = 0x1U; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.RX_DMA_ChInitStr.DstAddr = NULL; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.RX_DMA_ChInitStr.DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.RX_DMA_ChInitStr.DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + uart_obj[i].dma.RX_DMA_ChInitStr.DstBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherEn = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterEn = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + uart_obj[i].dma.RX_DMA_ChInitStr.BlkTfrSize = DMA_BLOCK_SIZE; + uart_obj[i].dma.RX_DMA_ChInitStr.pLinkListItem = uart_obj[i].dma.rx_dma.Read_LinkList; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherInterval = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcGatherCount = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterInterval = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.DstScatterCount = 0x0U; + uart_obj[i].dma.RX_DMA_ChInitStr.TfrType = DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED; + uart_obj[i].dma.RX_DMA_ChInitStr.ChannelPriority = DMA_CH_PRIORITY_7; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcHandshaking = DMA_CH_SRC_HANDSHAKING_HARDWARE; + uart_obj[i].dma.RX_DMA_ChInitStr.DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; + uart_obj[i].dma.RX_DMA_ChInitStr.SrcHsInterface = uart_obj[i].config->dma_rx->HsInterface; + + /* Set LLI control information */ + for (rt_size_t j = 0; j < uart_obj[i].dma.rx_dma.block_num; j++) + { + /* Link List Config */ + uart_obj[i].dma.rx_dma.Read_LinkList[j].IntEn = 0x1U; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcAddr = (uint32_t)&uart_obj[i].config->Instance->DAT; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddr = NULL; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcBurstLen = DMA_CH_BURST_LENGTH_1; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcGatherEn = false; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstScatterEn = false; + uart_obj[i].dma.rx_dma.Read_LinkList[j].TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2M_DMA; + uart_obj[i].dma.rx_dma.Read_LinkList[j].BlkTfrSize = DMA_BLOCK_SIZE; + uart_obj[i].dma.rx_dma.Read_LinkList[j].DstLinkedListEn = true; + uart_obj[i].dma.rx_dma.Read_LinkList[j].SrcLinkedListEn = false; + + /* The last block, so need to link to first block */ + if ((j + 1U) == uart_obj[i].dma.rx_dma.block_num) + { + uart_obj[i].dma.rx_dma.Read_LinkList[j].pNext = &uart_obj[i].dma.rx_dma.Read_LinkList[0U]; + } + else + { + uart_obj[i].dma.rx_dma.Read_LinkList[j].pNext = &uart_obj[i].dma.rx_dma.Read_LinkList[j + 1U]; + } + + /* The last block and block size ≠ BLOCK_SIZE */ + if ((j + 1U) == uart_obj[i].dma.rx_dma.block_num && uart_obj[i].dma.rx_dma.remain_len != 0U) + { + uart_obj[i].dma.rx_dma.Read_LinkList[j].BlkTfrSize = uart_obj[i].dma.rx_dma.remain_len; + } + } + + /* DMA controller must be enabled before initializing the channel */ + DMA_ControllerCmd(uart_obj[i].config->dma_rx->Instance, ENABLE); +#endif + } +#endif /* RT_SERIAL_USING_DMA */ + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#endif /* RT_USING_SERIAL */ + diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h new file mode 100644 index 0000000000..4b77bf06f2 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" +#include +#include +#include "drv_dma.h" + +int rt_hw_usart_init(void); + +#define UART_RX_DMA_IT_IDLE_FLAG 0x00 +#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01 + +/* n32 config class */ +struct n32_uart_config +{ + const char *name; + USART_Module *Instance; + IRQn_Type irq_type; + uint32_t periph; + void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd); + struct dma_config *dma_rx; + struct dma_config *dma_tx; +}; + +/* n32 uart dirver class */ +struct n32_uart +{ + struct n32_uart_config *config; + rt_uint32_t DR_mask; + +#ifdef RT_SERIAL_USING_DMA + struct + { + rt_bool_t DMA_Tx_Init; + DMA_ChInitType TX_DMA_ChInitStr; + + struct + { + rt_size_t record_length; + rt_size_t total_length; + rt_size_t already_send_length; + + rt_uint8_t *buf; + } tx_dma; + + + rt_bool_t DMA_Rx_Init; + DMA_ChInitType RX_DMA_ChInitStr; + + struct + { + rt_uint16_t block_num; + rt_uint16_t remain_len; + rt_size_t block_has_recv_cnt; + DMA_LinkListItemType *Read_LinkList; + + } rx_dma; + + } dma; + +#endif + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c new file mode 100644 index 0000000000..df3bef0836 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include "drv_common.h" +#include + +#ifdef RT_USING_PIN + #include +#endif + +#ifdef RT_USING_SERIAL + #ifdef RT_USING_SERIAL_V2 + #include + #else + #include + #endif /* RT_USING_SERIAL */ +#endif /* RT_USING_SERIAL_V2 */ + +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +static __IO uint32_t uwTick; +static uint32_t _systick_ms = 1; + +/* SysTick configuration */ +void rt_hw_systick_init(void) +{ + RCC_ClocksTypeDef RCC_Clocks = { 0 }; + + /* Get clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + /* Set Systick */ + SysTick_Config(RCC_Clocks.M7ClkFreq / RT_TICK_PER_SECOND); + + NVIC_SetPriorityGrouping(SCB_AIRCR_PRIGROUP3); + NVIC_SetPriority(SysTick_IRQn, 0xFF); + + _systick_ms = 1000u / RT_TICK_PER_SECOND; + if (_systick_ms == 0) + _systick_ms = 1; +} + +void System_Tick_Increase(void) +{ + uwTick += _systick_ms; +} + +uint32_t System_Tick_Get(void) +{ + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + System_Tick_Increase(); + + return uwTick; +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + System_Tick_Increase(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void _Error_Handler(char *s, int num) +{ + /* USER CODE BEGIN Error_Handler */ + LOG_E("Error_Handler at file:%s num:%d", s, num); + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint64_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * (reload / (1000000 / RT_TICK_PER_SECOND)); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will initial N32 board. + */ +rt_weak void rt_hw_board_init(void) +{ +#ifdef BSP_SCB_ENABLE_I_CACHE + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); +#endif + +#ifdef BSP_SCB_ENABLE_D_CACHE + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); +#endif + + /* Initialize system */ + System_Initialize(); + + /* Initialize Systick */ + rt_hw_systick_init(); + +#if defined(RT_USING_HEAP) + /* Heap initialization */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + /* Set the shell console output device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO) + extern void rt_hw_console_init(void); + rt_hw_console_init(); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* Board underlying hardware initialization */ + rt_components_board_init(); +#endif +} diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h new file mode 100644 index 0000000000..9c98335468 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif /* RT_USING_DEVICE */ + +#ifdef __cplusplus +extern "C" { +#endif + +void _Error_Handler(char *s, int num); + +#ifndef Error_Handler +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/SConscript b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/SConscript new file mode 100644 index 0000000000..99695defbc --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/SConscript @@ -0,0 +1,15 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +group = [] +src = ['drv_gpio.c'] +path = [cwd] + +if GetDepend(['RT_USING_CONSOLE']): + src += ['drv_console.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c new file mode 100644 index 0000000000..311b680bab --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include +#include +#include + + +static USART_Module* USARTx; + +void rt_hw_console_init(void) +{ + USART_InitType USART_InitStructure; + + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE); + +#ifdef USART1 + if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart1") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1, ENABLE); + USARTx = USART1; + } +#endif /* USART1 */ +#ifdef USART2 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart2") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART2, ENABLE); + USARTx = USART2; + } +#endif /* USART2 */ +#ifdef USART3 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart3") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART3, ENABLE); + USARTx = USART3; + } +#endif /* USART3 */ +#ifdef USART4 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart4") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART4, ENABLE); + USARTx = USART4; + } +#endif /* USART4 */ +#ifdef USART5 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart5") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART5, ENABLE); + USARTx = USART5; + } +#endif /* USART5 */ +#ifdef USART6 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart6") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART6, ENABLE); + USARTx = USART6; + } +#endif /* USART6 */ +#ifdef USART7 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart7") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART7, ENABLE); + USARTx = USART7; + } +#endif /* USART7 */ +#ifdef USART8 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart8") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART8, ENABLE); + USARTx = USART8; + } +#endif /* USART8 */ +#ifdef UART9 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart9") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART9, ENABLE); + USARTx = UART9; + } +#endif /* UART9 */ +#ifdef UART10 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart10") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART10, ENABLE); + USARTx = UART10; + } +#endif /* UART10 */ +#ifdef UART11 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart11") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART11, ENABLE); + USARTx = UART11; + } +#endif /* UART11 */ +#ifdef UART12 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart12") == 0) + { + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART12, ENABLE); + USARTx = UART12; + } +#endif /* UART12 */ +#ifdef UART13 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart13") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_UART13, ENABLE); + USARTx = UART13; + } +#endif /* UART13 */ +#ifdef UART14 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart14") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_UART14, ENABLE); + USARTx = UART14; + } +#endif /* UART14 */ +#ifdef UART15 + else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart15") == 0) + { + RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_UART15, ENABLE); + USARTx = UART15; + } +#endif /* UART15 */ + else + { + RT_ASSERT(0); + } + + USART_DeInit(USARTx); + + USART_StructInit(&USART_InitStructure); + USART_InitStructure.BaudRate = 115200; + USART_InitStructure.WordLength = USART_WL_8B; + USART_InitStructure.StopBits = USART_STPB_1; + USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.OverSampling = USART_16OVER; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_Init(USARTx, &USART_InitStructure); + USART_Enable(USARTx, ENABLE); +} + +void rt_hw_console_output(const char *str) +{ + rt_size_t i = 0, size = 0; + + size = rt_strlen(str); + for (i = 0; i < size; i++) + { + if (*(str + i) == '\n') + { + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXC) == RESET); + + USART_SendData(USARTx, (uint8_t)'\r'); + } + + while (USART_GetFlagStatus(USARTx, USART_FLAG_TXC) == RESET); + + USART_SendData(USARTx, (uint8_t )(*(str + i))); + } +} + +char rt_hw_console_getchar(void) +{ + int ch = -1; + + if (USART_GetFlagStatus(USARTx, USART_FLAG_RXDNE) != SET) + { + ch = -1; + rt_thread_mdelay(10); + } + else + { + ch = USART_ReceiveData(USARTx); + } + return ch; +} diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.c new file mode 100644 index 0000000000..6fc6b4585e --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include "drv_gpio.h" +#include +#include + +#define GET_GPIOx(pin) ((GPIO_Module *)(rt_uint32_t)(pin & 0xFFFFFFFFULL)) +#define GET_GPIOPin(pin) ((uint16_t)(pin >> 32U)) + +void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode) +{ + GPIO_InitType GPIO_InitStructure; + GPIO_Module *GPIOx = GET_GPIOx(pin); + uint16_t GPIO_Pin = GET_GPIOPin(pin); + + RT_ASSERT(mode == PIN_MODE_OUTPUT || mode == PIN_MODE_INPUT || + mode == PIN_MODE_INPUT_PULLUP || mode == PIN_MODE_INPUT_PULLDOWN || + mode == PIN_MODE_OUTPUT_OD); + + switch((rt_ubase_t)GPIOx) + { + case (rt_ubase_t)GPIOA: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE); + break; + case (rt_ubase_t)GPIOB: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE); + break; + case (rt_ubase_t)GPIOC: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE); + break; +#ifdef GPIOD + case (rt_ubase_t)GPIOD: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE); + break; +#endif /* GPIOD */ +#ifdef GPIOE + case (rt_ubase_t)GPIOE: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE); + break; +#endif /* GPIOE */ +#ifdef GPIOF + case (rt_ubase_t)GPIOF: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE); + break; +#endif /* GPIOF */ +#ifdef GPIOG + case (rt_ubase_t)GPIOG: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE); + break; +#endif /* GPIOG */ +#ifdef GPIOH + case (rt_ubase_t)GPIOH: + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE); + break; +#endif /* GPIOH */ +#ifdef GPIOI + case (rt_ubase_t)GPIOI: + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE); + break; +#endif /* GPIOI */ +#ifdef GPIOj + case (rt_ubase_t)GPIOj: + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE); + break; +#endif /* GPIOj */ +#ifdef GPIOk + case (rt_ubase_t)GPIOk: + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE); + break; +#endif /* GPIOk */ + } + + GPIO_InitStruct(&GPIO_InitStructure); + GPIO_InitStructure.Pin = GPIO_Pin; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStructure.GPIO_Pull = GPIO_NO_PULL; + } + + GPIO_InitPeripheral(GPIOx, &GPIO_InitStructure); +} + +void rt_pin_write(rt_uint64_t pin, rt_uint8_t value) +{ + GPIO_Module *GPIOx = GET_GPIOx(pin); + uint16_t GPIO_Pin = GET_GPIOPin(pin); + + RT_ASSERT(value == PIN_LOW || value == PIN_HIGH); + + GPIO_WriteBit(GPIOx, GPIO_Pin, ((value == PIN_LOW) ? Bit_RESET : Bit_SET)); +} + +rt_int8_t rt_pin_read(rt_uint64_t pin) +{ + GPIO_Module *GPIOx = GET_GPIOx(pin); + uint16_t GPIO_Pin = GET_GPIOPin(pin); + + return ((GPIO_ReadInputDataBit(GPIOx, GPIO_Pin) == Bit_RESET) ? PIN_LOW : PIN_HIGH); +} diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h new file mode 100644 index 0000000000..7970318d27 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_gpio.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_LOW 0x00 +#define PIN_HIGH 0x01 + +#define PIN_MODE_OUTPUT 0x00 +#define PIN_MODE_INPUT 0x01 +#define PIN_MODE_INPUT_PULLUP 0x02 +#define PIN_MODE_INPUT_PULLDOWN 0x03 +#define PIN_MODE_OUTPUT_OD 0x04 + +#define GET_PIN(PORTx,PIN) (rt_uint64_t)((((rt_uint64_t)GPIO_PIN_##PIN) << 32) | (rt_uint64_t)(rt_ubase_t)GPIO##PORTx) + +void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode); +void rt_pin_write(rt_uint64_t pin, rt_uint8_t value); +rt_int8_t rt_pin_read(rt_uint64_t pin); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml b/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 0000000000..e4646070a9 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,10 @@ +scons.args: &scons + scons_arg: + - '--strict' + +# ------ nano ------ +nano: + <<: *scons + kconfig: + - CONFIG_RT_USING_NANO=y + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.config b/bsp/n32/n32hxxx/n32h760zil7-stb/.config new file mode 100644 index 0000000000..5510c17115 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.config @@ -0,0 +1,1452 @@ +CONFIG_SOC_N32H760ZIL7=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=32 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=512 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=512 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_N32=y +CONFIG_SOC_SERIES_N32H7xx=y + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_HARD_I2C is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_ADC is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.gitignore b/bsp/n32/n32hxxx/n32h760zil7-stb/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/Kconfig b/bsp/n32/n32hxxx/n32h760zil7-stb/Kconfig new file mode 100644 index 0000000000..5bc307c934 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +config SOC_N32H760ZIL7 + bool + select SOC_SERIES_N32H7xx + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" + +if !RT_USING_NANO +rsource "board/Kconfig" +endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/README_zh.md b/bsp/n32/n32hxxx/n32h760zil7-stb/README_zh.md new file mode 100644 index 0000000000..2de3427aa3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/README_zh.md @@ -0,0 +1,107 @@ +# N32H760ZIL7-STB 开发板 BSP 说明 + +## 简介 + +本文档为 [OnlyoutzZ](https://github.com/OnlyoutzZ) 为 N32H760ZIL7-STB 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +N32H760ZIL7-STB 是 NSING 推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 600Mhz，该开发板具有丰富的板载资源，可以充分发挥 N32H760 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：N32H760，主频 600MHz，1920KB FLASH ，128KB AXI-SRAM +- 常用接口：USB 转串口(J1)、USB 接口(J2/J3)等 +- 调试接口：板载的 CMSIS-DAP SWD 下载(J1) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :---------------- | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | | +| UART | 支持 | UART1/2/3 | +| IIC | 支持 | 硬件I2C1, 软件IIC | +| SPI | 支持 | SPI1 | +| RTC | 支持 | RTC | +| ADC | 支持 | ADC1/2/3 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK5 工程。下面介绍如何在 MDK5 环境下将系统运行起来。 + +#### 硬件连接 + +使用 USB 数据线插入开发板 J1 接口并连接到 PC。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP SWD 下载程序，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.3.0 build Jan 27 2026 16:53:58 + 2006 - 2024 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5` 命令重新生成工程。 + +## 注意事项 + +- 调试串口为串口 1 映射说明 + + PA9 ------> USART1_TX + + PA10 ------> USART1_RX + +## 联系人信息 + +维护人: + +- [OnlyoutzZ](https://github.com/OnlyoutzZ) diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/SConscript b/bsp/n32/n32hxxx/n32h760zil7-stb/SConscript new file mode 100644 index 0000000000..4990dfeed8 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +Import('RTT_ROOT') +Import('env') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +env.Append(CPPDEFINES = ['N32H76x']) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/SConstruct b/bsp/n32/n32hxxx/n32h760zil7-stb/SConstruct new file mode 100644 index 0000000000..175c880f66 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/SConstruct @@ -0,0 +1,54 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('env') +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'N32_Drivers', 'SConscript'),variant_dir='build/libraries/N32_Drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/applications/SConscript b/bsp/n32/n32hxxx/n32h760zil7-stb/applications/SConscript new file mode 100644 index 0000000000..9bb9abae89 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/applications/main.c b/bsp/n32/n32hxxx/n32h760zil7-stb/applications/main.c new file mode 100644 index 0000000000..5d26523a64 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include +#include +#include +#ifndef RT_USING_NANO +#include +#endif /* RT_USING_NANO */ + +/* defined the LED0 pin: PA1 */ +#define LED0_PIN GET_PIN(A, 1) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube_Config.ntfx b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube_Config.ntfx new file mode 100644 index 0000000000000000000000000000000000000000..84d3b05a01940a4012492b8451b9a30232acd874 GIT binary patch literal 4998 zcmeHLXH-+$)(ss+dJ7g>qzg$fa4AYJi2B`5Cj5(g;0cm1f(NHkzzwZDS}7| z5kxwQTq!CDq9_;P|l6}S*^JK2E_gH7HJ=eBIvayQ*003@) z_3D=^%GhSP28+;IP4_ZWqdwnUsk`~ zSS_8iK$3r5#nUmU-z~a&zCV~Bp(*)&RON}%#k!@aPmGrR>EN8vyFm{|toP3@O<#mHKcX%8EbEaEt#E#l~z8N^*S6R!-YfxR2 zfpNa0R%zna4;<^V4~D8dSFX`kt}+XV3sxaMl%L{JD`xQ=A2sCH7*vgF{P?O}>w2_- zar{NIi{qZK62A3OFnlk+2tQ5$Wje_LAKP8y(J3ACXI0%kJG=!ZPtjaB7K1x~xnN}Z1x&DU0Z;lKP*Ib>Qt}*N*Cmr?vfeI! z-`t$*%K0C1PkTjt31-v9vNvS86MfX0T?dDK{JNk5yxQuaTDqlDaIF4b*Ub0_4ELj{Srp>WMgrUVauVsu04bo83~jH2Maco0u#*QL|h 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E2ddtb7ytkO literal 0 HcmV?d00001 diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armcc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armcc.h new file mode 100644 index 0000000000..59f173ac71 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armclang.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armclang_ltm.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..feec324059 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_compiler.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_gcc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_gcc.h new file mode 100644 index 0000000000..3ddcc58b69 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_iccarm.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_iccarm.h new file mode 100644 index 0000000000..12d68fd9a6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_version.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv81mml.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv81mml.h new file mode 100644 index 0000000000..8441e57fb1 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv8mbl.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv8mbl.h new file mode 100644 index 0000000000..344dca5148 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv8mml.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv8mml.h new file mode 100644 index 0000000000..5ddb8aeda7 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm0.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm0.h new file mode 100644 index 0000000000..cafae5a0a7 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm0plus.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm0plus.h new file mode 100644 index 0000000000..d104965db5 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm1.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm23.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm23.h new file mode 100644 index 0000000000..b79c6af0b1 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm3.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm3.h new file mode 100644 index 0000000000..8157ca782d --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm33.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm33.h new file mode 100644 index 0000000000..7fed59a88e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm35p.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm35p.h new file mode 100644 index 0000000000..5579c82306 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm4.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm4.h new file mode 100644 index 0000000000..12c023b801 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm7.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm7.h new file mode 100644 index 0000000000..c4515d8fa3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_sc000.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_sc000.h new file mode 100644 index 0000000000..cf92577b63 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_sc300.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_sc300.h new file mode 100644 index 0000000000..40f3af81be --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/mpu_armv7.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/mpu_armv7.h new file mode 100644 index 0000000000..66ef59b4a0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/mpu_armv8.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/tz_context.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/core/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/n32h76x_78x.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/n32h76x_78x.h new file mode 100644 index 0000000000..2135d1eda0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/n32h76x_78x.h @@ -0,0 +1,27708 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_H__ +#define __N32H76X_78X_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** N32H76x_78x_Library_Basic **/ + +#if !defined USE_STDPERIPH_DRIVER +/* + * Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_STDPERIPH_DRIVER +#endif + +/* + * In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE +#define HSE_VALUE (25000000U) /* Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** In the following line adjust the HSE\HSI\LSI\LSE Startup + Timeout value **/ +#define HSE_STARTUP_TIMEOUT ((uint32_t)0xF0000000) /* SYSCLK= 600M Time out for HSE start up */ +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x1800) /* SYSCLK= 600M Time out for HSI start up */ +#define MSI_STARTUP_TIMEOUT ((uint16_t)0x1800) /* SYSCLK= 600M Time out for HSI start up */ +#define LSI_STARTUP_TIMEOUT ((uint16_t)0xF000) /* SYSCLK= 600M Time out for LSI start up */ +#define SECLSI_STARTUP_TIMEOUT ((uint16_t)0xF000) /* SYSCLK= 600M Time out for LSI start up */ +#define LSE_STARTUP_TIMEOUT ((uint32_t)0x18000000) /* SYSCLK= 600M Time out for LSE start up */ + +#define HSI_VALUE (64000000U) /* Value of the Internal oscillator in Hz*/ +#define MSI_VALUE (16000000U) /* Value of the Internal Medium Speed oscillator in Hz*/ +#define LSI_VALUE (32000U) /* Value of the Internal Low Speed oscillator in Hz*/ + +#define __N32H76x_78x_STDPERIPH_VERSION_MAIN (0x00) /* [31:24] main version */ +#define __N32H76x_78x_STDPERIPH_VERSION_SUB1 (0x00) /* [23:16] sub1 version */ +#define __N32H76x_78x_STDPERIPH_VERSION_SUB2 (0x01) /* [15:8] sub2 version */ +#define __N32H76x_78x_STDPERIPH_VERSION_RC (0x00) /* [7:0] release candidate */ + +/** N32H76x_78x Standard Peripheral Library version number */ +#define __N32H76x_78x_STDPERIPH_VERSION \ + ((__N32H76x_78x_STDPERIPH_VERSION_MAIN << 24) | (__N32H76x_78x_STDPERIPH_VERSION_SUB1 << 16) \ + | (__N32H76x_78x_STDPERIPH_VERSION_SUB2 << 8) | (__N32H76x_78x_STDPERIPH_VERSION_RC)) + +/* + * Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#if defined (N32H76x) || defined (N32H78x) +#define __MPU_PRESENT 1 /* MPU present*/ +#define __FPU_PRESENT 1 /* FPU present */ +#else +#define __MPU_PRESENT 1 /*!< CORE CM7 devices provide an MPU */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#endif /* N32H76x_78x */ + +#if defined (N32H78x) +#define DUAL_CORE +#endif +#define __NVIC_PRIO_BITS 4 /* N32H76x_78x uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/** + * N32H76x_78x Interrupt Number Definition + */ +typedef enum IRQn +{ + /****** Processor Exceptions Numbers ***********************************************************/ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +#ifdef CORE_CM4 + WWDG2_IRQn = 0, /* Window2 Watchdog interrupt */ +#endif /* CORE_CM4 */ +#ifdef CORE_CM7 + WWDG1_IRQn = 0, /* Window1 Watchdog interrupt */ +#endif /* CORE_CM7 */ + PVD_IRQn = 1, /* PVD through EXTI Line16 detection interrupt */ + RTC_TAMPER_IRQn = 2, /* RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt */ + RTC_WKUP_IRQn = 3, /* RTC Wakeup timer through EXTI line 19 interrupt */ + RCC_IRQn = 4, /* RCC interrupt */ + EXTI0_IRQn = 5, /* EXTI Line 0 interrupt */ + EXTI1_IRQn = 6, /* EXTI Line 1 interrupt */ + EXTI2_IRQn = 7, /* EXTI Line 2 interrupt */ + EXTI3_IRQn = 8, /* EXTI Line 3 interrupt */ + EXTI4_IRQn = 9, /* EXTI Line 4 interrupt */ + EXTI9_5_IRQn = 10, /* EXTI Line[9:5] interrupt */ + EXTI15_10_IRQn = 11, /* EXTI Line[15:10] interrupt */ + DMA1_Channel0_IRQn = 12, /* DMA1 Channel 0 global interrupt */ + DMA1_Channel1_IRQn = 13, /* DMA1 Channel 1 global interrupt */ + DMA1_Channel2_IRQn = 14, /* DMA1 Channel 2 global interrupt */ + DMA1_Channel3_IRQn = 15, /* DMA1 Channel 3 global interrupt */ + DMA1_Channel4_IRQn = 16, /* DMA1 Channel 4 global interrupt */ + DMA1_Channel5_IRQn = 17, /* DMA1 Channel 5 global interrupt */ + DMA1_Channel6_IRQn = 18, /* DMA1 Channel 6 global interrupt */ + DMA1_Channel7_IRQn = 19, /* DMA1 Channel 7 global interrupt */ + DMA2_Channel0_IRQn = 20, /* DMA2 Channel 0 global interrupt */ + DMA2_Channel1_IRQn = 21, /* DMA2 Channel 1 global interrupt */ + DMA2_Channel2_IRQn = 22, /* DMA2 Channel 2 global interrupt */ + DMA2_Channel3_IRQn = 23, /* DMA2 Channel 3 global interrupt */ + DMA2_Channel4_IRQn = 24, /* DMA2 Channel 4 global interrupt */ + DMA2_Channel5_IRQn = 25, /* DMA2 Channel 5 global interrupt */ + DMA2_Channel6_IRQn = 26, /* DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 27, /* DMA2 Channel 7 global interrupt */ + DMA3_Channel0_IRQn = 28, /* DMA3 Channel 0 global interrupt */ + DMA3_Channel1_IRQn = 29, /* DMA3 Channel 1 global interrupt */ + DMA3_Channel2_IRQn = 30, /* DMA3 Channel 2 global interrupt */ + DMA3_Channel3_IRQn = 31, /* DMA3 Channel 3 global interrupt */ + DMA3_Channel4_IRQn = 32, /* DMA3 Channel 4 global interrupt */ + DMA3_Channel5_IRQn = 33, /* DMA3 Channel 5 global interrupt */ + DMA3_Channel6_IRQn = 34, /* DMA3 Channel 6 global interrupt */ + DMA3_Channel7_IRQn = 35, /* DMA3 Channel 7 global interrupt */ + MDMA_Channel0_IRQn = 36, /* MDMA Channel 0 global interrupt */ + MDMA_Channel1_IRQn = 37, /* MDMA Channel 1 global interrupt */ + MDMA_Channel2_IRQn = 38, /* MDMA Channel 2 global interrupt */ + MDMA_Channel3_IRQn = 39, /* MDMA Channel 3 global interrupt */ + MDMA_Channel4_IRQn = 40, /* MDMA Channel 4 global interrupt */ + MDMA_Channel5_IRQn = 41, /* MDMA Channel 5 global interrupt */ + MDMA_Channel6_IRQn = 42, /* MDMA Channel 6 global interrupt */ + MDMA_Channel7_IRQn = 43, /* MDMA Channel 7 global interrupt */ + MDMA_Channel8_IRQn = 44, /* MDMA Channel 8 global interrupt */ + MDMA_Channel9_IRQn = 45, /* MDMA Channel 9 global interrupt */ + MDMA_Channel10_IRQn = 46, /* MDMA Channel 10 global interrupt */ + MDMA_Channel11_IRQn = 47, /* MDMA Channel 11 global interrupt */ + MDMA_Channel12_IRQn = 48, /* MDMA Channel 12 global interrupt */ + MDMA_Channel13_IRQn = 49, /* MDMA Channel 13 global interrupt */ + MDMA_Channel14_IRQn = 50, /* MDMA Channel 14 global interrupt */ + MDMA_Channel15_IRQn = 51, /* MDMA Channel 15 global interrupt */ + SDPU_IRQn = 52, /* SDPU global interruptSDPU global interrupt */ +#ifdef CORE_CM4 + AHB_ICACHE_IRQn = 53, /*!< CM4 AHB iCache interrupt */ + AHB_DCACHE_IRQn = 54, /*!< CM4 AHB dCache interrupt */ + FPU_CPU2_IRQn = 55, /*!< FPU_CM4 global interrupt */ +#endif /* CORE_CM4 */ +#ifdef CORE_CM7 + FPU_CPU1_IRQn = 55, /*!< FPU_CM7 global interrupt */ +#endif /* CORE_CM7 */ + ECCMON_IRQn = 56, /*!< ECCMON global interrupt */ + RTC_ALARM_IRQn = 57, /*!< RTC Alarm via EXTI17 interrupt */ + I2C1_EV_IRQn = 58, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 59, /*!< I2C1 error interrupt */ + I2C2_EV_IRQn = 60, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 61, /*!< I2C2 error interrupt */ + I2C3_EV_IRQn = 62, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 63, /*!< I2C3 error interrupt */ + I2C4_EV_IRQn = 64, /*!< I2C4 event interrupt */ + I2C4_ER_IRQn = 65, /*!< I2C4 error interrupt */ + I2C5_EV_IRQn = 66, /*!< I2C5 event interrupt */ + I2C5_ER_IRQn = 67, /*!< I2C5 error interrupt */ + I2C6_EV_IRQn = 68, /*!< I2C6 event interrupt */ + I2C6_ER_IRQn = 69, /*!< I2C6 error interrupt */ + I2C7_EV_IRQn = 70, /*!< I2C7 event interrupt */ + I2C7_ER_IRQn = 71, /*!< I2C7 error interrupt */ + I2C8_EV_IRQn = 72, /*!< I2C8 event interrupt */ + I2C8_ER_IRQn = 73, /*!< I2C8 error interrupt */ + I2C9_EV_IRQn = 74, /*!< I2C9 event interrupt */ + I2C9_ER_IRQn = 75, /*!< I2C9 error interrupt */ + I2C10_EV_IRQn = 76, /*!< I2C10 event interrupt */ + I2C10_ER_IRQn = 77, /*!< I2C10 error interrupt */ + I2S1_IRQn = 78, /*!< I2S1 global interrupt */ + I2S2_IRQn = 79, /*!< I2S1 global interrupt */ + I2S3_IRQn = 80, /*!< I2S1 global interrupt */ + I2S4_IRQn = 81, /*!< I2S1 global interrupt */ + xSPI1_IRQn = 82, /*!< xSPI1 global interrupt */ + xSPI2_IRQn = 83, /*!< xSPI1 global interrupt */ + SPI1_IRQn = 84, /*!< SPI1 global interrupt */ + SPI2_IRQn = 85, /*!< SPI2 global interrupt */ + SPI3_IRQn = 86, /*!< SPI3 global interrupt */ + SPI4_IRQn = 87, /*!< SPI4 global interrupt */ + SPI5_IRQn = 88, /*!< SPI5 global interrupt */ + SPI6_IRQn = 89, /*!< SPI6 global interrupt */ + SPI7_IRQn = 90, /*!< SPI7 global interrupt */ + LCD_EV_IRQn = 91, /*!< TFT LCD Controller event interrupt */ + LCD_ER_IRQn = 92, /*!< TFT LCD Controller error interrupt */ + DVP1_IRQn = 93, /*!< DVP1 global interrupt */ + DVP2_IRQn = 94, /*!< DVP1 global interrupt */ + DMAMUX2_IRQn = 95, /*!< DMAMUX2 (MDMA MUX) global interrupt */ + USB1_HS_EPx_OUT_IRQn = 96, /*!< USB1_HS endpoint out global interrupt */ + USB1_HS_EPx_IN_IRQn = 97, /*!< USB1_HS endpoint in global interrupt */ + USB1_HS_WKUP_IRQn = 98, /*!< USB1_HS WKUP interrupt through EXTI line 62 */ + USB1_HS_IRQn = 99, /*!< USB1_HS global interrupt */ + USB2_HS_EPx_OUT_IRQn = 100, /*!< USB2_HS endpoint out global interrupt */ + USB2_HS_EPx_IN_IRQn = 101, /*!< USB2_HS endpoint in global interrupt */ + USB2_HS_WKUP_IRQn = 102, /*!< USB2_HS WKUP interrupt through EXTI line 63 */ + USB2_HS_IRQn = 103, /*!< USB2_HS global interrupt */ + ETH1_IRQn = 104, /*!< Ethernet 1 global interrupt */ + ETH1_PMT_LPI_IRQn = 105, /*!< Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 */ + ETH2_IRQn = 106, /*!< Ethernet 2 global interrupt */ + ETH2_PMT_LPI_IRQn = 107, /*!< Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 */ + FDCAN1_INT0_IRQn = 108, /*!< FDCAN1 global interrupt line 0 */ + FDCAN2_INT0_IRQn = 109, /*!< FDCAN2 global interrupt line 0 */ + FDCAN3_INT0_IRQn = 110, /*!< FDCAN3 global interrupt line 0 */ + FDCAN4_INT0_IRQn = 111, /*!< FDCAN4 global interrupt line 0 */ + FDCAN1_INT1_IRQn = 112, /*!< FDCAN1 global interrupt line 1 */ + FDCAN2_INT1_IRQn = 113, /*!< FDCAN2 global interrupt line 1 */ + FDCAN3_INT1_IRQn = 114, /*!< FDCAN3 global interrupt line 1 */ + FDCAN4_INT1_IRQn = 115, /*!< FDCAN4 global interrupt line 1 */ + USART1_IRQn = 116, /*!< USART1 global interrupt */ + USART2_IRQn = 117, /*!< USART2 global interrupt */ + USART3_IRQn = 118, /*!< USART3 global interrupt */ + USART4_IRQn = 119, /*!< USART4 global interrupt */ + USART5_IRQn = 120, /*!< USART5 global interrupt */ + USART6_IRQn = 121, /*!< USART6 global interrupt */ + USART7_IRQn = 122, /*!< USART7 global interrupt */ + USART8_IRQn = 123, /*!< USART8 global interrupt */ + UART9_IRQn = 124, /*!< UART9 global interrupt */ + UART10_IRQn = 125, /*!< UART10 global interrupt */ + UART11_IRQn = 126, /*!< UART11 global interrupt */ + UART12_IRQn = 127, /*!< UART12 global interrupt */ + UART13_IRQn = 128, /*!< UART13 global interrupt */ + UART14_IRQn = 129, /*!< UART14 global interrupt */ + UART15_IRQn = 130, /*!< UART15 global interrupt */ + LPUART1_IRQn = 131, /*!< LPUART1 global interrupt + wakeup through EXTI line 49 */ + LPUART2_IRQn = 132, /*!< LPUART2 global interrupt + wakeup through EXTI line 52 */ + GPU_IRQn = 133, /*!< GPU global interrupt */ + SDMMC1_IRQn = 135, /*!< SDMMC1_IRQ + WKUP through EXTI line 24 */ + SDMMC2_IRQn = 136, /*!< SDMMC2_IRQ + WKUP through EXTI line 25 */ + ADC1_IRQn = 137, /*!< ADC1 global interrupt */ + ADC2_IRQn = 138, /*!< ADC2 global interrupt */ + ADC3_IRQn = 139, /*!< ADC3 global interrupt */ + COMP1_2_IRQn = 140, /*!< COMP1 and COMP2 through EXTI line 20 and 21 */ + COMP3_4_IRQn = 141, /*!< COMP3 and COMP4 through EXTI line 22 and 23 */ + SHRTIM1_INT1_IRQn = 142, /*!< High Resolution timer 1 interrupt 1 */ + SHRTIM1_INT2_IRQn = 143, /*!< High Resolution timer 1 interrupt 2 */ + SHRTIM1_INT3_IRQn = 144, /*!< High Resolution timer 1 interrupt 3 */ + SHRTIM1_INT4_IRQn = 145, /*!< High Resolution timer 1 interrupt 4 */ + SHRTIM1_INT5_IRQn = 146, /*!< High Resolution timer 1 interrupt 5 */ + SHRTIM1_INT6_IRQn = 147, /*!< High Resolution timer 1 interrupt 6 */ + SHRTIM1_INT7_IRQn = 148, /*!< High Resolution timer 1 interrupt 7 */ + SHRTIM1_INT8_IRQn = 149, /*!< High Resolution timer 1 interrupt 8 */ + SHRTIM2_INT1_IRQn = 150, /*!< High Resolution timer 1 interrupt 1 */ + SHRTIM2_INT2_IRQn = 151, /*!< High Resolution timer 1 interrupt 2 */ + SHRTIM2_INT3_IRQn = 152, /*!< High Resolution timer 1 interrupt 3 */ + SHRTIM2_INT4_IRQn = 153, /*!< High Resolution timer 1 interrupt 4 */ + SHRTIM2_INT5_IRQn = 154, /*!< High Resolution timer 1 interrupt 5 */ + SHRTIM2_INT6_IRQn = 155, /*!< High Resolution timer 1 interrupt 6 */ + SHRTIM2_INT7_IRQn = 156, /*!< High Resolution timer 1 interrupt 7 */ + SHRTIM2_INT8_IRQn = 157, /*!< High Resolution timer 1 interrupt 8 */ + FDCAN5_INT0_IRQn = 158, /*!< FDCAN5 global interrupt line 0 */ + FDCAN6_INT0_IRQn = 159, /*!< FDCAN6 global interrupt line 0 */ + FDCAN7_INT0_IRQn = 160, /*!< FDCAN7 global interrupt line 0 */ + FDCAN8_INT0_IRQn = 161, /*!< FDCAN8 global interrupt line 0 */ + FDCAN5_INT1_IRQn = 162, /*!< FDCAN5 global interrupt line 1 */ + FDCAN6_INT1_IRQn = 163, /*!< FDCAN6 global interrupt line 1 */ + FDCAN7_INT1_IRQn = 164, /*!< FDCAN7 global interrupt line 1 */ + FDCAN8_INT1_IRQn = 165, /*!< FDCAN8 global interrupt line 1 */ + DSI_IRQn = 166, /*!< MIPI DSI Interrupt through EXTI line 87 */ +#ifdef CORE_CM4 + AHB_CACHE_PARMON_IRQn = 167, /*!< AHB i/dCACHE parity error intertupt */ +#endif /* CORE_CM4 */ + LPTIM5_WKUP_IRQn = 168, /*!< LPTIM5 wakeup through EXTI 86 */ + JPEG_SGDMA_H2P_IRQn = 169, /*!< JPEG SGDMA Host to Peripheral Interrupt */ + JPEG_SGDMA_P2H_IRQn = 170, /*!< JPEG SGDMA Peripheral to Host Interrupt */ + WAKEUP_IO_IRQn = 171, /*!< 6 WAKEUP IOs through EXTI line 70-75 */ + +#ifdef CORE_CM4 + SEMA4_INT2_IRQn = 173, /*!< SEMA4 interrupt2 */ + WWDG1_RST_IRQn = 174, /*!< WWDG1 reset interrupt through EXTI line 81 */ +#endif /* CORE_CM4 */ +#ifdef CORE_CM7 + SEMA4_INT1_IRQn = 172, /*!< SEMA4 interrupt1 */ + WWDG2_RST_IRQn = 174, /*!< WWDG2 reset interrupt through EXTI line 82 */ +#endif /* CORE_CM7 */ + OTPC_IRQn = 175, /*!< OTPC interrupt */ + FEMC_IRQn = 176, /*!< FEMC interrupt */ +#ifdef CORE_CM4 + DCMUA_IRQn = 177, /*!< DCMUA interrupt */ +#endif /* CORE_CM4 */ +#ifdef CORE_CM7 + DCMUB_IRQn = 177, /*!< DCMUB interrupt */ +#endif /* CORE_CM7 */ + DAC1_IRQn = 178, /*!< DAC1 IRQ */ + DAC2_IRQn = 179, /*!< DAC2 IRQ */ + MDMA_AHBS_ER_IRQn = 180, /*!< MDMA AHBS ERROR through EXTI line 90 */ + CM7_CATCH_READ_ER_IRQn = 181, /*!< CM7 Error on Cache Read through EXTI line 64-65 */ + DAC3_IRQn = 182, /*!< DAC3 interrupt */ + DAC4_IRQn = 183, /*!< DAC4 interrupt */ + EMC_IRQn = 184, /*!< EMC event interrupt through EXTI line 88-89 */ + DAC5_IRQn = 185, /*!< DAC5 interrupt */ + DAC6_IRQn = 186, /*!< DAC6 interrupt */ + ESC_OPB_IRQn = 187, /*!< ETHERCAT OPB Interrupt */ + ESC_SYNC0_IRQn = 188, /*!< ETHERCAT SYNC0 Interrupt */ + ESC_SYNC1_IRQn = 189, /*!< ETHERCAT SYNC1 Interrupt */ + ESC_WRP_IRQn = 190, /*!< ETHERCAT WRAPPER Interrupt */ + ATIM1_BRK_IRQn = 192, /*!< Advanced timer 1 break interrupt */ + ATIM1_TRG_COM_IRQn = 193, /*!< Advanced timer 1 trigger and commutation interrupts */ + ATIM1_CC_IRQn = 194, /*!< Advanced timer 1 capture/compare interrupt */ + ATIM1_UP_IRQn = 195, /*!< Advanced timer 1 update interrupt */ + ATIM2_BRK_IRQn = 196, /*!< Advanced timer 2 break interrupt */ + ATIM2_TRG_COM_IRQn = 197, /*!< advanced timer 2 trigger and commutation interrupts */ + ATIM2_CC_IRQn = 198, /*!< Advanced timer 2 capture/compare interrupt */ + ATIM2_UP_IRQn = 199, /*!< Advanced timer 2 update interrupt */ + ATIM3_BRK_IRQn = 200, /*!< Advanced timer 3 break interrupt */ + ATIM3_TRG_COM_IRQn = 201, /*!< Advanced timer 3 trigger and commutation interrupts */ + ATIM3_CC_IRQn = 202, /*!< Advanced timer 3 capture/compare interrupt */ + ATIM3_UP_IRQn = 203, /*!< Advanced timer 3 update interrupt */ + ATIM4_BRK_IRQn = 204, /*!< Advanced timer 4 break interrupt */ + ATIM4_TRG_COM_IRQn = 205, /*!< Advanced timer 4 trigger and commutation interrupts */ + ATIM4_CC_IRQn = 206, /*!< Advanced timer 4 capture/compare interrupt */ + ATIM4_UP_IRQn = 207, /*!< Advanced timer 4 update interrupt */ + GTIMA1_IRQn = 208, /*!< General timer A 1 global interrupt */ + GTIMA2_IRQn = 209, /*!< General timer A 2 global interrupt */ + GTIMA3_IRQn = 210, /*!< General timer A 3 global interrupt */ + GTIMA4_IRQn = 211, /*!< General timer A 4 global interrupt */ + GTIMA5_IRQn = 212, /*!< General timer A 5 global interrupt */ + GTIMA6_IRQn = 213, /*!< General timer A 6 global interrupt */ + GTIMA7_IRQn = 214, /*!< General timer A 7 global interrupt */ + GTIMB1_IRQn = 215, /*!< General timer B 1 global interrupt */ + GTIMB2_IRQn = 216, /*!< General timer B 2 global interrupt */ + GTIMB3_IRQn = 217, /*!< General timer B 3 global interrupt */ + BTIM1_IRQn = 218, /*!< Base timer 1 global interrupt */ + BTIM2_IRQn = 219, /*!< Base timer 2 global interrupt */ + BTIM3_IRQn = 220, /*!< Base timer 3 global interrupt */ + BTIM4_IRQn = 221, /*!< Base timer 4 global interrupt */ + LPTIM1_WKUP_IRQn = 222, /*!< LPTIM1 wakeup interrupt */ + LPTIM2_WKUP_IRQn = 223, /*!< LPTIM2 wakeup interrupt */ + LPTIM3_WKUP_IRQn = 224, /*!< LPTIM3 wakeup interrupt */ + LPTIM4_WKUP_IRQn = 225, /*!< LPTIM4 wakeup interrupt */ + DSMU_FLT0_IRQn = 226, /*!< DSMU_FLT0 */ + DSMU_FLT1_IRQn = 227, /*!< DSMU_FLT1 */ + DSMU_FLT2_IRQn = 228, /*!< DSMU_FLT2 */ + DSMU_FLT3_IRQn = 229, /*!< DSMU_FLT3 */ + FMAC_IRQn = 230, /*!< FMAC global interrupt */ + CORDIC_IRQn = 231, /*!< CORDIC global interrupt */ + DMAMUX_IRQn = 232, /*!< DMAMUX interrupt */ + MMU_INT_IRQn = 233, /*!< MMU interrupt */ +} IRQn_Type; + +#if defined (CORE_CM4) +#include "core_cm4.h" +#endif +#if defined (CORE_CM7) +#include "core_cm7.h" +#endif + +#include "system_n32h76x_78x.h" +#include +#include +#include + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus,ITStatus, + INTStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState,FunctionalStatus; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/* N32H76x_78x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE + +/*** Analog to Digital Converter ***/ +typedef struct +{ + __IO uint32_t STS; //0x00 + __IO uint32_t CTRL1; //0x04 + __IO uint32_t CTRL2; //0x08 + __IO uint32_t CTRL3; //0x0C + __IO uint32_t SAMPT1; //0x10 + __IO uint32_t SAMPT2; //0x14 + __IO uint32_t SAMPT3; //0x18 + __IO uint32_t DIFSEL; //0x1C + __IO uint32_t AWDCTRL; //0x20 + __IO uint32_t OFFSET1; //0x24 + __IO uint32_t OFFSET2; //0x28 + __IO uint32_t OFFSET3; //0x2C + __IO uint32_t OFFSET4; //0x30 + __IO uint32_t AWD1HIGH; //0x34 + __IO uint32_t AWD1LOW; //0x38 + __IO uint32_t AWD2HIGH; //0x3C + __IO uint32_t AWD2LOW; //0x40 + __IO uint32_t AWD3HIGH; //0x44 + __IO uint32_t AWD3LOW; //0x48 + __IO uint32_t AWD2EN; //0x4C + __IO uint32_t AWD3EN; //0x50 + __IO uint32_t AWD2INTEN; //0x54 + __IO uint32_t AWD3INTEN; //0x58 + __IO uint32_t AWD2STS; //0x5C + __IO uint32_t AWD3STS; //0x60 + __IO uint32_t RSEQ1; //0x64 + __IO uint32_t RSEQ2; //0x68 + __IO uint32_t RSEQ3; //0x6C + __IO uint32_t RSEQ4; //0x70 + __IO uint32_t JSEQ; //0x74 + __IO uint32_t JDAT1; //0x78 + __IO uint32_t JDAT2; //0x7C + __IO uint32_t JDAT3; //0x80 + __IO uint32_t JDAT4; //0x84 + __IO uint32_t DAT; //0x88 + __IO uint32_t FIFOCFG; //0x8C + __IO uint32_t FIFOSTS; //0x90 + __IO uint32_t DLYSMP; //0x94 + __IO uint32_t OSCFG; //0x98 + __IO uint32_t INTLRCFG; //0x9C + __IO uint32_t GCOMP; //0xA0 +}ADC_Module; + + +/*** LCDC Register ***/ +typedef struct +{ + __I uint32_t RESERVED0[2]; /* Reserved, 0x00, 0x04 */ + __IO uint32_t SYNCCTRL; /* LCDC Synchronization Size Conctrl Register, Address offset: 0x08 */ + __IO uint32_t BPCTRL; /* LCDC Back Porch Conctrl Register, Address offset: 0x0C */ + __IO uint32_t AWCTRL; /* LCDC Active Width Conctrl Register, Address offset: 0x10 */ + __IO uint32_t TWCTRL; /* LCDC Total Width Conctrl Register, Address offset: 0x14 */ + __IO uint32_t GCTRL; /* LCDC Global Control Register , Address offset: 0x18 */ + __I uint32_t RESERVED1[2]; /* Reserved, 0x1C, 0x20 */ + __IO uint32_t SRCTRL; /* LCDC Shadow Reload Conctrl Register, Address offset: 0x24 */ + __I uint32_t RESERVED2; /* Reserved, 0x28 */ + __IO uint32_t BGCCTRL; /* LCDC Background Color Conctrl Register, Address offset: 0x2C */ + __I uint32_t RESERVED3; /* Reserved, 0x30 */ + __IO uint32_t INTEN; /* LCDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t INTSTS; /* LCDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t INTCLR; /* LCDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LINTPCTRL; /* LCDC Line Interrupt Position Conctrl Register, Address offset: 0x40 */ + __IO uint32_t CPSTS; /* LCDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSTS; /* LCDC Current Display Status Register, Address offset: 0x48 */ + __I uint32_t RESERVED4[5]; /* Reserved, 0x4C ~ 0x5C */ + __IO uint32_t EXTDCTRL; /* LCDC External Display Control Register, Address offset: 0x60 */ +} LCDC_Module; + +typedef struct +{ + __I uint32_t RESERVED0[2]; /* Reserved, 0x00 0x04 */ + __IO uint32_t LSRCTRL; /* LCDC Layerx Reload Control Register Address offset: 0x08 */ + __IO uint32_t LCTRL; /* LCDC Layerx Control Register Address offset: 0x0C */ + __IO uint32_t WHPCTRL; /* LCDC Layerx Window Horizontal Position Configuration Register Address offset: 0x10 */ + __IO uint32_t WVPCTRL; /* LCDC Layerx Window Vertical Position Configuration Register Address offset: 0x14 */ + __IO uint32_t CKCTRL; /* LCDC Layerx Color Keying Configuration Register Address offset: 0x18 */ + __IO uint32_t PFCTRL; /* LCDC Layerx Pixel Format Configuration Register Address offset: 0x1C */ + __IO uint32_t CACTRL; /* LCDC Layerx Constant Alpha Configuration Register Address offset: 0x20 */ + __IO uint32_t DCCTRL; /* LCDC Layerx Default Color Configuration Register Address offset: 0x24 */ + __IO uint32_t BFCTRL; /* LCDC Layerx Blending Factors Configuration Register Address offset: 0x28 */ + __IO uint32_t FBBCTRL; /* LCDC Layerx Frame Buffer Bus Control Register Address offset: 0x2C */ + __IO uint32_t AFBCTRL; /* LCDC Layerx Auxiliary Frame Buffer Control Register Address offset: 0x30 */ + __IO uint32_t CFBADDR; /* LCDC Layerx Color Frame Buffer Address Register Address offset: 0x34 */ + __IO uint32_t CFBLEN; /* LCDC Layerx Color Frame Buffer Length Register Address offset: 0x38 */ + __IO uint32_t CFBLNUM; /* LCDC Layerx Color Frame Buffer Line Number Register Address offset: 0x3C */ + __IO uint32_t AFBADDR0; /* LCDC Layerx Auxiliary 0 Fram Buffer Address Register Address offset: 0x40 */ + __IO uint32_t AFBADDR1; /* LCDC Layerx Auxiliary 1 Fram Buffer Address Register Address offset: 0x44 */ + __IO uint32_t AFBLEN; /* LCDC Layerx Auxiliary Fram Buffer Length(pitch) Register Address offset: 0x48 */ + __IO uint32_t AFBLNUM; /* LCDC Layerx Auxiliary Fram Buffer Lines Register Address offset: 0x4C */ + __IO uint32_t CLUTWR; /* LCDC Layerx CLUT Write Register Address offset: 0x50 */ + __IO uint32_t SINS; /* LCDC Layerx Scaler Input Size Register Address offset: 0x54 */ + __IO uint32_t SOUTS; /* LCDC Layerx Scaler Output Size Register Address offset: 0x58 */ + __IO uint32_t VSF; /* LCDC Layerx Vertical Scaling Factor Register Address offset: 0x5C */ + __IO uint32_t VSP; /* LCDC Layerx Vertical Scaling Phase Register Address offset: 0x60 */ + __IO uint32_t HSF; /* LCDC Layerx Horizontal Scaling Factor Register Address offset: 0x64 */ + __IO uint32_t HSP; /* LCDC Layerx Horizontal Scaling Phase Register Address offset: 0x68 */ + __IO uint32_t YUVS1; /* LCDC Layerx YCbCr Scale 1 Register Address offset: 0x6c */ + __IO uint32_t YUVS2; /* LCDC Layerx YCbCr Scale 2 Register Address offset: 0x70 */ + __IO uint32_t FCF1; /* LCDC Layerx Flexible color format 1 Register Address offset: 0x74 */ + __IO uint32_t FCF2; /* LCDC Layerx Flexible color format 2 Register Address offset: 0x78 */ +} LCDC_Layer_Module; + +/* JPEG Module */ + +typedef struct +{ + __IO uint32_t CTRL; //0x0 +}JPEG_CTRL_Module; + +typedef struct +{ + __IO uint32_t INIT; //0x0 + __IO uint32_t EN; //0x4 + __IO uint32_t BUFBADDR; //0x8 + __IO uint32_t BUFSIZE; //0xc + uint32_t RESERVED1[13]; //0x10 + __IO uint32_t USMODE; //0x44 +}JPEG_BRC_Module; + +typedef struct +{ + __IO uint32_t INIT; //0x0 + __IO uint32_t EN; //0x4 + __IO uint32_t SWITCH; //0x8 + __IO uint32_t FRMW; //0xc + __IO uint32_t FRMH; //0x10 + uint32_t RESERVED0; //0x14 + __IO uint32_t PFORM; //0x18 + __IO uint32_t CNAME; //0x1c + __IO uint32_t C0SADD; //0x20 + __IO uint32_t C0EADD; //0x24 + uint32_t RESERVED1[14]; //0x28 + __IO uint32_t BPS0; //0x60 + __IO uint32_t BPS12; //0x64 + __IO uint32_t ROWS0; //0x68 + __IO uint32_t ROWS12; //0x6c + __IO uint32_t HHALF; //0x70 + __IO uint32_t BLSS0; //0x74 + __IO uint32_t BLSS12; //0x78 + __IO uint32_t BPRS0; //0x7c + __IO uint32_t BPRS12; //0x80 + __IO uint32_t MAXW; //0x84 + __IO uint32_t MAXH; //0x88 + __IO uint32_t MBSIZE; //0x8c +}JPEG_RBC_Module; + +typedef struct +{ + __IO uint32_t CTRL; //0x0 + __IO uint32_t STS; //0x4 + __IO uint32_t IE; //0x8 + __IO uint32_t INTSTS; //0xc + __IO uint32_t AOODT; //0x10 + __IO uint32_t MBSIZE; //0x14 + __IO uint32_t SGLPL; //0x18 + __IO uint32_t SGLPM; //0x1c + __IO uint32_t SGL_SIZE; //0x20 + __IO uint32_t SGL_HEAD; //0x24 + __IO uint32_t SGL_TAIL; //0x28 + __IO uint32_t MRADDL; //0x2c + __IO uint32_t MRADDM; //0x30 + __IO uint32_t MWADDL; //0x34 + __IO uint32_t MWADDM; //0x38 + __IO uint32_t DESCF; //0x3c + __IO uint32_t DESC_MBSIZE; //0x40 + __IO uint32_t DESC_MUS; //0x44 + __IO uint32_t DESC_MBADDL; //0x48 + __IO uint32_t DESC_MBADDH; //0x4c + uint32_t RESERVED0; //0x50 + __IO uint32_t DESC_LINKL; //0x54 + __IO uint32_t DESC_LINKH; //0x58 + __IO uint32_t PARACFG; //0x5c + __IO uint32_t FIFODP; //0x60 +}JPEG_SGDMA_Module; + +typedef struct +{ + __IO uint32_t MODE; //0x0 + __IO uint32_t ERROR; //0x4 + __IO uint32_t UNLOC; //0x8 + __IO uint32_t UELOC; //0xc + __IO uint32_t HESYM; //0x10 + __IO uint32_t HESYMECS; //0x14 + __IO uint32_t HUF_SELOC; //0x18 + __IO uint32_t TAB_ACCREQ; //0x1c + __IO uint32_t HUFTAB0_EOB; //0x20 + __IO uint32_t HUFTAB1_EOB; //0x24 + __IO uint32_t HUFTAB2_EOB; //0x28 + __IO uint32_t HUFTAB3_EOB; //0x2c + uint32_t RESERVED0[20]; //0x30 + __IO uint32_t HUF_ADDR; //0x80 + __IO uint32_t HUF_DATA; //0x84 + __IO uint32_t HUF_REM; //0x88 + uint32_t RESERVED1[221]; //0x8C + __IO uint32_t QT0[64]; //0x400 + __IO uint32_t QT1[64]; //0x500 + __IO uint32_t QT2[64]; //0x600 + __IO uint32_t QT3[64]; //0x700 +}JPEG_DEC_Module; + + +/*** Huffman tables ***/ +typedef struct +{ + __IO uint32_t DCOL[16]; + __IO uint32_t ACOL[240]; + __IO uint32_t DCCODE[16]; + __IO uint32_t ACCODE[16]; + __IO uint32_t EOBS; + __IO uint32_t ZRLS; + __IO uint32_t RESERVED[222]; +} Huffmantables_Type; + +/* JPEG Encoder */ +typedef struct +{ + Huffmantables_Type HT0; //0x00 + Huffmantables_Type HT1; //0x800 + Huffmantables_Type HT2; //0x1000 + Huffmantables_Type HT3; //0x1800 + __IO uint32_t QT0[64]; //0x2000 + __IO uint32_t QT1[64]; //0x2100 + __IO uint32_t QT2[64]; //0x2200 + __IO uint32_t QT3[64]; //0x2300 + uint32_t RESERVED1[1792];//0x2400 + __IO uint32_t HFBUFFER[512]; //0x4000 + __IO uint32_t HEADD; //0x4800 + __IO uint32_t RESERVED2[4]; //0x4804 + __IO uint32_t HUFTAB0E; //0x4814 + __IO uint32_t HUFTAB1E; //0x4818 + __IO uint32_t HUFTAB2E; //0x481c + __IO uint32_t HUFTAB3E; //0x4820 + __IO uint32_t FEADD; //0x4824 + __IO uint32_t RESERVED3[502]; //0x4828 + __IO uint32_t CTRL; //0x5000 + __IO uint32_t DYNRCFG; //0x5004 + __IO uint32_t RESERVED4[13]; //0x5008 + __IO uint32_t HSEL; //0x503c + __IO uint32_t RESERVED5[48]; //0x5040 + __IO uint32_t PIPESTS; //0x5100 + __IO uint32_t RESERVED6[959]; //0x5104 + __IO uint32_t RICTRL; //0x6000 + __IO uint32_t RESERVED7[4096];//0x6004 + __IO uint32_t HFSIZE; //0xa004 + __IO uint32_t IPNUM; //0xa008 + __IO uint32_t RESERVED8[3]; //0xa00c + __IO uint32_t PBSIZE; //0xa018 + __IO uint32_t RESERVED9[2]; //0xa01c + __IO uint32_t OBSIZE; //0xa024 +}JPEG_ENC_Module; + +/*** COMP_Single ***/ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t FILC; + __IO uint32_t FILP; + __IO uint32_t RES; +} COMP_SingleType; + +/*** Comparator ***/ +typedef struct +{ + __IO uint32_t RES[4]; + COMP_SingleType Cmp[4]; //0x10 + __IO uint32_t LPR; //0x50 + __IO uint32_t WINMODE; //0x54 + __IO uint32_t RES1; //0x58 + __IO uint32_t LOCK; //0x5C + __IO uint32_t INTEN; //0x60 + __IO uint32_t INTSTS; //0x64 + __IO uint32_t OTIMEN; //0x68 +}COMP_Module; + + +/*** Digital to Analog Converter ***/ +typedef struct +{ + __IO uint32_t CTRL; //0x00 + __IO uint32_t SOTTR; //0x04 + __IO uint32_t DATO1; //0x08 + __IO uint32_t DATO2; //0x0C + __IO uint32_t DR8CH1; //0x10 + __IO uint32_t DL12CH1; //0x14 + __IO uint32_t DR12CH1; //0x18 + __IO uint32_t DR8CH2; //0x1C + __IO uint32_t DL12CH2; //0x20 + __IO uint32_t DR12CH2; //0x24 + __IO uint32_t DR8DCH; //0x28 + __IO uint32_t DL12DCH; //0x2C + __IO uint32_t DR12DCH; //0x30 + __IO uint32_t RES0; //0x34 + __IO uint32_t SELCTRL; //0x38 + __IO uint32_t STS; //0x3C + __IO uint32_t GCTRL; //0x40 + __IO uint32_t STINC; //0x44 + __IO uint32_t STRST; //0x48 + __IO uint32_t RES1[4]; + __IO uint32_t CALC; //0x5C +} DAC_Module; + + +/*** CRC ***/ +typedef struct +{ + __IO uint32_t DAT; //0x00 + __IO uint32_t IDAT; //0x04 + __IO uint32_t CTRL; //0x08 + __IO uint32_t LRC; //0x0C + __IO uint32_t INIT; //0x10 + __IO uint32_t POL; //0x14 + __IO uint32_t INXORDAT; //0x18 + __IO uint32_t OUTXORDAT; //0x1C +} CRC_Module; + +/** + * @brief TCM Configuration + */ +typedef struct +{ + __IO uint32_t TCM_CR; /*!< (offset 0x000) TCM configuration Register */ +} TCMSRAMC_TypeDef; + + + +/*** DMA Controller on AHB Bus (DMA1,DMA2,DMA3) ***/ +typedef struct +{ + __IO uint32_t SA; /* (offset 0x0000) Source Address Register */ + __I uint32_t RESERVED0; + __IO uint32_t DA; /* (offset 0x0008) Destination Address Register */ + __I uint32_t RESERVED1; + __IO uint32_t LLP; /* (offset 0x0010) Linked List Pointer Register */ + __I uint32_t RESERVED2; + __IO uint64_t CTRL; /* (offset 0x0018) Control Register Low */ + __I uint32_t RESERVED3[8]; + __IO uint64_t CFG; /* (offset 0x0040) Configuration Register Low */ + __IO uint32_t SG; /* (offset 0x0048) Source Gather Register */ + __I uint32_t RESERVED4; + __IO uint32_t DS; /* (offset 0x0050) Destination Scatter Register */ + __I uint32_t RESERVED5; +} DMA_ChannelType; + +typedef struct +{ + /** DMA Channel Registers **/ + __IO DMA_ChannelType CH[8]; /* (offset 0x0000 + x * 0x58 ) Channel x from 0 to 7 */ + + /** DMA Interrupt Registers **/ + __IO uint32_t RAWTCINTSTS; /* (offset 0x02C0) Raw IntTfr Status */ + __I uint32_t RESERVED0; + __IO uint32_t RAWBTCINTSTS; /* (offset 0x02C8) Raw IntBlock Status */ + __I uint32_t RESERVED1; + __IO uint32_t RAWSTCINTSTS; /* (offset 0x02D0) Raw IntSrcTran Status */ + __I uint32_t RESERVED2; + __IO uint32_t RAWDTCINTSTS; /* (offset 0x02D8) Raw IntDstTran Status */ + __I uint32_t RESERVED3; + __IO uint32_t RAWERRINTSTS; /* (offset 0x02E0) Raw IntErr Status */ + __I uint32_t RESERVED4; + __I uint32_t TCINTSTS; /* (offset 0x02E8) IntTfr Status */ + __I uint32_t RESERVED5; + __I uint32_t BTCINTSTS; /* (offset 0x02F0) IntBlock Status */ + __I uint32_t RESERVED6; + __I uint32_t STCINTSTS; /* (offset 0x02F8) IntSrcTran Status */ + __I uint32_t RESERVED7; + __I uint32_t DTCINTSTS; /* (offset 0x0300) IntDstTran Status */ + __I uint32_t RESERVED8; + __I uint32_t ERRINTSTS; /* (offset 0x0308) IntErr Status */ + __I uint32_t RESERVED9; + __IO uint32_t TCINTMSK; /* (offset 0x0310) Mask for Raw IntTfr Status */ + __I uint32_t RESERVED10; + __IO uint32_t BTCINTMSK; /* (offset 0x0318) Mask for Raw IntBlock Status */ + __I uint32_t RESERVED11; + __IO uint32_t STCINTMSK; /* (offset 0x0320) Mask for Raw IntSrcTran Status */ + __I uint32_t RESERVED12; + __IO uint32_t DTCINTMSK; /* (offset 0x0328) Mask for Raw IntDstTran Status */ + __I uint32_t RESERVED13; + __IO uint32_t ERRINTMSK; /* (offset 0x0330) Mask for Raw IntErr Status */ + __I uint32_t RESERVED14; + __O uint32_t TCINTCLR; /* (offset 0x0338) Clear IntTfr Interrupt */ + __I uint32_t RESERVED15; + __O uint32_t BTCINTCLR; /* (offset 0x0340) Clear IntBlock Interrupt */ + __I uint32_t RESERVED16; + __O uint32_t STCINTCLR; /* (offset 0x0348) Clear IntSrcTran Interrupt */ + __I uint32_t RESERVED17; + __O uint32_t DTCINTCLR; /* (offset 0x0350) Clear IntDstTran Interrupt */ + __I uint32_t RESERVED18; + __O uint32_t ERRINTCLR; /* (offset 0x0358) Clear IntErr Interrupt */ + __I uint32_t RESERVED19; + __I uint32_t INTCBESTS; /* (offset 0x0360) Combined Interrupt Status Register */ + + /** DMA Software Handshake Registers **/ + __I uint32_t RESERVED20; + __IO uint32_t SRCSWTREQ; /* (offset 0x0368) Source Software Transaction Request Register */ + __I uint32_t RESERVED21; + __IO uint32_t DSTSWTREQ; /* (offset 0x0370) Destination Software Transaction Request Register */ + __I uint32_t RESERVED22; + __IO uint32_t SRCSGTREQ; /* (offset 0x0378) Single Source Transaction Request Register */ + __I uint32_t RESERVED23; + __IO uint32_t DSTSGTREQ; /* (offset 0x0380) Single Destination Transaction Request Register */ + __I uint32_t RESERVED24; + __IO uint32_t SRCLTREQ; /* (offset 0x0388) Last Source Transaction Request Register */ + __I uint32_t RESERVED25; + __IO uint32_t DSTLTREQ; /* (offset 0x0390) Last Destination Transaction Request Register */ + + /** DMA Miscellaneous Registers **/ + __I uint32_t RESERVED26; + __IO uint32_t CFG; /* (offset 0x0398) DMA Configuration Register */ + __I uint32_t RESERVED27; + __IO uint32_t CHEN; /* (offset 0x03A0) DMA Channel Enable Register */ + __I uint32_t RESERVED28; + __I uint32_t ID; /* (offset 0x03A8) DMA ID Register */ + __I uint32_t RESERVED29[19]; + __I uint32_t TYPE; /* (offset 0x03F8) DMA Component Type */ + __I uint32_t VERSION; /* (offset 0x03FC) DMA Component Version */ +} DMA_Module; + + +/*** DMA AXI Bus Controller (MDMA) ***/ +typedef struct +{ + __IO uint64_t SA; /* (offset 0x0100) Source Address */ + __IO uint64_t DA; /* (offset 0x0108) Destination Address */ + __IO uint32_t BTS; /* (offset 0x0110) Block Transfer Size */ + __I uint32_t RESERVED0; + __IO uint64_t CTRL; /* (offset 0x0118) Control */ + __IO uint64_t CFG; /* (offset 0x0120) Configuration */ + __IO uint64_t LLP; /* (offset 0x0128) Linked List Pointer */ + __I uint64_t STS; /* (offset 0x0130) Status */ + __IO uint32_t SHSRC; /* (offset 0x0138) Software Handshake Source */ + __I uint32_t RESERVED1; + __IO uint32_t SHDST; /* (offset 0x0140) Software Handshake Destination */ + __I uint32_t RESERVED2; + __O uint32_t BTRR; /* (offset 0x0148) Block Transfer Resume Request */ + __I uint32_t RESERVED3[3]; + __I uint32_t AXIQOS; /* (offset 0x0158) AXI QOS */ + __I uint32_t RESERVED4[9]; + __IO uint32_t INTSTSEN; /* (offset 0x0180) Interrupt Status Enable */ + __I uint32_t RESERVED5; + __I uint32_t INTSTS; /* (offset 0x0188) Interrupt Status */ + __I uint32_t RESERVED6; + __IO uint32_t INTSGLEN; /* (offset 0x0190) Interrupt Signal Enable */ + __I uint32_t RESERVED7; + __O uint32_t INTCLR; /* (offset 0x0198) Interrupt Clear */ + __I uint32_t RESERVED8[25]; +} MDMA_ChannelType; + +typedef struct +{ + /** MDMA Common Registers **/ + __I uint32_t ID; /* (offset 0x0000) DMAC ID */ + __I uint32_t RESERVED0; + __I uint32_t VERSION; /* (offset 0x0008) DMAC Component Version */ + __I uint32_t RESERVED1; + __IO uint32_t CFG; /* (offset 0x0010) DMAC Configuration */ + __I uint32_t RESERVED2; + __IO uint32_t CHEN; /* (offset 0x0018) DMAC Channel Enable */ + __I uint32_t RESERVED3; + __IO uint32_t CHSUSP; /* (offset 0x0020) DMAC Channel Suspend */ + __I uint32_t RESERVED4[3]; + __I uint64_t INTSTS; /* (offset 0x0030) DMAC Interrupt Status */ + __O uint32_t CRINTCLR; /* (offset 0x0038) DMAC Interrupt Clear */ + __I uint32_t RESERVED5; + __IO uint32_t CRINTSTSEN; /* (offset 0x0040) DMAC Interrupt Status Enable */ + __I uint32_t RESERVED6; + __IO uint32_t CRINTSGLEN; /* (offset 0x0048) DMAC Interrupt Signal Enable */ + __I uint32_t RESERVED7; + __I uint32_t CRINTSTS; /* (offset 0x0050) DMAC Interrupt Status */ + __I uint32_t RESERVED8; + __IO uint32_t SWRST; /* (offset 0x0058) DMAC Software Reset Register */ + __I uint32_t RESERVED9; + __IO uint64_t LPCFG; /* (offset 0x0060) DMAC Low Power Configuration Register */ + __I uint32_t RESERVED10[38]; + + /** MDMA Channel Registers **/ + MDMA_ChannelType CH[16]; /* (offset 0x0100 + x * 0x100) Channel x from 0 to 15 */ + +} MDMA_Module; + +/*** DMAMUX1 ***/ +typedef struct +{ + __IO uint32_t CHxCTRL[24]; /* DMA Multiplexer Channel x Control Register */ + __IO uint32_t STS; /* DMA Channel Status Register */ + __IO uint32_t CLR; /* DMA Channel Clear Flag Register */ + __IO uint32_t CHxCFG[24]; /* DMA Request Generator x Control Register */ + __IO uint32_t RGSTS; /* DMA Request Generator x Interrupt Status Register */ + __IO uint32_t RGCLR; /* DMA Request Generator x Interrupt Clear Register */ +}DMAMUX1_Module; + +/*** DMAMUX2 ***/ +typedef struct +{ + __IO uint32_t CHxCTRL[15]; /* DMA Multiplexer Channel x Control Register */ + __IO uint32_t STS; /* DMA Channel Status Register */ + __IO uint32_t CLR; /* DMA Channel Clear Flag Register */ + __IO uint32_t CHxCFG[15]; /* DMA Request Generator x Control Register */ + __IO uint32_t RGSTS; /* DMA Request Generator x Interrupt Status Register */ + __IO uint32_t RGCLR; /* DMA Request Generator x Interrupt Clear Register */ +}DMAMUX2_Module; + +typedef struct +{ + __IO uint32_t CHCTRL; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA Channel Status Register */ + __IO uint32_t CLR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t CHCFG; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSTS; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCLR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + + +/*** DCMU ***/ +typedef struct +{ + __O uint32_t TXMSG[4]; /*!< DCMU messaging transmit registers , Address offset: 00h-0Ch */ + __I uint32_t RCVMSG[4]; /*!< DCMU messaging receive registers , Address offset: 10h-1Ch */ + __IO uint32_t STS; /*!< DCMU messaging status register , Address offset: 20h */ + __IO uint32_t CTRL; /*!< DCMU messaging control register , Address offset: 24h */ + +} DCMU_Module; + +/*** SEMA4 ***/ +typedef struct +{ + __IO uint32_t R[32]; /* 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RL[32]; /* 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IEN; /* SEMA4 Interrupt 0 enable register , Address offset: 100h */ + __IO uint32_t C1ICLR; /* SEMA4 Interrupt 0 clear register , Address offset: 104h */ + __IO uint32_t C1ISTS; /* SEMA4 Interrupt 0 Status register , Address offset: 108h */ + __IO uint32_t C1MISTS; /* SEMA4 Interrupt 0 Masked Status register , Address offset: 10Ch */ + __IO uint32_t C2IEN; /* SEMA4 Interrupt 1 enable register , Address offset: 110h */ + __IO uint32_t C2ICLR; /* SEMA4 Interrupt 1 clear register , Address offset: 114h */ + __IO uint32_t C2ISTS; /* SEMA4 Interrupt 1 Status register , Address offset: 118h */ + __IO uint32_t C2MISTS; /* SEMA4 Interrupt 1 Masked Status register , Address offset: 11Ch */ + __IO uint32_t C1ILFSTS; /* SEMA4 Interrupt 0 Interrupt Lock Fail Status register Address offset: 0x120 */ + __IO uint32_t C2ILFSTS; /* SEMA4 Interrupt 1 Interrupt Lock Fail Status register Address offset: 0x124 */ + __IO uint32_t Res0[2]; /* Reserved Address offset: 128h-12Fh */ + __IO uint32_t C1ILFEN; /* SEMA4 Interrupt 0 Interrupt Lock Fail Enable register Address offset: 0x130 */ + __IO uint32_t C2ILFEN; /* SEMA4 Interrupt 1 Interrupt Lock Fail Enable register Address offset: 0x134 */ + __IO uint32_t Res1[2]; /* Reserved Address offset: 138h-13Fh */ + __IO uint32_t CLR; /* SEMA4 Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYCLR; /* SEMA4 Semaphore clear key register , Address offset: 144h */ +} SEMA4_Module; + + + /** + * @brief FLASH Registers + */ + + typedef struct + { + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t OBR2; + __IO uint32_t OBR; + __IO uint32_t WRPR; + __IO uint32_t CR2; + __IO uint32_t TIMR; + __IO uint32_t RESERVED1; + __IO uint32_t CAHR; + } FLASH_TypeDef; + + /** + * @brief Option Bytes Registers + */ + + typedef struct + { + __IO uint32_t USER_RDP; + __IO uint32_t Data1_Data0; + __IO uint32_t WRP1_WRP0; + __IO uint32_t WRP3_WRP2; + __IO uint32_t RDP2; + } OB_TypeDef; + + + + +/** + * @brief Digital to Analog Converter + */ + +/** + * @brief USB + */ + +/** Flexible Extended Memory Controller SRAM/NOR Flash **/ +typedef struct +{ + __IO uint32_t FEMC_SNTSTS; + __IO uint32_t FEMC_SNOMSTS; + uint32_t RESERVED[6]; +}FEMC_SN_Bank_Block; + +/** Flexible Extended Memory Controller NAND **/ +typedef struct +{ + __IO uint32_t FEMC_NTSTS; + __IO uint32_t FEMC_NOMSTS; + uint32_t RESERVED[6]; +}FEMC_NAND_Bank; + + +typedef struct +{ + __IO uint32_t FEMC_STS; /* FEMC Status Register Address offset: 0x000 */ + __IO uint32_t FEMC_STS1; /* FEMC Status Register1 Address offset: 0x004 */ + __IO uint32_t FEMC_CFG; /* FEMC Configuration Register Address offset: 0x008 */ + __IO uint32_t FEMC_CCFG; /* FEMC Configuration clear Register Address offset: 0x00C */ + __IO uint32_t FEMC_CTRL; /* FEMC Control Register1 Address offset: 0x010 */ + __IO uint32_t FEMC_TCFG; /* FEMC Timing Configuration Register Address offset: 0x014 */ + __IO uint32_t FEMC_OMCFG; /* FEMC Operate Mode Register Address offset: 0x018 */ + uint32_t RESERVED1C; + __IO uint32_t FEMC_RPE; /* FEMC Refresh Period Register Address offset: 0x020 */ + uint32_t RESERVED24[55]; /* 0x24 ~ 0xFC */ + FEMC_SN_Bank_Block block1; /* 0x100 ~ 0x11C */ + FEMC_SN_Bank_Block block2; /* 0x120 ~ 0x13C */ + FEMC_SN_Bank_Block block3; /* 0x140 ~ 0x15C */ + FEMC_SN_Bank_Block block4; /* 0x160 ~ 0x17C */ + FEMC_NAND_Bank bank1; /* 0x180 ~ 0x18C */ + FEMC_NAND_Bank bank2; /* 0x1A0 ~ 0x1BC */ + uint32_t RESERVED1B0[16]; /* 0x1C0 ~ 0x1FC */ + uint32_t RESERVED125[128];/* 0x200 ~ 0x3FC */ + __IO uint32_t FEMC_ECCSTS; /* FEMC ECC Status Register Address offset: 0x400 */ + __IO uint32_t FEMC_ECCCFG; /* FEMC ECC Configure Register Address offset: 0x404 */ + __IO uint32_t FEMC_ECCMD0; /* FEMC ECC Command0 Register Address offset: 0x408 */ + __IO uint32_t FEMC_ECCMD1; /* FEMC ECC Command1 Register Address offset: 0x40C */ + __IO uint32_t FEMC_ECCADDR0; /* FEMC ECC Address0 Register Address offset: 0x410 */ + __IO uint32_t FEMC_ECCADDR1; /* FEMC ECC Address1 Register Address offset: 0x414 */ + __IO uint32_t FEMC_ECCBLK[4]; /* FEMC ECC Block0 Register Address offset: 0x418 */ + __IO uint32_t FEMC_ECCEBLK; /* FEMC ECC Extra Block Register Address offset: 0x428 */ + uint32_t RESERVED42C[53]; /* 0x42C ~ 0x4FC */ + __IO uint32_t FEMC_SNADD1; /* FEMC SRAM/NOR Set Address1 Register Address offset: 0x500 */ + __IO uint32_t FEMC_SNADD2; /* FEMC SRAM/NOR Set Address2 Register Address offset: 0x504 */ + __IO uint32_t FEMC_SNADD3; /* FEMC SRAM/NOR Set Address3 Register Address offset: 0x508 */ + __IO uint32_t FEMC_SNADD4; /* FEMC SRAM/NOR Set Address4 Register Address offset: 0x50C */ + __IO uint32_t FEMC_NADD1; /* FEMC NAND Set Address1 Register Address offset: 0x510 */ + __IO uint32_t FEMC_NADD2; /* FEMC NAND Set Address2 Register Address offset: 0x514 */ + uint32_t RESERVED518[2]; /* 0x518 ~ 0x51C */ + __IO uint32_t FEMC_SNMOD; /* FEMC SRAM/NOR Mode Register Address offset: 0x520 */ + __IO uint32_t FEMC_NMOD; /* FEMC NAND Mode Register Address offset: 0x524 */ + __IO uint32_t FEMC_REMAP; /* FEMC Remap Register Address offset: 0x528 */ +} FEMC_Module; + + +/*** USB High Speed Global Register ***/ + +typedef struct +{ + __IO uint32_t GCTRLSTS; /* USBHS global Control and Status Register Address offset: 0x000 */ + uint32_t Reserved04; /* Reserved04 Address offset: 0x004 */ + __IO uint32_t GAHBCFG; /* Core AHB Configuration Register Address offset: 0x008 */ + __IO uint32_t GCFG; /* Core USB Configuration Register Address offset: 0x00C */ + __IO uint32_t GRSTCTRL; /* Core Reset Register Address offset: 0x010 */ + __IO uint32_t GINTSTS; /* Core Interrupt Register Address offset: 0x014 */ + __IO uint32_t GINTEN; /* Core Interrupt Mask Register Address offset: 0x018 */ + __IO uint32_t GRXSTS; /* Receive Sts Q Read Register Address offset: 0x01C */ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register Address offset: 0x020 */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset: 0x024 */ + __IO uint32_t GNPTXFSIZ_DINEP0TXFSIZ; /* Non Periodic/EP0 Tx FIFO Size/ Register Address offset: 0x028 */ + __IO uint32_t GNPTXFSTS; /* Non Periodic Tx FIFO/Queue Sts reg Address offset: 0x02C */ + uint32_t Reserved30[3]; /* Reserved Address offset: 0x030 */ + __IO uint32_t CID; /* User ID Register Address offset: 0x03C */ + __IO uint32_t Reserved40[6]; /* Reserved40 Address offset: 0x040 */ + __IO uint32_t GPD; /* Power Down Register Address offset: 0x058 */ + __IO uint32_t GDFCFG; /* DFIFO Software Config Register Address offset: 0x05C */ + uint32_t Reserved58[40]; /* Reserved Address offset: 0x60-0xFC */ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg Address offset: 0x100 */ + __IO uint32_t DINEPPTXFSIZ[16]; /* Device IN EP Periodic Transmit FIFO */ +} USB_Global_Registers; + +/*** USBHS Host Mode Register ***/ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register Address offset: 0x400 */ + __IO uint32_t HFRI; /* Host Frame Interval Register Address offset: 0x404 */ + __IO uint32_t HFNUM; /* Host Frame number and Frame Remaining Address offset: 0x408 */ + uint32_t Reserved0C; /* Reserved Address offset: 0x40C */ + __IO uint32_t HPTXFQSTS; /* Host Periodic Tx FIFO/Queue Status register Address offset: 0x410 */ + __IO uint32_t HACHINT; /* Host All Channels Interrupt Register Address offset: 0x414 */ + __IO uint32_t HACHINTEN; /* Host All Channels Interrupt Enable Address offset: 0x418 */ + uint32_t Reserved1C[0x0A]; /* Reserved Address offset: 0x41C */ +} USB_Host_Registers; + +/*** USBHS Host Channel Register ***/ + +typedef struct +{ + __IO uint32_t HCHCTRL; /* Host Channel Control Register Address offset: 0x500 */ + __IO uint32_t HCSCTRL; /* Host Channel Split Control Register Address offset: 0x504 */ + __IO uint32_t HCHINTSTS; /* Host Channel Interrupt Register Address offset: 0x508 */ + __IO uint32_t HCHINTEN; /* Host Channel Interrupt Enable Register Address offset: 0x50C */ + __IO uint32_t HCHTXSIZ; /* Host Channel Transfer Size Register Address offset: 0x510 */ + __IO uint32_t HCHDMADD; /* Host Channel DMA Address Register Address offset: 0x514 */ + uint32_t Reserved[2]; /* Reserved */ +} USB_HostCH_Registers; + + +/*** USBHS Device Register ***/ + +typedef struct +{ + __IO uint32_t DCFG; /* dev Configuration Register Address offset: 0x800 */ + __IO uint32_t DCTRL; /* dev Control Register Address offset: 0x804 */ + __IO uint32_t DSTS; /* dev Status Register Address offset: 0x808 */ + uint32_t Reserved0C; /* Reserved Address offset: 0x80C */ + __IO uint32_t DINEPINTEN; /* dev IN Endpoint Interrupt Enable Address offset: 0x810 */ + __IO uint32_t DOUTEPINTEN; /* dev OUT Endpoint Interrupt Enable Address offset: 0x814 */ + __IO uint32_t DAEPINTSTS; /* dev All Endpoints Interrupt Status Address offset: 0x818 */ + __IO uint32_t DAEPINTEN; /* dev All Endpoints Interrupt Enable Address offset: 0x81C */ + uint32_t Reserved20[4]; /* Reserved Address offset: 0x820-0x82C*/ + __IO uint32_t DTHRCTRL; /* dev threshold Contrl register Address offset: 0x830 */ + __IO uint32_t DINEPFEINTEN; /* dev IN EP fifo empty interrupt enable Address offset: 0x834 */ + __IO uint32_t DEEPINTSTS; /* Each EP interrupt Status register Address offset: 0x838 */ + __IO uint32_t DEEPINTEN; /* Each EP interrupt enable Address offset: 0x83C */ + __IO uint32_t DINEPXINTEN[9]; /* dedicated EP mask Address offset: 0x840-0x860 */ + uint32_t Reserved64[7]; /* Reserved Address offset: 0x864-0x87C */ + __IO uint32_t DOUTEPXINTEN[9]; /* dedicated EP msk Address offset: 0x880-0x8A0 */ +} USB_Device_Registers; + +/*** USBHS IN Endpoint Register ***/ + +typedef struct +{ + __IO uint32_t DINEPCTRL; /* dev IN Endpoint Control Register Address offset: 0x900 + (ep_num * 0x20) + 0x00 */ + uint32_t Reserved04; /* Reserved Address offset: 0x900 + (ep_num * 0x20) + 0x04 */ + __IO uint32_t DINEPINTSTS; /* dev IN Endpoint Interrupt Stauts Address offset: 0x900 + (ep_num * 0x20) + 0x08 */ + uint32_t Reserved0C; /* Reserved Address offset: 0x900 + (ep_num * 0x20) + 0x0C */ + __IO uint32_t DINEPTXSIZ; /* dev IN Endpoint Txfer Size Address offset: 0x900 + (ep_num * 0x20) + 0x10 */ + __IO uint32_t DINEPDMADD; /* dev IN Endpoint DMA Address Address offset: 0x900 + (ep_num * 0x20) + 0x14 */ + __IO uint32_t DINEPTXFSTS; /* dev IN Endpoint Tx FIFO Status Address offset: 0x900 + (ep_num * 0x20) + 0x18 */ + uint32_t Reserved1C; /* Reserved Address offset: 0x900 + (ep_num * 0x20) + 0x1C */ +} USB_INEP_Registers; + + +/*** USBHS OUT Endpoint Register ***/ + +typedef struct +{ + __IO uint32_t DOUTEPCTRL; /* dev OUT Endpoint Control Register Address offset: 0xB00 + (ep_num * 0x20) + 00 */ + uint32_t Reserved0; /* Reserved Address offset: 0xB00 + (ep_num * 0x20) + 04 */ + __IO uint32_t DOUTEPINTSTS; /* dev OUT Endpoint Interrupt Stauts Address offset: 0xB00 + (ep_num * 0x20) + 08 */ + uint32_t Reserved1; /* Reserved Address offset: 0xB00 + (ep_num * 0x20) + 0C */ + __IO uint32_t DOUTEPTXSIZ; /* dev OUT Endpoint Txfer Size Address offset: 0xB00 + (ep_num * 0x20) + 10 */ + __IO uint32_t DOUTEPDMADD; /* dev OUT Endpoint DMA Address Address offset: 0xB00 + (ep_num * 0x20) + 14 */ + uint32_t Reserved18[2]; /* Reserved */ +} USB_OUTEP_Registers; + +/*** USBHS PWR Control Register ***/ + +typedef struct +{ + __IO uint32_t PWRCTRL; /* USBHS Power Control Register Address offset: 0xE00 */ + __IO uint32_t PWRCTRL1; /* USBHS Power Control1 Register Address offset: 0xE04 */ +} USB_PWR_Registers; + +/*** USBHS Wrapper Register ***/ + +typedef struct +{ + __IO uint32_t WRPCTRL; /* USBHS Wrapper Control Register Address offset: 0x000 */ + __IO uint32_t WRPCFG; /* USBHS Wrapper Configuration Register Address offset: 0x004 */ +} USB_Wrapper_Registers; + +/*** DSI Wrapper Register ***/ +typedef struct +{ + __IO uint32_t DSI_WRPCTRL; /* DSI Wrapper Control Register Address offset: 0x000 */ + __IO uint32_t DSI_WRPSTS; /* DSI Wrapper Status Register Address offset: 0x004 */ + __IO uint32_t DSIPHY_CTRL1; /* DSI PHY Control Register1 Address offset: 0x008 */ + __IO uint32_t DSIPHY_CTRL2; /* DSI PHY Control Register2 Address offset: 0x00C */ + __IO uint32_t DSIPHY_CTRL3; /* DSI PHY Control Register3 Address offset: 0x010 */ + __IO uint32_t DSIPHY_CTRL4; /* DSI PHY Control Register4 Address offset: 0x014 */ + uint32_t Reserved0[19]; /* Reserved Address offset: 0x018~0x060 */ + __IO uint32_t DSIPHY_PLLCTRL1; /* DSI PHY PLL Control Register1 Address offset: 0x064 */ + __IO uint32_t DSIPHY_PLLCTRL2; /* DSI PHY PLL Control Register2 Address offset: 0x068 */ + __IO uint32_t DSIPHY_PLLCTRL3; /* DSI PHY PLL Control Register3 Address offset: 0x06C */ + __IO uint32_t DSIPHY_PLLCTRL4; /* DSI PHY PLL Control Register4 Address offset: 0x070 */ + __IO uint32_t DSIPHY_PLLCTRL5; /* DSI PHY PLL Control Register5 Address offset: 0x074 */ + __IO uint32_t DSIPHY_PLLSTS; /* DSI PHY PLL Status Register5 Address offset: 0x078 */ +}DSI_Wrapper_Module; + +/*** DSI Register ***/ +typedef struct +{ + __IO uint32_t DSI_NUMLANES; /* DSI Set number of active lanes Register Address offset: 0x000 */ + __IO uint32_t DSI_CONTHSCLK; /* DSI Set Host Continuous MIPI clock mode Address offset: 0x004 */ + __IO uint32_t DSI_TPRE; /* DSI Set wait clock after enabling clock lane Address offset: 0x008 */ + __IO uint32_t DSI_TPOST; /* DSI Set Wait clock before enter LP mode after data lane in Stop State Address offset: 0x00C */ + __IO uint32_t DSI_TXGAP; /* DSI Set Wait clock after clock lane in LP mode before enabling clock Address offset: 0x010 */ + __IO uint32_t DSI_AUTOINSERT_EOTP; /* DSI enable automatically insert an EoTp short packet Address offset: 0x014 */ + __IO uint32_t DSI_DISRXCRCCHK; /* DSI disable check payload CRC from longs packets Address offset: 0x018 */ + __IO uint32_t DSI_HSTXTOCNT; /* DSI Set HS TX timeout count Address offset: 0x01C */ + __IO uint32_t DSI_LRXTOCNT; /* DSI Set low power RX timeout count Address offset: 0x020 */ + __IO uint32_t DSI_BTATOCNT; /* DSI set host bus turn around timeout Address offset: 0x024 */ + __IO uint32_t DSI_TWAKEUP; /* DSI set DPHY Twakeup timing Address offset: 0x028 */ + __IO uint32_t DSI_DISBST; /* DSI Disable host bursting Address offset: 0x02C */ + uint32_t Reserved0[3]; /* Reserved Address offset: 0x030~0x038 */ + __IO uint32_t DSI_STS; /* DSI Status Register Address offset: 0x03C */ + __IO uint32_t DSI_ERRSTS; /* DSI Error Status Register Address offset: 0x040 */ + uint32_t Reserved1[7]; /* Reserved Address offset: 0x044~0x05C */ + __IO uint32_t DSI_CLKLANEN; /* DSI enable clock lane Address offset: 0x060 */ + __IO uint32_t DSI_DATLANEN; /* DSI enable data lane Address offset: 0x064 */ + uint32_t Reserved2[22]; /* DSI Register5 Address offset: 0x068~0x0BC */ + __IO uint32_t DSI_SKEWCALTIMI; /* DSI Register5 Address offset: 0x0C0 */ + __IO uint32_t DSI_SKEWCALTIMP; /* DSI Register5 Address offset: 0x0C4 */ + __IO uint32_t DSI_ALTCALTIM; /* DSI Register5 Address offset: 0x0C8 */ + __IO uint32_t DSI_SKEWCALINE; /* DSI Register5 Address offset: 0x0CC */ + uint32_t Reserved3[76]; /* DSI Register5 Address offset: 0x0D0~0x1FC */ + __IO uint32_t VID_EN; /* DSI Register5 Address offset: 0x200 */ + __IO uint32_t VID_PIXPERPKT; /* DSI Register5 Address offset: 0x204 */ + __IO uint32_t VID_PIXPLDSIZ; /* DSI Register5 Address offset: 0x208 */ + __IO uint32_t VID_PIXALIGN; /* DSI Register5 Address offset: 0x20C */ + __IO uint32_t VID_PIXFMT; /* DSI Register5 Address offset: 0x210 */ + __IO uint32_t VID_VSYNCPOL; /* DSI Register5 Address offset: 0x214 */ + __IO uint32_t VID_HSYNCPOL; /* DSI Register5 Address offset: 0x218 */ + __IO uint32_t VID_VIDEOMOD; /* DSI Register5 Address offset: 0x21C */ + __IO uint32_t VID_OVERIDE; /* DSI Register5 Address offset: 0x220 */ + __IO uint32_t VID_STD; /* DSI Register5 Address offset: 0x224 */ + __IO uint32_t VID_HFP; /* DSI Register5 Address offset: 0x228 */ + __IO uint32_t VID_HBP; /* DSI Register5 Address offset: 0x22C */ + __IO uint32_t VID_HSA; /* DSI Register5 Address offset: 0x230 */ + __IO uint32_t VID_PKTPERLINE; /* DSI Register5 Address offset: 0x234 */ + __IO uint32_t VID_VBP; /* DSI Register5 Address offset: 0x238 */ + __IO uint32_t VID_VFP; /* DSI Register5 Address offset: 0x23C */ + __IO uint32_t VID_BLLPMOD; /* DSI Register5 Address offset: 0x240 */ + __IO uint32_t VID_NULLPKTBLLP; /* DSI Register5 Address offset: 0x244 */ + __IO uint32_t VID_VACT; /* DSI Register5 Address offset: 0x248 */ + __IO uint32_t VID_VC; /* DSI Register5 Address offset: 0x24C */ + __IO uint32_t VID_EXTPKTEN; /* DSI Register5 Address offset: 0x250 */ + __IO uint32_t VID_VSSPLD; /* DSI Register5 Address offset: 0x254 */ + __IO uint32_t VID_PLDPERPKT; /* DSI Register5 Address offset: 0x258 */ + uint32_t Reserved4[9]; /* DSI Register5 Address offset: 0x25C~0x27C */ + __IO uint32_t DSI_TXPLD; /* DSI Register5 Address offset: 0x280 */ + __IO uint32_t DSI_PKTCTRL; /* DSI Register5 Address offset: 0x284 */ + __IO uint32_t DSI_SENDPKT; /* DSI Register5 Address offset: 0x288 */ + __IO uint32_t DSI_PKTSTS; /* DSI Register5 Address offset: 0x28C */ + __IO uint32_t DSI_PKTFWRLVL; /* DSI Register5 Address offset: 0x290 */ + __IO uint32_t DSI_PKTFRDLVL; /* DSI Register5 Address offset: 0x294 */ + __IO uint32_t DSI_PKTRXPLD; /* DSI Register5 Address offset: 0x298 */ + __IO uint32_t DSI_PKTRXHDR; /* DSI Register5 Address offset: 0x29C */ + uint32_t Reserved5[4]; /* DSI Register5 Address offset: 0x2A0~0x2AC */ + __IO uint32_t DSI_IFPRIOSEL; /* DSI Register5 Address offset: 0x2B0 */ +}DSI_Module; + + +typedef struct +{ +__IO uint32_t C1_PWR_CR; //0x00 +__IO uint32_t C1_PWR_CSR; //0x04 +__IO uint32_t C1_PWR_CR2; //0x08 +uint32_t RESERVE0[5]; +__IO uint32_t C2_PWR_CR; //0x20 +__IO uint32_t C2_PWR_CSR; //0x24 +__IO uint32_t C2_PWR_CR2; //0x28 +uint32_t RESERVE1[5]; +__IO uint32_t SYS_PWR_CR; //0x40 +__IO uint32_t SYS_PWR_CSR; //0x44 +__IO uint32_t SYS_PWR_CR2; //0x48 +__IO uint32_t SYS_PWR_CR3; //0x4C +__IO uint32_t SYS_PWR_CR4; //0x50 +__IO uint32_t SYS_PWR_BOR_CR; //0x54 +__IO uint32_t IP_MEMPWR_CR; //0x58 +__IO uint32_t IP_MEMPWR_CSR; //0x5C +__IO uint32_t C1_MEM_LPCR1; //0x60 +__IO uint32_t C1_MEM_LPSR1; //0x64 +__IO uint32_t C1_TCM_PG0; //0x68 +__IO uint32_t C1_TCM_PG1; //0x6C +__IO uint32_t C1_TCM_RET1N0; //0x70 +__IO uint32_t C1_TCM_RET1N1; //0x74 +__IO uint32_t C1_TCM_RET2N0; //0x78 +__IO uint32_t C1_TCM_RET2N1; //0x7C +uint32_t RESERVE2[4]; +__IO uint32_t C2_MEM_LPCR; //0x90 +uint32_t RESERVE3[3]; +__IO uint32_t SYS_MEM_LPCR; //0xA0 +uint32_t RESERVE4[3]; +__IO uint32_t SYS_PWR_SHRT_CR; //0xB0 +__IO uint32_t SYS_PWR_MDMA_CR; //0xB4 +__IO uint32_t SYS_PWR_ETHCAT_CR; //0xB8 +uint32_t RESERVE5[17]; +__IO uint32_t PWR_EMC_CR0; //0x100 +__IO uint32_t PWR_EMC_CR1; //0x104 +__IO uint32_t PWR_EMC_CR2; //0x108 +__IO uint32_t PWR_EMC_CR3; //0x10C +__IO uint32_t PWR_EMC_CR4; //0x110 +__IO uint32_t PWR_EMC_CR5; //0x114 +__IO uint32_t PWR_EMC_CR6; //0x118 +__IO uint32_t PWR_EMC_CR7; //0x11C +__IO uint32_t PWR_BKP_EMC_CR0; //0x120 +__IO uint32_t PWR_BKP_EMC_CR1; //0x124 + } PWR_TypeDef; + + /** Reset and Clock Control **/ + typedef struct + { + __IO uint32_t PLL1CTRL1; //0x00 + __IO uint32_t PLL1CTRL2; //0x04 + uint32_t RESERVED1; //0x08 + uint32_t RESERVED2; //0x0C + __IO uint32_t PLL2CTRL1; //0x10 + __IO uint32_t PLL2CTRL2; //0x14 + uint32_t RESERVED3; //0x18 + uint32_t RESERVED4; //0x1C + __IO uint32_t PLL3CTRL1; //0x20 + __IO uint32_t PLL3CTRL2; //0x24 + uint32_t RESERVED5; //0x28 + uint32_t RESERVED6; //0x2C + __IO uint32_t SRCCTRL1; //0x30 + __IO uint32_t PLL1DIV; //0x34 + __IO uint32_t PLL2DIV; //0x38 + __IO uint32_t PLL3DIV; //0x3C + __IO uint32_t SYSBUSDIV1; //0x40 + __IO uint32_t SYSBUSDIV2; //0x44 + __IO uint32_t BOOTMODE; //0x48 + __IO uint32_t AHB1DIV1; //0x4C + __IO uint32_t AHB1SEL1; //0x50 + __IO uint32_t AHB1EN1; //0x54 + __IO uint32_t AHB1EN2; //0x58 + __IO uint32_t AHB1EN3; //0x5C + __IO uint32_t AHB1EN4; //0x60 + __IO uint32_t AHB1RST1; //0x64 + __IO uint32_t AHB1RST2; //0x68 + __IO uint32_t AHB1RST3; //0x6C + __IO uint32_t AHB1RST4; //0x70 + __IO uint32_t APB1DIV1; //0x74 + __IO uint32_t APB1SEL1; //0x78 + __IO uint32_t APB1SEL2; //0x7C + __IO uint32_t APB1EN1; //0x80 + __IO uint32_t APB1EN2; //0x84 + __IO uint32_t APB1EN3; //0x88 + __IO uint32_t APB1EN4; //0x8C + __IO uint32_t APB1EN5; //0x90 + __IO uint32_t APB1RST1; //0x94 + __IO uint32_t APB1RST2; //0x98 + __IO uint32_t APB1RST3; //0x9C + __IO uint32_t APB1RST4; //0xA0 + __IO uint32_t APB1RST5; //0xA4 + __IO uint32_t AHB2DIV1; //0xA8 + __IO uint32_t AHB2SEL1; //0xAC + __IO uint32_t AHB2EN1; //0xB0 + __IO uint32_t AHB2RST1; //0xB4 + __IO uint32_t APB2DIV1; //0xB8 + __IO uint32_t APB2SEL1; //0xBC + __IO uint32_t APB2SEL2; //0xC0 + __IO uint32_t APB2EN1; //0xC4 + __IO uint32_t APB2EN2; //0xC8 + __IO uint32_t APB2EN3; //0xCC + __IO uint32_t APB2EN4; //0xD0 + __IO uint32_t APB2RST1; //0xD4 + __IO uint32_t APB2RST2; //0xD8 + __IO uint32_t APB2RST3; //0xDC + __IO uint32_t APB2RST4; //0xE0 + __IO uint32_t AHB5EN1; //0xE4 + __IO uint32_t AHB5EN2; //0xE8 + __IO uint32_t AHB5RST1; //0xEC + __IO uint32_t AHB5RST2; //0xF0 + __IO uint32_t APB5DIV1; //0xF4 + __IO uint32_t APB5SEL1; //0xF8 + __IO uint32_t APB5EN1; //0xFC + __IO uint32_t APB5EN2; //0x100 + __IO uint32_t APB5RST1; //0x104 + __IO uint32_t APB5RST2; //0x108 + __IO uint32_t RDDIV1; //0x10C + __IO uint32_t RDSEL1; //0x110 + __IO uint32_t RDEN1; //0x114 + __IO uint32_t RDEN2; //0x118 + __IO uint32_t RDRST1; //0x11C + __IO uint32_t RDRST2; //0x120 + __IO uint32_t BDCTRL; //0x124 + __IO uint32_t CTRLSTS; //0x128 + __IO uint32_t CLKINT1; //0x12C + __IO uint32_t CLKINT2; //0x130 + __IO uint32_t CFG1; //0x134 + __IO uint32_t AXIDIV1; //0x138 + __IO uint32_t AXISEL1; //0x13C + __IO uint32_t AXIEN1; //0x140 + __IO uint32_t AXIEN2; //0x144 + __IO uint32_t AXIEN3; //0x148 + __IO uint32_t AXIEN4; //0x14C + __IO uint32_t AXIRST1; //0x150 + __IO uint32_t AXIRST2; //0x154 + __IO uint32_t AXIRST3; //0x158 + __IO uint32_t AXIRST4; //0x15C + __IO uint32_t CFG2; //0x160 + __IO uint32_t CFG3; //0x164 + __IO uint32_t CFG4; //0x168 + __IO uint32_t SRCCTRL2; //0x16C + __IO uint32_t CFG5; //0x170 + __IO uint32_t M4RSTREL; //0x174 + __IO uint32_t AXIDIV2; //0x178 + __IO uint32_t AXISEL2; //0x17C + uint32_t RESERVED7; //0x180 + uint32_t RESERVED8; //0x184 + uint32_t RESERVED9; //0x188 + __IO uint32_t SHRPLLCTRL1; //0x18C + __IO uint32_t SHRPLLCTRL2; //0x190 + __IO uint32_t AHB1DIV2; //0x194 + __IO uint32_t LSERDDL; //0x198 + __IO uint32_t MSIRDDL; //0x19C + __IO uint32_t HSERDDL; //0x1A0 + __IO uint32_t PLLSFTLK; //0x1A4 + __IO uint32_t RDCTRL1; //0x1A8 + __IO uint32_t RDCTRL2; //0x1AC + __IO uint32_t RDCTRL3; //0x1B0 + __IO uint32_t AHB2EN2; //0x1B4 + __IO uint32_t AHB9DIV1; //0x1B8 + __IO uint32_t AHB9SEL1; //0x1BC + __IO uint32_t AHB9EN1; //0x1C0 + __IO uint32_t AHB9RST1; //0x1C4 + __IO uint32_t HSEOS; //0x1C8 + __IO uint32_t LSEOS; //0x1CC + __IO uint32_t HSECAL; //0x1D0 + __IO uint32_t CLKINT3; //0x1D4 + __IO uint32_t PLLFD; //0x1D8 + __IO uint32_t SRCCTRL3; //0x1DC + __IO uint32_t LSICSSDL; //0x1E0 + } RCC_Module; + + + + + +/*** @brief Debug MCU ***/ + +typedef struct +{ + __IO uint32_t ID; //0x00 + __IO uint32_t CTRL; //0x04 + __IO uint32_t M7APB1FZ; //0x08 + __IO uint32_t M4APB1FZ; //0x0C + __IO uint32_t M7APB2FZ; //0x10 + __IO uint32_t M4APB2FZ; //0x14 + __IO uint32_t M7APB5FZ; //0x18 + __IO uint32_t M4APB5FZ; //0x1C + __IO uint32_t M7APB6FZ; //0x20 + __IO uint32_t M4APB6FZ; //0x24 +}DBG_Module; + +/*** Ethernet MAC ***/ +typedef struct +{ + __IO uint32_t MACCFG; /* Offset: 0x0000 */ + __IO uint32_t MACEXTCFG; /* Offset: 0x0004 */ + __IO uint32_t MACPFLT; /* Offset: 0x0008 */ + __IO uint32_t MACWDGTO; /* Offset: 0x000C */ + __IO uint32_t MACHASHTR0; /* Offset: 0x0010 */ + __IO uint32_t MACHASHTR1; /* Offset: 0x0014 */ + uint32_t RESERVED0[14]; + __IO uint32_t MACVLANTAG; /* Offset: 0x0050 */ + uint32_t RESERVED1; + __IO uint32_t MACVHASHT; /* Offset: 0x0058 */ + uint32_t RESERVED2; + __IO uint32_t MACVLANINC; /* Offset: 0x0060 */ + __IO uint32_t MACIVLANINC; /* Offset: 0x0064 */ + uint32_t RESERVED3[2]; + __IO uint32_t MACTXFLWCTRL; /* Offset: 0x0070 */ + uint32_t RESERVED4[7]; + __IO uint32_t MACRXFLWCTRL; /* Offset: 0x0090 */ + uint32_t RESERVED5[7]; + __IO uint32_t MACINTSTS; /* Offset: 0x00B0 */ + __IO uint32_t MACINTEN; /* Offset: 0x00B4 */ + __IO uint32_t MACRXTXSTS; /* Offset: 0x00B8 */ + uint32_t RESERVED6; + __IO uint32_t MACPMTCTRLSTS; /* Offset: 0x00C0 */ + __IO uint32_t MACRWUPFLT; /* Offset: 0x00C4 */ + uint32_t RESERVED7[2]; + __IO uint32_t MACLPICTRLSTS; /* Offset: 0x00D0 */ + __IO uint32_t MACLPITIMCTRL; /* Offset: 0x00D4 */ + __IO uint32_t MACLPIETYTIM; /* Offset: 0x00D8 */ + __IO uint32_t MAC1USTICCNT; /* Offset: 0x00DC */ + uint32_t RESERVED8[12]; + __IO uint32_t MACVER; /* Offset: 0x0110 */ + __IO uint32_t MACDBG; /* Offset: 0x0114 */ + uint32_t RESERVED9; + __IO uint32_t MACHWF0; /* Offset: 0x011C */ + __IO uint32_t MACHWF1; /* Offset: 0x0120 */ + __IO uint32_t MACHWF2; /* Offset: 0x0124 */ + __IO uint32_t MACHWF3; /* Offset: 0x0128 */ + uint32_t RESERVED10[53]; + __IO uint32_t MACMDIOADDR; /* Offset: 0x0200 */ + __IO uint32_t MACMDIODATA; /* Offset: 0x0204 */ + uint32_t RESERVED11[2]; + __IO uint32_t MACARPADDR; /* Offset: 0x0210 */ + uint32_t RESERVED12[7]; + __IO uint32_t MACCSRSWCTRL; /* Offset: 0x0230 */ + uint32_t RESERVED13[3]; + __IO uint32_t MACPTNS; /* Offset: 0x0240 */ + __IO uint32_t MACPTUPDT; /* Offset: 0x0244 */ + uint32_t RESERVED14[46]; + __IO uint32_t MACADDR0H; /* Offset: 0x0300 */ + __IO uint32_t MACADDR0L; /* Offset: 0x0304 */ + __IO uint32_t MACADDR1H; /* Offset: 0x0308 */ + __IO uint32_t MACADDR1L; /* Offset: 0x030C */ + __IO uint32_t MACADDR2H; /* Offset: 0x0310 */ + __IO uint32_t MACADDR2L; /* Offset: 0x0314 */ + __IO uint32_t MACADDR3H; /* Offset: 0x0318 */ + __IO uint32_t MACADDR3L; /* Offset: 0x031C */ + uint32_t RESERVED15[248]; + __IO uint32_t MMCCTRL; /* Offset: 0x0700 */ + __IO uint32_t MMCRXINT; /* Offset: 0x0704 */ + __IO uint32_t MMCTXINT; /* Offset: 0x0708 */ + __IO uint32_t MMCRXINTMSK; /* Offset: 0x070C */ + __IO uint32_t MMCTXINTMSK; /* Offset: 0x0710 */ + uint32_t RESERVED16[14]; + __IO uint32_t MMCTXSCGP; /* Offset: 0x074C */ + __IO uint32_t MMCTXMCGP; /* Offset: 0x0750 */ + uint32_t RESERVED17[5]; + __IO uint32_t MMCTXPCG; /* Offset: 0x0768 */ + uint32_t RESERVED18[8]; + __IO uint32_t MMCRXBPG; /* Offset: 0x078C */ + __IO uint32_t MMCRXMPG; /* Offset: 0x0790 */ + __IO uint32_t MMCRXCRCEP; /* Offset: 0x0794 */ + __IO uint32_t MMCRXAEP; /* Offset: 0x0798 */ + uint32_t RESERVED19[10]; + __IO uint32_t MMCRXUPG; /* Offset: 0x07C4 */ + uint32_t RESERVED20[9]; + __IO uint32_t MMCTXLPIUS; /* Offset: 0x07EC */ + __IO uint32_t MMCTXLPITRAN; /* Offset: 0x07F0 */ + __IO uint32_t MMCRXLPIUS; /* Offset: 0x07F4 */ + __IO uint32_t MMCRXLPITRAN; /* Offset: 0x07F8 */ + uint32_t RESERVED21; + __IO uint32_t MMCIPCRXINTMSK; /* Offset: 0x0800 */ + uint32_t RESERVED22; + __IO uint32_t MMCIPCRXINT; /* Offset: 0x0808 */ + uint32_t RESERVED23; + __IO uint32_t MMCRXIPV4GP; /* Offset: 0x0810 */ + uint32_t RESERVED24[4]; + __IO uint32_t MMCRXIPV6GP; /* Offset: 0x0824 */ + uint32_t RESERVED25[2]; + __IO uint32_t MMCRXUDPGP; /* Offset: 0x0830 */ + __IO uint32_t MMCRXUDPEP; /* Offset: 0x0834 */ + __IO uint32_t MMCRXTCPGP; /* Offset: 0x0838 */ + __IO uint32_t MMCRXTCPEP; /* Offset: 0x083C */ + __IO uint32_t MMCRXICMPGP; /* Offset: 0x0840 */ + __IO uint32_t MMCRXICMPEP; /* Offset: 0x0844 */ + uint32_t RESERVED26[46]; + __IO uint32_t MACL3L4F0CTRL; /* Offset: 0x0900 */ + __IO uint32_t MACL4F0PORT; /* Offset: 0x0904 */ + uint32_t RESERVED27[2]; + __IO uint32_t MACL3F0ADDR0; /* Offset: 0x0910 */ + __IO uint32_t MACL3F0ADDR1; /* Offset: 0x0914 */ + __IO uint32_t MACL3F0ADDR2; /* Offset: 0x0918 */ + __IO uint32_t MACL3F0ADDR3; /* Offset: 0x091C */ + uint32_t RESERVED28[4]; + __IO uint32_t MACL3L4F1CTRL; /* Offset: 0x0930 */ + __IO uint32_t MACL4F1PORT; /* Offset: 0x0934 */ + uint32_t RESERVED29[2]; + __IO uint32_t MACL3F1ADDR0; /* Offset: 0x0940 */ + __IO uint32_t MACL3F1ADDR1; /* Offset: 0x0944 */ + __IO uint32_t MACL3F1ADDR2; /* Offset: 0x0948 */ + __IO uint32_t MACL3F1ADDR3; /* Offset: 0x094C */ + uint32_t RESERVED30[108]; + __IO uint32_t MACTSCTRL; /* Offset: 0x0B00 */ + __IO uint32_t MACSUBSINC; /* Offset: 0x0B04 */ + __IO uint32_t MACSYSTS; /* Offset: 0x0B08 */ + __IO uint32_t MACSYSTNS; /* Offset: 0x0B0C */ + __IO uint32_t MACSYSTSUP; /* Offset: 0x0B10 */ + __IO uint32_t MACSYSTNSUP; /* Offset: 0x0B14 */ + __IO uint32_t MACTSADD; /* Offset: 0x0B18 */ + __IO uint32_t MACSYSTHWS; /* Offset: 0x0B1C */ + __IO uint32_t MACTSSTS; /* Offset: 0x0B20 */ + uint32_t RESERVED31[3]; + __IO uint32_t MACTXTSSTSNS; /* Offset: 0x0B30 */ + __IO uint32_t MACTXTSSTSS; /* Offset: 0x0B34 */ + uint32_t RESERVED32[2]; + __IO uint32_t MACAUXCTRL; /* Offset: 0x0B40 */ + uint32_t RESERVED33; + __IO uint32_t MACAUXTSNS; /* Offset: 0x0B48 */ + __IO uint32_t MACAUXTSS; /* Offset: 0x0B4C */ + __IO uint32_t MACTSIGASYC; /* Offset: 0x0B50 */ + __IO uint32_t MACTSEGASYC; /* Offset: 0x0B54 */ + __IO uint32_t MACTSIGCNS; /* Offset: 0x0B58 */ + __IO uint32_t MACTSEGCNS; /* Offset: 0x0B5C */ + uint32_t RESERVED34[2]; + __IO uint32_t MACTSIGLAT; /* Offset: 0x0B68 */ + __IO uint32_t MACTSEGLAT; /* Offset: 0x0B6C */ + __IO uint32_t MACPPSCTRL; /* Offset: 0x0B70 */ + uint32_t RESERVED35[3]; + __IO uint32_t MACPPSTTS; /* Offset: 0x0B80 */ + __IO uint32_t MACPPSTTNS; /* Offset: 0x0B84 */ + __IO uint32_t MACPPSINTE; /* Offset: 0x0B88 */ + __IO uint32_t MACPPSWID; /* Offset: 0x0B8C */ + uint32_t RESERVED36[12]; + __IO uint32_t MACPTOCTRL; /* Offset: 0x0BC0 */ + __IO uint32_t MACSRCPID0; /* Offset: 0x0BC4 */ + __IO uint32_t MACSRCPID1; /* Offset: 0x0BC8 */ + __IO uint32_t MACSRCPID2; /* Offset: 0x0BCC */ + __IO uint32_t MACLOGMINTE; /* Offset: 0x0BD0 */ + uint32_t RESERVED37[11]; + + __IO uint32_t MTLOPMOD; /* Offset: 0x0C00 */ + uint32_t RESERVED38[7]; + __IO uint32_t MTLINTSTS; /* Offset: 0x0C20 */ + uint32_t RESERVED39[55]; + __IO uint32_t MTLTXQOPMOD; /* Offset: 0x0D00 */ + __IO uint32_t MTLTXQUDF; /* Offset: 0x0D04 */ + __IO uint32_t MTLTXQDBG; /* Offset: 0x0D08 */ + uint32_t RESERVED40[8]; + __IO uint32_t MTLQINTCTRLSTS; /* Offset: 0x0D2C */ + __IO uint32_t MTLRXQOPMOD; /* Offset: 0x0D30 */ + __IO uint32_t MTLRXQMPOFCNT; /* Offset: 0x0D34 */ + __IO uint32_t MTLRXQDBG; /* Offset: 0x0D38 */ + uint32_t RESERVED41[177]; + + __IO uint32_t DMAMODE; /* Offset: 0x1000 */ + __IO uint32_t DMASBMODE; /* Offset: 0x1004 */ + __IO uint32_t DMAINTSTS; /* Offset: 0x1008 */ + __IO uint32_t DMADBGSTS; /* Offset: 0x100C */ + uint32_t RESERVED42[60]; + __IO uint32_t DMACH0CTRL; /* Offset: 0x1100 */ + __IO uint32_t DMACH0TXCTRL; /* Offset: 0x1104 */ + __IO uint32_t DMACH0RXCTRL; /* Offset: 0x1108 */ + uint32_t RESERVED43[2]; + __IO uint32_t DMACH0TXDLA; /* Offset: 0x1114 */ + uint32_t RESERVED44; + __IO uint32_t DMACH0RXDLA; /* Offset: 0x111C */ + __IO uint32_t DMACH0TXDTP; /* Offset: 0x1120 */ + uint32_t RESERVED45; + __IO uint32_t DMACH0RXDTP; /* Offset: 0x1128 */ + __IO uint32_t DMACH0TXDRLEN; /* Offset: 0x112C */ + __IO uint32_t DMACH0RXCTRL2; /* Offset: 0x1130 */ + __IO uint32_t DMACH0INTEN; /* Offset: 0x1134 */ + __IO uint32_t DMACH0RXINTWT; /* Offset: 0x1138 */ + uint32_t RESERVED46[2]; + __IO uint32_t DMACH0CATXD; /* Offset: 0x1144 */ + uint32_t RESERVED47; + __IO uint32_t DMACH0CARXD; /* Offset: 0x114C */ + uint32_t RESERVED48; + __IO uint32_t DMACH0CATXB; /* Offset: 0x1154 */ + uint32_t RESERVED49; + __IO uint32_t DMACH0CARXB; /* Offset: 0x115C */ + __IO uint32_t DMACH0STS; /* Offset: 0x1160 */ + __IO uint32_t DMACH0DPCNT; /* Offset: 0x1164 */ + uint32_t RESERVED50; + __IO uint32_t DMACH0RXERICNT; /* Offset: 0x116C */ +} ETH_Module; + +/*** EXTI(External Interrupt/Event Controller) Regiters ***/ +typedef struct +{ + __IO uint32_t RT_CFG[2]; //0x00 + __IO uint32_t RESERVED0[6]; + __IO uint32_t FT_CFG[2]; //0x20 + __IO uint32_t RESERVED1[6]; + __IO uint32_t SWIE[2]; //0x40 + __IO uint32_t RESERVED2[6]; + __IO uint32_t M7IMASK[2]; //0x60 + __IO uint32_t RESERVED3[6]; + __IO uint32_t M4IMASK[2]; //0x80 + __IO uint32_t RESERVED4[6]; + __IO uint32_t M7EMASK[2]; //0xA0 + __IO uint32_t RESERVED5[6]; + __IO uint32_t M4EMASK[2]; //0xC0 + __IO uint32_t RESERVED6[6]; + __IO uint32_t M7PEND[2]; //0xE0 + __IO uint32_t RESERVED7[6]; + __IO uint32_t M4PEND[2]; //0x100 + __IO uint32_t RESERVED8[6]; + __IO uint32_t M7IMASK_DRC[2]; //0x120 + __IO uint32_t RESERVED9[6]; + __IO uint32_t M4IMASK_DRC[2]; //0x140 + __IO uint32_t RESERVED10[6]; + __IO uint32_t M7EMASK_DRC[2]; //0x160 + __IO uint32_t RESERVED11[6]; + __IO uint32_t M4EMASK_DRC[2]; //0x180 + __IO uint32_t RESERVED12[14]; + __IO uint32_t TSSEL; //0x1C0 +}EXTI_Module; + +/*** FDCAN(Flexible Datarate Controller Area Network) Registers ***/ +typedef struct +{ + __IO uint32_t CREL; //0x000 + __IO uint32_t ENDN; //0x004 + __IO uint32_t RESERVED1; //0x008 + __IO uint32_t DBTP; //0x00C + __IO uint32_t TEST; //0x010 + __IO uint32_t RWD; //0x014 + __IO uint32_t CCCR; //0x018 + __IO uint32_t NBTP; //0x01C + __IO uint32_t TSCC; //0x020 + __IO uint32_t TSCV; //0x024 + __IO uint32_t TOCC; //0x028 + __IO uint32_t TOCV; //0x02C + __IO uint32_t RESERVED2[4]; //0x030 + __IO uint32_t ECR; //0x040 + __IO uint32_t PSR; //0x044 + __IO uint32_t TDCR; //0x048 + __IO uint32_t RESERVED3; //0x04C + __IO uint32_t IR; //0x050 + __IO uint32_t IE; //0x054 + __IO uint32_t ILS; //0x058 + __IO uint32_t ILE; //0x05C + __IO uint32_t RESERVED4[8]; //0x060 + __IO uint32_t GFC; //0x080 + __IO uint32_t SIDFC; //0x084 + __IO uint32_t XIDFC; //0x088 + __IO uint32_t RESERVED5; //0x08C + __IO uint32_t XIDAM; //0x090 + __IO uint32_t HPMS; //0x094 + __IO uint32_t NDAT1; //0x098 + __IO uint32_t NDAT2; //0x09C + __IO uint32_t RXF0C; //0x0A0 + __IO uint32_t RXF0S; //0x0A4 + __IO uint32_t RXF0A; //0x0A8 + __IO uint32_t RXBC; //0x0AC + __IO uint32_t RXF1C; //0x0B0 + __IO uint32_t RXF1S; //0x0B4 + __IO uint32_t RXF1A; //0x0B8 + __IO uint32_t RXESC; //0x0BC + __IO uint32_t TXBC; //0x0C0 + __IO uint32_t TXFQS; //0x0C4 + __IO uint32_t TXESC; //0x0C8 + __IO uint32_t TXBRP; //0x0CC + __IO uint32_t TXBAR; //0x0D0 + __IO uint32_t TXBCR; //0x0D4 + __IO uint32_t TXBTO; //0x0D8 + __IO uint32_t TXBCF; //0x0DC + __IO uint32_t TXBTIE; //0x0E0 + __IO uint32_t TXBCIE; //0x0E4 + __IO uint32_t RESERVED6[2]; //0x0E8 + __IO uint32_t TXEFC; //0x0F0 + __IO uint32_t TXEFS; //0x0F4 + __IO uint32_t TXEFA; //0x0F8 + __IO uint32_t RESERVED7[1]; //0x0FC + __IO uint32_t TTTMC; //0x100 + __IO uint32_t TTRMC; //0x104 + __IO uint32_t TTOCF; //0x108 + __IO uint32_t TTMLM; //0x10c + __IO uint32_t TURCF; //0x110 + __IO uint32_t TTOCN; //0x114 + __IO uint32_t TTGTP; //0x118 + __IO uint32_t TTTMK; //0x11c + __IO uint32_t TTIR; //0x120 + __IO uint32_t TTIE; //0x124 + __IO uint32_t TTILS; //0x128 + __IO uint32_t TTOST; //0x12c + __IO uint32_t TURNA; //0x130 + __IO uint32_t TTLGT; //0x134 + __IO uint32_t TTCTC; //0x138 + __IO uint32_t TTCPT; //0x13C + __IO uint32_t TTCSM; //0x140 + __IO uint32_t TTSS; //0x144 +} FDCAN_Module; + +/*** FLASH Registers ***/ +typedef struct +{ + __IO uint32_t AC; //0x00 + __IO uint32_t CTRL; //0x04 + __IO uint32_t STS; //0x08 + __IO uint32_t ADD; //0x0C + __IO uint32_t KEY; //0x10 + __IO uint32_t OPTKEY; //0x14 + __IO uint32_t OB; //0x18 + __IO uint32_t WRP; //0x1C + __IO uint32_t ECC; //0x20 + __IO uint32_t RESERVED0[2]; + __IO uint32_t RDN; //0x2C + __IO uint32_t CAHR; //0x30 + __IO uint32_t ROWP; //0x34 + __IO uint32_t CCM_WRP1; //0x38 + __IO uint32_t CCM_KEY; //0x3C + __IO uint32_t CCM_ERASE; //0x40 + __IO uint32_t CCM_WRP2; //0x44 + __IO uint32_t CCM_MODE; //0x48 + __IO uint32_t XSPI_DSTRADD; //0x4C + __IO uint32_t XSPI_DENDADD; //0x50 + __IO uint32_t FEMC_DSTRADD; //0x54 + __IO uint32_t FEMC_DENDADD; //0x58 + __IO uint32_t RTPD_KEY; //0x5C + __IO uint32_t JTAG_SEAL; //0x60 + __IO uint32_t RTPD_KEY_WCNT;//0x64 + __IO uint32_t RESERVED1; + __IO uint32_t XSPI_FEMC_DEN;//0x6C + __IO uint32_t XUID; //0x70 +} FLASH_Module; + +/*** Option Bytes Registers ***/ + +typedef struct +{ + __IO uint32_t USER_RDP; //0x00 + __IO uint32_t Data1_Data0; //0x04 + __IO uint32_t WRP1_WRP0; //0x08 + __IO uint32_t WRP3_WRP2; //0x0C + __IO uint32_t USER2_RDP2; //0x10 + __IO uint32_t USER3; //0x14 + __IO uint32_t CCMSRAM_RST; //0x18 + __IO uint32_t RESERVED; +} OB_Module; + +/*** GPIO(General Purpose I/O) Registers ***/ +typedef struct +{ + __IO uint32_t PMODE; //0x00 + __IO uint32_t POTYPE; //0x04 + __IO uint32_t SR; //0x08 + __IO uint32_t PUPD; //0x0C + __IO uint32_t PID; //0x10 + __IO uint32_t POD; //0x14 + __IO uint32_t PBSC; //0x18 + __IO uint32_t PLOCK; //0x1C + __IO uint32_t AFL; //0x20 + __IO uint32_t AFH; //0x24 + __IO uint32_t PBC; //0x28 + __IO uint32_t DS; //0x2C +} GPIO_Module; + +/*** AFIO(Alternate Function I/O) Registers ***/ +typedef struct +{ + __IO uint32_t RMP_CFG; //0x00 + __IO uint32_t FILTER_CFG; //0x04 + __IO uint32_t XSPI1_NONCE0; //0x08 + __IO uint32_t XSPI1_NONCE1; //0x0C + __IO uint32_t XSPI1_NONCE2; //0x10 + __IO uint32_t ADCRMP_CFG; //0x14 + __IO uint32_t EXTI_CFG[4]; //0x18 + __IO uint32_t TOL5V_CFG1; //0x28 + __IO uint32_t TOL5V_CFG2; //0x2C + __IO uint32_t TOL5V_CFG3; //0x30 + __IO uint32_t SHRT1_FALT_CFG; //0x34 + __IO uint32_t SHRT2_FALT_CFG; //0x38 + __IO uint32_t TOL5V_CFG4; //0x3C + __IO uint32_t RESERVED40; //0x40 + __IO uint32_t TOL5V_CFG5; //0x44 + __IO uint32_t TOL5V_CFG6; //0x48 + __IO uint32_t TOL5V_CFG7; //0x4C + __IO uint32_t RESERVED50; //0x50 + __IO uint32_t EFT_CFG[6]; //0x54 + __IO uint32_t DIGEFT_CFG[6]; //0x6C + __IO uint32_t SHRT1_EXEV_CFG[2]; //0x84 + __IO uint32_t SHRT2_EXEV_CFG[2]; //0x8C + __IO uint32_t SIP_PUPD; //0x94 + __IO uint32_t HSMODE_CFG[5]; //0x98 + __IO uint32_t RESERVEDAC; //0xAC + __IO uint32_t SIPSR; //0xB0 + __IO uint32_t SIPDS; //0xB4 + __IO uint32_t RESERVEDB8[6]; //0xB8~0xCC + __IO uint32_t ADCSW_CFG; //0xD0 + __IO uint32_t RESERVEDD4; //0xD4 + __IO uint32_t SDRAM_VREF_EN[3]; //0xD8 + __IO uint32_t SDRAMDSN_CFG[3]; //0xE4 + __IO uint32_t SDRAMDSP_CFG[3]; //0xF0 +}AFIO_Module; + +/*** Low-Power Timer ***/ +typedef struct +{ + __IO uint32_t INTSTS; /* Offset: 0x0000 */ + __IO uint32_t INTCLR; /* Offset: 0x0004 */ + __IO uint32_t INTEN; /* Offset: 0x0008 */ + __IO uint32_t CFG; /* Offset: 0x000C */ + __IO uint32_t CTRL; /* Offset: 0x0010 */ + __IO uint32_t CMP; /* Offset: 0x0014 */ + __IO uint32_t ARR; /* Offset: 0x0018 */ + __IO uint32_t CNT; /* Offset: 0x001C */ + __IO uint32_t OPT; /* Offset: 0x0020 */ +} LPTIM_Module; + +/*** Inter Integrated Circuit Interface ***/ + +typedef struct +{ + __IO uint32_t CTRL1; //0x00 + __IO uint32_t CTRL2; //0x04 + __IO uint32_t ADR1; //0x08 + __IO uint32_t ADR2; //0x0C + __IO uint32_t BUSTIM; //0x10 + __IO uint32_t TMOUTR; //0x14 + __IO uint32_t STSINT; //0x18 + __IO uint32_t INTCLR; //0x1C + __IO uint32_t CRCR; //0x20 + __IO uint32_t RDR; //0x24 + __IO uint32_t WDR; //0x28 + __IO uint32_t HSBUSTM; //0x2C + __IO uint32_t FIFOCSR; //0x30 + __IO uint32_t QCMD; //0x34 + __IO uint32_t GFLTRCTRL; //0x38 +} I2C_Module; + + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KEY; + __IO uint32_t STS; + __IO uint32_t PREDIV; /* IWDG PREDIV */ + __IO uint32_t RELV; +} IWDG_Module; + +/** Power Control **/ +typedef struct +{ + __IO uint32_t M7CTRL1; //0x00 + __IO uint32_t M7CTRLSTS; //0x04 + __IO uint32_t M7CTRL2; //0x08 + __IO uint32_t RES1[5]; //0x0C + __IO uint32_t M4CTRL1; //0x20 + __IO uint32_t M4CTRLSTS; //0x24 + __IO uint32_t M4CTRL2; //0x28 + __IO uint32_t RES2[5]; //0x2C + __IO uint32_t SYSCTRL1; //0x40 + __IO uint32_t SYSCTRLSTS; //0x44 + __IO uint32_t SYSCTRL2; //0x48 + __IO uint32_t SYSCTRL3; //0x4C + __IO uint32_t SYSCTRL4; //0x50 + __IO uint32_t BORCTRL; //0x54 + __IO uint32_t IPMEMCTRL; //0x58 + __IO uint32_t IPMEMCTRLSTS; //0x5C + __IO uint32_t M7MEMLPCTRL; //0x60 + __IO uint32_t M7MEMLPSTS; //0x64 + __IO uint32_t M7TCMPG0; //0x68 + __IO uint32_t M7TCMPG1; //0x6C + __IO uint32_t M7TCMRET1N0; //0x70 + __IO uint32_t M7TCMRET1N1; //0x74 + __IO uint32_t M7TCMRET2N0; //0x78 + __IO uint32_t M7TCMRET2N1; //0x7C + __IO uint32_t M7TCMPRDY0; //0x80 + __IO uint32_t M7TCMPRDY1; //0x84 + __IO uint32_t RES3[2]; //0x88 + __IO uint32_t M4MEMLPCTRL; //0x90 + __IO uint32_t RES4[3]; //0x94 + __IO uint32_t SYSMEMLPCTRL; //0xA0 + __IO uint32_t RES5[3]; //0xA4 + __IO uint32_t SHRTIMCTRL; //0xB0 + __IO uint32_t MDMACTRL; //0xB4 + __IO uint32_t ESCCTRL; //0xB8 + __IO uint32_t RES6[17]; //0xBC + __IO uint32_t EMCRETCTRL1; //0x100 + __IO uint32_t EMCCTRLSTS1; //0x104 + __IO uint32_t EMCRETCTRL2; //0x108 + __IO uint32_t EMCRETSTS2; //0x10C + __IO uint32_t EMCRETCTRL3; //0x110 + __IO uint32_t EMCRETSTS3; //0x114 + __IO uint32_t EMCRETCTRL4; //0x118 + __IO uint32_t EMCRETSTS4; //0x11C + __IO uint32_t EMCBKPCTRL; //0x120 + __IO uint32_t EMCBKPSTS; //0x124 +}PWR_Module; + +/** Real-Time Clock **/ +typedef struct +{ + __IO uint32_t TSH; /* RTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /* RTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /* RTC control register, Address offset: 0x08 */ + __IO uint32_t INITSTS; /* RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRE; /* RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WKUPT; /* RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved18; /* Reserved */ + __IO uint32_t ALARMA; /* RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALARMB; /* RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WRP; /* RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SUBS; /* RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SCTRL; /* RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TST; /* RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSD; /* RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSS; /* RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALIB; /* RTC calibration register, Address offset: 0x3C */ + uint32_t reserved40; /* Reserved */ + __IO uint32_t ALRMASS; /* RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSS; /* RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OPT; /* RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP1; /* RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP2; /* RTC backup register 2, Address offset: 0x54 */ + __IO uint32_t BKP3; /* RTC backup register 3, Address offset: 0x58 */ + __IO uint32_t BKP4; /* RTC backup register 4, Address offset: 0x5C */ + __IO uint32_t BKP5; /* RTC backup register 5, Address offset: 0x60 */ + __IO uint32_t BKP6; /* RTC backup register 6, Address offset: 0x64 */ + __IO uint32_t BKP7; /* RTC backup register 7, Address offset: 0x68 */ + __IO uint32_t BKP8; /* RTC backup register 8, Address offset: 0x6C */ + __IO uint32_t BKP9; /* RTC backup register 9, Address offset: 0x70 */ + __IO uint32_t BKP10; /* RTC backup register 10, Address offset: 0x74 */ + __IO uint32_t BKP11; /* RTC backup register 11, Address offset: 0x78 */ + __IO uint32_t BKP12; /* RTC backup register 12, Address offset: 0x7C */ + __IO uint32_t BKP13; /* RTC backup register 13, Address offset: 0x80 */ + __IO uint32_t BKP14; /* RTC backup register 14, Address offset: 0x84 */ + __IO uint32_t BKP15; /* RTC backup register 15, Address offset: 0x88 */ + __IO uint32_t BKP16; /* RTC backup register 16, Address offset: 0x8C */ + __IO uint32_t BKP17; /* RTC backup register 17, Address offset: 0x90 */ + __IO uint32_t BKP18; /* RTC backup register 18, Address offset: 0x94 */ + __IO uint32_t BKP19; /* RTC backup register 19, Address offset: 0x98 */ + __IO uint32_t BKP20; /* RTC backup register 20, Address offset: 0x9C */ + __IO uint32_t BKP21; /* RTC backup register 21, Address offset: 0xA0 */ + __IO uint32_t BKP22; /* RTC backup register 22, Address offset: 0xA4 */ + __IO uint32_t BKP23; /* RTC backup register 23, Address offset: 0xA8 */ + __IO uint32_t BKP24; /* RTC backup register 24, Address offset: 0xAC */ + __IO uint32_t BKP25; /* RTC backup register 25, Address offset: 0xB0 */ + __IO uint32_t BKP26; /* RTC backup register 26, Address offset: 0xB4 */ + __IO uint32_t BKP27; /* RTC backup register 27, Address offset: 0xB8 */ + __IO uint32_t BKP28; /* RTC backup register 28, Address offset: 0xBC */ + __IO uint32_t BKP29; /* RTC backup register 29, Address offset: 0xC0 */ + __IO uint32_t BKP30; /* RTC backup register 30, Address offset: 0xC4 */ + __IO uint32_t BKP31; /* RTC backup register 31, Address offset: 0xC8 */ + __IO uint32_t BKP32; /* RTC backup register 31, Address offset: 0xCC */ + uint32_t reservedD0; /* Reserved */ + __IO uint32_t TMPCFG; /* RTC tamper configuration register, Address offset: 0xD4 */ + __IO uint32_t TMPCTRL[8]; /* RTC tamper configuration register, Address offset: 0xD8~0xF4 */ + +} RTC_Module; + +/** SDMMC Interface **/ + +typedef struct +{ + __IO uint32_t CFG1; //0x00 + __IO uint32_t CFG2; //0x04 + __IO uint32_t CFG3; //0x08 + __IO uint32_t PV0CTRL; //0x0C + __IO uint32_t PV1CTRL; //0x10 + __IO uint32_t PV2CTRL; //0x14 + __IO uint32_t PV3CTRL; //0x18 + uint32_t RESERVED; //0x1C + __IO uint32_t DLYCTRL; //0x20 +}SDMMC_Module; + +/** SD host Interface **/ +typedef struct +{ + __IO uint32_t DSADD; //0x00 + __IO uint32_t BLKCFG; //0x04 + __IO uint32_t CMDARG1; //0x08 + __IO uint32_t TMODE; //0x0C + __IO uint32_t CMDRSP0; //0x10 + __IO uint32_t CMDRSP1; //0x14 + __IO uint32_t CMDRSP2; //0x18 + __IO uint32_t CMDRSP3; //0x1C + __IO uint32_t BUFDAT; //0x20 + __IO uint32_t PRESTS; //0x24 + __IO uint32_t CTRL1; //0x28 + __IO uint32_t CTRL2; //0x2C + __IO uint32_t INTSTS; //0x30 + __IO uint32_t IE; //0x34 + __IO uint32_t ISE; //0x38 + __IO uint32_t CTRLSTS; //0x3C + __IO uint32_t CAP0STS; //0x40 + __IO uint32_t CAP1STS; //0x44 + uint32_t RESERVED0[2]; //0x48 + __IO uint32_t STSFE; //0x50 + __IO uint32_t ADMAESTS; //0x54 + __IO uint32_t ASADD0; //0x58 + __IO uint32_t ASADD1; //0x5C + __IO uint32_t PV0STS; //0x60 + __IO uint32_t PV1STS; //0x64 + __IO uint32_t PV2STS; //0x68 + __IO uint32_t PV3STS; //0x6C + __IO uint32_t BOOTTCTRL; //0x70 +}SDHOST_Module; + + +/*** TIM ***/ + +typedef struct +{ + __IO uint32_t CTRL1; //0x00 + __IO uint32_t CTRL2; //0x04 + __IO uint32_t STS; //0x08 + __IO uint32_t EVTGEN; //0x0C + __IO uint32_t SMCTRL; //0x10 + __IO uint32_t DINTEN; //0x14 + __IO uint32_t CCMOD1; //0x18 + __IO uint32_t CCMOD2; //0x1C + __IO uint32_t CCMOD3; //0x20 + __IO uint32_t CCEN; //0x24 + __IO uint32_t CCDAT1; //0x28 + __IO uint32_t CCDAT2; //0x2C + __IO uint32_t CCDAT3; //0x30 + __IO uint32_t CCDAT4; //0x34 + __IO uint32_t CCDAT5; //0x38 + __IO uint32_t CCDAT6; //0x3C + __IO uint32_t PSC; //0x40 + __IO uint32_t AR; //0x44 + __IO uint32_t CNT; //0x48 + __IO uint32_t REPCNT; //0x4C + __IO uint32_t BKDT; //0x50 + __IO uint32_t CCDAT7; //0x54 + __IO uint32_t CCDAT8; //0x58 + __IO uint32_t CCDAT9; //0x5C + __IO uint32_t BKFR; //0x60 + __IO uint32_t C1FILT; //0x64 + __IO uint32_t C2FILT; //0x68 + __IO uint32_t C3FILT; //0x6C + __IO uint32_t C4FILT; //0x70 + __IO uint32_t FILTO; //0x74 + __IO uint32_t INSEL; //0x78 + __IO uint32_t AF1; //0x7C + __IO uint32_t AF2; //0x80 + __IO uint32_t BKFR2; //0x84 + __IO uint32_t RESERVED0[3]; + __IO uint32_t DCTRL; //0x94 + __IO uint32_t DADDR; //0x98 +} TIM_Module; + + +/** Universal Synchronous Asynchronous Receiver Transmitter **/ + +typedef struct +{ + __IO uint32_t CTRL1; //0x00 + __IO uint32_t CTRL2; //0x04 + __IO uint32_t CTRL3; //0x08 + __IO uint32_t STS; //0x0C + __IO uint32_t DAT; //0x10 + __IO uint32_t BRCF; //0x14 + __IO uint32_t GTP; //0x18 + __IO uint32_t FIFO; //0x1C + __IO uint32_t IFW; //0x20 + __IO uint32_t RTO; //0x24 +} USART_Module; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CFG; /* WWDG Configuration Register Address offset: 0x00 */ + __IO uint32_t CTRL; /* WWDG Control Register Address offset: 0x04 */ + __IO uint32_t STS; /* WWDG Stauts Register Address offset: 0x08 */ +} WWDG_Module; + +/*** xSPI ***/ + +typedef struct +{ + __IO uint32_t CTRL0; /* xSPI Control Register 0, Address offset: 0x00 */ + __IO uint32_t CTRL1; /* xSPI Control Register 1, Address offset: 0x04 */ + __IO uint32_t SSIENR; /* xSPI Enable Register, Address offset: 0x08 */ + __IO uint32_t MW_CTRL; /* xSPI Microwire Control Register, Address offset: 0x0C */ + __IO uint32_t SLAVE_EN; /* xSPI Slave Enable Register, Address offset: 0x10 */ + __IO uint32_t BAUD; /* xSPI Baud Rate Select Register, Address offset: 0x14 */ + __IO uint32_t TXFT; /* xSPI Transmit FIFO Threshold Level, Address offset: 0x18 */ + __IO uint32_t RXFT; /* xSPI Receive FIFO Threshold Level, Address offset: 0x1C */ + __IO uint32_t TXFN; /* xSPI Transmit FIFO Level Register, Address offset: 0x20 */ + __IO uint32_t RXFN; /* xSPI Receive FIFO Level Register, Address offset: 0x24 */ + __IO uint32_t STS; /* xSPI Status Register, Address offset: 0x28 */ + __IO uint32_t IMASK; /* xSPI Interrupt Mask Register, Address offset: 0x2C */ + __IO uint32_t ISTS; /* xSPI Interrupt Status Register, Address offset: 0x30 */ + __IO uint32_t RISTS; /* xSPI Raw Interrupt Status Register, Address offset: 0x34 */ + __IO uint32_t TXEICR_CLR; /* xSPI Transmit FIFO Error Interrupt Clear Registers, Address offset: 0x38 */ + __IO uint32_t RXFOI_CLR; /* xSPI Receive FIFO Overflow Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t RXFUI_CLR; /* xSPI Receive FIFO Underflow Interrupt Clear Register, Address offset: 0x40 */ + __IO uint32_t MMCI_CLR; /* xSPI Multi-Master Interrupt Clear Register, Address offset: 0x44 */ + __IO uint32_t ICLR; /* xSPI Interrupt Clear Register, Address offset: 0x48 */ + __IO uint32_t DMA_CTRL; /* xSPI DMA Control Register, Address offset: 0x4C */ + __IO uint32_t DMATDL_CTRL; /* xSPI DMA Transmit Data Level, Address offset: 0x50 */ + __IO uint32_t DMARDL_CTRL; /* xSPI DMA Receive Data Level, Address offset: 0x54 */ + __IO uint32_t IDR; /* xSPI Identification Register, Address offset: 0x58 */ + __IO uint32_t VERSION_ID; /* xSPI component version, Address offset: 0x5C */ + __IO uint32_t DAT0; /* xSPI Data Register 0, Address offset: 0x60 */ + __IO uint32_t DAT1; /* xSPI Data Register 1, Address offset: 0x64 */ + __IO uint32_t DAT2; /* xSPI Data Register 2, Address offset: 0x68 */ + __IO uint32_t DAT3; /* xSPI Data Register 3, Address offset: 0x6C */ + __IO uint32_t DAT4; /* xSPI Data Register 4, Address offset: 0x70 */ + __IO uint32_t DAT5; /* xSPI Data Register 5, Address offset: 0x74 */ + __IO uint32_t DAT6; /* xSPI Data Register 6, Address offset: 0x78 */ + __IO uint32_t DAT7; /* xSPI Data Register 7, Address offset: 0x7C */ + __IO uint32_t DAT8; /* xSPI Data Register 8, Address offset: 0x80 */ + __IO uint32_t DAT9; /* xSPI Data Register 9, Address offset: 0x84 */ + __IO uint32_t DAT10; /* xSPI Data Register 10, Address offset: 0x88 */ + __IO uint32_t DAT11; /* xSPI Data Register 11, Address offset: 0x8C */ + __IO uint32_t DAT12; /* xSPI Data Register 12, Address offset: 0x90 */ + __IO uint32_t DAT13; /* xSPI Data Register 13, Address offset: 0x94 */ + __IO uint32_t DAT14; /* xSPI Data Register 14, Address offset: 0x98 */ + __IO uint32_t DAT15; /* xSPI Data Register 15, Address offset: 0x9C */ + __IO uint32_t DAT16; /* xSPI Data Register 16, Address offset: 0xA0 */ + __IO uint32_t DAT17; /* xSPI Data Register 17, Address offset: 0xA4 */ + __IO uint32_t DAT18; /* xSPI Data Register 18, Address offset: 0xA8 */ + __IO uint32_t DAT19; /* xSPI Data Register 19, Address offset: 0xAC */ + __IO uint32_t DAT20; /* xSPI Data Register 20, Address offset: 0xB0 */ + __IO uint32_t DAT21; /* xSPI Data Register 21, Address offset: 0xB4 */ + __IO uint32_t DAT22; /* xSPI Data Register 22, Address offset: 0xB8 */ + __IO uint32_t DAT23; /* xSPI Data Register 23, Address offset: 0xBC */ + __IO uint32_t DAT24; /* xSPI Data Register 24, Address offset: 0xC0 */ + __IO uint32_t DAT25; /* xSPI Data Register 25, Address offset: 0xC4 */ + __IO uint32_t DAT26; /* xSPI Data Register 26, Address offset: 0xC8 */ + __IO uint32_t DAT27; /* xSPI Data Register 27, Address offset: 0xCC */ + __IO uint32_t DAT28; /* xSPI Data Register 28, Address offset: 0xD0 */ + __IO uint32_t DAT29; /* xSPI Data Register 29, Address offset: 0xD4 */ + __IO uint32_t DAT30; /* xSPI Data Register 30, Address offset: 0xD8 */ + __IO uint32_t DAT31; /* xSPI Data Register 31, Address offset: 0xDC */ + __IO uint32_t DAT32; /* xSPI Data Register 32, Address offset: 0xE0 */ + __IO uint32_t DAT33; /* xSPI Data Register 33, Address offset: 0xE4 */ + __IO uint32_t DAT34; /* xSPI Data Register 34, Address offset: 0xE8 */ + __IO uint32_t DAT35; /* xSPI Data Register 35, Address offset: 0xEC */ + __IO uint32_t RX_DELAY; /* xSPI RX Sample Delay Register, Address offset: 0xF0 */ + __IO uint32_t ENH_CTRL0; /* xSPI Control Register, Address offset: 0xF4 */ + __IO uint32_t DDR_TXDE; /* xSPI Transmit Drive Edge Register, Address offset: 0xF8 */ + __IO uint32_t XIP_MODE; /* xSPI eXecute in Place - Mode bits, Address offset: 0xFC */ + __IO uint32_t XIP_INCR_TOC; /* xSPI XIP INCR transfer opcode, Address offset: 0x100 */ + __IO uint32_t XIP_WRAP_TOC; /* xSPI XIP WRAP transfer opcode, Address offset: 0x104 */ + __IO uint32_t XIP_CTRL; /* xSPI XIP Control Register, Address offset: 0x108 */ + __IO uint32_t XIP_SLAVE_EN; /* xSPI Slave Enable Register, Address offset: 0x10C */ + __IO uint32_t XIP_RXFOI_CLR; /* xSPI XIP Receive FIFO Overflow Interrupt Clear Register, Address offset: 0x110 */ + __IO uint32_t XIP_TOUT; /* xSPI XIP time out register for continuous transfers, Address offset: 0x114 */ + __IO uint32_t RESERVED0[10]; + __IO uint32_t XIP_WRITE_INCR_INST; /* xSPI XIP Write INCR transfer opcode, Address offset: 0x140 */ + __IO uint32_t XIP_WRITE_WRAP_INST; /* xSPI XIP Write WRAP transfer opcode, Address offset: 0x144 */ + __IO uint32_t XIP_WRITE_CTRL; /* xSPI XIP Write Control Register, Address offset: 0x148 */ + __IO uint32_t RESERVED1[13]; + __IO uint32_t XIP_WRITE_TIMING; /* xSPI XIP Write Timing Register, Address offset: 0x180 */ + __IO uint32_t RXDS_DELAY_CTRL; /* xSPI RXDS Delay line control, Address offset: 0x184 */ +} XSPI_Module; + + + +/*** DVP ***/ +typedef struct +{ + __IO uint32_t CTRL; /* DVP control register */ + __IO uint32_t INTEN; /* DVP interrupt enable register */ + __IO uint32_t INTSTS; /* DVP interrupt flag and status register */ + __IO uint32_t PORTCFG; /* DVP control port configuration register */ + __IO uint32_t FIFOCFG; /* DVP control fifo configuration register */ + __IO uint32_t SMADDR1; /* DVP frame 1 start memory address register */ + __IO uint32_t SMADDR2; /* DVP frame 2 start memory address register */ + __IO uint32_t FBS; /* DVP frame buffer size register */ + __IO uint32_t FPBC1; /* DVP frame 1 PIXEL byte count register */ + __IO uint32_t FPBC2; /* DVP frame 2 PIXEL byte count register */ + __IO uint32_t CSXY; /* DVP crop start XY register */ + __IO uint32_t CEXY; /* DVP crop end XY register */ + __IO uint32_t EMSC; /* DVP embedded sync code marker register */ + __IO uint32_t EMSCM; /* DVP embedded sync code mask register */ +} DVP_Module; + +/** FMAC **/ +typedef struct +{ + __IO uint32_t X1BUFCFG; //0x00 + __IO uint32_t X2BUFCFG; //0x04 + __IO uint32_t YBUFCFG; //0x08 + __IO uint32_t PARAMCFG; //0x0C + __IO uint32_t CTRL; //0x10 + __IO uint32_t STS; //0x14 + __IO uint32_t WDAT; //0x18 + __IO uint32_t RDAT; //0x1C +} FMAC_Module; + + +/** CORDIC **/ +typedef struct +{ + __IO uint32_t CTRLSTS; //0x00 + __IO uint32_t WDAT; //0x04 + __IO uint32_t RDAT; //0x08 +} CORDIC_Module; + +/** DSMU module registers **/ +typedef struct +{ + __IO uint32_t FLTCTRL1; //0x00 + __IO uint32_t FLTCTRL2; //0x04 + __IO uint32_t FLTSTS; //0x08 + __IO uint32_t FLTINTCLR; //0x0C + __IO uint32_t FLTJCHG; //0x10 + __IO uint32_t FLTFCTRL; //0x14 + __IO uint32_t FLTJDATA; //0x18 + __IO uint32_t FLTRDATA; //0x1C + __IO uint32_t FLTAWDHT; //0x20 + __IO uint32_t FLTAWDLT; //0x24 + __IO uint32_t FLTAWDSTS; //0x28 + __IO uint32_t FLTAWDCLR; //0x2C + __IO uint32_t FLTEXDETMAX; //0x30 + __IO uint32_t FLTEXDETMIN; //0x34 + __IO uint32_t FLTCOVTIM; //0x38 +} DSMU_Filter_Submodule; + +/** DSMU channel configuration registers **/ +typedef struct +{ + __IO uint32_t CHCFG1; //0x00 + __IO uint32_t CHCFG2; //0x04 + __IO uint32_t CHAWDSCDET; //0x08 + __IO uint32_t CHAWDDAT; //0x0C + __IO uint32_t CHDATIN; //0x10 +} DSMU_Channel_Submodule; + + +typedef struct +{ + __IO uint32_t MCTRL; /* SHRTIM configuration register for master timer, address offset: 0x00 */ + __IO uint32_t MINTSTS; /* SHRTIM status register for master timer interrupt, address offset: 0x04 */ + __IO uint32_t MINTCLR; /* SHRTIM master timer interrupt clear register, address offset: 0x08 */ + __IO uint32_t MIDEN; /* SHRTIM master timer interrupt and DMA request enable register, address offset: 0x0C */ + __IO uint32_t MCNT; /* SHRTIM master timer counter register, address offset: 0x10 */ + __IO uint32_t MPRD; /* SHRTIM master timer period register, address offset: 0x14 */ + __IO uint32_t MREPT; /* SHRTIM master timer repetition register, address offset: 0x18 */ + __IO uint32_t MCMP1DAT; /* SHRTIM master timer compare 1 register, address offset: 0x1C */ + uint32_t RESERVED0;/* Reserved, address offset: 0x20 */ + __IO uint32_t MCMP2DAT; /* SHRTIM master timer compare 2 register, address offset: 0x24 */ + __IO uint32_t MCMP3DAT; /* SHRTIM master timer compare 3 register, address offset: 0x28 */ + __IO uint32_t MCMP4DAT; /* SHRTIM master timer compare 4 register, address offset: 0x2C */ + __IO uint32_t SYNCOUT; /* SHRTIM SYNCOUT configure register, address offset: 0x30 */ + __IO uint32_t FRZDIS; /* SHRTIM Timer behavior during CPU freeze, address offset: 0x34 */ + uint32_t RESERVED1[18]; /* Reserved, 0x30..0x7C */ +}SHRTIM_Master_Submodule; + +/* SHRTIM Timer A to F registers definition */ +typedef struct +{ + __IO uint32_t TxCTRL; /* SHRTIM timer x control register, address offset: 0x00 */ + __IO uint32_t TxINTSTS; /* SHRTIM timer x interrupt status register, address offset: 0x04 */ + __IO uint32_t TxINTCLR; /* SHRTIM timer x interrupt clear register, address offset: 0x08 */ + __IO uint32_t TxIDEN; /* SHRTIM timer x interrupt DMA enable register, address offset: 0x0C */ + __IO uint32_t TxCNT; /* SHRTIM timer x counter register, address offset: 0x10 */ + __IO uint32_t TxPRD; /* SHRTIM timer x period register, address offset: 0x14 */ + __IO uint32_t TxREPT; /* SHRTIM timer x repetition register, address offset: 0x18 */ + __IO uint32_t TxCMP1DAT; /* SHRTIM timer x compare 1 register, address offset: 0x1C */ + __IO uint32_t TxRCMP1DAT; /* SHRTIM timer x compare 1 repetition alias register, address offset: 0x20 */ + __IO uint32_t TxCMP2DAT; /* SHRTIM timer x compare 2 register, address offset: 0x24 */ + __IO uint32_t TxCMP3DAT; /* SHRTIM timer x compare 3 register, address offset: 0x28 */ + __IO uint32_t TxCMP4DAT; /* SHRTIM timer x compare 4 register, address offset: 0x2C */ + __IO uint32_t TxCPT1; /* SHRTIM timer x compare 1 register, address offset: 0x30 */ + __IO uint32_t TxCPT2; /* SHRTIM timer x compare 2 register, address offset: 0x34 */ + __IO uint32_t TxDT; /* SHRTIM timer x deadtime register, address offset: 0x38 */ + __IO uint32_t TxSET1; /* SHRTIM timer x set register 1, address offset: 0x3C */ + __IO uint32_t TxRST1; /* SHRTIM timer x reset register 1, address offset: 0x40 */ + __IO uint32_t TxSET2; /* SHRTIM timer x set register 2, address offset: 0x44 */ + __IO uint32_t TxRST2; /* SHRTIM timer x reset register 2, address offset: 0x48 */ + __IO uint32_t TxEXEVFLT1; /* SHRTIM timer x external event filtering register 1, address offset: 0x4C */ + __IO uint32_t TxEXEVFLT2; /* SHRTIM timer x external event filtering register 1, address offset: 0x50 */ + __IO uint32_t TxCNTRST; /* SHRTIM timer x reset, address offset: 0x54 */ + __IO uint32_t TxCHOP; /* SHRTIM timer x chopper register, address offset: 0x58 */ + __IO uint32_t TxCPT1CTRL; /* SHRTIM timer x capture 1 control register, address offset: 0x5C */ + __IO uint32_t TxCPT2CTRL; /* SHRTIM timer x capture 2 control register, address offset: 0x60 */ + __IO uint32_t TxOUT; /* SHRTIM timer x output register, address offset: 0x64 */ + __IO uint32_t TxFALT; /* SHRTIM timer x fault register, address offset: 0x68 */ + __IO uint32_t TxCTRL2; /* SHRTIM timer x control register 2, address offset: 0x6C */ + __IO uint32_t TxEXEVFLT3; /* SHRTIM timer x external event filter register 3, address offset: 0x70 */ + __IO uint32_t TxCMP5DAT; /* SHRTIM timer x compare 5 register, address offset: 0x74 */ + uint32_t RESERVED0[2]; /* Reserved, address offset:0x78...0x7c */ +}SHRTIM_Timerx_Submodule; + + +/* SHRTIM common register definition */ +typedef struct +{ + __IO uint32_t CTRL1; /* SHRTIM control register 1, address offset: 0x00 */ + __IO uint32_t CTRL2; /* SHRTIM control register 2, address offset: 0x04 */ + __IO uint32_t INTSTS; /* SHRTIM interrupt status register, address offset: 0x08 */ + __IO uint32_t INTCLR; /* SHRTIM interrupt clear register, address offset: 0x0C */ + __IO uint32_t INTEN; /* SHRTIM interrupt enable register, address offset: 0x10 */ + __IO uint32_t OEN; /* SHRTIM output channel enable register, address offset: 0x14 */ + __IO uint32_t ODIS; /* SHRTIM output channel disable register, address offset: 0x18 */ + __IO uint32_t ODISSTS; /* SHRTIM output channel disable status register, address offset: 0x1C */ + __IO uint32_t BMCTRL; /* SHRTIM burst mode control register, address offset: 0x20 */ + __IO uint32_t BMTG; /* SHRTIM burst mode trigger register, address offset: 0x24 */ + __IO uint32_t BMCMP; /* SHRTIM burst mode compare register, address offset: 0x28 */ + __IO uint32_t BMPRD; /* SHRTIM burst mode period register, address offset: 0x2C */ + __IO uint32_t EXEVCTRL1; /* SHRTIM external event control register 1, address offset: 0x30 */ + __IO uint32_t EXEVCTRL2; /* SHRTIM external event control register 2, address offset: 0x34 */ + __IO uint32_t EXEVCTRL3; /* SHRTIM external event control register 4, address offset: 0x38 */ + __IO uint32_t EXEVCTRL4; /* SHRTIM external event control register 3, address offset: 0x3C */ + __IO uint32_t ADTG1SRC1; /* SHRTIM ADC trigger 1's source group1 register, address offset: 0x40 */ + __IO uint32_t ADTG1SRC2; /* SHRTIM ADC trigger 1's source group2 register, address offset: 0x44 */ + __IO uint32_t ADTG2SRC1; /* SHRTIM ADC trigger 2's source group1 register, address offset: 0x48 */ + __IO uint32_t ADTG2SRC2; /* SHRTIM ADC trigger 2's source group2 register, address offset: 0x4C */ + __IO uint32_t ADTG3SRC1; /* SHRTIM ADC trigger 3's source group1 register, address offset: 0x50 */ + __IO uint32_t ADTG3SRC2; /* SHRTIM ADC trigger 3's source group2 register, address offset: 0x54 */ + __IO uint32_t ADTG4SRC1; /* SHRTIM ADC trigger 4's source group1 register, address offset: 0x58 */ + __IO uint32_t ADTG4SRC2; /* SHRTIM ADC trigger 4's source group2 register, address offset: 0x5C */ + __IO uint32_t FALTIN1; /* SHRTIM fault input register 1, address offset: 0x60 */ + __IO uint32_t FALTIN2; /* SHRTIM fault input register 2, address offset: 0x64 */ + __IO uint32_t FALTIN3; /* SHRTIM fault input register 3, address offset: 0x68 */ + __IO uint32_t FALTIN4; /* SHRTIM fault input register 4, address offset: 0x6C */ + __IO uint32_t BDMTUPD; /* SHRTIM burst DMA master timer update register, address offset: 0x70 */ + __IO uint32_t BDTAUPD; /* SHRTIM burst DMA timer A update register, address offset: 0x74 */ + __IO uint32_t BDTBUPD; /* SHRTIM burst DMA timer B update register, address offset: 0x78 */ + __IO uint32_t BDTCUPD; /* SHRTIM burst DMA timer C update register, address offset: 0x7C */ + __IO uint32_t BDTDUPD; /* SHRTIM burst DMA timer D update register, address offset: 0x80 */ + __IO uint32_t BDTEUPD; /* SHRTIM burst DMA timer E update register, address offset: 0x84 */ + __IO uint32_t BDTFUPD; /* SHRTIM burst DMA timer F update register, address offset: 0x88 */ + __IO uint32_t BDDAT; /* SHRTIM burst DMA data register, address offset: 0x8C */ + __IO uint32_t ADTRGEX1; /* SHRTIM ADC extended trigger register 1, address offset: 0x90 */ + __IO uint32_t ADTRGEX2; /* SHRTIM ADC extended trigger register 2, address offset: 0x94 */ + __IO uint32_t ADTRGUPD; /* SHRTIM ADC trigger update register, address offset: 0x98 */ + __IO uint32_t ADCPSC1; /* SHRTIM ADC post scaler register 1, address offset: 0x9C */ + __IO uint32_t ADCPSC2; /* SHRTIM ADC post scaler register 2, address offset: 0xA0 */ + uint32_t RESERVED0; /* address offset: 0xA4 */ + __IO uint32_t SFTFALT; /* SHRTIM soft fault trigger register, address offset: 0xA8 */ + __IO uint32_t SFTDP; /* SHRTIM soft delayed protection trigger register, address offset: 0xAC */ + __IO uint32_t FALTIN5; /* SHRTIM fault input register 5, address offset: 0xB0 */ + __IO uint32_t EXEVCTRL5; /* SHRTIM external event control register 5, address offset: 0xB4 */ + __IO uint32_t EXTEND; /* SHRTIM extend register: 0xB8 */ +}SHRTIM_Common_Submodule; + +/* SHRTIM register definition */ +typedef struct { + SHRTIM_Master_Submodule sMasterRegs; + SHRTIM_Timerx_Submodule sTimerxRegs[6]; + SHRTIM_Common_Submodule sCommonRegs; +}SHRTIM_Module; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CTRL1; /* SPI Control Register 1, Address offset: 0x00 */ + uint16_t RESERVED0; + __IO uint16_t CTRL2; /* SPI Control Register 2, Address offset: 0x04 */ + uint16_t RESERVED1; + __IO uint16_t STS; /* SPI Status Register, Address offset: 0x08 */ + uint16_t RESERVED2; + __IO uint16_t DAT; /* SPI Data Register, Address offset: 0x0C */ + uint16_t RESERVED3; + __IO uint16_t CRCTDAT; /* SPI Transmit CRC Register, Address offset: 0x10 */ + uint16_t RESERVED4; + __IO uint16_t CRCRDAT; /* SPI Receive CRC Register, Address offset: 0x14 */ + uint16_t RESERVED5; + __IO uint16_t CRCPOLY; /* SPI CRC Polynomial Register, Address offset: 0x18 */ + uint16_t RESERVED6; + __IO uint16_t SPI_I2S_CFGR; /* SPI_I2S Configuration Register, Address offset: 0x1C */ + uint16_t RESERVED7; + __IO uint16_t I2SPREDIV; /* SPI_I2S Prescaler Register, Address offset: 0x20 */ + uint16_t RESERVED8; + __IO uint16_t RX_FIFO; /* SPI Receive FIFO, Address offset: 0x24 */ + uint16_t RESERVED9; + __IO uint16_t FIFONUM; /* SPI FIFO Configuration register, Address offset: 0x28 */ + uint16_t RESERVED10; + uint16_t RESERVED11; /* SPI FIFO Configuration register, Address offset: 0x2C */ + uint16_t RESERVED12; + __IO uint16_t FIFOCNT; /* SPI FIFO Count Register, Address offset: 0x30 */ + uint16_t RESERVED13; + __IO uint16_t TRANSNUM; /* SPI Transfer Number Configuration Register, Address offset: 0x34 */ + uint16_t RESERVED14; + __IO uint16_t CR3; /* SPI RX Sample Delay Register, Address offset: 0x38 */ +} SPI_Module; + +/** + * @brief I2S + */ +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t TXCRCR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t CRCPR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t RXFIFO; + uint16_t RESERVED9; + __IO uint16_t FIFONUM; + uint16_t RESERVED10; + uint32_t RESERVED11; + __IO uint16_t FIFOCNT; + uint16_t RESERVED12; + __IO uint32_t TRANSNUM; +} I2S_Module; + + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t I2S_CTRL2; /* I2S_EXT Control Register, Address offset: 0x04 */ + uint16_t RESERVED1; + __IO uint16_t I2S_STS; /* I2S_EXT Status Register, Address offset: 0x08 */ + uint16_t RESERVED2; + __IO uint16_t I2S_DAT; /* I2S_EXT Data Register, Address offset: 0x0C */ + uint16_t RESERVED3; + uint32_t RESERVED4; + uint32_t RESERVED5; + uint32_t RESERVED6; + __IO uint16_t I2S_CFGR; /* I2S_EXT Configuration Register Address offset: 0x1C */ + uint16_t RESERVED17; + +}I2S_EXT_Module; + + + + +typedef struct +{ + __IO uint32_t STS; //0x00 + __IO uint32_t INTEN; //0x04 + __IO uint32_t CTRL; //0x08 + __IO uint32_t BRCFG1; //0x0C + __IO uint32_t TXDAT; //0x10 + __IO uint32_t BRCFG2; //0x14 + __IO uint32_t WUDAT1; //0x18 + __IO uint32_t WUDAT2; //0x1C + __IO uint32_t RXDAT; //0x20 +}LPUART_Module; + +typedef struct +{ + __IO uint32_t CTRL1; //0x00 + __IO uint32_t CTRL2; //0x04 + __IO uint32_t EINJ; //0x08 + __IO uint32_t INTFS; //0x0C + __IO uint32_t INTF1; //0x10 + __IO uint32_t FEADR1; //0x14 + __IO uint32_t FEDATL1; //0x18 + __IO uint32_t FEDATH1; //0x1C + __IO uint32_t FECOD1; //0x20 + __IO uint32_t INTF2; //0x24 + __IO uint32_t FEADR2; //0x28 + __IO uint32_t FEDATL2; //0x2C + __IO uint32_t FEDATH2; //0x30 + __IO uint32_t FECOD2; //0x34 + __IO uint32_t INTF3; //0x38 + __IO uint32_t FEADR3; //0x3C + __IO uint32_t FEDATL3; //0x40 + __IO uint32_t FEDATH3; //0x44 + __IO uint32_t FECOD3; //0x48 + __IO uint32_t INTF4; //0x4C + __IO uint32_t FEADR4; //0x50 + __IO uint32_t FEDATL4; //0x54 + __IO uint32_t FEDATH4; //0x58 + __IO uint32_t FECOD4; //0x5C + __IO uint32_t INTF5; //0x60 + __IO uint32_t FEADR5; //0x64 + __IO uint32_t FEDATL5; //0x68 + __IO uint32_t FEDATH5; //0x6C + __IO uint32_t FECOD5; //0x70 + __IO uint32_t INTF6; //0x74 + __IO uint32_t FEADR6; //0x78 + __IO uint32_t FEDATL6; //0x7C + __IO uint32_t FEDATH6; //0x80 + __IO uint32_t FECOD6; //0x84 +}ECCMON_TypeDef; + +typedef struct +{ + __IO uint32_t CTRL; //0x00 + __IO uint32_t STS; //0x04 + __IO uint32_t KEY; //0x08 + __IO uint32_t USC; //0x0C + __IO uint32_t ADDR; //0x10 + __IO uint32_t RDATA; //0x14 + __IO uint32_t WDATA; //0x18 + __IO uint32_t RESERVED0; //0x1c + __IO uint32_t SECJVLD; //0x20 + __IO uint32_t RESERVED1; //0x24 + __IO uint32_t SECMDVLD; //0x28 + __IO uint32_t RESERVED2; //0x2c + __IO uint32_t RDP2PVLD; //0x30 + __IO uint32_t RESERVED3; //0x34 + __IO uint32_t BTMVLD; //0x38 + __IO uint32_t BORVLD; //0x3c + __IO uint32_t IWDGVLD; //0x40 + __IO uint32_t TCMSZVLD; //0x44 + __IO uint32_t RESERVED4[2]; //0x48 + __IO uint32_t JTAGKVLD; //0x50 + __IO uint32_t REKU1VLD; //0x54 + __IO uint32_t REKU2VLD; //0x58 + __IO uint32_t REKU3VLD; //0x5c + __IO uint32_t REKU4VLD; //0x60 + __IO uint32_t IDKU1VLD; //0x64 + __IO uint32_t IDKU2VLD; //0x68 + __IO uint32_t IDKU3VLD; //0x6c + __IO uint32_t IDKU4VLD; //0x70 + __IO uint32_t UMUU0; //0x74 + __IO uint32_t UMUU1; //0x78 + __IO uint32_t UMUU2; //0x7c + __IO uint32_t UMUU3; //0x80 + __IO uint32_t UMUU4; //0x84 + __IO uint32_t UMUU5; //0x88 + __IO uint32_t UMUU6; //0x8c + __IO uint32_t UMUU7; //0x90 + __IO uint32_t RESERVED5[9]; //0x94 + __IO uint32_t CRLD1; //0xb8 + __IO uint32_t CRLD2; //0xbc +}OTPC_Module; + +typedef struct +{ + __IO uint32_t CTRL; //0x00 + __IO uint32_t STS; //0x04 + __IO uint32_t RESERVED0[11];//0x08 + __IO uint32_t RTADC1; //0x34 + __IO uint32_t RTADC2; //0x38 + __IO uint32_t RTADC3; //0x3C + __IO uint32_t RTADC4; //0x40 + __IO uint32_t RTK1P0; //0x44 + __IO uint32_t RTK1P1; //0x48 + __IO uint32_t RTK1P2; //0x4C + __IO uint32_t RTK1P3; //0x50 + __IO uint32_t RTK2P0; //0x54 + __IO uint32_t RTK2P1; //0x58 + __IO uint32_t RTK2P2; //0x5c + __IO uint32_t RTK2P3; //0x60 + __IO uint32_t RTK3P0; //0x64 + __IO uint32_t RTK3P1; //0x68 + __IO uint32_t RTK3P2; //0x6c + __IO uint32_t RTK3P3; //0x70 + __IO uint32_t RTK4P0; //0x74 + __IO uint32_t RTK4P1; //0x78 + __IO uint32_t RTK4P2; //0x7c + __IO uint32_t RTK4P3; //0x80 + __IO uint32_t RTR1; //0x84 + __IO uint32_t RTR2; //0x88 + __IO uint32_t RTR3; //0x8c + __IO uint32_t RTR4; //0x90 + __IO uint32_t RESERVED1[9]; //0x94 + __IO uint32_t RTCRC; //0xb8 + __IO uint32_t RESERVED2[28];//0xbc + __IO uint32_t ETH1ME; //0x12c + __IO uint32_t ETH2ME; //0x130 + __IO uint32_t USB1ME; //0x134 + __IO uint32_t USB2ME; //0x138 + __IO uint32_t SD1ME; //0x13c + __IO uint32_t SD2ME; //0x140 + __IO uint32_t DVP1ME; //0x144 + __IO uint32_t DVP2ME; //0x148 + __IO uint32_t DMA1ME; //0x14c + __IO uint32_t DMA2ME; //0x150 + __IO uint32_t DMA3ME; //0x154 + __IO uint32_t MDMAME; //0x158 + __IO uint32_t JPEGME; //0x15c + __IO uint32_t LCDME; //0x160 + __IO uint32_t GPUME; //0x164 + __IO uint32_t SDPUME; //0x168 + __IO uint32_t RESERVED3; //0x16c + __IO uint32_t XRD; //0x170 + __IO uint32_t RESERVED4; //0x174 + __IO uint32_t XRAD; //0x178 + __IO uint32_t X1WD; //0x17c + __IO uint32_t X1RD; //0x180 + __IO uint32_t X1WAD; //0x184 + __IO uint32_t X1RAD; //0x188 + __IO uint32_t X2WD; //0x18c + __IO uint32_t X2RD; //0x190 + __IO uint32_t X2WAD; //0x194 + __IO uint32_t X2RAD; //0x198 + __IO uint32_t X3WD; //0x19c + __IO uint32_t X3RD; //0x1A0 + __IO uint32_t X3WAD; //0x1A4 + __IO uint32_t X3RAD; //0x1A8 + __IO uint32_t RESERVED5[25];//0x1AC + __IO uint32_t H1WD; //0x210 + __IO uint32_t H1RD; //0x214 + __IO uint32_t H1WAD; //0x218 + __IO uint32_t H1RAD; //0x21c + __IO uint32_t H2WD; //0x220 + __IO uint32_t H2RD; //0x224 + __IO uint32_t H2WAD; //0x228 + __IO uint32_t H2RAD; //0x22c + __IO uint32_t H3WD; //0x230 + __IO uint32_t H3RD; //0x234 + __IO uint32_t H3WAD; //0x238 + __IO uint32_t H3RAD; //0x23c + __IO uint32_t H4WD; //0x240 + __IO uint32_t H4RD; //0x244 + __IO uint32_t H4WAD; //0x248 + __IO uint32_t H4RAD; //0x24c + __IO uint32_t H5WD; //0x250 + __IO uint32_t H5RD; //0x254 + __IO uint32_t H5WAD; //0x258 + __IO uint32_t H5RAD; //0x25c + __IO uint32_t BKWD; //0x260 + __IO uint32_t BKRD; //0x264 + __IO uint32_t BKWAD; //0x268 + __IO uint32_t BKRAD; //0x26c + __IO uint32_t ITWD; //0x270 + __IO uint32_t ITRD; //0x274 + __IO uint32_t ITWAD; //0x278 + __IO uint32_t ITRAD; //0x27c +}MMU_Module; + +typedef struct +{ + uint32_t RESERVED0[32]; + __IO uint32_t BADD1; // 0x80 + __IO uint32_t ADDMASK1; // 0x84 + __IO uint32_t BADD2; // 0x88 + __IO uint32_t ADDMASK2; // 0x8C + uint32_t RESERVED1[4]; + __IO uint32_t CFG1; // 0xA0 + __IO uint32_t CFG2; // 0xA4 + uint32_t RESERVED2[2]; + __IO uint32_t RAT; // 0xB0 + __IO uint32_t RCT; // 0xB4 + __IO uint32_t RRDLY; // 0xB8 + __IO uint32_t PT; // 0xBC + __IO uint32_t WRT; // 0xC0 + __IO uint32_t RFCT; // 0xC4 + __IO uint32_t RCDLY; // 0xC8 + __IO uint32_t RI; // 0xCC + uint32_t RESERVED3[4]; + __IO uint32_t CBO; // 0xE0 + __IO uint32_t OR; // 0xE4 + __IO uint32_t OS; // 0xE8 + uint32_t RESERVED4[1]; + __IO uint32_t IINFO; // 0xF0 + uint32_t RESERVED5[3]; + __IO uint32_t WP; // 0x100 +} SDRAM_Module; + +/** +* @brief AFEC +*/ +typedef struct +{ + __IO uint32_t TRIMR0; + __IO uint32_t TRIMR1; + __IO uint32_t TRIMR2; + __IO uint32_t TRIMR3; + __IO uint32_t TRIMR4; + __IO uint32_t TRIMR5; + __IO uint32_t TRIMR6; + __IO uint32_t TRIMR7; + __IO uint32_t TRIMR8; + __IO uint32_t TRIMR9; + __IO uint32_t TRIMR10; + __IO uint32_t TRIMR11; + __IO uint32_t TRIMR12; + __IO uint32_t TESTR0; + __IO uint32_t TESTR1; + __IO uint32_t TESTR2; + __IO uint32_t TESTR3; + __IO uint32_t TESTR4; + __IO uint32_t TESTR5; + __IO uint32_t TESTR6; + __IO uint32_t TESTR7; + __IO uint32_t TESTR8; + __IO uint32_t TESTR9; + __IO uint32_t TESTR10; + __IO uint32_t TESTR11; + __IO uint32_t TESTR12; + __IO uint32_t TESTR13; + __IO uint32_t TESTR14; + __IO uint32_t TESTR15; + __IO uint32_t TESTR16; + __IO uint32_t TESTR17; + __IO uint32_t TESTR18; + __IO uint32_t TESTR19; + __IO uint32_t TESTR20; + __IO uint32_t TESTR21; + __IO uint32_t TESTR22; + __IO uint32_t TESTR23; + __IO uint32_t TESTR24; + __IO uint32_t TESTR25; + __IO uint32_t TESTR26; + __IO uint32_t TESTR27; + __IO uint32_t TESTR28; + __IO uint32_t TESTR29; + __IO uint32_t TESTR30; + __IO uint32_t TESTR31; + __IO uint32_t TESTR32; + __IO uint32_t TESTR33; + __IO uint32_t TESTR34; + __IO uint32_t TESTR35; + __IO uint32_t TESTR36; + __IO uint32_t TESTR37; + __IO uint32_t TESTR38; + __IO uint32_t TESTR39; + __IO uint32_t TESTR40; + __IO uint32_t TESTR41; + __IO uint32_t TESTR42; + __IO uint32_t TESTR43; + __IO uint32_t TESTR44; + __IO uint32_t TRIMR13; + __IO uint32_t TRIMR14; + __IO uint32_t TESTR45; +} AFEC_TypeDef; + +#define FLASH_BASE ((uint32_t)0x15000000UL) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x24000000UL) /*!< AXI SRAM base address in the alias region */ +#define DTCM_BASE ((uint32_t)0x20000000UL) /*!< DTCM base address in the alias region */ +#define ITCM_BASE ((uint32_t)0x00000000UL) /*!< ITCM base address in the alias region */ +#define AHBSRAM_BASE ((uint32_t)0x30000000UL) /*!< AHB SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000UL) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define UCID_BASE ((uint32_t)0x1FFFC238U) /* UCID Address : 0x1FFF_F238 */ +#define UCID_LENGTH ((uint32_t)0x10U) /* UCID Length : 16Bytes */ +// #define UID_BASE ((uint32_t)0x1FFFC760U) /* UID Address : 0x1FFF_C760 */ +// #define UID_LENGTH ((uint32_t)0x0CU) /* UID Length : 12Bytes */ +#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF248U) /* DBGMCU_ID Address: 0x1FFF_F248 */ +#define DBGMCU_ID_LENGTH ((uint32_t)0x04U) /* DBGMCU_ID Length : 4 Bytes */ + + /*!< Peripheral memory map */ +#define APB1PERIPH_BASE (PERIPH_BASE) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x40000) +#define AHB9PERIPH_BASE (PERIPH_BASE + 0xB0000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0xD0000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0xF0000) +#define APB6PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHB6PERIPH_BASE (PERIPH_BASE + 0x11000000) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x18030000) + + /* APB1 */ +#define BTIM4_BASE (APB1PERIPH_BASE + 0x10C00) +#define BTIM3_BASE (APB1PERIPH_BASE + 0x10800) +#define WWDG2_BASE (APB1PERIPH_BASE + 0x10000) +#define DAC12_BASE (APB1PERIPH_BASE + 0xFC00) +#define I2S4EXT_BASE (APB1PERIPH_BASE + 0xFA00) +#define I2S3EXT_BASE (APB1PERIPH_BASE + 0xF600) +#define I2S4_BASE (APB1PERIPH_BASE + 0xF800) +#define I2S3_BASE (APB1PERIPH_BASE + 0xF400) +#define I2C3_BASE (APB1PERIPH_BASE + 0xF000) +#define I2C2_BASE (APB1PERIPH_BASE + 0xEC00) +#define I2C1_BASE (APB1PERIPH_BASE + 0xE800) +#define SPI3_BASE (APB1PERIPH_BASE + 0xE400) +#define UART12_BASE (APB1PERIPH_BASE + 0xE000) +#define UART11_BASE (APB1PERIPH_BASE + 0xDC00) +#define UART10_BASE (APB1PERIPH_BASE + 0xD800) +#define UART9_BASE (APB1PERIPH_BASE + 0xD400) +#define USART4_BASE (APB1PERIPH_BASE + 0xD000) +#define USART3_BASE (APB1PERIPH_BASE + 0xCC00) +#define USART2_BASE (APB1PERIPH_BASE + 0xC800) +#define USART1_BASE (APB1PERIPH_BASE + 0xC400) +#define GTIMA7_BASE (APB1PERIPH_BASE + 0xC000) +#define GTIMA6_BASE (APB1PERIPH_BASE + 0xBC00) +#define GTIMA5_BASE (APB1PERIPH_BASE + 0xB800) +#define GTIMA4_BASE (APB1PERIPH_BASE + 0xB400) +#define GTIMB1_BASE (APB1PERIPH_BASE + 0xA800) +#define GTIMB2_BASE (APB1PERIPH_BASE + 0xAC00) +#define GTIMB3_BASE (APB1PERIPH_BASE + 0xB000) +#define BTIM2_BASE (APB1PERIPH_BASE + 0xA400) +#define BTIM1_BASE (APB1PERIPH_BASE + 0xA000) +#define AHBdCache_BASE (APB1PERIPH_BASE + 0x9000) +#define AHBiCache_BASE (APB1PERIPH_BASE + 0x8000) +#define FDCAN6_BASE (APB1PERIPH_BASE + 0xC00) +#define FDCAN5_BASE (APB1PERIPH_BASE + 0x800) +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x400) +#define FDCAN1_BASE (APB1PERIPH_BASE) + + + /* APB2 */ +#define UART15_BASE (APB2PERIPH_BASE + 0xF800) +#define UART14_BASE (APB2PERIPH_BASE + 0xF400) +#define UART13_BASE (APB2PERIPH_BASE + 0xF000) +#define USART8_BASE (APB2PERIPH_BASE + 0xEC00) +#define USART7_BASE (APB2PERIPH_BASE + 0xE800) +#define USART6_BASE (APB2PERIPH_BASE + 0xE400) +#define USART5_BASE (APB2PERIPH_BASE + 0xE000) +#define I2C6_BASE (APB2PERIPH_BASE + 0xDC00) +#define I2C5_BASE (APB2PERIPH_BASE + 0xD800) +#define I2C4_BASE (APB2PERIPH_BASE + 0xD400) +#define GTIMA3_BASE (APB2PERIPH_BASE + 0xD000) +#define GTIMA2_BASE (APB2PERIPH_BASE + 0xCC00) +#define GTIMA1_BASE (APB2PERIPH_BASE + 0xC800) +#define SPI2_BASE (APB2PERIPH_BASE + 0xC400) +#define SPI1_BASE (APB2PERIPH_BASE + 0xC000) +#define I2S2_BASE (APB2PERIPH_BASE + 0xBC00) +#define I2S1_BASE (APB2PERIPH_BASE + 0xB800) +#define I2S2EXT_BASE (APB2PERIPH_BASE + 0xBE00) +#define I2S1EXT_BASE (APB2PERIPH_BASE + 0xBA00) + +#define ATIM2_BASE (APB2PERIPH_BASE + 0xB400) +#define ATIM1_BASE (APB2PERIPH_BASE + 0xB000) +#define DSMU_BASE (APB2PERIPH_BASE + 0xA000) +#define DSMU_Channel0_BASE (DSMU_BASE + 0x00UL) +#define DSMU_Channel1_BASE (DSMU_BASE + 0x20UL) +#define DSMU_Channel2_BASE (DSMU_BASE + 0x40UL) +#define DSMU_Channel3_BASE (DSMU_BASE + 0x60UL) +#define DSMU_Channel4_BASE (DSMU_BASE + 0x80UL) +#define DSMU_Channel5_BASE (DSMU_BASE + 0xA0UL) +#define DSMU_Channel6_BASE (DSMU_BASE + 0xC0UL) +#define DSMU_Channel7_BASE (DSMU_BASE + 0xE0UL) +#define DSMU_Filter0_BASE (DSMU_BASE + 0x100UL) +#define DSMU_Filter1_BASE (DSMU_BASE + 0x180UL) +#define DSMU_Filter2_BASE (DSMU_BASE + 0x200UL) +#define DSMU_Filter3_BASE (DSMU_BASE + 0x280UL) + +#define SHRTIM2_BASE (APB2PERIPH_BASE + 0x9000) +#define SHRTIM1_BASE (APB2PERIPH_BASE + 0x8000) +#define FDCAN8_BASE (APB2PERIPH_BASE + 0x0C00) +#define FDCAN7_BASE (APB2PERIPH_BASE + 0x0800) +#define FDCAN4_BASE (APB2PERIPH_BASE + 0x0400) +#define FDCAN3_BASE (APB2PERIPH_BASE) + + /* APB5 */ +#define LPTIM5_BASE (APB5PERIPH_BASE + 0x5800) +#define RTC_BASE (APB5PERIPH_BASE + 0x5400) +#define IWDG2_BASE (APB5PERIPH_BASE + 0x5000) +#define IWDG1_BASE (APB5PERIPH_BASE + 0x4C00) +#define COMP_BASE (APB5PERIPH_BASE + 0x4800) +#define ATIM4_BASE (APB5PERIPH_BASE + 0x4400) +#define ATIM3_BASE (APB5PERIPH_BASE + 0x4000) +#define I2C10_BASE (APB5PERIPH_BASE + 0x3C00) +#define I2C9_BASE (APB5PERIPH_BASE + 0x3800) +#define I2C8_BASE (APB5PERIPH_BASE + 0x3400) +#define I2C7_BASE (APB5PERIPH_BASE + 0x3000) +#define SPI7_BASE (APB5PERIPH_BASE + 0x2C00) +#define SPI6_BASE (APB5PERIPH_BASE + 0x2800) +#define SPI5_BASE (APB5PERIPH_BASE + 0x2400) +#define SPI4_BASE (APB5PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB5PERIPH_BASE + 0x1C00) +#define LPTIM3_BASE (APB5PERIPH_BASE + 0x1800) +#define LPTIM2_BASE (APB5PERIPH_BASE + 0x1400) +#define LPTIM1_BASE (APB5PERIPH_BASE + 0x1000) +#define LPUART2_BASE (APB5PERIPH_BASE + 0x0C00) +#define LPUART1_BASE (APB5PERIPH_BASE + 0x0800) +#define AFEC_BASE (APB5PERIPH_BASE + 0x0400) +#define EXTI_BASE (APB5PERIPH_BASE) + + /* APB6 */ +#define JPEG_CTRL_BASE (APB6PERIPH_BASE + 0x90800) +#define JPEG_SGDMA_P2H_BASE (APB6PERIPH_BASE + 0x90400) +#define JPEG_BRC_BASE (APB6PERIPH_BASE + 0x90000) +#define JPEG_DEC_BASE (APB6PERIPH_BASE + 0x80000) +#define JPEG_SGDMA_H2P_BASE (APB6PERIPH_BASE + 0x70400) +#define JPEG_RBC_BASE (APB6PERIPH_BASE + 0x70000) +#define JPEG_ENC_BASE (APB6PERIPH_BASE + 0x60000) +#define FEMC_BASE (APB6PERIPH_BASE + 0x4C000) +#define TCMSRAMC_BASE (APB6PERIPH_BASE + 0x4B000) +#define DSI_HOST_WRAPPER_BASE (APB6PERIPH_BASE + 0x4AC00) +#define WWDG1_BASE (APB6PERIPH_BASE + 0x4A800) +#define LCDC_BASE (APB6PERIPH_BASE + 0x4A000) +#define LCDC_Layer1_BASE (LCDC_BASE + 0x100) +#define LCDC_Layer2_BASE (LCDC_BASE + 0x200) +#define LCDC_Layer3_BASE (LCDC_BASE + 0x300) +#define LCDC_Layer4_BASE (LCDC_BASE + 0x400) +#define DVP2_BASE (APB6PERIPH_BASE + 0x49000) +#define DVP1_BASE (APB6PERIPH_BASE + 0x48000) +#define GPU_BASE (APB6PERIPH_BASE + 0x40000) +#define DSI_HOST_BASE (APB6PERIPH_BASE) + + /* AHB1 */ +#define USB_CTRL2_WRAPPER_BASE (AHB1PERIPH_BASE + 0x60000) +#define USB_CTRL2_BASE (AHB1PERIPH_BASE + 0x20000) +#define SDHOST2_BASE (AHB1PERIPH_BASE + 0x10000) +#define SDMMC2_BASE (AHB1PERIPH_BASE + 0xA000) +#define DMA3_BASE (AHB1PERIPH_BASE + 0x7000) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6800) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x6400) +#define ECCMON_AHB_CACHE_BASE (AHB1PERIPH_BASE + 0x5000) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x4000) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x4400) +#define ADC3_BASE (AHB1PERIPH_BASE + 0x4800) +#define ETH2_BASE (AHB1PERIPH_BASE + 0x2000) + + /* AHB2 */ +#define USB_CTRL1_WRAPPER_BASE (AHB1PERIPH_BASE + 0x50000) +#define USB_CTRL1_BASE (AHB1PERIPH_BASE + 0x10000) +#define DCMUB_CM4_BASE (AHB2PERIPH_BASE + 0x8000) +#define DCMUA_CM7_BASE (AHB2PERIPH_BASE + 0x7000) +#define SEMA4_BASE (AHB2PERIPH_BASE + 0x6000) +#define ETH1_BASE (AHB2PERIPH_BASE + 0x4000) +#define SDPU_BASE (AHB2PERIPH_BASE + 0x2000) +#define DAC56_BASE (AHB2PERIPH_BASE + 0x1C00) +#define DAC34_BASE (AHB2PERIPH_BASE + 0x1800) +#define FMAC_BASE (AHB2PERIPH_BASE + 0x1400) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x1000) +#define ECCMON2_BASE (AHB2PERIPH_BASE ) + +/* AHB5 */ +#define ECCMON3_BASE (AHB5PERIPH_BASE + 0x6000) +#define DBGMCU_BASE (AHB5PERIPH_BASE + 0x5400) +#define GPIOK_BASE (AHB5PERIPH_BASE + 0x5000) +#define GPIOJ_BASE (AHB5PERIPH_BASE + 0x4C00) +#define GPIOI_BASE (AHB5PERIPH_BASE + 0x4800) +#define GPIOH_BASE (AHB5PERIPH_BASE + 0x4400) +#define GPIOG_BASE (AHB5PERIPH_BASE + 0x4000) +#define GPIOF_BASE (AHB5PERIPH_BASE + 0x3C00) +#define GPIOE_BASE (AHB5PERIPH_BASE + 0x3800) +#define GPIOD_BASE (AHB5PERIPH_BASE + 0x3400) +#define GPIOC_BASE (AHB5PERIPH_BASE + 0x3000) +#define GPIOB_BASE (AHB5PERIPH_BASE + 0x2C00) +#define GPIOA_BASE (AHB5PERIPH_BASE + 0x2800) +#define AFIO_BASE (AHB5PERIPH_BASE + 0x2400) +#define CRC_BASE (AHB5PERIPH_BASE + 0x2000) +#define PWR_BASE (AHB5PERIPH_BASE + 0x1000) +#define RCC_BASE (AHB5PERIPH_BASE) + +/* AHB6 */ +#define MDMA_WRAPPER_BASE (AHB6PERIPH_BASE + 0x120800) +#define DMAMUX2_MDMA_BASE (AHB6PERIPH_BASE + 0x120000) +#define OTPC_BASE (AHB6PERIPH_BASE + 0x118000) +#define SDHOST1_BASE (AHB6PERIPH_BASE + 0x110000) +#define SDMMC1_BASE (AHB6PERIPH_BASE + 0x107000) +#define SDRAM_BASE (AHB6PERIPH_BASE + 0x106000) +#define MMU_BASE (AHB6PERIPH_BASE + 0x105000) +#define ECCMON1P1_BASE (AHB6PERIPH_BASE + 0x104000) +#define ECCMON1P2_BASE (AHB6PERIPH_BASE + 0x104400) +#define ECCMON1P3_BASE (AHB6PERIPH_BASE + 0x104800) +#define ECCMON1P4_BASE (AHB6PERIPH_BASE + 0x104c00) +#define MDMA_BASE (AHB6PERIPH_BASE + 0x102000) +#define xSPI2_BASE (AHB6PERIPH_BASE + 0x101000) +#define xSPI1_BASE (AHB6PERIPH_BASE + 0x100000) +#define GPV_BASE (AHB6PERIPH_BASE) + +/*AHB9*/ +#define ETHERCAT_WRAPPER_BASE (AHB9PERIPH_BASE + 0x10000) +#define ETHERCAT_BASE (AHB9PERIPH_BASE) + + +#define DMA1_CH0_BASE ( DMA1_BASE +0*0x58) +#define DMA1_CH1_BASE ( DMA1_BASE +1*0x58) +#define DMA1_CH2_BASE ( DMA1_BASE +2*0x58) +#define DMA1_CH3_BASE ( DMA1_BASE +3*0x58) +#define DMA1_CH4_BASE ( DMA1_BASE +4*0x58) +#define DMA1_CH5_BASE ( DMA1_BASE +5*0x58) +#define DMA1_CH6_BASE ( DMA1_BASE +6*0x58) +#define DMA1_CH7_BASE ( DMA1_BASE +7*0x58) + +#define DMA2_CH0_BASE ( DMA2_BASE +0*0x58) +#define DMA2_CH1_BASE ( DMA2_BASE +1*0x58) +#define DMA2_CH2_BASE ( DMA2_BASE +2*0x58) +#define DMA2_CH3_BASE ( DMA2_BASE +3*0x58) +#define DMA2_CH4_BASE ( DMA2_BASE +4*0x58) +#define DMA2_CH5_BASE ( DMA2_BASE +5*0x58) +#define DMA2_CH6_BASE ( DMA2_BASE +6*0x58) +#define DMA2_CH7_BASE ( DMA2_BASE +7*0x58) + +#define DMA3_CH0_BASE ( DMA3_BASE +0*0x58) +#define DMA3_CH1_BASE ( DMA3_BASE +1*0x58) +#define DMA3_CH2_BASE ( DMA3_BASE +2*0x58) +#define DMA3_CH3_BASE ( DMA3_BASE +3*0x58) +#define DMA3_CH4_BASE ( DMA3_BASE +4*0x58) +#define DMA3_CH5_BASE ( DMA3_BASE +5*0x58) +#define DMA3_CH6_BASE ( DMA3_BASE +6*0x58) +#define DMA3_CH7_BASE ( DMA3_BASE +7*0x58) + +/** MDMA channel register base address: 0x0100 + 0x100 * n (n = 0 to 15) **/ +#define MDMA_CH0_BASE ( MDMA_BASE +1*0x100) +#define MDMA_CH1_BASE ( MDMA_BASE +2*0x100) +#define MDMA_CH2_BASE ( MDMA_BASE +3*0x100) +#define MDMA_CH3_BASE ( MDMA_BASE +4*0x100) +#define MDMA_CH4_BASE ( MDMA_BASE +5*0x100) +#define MDMA_CH5_BASE ( MDMA_BASE +6*0x100) +#define MDMA_CH6_BASE ( MDMA_BASE +7*0x100) +#define MDMA_CH7_BASE ( MDMA_BASE +8*0x100) +#define MDMA_CH8_BASE ( MDMA_BASE +9*0x100) +#define MDMA_CH9_BASE ( MDMA_BASE +10*0x100) +#define MDMA_CH10_BASE ( MDMA_BASE +11*0x100) +#define MDMA_CH11_BASE ( MDMA_BASE +12*0x100) +#define MDMA_CH12_BASE ( MDMA_BASE +13*0x100) +#define MDMA_CH13_BASE ( MDMA_BASE +14*0x100) +#define MDMA_CH14_BASE ( MDMA_BASE +15*0x100) +#define MDMA_CH15_BASE ( MDMA_BASE +16*0x100) + + +//somema TBD +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE + 0x0000UL) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_Channel16_BASE (DMAMUX1_BASE + 0x0040UL) +#define DMAMUX1_Channel17_BASE (DMAMUX1_BASE + 0x0044UL) +#define DMAMUX1_Channel18_BASE (DMAMUX1_BASE + 0x0048UL) +#define DMAMUX1_Channel19_BASE (DMAMUX1_BASE + 0x004CUL) +#define DMAMUX1_Channel20_BASE (DMAMUX1_BASE + 0x0050UL) +#define DMAMUX1_Channel21_BASE (DMAMUX1_BASE + 0x0044UL) +#define DMAMUX1_Channel22_BASE (DMAMUX1_BASE + 0x0058UL) +#define DMAMUX1_Channel23_BASE (DMAMUX1_BASE + 0x005CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) +#define DMAMUX1_RequestGenerator8_BASE (DMAMUX1_BASE + 0x0120UL) +#define DMAMUX1_RequestGenerator9_BASE (DMAMUX1_BASE + 0x0124UL) +#define DMAMUX1_RequestGenerator10_BASE (DMAMUX1_BASE + 0x0128UL) +#define DMAMUX1_RequestGenerator11_BASE (DMAMUX1_BASE + 0x012CUL) +#define DMAMUX1_RequestGenerator12_BASE (DMAMUX1_BASE + 0x0130UL) +#define DMAMUX1_RequestGenerator13_BASE (DMAMUX1_BASE + 0x0134UL) +#define DMAMUX1_RequestGenerator14_BASE (DMAMUX1_BASE + 0x0138UL) +#define DMAMUX1_RequestGenerator15_BASE (DMAMUX1_BASE + 0x013CUL) +#define DMAMUX1_RequestGenerator16_BASE (DMAMUX1_BASE + 0x0140UL) +#define DMAMUX1_RequestGenerator17_BASE (DMAMUX1_BASE + 0x0144UL) +#define DMAMUX1_RequestGenerator18_BASE (DMAMUX1_BASE + 0x0148UL) +#define DMAMUX1_RequestGenerator19_BASE (DMAMUX1_BASE + 0x014CUL) +#define DMAMUX1_RequestGenerator20_BASE (DMAMUX1_BASE + 0x0150UL) +#define DMAMUX1_RequestGenerator21_BASE (DMAMUX1_BASE + 0x0154UL) +#define DMAMUX1_RequestGenerator22_BASE (DMAMUX1_BASE + 0x0158UL) +#define DMAMUX1_RequestGenerator23_BASE (DMAMUX1_BASE + 0x015CUL) + +//somema TBD +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +//somema TBD +#define DMAMUX1_RGISR_BASE (DMAMUX1_BASE + 0x0180UL) +#define DMAMUX1_RGICF_BASE (DMAMUX1_BASE + 0x0184UL) + +#define DMAMUX_MDMA_RequestGenerator0_BASE (DMAMUX_MDMA_BASE + 0x0100UL) +#define DMAMUX_MDMA_RequestGenerator1_BASE (DMAMUX_MDMA_BASE + 0x0104UL) +#define DMAMUX_MDMA_RequestGenerator2_BASE (DMAMUX_MDMA_BASE + 0x0108UL) +#define DMAMUX_MDMA_RequestGenerator3_BASE (DMAMUX_MDMA_BASE + 0x010CUL) +#define DMAMUX_MDMA_RequestGenerator4_BASE (DMAMUX_MDMA_BASE + 0x0110UL) +#define DMAMUX_MDMA_RequestGenerator5_BASE (DMAMUX_MDMA_BASE + 0x0114UL) +#define DMAMUX_MDMA_RequestGenerator6_BASE (DMAMUX_MDMA_BASE + 0x0118UL) +#define DMAMUX_MDMA_RequestGenerator7_BASE (DMAMUX_MDMA_BASE + 0x011CUL) +//somema, TBD to confirm that MDMA only support 8 channel request generator +// #define DMAMUX_MDMA_RequestGenerator8_BASE (DMAMUX_MDMA_BASE + 0x0120UL) +// #define DMAMUX_MDMA_RequestGenerator9_BASE (DMAMUX_MDMA_BASE + 0x0124UL) +// #define DMAMUX_MDMA_RequestGenerator10_BASE (DMAMUX_MDMA_BASE + 0x0128UL) +// #define DMAMUX_MDMA_RequestGenerator11_BASE (DMAMUX_MDMA_BASE + 0x012CUL) +// #define DMAMUX_MDMA_RequestGenerator12_BASE (DMAMUX_MDMA_BASE + 0x0130UL) +// #define DMAMUX_MDMA_RequestGenerator13_BASE (DMAMUX_MDMA_BASE + 0x0134UL) +// #define DMAMUX_MDMA_RequestGenerator14_BASE (DMAMUX_MDMA_BASE + 0x0138UL) +// #define DMAMUX_MDMA_RequestGenerator15_BASE (DMAMUX_MDMA_BASE + 0x013CUL) +// #define DMAMUX_MDMA_RequestGenerator16_BASE (DMAMUX_MDMA_BASE + 0x0140UL) +// #define DMAMUX_MDMA_RequestGenerator17_BASE (DMAMUX_MDMA_BASE + 0x0144UL) +// #define DMAMUX_MDMA_RequestGenerator18_BASE (DMAMUX_MDMA_BASE + 0x0148UL) +// #define DMAMUX_MDMA_RequestGenerator19_BASE (DMAMUX_MDMA_BASE + 0x014CUL) +// #define DMAMUX_MDMA_RequestGenerator20_BASE (DMAMUX_MDMA_BASE + 0x0150UL) +// #define DMAMUX_MDMA_RequestGenerator21_BASE (DMAMUX_MDMA_BASE + 0x0154UL) +// #define DMAMUX_MDMA_RequestGenerator22_BASE (DMAMUX_MDMA_BASE + 0x0158UL) +// #define DMAMUX_MDMA_RequestGenerator23_BASE (DMAMUX_MDMA_BASE + 0x015CUL) + +#define DMAMUX_MDMA_RGISR_BASE (DMAMUX_MDMA_BASE + 0x0180UL) +#define DMAMUX_MDMA_RGICF_BASE (DMAMUX_MDMA_BASE + 0x0184UL) + +#if defined(CORE_CM7) +#define DCMU_BASE ((DCMU_Module *) (DCMUA_CM7_BASE)) +#else /* CORE_CM4 */ +#define DCMU_BASE ((DCMU_Module *) (DCMUB_CM4_BASE)) +#endif /* CORE_CM7 */ + + +//#define JPEG IPs here +//#define GPU here + + + + + + +#define BTIM4 ((TIM_Module *) BTIM4_BASE) +#define BTIM3 ((TIM_Module *) BTIM3_BASE) +#define MMU ((MMU_Module *) MMU_BASE) +#define WWDG2 ((WWDG_Module *) WWDG2_BASE) +#define DAC12 ((DAC_Module *) DAC12_BASE) +#define DAC34 ((DAC_Module *) DAC34_BASE) +#define DAC56 ((DAC_Module *) DAC56_BASE) +#define I2S4_EXT ((I2S_EXT_Module *) I2S4EXT_BASE) +#define I2S3_EXT ((I2S_EXT_Module *) I2S3EXT_BASE) +#define I2S4 ((I2S_Module *) I2S4_BASE) +#define I2S3 ((I2S_Module *) I2S3_BASE) +#define I2C3 ((I2C_Module *) I2C3_BASE) +#define I2C2 ((I2C_Module *) I2C2_BASE) +#define I2C1 ((I2C_Module *) I2C1_BASE) +#define SPI3 ((SPI_Module *) SPI3_BASE) +#define UART12 ((USART_Module *) UART12_BASE) +#define UART11 ((USART_Module *) UART11_BASE) +#define UART10 ((USART_Module *) UART10_BASE) +#define UART9 ((USART_Module *) UART9_BASE) +#define USART4 ((USART_Module *) USART4_BASE) +#define USART3 ((USART_Module *) USART3_BASE) +#define USART2 ((USART_Module *) USART2_BASE) +#define USART1 ((USART_Module *) USART1_BASE) +#define GTIMA7 ((TIM_Module *) GTIMA7_BASE) +#define GTIMA6 ((TIM_Module *) GTIMA6_BASE) +#define GTIMA5 ((TIM_Module *) GTIMA5_BASE) +#define GTIMA4 ((TIM_Module *) GTIMA4_BASE) +#define GTIMA3 ((TIM_Module *) GTIMA3_BASE) +#define GTIMA2 ((TIM_Module *) GTIMA2_BASE) +#define GTIMA1 ((TIM_Module *) GTIMA1_BASE) +#define BTIM2 ((TIM_Module *) BTIM2_BASE) +#define BTIM1 ((TIM_Module *) BTIM1_BASE) +#define FDCAN6 ((FDCAN_Module *) FDCAN6_BASE) +#define FDCAN5 ((FDCAN_Module *) FDCAN5_BASE) +#define FDCAN2 ((FDCAN_Module *) FDCAN2_BASE) +#define FDCAN1 ((FDCAN_Module *) FDCAN1_BASE) + +#define UART15 ((USART_Module *) UART15_BASE) +#define UART14 ((USART_Module *) UART14_BASE) +#define UART13 ((USART_Module *) UART13_BASE) +#define USART8 ((USART_Module *) USART8_BASE) +#define USART7 ((USART_Module *) USART7_BASE) +#define USART6 ((USART_Module *) USART6_BASE) +#define USART5 ((USART_Module *) USART5_BASE) +#define I2C6 ((I2C_Module *) I2C6_BASE) +#define I2C5 ((I2C_Module *) I2C5_BASE) +#define I2C4 ((I2C_Module *) I2C4_BASE) +#define GTIMB1 ((TIM_Module *) GTIMB1_BASE) +#define GTIMB2 ((TIM_Module *) GTIMB2_BASE) +#define GTIMB3 ((TIM_Module *) GTIMB3_BASE) +#define SPI2 ((SPI_Module *) SPI2_BASE) +#define SPI1 ((SPI_Module *) SPI1_BASE) +#define I2S2 ((I2S_Module *) I2S2_BASE) +#define I2S1 ((I2S_Module *) I2S1_BASE) +#define I2S2_EXT ((I2S_EXT_Module *) I2S2EXT_BASE) +#define I2S1_EXT ((I2S_EXT_Module *) I2S1EXT_BASE) +#define ATIM4 ((TIM_Module *) ATIM4_BASE) +#define ATIM3 ((TIM_Module *) ATIM3_BASE) +#define ATIM2 ((TIM_Module *) ATIM2_BASE) +#define ATIM1 ((TIM_Module *) ATIM1_BASE) +#define DSMU ((DSMU_TypeDef *) DSMU_BASE) +#define SHRTIM2 ((SHRTIM_Module *) SHRTIM2_BASE) +#define SHRTIM1 ((SHRTIM_Module *) SHRTIM1_BASE) +#define FDCAN8 ((FDCAN_Module *) FDCAN8_BASE) +#define FDCAN7 ((FDCAN_Module *) FDCAN7_BASE) +#define FDCAN4 ((FDCAN_Module *) FDCAN4_BASE) +#define FDCAN3 ((FDCAN_Module *) FDCAN3_BASE) + +#define RTC ((RTC_Module *) RTC_BASE) +#define IWDG2 ((IWDG_Module *) IWDG2_BASE) +#define IWDG1 ((IWDG_Module *) IWDG1_BASE) +#define COMP ((COMP_Module *) COMP_BASE) +#define ATIMER4 ((ATIMER_TypeDef *) ATIMER4_BASE) +#define ATIMER3 ((ATIMER_TypeDef *) ATIMER3_BASE) +#define I2C10 ((I2C_Module *) I2C10_BASE) +#define I2C9 ((I2C_Module *) I2C9_BASE) +#define I2C8 ((I2C_Module *) I2C8_BASE) +#define I2C7 ((I2C_Module *) I2C7_BASE) +#define SPI7 ((SPI_Module *) SPI7_BASE) +#define SPI6 ((SPI_Module *) SPI6_BASE) +#define SPI5 ((SPI_Module *) SPI5_BASE) +#define SPI4 ((SPI_Module *) SPI4_BASE) +#define LPTIM5 ((LPTIM_Module *) LPTIM5_BASE) +#define LPTIM4 ((LPTIM_Module *) LPTIM4_BASE) +#define LPTIM3 ((LPTIM_Module *) LPTIM3_BASE) +#define LPTIM2 ((LPTIM_Module *) LPTIM2_BASE) +#define LPTIM1 ((LPTIM_Module *) LPTIM1_BASE) +#define LPUART2 ((LPUART_Module *) LPUART2_BASE) +#define LPUART1 ((LPUART_Module *) LPUART1_BASE) +#define AFEC ((AFEC_TypeDef *) AFEC_BASE) +#define EXTI ((EXTI_Module *) EXTI_BASE) + +#define JPEG_CTRL ((JPEG_CTRL_Module *) JPEG_CTRL_BASE) +#define JPEG_SGDMA_P2H ((JPEG_SGDMA_Module *) JPEG_SGDMA_P2H_BASE) +#define JPEG_BRC ((JPEG_BRC_Module *) JPEG_BRC_BASE) +#define JPEG_DEC ((JPEG_DEC_Module *) JPEG_DEC_BASE) +#define JPEG_SGDMA_H2P ((JPEG_SGDMA_Module *) JPEG_SGDMA_H2P_BASE) +#define JPEG_RBC ((JPEG_RBC_Module *) JPEG_RBC_BASE) +#define JPEG_ENC ((JPEG_ENC_Module *) JPEG_ENC_BASE) +#define FEMC ((FEMC_Module *) FEMC_BASE) +#define TCMSRAMC ((TCMSRAMC_TypeDef *) TCMSRAMC_BASE) +#define WWDG1 ((WWDG_Module *) WWDG1_BASE) +#define LCDC ((LCDC_Module *) LCDC_BASE) +#define LCDC_Layer1 ((LCDC_Layer_Module *)LCDC_Layer1_BASE) +#define LCDC_Layer2 ((LCDC_Layer_Module *)LCDC_Layer2_BASE) +#define LCDC_Layer3 ((LCDC_Layer_Module *)LCDC_Layer3_BASE) +#define LCDC_Layer4 ((LCDC_Layer_Module *)LCDC_Layer4_BASE) +#define DVP2 ((DVP_Module *) DVP2_BASE) +#define DVP1 ((DVP_Module *) DVP1_BASE) +#define OTPC ((OTPC_Module *) OTPC_BASE) +#define GPU ((GPU_TypeDef *) GPU_BASE) +#define DSI_HOST ((DSI_Module *) DSI_HOST_BASE) +#define DSI_HOST_WRAPPER ((DSI_Wrapper_Module *)DSI_HOST_WRAPPER_BASE) + +#define SDMMC2 ((SDMMC_Module *) SDMMC2_BASE) +#define SDHOST2 ((SDHOST_Module *) SDHOST2_BASE) +#define USB2OTG_HS ((USBOTG_HS_TypeDef *) USB2OTG_HS_BASE) +#define USB1OTG_HS ((USBOTG_HS_TypeDef *) USBOTG_HS_BASE) +#define DMA3 ((DMA_Module *) DMA3_BASE) +#define DMA3_CH0 ((DMA_ChannelType *) DMA3_CH0_BASE) +#define DMA3_CH1 ((DMA_ChannelType *) DMA3_CH1_BASE) +#define DMA3_CH2 ((DMA_ChannelType *) DMA3_CH2_BASE) +#define DMA3_CH3 ((DMA_ChannelType *) DMA3_CH3_BASE) +#define DMA3_CH4 ((DMA_ChannelType *) DMA3_CH4_BASE) +#define DMA3_CH5 ((DMA_ChannelType *) DMA3_CH5_BASE) +#define DMA3_CH6 ((DMA_ChannelType *) DMA3_CH6_BASE) +#define DMA3_CH7 ((DMA_ChannelType *) DMA3_CH7_BASE) + +#define DMA2 ((DMA_Module *) DMA2_BASE) +#define DMA2_CH0 ((DMA_ChannelType *) DMA2_CH0_BASE) +#define DMA2_CH1 ((DMA_ChannelType *) DMA2_CH1_BASE) +#define DMA2_CH2 ((DMA_ChannelType *) DMA2_CH2_BASE) +#define DMA2_CH3 ((DMA_ChannelType *) DMA2_CH3_BASE) +#define DMA2_CH4 ((DMA_ChannelType *) DMA2_CH4_BASE) +#define DMA2_CH5 ((DMA_ChannelType *) DMA2_CH5_BASE) +#define DMA2_CH6 ((DMA_ChannelType *) DMA2_CH6_BASE) +#define DMA2_CH7 ((DMA_ChannelType *) DMA2_CH7_BASE) +#define DMA1 ((DMA_Module *) DMA1_BASE) + +#define DMA1_CH0 ((DMA_ChannelType *) DMA1_CH0_BASE) +#define DMA1_CH1 ((DMA_ChannelType *) DMA1_CH1_BASE) +#define DMA1_CH2 ((DMA_ChannelType *) DMA1_CH2_BASE) +#define DMA1_CH3 ((DMA_ChannelType *) DMA1_CH3_BASE) +#define DMA1_CH4 ((DMA_ChannelType *) DMA1_CH4_BASE) +#define DMA1_CH5 ((DMA_ChannelType *) DMA1_CH5_BASE) +#define DMA1_CH6 ((DMA_ChannelType *) DMA1_CH6_BASE) +#define DMA1_CH7 ((DMA_ChannelType *) DMA1_CH7_BASE) +#define DMAMUX1 ((DMAMUX1_Module *) DMAMUX1_BASE) +#define ADC1 ((ADC_Module *) ADC1_BASE) +#define ADC2 ((ADC_Module *) ADC2_BASE) +#define ADC3 ((ADC_Module *) ADC3_BASE) +#define ETH1 ((ETH_Module *) ETH1_BASE) +#define ETH2 ((ETH_Module *) ETH2_BASE) + + +//#define DCMUB_CM4 ((DCMUB_CM4_TypeDef *) DCMUB_CM4_BASE) +//#define DCMUA_CM7 ((DCMUA_CM7_TypeDef *) DCMUA_CM7_BASE) +#define DCMU ((DCMU_Module *) DCMU_BASE) + +#define SEMA4 ((SEMA4_Module *) SEMA4_BASE) +#define CUSTOM ((CUSTOM_TypeDef *) CUSTOM_BASE) +#define SDPU ((SDPU_TypeDef *) SDPU_BASE) +#define FMAC ((FMAC_Module *) FMAC_BASE) +#define CORDIC ((CORDIC_Module *) CORDIC_BASE) +#define ECCMON2 ((ECCMON_TypeDef *) ECCMON2_BASE) + +#define ECCMON3 ((ECCMON_TypeDef *) ECCMON3_BASE) +#define GPIOK ((GPIO_Module *) GPIOK_BASE) +#define GPIOJ ((GPIO_Module *) GPIOJ_BASE) +#define GPIOI ((GPIO_Module *) GPIOI_BASE) +#define GPIOH ((GPIO_Module *) GPIOH_BASE) +#define GPIOG ((GPIO_Module *) GPIOG_BASE) +#define GPIOF ((GPIO_Module *) GPIOF_BASE) +#define GPIOE ((GPIO_Module *) GPIOE_BASE) +#define GPIOD ((GPIO_Module *) GPIOD_BASE) +#define GPIOC ((GPIO_Module *) GPIOC_BASE) +#define GPIOB ((GPIO_Module *) GPIOB_BASE) +#define GPIOA ((GPIO_Module *) GPIOA_BASE) +#define AFIO ((AFIO_Module *) AFIO_BASE) +#define CRC ((CRC_Module *) CRC_BASE) +#define PWR ((PWR_Module *) PWR_BASE) +#define RCC ((RCC_Module *) RCC_BASE) + +#define SDRAM ((SDRAM_Module*)SDRAM_BASE) +#define DMAMUX_MDMA ((DMAMUX2_Module *) DMAMUX_MDMA_BASE) +#define SDMMC1 ((SDMMC_Module *) SDMMC1_BASE) +#define SDHOST1 ((SDHOST_Module *) SDHOST1_BASE) +#define ECCMON1P1 ((ECCMON_TypeDef *) ECCMON1P1_BASE) +#define ECCMON1P2 ((ECCMON_TypeDef *) ECCMON1P2_BASE) +#define ECCMON1P3 ((ECCMON_TypeDef *) ECCMON1P3_BASE) +#define ECCMON1P4 ((ECCMON_TypeDef *) ECCMON1P4_BASE) +#define MDMA ((MDMA_Module *) MDMA_BASE) +#define xSPI2 ((XSPI_Module *) xSPI2_BASE) +#define xSPI1 ((XSPI_Module *) xSPI1_BASE) +#define GPV ((GPV_TypeDef *) GPV_BASE ) + +#define DBG ((DBG_Module *) DBGMCU_BASE) + +#define DSMU_Channel0 ((DSMU_Channel_Submodule *) DSMU_Channel0_BASE) +#define DSMU_Channel1 ((DSMU_Channel_Submodule *) DSMU_Channel1_BASE) +#define DSMU_Channel2 ((DSMU_Channel_Submodule *) DSMU_Channel2_BASE) +#define DSMU_Channel3 ((DSMU_Channel_Submodule *) DSMU_Channel3_BASE) +#define DSMU_Channel4 ((DSMU_Channel_Submodule *) DSMU_Channel4_BASE) +#define DSMU_Channel5 ((DSMU_Channel_Submodule *) DSMU_Channel5_BASE) +#define DSMU_Channel6 ((DSMU_Channel_Submodule *) DSMU_Channel6_BASE) +#define DSMU_Channel7 ((DSMU_Channel_Submodule *) DSMU_Channel7_BASE) +#define DSMU_Filter0 ((DSMU_Filter_Submodule *) DSMU_Filter0_BASE) +#define DSMU_Filter1 ((DSMU_Filter_Submodule *) DSMU_Filter1_BASE) +#define DSMU_Filter2 ((DSMU_Filter_Submodule *) DSMU_Filter2_BASE) +#define DSMU_Filter3 ((DSMU_Filter_Submodule *) DSMU_Filter3_BASE) + +/*** SystemTick ***/ + +/** Bit definition for SysTick_CTRL register **/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001U) /* Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002U) /* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004U) /* Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000U) /* Count Flag */ + +/** Bit definition for SysTick_LOAD register **/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFFU) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ +/** Bit definition for SysTick_VAL register **/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFFU) /* Current value at the time the register is accessed */ + +/** Bit definition for SysTick_CALIB register **/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFFU) /* Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000U) /* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000U) /* The reference clock is not provided */ + +/*** Nested Vectored Interrupt Controller ***/ + +/** Bit definition for NVIC_ISER register **/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFFU) /* Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001U) /* bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002U) /* bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004U) /* bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008U) /* bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010U) /* bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020U) /* bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040U) /* bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080U) /* bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100U) /* bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200U) /* bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400U) /* bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800U) /* bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000U) /* bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000U) /* bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000U) /* bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000U) /* bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000U) /* bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000U) /* bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000U) /* bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000U) /* bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000U) /* bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000U) /* bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000U) /* bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000U) /* bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000U) /* bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000U) /* bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000U) /* bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000U) /* bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000U) /* bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000U) /* bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000U) /* bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000U) /* bit 31 */ + +/** Bit definition for NVIC_ICER register ***/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFFU) /* Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001U) /* bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002U) /* bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004U) /* bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008U) /* bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010U) /* bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020U) /* bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040U) /* bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080U) /* bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100U) /* bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200U) /* bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400U) /* bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800U) /* bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000U) /* bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000U) /* bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000U) /* bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000U) /* bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000U) /* bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000U) /* bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000U) /* bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000U) /* bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000U) /* bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000U) /* bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000U) /* bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000U) /* bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000U) /* bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000U) /* bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000U) /* bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000U) /* bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000U) /* bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000U) /* bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000U) /* bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000U) /* bit 31 */ + +/** Bit definition for NVIC_ISPR register **/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFFU) /* Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001U) /* bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002U) /* bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004U) /* bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008U) /* bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010U) /* bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020U) /* bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040U) /* bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080U) /* bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100U) /* bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200U) /* bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400U) /* bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800U) /* bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000U) /* bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000U) /* bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000U) /* bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000U) /* bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000U) /* bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000U) /* bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000U) /* bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000U) /* bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000U) /* bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000U) /* bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000U) /* bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000U) /* bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000U) /* bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000U) /* bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000U) /* bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000U) /* bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000U) /* bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000U) /* bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000U) /* bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000U) /* bit 31 */ + +/** Bit definition for NVIC_ICPR register **/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFFU) /* Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001U) /* bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002U) /* bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004U) /* bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008U) /* bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010U) /* bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020U) /* bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040U) /* bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080U) /* bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100U) /* bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200U) /* bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400U) /* bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800U) /* bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000U) /* bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000U) /* bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000U) /* bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000U) /* bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000U) /* bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000U) /* bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000U) /* bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000U) /* bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000U) /* bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000U) /* bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000U) /* bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000U) /* bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000U) /* bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000U) /* bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000U) /* bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000U) /* bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000U) /* bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000U) /* bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000U) /* bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000U) /* bit 31 */ + +/** Bit definition for NVIC_IABR register **/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFFU) /* Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001U) /* bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002U) /* bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004U) /* bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008U) /* bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010U) /* bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020U) /* bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040U) /* bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080U) /* bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100U) /* bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200U) /* bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400U) /* bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800U) /* bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000U) /* bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000U) /* bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000U) /* bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000U) /* bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000U) /* bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000U) /* bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000U) /* bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000U) /* bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000U) /* bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000U) /* bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000U) /* bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000U) /* bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000U) /* bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000U) /* bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000U) /* bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000U) /* bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000U) /* bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000U) /* bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000U) /* bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000U) /* bit 31 */ + +/** Bit definition for NVIC_PRI0 register **/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FFU) /* Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00U) /* Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000U) /* Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000U) /* Priority of interrupt 3 */ + +/** Bit definition for NVIC_PRI1 register **/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FFU) /* Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00U) /* Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000U) /* Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000U) /* Priority of interrupt 7 */ + +/** Bit definition for NVIC_PRI2 register **/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FFU) /* Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00U) /* Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000U) /* Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000U) /* Priority of interrupt 11 */ + +/** Bit definition for NVIC_PRI3 register **/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FFU) /* Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00U) /* Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000U) /* Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000U) /* Priority of interrupt 15 */ + +/** Bit definition for NVIC_PRI4 register **/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FFU) /* Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00U) /* Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000U) /* Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000U) /* Priority of interrupt 19 */ + +/** Bit definition for NVIC_PRI5 register **/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FFU) /* Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00U) /* Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000U) /* Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000U) /* Priority of interrupt 23 */ + +/** Bit definition for NVIC_PRI6 register **/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FFU) /* Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00U) /* Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000U) /* Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000U) /* Priority of interrupt 27 */ + +/** Bit definition for NVIC_PRI7 register **/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FFU) /* Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00U) /* Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000U) /* Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000U) /* Priority of interrupt 31 */ + +/** Bit definition for SCB_CPUID register **/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000FU) /* Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0U) /* Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000U) /* Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000U) /* Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000U) /* Implementer code. ARM is 0x41 */ + +/** Bit definition for SCB_ICSR register **/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FFU) /* Active INTSTS number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800U) /* All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000U) /* Pending INTSTS number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000U) /* Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000U) /* It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000U) /* Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000U) /* Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000U) /* Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000U) /* Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000U) /* Set pending NMI bit */ + +/** Bit definition for SCB_VTOR register **/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80U) /* Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000U) /* Table base in code(0) or RAM(1) */ + +/** Bit definition for SCB_AIRCR register **/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001U) /* System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002U) /* Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004U) /* Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700U) /* PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400U) /* Bit 2 */ + +/** prority group configuration **/ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000U) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100U) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200U) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300U) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400U) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500U) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600U) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700U) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000U) /* Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000U) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/** Bit definition for SCB_SCR register **/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /* Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /* Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /* Wake up from WFE */ + +/** Bit definition for SCB_CCR register **/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001U) /* Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002U) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a \ + Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008U) /* Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010U) /* Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100U) /* Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200U) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/** Bit definition for SCB_SHPR register **/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FFU) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00U) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000U) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000U) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/** Bit definition for SCB_SHCSR register **/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001U) /* MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002U) /* BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008U) /* UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080U) /* SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100U) /* Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400U) /* PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800U) /* SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000U) /* Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000U) /* MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000U) /* Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000U) /* SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000U) /* MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000U) /* Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000U) /* UsageFault enable */ + +/*** Bit definition for SCB_CFSR register ***/ +/** MFSR **/ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001U) /* Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002U) /* Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008U) /* Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010U) /* Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080U) /* Memory Manage Address Register address valid flag */ +/** BFSR **/ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100U) /* Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200U) /* Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400U) /* Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800U) /* Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000U) /* Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000U) /* Bus Fault Address Register address valid flag */ +/** UFSR **/ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000U) /* The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000U) /* Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000U) /* Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000U) /* Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000U) /* Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000U) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/** Bit definition for SCB_HFSR register **/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002U) /* Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000U) /* Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000U) /* Fault related to debug */ + +/** Bit definition for SCB_DFSR register **/ +#define SCB_DFSR_HALTED ((uint8_t)0x01U) /* Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02U) /* BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04U) /* Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08U) /* Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10U) /* External debug request flag */ + +/** Bit definition for SCB_MMFAR register **/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFFU) /* Mem Manage fault address field */ + +/** Bit definition for SCB_BFAR register **/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFFU) /* Bus fault address field */ + +/** Bit definition for SCB_afsr register **/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFFU) /* Implementation defined */ + /******************************************************************************/ + /* */ + /* External Interrupt/Event Controller */ + /* */ + /******************************************************************************/ +/******** Bit definition for EXTI_RT_CFG0 register ********/ +#define EXTI_RT_CFG0_RT_CFG0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_RT_CFG0_RT_CFG0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_RT_CFG0_RT_CFG0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_RT_CFG0_RT_CFG0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_RT_CFG0_RT_CFG0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_RT_CFG0_RT_CFG0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_RT_CFG0_RT_CFG0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_RT_CFG0_RT_CFG0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_RT_CFG0_RT_CFG0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_RT_CFG0_RT_CFG0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_RT_CFG0_RT_CFG0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_RT_CFG0_RT_CFG0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_RT_CFG0_RT_CFG0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_RT_CFG0_RT_CFG0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_RT_CFG0_RT_CFG0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_RT_CFG0_RT_CFG0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_RT_CFG0_RT_CFG0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_RT_CFG0_RT_CFG0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_RT_CFG0_RT_CFG0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_RT_CFG0_RT_CFG0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_RT_CFG0_RT_CFG0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_RT_CFG0_RT_CFG0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_RT_CFG0_RT_CFG0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_RT_CFG0_RT_CFG0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_RT_CFG0_RT_CFG0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_RT_CFG0_RT_CFG0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_RT_CFG0_RT_CFG0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_RT_CFG0_RT_CFG0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_RT_CFG0_RT_CFG0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_RT_CFG0_RT_CFG0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_RT_CFG0_RT_CFG0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_RT_CFG0_RT_CFG0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_RT_CFG0_RT_CFG0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_RT_CFG1 register ********/ +#define EXTI_RT_CFG1_RT_CFG1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_RT_CFG1_RT_CFG1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_RT_CFG1_RT_CFG1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_RT_CFG1_RT_CFG1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_RT_CFG1_RT_CFG1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_RT_CFG1_RT_CFG1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_RT_CFG1_RT_CFG1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_RT_CFG1_RT_CFG1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_RT_CFG1_RT_CFG1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_RT_CFG1_RT_CFG1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_RT_CFG1_RT_CFG1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_RT_CFG1_RT_CFG1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_RT_CFG1_RT_CFG1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_RT_CFG1_RT_CFG1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_RT_CFG1_RT_CFG1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_RT_CFG1_RT_CFG1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_RT_CFG1_RT_CFG1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_RT_CFG1_RT_CFG1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_RT_CFG1_RT_CFG1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_RT_CFG1_RT_CFG1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_RT_CFG1_RT_CFG1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_FT_CFG0 register ********/ +#define EXTI_FT_CFG0_FT_CFG0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_FT_CFG0_FT_CFG0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_FT_CFG0_FT_CFG0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_FT_CFG0_FT_CFG0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_FT_CFG0_FT_CFG0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_FT_CFG0_FT_CFG0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_FT_CFG0_FT_CFG0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_FT_CFG0_FT_CFG0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_FT_CFG0_FT_CFG0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_FT_CFG0_FT_CFG0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_FT_CFG0_FT_CFG0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_FT_CFG0_FT_CFG0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_FT_CFG0_FT_CFG0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_FT_CFG0_FT_CFG0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_FT_CFG0_FT_CFG0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_FT_CFG0_FT_CFG0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_FT_CFG0_FT_CFG0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_FT_CFG0_FT_CFG0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_FT_CFG0_FT_CFG0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_FT_CFG0_FT_CFG0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_FT_CFG0_FT_CFG0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_FT_CFG0_FT_CFG0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_FT_CFG0_FT_CFG0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_FT_CFG0_FT_CFG0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_FT_CFG0_FT_CFG0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_FT_CFG0_FT_CFG0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_FT_CFG0_FT_CFG0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_FT_CFG0_FT_CFG0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_FT_CFG0_FT_CFG0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_FT_CFG0_FT_CFG0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_FT_CFG0_FT_CFG0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_FT_CFG0_FT_CFG0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_FT_CFG0_FT_CFG0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_FT_CFG1 register ********/ +#define EXTI_FT_CFG1_FT_CFG1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_FT_CFG1_FT_CFG1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_FT_CFG1_FT_CFG1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_FT_CFG1_FT_CFG1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_FT_CFG1_FT_CFG1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_FT_CFG1_FT_CFG1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_FT_CFG1_FT_CFG1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_FT_CFG1_FT_CFG1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_FT_CFG1_FT_CFG1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_FT_CFG1_FT_CFG1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_FT_CFG1_FT_CFG1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_FT_CFG1_FT_CFG1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_FT_CFG1_FT_CFG1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_FT_CFG1_FT_CFG1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_FT_CFG1_FT_CFG1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_FT_CFG1_FT_CFG1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_FT_CFG1_FT_CFG1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_FT_CFG1_FT_CFG1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_FT_CFG1_FT_CFG1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_FT_CFG1_FT_CFG1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_FT_CFG1_FT_CFG1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_SWIE0 register ********/ +#define EXTI_SWIE0_SWIE0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_SWIE0_SWIE0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_SWIE0_SWIE0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_SWIE0_SWIE0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_SWIE0_SWIE0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_SWIE0_SWIE0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_SWIE0_SWIE0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_SWIE0_SWIE0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_SWIE0_SWIE0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_SWIE0_SWIE0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_SWIE0_SWIE0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_SWIE0_SWIE0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_SWIE0_SWIE0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_SWIE0_SWIE0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_SWIE0_SWIE0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_SWIE0_SWIE0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_SWIE0_SWIE0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_SWIE0_SWIE0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_SWIE0_SWIE0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_SWIE0_SWIE0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_SWIE0_SWIE0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_SWIE0_SWIE0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_SWIE0_SWIE0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_SWIE0_SWIE0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_SWIE0_SWIE0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_SWIE0_SWIE0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_SWIE0_SWIE0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_SWIE0_SWIE0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_SWIE0_SWIE0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_SWIE0_SWIE0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_SWIE0_SWIE0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_SWIE0_SWIE0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_SWIE0_SWIE0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_SWIE1 register ********/ +#define EXTI_SWIE1_SWIE1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_SWIE1_SWIE1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_SWIE1_SWIE1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_SWIE1_SWIE1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_SWIE1_SWIE1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_SWIE1_SWIE1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_SWIE1_SWIE1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_SWIE1_SWIE1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_SWIE1_SWIE1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_SWIE1_SWIE1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_SWIE1_SWIE1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_SWIE1_SWIE1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_SWIE1_SWIE1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_SWIE1_SWIE1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_SWIE1_SWIE1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_SWIE1_SWIE1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_SWIE1_SWIE1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_SWIE1_SWIE1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_SWIE1_SWIE1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_SWIE1_SWIE1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_SWIE1_SWIE1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M7IMASK0 register ********/ +#define EXTI_M7IMASK0_M7IMSK0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M7IMASK0_M7IMSK0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7IMASK0_M7IMSK0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7IMASK0_M7IMSK0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7IMASK0_M7IMSK0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7IMASK0_M7IMSK0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7IMASK0_M7IMSK0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7IMASK0_M7IMSK0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7IMASK0_M7IMSK0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7IMASK0_M7IMSK0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7IMASK0_M7IMSK0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7IMASK0_M7IMSK0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7IMASK0_M7IMSK0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7IMASK0_M7IMSK0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7IMASK0_M7IMSK0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7IMASK0_M7IMSK0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7IMASK0_M7IMSK0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7IMASK0_M7IMSK0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7IMASK0_M7IMSK0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7IMASK0_M7IMSK0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7IMASK0_M7IMSK0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7IMASK0_M7IMSK0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7IMASK0_M7IMSK0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7IMASK0_M7IMSK0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7IMASK0_M7IMSK0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7IMASK0_M7IMSK0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7IMASK0_M7IMSK0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7IMASK0_M7IMSK0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M7IMASK0_M7IMSK0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M7IMASK0_M7IMSK0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M7IMASK0_M7IMSK0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M7IMASK0_M7IMSK0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M7IMASK0_M7IMSK0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M7IMASK1 register ********/ +#define EXTI_M7IMASK1_M7IMSK1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_M7IMASK1_M7IMSK1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7IMASK1_M7IMSK1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7IMASK1_M7IMSK1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7IMASK1_M7IMSK1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7IMASK1_M7IMSK1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7IMASK1_M7IMSK1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7IMASK1_M7IMSK1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7IMASK1_M7IMSK1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7IMASK1_M7IMSK1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7IMASK1_M7IMSK1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7IMASK1_M7IMSK1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7IMASK1_M7IMSK1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7IMASK1_M7IMSK1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7IMASK1_M7IMSK1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7IMASK1_M7IMSK1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7IMASK1_M7IMSK1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7IMASK1_M7IMSK1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7IMASK1_M7IMSK1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7IMASK1_M7IMSK1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7IMASK1_M7IMSK1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M4IMASK0 register ********/ +#define EXTI_M4IMASK0_M4IMSK0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M4IMASK0_M4IMSK0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4IMASK0_M4IMSK0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4IMASK0_M4IMSK0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4IMASK0_M4IMSK0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4IMASK0_M4IMSK0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4IMASK0_M4IMSK0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4IMASK0_M4IMSK0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4IMASK0_M4IMSK0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4IMASK0_M4IMSK0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4IMASK0_M4IMSK0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4IMASK0_M4IMSK0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4IMASK0_M4IMSK0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4IMASK0_M4IMSK0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4IMASK0_M4IMSK0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4IMASK0_M4IMSK0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4IMASK0_M4IMSK0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4IMASK0_M4IMSK0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4IMASK0_M4IMSK0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4IMASK0_M4IMSK0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4IMASK0_M4IMSK0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4IMASK0_M4IMSK0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4IMASK0_M4IMSK0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4IMASK0_M4IMSK0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4IMASK0_M4IMSK0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4IMASK0_M4IMSK0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4IMASK0_M4IMSK0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4IMASK0_M4IMSK0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M4IMASK0_M4IMSK0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M4IMASK0_M4IMSK0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M4IMASK0_M4IMSK0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M4IMASK0_M4IMSK0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M4IMASK0_M4IMSK0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M4IMASK1 register ********/ +#define EXTI_M4IMASK1_M4IMSK1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_M4IMASK1_M4IMSK1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4IMASK1_M4IMSK1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4IMASK1_M4IMSK1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4IMASK1_M4IMSK1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4IMASK1_M4IMSK1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4IMASK1_M4IMSK1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4IMASK1_M4IMSK1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4IMASK1_M4IMSK1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4IMASK1_M4IMSK1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4IMASK1_M4IMSK1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4IMASK1_M4IMSK1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4IMASK1_M4IMSK1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4IMASK1_M4IMSK1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4IMASK1_M4IMSK1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4IMASK1_M4IMSK1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4IMASK1_M4IMSK1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4IMASK1_M4IMSK1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4IMASK1_M4IMSK1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4IMASK1_M4IMSK1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4IMASK1_M4IMSK1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M7EMASK0 register ********/ +#define EXTI_M7EMASK0_M7EMASK0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M7EMASK0_M7EMASK0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7EMASK0_M7EMASK0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7EMASK0_M7EMASK0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7EMASK0_M7EMASK0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7EMASK0_M7EMASK0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7EMASK0_M7EMASK0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7EMASK0_M7EMASK0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7EMASK0_M7EMASK0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7EMASK0_M7EMASK0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7EMASK0_M7EMASK0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7EMASK0_M7EMASK0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7EMASK0_M7EMASK0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7EMASK0_M7EMASK0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7EMASK0_M7EMASK0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7EMASK0_M7EMASK0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7EMASK0_M7EMASK0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7EMASK0_M7EMASK0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7EMASK0_M7EMASK0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7EMASK0_M7EMASK0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7EMASK0_M7EMASK0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7EMASK0_M7EMASK0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7EMASK0_M7EMASK0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7EMASK0_M7EMASK0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7EMASK0_M7EMASK0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7EMASK0_M7EMASK0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7EMASK0_M7EMASK0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7EMASK0_M7EMASK0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M7EMASK0_M7EMASK0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M7EMASK0_M7EMASK0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M7EMASK0_M7EMASK0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M7EMASK0_M7EMASK0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M7EMASK0_M7EMASK0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M7EMASK1 register ********/ +#define EXTI_M7EMASK1_M7EMASK1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_M7EMASK1_M7EMASK1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7EMASK1_M7EMASK1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7EMASK1_M7EMASK1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7EMASK1_M7EMASK1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7EMASK1_M7EMASK1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7EMASK1_M7EMASK1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7EMASK1_M7EMASK1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7EMASK1_M7EMASK1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7EMASK1_M7EMASK1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7EMASK1_M7EMASK1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7EMASK1_M7EMASK1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7EMASK1_M7EMASK1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7EMASK1_M7EMASK1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7EMASK1_M7EMASK1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7EMASK1_M7EMASK1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7EMASK1_M7EMASK1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7EMASK1_M7EMASK1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7EMASK1_M7EMASK1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7EMASK1_M7EMASK1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7EMASK1_M7EMASK1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M4EMASK0 register ********/ +#define EXTI_M4EMASK0_M4EMASK0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M4EMASK0_M4EMASK0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4EMASK0_M4EMASK0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4EMASK0_M4EMASK0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4EMASK0_M4EMASK0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4EMASK0_M4EMASK0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4EMASK0_M4EMASK0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4EMASK0_M4EMASK0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4EMASK0_M4EMASK0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4EMASK0_M4EMASK0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4EMASK0_M4EMASK0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4EMASK0_M4EMASK0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4EMASK0_M4EMASK0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4EMASK0_M4EMASK0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4EMASK0_M4EMASK0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4EMASK0_M4EMASK0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4EMASK0_M4EMASK0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4EMASK0_M4EMASK0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4EMASK0_M4EMASK0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4EMASK0_M4EMASK0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4EMASK0_M4EMASK0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4EMASK0_M4EMASK0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4EMASK0_M4EMASK0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4EMASK0_M4EMASK0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4EMASK0_M4EMASK0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4EMASK0_M4EMASK0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4EMASK0_M4EMASK0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4EMASK0_M4EMASK0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M4EMASK0_M4EMASK0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M4EMASK0_M4EMASK0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M4EMASK0_M4EMASK0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M4EMASK0_M4EMASK0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M4EMASK0_M4EMASK0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M4EMASK1 register ********/ +#define EXTI_M4EMASK1_M4EMASK1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_M4EMASK1_M4EMASK1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4EMASK1_M4EMASK1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4EMASK1_M4EMASK1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4EMASK1_M4EMASK1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4EMASK1_M4EMASK1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4EMASK1_M4EMASK1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4EMASK1_M4EMASK1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4EMASK1_M4EMASK1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4EMASK1_M4EMASK1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4EMASK1_M4EMASK1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4EMASK1_M4EMASK1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4EMASK1_M4EMASK1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4EMASK1_M4EMASK1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4EMASK1_M4EMASK1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4EMASK1_M4EMASK1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4EMASK1_M4EMASK1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4EMASK1_M4EMASK1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4EMASK1_M4EMASK1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4EMASK1_M4EMASK1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4EMASK1_M4EMASK1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M7PEND0 register ********/ +#define EXTI_M7PEND0_M7PEND0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M7PEND0_M7PEND0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7PEND0_M7PEND0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7PEND0_M7PEND0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7PEND0_M7PEND0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7PEND0_M7PEND0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7PEND0_M7PEND0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7PEND0_M7PEND0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7PEND0_M7PEND0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7PEND0_M7PEND0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7PEND0_M7PEND0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7PEND0_M7PEND0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7PEND0_M7PEND0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7PEND0_M7PEND0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7PEND0_M7PEND0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7PEND0_M7PEND0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7PEND0_M7PEND0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7PEND0_M7PEND0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7PEND0_M7PEND0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7PEND0_M7PEND0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7PEND0_M7PEND0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7PEND0_M7PEND0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7PEND0_M7PEND0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7PEND0_M7PEND0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7PEND0_M7PEND0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7PEND0_M7PEND0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7PEND0_M7PEND0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7PEND0_M7PEND0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M7PEND0_M7PEND0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M7PEND0_M7PEND0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M7PEND0_M7PEND0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M7PEND0_M7PEND0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M7PEND0_M7PEND0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M7PEND1 register ********/ +#define EXTI_M7PEND1_M7PEND1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_M7PEND1_M7PEND1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7PEND1_M7PEND1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7PEND1_M7PEND1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7PEND1_M7PEND1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7PEND1_M7PEND1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7PEND1_M7PEND1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7PEND1_M7PEND1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7PEND1_M7PEND1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7PEND1_M7PEND1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7PEND1_M7PEND1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7PEND1_M7PEND1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7PEND1_M7PEND1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7PEND1_M7PEND1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7PEND1_M7PEND1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7PEND1_M7PEND1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7PEND1_M7PEND1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7PEND1_M7PEND1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7PEND1_M7PEND1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7PEND1_M7PEND1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7PEND1_M7PEND1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M4PEND0 register ********/ +#define EXTI_M4PEND0_M4PEND0x ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M4PEND0_M4PEND0x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4PEND0_M4PEND0x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4PEND0_M4PEND0x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4PEND0_M4PEND0x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4PEND0_M4PEND0x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4PEND0_M4PEND0x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4PEND0_M4PEND0x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4PEND0_M4PEND0x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4PEND0_M4PEND0x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4PEND0_M4PEND0x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4PEND0_M4PEND0x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4PEND0_M4PEND0x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4PEND0_M4PEND0x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4PEND0_M4PEND0x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4PEND0_M4PEND0x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4PEND0_M4PEND0x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4PEND0_M4PEND0x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4PEND0_M4PEND0x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4PEND0_M4PEND0x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4PEND0_M4PEND0x_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4PEND0_M4PEND0x_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4PEND0_M4PEND0x_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4PEND0_M4PEND0x_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4PEND0_M4PEND0x_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4PEND0_M4PEND0x_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4PEND0_M4PEND0x_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4PEND0_M4PEND0x_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M4PEND0_M4PEND0x_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M4PEND0_M4PEND0x_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M4PEND0_M4PEND0x_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M4PEND0_M4PEND0x_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M4PEND0_M4PEND0x_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M4PEND1 register ********/ +#define EXTI_M4PEND1_M4PEND1x ((uint32_t)0x000FFFFFU) /* Bit[19:0] */ +#define EXTI_M4PEND1_M4PEND1x_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4PEND1_M4PEND1x_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4PEND1_M4PEND1x_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4PEND1_M4PEND1x_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4PEND1_M4PEND1x_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4PEND1_M4PEND1x_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4PEND1_M4PEND1x_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4PEND1_M4PEND1x_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4PEND1_M4PEND1x_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4PEND1_M4PEND1x_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4PEND1_M4PEND1x_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4PEND1_M4PEND1x_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4PEND1_M4PEND1x_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4PEND1_M4PEND1x_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4PEND1_M4PEND1x_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4PEND1_M4PEND1x_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4PEND1_M4PEND1x_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4PEND1_M4PEND1x_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4PEND1_M4PEND1x_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4PEND1_M4PEND1x_19 ((uint32_t)0x00080000U) /* Bit19*/ + +/******** Bit definition for EXTI_M7IMASK0_DRC register ********/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M7IMASK0_DRC_M7IMASK0_DRCx_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M7IMASK1_DRC register ********/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx ((uint32_t)0x07FFFFFFU) /* Bit[26:0] */ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7IMASK1_DRC_M7IMASK1_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ + +/******** Bit definition for EXTI_M4IMASK0_DRC register ********/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M4IMASK0_DRC_M4IMASK0_DRCx_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M4IMASK1_DRC register ********/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx ((uint32_t)0x07FFFFFFU) /* Bit[26:0] */ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4IMASK1_DRC_M4IMASK1_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ + +/******** Bit definition for EXTI_M7EMASK0_DRC register ********/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M7EMASK0_DRC_M7EMASK0_DRCx_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M7EMASK1_DRC register ********/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx ((uint32_t)0x07FFFFFFU) /* Bit[26:0] */ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M7EMASK1_DRC_M7EMASK1_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ + +/******** Bit definition for EXTI_M4EMASK0_DRC register ********/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define EXTI_M4EMASK0_DRC_M4EMASK0_DRCx_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for EXTI_M4EMASK1_DRC register ********/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx ((uint32_t)0x07FFFFFFU) /* Bit[26:0] */ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define EXTI_M4EMASK1_DRC_M4EMASK1_DRCx_26 ((uint32_t)0x04000000U) /* Bit26*/ + +/******** Bit definition for EXTI_TS_SEL register ********/ +#define EXTI_TS_SEL_TSSEL ((uint32_t)0x00000F00U) /* Bit[11:8] */ +#define EXTI_TS_SEL_TSSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define EXTI_TS_SEL_TSSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define EXTI_TS_SEL_TSSEL_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define EXTI_TS_SEL_TSSEL_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define EXTI_TS_SEL_EXTI0 ((uint32_t)0x00000000U) /* Select EXTI0 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI1 ((uint32_t)0x00000100U) /* Select EXTI1 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI2 ((uint32_t)0x00000200U) /* Select EXTI2 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI3 ((uint32_t)0x00000300U) /* Select EXTI3 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI4 ((uint32_t)0x00000400U) /* Select EXTI4 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI5 ((uint32_t)0x00000500U) /* Select EXTI5 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI6 ((uint32_t)0x00000600U) /* Select EXTI6 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI7 ((uint32_t)0x00000700U) /* Select EXTI7 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI8 ((uint32_t)0x00000800U) /* Select EXTI8 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI9 ((uint32_t)0x00000900U) /* Select EXTI9 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI10 ((uint32_t)0x00000A00U) /* Select EXTI10 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI11 ((uint32_t)0x00000B00U) /* Select EXTI11 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI12 ((uint32_t)0x00000C00U) /* Select EXTI12 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI13 ((uint32_t)0x00000D00U) /* Select EXTI13 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI14 ((uint32_t)0x00000E00U) /* Select EXTI14 as trigger source of timestamp event */ +#define EXTI_TS_SEL_EXTI15 ((uint32_t)0x00000F00U) /* Select EXTI15 as trigger source of timestamp event */ + +/*** Synchronous Dynamic Random Access Memory(SDRAM) interface ***/ + +/** Bit definition for SDRAM_BADD1 register **/ +#define SDRAM_BADD1_ADDBASE ((uint32_t)0x000FFFFFU) /* ADDBASE[19:0] bits (Base address value for SDRAM1) */ + +/** Bit definition for SDRAM_ADDMASK1 register **/ +#define SDRAM_ADDMASK1_ADDMASK ((uint32_t)0x000FFFFFU) /* ADDMASK[19:0] bits (Address mask value for SDRAM1) */ + +/** Bit definition for SDRAM_BADD2 register **/ +#define SDRAM_BADD2_ADDBASE ((uint32_t)0x000FFFFFU) /* ADDBASE[19:0] bits (Base address value for SDRAM2) */ + +/** Bit definition for SDRAM_ADDMASK2 register **/ +#define SDRAM_ADDMASK2_ADDMASK ((uint32_t)0x000FFFFFU) /* ADDMASK[19:0] bits (Address mask value for SDRAM2) */ + +/** Bit definition for SDRAM_CFG1 and SDRAM_CFG2 register **/ +#define SDRAM_CFG_SDRAMEN ((uint32_t)0x80000000U) /* SDRAM1 or SDRAM2 enable bit */ +#define SDRAM_CFG_REFRESHEN ((uint32_t)0x40000000U) /* Refresh commands enable bit */ +#define SDRAM_CFG_AUTOPCHEN ((uint32_t)0x00800000U) /* Auto precharge enable bit */ +#define SDRAM_CFG_BUSWID ((uint32_t)0x00600000U) /* BUSWID[1:0] bits (bus width) */ +#define SDRAM_CFG_BUSWID_0 ((uint32_t)0x00200000U) /* Bit 0 */ +#define SDRAM_CFG_BUSWID_1 ((uint32_t)0x00400000U) /* Bit 1 */ +#define SDRAM_CFG_BURSTLEN ((uint32_t)0x001C0000U) /* BURSTLEN[2:0] bits (burst length) */ +#define SDRAM_CFG_BURSTLEN_0 ((uint32_t)0x00040000U) /* Bit 0 */ +#define SDRAM_CFG_BURSTLEN_1 ((uint32_t)0x00080000U) /* Bit 1 */ +#define SDRAM_CFG_BURSTLEN_2 ((uint32_t)0x00100000U) /* Bit 2 */ +#define SDRAM_CFG_CASLATENCY ((uint32_t)0x00030000U) /* CASLATENCY[1:0] bits (CAS latency) */ +#define SDRAM_CFG_CASLATENCY_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define SDRAM_CFG_CASLATENCY_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define SDRAM_CFG_PREFCHRDEN ((uint32_t)0x00000200U) /* Prefetch read enable bit */ +#define SDRAM_CFG_SOMEN ((uint32_t)0x00000100U) /* Write buffer store on miss(SOM) enable bit */ +#define SDRAM_CFG_BANKINTRLEN ((uint32_t)0x00000010U) /* Bank interleaving enable bit */ +#define SDRAM_CFG_ADDCFG ((uint32_t)0x0000000FU) /* ADDCFG[3:0] bits (Address organization configuration of SDRAM1 or SDRAM2) */ +#define SDRAM_CFG_ADDCFG_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define SDRAM_CFG_ADDCFG_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define SDRAM_CFG_ADDCFG_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define SDRAM_CFG_ADDCFG_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +/** Bit definition for SDRAM_RAT register **/ +#define SDRAM_RAT_TRAS ((uint32_t)0x0000003FU) /* TRAS[5:0] bits (Row active time) */ + +/** Bit definition for SDRAM_RCT register **/ +#define SDRAM_RCT_TRC ((uint32_t)0x0000003FU) /* TRC[5:0] bits (Row cycle time) */ + +/** Bit definition for SDRAM_RRDLY register **/ +#define SDRAM_RRDLY_TRRD ((uint32_t)0x0000003FU) /* TRRD[5:0] bits (Row active to row active delay time) */ + +/** Bit definition for SDRAM_PT register **/ +#define SDRAM_PT_TRP ((uint32_t)0x0000003FU) /* TRP[5:0] bits (Precharge time) */ + +/** Bit definition for SDRAM_WRT register **/ +#define SDRAM_WRT_TWR ((uint32_t)0x0000003FU) /* TWR[5:0] bits (Write recovery time) */ + +/** Bit definition for SDRAM_RFCT register **/ +#define SDRAM_RFCT_TRFC ((uint32_t)0x0000003FU) /* TRFC[5:0] bits (Refresh cycle time) */ + +/** Bit definition for SDRAM_RCDLY register **/ +#define SDRAM_RCDLY_TRCD ((uint32_t)0x0000000FU) /* TRCD[3:0] bits (RAS to CAS delay time) */ + +/** Bit definition for SDRAM_RI register **/ +#define SDRAM_RI_TRI ((uint32_t)0x00FFFFFFU) /* TRI[23:0] bits (Refresh interval time) */ + +/** Bit definition for SDRAM_CBO register **/ +#define SDRAM_CBO_DUMMY ((uint32_t)0xFFFFFFFFU) /* DUMMY[31:0] bits (Dummy data) */ + +/** Bit definition for SDRAM_OR register **/ +#define SDRAM_OR_DUMMY ((uint32_t)0xFFFFFFFFU) /* DUMMY[31:0] bits (Dummy data) */ + +/** Bit definition for SDRAM_OS register **/ +#define SDRAM_OS_CKEN ((uint32_t)0x40000000U) /* Clock enable bit */ +#define SDRAM_OS_OPCODE ((uint32_t)0x30000000U) /* OPCODE[1:0] bits (Operation code) */ +#define SDRAM_OS_OPCODE_0 ((uint32_t)0x10000000U) /* Bit 0 */ +#define SDRAM_OS_OPCODE_1 ((uint32_t)0x20000000U) /* Bit 1 */ +#define SDRAM_OS_CS ((uint32_t)0x03000000U) /* CS[1:0] bits (Chip select) */ +#define SDRAM_OS_CS_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define SDRAM_OS_CS_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define SDRAM_OS_BANKADD ((uint32_t)0x00030000U) /* BANKADD[1:0] bits (Bank address) */ +#define SDRAM_OS_BANKADD_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define SDRAM_OS_BANKADD_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define SDRAM_OS_ADD ((uint32_t)0x00003FFFU) /* ADD[3:0] bits (Address) */ + + +/** Bit definition for SDRAM_IINFO register **/ +#define SDRAM_IINFO_SYNCMEMBUFSIZE ((uint32_t)0x00FF0000U) /* SYNCMEMBUFSIZE[7:0] bits (Synchronous memory buffer size) */ + +/** Bit definition for SDRAM_WP register **/ +#define SDRAM_WP_WP1 ((uint32_t)0x00000001U) /* SRAM1 Write protection */ +#define SDRAM_WP_WP2 ((uint32_t)0x00000002U) /* SRAM2 Write protection */ + + +/******** Bit definition for RCC_PLL1CTRL1 register ********/ +#define RCC_PLL1CTRL1_PLL1SRC ((uint32_t)0x30000000U) /* Bit[29:28] */ +#define RCC_PLL1CTRL1_PLL1SRC_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_PLL1CTRL1_PLL1SRC_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_PLL1CTRL1_PLL1PHLK ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_PLL1CTRL1_PLL1LDOEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_PLL1CTRL1_PLL1EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_PLL1CTRL1_PLL1RST ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_PLL1CTRL1_PLL1PD ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_PLL1CTRL1_PLL1BWAJ ((uint32_t)0x00000FFFU) /* Bit */ +#define RCC_PLL1CTRL1_PLL1BWAJ_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL1CTRL1_PLL1BWAJ_11 ((uint32_t)0x00000800U) /* Bit11*/ + +/******** Bit definition for RCC_PLL1CTRL2 register ********/ +#define RCC_PLL1CTRL2_PLL1CLKR ((uint32_t)0xFC000000U) /* Bit[31:26] */ +#define RCC_PLL1CTRL2_PLL1CLKR_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_PLL1CTRL2_PLL1CLKR_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_PLL1CTRL2_PLL1CLKR_2 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_PLL1CTRL2_PLL1CLKR_3 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_PLL1CTRL2_PLL1CLKR_4 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_PLL1CTRL2_PLL1CLKR_5 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_PLL1CTRL2_PLL1CLKF ((uint32_t)0x03FFFFFFU) /* Bit */ +#define RCC_PLL1CTRL2_PLL1CLKF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL1CTRL2_PLL1CLKF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL1CTRL2_PLL1CLKF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL1CTRL2_PLL1CLKF_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL1CTRL2_PLL1CLKF_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL1CTRL2_PLL1CLKF_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_PLL1CTRL2_PLL1CLKF_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_PLL1CTRL2_PLL1CLKF_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_PLL1CTRL2_PLL1CLKF_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL1CTRL2_PLL1CLKF_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL1CTRL2_PLL1CLKF_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL1CTRL2_PLL1CLKF_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_PLL1CTRL2_PLL1CLKF_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_PLL1CTRL2_PLL1CLKF_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_PLL1CTRL2_PLL1CLKF_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_PLL1CTRL2_PLL1CLKF_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_PLL1CTRL2_PLL1CLKF_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_PLL1CTRL2_PLL1CLKF_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_PLL1CTRL2_PLL1CLKF_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_PLL1CTRL2_PLL1CLKF_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_PLL1CTRL2_PLL1CLKF_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_PLL1CTRL2_PLL1CLKF_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_PLL1CTRL2_PLL1CLKF_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_PLL1CTRL2_PLL1CLKF_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_PLL1CTRL2_PLL1CLKF_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_PLL1CTRL2_PLL1CLKF_25 ((uint32_t)0x02000000U) /* Bit25*/ + +/******** Bit definition for RCC_PLL2CTRL1 register ********/ +#define RCC_PLL2CTRL1_PLL2SRC ((uint32_t)0x30000000U) /* Bit[29:28] */ +#define RCC_PLL2CTRL1_PLL2SRC_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_PLL2CTRL1_PLL2SRC_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_PLL2CTRL1_PLL2PHLK ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_PLL2CTRL1_PLL2LDOEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_PLL2CTRL1_PLL2EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_PLL2CTRL1_PLL2RST ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_PLL2CTRL1_PLL2PD ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_PLL2CTRL1_PLL2BWAJ ((uint32_t)0x00000FFFU) /* Bit */ +#define RCC_PLL2CTRL1_PLL2BWAJ_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL2CTRL1_PLL2BWAJ_11 ((uint32_t)0x00000800U) /* Bit11*/ + +/******** Bit definition for RCC_PLL2CTRL2 register ********/ +#define RCC_PLL2CTRL2_PLL2CLKR ((uint32_t)0xFC000000U) /* Bit[31:26] */ +#define RCC_PLL2CTRL2_PLL2CLKR_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_PLL2CTRL2_PLL2CLKR_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_PLL2CTRL2_PLL2CLKR_2 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_PLL2CTRL2_PLL2CLKR_3 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_PLL2CTRL2_PLL2CLKR_4 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_PLL2CTRL2_PLL2CLKR_5 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_PLL2CTRL2_PLL2CLKF ((uint32_t)0x03FFFFFFU) /* Bit */ +#define RCC_PLL2CTRL2_PLL2CLKF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL2CTRL2_PLL2CLKF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL2CTRL2_PLL2CLKF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL2CTRL2_PLL2CLKF_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL2CTRL2_PLL2CLKF_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL2CTRL2_PLL2CLKF_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_PLL2CTRL2_PLL2CLKF_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_PLL2CTRL2_PLL2CLKF_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_PLL2CTRL2_PLL2CLKF_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL2CTRL2_PLL2CLKF_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL2CTRL2_PLL2CLKF_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL2CTRL2_PLL2CLKF_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_PLL2CTRL2_PLL2CLKF_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_PLL2CTRL2_PLL2CLKF_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_PLL2CTRL2_PLL2CLKF_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_PLL2CTRL2_PLL2CLKF_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_PLL2CTRL2_PLL2CLKF_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_PLL2CTRL2_PLL2CLKF_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_PLL2CTRL2_PLL2CLKF_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_PLL2CTRL2_PLL2CLKF_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_PLL2CTRL2_PLL2CLKF_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_PLL2CTRL2_PLL2CLKF_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_PLL2CTRL2_PLL2CLKF_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_PLL2CTRL2_PLL2CLKF_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_PLL2CTRL2_PLL2CLKF_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_PLL2CTRL2_PLL2CLKF_25 ((uint32_t)0x02000000U) /* Bit25*/ + + +/******** Bit definition for RCC_PLL3CTRL1 register ********/ +#define RCC_PLL3CTRL1_PLL3SRC ((uint32_t)0x30000000U) /* Bit[29:28] */ +#define RCC_PLL3CTRL1_PLL3SRC_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_PLL3CTRL1_PLL3SRC_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_PLL3CTRL1_PLL3PHLK ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_PLL3CTRL1_PLL3LDOEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_PLL3CTRL1_PLL3EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_PLL3CTRL1_PLL3RST ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_PLL3CTRL1_PLL3PD ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_PLL3CTRL1_PLL3BWAJ ((uint32_t)0x00000FFFU) /* Bit */ +#define RCC_PLL3CTRL1_PLL3BWAJ_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL3CTRL1_PLL3BWAJ_11 ((uint32_t)0x00000800U) /* Bit11*/ + +/******** Bit definition for RCC_PLL3CTRL2 register ********/ +#define RCC_PLL3CTRL2_PLL3CLKR ((uint32_t)0xFC000000U) /* Bit[31:26] */ +#define RCC_PLL3CTRL2_PLL3CLKR_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_PLL3CTRL2_PLL3CLKR_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_PLL3CTRL2_PLL3CLKR_2 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_PLL3CTRL2_PLL3CLKR_3 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_PLL3CTRL2_PLL3CLKR_4 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_PLL3CTRL2_PLL3CLKR_5 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_PLL3CTRL2_PLL3CLKF ((uint32_t)0x03FFFFFFU) /* Bit */ +#define RCC_PLL3CTRL2_PLL3CLKF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL3CTRL2_PLL3CLKF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL3CTRL2_PLL3CLKF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL3CTRL2_PLL3CLKF_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL3CTRL2_PLL3CLKF_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL3CTRL2_PLL3CLKF_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_PLL3CTRL2_PLL3CLKF_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_PLL3CTRL2_PLL3CLKF_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_PLL3CTRL2_PLL3CLKF_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL3CTRL2_PLL3CLKF_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL3CTRL2_PLL3CLKF_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL3CTRL2_PLL3CLKF_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_PLL3CTRL2_PLL3CLKF_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_PLL3CTRL2_PLL3CLKF_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_PLL3CTRL2_PLL3CLKF_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_PLL3CTRL2_PLL3CLKF_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_PLL3CTRL2_PLL3CLKF_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_PLL3CTRL2_PLL3CLKF_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_PLL3CTRL2_PLL3CLKF_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_PLL3CTRL2_PLL3CLKF_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_PLL3CTRL2_PLL3CLKF_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_PLL3CTRL2_PLL3CLKF_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_PLL3CTRL2_PLL3CLKF_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_PLL3CTRL2_PLL3CLKF_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_PLL3CTRL2_PLL3CLKF_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_PLL3CTRL2_PLL3CLKF_25 ((uint32_t)0x02000000U) /* Bit25*/ + + +/******** Bit definition for RCC_SHRPLLCTRL1 register ********/ +#define RCC_SHRPLLCTRL1_SHRPLLSRC ((uint32_t)0x30000000U) /* Bit[29:28] */ +#define RCC_SHRPLLCTRL1_SHRPLLSRC_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_SHRPLLCTRL1_SHRPLLSRC_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_SHRPLLCTRL1_SHRPLLPHLK ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_SHRPLLCTRL1_SHRPLLLDOEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_SHRPLLCTRL1_SHRPLLEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_SHRPLLCTRL1_SHRPLLRST ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_SHRPLLCTRL1_SHRPLLPD ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ ((uint32_t)0x00000FFFU) /* Bit */ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_SHRPLLCTRL1_SHRPLLBWAJ_11 ((uint32_t)0x00000800U) /* Bit11*/ + +/******** Bit definition for RCC_SHRPLLCTRL2 register ********/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR ((uint32_t)0xFC000000U) /* Bit[31:26] */ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR_2 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR_3 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR_4 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKR_5 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF ((uint32_t)0x03FFFFFFU) /* Bit */ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_SHRPLLCTRL2_SHRPLLCLKF_25 ((uint32_t)0x02000000U) /* Bit25*/ + +/******** Bit definition for RCC_SRCCTRL1 register ********/ +#define RCC_SRCCTRL1_AFEMSIRDF ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_SRCCTRL1_AFEHSIRDF ((uint32_t)0x40000000U) /* Bit[30] */ + +#define RCC_SRCCTRL1_SCLKSTS ((uint32_t)0x0C000000U) /* Bit[27:26] */ +#define RCC_SRCCTRL1_SCLKSTS_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_SRCCTRL1_SCLKSTS_1 ((uint32_t)0x08000000U) /* Bit27*/ + +#define RCC_SRCCTRL1_SCLKSTS_HSI ((uint32_t)0x00000000U) +#define RCC_SRCCTRL1_SCLKSTS_MSI ((uint32_t)0x04000000U) +#define RCC_SRCCTRL1_SCLKSTS_HSE ((uint32_t)0x08000000U) +#define RCC_SRCCTRL1_SCLKSTS_PLL1 ((uint32_t)0x0C000000U) + +#define RCC_SRCCTRL1_SCLKSW ((uint32_t)0x03000000U) /* Bit[25:24] */ +#define RCC_SRCCTRL1_SCLKSW_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_SRCCTRL1_SCLKSW_1 ((uint32_t)0x02000000U) /* Bit25*/ + +#define RCC_SRCCTRL1_SCLKSW_HSI ((uint32_t)0x00000000U) +#define RCC_SRCCTRL1_SCLKSW_MSI ((uint32_t)0x01000000U) +#define RCC_SRCCTRL1_SCLKSW_HSE ((uint32_t)0x02000000U) +#define RCC_SRCCTRL1_SCLKSW_PLL1 ((uint32_t)0x03000000U) + +#define RCC_SRCCTRL1_HSERDCNTEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_SRCCTRL1_MSIRDF ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_SRCCTRL1_MSIEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_SRCCTRL1_HSECSSEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_SRCCTRL1_HSEBP ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_SRCCTRL1_HSERDF ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_SRCCTRL1_HSEEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_SRCCTRL1_HSIRDF ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_SRCCTRL1_HSIEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_SRCCTRL2 register ********/ +#define RCC_SRCCTRL2_BORF ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_SRCCTRL2_HSICALEF ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_SRCCTRL2_MSICALEF ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_SRCCTRL2_M7HYPSEL ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_SRCCTRL2_AXIHYPSEL ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_SRCCTRL2_MSICAL ((uint32_t)0x00001F00U) /* Bit[12:8] */ +#define RCC_SRCCTRL2_MSICAL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_SRCCTRL2_MSICAL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_SRCCTRL2_MSICAL_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_SRCCTRL2_MSICAL_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_SRCCTRL2_MSICAL_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_SRCCTRL2_MSITRIM ((uint32_t)0x0000001FU) /* Bit */ +#define RCC_SRCCTRL2_MSITRIM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_SRCCTRL2_MSITRIM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_SRCCTRL2_MSITRIM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_SRCCTRL2_MSITRIM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_SRCCTRL2_MSITRIM_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for RCC_SRCCTRL3 register ********/ +#define RCC_SRCCTRL3_HSICAL ((uint32_t)0x01FF0000U) /* Bit[24:16] */ +#define RCC_SRCCTRL3_HSICAL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_SRCCTRL3_HSICAL_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_SRCCTRL3_HSICAL_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_SRCCTRL3_HSICAL_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_SRCCTRL3_HSICAL_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_SRCCTRL3_HSICAL_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_SRCCTRL3_HSICAL_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_SRCCTRL3_HSICAL_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_SRCCTRL3_HSICAL_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_SRCCTRL3_HSITRIM ((uint32_t)0x000001FFU) /* Bit */ +#define RCC_SRCCTRL3_HSITRIM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_SRCCTRL3_HSITRIM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_SRCCTRL3_HSITRIM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_SRCCTRL3_HSITRIM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_SRCCTRL3_HSITRIM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_SRCCTRL3_HSITRIM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_SRCCTRL3_HSITRIM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_SRCCTRL3_HSITRIM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_SRCCTRL3_HSITRIM_8 ((uint32_t)0x00000100U) /* Bit8*/ + +/******** Bit definition for RCC_PLL1DIV register ********/ +#define RCC_PLL1DIV_PLL1CDIV ((uint32_t)0x003F0000U) /* Bit[21:16] */ +#define RCC_PLL1DIV_PLL1CDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_PLL1DIV_PLL1CDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_PLL1DIV_PLL1CDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_PLL1DIV_PLL1CDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_PLL1DIV_PLL1CDIV_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_PLL1DIV_PLL1CDIV_5 ((uint32_t)0x00200000U) /* Bit21*/ + +#define RCC_PLL1DIV_PLL1CDIV_DIV1 ((uint32_t)0x00010000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV2 ((uint32_t)0x00020000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV3 ((uint32_t)0x00030000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV4 ((uint32_t)0x00040000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV5 ((uint32_t)0x00050000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV6 ((uint32_t)0x00060000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV7 ((uint32_t)0x00070000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV8 ((uint32_t)0x00080000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV9 ((uint32_t)0x00090000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV10 ((uint32_t)0x000A0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV11 ((uint32_t)0x000B0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV12 ((uint32_t)0x000C0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV13 ((uint32_t)0x000D0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV14 ((uint32_t)0x000E0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV15 ((uint32_t)0x000F0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV16 ((uint32_t)0x00100000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV17 ((uint32_t)0x00110000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV18 ((uint32_t)0x00120000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV19 ((uint32_t)0x00130000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV20 ((uint32_t)0x00140000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV21 ((uint32_t)0x00150000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV22 ((uint32_t)0x00160000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV23 ((uint32_t)0x00170000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV24 ((uint32_t)0x00180000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV25 ((uint32_t)0x00190000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV26 ((uint32_t)0x001A0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV27 ((uint32_t)0x001B0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV28 ((uint32_t)0x001C0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV29 ((uint32_t)0x001D0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV30 ((uint32_t)0x001E0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV31 ((uint32_t)0x001F0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV32 ((uint32_t)0x00200000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV33 ((uint32_t)0x00210000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV34 ((uint32_t)0x00220000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV35 ((uint32_t)0x00230000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV36 ((uint32_t)0x00240000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV37 ((uint32_t)0x00250000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV38 ((uint32_t)0x00260000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV39 ((uint32_t)0x00270000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV40 ((uint32_t)0x00280000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV41 ((uint32_t)0x00290000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV42 ((uint32_t)0x002A0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV43 ((uint32_t)0x002B0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV44 ((uint32_t)0x002C0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV45 ((uint32_t)0x002D0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV46 ((uint32_t)0x002E0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV47 ((uint32_t)0x002F0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV48 ((uint32_t)0x00300000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV49 ((uint32_t)0x00310000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV50 ((uint32_t)0x00320000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV51 ((uint32_t)0x00330000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV52 ((uint32_t)0x00340000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV53 ((uint32_t)0x00350000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV54 ((uint32_t)0x00360000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV55 ((uint32_t)0x00370000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV56 ((uint32_t)0x00380000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV57 ((uint32_t)0x00390000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV58 ((uint32_t)0x003A0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV59 ((uint32_t)0x003B0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV60 ((uint32_t)0x003C0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV61 ((uint32_t)0x003D0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV62 ((uint32_t)0x003E0000U) +#define RCC_PLL1DIV_PLL1CDIV_DIV63 ((uint32_t)0x003F0000U) + +#define RCC_PLL1DIV_PLL1BDIV ((uint32_t)0x00003F00U) /* Bit[13:8] */ +#define RCC_PLL1DIV_PLL1BDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL1DIV_PLL1BDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL1DIV_PLL1BDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL1DIV_PLL1BDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_PLL1DIV_PLL1BDIV_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_PLL1DIV_PLL1BDIV_5 ((uint32_t)0x00002000U) /* Bit13*/ + +#define RCC_PLL1DIV_PLL1BDIV_DIV1 ((uint32_t)0x00000100U) +#define RCC_PLL1DIV_PLL1BDIV_DIV2 ((uint32_t)0x00000200U) +#define RCC_PLL1DIV_PLL1BDIV_DIV3 ((uint32_t)0x00000300U) +#define RCC_PLL1DIV_PLL1BDIV_DIV4 ((uint32_t)0x00000400U) +#define RCC_PLL1DIV_PLL1BDIV_DIV5 ((uint32_t)0x00000500U) +#define RCC_PLL1DIV_PLL1BDIV_DIV6 ((uint32_t)0x00000600U) +#define RCC_PLL1DIV_PLL1BDIV_DIV7 ((uint32_t)0x00000700U) +#define RCC_PLL1DIV_PLL1BDIV_DIV8 ((uint32_t)0x00000800U) +#define RCC_PLL1DIV_PLL1BDIV_DIV9 ((uint32_t)0x00000900U) +#define RCC_PLL1DIV_PLL1BDIV_DIV10 ((uint32_t)0x00000A00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV11 ((uint32_t)0x00000B00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV12 ((uint32_t)0x00000C00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV13 ((uint32_t)0x00000D00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV14 ((uint32_t)0x00000E00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV15 ((uint32_t)0x00000F00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV16 ((uint32_t)0x00001000U) +#define RCC_PLL1DIV_PLL1BDIV_DIV17 ((uint32_t)0x00001100U) +#define RCC_PLL1DIV_PLL1BDIV_DIV18 ((uint32_t)0x00001200U) +#define RCC_PLL1DIV_PLL1BDIV_DIV19 ((uint32_t)0x00001300U) +#define RCC_PLL1DIV_PLL1BDIV_DIV20 ((uint32_t)0x00001400U) +#define RCC_PLL1DIV_PLL1BDIV_DIV21 ((uint32_t)0x00001500U) +#define RCC_PLL1DIV_PLL1BDIV_DIV22 ((uint32_t)0x00001600U) +#define RCC_PLL1DIV_PLL1BDIV_DIV23 ((uint32_t)0x00001700U) +#define RCC_PLL1DIV_PLL1BDIV_DIV24 ((uint32_t)0x00001800U) +#define RCC_PLL1DIV_PLL1BDIV_DIV25 ((uint32_t)0x00001900U) +#define RCC_PLL1DIV_PLL1BDIV_DIV26 ((uint32_t)0x00001A00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV27 ((uint32_t)0x00001B00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV28 ((uint32_t)0x00001C00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV29 ((uint32_t)0x00001D00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV30 ((uint32_t)0x00001E00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV31 ((uint32_t)0x00001F00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV32 ((uint32_t)0x00002000U) +#define RCC_PLL1DIV_PLL1BDIV_DIV33 ((uint32_t)0x00002100U) +#define RCC_PLL1DIV_PLL1BDIV_DIV34 ((uint32_t)0x00002200U) +#define RCC_PLL1DIV_PLL1BDIV_DIV35 ((uint32_t)0x00002300U) +#define RCC_PLL1DIV_PLL1BDIV_DIV36 ((uint32_t)0x00002400U) +#define RCC_PLL1DIV_PLL1BDIV_DIV37 ((uint32_t)0x00002500U) +#define RCC_PLL1DIV_PLL1BDIV_DIV38 ((uint32_t)0x00002600U) +#define RCC_PLL1DIV_PLL1BDIV_DIV39 ((uint32_t)0x00002700U) +#define RCC_PLL1DIV_PLL1BDIV_DIV40 ((uint32_t)0x00002800U) +#define RCC_PLL1DIV_PLL1BDIV_DIV41 ((uint32_t)0x00002900U) +#define RCC_PLL1DIV_PLL1BDIV_DIV42 ((uint32_t)0x00002A00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV43 ((uint32_t)0x00002B00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV44 ((uint32_t)0x00002C00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV45 ((uint32_t)0x00002D00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV46 ((uint32_t)0x00002E00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV47 ((uint32_t)0x00002F00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV48 ((uint32_t)0x00003000U) +#define RCC_PLL1DIV_PLL1BDIV_DIV49 ((uint32_t)0x00003100U) +#define RCC_PLL1DIV_PLL1BDIV_DIV50 ((uint32_t)0x00003200U) +#define RCC_PLL1DIV_PLL1BDIV_DIV51 ((uint32_t)0x00003300U) +#define RCC_PLL1DIV_PLL1BDIV_DIV52 ((uint32_t)0x00003400U) +#define RCC_PLL1DIV_PLL1BDIV_DIV53 ((uint32_t)0x00003500U) +#define RCC_PLL1DIV_PLL1BDIV_DIV54 ((uint32_t)0x00003600U) +#define RCC_PLL1DIV_PLL1BDIV_DIV55 ((uint32_t)0x00003700U) +#define RCC_PLL1DIV_PLL1BDIV_DIV56 ((uint32_t)0x00003800U) +#define RCC_PLL1DIV_PLL1BDIV_DIV57 ((uint32_t)0x00003900U) +#define RCC_PLL1DIV_PLL1BDIV_DIV58 ((uint32_t)0x00003A00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV59 ((uint32_t)0x00003B00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV60 ((uint32_t)0x00003C00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV61 ((uint32_t)0x00003D00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV62 ((uint32_t)0x00003E00U) +#define RCC_PLL1DIV_PLL1BDIV_DIV63 ((uint32_t)0x00003F00U) + +#define RCC_PLL1DIV_PLL1ADIV ((uint32_t)0x0000003FU) /* Bit */ +#define RCC_PLL1DIV_PLL1ADIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL1DIV_PLL1ADIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL1DIV_PLL1ADIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL1DIV_PLL1ADIV_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL1DIV_PLL1ADIV_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL1DIV_PLL1ADIV_5 ((uint32_t)0x00000020U) /* Bit5*/ + +#define RCC_PLL1DIV_PLL1ADIV_DIV1 ((uint32_t)0x00000001U) +#define RCC_PLL1DIV_PLL1ADIV_DIV2 ((uint32_t)0x00000002U) +#define RCC_PLL1DIV_PLL1ADIV_DIV3 ((uint32_t)0x00000003U) +#define RCC_PLL1DIV_PLL1ADIV_DIV4 ((uint32_t)0x00000004U) +#define RCC_PLL1DIV_PLL1ADIV_DIV5 ((uint32_t)0x00000005U) +#define RCC_PLL1DIV_PLL1ADIV_DIV6 ((uint32_t)0x00000006U) +#define RCC_PLL1DIV_PLL1ADIV_DIV7 ((uint32_t)0x00000007U) +#define RCC_PLL1DIV_PLL1ADIV_DIV8 ((uint32_t)0x00000008U) +#define RCC_PLL1DIV_PLL1ADIV_DIV9 ((uint32_t)0x00000009U) +#define RCC_PLL1DIV_PLL1ADIV_DIV10 ((uint32_t)0x0000000AU) +#define RCC_PLL1DIV_PLL1ADIV_DIV11 ((uint32_t)0x0000000BU) +#define RCC_PLL1DIV_PLL1ADIV_DIV12 ((uint32_t)0x0000000CU) +#define RCC_PLL1DIV_PLL1ADIV_DIV13 ((uint32_t)0x0000000DU) +#define RCC_PLL1DIV_PLL1ADIV_DIV14 ((uint32_t)0x0000000EU) +#define RCC_PLL1DIV_PLL1ADIV_DIV15 ((uint32_t)0x0000000FU) +#define RCC_PLL1DIV_PLL1ADIV_DIV16 ((uint32_t)0x00000010U) +#define RCC_PLL1DIV_PLL1ADIV_DIV17 ((uint32_t)0x00000011U) +#define RCC_PLL1DIV_PLL1ADIV_DIV18 ((uint32_t)0x00000012U) +#define RCC_PLL1DIV_PLL1ADIV_DIV19 ((uint32_t)0x00000013U) +#define RCC_PLL1DIV_PLL1ADIV_DIV20 ((uint32_t)0x00000014U) +#define RCC_PLL1DIV_PLL1ADIV_DIV21 ((uint32_t)0x00000015U) +#define RCC_PLL1DIV_PLL1ADIV_DIV22 ((uint32_t)0x00000016U) +#define RCC_PLL1DIV_PLL1ADIV_DIV23 ((uint32_t)0x00000017U) +#define RCC_PLL1DIV_PLL1ADIV_DIV24 ((uint32_t)0x00000018U) +#define RCC_PLL1DIV_PLL1ADIV_DIV25 ((uint32_t)0x00000019U) +#define RCC_PLL1DIV_PLL1ADIV_DIV26 ((uint32_t)0x0000001AU) +#define RCC_PLL1DIV_PLL1ADIV_DIV27 ((uint32_t)0x0000001BU) +#define RCC_PLL1DIV_PLL1ADIV_DIV28 ((uint32_t)0x0000001CU) +#define RCC_PLL1DIV_PLL1ADIV_DIV29 ((uint32_t)0x0000001DU) +#define RCC_PLL1DIV_PLL1ADIV_DIV30 ((uint32_t)0x0000001EU) +#define RCC_PLL1DIV_PLL1ADIV_DIV31 ((uint32_t)0x0000001FU) +#define RCC_PLL1DIV_PLL1ADIV_DIV32 ((uint32_t)0x00000020U) +#define RCC_PLL1DIV_PLL1ADIV_DIV33 ((uint32_t)0x00000021U) +#define RCC_PLL1DIV_PLL1ADIV_DIV34 ((uint32_t)0x00000022U) +#define RCC_PLL1DIV_PLL1ADIV_DIV35 ((uint32_t)0x00000023U) +#define RCC_PLL1DIV_PLL1ADIV_DIV36 ((uint32_t)0x00000024U) +#define RCC_PLL1DIV_PLL1ADIV_DIV37 ((uint32_t)0x00000025U) +#define RCC_PLL1DIV_PLL1ADIV_DIV38 ((uint32_t)0x00000026U) +#define RCC_PLL1DIV_PLL1ADIV_DIV39 ((uint32_t)0x00000027U) +#define RCC_PLL1DIV_PLL1ADIV_DIV40 ((uint32_t)0x00000028U) +#define RCC_PLL1DIV_PLL1ADIV_DIV41 ((uint32_t)0x00000029U) +#define RCC_PLL1DIV_PLL1ADIV_DIV42 ((uint32_t)0x0000002AU) +#define RCC_PLL1DIV_PLL1ADIV_DIV43 ((uint32_t)0x0000002BU) +#define RCC_PLL1DIV_PLL1ADIV_DIV44 ((uint32_t)0x0000002CU) +#define RCC_PLL1DIV_PLL1ADIV_DIV45 ((uint32_t)0x0000002DU) +#define RCC_PLL1DIV_PLL1ADIV_DIV46 ((uint32_t)0x0000002EU) +#define RCC_PLL1DIV_PLL1ADIV_DIV47 ((uint32_t)0x0000002FU) +#define RCC_PLL1DIV_PLL1ADIV_DIV48 ((uint32_t)0x00000030U) +#define RCC_PLL1DIV_PLL1ADIV_DIV49 ((uint32_t)0x00000031U) +#define RCC_PLL1DIV_PLL1ADIV_DIV50 ((uint32_t)0x00000032U) +#define RCC_PLL1DIV_PLL1ADIV_DIV51 ((uint32_t)0x00000033U) +#define RCC_PLL1DIV_PLL1ADIV_DIV52 ((uint32_t)0x00000034U) +#define RCC_PLL1DIV_PLL1ADIV_DIV53 ((uint32_t)0x00000035U) +#define RCC_PLL1DIV_PLL1ADIV_DIV54 ((uint32_t)0x00000036U) +#define RCC_PLL1DIV_PLL1ADIV_DIV55 ((uint32_t)0x00000037U) +#define RCC_PLL1DIV_PLL1ADIV_DIV56 ((uint32_t)0x00000038U) +#define RCC_PLL1DIV_PLL1ADIV_DIV57 ((uint32_t)0x00000039U) +#define RCC_PLL1DIV_PLL1ADIV_DIV58 ((uint32_t)0x0000003AU) +#define RCC_PLL1DIV_PLL1ADIV_DIV59 ((uint32_t)0x0000003BU) +#define RCC_PLL1DIV_PLL1ADIV_DIV60 ((uint32_t)0x0000003CU) +#define RCC_PLL1DIV_PLL1ADIV_DIV61 ((uint32_t)0x0000003DU) +#define RCC_PLL1DIV_PLL1ADIV_DIV62 ((uint32_t)0x0000003EU) +#define RCC_PLL1DIV_PLL1ADIV_DIV63 ((uint32_t)0x0000003FU) + + +/******** Bit definition for RCC_PLL2DIV register ********/ +#define RCC_PLL2DIV_PLL2CDIV ((uint32_t)0x003F0000U) /* Bit[21:16] */ +#define RCC_PLL2DIV_PLL2CDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_PLL2DIV_PLL2CDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_PLL2DIV_PLL2CDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_PLL2DIV_PLL2CDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_PLL2DIV_PLL2CDIV_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_PLL2DIV_PLL2CDIV_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_PLL2DIV_PLL2BDIV ((uint32_t)0x00003F00U) /* Bit[13:8] */ +#define RCC_PLL2DIV_PLL2BDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL2DIV_PLL2BDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL2DIV_PLL2BDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL2DIV_PLL2BDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_PLL2DIV_PLL2BDIV_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_PLL2DIV_PLL2BDIV_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_PLL2DIV_PLL2ADIV ((uint32_t)0x0000003FU) /* Bit */ +#define RCC_PLL2DIV_PLL2ADIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL2DIV_PLL2ADIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL2DIV_PLL2ADIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL2DIV_PLL2ADIV_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL2DIV_PLL2ADIV_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL2DIV_PLL2ADIV_5 ((uint32_t)0x00000020U) /* Bit5*/ + +/******** Bit definition for RCC_PLL3DIV register ********/ +#define RCC_PLL3DIV_PLL3CDIV ((uint32_t)0x003F0000U) /* Bit[21:16] */ +#define RCC_PLL3DIV_PLL3CDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_PLL3DIV_PLL3CDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_PLL3DIV_PLL3CDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_PLL3DIV_PLL3CDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_PLL3DIV_PLL3CDIV_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_PLL3DIV_PLL3CDIV_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_PLL3DIV_PLL3BDIV ((uint32_t)0x00003F00U) /* Bit[13:8] */ +#define RCC_PLL3DIV_PLL3BDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_PLL3DIV_PLL3BDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_PLL3DIV_PLL3BDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_PLL3DIV_PLL3BDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_PLL3DIV_PLL3BDIV_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_PLL3DIV_PLL3BDIV_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_PLL3DIV_PLL3ADIV ((uint32_t)0x0000003FU) /* Bit */ +#define RCC_PLL3DIV_PLL3ADIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_PLL3DIV_PLL3ADIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_PLL3DIV_PLL3ADIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_PLL3DIV_PLL3ADIV_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_PLL3DIV_PLL3ADIV_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_PLL3DIV_PLL3ADIV_5 ((uint32_t)0x00000020U) /* Bit5*/ + +/******** Bit definition for RCC_SYSBUSDIV1 register ********/ +#define RCC_SYSBUSDIV1_AXIHYPDIV ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define RCC_SYSBUSDIV1_AXIHYPDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_SYSBUSDIV1_AXIHYPDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_SYSBUSDIV1_AXIHYPDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_SYSBUSDIV1_AXIHYPDIV_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV2 ((uint32_t)0x01000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV4 ((uint32_t)0x02000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV8 ((uint32_t)0x04000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV16 ((uint32_t)0x07000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV32 ((uint32_t)0x08000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV64 ((uint32_t)0x09000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV128 ((uint32_t)0x0A000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV256 ((uint32_t)0x0B000000U) +#define RCC_SYSBUSDIV1_AXIHYPDIV_DIV512 ((uint32_t)0x0C000000U) + +#define RCC_SYSBUSDIV1_HSIDIV ((uint32_t)0x00F00000U) /* Bit[23:20] */ +#define RCC_SYSBUSDIV1_HSIDIV_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_SYSBUSDIV1_HSIDIV_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_SYSBUSDIV1_HSIDIV_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_SYSBUSDIV1_HSIDIV_3 ((uint32_t)0x00800000U) /* Bit23*/ + +#define RCC_SYSBUSDIV1_HSIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV2 ((uint32_t)0x00100000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV4 ((uint32_t)0x00200000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV8 ((uint32_t)0x00400000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV16 ((uint32_t)0x00700000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV32 ((uint32_t)0x00800000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV64 ((uint32_t)0x00900000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV128 ((uint32_t)0x00A00000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV256 ((uint32_t)0x00B00000U) +#define RCC_SYSBUSDIV1_HSIDIV_DIV512 ((uint32_t)0x00C00000U) + +#define RCC_SYSBUSDIV1_M7HYPDIV ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define RCC_SYSBUSDIV1_M7HYPDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_SYSBUSDIV1_M7HYPDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_SYSBUSDIV1_M7HYPDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_SYSBUSDIV1_M7HYPDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV2 ((uint32_t)0x00010000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV4 ((uint32_t)0x00020000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV8 ((uint32_t)0x00040000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV16 ((uint32_t)0x00070000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV32 ((uint32_t)0x00080000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV64 ((uint32_t)0x00090000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV128 ((uint32_t)0x000A0000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV256 ((uint32_t)0x000B0000U) +#define RCC_SYSBUSDIV1_M7HYPDIV_DIV512 ((uint32_t)0x000C0000U) + +#define RCC_SYSBUSDIV1_AXIDIV ((uint32_t)0x0000F000U) /* Bit[15:12] */ +#define RCC_SYSBUSDIV1_AXIDIV_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_SYSBUSDIV1_AXIDIV_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_SYSBUSDIV1_AXIDIV_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_SYSBUSDIV1_AXIDIV_3 ((uint32_t)0x00008000U) /* Bit15*/ + +#define RCC_SYSBUSDIV1_AXIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV2 ((uint32_t)0x00001000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV4 ((uint32_t)0x00002000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV8 ((uint32_t)0x00004000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV16 ((uint32_t)0x00007000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV32 ((uint32_t)0x00008000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV64 ((uint32_t)0x00009000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV128 ((uint32_t)0x0000A000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV256 ((uint32_t)0x0000B000U) +#define RCC_SYSBUSDIV1_AXIDIV_DIV512 ((uint32_t)0x0000C000U) + +#define RCC_SYSBUSDIV1_BUSDIV ((uint32_t)0x00000F00U) /* Bit[11:8] */ +#define RCC_SYSBUSDIV1_BUSDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_SYSBUSDIV1_BUSDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_SYSBUSDIV1_BUSDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_SYSBUSDIV1_BUSDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define RCC_SYSBUSDIV1_BUSDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV2 ((uint32_t)0x00000100U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV4 ((uint32_t)0x00000200U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV8 ((uint32_t)0x00000400U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV16 ((uint32_t)0x00000700U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV32 ((uint32_t)0x00000800U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV64 ((uint32_t)0x00000900U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV128 ((uint32_t)0x00000A00U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV256 ((uint32_t)0x00000B00U) +#define RCC_SYSBUSDIV1_BUSDIV_DIV512 ((uint32_t)0x00000C00U) + +#define RCC_SYSBUSDIV1_MSIDIV ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define RCC_SYSBUSDIV1_MSIDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_SYSBUSDIV1_MSIDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_SYSBUSDIV1_MSIDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_SYSBUSDIV1_MSIDIV_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define RCC_SYSBUSDIV1_MSIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV2 ((uint32_t)0x00000010U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV4 ((uint32_t)0x00000020U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV8 ((uint32_t)0x00000040U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV16 ((uint32_t)0x00000070U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV32 ((uint32_t)0x00000080U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV64 ((uint32_t)0x00000090U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV128 ((uint32_t)0x000000A0U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV256 ((uint32_t)0x000000B0U) +#define RCC_SYSBUSDIV1_MSIDIV_DIV512 ((uint32_t)0x000000C0U) + +#define RCC_SYSBUSDIV1_SCLKDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_SYSBUSDIV1_SCLKDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_SYSBUSDIV1_SCLKDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_SYSBUSDIV1_SCLKDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_SYSBUSDIV1_SCLKDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +#define RCC_SYSBUSDIV1_SCLKDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV2 ((uint32_t)0x00000001U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV4 ((uint32_t)0x00000002U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV8 ((uint32_t)0x00000004U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV16 ((uint32_t)0x00000007U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV32 ((uint32_t)0x00000008U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV64 ((uint32_t)0x00000009U) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV128 ((uint32_t)0x0000000AU) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV256 ((uint32_t)0x0000000BU) +#define RCC_SYSBUSDIV1_SCLKDIV_DIV512 ((uint32_t)0x0000000CU) + +/******** Bit definition for RCC_SYSBUSDIV2 register ********/ +#define RCC_SYSBUSDIV2_APB6DIV ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_SYSBUSDIV2_APB6DIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_SYSBUSDIV2_APB6DIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_SYSBUSDIV2_APB6DIV_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define RCC_SYSBUSDIV2_APB6DIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV2_APB6DIV_DIV2 ((uint32_t)0x04000000U) +#define RCC_SYSBUSDIV2_APB6DIV_DIV4 ((uint32_t)0x05000000U) +#define RCC_SYSBUSDIV2_APB6DIV_DIV8 ((uint32_t)0x06000000U) +#define RCC_SYSBUSDIV2_APB6DIV_DIV16 ((uint32_t)0x07000000U) + +#define RCC_SYSBUSDIV2_APB5DIV ((uint32_t)0x00070000U) /* Bit[18:16] */ +#define RCC_SYSBUSDIV2_APB5DIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_SYSBUSDIV2_APB5DIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_SYSBUSDIV2_APB5DIV_2 ((uint32_t)0x00040000U) /* Bit18*/ + +#define RCC_SYSBUSDIV2_APB5DIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV2_APB5DIV_DIV2 ((uint32_t)0x00040000U) +#define RCC_SYSBUSDIV2_APB5DIV_DIV4 ((uint32_t)0x00050000U) +#define RCC_SYSBUSDIV2_APB5DIV_DIV8 ((uint32_t)0x00060000U) +#define RCC_SYSBUSDIV2_APB5DIV_DIV16 ((uint32_t)0x00070000U) + +#define RCC_SYSBUSDIV2_APB2DIV ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_SYSBUSDIV2_APB2DIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_SYSBUSDIV2_APB2DIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_SYSBUSDIV2_APB2DIV_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define RCC_SYSBUSDIV2_APB2DIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV2_APB2DIV_DIV2 ((uint32_t)0x00000400U) +#define RCC_SYSBUSDIV2_APB2DIV_DIV4 ((uint32_t)0x00000500U) +#define RCC_SYSBUSDIV2_APB2DIV_DIV8 ((uint32_t)0x00000600U) +#define RCC_SYSBUSDIV2_APB2DIV_DIV16 ((uint32_t)0x00000700U) + +#define RCC_SYSBUSDIV2_APB1DIV ((uint32_t)0x00000007U) /* Bit */ +#define RCC_SYSBUSDIV2_APB1DIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_SYSBUSDIV2_APB1DIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_SYSBUSDIV2_APB1DIV_2 ((uint32_t)0x00000004U) /* Bit2*/ + +#define RCC_SYSBUSDIV2_APB1DIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_SYSBUSDIV2_APB1DIV_DIV2 ((uint32_t)0x00000004U) +#define RCC_SYSBUSDIV2_APB1DIV_DIV4 ((uint32_t)0x00000005U) +#define RCC_SYSBUSDIV2_APB1DIV_DIV8 ((uint32_t)0x00000006U) +#define RCC_SYSBUSDIV2_APB1DIV_DIV16 ((uint32_t)0x00000007U) + +/******** Bit definition for RCC_BOOTMODE register ********/ +#define RCC_BOOTMODE_MODE ((uint32_t)0xFFFFFFFFU) /* Bit */ +#define RCC_BOOTMODE_MODE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_BOOTMODE_MODE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_BOOTMODE_MODE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_BOOTMODE_MODE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_BOOTMODE_MODE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_BOOTMODE_MODE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_BOOTMODE_MODE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_BOOTMODE_MODE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_BOOTMODE_MODE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_BOOTMODE_MODE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_BOOTMODE_MODE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_BOOTMODE_MODE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_BOOTMODE_MODE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_BOOTMODE_MODE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_BOOTMODE_MODE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_BOOTMODE_MODE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_BOOTMODE_MODE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_BOOTMODE_MODE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_BOOTMODE_MODE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_BOOTMODE_MODE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_BOOTMODE_MODE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_BOOTMODE_MODE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_BOOTMODE_MODE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_BOOTMODE_MODE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_BOOTMODE_MODE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_BOOTMODE_MODE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_BOOTMODE_MODE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_BOOTMODE_MODE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_BOOTMODE_MODE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_BOOTMODE_MODE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_BOOTMODE_MODE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_BOOTMODE_MODE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for RCC_AHB1DIV1 register ********/ +#define RCC_AHB1DIV1_ETH2SYSDIV ((uint32_t)0xF0000000U) /* Bit[31:28] */ +#define RCC_AHB1DIV1_ETH2SYSDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_AHB1DIV1_ETH2SYSDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_AHB1DIV1_ETH2SYSDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_AHB1DIV1_ETH2SYSDIV_3 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_AHB1DIV1_SDMMC2SYSDIV ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define RCC_AHB1DIV1_SDMMC2SYSDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_AHB1DIV1_SDMMC2SYSDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_AHB1DIV1_SDMMC2SYSDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_AHB1DIV1_SDMMC2SYSDIV_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV2 ((uint32_t)0x01000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV4 ((uint32_t)0x02000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV8 ((uint32_t)0x04000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV16 ((uint32_t)0x07000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV32 ((uint32_t)0x08000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV64 ((uint32_t)0x09000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV128 ((uint32_t)0x0A000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV256 ((uint32_t)0x0B000000U) +#define RCC_AHB1DIV1_SDMMC2SYSDIV_DIV512 ((uint32_t)0x0C000000U) +/******** Bit definition for RCC_AHB1DIV2 register ********/ +#define RCC_AHB1DIV2_ADC3SYSDIV ((uint32_t)0x003F0000U) /* Bit[21:16] */ +#define RCC_AHB1DIV2_ADC3SYSDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_AHB1DIV2_ADC3SYSDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_AHB1DIV2_ADC3SYSDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_AHB1DIV2_ADC3SYSDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_AHB1DIV2_ADC3SYSDIV_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_AHB1DIV2_ADC3SYSDIV_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_AHB1DIV2_ADC2SYSDIV ((uint32_t)0x00003F00U) /* Bit[13:8] */ +#define RCC_AHB1DIV2_ADC2SYSDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_AHB1DIV2_ADC2SYSDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_AHB1DIV2_ADC2SYSDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_AHB1DIV2_ADC2SYSDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_AHB1DIV2_ADC2SYSDIV_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_AHB1DIV2_ADC2SYSDIV_5 ((uint32_t)0x00002000U) /* Bit13*/ + +#define RCC_AHB1DIV2_ADC1SYSDIV ((uint32_t)0x0000003FU) /* Bit */ +#define RCC_AHB1DIV2_ADC1SYSDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AHB1DIV2_ADC1SYSDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AHB1DIV2_ADC1SYSDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_AHB1DIV2_ADC1SYSDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_AHB1DIV2_ADC1SYSDIV_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_AHB1DIV2_ADC1SYSDIV_5 ((uint32_t)0x00000020U) /* Bit5*/ + +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV1 ((uint32_t)0x00000001U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV2 ((uint32_t)0x00000002U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV3 ((uint32_t)0x00000003U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV4 ((uint32_t)0x00000004U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV5 ((uint32_t)0x00000005U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV6 ((uint32_t)0x00000006U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV7 ((uint32_t)0x00000007U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV8 ((uint32_t)0x00000008U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV9 ((uint32_t)0x00000009U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV10 ((uint32_t)0x0000000AU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV11 ((uint32_t)0x0000000BU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV12 ((uint32_t)0x0000000CU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV13 ((uint32_t)0x0000000DU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV14 ((uint32_t)0x0000000EU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV15 ((uint32_t)0x0000000FU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV16 ((uint32_t)0x00000010U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV17 ((uint32_t)0x00000011U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV18 ((uint32_t)0x00000012U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV19 ((uint32_t)0x00000013U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV20 ((uint32_t)0x00000014U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV21 ((uint32_t)0x00000015U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV22 ((uint32_t)0x00000016U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV23 ((uint32_t)0x00000017U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV24 ((uint32_t)0x00000018U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV25 ((uint32_t)0x00000019U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV26 ((uint32_t)0x0000001AU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV27 ((uint32_t)0x0000001BU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV28 ((uint32_t)0x0000001CU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV29 ((uint32_t)0x0000001DU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV30 ((uint32_t)0x0000001EU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV31 ((uint32_t)0x0000001FU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV32 ((uint32_t)0x00000020U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV33 ((uint32_t)0x00000021U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV34 ((uint32_t)0x00000022U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV35 ((uint32_t)0x00000023U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV36 ((uint32_t)0x00000024U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV37 ((uint32_t)0x00000025U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV38 ((uint32_t)0x00000026U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV39 ((uint32_t)0x00000027U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV40 ((uint32_t)0x00000028U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV41 ((uint32_t)0x00000029U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV42 ((uint32_t)0x0000002AU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV43 ((uint32_t)0x0000002BU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV44 ((uint32_t)0x0000002CU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV45 ((uint32_t)0x0000002DU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV46 ((uint32_t)0x0000002EU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV47 ((uint32_t)0x0000002FU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV48 ((uint32_t)0x00000030U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV49 ((uint32_t)0x00000031U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV50 ((uint32_t)0x00000032U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV51 ((uint32_t)0x00000033U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV52 ((uint32_t)0x00000034U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV53 ((uint32_t)0x00000035U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV54 ((uint32_t)0x00000036U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV55 ((uint32_t)0x00000037U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV56 ((uint32_t)0x00000038U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV57 ((uint32_t)0x00000039U) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV58 ((uint32_t)0x0000003AU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV59 ((uint32_t)0x0000003BU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV60 ((uint32_t)0x0000003CU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV61 ((uint32_t)0x0000003DU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV62 ((uint32_t)0x0000003EU) +#define RCC_AHB1DIV2_ADC1SYSDIV_DIV63 ((uint32_t)0x0000003FU) +/******** Bit definition for RCC_AHB1SEL1 register ********/ +#define RCC_AHB1SEL1_ETH2PTPSEL ((uint32_t)0x00300000U) /* Bit[21:20] */ +#define RCC_AHB1SEL1_ETH2PTPSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_AHB1SEL1_ETH2PTPSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_AHB1SEL1_SDMMC2KERSEL ((uint32_t)0x00007000U) /* Bit[14:12] */ +#define RCC_AHB1SEL1_SDMMC2KERSEL_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_AHB1SEL1_SDMMC2KERSEL_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_AHB1SEL1_SDMMC2KERSEL_2 ((uint32_t)0x00004000U) /* Bit14*/ + +#define RCC_AHB1SEL1_SDMMC2KERSEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_AHB1SEL1_SDMMC2KERSEL_PERIPH ((uint32_t)0x00001000U) +#define RCC_AHB1SEL1_SDMMC2KERSEL_PLL2A ((uint32_t)0x00002000U) +#define RCC_AHB1SEL1_SDMMC2KERSEL_PLL3A ((uint32_t)0x00003000U) +#define RCC_AHB1SEL1_SDMMC2KERSEL_PLL1B ((uint32_t)0x00004000U) + +#define RCC_AHB1SEL1_ADC3PLLSEL ((uint32_t)0x00000300U) /* Bit[9:8] */ +#define RCC_AHB1SEL1_ADC3PLLSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_AHB1SEL1_ADC3PLLSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_AHB1SEL1_ADC2PLLSEL ((uint32_t)0x00000030U) /* Bit[5:4] */ +#define RCC_AHB1SEL1_ADC2PLLSEL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_AHB1SEL1_ADC2PLLSEL_1 ((uint32_t)0x00000020U) /* Bit5*/ + +#define RCC_AHB1SEL1_ADC1PLLSEL ((uint32_t)0x00000003U) /* Bit */ +#define RCC_AHB1SEL1_ADC1PLLSEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AHB1SEL1_ADC1PLLSEL_1 ((uint32_t)0x00000002U) /* Bit1*/ + +#define RCC_AHB1SEL1_ADC1PLLSEL_PLL2B ((uint32_t)0x00000000U) /* Bit */ +#define RCC_AHB1SEL1_ADC1PLLSEL_PLL1B ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AHB1SEL1_ADC1PLLSEL_PLL3B ((uint32_t)0x00000002U) +#define RCC_AHB1SEL1_ADC1PLLSEL_PLL3C ((uint32_t)0x00000003U) +/******** Bit definition for RCC_AHB1EN1 register ********/ +#define RCC_AHB1EN1_M7SDMMC2EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AHB1EN1_M4SDMMC2EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AHB1EN1_M7SDMMC2LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AHB1EN1_M4SDMMC2LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB1EN1_M7USB2EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AHB1EN1_M4USB2EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB1EN1_M7USB2LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB1EN1_M4USB2LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB1EN1_M7DMAMUX1EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AHB1EN1_M4DMAMUX1EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AHB1EN1_M7DMAMUX1LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AHB1EN1_M4DMAMUX1LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB1EN1_M7ADC1PLLEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AHB1EN1_M4ADC1PLLEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AHB1EN1_M7ADC1PLLLPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AHB1EN1_M4ADC1PLLLPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB1EN1_M7ADC1SYSEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB1EN1_M4ADC1SYSEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB1EN1_M7ADC1SYSLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB1EN1_M4ADC1SYSLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB1EN1_M7ADC1BUSEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB1EN1_M4ADC1BUSEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB1EN1_M7ADC1BUSLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB1EN1_M4ADC1BUSLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1EN2 register ********/ +#define RCC_AHB1EN2_M7ETH2TXEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB1EN2_M4ETH2TXEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB1EN2_M7ETH2TXLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB1EN2_M4ETH2TXLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB1EN2_M7ETH2RXEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AHB1EN2_M4ETH2RXEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AHB1EN2_M7ETH2RXLPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AHB1EN2_M4ETH2RXLPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB1EN2_M7ETH2MACEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB1EN2_M4ETH2MACEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB1EN2_M7ETH2MACLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB1EN2_M4ETH2MACLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1EN3 register ********/ +#define RCC_AHB1EN3_M7ECCMACEN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AHB1EN3_M4ECCMACEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AHB1EN3_M7ECCMACLPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AHB1EN3_M4ECCMACLPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB1EN3_M7DMA1EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AHB1EN3_M4DMA1EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AHB1EN3_M7DMA1LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AHB1EN3_M4DMA1LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB1EN3_M7DMA2EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB1EN3_M4DMA2EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB1EN3_M7DMA2LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB1EN3_M4DMA2LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB1EN3_M7DMA3EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB1EN3_M4DMA3EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB1EN3_M7DMA3LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB1EN3_M4DMA3LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1EN4 register ********/ +#define RCC_AHB1EN4_M7ADC2PLLEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AHB1EN4_M4ADC2PLLEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AHB1EN4_M7ADC2PLLLPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AHB1EN4_M4ADC2PLLLPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB1EN4_M7ADC2SYSEN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AHB1EN4_M4ADC2SYSEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AHB1EN4_M7ADC2SYSLPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AHB1EN4_M4ADC2SYSLPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB1EN4_M7ADC2BUSEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AHB1EN4_M4ADC2BUSEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AHB1EN4_M7ADC2BUSLPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AHB1EN4_M4ADC2BUSLPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB1EN4_M7ADC3PLLEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AHB1EN4_M4ADC3PLLEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AHB1EN4_M7ADC3PLLLPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AHB1EN4_M4ADC3PLLLPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB1EN4_M7ADC3SYSEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB1EN4_M4ADC3SYSEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB1EN4_M7ADC3SYSLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB1EN4_M4ADC3SYSLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB1EN4_M7ADC3BUSEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB1EN4_M4ADC3BUSEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB1EN4_M7ADC3BUSLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB1EN4_M4ADC3BUSLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1RST1 register ********/ +#define RCC_AHB1RST1_SDMMC2RST ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AHB1RST1_SDHOST2RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB1RST1_USB2WRAPRST ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB1RST1_USB2PORRST ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB1RST1_USB2RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB1RST1_DMAMUX1RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB1RST1_ADC1RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1RST2 register ********/ +#define RCC_AHB1RST2_ETH2RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1RST3 register ********/ +#define RCC_AHB1RST3_ECCMACRST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB1RST3_DMA1RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB1RST3_DMA2RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB1RST3_DMA3RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB1RST4 register ********/ +#define RCC_AHB1RST4_ADC2RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB1RST4_ADC3RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB1DIV1 register ********/ +#define RCC_APB1DIV1_APB1USARTDIV ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB1DIV1_APB1USARTDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB1DIV1_APB1USARTDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB1DIV1_APB1USARTDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ + +#define RCC_APB1DIV1_APB1USARTDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB1DIV1_APB1USARTDIV_DIV2 ((uint32_t)0x40000000U) +#define RCC_APB1DIV1_APB1USARTDIV_DIV4 ((uint32_t)0x50000000U) +#define RCC_APB1DIV1_APB1USARTDIV_DIV8 ((uint32_t)0x60000000U) +#define RCC_APB1DIV1_APB1USARTDIV_DIV16 ((uint32_t)0x70000000U) + +#define RCC_APB1DIV1_APB1BTIMDIV ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_APB1DIV1_APB1BTIMDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_APB1DIV1_APB1BTIMDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_APB1DIV1_APB1BTIMDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define RCC_APB1DIV1_APB1BTIMDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB1DIV1_APB1BTIMDIV_DIV2 ((uint32_t)0x04000000U) +#define RCC_APB1DIV1_APB1BTIMDIV_DIV4 ((uint32_t)0x05000000U) +#define RCC_APB1DIV1_APB1BTIMDIV_DIV8 ((uint32_t)0x06000000U) +#define RCC_APB1DIV1_APB1BTIMDIV_DIV16 ((uint32_t)0x07000000U) + +#define RCC_APB1DIV1_APB1GTIMDIV ((uint32_t)0x00070000U) /* Bit[18:16] */ +#define RCC_APB1DIV1_APB1GTIMDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_APB1DIV1_APB1GTIMDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_APB1DIV1_APB1GTIMDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ + +#define RCC_APB1DIV1_APB1GTIMDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB1DIV1_APB1GTIMDIV_DIV2 ((uint32_t)0x00040000U) +#define RCC_APB1DIV1_APB1GTIMDIV_DIV4 ((uint32_t)0x00050000U) +#define RCC_APB1DIV1_APB1GTIMDIV_DIV8 ((uint32_t)0x00060000U) +#define RCC_APB1DIV1_APB1GTIMDIV_DIV16 ((uint32_t)0x00070000U) + +#define RCC_APB1DIV1_APB1I2SDIV ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_APB1DIV1_APB1I2SDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_APB1DIV1_APB1I2SDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_APB1DIV1_APB1I2SDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define RCC_APB1DIV1_APB1I2SDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB1DIV1_APB1I2SDIV_DIV2 ((uint32_t)0x00000400U) +#define RCC_APB1DIV1_APB1I2SDIV_DIV4 ((uint32_t)0x00000500U) +#define RCC_APB1DIV1_APB1I2SDIV_DIV8 ((uint32_t)0x00000600U) +#define RCC_APB1DIV1_APB1I2SDIV_DIV16 ((uint32_t)0x00000700U) + +#define RCC_APB1DIV1_APB1FDCANDIV ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_APB1DIV1_APB1FDCANDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_APB1DIV1_APB1FDCANDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_APB1DIV1_APB1FDCANDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define RCC_APB1DIV1_APB1FDCANDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB1DIV1_APB1FDCANDIV_DIV2 ((uint32_t)0x00000040U) +#define RCC_APB1DIV1_APB1FDCANDIV_DIV4 ((uint32_t)0x00000050U) +#define RCC_APB1DIV1_APB1FDCANDIV_DIV8 ((uint32_t)0x00000060U) +#define RCC_APB1DIV1_APB1FDCANDIV_DIV16 ((uint32_t)0x00000070U) + +#define RCC_APB1DIV1_APB1I2CDIV ((uint32_t)0x00000007U) /* Bit */ +#define RCC_APB1DIV1_APB1I2CDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_APB1DIV1_APB1I2CDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_APB1DIV1_APB1I2CDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ + +#define RCC_APB1DIV1_APB1I2CDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB1DIV1_APB1I2CDIV_DIV2 ((uint32_t)0x00000004U) +#define RCC_APB1DIV1_APB1I2CDIV_DIV4 ((uint32_t)0x00000005U) +#define RCC_APB1DIV1_APB1I2CDIV_DIV8 ((uint32_t)0x00000006U) +#define RCC_APB1DIV1_APB1I2CDIV_DIV16 ((uint32_t)0x00000007U) +/******** Bit definition for RCC_APB1SEL1 register ********/ +#define RCC_APB1SEL1_I2C1KERSEL ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB1SEL1_I2C1KERSEL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB1SEL1_I2C1KERSEL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB1SEL1_I2C1KERSEL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_APB1SEL1_I2C2KERSEL ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_APB1SEL1_I2C2KERSEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_APB1SEL1_I2C2KERSEL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_APB1SEL1_I2C2KERSEL_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define RCC_APB1SEL1_I2C3KERSEL ((uint32_t)0x00700000U) /* Bit[22:20] */ +#define RCC_APB1SEL1_I2C3KERSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_APB1SEL1_I2C3KERSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_APB1SEL1_I2C3KERSEL_2 ((uint32_t)0x00400000U) /* Bit22*/ + +#define RCC_APB1SEL1_I2C3KERSEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_APB1SEL1_I2C3KERSEL_PLL3C ((uint32_t)0x00100000U) +#define RCC_APB1SEL1_I2C3KERSEL_HSI ((uint32_t)0x00200000U) +#define RCC_APB1SEL1_I2C3KERSEL_MSI ((uint32_t)0x00300000U) + +#define RCC_APB1SEL1_FDCAN1KERSEL ((uint32_t)0x00070000U) /* Bit[18:16] */ +#define RCC_APB1SEL1_FDCAN1KERSEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_APB1SEL1_FDCAN1KERSEL_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_APB1SEL1_FDCAN1KERSEL_2 ((uint32_t)0x00040000U) /* Bit18*/ + +#define RCC_APB1SEL1_FDCAN2KERSEL ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_APB1SEL1_FDCAN2KERSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_APB1SEL1_FDCAN2KERSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_APB1SEL1_FDCAN2KERSEL_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define RCC_APB1SEL1_FDCAN2KERSEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_APB1SEL1_FDCAN2KERSEL_PLL1C ((uint32_t)0x00000100U) +#define RCC_APB1SEL1_FDCAN2KERSEL_PLL2C ((uint32_t)0x00000200U) +#define RCC_APB1SEL1_FDCAN2KERSEL_PLL3B ((uint32_t)0x00000300U) +#define RCC_APB1SEL1_FDCAN2KERSEL_PERIPH ((uint32_t)0x00000400U) + +#define RCC_APB1SEL1_I2S4KERSEL ((uint32_t)0x0000000CU) /* Bit[3:2] */ +#define RCC_APB1SEL1_I2S4KERSEL_0 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_APB1SEL1_I2S4KERSEL_1 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_APB1SEL1_I2S3KERSEL ((uint32_t)0x00000003U) /* Bit */ +#define RCC_APB1SEL1_I2S3KERSEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_APB1SEL1_I2S3KERSEL_1 ((uint32_t)0x00000002U) /* Bit1*/ + +/******** Bit definition for RCC_APB1SEL2 register ********/ +#define RCC_APB1SEL2_FDCAN5KERSEL ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB1SEL2_FDCAN5KERSEL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB1SEL2_FDCAN5KERSEL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB1SEL2_FDCAN5KERSEL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_APB1SEL2_FDCAN6KERSEL ((uint32_t)0x00700000U) /* Bit[22:20] */ +#define RCC_APB1SEL2_FDCAN6KERSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_APB1SEL2_FDCAN6KERSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_APB1SEL2_FDCAN6KERSEL_2 ((uint32_t)0x00400000U) /* Bit22*/ + +/******** Bit definition for RCC_APB1EN1 register ********/ +#define RCC_APB1EN1_M7BTIM1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB1EN1_M4BTIM1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB1EN1_M7BTIM1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB1EN1_M4BTIM1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1EN1_M7BTIM2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB1EN1_M4BTIM2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB1EN1_M7BTIM2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB1EN1_M4BTIM2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1EN1_M7BTIM3EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB1EN1_M4BTIM3EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB1EN1_M7BTIM3LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB1EN1_M4BTIM3LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1EN1_M7BTIM4EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB1EN1_M4BTIM4EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB1EN1_M7BTIM4LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB1EN1_M4BTIM4LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1EN1_M7GTIMB1EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB1EN1_M4GTIMB1EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB1EN1_M7GTIMB1LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB1EN1_M4GTIMB1LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB1EN1_M7GTIMB2EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB1EN1_M4GTIMB2EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB1EN1_M7GTIMB2LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB1EN1_M4GTIMB2LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB1EN1_M7GTIMB3EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB1EN1_M4GTIMB3EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB1EN1_M7GTIMB3LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB1EN1_M4GTIMB3LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB1EN1_M7GTIMA4EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB1EN1_M4GTIMA4EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_APB1EN1_M7GTIMA4LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_APB1EN1_M4GTIMA4LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB1EN2 register ********/ +#define RCC_APB1EN2_M7GTIMA5EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB1EN2_M4GTIMA5EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB1EN2_M7GTIMA5LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB1EN2_M4GTIMA5LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1EN2_M7GTIMA6EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB1EN2_M4GTIMA6EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB1EN2_M7GTIMA6LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB1EN2_M4GTIMA6LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1EN2_M7GTIMA7EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB1EN2_M4GTIMA7EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB1EN2_M7GTIMA7LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB1EN2_M4GTIMA7LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1EN2_M7SPI3EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB1EN2_M4SPI3EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB1EN2_M7SPI3LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB1EN2_M4SPI3LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1EN2_M7DAC12EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB1EN2_M4DAC12EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB1EN2_M7DAC12LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB1EN2_M4DAC12LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB1EN2_M7WWDG2EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB1EN2_M4WWDG2EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB1EN2_M7WWDG2LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB1EN2_M4WWDG2LPEN ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_APB1EN3 register ********/ +#define RCC_APB1EN3_M7USART1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB1EN3_M4USART1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB1EN3_M7USART1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB1EN3_M4USART1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1EN3_M7USART2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB1EN3_M4USART2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB1EN3_M7USART2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB1EN3_M4USART2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1EN3_M7USART3EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB1EN3_M4USART3EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB1EN3_M7USART3LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB1EN3_M4USART3LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1EN3_M7USART4EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB1EN3_M4USART4EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB1EN3_M7USART4LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB1EN3_M4USART4LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1EN3_M7UART9EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB1EN3_M4UART9EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB1EN3_M7UART9LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB1EN3_M4UART9LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB1EN3_M7UART10EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB1EN3_M4UART10EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB1EN3_M7UART10LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB1EN3_M4UART10LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB1EN3_M7UART11EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB1EN3_M4UART11EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB1EN3_M7UART11LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB1EN3_M4UART11LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB1EN3_M7UART12EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB1EN3_M4UART12EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_APB1EN3_M7UART12LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_APB1EN3_M4UART12LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB1EN4 register ********/ +#define RCC_APB1EN4_M7I2S3EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB1EN4_M4I2S3EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB1EN4_M7I2S3LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB1EN4_M4I2S3LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1EN4_M7I2S4EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB1EN4_M4I2S4EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB1EN4_M7I2S4LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB1EN4_M4I2S4LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1EN4_M7I2C1EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB1EN4_M4I2C1EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB1EN4_M7I2C1LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB1EN4_M4I2C1LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1EN4_M7I2C2EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB1EN4_M4I2C2EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB1EN4_M7I2C2LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB1EN4_M4I2C2LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1EN4_M7I2C3EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB1EN4_M4I2C3EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB1EN4_M7I2C3LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB1EN4_M4I2C3LPEN ((uint32_t)0x00001000U) /* Bit[12] */ + +/******** Bit definition for RCC_APB1EN5 register ********/ +#define RCC_APB1EN5_M7FDCAN1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB1EN5_M4FDCAN1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB1EN5_M7FDCAN1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB1EN5_M4FDCAN1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1EN5_M7FDCAN2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB1EN5_M4FDCAN2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB1EN5_M7FDCAN2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB1EN5_M4FDCAN2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1EN5_M7FDCAN5EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB1EN5_M4FDCAN5EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB1EN5_M7FDCAN5LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB1EN5_M4FDCAN5LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1EN5_M7FDCAN6EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB1EN5_M4FDCAN6EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB1EN5_M7FDCAN6LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB1EN5_M4FDCAN6LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1EN5_FDCAN1STPREQ ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB1EN5_FDCAN1STPACK ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB1EN5_FDCAN2STPREQ ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB1EN5_FDCAN2STPACK ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB1EN5_FDCAN5STPREQ ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB1EN5_FDCAN5STPACK ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB1EN5_FDCAN6STPREQ ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB1EN5_FDCAN6STPACK ((uint32_t)0x00000004U) /* Bit[2] */ + +/******** Bit definition for RCC_APB1RST1 register ********/ +#define RCC_APB1RST1_BTIM1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1RST1_BTIM2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1RST1_BTIM3RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1RST1_BTIM4RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1RST1_GTIMB1RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB1RST1_GTIMB2RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB1RST1_GTIMB3RST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB1RST1_GTIMA4RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB1RST2 register ********/ +#define RCC_APB1RST2_GTIMA5RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1RST2_GTIMA6RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1RST2_GTIMA7RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1RST2_SPI3RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1RST2_DAC12RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB1RST2_WWDG2RST ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_APB1RST3 register ********/ +#define RCC_APB1RST3_USART1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1RST3_USART2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1RST3_USART3RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1RST3_USART4RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1RST3_UART9RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB1RST3_UART10RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB1RST3_UART11RST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB1RST3_UART12RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB1RST4 register ********/ +#define RCC_APB1RST4_I2S3RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1RST4_I2S4RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1RST4_I2C1RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1RST4_I2C2RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1RST4_I2C3RST ((uint32_t)0x00001000U) /* Bit[12] */ + +/******** Bit definition for RCC_APB1RST5 register ********/ +#define RCC_APB1RST5_FDCAN1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB1RST5_FDCAN2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB1RST5_FDCAN5RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB1RST5_FDCAN6RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB1RST5_CAHIRST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB1RST5_CAHDRST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB2DIV1 register ********/ +#define RCC_AHB2DIV1_ETH1SYSDIV ((uint32_t)0xF0000000U) /* Bit[31:28] */ +#define RCC_AHB2DIV1_ETH1SYSDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_AHB2DIV1_ETH1SYSDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_AHB2DIV1_ETH1SYSDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_AHB2DIV1_ETH1SYSDIV_3 ((uint32_t)0x80000000U) /* Bit31*/ + +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV2 ((uint32_t)0x10000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV4 ((uint32_t)0x20000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV8 ((uint32_t)0x40000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV16 ((uint32_t)0x70000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV32 ((uint32_t)0x80000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV64 ((uint32_t)0x90000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV128 ((uint32_t)0xA0000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV256 ((uint32_t)0xB0000000U) +#define RCC_AHB2DIV1_ETH1SYSDIV_DIV512 ((uint32_t)0xC0000000U) + +#define RCC_AHB2DIV1_USBHSEDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_AHB2DIV1_USBHSEDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AHB2DIV1_USBHSEDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AHB2DIV1_USBHSEDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_AHB2DIV1_USBHSEDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +#define RCC_AHB2DIV1_USBHSEDIV_DIV1 ((uint32_t)0x00000000U) /* Bit */ +#define RCC_AHB2DIV1_USBHSEDIV_DIV2 ((uint32_t)0x00000001U) +/******** Bit definition for RCC_AHB2SEL1 register ********/ +#define RCC_AHB2SEL1_ETH1PTPSEL ((uint32_t)0x00300000U) /* Bit[21:20] */ +#define RCC_AHB2SEL1_ETH1PTPSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_AHB2SEL1_ETH1PTPSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ + +#define RCC_AHB2SEL1_ETH1PTPSEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_AHB2SEL1_ETH1PTPSEL_PERIPH ((uint32_t)0x00100000U) +#define RCC_AHB2SEL1_ETH1PTPSEL_PLL2C ((uint32_t)0x00200000U) +#define RCC_AHB2SEL1_ETH1PTPSEL_PLL3A ((uint32_t)0x00300000U) + +#define RCC_AHB2SEL1_ETH1GMIITXSEL ((uint32_t)0x000C0000U) /* Bit[19:18] */ +#define RCC_AHB2SEL1_ETH1GMIITXSEL_0 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_AHB2SEL1_ETH1GMIITXSEL_1 ((uint32_t)0x00080000U) /* Bit19*/ + +#define RCC_AHB2SEL1_ETH1GMIITXSEL_PLL3A ((uint32_t)0x00000000U) +#define RCC_AHB2SEL1_ETH1GMIITXSEL_PLL2B ((uint32_t)0x00040000U) +#define RCC_AHB2SEL1_ETH1GMIITXSEL_IOM ((uint32_t)0x00080000U) +#define RCC_AHB2SEL1_ETH1GMIITXSEL_PLL1C ((uint32_t)0x000C0000U) +/******** Bit definition for RCC_AHB2EN1 register ********/ +#define RCC_AHB2EN1_M7USB1EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AHB2EN1_M4USB1EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB2EN1_M7USB1LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB2EN1_M4USB1LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB2EN1_M7ECCM2EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AHB2EN1_M4ECCM2EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AHB2EN1_M7ECCM2LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AHB2EN1_M4ECCM2LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB2EN1_M7CORDICEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB2EN1_M4CORDICEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB2EN1_M7CORDICLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB2EN1_M4CORDICLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB2EN1_M7SDPUEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AHB2EN1_M4SDPUEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AHB2EN1_M7SDPULPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AHB2EN1_M4SDPULPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB2EN1_M7FMACEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB2EN1_M4FMACEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB2EN1_M7FMACLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB2EN1_M4FMACLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB2EN2 register ********/ +#define RCC_AHB2EN2_M7DAC56EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AHB2EN2_M4DAC56EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB2EN2_M7DAC56LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB2EN2_M4DAC56LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB2EN2_M7DAC34EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AHB2EN2_M4DAC34EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AHB2EN2_M7DAC34LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AHB2EN2_M4DAC34LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB2EN2_M7ETH1TXEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB2EN2_M4ETH1TXEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB2EN2_M7ETH1TXLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB2EN2_M4ETH1TXLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB2EN2_M7ETH1RXEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AHB2EN2_M4ETH1RXEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AHB2EN2_M7ETH1RXLPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AHB2EN2_M4ETH1RXLPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB2EN2_M7ETH1MACEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB2EN2_M4ETH1MACEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB2EN2_M7ETH1MACLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB2EN2_M4ETH1MACLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB2RST1 register ********/ +#define RCC_AHB2RST1_DAC56RST ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AHB2RST1_DAC34RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB2RST1_USB1WRAPRST ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB2RST1_USB1PORRST ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB2RST1_USB1RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB2RST1_ETH1RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB2RST1_ECCM2RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB2RST1_CORDICRST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB2RST1_SDPURST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB2RST1_FMACRST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB2DIV1 register ********/ +#define RCC_APB2DIV1_APB2ATIMDIV ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB2DIV1_APB2ATIMDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB2DIV1_APB2ATIMDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB2DIV1_APB2ATIMDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ + +#define RCC_APB2DIV1_APB2ATIMDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB2DIV1_APB2ATIMDIV_DIV2 ((uint32_t)0x40000000U) +#define RCC_APB2DIV1_APB2ATIMDIV_DIV4 ((uint32_t)0x50000000U) +#define RCC_APB2DIV1_APB2ATIMDIV_DIV8 ((uint32_t)0x60000000U) +#define RCC_APB2DIV1_APB2ATIMDIV_DIV16 ((uint32_t)0x70000000U) + +#define RCC_APB2DIV1_APB2GTIMDIV ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_APB2DIV1_APB2GTIMDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_APB2DIV1_APB2GTIMDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_APB2DIV1_APB2GTIMDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define RCC_APB2DIV1_APB2GTIMDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB2DIV1_APB2GTIMDIV_DIV2 ((uint32_t)0x04000000U) +#define RCC_APB2DIV1_APB2GTIMDIV_DIV4 ((uint32_t)0x05000000U) +#define RCC_APB2DIV1_APB2GTIMDIV_DIV8 ((uint32_t)0x06000000U) +#define RCC_APB2DIV1_APB2GTIMDIV_DIV16 ((uint32_t)0x07000000U) + + +#define RCC_APB2DIV1_APB2I2SDIV ((uint32_t)0x00070000U) /* Bit[18:16] */ +#define RCC_APB2DIV1_APB2I2SDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_APB2DIV1_APB2I2SDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_APB2DIV1_APB2I2SDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ + +#define RCC_APB2DIV1_APB2DSMUDIV ((uint32_t)0x00007000U) /* Bit[14:12] */ +#define RCC_APB2DIV1_APB2DSMUDIV_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_APB2DIV1_APB2DSMUDIV_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_APB2DIV1_APB2DSMUDIV_2 ((uint32_t)0x00004000U) /* Bit14*/ + +#define RCC_APB2DIV1_APB2DSMUDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB2DIV1_APB2DSMUDIV_DIV2 ((uint32_t)0x00004000U) +#define RCC_APB2DIV1_APB2DSMUDIV_DIV4 ((uint32_t)0x00005000U) +#define RCC_APB2DIV1_APB2DSMUDIV_DIV8 ((uint32_t)0x00006000U) +#define RCC_APB2DIV1_APB2DSMUDIV_DIV16 ((uint32_t)0x00007000U) + +#define RCC_APB2DIV1_APB2I2CDIV ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_APB2DIV1_APB2I2CDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_APB2DIV1_APB2I2CDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_APB2DIV1_APB2I2CDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define RCC_APB2DIV1_APB2FDCANDIV ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_APB2DIV1_APB2FDCANDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_APB2DIV1_APB2FDCANDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_APB2DIV1_APB2FDCANDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ + +/******** Bit definition for RCC_APB2SEL1 register ********/ +#define RCC_APB2SEL1_DSMUKERSEL ((uint32_t)0x00100000U) /* Bit[20] */ + +#define RCC_APB2SEL1_DSMUKERSEL_APB2 ((uint32_t)0x00000000U) +#define RCC_APB2SEL1_DSMUKERSEL_SYSBUSDIV ((uint32_t)0x00100000U) + +#define RCC_APB2SEL1_DSMUKERASEL ((uint32_t)0x00070000U) /* Bit[18:16] */ +#define RCC_APB2SEL1_DSMUKERASEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_APB2SEL1_DSMUKERASEL_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_APB2SEL1_DSMUKERASEL_2 ((uint32_t)0x00040000U) /* Bit18*/ + +#define RCC_APB2SEL1_DSMUKERASEL_APB2 ((uint32_t)0x00000000U) +#define RCC_APB2SEL1_DSMUKERASEL_PLL1B ((uint32_t)0x00010000U) +#define RCC_APB2SEL1_DSMUKERASEL_PLL2B ((uint32_t)0x00020000U) +#define RCC_APB2SEL1_DSMUKERASEL_PLL3A ((uint32_t)0x00030000U) +#define RCC_APB2SEL1_DSMUKERASEL_CKIN ((uint32_t)0x00040000U) +#define RCC_APB2SEL1_DSMUKERASEL_PERIPH ((uint32_t)0x00050000U) + +#define RCC_APB2SEL1_I2C4KERSEL ((uint32_t)0x00007000U) /* Bit[14:12] */ +#define RCC_APB2SEL1_I2C4KERSEL_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_APB2SEL1_I2C4KERSEL_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_APB2SEL1_I2C4KERSEL_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_APB2SEL1_I2C5KERSEL ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_APB2SEL1_I2C5KERSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_APB2SEL1_I2C5KERSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_APB2SEL1_I2C5KERSEL_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_APB2SEL1_I2C6KERSEL ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_APB2SEL1_I2C6KERSEL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_APB2SEL1_I2C6KERSEL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_APB2SEL1_I2C6KERSEL_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define RCC_APB2SEL1_I2S2KERSEL ((uint32_t)0x0000000CU) /* Bit[3:2] */ +#define RCC_APB2SEL1_I2S2KERSEL_0 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_APB2SEL1_I2S2KERSEL_1 ((uint32_t)0x00000008U) /* Bit3*/ + +#define RCC_APB2SEL1_I2S1KERSEL ((uint32_t)0x00000003U) /* Bit */ +#define RCC_APB2SEL1_I2S1KERSEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_APB2SEL1_I2S1KERSEL_1 ((uint32_t)0x00000002U) /* Bit1*/ + +#define RCC_APB2SEL1_I2S1KERSEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_APB2SEL1_I2S1KERSEL_PLL3B ((uint32_t)0x00000001U) +#define RCC_APB2SEL1_I2S1KERSEL_HSI ((uint32_t)0x00000002U) +#define RCC_APB2SEL1_I2S1KERSEL_CLKIN ((uint32_t)0x00000003U) +/******** Bit definition for RCC_APB2SEL2 register ********/ +#define RCC_APB2SEL2_FDCAN3KERSEL ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB2SEL2_FDCAN3KERSEL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB2SEL2_FDCAN3KERSEL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB2SEL2_FDCAN3KERSEL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_APB2SEL2_FDCAN4KERSEL ((uint32_t)0x00700000U) /* Bit[22:20] */ +#define RCC_APB2SEL2_FDCAN4KERSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_APB2SEL2_FDCAN4KERSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_APB2SEL2_FDCAN4KERSEL_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_APB2SEL2_FDCAN7KERSEL ((uint32_t)0x00007000U) /* Bit[14:12] */ +#define RCC_APB2SEL2_FDCAN7KERSEL_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_APB2SEL2_FDCAN7KERSEL_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_APB2SEL2_FDCAN7KERSEL_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_APB2SEL2_FDCAN8KERSEL ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_APB2SEL2_FDCAN8KERSEL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_APB2SEL2_FDCAN8KERSEL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_APB2SEL2_FDCAN8KERSEL_2 ((uint32_t)0x00000040U) /* Bit6*/ + +/******** Bit definition for RCC_APB2EN1 register ********/ +#define RCC_APB2EN1_M7ATIM1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB2EN1_M4ATIM1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB2EN1_M7ATIM1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB2EN1_M4ATIM1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2EN1_M7ATIM2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB2EN1_M4ATIM2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB2EN1_M7ATIM2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB2EN1_M4ATIM2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2EN1_M7GTIMA1EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB2EN1_M4GTIMA1EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB2EN1_M7GTIMA1LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB2EN1_M4GTIMA1LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2EN1_M7GTIMA2EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB2EN1_M4GTIMA2EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB2EN1_M7GTIMA2LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB2EN1_M4GTIMA2LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2EN1_M7GTIMA3EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB2EN1_M4GTIMA3EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB2EN1_M7GTIMA3LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB2EN1_M4GTIMA3LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB2EN1_M7SHRTIM1EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB2EN1_M4SHRTIM1EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB2EN1_M7SHRTIM1LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB2EN1_M4SHRTIM1LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB2EN1_M7SHRTIM2EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB2EN1_M4SHRTIM2EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB2EN1_M7SHRTIM2LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB2EN1_M4SHRTIM2LPEN ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_APB2EN2 register ********/ +#define RCC_APB2EN2_M7I2S1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB2EN2_M4I2S1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB2EN2_M7I2S1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB2EN2_M4I2S1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2EN2_M7I2S2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB2EN2_M4I2S2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB2EN2_M7I2S2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB2EN2_M4I2S2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2EN2_M7SPI1EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB2EN2_M4SPI1EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB2EN2_M7SPI1LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB2EN2_M4SPI1LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2EN2_M7SPI2EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB2EN2_M4SPI2EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB2EN2_M7SPI2LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB2EN2_M4SPI2LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2EN2_M7DSMUEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB2EN2_M4DSMUEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB2EN2_M7DSMULPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB2EN2_M4DSMULPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB2EN2_M7I2C4EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB2EN2_M4I2C4EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB2EN2_M7I2C4LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB2EN2_M4I2C4LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB2EN2_M7I2C5EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB2EN2_M4I2C5EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB2EN2_M7I2C5LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB2EN2_M4I2C5LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB2EN2_M7I2C6EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB2EN2_M4I2C6EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_APB2EN2_M7I2C6LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_APB2EN2_M4I2C6LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB2EN3 register ********/ +#define RCC_APB2EN3_M7USART5EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB2EN3_M4USART5EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB2EN3_M7USART5LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB2EN3_M4USART5LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2EN3_M7USART6EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB2EN3_M4USART6EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB2EN3_M7USART6LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB2EN3_M4USART6LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2EN3_M7USART7EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB2EN3_M4USART7EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB2EN3_M7USART7LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB2EN3_M4USART7LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2EN3_M7USART8EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB2EN3_M4USART8EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB2EN3_M7USART8LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB2EN3_M4USART8LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2EN3_M7UART13EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB2EN3_M4UART13EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB2EN3_M7UART13LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB2EN3_M4UART13LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB2EN3_M7UART14EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB2EN3_M4UART14EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB2EN3_M7UART14LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB2EN3_M4UART14LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB2EN3_M7UART15EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB2EN3_M4UART15EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB2EN3_M7UART15LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB2EN3_M4UART15LPEN ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_APB2EN4 register ********/ +#define RCC_APB2EN4_M7FDCAN3EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB2EN4_M4FDCAN3EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB2EN4_M7FDCAN3LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB2EN4_M4FDCAN3LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2EN4_M7FDCAN4EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB2EN4_M4FDCAN4EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB2EN4_M7FDCAN4LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB2EN4_M4FDCAN4LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2EN4_M7FDCAN7EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB2EN4_M4FDCAN7EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB2EN4_M7FDCAN7LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB2EN4_M4FDCAN7LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2EN4_M7FDCAN8EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB2EN4_M4FDCAN8EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB2EN4_M7FDCAN8LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB2EN4_M4FDCAN8LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2EN4_FDCAN3STPREQ ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB2EN4_FDCAN3STPACK ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB2EN4_FDCAN4STPREQ ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB2EN4_FDCAN4STPACK ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB2EN4_FDCAN7STPREQ ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB2EN4_FDCAN7STPACK ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB2EN4_FDCAN8STPREQ ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB2EN4_FDCAN8STPACK ((uint32_t)0x00000004U) /* Bit[2] */ + +/******** Bit definition for RCC_APB2RST1 register ********/ +#define RCC_APB2RST1_ATIM1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2RST1_ATIM2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2RST1_GTIMA1RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2RST1_GTIMA2RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2RST1_GTIMA3RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB2RST1_SHRTIM1RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB2RST1_SHRTIM2RST ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_APB2RST2 register ********/ +#define RCC_APB2RST2_I2S1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2RST2_I2S2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2RST2_SPI1RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2RST2_SPI2RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2RST2_DSMURST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB2RST2_I2C4RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB2RST2_I2C5RST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB2RST2_I2C6RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB2RST3 register ********/ +#define RCC_APB2RST3_USART5RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2RST3_USART6RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2RST3_USART7RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2RST3_USART8RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB2RST3_UART13RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB2RST3_UART14RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB2RST3_UART15RST ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_APB2RST4 register ********/ +#define RCC_APB2RST4_FDCAN3RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB2RST4_FDCAN4RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB2RST4_FDCAN7RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB2RST4_FDCAN8RST ((uint32_t)0x00010000U) /* Bit[16] */ + +/******** Bit definition for RCC_AHB5EN1 register ********/ +#define RCC_AHB5EN1_M7GPIOAEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AHB5EN1_M4GPIOAEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AHB5EN1_M7GPIOALPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AHB5EN1_M4GPIOALPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB5EN1_M7GPIOBEN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AHB5EN1_M4GPIOBEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AHB5EN1_M7GPIOBLPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AHB5EN1_M4GPIOBLPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB5EN1_M7GPIOCEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AHB5EN1_M4GPIOCEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB5EN1_M7GPIOCLPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB5EN1_M4GPIOCLPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB5EN1_M7GPIODEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AHB5EN1_M4GPIODEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AHB5EN1_M7GPIODLPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AHB5EN1_M4GPIODLPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB5EN1_M7GPIOEEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AHB5EN1_M4GPIOEEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AHB5EN1_M7GPIOELPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AHB5EN1_M4GPIOELPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB5EN1_M7GPIOFEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB5EN1_M4GPIOFEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB5EN1_M7GPIOFLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB5EN1_M4GPIOFLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB5EN1_M7GPIOGEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AHB5EN1_M4GPIOGEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AHB5EN1_M7GPIOGLPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AHB5EN1_M4GPIOGLPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB5EN1_M7GPIOHEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB5EN1_M4GPIOHEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB5EN1_M7GPIOHLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB5EN1_M4GPIOHLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB5EN2 register ********/ +#define RCC_AHB5EN2_M7GPIOIEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AHB5EN2_M4GPIOIEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AHB5EN2_M7GPIOILPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AHB5EN2_M4GPIOILPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB5EN2_M7GPIOJEN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AHB5EN2_M4GPIOJEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AHB5EN2_M7GPIOJLPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AHB5EN2_M4GPIOJLPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB5EN2_M7GPIOKEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AHB5EN2_M4GPIOKEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AHB5EN2_M7GPIOKLPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AHB5EN2_M4GPIOKLPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB5EN2_M7ECCM3EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AHB5EN2_M4ECCM3EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AHB5EN2_M7ECCM3LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AHB5EN2_M4ECCM3LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB5EN2_PWREN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AHB5EN2_PWRLPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AHB5EN2_M7CRCEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AHB5EN2_M4CRCEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AHB5EN2_M7CRCLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AHB5EN2_M4CRCLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB5EN2_M7SEMA4EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AHB5EN2_M4SEMA4EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AHB5EN2_M7SEMA4LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AHB5EN2_M4SEMA4LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB5EN2_M7AFIOEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB5EN2_M4AFIOEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB5EN2_M7AFIOLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB5EN2_M4AFIOLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB5RST1 register ********/ +#define RCC_AHB5RST1_GPIOARST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB5RST1_GPIOBRST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB5RST1_GPIOCRST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB5RST1_GPIODRST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB5RST1_GPIOERST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB5RST1_GPIOFRST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB5RST1_GPIOGRST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB5RST1_GPIOHRST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB5RST2 register ********/ +#define RCC_AHB5RST2_GPIOIRST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AHB5RST2_GPIOJRST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AHB5RST2_GPIOKRST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AHB5RST2_ECCM3RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AHB5RST2_PWRRST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AHB5RST2_CRCRST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AHB5RST2_SEMA4RST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AHB5RST2_AFIORST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB5DIV1 register ********/ +#define RCC_APB5DIV1_APB5ATIMDIV ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB5DIV1_APB5ATIMDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB5DIV1_APB5ATIMDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB5DIV1_APB5ATIMDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ + +#define RCC_APB5DIV1_APB5ATIMDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB5DIV1_APB5ATIMDIV_DIV2 ((uint32_t)0x40000000U) +#define RCC_APB5DIV1_APB5ATIMDIV_DIV4 ((uint32_t)0x50000000U) +#define RCC_APB5DIV1_APB5ATIMDIV_DIV8 ((uint32_t)0x60000000U) +#define RCC_APB5DIV1_APB5ATIMDIV_DIV16 ((uint32_t)0x70000000U) + +#define RCC_APB5DIV1_APB5I2CDIV ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_APB5DIV1_APB5I2CDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_APB5DIV1_APB5I2CDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_APB5DIV1_APB5I2CDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define RCC_APB5DIV1_APB5EXTIDIV ((uint32_t)0x00700000U) /* Bit[22:20] */ +#define RCC_APB5DIV1_APB5EXTIDIV_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_APB5DIV1_APB5EXTIDIV_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_APB5DIV1_APB5EXTIDIV_2 ((uint32_t)0x00400000U) /* Bit22*/ + +#define RCC_APB5DIV1_APB5EXTIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_APB5DIV1_APB5EXTIDIV_DIV2 ((uint32_t)0x00400000U) +#define RCC_APB5DIV1_APB5EXTIDIV_DIV4 ((uint32_t)0x00500000U) +#define RCC_APB5DIV1_APB5EXTIDIV_DIV8 ((uint32_t)0x00600000U) +#define RCC_APB5DIV1_APB5EXTIDIV_DIV16 ((uint32_t)0x00700000U) +/******** Bit definition for RCC_APB5SEL1 register ********/ +#define RCC_APB5SEL1_I2C7KERSEL ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_APB5SEL1_I2C7KERSEL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_APB5SEL1_I2C7KERSEL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_APB5SEL1_I2C7KERSEL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_APB5SEL1_I2C8KERSEL ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_APB5SEL1_I2C8KERSEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_APB5SEL1_I2C8KERSEL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_APB5SEL1_I2C8KERSEL_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_APB5SEL1_I2C9KERSEL ((uint32_t)0x00700000U) /* Bit[22:20] */ +#define RCC_APB5SEL1_I2C9KERSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_APB5SEL1_I2C9KERSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_APB5SEL1_I2C9KERSEL_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_APB5SEL1_I2C10KERSEL ((uint32_t)0x00070000U) /* Bit[18:16] */ +#define RCC_APB5SEL1_I2C10KERSEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_APB5SEL1_I2C10KERSEL_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_APB5SEL1_I2C10KERSEL_2 ((uint32_t)0x00040000U) /* Bit18*/ + +/******** Bit definition for RCC_APB5EN1 register ********/ +#define RCC_APB5EN1_M7ATIM3EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB5EN1_M4ATIM3EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB5EN1_M7ATIM3LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB5EN1_M4ATIM3LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB5EN1_M7ATIM4EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB5EN1_M4ATIM4EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB5EN1_M7ATIM4LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB5EN1_M4ATIM4LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB5EN1_M7AFECEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB5EN1_M4AFECEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB5EN1_M7AFECLPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB5EN1_M4AFECLPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB5EN1_M7SPI4EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB5EN1_M4SPI4EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_APB5EN1_M7SPI4LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB5EN1_M4SPI4LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB5EN1_M7SPI5EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB5EN1_M4SPI5EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB5EN1_M7SPI5LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB5EN1_M4SPI5LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB5EN1_M7SPI6EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB5EN1_M4SPI6EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_APB5EN1_M7SPI6LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB5EN1_M4SPI6LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB5EN1_M7SPI7EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB5EN1_M4SPI7EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_APB5EN1_M7SPI7LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_APB5EN1_M4SPI7LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB5EN2 register ********/ +#define RCC_APB5EN2_M7I2C7EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_APB5EN2_M4I2C7EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_APB5EN2_M7I2C7LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_APB5EN2_M4I2C7LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB5EN2_M7I2C8EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_APB5EN2_M4I2C8EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_APB5EN2_M7I2C8LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_APB5EN2_M4I2C8LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB5EN2_M7I2C9EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_APB5EN2_M4I2C9EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_APB5EN2_M7I2C9LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_APB5EN2_M4I2C9LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB5EN2_M7I2C10EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_APB5EN2_M4I2C10EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_APB5EN2_M7I2C10LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_APB5EN2_M4I2C10LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_APB5EN2_EXTIEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_APB5EN2_EXTILPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_APB5EN2_M7RTCPCLKEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_APB5EN2_M4RTCPCLKEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_APB5EN2_M7RTCPCLKLPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_APB5EN2_M4RTCPCLKLPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB5EN2_IWDG1PCLKEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_APB5EN2_IWDG1PCLKLPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_APB5EN2_IWDG2PCLKEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_APB5EN2_IWDG2PCLKLPEN ((uint32_t)0x00000002U) /* Bit[1] */ + +/******** Bit definition for RCC_APB5RST1 register ********/ +#define RCC_APB5RST1_ATIM3RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB5RST1_ATIM4RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB5RST1_AFECRST ((uint32_t)0x00100000U) +#define RCC_APB5RST1_SPI4RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_APB5RST1_SPI5RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_APB5RST1_SPI6RST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_APB5RST1_SPI7RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_APB5RST2 register ********/ +#define RCC_APB5RST2_I2C7RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_APB5RST2_I2C8RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_APB5RST2_I2C9RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_APB5RST2_I2C10RST ((uint32_t)0x00010000U) /* Bit[16] */ + +/******** Bit definition for RCC_AHB9DIV1 register ********/ +#define RCC_AHB9DIV1_ESCSYSDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_AHB9DIV1_ESCSYSDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AHB9DIV1_ESCSYSDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AHB9DIV1_ESCSYSDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_AHB9DIV1_ESCSYSDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +#define RCC_AHB9DIV1_ESCSYSDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV2 ((uint32_t)0x00000001U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV4 ((uint32_t)0x00000002U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV8 ((uint32_t)0x00000004U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV16 ((uint32_t)0x00000007U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV32 ((uint32_t)0x00000008U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV64 ((uint32_t)0x00000009U) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV128 ((uint32_t)0x0000000AU) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV256 ((uint32_t)0x0000000BU) +#define RCC_AHB9DIV1_ESCSYSDIV_DIV512 ((uint32_t)0x0000000CU) +/******** Bit definition for RCC_AHB9SEL1 register ********/ +#define RCC_AHB9SEL1_ESCKERSEL ((uint32_t)0x00000007U) /* Bit */ +#define RCC_AHB9SEL1_ESCKERSEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AHB9SEL1_ESCKERSEL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AHB9SEL1_ESCKERSEL_2 ((uint32_t)0x00000004U) /* Bit2*/ + +#define RCC_AHB9SEL1_ESCKERSEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_AHB9SEL1_ESCKERSEL_PLL2B ((uint32_t)0x00000001U) +#define RCC_AHB9SEL1_ESCKERSEL_PLL3A ((uint32_t)0x00000002U) +#define RCC_AHB9SEL1_ESCKERSEL_PLL3C ((uint32_t)0x00000003U) +#define RCC_AHB9SEL1_ESCKERSEL_PLL1B ((uint32_t)0x00000004U) +/******** Bit definition for RCC_AHB9EN1 register ********/ +#define RCC_AHB9EN1_M7ESCEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AHB9EN1_M4ESCEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AHB9EN1_M7ESCLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AHB9EN1_M4ESCLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AHB9RST1 register ********/ +#define RCC_AHB9RST1_ESCRST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_RDDIV1 register ********/ +#define RCC_RDDIV1_COMPDIV ((uint32_t)0x70000000U) /* Bit[30:28] */ +#define RCC_RDDIV1_COMPDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_RDDIV1_COMPDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_RDDIV1_COMPDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ + +#define RCC_RDDIV1_COMPDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_RDDIV1_COMPDIV_DIV2 ((uint32_t)0x40000000U) +#define RCC_RDDIV1_COMPDIV_DIV4 ((uint32_t)0x50000000U) +#define RCC_RDDIV1_COMPDIV_DIV8 ((uint32_t)0x60000000U) +#define RCC_RDDIV1_COMPDIV_DIV16 ((uint32_t)0x70000000U) + +#define RCC_RDDIV1_LPUARTDIV ((uint32_t)0x07000000U) /* Bit[26:24] */ +#define RCC_RDDIV1_LPUARTDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_RDDIV1_LPUARTDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_RDDIV1_LPUARTDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define RCC_RDDIV1_LPUARTDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_RDDIV1_LPUARTDIV_DIV2 ((uint32_t)0x04000000U) +#define RCC_RDDIV1_LPUARTDIV_DIV4 ((uint32_t)0x05000000U) +#define RCC_RDDIV1_LPUARTDIV_DIV8 ((uint32_t)0x06000000U) +#define RCC_RDDIV1_LPUARTDIV_DIV16 ((uint32_t)0x07000000U) +/******** Bit definition for RCC_RDSEL1 register ********/ +#define RCC_RDSEL1_LPTIM1SEL ((uint32_t)0xF0000000U) /* Bit[31:28] */ +#define RCC_RDSEL1_LPTIM1SEL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_RDSEL1_LPTIM1SEL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_RDSEL1_LPTIM1SEL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_RDSEL1_LPTIM1SEL_3 ((uint32_t)0x80000000U) /* Bit31*/ + +#define RCC_RDSEL1_LPTIM1SEL_APB5 ((uint32_t)0x00000000) +#define RCC_RDSEL1_LPTIM1SEL_LSI ((uint32_t)0x10000000) +#define RCC_RDSEL1_LPTIM1SEL_LSE ((uint32_t)0x20000000) +#define RCC_RDSEL1_LPTIM1SEL_HSE ((uint32_t)0x30000000) +#define RCC_RDSEL1_LPTIM1SEL_HSI ((uint32_t)0x40000000) +#define RCC_RDSEL1_LPTIM1SEL_MSI ((uint32_t)0x50000000) +#define RCC_RDSEL1_LPTIM1SEL_COMP1 ((uint32_t)0x80000000) +#define RCC_RDSEL1_LPTIM1SEL_COMP2 ((uint32_t)0x90000000) +#define RCC_RDSEL1_LPTIM1SEL_COMP3 ((uint32_t)0xA0000000) +#define RCC_RDSEL1_LPTIM1SEL_COMP4 ((uint32_t)0xB0000000) + +#define RCC_RDSEL1_LPTIM2SEL ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define RCC_RDSEL1_LPTIM2SEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_RDSEL1_LPTIM2SEL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_RDSEL1_LPTIM2SEL_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_RDSEL1_LPTIM2SEL_3 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_RDSEL1_LPTIM3SEL ((uint32_t)0x00F00000U) /* Bit[23:20] */ +#define RCC_RDSEL1_LPTIM3SEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_RDSEL1_LPTIM3SEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_RDSEL1_LPTIM3SEL_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_RDSEL1_LPTIM3SEL_3 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_RDSEL1_LPTIM4SEL ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define RCC_RDSEL1_LPTIM4SEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_RDSEL1_LPTIM4SEL_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_RDSEL1_LPTIM4SEL_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_RDSEL1_LPTIM4SEL_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_RDSEL1_LPTIM5SEL ((uint32_t)0x0000F000U) /* Bit[15:12] */ +#define RCC_RDSEL1_LPTIM5SEL_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_RDSEL1_LPTIM5SEL_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_RDSEL1_LPTIM5SEL_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_RDSEL1_LPTIM5SEL_3 ((uint32_t)0x00008000U) /* Bit15*/ + +#define RCC_RDSEL1_LPUART1SEL ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_RDSEL1_LPUART1SEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_RDSEL1_LPUART1SEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_RDSEL1_LPUART1SEL_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define RCC_RDSEL1_LPUART1SEL_SYSBUSDIV ((uint32_t)0x00000000U) +#define RCC_RDSEL1_LPUART1SEL_HSI ((uint32_t)0x00000100U) +#define RCC_RDSEL1_LPUART1SEL_LSE ((uint32_t)0x00000200U) +#define RCC_RDSEL1_LPUART1SEL_HSE ((uint32_t)0x00000300U) +#define RCC_RDSEL1_LPUART1SEL_MSI ((uint32_t)0x00000400U) + +#define RCC_RDSEL1_LPUART2SEL ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_RDSEL1_LPUART2SEL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_RDSEL1_LPUART2SEL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_RDSEL1_LPUART2SEL_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define RCC_RDSEL1_COMPSEL ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_RDCTRL1 register ********/ +#define RCC_RDCTRL1_LPTIM2FLTEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_RDCTRL1_LPTIM2FLTSEL ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_RDCTRL1_LPTIM2COMP4EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_RDCTRL1_LPTIM2COMP3EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_RDCTRL1_LPTIM2COMP2EN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_RDCTRL1_LPTIM2COMP1EN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_RDCTRL1_LPTIM2FLTDFC ((uint32_t)0x001F0000U) /* Bit[20:16] */ +#define RCC_RDCTRL1_LPTIM2FLTDFC_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_RDCTRL1_LPTIM2FLTDFC_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_RDCTRL1_LPTIM2FLTDFC_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_RDCTRL1_LPTIM2FLTDFC_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_RDCTRL1_LPTIM2FLTDFC_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_RDCTRL1_LPTIM1FLTEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_RDCTRL1_LPTIM1FLTSEL ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_RDCTRL1_LPTIM1COMP4EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_RDCTRL1_LPTIM1COMP3EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_RDCTRL1_LPTIM1COMP2EN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_RDCTRL1_LPTIM1COMP1EN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_RDCTRL1_LPTIM1FLTDFC ((uint32_t)0x0000001FU) /* Bit */ +#define RCC_RDCTRL1_LPTIM1FLTDFC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_RDCTRL1_LPTIM1FLTDFC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_RDCTRL1_LPTIM1FLTDFC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_RDCTRL1_LPTIM1FLTDFC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_RDCTRL1_LPTIM1FLTDFC_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for RCC_RDCTRL2 register ********/ +#define RCC_RDCTRL2_LPTIM4FLTEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_RDCTRL2_LPTIM4FLTSEL ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_RDCTRL2_LPTIM4COMP4EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_RDCTRL2_LPTIM4COMP3EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_RDCTRL2_LPTIM4COMP2EN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_RDCTRL2_LPTIM4COMP1EN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_RDCTRL2_LPTIM4FLTDFC ((uint32_t)0x001F0000U) /* Bit[20:16] */ +#define RCC_RDCTRL2_LPTIM4FLTDFC_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_RDCTRL2_LPTIM4FLTDFC_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_RDCTRL2_LPTIM4FLTDFC_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_RDCTRL2_LPTIM4FLTDFC_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_RDCTRL2_LPTIM4FLTDFC_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_RDCTRL2_LPTIM3FLTEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_RDCTRL2_LPTIM3FLTSEL ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_RDCTRL2_LPTIM3COMP4EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_RDCTRL2_LPTIM3COMP3EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_RDCTRL2_LPTIM3COMP2EN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_RDCTRL2_LPTIM3COMP1EN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_RDCTRL2_LPTIM3FLTDFC ((uint32_t)0x0000001FU) /* Bit */ +#define RCC_RDCTRL2_LPTIM3FLTDFC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_RDCTRL2_LPTIM3FLTDFC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_RDCTRL2_LPTIM3FLTDFC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_RDCTRL2_LPTIM3FLTDFC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_RDCTRL2_LPTIM3FLTDFC_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for RCC_RDCTRL3 register ********/ +#define RCC_RDCTRL3_LPTIM5FLTEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_RDCTRL3_LPTIM5FLTSEL ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_RDCTRL3_LPTIM5COMP4EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_RDCTRL3_LPTIM5COMP3EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_RDCTRL3_LPTIM5COMP2EN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_RDCTRL3_LPTIM5COMP1EN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_RDCTRL3_LPTIM5FLTDFC ((uint32_t)0x0000001FU) /* Bit */ +#define RCC_RDCTRL3_LPTIM5FLTDFC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_RDCTRL3_LPTIM5FLTDFC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_RDCTRL3_LPTIM5FLTDFC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_RDCTRL3_LPTIM5FLTDFC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_RDCTRL3_LPTIM5FLTDFC_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for RCC_RDEN1 register ********/ +#define RCC_RDEN1_M7LPTIM1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_RDEN1_M4LPTIM1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_RDEN1_M7LPTIM1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_RDEN1_M4LPTIM1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_RDEN1_M7LPTIM2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_RDEN1_M4LPTIM2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_RDEN1_M7LPTIM2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_RDEN1_M4LPTIM2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_RDEN1_M7LPTIM3EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_RDEN1_M4LPTIM3EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_RDEN1_M7LPTIM3LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_RDEN1_M4LPTIM3LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_RDEN1_M7LPTIM4EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_RDEN1_M4LPTIM4EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_RDEN1_M7LPTIM4LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_RDEN1_M4LPTIM4LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_RDEN1_M7LPTIM5EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_RDEN1_M4LPTIM5EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_RDEN1_M7LPTIM5LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_RDEN1_M4LPTIM5LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_RDEN1_M7LPUART1EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_RDEN1_M4LPUART1EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_RDEN1_M7LPUART1LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_RDEN1_M4LPUART1LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_RDEN1_M7LPUART2EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_RDEN1_M4LPUART2EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_RDEN1_M7LPUART2LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_RDEN1_M4LPUART2LPEN ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_RDEN2 register ********/ +#define RCC_RDEN2_M7COMPEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_RDEN2_M4COMPEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_RDEN2_M7COMPLPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_RDEN2_M4COMPLPEN ((uint32_t)0x10000000U) /* Bit[28] */ + +/******** Bit definition for RCC_RDRST1 register ********/ +#define RCC_RDRST1_LPTIM1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_RDRST1_LPTIM2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_RDRST1_LPTIM3RST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_RDRST1_LPTIM4RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_RDRST1_LPTIM5RST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_RDRST1_LPUART1RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_RDRST1_LPUART2RST ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_RDRST2 register ********/ +#define RCC_RDRST2_COMPRST ((uint32_t)0x10000000U) /* Bit[28] */ + +/******** Bit definition for RCC_BDCTRL register ********/ +#define RCC_BDCTRL_AFELSERDF ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_BDCTRL_AFELSIRDF ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_BDCTRL_LSELDOEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_BDCTRL_LSIOVREN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_BDCTRL_LSIPFACK ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_BDCTRL_LSIPFF ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_BDCTRL_LSICSSEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_BDCTRL_LSERDCNTEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_BDCTRL_RTCLSFSW ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_BDCTRL_RTCHSFSW ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_BDCTRL_LSISECRDF ((uint32_t)0x00080000U) /* Bit[19] */ + +#define RCC_BDCTRL_RTCEN ((uint32_t)0x00040000U) /* Bit[18] */ + +#define RCC_BDCTRL_RTCSEL ((uint32_t)0x00030000U) /* Bit[17:16] */ +#define RCC_BDCTRL_RTCSEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_BDCTRL_RTCSEL_1 ((uint32_t)0x00020000U) /* Bit17*/ + +#define RCC_BDCTRL_RTCSEL_LSE ((uint32_t)0x00010000U) +#define RCC_BDCTRL_RTCSEL_LSI ((uint32_t)0x00020000U) +#define RCC_BDCTRL_RTCSEL_HSEDIV ((uint32_t)0x00030000U) + +#define RCC_BDCTRL_BORRSTEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_BDCTRL_C1LPRSTEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_BDCTRL_C2LPRSTEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_BDCTRL_BDRST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_BDCTRL_BKPEMCRSTEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_BDCTRL_RETEMCRSTEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_BDCTRL_LSECSSF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_BDCTRL_LSECSSEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_BDCTRL_LSERDEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_BDCTRL_LSEBP ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_BDCTRL_LSERDF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_BDCTRL_LSEEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_BDCTRL_LSIRDEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_BDCTRL_LSISECEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_BDCTRL_LSIRDF ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_BDCTRL_LSIEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_LSICSSDL register ********/ +#define RCC_LSICSSDL_DELAY ((uint32_t)0xFFFFFFFFU) /* Bit */ +#define RCC_LSICSSDL_DELAY_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_LSICSSDL_DELAY_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_LSICSSDL_DELAY_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_LSICSSDL_DELAY_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_LSICSSDL_DELAY_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_LSICSSDL_DELAY_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_LSICSSDL_DELAY_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_LSICSSDL_DELAY_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_LSICSSDL_DELAY_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_LSICSSDL_DELAY_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_LSICSSDL_DELAY_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_LSICSSDL_DELAY_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_LSICSSDL_DELAY_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_LSICSSDL_DELAY_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_LSICSSDL_DELAY_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_LSICSSDL_DELAY_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_LSICSSDL_DELAY_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_LSICSSDL_DELAY_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_LSICSSDL_DELAY_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_LSICSSDL_DELAY_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_LSICSSDL_DELAY_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_LSICSSDL_DELAY_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_LSICSSDL_DELAY_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_LSICSSDL_DELAY_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_LSICSSDL_DELAY_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_LSICSSDL_DELAY_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_LSICSSDL_DELAY_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_LSICSSDL_DELAY_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_LSICSSDL_DELAY_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_LSICSSDL_DELAY_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_LSICSSDL_DELAY_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_LSICSSDL_DELAY_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for RCC_CTRLSTS register ********/ +#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_CTRLSTS_C1LPRSTF ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_CTRLSTS_C2LPRSTF ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_CTRLSTS_RETEMCRSTF ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CTRLSTS_BKPEMCRSTF ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_CTRLSTS_BORRSTF ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_CTRLSTS_MMURSTF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_CTRLSTS_WWDG1RSTF ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_CTRLSTS_WWDG2RSTF ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_CTRLSTS_IWDG1RSTF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_CTRLSTS_IWDG2RSTF ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_CTRLSTS_CM4SFTRSTF ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_CTRLSTS_CM7SFTRSTF ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_CLKINT1 register ********/ +#define RCC_CLKINT1_LSECSSIE ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_CLKINT1_LSECSSIF ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_CLKINT1_LSECSSIC ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_CLKINT1_HSECSSIF ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_CLKINT1_HSECSSIC ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_CLKINT1_BORIE ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_CLKINT1_BORIF ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_CLKINT1_BORIC ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_CLKINT1_PLL1RDIE ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_CLKINT1_PLL1RDIF ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_CLKINT1_PLL1RDIC ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_CLKINT1_PLL2RDIE ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_CLKINT1_PLL2RDIF ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CLKINT1_PLL2RDIC ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_CLKINT1_PLL3RDIE ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_CLKINT1_PLL3RDIF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_CLKINT1_PLL3RDIC ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_CLKINT1_SHRPLLRDIE ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_CLKINT1_SHRPLLRDIF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_CLKINT1_SHRPLLRDIC ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_CLKINT2 register ********/ +#define RCC_CLKINT2_HSERDIE ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_CLKINT2_HSERDIF ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_CLKINT2_HSERDIC ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_CLKINT2_HSIRDIE ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_CLKINT2_HSIRDIF ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_CLKINT2_HSIRDIC ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_CLKINT2_MSIRDIE ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_CLKINT2_MSIRDIF ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_CLKINT2_MSIRDIC ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_CLKINT2_LSERDIE ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_CLKINT2_LSERDIF ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_CLKINT2_LSERDIC ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_CLKINT2_LSIRDIE ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_CLKINT2_LSIRDIF ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CLKINT2_LSIRDIC ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_CLKINT2_HSICALEIE ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_CLKINT2_HSICALEIF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_CLKINT2_HSICALEIC ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_CLKINT2_MSICALEIE ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_CLKINT2_MSICALEIF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_CLKINT2_MSICALEIC ((uint32_t)0x00000010U) /* Bit[4] */ + +/******** Bit definition for RCC_CLKINT3 register ********/ +#define RCC_CLKINT3_PLL1LKFIE ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_CLKINT3_PLL1LKFIF ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_CLKINT3_PLL1LKFIC ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_CLKINT3_PLL2LKFIE ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_CLKINT3_PLL2LKFIF ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CLKINT3_PLL2LKFIC ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_CLKINT3_PLL3LKFIE ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_CLKINT3_PLL3LKFIF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_CLKINT3_PLL3LKFIC ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_CLKINT3_SHRPLLLKFIE ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_CLKINT3_SHRPLLLKFIF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_CLKINT3_SHRPLLLKFIC ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_CLKINT3_LSIFIE ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_CLKINT3_LSIFIF ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_CLKINT3_LSIFIC ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_CFG1 register ********/ +#define RCC_CFG1_WWDG2RSTDLCNT ((uint32_t)0x00F00000U) /* Bit[23:20] */ +#define RCC_CFG1_WWDG2RSTDLCNT_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_CFG1_WWDG2RSTDLCNT_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_CFG1_WWDG2RSTDLCNT_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_CFG1_WWDG2RSTDLCNT_3 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_CFG1_WWDG1RSTDLCNT ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define RCC_CFG1_WWDG1RSTDLCNT_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_CFG1_WWDG1RSTDLCNT_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_CFG1_WWDG1RSTDLCNT_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_CFG1_WWDG1RSTDLCNT_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_CFG1_WWDG2RSTEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_CFG1_WWDG1RSTEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_CFG1_M7TRACEDIV ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define RCC_CFG1_M7TRACEDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_CFG1_M7TRACEDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_CFG1_M7TRACEDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_CFG1_M7TRACEDIV_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define RCC_CFG1_M7TRACEDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_CFG1_M7TRACEDIV_DIV2 ((uint32_t)0x00000010U) +#define RCC_CFG1_M7TRACEDIV_DIV4 ((uint32_t)0x00000020U) +#define RCC_CFG1_M7TRACEDIV_DIV8 ((uint32_t)0x00000040U) +#define RCC_CFG1_M7TRACEDIV_DIV16 ((uint32_t)0x00000070U) +#define RCC_CFG1_M7TRACEDIV_DIV32 ((uint32_t)0x00000080U) +#define RCC_CFG1_M7TRACEDIV_DIV64 ((uint32_t)0x00000090U) +#define RCC_CFG1_M7TRACEDIV_DIV128 ((uint32_t)0x000000A0U) +#define RCC_CFG1_M7TRACEDIV_DIV256 ((uint32_t)0x000000B0U) +#define RCC_CFG1_M7TRACEDIV_DIV512 ((uint32_t)0x000000C0U) + +#define RCC_CFG1_M4TRACEDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_CFG1_M4TRACEDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_CFG1_M4TRACEDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_CFG1_M4TRACEDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_CFG1_M4TRACEDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for RCC_AXIDIV1 register ********/ +#define RCC_AXIDIV1_JPEGAXIDIV ((uint32_t)0xF0000000U) /* Bit[31:28] */ +#define RCC_AXIDIV1_JPEGAXIDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_AXIDIV1_JPEGAXIDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_AXIDIV1_JPEGAXIDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_AXIDIV1_JPEGAXIDIV_3 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_AXIDIV1_JPEGSGDMADIV ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define RCC_AXIDIV1_JPEGSGDMADIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_AXIDIV1_JPEGSGDMADIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_AXIDIV1_JPEGSGDMADIV_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_AXIDIV1_JPEGSGDMADIV_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define RCC_AXIDIV1_SDMMC1AXIDIV ((uint32_t)0x00F00000U) /* Bit[23:20] */ +#define RCC_AXIDIV1_SDMMC1AXIDIV_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_AXIDIV1_SDMMC1AXIDIV_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_AXIDIV1_SDMMC1AXIDIV_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_AXIDIV1_SDMMC1AXIDIV_3 ((uint32_t)0x00800000U) /* Bit23*/ + +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV2 ((uint32_t)0x00100000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV4 ((uint32_t)0x00200000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV8 ((uint32_t)0x00400000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV16 ((uint32_t)0x00700000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV32 ((uint32_t)0x00800000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV64 ((uint32_t)0x00900000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV128 ((uint32_t)0x00A00000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV256 ((uint32_t)0x00B00000U) +#define RCC_AXIDIV1_SDMMC1AXIDIV_DIV512 ((uint32_t)0x00C00000U) + +#define RCC_AXIDIV1_DSIREFDIV ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define RCC_AXIDIV1_DSIREFDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_AXIDIV1_DSIREFDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_AXIDIV1_DSIREFDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_AXIDIV1_DSIREFDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define RCC_AXIDIV1_DSIREFDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV2 ((uint32_t)0x00010000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV4 ((uint32_t)0x00020000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV8 ((uint32_t)0x00040000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV16 ((uint32_t)0x00070000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV32 ((uint32_t)0x00080000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV64 ((uint32_t)0x00090000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV128 ((uint32_t)0x000A0000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV256 ((uint32_t)0x000B0000U) +#define RCC_AXIDIV1_DSIREFDIV_DIV512 ((uint32_t)0x000C0000U) + +#define RCC_AXIDIV1_LCDCAXIDIV ((uint32_t)0x0000F000U) /* Bit[15:12] */ +#define RCC_AXIDIV1_LCDCAXIDIV_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_AXIDIV1_LCDCAXIDIV_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_AXIDIV1_LCDCAXIDIV_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_AXIDIV1_LCDCAXIDIV_3 ((uint32_t)0x00008000U) /* Bit15*/ + +#define RCC_AXIDIV1_LCDCAXIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV2 ((uint32_t)0x00001000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV4 ((uint32_t)0x00002000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV8 ((uint32_t)0x00004000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV16 ((uint32_t)0x00007000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV32 ((uint32_t)0x00008000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV64 ((uint32_t)0x00009000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV128 ((uint32_t)0x0000A000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV256 ((uint32_t)0x0000B000U) +#define RCC_AXIDIV1_LCDCAXIDIV_DIV512 ((uint32_t)0x0000C000U) + +#define RCC_AXIDIV1_DVPMAXIDIV ((uint32_t)0x00000F00U) /* Bit[11:8] */ +#define RCC_AXIDIV1_DVPMAXIDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_AXIDIV1_DVPMAXIDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_AXIDIV1_DVPMAXIDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_AXIDIV1_DVPMAXIDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define RCC_AXIDIV1_DVPMAXIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV2 ((uint32_t)0x00000100U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV4 ((uint32_t)0x00000200U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV8 ((uint32_t)0x00000400U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV16 ((uint32_t)0x00000700U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV32 ((uint32_t)0x00000800U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV64 ((uint32_t)0x00000900U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV128 ((uint32_t)0x00000A00U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV256 ((uint32_t)0x00000B00U) +#define RCC_AXIDIV1_DVPMAXIDIV_DIV512 ((uint32_t)0x00000C00U) +/******** Bit definition for RCC_AXIDIV2 register ********/ +#define RCC_AXIDIV2_DSIAXIPPIDIV ((uint32_t)0x00F00000U) /* Bit[23:20] */ +#define RCC_AXIDIV2_DSIAXIPPIDIV_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_AXIDIV2_DSIAXIPPIDIV_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_AXIDIV2_DSIAXIPPIDIV_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_AXIDIV2_DSIAXIPPIDIV_3 ((uint32_t)0x00800000U) /* Bit23*/ + +#define RCC_AXIDIV2_DSIREFULPSDIV ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define RCC_AXIDIV2_DSIREFULPSDIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_AXIDIV2_DSIREFULPSDIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_AXIDIV2_DSIREFULPSDIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_AXIDIV2_DSIREFULPSDIV_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV2 ((uint32_t)0x00010000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV4 ((uint32_t)0x00020000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV8 ((uint32_t)0x00040000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV16 ((uint32_t)0x00070000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV32 ((uint32_t)0x00080000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV64 ((uint32_t)0x00090000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV128 ((uint32_t)0x000A0000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV256 ((uint32_t)0x000B0000U) +#define RCC_AXIDIV2_DSIREFULPSDIV_DIV512 ((uint32_t)0x000C0000U) + +#define RCC_AXIDIV2_SDRAMMEMDIV ((uint32_t)0x00000F00U) /* Bit[11:8] */ +#define RCC_AXIDIV2_SDRAMMEMDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_AXIDIV2_SDRAMMEMDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_AXIDIV2_SDRAMMEMDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_AXIDIV2_SDRAMMEMDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV2 ((uint32_t)0x00000100U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV4 ((uint32_t)0x00000200U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV8 ((uint32_t)0x00000400U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV16 ((uint32_t)0x00000700U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV32 ((uint32_t)0x00000800U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV64 ((uint32_t)0x00000900U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV128 ((uint32_t)0x00000A00U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV256 ((uint32_t)0x00000B00U) +#define RCC_AXIDIV2_SDRAMMEMDIV_DIV512 ((uint32_t)0x00000C00U) + +#define RCC_AXIDIV2_FEMCM1AXIDIV ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define RCC_AXIDIV2_FEMCM1AXIDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_AXIDIV2_FEMCM1AXIDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_AXIDIV2_FEMCM1AXIDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_AXIDIV2_FEMCM1AXIDIV_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define RCC_AXIDIV2_FEMCM0AXIDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_AXIDIV2_FEMCM0AXIDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AXIDIV2_FEMCM0AXIDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AXIDIV2_FEMCM0AXIDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_AXIDIV2_FEMCM0AXIDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV1 ((uint32_t)0x00000001U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV2 ((uint32_t)0x00000002U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV3 ((uint32_t)0x00000003U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV4 ((uint32_t)0x00000004U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV5 ((uint32_t)0x00000005U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV6 ((uint32_t)0x00000006U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV7 ((uint32_t)0x00000007U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV8 ((uint32_t)0x00000008U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV9 ((uint32_t)0x00000009U) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV10 ((uint32_t)0x0000000AU) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV11 ((uint32_t)0x0000000BU) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV12 ((uint32_t)0x0000000CU) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV13 ((uint32_t)0x0000000DU) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV14 ((uint32_t)0x0000000EU) +#define RCC_AXIDIV2_FEMCM0AXIDIV_DIV15 ((uint32_t)0x0000000FU) +/******** Bit definition for RCC_AXISEL1 register ********/ +#define RCC_AXISEL1_DSIULPSSEL ((uint32_t)0x0C000000U) /* Bit[27:26] */ +#define RCC_AXISEL1_DSIULPSSEL_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_AXISEL1_DSIULPSSEL_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_AXISEL1_DSIKERSEL ((uint32_t)0x03000000U) /* Bit[25:24] */ +#define RCC_AXISEL1_DSIKERSEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_AXISEL1_DSIKERSEL_1 ((uint32_t)0x02000000U) /* Bit25*/ + +#define RCC_AXISEL1_SDMMC1KERSEL ((uint32_t)0x00700000U) /* Bit[22:20] */ +#define RCC_AXISEL1_SDMMC1KERSEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_AXISEL1_SDMMC1KERSEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_AXISEL1_SDMMC1KERSEL_2 ((uint32_t)0x00400000U) /* Bit22*/ + +#define RCC_AXISEL1_SDMMC1KERSEL_AXIDIV ((uint32_t)0x00000000U) +#define RCC_AXISEL1_SDMMC1KERSEL_PERIPH ((uint32_t)0x00100000U) +#define RCC_AXISEL1_SDMMC1KERSEL_PLL2A ((uint32_t)0x00200000U) +#define RCC_AXISEL1_SDMMC1KERSEL_PLL3A ((uint32_t)0x00300000U) +#define RCC_AXISEL1_SDMMC1KERSEL_PLL1B ((uint32_t)0x00400000U) + +#define RCC_AXISEL1_DSIPPITXSEL ((uint32_t)0x00030000U) /* Bit[17:16] */ +#define RCC_AXISEL1_DSIPPITXSEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_AXISEL1_DSIPPITXSEL_1 ((uint32_t)0x00020000U) /* Bit17*/ + +#define RCC_AXISEL1_DSIPPITXSEL_REFDIV ((uint32_t)0x00000000U) +#define RCC_AXISEL1_DSIPPITXSEL_PLL2B ((uint32_t)0x00010000U) +#define RCC_AXISEL1_DSIPPITXSEL_PERIPH ((uint32_t)0x00020000U) +#define RCC_AXISEL1_DSIPPITXSEL_AXIDIV ((uint32_t)0x00030000U) + +#define RCC_AXISEL1_LCDCKERSEL ((uint32_t)0x00003000U) /* Bit[13:12] */ +#define RCC_AXISEL1_LCDCKERSEL_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_AXISEL1_LCDCKERSEL_1 ((uint32_t)0x00002000U) /* Bit13*/ + +#define RCC_AXISEL1_LCDCKERSEL_AXIDIV ((uint32_t)0x00000000U) +#define RCC_AXISEL1_LCDCKERSEL_PERIPH ((uint32_t)0x00001000U) +#define RCC_AXISEL1_LCDCKERSEL_PLL2C ((uint32_t)0x00002000U) +#define RCC_AXISEL1_LCDCKERSEL_PLL3B ((uint32_t)0x00003000U) + +#define RCC_AXISEL1_DVP1MSEL ((uint32_t)0x00000C00U) /* Bit[11:10] */ +#define RCC_AXISEL1_DVP1MSEL_0 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_AXISEL1_DVP1MSEL_1 ((uint32_t)0x00000800U) /* Bit11*/ + +#define RCC_AXISEL1_DVP1MSEL_AXIDIV ((uint32_t)0x00000000U) +#define RCC_AXISEL1_DVP1MSEL_PERIPH ((uint32_t)0x00000400U) +#define RCC_AXISEL1_DVP1MSEL_PLL2C ((uint32_t)0x00000800U) +#define RCC_AXISEL1_DVP1MSEL_PLL3A ((uint32_t)0x00000C00U) + +#define RCC_AXISEL1_DVP2MSEL ((uint32_t)0x00000300U) /* Bit[9:8] */ +#define RCC_AXISEL1_DVP2MSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_AXISEL1_DVP2MSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ + +#define RCC_AXISEL1_XSPI1SSISEL ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_AXISEL1_XSPI1SSISEL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_AXISEL1_XSPI1SSISEL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_AXISEL1_XSPI1SSISEL_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define RCC_AXISEL1_XSPI1SSISEL_AXI ((uint32_t)0x00000000U) +#define RCC_AXISEL1_XSPI1SSISEL_PLL3C ((uint32_t)0x00000010U) +#define RCC_AXISEL1_XSPI1SSISEL_PLL1B ((uint32_t)0x00000020U) +#define RCC_AXISEL1_XSPI1SSISEL_PLL2A ((uint32_t)0x00000030U) +#define RCC_AXISEL1_XSPI1SSISEL_PLL2C ((uint32_t)0x00000040U) + +#define RCC_AXISEL1_XSPI2SSISEL ((uint32_t)0x00000007U) /* Bit */ +#define RCC_AXISEL1_XSPI2SSISEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AXISEL1_XSPI2SSISEL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AXISEL1_XSPI2SSISEL_2 ((uint32_t)0x00000004U) /* Bit2*/ + +/******** Bit definition for RCC_AXISEL2 register ********/ +#define RCC_AXISEL2_SDRAMMEMSEL ((uint32_t)0x00000700U) /* Bit[10:8] */ +#define RCC_AXISEL2_SDRAMMEMSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_AXISEL2_SDRAMMEMSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_AXISEL2_SDRAMMEMSEL_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define RCC_AXISEL2_SDRAMMEMSEL_AXIDIV ((uint32_t)0x00000000U) +#define RCC_AXISEL2_SDRAMMEMSEL_PERIPH ((uint32_t)0x00000100U) +#define RCC_AXISEL2_SDRAMMEMSEL_PLL2A ((uint32_t)0x00000200U) +#define RCC_AXISEL2_SDRAMMEMSEL_PLL3A ((uint32_t)0x00000300U) +#define RCC_AXISEL2_SDRAMMEMSEL_PLL1B ((uint32_t)0x00000400U) + +#define RCC_AXISEL2_FEMCM1SEL ((uint32_t)0x00000070U) /* Bit[6:4] */ +#define RCC_AXISEL2_FEMCM1SEL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_AXISEL2_FEMCM1SEL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_AXISEL2_FEMCM1SEL_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define RCC_AXISEL2_FEMCM0SEL ((uint32_t)0x00000007U) /* Bit */ +#define RCC_AXISEL2_FEMCM0SEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_AXISEL2_FEMCM0SEL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_AXISEL2_FEMCM0SEL_2 ((uint32_t)0x00000004U) /* Bit2*/ + +#define RCC_AXISEL2_FEMCM0SEL_AXIDIV ((uint32_t)0x00000000U) +#define RCC_AXISEL2_FEMCM0SEL_PERIPH ((uint32_t)0x00000001U) +#define RCC_AXISEL2_FEMCM0SEL_PLL2C ((uint32_t)0x00000002U) +#define RCC_AXISEL2_FEMCM0SEL_PLL3B ((uint32_t)0x00000003U) +#define RCC_AXISEL2_FEMCM0SEL_PLL1B ((uint32_t)0x00000004U) +/******** Bit definition for RCC_AXIEN1 register ********/ +#define RCC_AXIEN1_M7JPEGDEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AXIEN1_M4JPEGDEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AXIEN1_M7JPEGDLPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AXIEN1_M4JPEGDLPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIEN1_M7JPEGEEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AXIEN1_M4JPEGEEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AXIEN1_M7JPEGELPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AXIEN1_M4JPEGELPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AXIEN1_M7DMAMUX2EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AXIEN1_M4DMAMUX2EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AXIEN1_M7DMAMUX2LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AXIEN1_M4DMAMUX2LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AXIEN1_M7MDMAEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AXIEN1_M4MDMAEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AXIEN1_M7MDMALPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AXIEN1_M4MDMALPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AXIEN1_M7SDMMC1EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AXIEN1_M4SDMMC1EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AXIEN1_M7SDMMC1LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AXIEN1_M4SDMMC1LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AXIEN1_M7ECCM1EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AXIEN1_M4ECCM1EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AXIEN1_M7ECCM1LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AXIEN1_M4ECCM1LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AXIEN1_M7OTPCEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AXIEN1_M4OTPCEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AXIEN1_M7OTPCLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AXIEN1_M4OTPCLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIEN2 register ********/ +#define RCC_AXIEN2_M7DSIEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AXIEN2_M4DSIEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AXIEN2_M7DSILPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AXIEN2_M4DSILPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIEN2_M7LCDCEN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AXIEN2_M4LCDCEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AXIEN2_M7LCDCLPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AXIEN2_M4LCDCLPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AXIEN2_M7LCDCAPBEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AXIEN2_M4LCDCAPBEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AXIEN2_M7LCDCAPBLPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AXIEN2_M4LCDCAPBLPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AXIEN2_M7DVP1EN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AXIEN2_M4DVP1EN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AXIEN2_M7DVP1LPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AXIEN2_M4DVP1LPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AXIEN2_M7DVP1APBEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AXIEN2_M4DVP1APBEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AXIEN2_M7DVP1APBLPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AXIEN2_M4DVP1APBLPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AXIEN2_M7DVP2EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AXIEN2_M4DVP2EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AXIEN2_M7DVP2LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AXIEN2_M4DVP2LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AXIEN2_M7DVP2APBEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AXIEN2_M4DVP2APBEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AXIEN2_M7DVP2APBLPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AXIEN2_M4DVP2APBLPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AXIEN2_M7WWDG1EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AXIEN2_M4WWDG1EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AXIEN2_M7WWDG1LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AXIEN2_M4WWDG1LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIEN3 register ********/ +#define RCC_AXIEN3_M7TASRAM2EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AXIEN3_M4TASRAM2EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AXIEN3_M7TASRAM2LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AXIEN3_M4TASRAM2LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIEN3_M7TASRAM3EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AXIEN3_M4TASRAM3EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AXIEN3_M7TASRAM3LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AXIEN3_M4TASRAM3LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AXIEN3_M7TCMEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AXIEN3_M4TCMEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AXIEN3_M7TCMLPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AXIEN3_M4TCMLPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AXIEN3_M7TCMAXIEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AXIEN3_M4TCMAXIEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AXIEN3_M7TCMAXILPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AXIEN3_M4TCMAXILPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AXIEN3_M7TCMAPBEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_AXIEN3_M4TCMAPBEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_AXIEN3_M7TCMAPBLPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_AXIEN3_M4TCMAPBLPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AXIEN3_M7ASRAM1EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_AXIEN3_M4ASRAM1EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_AXIEN3_M7ASRAM1LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AXIEN3_M4ASRAM1LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AXIEN3_M7AXIROMEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_AXIEN3_M4AXIROMEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_AXIEN3_M7AXIROMLPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_AXIEN3_M4AXIROMLPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AXIEN3_M7GPUEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AXIEN3_M4GPUEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AXIEN3_M7GPULPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AXIEN3_M4GPULPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIEN4 register ********/ +#define RCC_AXIEN4_M7XSPI1EN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_AXIEN4_M4XSPI1EN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_AXIEN4_M7XSPI1LPEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AXIEN4_M4XSPI1LPEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIEN4_M7XSPI2EN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_AXIEN4_M4XSPI2EN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_AXIEN4_M7XSPI2LPEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_AXIEN4_M4XSPI2LPEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AXIEN4_M7FEMCEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_AXIEN4_M4FEMCEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_AXIEN4_M7FEMCLPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AXIEN4_M4FEMCLPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AXIEN4_M7SDRAMEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_AXIEN4_M4SDRAMEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_AXIEN4_M7SDRAMLPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_AXIEN4_M4SDRAMLPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AXIEN4_M7DSIULPSEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_AXIEN4_M4DSIULPSEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_AXIEN4_M7DSIULPSLPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_AXIEN4_M4DSIULPSLPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIRST1 register ********/ +#define RCC_AXIRST1_JPEGDRST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIRST1_JPEGERST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AXIRST1_DMAMUX2RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AXIRST1_MDMARST ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_AXIRST1_SDMMC1RST ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_AXIRST1_SDHOST1RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AXIRST1_ECCM1RST ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_AXIRST1_OTPCRST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIRST2 register ********/ +#define RCC_AXIRST2_DSICFGRST ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_AXIRST2_DSIRST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIRST2_LCDCRST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AXIRST2_DVP1RST ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_AXIRST2_DVP2RST ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_AXIRST2_WWDG1RST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIRST3 register ********/ +#define RCC_AXIRST3_GPURST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_AXIRST4 register ********/ +#define RCC_AXIRST4_XSPI1RST ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_AXIRST4_XSPI2RST ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_AXIRST4_FEMCCFGRST ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_AXIRST4_FEMCRST ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_AXIRST4_SDRAMRST ((uint32_t)0x00010000U) /* Bit[16] */ + +/******** Bit definition for RCC_CFG2 register ********/ +#define RCC_CFG2_M4CAHIEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_CFG2_M4CAHIPCLKEN ((uint32_t)0x10000000U) /* Bit[28] */ +#define RCC_CFG2_M4CAHDEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_CFG2_M4CAHDPCLKEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_CFG2_M7MMUEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_CFG2_M7MMULPEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_CFG2_M4MMUEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_CFG2_M4MMULPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_CFG2_M7SRAMBKPEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_CFG2_M4SRAMBKPEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_CFG2_M7SRAMBKPLPEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_CFG2_M4SRAMBKPLPEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_CFG2_M7SRAM1EN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_CFG2_M4SRAM1EN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_CFG2_M7SRAM1LPEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CFG2_M4SRAM1LPEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_CFG2_M7SRAM2EN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_CFG2_M4SRAM2EN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_CFG2_M7SRAM2LPEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_CFG2_M4SRAM2LPEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_CFG2_M7SRAM3EN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_CFG2_M4SRAM3EN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_CFG2_M7SRAM3LPEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_CFG2_M4SRAM3LPEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_CFG2_M7SRAM4EN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_CFG2_M4SRAM4EN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_CFG2_M7SRAM4LPEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_CFG2_M4SRAM4LPEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_CFG3 register ********/ +#define RCC_CFG3_MCO1SEL ((uint32_t)0xF0000000U) /* Bit[31:28] */ +#define RCC_CFG3_MCO1SEL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_CFG3_MCO1SEL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_CFG3_MCO1SEL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_CFG3_MCO1SEL_3 ((uint32_t)0x80000000U) /* Bit31*/ + +#define RCC_CFG3_MCO1SEL_LSI ((uint32_t)0x80000000U) +#define RCC_CFG3_MCO1SEL_HSI ((uint32_t)0x90000000U) +#define RCC_CFG3_MCO1SEL_MSI ((uint32_t)0xA0000000U) +#define RCC_CFG3_MCO1SEL_LSE ((uint32_t)0xB0000000U) +#define RCC_CFG3_MCO1SEL_HSE ((uint32_t)0xC0000000U) +#define RCC_CFG3_MCO1SEL_PLL3B ((uint32_t)0xD0000000U) + +#define RCC_CFG3_MCO1DIV ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define RCC_CFG3_MCO1DIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_CFG3_MCO1DIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_CFG3_MCO1DIV_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_CFG3_MCO1DIV_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define RCC_CFG3_MCO1DIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_CFG3_MCO1DIV_DIV2 ((uint32_t)0x01000000U) +#define RCC_CFG3_MCO1DIV_DIV4 ((uint32_t)0x02000000U) +#define RCC_CFG3_MCO1DIV_DIV8 ((uint32_t)0x04000000U) +#define RCC_CFG3_MCO1DIV_DIV16 ((uint32_t)0x07000000U) +#define RCC_CFG3_MCO1DIV_DIV32 ((uint32_t)0x08000000U) +#define RCC_CFG3_MCO1DIV_DIV64 ((uint32_t)0x09000000U) +#define RCC_CFG3_MCO1DIV_DIV128 ((uint32_t)0x0A000000U) + +#define RCC_CFG3_MCO2SEL ((uint32_t)0x00F00000U) /* Bit[23:20] */ +#define RCC_CFG3_MCO2SEL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_CFG3_MCO2SEL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_CFG3_MCO2SEL_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_CFG3_MCO2SEL_3 ((uint32_t)0x00800000U) /* Bit23*/ + +#define RCC_CFG3_MCO2SEL_SYSCLK ((uint32_t)0x00800000U) +#define RCC_CFG3_MCO2SEL_PLL1A ((uint32_t)0x00900000U) +#define RCC_CFG3_MCO2SEL_PLL2A ((uint32_t)0x00A00000U) +#define RCC_CFG3_MCO2SEL_PLL3A ((uint32_t)0x00B00000U) +#define RCC_CFG3_MCO2SEL_SHRPLL ((uint32_t)0x00C00000U) +#define RCC_CFG3_MCO2SEL_LSE ((uint32_t)0x00D00000U) + +#define RCC_CFG3_MCO2DIV ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define RCC_CFG3_MCO2DIV_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_CFG3_MCO2DIV_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_CFG3_MCO2DIV_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_CFG3_MCO2DIV_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define RCC_CFG3_MCO2DIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_CFG3_MCO2DIV_DIV2 ((uint32_t)0x00010000U) +#define RCC_CFG3_MCO2DIV_DIV4 ((uint32_t)0x00020000U) +#define RCC_CFG3_MCO2DIV_DIV8 ((uint32_t)0x00040000U) +#define RCC_CFG3_MCO2DIV_DIV16 ((uint32_t)0x00070000U) +#define RCC_CFG3_MCO2DIV_DIV32 ((uint32_t)0x00080000U) +#define RCC_CFG3_MCO2DIV_DIV64 ((uint32_t)0x00090000U) +#define RCC_CFG3_MCO2DIV_DIV128 ((uint32_t)0x000A0000U) + +#define RCC_CFG3_I2SSEL ((uint32_t)0x0000C000U) /* Bit[15:14] */ +#define RCC_CFG3_I2SSEL_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_CFG3_I2SSEL_1 ((uint32_t)0x00008000U) /* Bit15*/ + +#define RCC_CFG3_I2SSEL_I2S1 ((uint32_t)0x00000000U) +#define RCC_CFG3_I2SSEL_I2S2 ((uint32_t)0x00004000U) +#define RCC_CFG3_I2SSEL_I2S3 ((uint32_t)0x00008000U) +#define RCC_CFG3_I2SSEL_I2S4 ((uint32_t)0x0000C000U) + +#define RCC_CFG3_PERSW ((uint32_t)0x00003000U) /* Bit[13:12] */ +#define RCC_CFG3_PERSW_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_CFG3_PERSW_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_CFG3_M7STCLKDIV ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define RCC_CFG3_M7STCLKDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_CFG3_M7STCLKDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_CFG3_M7STCLKDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_CFG3_M7STCLKDIV_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define RCC_CFG3_M7STCLKDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_CFG3_M7STCLKDIV_DIV2 ((uint32_t)0x00000010U) +#define RCC_CFG3_M7STCLKDIV_DIV4 ((uint32_t)0x00000020U) +#define RCC_CFG3_M7STCLKDIV_DIV8 ((uint32_t)0x00000040U) +#define RCC_CFG3_M7STCLKDIV_DIV16 ((uint32_t)0x00000070U) +#define RCC_CFG3_M7STCLKDIV_DIV32 ((uint32_t)0x00000080U) +#define RCC_CFG3_M7STCLKDIV_DIV64 ((uint32_t)0x00000090U) +#define RCC_CFG3_M7STCLKDIV_DIV128 ((uint32_t)0x000000A0U) +#define RCC_CFG3_M7STCLKDIV_DIV256 ((uint32_t)0x000000B0U) +#define RCC_CFG3_M7STCLKDIV_DIV512 ((uint32_t)0x000000C0U) + +#define RCC_CFG3_M4STCLKDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_CFG3_M4STCLKDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_CFG3_M4STCLKDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_CFG3_M4STCLKDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_CFG3_M4STCLKDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for RCC_CFG4 register ********/ +#define RCC_CFG4_AHB1CLKEN ((uint32_t)0x80000000U) /* Bit[31] */ +#define RCC_CFG4_AHB2CLKEN ((uint32_t)0x40000000U) /* Bit[30] */ +#define RCC_CFG4_AHB3CLKEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define RCC_CFG4_AHB5CLKEN ((uint32_t)0x08000000U) /* Bit[27] */ +#define RCC_CFG4_AHB6CLKEN ((uint32_t)0x04000000U) /* Bit[26] */ +#define RCC_CFG4_AXICLKEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_CFG4_APB1CLKEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_CFG4_APB2CLKEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_CFG4_APB5CLKEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_CFG4_APB6CLKEN ((uint32_t)0x00080000U) /* Bit[19] */ +#define RCC_CFG4_AHB9CLKEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define RCC_CFG4_AXIMM7GCLKEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_CFG4_AXIMM4GCLKEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_CFG4_HSICGEN ((uint32_t)0x00008000U) /* Bit[15] */ +#define RCC_CFG4_HSIKERCGEN ((uint32_t)0x00004000U) /* Bit[14] */ +#define RCC_CFG4_HSECGEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CFG4_HSEKERCGEN ((uint32_t)0x00001000U) /* Bit[12] */ +#define RCC_CFG4_MSICGEN ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_CFG4_MSIKERCGEN ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_CFG4_AXIMM7CLKEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_CFG4_AXIGCLKEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_CFG4_AXIMM4CLKEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_CFG4_DCMUM7CLKEN ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_CFG4_DCMUM4CLKEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_CFG4_AHBM1CLKEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_CFG4_AHBM2CLKEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_CFG4_AHBM3CLKEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_CFG4_DCMURST ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_CFG5 register ********/ +#define RCC_CFG5_RTCHSEDIV ((uint32_t)0x3F000000U) /* Bit[29:24] */ +#define RCC_CFG5_RTCHSEDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_CFG5_RTCHSEDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_CFG5_RTCHSEDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_CFG5_RTCHSEDIV_3 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_CFG5_RTCHSEDIV_4 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_CFG5_RTCHSEDIV_5 ((uint32_t)0x20000000U) /* Bit29*/ + +#define RCC_CFG5_RTCHSEDIV_DIV1 ((uint32_t)0x01000000U) +#define RCC_CFG5_RTCHSEDIV_DIV2 ((uint32_t)0x02000000U) +#define RCC_CFG5_RTCHSEDIV_DIV3 ((uint32_t)0x03000000U) +#define RCC_CFG5_RTCHSEDIV_DIV4 ((uint32_t)0x04000000U) +#define RCC_CFG5_RTCHSEDIV_DIV5 ((uint32_t)0x05000000U) +#define RCC_CFG5_RTCHSEDIV_DIV6 ((uint32_t)0x06000000U) +#define RCC_CFG5_RTCHSEDIV_DIV7 ((uint32_t)0x07000000U) +#define RCC_CFG5_RTCHSEDIV_DIV8 ((uint32_t)0x08000000U) +#define RCC_CFG5_RTCHSEDIV_DIV9 ((uint32_t)0x09000000U) +#define RCC_CFG5_RTCHSEDIV_DIV10 ((uint32_t)0x0A000000U) +#define RCC_CFG5_RTCHSEDIV_DIV11 ((uint32_t)0x0B000000U) +#define RCC_CFG5_RTCHSEDIV_DIV12 ((uint32_t)0x0C000000U) +#define RCC_CFG5_RTCHSEDIV_DIV13 ((uint32_t)0x0D000000U) +#define RCC_CFG5_RTCHSEDIV_DIV14 ((uint32_t)0x0E000000U) +#define RCC_CFG5_RTCHSEDIV_DIV15 ((uint32_t)0x0F000000U) +#define RCC_CFG5_RTCHSEDIV_DIV16 ((uint32_t)0x10000000U) +#define RCC_CFG5_RTCHSEDIV_DIV17 ((uint32_t)0x11000000U) +#define RCC_CFG5_RTCHSEDIV_DIV18 ((uint32_t)0x12000000U) +#define RCC_CFG5_RTCHSEDIV_DIV19 ((uint32_t)0x13000000U) +#define RCC_CFG5_RTCHSEDIV_DIV20 ((uint32_t)0x14000000U) +#define RCC_CFG5_RTCHSEDIV_DIV21 ((uint32_t)0x15000000U) +#define RCC_CFG5_RTCHSEDIV_DIV22 ((uint32_t)0x16000000U) +#define RCC_CFG5_RTCHSEDIV_DIV23 ((uint32_t)0x17000000U) +#define RCC_CFG5_RTCHSEDIV_DIV24 ((uint32_t)0x18000000U) +#define RCC_CFG5_RTCHSEDIV_DIV25 ((uint32_t)0x19000000U) +#define RCC_CFG5_RTCHSEDIV_DIV26 ((uint32_t)0x1A000000U) +#define RCC_CFG5_RTCHSEDIV_DIV27 ((uint32_t)0x1B000000U) +#define RCC_CFG5_RTCHSEDIV_DIV28 ((uint32_t)0x1C000000U) +#define RCC_CFG5_RTCHSEDIV_DIV29 ((uint32_t)0x1D000000U) +#define RCC_CFG5_RTCHSEDIV_DIV30 ((uint32_t)0x1E000000U) +#define RCC_CFG5_RTCHSEDIV_DIV31 ((uint32_t)0x1F000000U) +#define RCC_CFG5_RTCHSEDIV_DIV32 ((uint32_t)0x20000000U) +#define RCC_CFG5_RTCHSEDIV_DIV33 ((uint32_t)0x21000000U) +#define RCC_CFG5_RTCHSEDIV_DIV34 ((uint32_t)0x22000000U) +#define RCC_CFG5_RTCHSEDIV_DIV35 ((uint32_t)0x23000000U) +#define RCC_CFG5_RTCHSEDIV_DIV36 ((uint32_t)0x24000000U) +#define RCC_CFG5_RTCHSEDIV_DIV37 ((uint32_t)0x25000000U) +#define RCC_CFG5_RTCHSEDIV_DIV38 ((uint32_t)0x26000000U) +#define RCC_CFG5_RTCHSEDIV_DIV39 ((uint32_t)0x27000000U) +#define RCC_CFG5_RTCHSEDIV_DIV40 ((uint32_t)0x28000000U) +#define RCC_CFG5_RTCHSEDIV_DIV41 ((uint32_t)0x29000000U) +#define RCC_CFG5_RTCHSEDIV_DIV42 ((uint32_t)0x2A000000U) +#define RCC_CFG5_RTCHSEDIV_DIV43 ((uint32_t)0x2B000000U) +#define RCC_CFG5_RTCHSEDIV_DIV44 ((uint32_t)0x2C000000U) +#define RCC_CFG5_RTCHSEDIV_DIV45 ((uint32_t)0x2D000000U) +#define RCC_CFG5_RTCHSEDIV_DIV46 ((uint32_t)0x2E000000U) +#define RCC_CFG5_RTCHSEDIV_DIV47 ((uint32_t)0x2F000000U) +#define RCC_CFG5_RTCHSEDIV_DIV48 ((uint32_t)0x30000000U) +#define RCC_CFG5_RTCHSEDIV_DIV49 ((uint32_t)0x31000000U) +#define RCC_CFG5_RTCHSEDIV_DIV50 ((uint32_t)0x32000000U) +#define RCC_CFG5_RTCHSEDIV_DIV51 ((uint32_t)0x33000000U) +#define RCC_CFG5_RTCHSEDIV_DIV52 ((uint32_t)0x34000000U) +#define RCC_CFG5_RTCHSEDIV_DIV53 ((uint32_t)0x35000000U) +#define RCC_CFG5_RTCHSEDIV_DIV54 ((uint32_t)0x36000000U) +#define RCC_CFG5_RTCHSEDIV_DIV55 ((uint32_t)0x37000000U) +#define RCC_CFG5_RTCHSEDIV_DIV56 ((uint32_t)0x38000000U) +#define RCC_CFG5_RTCHSEDIV_DIV57 ((uint32_t)0x39000000U) +#define RCC_CFG5_RTCHSEDIV_DIV58 ((uint32_t)0x3A000000U) +#define RCC_CFG5_RTCHSEDIV_DIV59 ((uint32_t)0x3B000000U) +#define RCC_CFG5_RTCHSEDIV_DIV60 ((uint32_t)0x3C000000U) +#define RCC_CFG5_RTCHSEDIV_DIV61 ((uint32_t)0x3D000000U) +#define RCC_CFG5_RTCHSEDIV_DIV62 ((uint32_t)0x3E000000U) +#define RCC_CFG5_RTCHSEDIV_DIV63 ((uint32_t)0x3F000000U) + +#define RCC_CFG5_M7SRAM5EN ((uint32_t)0x00800000U) /* Bit[23] */ +#define RCC_CFG5_M4SRAM5EN ((uint32_t)0x00400000U) /* Bit[22] */ +#define RCC_CFG5_M7SRAM5LPEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define RCC_CFG5_M4SRAM5LPEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define RCC_CFG5_DCDCLKEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_CFG5_TRNGEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define RCC_CFG5_TRNGSEL ((uint32_t)0x00001000U) /* Bit[12] */ + +#define RCC_CFG5_TRNGDIV ((uint32_t)0x00000F00U) /* Bit[11:8] */ +#define RCC_CFG5_TRNGDIV_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_CFG5_TRNGDIV_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_CFG5_TRNGDIV_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_CFG5_TRNGDIV_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define RCC_CFG5_TRNGDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_CFG5_TRNGDIV_DIV2 ((uint32_t)0x00000100U) +#define RCC_CFG5_TRNGDIV_DIV4 ((uint32_t)0x00000200U) +#define RCC_CFG5_TRNGDIV_DIV8 ((uint32_t)0x00000400U) +#define RCC_CFG5_TRNGDIV_DIV16 ((uint32_t)0x00000700U) +#define RCC_CFG5_TRNGDIV_DIV32 ((uint32_t)0x00000800U) +#define RCC_CFG5_TRNGDIV_DIV64 ((uint32_t)0x00000900U) +#define RCC_CFG5_TRNGDIV_DIV128 ((uint32_t)0x00000A00U) +#define RCC_CFG5_TRNGDIV_DIV256 ((uint32_t)0x00000B00U) +#define RCC_CFG5_TRNGDIV_DIV512 ((uint32_t)0x00000C00U) + +#define RCC_CFG5_DSIHSEDIV ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define RCC_CFG5_DSIHSEDIV_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_CFG5_DSIHSEDIV_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_CFG5_DSIHSEDIV_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_CFG5_DSIHSEDIV_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define RCC_CFG5_RTCHSIDIV ((uint32_t)0x0000000FU) /* Bit */ +#define RCC_CFG5_RTCHSIDIV_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_CFG5_RTCHSIDIV_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_CFG5_RTCHSIDIV_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_CFG5_RTCHSIDIV_3 ((uint32_t)0x00000008U) /* Bit3*/ + +#define RCC_CFG5_RTCHSIDIV_DIV1 ((uint32_t)0x00000000U) +#define RCC_CFG5_RTCHSIDIV_DIV2 ((uint32_t)0x00000001U) +#define RCC_CFG5_RTCHSIDIV_DIV4 ((uint32_t)0x00000002U) +#define RCC_CFG5_RTCHSIDIV_DIV8 ((uint32_t)0x00000004U) +#define RCC_CFG5_RTCHSIDIV_DIV16 ((uint32_t)0x00000007U) +#define RCC_CFG5_RTCHSIDIV_DIV32 ((uint32_t)0x00000008U) +#define RCC_CFG5_RTCHSIDIV_DIV64 ((uint32_t)0x00000009U) +#define RCC_CFG5_RTCHSIDIV_DIV128 ((uint32_t)0x0000000AU) +#define RCC_CFG5_RTCHSIDIV_DIV256 ((uint32_t)0x0000000BU) +#define RCC_CFG5_RTCHSIDIV_DIV512 ((uint32_t)0x0000000CU) +/******** Bit definition for RCC_M4RSTREL register ********/ +#define RCC_M4RSTREL_EN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_LSERDDL register ********/ +#define RCC_LSERDDL_DELAY ((uint32_t)0xFFFFFFFFU) /* Bit */ +#define RCC_LSERDDL_DELAY_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_LSERDDL_DELAY_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_LSERDDL_DELAY_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_LSERDDL_DELAY_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_LSERDDL_DELAY_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_LSERDDL_DELAY_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_LSERDDL_DELAY_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_LSERDDL_DELAY_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_LSERDDL_DELAY_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_LSERDDL_DELAY_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_LSERDDL_DELAY_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_LSERDDL_DELAY_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_LSERDDL_DELAY_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_LSERDDL_DELAY_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_LSERDDL_DELAY_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_LSERDDL_DELAY_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_LSERDDL_DELAY_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_LSERDDL_DELAY_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_LSERDDL_DELAY_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_LSERDDL_DELAY_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_LSERDDL_DELAY_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_LSERDDL_DELAY_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_LSERDDL_DELAY_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_LSERDDL_DELAY_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_LSERDDL_DELAY_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_LSERDDL_DELAY_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_LSERDDL_DELAY_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_LSERDDL_DELAY_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_LSERDDL_DELAY_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_LSERDDL_DELAY_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_LSERDDL_DELAY_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_LSERDDL_DELAY_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for RCC_MSIRDDL register ********/ +#define RCC_MSIRDDL_DELAY ((uint32_t)0xFFFFFFFFU) /* Bit */ +#define RCC_MSIRDDL_DELAY_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_MSIRDDL_DELAY_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_MSIRDDL_DELAY_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_MSIRDDL_DELAY_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_MSIRDDL_DELAY_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_MSIRDDL_DELAY_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_MSIRDDL_DELAY_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_MSIRDDL_DELAY_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_MSIRDDL_DELAY_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_MSIRDDL_DELAY_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_MSIRDDL_DELAY_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_MSIRDDL_DELAY_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_MSIRDDL_DELAY_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_MSIRDDL_DELAY_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_MSIRDDL_DELAY_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_MSIRDDL_DELAY_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_MSIRDDL_DELAY_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_MSIRDDL_DELAY_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_MSIRDDL_DELAY_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_MSIRDDL_DELAY_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_MSIRDDL_DELAY_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_MSIRDDL_DELAY_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_MSIRDDL_DELAY_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_MSIRDDL_DELAY_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_MSIRDDL_DELAY_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_MSIRDDL_DELAY_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_MSIRDDL_DELAY_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_MSIRDDL_DELAY_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_MSIRDDL_DELAY_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_MSIRDDL_DELAY_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_MSIRDDL_DELAY_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_MSIRDDL_DELAY_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for RCC_HSERDDL register ********/ +#define RCC_HSERDDL_DELAY ((uint32_t)0xFFFFFFFFU) /* Bit */ +#define RCC_HSERDDL_DELAY_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_HSERDDL_DELAY_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_HSERDDL_DELAY_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_HSERDDL_DELAY_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_HSERDDL_DELAY_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_HSERDDL_DELAY_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_HSERDDL_DELAY_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_HSERDDL_DELAY_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_HSERDDL_DELAY_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_HSERDDL_DELAY_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_HSERDDL_DELAY_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_HSERDDL_DELAY_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_HSERDDL_DELAY_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_HSERDDL_DELAY_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_HSERDDL_DELAY_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_HSERDDL_DELAY_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_HSERDDL_DELAY_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_HSERDDL_DELAY_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_HSERDDL_DELAY_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_HSERDDL_DELAY_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_HSERDDL_DELAY_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_HSERDDL_DELAY_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_HSERDDL_DELAY_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_HSERDDL_DELAY_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_HSERDDL_DELAY_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_HSERDDL_DELAY_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_HSERDDL_DELAY_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_HSERDDL_DELAY_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_HSERDDL_DELAY_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_HSERDDL_DELAY_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_HSERDDL_DELAY_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_HSERDDL_DELAY_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for RCC_PLLSFTLK register ********/ +#define RCC_PLLSFTLK_SDRAMDLSEL ((uint32_t)0x1E000000U) /* Bit[28:25] */ +#define RCC_PLLSFTLK_SDRAMDLSEL_0 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_PLLSFTLK_SDRAMDLSEL_1 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_PLLSFTLK_SDRAMDLSEL_2 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_PLLSFTLK_SDRAMDLSEL_3 ((uint32_t)0x10000000U) /* Bit28*/ + +#define RCC_PLLSFTLK_SDRAMDLSEL_0_2NS ((uint32_t)0x00000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_0_4NS ((uint32_t)0x02000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_0_6NS ((uint32_t)0x04000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_0_8NS ((uint32_t)0x06000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_1_0NS ((uint32_t)0x08000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_1_2NS ((uint32_t)0x0A000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_1_4NS ((uint32_t)0x0C000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_1_6NS ((uint32_t)0x0E000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_1_8NS ((uint32_t)0x10000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_2_0NS ((uint32_t)0x12000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_2_2NS ((uint32_t)0x14000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_2_4NS ((uint32_t)0x16000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_2_6NS ((uint32_t)0x18000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_2_8NS ((uint32_t)0x1A000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_3_0NS ((uint32_t)0x1C000000U) +#define RCC_PLLSFTLK_SDRAMDLSEL_3_2NS ((uint32_t)0x1E000000U) + +#define RCC_PLLSFTLK_SDRAMDLEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_PLLSFTLK_SHRTIMAFERST ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_PLLSFTLK_SHRPLLSFTLK ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_PLLSFTLK_PLL3SFTLK ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_PLLSFTLK_PLL2SFTLK ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_PLLSFTLK_PLL1SFTLK ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_HSEOS register ********/ +#define RCC_HSEOS_HSEMAXPDTHR ((uint32_t)0xFF000000U) /* Bit[31:24] */ +#define RCC_HSEOS_HSEMAXPDTHR_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define RCC_HSEOS_HSEMAXPDTHR_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define RCC_HSEOS_HSEMAXPDTHR_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define RCC_HSEOS_HSEMAXPDTHR_3 ((uint32_t)0x08000000U) /* Bit27*/ +#define RCC_HSEOS_HSEMAXPDTHR_4 ((uint32_t)0x10000000U) /* Bit28*/ +#define RCC_HSEOS_HSEMAXPDTHR_5 ((uint32_t)0x20000000U) /* Bit29*/ +#define RCC_HSEOS_HSEMAXPDTHR_6 ((uint32_t)0x40000000U) /* Bit30*/ +#define RCC_HSEOS_HSEMAXPDTHR_7 ((uint32_t)0x80000000U) /* Bit31*/ +#define RCC_HSEOS_HSEMINNDTHR ((uint32_t)0x00FF0000U) /* Bit[23:16] */ +#define RCC_HSEOS_HSEMINNDTHR_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_HSEOS_HSEMINNDTHR_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_HSEOS_HSEMINNDTHR_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_HSEOS_HSEMINNDTHR_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_HSEOS_HSEMINNDTHR_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_HSEOS_HSEMINNDTHR_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_HSEOS_HSEMINNDTHR_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_HSEOS_HSEMINNDTHR_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_HSEOS_HSEOSTHR ((uint32_t)0x0000FF00U) /* Bit[15:8] */ +#define RCC_HSEOS_HSEOSTHR_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_HSEOS_HSEOSTHR_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_HSEOS_HSEOSTHR_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_HSEOS_HSEOSTHR_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_HSEOS_HSEOSTHR_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_HSEOS_HSEOSTHR_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_HSEOS_HSEOSTHR_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_HSEOS_HSEOSTHR_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define RCC_HSEOS_HSEMAXPDF ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_HSEOS_HSEMINNDF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_HSEOS_HSEOSF ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_HSEOS_HSEMAXPDEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_HSEOS_HSEMINNDEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_HSEOS_HSEOSEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for RCC_HSECAL register ********/ +#define RCC_HSECAL_HSECALCNTEN ((uint32_t)0x00020000U) /* Bit[17] */ +#define RCC_HSECAL_HSECALCNTF ((uint32_t)0x00010000U) /* Bit[16] */ +#define RCC_HSECAL_HSECALCNT ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define RCC_HSECAL_HSECALCNT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_HSECAL_HSECALCNT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_HSECAL_HSECALCNT_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_HSECAL_HSECALCNT_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_HSECAL_HSECALCNT_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_HSECAL_HSECALCNT_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_HSECAL_HSECALCNT_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_HSECAL_HSECALCNT_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define RCC_HSECAL_HSECALCNT_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define RCC_HSECAL_HSECALCNT_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define RCC_HSECAL_HSECALCNT_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define RCC_HSECAL_HSECALCNT_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define RCC_HSECAL_HSECALCNT_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define RCC_HSECAL_HSECALCNT_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define RCC_HSECAL_HSECALCNT_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define RCC_HSECAL_HSECALCNT_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for RCC_LSEOS register ********/ +#define RCC_LSEOS_LSECALCNTEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define RCC_LSEOS_LSECALCNTF ((uint32_t)0x01000000U) /* Bit[24] */ +#define RCC_LSEOS_LSECALCNT ((uint32_t)0x00FF0000U) /* Bit[23:16] */ +#define RCC_LSEOS_LSECALCNT_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define RCC_LSEOS_LSECALCNT_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define RCC_LSEOS_LSECALCNT_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define RCC_LSEOS_LSECALCNT_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define RCC_LSEOS_LSECALCNT_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define RCC_LSEOS_LSECALCNT_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define RCC_LSEOS_LSECALCNT_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define RCC_LSEOS_LSECALCNT_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define RCC_LSEOS_LSEOSF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_LSEOS_LSEOSEN ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_LSEOS_LSEOSTHR ((uint32_t)0x000000FFU) /* Bit */ +#define RCC_LSEOS_LSEOSTHR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define RCC_LSEOS_LSEOSTHR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define RCC_LSEOS_LSEOSTHR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define RCC_LSEOS_LSEOSTHR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define RCC_LSEOS_LSEOSTHR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define RCC_LSEOS_LSEOSTHR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define RCC_LSEOS_LSEOSTHR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define RCC_LSEOS_LSEOSTHR_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for RCC_PLLFD register ********/ +#define RCC_PLLFD_SHRPLLGF ((uint32_t)0x00000800U) /* Bit[11] */ +#define RCC_PLLFD_PLL3GF ((uint32_t)0x00000400U) /* Bit[10] */ +#define RCC_PLLFD_PLL2GF ((uint32_t)0x00000200U) /* Bit[9] */ +#define RCC_PLLFD_PLL1GF ((uint32_t)0x00000100U) /* Bit[8] */ +#define RCC_PLLFD_SHRPLLFF ((uint32_t)0x00000080U) /* Bit[7] */ +#define RCC_PLLFD_PLL3FF ((uint32_t)0x00000040U) /* Bit[6] */ +#define RCC_PLLFD_PLL2FF ((uint32_t)0x00000020U) /* Bit[5] */ +#define RCC_PLLFD_PLL1FF ((uint32_t)0x00000010U) /* Bit[4] */ +#define RCC_PLLFD_SHRPLLFEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define RCC_PLLFD_PLL3FEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define RCC_PLLFD_PLL2FEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define RCC_PLLFD_PLL1FEN ((uint32_t)0x00000001U) /* Bit[0] */ + + +/*** Power Control ***/ + +/******** Bit definition for PWR_M7CTRL1 register ********/ +#define PWR_M7CTRL1_CVBATF ((uint32_t)0x00010000U) /* Bit[16] Clear VBAT flags*/ +#define PWR_M7CTRL1_CSBF ((uint32_t)0x00000008U) /* Bit[3] Clear STANDBY flags*/ +#define PWR_M7CTRL1_CWKUPF ((uint32_t)0x00000004U) /* Bit[2] Clear the pin wakeup bit*/ +#define PWR_M7CTRL1_PDS ((uint32_t)0x00000002U) /* Bit[1] Power down deep sleep bit*/ + +/******** Bit definition for PWR_M7CTRLSTS register ********/ +#define PWR_M7CTRLSTS_WKUPxF_MASK ((uint32_t)0x07F00000U) /* Bit[26:20] WKUPx pin wakeup flag*/ +#define PWR_M7CTRLSTS_WKUP0F ((uint32_t)0x00100000U) /* Bit20*/ +#define PWR_M7CTRLSTS_WKUP1F ((uint32_t)0x00200000U) /* Bit21*/ +#define PWR_M7CTRLSTS_WKUP2F ((uint32_t)0x00400000U) /* Bit22*/ +#define PWR_M7CTRLSTS_WKUP3F ((uint32_t)0x00800000U) /* Bit23*/ +#define PWR_M7CTRLSTS_WKUP4F ((uint32_t)0x01000000U) /* Bit24*/ +#define PWR_M7CTRLSTS_WKUP5F ((uint32_t)0x02000000U) /* Bit25*/ +#define PWR_M7CTRLSTS_WKUP6F ((uint32_t)0x04000000U) /* Bit26*/ + +#define PWR_M7CTRLSTS_WKUPxPOL_MASK ((uint32_t)0x000FC000U) /* Bit[19:14] Wake-up polarity for the WKUPx pin*/ +#define PWR_M7CTRLSTS_WKUP0POL ((uint32_t)0x00004000U) /* Bit14*/ +#define PWR_M7CTRLSTS_WKUP1POL ((uint32_t)0x00008000U) /* Bit15*/ +#define PWR_M7CTRLSTS_WKUP2POL ((uint32_t)0x00010000U) /* Bit16*/ +#define PWR_M7CTRLSTS_WKUP3POL ((uint32_t)0x00020000U) /* Bit17*/ +#define PWR_M7CTRLSTS_WKUP4POL ((uint32_t)0x00040000U) /* Bit18*/ +#define PWR_M7CTRLSTS_WKUP5POL ((uint32_t)0x00080000U) /* Bit19*/ + +#define PWR_M7CTRLSTS_WKUPxEN_MASK ((uint32_t)0x00003F00U) /* Bit[13:8] WKUPx pin wakeup enable*/ +#define PWR_M7CTRLSTS_WKUP0EN ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_M7CTRLSTS_WKUP1EN ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_M7CTRLSTS_WKUP2EN ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_M7CTRLSTS_WKUP3EN ((uint32_t)0x00000800U) /* Bit11*/ +#define PWR_M7CTRLSTS_WKUP4EN ((uint32_t)0x00001000U) /* Bit12*/ +#define PWR_M7CTRLSTS_WKUP5EN ((uint32_t)0x00002000U) /* Bit13*/ + +#define PWR_M7CTRLSTS_VBATF ((uint32_t)0x00000004U) /* Bit[2] VBAT flag*/ +#define PWR_M7CTRLSTS_SBF ((uint32_t)0x00000002U) /* Bit[1] STANDBY flag*/ + +/******** Bit definition for PWR_M7CTRL2 register ********/ +#define PWR_M7CTRL2_MEM_CNTVAL ((uint32_t)0x7E000000U) /* Bit[30:25] counter value for memory power ready count down*/ + +#define PWR_M7CTRL2_PWR_CNTVAL ((uint32_t)0x01FE0000U) /* Bit[24:17] counter value for CM7 logic power ready count down*/ + +#define PWR_M7CTRL2_TCM_RDYMD ((uint32_t)0x00018000U) /* Bit[16:15] Selected the way of check TCM power ready for CM7 domain*/ +#define PWR_M7CTRL2_TCM_RDYMD_0 ((uint32_t)0x00008000U) /* Bit15*/ +#define PWR_M7CTRL2_TCM_RDYMD_1 ((uint32_t)0x00010000U) /* Bit16*/ + +#define PWR_M7CTRL2_PWR_RDYMD ((uint32_t)0x00006000U) /* Bit[14:13] Selected the way of check power ready for CM7 domain*/ +#define PWR_M7CTRL2_PWR_RDYMD_0 ((uint32_t)0x00002000U) /* Bit13*/ +#define PWR_M7CTRL2_PWR_RDYMD_1 ((uint32_t)0x00004000U) /* Bit14*/ + +#define PWR_M7CTRL2_HCLK_ONINSLP ((uint32_t)0x00001000U) /* Bit[12] HCLK is on when M7 core in sleep*/ +#define PWR_M7CTRL2_NRST_WUPEN ((uint32_t)0x00000800U) /* Bit[11] NRST wakeup event enable in standby mode for M7 core*/ +#define PWR_M7CTRL2_RET_PSWACK1 ((uint32_t)0x00000400U) /* Bit[10] M7 retention power switch ACK1 used as ENA2 enanle for dual-input-header*/ +#define PWR_M7CTRL2_DMN_PSWACK1 ((uint32_t)0x00000200U) /* Bit[9] M7 Domain power switch ACK1 used as ENA2 enanle for dual-input-header*/ +#define PWR_M7CTRL2_RTC_ALMWUPEN ((uint32_t)0x00000100U) /* Bit[8] RTC_ALARM wakeup enable in standby mode for M7 core*/ +#define PWR_M7CTRL2_BSRSTBRET ((uint32_t)0x00000004U) /* Bit[2] Backup SRAM retention enable in STANDBY mode*/ +#define PWR_M7CTRL2_BSRVBRET ((uint32_t)0x00000002U) /* Bit[1] Backup SRAM retention enable in VBAT mode*/ +#define PWR_M7CTRL2_STOP2EN ((uint32_t)0x00000001U) /* Bit[0] M7 core STOP2 mode enable*/ + +/******** Bit definition for PWR_M4CTRL1 register ********/ +#define PWR_M4CTRL1_CVBATF ((uint32_t)0x00010000U) /* Bit[16] Clear VBAT flags*/ +#define PWR_M4CTRL1_CSBVBF ((uint32_t)0x00000008U) /* Bit[3] Clear STANDBY flags*/ +#define PWR_M4CTRL1_CWKUPF ((uint32_t)0x00000004U) /* Bit[2] Clear the pin wakeup bit*/ +#define PWR_M4CTRL1_PDS ((uint32_t)0x00000002U) /* Bit[1] Power down deep sleep bit*/ + +/******** Bit definition for PWR_M4CTRLSTS register ********/ +#define PWR_M4CTRLSTS_WKUPxF_MASK ((uint32_t)0x07F00000U) /* Bit[26:20] WKUP pin flag*/ +#define PWR_M4CTRLSTS_WKUP0F ((uint32_t)0x00100000U) /* Bit20*/ +#define PWR_M4CTRLSTS_WKUP1F ((uint32_t)0x00200000U) /* Bit21*/ +#define PWR_M4CTRLSTS_WKUP2F ((uint32_t)0x00400000U) /* Bit22*/ +#define PWR_M4CTRLSTS_WKUP3F ((uint32_t)0x00800000U) /* Bit23*/ +#define PWR_M4CTRLSTS_WKUP4F ((uint32_t)0x01000000U) /* Bit24*/ +#define PWR_M4CTRLSTS_WKUP5F ((uint32_t)0x02000000U) /* Bit25*/ +#define PWR_M4CTRLSTS_WKUP6F ((uint32_t)0x04000000U) /* Bit26*/ + +#define PWR_M4CTRLSTS_WKUPxPOL_MASK ((uint32_t)0x000FC000U) /* Bit[19:14] Wake-up polarity for the WKUPX pin*/ +#define PWR_M4CTRLSTS_WKUP0POL ((uint32_t)0x00004000U) /* Bit14*/ +#define PWR_M4CTRLSTS_WKUP1POL ((uint32_t)0x00008000U) /* Bit15*/ +#define PWR_M4CTRLSTS_WKUP2POL ((uint32_t)0x00010000U) /* Bit16*/ +#define PWR_M4CTRLSTS_WKUP3POL ((uint32_t)0x00020000U) /* Bit17*/ +#define PWR_M4CTRLSTS_WKUP4POL ((uint32_t)0x00040000U) /* Bit18*/ +#define PWR_M4CTRLSTS_WKUP5POL ((uint32_t)0x00080000U) /* Bit19*/ + +#define PWR_M4CTRLSTS_WKUPxEN ((uint32_t)0x00003F00U) /* Bit[13:8] WKUPx pin wakeup enable*/ +#define PWR_M4CTRLSTS_WKUP0EN ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_M4CTRLSTS_WKUP1EN ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_M4CTRLSTS_WKUP2EN ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_M4CTRLSTS_WKUP3EN ((uint32_t)0x00000800U) /* Bit11*/ +#define PWR_M4CTRLSTS_WKUP4EN ((uint32_t)0x00001000U) /* Bit12*/ +#define PWR_M4CTRLSTS_WKUP5EN ((uint32_t)0x00002000U) /* Bit13*/ + +#define PWR_M4CTRLSTS_VBATF ((uint32_t)0x00000004U) /* Bit[2] VBAT flag.*/ +#define PWR_M4CTRLSTS_SBF ((uint32_t)0x00000002U) /* Bit[1] STANDBY flag.*/ + +/******** Bit definition for PWR_M4CTRL2 register ********/ +#define PWR_M4CTRL2_MEM_CNTVAL ((uint32_t)0x7E000000U) /* Bit[30:25] counter value for M4 memory power ready count down*/ +#define PWR_M4CTRL2_MEM_CNTVAL_0 ((uint32_t)0x02000000U) /* Bit25*/ +#define PWR_M4CTRL2_MEM_CNTVAL_1 ((uint32_t)0x04000000U) /* Bit26*/ +#define PWR_M4CTRL2_MEM_CNTVAL_2 ((uint32_t)0x08000000U) /* Bit27*/ +#define PWR_M4CTRL2_MEM_CNTVAL_3 ((uint32_t)0x10000000U) /* Bit28*/ +#define PWR_M4CTRL2_MEM_CNTVAL_4 ((uint32_t)0x20000000U) /* Bit29*/ +#define PWR_M4CTRL2_MEM_CNTVAL_5 ((uint32_t)0x40000000U) /* Bit30*/ + +#define PWR_M4CTRL2_PWR_CNTVAL ((uint32_t)0x01FE0000U) /* Bit[24:17] counter value for CM4 logic power ready count down*/ +#define PWR_M4CTRL2_PWR_CNTVAL_0 ((uint32_t)0x00020000U) /* Bit17*/ +#define PWR_M4CTRL2_PWR_CNTVAL_1 ((uint32_t)0x00040000U) /* Bit18*/ +#define PWR_M4CTRL2_PWR_CNTVAL_2 ((uint32_t)0x00080000U) /* Bit19*/ +#define PWR_M4CTRL2_PWR_CNTVAL_3 ((uint32_t)0x00100000U) /* Bit20*/ +#define PWR_M4CTRL2_PWR_CNTVAL_4 ((uint32_t)0x00200000U) /* Bit21*/ +#define PWR_M4CTRL2_PWR_CNTVAL_5 ((uint32_t)0x00400000U) /* Bit22*/ +#define PWR_M4CTRL2_PWR_CNTVAL_6 ((uint32_t)0x00800000U) /* Bit23*/ +#define PWR_M4CTRL2_PWR_CNTVAL_7 ((uint32_t)0x01000000U) /* Bit24*/ + +#define PWR_M4CTRL2_MEM_RDYMD ((uint32_t)0x00018000U) /* Bit[16:15] Selected the way of check TCM power ready for CM4 domain*/ +#define PWR_M4CTRL2_MEM_RDYMD_0 ((uint32_t)0x00008000U) /* Bit15*/ +#define PWR_M4CTRL2_MEM_RDYMD_1 ((uint32_t)0x00010000U) /* Bit16*/ + +#define PWR_M4CTRL2_PWR_RDYMD ((uint32_t)0x00006000U) /* Bit[14:13] Selected the way of check power ready for CM4 domain*/ +#define PWR_M4CTRL2_PWR_RDYMD_0 ((uint32_t)0x00002000U) /* Bit13*/ +#define PWR_M4CTRL2_PWR_RDYMD_1 ((uint32_t)0x00004000U) /* Bit14*/ + +#define PWR_M4CTRL2_NRST_WAUPEN ((uint32_t)0x00000800U) /* Bit[11] NRST wakeup event enable in standby mode for M4 core*/ +#define PWR_M4CTRL2_RET_PSWACK1 ((uint32_t)0x00000400U) /* Bit[10] M4 retention power switch ACK1 used as ENA2 enanle for dual-input-header*/ +#define PWR_M4CTRL2_DMN_PSWACK1 ((uint32_t)0x00000200U) /* Bit[9] M4 Domain power switch ACK1 used as ENA2 enanle for dual-input-header*/ +#define PWR_M4CTRL2_RTC_ALMWUPEN ((uint32_t)0x00000100U) /* Bit[8] RTC_ALARM wakeup enable in standby mode for M4 core*/ +#define PWR_M4CTRL2_BSRSTBRET ((uint32_t)0x00000004U) /* Bit[2] Backup SRAM retention enable in STANDBY mode*/ +#define PWR_M4CTRL2_BSRVBRET ((uint32_t)0x00000002U) /* Bit[1] Backup SRAM retention enable in VBAT mode*/ +#define PWR_M4CTRL2_STOP2EN ((uint32_t)0x00000001U) /* Bit[0] M4 core STOP2 mode enable*/ + +/******** Bit definition for PWR_SYSCTRL1 register ********/ +#define PWR_SYSCTRL1_DCDC_VSELKEY ((uint32_t)0xF0000000U) /* Bit[31:28] DCDC_VSELKEY_UNLOCK key*/ +#define PWR_SYSCTRL1_DCDC_VSELKEY_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define PWR_SYSCTRL1_DCDC_VSELKEY_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define PWR_SYSCTRL1_DCDC_VSELKEY_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define PWR_SYSCTRL1_DCDC_VSELKEY_3 ((uint32_t)0x80000000U) /* Bit31*/ + +#define PWR_SYSCTRL1_NRST_DGFCNT ((uint32_t)0x0FFF0000U) /* Bit[27:16] Digtal Glitch Filter on NRST filtered pulse width configuration*/ + +#define PWR_SYSCTRL1_NRST_DGFBP ((uint32_t)0x00008000U) /* Bit[15] Bypass digital glitch Filter on NRST*/ +#define PWR_SYSCTRL1_AGF_STBWUPPBP ((uint32_t)0x00002000U) /* Bit[13] Bypass analog glitch filter on stanby wakeup pads*/ +#define PWR_SYSCTRL1_AGF_DTASGBP ((uint32_t)0x00001000U) /* Bit[12] Bypass analog glitch filter on some Digtal to Analog Enable singnals*/ +#define PWR_SYSCTRL1_AGF_ARSTOBP ((uint32_t)0x00000800U) /* Bit[11] Bypass analog glitch filter on Analog Reset outputs*/ +#define PWR_SYSCTRL1_VDDDRET_PSWACK1 ((uint32_t)0x00000400U) /* Bit[10] Retention domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SYSCTRL1_VDDDM_PSWACK1 ((uint32_t)0x00000200U) /* Bit[9] VDDD Main Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SYSCTRL1_DBKP ((uint32_t)0x00000100U) /* Bit[8] Disable write protection for the backup domain*/ +#define PWR_SYSCTRL1_PVDEN ((uint32_t)0x00000010U) /* Bit[4] Power Voltage Detector (PVD) Enable*/ +#define PWR_SYSCTRL1_AVDEN ((uint32_t)0x00000008U) /* Bit[3] Anolog Voltage Detector (AVD) Enable.*/ +#define PWR_SYSCTRL1_SW3EN ((uint32_t)0x00000002U) /* Bit[1] VDDD Backup from Backup LDO*/ +#define PWR_SYSCTRL1_BKPLDOEN ((uint32_t)0x00000001U) /* Bit[0] Backup LDO enable*/ + +/******** Bit definition for PWR_SYSCTRLSTS register ********/ +#define PWR_SYSCTRLSTS_PVDO ((uint32_t)0x00000010U) /* Bit[4] PVD output.*/ +#define PWR_SYSCTRLSTS_AVDO ((uint32_t)0x00000008U) /* Bit[3] AVD output.*/ +#define PWR_SYSCTRLSTS_OTP_PWRRDY ((uint32_t)0x00000002U) /* Bit[1] OTP Power Ready*/ +#define PWR_SYSCTRLSTS_DCDC_BPF ((uint32_t)0x00000001U) /* Bit[0] Working mode is bypass or not for DCDC*/ + +/******** Bit definition for PWR_SYSCTRL2 register ********/ +#define PWR_SYSCTRL2_OTP_LPCLKDIV ((uint32_t)0x07000000U) /* Bit[26:24] Clock dividor of pwr_sys_clk for OTP low power mode cotrol*/ +#define PWR_SYSCTRL2_OTP_LPCLKDIV_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define PWR_SYSCTRL2_OTP_LPCLKDIV_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define PWR_SYSCTRL2_OTP_LPCLKDIV_2 ((uint32_t)0x04000000U) /* Bit26*/ + +#define PWR_SYSCTRL2_OTP_FRCSTB ((uint32_t)0x00800000U) /* Bit[23] OTP_FRCDSTB and OTP_FRCSTB decide the OTP power state in all system power modes*/ +#define PWR_SYSCTRL2_OTP_FRCDSTB ((uint32_t)0x00400000U) /* Bit[22] */ + +#define PWR_SYSCTRL2_OTP_STB_INSTP0 ((uint32_t)0x00200000U) /* Bit[21] OTP_DSTB_INSTP0 and OTP_STB_INSTP0 decide the OTP power state in system STOP0 mode*/ +#define PWR_SYSCTRL2_OTP_DSTB_INSTP0 ((uint32_t)0x00100000U) /* Bit[20] */ + +#define PWR_SYSCTRL2_OTP_STB_INSTP2 ((uint32_t)0x00080000U) /* Bit[19] OTP_DSTB_INSTP2 and OTP_STB_INSTP2 decide the OTP power state in system STOP2 mode*/ +#define PWR_SYSCTRL2_OTP_DSTB_INSTP2 ((uint32_t)0x00040000U) /* Bit[18] */ + +#define PWR_SYSCTRL2_EXTI_MASKRSTEN ((uint32_t)0x00020000U) /* Bit[17] When PWR start to power down CPUn to standby mode, EXTI's IMRn/EMRn register will be reset \ + and no interrupt/event will be send to CPU from exti*/ + +#define PWR_SYSCTRL2_VDDDM_RDYMD ((uint32_t)0x00010000U) /* Bit[16] PWR use dpts4 rdy(feedback from power switch chain) + 2cycle LSI delay as main domain ready*/ +#define PWR_SYSCTRL2_PVS_STBRET ((uint32_t)0x00002000U) /* Bit[13] IO in Retention domain in Retention mode in STANDBY*/ +#define PWR_SYSCTRL2_BKLDO_RUNOFFEN ((uint32_t)0x00000800U) /* Bit[11] Eanble/disable of BKLDO*/ +#define PWR_SYSCTRL2_BG_CTRLEN ((uint32_t)0x00000400U) /* Bit[10] BG is controlled by pwr*/ +#define PWR_SYSCTRL2_SRAM_CTRLEN ((uint32_t)0x00000200U) /* Bit[9] BKP SRAM Power control interface is controlled by pwr*/ +#define PWR_SYSCTRL2_PVS_RETCTRLEN ((uint32_t)0x00000100U) /* Bit[8] PV sense retation on/off is controlled by pwr.*/ +#define PWR_SYSCTRL2_PVS_CTRLEN ((uint32_t)0x00000080U) /* Bit[7] PV sense is controlled by pwr*/ +#define PWR_SYSCTRL2_HSE_CTRLEN ((uint32_t)0x00000040U) /* Bit[6] HSE is controlled by pwr*/ +#define PWR_SYSCTRL2_HSI_CTRLEN ((uint32_t)0x00000020U) /* Bit[5] HSI is controlled by pwr*/ +#define PWR_SYSCTRL2_PLL_CTRLEN ((uint32_t)0x00000010U) /* Bit[4] PLL is controlled by pwr*/ +#define PWR_SYSCTRL2_MR_STBOFFEN ((uint32_t)0x00000002U) /* Bit[1] MR off enable when system enters into Standby mode*/ + +/******** Bit definition for PWR_SYSCTRL3 register ********/ +#define PWR_SYSCTRL3_HSC2_PSWACK1 ((uint32_t)0x00400000U) /* Bit[22] HSC2 Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SYSCTRL3_HSC1_PSW_ACK1 ((uint32_t)0x00200000U) /* Bit[21] HSC1 Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SYSCTRL3_GRC_PSWACK1 ((uint32_t)0x00100000U) /* Bit[20] GRAPHIC Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SYSCTRL3_HSC2_PWRRDY ((uint32_t)0x00040000U) /* Bit[18] HSC2 power domain ready flag*/ +#define PWR_SYSCTRL3_HSC1_PWRRDY ((uint32_t)0x00020000U) /* Bit[17] HSC1 power domain ready flag*/ +#define PWR_SYSCTRL3_GRC_PWRRDY ((uint32_t)0x00010000U) /* Bit[16] GRAPHIC power domain ready flag*/ +#define PWR_SYSCTRL3_HSC2_ISNEN ((uint32_t)0x00000400U) /* Bit[10] HSC2 power domain isolation signal*/ +#define PWR_SYSCTRL3_HSC1_ISNEN ((uint32_t)0x00000200U) /* Bit[9] HSC1 power domain isolation signal*/ +#define PWR_SYSCTRL3_GRC_ISNEN ((uint32_t)0x00000100U) /* Bit[8] GRAPHIC power domain isolation signal*/ +#define PWR_SYSCTRL3_HSC2_FUCEN ((uint32_t)0x00000040U) /* Bit[6] Function mode enable for HSC2 domain*/ +#define PWR_SYSCTRL3_HSC1_FUCEN ((uint32_t)0x00000020U) /* Bit[5] Function mode enable for HSC1 domain*/ +#define PWR_SYSCTRL3_GRC_FUCEN ((uint32_t)0x00000010U) /* Bit[4] Function mode enable for GRAPHIC domain*/ +#define PWR_SYSCTRL3_HSC2_PWREN ((uint32_t)0x00000004U) /* Bit[2] HSC2 domain power enable*/ +#define PWR_SYSCTRL3_HSC1_PWREN ((uint32_t)0x00000002U) /* Bit[1] HSC1 domain power enable*/ +#define PWR_SYSCTRL3_GRC_PWREN ((uint32_t)0x00000001U) /* Bit[0] GRPAHIC domain power enable*/ + +/******** Bit definition for PWR_SYSCTRL4 register ********/ +#define PWR_SYSCTRL4_MR_LPVSELEN ((uint32_t)0x20000000U) /* Bit[29] Enable targeting MR voltage output in low power mode*/ + +#define PWR_SYSCTRL4_DCDC_LPVSEL_MASK ((uint32_t)0x0F000000U) /* Bit[27:24] Targeting dcdc voltage in low power mode*/ +#define PWR_SYSCTRL4_DCDC_LPVSEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define PWR_SYSCTRL4_DCDC_LPVSEL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define PWR_SYSCTRL4_DCDC_LPVSEL_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define PWR_SYSCTRL4_DCDC_LPVSEL_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define PWR_SYSCTRL4_VDDD_LPPORSEL_MASK ((uint32_t)0x00C00000U) /* Bit[23:22] VDDD por config in low power mode*/ +#define PWR_SYSCTRL4_VDDD_LPPORSEL_0 ((uint32_t)0x00400000U) /* Bit22*/ +#define PWR_SYSCTRL4_VDDD_LPPORSEL_1 ((uint32_t)0x00800000U) /* Bit23*/ + +#define PWR_SYSCTRL4_DCDC_LPPORVSEL ((uint32_t)0x003E0000U) /* Bit[21:17] DCDC POR voltage value 0.05V per step in low power mode*/ +#define PWR_SYSCTRL4_DCDC_LPPORVSEL_0 ((uint32_t)0x00020000U) /* Bit17*/ +#define PWR_SYSCTRL4_DCDC_LPPORVSEL_1 ((uint32_t)0x00040000U) /* Bit18*/ +#define PWR_SYSCTRL4_DCDC_LPPORVSEL_2 ((uint32_t)0x00080000U) /* Bit19*/ +#define PWR_SYSCTRL4_DCDC_LPPORVSEL_3 ((uint32_t)0x00100000U) /* Bit20*/ +#define PWR_SYSCTRL4_DCDC_LPPORVSEL_4 ((uint32_t)0x00200000U) /* Bit21*/ + +#define PWR_SYSCTRL4_BG_LPVREFVSEL ((uint32_t)0x00010000U) /* Bit[16] targeting aldo ref in low power mode*/ +#define PWR_SYSCTRL4_BG_VREFVSEL ((uint32_t)0x00008000U) /* Bit[15] targeting BG in low power mode*/ + +#define PWR_SYSCTRL4_VDDD_PORSEL ((uint32_t)0x00003000U) /* Bit[13:12] VDDD por config in low power mode*/ +#define PWR_SYSCTRL4_VDDD_PORSEL_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define PWR_SYSCTRL4_VDDD_PORSEL_1 ((uint32_t)0x00002000U) /* Bit13*/ + +#define PWR_SYSCTRL4_MLDO_LPOVSEL ((uint32_t)0x00000C00U) /* Bit[11:10] Output voltage of Main Regulator LDO option in SYS STOP2 and STANDBY mode*/ +#define PWR_SYSCTRL4_MLDO_LPOVSEL_0 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_SYSCTRL4_MLDO_LPOVSEL_1 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_SYSCTRL4_MLDO_OVSEL ((uint32_t)0x00000300U) /* Bit[9:8] Output voltage of Main Regulator LDO option in SYS RUN mode*/ +#define PWR_SYSCTRL4_MLDO_OVSEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_SYSCTRL4_MLDO_OVSEL_1 ((uint32_t)0x00000200U) /* Bit9*/ + +#define PWR_SYSCTRL4_DCDCFRCEN ((uint32_t)0x00000008U) /* Bit[3] DCDC is forcibly activated*/ +#define PWR_SYSCTRL4_DCDCEN ((uint32_t)0x00000004U) /* Bit[2] DCDC is activated*/ +#define PWR_SYSCTRL4_MLDOEN ((uint32_t)0x00000002U) /* Bit[1] LDO is forcibly activated*/ +#define PWR_SYSCTRL4_VCORESRC ((uint32_t)0x00000001U) /* Bit[0] VCORE/VDDD spupplied by external source*/ + +/******** Bit definition for PWR_BORCTRL register ********/ +#define PWR_BORCTRL_BORVSEL_MASK ((uint32_t)0x0000003EU) /* Bit[5:1] BOR voltage selelction*/ +#define PWR_BORCTRL_BORVSEL_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_BORCTRL_BORVSEL_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_BORCTRL_BORVSEL_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define PWR_BORCTRL_BORVSEL_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_BORCTRL_BORVSEL_4 ((uint32_t)0x00000020U) /* Bit5*/ + +#define PWR_BORCTRL_BOREN ((uint32_t)0x00000001U) /* Bit[0] BOR enable*/ + +/******** Bit definition for PWR_IPMEMCTRL register ********/ +#define PWR_IPMEMCTRL_ESC_PWREN ((uint32_t)0x00001000U) /* Bit[12] ESC memory power gate enable*/ +#define PWR_IPMEMCTRL_FMAC_PWREN ((uint32_t)0x00000800U) /* Bit[11] FMAC memory power gate enable*/ +#define PWR_IPMEMCTRL_SDMMC1_PWREN ((uint32_t)0x00000400U) /* Bit[10] SDMMC1 memory power gate enable*/ +#define PWR_IPMEMCTRL_USB1_PWREN ((uint32_t)0x00000200U) /* Bit[9] USB1 memory power gate enable*/ +#define PWR_IPMEMCTRL_ETH1_PWREN ((uint32_t)0x00000100U) /* Bit[8] ETH1 memory power gate enable*/ +#define PWR_IPMEMCTRL_SDMMC2_PWREN ((uint32_t)0x00000080U) /* Bit[7] SDMMC2 memory power gate enable*/ +#define PWR_IPMEMCTRL_USB2_PWREN ((uint32_t)0x00000040U) /* Bit[6] USB2 memory power gate enable*/ +#define PWR_IPMEMCTRL_ETH2_PWREN ((uint32_t)0x00000020U) /* Bit[5] ETH2 memory power gate enable*/ +#define PWR_IPMEMCTRL_DVP_PWREN ((uint32_t)0x00000010U) /* Bit[4] DVP memory power gate enable*/ +#define PWR_IPMEMCTRL_DSI_PWREN ((uint32_t)0x00000008U) /* Bit[3] DSI memory power gate enable*/ +#define PWR_IPMEMCTRL_JPEG_PWREN ((uint32_t)0x00000004U) /* Bit[2] JPEG memory power gate enable*/ +#define PWR_IPMEMCTRL_LCDC_PWREN ((uint32_t)0x00000002U) /* Bit[1] LCDC memory power gate enable*/ +#define PWR_IPMEMCTRL_GPU_PWREN ((uint32_t)0x00000001U) /* Bit[0] GPU memory power gate enable*/ + +/******** Bit definition for PWR_IPMEMCTRLSTS register ********/ +#define PWR_IPMEMCTRLSTS_AIP_MEMPWRRDY ((uint32_t)0x80000000U) /* Bit[31] ALL IP memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_ESC_PWRRDY ((uint32_t)0x00001000U) /* Bit[12] ESC memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_FMAC_PWRRDY ((uint32_t)0x00000800U) /* Bit[11] FMAC memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_SDMMC1_PWRRDY ((uint32_t)0x00000400U) /* Bit[10] SDMMC1 memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_USB1_PWRRDY ((uint32_t)0x00000200U) /* Bit[9] USB1 memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_ETH1_PWRRDY ((uint32_t)0x00000100U) /* Bit[8] ETH1 memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_SDMMC2_PWRRDY ((uint32_t)0x00000080U) /* Bit[7] SDMMC2 memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_USB2_PWRRDY ((uint32_t)0x00000040U) /* Bit[6] USB2 memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_ETH2_PWRRDY ((uint32_t)0x00000020U) /* Bit[5] ETH2 memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_DVP_PWRRDY ((uint32_t)0x00000010U) /* Bit[4] DVP memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_DSI_PWRRDY ((uint32_t)0x00000008U) /* Bit[3] DSI memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_JPEG_PWRRDY ((uint32_t)0x00000004U) /* Bit[2] JPEG memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_LCDC_PWRRDY ((uint32_t)0x00000002U) /* Bit[1] LCDC memory power ready flag*/ +#define PWR_IPMEMCTRLSTS_GPU_PWRRDY ((uint32_t)0x00000001U) /* Bit[0] GPU memory power ready flag*/ + +/******** Bit definition for PWR_M7MEMLPCTRL register ********/ +#define PWR_M7MEMLPCTRL_MEM_PGCFG ((uint32_t)0x0000000CU) /* Bit[3:2] Memory power gate sequence control*/ +#define PWR_M7MEMLPCTRL_MEM_PGCFG_0 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_M7MEMLPCTRL_MEM_PGCFG_1 ((uint32_t)0x00000008U) /* Bit3*/ +#define PWR_M7MEMLPCTRL_MEM_RETSTP0EN ((uint32_t)0x00000002U) /* Bit[1] */ +#define PWR_M7MEMLPCTRL_MEM_PGENSTP0 ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for PWR_M7MEMLPSTS register ********/ +#define PWR_M7MEMLPSTS_TCMRDY ((uint32_t)0x80000000U) /* Bit[31] All enabled TCM memory power ready flag*/ + +/******** Bit definition for PWR_M7TCMPG0 register ********/ +#define PWR_M7TCMPG0_M7TCM_SWPG0 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Software control to power gate TCM memories*/ +#define PWR_M7TCMPG0_M7TCM_SWPG0_0 ((uint32_t)0x00000001U) /* Bit0 range :0x20000000U ?C 0x20003FFFU*/ +#define PWR_M7TCMPG0_M7TCM_SWPG0_1 ((uint32_t)0x00000002U) /* Bit1 range :0x20004000U ?C 0x20007FFFU*/ +#define PWR_M7TCMPG0_M7TCM_SWPG0_2 ((uint32_t)0x00000004U) /* Bit2 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_3 ((uint32_t)0x00000008U) /* Bit3 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_4 ((uint32_t)0x00000010U) /* Bit4 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_5 ((uint32_t)0x00000020U) /* Bit5 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_6 ((uint32_t)0x00000040U) /* Bit6 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_7 ((uint32_t)0x00000080U) /* Bit7 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_8 ((uint32_t)0x00000100U) /* Bit8 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_9 ((uint32_t)0x00000200U) /* Bit9 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_10 ((uint32_t)0x00000400U) /* Bit10 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_11 ((uint32_t)0x00000800U) /* Bit11 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_12 ((uint32_t)0x00001000U) /* Bit12 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_13 ((uint32_t)0x00002000U) /* Bit13 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_14 ((uint32_t)0x00004000U) /* Bit14 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_15 ((uint32_t)0x00008000U) /* Bit15 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_16 ((uint32_t)0x00010000U) /* Bit16 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_17 ((uint32_t)0x00020000U) /* Bit17 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_18 ((uint32_t)0x00040000U) /* Bit18 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_19 ((uint32_t)0x00080000U) /* Bit19 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_20 ((uint32_t)0x00100000U) /* Bit20 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_21 ((uint32_t)0x00200000U) /* Bit21 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_22 ((uint32_t)0x00400000U) /* Bit22 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_23 ((uint32_t)0x00800000U) /* Bit23 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_24 ((uint32_t)0x01000000U) /* Bit24 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_25 ((uint32_t)0x02000000U) /* Bit25 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_26 ((uint32_t)0x04000000U) /* Bit26 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_27 ((uint32_t)0x08000000U) /* Bit27 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_28 ((uint32_t)0x10000000U) /* Bit28 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_29 ((uint32_t)0x20000000U) /* Bit29 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_30 ((uint32_t)0x40000000U) /* Bit30 .... */ +#define PWR_M7TCMPG0_M7TCM_SWPG0_31 ((uint32_t)0x80000000U) /* Bit31 range :0x2007FBFFU ?C 0x2007FFFFU*/ + +/******** Bit definition for PWR_M7TCMPG1 register ********/ +#define PWR_M7TCMPG1_M7TCM_SWPG1 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Software control to power gate TCM memories*/ +#define PWR_M7TCMPG1_M7TCM_SWPG1_0 ((uint32_t)0x00000001U) /* Bit0 range :0x20080000U ?C 0x20083FFFU*/ +#define PWR_M7TCMPG1_M7TCM_SWPG1_1 ((uint32_t)0x00000002U) /* Bit1 range :0x20084000U ?C 0x20087FFFU*/ +#define PWR_M7TCMPG1_M7TCM_SWPG1_2 ((uint32_t)0x00000004U) /* Bit2 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_3 ((uint32_t)0x00000008U) /* Bit3 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_4 ((uint32_t)0x00000010U) /* Bit4 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_5 ((uint32_t)0x00000020U) /* Bit5 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_6 ((uint32_t)0x00000040U) /* Bit6 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_7 ((uint32_t)0x00000080U) /* Bit7 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_8 ((uint32_t)0x00000100U) /* Bit8 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_9 ((uint32_t)0x00000200U) /* Bit9 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_10 ((uint32_t)0x00000400U) /* Bit10 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_11 ((uint32_t)0x00000800U) /* Bit11 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_12 ((uint32_t)0x00001000U) /* Bit12 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_13 ((uint32_t)0x00002000U) /* Bit13 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_14 ((uint32_t)0x00004000U) /* Bit14 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_15 ((uint32_t)0x00008000U) /* Bit15 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_16 ((uint32_t)0x00010000U) /* Bit16 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_17 ((uint32_t)0x00020000U) /* Bit17 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_18 ((uint32_t)0x00040000U) /* Bit18 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_19 ((uint32_t)0x00080000U) /* Bit19 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_20 ((uint32_t)0x00100000U) /* Bit20 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_21 ((uint32_t)0x00200000U) /* Bit21 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_22 ((uint32_t)0x00400000U) /* Bit22 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_23 ((uint32_t)0x00800000U) /* Bit23 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_24 ((uint32_t)0x01000000U) /* Bit24 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_25 ((uint32_t)0x02000000U) /* Bit25 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_26 ((uint32_t)0x04000000U) /* Bit26 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_27 ((uint32_t)0x08000000U) /* Bit27 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_28 ((uint32_t)0x10000000U) /* Bit28 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_29 ((uint32_t)0x20000000U) /* Bit29 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_30 ((uint32_t)0x40000000U) /* Bit30 .... */ +#define PWR_M7TCMPG1_M7TCM_SWPG1_31 ((uint32_t)0x80000000U) /* Bit31 range :0x200FFBFFU ?C 0x200FFFFFU*/ + +/******** Bit definition for PWR_M7TCMRET1N0 register ********/ +#define PWR_M7TCMRET1N0_M7TCM_RET1CFG0 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/******** Bit definition for PWR_M7TCMRET1N1 register ********/ +#define PWR_M7TCMRET1N1_M7TCM_RET1CFG1 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/******** Bit definition for PWR_M7TCMRET2CFG0 register ********/ +#define PWR_M7TCMRET2CFG0_M7TCM_RET2CFG0 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/******** Bit definition for PWR_M7TCM_RET2CFG1 register ********/ +#define PWR_M7TCM_RET2CFG1_M7TCM_RET2CFG1 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/******** Bit definition for PWR_M7TCMPRDY0 register ********/ +#define PWR_M7TCMPRDY0_TCM_PRDY0 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/******** Bit definition for PWR_M7TCMPRDY1 register ********/ +#define PWR_M7TCMPRDY1_TCM_PRDY1 ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/******** Bit definition for PWR_M4MEMLPCTRL register ********/ +#define PWR_M4MEMLPCTRL_MEM_PGCFG ((uint32_t)0x0000000CU) /* Bit[3:2] Memory power gate sequence control*/ +#define PWR_M4MEMLPCTRL_MEM_PGCFG_0 ((uint32_t)0x00000004U) /* Bit2 */ +#define PWR_M4MEMLPCTRL_MEM_PGCFG_1 ((uint32_t)0x00000008U) /* Bit3 */ + +#define PWR_M4MEMLPCTRL_MEM_RETSTP0EN ((uint32_t)0x00000002U) /* Bit[1] */ +#define PWR_M4MEMLPCTRL_MEM_PGSTP0EN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for PWR_SYSMEMLPCTRL register ********/ +#define PWR_SYSMEMLPCTRL_ALLPRDY ((uint32_t)0x80000000U) /* Bit[31] All enabled system memory power ready flag*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM5S2_RET2N ((uint32_t)0x04000000U) /* Bit[26] System SRAM5S2 memory status control */ +#define PWR_SYSMEMLPCTRL_AHBSRAM5S2_RET1N ((uint32_t)0x02000000U) /* Bit[25] System SRAM5S2 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM5S1_RET2N ((uint32_t)0x01000000U) /* Bit[24] System SRAM5S1 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM5S1_RET1N ((uint32_t)0x00800000U) /* Bit[23] System SRAM5S1 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM4_RET2N ((uint32_t)0x00400000U) /* Bit[22] System SRAM4 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM4_RET1N ((uint32_t)0x00200000U) /* Bit[21] System SRAM4 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM3_RET2N ((uint32_t)0x00100000U) /* Bit[20] System SRAM3 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM3_RET1N ((uint32_t)0x00080000U) /* Bit[19] System SRAM3 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM2_RET2N ((uint32_t)0x00040000U) /* Bit[18] System SRAM2 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM2_RET1N ((uint32_t)0x00020000U) /* Bit[17] System SRAM2 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM1_RET2N ((uint32_t)0x00010000U) /* Bit[16] System SRAM1 memory status control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM1_RET1N ((uint32_t)0x00008000U) /* Bit[15] System SRAM1 memory status control*/ +#define PWR_SYSMEMLPCTRL_AXISRAM_RET2N ((uint32_t)0x00004000U) /* Bit[14] System memory status control*/ +#define PWR_SYSMEMLPCTRL_AXISRAM_RET1N ((uint32_t)0x00002000U) /* Bit[13] System memory status control*/ +#define PWR_SYSMEMLPCTRL_MEM_RETSTP0EN ((uint32_t)0x00000200U) /* Bit[9] all system memory control*/ +#define PWR_SYSMEMLPCTRL_MEM_PGSTP0EN ((uint32_t)0x00000100U) /* Bit[8] all system memory control*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM5S2PG ((uint32_t)0x00000040U) /* Bit[6] Software control to power gate AHB SRAM5S2 in SYS RUN mode*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM5S1_PG ((uint32_t)0x00000020U) /* Bit[5] Software control to power gate AHB SRAM5S1 in SYS RUN mode*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM4PG ((uint32_t)0x00000010U) /* Bit[4] Software control to power gate AHB SRAM4 in SYS RUN mode*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM3_PG ((uint32_t)0x00000008U) /* Bit[3] Software control to power gate AHB SRAM3 in SYS RUN mode*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM2_PG ((uint32_t)0x00000004U) /* Bit[2] Software control to power gate AHB SRAM2 in SYS RUN mode*/ +#define PWR_SYSMEMLPCTRL_AHBSRAM1_PG ((uint32_t)0x00000002U) /* Bit[1] Software control to power gate AHB SRAM1 in SYS RUN mode*/ +#define PWR_SYSMEMLPCTRL_AXISRAM_PG ((uint32_t)0x00000001U) /* Bit[0] Software control to power gate AXI SRAM in SYS RUN mode*/ + +/******** Bit definition for PWR_SHRTIMCTRL register ********/ +#define PWR_SHRTIMCTRL_SHRA_PSWACK1 ((uint32_t)0x00100000U) /* Bit[20] SHRTIM AFE Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SHRTIMCTRL_SHRA_PRDY ((uint32_t)0x00080000U) /* Bit[19] SHRTIM AFE power domain ready flag*/ +#define PWR_SHRTIMCTRL_SHRA_ISNEN ((uint32_t)0x00040000U) /* Bit[18] SHRTIM AFE power domain isolation signal*/ +#define PWR_SHRTIMCTRL_SHRA_FUCEN ((uint32_t)0x00020000U) /* Bit[17] Function mode enable for SHRTIM AFE*/ +#define PWR_SHRTIMCTRL_SHRA_PWREN ((uint32_t)0x00010000U) /* Bit[16] SHRTIM AFE power gate enable*/ +#define PWR_SHRTIMCTRL_SHR2_PSWACK1 ((uint32_t)0x00001000U) /* Bit[12] HRTIM2 Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SHRTIMCTRL_SHR2_PRDY ((uint32_t)0x00000800U) /* Bit[11] SHRTIM2 power domain ready flag*/ +#define PWR_SHRTIMCTRL_SHR2_ISNEN ((uint32_t)0x00000400U) /* Bit[10] SHRTIM2 power domain isolation signal*/ +#define PWR_SHRTIMCTRL_SHR2_FUCEN ((uint32_t)0x00000200U) /* Bit[9] Function mode enable for SHRTIM2 */ +#define PWR_SHRTIMCTRL_SHR2_PWREN ((uint32_t)0x00000100U) /* Bit[8] SHRTIM2 power gate enable*/ +#define PWR_SHRTIMCTRL_SHR1_PSWACK1 ((uint32_t)0x00000010U) /* Bit[4] HRTIM1 Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_SHRTIMCTRL_SHR1_PRDY ((uint32_t)0x00000008U) /* Bit[3] SHRTIM1 power domain ready flag*/ +#define PWR_SHRTIMCTRL_SHR1_ISNEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM1 power domain isolation signal*/ +#define PWR_SHRTIMCTRL_SHR1_FUCEN ((uint32_t)0x00000002U) /* Bit[1] Function mode enable for SHRTIM1 */ +#define PWR_SHRTIMCTRL_SHR1_PWREN ((uint32_t)0x00000001U) /* Bit[0] SHRTIM1 power gate enable*/ + +/******** Bit definition for PWR_MDMACTRL register ********/ +#define PWR_MDMACTRL_MDMA_PSWACK1 ((uint32_t)0x00000010U) /* Bit[4] MDMA Domain power switch ACK1 used as ENA2 for dual-input-header*/ +#define PWR_MDMACTRL_MDMA_PRDY ((uint32_t)0x00000008U) /* Bit[3] MDMA power domain ready flag*/ +#define PWR_MDMACTRL_MDMA_ISNEN ((uint32_t)0x00000004U) /* Bit[2] MDMA power domain isolation signal*/ +#define PWR_MDMACTRL_MDMA_FUCEN ((uint32_t)0x00000002U) /* Bit[1] Function mode enable for MDMA*/ +#define PWR_MDMACTRL_MDMA_PWREN ((uint32_t)0x00000001U) /* Bit[0] MDMA power gate enable*/ + +/******** Bit definition for PWR_ESCCTRL register ********/ +#define PWR_ESCCTRL_ESC_PSWACK1 ((uint32_t)0x00000010U) /* Bit[4] ESC Domain power switch ACK1 used as ENA2 for dual-input-header */ +#define PWR_ESCCTRL_ESC_PRDY ((uint32_t)0x00000008U) /* Bit[3] ESC power domain ready flag*/ +#define PWR_ESCCTRL_ESC_ISNEN ((uint32_t)0x00000004U) /* Bit[2] ESC power domain isolation signal*/ +#define PWR_ESCCTRL_ESC_FUCEN ((uint32_t)0x00000002U) /* Bit[1] Function mode enable for ESC*/ +#define PWR_ESCCTRL_ESC_PWREN ((uint32_t)0x00000001U) /* Bit[0] ESC power gate enable*/ + +/******** Bit definition for PWR_DBGPROB0 register ********/ +#define PWR_DBGPROB0_DBG_PRO1 ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set 1*/ + +#define PWR_DBGPROB0_DBG_PRO0 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set 0*/ + +/******** Bit definition for PWR_DBGPROB1 register ********/ +#define PWR_DBGPROB1_DBG_PRO3 ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set 3*/ + +#define PWR_DBGPROB1_DBG_PRO2 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set 2*/ + +/******** Bit definition for PWR_DBGPRO2 register ********/ +#define PWR_DBGPRO2_DBG_PRO5 ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set 5*/ + +#define PWR_DBGPRO2_DBG_PRO4 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set 4*/ + +/******** Bit definition for PWR_DBGPRO3 register ********/ +#define PWR_DBGPRO3_DBG_PRO7 ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set 5*/ + +#define PWR_DBGPRO3_DBG_PRO6 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set 6*/ + +/******** Bit definition for PWR_DBGPRO4 register ********/ +#define PWR_DBGPRO4_DBG_PRO9 ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set 9*/ + +#define PWR_DBGPRO4_DBG_PRO8 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set 8*/ + +/******** Bit definition for PWR_DBGPRO5 register ********/ +#define PWR_DBGPRO5_DBG_PROB ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set B*/ + +#define PWR_DBGPRO5_DBG_PROA ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set A*/ + +/******** Bit definition for PWR_DBGPRO6 register ********/ +#define PWR_DBGPRO6_DBG_PROD ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set D*/ + +#define PWR_DBGPRO6_DBG_PROC ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set C*/ + +/******** Bit definition for PWR_DBGPRO7 register ********/ +#define PWR_DBGPRO7_DBG_PROF ((uint32_t)0xFFFF0000U) /* Bit[31:16] Debug probe observation to PWR interanl signals set F*/ + +#define PWR_DBGPRO7_DBG_PROE ((uint32_t)0x0000FFFFU) /* Bit[15:0] Debug probe observation to PWR interanl signals set E*/ + +/******** Bit definition for PWR_DBGPROBCTRL register ********/ +#define PWR_DBGPROBCTRL_PROB_SEL_MASK ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define PWR_DBGPROBCTRL_PROB_SEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_DBGPROBCTRL_PROB_SEL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_DBGPROBCTRL_PROB_SEL_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_DBGPROBCTRL_PROB_SEL_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCRETCTRL1 register ********/ +#define PWR_EMCRETCTRL1_RETGBxDET ((uint32_t)0x00000F00U) /* Bit[11:8] RET domain EMC GBx detection enable*/ +#define PWR_EMCRETCTRL1_RETGBxDET_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETCTRL1_RETGBxDET_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETCTRL1_RETGBxDET_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_EMCRETCTRL1_RETGBxDET_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_EMCRETCTRL1_RETGBNxDET ((uint32_t)0x000000F0U) /* Bit[7:4] RET domain EMC GBNx detection enable*/ +#define PWR_EMCRETCTRL1_RETGBNxDET_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETCTRL1_RETGBNxDET_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETCTRL1_RETGBNxDET_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define PWR_EMCRETCTRL1_RETGBNxDET_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define PWR_EMCRETCTRL1_RETCLPxDET ((uint32_t)0x0000000FU) /* Bit[3:0] RET domain EMC Clampx detection enable*/ +#define PWR_EMCRETCTRL1_RETCLPxDET_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETCTRL1_RETCLPxDET_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETCTRL1_RETCLPxDET_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_EMCRETCTRL1_RETCLPxDET_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCCTRLSTS1 register ********/ +#define PWR_EMCCTRLSTS1_EMCFCLR ((uint32_t)0x01000000U) /* Bit[24] Clear EMC Flag*/ + +#define PWR_EMCCTRLSTS1_RETGBxF ((uint32_t)0x00000F00U) /* Bit[11:8] RET Domain EMC GBx Flag*/ +#define PWR_EMCCTRLSTS1_RETGBxF_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCCTRLSTS1_RETGBxF_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCCTRLSTS1_RETGBxF_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_EMCCTRLSTS1_RETGBxF_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_EMCCTRLSTS1_RETGBNxF ((uint32_t)0x000000F0U) /* Bit[7:4] RET Domain EMC GBNx Flag*/ +#define PWR_EMCCTRLSTS1_RETGBNxF_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCCTRLSTS1_RETGBNxF_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCCTRLSTS1_RETGBNxF_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define PWR_EMCCTRLSTS1_RETGBNxF_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define PWR_EMCCTRLSTS1_RETCLPxF ((uint32_t)0x0000000FU) /* Bit[3:0] RET Domain EMC Clampx Flag*/ +#define PWR_EMCCTRLSTS1_RETCLPxF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCCTRLSTS1_RETCLPxF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCCTRLSTS1_RETCLPxF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_EMCCTRLSTS1_RETCLPxF_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCRETCTRL2 register ********/ +#define PWR_EMCRETCTRL2_RETGBxDET ((uint32_t)0x00000F00U) /* Bit[11:8] RET domain EMC GBx detection enable*/ +#define PWR_EMCRETCTRL2_RETGBxDET_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETCTRL2_RETGBxDET_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETCTRL2_RETGBxDET_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_EMCRETCTRL2_RETGBxDET_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_EMCRETCTRL2_RETGBNxDET ((uint32_t)0x000000F0U) /* Bit[7:4] RET domain EMC GBNx detection enable*/ +#define PWR_EMCRETCTRL2_RETGBNxDET_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETCTRL2_RETGBNxDET_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETCTRL2_RETGBNxDET_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define PWR_EMCRETCTRL2_RETGBNxDET_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define PWR_EMCRETCTRL2_RETCLPxDET ((uint32_t)0x0000000FU) /* Bit[3:0] RET domain EMC Clampx detection enable*/ +#define PWR_EMCRETCTRL2_RETCLPxDET_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETCTRL2_RETCLPxDET_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETCTRL2_RETCLPxDET_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_EMCRETCTRL2_RETCLPxDET_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCRETSTS2 register ********/ +#define PWR_EMCRETSTS2_RETGBxF ((uint32_t)0x00000F00U) /* Bit[11:8] RET Domain EMC GBx Flag*/ +#define PWR_EMCRETSTS2_RETGBxF_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETSTS2_RETGBxF_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETSTS2_RETGBxF_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_EMCRETSTS2_RETGBxF_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_EMCRETSTS2_RETGBNxF ((uint32_t)0x000000F0U) /* Bit[7:4] RET Domain EMC GBNx Flag*/ +#define PWR_EMCRETSTS2_RETGBNxF_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETSTS2_RETGBNxF_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETSTS2_RETGBNxF_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define PWR_EMCRETSTS2_RETGBNxF_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define PWR_EMCRETSTS2_RETCLPxF ((uint32_t)0x0000000FU) /* Bit[3:0] RET Domain EMC Clampx Flag*/ +#define PWR_EMCRETSTS2_RETCLPxF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETSTS2_RETCLPxF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETSTS2_RETCLPxF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_EMCRETSTS2_RETCLPxF_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCRETCTRL3 register ********/ +#define PWR_EMCRETCTRL3_RETGBxDET ((uint32_t)0x00000F00U) /* Bit[11:8] RET domain EMC GBx detection enable*/ +#define PWR_EMCRETCTRL3_RETGBxDET_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETCTRL3_RETGBxDET_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETCTRL3_RETGBxDET_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_EMCRETCTRL3_RETGBxDET_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_EMCRETCTRL3_RETGBNxDET ((uint32_t)0x000000F0U) /* Bit[7:4] RET domain EMC GBNx detection enable*/ +#define PWR_EMCRETCTRL3_RETGBNxDET_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETCTRL3_RETGBNxDET_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETCTRL3_RETGBNxDET_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define PWR_EMCRETCTRL3_RETGBNxDET_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define PWR_EMCRETCTRL3_RETCLPxDET ((uint32_t)0x0000000FU) /* Bit[3:0] RET domain EMC Clampx detection enable*/ +#define PWR_EMCRETCTRL3_RETCLPxDET_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETCTRL3_RETCLPxDET_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETCTRL3_RETCLPxDET_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_EMCRETCTRL3_RETCLPxDET_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCRETSTS3 register ********/ +#define PWR_EMCRETSTS3_RETGBF ((uint32_t)0x00000F00U) /* Bit[11:8] RET Domain EMC GBx Flag*/ +#define PWR_EMCRETSTS3_RETGBF_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETSTS3_RETGBF_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETSTS3_RETGBF_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define PWR_EMCRETSTS3_RETGBF_3 ((uint32_t)0x00000800U) /* Bit11*/ + +#define PWR_EMCRETSTS3_RETGBNF ((uint32_t)0x000000F0U) /* Bit[7:4] RET Domain EMC GBNx Flag*/ +#define PWR_EMCRETSTS3_RETGBNF_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETSTS3_RETGBNF_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETSTS3_RETGBNF_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define PWR_EMCRETSTS3_RETGBNF_3 ((uint32_t)0x00000080U) /* Bit7*/ + +#define PWR_EMCRETSTS3_RETCLPF ((uint32_t)0x0000000FU) /* Bit[3:0] RET Domain EMC Clampx Flag*/ +#define PWR_EMCRETSTS3_RETCLPF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETSTS3_RETCLPF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETSTS3_RETCLPF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define PWR_EMCRETSTS3_RETCLPF_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for PWR_EMCRETCTRL4 register ********/ +#define PWR_EMCRETCTRL4_RETGBxDET ((uint32_t)0x00000700U) /* Bit[10:8] RET domain EMC GBx detection enable*/ +#define PWR_EMCRETCTRL4_RETGBxDET_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETCTRL4_RETGBxDET_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETCTRL4_RETGBxDET_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define PWR_EMCRETCTRL4_RETGBNxDET ((uint32_t)0x00000070U) /* Bit[6:4] RET domain EMC GBNx detection enable*/ +#define PWR_EMCRETCTRL4_RETGBNxDET_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETCTRL4_RETGBNxDET_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETCTRL4_RETGBNxDET_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define PWR_EMCRETCTRL4_RETCLPxDET ((uint32_t)0x00000007U) /* Bit[2:0] RET domain EMC Clampx detection enable*/ +#define PWR_EMCRETCTRL4_RETCLPxDET_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETCTRL4_RETCLPxDET_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETCTRL4_RETCLPxDET_2 ((uint32_t)0x00000004U) /* Bit2*/ + +/******** Bit definition for PWR_EMCRETSTS4 register ********/ +#define PWR_EMCRETSTS4_RETGBxF ((uint32_t)0x00000700U) /* Bit[10:8] RET Domain EMC GBx Flag*/ +#define PWR_EMCRETSTS4_RETGBxF_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define PWR_EMCRETSTS4_RETGBxF_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define PWR_EMCRETSTS4_RETGBxF_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define PWR_EMCRETSTS4_RETGBNxF ((uint32_t)0x00000070U) /* Bit[6:4] RET Domain EMC GBNx Flag*/ +#define PWR_EMCRETSTS4_RETGBNxF_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define PWR_EMCRETSTS4_RETGBNxF_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define PWR_EMCRETSTS4_RETGBNxF_2 ((uint32_t)0x00000040U) /* Bit6*/ + +#define PWR_EMCRETSTS4_RETCLPxF ((uint32_t)0x00000007U) /* Bit[2:0] RET Domain EMC Clampx Flag*/ +#define PWR_EMCRETSTS4_RETCLPxF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define PWR_EMCRETSTS4_RETCLPxF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define PWR_EMCRETSTS4_RETCLPxF_2 ((uint32_t)0x00000004U) /* Bit2*/ + +/******** Bit definition for PWR_EMCBKPCTRL register ********/ +#define PWR_EMCBKPCTRL_BKPCBDET ((uint32_t)0x00000100U) /* Bit[8] Backup domain EMC GB detection enable*/ +#define PWR_EMCBKPCTRL_BKPCBNDET ((uint32_t)0x00000010U) /* Bit[4] Backup domain EMC GBN detection enable*/ +#define PWR_EMCBKPCTRL_BKPCLPDET ((uint32_t)0x00000001U) /* Bit[0] Backup domain EMC Clamp detection enable*/ + +/******** Bit definition for PWR_EMCBKPSTS register ********/ +#define PWR_EMCBKPSTS_BKPCLR ((uint32_t)0x01000000U) /* Bit[24] Clear EMC BKP flag*/ +#define PWR_EMCBKPSTS_BKPGBF ((uint32_t)0x00000100U) /* Bit[8] Backup Domain EMC GB Flag*/ +#define PWR_EMCBKPSTS_BKPGBNF ((uint32_t)0x00000010U) /* Bit[4] Backup Domain EMC GBN Flag*/ +#define PWR_EMCBKPSTS_BKPCLPF ((uint32_t)0x00000001U) /* Bit[0] Backup Domain EMC Clamp Flag*/ + + + /******************************************************************************/ + /* */ + /* Low Power UART */ + /* */ + /******************************************************************************/ +/******** Bit definition for LPUART_STS register ********/ +#define LPUART_STS_TXFEF ((uint32_t)0x00010000U) /* Bit[16] transmit FIFO Empty Flag,1:FIFO is empty*/ +#define LPUART_STS_FE ((uint32_t)0x00008000U) /* Bit[15]frame error detected, 1:detect frame error*/ +#define LPUART_STS_IDLEF ((uint32_t)0x00004000U) /* Bit[14] IDLE frame detected,1:detect idle frame*/ +#define LPUART_STS_TXFNEF ((uint32_t)0x00002000U) /* Bit[13] transmit FIFO Non-Empty Flag,1:FIFO is non-empty*/ +#define LPUART_STS_TXFHFF ((uint32_t)0x00001000U) /* Bit[12] transmit FIFO Half Full Flag,1:FIFO is Half-Full*/ +#define LPUART_STS_TXFQFF ((uint32_t)0x00000800U) /* Bit[11] transmit FIFO quarter Full Flag,1:FIFO is three-QUAR-Full*/ +#define LPUART_STS_TXFFF ((uint32_t)0x00000400U) /* Bit[10] transmit FIFO Full Flag,1:FIFO is Full*/ +#define LPUART_STS_TXFOF ((uint32_t)0x00000200U) /* Bit[9] transmit FIFO Overflow Flag,1:FIFO is overflow */ +#define LPUART_STS_NEF ((uint32_t)0x00000100U) /* Bit[8] Noise error Flag,1:Noise is detected*/ +#define LPUART_STS_WUF ((uint32_t)0x00000080U) /* Bit[7] Wakeup from Stop mode Flag,1:Wakeup Events Detected*/ +#define LPUART_STS_CTSF ((uint32_t)0x00000040U) /* Bit[6] Clear to Send Flag,1:CTS Line is Set*/ +#define LPUART_STS_RXFNEF ((uint32_t)0x00000020U) /* Bit[5] FIFO Non-Empty Flag,1:FIFO is non-empty*/ +#define LPUART_STS_RXFHFF ((uint32_t)0x00000010U) /* Bit[4] FIFO Half Full Flag,1:FIFO is Half-Full*/ +#define LPUART_STS_RXFFF ((uint32_t)0x00000008U) /* Bit[3] FIFO Full Flag,1:FIFO is Full */ +#define LPUART_STS_RXFOF ((uint32_t)0x00000004U) /* Bit[2] FIFO Overflow Flag, 1:FIFO is overflow*/ +#define LPUART_STS_TXCF ((uint32_t)0x00000002U) /* Bit[1] TX Complete Flag,1:TX Transmission is Done*/ +#define LPUART_STS_PCEF ((uint32_t)0x00000001U) /* Bit[0] Parity Check Error Flag,1:TX/RX Parity Error is Detected*/ + +/******** Bit definition for LPUART_INTEN register ********/ +#define LPUART_INTEN_TXFEIEN ((uint32_t)0x00004000U) /* Bit[14] TXFIFO Empty Interrupt Enable */ +#define LPUART_INTEN_FEIEN ((uint32_t)0x00002000U) /* Bit[13] FRAME_ERROR Interrupt Enable*/ +#define LPUART_INTEN_IDLEFIEN ((uint32_t)0x00001000U) /* Bit[12] IDLE_FRAMEIE Interrupt Enable*/ +#define LPUART_INTEN_TXFNEIEN ((uint32_t)0x00000800U) /* Bit[11] TXFIFO Non-Empty Interrupt Enable*/ +#define LPUART_INTEN_TXFHFIEN ((uint32_t)0x00000400U) /* Bit[10] TXFIFO Half Full Interrupt Enable*/ +#define LPUART_INTEN_TXFQFIEN ((uint32_t)0x00000200U) /* Bit[9] TXFIFO QUAR Full Interrupt Enable*/ +#define LPUART_INTEN_TXFFIEN ((uint32_t)0x00000100U) /* Bit[8] TXFIFO Full Interrupt Enable*/ +#define LPUART_INTEN_TXFOIEN ((uint32_t)0x00000080U) /* Bit[7] TXFIFO Overflow Interrupt Enable*/ +#define LPUART_INTEN_WUIEN ((uint32_t)0x00000040U) /* Bit[6] Wakeup Interrupt Enable*/ +#define LPUART_INTEN_RXFNEIEN ((uint32_t)0x00000020U) /* Bit[5] FIFO Non-Empty Interrupt Enable*/ +#define LPUART_INTEN_RXFHFIEN ((uint32_t)0x00000010U) /* Bit[4] FIFO Half Full Interrupt Enable*/ +#define LPUART_INTEN_RXFFIEN ((uint32_t)0x00000008U) /* Bit[3] FIFO Full Interrupt Enable*/ +#define LPUART_INTEN_RXFOIEN ((uint32_t)0x00000004U) /* Bit[2] FIFO Overflow Interrupt Enable*/ +#define LPUART_INTEN_TXCIEN ((uint32_t)0x00000002U) /* Bit[1] TX Complete Interrupt Enable*/ +#define LPUART_INTEN_PCEIEN ((uint32_t)0x00000001U) /* Bit[0] Parity Check Error Interrupt Enable*/ + +/******** Bit definition for LPUART_CTRL register ********/ +#define LPUART_CTRL_RXEN ((uint32_t)0x01000000U) /* Bit[24] RX Enable,1 Enable RX*/ +#define LPUART_CTRL_RXNUMWU ((uint32_t)0x00F80000U) /* Bit[23:19] can be configured to receive how many bytes of data to wake */ +#define LPUART_CTRL_RXNUMWU_0 ((uint32_t)0x00080000U) /* Bit19*/ +#define LPUART_CTRL_RXNUMWU_1 ((uint32_t)0x00100000U) /* Bit20*/ +#define LPUART_CTRL_RXNUMWU_2 ((uint32_t)0x00200000U) /* Bit21*/ +#define LPUART_CTRL_RXNUMWU_3 ((uint32_t)0x00400000U) /* Bit22*/ +#define LPUART_CTRL_RXNUMWU_4 ((uint32_t)0x00800000U) /* Bit23*/ +#define LPUART_CTRL_FTXF ((uint32_t)0x00040000U) /* Bit[18] Flush transmit TXFIFO,1:Enable to Flush TXFIFO Content*/ +#define LPUART_CTRL_IDLEFEN ((uint32_t)0x00020000U) /* Bit[17] idle frame detect en,1:enable*/ +#define LPUART_CTRL_SSM ((uint32_t)0x00010000U) /* Bit[16] Specify the sampling method,1: 1 Sample*/ +#define LPUART_CTRL_WUS ((uint32_t)0x0000F000U) /* Bit[15:12] Wakeup Event Selection*/ +#define LPUART_CTRL_WUS_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define LPUART_CTRL_WUS_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define LPUART_CTRL_WUS_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define LPUART_CTRL_WUS_3 ((uint32_t)0x00008000U) /* Bit15*/ +#define LPUART_CTRL_RTSEN ((uint32_t)0x00000800U) /* Bit[11] Hardware Flow Control RX Enable,1: Enable*/ +#define LPUART_CTRL_CTSEN ((uint32_t)0x00000400U) /* Bit[10] Hardware Flow Control TX Enable,1: Enable*/ +#define LPUART_CTRL_RTST ((uint32_t)0x00000300U) /* Bit[9:8] RTS Threshold*/ +#define LPUART_CTRL_RTST_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define LPUART_CTRL_RTST_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define LPUART_CTRL_WUSTPEN ((uint32_t)0x00000080U) /* Bit[7] LPUART Wakeup Enable in Stop mode,1: Able to Wakeup in Stop mode*/ +#define LPUART_CTRL_DMARXEN ((uint32_t)0x00000040U) /* Bit[6] DMA RX Request Enable*/ +#define LPUART_CTRL_DMATXEN ((uint32_t)0x00000020U) /* Bit[5] DMA TX Request Enable*/ +#define LPUART_CTRL_LB ((uint32_t)0x00000010U) /* Bit[4] LoopBack Self-Test,1: Loop Back Test*/ +#define LPUART_CTRL_PC ((uint32_t)0x00000008U) /* Bit[3] Parity Control,1: Disabled Parity Bit*/ +#define LPUART_CTRL_FRXF ((uint32_t)0x00000004U) /* Bit[2] Flush Receiver FIFO,1: Enable to Flush FIFO Content*/ +#define LPUART_CTRL_TXEN ((uint32_t)0x00000002U) /* Bit[1] TX Enable,1: Enable TX*/ +#define LPUART_CTRL_PEN ((uint32_t)0x00000001U) /* Bit[0] Odd Parity Bit Enable,1: Odd Parity Bit*/ + +/******** Bit definition for LPUART_BRCFG1 register ********/ +#define LPUART_BRCFG1_BRP ((uint32_t)0x0000FFFFU) /* Bit[15:0] Baud Rate Parameter Register*/ +#define LPUART_BRCFG1_BRP_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define LPUART_BRCFG1_BRP_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define LPUART_BRCFG1_BRP_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define LPUART_BRCFG1_BRP_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define LPUART_BRCFG1_BRP_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define LPUART_BRCFG1_BRP_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define LPUART_BRCFG1_BRP_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define LPUART_BRCFG1_BRP_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define LPUART_BRCFG1_BRP_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define LPUART_BRCFG1_BRP_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define LPUART_BRCFG1_BRP_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define LPUART_BRCFG1_BRP_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define LPUART_BRCFG1_BRP_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define LPUART_BRCFG1_BRP_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define LPUART_BRCFG1_BRP_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define LPUART_BRCFG1_BRP_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for LPUART_TXDAT register ********/ +#define LPUART_TXDAT_DAT ((uint32_t)0x000000FFU) /* Bit[7:0] Write to Data Register for TXFIFO */ +#define LPUART_TXDAT_DAT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define LPUART_TXDAT_DAT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define LPUART_TXDAT_DAT_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define LPUART_TXDAT_DAT_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define LPUART_TXDAT_DAT_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define LPUART_TXDAT_DAT_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define LPUART_TXDAT_DAT_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define LPUART_TXDAT_DAT_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for LPUART_BRCFG2 register ********/ +#define LPUART_BRCFG2_MC ((uint32_t)0x000000FFU) /* Bit[7:0] Modulation Control Register For Baud Rate Error Correction at Low */ +#define LPUART_BRCFG2_MC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define LPUART_BRCFG2_MC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define LPUART_BRCFG2_MC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define LPUART_BRCFG2_MC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define LPUART_BRCFG2_MC_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define LPUART_BRCFG2_MC_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define LPUART_BRCFG2_MC_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define LPUART_BRCFG2_MC_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for LPUART_WUDAT1 register ********/ +#define LPUART_WUDAT1_DAT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Configure this register to detect byte or frame match for wakeup CPU from stop mode*/ + +/******** Bit definition for LPUART_WUDAT2 register ********/ +#define LPUART_WUDAT2_DAT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Configure this register to detect byte or frame match for wakeup CPU from stop mode*/ + +/******** Bit definition for LPUART_RXDAT register ********/ +#define LPUART_RXDAT_DAT ((uint32_t)0x000000FFU) /* Bit[7:0] Read this register to read RX data from RX FIFO*/ +#define LPUART_RXDAT_DAT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define LPUART_RXDAT_DAT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define LPUART_RXDAT_DAT_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define LPUART_RXDAT_DAT_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define LPUART_RXDAT_DAT_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define LPUART_RXDAT_DAT_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define LPUART_RXDAT_DAT_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define LPUART_RXDAT_DAT_7 ((uint32_t)0x00000080U) /* Bit7*/ + + + + /******************************************************************************/ + /* */ + /* Backup registers */ + /* */ + /******************************************************************************/ + + /******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + + /****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + + /******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + + /******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + + + +/*** Cylic Redundancy Check(CRC) Calculation Unit ***/ +/******************** Bit definition for CRC_DAT register ********************/ +#define CRC_DAT_DAT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC data */ + +/******************** Bit definition for CRC_IDAT register ********************/ +#define CRC_IDAT_IDAT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC independent data */ + +/******************** Bit definition for CRC_CTRL register ********************/ +#define CRC_CTRL_RESET ((uint32_t)0x00000001U) /* Bit[0] CRC calculation unit reset */ + +#define CRC_CTRL_BYTEENDIAN ((uint32_t)0x00000006U) /* Bit[2:1] CRC byte Endian bits[1:0] */ +#define CRC_CTRL_BYTEENDIAN_0 ((uint32_t)0x00000002U) /* Bit[1] CRC byte Endian bit0 */ +#define CRC_CTRL_BYTEENDIAN_1 ((uint32_t)0x00000004U) /* Bit[2] CRC byte Endian bit1 */ + +#define CRC_CTRL_POLYSIZE ((uint32_t)0x00000018U) /* Bit[4:3] CRC polynomial size bits[1:0] */ +#define CRC_CTRL_POLYSIZE_0 ((uint32_t)0x00000008U) /* Bit[3] CRC polynomial size bit0 */ +#define CRC_CTRL_POLYSIZE_1 ((uint32_t)0x00000010U) /* Bit[4] CRC polynomial size bit1 */ + +#define CRC_CTRL_REVIN ((uint32_t)0x00000060U) /* Bit[6:5] CRC input data reverse bits[1:0] */ +#define CRC_CTRL_REVIN_0 ((uint32_t)0x00000020U) /* Bit[5] CRC input data reverse bit0 */ +#define CRC_CTRL_REVIN_1 ((uint32_t)0x00000040U) /* Bit[6] CRC input data reverse bit1 */ + +#define CRC_CTRL_REVOUT ((uint32_t)0x00000080U) /* Bit[7] CRC output data reverse bit */ + +/******************** Bit definition for CRC_LRC register ********************/ +#define CRC_LRC_LRC ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC LRC value bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC initial value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC pllynomial coefficients bits */ + +/******************* Bit definition for CRC_INXORDAT register ********************/ +#define CRC_INXORDAT_INXOR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC XOR bits before calculation */ + +/******************* Bit definition for CRC_OUTXORDAT register ********************/ +#define CRC_OUTXORDAT_OUTXOR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] CRC XOR bits after calculation */ + + + + /******************************************************************************/ + /* */ + /* General Purpose and Alternate Function I/O */ + /* */ + /******************************************************************************/ + +/******** Bit definition for GPIOx_PMODE register ********/ +#define GPIO_PMODE_PMODE0 ((uint32_t)0x00000003U) /* Port x Pin 0 mode bits */ +#define GPIO_PMODE_PMODE0_0 ((uint32_t)0x00000001U) /* Port x Pin 0 mode bit 0 */ +#define GPIO_PMODE_PMODE0_1 ((uint32_t)0x00000002U) /* Port x Pin 0 mode bit 1 */ + +#define GPIO_PMODE_PMODE1 ((uint32_t)0x0000000CU) /* Port x Pin 1 mode bits */ +#define GPIO_PMODE_PMODE1_0 ((uint32_t)0x00000004U) /* Port x Pin 1 mode bit 0 */ +#define GPIO_PMODE_PMODE1_1 ((uint32_t)0x00000008U) /* Port x Pin 1 mode bit 1 */ + +#define GPIO_PMODE_PMODE2 ((uint32_t)0x00000030U) /* Port x Pin 2 mode bits */ +#define GPIO_PMODE_PMODE2_0 ((uint32_t)0x00000010U) /* Port x Pin 2 mode bit 0 */ +#define GPIO_PMODE_PMODE2_1 ((uint32_t)0x00000020U) /* Port x Pin 2 mode bit 1 */ + +#define GPIO_PMODE_PMODE3 ((uint32_t)0x000000C0U) /* Port x Pin 3 mode bits */ +#define GPIO_PMODE_PMODE3_0 ((uint32_t)0x00000040U) /* Port x Pin 3 mode bit 0 */ +#define GPIO_PMODE_PMODE3_1 ((uint32_t)0x00000080U) /* Port x Pin 3 mode bit 1 */ + +#define GPIO_PMODE_PMODE4 ((uint32_t)0x00000300U) /* Port x Pin 4 mode bits */ +#define GPIO_PMODE_PMODE4_0 ((uint32_t)0x00000100U) /* Port x Pin 4 mode bit 0 */ +#define GPIO_PMODE_PMODE4_1 ((uint32_t)0x00000200U) /* Port x Pin 4 mode bit 1 */ + +#define GPIO_PMODE_PMODE5 ((uint32_t)0x00000C00U) /* Port x Pin 5 mode bits */ +#define GPIO_PMODE_PMODE5_0 ((uint32_t)0x00000400U) /* Port x Pin 5 mode bit 0 */ +#define GPIO_PMODE_PMODE5_1 ((uint32_t)0x00000800U) /* Port x Pin 5 mode bit 1 */ + +#define GPIO_PMODE_PMODE6 ((uint32_t)0x00003000U) /* Port x Pin 6 mode bits */ +#define GPIO_PMODE_PMODE6_0 ((uint32_t)0x00001000U) /* Port x Pin 6 mode bit 0 */ +#define GPIO_PMODE_PMODE6_1 ((uint32_t)0x00002000U) /* Port x Pin 6 mode bit 1 */ + +#define GPIO_PMODE_PMODE7 ((uint32_t)0x0000C000U) /* Port x Pin 7 mode bits */ +#define GPIO_PMODE_PMODE7_0 ((uint32_t)0x00004000U) /* Port x Pin 7 mode bit 0 */ +#define GPIO_PMODE_PMODE7_1 ((uint32_t)0x00008000U) /* Port x Pin 7 mode bit 1 */ + +#define GPIO_PMODE_PMODE8 ((uint32_t)0x00030000U) /* Port x Pin 8 mode bits */ +#define GPIO_PMODE_PMODE8_0 ((uint32_t)0x00010000U) /* Port x Pin 8 mode bit 0 */ +#define GPIO_PMODE_PMODE8_1 ((uint32_t)0x00020000U) /* Port x Pin 8 mode bit 1 */ + +#define GPIO_PMODE_PMODE9 ((uint32_t)0x000C0000U) /* Port x Pin 9 mode bits */ +#define GPIO_PMODE_PMODE9_0 ((uint32_t)0x00040000U) /* Port x Pin 9 mode bit 0 */ +#define GPIO_PMODE_PMODE9_1 ((uint32_t)0x00080000U) /* Port x Pin 9 mode bit 1 */ + +#define GPIO_PMODE_PMODE10 ((uint32_t)0x00300000U) /* Port x Pin 10 mode bits */ +#define GPIO_PMODE_PMODE10_0 ((uint32_t)0x00100000U) /* Port x Pin 10 mode bit 0 */ +#define GPIO_PMODE_PMODE10_1 ((uint32_t)0x00200000U) /* Port x Pin 10 mode bit 1 */ + +#define GPIO_PMODE_PMODE11 ((uint32_t)0x00C00000U) /* Port x Pin 11 mode bits */ +#define GPIO_PMODE_PMODE11_0 ((uint32_t)0x00400000U) /* Port x Pin 11 mode bit 0 */ +#define GPIO_PMODE_PMODE11_1 ((uint32_t)0x00800000U) /* Port x Pin 11 mode bit 1 */ + +#define GPIO_PMODE_PMODE12 ((uint32_t)0x03000000U) /* Port x Pin 12 mode bits */ +#define GPIO_PMODE_PMODE12_0 ((uint32_t)0x01000000U) /* Port x Pin 12 mode bit 0 */ +#define GPIO_PMODE_PMODE12_1 ((uint32_t)0x02000000U) /* Port x Pin 12 mode bit 1 */ + +#define GPIO_PMODE_PMODE13 ((uint32_t)0x0C000000U) /* Port x Pin 13 mode bits */ +#define GPIO_PMODE_PMODE13_0 ((uint32_t)0x04000000U) /* Port x Pin 13 mode bit 0 */ +#define GPIO_PMODE_PMODE13_1 ((uint32_t)0x08000000U) /* Port x Pin 13 mode bit 1 */ + +#define GPIO_PMODE_PMODE14 ((uint32_t)0x30000000U) /* Port x Pin 14 mode bits */ +#define GPIO_PMODE_PMODE14_0 ((uint32_t)0x10000000U) /* Port x Pin 14 mode bit 0 */ +#define GPIO_PMODE_PMODE14_1 ((uint32_t)0x20000000U) /* Port x Pin 14 mode bit 1 */ + +#define GPIO_PMODE_PMODE15 ((uint32_t)0xC0000000U) /* Port x Pin 15 mode bits */ +#define GPIO_PMODE_PMODE15_0 ((uint32_t)0x40000000U) /* Port x Pin 15 mode bit 0 */ +#define GPIO_PMODE_PMODE15_1 ((uint32_t)0x80000000U) /* Port x Pin 15 mode bit 1 */ + +#define GPIO_PMODE_INPUT ((uint32_t)0x00000000U) /* Input mode */ +#define GPIO_PMODE_OUTPUT ((uint32_t)0x00000001U) /* General output mode */ +#define GPIO_PMODE_AF_OUTPUT ((uint32_t)0x00000002U) /* Alternate output mode */ +#define GPIO_PMODE_ANALOG ((uint32_t)0x00000003U) /* Analog mode */ + + /****************** Bit definition for GPIO_POTYPE register *****************/ +#define GPIO_POTYPE_POT0 ((uint32_t)0x00000001U) /* Port x Pin 0 output type bits */ +#define GPIO_POTYPE_POT1 ((uint32_t)0x00000002U) /* Port x Pin 1 output type bits */ +#define GPIO_POTYPE_POT2 ((uint32_t)0x00000004U) /* Port x Pin 2 output type bits */ +#define GPIO_POTYPE_POT3 ((uint32_t)0x00000008U) /* Port x Pin 3 output type bits */ +#define GPIO_POTYPE_POT4 ((uint32_t)0x00000010U) /* Port x Pin 4 output type bits */ +#define GPIO_POTYPE_POT5 ((uint32_t)0x00000020U) /* Port x Pin 5 output type bits */ +#define GPIO_POTYPE_POT6 ((uint32_t)0x00000040U) /* Port x Pin 6 output type bits */ +#define GPIO_POTYPE_POT7 ((uint32_t)0x00000080U) /* Port x Pin 7 output type bits */ +#define GPIO_POTYPE_POT8 ((uint32_t)0x00000100U) /* Port x Pin 8 output type bits */ +#define GPIO_POTYPE_POT9 ((uint32_t)0x00000200U) /* Port x Pin 9 output type bits */ +#define GPIO_POTYPE_POT10 ((uint32_t)0x00000400U) /* Port x Pin 10 output type bits */ +#define GPIO_POTYPE_POT11 ((uint32_t)0x00000800U) /* Port x Pin 11 output type bits */ +#define GPIO_POTYPE_POT12 ((uint32_t)0x00001000U) /* Port x Pin 12 output type bits */ +#define GPIO_POTYPE_POT13 ((uint32_t)0x00002000U) /* Port x Pin 13 output type bits */ +#define GPIO_POTYPE_POT14 ((uint32_t)0x00004000U) /* Port x Pin 14 output type bits */ +#define GPIO_POTYPE_POT15 ((uint32_t)0x00008000U) /* Port x Pin 15 output type bits */ + +#define GPIO_POTYPE_PUSH_PULL ((uint32_t)0x00000000U) +#define GPIO_POTYPE_OPEN_DRAIN ((uint32_t)0x00000001U) + +/** Bit definition for GPIO_SR register **/ +#define GPIO_SR_SR0 ((uint32_t)0x00000001U) /* Port x Pin 0 Slew rate bit */ +#define GPIO_SR_SR1 ((uint32_t)0x00000002U) /* Port x Pin 1 Slew rate bit */ +#define GPIO_SR_SR2 ((uint32_t)0x00000004U) /* Port x Pin 2 Slew rate bit */ +#define GPIO_SR_SR3 ((uint32_t)0x00000008U) /* Port x Pin 3 Slew rate bit */ +#define GPIO_SR_SR4 ((uint32_t)0x00000010U) /* Port x Pin 4 Slew rate bit */ +#define GPIO_SR_SR5 ((uint32_t)0x00000020U) /* Port x Pin 5 Slew rate bit */ +#define GPIO_SR_SR6 ((uint32_t)0x00000040U) /* Port x Pin 6 Slew rate bit */ +#define GPIO_SR_SR7 ((uint32_t)0x00000080U) /* Port x Pin 7 Slew rate bit */ +#define GPIO_SR_SR8 ((uint32_t)0x00000100U) /* Port x Pin 8 Slew rate bit */ +#define GPIO_SR_SR9 ((uint32_t)0x00000200U) /* Port x Pin 9 Slew rate bit */ +#define GPIO_SR_SR10 ((uint32_t)0x00000400U) /* Port x Pin 10 Slew rate bit */ +#define GPIO_SR_SR11 ((uint32_t)0x00000800U) /* Port x Pin 11 Slew rate bit */ +#define GPIO_SR_SR12 ((uint32_t)0x00001000U) /* Port x Pin 12 Slew rate bit */ +#define GPIO_SR_SR13 ((uint32_t)0x00002000U) /* Port x Pin 13 Slew rate bit */ +#define GPIO_SR_SR14 ((uint32_t)0x00004000U) /* Port x Pin 14 Slew rate bit */ +#define GPIO_SR_SR15 ((uint32_t)0x00008000U) /* Port x Pin 15 Slew rate bit */ + +#define GPIO_SR_FAST_SLEW ((uint32_t)0x00000000U) /* Fast slew rate */ +#define GPIO_SR_SLOW_SLEW ((uint32_t)0x00000001U) /* Slow slew rate */ + +/** Bit definition for GPIO_PUPD register **/ +#define GPIO_PUPD_PUPD0 ((uint32_t)0x00000003U) /* Port x Pin 0 pull control bits */ +#define GPIO_PUPD_PUPD0_0 ((uint32_t)0x00000001U) /* Port x Pin 0 pull control bit 0 */ +#define GPIO_PUPD_PUPD0_1 ((uint32_t)0x00000002U) /* Port x Pin 0 pull control bit 1 */ + +#define GPIO_PUPD_PUPD1 ((uint32_t)0x0000000CU) /* Port x Pin 1 pull control bits */ +#define GPIO_PUPD_PUPD1_0 ((uint32_t)0x00000004U) /* Port x Pin 1 pull control bit 0 */ +#define GPIO_PUPD_PUPD1_1 ((uint32_t)0x00000008U) /* Port x Pin 1 pull control bit 1 */ + +#define GPIO_PUPD_PUPD2 ((uint32_t)0x00000030U) /* Port x Pin 2 pull control bits */ +#define GPIO_PUPD_PUPD2_0 ((uint32_t)0x00000010U) /* Port x Pin 2 pull control bit 0 */ +#define GPIO_PUPD_PUPD2_1 ((uint32_t)0x00000020U) /* Port x Pin 2 pull control bit 1 */ + +#define GPIO_PUPD_PUPD3 ((uint32_t)0x000000C0U) /* Port x Pin 3 pull control bits */ +#define GPIO_PUPD_PUPD3_0 ((uint32_t)0x00000040U) /* Port x Pin 3 pull control bit 0 */ +#define GPIO_PUPD_PUPD3_1 ((uint32_t)0x00000080U) /* Port x Pin 3 pull control bit 1 */ + +#define GPIO_PUPD_PUPD4 ((uint32_t)0x00000300U) /* Port x Pin 4 pull control bits */ +#define GPIO_PUPD_PUPD4_0 ((uint32_t)0x00000100U) /* Port x Pin 4 pull control bit 0 */ +#define GPIO_PUPD_PUPD4_1 ((uint32_t)0x00000200U) /* Port x Pin 4 pull control bit 1 */ + +#define GPIO_PUPD_PUPD5 ((uint32_t)0x00000C00U) /* Port x Pin 5 pull control bits */ +#define GPIO_PUPD_PUPD5_0 ((uint32_t)0x00000400U) /* Port x Pin 5 pull control bit 0 */ +#define GPIO_PUPD_PUPD5_1 ((uint32_t)0x00000800U) /* Port x Pin 5 pull control bit 1 */ + +#define GPIO_PUPD_PUPD6 ((uint32_t)0x00003000U) /* Port x Pin 6 pull control bits */ +#define GPIO_PUPD_PUPD6_0 ((uint32_t)0x00001000U) /* Port x Pin 6 pull control bit 0 */ +#define GPIO_PUPD_PUPD6_1 ((uint32_t)0x00002000U) /* Port x Pin 6 pull control bit 1 */ + +#define GPIO_PUPD_PUPD7 ((uint32_t)0x0000C000U) /* Port x Pin 7 pull control bits */ +#define GPIO_PUPD_PUPD7_0 ((uint32_t)0x00004000U) /* Port x Pin 7 pull control bit 0 */ +#define GPIO_PUPD_PUPD7_1 ((uint32_t)0x00008000U) /* Port x Pin 7 pull control bit 1 */ + +#define GPIO_PUPD_PUPD8 ((uint32_t)0x00030000U) /* Port x Pin 8 pull control bits */ +#define GPIO_PUPD_PUPD8_0 ((uint32_t)0x00010000U) /* Port x Pin 8 pull control bit 0 */ +#define GPIO_PUPD_PUPD8_1 ((uint32_t)0x00020000U) /* Port x Pin 8 pull control bit 1 */ + +#define GPIO_PUPD_PUPD9 ((uint32_t)0x000C0000U) /* Port x Pin 9 pull control bits */ +#define GPIO_PUPD_PUPD9_0 ((uint32_t)0x00040000U) /* Port x Pin 9 pull control bit 0 */ +#define GPIO_PUPD_PUPD9_1 ((uint32_t)0x00080000U) /* Port x Pin 9 pull control bit 1 */ + +#define GPIO_PUPD_PUPD10 ((uint32_t)0x00300000U) /* Port x Pin 10 pull control bits */ +#define GPIO_PUPD_PUPD10_0 ((uint32_t)0x00100000U) /* Port x Pin 10 pull control bit 0 */ +#define GPIO_PUPD_PUPD10_1 ((uint32_t)0x00200000U) /* Port x Pin 10 pull control bit 1 */ + +#define GPIO_PUPD_PUPD11 ((uint32_t)0x00C00000U) /* Port x Pin 11 pull control bits */ +#define GPIO_PUPD_PUPD11_0 ((uint32_t)0x00400000U) /* Port x Pin 11 pull control bit 0 */ +#define GPIO_PUPD_PUPD11_1 ((uint32_t)0x00800000U) /* Port x Pin 11 pull control bit 1 */ + +#define GPIO_PUPD_PUPD12 ((uint32_t)0x03000000U) /* Port x Pin 12 pull control bits */ +#define GPIO_PUPD_PUPD12_0 ((uint32_t)0x01000000U) /* Port x Pin 12 pull control bit 0 */ +#define GPIO_PUPD_PUPD12_1 ((uint32_t)0x02000000U) /* Port x Pin 12 pull control bit 1 */ + +#define GPIO_PUPD_PUPD13 ((uint32_t)0x0C000000U) /* Port x Pin 13 pull control bits */ +#define GPIO_PUPD_PUPD13_0 ((uint32_t)0x04000000U) /* Port x Pin 13 pull control bit 0 */ +#define GPIO_PUPD_PUPD13_1 ((uint32_t)0x08000000U) /* Port x Pin 13 pull control bit 1 */ + +#define GPIO_PUPD_PUPD14 ((uint32_t)0x30000000U) /* Port x Pin 14 pull control bits */ +#define GPIO_PUPD_PUPD14_0 ((uint32_t)0x10000000U) /* Port x Pin 14 pull control bit 0 */ +#define GPIO_PUPD_PUPD14_1 ((uint32_t)0x20000000U) /* Port x Pin 14 pull control bit 1 */ + +#define GPIO_PUPD_PUPD15 ((uint32_t)0xC0000000U) /* Port x Pin 15 pull control bits */ +#define GPIO_PUPD_PUPD15_0 ((uint32_t)0x40000000U) /* Port x Pin 15 pull control bit 0 */ +#define GPIO_PUPD_PUPD15_1 ((uint32_t)0x80000000U) /* Port x Pin 15 pull control bit 1 */ + + +#define GPIO_PUPD_NO_PULL ((uint32_t)0x00000000U) /* No pull */ +#define GPIO_PUPD_PULL_UP ((uint32_t)0x00000001U) /* Pull up*/ +#define GPIO_PUPD_PULL_DOWN ((uint32_t)0x00000002U) /* Pull down */ + +/** Bit definition for GPIO_PID register **/ +#define GPIO_PID_PID0 ((uint16_t)0x0001U) /* Port x Pin 0 input bit */ +#define GPIO_PID_PID1 ((uint16_t)0x0002U) /* Port x Pin 1 input bit */ +#define GPIO_PID_PID2 ((uint16_t)0x0004U) /* Port x Pin 2 input bit */ +#define GPIO_PID_PID3 ((uint16_t)0x0008U) /* Port x Pin 3 input bit */ +#define GPIO_PID_PID4 ((uint16_t)0x0010U) /* Port x Pin 4 input bit */ +#define GPIO_PID_PID5 ((uint16_t)0x0020U) /* Port x Pin 5 input bit */ +#define GPIO_PID_PID6 ((uint16_t)0x0040U) /* Port x Pin 6 input bit */ +#define GPIO_PID_PID7 ((uint16_t)0x0080U) /* Port x Pin 7 input bit */ +#define GPIO_PID_PID8 ((uint16_t)0x0100U) /* Port x Pin 8 input bit */ +#define GPIO_PID_PID9 ((uint16_t)0x0200U) /* Port x Pin 9 input bit */ +#define GPIO_PID_PID10 ((uint16_t)0x0400U) /* Port x Pin 10 input bit */ +#define GPIO_PID_PID11 ((uint16_t)0x0800U) /* Port x Pin 11 input bit */ +#define GPIO_PID_PID12 ((uint16_t)0x1000U) /* Port x Pin 12 input bit */ +#define GPIO_PID_PID13 ((uint16_t)0x2000U) /* Port x Pin 13 input bit */ +#define GPIO_PID_PID14 ((uint16_t)0x4000U) /* Port x Pin 14 input bit */ +#define GPIO_PID_PID15 ((uint16_t)0x8000U) /* Port x Pin 15 input bit */ + +/** Bit definition for GPIO_POD register **/ +#define GPIO_POD_POD0 ((uint16_t)0x0001U) /* Port x Pin 0 output bit */ +#define GPIO_POD_POD1 ((uint16_t)0x0002U) /* Port x Pin 1 output bit */ +#define GPIO_POD_POD2 ((uint16_t)0x0004U) /* Port x Pin 2 output bit */ +#define GPIO_POD_POD3 ((uint16_t)0x0008U) /* Port x Pin 3 output bit */ +#define GPIO_POD_POD4 ((uint16_t)0x0010U) /* Port x Pin 4 output bit */ +#define GPIO_POD_POD5 ((uint16_t)0x0020U) /* Port x Pin 5 output bit */ +#define GPIO_POD_POD6 ((uint16_t)0x0040U) /* Port x Pin 6 output bit */ +#define GPIO_POD_POD7 ((uint16_t)0x0080U) /* Port x Pin 7 output bit */ +#define GPIO_POD_POD8 ((uint16_t)0x0100U) /* Port x Pin 8 output bit */ +#define GPIO_POD_POD9 ((uint16_t)0x0200U) /* Port x Pin 9 output bit */ +#define GPIO_POD_POD10 ((uint16_t)0x0400U) /* Port x Pin 10 output bit */ +#define GPIO_POD_POD11 ((uint16_t)0x0800U) /* Port x Pin 11 output bit */ +#define GPIO_POD_POD12 ((uint16_t)0x1000U) /* Port x Pin 12 output bit */ +#define GPIO_POD_POD13 ((uint16_t)0x2000U) /* Port x Pin 13 output bit */ +#define GPIO_POD_POD14 ((uint16_t)0x4000U) /* Port x Pin 14 output bit */ +#define GPIO_POD_POD15 ((uint16_t)0x8000U) /* Port x Pin 15 output bit */ + +/** Bit definition for GPIO_PBSC register **/ +#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001U) /* Port x Pin 0 Set bit 0 */ +#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002U) /* Port x Pin 1 Set bit 1 */ +#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004U) /* Port x Pin 2 Set bit 2 */ +#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008U) /* Port x Pin 3 Set bit 3 */ +#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010U) /* Port x Pin 4 Set bit 4 */ +#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020U) /* Port x Pin 5 Set bit 5 */ +#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040U) /* Port x Pin 6 Set bit 6 */ +#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080U) /* Port x Pin 7 Set bit 7 */ +#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100U) /* Port x Pin 8 Set bit 8 */ +#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200U) /* Port x Pin 9 Set bit 9 */ +#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400U) /* Port x Pin 10 Set bit 10 */ +#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800U) /* Port x Pin 11 Set bit 11 */ +#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000U) /* Port x Pin 12 Set bit 12 */ +#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000U) /* Port x Pin 13 Set bit 13 */ +#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000U) /* Port x Pin 14 Set bit 14 */ +#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000U) /* Port x Pin 15 Set bit 15 */ + +#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000U) /* Port x Pin 0 Reset bit 0 */ +#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000U) /* Port x Pin 1 Reset bit 1 */ +#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000U) /* Port x Pin 2 Reset bit 2 */ +#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000U) /* Port x Pin 3 Reset bit 3 */ +#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000U) /* Port x Pin 4 Reset bit 4 */ +#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000U) /* Port x Pin 5 Reset bit 5 */ +#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000U) /* Port x Pin 6 Reset bit 6 */ +#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000U) /* Port x Pin 7 Reset bit 7 */ +#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000U) /* Port x Pin 8 Reset bit 8 */ +#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000U) /* Port x Pin 9 Reset bit 9 */ +#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000U) /* Port x Pin 10 Reset bit 10 */ +#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000U) /* Port x Pin 11 Reset bit 11 */ +#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000U) /* Port x Pin 12 Reset bit 12 */ +#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000U) /* Port x Pin 13 Reset bit 13 */ +#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000U) /* Port x Pin 14 Reset bit 14 */ +#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000U) /* Port x Pin 15 Reset bit 15 */ + +/** Bit definition for GPIO_PLOCK register **/ +#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001U) /* Port x Pin 0 Lock bit */ +#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002U) /* Port x Pin 1 Lock bit */ +#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004U) /* Port x Pin 2 Lock bit */ +#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008U) /* Port x Pin 3 Lock bit */ +#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010U) /* Port x Pin 4 Lock bit */ +#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020U) /* Port x Pin 5 Lock bit */ +#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040U) /* Port x Pin 6 Lock bit */ +#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080U) /* Port x Pin 7 Lock bit */ +#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100U) /* Port x Pin 8 Lock bit */ +#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200U) /* Port x Pin 9 Lock bit */ +#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400U) /* Port x Pin 10 Lock bit */ +#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800U) /* Port x Pin 11 Lock bit */ +#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000U) /* Port x Pin 12 Lock bit */ +#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000U) /* Port x Pin 13 Lock bit */ +#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000U) /* Port x Pin 14 Lock bit */ +#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000U) /* Port x Pin 15 Lock bit */ +#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000U) /* Port x Lock key */ + +/******** Bit definition for GPIOx_AFRL register ********/ +#define GPIOx_AFRL_AFSEL7 ((uint32_t)0xF0000000) /* Bit[31:28] */ +#define GPIOx_AFRL_AFSEL7_0 ((uint32_t)0x10000000) /* Bit28*/ +#define GPIOx_AFRL_AFSEL7_1 ((uint32_t)0x20000000) /* Bit29*/ +#define GPIOx_AFRL_AFSEL7_2 ((uint32_t)0x40000000) /* Bit30*/ +#define GPIOx_AFRL_AFSEL7_3 ((uint32_t)0x80000000) /* Bit31*/ +#define GPIOx_AFRL_AFSEL6 ((uint32_t)0x0F000000) /* Bit[27:24] */ +#define GPIOx_AFRL_AFSEL6_0 ((uint32_t)0x01000000) /* Bit24*/ +#define GPIOx_AFRL_AFSEL6_1 ((uint32_t)0x02000000) /* Bit25*/ +#define GPIOx_AFRL_AFSEL6_2 ((uint32_t)0x04000000) /* Bit26*/ +#define GPIOx_AFRL_AFSEL6_3 ((uint32_t)0x08000000) /* Bit27*/ +#define GPIOx_AFRL_AFSEL5 ((uint32_t)0x00F00000) /* Bit[23:20] */ +#define GPIOx_AFRL_AFSEL5_0 ((uint32_t)0x00100000) /* Bit20*/ +#define GPIOx_AFRL_AFSEL5_1 ((uint32_t)0x00200000) /* Bit21*/ +#define GPIOx_AFRL_AFSEL5_2 ((uint32_t)0x00400000) /* Bit22*/ +#define GPIOx_AFRL_AFSEL5_3 ((uint32_t)0x00800000) /* Bit23*/ +#define GPIOx_AFRL_AFSEL4 ((uint32_t)0x000F0000) /* Bit[19:16] */ +#define GPIOx_AFRL_AFSEL4_0 ((uint32_t)0x00010000) /* Bit16*/ +#define GPIOx_AFRL_AFSEL4_1 ((uint32_t)0x00020000) /* Bit17*/ +#define GPIOx_AFRL_AFSEL4_2 ((uint32_t)0x00040000) /* Bit18*/ +#define GPIOx_AFRL_AFSEL4_3 ((uint32_t)0x00080000) /* Bit19*/ +#define GPIOx_AFRL_AFSEL3 ((uint32_t)0x0000F000) /* Bit[15:12] */ +#define GPIOx_AFRL_AFSEL3_0 ((uint32_t)0x00001000) /* Bit12*/ +#define GPIOx_AFRL_AFSEL3_1 ((uint32_t)0x00002000) /* Bit13*/ +#define GPIOx_AFRL_AFSEL3_2 ((uint32_t)0x00004000) /* Bit14*/ +#define GPIOx_AFRL_AFSEL3_3 ((uint32_t)0x00008000) /* Bit15*/ +#define GPIOx_AFRL_AFSEL2 ((uint32_t)0x00000F00) /* Bit[11:8] */ +#define GPIOx_AFRL_AFSEL2_0 ((uint32_t)0x00000100) /* Bit8*/ +#define GPIOx_AFRL_AFSEL2_1 ((uint32_t)0x00000200) /* Bit9*/ +#define GPIOx_AFRL_AFSEL2_2 ((uint32_t)0x00000400) /* Bit10*/ +#define GPIOx_AFRL_AFSEL2_3 ((uint32_t)0x00000800) /* Bit11*/ +#define GPIOx_AFRL_AFSEL1 ((uint32_t)0x000000F0) /* Bit[7:4] */ +#define GPIOx_AFRL_AFSEL1_0 ((uint32_t)0x00000010) /* Bit4*/ +#define GPIOx_AFRL_AFSEL1_1 ((uint32_t)0x00000020) /* Bit5*/ +#define GPIOx_AFRL_AFSEL1_2 ((uint32_t)0x00000040) /* Bit6*/ +#define GPIOx_AFRL_AFSEL1_3 ((uint32_t)0x00000080) /* Bit7*/ +#define GPIOx_AFRL_AFSEL0 ((uint32_t)0x0000000F) /* Bit[3:0] */ +#define GPIOx_AFRL_AFSEL0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define GPIOx_AFRL_AFSEL0_1 ((uint32_t)0x00000002) /* Bit1*/ +#define GPIOx_AFRL_AFSEL0_2 ((uint32_t)0x00000004) /* Bit2*/ +#define GPIOx_AFRL_AFSEL0_3 ((uint32_t)0x00000008) /* Bit3*/ + +/******** Bit definition for GPIOx_AFRH register ********/ +#define GPIOx_AFRH_AFSEL15 ((uint32_t)0xF0000000) /* Bit[31:28] */ +#define GPIOx_AFRH_AFSEL15_0 ((uint32_t)0x10000000) /* Bit28*/ +#define GPIOx_AFRH_AFSEL15_1 ((uint32_t)0x20000000) /* Bit29*/ +#define GPIOx_AFRH_AFSEL15_2 ((uint32_t)0x40000000) /* Bit30*/ +#define GPIOx_AFRH_AFSEL15_3 ((uint32_t)0x80000000) /* Bit31*/ +#define GPIOx_AFRH_AFSEL14 ((uint32_t)0x0F000000) /* Bit[27:24] */ +#define GPIOx_AFRH_AFSEL14_0 ((uint32_t)0x01000000) /* Bit24*/ +#define GPIOx_AFRH_AFSEL14_1 ((uint32_t)0x02000000) /* Bit25*/ +#define GPIOx_AFRH_AFSEL14_2 ((uint32_t)0x04000000) /* Bit26*/ +#define GPIOx_AFRH_AFSEL14_3 ((uint32_t)0x08000000) /* Bit27*/ +#define GPIOx_AFRH_AFSEL13 ((uint32_t)0x00F00000) /* Bit[23:20] */ +#define GPIOx_AFRH_AFSEL13_0 ((uint32_t)0x00100000) /* Bit20*/ +#define GPIOx_AFRH_AFSEL13_1 ((uint32_t)0x00200000) /* Bit21*/ +#define GPIOx_AFRH_AFSEL13_2 ((uint32_t)0x00400000) /* Bit22*/ +#define GPIOx_AFRH_AFSEL13_3 ((uint32_t)0x00800000) /* Bit23*/ +#define GPIOx_AFRH_AFSEL12 ((uint32_t)0x000F0000) /* Bit[19:16] */ +#define GPIOx_AFRH_AFSEL12_0 ((uint32_t)0x00010000) /* Bit16*/ +#define GPIOx_AFRH_AFSEL12_1 ((uint32_t)0x00020000) /* Bit17*/ +#define GPIOx_AFRH_AFSEL12_2 ((uint32_t)0x00040000) /* Bit18*/ +#define GPIOx_AFRH_AFSEL12_3 ((uint32_t)0x00080000) /* Bit19*/ +#define GPIOx_AFRH_AFSEL11 ((uint32_t)0x0000F000) /* Bit[15:12] */ +#define GPIOx_AFRH_AFSEL11_0 ((uint32_t)0x00001000) /* Bit12*/ +#define GPIOx_AFRH_AFSEL11_1 ((uint32_t)0x00002000) /* Bit13*/ +#define GPIOx_AFRH_AFSEL11_2 ((uint32_t)0x00004000) /* Bit14*/ +#define GPIOx_AFRH_AFSEL11_3 ((uint32_t)0x00008000) /* Bit15*/ +#define GPIOx_AFRH_AFSEL10 ((uint32_t)0x00000F00) /* Bit[11:8] */ +#define GPIOx_AFRH_AFSEL10_0 ((uint32_t)0x00000100) /* Bit8*/ +#define GPIOx_AFRH_AFSEL10_1 ((uint32_t)0x00000200) /* Bit9*/ +#define GPIOx_AFRH_AFSEL10_2 ((uint32_t)0x00000400) /* Bit10*/ +#define GPIOx_AFRH_AFSEL10_3 ((uint32_t)0x00000800) /* Bit11*/ +#define GPIOx_AFRH_AFSEL9 ((uint32_t)0x000000F0) /* Bit[7:4] */ +#define GPIOx_AFRH_AFSEL9_0 ((uint32_t)0x00000010) /* Bit4*/ +#define GPIOx_AFRH_AFSEL9_1 ((uint32_t)0x00000020) /* Bit5*/ +#define GPIOx_AFRH_AFSEL9_2 ((uint32_t)0x00000040) /* Bit6*/ +#define GPIOx_AFRH_AFSEL9_3 ((uint32_t)0x00000080) /* Bit7*/ +#define GPIOx_AFRH_AFSEL8 ((uint32_t)0x0000000F) /* Bit[3:0] */ +#define GPIOx_AFRH_AFSEL8_0 ((uint32_t)0x00000001) /* Bit0*/ +#define GPIOx_AFRH_AFSEL8_1 ((uint32_t)0x00000002) /* Bit1*/ +#define GPIOx_AFRH_AFSEL8_2 ((uint32_t)0x00000004) /* Bit2*/ +#define GPIOx_AFRH_AFSEL8_3 ((uint32_t)0x00000008) /* Bit3*/ + + +#define GPIO_AFSEL_AF0 ((uint32_t)0x00000000U) /* Alternate function 0 */ +#define GPIO_AFSEL_AF1 ((uint32_t)0x00000001U) /* Alternate function 1 */ +#define GPIO_AFSEL_AF2 ((uint32_t)0x00000002U) /* Alternate function 2 */ +#define GPIO_AFSEL_AF3 ((uint32_t)0x00000003U) /* Alternate function 3 */ +#define GPIO_AFSEL_AF4 ((uint32_t)0x00000004U) /* Alternate function 4 */ +#define GPIO_AFSEL_AF5 ((uint32_t)0x00000005U) /* Alternate function 5 */ +#define GPIO_AFSEL_AF6 ((uint32_t)0x00000006U) /* Alternate function 6 */ +#define GPIO_AFSEL_AF7 ((uint32_t)0x00000007U) /* Alternate function 7 */ +#define GPIO_AFSEL_AF8 ((uint32_t)0x00000008U) /* Alternate function 8 */ +#define GPIO_AFSEL_AF9 ((uint32_t)0x00000009U) /* Alternate function 9 */ +#define GPIO_AFSEL_AF10 ((uint32_t)0x0000000AU) /* Alternate function 10 */ +#define GPIO_AFSEL_AF11 ((uint32_t)0x0000000BU) /* Alternate function 11 */ +#define GPIO_AFSEL_AF12 ((uint32_t)0x0000000CU) /* Alternate function 12 */ +#define GPIO_AFSEL_AF13 ((uint32_t)0x0000000DU) /* Alternate function 13 */ +#define GPIO_AFSEL_AF14 ((uint32_t)0x0000000EU) /* Alternate function 14 */ +#define GPIO_AFSEL_AF15 ((uint32_t)0x0000000FU) /* Alternate function 15 */ + +/** Bit definition for GPIO_PBC register **/ +#define GPIO_PBC_PBC0 ((uint16_t)0x0001U) /* Port x Pin 0 Reset bit 0 */ +#define GPIO_PBC_PBC1 ((uint16_t)0x0002U) /* Port x Pin 1 Reset bit 1 */ +#define GPIO_PBC_PBC2 ((uint16_t)0x0004U) /* Port x Pin 2 Reset bit 2 */ +#define GPIO_PBC_PBC3 ((uint16_t)0x0008U) /* Port x Pin 3 Reset bit 3 */ +#define GPIO_PBC_PBC4 ((uint16_t)0x0010U) /* Port x Pin 4 Reset bit 4 */ +#define GPIO_PBC_PBC5 ((uint16_t)0x0020U) /* Port x Pin 5 Reset bit 5 */ +#define GPIO_PBC_PBC6 ((uint16_t)0x0040U) /* Port x Pin 6 Reset bit 6 */ +#define GPIO_PBC_PBC7 ((uint16_t)0x0080U) /* Port x Pin 7 Reset bit 7 */ +#define GPIO_PBC_PBC8 ((uint16_t)0x0100U) /* Port x Pin 8 Reset bit 8 */ +#define GPIO_PBC_PBC9 ((uint16_t)0x0200U) /* Port x Pin 9 Reset bit 9 */ +#define GPIO_PBC_PBC10 ((uint16_t)0x0400U) /* Port x Pin 10 Reset bit 10 */ +#define GPIO_PBC_PBC11 ((uint16_t)0x0800U) /* Port x Pin 11 Reset bit 11 */ +#define GPIO_PBC_PBC12 ((uint16_t)0x1000U) /* Port x Pin 12 Reset bit 12 */ +#define GPIO_PBC_PBC13 ((uint16_t)0x2000U) /* Port x Pin 13 Reset bit 13 */ +#define GPIO_PBC_PBC14 ((uint16_t)0x4000U) /* Port x Pin 14 Reset bit 14 */ +#define GPIO_PBC_PBC15 ((uint16_t)0x8000U) /* Port x Pin 15 Reset bit 15 */ + +/** Bit definition for GPIO_DS register **/ +#define GPIO_DS_DS0 ((uint32_t)0x00000003U) /* Port x Pin 0 Drive bitS */ +#define GPIO_DS_DS0_0 ((uint32_t)0x00000001U) /* Port x Pin 0 Drive bit 0 */ +#define GPIO_DS_DS0_1 ((uint32_t)0x00000002U) /* Port x Pin 0 Drive bit 1 */ + +#define GPIO_DS_DS1 ((uint32_t)0x0000000CU) /* Port x Pin 1 Drive bitS */ +#define GPIO_DS_DS1_0 ((uint32_t)0x00000004U) /* Port x Pin 1 Drive bit 0 */ +#define GPIO_DS_DS1_1 ((uint32_t)0x00000008U) /* Port x Pin 1 Drive bit 1 */ + +#define GPIO_DS_DS2 ((uint32_t)0x00000030U) /* Port x Pin 2 Drive bitS */ +#define GPIO_DS_DS2_0 ((uint32_t)0x00000010U) /* Port x Pin 2 Drive bit 0 */ +#define GPIO_DS_DS2_1 ((uint32_t)0x00000020U) /* Port x Pin 2 Drive bit 1 */ + +#define GPIO_DS_DS3 ((uint32_t)0x000000C0U) /* Port x Pin 3 Drive bitS */ +#define GPIO_DS_DS3_0 ((uint32_t)0x00000040U) /* Port x Pin 3 Drive bit 0 */ +#define GPIO_DS_DS3_1 ((uint32_t)0x00000080U) /* Port x Pin 3 Drive bit 1 */ + +#define GPIO_DS_DS4 ((uint32_t)0x00000300U) /* Port x Pin 4 Drive bitS */ +#define GPIO_DS_DS4_0 ((uint32_t)0x00000100U) /* Port x Pin 4 Drive bit 0 */ +#define GPIO_DS_DS4_1 ((uint32_t)0x00000200U) /* Port x Pin 4 Drive bit 1 */ + +#define GPIO_DS_DS5 ((uint32_t)0x00000C00U) /* Port x Pin 5 Drive bitS */ +#define GPIO_DS_DS5_0 ((uint32_t)0x00000400U) /* Port x Pin 5 Drive bit 0 */ +#define GPIO_DS_DS5_1 ((uint32_t)0x00000800U) /* Port x Pin 5 Drive bit 1 */ + +#define GPIO_DS_DS6 ((uint32_t)0x00003000U) /* Port x Pin 6 Drive bitS */ +#define GPIO_DS_DS6_0 ((uint32_t)0x00001000U) /* Port x Pin 6 Drive bit 0 */ +#define GPIO_DS_DS6_1 ((uint32_t)0x00002000U) /* Port x Pin 6 Drive bit 1 */ + +#define GPIO_DS_DS7 ((uint32_t)0x0000C000U) /* Port x Pin 7 Drive bitS */ +#define GPIO_DS_DS7_0 ((uint32_t)0x00004000U) /* Port x Pin 7 Drive bit 0 */ +#define GPIO_DS_DS7_1 ((uint32_t)0x00008000U) /* Port x Pin 7 Drive bit 1 */ + +#define GPIO_DS_DS8 ((uint32_t)0x00030000U) /* Port x Pin 8 Drive bitS */ +#define GPIO_DS_DS8_0 ((uint32_t)0x00010000U) /* Port x Pin 8 Drive bit 0 */ +#define GPIO_DS_DS8_1 ((uint32_t)0x00020000U) /* Port x Pin 8 Drive bit 1 */ + +#define GPIO_DS_DS9 ((uint32_t)0x000C0000U) /* Port x Pin 9 Drive bitS */ +#define GPIO_DS_DS9_0 ((uint32_t)0x00040000U) /* Port x Pin 9 Drive bit 0 */ +#define GPIO_DS_DS9_1 ((uint32_t)0x00080000U) /* Port x Pin 9 Drive bit 1 */ + +#define GPIO_DS_DS10 ((uint32_t)0x00300000U) /* Port x Pin 10 Drive bitS */ +#define GPIO_DS_DS10_0 ((uint32_t)0x00100000U) /* Port x Pin 10 Drive bit 0 */ +#define GPIO_DS_DS10_1 ((uint32_t)0x00200000U) /* Port x Pin 10 Drive bit 1 */ + +#define GPIO_DS_DS11 ((uint32_t)0x00C00000U) /* Port x Pin 11 Drive bitS */ +#define GPIO_DS_DS11_0 ((uint32_t)0x00400000U) /* Port x Pin 11 Drive bit 0 */ +#define GPIO_DS_DS11_1 ((uint32_t)0x00800000U) /* Port x Pin 11 Drive bit 1 */ + +#define GPIO_DS_DS12 ((uint32_t)0x03000000U) /* Port x Pin 12 Drive bitS */ +#define GPIO_DS_DS12_0 ((uint32_t)0x01000000U) /* Port x Pin 12 Drive bit 0 */ +#define GPIO_DS_DS12_1 ((uint32_t)0x02000000U) /* Port x Pin 12 Drive bit 1 */ + +#define GPIO_DS_DS13 ((uint32_t)0x0C000000U) /* Port x Pin 13 Drive bitS */ +#define GPIO_DS_DS13_0 ((uint32_t)0x04000000U) /* Port x Pin 13 Drive bit 0 */ +#define GPIO_DS_DS13_1 ((uint32_t)0x08000000U) /* Port x Pin 13 Drive bit 1 */ + +#define GPIO_DS_DS14 ((uint32_t)0x30000000U) /* Port x Pin 14 Drive bitS */ +#define GPIO_DS_DS14_0 ((uint32_t)0x10000000U) /* Port x Pin 14 Drive bit 0 */ +#define GPIO_DS_DS14_1 ((uint32_t)0x20000000U) /* Port x Pin 14 Drive bit 1 */ + +#define GPIO_DS_DS15 ((uint32_t)0xC0000000U) /* Port x Pin 15 Drive bitS */ +#define GPIO_DS_DS15_0 ((uint32_t)0x40000000U) /* Port x Pin 15 Drive bit 0 */ +#define GPIO_DS_DS15_1 ((uint32_t)0x80000000U) /* Port x Pin 15 Drive bit 1 */ + +#define GPIO_DS_2mA ((uint32_t)0x00000000U) /* Drive strength is 2mA */ +#define GPIO_DS_4mA ((uint32_t)0x00000002U) /* Drive strength is 4mA */ +#define GPIO_DS_8mA ((uint32_t)0x00000001U) /* Drive strength is 8mA */ +#define GPIO_DS_12mA ((uint32_t)0x00000003U) /* Drive strength is 12mA */ + + + +/******** Bit definition for AFIO_RMP_CFG register ********/ +#define AFIO_RMP_CFG_EXTI_AFLTBYPS ((uint32_t)0x40000000) /* Bit[30] */ +#define AFIO_RMP_CFG_SIP_SDRAM_SEL ((uint32_t)0x20000000) /* Bit[29] */ +#define AFIO_RMP_CFG_SPI4_SEL ((uint32_t)0x10000000) /* Bit[28] */ +#define AFIO_RMP_CFG_SPI3_SEL ((uint32_t)0x08000000) /* Bit[27] */ +#define AFIO_RMP_CFG_SPI2_SEL ((uint32_t)0x04000000) /* Bit[26] */ +#define AFIO_RMP_CFG_SPI1_SEL ((uint32_t)0x02000000) /* Bit[25] */ +#define AFIO_RMP_CFG_SDMMC1_CLKFB ((uint32_t)0x01000000) /* Bit[24] */ +#define AFIO_RMP_CFG_SDMMC2_CLKFB ((uint32_t)0x00800000) /* Bit[23] */ +#define AFIO_RMP_CFG_I2S_FDUP ((uint32_t)0x00600000) /* Bit[22:21] */ +#define AFIO_RMP_CFG_I2S_FDUP_0 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_RMP_CFG_I2S_FDUP_1 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_RMP_CFG_XSPI2_EDN ((uint32_t)0x00080000) /* Bit[19] */ +#define AFIO_RMP_CFG_XSPI1_EDN ((uint32_t)0x00040000) /* Bit[18] */ +#define AFIO_RMP_CFG_FEMCSEL ((uint32_t)0x00020000) /* Bit[17] */ +#define AFIO_RMP_CFG_FEMC_NOBYTE ((uint32_t)0x00010000) /* Bit[16] */ +#define AFIO_RMP_CFG_ETH2_PHY ((uint32_t)0x00008000) /* Bit[15] */ +#define AFIO_RMP_CFG_ETH1_PHY ((uint32_t)0x00006000) /* Bit[14:13] */ +#define AFIO_RMP_CFG_ETH1_PHY_0 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_RMP_CFG_ETH1_PHY_1 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_RMP_CFG_SPI7_NSS ((uint32_t)0x00001000) /* Bit[12] */ +#define AFIO_RMP_CFG_SPI6_NSS ((uint32_t)0x00000800) /* Bit[11] */ +#define AFIO_RMP_CFG_SPI5_NSS ((uint32_t)0x00000400) /* Bit[10] */ +#define AFIO_RMP_CFG_SPI4_NSS ((uint32_t)0x00000200) /* Bit[9] */ +#define AFIO_RMP_CFG_SPI3_NSS ((uint32_t)0x00000100) /* Bit[8] */ +#define AFIO_RMP_CFG_SPI2_NSS ((uint32_t)0x00000080) /* Bit[7] */ +#define AFIO_RMP_CFG_SPI1_NSS ((uint32_t)0x00000040) /* Bit[6] */ +#define AFIO_RMP_CFG_SIP_FLASHSEL ((uint32_t)0x00000007) /* Bit[2:0] */ +#define AFIO_RMP_CFG_SIP_FLASHSEL_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_RMP_CFG_SIP_FLASHSEL_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_RMP_CFG_SIP_FLASHSEL_2 ((uint32_t)0x00000004) /* Bit2*/ + +/******** Bit definition for AFIO_FILTER_CFG register ********/ +#define AFIO_FILTER_CFG_IOFLTCFG ((uint32_t)0x0000007F) /* Bit[6:0] */ +#define AFIO_FILTER_CFG_IOFLTCFG_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_FILTER_CFG_IOFLTCFG_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_FILTER_CFG_IOFLTCFG_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_FILTER_CFG_IOFLTCFG_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_FILTER_CFG_IOFLTCFG_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_FILTER_CFG_IOFLTCFG_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_FILTER_CFG_IOFLTCFG_6 ((uint32_t)0x00000040) /* Bit6*/ + +/** Bit definition for AFIO_XSPI1_NON0 register **/ +#define AFIO_XSPI1_NON0_XSPI1_DEC_NONCE ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +/** Bit definition for AFIO_XSPI1_NON1 register **/ +#define AFIO_XSPI1_NON1_XSPI1_DEC_NONCE ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +/** Bit definition for AFIO_XSPI1_NON2 register **/ +#define AFIO_XSPI1_NON2_XSPI1_DEC_NONCE ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ + +/** Bit definition for AFIO_ADCRMP_CFG register **/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRISEL ((uint32_t)0x00F00000) /* Bit[23:20] */ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRISEL_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRISEL_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRISEL_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRISEL_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRRSEL ((uint32_t)0x000F0000) /* Bit[19:16] */ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRRSEL_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRRSEL_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRRSEL_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_ADCRMP_CFG_ADC1_EXTIRRSEL_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRISEL ((uint32_t)0x0000F000) /* Bit[15:12] */ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRISEL_0 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRISEL_1 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRISEL_2 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRISEL_3 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRRSEL ((uint32_t)0x00000F00) /* Bit[11:8] */ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRRSEL_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRRSEL_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRRSEL_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_ADCRMP_CFG_ADC2_EXTIRRSEL_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRISEL ((uint32_t)0x000000F0) /* Bit[7:4] */ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRISEL_0 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRISEL_1 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRISEL_2 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRISEL_3 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRRSEL ((uint32_t)0x0000000F) /* Bit[3:0] */ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRRSEL_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRRSEL_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRRSEL_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_ADCRMP_CFG_ADC3_EXTIRRSEL_3 ((uint32_t)0x00000008) /* Bit3*/ + +/******** Bit definition for AFIO_EXTI_CFG1 register ********/ +#define AFIO_EXTI_CFG1_EXTI3 ((uint32_t)0xFF000000) /* Bit[31:24] */ +#define AFIO_EXTI_CFG1_EXTI3_0 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EXTI_CFG1_EXTI3_1 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EXTI_CFG1_EXTI3_2 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EXTI_CFG1_EXTI3_3 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EXTI_CFG1_EXTI3_4 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EXTI_CFG1_EXTI3_5 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EXTI_CFG1_EXTI3_6 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EXTI_CFG1_EXTI3_7 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EXTI_CFG1_EXTI2 ((uint32_t)0x00FF0000) /* Bit[23:16] */ +#define AFIO_EXTI_CFG1_EXTI2_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EXTI_CFG1_EXTI2_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EXTI_CFG1_EXTI2_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EXTI_CFG1_EXTI2_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EXTI_CFG1_EXTI2_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EXTI_CFG1_EXTI2_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EXTI_CFG1_EXTI2_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EXTI_CFG1_EXTI2_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EXTI_CFG1_EXTI1 ((uint32_t)0x0000FF00) /* Bit[15:8] */ +#define AFIO_EXTI_CFG1_EXTI1_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EXTI_CFG1_EXTI1_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EXTI_CFG1_EXTI1_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EXTI_CFG1_EXTI1_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EXTI_CFG1_EXTI1_4 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EXTI_CFG1_EXTI1_5 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EXTI_CFG1_EXTI1_6 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EXTI_CFG1_EXTI1_7 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_EXTI_CFG1_EXTI0 ((uint32_t)0x000000FF) /* Bit[7:0] */ +#define AFIO_EXTI_CFG1_EXTI0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EXTI_CFG1_EXTI0_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EXTI_CFG1_EXTI0_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EXTI_CFG1_EXTI0_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EXTI_CFG1_EXTI0_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EXTI_CFG1_EXTI0_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EXTI_CFG1_EXTI0_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EXTI_CFG1_EXTI0_7 ((uint32_t)0x00000080) /* Bit7*/ + +/******** Bit definition for AFIO_EXTI_CFG2 register ********/ +#define AFIO_EXTI_CFG2_EXTI7 ((uint32_t)0xFF000000) /* Bit[31:24] */ +#define AFIO_EXTI_CFG2_EXTI7_0 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EXTI_CFG2_EXTI7_1 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EXTI_CFG2_EXTI7_2 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EXTI_CFG2_EXTI7_3 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EXTI_CFG2_EXTI7_4 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EXTI_CFG2_EXTI7_5 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EXTI_CFG2_EXTI7_6 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EXTI_CFG2_EXTI7_7 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EXTI_CFG2_EXTI6 ((uint32_t)0x00FF0000) /* Bit[23:16] */ +#define AFIO_EXTI_CFG2_EXTI6_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EXTI_CFG2_EXTI6_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EXTI_CFG2_EXTI6_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EXTI_CFG2_EXTI6_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EXTI_CFG2_EXTI6_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EXTI_CFG2_EXTI6_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EXTI_CFG2_EXTI6_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EXTI_CFG2_EXTI6_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EXTI_CFG2_EXTI5 ((uint32_t)0x0000FF00) /* Bit[15:8] */ +#define AFIO_EXTI_CFG2_EXTI5_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EXTI_CFG2_EXTI5_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EXTI_CFG2_EXTI5_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EXTI_CFG2_EXTI5_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EXTI_CFG2_EXTI5_4 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EXTI_CFG2_EXTI5_5 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EXTI_CFG2_EXTI5_6 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EXTI_CFG2_EXTI5_7 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_EXTI_CFG2_EXTI4 ((uint32_t)0x000000FF) /* Bit[7:0] */ +#define AFIO_EXTI_CFG2_EXTI4_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EXTI_CFG2_EXTI4_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EXTI_CFG2_EXTI4_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EXTI_CFG2_EXTI4_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EXTI_CFG2_EXTI4_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EXTI_CFG2_EXTI4_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EXTI_CFG2_EXTI4_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EXTI_CFG2_EXTI4_7 ((uint32_t)0x00000080) /* Bit7*/ + +/******** Bit definition for AFIO_EXTI_CFG3 register ********/ +#define AFIO_EXTI_CFG3_EXTI11 ((uint32_t)0xFF000000) /* Bit[31:24] */ +#define AFIO_EXTI_CFG3_EXTI11_0 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EXTI_CFG3_EXTI11_1 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EXTI_CFG3_EXTI11_2 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EXTI_CFG3_EXTI11_3 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EXTI_CFG3_EXTI11_4 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EXTI_CFG3_EXTI11_5 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EXTI_CFG3_EXTI11_6 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EXTI_CFG3_EXTI11_7 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EXTI_CFG3_EXTI10 ((uint32_t)0x00FF0000) /* Bit[23:16] */ +#define AFIO_EXTI_CFG3_EXTI10_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EXTI_CFG3_EXTI10_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EXTI_CFG3_EXTI10_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EXTI_CFG3_EXTI10_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EXTI_CFG3_EXTI10_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EXTI_CFG3_EXTI10_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EXTI_CFG3_EXTI10_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EXTI_CFG3_EXTI10_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EXTI_CFG3_EXTI9 ((uint32_t)0x0000FF00) /* Bit[15:8] */ +#define AFIO_EXTI_CFG3_EXTI9_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EXTI_CFG3_EXTI9_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EXTI_CFG3_EXTI9_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EXTI_CFG3_EXTI9_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EXTI_CFG3_EXTI9_4 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EXTI_CFG3_EXTI9_5 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EXTI_CFG3_EXTI9_6 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EXTI_CFG3_EXTI9_7 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_EXTI_CFG3_EXTI8 ((uint32_t)0x000000FF) /* Bit[7:0] */ +#define AFIO_EXTI_CFG3_EXTI8_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EXTI_CFG3_EXTI8_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EXTI_CFG3_EXTI8_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EXTI_CFG3_EXTI8_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EXTI_CFG3_EXTI8_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EXTI_CFG3_EXTI8_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EXTI_CFG3_EXTI8_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EXTI_CFG3_EXTI8_7 ((uint32_t)0x00000080) /* Bit7*/ + +/******** Bit definition for AFIO_EXTI_CFG4 register ********/ +#define AFIO_EXTI_CFG4_EXTI15 ((uint32_t)0xFF000000) /* Bit[31:24] */ +#define AFIO_EXTI_CFG4_EXTI15_0 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EXTI_CFG4_EXTI15_1 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EXTI_CFG4_EXTI15_2 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EXTI_CFG4_EXTI15_3 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EXTI_CFG4_EXTI15_4 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EXTI_CFG4_EXTI15_5 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EXTI_CFG4_EXTI15_6 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EXTI_CFG4_EXTI15_7 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EXTI_CFG4_EXTI14 ((uint32_t)0x00FF0000) /* Bit[23:16] */ +#define AFIO_EXTI_CFG4_EXTI14_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EXTI_CFG4_EXTI14_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EXTI_CFG4_EXTI14_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EXTI_CFG4_EXTI14_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EXTI_CFG4_EXTI14_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EXTI_CFG4_EXTI14_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EXTI_CFG4_EXTI14_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EXTI_CFG4_EXTI14_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EXTI_CFG4_EXTI13 ((uint32_t)0x0000FF00) /* Bit[15:8] */ +#define AFIO_EXTI_CFG4_EXTI13_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EXTI_CFG4_EXTI13_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EXTI_CFG4_EXTI13_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EXTI_CFG4_EXTI13_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EXTI_CFG4_EXTI13_4 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EXTI_CFG4_EXTI13_5 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EXTI_CFG4_EXTI13_6 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EXTI_CFG4_EXTI13_7 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_EXTI_CFG4_EXTI12 ((uint32_t)0x000000FF) /* Bit[7:0] */ +#define AFIO_EXTI_CFG4_EXTI12_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EXTI_CFG4_EXTI12_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EXTI_CFG4_EXTI12_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EXTI_CFG4_EXTI12_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EXTI_CFG4_EXTI12_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EXTI_CFG4_EXTI12_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EXTI_CFG4_EXTI12_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EXTI_CFG4_EXTI12_7 ((uint32_t)0x00000080) /* Bit7*/ + +/******** Bit definition for AFIO_TOL5V_CFG1 register ********/ +#define AFIO_TOL5V_CFG1_PA7TOLENN ((uint32_t)0x00000200) /* Bit[9] */ +#define AFIO_TOL5V_CFG1_PA6TOLENN ((uint32_t)0x00000100) /* Bit[8] */ +#define AFIO_TOL5V_CFG1_PA5TOLENN ((uint32_t)0x00000080) /* Bit[7] */ +#define AFIO_TOL5V_CFG1_PA4TOLENN ((uint32_t)0x00000040) /* Bit[6] */ +#define AFIO_TOL5V_CFG1_PA3TOLENN ((uint32_t)0x00000020) /* Bit[5] */ +#define AFIO_TOL5V_CFG1_PA2TOLENN ((uint32_t)0x00000010) /* Bit[4] */ +#define AFIO_TOL5V_CFG1_PA1_C_TOLENN ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_TOL5V_CFG1_PA1TOLENN ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_TOL5V_CFG1_PA0_C_TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG1_PA0TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_TOL5V_CFG2 register ********/ +#define AFIO_TOL5V_CFG2_PB1TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG2_PB0TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_TOL5V_CFG3 register ********/ +#define AFIO_TOL5V_CFG3_PC13TOLENN ((uint32_t)0x00000400) /* Bit[10] */ +#define AFIO_TOL5V_CFG3_PC8TOLENN ((uint32_t)0x00000200) /* Bit[9] */ +#define AFIO_TOL5V_CFG3_PC6TOLENN ((uint32_t)0x00000100) /* Bit[8] */ +#define AFIO_TOL5V_CFG3_PC5TOLENN ((uint32_t)0x00000080) /* Bit[7] */ +#define AFIO_TOL5V_CFG3_PC4TOLENN ((uint32_t)0x00000040) /* Bit[6] */ +#define AFIO_TOL5V_CFG3_PC3_C_TOLENN ((uint32_t)0x00000020) /* Bit[5] */ +#define AFIO_TOL5V_CFG3_PC3TOLENN ((uint32_t)0x00000010) /* Bit[4] */ +#define AFIO_TOL5V_CFG3_PC2_C_TOLENN ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_TOL5V_CFG3_PC2TOLENN ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_TOL5V_CFG3_PC1TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG3_PC0TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_SHRT1_FALT_CFG register ********/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT6 ((uint32_t)0x00F00000) /* Bit[23:20] */ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT6_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT6_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT6_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT6_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT5 ((uint32_t)0x000F0000) /* Bit[19:16] */ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT5_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT5_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT5_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT5_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT4 ((uint32_t)0x0000F000) /* Bit[15:12] */ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT4_0 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT4_1 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT4_2 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT4_3 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT3 ((uint32_t)0x00000F00) /* Bit[11:8] */ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT3_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT3_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT3_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT3_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT2 ((uint32_t)0x000000F0) /* Bit[7:4] */ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT2_0 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT2_1 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT2_2 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT2_3 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT1 ((uint32_t)0x0000000F) /* Bit[3:0] */ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SHRT1_FALT_CFG_SHRT_FALT1_3 ((uint32_t)0x00000008) /* Bit3*/ + +/******** Bit definition for AFIO_SHRT2_FALT_CFG register ********/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT6 ((uint32_t)0x00F00000) /* Bit[23:20] */ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT6_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT6_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT6_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT6_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT5 ((uint32_t)0x000F0000) /* Bit[19:16] */ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT5_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT5_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT5_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT5_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT4 ((uint32_t)0x0000F000) /* Bit[15:12] */ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT4_0 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT4_1 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT4_2 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT4_3 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT3 ((uint32_t)0x00000F00) /* Bit[11:8] */ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT3_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT3_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT3_2 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT3_3 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT2 ((uint32_t)0x000000F0) /* Bit[7:4] */ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT2_0 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT2_1 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT2_2 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT2_3 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT1 ((uint32_t)0x0000000F) /* Bit[3:0] */ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SHRT2_FALT_CFG_SHRT_FALT1_3 ((uint32_t)0x00000008) /* Bit3*/ + +/******** Bit definition for AFIO_TOL5V_CFG4 register ********/ +#define AFIO_TOL5V_CFG4_PF14TOLENN ((uint32_t)0x00000800) /* Bit[11] */ +#define AFIO_TOL5V_CFG4_PF13TOLENN ((uint32_t)0x00000400) /* Bit[10] */ +#define AFIO_TOL5V_CFG4_PF12TOLENN ((uint32_t)0x00000200) /* Bit[9] */ +#define AFIO_TOL5V_CFG4_PF11TOLENN ((uint32_t)0x00000100) /* Bit[8] */ +#define AFIO_TOL5V_CFG4_PF10TOLENN ((uint32_t)0x00000080) /* Bit[7] */ +#define AFIO_TOL5V_CFG4_PF9TOLENN ((uint32_t)0x00000040) /* Bit[6] */ +#define AFIO_TOL5V_CFG4_PF8TOLENN ((uint32_t)0x00000020) /* Bit[5] */ +#define AFIO_TOL5V_CFG4_PF7TOLENN ((uint32_t)0x00000010) /* Bit[4] */ +#define AFIO_TOL5V_CFG4_PF6TOLENN ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_TOL5V_CFG4_PF5TOLENN ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_TOL5V_CFG4_PF4TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG4_PF3TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_TOL5V_CFG5 register ********/ +#define AFIO_TOL5V_CFG5_PH5TOLENN ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_TOL5V_CFG5_PH4TOLENN ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_TOL5V_CFG5_PH3TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG5_PH2TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_TOL5V_CFG6 register ********/ +#define AFIO_TOL5V_CFG6_PI15TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG6_PI8TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_TOL5V_CFG7 register ********/ +#define AFIO_TOL5V_CFG7_PJ7TOLENN ((uint32_t)0x00000020) /* Bit[5] */ +#define AFIO_TOL5V_CFG7_PJ6TOLENN ((uint32_t)0x00000010) /* Bit[4] */ +#define AFIO_TOL5V_CFG7_PJ5TOLENN ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_TOL5V_CFG7_PJ4TOLENN ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_TOL5V_CFG7_PJ3TOLENN ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_TOL5V_CFG7_PJ0TOLENN ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_EFT_CFG1 register ********/ +#define AFIO_EFT_CFG1_PB_EFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_EFT_CFG1_PB_EFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EFT_CFG1_PB_EFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EFT_CFG1_PB_EFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EFT_CFG1_PB_EFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EFT_CFG1_PB_EFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EFT_CFG1_PB_EFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EFT_CFG1_PB_EFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EFT_CFG1_PB_EFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EFT_CFG1_PB_EFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EFT_CFG1_PB_EFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EFT_CFG1_PB_EFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EFT_CFG1_PB_EFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EFT_CFG1_PB_EFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EFT_CFG1_PB_EFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EFT_CFG1_PB_EFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EFT_CFG1_PB_EFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EFT_CFG1_PA_EFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_EFT_CFG1_PA_EFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EFT_CFG1_PA_EFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EFT_CFG1_PA_EFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EFT_CFG1_PA_EFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EFT_CFG1_PA_EFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EFT_CFG1_PA_EFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EFT_CFG1_PA_EFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EFT_CFG1_PA_EFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_EFT_CFG1_PA_EFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EFT_CFG1_PA_EFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EFT_CFG1_PA_EFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EFT_CFG1_PA_EFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EFT_CFG1_PA_EFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EFT_CFG1_PA_EFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EFT_CFG1_PA_EFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EFT_CFG1_PA_EFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_EFT_CFG2 register ********/ +#define AFIO_EFT_CFG2_PD_EFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_EFT_CFG2_PD_EFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EFT_CFG2_PD_EFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EFT_CFG2_PD_EFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EFT_CFG2_PD_EFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EFT_CFG2_PD_EFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EFT_CFG2_PD_EFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EFT_CFG2_PD_EFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EFT_CFG2_PD_EFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EFT_CFG2_PD_EFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EFT_CFG2_PD_EFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EFT_CFG2_PD_EFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EFT_CFG2_PD_EFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EFT_CFG2_PD_EFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EFT_CFG2_PD_EFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EFT_CFG2_PD_EFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EFT_CFG2_PD_EFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EFT_CFG2_PC_EFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_EFT_CFG2_PC_EFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EFT_CFG2_PC_EFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EFT_CFG2_PC_EFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EFT_CFG2_PC_EFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EFT_CFG2_PC_EFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EFT_CFG2_PC_EFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EFT_CFG2_PC_EFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EFT_CFG2_PC_EFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_EFT_CFG2_PC_EFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EFT_CFG2_PC_EFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EFT_CFG2_PC_EFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EFT_CFG2_PC_EFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EFT_CFG2_PC_EFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EFT_CFG2_PC_EFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EFT_CFG2_PC_EFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EFT_CFG2_PC_EFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_EFT_CFG3 register ********/ +#define AFIO_EFT_CFG3_PF_EFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_EFT_CFG3_PF_EFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EFT_CFG3_PF_EFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EFT_CFG3_PF_EFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EFT_CFG3_PF_EFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EFT_CFG3_PF_EFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EFT_CFG3_PF_EFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EFT_CFG3_PF_EFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EFT_CFG3_PF_EFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EFT_CFG3_PF_EFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EFT_CFG3_PF_EFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EFT_CFG3_PF_EFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EFT_CFG3_PF_EFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EFT_CFG3_PF_EFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EFT_CFG3_PF_EFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EFT_CFG3_PF_EFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EFT_CFG3_PF_EFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EFT_CFG3_PE_EFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_EFT_CFG3_PE_EFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EFT_CFG3_PE_EFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EFT_CFG3_PE_EFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EFT_CFG3_PE_EFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EFT_CFG3_PE_EFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EFT_CFG3_PE_EFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EFT_CFG3_PE_EFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EFT_CFG3_PE_EFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_EFT_CFG3_PE_EFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EFT_CFG3_PE_EFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EFT_CFG3_PE_EFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EFT_CFG3_PE_EFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EFT_CFG3_PE_EFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EFT_CFG3_PE_EFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EFT_CFG3_PE_EFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EFT_CFG3_PE_EFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_EFT_CFG4 register ********/ +#define AFIO_EFT_CFG4_PH_EFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_EFT_CFG4_PH_EFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EFT_CFG4_PH_EFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EFT_CFG4_PH_EFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EFT_CFG4_PH_EFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EFT_CFG4_PH_EFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EFT_CFG4_PH_EFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EFT_CFG4_PH_EFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EFT_CFG4_PH_EFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EFT_CFG4_PH_EFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EFT_CFG4_PH_EFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EFT_CFG4_PH_EFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EFT_CFG4_PH_EFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EFT_CFG4_PH_EFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EFT_CFG4_PH_EFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EFT_CFG4_PH_EFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EFT_CFG4_PH_EFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EFT_CFG4_PG_EFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_EFT_CFG4_PG_EFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EFT_CFG4_PG_EFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EFT_CFG4_PG_EFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EFT_CFG4_PG_EFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EFT_CFG4_PG_EFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EFT_CFG4_PG_EFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EFT_CFG4_PG_EFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EFT_CFG4_PG_EFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_EFT_CFG4_PG_EFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EFT_CFG4_PG_EFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EFT_CFG4_PG_EFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EFT_CFG4_PG_EFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EFT_CFG4_PG_EFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EFT_CFG4_PG_EFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EFT_CFG4_PG_EFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EFT_CFG4_PG_EFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_EFT_CFG5 register ********/ +#define AFIO_EFT_CFG5_PI_EFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_EFT_CFG5_PI_EFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_EFT_CFG5_PI_EFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_EFT_CFG5_PI_EFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_EFT_CFG5_PI_EFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_EFT_CFG5_PI_EFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_EFT_CFG5_PI_EFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_EFT_CFG5_PI_EFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_EFT_CFG5_PI_EFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_EFT_CFG5_PI_EFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_EFT_CFG5_PI_EFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_EFT_CFG5_PI_EFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_EFT_CFG5_PI_EFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_EFT_CFG5_PI_EFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_EFT_CFG5_PI_EFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_EFT_CFG5_PI_EFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_EFT_CFG5_PI_EFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_EFT_CFG5_PJ_EFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_EFT_CFG5_PJ_EFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_EFT_CFG5_PJ_EFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_EFTIE_CFG6 register ********/ +#define AFIO_EFT_CFG6_JRST_ANA_FIL_BYPASS ((uint32_t)0x00000200) /* Bit[9] */ +#define AFIO_EFT_CFG6_BOOT_EFTEN ((uint32_t)0x00000100) /* Bit[8] */ +#define AFIO_EFT_CFG6_PK_EFTEN ((uint32_t)0x000000FF) /* Bit[7:0] */ +#define AFIO_EFT_CFG6_PK_EFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_EFT_CFG6_PK_EFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_EFT_CFG6_PK_EFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_EFT_CFG6_PK_EFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_EFT_CFG6_PK_EFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_EFT_CFG6_PK_EFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_EFT_CFG6_PK_EFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_EFT_CFG6_PK_EFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ + +/******** Bit definition for AFIO_DIGEFT_CFG1 register ********/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_DIGEFT_CFG1_PB_DIGEFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_DIGEFT_CFG1_PA_DIGEFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_DIGEFT_CFG2 register ********/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_DIGEFT_CFG2_PD_DIGEFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_DIGEFT_CFG2_PC_DIGEFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_DIGEFT_CFG3 register ********/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_DIGEFT_CFG3_PF_DIGEFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_DIGEFT_CFG3_PE_DIGEFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_DIGEFT_CFG4 register ********/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_DIGEFT_CFG4_PH_DIGEFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_DIGEFT_CFG4_PG_DIGEFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_DIGEFT_CFG5 register ********/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_DIGEFT_CFG5_PI_DIGEFTEN_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_DIGEFT_CFG5_PJ_DIGEFTEN_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_DIGEFT_CFG6 register ********/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN ((uint32_t)0x000000FF) /* Bit[7:0] */ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_DIGEFT_CFG6_PK_DIGEFTEN_7 ((uint32_t)0x00000080) /* Bit7*/ + +/******** Bit definition for AFIO_SHRT1_EXEV_CFG1 register ********/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV5 ((uint32_t)0x01F00000) /* Bit[24:20] */ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV5_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV5_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV5_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV5_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV5_4 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV4 ((uint32_t)0x000F8000) /* Bit[19:15] */ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV4_0 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV4_1 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV4_2 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV4_3 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV4_4 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV3 ((uint32_t)0x00007C00) /* Bit[14:10] */ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV3_0 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV3_1 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV3_2 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV3_3 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV3_4 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV2 ((uint32_t)0x000003E0) /* Bit[9:5] */ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV2_0 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV2_1 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV2_2 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV2_3 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV2_4 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1 ((uint32_t)0x0000001F) /* Bit[4:0] */ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1_4 ((uint32_t)0x00000010) /* Bit4*/ + +/******** Bit definition for AFIO_SHRT1_EXEV_CFG2 register ********/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV10 ((uint32_t)0x01F00000) /* Bit[24:20] */ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV10_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV10_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV10_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV10_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV10_4 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV9 ((uint32_t)0x000F8000) /* Bit[19:15] */ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV9_0 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV9_1 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV9_2 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV9_3 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV9_4 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV8 ((uint32_t)0x00007C00) /* Bit[14:10] */ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV8_0 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV8_1 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV8_2 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV8_3 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV8_4 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV7 ((uint32_t)0x000003E0) /* Bit[9:5] */ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV7_0 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV7_1 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV7_2 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV7_3 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV7_4 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV6 ((uint32_t)0x0000001F) /* Bit[4:0] */ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV6_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV6_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV6_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV6_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SHRT1_EXEV_CFG2_SHRT_EXEV6_4 ((uint32_t)0x00000010) /* Bit4*/ + +/******** Bit definition for AFIO_SHRT2_EXEV_CFG1 register ********/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV5 ((uint32_t)0x01F00000) /* Bit[24:20] */ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV5_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV5_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV5_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV5_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV5_4 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV4 ((uint32_t)0x000F8000) /* Bit[19:15] */ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV4_0 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV4_1 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV4_2 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV4_3 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV4_4 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV3 ((uint32_t)0x00007C00) /* Bit[14:10] */ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV3_0 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV3_1 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV3_2 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV3_3 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV3_4 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV2 ((uint32_t)0x000003E0) /* Bit[9:5] */ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV2_0 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV2_1 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV2_2 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV2_3 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV2_4 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1 ((uint32_t)0x0000001F) /* Bit[4:0] */ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1_4 ((uint32_t)0x00000010) /* Bit4*/ + +/******** Bit definition for AFIO_SHRT2_EXEV_CFG2 register ********/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV10 ((uint32_t)0x01F00000) /* Bit[24:20] */ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV10_0 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV10_1 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV10_2 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV10_3 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV10_4 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV9 ((uint32_t)0x000F8000) /* Bit[19:15] */ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV9_0 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV9_1 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV9_2 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV9_3 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV9_4 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV8 ((uint32_t)0x00007C00) /* Bit[14:10] */ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV8_0 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV8_1 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV8_2 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV8_3 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV8_4 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV7 ((uint32_t)0x000003E0) /* Bit[9:5] */ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV7_0 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV7_1 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV7_2 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV7_3 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV7_4 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV6 ((uint32_t)0x0000001F) /* Bit[4:0] */ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV6_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV6_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV6_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV6_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SHRT2_EXEV_CFG2_SHRT_EXEV6_4 ((uint32_t)0x00000010) /* Bit4*/ + +/******** Bit definition for AFIO_SIP_PUPD register ********/ +#define AFIO_SIP_PUPD_PUPD7 ((uint32_t)0x0000C000) /* Bit[15:14] */ +#define AFIO_SIP_PUPD_PUPD7_0 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SIP_PUPD_PUPD7_1 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SIP_PUPD_PUPD6 ((uint32_t)0x00003000) /* Bit[13:12] */ +#define AFIO_SIP_PUPD_PUPD6_0 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SIP_PUPD_PUPD6_1 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SIP_PUPD_PUPD5 ((uint32_t)0x00000C00) /* Bit[11:10] */ +#define AFIO_SIP_PUPD_PUPD5_0 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SIP_PUPD_PUPD5_1 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SIP_PUPD_PUPD4 ((uint32_t)0x00000300) /* Bit[9:8] */ +#define AFIO_SIP_PUPD_PUPD4_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SIP_PUPD_PUPD4_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SIP_PUPD_PUPD3 ((uint32_t)0x000000C0) /* Bit[7:6] */ +#define AFIO_SIP_PUPD_PUPD3_0 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SIP_PUPD_PUPD3_1 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SIP_PUPD_PUPD2 ((uint32_t)0x00000030) /* Bit[5:4] */ +#define AFIO_SIP_PUPD_PUPD2_0 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SIP_PUPD_PUPD2_1 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SIP_PUPD_PUPD1 ((uint32_t)0x0000000C) /* Bit[3:2] */ +#define AFIO_SIP_PUPD_PUPD1_0 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SIP_PUPD_PUPD1_1 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SIP_PUPD_PUPD0 ((uint32_t)0x00000003) /* Bit[1:0] */ +#define AFIO_SIP_PUPD_PUPD0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SIP_PUPD_PUPD0_1 ((uint32_t)0x00000002) /* Bit1*/ + +/******** Bit definition for AFIO_SDRAM_HSMOD_CFG1 register ********/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSA_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAM_HSMOD_CFG1_HSB_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_SDRAM_HSMOD_CFG2 register ********/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSC_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAM_HSMOD_CFG2_HSD_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_SDRAM_HSMOD_CFG3 register ********/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSE_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAM_HSMOD_CFG3_HSF_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_SDRAM_HSMOD_CFG4 register ********/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSG_15 ((uint32_t)0x80000000) /* Bit31*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH ((uint32_t)0x0000FFFF) /* Bit[15:0] */ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAM_HSMOD_CFG4_HSH_15 ((uint32_t)0x00008000) /* Bit15*/ + +/******** Bit definition for AFIO_SDRAM_HSMOD_CFG5 register ********/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI ((uint32_t)0xFFFF0000) /* Bit[31:16] */ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_0 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_1 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_2 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_3 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_4 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_5 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_6 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_7 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_8 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_9 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_10 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_11 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_12 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_13 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_14 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_HSMOD_CFG5_HSI_15 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SIP_SR register ********/ +#define AFIO_SIP_SR_SR7 ((uint32_t)0x00000080) /* Bit[7] */ +#define AFIO_SIP_SR_SR6 ((uint32_t)0x00000040) /* Bit[6] */ +#define AFIO_SIP_SR_SR5 ((uint32_t)0x00000020) /* Bit[5] */ +#define AFIO_SIP_SR_SR4 ((uint32_t)0x00000010) /* Bit[4] */ +#define AFIO_SIP_SR_SR3 ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_SIP_SR_SR2 ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_SIP_SR_SR1 ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_SIP_SR_SR0 ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_SIPDS_CFG register ********/ +#define AFIO_SIP_DS_DS7 ((uint32_t)0x0000C000) /* Bit[15:14] */ +#define AFIO_SIP_DS_DS7_0 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SIP_DS_DS7_1 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SIP_DS_DS6 ((uint32_t)0x00003000) /* Bit[13:12] */ +#define AFIO_SIP_DS_DS6_0 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SIP_DS_DS6_1 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SIP_DS_DS5 ((uint32_t)0x00000C00) /* Bit[11:10] */ +#define AFIO_SIP_DS_DS5_0 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SIP_DS_DS5_1 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SIP_DS_DS4 ((uint32_t)0x00000300) /* Bit[9:8] */ +#define AFIO_SIP_DS_DS4_0 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SIP_DS_DS4_1 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SIP_DS_DS3 ((uint32_t)0x000000C0) /* Bit[7:6] */ +#define AFIO_SIP_DS_DS3_0 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SIP_DS_DS3_1 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SIP_DS_DS2 ((uint32_t)0x00000030) /* Bit[5:4] */ +#define AFIO_SIP_DS_DS2_0 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SIP_DS_DS2_1 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SIP_DS_DS1 ((uint32_t)0x0000000C) /* Bit[3:2] */ +#define AFIO_SIP_DS_DS1_0 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SIP_DS_DS1_1 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SIP_DS_DS0 ((uint32_t)0x00000003) /* Bit[1:0] */ +#define AFIO_SIP_DS_DS0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SIP_DS_DS0_1 ((uint32_t)0x00000002) /* Bit1*/ + +/******** Bit definition for AFIO_ADCSW_CFG register ********/ +#define AFIO_ADCSW_CFG_VREF ((uint32_t)0x10000000) /* Bit[28] */ +#define AFIO_ADCSW_CFG_SW_PJ7 ((uint32_t)0x08000000) /* Bit[27] */ +#define AFIO_ADCSW_CFG_SW_PJ6 ((uint32_t)0x04000000) /* Bit[26] */ +#define AFIO_ADCSW_CFG_SW_DAC135_OUT ((uint32_t)0x03800000) /* Bit[25:23] */ +#define AFIO_ADCSW_CFG_SW_DAC5_OUT ((uint32_t)0x02000000) /* Bit[25] */ +#define AFIO_ADCSW_CFG_SW_DAC3_OUT ((uint32_t)0x01000000) /* Bit[24] */ +#define AFIO_ADCSW_CFG_SW_DAC1_OUT ((uint32_t)0x00800000) /* Bit[23] */ +#define AFIO_ADCSW_CFG_SW_PJ5 ((uint32_t)0x00400000) /* Bit[22] */ +#define AFIO_ADCSW_CFG_SW_PJ4 ((uint32_t)0x00200000) /* Bit[21] */ +#define AFIO_ADCSW_CFG_SW_TEMP ((uint32_t)0x00100000) /* Bit[20] */ +#define AFIO_ADCSW_CFG_SW_PJ3 ((uint32_t)0x00080000) /* Bit[19] */ +#define AFIO_ADCSW_CFG_SW_PJ0 ((uint32_t)0x00040000) /* Bit[18] */ +#define AFIO_ADCSW_CFG_SW_DAC246_OUT ((uint32_t)0x00038000) /* Bit[17:15] */ +#define AFIO_ADCSW_CFG_SW_DAC6_OUT ((uint32_t)0x00020000) /* Bit[17] */ +#define AFIO_ADCSW_CFG_SW_DAC4_OUT ((uint32_t)0x00010000) /* Bit[16] */ +#define AFIO_ADCSW_CFG_SW_DAC2_OUT ((uint32_t)0x00008000) /* Bit[15] */ +#define AFIO_ADCSW_CFG_VBAT ((uint32_t)0x00004000) /* Bit[14] */ +#define AFIO_ADCSW_CFG_SWPI15 ((uint32_t)0x00003000) /* Bit[13:12] */ +#define AFIO_ADCSW_CFG_SWPI15_1 ((uint32_t)0x00002000) /* Bit[13] */ +#define AFIO_ADCSW_CFG_SWPI15_0 ((uint32_t)0x00001000) /* Bit[12] */ +#define AFIO_ADCSW_CFG_SWPA1_C ((uint32_t)0x00000C00) /* Bit[11:10] */ +#define AFIO_ADCSW_CFG_SWPA1_C_1 ((uint32_t)0x00000800) /* Bit[11] */ +#define AFIO_ADCSW_CFG_SWPA1_C_0 ((uint32_t)0x00000400) /* Bit[10] */ +#define AFIO_ADCSW_CFG_SWPC3_C ((uint32_t)0x00000300) /* Bit[9:8] */ +#define AFIO_ADCSW_CFG_SWPC3_C_1 ((uint32_t)0x00000200) /* Bit[9] */ +#define AFIO_ADCSW_CFG_SWPC3_C_0 ((uint32_t)0x00000100) /* Bit[8] */ +#define AFIO_ADCSW_CFG_SWPC2_C ((uint32_t)0x000000F0) /* Bit[7:4] */ +#define AFIO_ADCSW_CFG_SWPC2_C_3 ((uint32_t)0x00000080) /* Bit[7] */ +#define AFIO_ADCSW_CFG_SWPC2_C_2 ((uint32_t)0x00000040) /* Bit[6] */ +#define AFIO_ADCSW_CFG_SWPC2_C_1 ((uint32_t)0x00000020) /* Bit[5] */ +#define AFIO_ADCSW_CFG_SWPC2_C_0 ((uint32_t)0x00000010) /* Bit[4] */ +#define AFIO_ADCSW_CFG_SWPA0_C ((uint32_t)0x0000000F) /* Bit[3:0] */ +#define AFIO_ADCSW_CFG_SWPA0_C_3 ((uint32_t)0x00000008) /* Bit[3] */ +#define AFIO_ADCSW_CFG_SWPA0_C_2 ((uint32_t)0x00000004) /* Bit[2] */ +#define AFIO_ADCSW_CFG_SWPA0_C_1 ((uint32_t)0x00000002) /* Bit[1] */ +#define AFIO_ADCSW_CFG_SWPA0_C_0 ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for AFIO_SDRAM_VREF_EN0 register ********/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0 ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_15 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_16 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_17 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_18 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_19 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_20 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_21 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_22 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_23 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_24 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_25 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_26 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_27 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_28 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_29 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_30 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_VREF_EN0_VREF_EN0_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SDRAM_VREF_EN1 register ********/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1 ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_15 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_16 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_17 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_18 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_19 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_20 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_21 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_22 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_23 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_24 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_25 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_26 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_27 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_28 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_29 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_30 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAM_VREF_EN1_VREF_EN1_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SDRAM_VREF_EN2 register ********/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2 ((uint32_t)0x000007FF) /* Bit[10:0] */ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAM_VREF_EN2_VREF_EN2_10 ((uint32_t)0x00000400) /* Bit10*/ + +/******** Bit definition for AFIO_SDRAMDSN_CFG0 register ********/ +#define AFIO_SDRAMDSN_CFG0_DSN0 ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define AFIO_SDRAMDSN_CFG0_DSN0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_15 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_16 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_17 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_18 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_19 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_20 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_21 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_22 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_23 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_24 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_25 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_26 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_27 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_28 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_29 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_30 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAMDSN_CFG0_DSN0_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SDRAMDSN_CFG1 register ********/ +#define AFIO_SDRAMDSN_CFG1_DSN1 ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define AFIO_SDRAMDSN_CFG1_DSN1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_15 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_16 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_17 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_18 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_19 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_20 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_21 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_22 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_23 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_24 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_25 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_26 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_27 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_28 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_29 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_30 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAMDSN_CFG1_DSN1_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SDRAMDSN_CFG2 register ********/ +#define AFIO_SDRAMDSN_CFG2_DSN2 ((uint32_t)0x000007FF) /* Bit[10:0] */ +#define AFIO_SDRAMDSN_CFG2_DSN2_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAMDSN_CFG2_DSN2_10 ((uint32_t)0x00000400) /* Bit10*/ + +/******** Bit definition for AFIO_SDRAMDSP_CFG0 register ********/ +#define AFIO_SDRAMDSP_CFG0_DSP0 ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define AFIO_SDRAMDSP_CFG0_DSP0_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_15 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_16 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_17 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_18 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_19 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_20 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_21 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_22 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_23 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_24 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_25 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_26 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_27 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_28 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_29 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_30 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAMDSP_CFG0_DSP0_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SDRAMDSP_CFG1 register ********/ +#define AFIO_SDRAMDSP_CFG1_DSP1 ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define AFIO_SDRAMDSP_CFG1_DSP1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_10 ((uint32_t)0x00000400) /* Bit10*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_11 ((uint32_t)0x00000800) /* Bit11*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_12 ((uint32_t)0x00001000) /* Bit12*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_13 ((uint32_t)0x00002000) /* Bit13*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_14 ((uint32_t)0x00004000) /* Bit14*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_15 ((uint32_t)0x00008000) /* Bit15*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_16 ((uint32_t)0x00010000) /* Bit16*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_17 ((uint32_t)0x00020000) /* Bit17*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_18 ((uint32_t)0x00040000) /* Bit18*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_19 ((uint32_t)0x00080000) /* Bit19*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_20 ((uint32_t)0x00100000) /* Bit20*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_21 ((uint32_t)0x00200000) /* Bit21*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_22 ((uint32_t)0x00400000) /* Bit22*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_23 ((uint32_t)0x00800000) /* Bit23*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_24 ((uint32_t)0x01000000) /* Bit24*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_25 ((uint32_t)0x02000000) /* Bit25*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_26 ((uint32_t)0x04000000) /* Bit26*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_27 ((uint32_t)0x08000000) /* Bit27*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_28 ((uint32_t)0x10000000) /* Bit28*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_29 ((uint32_t)0x20000000) /* Bit29*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_30 ((uint32_t)0x40000000) /* Bit30*/ +#define AFIO_SDRAMDSP_CFG1_DSP1_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for AFIO_SDRAMDSP_CFG2 register ********/ +#define AFIO_SDRAMDSP_CFG2_DSP2 ((uint32_t)0x000007FF) /* Bit[10:0] */ +#define AFIO_SDRAMDSP_CFG2_DSP2_0 ((uint32_t)0x00000001) /* Bit0*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_1 ((uint32_t)0x00000002) /* Bit1*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_2 ((uint32_t)0x00000004) /* Bit2*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_3 ((uint32_t)0x00000008) /* Bit3*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_4 ((uint32_t)0x00000010) /* Bit4*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_5 ((uint32_t)0x00000020) /* Bit5*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_6 ((uint32_t)0x00000040) /* Bit6*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_7 ((uint32_t)0x00000080) /* Bit7*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_8 ((uint32_t)0x00000100) /* Bit8*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_9 ((uint32_t)0x00000200) /* Bit9*/ +#define AFIO_SDRAMDSP_CFG2_DSP2_10 ((uint32_t)0x00000400) /* Bit10*/ + + + +/*** Analog to Digital Converter Peripheral Interface ***/ +/******************** Bit definition for ADC_STS register ********************/ +#define ADC_STS_ALL ((uint32_t)0x0003EB7FU) +#define ADC_STS_WEFLAG ((uint32_t)0x00020000U) /* Bit[17] FIFO write error status */ +#define ADC_STS_REFLAG ((uint32_t)0x00010000U) /* Bit[16] FIFO read error status */ +#define ADC_STS_ROSOVFDSMU ((uint32_t)0x00004000U) /* Bit[14] Regular channel oversampling overrun flag in DSMU mode */ +#define ADC_STS_JOSOVF ((uint32_t)0x00002000U) /* Bit[13] Injected channel oversampling overrun flag*/ +#define ADC_STS_ROSOVF ((uint32_t)0x00001000U) /* Bit[12] Regular channel oversampling overrun flag*/ +#define ADC_STS_EOSAMP ((uint32_t)0x00000800U) /* Bit[11] End of Sampling */ +#define ADC_STS_PDRDY ((uint32_t)0x00000200U) /* Bit[9] ADC power down ready*/ +#define ADC_STS_RDY ((uint32_t)0x00000100U) /* Bit[8] ADC power up ready */ +#define ADC_STS_AWDG1 ((uint32_t)0x00000040U) /* Bit[6] Analog watchdog 1 flag */ +#define ADC_STS_STR ((uint32_t)0x00000020U) /* Bit[5] Regular channel Start flag */ +#define ADC_STS_JENDCA ((uint32_t)0x00000010U) /* Bit[4] Any injected channel end of conversion */ +#define ADC_STS_JENDC ((uint32_t)0x00000008U) /* Bit[3] Injected channel end of conversion */ +#define ADC_STS_JSTR ((uint32_t)0x00000004U) /* Bit[2] Injected channel Start flag*/ +#define ADC_STS_ENDCA ((uint32_t)0x00000002U) /* Bit[1] Any end of conversion */ +#define ADC_STS_ENDC ((uint32_t)0x00000001U) /* Bit[0] End of conversion */ + +/******************* Bit definition for ADC_CTRL1 register ********************/ +#define ADC_CTRL1_WEIEN ((uint32_t)0x40000000U) /* Bit[30] FIFO write error interrupt enable */ +#define ADC_CTRL1_REIEN ((uint32_t)0x20000000U) /* Bit[29] FIFO read error interrupt enable*/ + +#define ADC_CTRL1_EOSMPIEN ((uint32_t)0x10000000U) /* Bit[28] End of Sampling interrupt enable */ +#define ADC_CTRL1_PDRDYIEN ((uint32_t)0x08000000U) /* Bit[27] ADC power up ready interrupt enable */ +#define ADC_CTRL1_RDYIEN ((uint32_t)0x04000000U) /* Bit[26] ADC power up ready interrupt enable */ +#define ADC_CTRL1_DJCH ((uint32_t)0x01000000U) /* Bit[24] Discontinuous mode on injected channels */ +#define ADC_CTRL1_DREGCH ((uint32_t)0x00800000U) /* Bit[23] Discontinuous mode on regular channels*/ +#define ADC_CTRL1_AWD1ERCH ((uint32_t)0x00400000U) /* Bit[22] Analog watchdog 1 enable on regular channels */ +#define ADC_CTRL1_AWD1EJCH ((uint32_t)0x00200000U) /* Bit[21] Analog watchdog 1 enable on injected channels */ + +#define ADC_CTRL1_AWD1CH ((uint32_t)0x001F0000U) /* Bit[20:16] Analog watchdog 1 channel select bits */ +#define ADC_CTRL1_AWD1CH_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define ADC_CTRL1_AWD1CH_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define ADC_CTRL1_AWD1CH_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define ADC_CTRL1_AWD1CH_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define ADC_CTRL1_AWD1CH_4 ((uint32_t)0x00100000U) /* Bit20*/ + +#define ADC_CTRL1_MULTMODE ((uint32_t)0x0000F800U) /* Bit[15:11] Mult-ADC mode selection*/ +#define ADC_CTRL1_MULTMODE_0 ((uint32_t)0x00000800U) /* Bit11*/ +#define ADC_CTRL1_MULTMODE_1 ((uint32_t)0x00001000U) /* Bit12*/ +#define ADC_CTRL1_MULTMODE_2 ((uint32_t)0x00002000U) /* Bit13*/ +#define ADC_CTRL1_MULTMODE_3 ((uint32_t)0x00004000U) /* Bit14*/ +#define ADC_CTRL1_MULTMODE_4 ((uint32_t)0x00008000U) /* Bit15*/ + +#define ADC_CTRL1_DCTU ((uint32_t)0x00000700U) /* Bit[10:8] DISC_NUM[2:0] bits (Discontinuous mode channel count)*/ +#define ADC_CTRL1_DCTU_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define ADC_CTRL1_DCTU_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define ADC_CTRL1_DCTU_2 ((uint32_t)0x00000400U) /* Bit10*/ + +#define ADC_CTRL1_AUTOJC ((uint32_t)0x00000080U) /* Bit[7] Automatic injected group conversion*/ +#define ADC_CTRL1_AWD1SGLEN ((uint32_t)0x00000040U) /* Bit[6] Enable the watchdog 1 on a single channel in scan mode */ + +#define ADC_CTRL1_AWD1IEN ((uint32_t)0x00000020U) /* Bit[5] Analog watchdog 1 interrupt enable*/ +#define ADC_CTRL1_JENDCIEN ((uint32_t)0x00000010U) /* Bit[4] Injected channel end of conversion interrupt enable */ +#define ADC_CTRL1_JENDCAIEN ((uint32_t)0x00000008U) /* Bit[3] Any injected channel end of conversion interrupt enable */ +#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000004U) /* Bit[2] End of conversion interrupt enable*/ +#define ADC_CTRL1_ENDCAIEN ((uint32_t)0x00000002U) /* Bit[1] Any end of conversion interrupt enable */ + +#define ADC_CTRL1_SCANMD ((uint32_t)0x00000001U) /* Bit[0] Scan mode */ + +/******************* Bit definition for ADC_CTRL2 register ********************/ +#define ADC_CTRL2_EXTPRSEL ((uint32_t)0xC0000000U) /* Bit[31:30] External trigger enable and polarity selection for regular channels */ +#define ADC_CTRL2_EXTPRSEL_0 ((uint32_t)0x40000000U) /* Bit30*/ +#define ADC_CTRL2_EXTPRSEL_1 ((uint32_t)0x80000000U) /* Bit31*/ + +#define ADC_CTRL2_EXTRSEL ((uint32_t)0x3F000000U) /* Bit[29:24] External event select for regular group */ +#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define ADC_CTRL2_EXTRSEL_3 ((uint32_t)0x08000000U) /* Bit27*/ +#define ADC_CTRL2_EXTRSEL_4 ((uint32_t)0x10000000U) /* Bit28*/ +#define ADC_CTRL2_EXTRSEL_5 ((uint32_t)0x20000000U) /* Bit29*/ + +#define ADC_CTRL2_TEMPEN ((uint32_t)0x00800000U) /* Bit[23] Temperature Sensor Enable*/ +#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00400000U) /* Bit[22] Start Conversion of regular channels*/ +#define ADC_CTRL2_SWSTRJCH ((uint32_t)0x00200000U) /* Bit[21] Start Conversion of injected channels*/ +#define ADC_CTRL2_EXTTRIG ((uint32_t)0x00100000U) /* Bit[20] External event trigger of regular channels enable*/ + +#define ADC_CTRL2_EXTJSEL ((uint32_t)0x0007E000U) /* Bit[18:13] External event select for injected group*/ +#define ADC_CTRL2_EXTJSEL_0 ((uint32_t)0x00002000U) /* Bit13*/ +#define ADC_CTRL2_EXTJSEL_1 ((uint32_t)0x00004000U) /* Bit14*/ +#define ADC_CTRL2_EXTJSEL_2 ((uint32_t)0x00008000U) /* Bit15*/ +#define ADC_CTRL2_EXTJSEL_3 ((uint32_t)0x00010000U) /* Bit16*/ +#define ADC_CTRL2_EXTJSEL_4 ((uint32_t)0x00020000U) /* Bit17*/ +#define ADC_CTRL2_EXTJSEL_5 ((uint32_t)0x00040000U) /* Bit18*/ + +#define ADC_CTRL2_JEXTTRIG ((uint32_t)0x00001000U) /* Bit[12] External event trigger of injected channels enable*/ +#define ADC_CTRL2_ALIG ((uint32_t)0x00000800U) /* Bit[11] Data Alignment*/ + +#define ADC_CTRL2_EXTPJSEL ((uint32_t)0x00000600U) /* Bit[10:9] External trigger enable and polarity selection for injected channels*/ +#define ADC_CTRL2_EXTPJSEL_0 ((uint32_t)0x00000200U) /* Bit9*/ +#define ADC_CTRL2_EXTPJSEL_1 ((uint32_t)0x00000400U) /* Bit10*/ + +#define ADC_CTRL2_DMAMD ((uint32_t)0x00000180U) /* Bit[8:7] DMA mode*/ +#define ADC_CTRL2_DMAMD_0 ((uint32_t)0x00000080U) /* Bit7*/ +#define ADC_CTRL2_DMAMD_1 ((uint32_t)0x00000100U) /* Bit8*/ + +#define ADC_CTRL2_MDSMU ((uint32_t)0x00000040U) /* Bit[6] Multi-adc DSMU mode*/ + +#define ADC_CTRL2_DMNGT ((uint32_t)0x00000030U) /* Bit[5:4] Data management configuration for regular conversion data*/ +#define ADC_CTRL2_DMNGT_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define ADC_CTRL2_DMNGT_1 ((uint32_t)0x00000020U) /* Bit5*/ + +#define ADC_CTRL2_ENCAL ((uint32_t)0x00000004U) /* Bit[2] A/D Calibration */ +#define ADC_CTRL2_CTU ((uint32_t)0x00000002U) /* Bit[1] Continuous Conversion*/ +#define ADC_CTRL2_ON ((uint32_t)0x00000001U) /* Bit[0] A/D Converter ON / OFF */ + +/******************* Bit definition for ADC_CTRL3 register ********************/ +#define ADC_CTRL3_GCOMP_SATEN ((uint32_t)0x20000000U) /* Bit[29] Gain compensation saturation enable*/ +#define ADC_CTRL3_GCOMPEN ((uint32_t)0x10000000U) /* Bit[28] Gain compensation Enable*/ + +#define ADC_CTRL3_SWJSTOP ((uint32_t)0x08000000U) /* Bit[27] Stop Conversion of injected channels*/ +#define ADC_CTRL3_SWRSTOP ((uint32_t)0x04000000U) /* Bit[26] Stop Conversion of regular channels*/ + +#define ADC_CTRL3_JSTART ((uint32_t)0x02000000U) /* Bit[25] ADC start of injected conversion*/ +#define ADC_CTRL3_RSTART ((uint32_t)0x01000000U) /* Bit[24] ADC start of regular conversion*/ + +#define ADC_CTRL3_VBATMEN ((uint32_t)0x00000200U) /* Bit[9] Vbat monitor enable*/ +#define ADC_CTRL3_VREFINTEN ((uint32_t)0x00000100U) /* Bit[8] Internal Vrefence Voltage enable*/ + +#define ADC_CTRL3_BPCAL ((uint32_t)0x00000080U) /* Bit[7] Bypass calibration*/ + +#define ADC_CTRL3_PDRDY ((uint32_t)0x00000040U) /* Bit[6] 6.0*/ +#define ADC_CTRL3_RDY ((uint32_t)0x00000020U) /* Bit[5] 5.0*/ + +#define ADC_CTRL3_CLOCKMOD ((uint32_t)0x00000010U) /* Bit[4] Clock Mode*/ + +#define ADC_CTRL3_RES ((uint32_t)0x00000002U) /* Bit[1] Data resolution*/ + +/****************** Bit definition for ADC_SAMPT1 register *******************/ +#define ADC_SAMPT1_SAMP0 ((uint32_t)0x0000000FU) /* SAMP0[3:0] bits (Channel 0 Sample time selection) */ +#define ADC_SAMPT1_SAMP0_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP0_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP0_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP0_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP1 ((uint32_t)0x000000F0U) /* SAMP1[3:0] bits (Channel 1 Sample time selection) */ +#define ADC_SAMPT1_SAMP1_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP1_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP1_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP1_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP2 ((uint32_t)0x00000F00U) /* SAMP2[3:0] bits (Channel 2 Sample time selection) */ +#define ADC_SAMPT1_SAMP2_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP2_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP2_2 ((uint32_t)0x00000400U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP2_3 ((uint32_t)0x00000800U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP3 ((uint32_t)0x0000F000U) /* SAMP3[3:0] bits (Channel 3 Sample time selection) */ +#define ADC_SAMPT1_SAMP3_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP3_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP3_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP3_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP4 ((uint32_t)0x000F0000U) /* SAMP4[3:0] bits (Channel 4 Sample time selection) */ +#define ADC_SAMPT1_SAMP4_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP4_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP4_2 ((uint32_t)0x00040000U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP4_3 ((uint32_t)0x00080000U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP5 ((uint32_t)0x00F00000U) /* SAMP5[3:0] bits (Channel 5 Sample time selection) */ +#define ADC_SAMPT1_SAMP5_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP5_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP5_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP5_3 ((uint32_t)0x00800000U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP6 ((uint32_t)0x0F000000U) /* SAMP6[3:0] bits (Channel 6 Sample time selection) */ +#define ADC_SAMPT1_SAMP6_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP6_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP6_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP6_3 ((uint32_t)0x08000000U) /* Bit 3 */ + +#define ADC_SAMPT1_SAMP7 ((uint32_t)0xF0000000U) /* SAMP7[3:0] bits (Channel 7 Sample time selection) */ +#define ADC_SAMPT1_SAMP7_0 ((uint32_t)0x10000000U) /* Bit 0 */ +#define ADC_SAMPT1_SAMP7_1 ((uint32_t)0x20000000U) /* Bit 1 */ +#define ADC_SAMPT1_SAMP7_2 ((uint32_t)0x40000000U) /* Bit 2 */ +#define ADC_SAMPT1_SAMP7_3 ((uint32_t)0x80000000U) /* Bit 3 */ + +/****************** Bit definition for ADC_SAMPT2 register *******************/ +#define ADC_SAMPT2_SAMP8 ((uint32_t)0x0000000FU) /* SAMP8[3:0] bits (Channel 8 Sample time selection) */ +#define ADC_SAMPT2_SAMP8_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP8_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP8_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP8_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP9 ((uint32_t)0x000000F0U) /* SAMP9[3:0] bits (Channel 9 Sample time selection) */ +#define ADC_SAMPT2_SAMP9_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP9_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP9_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP9_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP10 ((uint32_t)0x00000F00U) /* SAMP10[3:0] bits (Channel 10 Sample time selection) */ +#define ADC_SAMPT2_SAMP10_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP10_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP10_2 ((uint32_t)0x00000400U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP10_3 ((uint32_t)0x00000800U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP11 ((uint32_t)0x0000F000U) /* SAMP11[3:0] bits (Channel 11 Sample time selection) */ +#define ADC_SAMPT2_SAMP11_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP11_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP11_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP11_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP12 ((uint32_t)0x000F0000U) /* SAMP12[3:0] bits (Channel 12 Sample time selection) */ +#define ADC_SAMPT2_SAMP12_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP12_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP12_2 ((uint32_t)0x00040000U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP12_3 ((uint32_t)0x00080000U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP13 ((uint32_t)0x00F00000U) /* SAMP13[3:0] bits (Channel 13 Sample time selection) */ +#define ADC_SAMPT2_SAMP13_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP13_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP13_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP13_3 ((uint32_t)0x00800000U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP14 ((uint32_t)0x0F000000U) /* SAMP14[3:0] bits (Channel 14 Sample time selection) */ +#define ADC_SAMPT2_SAMP14_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP14_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP14_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP14_3 ((uint32_t)0x08000000U) /* Bit 3 */ + +#define ADC_SAMPT2_SAMP15 ((uint32_t)0xF0000000U) /* SAMP15[3:0] bits (Channel 15 Sample time selection) */ +#define ADC_SAMPT2_SAMP15_0 ((uint32_t)0x10000000U) /* Bit 0 */ +#define ADC_SAMPT2_SAMP15_1 ((uint32_t)0x20000000U) /* Bit 1 */ +#define ADC_SAMPT2_SAMP15_2 ((uint32_t)0x40000000U) /* Bit 2 */ +#define ADC_SAMPT2_SAMP15_3 ((uint32_t)0x80000000U) /* Bit 3 */ + +/****************** Bit definition for ADC_SAMPT3 register *******************/ +#define ADC_SAMPT3_SAMP16 ((uint32_t)0x0000000FU) /* SAMP16[3:0] bits (Channel 16 Sample time selection) */ +#define ADC_SAMPT3_SAMP16_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_SAMPT3_SAMP16_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_SAMPT3_SAMP16_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_SAMPT3_SAMP16_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +#define ADC_SAMPT3_SAMP17 ((uint32_t)0x000000F0U) /* SAMP17[3:0] bits (Channel 17 Sample time selection) */ +#define ADC_SAMPT3_SAMP17_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define ADC_SAMPT3_SAMP17_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define ADC_SAMPT3_SAMP17_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define ADC_SAMPT3_SAMP17_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define ADC_SAMPT3_SAMP18 ((uint32_t)0x00000F00U) /* SAMP18[3:0] bits (Channel 18 Sample time selection) */ +#define ADC_SAMPT3_SAMP18_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define ADC_SAMPT3_SAMP18_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define ADC_SAMPT3_SAMP18_2 ((uint32_t)0x00000400U) /* Bit 2 */ +#define ADC_SAMPT3_SAMP18_3 ((uint32_t)0x00000800U) /* Bit 3 */ + +#define ADC_SAMPT3_SAMP19 ((uint32_t)0x0000F000U) /* SAMP19[3:0] bits (Channel 19 Sample time selection) */ +#define ADC_SAMPT3_SAMP19_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define ADC_SAMPT3_SAMP19_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define ADC_SAMPT3_SAMP19_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define ADC_SAMPT3_SAMP19_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +/******************** Bit definition for ADC_DIFSEL register *****************/ +#define ADC_DIFSEL_DIFSEL ((uint32_t)0x000FFFFEU) /* SAMP19[3:0] bits (Differential mode for channels 19 to 1) */ +#define ADC_DIFSEL_DIFSEL_CH1 ((uint32_t)0x00000002U) /* Bit1 */ +#define ADC_DIFSEL_DIFSEL_CH2 ((uint32_t)0x00000004U) /* Bit2 */ +#define ADC_DIFSEL_DIFSEL_CH3 ((uint32_t)0x00000008U) /* Bit3 */ +#define ADC_DIFSEL_DIFSEL_CH4 ((uint32_t)0x00000010U) /* Bit4 */ +#define ADC_DIFSEL_DIFSEL_CH5 ((uint32_t)0x00000020U) /* Bit5 */ +#define ADC_DIFSEL_DIFSEL_CH6 ((uint32_t)0x00000040U) /* Bit6 */ +#define ADC_DIFSEL_DIFSEL_CH7 ((uint32_t)0x00000080U) /* Bit7 */ +#define ADC_DIFSEL_DIFSEL_CH8 ((uint32_t)0x00000100U) /* Bit8 */ +#define ADC_DIFSEL_DIFSEL_CH9 ((uint32_t)0x00000200U) /* Bit9 */ +#define ADC_DIFSEL_DIFSEL_CH10 ((uint32_t)0x00000400U) /* Bit10 */ +#define ADC_DIFSEL_DIFSEL_CH11 ((uint32_t)0x00000800U) /* Bit11 */ +#define ADC_DIFSEL_DIFSEL_CH12 ((uint32_t)0x00001000U) /* Bit12 */ +#define ADC_DIFSEL_DIFSEL_CH13 ((uint32_t)0x00002000U) /* Bit13 */ +#define ADC_DIFSEL_DIFSEL_CH14 ((uint32_t)0x00004000U) /* Bit14 */ +#define ADC_DIFSEL_DIFSEL_CH15 ((uint32_t)0x00008000U) /* Bit15 */ +#define ADC_DIFSEL_DIFSEL_CH16 ((uint32_t)0x00010000U) /* Bit16 */ +#define ADC_DIFSEL_DIFSEL_CH17 ((uint32_t)0x00020000U) /* Bit17 */ +#define ADC_DIFSEL_DIFSEL_CH18 ((uint32_t)0x00040000U) /* Bit18 */ +#define ADC_DIFSEL_DIFSEL_CH19 ((uint32_t)0x00080000U) /* Bit19 */ + +/******************** Bit definition for ADC_AWDOTIM register ***************/ +#define ADC_AWDCTRL_AWD3TIMEN ((uint32_t)0x00000004U) /* Bit[2] Analog watchdog 3 event to timer enable*/ +#define ADC_AWDCTRL_AWD2TIMEN ((uint32_t)0x00000002U) /* Bit[1] Analog watchdog 2 event to timer enable*/ +#define ADC_AWDCTRL_AWD1TIMEN ((uint32_t)0x00000001U) /* Bit[0] Analog watchdog 1 event to timer enable*/ + + +/****************** Bit definition for ADC_OFFSET1 register *******************/ +#define ADC_OFFSET1_OFFSCH1DAT ((uint32_t)0x00000FFFU) /* ADC offset number 1 offset date */ +#define ADC_OFFSET1_OFFSCH1DIR ((uint32_t)0x01000000U) /* ADC offset number 1 positive */ +#define ADC_OFFSET1_OFFSCH1SATEN ((uint32_t)0x02000000U) /* ADC offset number 1 saturation enable */ + +#define ADC_OFFSET1_OFFSCH1CH ((uint32_t)0x7C000000U) /* OFFSCH1CH[4:0] bits (ADC offset number 1 channel selection) */ +#define ADC_OFFSET1_OFFSCH1CH_0 ((uint32_t)0x04000000U) /* Bit 0 */ +#define ADC_OFFSET1_OFFSCH1CH_1 ((uint32_t)0x08000000U) /* Bit 1 */ +#define ADC_OFFSET1_OFFSCH1CH_2 ((uint32_t)0x10000000U) /* Bit 2 */ +#define ADC_OFFSET1_OFFSCH1CH_3 ((uint32_t)0x20000000U) /* Bit 3 */ +#define ADC_OFFSET1_OFFSCH1CH_4 ((uint32_t)0x40000000U) /* Bit 4 */ + +#define ADC_OFFSET1_OFFSCH1EN ((uint32_t)0x80000000U) /* ADC offset number 1 offset enable */ + +/****************** Bit definition for ADC_OFFSET2 register *******************/ +#define ADC_OFFSET2_OFFSCH2DAT ((uint32_t)0x00000FFFU) /* ADC offset number 2 offset date */ +#define ADC_OFFSET2_OFFSCH2DIR ((uint32_t)0x01000000U) /* ADC offset number 2 positive */ +#define ADC_OFFSET2_OFFSCH2SATEN ((uint32_t)0x02000000U) /* ADC offset number 2 saturation enable */ + +#define ADC_OFFSET2_OFFSCH2CH ((uint32_t)0x7C000000U) /* OFFSCH2CH[4:0] bits (ADC offset number 2 channel selection) */ +#define ADC_OFFSET2_OFFSCH2CH_0 ((uint32_t)0x04000000U) /* Bit 0 */ +#define ADC_OFFSET2_OFFSCH2CH_1 ((uint32_t)0x08000000U) /* Bit 1 */ +#define ADC_OFFSET2_OFFSCH2CH_2 ((uint32_t)0x10000000U) /* Bit 2 */ +#define ADC_OFFSET2_OFFSCH2CH_3 ((uint32_t)0x20000000U) /* Bit 3 */ +#define ADC_OFFSET2_OFFSCH2CH_4 ((uint32_t)0x40000000U) /* Bit 4 */ + +#define ADC_OFFSET2_OFFSCH2EN ((uint32_t)0x80000000U) /* ADC offset number 2 offset enable */ + +/****************** Bit definition for ADC_OFFSET3 register *******************/ +#define ADC_OFFSET3_OFFSCH3DAT ((uint32_t)0x00000FFFU) /* ADC offset number 3 offset date */ +#define ADC_OFFSET3_OFFSCH3DIR ((uint32_t)0x01000000U) /* ADC offset number 3 positive */ +#define ADC_OFFSET3_OFFSCH3SATEN ((uint32_t)0x02000000U) /* ADC offset number 3 saturation enable */ + +#define ADC_OFFSET3_OFFSCH3CH ((uint32_t)0x7C000000U) /* OFFSCH3CH[4:0] bits (ADC offset number 3 channel selection) */ +#define ADC_OFFSET3_OFFSCH3CH_0 ((uint32_t)0x04000000U) /* Bit 0 */ +#define ADC_OFFSET3_OFFSCH3CH_1 ((uint32_t)0x08000000U) /* Bit 1 */ +#define ADC_OFFSET3_OFFSCH3CH_2 ((uint32_t)0x10000000U) /* Bit 2 */ +#define ADC_OFFSET3_OFFSCH3CH_3 ((uint32_t)0x20000000U) /* Bit 3 */ +#define ADC_OFFSET3_OFFSCH3CH_4 ((uint32_t)0x40000000U) /* Bit 4 */ + +#define ADC_OFFSET3_OFFSCH3EN ((uint32_t)0x80000000U) /* ADC offset number 3 offset enable */ + +/****************** Bit definition for ADC_OFFSET4 register *******************/ +#define ADC_OFFSET4_OFFSCH4DAT ((uint32_t)0x00000FFFU) /* ADC offset number 4 offset date */ +#define ADC_OFFSET4_OFFSCH4DIR ((uint32_t)0x01000000U) /* ADC offset number 4 positive */ +#define ADC_OFFSET4_OFFSCH4SATEN ((uint32_t)0x02000000U) /* ADC offset number 4 saturation enable */ + +#define ADC_OFFSET4_OFFSCH4CH ((uint32_t)0x7C000000U) /* OFFSCH4CH[4:0] bits (ADC offset number 4 channel selection) */ +#define ADC_OFFSET4_OFFSCH4CH_0 ((uint32_t)0x04000000U) /* Bit 0 */ +#define ADC_OFFSET4_OFFSCH4CH_1 ((uint32_t)0x08000000U) /* Bit 1 */ +#define ADC_OFFSET4_OFFSCH4CH_2 ((uint32_t)0x10000000U) /* Bit 2 */ +#define ADC_OFFSET4_OFFSCH4CH_3 ((uint32_t)0x20000000U) /* Bit 3 */ +#define ADC_OFFSET4_OFFSCH4CH_4 ((uint32_t)0x40000000U) /* Bit 4 */ + +#define ADC_OFFSET4_OFFSCH1EN ((uint32_t)0x80000000U) /* ADC offset number 4 offset enable */ + +/****************** Bit definition for ADC_AWD1HIGH register *******************/ +#define ADC_AWD1HIGH_HTH ((uint32_t)0x00000FFFU) /* Analog watchdog 1 high threshold */ + +/****************** Bit definition for ADC_AWD1LOW register ********************/ +#define ADC_AWD1LOW_LTH ((uint32_t)0x00000FFFU) /* Analog watchdog 1 low threshold */ + +#define ADC_AWD1LOW_AWDFIL ((uint32_t)0x00007000U) /* AWDFIL[2:0] bits (Analog watchdog 1 Filter value) */ +#define ADC_AWD1LOW_AWDFIL_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define ADC_AWD1LOW_AWDFIL_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define ADC_AWD1LOW_AWDFIL_2 ((uint32_t)0x00004000U) /* Bit 2 */ + +/******************* Bit definition for ADC_AWD2HIGH register *****************/ +#define ADC_AWD2HIGH_HTH ((uint32_t)0x00000FFFU) /* Analog watchdog 2 high threshold */ + +/******************* Bit definition for ADC_AWD2LOW register ******************/ +#define ADC_AWD2LOW_LTH ((uint32_t)0x00000FFFU) /* Analog watchdog 2 low threshold */ + +/******************* Bit definition for ADC_AWD3HIGH register *****************/ +#define ADC_AWD3HIGH_HTH ((uint32_t)0x00000FFFU) /* Analog watchdog 3 high threshold */ + +/******************* Bit definition for ADC_AWD3LOW register ******************/ +#define ADC_AWD3LOW_LTH ((uint32_t)0x00000FFFU) /* Analog watchdog 3 low threshold */ + +/******************** Bit definition for ADC_AWD2EN register ****************/ +#define ADC_AWD2EN_AWD2EN ((uint32_t)0x000FFFFFU) /* AWD2EN[19:0] bits (ADC analog watchdog 2 monitored channel selection) */ +#define ADC_AWD2EN_AWD2EN_CH0 ((uint32_t)0x00000001U) /* ADC analog watchdog 2 monitored channel 0 */ +#define ADC_AWD2EN_AWD2EN_CH1 ((uint32_t)0x00000002U) /* ADC analog watchdog 2 monitored channel 1 */ +#define ADC_AWD2EN_AWD2EN_CH2 ((uint32_t)0x00000004U) /* ADC analog watchdog 2 monitored channel 2 */ +#define ADC_AWD2EN_AWD2EN_CH3 ((uint32_t)0x00000008U) /* ADC analog watchdog 2 monitored channel 3 */ +#define ADC_AWD2EN_AWD2EN_CH4 ((uint32_t)0x00000010U) /* ADC analog watchdog 2 monitored channel 4 */ +#define ADC_AWD2EN_AWD2EN_CH5 ((uint32_t)0x00000020U) /* ADC analog watchdog 2 monitored channel 5 */ +#define ADC_AWD2EN_AWD2EN_CH6 ((uint32_t)0x00000040U) /* ADC analog watchdog 2 monitored channel 6 */ +#define ADC_AWD2EN_AWD2EN_CH7 ((uint32_t)0x00000080U) /* ADC analog watchdog 2 monitored channel 7 */ +#define ADC_AWD2EN_AWD2EN_CH8 ((uint32_t)0x00000100U) /* ADC analog watchdog 2 monitored channel 8 */ +#define ADC_AWD2EN_AWD2EN_CH9 ((uint32_t)0x00000200U) /* ADC analog watchdog 2 monitored channel 9 */ +#define ADC_AWD2EN_AWD2EN_CH10 ((uint32_t)0x00000400U) /* ADC analog watchdog 2 monitored channel 10 */ +#define ADC_AWD2EN_AWD2EN_CH11 ((uint32_t)0x00000800U) /* ADC analog watchdog 2 monitored channel 11 */ +#define ADC_AWD2EN_AWD2EN_CH12 ((uint32_t)0x00001000U) /* ADC analog watchdog 2 monitored channel 12 */ +#define ADC_AWD2EN_AWD2EN_CH13 ((uint32_t)0x00002000U) /* ADC analog watchdog 2 monitored channel 13 */ +#define ADC_AWD2EN_AWD2EN_CH14 ((uint32_t)0x00004000U) /* ADC analog watchdog 2 monitored channel 14 */ +#define ADC_AWD2EN_AWD2EN_CH15 ((uint32_t)0x00008000U) /* ADC analog watchdog 2 monitored channel 15 */ +#define ADC_AWD2EN_AWD2EN_CH16 ((uint32_t)0x00010000U) /* ADC analog watchdog 2 monitored channel 16 */ +#define ADC_AWD2EN_AWD2EN_CH17 ((uint32_t)0x00020000U) /* ADC analog watchdog 2 monitored channel 17 */ +#define ADC_AWD2EN_AWD2EN_CH18 ((uint32_t)0x00040000U) /* ADC analog watchdog 2 monitored channel 18 */ +#define ADC_AWD2EN_AWD2EN_CH19 ((uint32_t)0x00080000U) /* ADC analog watchdog 2 monitored channel 19 */ + +/******************** Bit definition for ADC_AWD3EN register ****************/ +#define ADC_AWD3EN_AWD3EN ((uint32_t)0x000FFFFFU) /* AWD3EN[19:0] bits (ADC analog watchdog 3 monitored channel selection) */ +#define ADC_AWD3EN_AWD3EN_CH0 ((uint32_t)0x00000001U) /* ADC analog watchdog 3 monitored channel 0 */ +#define ADC_AWD3EN_AWD3EN_CH1 ((uint32_t)0x00000002U) /* ADC analog watchdog 3 monitored channel 1 */ +#define ADC_AWD3EN_AWD3EN_CH2 ((uint32_t)0x00000004U) /* ADC analog watchdog 3 monitored channel 2 */ +#define ADC_AWD3EN_AWD3EN_CH3 ((uint32_t)0x00000008U) /* ADC analog watchdog 3 monitored channel 3 */ +#define ADC_AWD3EN_AWD3EN_CH4 ((uint32_t)0x00000010U) /* ADC analog watchdog 3 monitored channel 4 */ +#define ADC_AWD3EN_AWD3EN_CH5 ((uint32_t)0x00000020U) /* ADC analog watchdog 3 monitored channel 5 */ +#define ADC_AWD3EN_AWD3EN_CH6 ((uint32_t)0x00000040U) /* ADC analog watchdog 3 monitored channel 6 */ +#define ADC_AWD3EN_AWD3EN_CH7 ((uint32_t)0x00000080U) /* ADC analog watchdog 3 monitored channel 7 */ +#define ADC_AWD3EN_AWD3EN_CH8 ((uint32_t)0x00000100U) /* ADC analog watchdog 3 monitored channel 8 */ +#define ADC_AWD3EN_AWD3EN_CH9 ((uint32_t)0x00000200U) /* ADC analog watchdog 3 monitored channel 9 */ +#define ADC_AWD3EN_AWD3EN_CH10 ((uint32_t)0x00000400U) /* ADC analog watchdog 3 monitored channel 10 */ +#define ADC_AWD3EN_AWD3EN_CH11 ((uint32_t)0x00000800U) /* ADC analog watchdog 3 monitored channel 11 */ +#define ADC_AWD3EN_AWD3EN_CH12 ((uint32_t)0x00001000U) /* ADC analog watchdog 3 monitored channel 12 */ +#define ADC_AWD3EN_AWD3EN_CH13 ((uint32_t)0x00002000U) /* ADC analog watchdog 3 monitored channel 13 */ +#define ADC_AWD3EN_AWD3EN_CH14 ((uint32_t)0x00004000U) /* ADC analog watchdog 3 monitored channel 14 */ +#define ADC_AWD3EN_AWD3EN_CH15 ((uint32_t)0x00008000U) /* ADC analog watchdog 3 monitored channel 15 */ +#define ADC_AWD3EN_AWD3EN_CH16 ((uint32_t)0x00010000U) /* ADC analog watchdog 3 monitored channel 16 */ +#define ADC_AWD3EN_AWD3EN_CH17 ((uint32_t)0x00020000U) /* ADC analog watchdog 3 monitored channel 17 */ +#define ADC_AWD3EN_AWD3EN_CH18 ((uint32_t)0x00040000U) /* ADC analog watchdog 3 monitored channel 18 */ +#define ADC_AWD3EN_AWD3EN_CH19 ((uint32_t)0x00080000U) /* ADC analog watchdog 3 monitored channel 19 */ + +/******************** Bit definition for ADC_AWD2INTEN register ****************/ +#define ADC_AWD2INTEN ((uint32_t)0x000FFFFFU) /* AWD2INTEN[19:0] bits (ADC analog watchdog 2 channel interrupt enable) */ +#define ADC_AWD2INTEN_CH0 ((uint32_t)0x00000001U) /* ADC analog watchdog 2 channel0 interrupt enable */ +#define ADC_AWD2INTEN_CH1 ((uint32_t)0x00000002U) /* ADC analog watchdog 2 channel1 interrupt enable */ +#define ADC_AWD2INTEN_CH2 ((uint32_t)0x00000004U) /* ADC analog watchdog 2 channel2 interrupt enable */ +#define ADC_AWD2INTEN_CH3 ((uint32_t)0x00000008U) /* ADC analog watchdog 2 channel3 interrupt enable */ +#define ADC_AWD2INTEN_CH4 ((uint32_t)0x00000010U) /* ADC analog watchdog 2 channel4 interrupt enable */ +#define ADC_AWD2INTEN_CH5 ((uint32_t)0x00000020U) /* ADC analog watchdog 2 channel5 interrupt enable */ +#define ADC_AWD2INTEN_CH6 ((uint32_t)0x00000040U) /* ADC analog watchdog 2 channel6 interrupt enable */ +#define ADC_AWD2INTEN_CH7 ((uint32_t)0x00000080U) /* ADC analog watchdog 2 channel7 interrupt enable */ +#define ADC_AWD2INTEN_CH8 ((uint32_t)0x00000100U) /* ADC analog watchdog 2 channel8 interrupt enable */ +#define ADC_AWD2INTEN_CH9 ((uint32_t)0x00000200U) /* ADC analog watchdog 2 channel9 interrupt enable */ +#define ADC_AWD2INTEN_CH10 ((uint32_t)0x00000400U) /* ADC analog watchdog 2 channel10 interrupt enable */ +#define ADC_AWD2INTEN_CH11 ((uint32_t)0x00000800U) /* ADC analog watchdog 2 channel11 interrupt enable */ +#define ADC_AWD2INTEN_CH12 ((uint32_t)0x00001000U) /* ADC analog watchdog 2 channel12 interrupt enable */ +#define ADC_AWD2INTEN_CH13 ((uint32_t)0x00002000U) /* ADC analog watchdog 2 channel13 interrupt enable */ +#define ADC_AWD2INTEN_CH14 ((uint32_t)0x00004000U) /* ADC analog watchdog 2 channel14 interrupt enable */ +#define ADC_AWD2INTEN_CH15 ((uint32_t)0x00008000U) /* ADC analog watchdog 2 channel15 interrupt enable */ +#define ADC_AWD2INTEN_CH16 ((uint32_t)0x00010000U) /* ADC analog watchdog 2 channel16 interrupt enable */ +#define ADC_AWD2INTEN_CH17 ((uint32_t)0x00020000U) /* ADC analog watchdog 2 channel17 interrupt enable */ +#define ADC_AWD2INTEN_CH18 ((uint32_t)0x00040000U) /* ADC analog watchdog 2 channel18 interrupt enable */ +#define ADC_AWD2INTEN_CH19 ((uint32_t)0x00080000U) /* ADC analog watchdog 2 channel19 interrupt enable */ + +/******************** Bit definition for ADC_AWD3EN register ****************/ +#define ADC_AWD3INTEN ((uint32_t)0x000FFFFFU) /* AWD3INTEN[19:0] bits (ADC analog watchdog 3 channel interrupt enable) */ +#define ADC_AWD3INTEN_CH0 ((uint32_t)0x00000001U) /* ADC analog watchdog 3 channel0 interrupt enable */ +#define ADC_AWD3INTEN_CH1 ((uint32_t)0x00000002U) /* ADC analog watchdog 3 channel1 interrupt enable */ +#define ADC_AWD3INTEN_CH2 ((uint32_t)0x00000004U) /* ADC analog watchdog 3 channel2 interrupt enable */ +#define ADC_AWD3INTEN_CH3 ((uint32_t)0x00000008U) /* ADC analog watchdog 3 channel3 interrupt enable */ +#define ADC_AWD3INTEN_CH4 ((uint32_t)0x00000010U) /* ADC analog watchdog 3 channel4 interrupt enable */ +#define ADC_AWD3INTEN_CH5 ((uint32_t)0x00000020U) /* ADC analog watchdog 3 channel5 interrupt enable */ +#define ADC_AWD3INTEN_CH6 ((uint32_t)0x00000040U) /* ADC analog watchdog 3 channel6 interrupt enable */ +#define ADC_AWD3INTEN_CH7 ((uint32_t)0x00000080U) /* ADC analog watchdog 3 channel7 interrupt enable */ +#define ADC_AWD3INTEN_CH8 ((uint32_t)0x00000100U) /* ADC analog watchdog 3 channel8 interrupt enable */ +#define ADC_AWD3INTEN_CH9 ((uint32_t)0x00000200U) /* ADC analog watchdog 3 channel9 interrupt enable */ +#define ADC_AWD3INTEN_CH10 ((uint32_t)0x00000400U) /* ADC analog watchdog 3 channel10 interrupt enable */ +#define ADC_AWD3INTEN_CH11 ((uint32_t)0x00000800U) /* ADC analog watchdog 3 channel11 interrupt enable */ +#define ADC_AWD3INTEN_CH12 ((uint32_t)0x00001000U) /* ADC analog watchdog 3 channel12 interrupt enable */ +#define ADC_AWD3INTEN_CH13 ((uint32_t)0x00002000U) /* ADC analog watchdog 3 channel13 interrupt enable */ +#define ADC_AWD3INTEN_CH14 ((uint32_t)0x00004000U) /* ADC analog watchdog 3 channel14 interrupt enable */ +#define ADC_AWD3INTEN_CH15 ((uint32_t)0x00008000U) /* ADC analog watchdog 3 channel15 interrupt enable */ +#define ADC_AWD3INTEN_CH16 ((uint32_t)0x00010000U) /* ADC analog watchdog 3 channel16 interrupt enable */ +#define ADC_AWD3INTEN_CH17 ((uint32_t)0x00020000U) /* ADC analog watchdog 3 channel17 interrupt enable */ +#define ADC_AWD3INTEN_CH18 ((uint32_t)0x00040000U) /* ADC analog watchdog 3 channel18 interrupt enable */ +#define ADC_AWD3INTEN_CH19 ((uint32_t)0x00080000U) /* ADC analog watchdog 3 channel19 interrupt enable */ + +/******************** Bit definition for ADC_AWD2STS register ****************/ +#define ADC_AWD2STS ((uint32_t)0x000FFFFFU) /* AWD2FLAG[18:0] bits (ADC analog watchdog 2 status flag) */ +#define ADC_AWD2STS_AWD2FLAG_CH0 ((uint32_t)0x00000001U) /* ADC analog watchdog 2 channel0 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH1 ((uint32_t)0x00000002U) /* ADC analog watchdog 2 channel1 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH2 ((uint32_t)0x00000004U) /* ADC analog watchdog 2 channel2 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH3 ((uint32_t)0x00000008U) /* ADC analog watchdog 2 channel3 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH4 ((uint32_t)0x00000010U) /* ADC analog watchdog 2 channel4 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH5 ((uint32_t)0x00000020U) /* ADC analog watchdog 2 channel5 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH6 ((uint32_t)0x00000040U) /* ADC analog watchdog 2 channel6 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH7 ((uint32_t)0x00000080U) /* ADC analog watchdog 2 channel7 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH8 ((uint32_t)0x00000100U) /* ADC analog watchdog 2 channel8 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH9 ((uint32_t)0x00000200U) /* ADC analog watchdog 2 channel9 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH10 ((uint32_t)0x00000400U) /* ADC analog watchdog 2 channel10 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH11 ((uint32_t)0x00000800U) /* ADC analog watchdog 2 channel11 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH12 ((uint32_t)0x00001000U) /* ADC analog watchdog 2 channel12 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH13 ((uint32_t)0x00002000U) /* ADC analog watchdog 2 channel13 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH14 ((uint32_t)0x00004000U) /* ADC analog watchdog 2 channel14 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH15 ((uint32_t)0x00008000U) /* ADC analog watchdog 2 channel15 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH16 ((uint32_t)0x00010000U) /* ADC analog watchdog 2 channel16 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH17 ((uint32_t)0x00020000U) /* ADC analog watchdog 2 channel17 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH18 ((uint32_t)0x00040000U) /* ADC analog watchdog 2 channel18 status flag */ +#define ADC_AWD2STS_AWD2FLAG_CH19 ((uint32_t)0x00080000U) /* ADC analog watchdog 2 channel19 status flag */ + +/******************** Bit definition for ADC_AWD3STS register ****************/ +#define ADC_AWD3STS ((uint32_t)0x000FFFFFU) /* AWD3FLAG[19:0] bits (ADC analog watchdog 3 status flag) */ +#define ADC_AWD3STS_AWD3FLAG_CH0 ((uint32_t)0x00000001U) /* ADC analog watchdog 3 channel0 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH1 ((uint32_t)0x00000002U) /* ADC analog watchdog 3 channel1 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH2 ((uint32_t)0x00000004U) /* ADC analog watchdog 3 channel2 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH3 ((uint32_t)0x00000008U) /* ADC analog watchdog 3 channel3 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH4 ((uint32_t)0x00000010U) /* ADC analog watchdog 3 channel4 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH5 ((uint32_t)0x00000020U) /* ADC analog watchdog 3 channel5 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH6 ((uint32_t)0x00000040U) /* ADC analog watchdog 3 channel6 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH7 ((uint32_t)0x00000080U) /* ADC analog watchdog 3 channel7 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH8 ((uint32_t)0x00000100U) /* ADC analog watchdog 3 channel8 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH9 ((uint32_t)0x00000200U) /* ADC analog watchdog 3 channel9 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH10 ((uint32_t)0x00000400U) /* ADC analog watchdog 3 channel10 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH11 ((uint32_t)0x00000800U) /* ADC analog watchdog 3 channel11 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH12 ((uint32_t)0x00001000U) /* ADC analog watchdog 3 channel12 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH13 ((uint32_t)0x00002000U) /* ADC analog watchdog 3 channel13 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH14 ((uint32_t)0x00004000U) /* ADC analog watchdog 3 channel14 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH15 ((uint32_t)0x00008000U) /* ADC analog watchdog 3 channel15 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH16 ((uint32_t)0x00010000U) /* ADC analog watchdog 3 channel16 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH17 ((uint32_t)0x00020000U) /* ADC analog watchdog 3 channel17 status flag */ +#define ADC_AWD3STS_AWD3FLAG_CH18 ((uint32_t)0x00040000U) /* ADC analog watchdog 3 channel18 status flag */ +#define ADC_AWD2STS_AWD3FLAG_CH19 ((uint32_t)0x00080000U) /* ADC analog watchdog 3 channel19 status flag */ + +/******************* Bit definition for ADC_RSEQ1 register *******************/ +#define ADC_RSEQ1_SEQ19 ((uint32_t)0x0000001FU) /* SEQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ19_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_RSEQ1_SEQ19_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_RSEQ1_SEQ19_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_RSEQ1_SEQ19_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define ADC_RSEQ1_SEQ19_4 ((uint32_t)0x00000010U) /* Bit 4 */ + +#define ADC_RSEQ1_SEQ20 ((uint32_t)0x000003E0U) /* SEQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_RSEQ1_SEQ20_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define ADC_RSEQ1_SEQ20_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define ADC_RSEQ1_SEQ20_2 ((uint32_t)0x00000080U) /* Bit 2 */ +#define ADC_RSEQ1_SEQ20_3 ((uint32_t)0x00000100U) /* Bit 3 */ +#define ADC_RSEQ1_SEQ20_4 ((uint32_t)0x00000200U) /* Bit 4 */ + +#define ADC_RSEQ1_LEN ((uint32_t)0x00007C00U) /* LEN[4:0] bits (Regular channel sequence length) */ +#define ADC_RSEQ1_LEN_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define ADC_RSEQ1_LEN_1 ((uint32_t)0x00000800U) /* Bit 1 */ +#define ADC_RSEQ1_LEN_2 ((uint32_t)0x00001000U) /* Bit 2 */ +#define ADC_RSEQ1_LEN_3 ((uint32_t)0x00002000U) /* Bit 3 */ +#define ADC_RSEQ1_LEN_4 ((uint32_t)0x00004000U) /* Bit 4 */ + +/******************* Bit definition for ADC_RSEQ2 register *******************/ +#define ADC_RSEQ2_SEQ13 ((uint32_t)0x0000001FU) /* SEQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ13_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_RSEQ2_SEQ13_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_RSEQ2_SEQ13_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_RSEQ2_SEQ13_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define ADC_RSEQ2_SEQ13_4 ((uint32_t)0x00000010U) /* Bit 4 */ + +#define ADC_RSEQ2_SEQ14 ((uint32_t)0x000003E0U) /* SEQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ14_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define ADC_RSEQ2_SEQ14_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define ADC_RSEQ2_SEQ14_2 ((uint32_t)0x00000080U) /* Bit 2 */ +#define ADC_RSEQ2_SEQ14_3 ((uint32_t)0x00000100U) /* Bit 3 */ +#define ADC_RSEQ2_SEQ14_4 ((uint32_t)0x00000200U) /* Bit 4 */ + +#define ADC_RSEQ2_SEQ15 ((uint32_t)0x00007C00U) /* SEQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ15_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define ADC_RSEQ2_SEQ15_1 ((uint32_t)0x00000800U) /* Bit 1 */ +#define ADC_RSEQ2_SEQ15_2 ((uint32_t)0x00001000U) /* Bit 2 */ +#define ADC_RSEQ2_SEQ15_3 ((uint32_t)0x00002000U) /* Bit 3 */ +#define ADC_RSEQ2_SEQ15_4 ((uint32_t)0x00004000U) /* Bit 4 */ + +#define ADC_RSEQ2_SEQ16 ((uint32_t)0x000F8000U) /* SEQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ16_0 ((uint32_t)0x00008000U) /* Bit 0 */ +#define ADC_RSEQ2_SEQ16_1 ((uint32_t)0x00010000U) /* Bit 1 */ +#define ADC_RSEQ2_SEQ16_2 ((uint32_t)0x00020000U) /* Bit 2 */ +#define ADC_RSEQ2_SEQ16_3 ((uint32_t)0x00040000U) /* Bit 3 */ +#define ADC_RSEQ2_SEQ16_4 ((uint32_t)0x00080000U) /* Bit 4 */ + +#define ADC_RSEQ2_SEQ17 ((uint32_t)0x01F00000U) /* SEQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ17_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define ADC_RSEQ2_SEQ17_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define ADC_RSEQ2_SEQ17_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define ADC_RSEQ2_SEQ17_3 ((uint32_t)0x00800000U) /* Bit 3 */ +#define ADC_RSEQ2_SEQ17_4 ((uint32_t)0x01000000U) /* Bit 4 */ + +#define ADC_RSEQ2_SEQ18 ((uint32_t)0x3E000000U) /* SEQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_RSEQ2_SEQ18_0 ((uint32_t)0x02000000U) /* Bit 0 */ +#define ADC_RSEQ2_SEQ18_1 ((uint32_t)0x04000000U) /* Bit 1 */ +#define ADC_RSEQ2_SEQ18_2 ((uint32_t)0x08000000U) /* Bit 2 */ +#define ADC_RSEQ2_SEQ18_3 ((uint32_t)0x10000000U) /* Bit 3 */ +#define ADC_RSEQ2_SEQ18_4 ((uint32_t)0x20000000U) /* Bit 4 */ + +/******************* Bit definition for ADC_RSEQ3 register *******************/ +#define ADC_RSEQ3_SEQ7 ((uint32_t)0x0000001FU) /* SEQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ7_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_RSEQ3_SEQ7_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_RSEQ3_SEQ7_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_RSEQ3_SEQ7_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define ADC_RSEQ3_SEQ7_4 ((uint32_t)0x00000010U) /* Bit 4 */ + +#define ADC_RSEQ3_SEQ8 ((uint32_t)0x000003E0U) /* SEQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ8_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define ADC_RSEQ3_SEQ8_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define ADC_RSEQ3_SEQ8_2 ((uint32_t)0x00000080U) /* Bit 2 */ +#define ADC_RSEQ3_SEQ8_3 ((uint32_t)0x00000100U) /* Bit 3 */ +#define ADC_RSEQ3_SEQ8_4 ((uint32_t)0x00000200U) /* Bit 4 */ + +#define ADC_RSEQ3_SEQ9 ((uint32_t)0x00007C00U) /* SEQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ9_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define ADC_RSEQ3_SEQ9_1 ((uint32_t)0x00000800U) /* Bit 1 */ +#define ADC_RSEQ3_SEQ9_2 ((uint32_t)0x00001000U) /* Bit 2 */ +#define ADC_RSEQ3_SEQ9_3 ((uint32_t)0x00002000U) /* Bit 3 */ +#define ADC_RSEQ3_SEQ9_4 ((uint32_t)0x00004000U) /* Bit 4 */ + +#define ADC_RSEQ3_SEQ10 ((uint32_t)0x000F8000U) /* SEQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ10_0 ((uint32_t)0x00008000U) /* Bit 0 */ +#define ADC_RSEQ3_SEQ10_1 ((uint32_t)0x00010000U) /* Bit 1 */ +#define ADC_RSEQ3_SEQ10_2 ((uint32_t)0x00020000U) /* Bit 2 */ +#define ADC_RSEQ3_SEQ10_3 ((uint32_t)0x00040000U) /* Bit 3 */ +#define ADC_RSEQ3_SEQ10_4 ((uint32_t)0x00080000U) /* Bit 4 */ + +#define ADC_RSEQ3_SEQ11 ((uint32_t)0x01F00000U) /* SEQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ11_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define ADC_RSEQ3_SEQ11_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define ADC_RSEQ3_SEQ11_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define ADC_RSEQ3_SEQ11_3 ((uint32_t)0x00800000U) /* Bit 3 */ +#define ADC_RSEQ3_SEQ11_4 ((uint32_t)0x01000000U) /* Bit 4 */ + +#define ADC_RSEQ3_SEQ12 ((uint32_t)0x3E000000U) /* SEQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_RSEQ3_SEQ12_0 ((uint32_t)0x02000000U) /* Bit 0 */ +#define ADC_RSEQ3_SEQ12_1 ((uint32_t)0x04000000U) /* Bit 1 */ +#define ADC_RSEQ3_SEQ12_2 ((uint32_t)0x08000000U) /* Bit 2 */ +#define ADC_RSEQ3_SEQ12_3 ((uint32_t)0x10000000U) /* Bit 3 */ +#define ADC_RSEQ3_SEQ12_4 ((uint32_t)0x20000000U) /* Bit 4 */ + +/******************* Bit definition for ADC_RSEQ4 register *******************/ +#define ADC_RSEQ4_SEQ1 ((uint32_t)0x0000001FU) /* SEQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_RSEQ4_SEQ1_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_RSEQ4_SEQ1_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_RSEQ4_SEQ1_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_RSEQ4_SEQ1_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define ADC_RSEQ4_SEQ1_4 ((uint32_t)0x00000010U) /* Bit 4 */ + +#define ADC_RSEQ4_SEQ2 ((uint32_t)0x000003E0U) /* SEQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_RSEQ4_SEQ2_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define ADC_RSEQ4_SEQ2_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define ADC_RSEQ4_SEQ2_2 ((uint32_t)0x00000080U) /* Bit 2 */ +#define ADC_RSEQ4_SEQ2_3 ((uint32_t)0x00000100U) /* Bit 3 */ +#define ADC_RSEQ4_SEQ2_4 ((uint32_t)0x00000200U) /* Bit 4 */ + +#define ADC_RSEQ4_SEQ3 ((uint32_t)0x00007C00U) /* SEQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_RSEQ4_SEQ3_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define ADC_RSEQ4_SEQ3_1 ((uint32_t)0x00000800U) /* Bit 1 */ +#define ADC_RSEQ4_SEQ3_2 ((uint32_t)0x00001000U) /* Bit 2 */ +#define ADC_RSEQ4_SEQ3_3 ((uint32_t)0x00002000U) /* Bit 3 */ +#define ADC_RSEQ4_SEQ3_4 ((uint32_t)0x00004000U) /* Bit 4 */ + +#define ADC_RSEQ4_SEQ4 ((uint32_t)0x000F8000U) /* SEQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_RSEQ4_SEQ4_0 ((uint32_t)0x00008000U) /* Bit 0 */ +#define ADC_RSEQ4_SEQ4_1 ((uint32_t)0x00010000U) /* Bit 1 */ +#define ADC_RSEQ4_SEQ4_2 ((uint32_t)0x00020000U) /* Bit 2 */ +#define ADC_RSEQ4_SEQ4_3 ((uint32_t)0x00040000U) /* Bit 3 */ +#define ADC_RSEQ4_SEQ4_4 ((uint32_t)0x00080000U) /* Bit 4 */ + +#define ADC_RSEQ4_SEQ5 ((uint32_t)0x01F00000U) /* SEQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_RSEQ4_SEQ5_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define ADC_RSEQ4_SEQ5_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define ADC_RSEQ4_SEQ5_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define ADC_RSEQ4_SEQ5_3 ((uint32_t)0x00800000U) /* Bit 3 */ +#define ADC_RSEQ4_SEQ5_4 ((uint32_t)0x01000000U) /* Bit 4 */ + +#define ADC_RSEQ4_SEQ6 ((uint32_t)0x3E000000U) /* SEQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_RSEQ4_SEQ6_0 ((uint32_t)0x02000000U) /* Bit 0 */ +#define ADC_RSEQ4_SEQ6_1 ((uint32_t)0x04000000U) /* Bit 1 */ +#define ADC_RSEQ4_SEQ6_2 ((uint32_t)0x08000000U) /* Bit 2 */ +#define ADC_RSEQ4_SEQ6_3 ((uint32_t)0x10000000U) /* Bit 3 */ +#define ADC_RSEQ4_SEQ6_4 ((uint32_t)0x20000000U) /* Bit 4 */ + +/******************* Bit definition for ADC_JSEQ register *******************/ +#define ADC_JSEQ_JSEQ1 ((uint32_t)0x0000001FU) /* JSEQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ1_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define ADC_JSEQ_JSEQ1_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define ADC_JSEQ_JSEQ1_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define ADC_JSEQ_JSEQ1_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define ADC_JSEQ_JSEQ1_4 ((uint32_t)0x00000010U) /* Bit 4 */ + +#define ADC_JSEQ_JSEQ2 ((uint32_t)0x000003E0U) /* JSEQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ2_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define ADC_JSEQ_JSEQ2_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define ADC_JSEQ_JSEQ2_2 ((uint32_t)0x00000080U) /* Bit 2 */ +#define ADC_JSEQ_JSEQ2_3 ((uint32_t)0x00000100U) /* Bit 3 */ +#define ADC_JSEQ_JSEQ2_4 ((uint32_t)0x00000200U) /* Bit 4 */ + +#define ADC_JSEQ_JSEQ3 ((uint32_t)0x00007C00U) /* JSEQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ3_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define ADC_JSEQ_JSEQ3_1 ((uint32_t)0x00000800U) /* Bit 1 */ +#define ADC_JSEQ_JSEQ3_2 ((uint32_t)0x00001000U) /* Bit 2 */ +#define ADC_JSEQ_JSEQ3_3 ((uint32_t)0x00002000U) /* Bit 3 */ +#define ADC_JSEQ_JSEQ3_4 ((uint32_t)0x00004000U) /* Bit 4 */ + +#define ADC_JSEQ_JSEQ4 ((uint32_t)0x000F8000U) /* JSEQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSEQ_JSEQ4_0 ((uint32_t)0x00008000U) /* Bit 0 */ +#define ADC_JSEQ_JSEQ4_1 ((uint32_t)0x00010000U) /* Bit 1 */ +#define ADC_JSEQ_JSEQ4_2 ((uint32_t)0x00020000U) /* Bit 2 */ +#define ADC_JSEQ_JSEQ4_3 ((uint32_t)0x00040000U) /* Bit 3 */ +#define ADC_JSEQ_JSEQ4_4 ((uint32_t)0x00080000U) /* Bit 4 */ + +#define ADC_JSEQ_JLEN ((uint32_t)0x06000000U) /* JLEN[1:0] bits (Injected Sequence length) */ +#define ADC_JSEQ_JLEN_0 ((uint32_t)0x02000000U) /* Bit 0 */ +#define ADC_JSEQ_JLEN_1 ((uint32_t)0x04000000U) /* Bit 1 */ + +/******************* Bit definition for ADC_JDAT1 register *******************/ +#define ADC_JDAT1_JDAT ((uint16_t)0xFFFFU) /* Injected data */ + +/******************* Bit definition for ADC_JDAT2 register *******************/ +#define ADC_JDAT2_JDAT ((uint16_t)0xFFFFU) /* Injected data */ + +/******************* Bit definition for ADC_JDAT3 register *******************/ +#define ADC_JDAT3_JDAT ((uint16_t)0xFFFFU) /* Injected data */ + +/******************* Bit definition for ADC_JDAT4 register *******************/ +#define ADC_JDAT4_JDAT ((uint16_t)0xFFFFU) /* Injected data */ + +/******************** Bit definition for ADC_DAT register ********************/ +#define ADC_DAT_DAT ((uint32_t)0x0000FFFFU) /* Regular data */ +#define ADC_DAT_ADC2DAT ((uint32_t)0xFFFF0000U) /* Slave ADC data when operating on Muti-ADC */ + +/******************** Bit definition for ADC_FIFOCFG register ********************/ +#define ADC_FIFOCFG_FINTEN ((uint32_t)0x00000004U) /* FIFO full interrup enable */ +#define ADC_FIFOCFG_EINTEN ((uint32_t)0x00000008U) /* FIFO empty interrup enable */ +#define ADC_FIFOCFG_HFINTEN ((uint32_t)0x00000010U) /* FIFO half-full interrup enable */ +#define ADC_FIFOCFG_EN ((uint32_t)0x00000020U) /* FIFO enable */ + +#define ADC_FIFOCFG_WL ((uint32_t)0x000003C0U) /* WL[1:0] bits (FIFO water level) */ +#define ADC_FIFOCFG_WL_0 ((uint32_t)0x00000040U) /* Bit 0 */ +#define ADC_FIFOCFG_WL_1 ((uint32_t)0x00000080U) /* Bit 1 */ +#define ADC_FIFOCFG_WL_2 ((uint32_t)0x00000100U) /* Bit 2 */ +#define ADC_FIFOCFG_WL_3 ((uint32_t)0x00000200U) /* Bit 3 */ + +#define ADC_FIFOCFG_CLR ((uint32_t)0x00000400U) /* FIFO clear enable */ +#define ADC_FIFOCFG_NEINTEN ((uint32_t)0x00000800U) /* FIFO non-empty interrupt enable */ + +/******************** Bit definition for ADC_FIFOSTS register ********************/ +#define ADC_FIFOSTS_FFLAG ((uint32_t)0x00000004U) /* FIFO full status flag */ +#define ADC_FIFOSTS_EFLAG ((uint32_t)0x00000008U) /* FIFO empty status flag*/ +#define ADC_FIFOSTS_HFFLAG ((uint32_t)0x00000010U) /* FIFO half-full status flag */ + +#define ADC_FIFOSTS_DATCNT ((uint32_t)0x000003E0U) /* DATCNT[4:0] bits (FIFO invalid data count) */ +#define ADC_FIFOSTS_DATCNT_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define ADC_FIFOSTS_DATCNT_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define ADC_FIFOSTS_DATCNT_2 ((uint32_t)0x00000080U) /* Bit 2 */ +#define ADC_FIFOSTS_DATCNT_3 ((uint32_t)0x00000100U) /* Bit 3 */ +#define ADC_FIFOSTS_DATCNT_4 ((uint32_t)0x00000200U) /* Bit 4 */ + +#define ADC_FIFOSTS_NEFLAG ((uint32_t)0x00000800U) /* FIFO non-empty status flag */ + +/******************** Bit definition for ADC_DLYSMP register ********************/ +#define ADC_DLYSMP_INTLEADVAL ((uint32_t)0xF0000000U) /* Bit[31:28] The delay time when operating on interleaved mode of dual-ADC or Tripple- ADC */ +#define ADC_DLYSMP_INTLEADVAL_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define ADC_DLYSMP_INTLEADVAL_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define ADC_DLYSMP_INTLEADVAL_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define ADC_DLYSMP_INTLEADVAL_3 ((uint32_t)0x80000000U) /* Bit31*/ + +#define ADC_DLYSMP_DLYVAL ((uint32_t)0x0F000000U) /* Bit[27:24] Delayed sampling cycle configuration in independent mode*/ +#define ADC_DLYSMP_DLYVAL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define ADC_DLYSMP_DLYVAL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define ADC_DLYSMP_DLYVAL_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define ADC_DLYSMP_DLYVAL_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define ADC_DLYSMP_DLYSAMPEN ((uint32_t)0x00800000U) /* Bit[23] */ + +/******************** Bit definition for ADC_OSCFG register *****************/ +#define ADC_OSCFG_OSAWD ((uint32_t)0x01000000U) /* Bit[24] Oversampling data for analog watchdog comparision */ +#define ADC_OSCFG_OSRMD ((uint32_t)0x00800000U) /* Bit[23] Regular channels oversample mode */ +#define ADC_OSCFG_OSRTRIG ((uint32_t)0x00400000U) /* Bit[22] egular channels oversample triagger mode */ + +#define ADC_OSCFG_OSS ((uint32_t)0x003C0000U) /* Bit[21:18] Oversample data right shift */ +#define ADC_OSCFG_OSS_0 ((uint32_t)0x00040000U) /* Bit18*/ +#define ADC_OSCFG_OSS_1 ((uint32_t)0x00080000U) /* Bit19*/ +#define ADC_OSCFG_OSS_2 ((uint32_t)0x00100000U) /* Bit20*/ +#define ADC_OSCFG_OSS_3 ((uint32_t)0x00200000U) /* Bit21*/ + +#define ADC_OSCFG_OSR ((uint32_t)0x0003C000U) /* Bit[17:14] ADC oversampling ratio times */ +#define ADC_OSCFG_OSR_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define ADC_OSCFG_OSR_1 ((uint32_t)0x00008000U) /* Bit15*/ +#define ADC_OSCFG_OSR_2 ((uint32_t)0x00010000U) /* Bit16*/ +#define ADC_OSCFG_OSR_3 ((uint32_t)0x00020000U) /* Bit17*/ + +#define ADC_OSCFG_OSJE ((uint32_t)0x00002000U) /* Bit[13] Injected channels oversample enable*/ +#define ADC_OSCFG_OSRE ((uint32_t)0x00001000U) /* Bit[12] Regular channels oversample enable */ + +/******************** Bit definition for ADC_INTLRCFG register ****************/ +#define ADC_INTLRCFG_WEN ((uint32_t)0x80000000U) /* WEN bits (Write enable) */ +#define ADC_INTLRCFG_RWSTART ((uint32_t)0x40000000U) /* RWSTART bits (Start Write/Read Internal Register) */ +#define ADC_INTLRCFG_DONE ((uint32_t)0x20000000U) /* DONE bits (Write/Read Internal Register Finish Flag) */ + +#define ADC_INTLRCFG_ADDR ((uint32_t)0x1C000000U) /* ADDR[2:0] bits (The address of internal registers) */ +#define ADC_INTLRCFG_WDATA ((uint32_t)0x03FC0000U) /* WDATA[7:0] bits (Data write into internal register) */ +#define ADC_INTLRCFG_RDATA ((uint32_t)0x00003FC0U) /* RDATA[7:0] bits (Data read from internal register) */ + +/******************** Bit definition for ADC_GCOMP register ****************/ +#define ADC_GCOMP_GCOMPDAT ((uint32_t)0x00003FFFU) /* GCOMPDAT[13:0] bits (ADC Gain Compensation Coefficient) */ + + +/*** Digital to Analog Converter Peripheral Interface ***/ +/******************** Bit definition for DAC_CTRL register ********************/ +#define DAC_CTRL_DACxEN ((uint32_t)0x00000001U) /* DACx enable */ +#define DAC_CTRL_DMAxEN ((uint32_t)0x00000002U) /* DACx DMA enable */ +#define DAC_CTRL_BxEN ((uint32_t)0x00000004U) /* DACx output buffer enable */ +#define DAC_CTRL_TxEN ((uint32_t)0x00000008U) /* DACx Trigger enable */ +#define DAC_CTRL_DMAUDRxIEn ((uint32_t)0x00000010U) /* DACx DMA underrun interrupt enable */ +#define DAC_CTRL_HDBxEN ((uint32_t)0x00000020U) /* DACx high driver output buffer enable */ +#define DAC_CTRL_DMADOUBLExEN ((uint32_t)0x00000040U) /* DACx DMA double data mode enable */ +#define DAC_CTRL_SINFORMATxEN ((uint32_t)0x00000080U) /* DACx signed format enable */ + +#define DAC_CTRL_WxEN ((uint32_t)0x00000700U) /* WAVE1[1:0] (DACx noise/triangle wave generation enable) */ +#define DAC_CTRL_WxEN_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define DAC_CTRL_WxEN_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define DAC_CTRL_WxEN_2 ((uint32_t)0x00000400U) /* Bit 2 */ + +#define DAC_CTRL_CALxEN ((uint32_t)0x00000800U) /* DACx calibrate enable */ +#define DAC_CTRL_INOUTx ((uint32_t)0x00001000U) /* DACx is connected to on chip peripherals enable */ +#define DAC_CTRL_EXOUTx ((uint32_t)0x00002000U) /* DACx is connected to external pin enable */ +#define DAC_CTRL_TROVCxIEN ((uint32_t)0x00004000U) /* DACx's trigger overclock interrupt enable */ + +#define DAC_CTRL_DACyEN ((uint32_t)0x00010000U) /* DACy enable */ +#define DAC_CTRL_DMAyEN ((uint32_t)0x00020000U) /* DACy DMA enable */ +#define DAC_CTRL_ByEN ((uint32_t)0x00040000U) /* DACy output buffer enable */ +#define DAC_CTRL_TyEN ((uint32_t)0x00080000U) /* DACy Trigger enable */ +#define DAC_CTRL_DMAUDRyIEn ((uint32_t)0x00100000U) /* DACy DMA underrun interrupt enable */ +#define DAC_CTRL_HDByEN ((uint32_t)0x00200000U) /* DACy high driver output buffer enable */ +#define DAC_CTRL_DMADOUBLEyEN ((uint32_t)0x00400000U) /* DACy DMA double data mode enable */ +#define DAC_CTRL_SINFORMATyEN ((uint32_t)0x00800000U) /* DACy signed format enable */ + +#define DAC_CTRL_WyEN ((uint32_t)0x07000000U) /* WAVE2[1:0] (DACy noise/triangle wave generation enable) */ +#define DAC_CTRL_WyEN_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define DAC_CTRL_WyEN_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define DAC_CTRL_WyEN_2 ((uint32_t)0x04000000U) /* Bit 2 */ + +#define DAC_CTRL_CALyEN ((uint32_t)0x08000000U) /* DACy calibrate enable */ +#define DAC_CTRL_INOUTy ((uint32_t)0x10000000U) /* DACy is connected to on chip peripherals enable */ +#define DAC_CTRL_EXOUTy ((uint32_t)0x20000000U) /* DACy is connected to external pin enable */ +#define DAC_CTRL_TROVCyIEN ((uint32_t)0x40000000U) /* DACy's trigger overclock interrupt enable */ + +/***************** Bit definition for DAC_SOTTR register ******************/ +#define DAC_SOTTR_TRxEN ((uint32_t)0x00000001U) /* DACx software trigger */ +#define DAC_SOTTR_TRyEN ((uint32_t)0x00000002U) /* DACy software trigger */ +#define DAC_SOTTR_TRBxEN ((uint32_t)0x00010000U) /* DACx sawtooth step signal software trigger */ +#define DAC_SOTTR_TRByEN ((uint32_t)0x00020000U) /* DACy sawtooth step signal software trigger */ + +/******************* Bit definiti on for DAC_DATO1 register *******************/ +#define DACx_DATO_DACxDO ((uint16_t)0x0FFFU) /* DACx data output */ + +/******************* Bit definition for DAC_DATO2 register *******************/ +#define DACy_DATO_DACyDO ((uint16_t)0x0FFFU) /* DACy data output */ + +/****************** Bit definition for DAC_DR8CH1 register ******************/ +#define DACx_DR8_DACxD ((uint16_t)0xFF00U) /* DACx 8-bit Right aligned data */ +#define DACx_DR8_DACxDB ((uint16_t)0x00FFU) /* DACx 8-bit Right aligned data, operating only on double data mode */ + +/***************** Bit definition for DAC_DL12CH1 register ******************/ +#define DACx_DL12_DACxDB ((uint32_t)0x0000FFF0U) /* DACx 12-bit Left aligned data */ +#define DACx_DL12_DACxD ((uint32_t)0xFFF00000U) /* DACx 12-bit Left aligned data, operating only on double data mode */ + +/***************** Bit definition for DAC_DR12CH1 register ******************/ +#define DACx_DR12_DACxDB ((uint32_t)0x00000FFFU) /* DACx 12-bit Right aligned data */ +#define DACx_DR12_DACxD ((uint32_t)0x0FFF0000U) /* DACx 12-bit Right aligned data, operating only on double data mode */ + +/****************** Bit definition for DAC_DR8CH2 register ******************/ +#define DACy_DR8_DACyD ((uint16_t)0xFF00U) /* DACy 8-bit Right aligned data */ +#define DACy_DR8_DACyDB ((uint16_t)0x00FFU) /* DACy 8-bit Right aligned data, operating only on double data mode */ + +/***************** Bit definition for DAC_DL12CH2 register ******************/ +#define DACy_DL12_DACyDB ((uint32_t)0x0000FFF0U) /* DACy 12-bit Left aligned data */ +#define DACy_DL12_DACyD ((uint32_t)0xFFF00000U) /* DACy 12-bit Left aligned data, operating only on double data mode */ + +/***************** Bit definition for DAC_DR12CH2 register ******************/ +#define DACy_DR12_DACyDB ((uint32_t)0x00000FFFU) /* DACy 12-bit Right aligned data */ +#define DACy_DR12_DACyD ((uint32_t)0x0FFF0000U) /* DACy 12-bit Right aligned data, operating only on double data mode */ + +/****************** Bit definition for DAC_DR8DCH register ******************/ +#define DAC_DR8D_DACxD ((uint16_t)0x00FFU) /* DACx 8-bit Right aligned data */ +#define DAC_DR8D_DACyD ((uint16_t)0xFF00U) /* DACy 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DL12DCH register ******************/ +#define DAC_DL12D_DACxD ((uint32_t)0x0000FFF0U) /* DACx 12-bit Left aligned data */ +#define DAC_DL12D_DACyD ((uint32_t)0xFFF00000U) /* DACy 12-bit Left aligned data */ + +/***************** Bit definition for DAC_DR12DCH register ******************/ +#define DAC_DR12D_DACxD ((uint32_t)0x00000FFFU) /* DACx 12-bit Right aligned data */ +#define DAC_DR12D_DACyD ((uint32_t)0x0FFF0000U) /* DACy 12-bit Right aligned data */ + +/***************** Bit definition for DAC_SELCTRL register ******************/ +#define DAC_SETCTRL_SINCSELx ((uint32_t)0x0000003EU) /* DACx sawtooth increment trigger selection */ +#define DAC_SETCTRL_SINCSELx_0 ((uint32_t)0x00000002U) /* Bit 0 */ +#define DAC_SETCTRL_SINCSELx_1 ((uint32_t)0x00000004U) /* Bit 1 */ +#define DAC_SETCTRL_SINCSELx_2 ((uint32_t)0x00000008U) /* Bit 2 */ +#define DAC_SETCTRL_SINCSELx_3 ((uint32_t)0x00000010U) /* Bit 3 */ +#define DAC_SETCTRL_SINCSELx_4 ((uint32_t)0x00000020U) /* Bit 4 */ + +#define DAC_SETCTRL_MAxSEL ((uint32_t)0x000003C0U) /* MAMPx[3:0] (DACx Mask/Amplitude selector) */ +#define DAC_SETCTRL_MAxSEL_0 ((uint32_t)0x00000040U) /* Bit 0 */ +#define DAC_SETCTRL_MAxSEL_1 ((uint32_t)0x00000080U) /* Bit 1 */ +#define DAC_SETCTRL_MAxSEL_2 ((uint32_t)0x00000100U) /* Bit 2 */ +#define DAC_SETCTRL_MAxSEL_3 ((uint32_t)0x00000200U) /* Bit 3 */ + +#define DAC_SETCTRL_TxSEL ((uint32_t)0x0000F100U) /* TSELx[4:0] (DACx Trigger source selection) */ +#define DAC_SETCTRL_TxSEL_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define DAC_SETCTRL_TxSEL_1 ((uint32_t)0x00001000U) /* Bit 1 */ +#define DAC_SETCTRL_TxSEL_2 ((uint32_t)0x00002000U) /* Bit 2 */ +#define DAC_SETCTRL_TxSEL_3 ((uint32_t)0x00004000U) /* Bit 3 */ +#define DAC_SETCTRL_TxSEL_4 ((uint32_t)0x00008000U) /* Bit 4 */ + +#define DAC_SETCTRL_SINCSELy ((uint32_t)0x003E0000U) /* SINCSELy[3:0] (DACy sawtooth increment trigger selection) */ +#define DAC_SETCTRL_SINCSELy_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define DAC_SETCTRL_SINCSELy_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define DAC_SETCTRL_SINCSELy_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define DAC_SETCTRL_SINCSELy_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define DAC_SETCTRL_SINCSELy_4 ((uint32_t)0x00200000U) /* Bit 4 */ + +#define DAC_SETCTRL_MAySEL ((uint32_t)0x03C00000U) /* MAMPy[3:0] (DACy Mask/Amplitude selector) */ +#define DAC_SETCTRL_MAySEL_0 ((uint32_t)0x00400000U) /* Bit 0 */ +#define DAC_SETCTRL_MAySEL_1 ((uint32_t)0x00800000U) /* Bit 1 */ +#define DAC_SETCTRL_MAySEL_2 ((uint32_t)0x01000000U) /* Bit 2 */ +#define DAC_SETCTRL_MAySEL_3 ((uint32_t)0x02000000U) /* Bit 3 */ + +#define DAC_SETCTRL_TySEL ((uint32_t)0xF1000000U) /* TSELy[4:0] (DACy Trigger source selection) */ +#define DAC_SETCTRL_TySEL_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define DAC_SETCTRL_TySEL_1 ((uint32_t)0x10000000U) /* Bit 1 */ +#define DAC_SETCTRL_TySEL_2 ((uint32_t)0x20000000U) /* Bit 2 */ +#define DAC_SETCTRL_TySEL_3 ((uint32_t)0x40000000U) /* Bit 3 */ +#define DAC_SETCTRL_TySEL_4 ((uint32_t)0x80000000U) /* Bit 4 */ + +/***************** Bit definition for DAC_STS register ******************/ +#define DAC_STS_DMAUDRx ((uint32_t)0x00000001U) /* DACx DMA underrun status flag */ +#define DAC_STS_CALFLAGx ((uint32_t)0x00000002U) /* DACx calibrate offset status flag */ +#define DAC_STS_DORSTATx ((uint32_t)0x00000004U) /* DACx data output register status flag */ +#define DAC_STS_TROVCFLAGx ((uint32_t)0x00000008U) /* DACx trigger source overclock status flag */ +#define DAC_STS_VFLAGxCOMP ((uint32_t)0x00000010U) /* Status flag that indicates DACx output is stable or not */ + +#define DAC_STS_DMAUDRy ((uint32_t)0x00010000U) /* DACy DMA underrun status flag */ +#define DAC_STS_CALFLAGy ((uint32_t)0x00020000U) /* DACy calibrate offset status flag */ +#define DAC_STS_DORSTATy ((uint32_t)0x00040000U) /* DACy data output register status flag */ +#define DAC_STS_TROVCFLAGy ((uint32_t)0x00080000U) /* DACy trigger source overclock status flag */ +#define DAC_STS_VFLAGyCOMP ((uint32_t)0x00100000U) /* Status flag that indicates DACy output is stable or not */ + +/***************** Bit definition for DAC_GCTRL register ******************/ +#define DAC12_GCTRL_HFSEL ((uint32_t)0x00000006U) /* HFSEL[1:0] (High frequency interface mode selection for DAC1/DAC2) */ +#define DAC12_GCTRL_HFSEL_0 ((uint32_t)0x00000002U) /* Bit 0 */ +#define DAC12_GCTRL_HFSEL_1 ((uint32_t)0x00000004U) /* Bit 1 */ + +#define DAC12_GCTRL_PCS ((uint32_t)0x00FF0000U) /* PCS[7:0] (The clock prescale of DAC1/DAC2 selection) */ +#define DAC12_GCTRL_PCS_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define DAC12_GCTRL_PCS_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define DAC12_GCTRL_PCS_2 ((uint32_t)0x00040000U) /* Bit 2 */ +#define DAC12_GCTRL_PCS_3 ((uint32_t)0x00080000U) /* Bit 3 */ +#define DAC12_GCTRL_PCS_4 ((uint32_t)0x00100000U) /* Bit 4 */ +#define DAC12_GCTRL_PCS_5 ((uint32_t)0x00200000U) /* Bit 5 */ +#define DAC12_GCTRL_PCS_6 ((uint32_t)0x00400000U) /* Bit 6 */ +#define DAC12_GCTRL_PCS_7 ((uint32_t)0x00800000U) /* Bit 7 */ + +#define DAC3456_GCTRL_PCS ((uint32_t)0x001F0000U) /* PCS[4:0] (The clock prescale of DAC3/DAC4DAC5/DAC6 selection) */ +#define DAC3456_GCTRL_PCS_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define DAC3456_GCTRL_PCS_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define DAC3456_GCTRL_PCS_2 ((uint32_t)0x00040000U) /* Bit 2 */ +#define DAC3456_GCTRL_PCS_3 ((uint32_t)0x00080000U) /* Bit 3 */ +#define DAC3456_GCTRL_PCS_4 ((uint32_t)0x00100000U) /* Bit 4 */ + +/***************** Bit definition for DAC_STINC register ******************/ +#define DAC_STINC_STINCDATAx ((uint32_t)0x00000FFFU) /* STINCDATAx[11:0] (The sawtooth step value of DACx) */ +#define DAC_STINC_STINCDATAy ((uint32_t)0x0FFF0000U) /* STINCDATAy[11:0] (The sawtooth step value of DACy) */ + +/***************** Bit definition for DAC_STRST register ******************/ +#define DAC_STRST_STRSTDATAx ((uint32_t)0x00000FFFU) /* STRSTDATAx[11:0] (The sawtooth reset value of DACx) */ +#define DAC_STRST_STRSTDATAy ((uint32_t)0x0FFF0000U) /* STRSTDATAy[11:0] (The sawtooth reset value of DACy) */ + +/***************** Bit definition for DAC_CALC register ******************/ +#define DAC_CALC_OTRIMx ((uint32_t)0x0000001FU) /* OTRIMx[4:0] (The calibration offset value of DACx) */ +#define DAC_CALC_OTRIMy ((uint32_t)0x001F0000U) /* OTRIMy[4:0] (The calibration offset value of DACy) */ + + +/*** Comparators Peripheral Interface ***/ +/******** Bit definition for COMP1_CTRL register ********/ +#define COMP1_CTRL_VV1TRM ((uint32_t)0x1F800000U) /* Bit[28:23] Internal 6bit-dac1 output voltage size*/ +#define COMP1_CTRL_VV1TRM_0 ((uint32_t)0x00800000U) /* Bit23*/ +#define COMP1_CTRL_VV1TRM_1 ((uint32_t)0x01000000U) /* Bit24*/ +#define COMP1_CTRL_VV1TRM_2 ((uint32_t)0x02000000U) /* Bit25*/ +#define COMP1_CTRL_VV1TRM_3 ((uint32_t)0x04000000U) /* Bit26*/ +#define COMP1_CTRL_VV1TRM_4 ((uint32_t)0x08000000U) /* Bit27*/ +#define COMP1_CTRL_VV1TRM_5 ((uint32_t)0x10000000U) /* Bit28*/ + +#define COMP1_CTRL_VV1EN ((uint32_t)0x00400000U) /* Bit[22] Internal 6bit-dac1 output enable*/ + +#define COMP1_CTRL_OUT ((uint32_t)0x00200000U) /* Bit[21] Output state of Comparator_1 */ + +#define COMP1_CTRL_BLKINGEN ((uint32_t)0x00100000U) /* Bit[20] Comparator_1 Blanking enable */ + +#define COMP1_CTRL_BLKING ((uint32_t)0x000F0000U) /* Bit[19:16] Blanking source select of Comparator_1 */ +#define COMP1_CTRL_BLKING_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define COMP1_CTRL_BLKING_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define COMP1_CTRL_BLKING_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define COMP1_CTRL_BLKING_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define COMP1_CTRL_HYST ((uint32_t)0x0000C000U) /* Bit[15:14] Hysteresis level select of Comparator_1*/ +#define COMP1_CTRL_HYST_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define COMP1_CTRL_HYST_1 ((uint32_t)0x00008000U) /* Bit15*/ + +#define COMP1_CTRL_POL ((uint32_t)0x00002000U) /* Bit[13] */ + +#define COMP1_CTRL_INPSEL ((uint32_t)0x000001E0U) /* Bit[8:5] Non inverting input select of Comparator_1*/ +#define COMP1_CTRL_INPSEL_0 ((uint32_t)0x00000020U) /* Bit5*/ +#define COMP1_CTRL_INPSEL_1 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP1_CTRL_INPSEL_2 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP1_CTRL_INPSEL_3 ((uint32_t)0x00000100U) /* Bit8*/ + +#define COMP1_CTRL_INMSEL ((uint32_t)0x0000001EU) /* Bit[4:1] Inverting input select of Comparator_1*/ +#define COMP1_CTRL_INMSEL_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP1_CTRL_INMSEL_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP1_CTRL_INMSEL_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP1_CTRL_INMSEL_3 ((uint32_t)0x00000010U) /* Bit4*/ + +#define COMP1_CTRL_EN ((uint32_t)0x00000001U) /* Bit[0] Comparator_1 enable */ + +/******** Bit definition for COMP1_FILC register ********/ +#define COMP1_FILC_VN_FLAG ((uint32_t)0x00001000U) /* Bit12*/ +#define COMP1_FILC_VP_FLAG ((uint32_t)0x00000800U) /* Bit11*/ + +#define COMP1_FILC_SAMPW ((uint32_t)0x000007C0U) /* Bit[10:6] Comparator_1 filter window size*/ +#define COMP1_FILC_SAMPW_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP1_FILC_SAMPW_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP1_FILC_SAMPW_2 ((uint32_t)0x00000100U) /* Bit8*/ +#define COMP1_FILC_SAMPW_3 ((uint32_t)0x00000200U) /* Bit9*/ +#define COMP1_FILC_SAMPW_4 ((uint32_t)0x00000400U) /* Bit10*/ + +#define COMP1_FILC_THRESH ((uint32_t)0x0000003EU) /* Bit[5:1] Comparator_1 filter threshold size*/ +#define COMP1_FILC_THRESH_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP1_FILC_THRESH_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP1_FILC_THRESH_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP1_FILC_THRESH_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define COMP1_FILC_THRESH_4 ((uint32_t)0x00000020U) /* Bit5*/ + +#define COMP1_FILC_FILEN ((uint32_t)0x00000001U) /* Bit[0] Comparator_1 filter enable*/ + +/******** Bit definition for COMP1_FILP register ********/ +#define COMP1_FILP_CLKPSC ((uint32_t)0x0000FFFFU) /* Bit[15:0] Comparator_1 filter sample clock prescale*/ + +/******** Bit definition for COMP2_CTRL register ********/ +#define COMP2_CTRL_VV2TRM ((uint32_t)0x1F800000U) /* Bit[28:23] Internal 6bit-dac2 output voltage size*/ +#define COMP2_CTRL_VV2TRM_0 ((uint32_t)0x00800000U) /* Bit23*/ +#define COMP2_CTRL_VV2TRM_1 ((uint32_t)0x01000000U) /* Bit24*/ +#define COMP2_CTRL_VV2TRM_2 ((uint32_t)0x02000000U) /* Bit25*/ +#define COMP2_CTRL_VV2TRM_3 ((uint32_t)0x04000000U) /* Bit26*/ +#define COMP2_CTRL_VV2TRM_4 ((uint32_t)0x08000000U) /* Bit27*/ +#define COMP2_CTRL_VV2TRM_5 ((uint32_t)0x10000000U) /* Bit28*/ + +#define COMP2_CTRL_VV2EN ((uint32_t)0x00400000U) /* Bit[22] Internal 6bit-dac2 output enable*/ +#define COMP2_CTRL_OUT ((uint32_t)0x00200000U) /* Bit[21] Output state of Comparator_2*/ + +#define COMP2_CTRL_BLKINGEN ((uint32_t)0x00100000U) /* Bit[20] Comparator_2 Blanking enable*/ + +#define COMP2_CTRL_BLKING ((uint32_t)0x000F0000U) /* Bit[19:16] Blanking source select of Comparator_2*/ +#define COMP2_CTRL_BLKING_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define COMP2_CTRL_BLKING_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define COMP2_CTRL_BLKING_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define COMP2_CTRL_BLKING_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define COMP2_CTRL_HYST ((uint32_t)0x0000C000U) /* Bit[15:14] Hysteresis level select of Comparator_2*/ +#define COMP2_CTRL_HYST_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define COMP2_CTRL_HYST_1 ((uint32_t)0x00008000U) /* Bit15*/ + +#define COMP2_CTRL_POL ((uint32_t)0x00002000U) /* Bit[13] */ + +#define COMP2_CTRL_INPSEL ((uint32_t)0x000001E0U) /* Bit[8:5] Non inverting input select of Comparator_2*/ +#define COMP2_CTRL_INPSEL_0 ((uint32_t)0x00000020U) /* Bit5*/ +#define COMP2_CTRL_INPSEL_1 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP2_CTRL_INPSEL_2 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP2_CTRL_INPSEL_3 ((uint32_t)0x00000100U) /* Bit8*/ + +#define COMP2_CTRL_INMSEL ((uint32_t)0x0000001EU) /* Bit[4:1] Inverting input select of Comparator_2*/ +#define COMP2_CTRL_INMSEL_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP2_CTRL_INMSEL_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP2_CTRL_INMSEL_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP2_CTRL_INMSEL_3 ((uint32_t)0x00000010U) /* Bit4*/ + +#define COMP2_CTRL_EN ((uint32_t)0x00000001U) /* Bit[0] Comparator_2 enable*/ + +/******** Bit definition for COMP2_FILC register ********/ +#define COMP2_FILC_SAMPW ((uint32_t)0x000007C0U) /* Bit[10:6] Comparator_2 filter window size*/ +#define COMP2_FILC_SAMPW_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP2_FILC_SAMPW_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP2_FILC_SAMPW_2 ((uint32_t)0x00000100U) /* Bit8*/ +#define COMP2_FILC_SAMPW_3 ((uint32_t)0x00000200U) /* Bit9*/ +#define COMP2_FILC_SAMPW_4 ((uint32_t)0x00000400U) /* Bit10*/ + +#define COMP2_FILC_THRESH ((uint32_t)0x0000003EU) /* Bit[5:1] Comparator_2 filter threshold size*/ +#define COMP2_FILC_THRESH_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP2_FILC_THRESH_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP2_FILC_THRESH_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP2_FILC_THRESH_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define COMP2_FILC_THRESH_4 ((uint32_t)0x00000020U) /* Bit5*/ + +#define COMP2_FILC_FILEN ((uint32_t)0x00000001U) /* Bit[0] Comparator_2 filter enable */ + +/******** Bit definition for COMP2_FILP register ********/ +#define COMP2_FILP_CLKPSC ((uint32_t)0x0000FFFFU) /* Bit[15:0] Comparator_2 filter sample clock prescale*/ + +/******** Bit definition for COMP3_CTRL register ********/ +#define COMP3_CTRL_OUT ((uint32_t)0x00200000U) /* Bit[21] Output state of Comparator_3*/ + +#define COMP3_CTRL_BLKINGEN ((uint32_t)0x00100000U) /* Bit[20] Comparator_3 Blanking enable*/ + +#define COMP3_CTRL_BLKING ((uint32_t)0x000F0000U) /* Bit[19:16] Blanking source select of Comparator_3*/ +#define COMP3_CTRL_BLKING_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define COMP3_CTRL_BLKING_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define COMP3_CTRL_BLKING_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define COMP3_CTRL_BLKING_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define COMP3_CTRL_HYST ((uint32_t)0x0000C000U) /* Bit[15:14] Hysteresis level select of Comparator_3*/ +#define COMP3_CTRL_HYST_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define COMP3_CTRL_HYST_1 ((uint32_t)0x00008000U) /* Bit15*/ +#define COMP3_CTRL_POL ((uint32_t)0x00002000U) /* Bit[13] */ + +#define COMP3_CTRL_INPSEL ((uint32_t)0x000001E0U) /* Bit[8:5] Non inverting input select of Comparator_3*/ +#define COMP3_CTRL_INPSEL_0 ((uint32_t)0x00000020U) /* Bit5*/ +#define COMP3_CTRL_INPSEL_1 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP3_CTRL_INPSEL_2 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP3_CTRL_INPSEL_3 ((uint32_t)0x00000100U) /* Bit8*/ + +#define COMP3_CTRL_INMSEL ((uint32_t)0x0000001EU) /* Bit[4:1] Inverting input select of Comparator_3*/ +#define COMP3_CTRL_INMSEL_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP3_CTRL_INMSEL_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP3_CTRL_INMSEL_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP3_CTRL_INMSEL_3 ((uint32_t)0x00000010U) /* Bit4*/ + +#define COMP3_CTRL_EN ((uint32_t)0x00000001U) /* Bit[0] Comparator_3 enable*/ + +/******** Bit definition for COMP3_FILC register ********/ +#define COMP3_FILC_SAMPW ((uint32_t)0x000007C0U) /* Bit[10:6] Comparator_3 filter window size*/ +#define COMP3_FILC_SAMPW_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP3_FILC_SAMPW_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP3_FILC_SAMPW_2 ((uint32_t)0x00000100U) /* Bit8*/ +#define COMP3_FILC_SAMPW_3 ((uint32_t)0x00000200U) /* Bit9*/ +#define COMP3_FILC_SAMPW_4 ((uint32_t)0x00000400U) /* Bit10*/ + +#define COMP3_FILC_THRESH ((uint32_t)0x0000003EU) /* Bit[5:1] Comparator_3 filter threshold size*/ +#define COMP3_FILC_THRESH_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP3_FILC_THRESH_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP3_FILC_THRESH_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP3_FILC_THRESH_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define COMP3_FILC_THRESH_4 ((uint32_t)0x00000020U) /* Bit5*/ + +#define COMP3_FILC_FILEN ((uint32_t)0x00000001U) /* Bit[0] Comparator_3 filter enable */ + +/******** Bit definition for COMP3_FILP register ********/ +#define COMP3_FILP_CLKPSC ((uint32_t)0x0000FFFFU) /* Bit[15:0] Comparator_3 filter sample clock prescale*/ + +/******** Bit definition for COMP4_CTRL register ********/ +#define COMP4_CTRL_OUT ((uint32_t)0x00100000U) /* Bit[20] Output state of Comparator_4*/ + +#define COMP4_CTRL_BLKINGEN ((uint32_t)0x00100000U) /* Bit[20] Comparator_4 Blanking enable*/ + +#define COMP4_CTRL_BLKING ((uint32_t)0x000F0000U) /* Bit[19:16] Blanking source select of Comparator_4*/ +#define COMP4_CTRL_BLKING_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define COMP4_CTRL_BLKING_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define COMP4_CTRL_BLKING_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define COMP4_CTRL_BLKING_3 ((uint32_t)0x00080000U) /* Bit19*/ + +#define COMP4_CTRL_HYST ((uint32_t)0x0000C000U) /* Bit[15:14] Hysteresis level select of Comparator_4*/ +#define COMP4_CTRL_HYST_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define COMP4_CTRL_HYST_1 ((uint32_t)0x00008000U) /* Bit15*/ +#define COMP4_CTRL_POL ((uint32_t)0x00002000U) /* Bit[13] */ + +#define COMP4_CTRL_INPSEL ((uint32_t)0x000001E0U) /* Bit[8:5] Non inverting input select of Comparator_4*/ +#define COMP4_CTRL_INPSEL_0 ((uint32_t)0x00000020U) /* Bit5*/ +#define COMP4_CTRL_INPSEL_1 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP4_CTRL_INPSEL_2 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP4_CTRL_INPSEL_3 ((uint32_t)0x00000100U) /* Bit8*/ + +#define COMP4_CTRL_INMSEL ((uint32_t)0x0000001EU) /* Bit[4:1] Inverting input select of Comparator_4*/ +#define COMP4_CTRL_INMSEL_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP4_CTRL_INMSEL_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP4_CTRL_INMSEL_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP4_CTRL_INMSEL_3 ((uint32_t)0x00000010U) /* Bit4*/ + +#define COMP4_CTRL_EN ((uint32_t)0x00000001U) /* Bit[0] Comparator_4 enable*/ + +/******** Bit definition for COMP4_FILC register ********/ +#define COMP4_FILC_SAMPW ((uint32_t)0x000007C0U) /* Bit[10:6] Comparator_4 filter window size*/ +#define COMP4_FILC_SAMPW_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define COMP4_FILC_SAMPW_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define COMP4_FILC_SAMPW_2 ((uint32_t)0x00000100U) /* Bit8*/ +#define COMP4_FILC_SAMPW_3 ((uint32_t)0x00000200U) /* Bit9*/ +#define COMP4_FILC_SAMPW_4 ((uint32_t)0x00000400U) /* Bit10*/ + +#define COMP4_FILC_THRESH ((uint32_t)0x0000003EU) /* Bit[5:1] Comparator_4 filter threshold size*/ +#define COMP4_FILC_THRESH_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define COMP4_FILC_THRESH_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define COMP4_FILC_THRESH_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define COMP4_FILC_THRESH_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define COMP4_FILC_THRESH_4 ((uint32_t)0x00000020U) /* Bit5*/ + +#define COMP4_FILC_FILEN ((uint32_t)0x00000001U) /* Bit[0] Comparator_4 filter enable */ + +/******** Bit definition for COMP4_FILP register ********/ +#define COMP4_FILP_CLKPSC ((uint32_t)0x0000FFFFU) /* Bit[15:0] Comparator_4 filter sample clock prescale*/ + +/******** Bit definition for COMP_LPR register ********/ +#define COMP_LPR_CLKSEL ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for COMP_WINMODE register ********/ +#define COMP_WINMODE_COMP34MD ((uint32_t)0x00000002U) /* Bit[1] Comparator_3&4 XOR output*/ +#define COMP_WINMODE_COMP12MD ((uint32_t)0x00000001U) /* Bit[0] Comparator_1&2 XOR output*/ + +/******** Bit definition for COMP_LOCK register ********/ +#define COMP_LOCK_MASK ((uint32_t)0x0000000FU) /* All comparator lock enable */ +#define COMP_LOCK_CMP4LK ((uint32_t)0x00000008U) /* Bit[3] */ +#define COMP_LOCK_CMP3LK ((uint32_t)0x00000004U) /* Bit[2] */ +#define COMP_LOCK_CMP2LK ((uint32_t)0x00000002U) /* Bit[1] */ +#define COMP_LOCK_CMP1LK ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for COMP_INTEN register ********/ +#define COMP_INTEN_MASK ((uint32_t)0x0000000FU) /* Interrupt enable for all COMP */ +#define COMP_INTEN_CMP4IEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define COMP_INTEN_CMP3IEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define COMP_INTEN_CMP2IEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define COMP_INTEN_CMP1IEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for COMP_STS register ********/ +#define COMP_STS_MASK ((uint32_t)0x0000007FU) /* status of all Comparator */ +#define COMP_STS_CMP4IS ((uint32_t)0x00000008U) /* Bit[3] */ +#define COMP_STS_CMP3IS ((uint32_t)0x00000004U) /* Bit[2] */ +#define COMP_STS_CMP2IS ((uint32_t)0x00000002U) /* Bit[1] */ +#define COMP_STS_CMP1IS ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for COMP_OTIMEN register ********/ +#define COMP_OTIMEN_MASK ((uint32_t)0x0000000FU) /* Output to timer for all Comparator */ +#define COMP_OTIMEN_CMP4OEN ((uint32_t)0x00000008U) /* Bit[3] */ +#define COMP_OTIMEN_CMP3OEN ((uint32_t)0x00000004U) /* Bit[2] */ +#define COMP_OTIMEN_CMP2OEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define COMP_OTIMEN_CMP1OEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/*** VREFBUF ***/ +/******** Bit definition for VREFBUF_TRIM1 register ********/ +#define VREFBUF_TRIM1_2_5V_MASK ((uint32_t)0x003F0000U) /* VREFBUF 2.5V TRIMMING*/ +#define VREFBUF_TRIM1_2_048V_MASK ((uint32_t)0x0FC00000U) /* VREFBUF 2.048V TRIMMING */ + +/******** Bit definition for VREFBUF_STS register ********/ +#define VREFBUF_STS_RDY ((uint32_t)0x20000000U) /* VREFBUF ready flag */ + +/******** Bit definition for VREFBUF_CTRL1 register ********/ +#define VREFBUF_CTRL1_EN ((uint32_t)0x00000080U) /* VREFBUF enable */ +#define VREFBUF_CTRL1_HIM ((uint32_t)0x00000200U) /* VREFBUF high implement enable */ + +/******** Bit definition for VREFBUF_CTRL2 register ********/ +#define VREFBUF_CTRL2_VLSEL ((uint32_t)0x00000003U) /* VLSEL[1:0]*/ +#define VREFBUF_CTRL2_VLSEL_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define VREFBUF_CTRL2_VLSEL_1 ((uint32_t)0x00000002U) /* Bit 1 */ + +/******** Bit definition for VREFBUF_TRIM1 register ********/ +#define VREFBUF_TRIM1_1_5V_MASK ((uint32_t)0x00003F00U) /* VREFBUF 1.5V TRIMMING*/ +#define VREFBUF_TRIM1_1_8V_MASK ((uint32_t)0x0000003FU) /* VREFBUF 1.8V TRIMMING */ + + +/*** TIM ***/ + +/** Bit definition for TIM_CTRL1 register **/ +#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001U) /* Counter enable */ +#define TIM_CTRL1_DIR ((uint32_t)0x00000002U) /* Direction */ + +#define TIM_CTRL1_CAMSEL ((uint32_t)0x0000000CU) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000004U) /* Bit 0 */ +#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000008U) /* Bit 1 */ + +#define TIM_CTRL1_UPRS ((uint32_t)0x00000010U) /* Update request source */ +#define TIM_CTRL1_UPDIS ((uint32_t)0x00000020U) /* Update disable */ + +#define TIM_CTRL1_CLKD ((uint32_t)0x000000C0U) /* CKD[1:0] bits (clock division) */ +#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000040U) /* Bit 0 */ +#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000080U) /* Bit 1 */ + +#define TIM_CTRL1_ONEPM ((uint32_t)0x00000100U) /* One pulse mode */ +#define TIM_CTRL1_ARPEN ((uint32_t)0x00000200U) /* Auto-reload preload enable */ +#define TIM_CTRL1_LBKPEN ((uint32_t)0x00000400U) /* LOCKUP as bkp Enable*/ +#define TIM_CTRL1_PBKPEN ((uint32_t)0x00000800U) /* PVD as bkp Enable */ +#define TIM_CTRL1_SMPARERREN ((uint32_t)0x00001000U) /* Sram parity error as bkp Enable */ +#define TIM_CTRL1_CLRSEL ((uint32_t)0x00002000U) /* OCxRef clear selection */ +#define TIM_CTRL1_SMECCERREN ((uint32_t)0x00008000U) /* Sram ecc error as bkp Enable */ + +#define TIM_CTRL1_C1SEL ((uint32_t)0x00010000U) /* Channel 1 selection */ +#define TIM_CTRL1_C2SEL ((uint32_t)0x00020000U) /* Channel 2 selection */ +#define TIM_CTRL1_C3SEL ((uint32_t)0x00040000U) /* Channel 3 selection */ +#define TIM_CTRL1_C4SEL ((uint32_t)0x00080000U) /* Channel 4 selection */ + +#define TIM_CTRL1_CMODE ((uint32_t)0x00300000U) /* In center-aligned mode, channel 4/7/8/9 trigger mode */ +#define TIM_CTRL1_CMODE_0 ((uint32_t)0x00100000U) /* Bit0 */ +#define TIM_CTRL1_CMODE_1 ((uint32_t)0x00200000U) /* Bit1 */ + +#define TIM_CTRL1_ASMMETRIC ((uint32_t)0x00800000U) /* Asynmmetric mode enable in center-aligned */ +#define TIM_CTRL1_UDITFREMAP ((uint32_t)0x01000000U) /* UDITF status bit remapping */ + +/** Bit definition for TIM_CTRL2 register **/ +#define TIM_CTRL2_OI1 ((uint32_t)0x00000001U) /* Output Idle state 1 (OC1 output) */ +#define TIM_CTRL2_OI1N ((uint32_t)0x00000002U) /* Output Idle state 1 (OC1N output) */ +#define TIM_CTRL2_OI2 ((uint32_t)0x00000004U) /* Output Idle state 2 (OC2 output) */ +#define TIM_CTRL2_OI2N ((uint32_t)0x00000008U) /* Output Idle state 2 (OC2N output) */ +#define TIM_CTRL2_OI3 ((uint32_t)0x00000010U) /* Output Idle state 3 (OC3 output) */ +#define TIM_CTRL2_OI3N ((uint32_t)0x00000020U) /* Output Idle state 3 (OC3N output) */ +#define TIM_CTRL2_OI4 ((uint32_t)0x00000040U) /* Output Idle state 4 (OC4 output) */ +#define TIM_CTRL2_OI4N ((uint32_t)0x00000080U) /* Output Idle state 4 (OC4N output) */ +#define TIM_CTRL2_OI5 ((uint32_t)0x00000100U) /* Output Idle state 5 (OC5 output) */ +#define TIM_CTRL2_OI6 ((uint32_t)0x00000400U) /* Output Idle state 6 (OC6 output) */ + +#define TIM_CTRL2_MMSEL ((uint32_t)0x0000F000U) /* MMSEL[3:0] bits (Master Mode Selection) */ +#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define TIM_CTRL2_MMSEL_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +#define TIM_CTRL2_CCUSEL ((uint32_t)0x00010000U) /* Capture/Compare Control Update Selection */ +#define TIM_CTRL2_CCDSEL ((uint32_t)0x00020000U) /* Capture/Compare DMA Selection */ +#define TIM_CTRL2_CCPCTL ((uint32_t)0x00040000U) /* Capture/Compare Preloaded Control */ +#define TIM_CTRL2_TI1SEL ((uint32_t)0x00080000U) /* TI1 Selection */ +#define TIM_CTRL2_TRIG4 ((uint32_t)0x00100000U) /* OC4REF trigger to ADC enable */ +#define TIM_CTRL2_TRIG7 ((uint32_t)0x00200000U) /* OC7REF trigger to ADC enable */ +#define TIM_CTRL2_TRIG8 ((uint32_t)0x00400000U) /* OC7REF trigger to ADC enable */ +#define TIM_CTRL2_TRIG9 ((uint32_t)0x00800000U) /* OC7REF trigger to ADC enable */ + +#define TIM_CTRL2_MMSEL2 ((uint32_t)0x0F000000U) /* MMSEL2[3:0] bits (Master Mode Selection) */ +#define TIM_CTRL2_MMSEL2_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_CTRL2_MMSEL2_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_CTRL2_MMSEL2_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_CTRL2_MMSEL2_3 ((uint32_t)0x08000000U) /* Bit 3 */ + +/** Bit definition for TIM_STS register **/ +#define TIM_STS_CC1ITF ((uint32_t)0x00000001U) /* Capture/Compare 1 interrupt Flag */ +#define TIM_STS_CC2ITF ((uint32_t)0x00000002U) /* Capture/Compare 2 interrupt Flag */ +#define TIM_STS_CC3ITF ((uint32_t)0x00000004U) /* Capture/Compare 3 interrupt Flag */ +#define TIM_STS_CC4ITF ((uint32_t)0x00000008U) /* Capture/Compare 4 interrupt Flag */ +#define TIM_STS_CC5ITF ((uint32_t)0x00000010U) /* Capture/Compare 5 interrupt Flag */ +#define TIM_STS_CC6ITF ((uint32_t)0x00000020U) /* Capture/Compare 6 interrupt Flag */ +#define TIM_STS_CC1OCF ((uint32_t)0x00000100U) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_STS_CC2OCF ((uint32_t)0x00000200U) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_STS_CC3OCF ((uint32_t)0x00000400U) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_STS_CC4OCF ((uint32_t)0x00000800U) /* Capture/Compare 4 Overcapture Flag */ +#define TIM_STS_UDITF ((uint32_t)0x00010000U) /* Update interrupt Flag */ +#define TIM_STS_COMITF ((uint32_t)0x00020000U) /* COM interrupt Flag */ +#define TIM_STS_TITF ((uint32_t)0x00040000U) /* Trigger interrupt Flag */ +#define TIM_STS_BITF ((uint32_t)0x00080000U) /* Break interrupt Flag */ +#define TIM_STS_BITF2 ((uint32_t)0x00100000U) /* Break2 interrupt Flag */ +#define TIM_STS_SBITF ((uint32_t)0x00200000U) /* System Break interrupt Flag */ +#define TIM_STS_CC7ITF ((uint32_t)0x01000000U) /* Capture/Compare 7 interrupt Flag */ +#define TIM_STS_CC8ITF ((uint32_t)0x02000000U) /* Capture/Compare 8 interrupt Flag */ +#define TIM_STS_CC9ITF ((uint32_t)0x04000000U) /* Capture/Compare 9 interrupt Flag */ + +/** Bit definition for TIM_EVTGEN register **/ +#define TIM_EVTGEN_CC1GN ((uint32_t)0x00000001U) /* Capture/Compare 1 Generation */ +#define TIM_EVTGEN_CC2GN ((uint32_t)0x00000002U) /* Capture/Compare 2 Generation */ +#define TIM_EVTGEN_CC3GN ((uint32_t)0x00000004U) /* Capture/Compare 3 Generation */ +#define TIM_EVTGEN_CC4GN ((uint32_t)0x00000008U) /* Capture/Compare 4 Generation */ +#define TIM_EVTGEN_UDGN ((uint32_t)0x00000100U) /* Update Generation */ +#define TIM_EVTGEN_CCUDGN ((uint32_t)0x00000200U) /* Capture/Compare Control Update Generation */ +#define TIM_EVTGEN_TGN ((uint32_t)0x00000400U) /* Trigger Generation */ +#define TIM_EVTGEN_BGN ((uint32_t)0x00000800U) /* Break Generation */ +#define TIM_EVTGEN_BGN2 ((uint32_t)0x00001000U) /* Break2 Generation */ + +/** Bit definition for TIM_SMCTRL register **/ +#define TIM_SMCTRL_TSEL ((uint32_t)0x00000007U) /* TS[2:0] bits (Trigger selection) */ +#define TIM_SMCTRL_TSEL_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define TIM_SMCTRL_TSEL_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define TIM_SMCTRL_TSEL_2 ((uint32_t)0x00000004U) /* Bit 2 */ + +#define TIM_SMCTRL_SMSEL ((uint32_t)0x000000F0U) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCTRL_SMSEL_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define TIM_SMCTRL_SMSEL_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define TIM_SMCTRL_SMSEL_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define TIM_SMCTRL_SMSEL_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define TIM_SMCTRL_EXTPS ((uint32_t)0x00000300U) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCTRL_EXTPS_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define TIM_SMCTRL_EXTPS_1 ((uint32_t)0x00000200U) /* Bit 1 */ + +#define TIM_SMCTRL_EXCEN ((uint32_t)0x00000400U) /* External clock enable */ +#define TIM_SMCTRL_EXTP ((uint32_t)0x00000800U) /* External trigger polarity */ + +#define TIM_SMCTRL_EXTF ((uint32_t)0x0000F000U) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCTRL_EXTF_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define TIM_SMCTRL_EXTF_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define TIM_SMCTRL_EXTF_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define TIM_SMCTRL_EXTF_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +#define TIM_SMCTRL_MSMD ((uint32_t)0x00010000U) /* Master/slave mode */ + +#define TIM_SMCTRL_OCREFCLRP ((uint32_t)0x00080000U) /* Ocrefclear signal polarity */ + +#define TIM_SMCTRL_OCREFCLRF ((uint32_t)0x00F00000U) /* OCREFCLRF[3:0] bits (Ocrefclear signal prescaler) */ +#define TIM_SMCTRL_OCREFCLRF_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define TIM_SMCTRL_OCREFCLRF_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define TIM_SMCTRL_OCREFCLRF_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define TIM_SMCTRL_OCREFCLRF_3 ((uint32_t)0x00800000U) /* Bit 3 */ + +/** Bit definition for TIM_DINTEN register **/ +#define TIM_DINTEN_CC1IEN ((uint32_t)0x00000001U) /* Capture/Compare 1 interrupt enable */ +#define TIM_DINTEN_CC2IEN ((uint32_t)0x00000002U) /* Capture/Compare 2 interrupt enable */ +#define TIM_DINTEN_CC3IEN ((uint32_t)0x00000004U) /* Capture/Compare 3 interrupt enable */ +#define TIM_DINTEN_CC4IEN ((uint32_t)0x00000008U) /* Capture/Compare 4 interrupt enable */ +#define TIM_DINTEN_CC5IEN ((uint32_t)0x00000010U) /* Capture/Compare 5 interrupt enable */ +#define TIM_DINTEN_CC6IEN ((uint32_t)0x00000020U) /* Capture/Compare 6 interrupt enable */ +#define TIM_DINTEN_CC7IEN ((uint32_t)0x00000040U) /* Capture/Compare 7 interrupt enable */ +#define TIM_DINTEN_CC8IEN ((uint32_t)0x00000080U) /* Capture/Compare 8 interrupt enable */ +#define TIM_DINTEN_CC1DEN ((uint32_t)0x00000100U) /* Capture/Compare 1 DMA request enable */ +#define TIM_DINTEN_CC2DEN ((uint32_t)0x00000200U) /* Capture/Compare 2 DMA request enable */ +#define TIM_DINTEN_CC3DEN ((uint32_t)0x00000400U) /* Capture/Compare 3 DMA request enable */ +#define TIM_DINTEN_CC4DEN ((uint32_t)0x00000800U) /* Capture/Compare 4 DMA request enable */ +#define TIM_DINTEN_UIEN ((uint32_t)0x00010000U) /* Update interrupt enable */ +#define TIM_DINTEN_TIEN ((uint32_t)0x00020000U) /* Trigger interrupt enable */ +#define TIM_DINTEN_BIEN ((uint32_t)0x00040000U) /* Break interrupt enable */ +#define TIM_DINTEN_UDEN ((uint32_t)0x00080000U) /* Update DMA request enable */ +#define TIM_DINTEN_COMDEN ((uint32_t)0x00100000U) /* COM DMA request enable */ +#define TIM_DINTEN_TDEN ((uint32_t)0x00200000U) /* Trigger DMA request enable */ +#define TIM_DINTEN_COMIEN ((uint32_t)0x00400000U) /* COM interrupt enable */ +#define TIM_DINTEN_CC9IEN ((uint32_t)0x00800000U) /* Capture/Compare 9 interrupt enable */ + +/** Bit definition for TIM_CCMOD1 register **/ +#define TIM_CCMOD1_CC1SEL ((uint32_t)0x00000003U) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMOD1_CC1SEL_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define TIM_CCMOD1_CC1SEL_1 ((uint32_t)0x00000002U) /* Bit 1 */ + +#define TIM_CCMOD1_OC1PEN ((uint32_t)0x00000004U) /* Output Compare 1 Preload enable */ +#define TIM_CCMOD1_OC1FEN ((uint32_t)0x00000008U) /* Output Compare 1 Fast enable */ +#define TIM_CCMOD1_OC1CEN ((uint32_t)0x00000010U) /* Output Compare 1 Clear Enable */ + +#define TIM_CCMOD1_OC1MD ((uint32_t)0x000000E0U) /* OC1MD[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMOD1_OC1MD_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define TIM_CCMOD1_OC1MD_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define TIM_CCMOD1_OC1MD_2 ((uint32_t)0x00000080U) /* Bit 2 */ + +#define TIM_CCMOD1_CC2SEL ((uint32_t)0x00000300U) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMOD1_CC2SEL_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define TIM_CCMOD1_CC2SEL_1 ((uint32_t)0x00000200U) /* Bit 1 */ + +#define TIM_CCMOD1_OC2PEN ((uint32_t)0x00000400U) /* Output Compare 2 Preload enable */ +#define TIM_CCMOD1_OC2FEN ((uint32_t)0x00000800U) /* Output Compare 2 Fast enable */ +#define TIM_CCMOD1_OC2CEN ((uint32_t)0x00001000U) /* Output Compare 2 Clear Enable */ + +#define TIM_CCMOD1_OC2MD ((uint32_t)0x0000E000U) /* OC2MD[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMOD1_OC2MD_0 ((uint32_t)0x00002000U) /* Bit 0 */ +#define TIM_CCMOD1_OC2MD_1 ((uint32_t)0x00004000U) /* Bit 1 */ +#define TIM_CCMOD1_OC2MD_2 ((uint32_t)0x00008000U) /* Bit 2 */ + +#define TIM_CCMOD1_OC1MD_3 ((uint32_t)0x00020000U) /* OC1MD3 bit (Output Compare 1 Mode) */ +#define TIM_CCMOD1_OC2MD_3 ((uint32_t)0x00040000U) /* OC2MD3 bit (Output Compare 2 Mode) */ + +#define TIM_CCMOD1_IC1PSC ((uint32_t)0x0000000CU) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMOD1_IC1PSC_0 ((uint32_t)0x00000004U) /* Bit 0 */ +#define TIM_CCMOD1_IC1PSC_1 ((uint32_t)0x00000008U) /* Bit 1 */ + +#define TIM_CCMOD1_IC1F ((uint32_t)0x000000F0U) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMOD1_IC1F_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define TIM_CCMOD1_IC1F_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define TIM_CCMOD1_IC1F_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define TIM_CCMOD1_IC1F_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define TIM_CCMOD1_IC2PSC ((uint32_t)0x00000C00U) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMOD1_IC2PSC_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define TIM_CCMOD1_IC2PSC_1 ((uint32_t)0x00000800U) /* Bit 1 */ + +#define TIM_CCMOD1_IC2F ((uint32_t)0x0000F000U) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMOD1_IC2F_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define TIM_CCMOD1_IC2F_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define TIM_CCMOD1_IC2F_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define TIM_CCMOD1_IC2F_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +/** Bit definition for TIM_CCMOD2 register **/ +#define TIM_CCMOD2_CC3SEL ((uint32_t)0x00000003U) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMOD2_CC3SEL_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define TIM_CCMOD2_CC3SEL_1 ((uint32_t)0x00000002U) /* Bit 1 */ + +#define TIM_CCMOD2_OC3PEN ((uint32_t)0x00000004U) /* Output Compare 3 Preload enable */ +#define TIM_CCMOD2_OC3FEN ((uint32_t)0x00000008U) /* Output Compare 3 Fast enable */ +#define TIM_CCMOD2_OC3CEN ((uint32_t)0x00000010U) /* Output Compare 3 Clear Enable */ + +#define TIM_CCMOD2_OC3MD ((uint32_t)0x000000E0U) /* OC3MD[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMOD2_OC3MD_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define TIM_CCMOD2_OC3MD_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define TIM_CCMOD2_OC3MD_2 ((uint32_t)0x00000080U) /* Bit 2 */ + +#define TIM_CCMOD2_CC4SEL ((uint32_t)0x00000300U) /* CC3S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMOD2_CC4SEL_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define TIM_CCMOD2_CC4SEL_1 ((uint32_t)0x00000200U) /* Bit 1 */ + +#define TIM_CCMOD2_OC4PEN ((uint32_t)0x00000400U) /* Output Compare 4 Preload enable */ +#define TIM_CCMOD2_OC4FEN ((uint32_t)0x00000800U) /* Output Compare 4 Fast enable */ +#define TIM_CCMOD2_OC4CEN ((uint32_t)0x00001000U) /* Output Compare 4 Clear Enable */ + +#define TIM_CCMOD2_OC4MD ((uint32_t)0x0000E000U) /* OC4MD[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMOD2_OC4MD_0 ((uint32_t)0x00002000U) /* Bit 0 */ +#define TIM_CCMOD2_OC4MD_1 ((uint32_t)0x00004000U) /* Bit 1 */ +#define TIM_CCMOD2_OC4MD_2 ((uint32_t)0x00008000U) /* Bit 2 */ + +#define TIM_CCMOD2_OC3MD_3 ((uint32_t)0x00020000U) /* OC3MD3 bit (Output Compare 3 Mode) */ +#define TIM_CCMOD2_OC4MD_3 ((uint32_t)0x00040000U) /* OC4MD3 bit (Output Compare 4 Mode) */ + +#define TIM_CCMOD2_IC3PSC ((uint32_t)0x0000000CU) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMOD2_IC3PSC_0 ((uint32_t)0x00000004U) /* Bit 0 */ +#define TIM_CCMOD2_IC3PSC_1 ((uint32_t)0x00000008U) /* Bit 1 */ + +#define TIM_CCMOD2_IC3F ((uint32_t)0x000000F0U) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMOD2_IC3F_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define TIM_CCMOD2_IC3F_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define TIM_CCMOD2_IC3F_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define TIM_CCMOD2_IC3F_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define TIM_CCMOD2_IC4PSC ((uint32_t)0x00000C00U) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMOD2_IC4PSC_0 ((uint32_t)0x00000400U) /* Bit 0 */ +#define TIM_CCMOD2_IC4PSC_1 ((uint32_t)0x00000800U) /* Bit 1 */ + +#define TIM_CCMOD2_IC4F ((uint32_t)0x0000F000U) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMOD2_IC4F_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define TIM_CCMOD2_IC4F_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define TIM_CCMOD2_IC4F_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define TIM_CCMOD2_IC4F_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +/** Bit definition for TIM_CCMOD3 register **/ +#define TIM_CCMOD3_OC5PEN ((uint32_t)0x00000004U) /* Output Compare 5 Preload enable */ +#define TIM_CCMOD3_OC5FEN ((uint32_t)0x00000008U) /* Output Compare 5 Fast enable */ +#define TIM_CCMOD3_OC5CEN ((uint32_t)0x00000010U) /* Output Compare 5 Clear Enable */ + +#define TIM_CCMOD3_OC5MD ((uint32_t)0x000000E0U) /* OC5M[2:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMOD3_OC5MD_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define TIM_CCMOD3_OC5MD_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define TIM_CCMOD3_OC5MD_2 ((uint32_t)0x00000080U) /* Bit 2 */ + +#define TIM_CCMOD3_OC6PEN ((uint32_t)0x00000400U) /* Output Compare 6 Preload enable */ +#define TIM_CCMOD3_OC6FEN ((uint32_t)0x00000800U) /* Output Compare 6 Fast enable */ +#define TIM_CCMOD3_OC6CEN ((uint32_t)0x00001000U) /* Output Compare 6 Clear Enable */ + +#define TIM_CCMOD3_OC6MD ((uint32_t)0x0000E000U) /* OC6M[2:0] bits (Output Compare 6 Mode) */ +#define TIM_CCMOD3_OC6MD_0 ((uint32_t)0x00002000U) /* Bit 0 */ +#define TIM_CCMOD3_OC6MD_1 ((uint32_t)0x00004000U) /* Bit 1 */ +#define TIM_CCMOD3_OC6MD_2 ((uint32_t)0x00008000U) /* Bit 2 */ + +#define TIM_CCMOD3_OC7PEN ((uint32_t)0x00010000U) /* Output Compare 7 Preload enable */ +#define TIM_CCMOD3_OC8PEN ((uint32_t)0x00100000U) /* Output Compare 8 Preload enable */ +#define TIM_CCMOD3_OC9PEN ((uint32_t)0x01000000U) /* Output Compare 9 Preload enable */ + +/** Bit definition for TIM_CCEN register **/ +#define TIM_CCEN_CC1NEN ((uint32_t)0x00000001U) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CCEN_CC1NP ((uint32_t)0x00000002U) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCEN_CC1EN ((uint32_t)0x00000004U) /* Capture/Compare 1 output enable */ +#define TIM_CCEN_CC1P ((uint32_t)0x00000008U) /* Capture/Compare 1 output Polarity */ +#define TIM_CCEN_CC2NEN ((uint32_t)0x00000010U) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CCEN_CC2NP ((uint32_t)0x00000020U) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCEN_CC2EN ((uint32_t)0x00000040U) /* Capture/Compare 2 output enable */ +#define TIM_CCEN_CC2P ((uint32_t)0x00000080U) /* Capture/Compare 2 output Polarity */ +#define TIM_CCEN_CC3NEN ((uint32_t)0x00000100U) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CCEN_CC3NP ((uint32_t)0x00000200U) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCEN_CC3EN ((uint32_t)0x00000400U) /* Capture/Compare 3 output enable */ +#define TIM_CCEN_CC3P ((uint32_t)0x00000800U) /* Capture/Compare 3 output Polarity */ +#define TIM_CCEN_CC4NEN ((uint32_t)0x00001000U) /* Capture/Compare 4 Complementary output enable */ +#define TIM_CCEN_CC4NP ((uint32_t)0x00002000U) /* Capture/Compare 4 Complementary output Polarity */ +#define TIM_CCEN_CC4EN ((uint32_t)0x00004000U) /* Capture/Compare 4 output enable */ +#define TIM_CCEN_CC4P ((uint32_t)0x00008000U) /* Capture/Compare 4 output Polarity */ +#define TIM_CCEN_CC5EN ((uint32_t)0x00040000U) /* Capture/Compare 5 output enable */ +#define TIM_CCEN_CC5P ((uint32_t)0x00080000U) /* Capture/Compare 5 output Polarity */ +#define TIM_CCEN_CC6EN ((uint32_t)0x00400000U) /* Capture/Compare 6 output enable */ +#define TIM_CCEN_CC6P ((uint32_t)0x00800000U) /* Capture/Compare 6 output Polarity */ + +/** Bit definition for TIM_CCDAT1 register **/ +#define TIM_CCDAT1_CCDAT1 ((uint32_t)0x0000FFFFU) /* Capture/Compare 1 Value */ +#define TIM_CCDAT1_CCDDAT1 ((uint32_t)0xFFFF0000U) /* Capture/Compare 1 down-counting Value */ + +/** Bit definition for TIM_CCDAT2 register **/ +#define TIM_CCDAT2_CCDAT2 ((uint32_t)0x0000FFFFU) /* Capture/Compare 2 Value */ +#define TIM_CCDAT2_CCDDAT2 ((uint32_t)0xFFFF0000U) /* Capture/Compare 2 down-counting Value */ + +/** Bit definition for TIM_CCDAT3 register **/ +#define TIM_CCDAT3_CCDAT3 ((uint32_t)0x0000FFFFU) /* Capture/Compare 3 Value */ +#define TIM_CCDAT3_CCDDAT3 ((uint32_t)0xFFFF0000U) /* Capture/Compare 3 down-counting Value */ + +/** Bit definition for TIM_CCDAT4 register **/ +#define TIM_CCDAT4_CCDAT4 ((uint32_t)0x0000FFFFU) /* Capture/Compare 4 Value */ +#define TIM_CCDAT4_CCDDAT4 ((uint32_t)0xFFFF0000U) /* Capture/Compare 4 down-counting Value */ + +/** Bit definition for TIM_CCDAT5 register **/ +#define TIM_CCDAT5_CCDAT5 ((uint32_t)0x0000FFFFU) /* Capture/Compare 5 Value */ + +/** Bit definition for TIM_CCDAT6 register **/ +#define TIM_CCDAT6_CCDAT6 ((uint32_t)0x0000FFFFU) /* Capture/Compare 6 Value */ + +/** Bit definition for TIM_PSC register **/ +#define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /* Prescaler Value */ + +/** Bit definition for TIM_AR register **/ +#define TIM_AR_AR ((uint32_t)0x0000FFFFU) /* actual auto-reload Value */ + +/** Bit definition for TIM_CNT register **/ +#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFFU) /* Counter Value */ + +/** Bit definition for TIM_REPCNT register **/ +#define TIM_REPCNT_REPCNT ((uint32_t)0x000000FFU) /* Repetition Counter Value */ + +/** Bit definition for TIM_BKDT register **/ +#define TIM_BKDT_DTGN ((uint32_t)0x000000FFU) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BKDT_DTGN_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define TIM_BKDT_DTGN_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define TIM_BKDT_DTGN_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define TIM_BKDT_DTGN_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define TIM_BKDT_DTGN_4 ((uint32_t)0x00000010U) /* Bit 4 */ +#define TIM_BKDT_DTGN_5 ((uint32_t)0x00000020U) /* Bit 5 */ +#define TIM_BKDT_DTGN_6 ((uint32_t)0x00000040U) /* Bit 6 */ +#define TIM_BKDT_DTGN_7 ((uint32_t)0x00000080U) /* Bit 7 */ + +#define TIM_BKDT_MOEN ((uint32_t)0x00000100U) /* Main Output enable */ +#define TIM_BKDT_AOEN ((uint32_t)0x00000200U) /* Automatic Output enable */ +#define TIM_BKDT_BKP ((uint32_t)0x00000400U) /* Break Polarity */ +#define TIM_BKDT_BKEN ((uint32_t)0x00000800U) /* Break enable */ +#define TIM_BKDT_OSSI ((uint32_t)0x00001000U) /* Off-State Selection for Idle mode */ +#define TIM_BKDT_OSSR ((uint32_t)0x00002000U) /* Off-State Selection for Run mode */ + +#define TIM_BKDT_LCKCFG ((uint32_t)0x0000C000U) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BKDT_LCKCFG_0 ((uint32_t)0x00004000U) /* Bit 0 */ +#define TIM_BKDT_LCKCFG_1 ((uint32_t)0x00008000U) /* Bit 1 */ + +#define TIM_BKDT_BK2P ((uint32_t)0x00010000U) /* Break2 Polarity */ +#define TIM_BKDT_BK2EN ((uint32_t)0x00020000U) /* Break2 enable */ +#define TIM_BKDT_BRKDSRM ((uint32_t)0x00040000U) /* Break disarm */ +#define TIM_BKDT_BRK2DSRM ((uint32_t)0x00080000U) /* Break2 disarm */ +#define TIM_BKDT_BRKBID ((uint32_t)0x00100000U) /* Break bidirectional enable */ +#define TIM_BKDT_BRK2BID ((uint32_t)0x00200000U) /* Break2 bidirectional enable */ + +/** Bit definition for TIM_CCDAT7 register **/ +#define TIM_CCDAT7_CCDAT7 ((uint32_t)0x0000FFFFU) /* Capture/Compare 7 Value */ + +/** Bit definition for TIM_CCDAT8 register **/ +#define TIM_CCDAT8_CCDAT8 ((uint32_t)0x0000FFFFU) /* Capture/Compare 8 Value */ + +/** Bit definition for TIM_CCDAT9 register **/ +#define TIM_CCDAT9_CCDAT9 ((uint32_t)0x0000FFFFU) /* Capture/Compare 9 Value */ + +/** Bit definition for TIM_BKFR register **/ +#define TIM_BKFR_THRESH ((uint32_t)0x3F000000U) /* Break1 filter threshold */ +#define TIM_BKFR_THRESH_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_BKFR_THRESH_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_BKFR_THRESH_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_BKFR_THRESH_3 ((uint32_t)0x08000000U) /* Bit 3 */ +#define TIM_BKFR_THRESH_4 ((uint32_t)0x10000000U) /* Bit 4 */ +#define TIM_BKFR_THRESH_5 ((uint32_t)0x20000000U) /* Bit 5 */ + +#define TIM_BKFR_WSIZE ((uint32_t)0x007E0000U) /* Break1 filter window size */ +#define TIM_BKFR_WSIZE_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define TIM_BKFR_WSIZE_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define TIM_BKFR_WSIZE_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define TIM_BKFR_WSIZE_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define TIM_BKFR_WSIZE_4 ((uint32_t)0x00200000U) /* Bit 4 */ +#define TIM_BKFR_WSIZE_5 ((uint32_t)0x00400000U) /* Bit 5 */ + +#define TIM_BKFR_FILTEN ((uint32_t)0x00010000U) /* Break1 filter enable */ +#define TIM_BKFR_SFPSC ((uint32_t)0x0000FFFFU) + +/** Bit definition for TIM_C1FILT register **/ +#define TIM_C1FILT_THRESH ((uint32_t)0x3F000000U) /* CH1 filter threshold */ +#define TIM_C1FILT_THRESH_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_C1FILT_THRESH_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_C1FILT_THRESH_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_C1FILT_THRESH_3 ((uint32_t)0x08000000U) /* Bit 3 */ +#define TIM_C1FILT_THRESH_4 ((uint32_t)0x10000000U) /* Bit 4 */ +#define TIM_C1FILT_THRESH_5 ((uint32_t)0x20000000U) /* Bit 5 */ + +#define TIM_C1FILT_WSIZE ((uint32_t)0x007E0000U) /* CH1 filter window size */ +#define TIM_C1FILT_WSIZE_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define TIM_C1FILT_WSIZE_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define TIM_C1FILT_WSIZE_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define TIM_C1FILT_WSIZE_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define TIM_C1FILT_WSIZE_4 ((uint32_t)0x00200000U) /* Bit 4 */ +#define TIM_C1FILT_WSIZE_5 ((uint32_t)0x00400000U) /* Bit 5 */ + +#define TIM_C1FILT_FILTEN ((uint32_t)0x00010000U) +#define TIM_C1FILT_SFPSC ((uint32_t)0x0000FFFFU) + +/** Bit definition for TIM_C2FILT register **/ +#define TIM_C2FILT_THRESH ((uint32_t)0x3F000000U) /* CH2 filter threshold */ +#define TIM_C2FILT_THRESH_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_C2FILT_THRESH_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_C2FILT_THRESH_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_C2FILT_THRESH_3 ((uint32_t)0x08000000U) /* Bit 3 */ +#define TIM_C2FILT_THRESH_4 ((uint32_t)0x10000000U) /* Bit 4 */ +#define TIM_C2FILT_THRESH_5 ((uint32_t)0x20000000U) /* Bit 5 */ + +#define TIM_C2FILT_WSIZE ((uint32_t)0x007E0000U) /* CH2 filter window size */ +#define TIM_C2FILT_WSIZE_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define TIM_C2FILT_WSIZE_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define TIM_C2FILT_WSIZE_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define TIM_C2FILT_WSIZE_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define TIM_C2FILT_WSIZE_4 ((uint32_t)0x00200000U) /* Bit 4 */ +#define TIM_C2FILT_WSIZE_5 ((uint32_t)0x00400000U) /* Bit 5 */ + +#define TIM_C2FILT_FILTEN ((uint32_t)0x00010000U) +#define TIM_C2FILT_SFPSC ((uint32_t)0x0000FFFFU) + +/** Bit definition for TIM_C3FILT register **/ +#define TIM_C3FILT_THRESH ((uint32_t)0x3F000000U) /* CH3 filter threshold */ +#define TIM_C3FILT_THRESH_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_C3FILT_THRESH_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_C3FILT_THRESH_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_C3FILT_THRESH_3 ((uint32_t)0x08000000U) /* Bit 3 */ +#define TIM_C3FILT_THRESH_4 ((uint32_t)0x10000000U) /* Bit 4 */ +#define TIM_C3FILT_THRESH_5 ((uint32_t)0x20000000U) /* Bit 5 */ + +#define TIM_C3FILT_WSIZE ((uint32_t)0x007E0000U) /* CH3 filter window size */ +#define TIM_C3FILT_WSIZE_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define TIM_C3FILT_WSIZE_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define TIM_C3FILT_WSIZE_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define TIM_C3FILT_WSIZE_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define TIM_C3FILT_WSIZE_4 ((uint32_t)0x00200000U) /* Bit 4 */ +#define TIM_C3FILT_WSIZE_5 ((uint32_t)0x00400000U) /* Bit 5 */ + +#define TIM_C3FILT_FILTEN ((uint32_t)0x00010000U) +#define TIM_C3FILT_SFPSC ((uint32_t)0x0000FFFFU) + +/** Bit definition for TIM_C4FILT register **/ +#define TIM_C4FILT_THRESH ((uint32_t)0x3F000000U) /* CH4 filter threshold */ +#define TIM_C4FILT_THRESH_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_C4FILT_THRESH_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_C4FILT_THRESH_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_C4FILT_THRESH_3 ((uint32_t)0x08000000U) /* Bit 3 */ +#define TIM_C4FILT_THRESH_4 ((uint32_t)0x10000000U) /* Bit 4 */ +#define TIM_C4FILT_THRESH_5 ((uint32_t)0x20000000U) /* Bit 5 */ + +#define TIM_C4FILT_WSIZE ((uint32_t)0x007E0000U) /* CH4 filter window size */ +#define TIM_C4FILT_WSIZE_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define TIM_C4FILT_WSIZE_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define TIM_C4FILT_WSIZE_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define TIM_C4FILT_WSIZE_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define TIM_C4FILT_WSIZE_4 ((uint32_t)0x00200000U) /* Bit 4 */ +#define TIM_C4FILT_WSIZE_5 ((uint32_t)0x00400000U) /* Bit 5 */ + +#define TIM_C4FILT_FILTEN ((uint32_t)0x00010000U) +#define TIM_C4FILT_SFPSC ((uint32_t)0x0000FFFFU) + +/** Bit definition for TIM_FILTO register **/ +#define TIM_FILTO_C1FILTO ((uint32_t)0x00000001U) /* CH1 filter output state */ +#define TIM_FILTO_C2FILTO ((uint32_t)0x00000002U) /* CH2 filter output state */ +#define TIM_FILTO_C3FILTO ((uint32_t)0x00000004U) /* CH3 filter output state */ +#define TIM_FILTO_C4FILTO ((uint32_t)0x00000008U) /* CH4 filter output state */ + +/** Bit definition for TIM_INSEL register **/ +#define TIM_INSEL_TI1S ((uint32_t)0x0000000FU) /* TI1 signal selection */ +#define TIM_INSEL_TI1S_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define TIM_INSEL_TI1S_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define TIM_INSEL_TI1S_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define TIM_INSEL_TI1S_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +#define TIM_INSEL_TI2S ((uint32_t)0x000000F0U) /* TI2 signal selection */ +#define TIM_INSEL_TI2S_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define TIM_INSEL_TI2S_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define TIM_INSEL_TI2S_2 ((uint32_t)0x00000040U) /* Bit 2 */ +#define TIM_INSEL_TI2S_3 ((uint32_t)0x00000080U) /* Bit 3 */ + +#define TIM_INSEL_TI3S ((uint32_t)0x00000F00U) /* TI3 signal selection */ +#define TIM_INSEL_TI3S_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define TIM_INSEL_TI3S_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define TIM_INSEL_TI3S_2 ((uint32_t)0x00000400U) /* Bit 2 */ +#define TIM_INSEL_TI3S_3 ((uint32_t)0x00000800U) /* Bit 3 */ + +#define TIM_INSEL_TI4S ((uint32_t)0x0000F000U) /* TI4 signal selection */ +#define TIM_INSEL_TI4S_0 ((uint32_t)0x00001000U) /* Bit 0 */ +#define TIM_INSEL_TI4S_1 ((uint32_t)0x00002000U) /* Bit 1 */ +#define TIM_INSEL_TI4S_2 ((uint32_t)0x00004000U) /* Bit 2 */ +#define TIM_INSEL_TI4S_3 ((uint32_t)0x00008000U) /* Bit 3 */ + +#define TIM_INSEL_ETRS ((uint32_t)0x000F0000U) /* etr signal selection */ +#define TIM_INSEL_ETRS_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define TIM_INSEL_ETRS_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define TIM_INSEL_ETRS_2 ((uint32_t)0x00040000U) /* Bit 2 */ +#define TIM_INSEL_ETRS_3 ((uint32_t)0x00080000U) /* Bit 3 */ + +#define TIM_INSEL_ITRS ((uint32_t)0x00F00000U) /* itr signal selection */ +#define TIM_INSEL_ITRS_0 ((uint32_t)0x00100000U) /* Bit 0 */ +#define TIM_INSEL_ITRS_1 ((uint32_t)0x00200000U) /* Bit 1 */ +#define TIM_INSEL_ITRS_2 ((uint32_t)0x00400000U) /* Bit 2 */ +#define TIM_INSEL_ITRS_3 ((uint32_t)0x00800000U) /* Bit 3 */ + +#define TIM_INSEL_CLRS ((uint32_t)0x0F000000U) /* Ocrefclear signal selection */ +#define TIM_INSEL_CLRS_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_INSEL_CLRS_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_INSEL_CLRS_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_INSEL_CLRS_3 ((uint32_t)0x08000000U) /* Bit 3 */ + +/** Bit definition for TIM_AF1 register **/ +#define TIM_AF1_IOMBRKEN ((uint32_t)0x00000001U) /* Enable IOM as break1 input */ +#define TIM_AF1_COMP1BRKEN ((uint32_t)0x00000002U) /* Enable COMP1 as break1 input */ +#define TIM_AF1_COMP2BRKEN ((uint32_t)0x00000004U) /* Enable COMP2 as break1 input */ +#define TIM_AF1_COMP3BRKEN ((uint32_t)0x00000008U) /* Enable COMP3 as break1 input */ +#define TIM_AF1_COMP4BRKEN ((uint32_t)0x00000010U) /* Enable COMP4 as break1 input */ +#define TIM_AF1_DSMU0BRKEN ((uint32_t)0x01000000U) /* Enable DSMU0 as break1 input */ +#define TIM_AF1_DSMU1BRKEN ((uint32_t)0x02000000U) /* Enable DSMU1 as break1 input */ +#define TIM_AF1_DSMU2BRKEN ((uint32_t)0x04000000U) /* Enable DSMU2 as break1 input */ +#define TIM_AF1_DSMU3BRKEN ((uint32_t)0x08000000U) /* Enable DSMU3 as break1 input */ + +#define TIM_AF1_IOMBRKP ((uint32_t)0x00000200U) /* Select polarity of break1 input from IOM */ +#define TIM_AF1_COMP1BRKP ((uint32_t)0x00000400U) /* Select polarity of break1 input from COMP1 */ +#define TIM_AF1_COMP2BRKP ((uint32_t)0x00000800U) /* Select polarity of break1 input from COMP2 */ +#define TIM_AF1_COMP3BRKP ((uint32_t)0x00001000U) /* Select polarity of break1 input from COMP3 */ +#define TIM_AF1_COMP4BRKP ((uint32_t)0x00002000U) /* Select polarity of break1 input from COMP4 */ + +/** Bit definition for TIM_AF2 register **/ +#define TIM_AF2_IOMBRK2EN ((uint32_t)0x00000001U) /* Enable IOM as break2 input */ +#define TIM_AF2_COMP1BRK2EN ((uint32_t)0x00000002U) /* Enable COMP1 as break2 input */ +#define TIM_AF2_COMP2BRK2EN ((uint32_t)0x00000004U) /* Enable COMP2 as break2 input */ +#define TIM_AF2_COMP3BRK2EN ((uint32_t)0x00000008U) /* Enable COMP3 as break2 input */ +#define TIM_AF2_COMP4BRK2EN ((uint32_t)0x00000010U) /* Enable COMP4 as break2 input */ +#define TIM_AF2_DSMU0BRK2EN ((uint32_t)0x01000000U) /* Enable DSMU0 as break2 input */ +#define TIM_AF2_DSMU1BRK2EN ((uint32_t)0x02000000U) /* Enable DSMU1 as break2 input */ +#define TIM_AF2_DSMU2BRK2EN ((uint32_t)0x04000000U) /* Enable DSMU2 as break2 input */ +#define TIM_AF2_DSMU3BRK2EN ((uint32_t)0x08000000U) /* Enable DSMU3 as break2 input */ + + +#define TIM_AF2_IOMBRK2P ((uint32_t)0x00000200U) /* Select polarity of break2 input from IOM */ +#define TIM_AF2_COMP1BRK2P ((uint32_t)0x00000400U) /* Select polarity of break2 input from COMP1 */ +#define TIM_AF2_COMP2BRK2P ((uint32_t)0x00000800U) /* Select polarity of break2 input from COMP2 */ +#define TIM_AF2_COMP3BRK2P ((uint32_t)0x00001000U) /* Select polarity of break2 input from COMP3 */ +#define TIM_AF2_COMP4BRK2P ((uint32_t)0x00002000U) /* Select polarity of break2 input from COMP4 */ + +/** Bit definition for TIM_BKFR2 register **/ +#define TIM_BKFR2_THRESH ((uint32_t)0x3F000000U) /* Break2 filter threshold */ +#define TIM_BKFR2_THRESH_0 ((uint32_t)0x01000000U) /* Bit 0 */ +#define TIM_BKFR2_THRESH_1 ((uint32_t)0x02000000U) /* Bit 1 */ +#define TIM_BKFR2_THRESH_2 ((uint32_t)0x04000000U) /* Bit 2 */ +#define TIM_BKFR2_THRESH_3 ((uint32_t)0x08000000U) /* Bit 3 */ +#define TIM_BKFR2_THRESH_4 ((uint32_t)0x10000000U) /* Bit 4 */ +#define TIM_BKFR2_THRESH_5 ((uint32_t)0x20000000U) /* Bit 5 */ + +#define TIM_BKFR2_WSIZE ((uint32_t)0x007E0000U) /* Break2 filter window size */ +#define TIM_BKFR2_WSIZE_0 ((uint32_t)0x00020000U) /* Bit 0 */ +#define TIM_BKFR2_WSIZE_1 ((uint32_t)0x00040000U) /* Bit 1 */ +#define TIM_BKFR2_WSIZE_2 ((uint32_t)0x00080000U) /* Bit 2 */ +#define TIM_BKFR2_WSIZE_3 ((uint32_t)0x00100000U) /* Bit 3 */ +#define TIM_BKFR2_WSIZE_4 ((uint32_t)0x00200000U) /* Bit 4 */ +#define TIM_BKFR2_WSIZE_5 ((uint32_t)0x00400000U) /* Bit 5 */ + +#define TIM_BKFR2_FILTEN ((uint32_t)0x00010000U) +#define TIM_BKFR2_SFPSC ((uint32_t)0x0000FFFFU) + + + +/** Bit definition for TIM_DCTRL register **/ +#define TIM_DCTRL_DBADDR ((uint32_t)0x00003F00U) /* DBA[5:0] bits (DMA Base Address) */ +#define TIM_DCTRL_DBADDR_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define TIM_DCTRL_DBADDR_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define TIM_DCTRL_DBADDR_2 ((uint32_t)0x00000400U) /* Bit 2 */ +#define TIM_DCTRL_DBADDR_3 ((uint32_t)0x00000800U) /* Bit 3 */ +#define TIM_DCTRL_DBADDR_4 ((uint32_t)0x00001000U) /* Bit 4 */ +#define TIM_DCTRL_DBADDR_5 ((uint32_t)0x00002000U) /* Bit 5 */ + +#define TIM_DCTRL_DBLEN ((uint32_t)0x0000003FU) /* DBL[5:0] bits (DMA Burst Length) */ +#define TIM_DCTRL_DBLEN_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define TIM_DCTRL_DBLEN_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define TIM_DCTRL_DBLEN_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define TIM_DCTRL_DBLEN_3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define TIM_DCTRL_DBLEN_4 ((uint32_t)0x00000010U) /* Bit 4 */ +#define TIM_DCTRL_DBLEN_5 ((uint32_t)0x00000020U) /* Bit 5 */ + +/** Bit definition for TIM_DADDR register **/ +#define TIM_DADDR_BURST ((uint32_t)0xFFFFFFFFU) /* DMA register for burst accesses */ + +/*** LCDC ***/ + +/** Bit definition for LCDC_SYNCCTRL register **/ +#define LCDC_SYNCCTRL_VSH ((uint32_t)0x0000FFFFU) /* Vertical synchronization height */ +#define LCDC_SYNCCTRL_HSW ((uint32_t)0xFFFF0000U) /* Horizontal synchronization width */ + +/** Bit definition for LCDC_BPCTRL register **/ +#define LCDC_BPCTRL_AHBP ((uint32_t)0x0000FFFFU) /* Accumulated vertical back porch */ +#define LCDC_BPCTRL_AVBP ((uint32_t)0xFFFF0000U) /* Accumulated horizontal back porch */ + +/** Bit definition for LCDC_AWCTRL register **/ +#define LCDC_AWCTRL_AAH ((uint32_t)0x0000FFFFU) /* Accumulated active height */ +#define LCDC_AWCTRL_AAW ((uint32_t)0xFFFF0000U) /* Accumulated active width */ + +/** Bit definition for LCDC_TWCTRL register **/ +#define LCDC_TWCTRL_TOTALH ((uint32_t)0x0000FFFFU) /* Total height */ +#define LCDC_TWCTRL_TOTALW ((uint32_t)0xFFFF0000U) /* Total width */ + +/** Bit definition for LCDC_GCTRL register **/ +#define LCDC_GCTRL_EN ((uint32_t)0x00000001U) /* LCDC enable */ +#define LCDC_GCTRL_GCEN ((uint32_t)0x00000002U) /* Gamma correction enable */ +#define LCDC_GCTRL_DBW ((uint32_t)0x00000070U) /* Bit[6:4] Dither blue width */ +#define LCDC_GCTRL_DGW ((uint32_t)0x00000700U) /* Bit[10:8] Dither green width */ +#define LCDC_GCTRL_DRW ((uint32_t)0x00007000U) /* Bit[14:12] Dither red width */ +#define LCDC_GCTRL_DEN ((uint32_t)0x00010000U) /* Dither enable */ +#define LCDC_GCTRL_PCLKPOL ((uint32_t)0x10000000U) /* Pixel clock polarity */ +#define LCDC_GCTRL_DEPOL ((uint32_t)0x20000000U) /* Data enable polarity */ +#define LCDC_GCTRL_VSPOL ((uint32_t)0x40000000U) /* Vertical polarity */ +#define LCDC_GCTRL_HSPOL ((uint32_t)0x80000000U) /* Horizontal polarity */ + +/** Bit definition for LCDC_SRCTRL register **/ +#define LCDC_SRCTRL_IMR ((uint32_t)0x00000001U) /* Immediate reload */ +#define LCDC_SRCTRL_VBR ((uint32_t)0x00000002U) /* Vertical blanking reload */ + +/** Bit definition for LCDC_BGCCTRL register **/ +#define LCDC_BGCCTRL_BCB ((uint32_t)0x000000FFU) /* Background blue value */ +#define LCDC_BGCCTRL_BCG ((uint32_t)0x0000FF00U) /* Background green value */ +#define LCDC_BGCCTRL_BCR ((uint32_t)0x00FF0000U) /* Background red value */ + +/** Bit definition for LCDC_INTEN register **/ +#define LCDC_INTEN_LIEN ((uint32_t)0x00000001U) /* Line interrupt enable */ +#define LCDC_INTEN_FUIEN ((uint32_t)0x00000002U) /* FIFO underrun interrupt enable */ +#define LCDC_INTEN_BEIEN ((uint32_t)0x00000004U) /* BUS error interrupt enable */ +#define LCDC_INTEN_RRIEN ((uint32_t)0x00000008U) /* Register reload interrupt enable */ +#define LCDC_INTEN_STNSIGIEN ((uint32_t)0x00000010U) /* Slave timing no signal interrupt enable */ +#define LCDC_INTEN_STNSYNCIEN ((uint32_t)0x00000020U) /* Slave timing not in sync interrupt enable */ +#define LCDC_INTEN_FUKIEN ((uint32_t)0x00000040U) /* FIFO underrun killing interrupt enable */ +#define LCDC_INTEN_CRCIEN ((uint32_t)0x00000080U) /* CRC interrupt enable */ +#define LCDC_INTEN_RFEIEN ((uint32_t)0x00000100U) /* Rotation FIFO error interrupt enable */ + +/** Bit definition for LCDC_INTSTS register **/ +#define LCDC_INTSTS_LIF ((uint32_t)0x00000001U) /* Line interrupt flag */ +#define LCDC_INTSTS_FUIF ((uint32_t)0x00000002U) /* FIFO underrun interrupt flag */ +#define LCDC_INTSTS_BEIF ((uint32_t)0x00000004U) /* BUS error interrupt flag */ +#define LCDC_INTSTS_RRIF ((uint32_t)0x00000008U) /* Register reload interrupt flag */ +#define LCDC_INTSTS_STNSIGIF ((uint32_t)0x00000010U) /* Slave timing no signal interrupt flag */ +#define LCDC_INTSTS_STNSYNCIF ((uint32_t)0x00000020U) /* Slave timing not in sync interrupt flag */ +#define LCDC_INTSTS_FUKIF ((uint32_t)0x00000040U) /* FIFO underrun killing interrupt flag */ +#define LCDC_INTSTS_CRCIF ((uint32_t)0x00000080U) /* CRC interrupt flag */ +#define LCDC_INTSTS_RFEIF ((uint32_t)0x00000100U) /* Rotation FIFO error interrupt flag */ + +/** Bit definition for LCDC_INTCLR register **/ +#define LCDC_INTCLR_LICLR ((uint32_t)0x00000001U) /* Line interrupt flag clear */ +#define LCDC_INTCLR_FUICLR ((uint32_t)0x00000002U) /* FIFO underrun interrupt flag clear */ +#define LCDC_INTCLR_BEICLR ((uint32_t)0x00000004U) /* BUS error interrupt flag clear */ +#define LCDC_INTCLR_RRICLR ((uint32_t)0x00000008U) /* Register reload interrupt flag clear */ +#define LCDC_INTCLR_STNSIGICLR ((uint32_t)0x00000010U) /* Slave timing no signal interrupt flag clear */ +#define LCDC_INTCLR_STNSYNCICLR ((uint32_t)0x00000020U) /* Slave timing not in sync interrupt flag clear */ +#define LCDC_INTCLR_FUKICLR ((uint32_t)0x00000040U) /* FIFO underrun killing interrupt flag clear */ +#define LCDC_INTCLR_CRCICLR ((uint32_t)0x00000080U) /* CRC interrupt flag clear */ +#define LCDC_INTCLR_RFEICLR ((uint32_t)0x00000100U) /* Rotation FIFO error interrupt flag clear */ + +/** Bit definition for LCDC_LINTPCTRL register **/ +#define LCDC_LINTPCTRL_LINTP ((uint32_t)0x0000FFFFU) /* Line interrupt position */ + +/** Bit definition for LCDC_CPSTS register **/ +#define LCDC_CPSTS_CYPOS ((uint32_t)0x0000FFFFU) /* Current Y position */ +#define LCDC_CPSTS_CXPOS ((uint32_t)0xFFFF0000U) /* Current X position */ + +/** Bit definition for LCDC_CDSTS register **/ +#define LCDC_CDSTS_VBS ((uint32_t)0x00000001U) /* Vertical blanking status */ +#define LCDC_CDSTS_HBS ((uint32_t)0x00000002U) /* Horizontal blanking status */ +#define LCDC_CDSTS_VSYNCS ((uint32_t)0x00000004U) /* Vertical synchronization status */ +#define LCDC_CDSTS_HSYNCS ((uint32_t)0x00000008U) /* Horizontal synchronization status */ + +/** Bit definition for LCDC_EXTDCTRL register **/ +#define LCDC_EXTDCTRL_DVEN ((uint32_t)0x00100000U) /* Dual view enable */ +#define LCDC_EXTDCTRL_SPMEN ((uint32_t)0x00200000U) /* Sub-pixel mixing enable */ +#define LCDC_EXTDCTRL_PCLKHEEN ((uint32_t)0x00400000U) /* Pixel clock half even enable */ +#define LCDC_EXTDCTRL_PCLKHOEN ((uint32_t)0x00800000U) /* Pixel clock half odd enable */ +#define LCDC_EXTDCTRL_PCLKHES ((uint32_t)0x01000000U) /* Pixel clock half odd/even active edge shift */ + +/** Bit definition for LCDC_LSRCTRL register **/ +#define LCDC_LSRCTRL_IMR ((uint32_t)0x00000001U) /* Layer reload immediate */ +#define LCDC_LSRCTRL_VBR ((uint32_t)0x00000002U) /* Layer reload vertical blanking */ +#define LCDC_LSRCTRL_MGR ((uint32_t)0x00000004U) /* Layer reload mask global */ + +/** Bit definition for LCDC_LCTRL register **/ +#define LCDC_LCTRL_LEN ((uint32_t)0x00000001U) /* Layer enable */ +#define LCDC_LCTRL_CKEN ((uint32_t)0x00000002U) /* Color key enable */ +#define LCDC_LCTRL_VDEN ((uint32_t)0x00000004U) /* Vertical duplication enable */ +#define LCDC_LCTRL_HDEN ((uint32_t)0x00000008U) /* Horizontal duplication enable */ +#define LCDC_LCTRL_CLUTEN ((uint32_t)0x00000010U) /* CLUT enable */ +#define LCDC_LCTRL_CKREN ((uint32_t)0x00000020U) /* Color key replace enable */ + +#define LCDC_LCTRL_DVMD ((uint32_t)0x000000C0U) /* Dual-view insertion mode */ +#define LCDC_LCTRL_DVMD_0 ((uint32_t)0x00000040U) /* Bit 0 */ +#define LCDC_LCTRL_DVMD_1 ((uint32_t)0x00000080U) /* Bit 1 */ + +#define LCDC_LCTRL_HMEN ((uint32_t)0x00000100U) /* Horizontal mirroring enable */ +#define LCDC_LCTRL_DCBEN ((uint32_t)0x00000200U) /* Default color blending enable */ +#define LCDC_LCTRL_SEN ((uint32_t)0x00000400U) /* Scaler enable */ + +/** Bit definition for LCDC_WHCTRL register **/ +#define LCDC_WHPCTRL_WHSTPOS ((uint32_t)0x0000FFFFU) /* Window horizontal start position */ +#define LCDC_WHPCTRL_WHSPPOS ((uint32_t)0xFFFF0000U) /* Window horizontal stop position */ + +/** Bit definition for LCDC_WVCTRL register **/ +#define LCDC_WVPCTRL_WVSTPOS ((uint32_t)0x0000FFFFU) /* Window vertical start position */ +#define LCDC_WVPCTRL_WVSPPOS ((uint32_t)0xFFFF0000U) /* Window vertical stop position */ + +/** Bit definition for LCDC_CKCTRL register **/ +#define LCDC_CKCTRL_CKB ((uint32_t)0x000000FFU) /* Color key blue value */ +#define LCDC_CKCTRL_CKG ((uint32_t)0x0000FF00U) /* Color key green value */ +#define LCDC_CKCTRL_CKR ((uint32_t)0x00FF0000U) /* Color key red value */ + +/** Bit definition for LCDC_PFCTRL register **/ +#define LCDC_PFCTRL_PF ((uint32_t)0x00000007U) /* Pixel format */ +#define LCDC_PFCTRL_PF_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define LCDC_PFCTRL_PF_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define LCDC_PFCTRL_PF_2 ((uint32_t)0x00000004U) /* Bit 2 */ + +/** Bit definition for LCDC_CACTRL register **/ +#define LCDC_CACTRL_CA ((uint32_t)0x000000FFU) /* Constant alpha */ + +/** Bit definition for LCDC_DCCTRL register **/ +#define LCDC_DCCTRL_DCB ((uint32_t)0x000000FFU) /* Default color blue */ +#define LCDC_DCCTRL_DCG ((uint32_t)0x0000FF00U) /* Default color green */ +#define LCDC_DCCTRL_DCR ((uint32_t)0x00FF0000U) /* Default color red */ +#define LCDC_DCCTRL_DCA ((uint32_t)0xFF000000U) /* Default color alpha */ + +/** Bit definition for LCDC_BFCTRL register **/ +#define LCDC_BFCTRL_BF2 ((uint32_t)0x00000007U) /* Blending factor 2 */ +#define LCDC_BFCTRL_BF2_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define LCDC_BFCTRL_BF2_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define LCDC_BFCTRL_BF2_2 ((uint32_t)0x00000004U) /* Bit 2 */ + +#define LCDC_BFCTRL_BF1 ((uint32_t)0x00000700U) /* Blending factor 2 */ +#define LCDC_BFCTRL_BF1_0 ((uint32_t)0x00000100U) /* Bit 0 */ +#define LCDC_BFCTRL_BF1_1 ((uint32_t)0x00000200U) /* Bit 1 */ +#define LCDC_BFCTRL_BF1_2 ((uint32_t)0x00000400U) /* Bit 2 */ + +#define LCDC_BFCTRL_LBOP ((uint32_t)0x000F0000U) /* Layer blending order position */ +#define LCDC_BFCTRL_LBOP_0 ((uint32_t)0x00010000U) /* Bit 0 */ +#define LCDC_BFCTRL_LBOP_1 ((uint32_t)0x00020000U) /* Bit 1 */ +#define LCDC_BFCTRL_LBOP_2 ((uint32_t)0x00040000U) /* Bit 2 */ +#define LCDC_BFCTRL_LBOP_3 ((uint32_t)0x00080000U) /* Bit 3 */ + +/** Bit definition for LCDC_FBBCTRL register **/ +#define LCDC_FBBCTRL_NWB ((uint32_t)0x000000FFU) /* Number of words per burst */ + +/** Bit definition for LCDC_AFBCTRL register **/ +#define LCDC_AFBCTRL_APEN ((uint32_t)0x00000001U) /* Alpha plane enable */ +#define LCDC_AFBCTRL_VDEN ((uint32_t)0x00000002U) /* Vertical duplication enable */ +#define LCDC_AFBCTRL_HDEN ((uint32_t)0x00000004U) /* Horizontal duplication enable */ +#define LCDC_AFBCTRL_YUVEN ((uint32_t)0x00000008U) /* YUV conversion enable */ + +#define LCDC_AFBCTRL_YUVMD ((uint32_t)0x00000030U) /* YUV conversion mode */ +#define LCDC_AFBCTRL_YUVMD_0 ((uint32_t)0x00000010U) /* Bit 0 */ +#define LCDC_AFBCTRL_YUVMD_1 ((uint32_t)0x00000020U) /* Bit 1 */ +#define LCDC_AFBCTRL_YUVMD_2 ((uint32_t)0x00000040U) /* Bit 2 */ + +#define LCDC_AFBCTRL_YUVIMDO ((uint32_t)0x000001C0U) /* YUV interleaved mode order */ +#define LCDC_AFBCTRL_YHEN ((uint32_t)0x00000200U) /* Y headroom enable */ + +/** Bit definition for LCDC_CFBADDR register **/ +#define LCDC_CFBADDR_CFBADDR ((uint32_t)0xFFFFFFFFU) /* Color frame buffer start address */ + +/** Bit definition for LCDC_CFBLEN register **/ +#define LCDC_CFBLEN_CFBLLEN ((uint32_t)0x0000FFFFU) /* Color frame buffer line length */ +#define LCDC_CFBLEN_CFBP ((uint32_t)0xFFFF0000U) /* Color frame buffer pitch in bytes */ + +/** Bit definition for LCDC_CFBLNUM register **/ +#define LCDC_CFBLNUM_CFBLNUM ((uint32_t)0x0000FFFFU) /* Color frame buffer line number */ + +/** Bit definition for LCDC_AFBADDR0 register **/ +#define LCDC_AFBADDR0_AFBADDR0 ((uint32_t)0xFFFFFFFFU) /* Auxiliary 0 frame buffer start address */ + +/** Bit definition for LCDC_AFBADDR1 register **/ +#define LCDC_AFBADDR0_AFBADDR1 ((uint32_t)0xFFFFFFFFU) /* Auxiliary 1 frame buffer start address */ + +/** Bit definition for LCDC_AFBLEN register **/ +#define LCDC_AFBLEN_AFBLLEN ((uint32_t)0x0000FFFFU) /* Auxiliary frame buffer line length */ +#define LCDC_AFBLEN_AFBP ((uint32_t)0xFFFF0000U) /* Auxiliary frame buffer pitch in bytes */ + +/** Bit definition for LCDC_AFBLNUM register **/ +#define LCDC_AFBLNUM_AFBLNUM ((uint32_t)0x0000FFFFU) /* Auxiliary frame buffer line number */ + +/** Bit definition for LCDC_CLUTWR register **/ +#define LCDC_CLUTWR_CLUTB ((uint32_t)0x000000FFU) /* CLUT blue value */ +#define LCDC_CLUTWR_CLUTG ((uint32_t)0x0000FF00U) /* CLUT green value */ +#define LCDC_CLUTWR_CLUTR ((uint32_t)0x00FF0000U) /* CLUT red value */ +#define LCDC_CLUTWR_CLUTADDR ((uint32_t)0xFF000000U) /* CLUT address */ + +/** Bit definition for LCDC_SINS register **/ +#define LCDC_SINS_SINW ((uint32_t)0x00000FFFU) /* Scaler input width */ +#define LCDC_SINS_SINH ((uint32_t)0x0FFF0000U) /* Scaler input height */ + +/** Bit definition for LCDC_SOUTS register **/ +#define LCDC_SOUTS_SOUTW ((uint32_t)0x00000FFFU) /* Scaler output width */ +#define LCDC_SOUTS_SOUTH ((uint32_t)0x0FFF0000U) /* Scaler output height */ + +/** Bit definition for LCDC_VSF register **/ +#define LCDC_VSF_VSF ((uint32_t)0x0000FFFFU) /* Vertical scaling factor */ + +/** Bit definition for LCDC_VSP register **/ +#define LCDC_VSP_VSP ((uint32_t)0x0000FFFFU) /* Vertical scaling phase */ + +/** Bit definition for LCDC_HSF register **/ +#define LCDC_HSF_HSF ((uint32_t)0x0000FFFFU) /* Horizontal scaling factor */ + +/** Bit definition for LCDC_HSP register **/ +#define LCDC_HSP_HSP ((uint32_t)0x0000FFFFU) /* Horizontal scaling phase */ + +/** Bit definition for LCDC_YUVS1 register **/ +#define LCDC_YUVS1_RVCS ((uint32_t)0x000003FFU) /* Red Cr(V) scale */ +#define LCDC_YUVS1_BUCS ((uint32_t)0x03FF0000U) /* Blue Cb(U) scale */ + +/** Bit definition for LCDC_YUVS2 register **/ +#define LCDC_YUVS2_GVCS ((uint32_t)0x000003FFU) /* Green Cr(V) scale */ +#define LCDC_YUVS2_GUCS ((uint32_t)0x03FF0000U) /* Green Cb(U) scale */ + +/** Bit definition for LCDC_FCF1 register **/ +#define LCDC_FCF1_ASB ((uint32_t)0x0000001FU) /* Alpha start bit */ +#define LCDC_FCF1_ALENB ((uint32_t)0x000001E0U) /* Alpha length bit */ +#define LCDC_FCF1_RSB ((uint32_t)0x00003E00U) /* Red start bit */ +#define LCDC_FCF1_RLENB ((uint32_t)0x0003C000U) /* Red length bit */ + +/** Bit definition for LCDC_FCF2 register **/ +#define LCDC_FCF2_GSB ((uint32_t)0x0000001FU) /* Green start bit */ +#define LCDC_FCF2_GLENB ((uint32_t)0x000001E0U) /* Green length bit */ +#define LCDC_FCF2_BSB ((uint32_t)0x00003E00U) /* Blue start bit */ +#define LCDC_FCF2_BLENB ((uint32_t)0x0003C000U) /* Blue length bit */ +#define LCDC_FCF2_BPP ((uint32_t)0x001C0000U) /* Bytes per pixel */ + +/**** JPEG controller ****/ + +/*** JPEG CTRL controller ***/ +/** Bit definition for JPEG_CTRL register **/ +#define JPEG_CTRL_TYPE ((uint32_t)0x00000001U) /* Choose JPEG operation */ +#define JPEG_CTRL_SWAP ((uint32_t)0x00000002U) /* Swap Data for YCbCr 4:2:2 Format in BRC bit */ + + +/*** JPEG BRC controller ***/ +/** Bit definition for JPEGBRC_INIT register **/ +#define JPEGBRC_INIT_INITF ((uint32_t)0x00000010U) /* Initialization completion flag bit */ +#define JPEGBRC_INIT_BUSY ((uint32_t)0x00000002U) /* busy bit */ +#define JPEGBRC_INIT_INIT ((uint32_t)0x00000001U) /* init bit */ + +/** Bit definition for JPEGBRC_EN register **/ +#define JPEGBRC_EN_EN ((uint32_t)0x00000001U) /* Enables stream processing of the core */ + +/** Bit definition for JPEGBRC_BUFBADDR register **/ +#define JPEGBRC_BUFBADDR_ADDR ((uint32_t)0xFFFFFFFFU) /* AXI buffer base address */ +#define JPEGBRC_BUFBADDR_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGBRC_BUFBADDR_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGBRC_BUFBADDR_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGBRC_BUFBADDR_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGBRC_BUFBADDR_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGBRC_BUFBADDR_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGBRC_BUFBADDR_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGBRC_BUFBADDR_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGBRC_BUFBADDR_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGBRC_BUFBADDR_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGBRC_BUFBADDR_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGBRC_BUFBADDR_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGBRC_BUFBADDR_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGBRC_BUFBADDR_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGBRC_BUFBADDR_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGBRC_BUFBADDR_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGBRC_BUFBADDR_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGBRC_BUFBADDR_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGBRC_BUFBADDR_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGBRC_BUFBADDR_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGBRC_BUFBADDR_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGBRC_BUFBADDR_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGBRC_BUFBADDR_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGBRC_BUFBADDR_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGBRC_BUFBADDR_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGBRC_BUFBADDR_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGBRC_BUFBADDR_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGBRC_BUFBADDR_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGBRC_BUFBADDR_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGBRC_BUFBADDR_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGBRC_BUFBADDR_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGBRC_BUFBADDR_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGBRC_BUFSIZE register **/ +#define JPEGBRC_BUFSIZE_SIZE ((uint32_t)0x0000FFFFU) /* AXI buffer size */ +#define JPEGBRC_BUFSIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGBRC_BUFSIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGBRC_BUFSIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGBRC_BUFSIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGBRC_BUFSIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGBRC_BUFSIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGBRC_BUFSIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGBRC_BUFSIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGBRC_BUFSIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGBRC_BUFSIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGBRC_BUFSIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGBRC_BUFSIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGBRC_BUFSIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGBRC_BUFSIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGBRC_BUFSIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGBRC_BUFSIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGBRC_USMODE register **/ +#define JPEGBRC_USMODE_MODE ((uint32_t)0x00000003U) /* Up sampling mode */ +#define JPEGBRC_USMODE_MODE_0 ((uint32_t)0x00000001U) /* bit1 */ +#define JPEGBRC_USMODE_MODE_1 ((uint32_t)0x00000002U) /* bit0 */ + + + +/*** JPEG RBC controller ***/ +/** Bit definition for JPEGRBC_INIT register **/ +#define JPEGRBC_INIT_INITF ((uint32_t)0x00000010U) /* Init complete flag */ +#define JPEGRBC_INIT_INIT ((uint32_t)0x00000001U) /* Init bit */ + +/** Bit definition for JPEGRBC_EN register **/ +#define JPEGRBC_EN_EN ((uint32_t)0x00000001U) /* Enables stream processing of the core */ + +/** Bit definition for JPEGRBC_SWITCH register **/ +#define JPEGRBC_SWITCH_SWITCH ((uint32_t)0x00000001U) /* Switch input sample order */ + +/** Bit definition for JPEGRBC_FRMW register **/ +#define JPEGRBC_FRMW_WIDTH ((uint32_t)0x0000FFFFU) /* Frame width */ +#define JPEGRBC_FRMW_WIDTH_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_FRMW_WIDTH_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_FRMW_WIDTH_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_FRMW_WIDTH_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_FRMW_WIDTH_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_FRMW_WIDTH_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_FRMW_WIDTH_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_FRMW_WIDTH_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_FRMW_WIDTH_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_FRMW_WIDTH_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_FRMW_WIDTH_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_FRMW_WIDTH_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_FRMW_WIDTH_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_FRMW_WIDTH_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_FRMW_WIDTH_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_FRMW_WIDTH_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGRBC_FRMH register **/ +#define JPEGRBC_FRMH_HEIGHT ((uint32_t)0x0000FFFFU) /* Frame height */ +#define JPEGRBC_FRMH_HEIGHT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_FRMH_HEIGHT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_FRMH_HEIGHT_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_FRMH_HEIGHT_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_FRMH_HEIGHT_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_FRMH_HEIGHT_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_FRMH_HEIGHT_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_FRMH_HEIGHT_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_FRMH_HEIGHT_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_FRMH_HEIGHT_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_FRMH_HEIGHT_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_FRMH_HEIGHT_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_FRMH_HEIGHT_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_FRMH_HEIGHT_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_FRMH_HEIGHT_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_FRMH_HEIGHT_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGRBC_PFORM register **/ +#define JPEGRBC_PFORM_FORMAT ((uint32_t)0x00000007U) /* Pixel format */ +#define JPEGRBC_PFORM_FORMAT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_PFORM_FORMAT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_PFORM_FORMAT_2 ((uint32_t)0x00000004U) /* Bit2*/ + +/** Bit definition for JPEGRBC_CNAME register **/ +#define JPEGRBC_CNAME_C2 ((uint32_t)0x00FF0000U) /* Name of component 2 */ +#define JPEGRBC_CNAME_C2_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_CNAME_C2_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_CNAME_C2_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_CNAME_C2_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_CNAME_C2_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_CNAME_C2_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_CNAME_C2_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_CNAME_C2_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_CNAME_C1 ((uint32_t)0x0000FF00U) /* Name of component 1 */ +#define JPEGRBC_CNAME_C1_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_CNAME_C1_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_CNAME_C1_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_CNAME_C1_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_CNAME_C1_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_CNAME_C1_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_CNAME_C1_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_CNAME_C1_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_CNAME_C0 ((uint32_t)0x000000FFU) /* Name of component 0 */ +#define JPEGRBC_CNAME_C0_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_CNAME_C0_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_CNAME_C0_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_CNAME_C0_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_CNAME_C0_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_CNAME_C0_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_CNAME_C0_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_CNAME_C0_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGRBC_C0SADD register **/ +#define JPEGRBC_C0SADD_ADDR ((uint32_t)0xFFFFFFFFU) /* Component 0 start address */ +#define JPEGRBC_C0SADD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_C0SADD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_C0SADD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_C0SADD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_C0SADD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_C0SADD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_C0SADD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_C0SADD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_C0SADD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_C0SADD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_C0SADD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_C0SADD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_C0SADD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_C0SADD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_C0SADD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_C0SADD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_C0SADD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_C0SADD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_C0SADD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_C0SADD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_C0SADD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_C0SADD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_C0SADD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_C0SADD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_C0SADD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGRBC_C0SADD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGRBC_C0SADD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGRBC_C0SADD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGRBC_C0SADD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGRBC_C0SADD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGRBC_C0SADD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGRBC_C0SADD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGRBC_C0EADD register **/ +#define JPEGRBC_C0EADD_ADDR ((uint32_t)0x000003FFU) /* Component 0 end address */ +#define JPEGRBC_C0EADD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_C0EADD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_C0EADD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_C0EADD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_C0EADD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_C0EADD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_C0EADD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_C0EADD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_C0EADD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_C0EADD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ + +/** Bit definition for JPEGRBC_BPS0 register **/ +#define JPEGRBC_BPS0_NUM ((uint32_t)0x0FFFFFFFU) /* Blocks per Scan 0 */ +#define JPEGRBC_BPS0_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_BPS0_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_BPS0_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_BPS0_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_BPS0_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_BPS0_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_BPS0_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_BPS0_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_BPS0_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_BPS0_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_BPS0_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_BPS0_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_BPS0_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_BPS0_NUM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_BPS0_NUM_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_BPS0_NUM_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_BPS0_NUM_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_BPS0_NUM_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_BPS0_NUM_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_BPS0_NUM_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_BPS0_NUM_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_BPS0_NUM_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_BPS0_NUM_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_BPS0_NUM_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_BPS0_NUM_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGRBC_BPS0_NUM_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGRBC_BPS0_NUM_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGRBC_BPS0_NUM_27 ((uint32_t)0x08000000U) /* Bit27*/ + +/** Bit definition for JPEGRBC_BPS12 register **/ +#define JPEGRBC_BPS12_NUM ((uint32_t)0x0FFFFFFFU) /* Blocks per Scan 1,2 */ +#define JPEGRBC_BPS12_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_BPS12_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_BPS12_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_BPS12_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_BPS12_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_BPS12_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_BPS12_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_BPS12_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_BPS12_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_BPS12_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_BPS12_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_BPS12_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_BPS12_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_BPS12_NUM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_BPS12_NUM_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_BPS12_NUM_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_BPS12_NUM_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_BPS12_NUM_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_BPS12_NUM_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_BPS12_NUM_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_BPS12_NUM_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_BPS12_NUM_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_BPS12_NUM_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_BPS12_NUM_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_BPS12_NUM_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGRBC_BPS12_NUM_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGRBC_BPS12_NUM_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGRBC_BPS12_NUM_27 ((uint32_t)0x08000000U) /* Bit27*/ + +/** Bit definition for JPEGRBC_ROWS0 register **/ +#define JPEGRBC_ROWS0_NUM ((uint32_t)0x00001FFFU) /* MCU rows Scan 0 */ +#define JPEGRBC_ROWS0_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_ROWS0_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_ROWS0_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_ROWS0_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_ROWS0_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_ROWS0_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_ROWS0_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_ROWS0_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_ROWS0_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_ROWS0_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_ROWS0_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_ROWS0_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_ROWS0_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ + +/** Bit definition for JPEGRBC_ROWS12 register **/ +#define JPEGRBC_ROWS12_NUM ((uint32_t)0x00001FFFU) /* MCU rows Scan 1,2 */ +#define JPEGRBC_ROWS12_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_ROWS12_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_ROWS12_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_ROWS12_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_ROWS12_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_ROWS12_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_ROWS12_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_ROWS12_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_ROWS12_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_ROWS12_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_ROWS12_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_ROWS12_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_ROWS12_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ + +/** Bit definition for JPEGRBC_HHALF register **/ +#define JPEGRBC_HHALF_HHALF ((uint32_t)0x00007FFFU) /* Frame height half */ +#define JPEGRBC_HHALF_HHALF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_HHALF_HHALF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_HHALF_HHALF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_HHALF_HHALF_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_HHALF_HHALF_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_HHALF_HHALF_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_HHALF_HHALF_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_HHALF_HHALF_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_HHALF_HHALF_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_HHALF_HHALF_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_HHALF_HHALF_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_HHALF_HHALF_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_HHALF_HHALF_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_HHALF_HHALF_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_HHALF_HHALF_14 ((uint32_t)0x00004000U) /* Bit14*/ + +/** Bit definition for JPEGRBC_BLSS0 register **/ +#define JPEGRBC_BLSS0_SIZE ((uint32_t)0x0003FFFFU) /* Block line stride Scan 0 */ +#define JPEGRBC_BLSS0_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_BLSS0_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_BLSS0_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_BLSS0_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_BLSS0_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_BLSS0_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_BLSS0_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_BLSS0_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_BLSS0_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_BLSS0_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_BLSS0_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_BLSS0_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_BLSS0_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_BLSS0_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_BLSS0_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_BLSS0_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_BLSS0_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_BLSS0_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ + +/** Bit definition for JPEGRBC_BLSS12 register **/ +#define JPEGRBC_BLSS12_SIZE ((uint32_t)0x0003FFFFU) /* Block line stride Scan 1,2 */ +#define JPEGRBC_BLSS12_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_BLSS12_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_BLSS12_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_BLSS12_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_BLSS12_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_BLSS12_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_BLSS12_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_BLSS12_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_BLSS12_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_BLSS12_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_BLSS12_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_BLSS12_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_BLSS12_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_BLSS12_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_BLSS12_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_BLSS12_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_BLSS12_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_BLSS12_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ + +/** Bit definition for JPEGRBC_BPRS0 register **/ +#define JPEGRBC_BPRS0_NUM ((uint32_t)0x00007FFFU) /* Blocks per MCU row Scan 0 */ +#define JPEGRBC_BPRS0_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_BPRS0_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_BPRS0_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_BPRS0_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_BPRS0_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_BPRS0_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_BPRS0_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_BPRS0_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_BPRS0_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_BPRS0_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_BPRS0_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_BPRS0_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_BPRS0_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_BPRS0_NUM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_BPRS0_NUM_14 ((uint32_t)0x00004000U) /* Bit14*/ + +/** Bit definition for JPEGRBC_BPRS12 register **/ +#define JPEGRBC_BPRS12_NUM ((uint32_t)0x00007FFFU) /* Blocks per MCU row Scan 1,2 */ +#define JPEGRBC_BPRS12_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_BPRS12_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_BPRS12_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_BPRS12_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_BPRS12_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_BPRS12_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_BPRS12_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_BPRS12_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_BPRS12_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_BPRS12_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_BPRS12_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_BPRS12_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_BPRS12_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_BPRS12_NUM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_BPRS12_NUM_14 ((uint32_t)0x00004000U) /* Bit14*/ + +/** Bit definition for JPEGRBC_MAXW register **/ +#define JPEGRBC_MAXW_WIDTH ((uint32_t)0xFFFFFFFFU) /* Maximum supported width */ +#define JPEGRBC_MAXW_WIDTH_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_MAXW_WIDTH_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_MAXW_WIDTH_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_MAXW_WIDTH_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_MAXW_WIDTH_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_MAXW_WIDTH_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_MAXW_WIDTH_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_MAXW_WIDTH_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_MAXW_WIDTH_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_MAXW_WIDTH_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_MAXW_WIDTH_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_MAXW_WIDTH_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_MAXW_WIDTH_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_MAXW_WIDTH_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_MAXW_WIDTH_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_MAXW_WIDTH_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_MAXW_WIDTH_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_MAXW_WIDTH_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_MAXW_WIDTH_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_MAXW_WIDTH_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_MAXW_WIDTH_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_MAXW_WIDTH_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_MAXW_WIDTH_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_MAXW_WIDTH_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_MAXW_WIDTH_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGRBC_MAXW_WIDTH_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGRBC_MAXW_WIDTH_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGRBC_MAXW_WIDTH_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGRBC_MAXW_WIDTH_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGRBC_MAXW_WIDTH_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGRBC_MAXW_WIDTH_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGRBC_MAXW_WIDTH_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGRBC_MAXH register **/ +#define JPEGRBC_MAXH_HEIGHT ((uint32_t)0xFFFFFFFFU) /* Maximum supported height */ +#define JPEGRBC_MAXH_HEIGHT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_MAXH_HEIGHT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_MAXH_HEIGHT_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_MAXH_HEIGHT_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_MAXH_HEIGHT_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_MAXH_HEIGHT_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_MAXH_HEIGHT_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_MAXH_HEIGHT_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_MAXH_HEIGHT_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_MAXH_HEIGHT_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_MAXH_HEIGHT_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_MAXH_HEIGHT_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_MAXH_HEIGHT_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_MAXH_HEIGHT_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_MAXH_HEIGHT_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_MAXH_HEIGHT_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_MAXH_HEIGHT_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_MAXH_HEIGHT_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_MAXH_HEIGHT_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_MAXH_HEIGHT_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_MAXH_HEIGHT_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_MAXH_HEIGHT_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_MAXH_HEIGHT_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_MAXH_HEIGHT_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_MAXH_HEIGHT_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGRBC_MAXH_HEIGHT_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGRBC_MAXH_HEIGHT_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGRBC_MAXH_HEIGHT_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGRBC_MAXH_HEIGHT_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGRBC_MAXH_HEIGHT_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGRBC_MAXH_HEIGHT_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGRBC_MAXH_HEIGHT_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGRBC_MBSIZE register **/ +#define JPEGRBC_MBSIZE_SIZE ((uint32_t)0xFFFFFFFFU) /* Maximum supported buffer size */ +#define JPEGRBC_MBSIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGRBC_MBSIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGRBC_MBSIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGRBC_MBSIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGRBC_MBSIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGRBC_MBSIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGRBC_MBSIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGRBC_MBSIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGRBC_MBSIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGRBC_MBSIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGRBC_MBSIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGRBC_MBSIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGRBC_MBSIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGRBC_MBSIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGRBC_MBSIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGRBC_MBSIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGRBC_MBSIZE_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGRBC_MBSIZE_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGRBC_MBSIZE_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGRBC_MBSIZE_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGRBC_MBSIZE_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGRBC_MBSIZE_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGRBC_MBSIZE_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGRBC_MBSIZE_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGRBC_MBSIZE_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGRBC_MBSIZE_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGRBC_MBSIZE_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGRBC_MBSIZE_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGRBC_MBSIZE_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGRBC_MBSIZE_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGRBC_MBSIZE_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGRBC_MBSIZE_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + + +/*** JPEG SGDMA(P2H/H2P) controller ***/ +/** Bit definition for JPEGDMA_CTRL register **/ +#define JPEGDMA_CTRL_HARDRST ((uint32_t)0x80000000U) /* Software hard reset */ +#define JPEGDMA_CTRL_SGLTRST ((uint32_t)0x00000200U) /* Reset the TAIL of the SGList to zero */ +#define JPEGDMA_CTRL_MMODE ((uint32_t)0x000001C0U) /* Descriptor Memory Mode settings */ +#define JPEGDMA_CTRL_MMODE_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_CTRL_MMODE_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_CTRL_MMODE_2 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_CTRL_OPMODE ((uint32_t)0x00000038U) /* Operation Mode Settings */ +#define JPEGDMA_CTRL_OPMODE_0 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_CTRL_OPMODE_1 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_CTRL_OPMODE_2 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_CTRL_START ((uint32_t)0x00000004U) /* DMA Start */ +#define JPEGDMA_CTRL_EN ((uint32_t)0x00000002U) /* Software enable */ +#define JPEGDMA_CTRL_CLR ((uint32_t)0x00000001U) /* Software reset for the entire H2P/P2H */ + +/** Bit definition for JPEGDMA_STS register **/ +#define JPEGDMA_STS_RRERR ((uint32_t)0x00008000U) /* AXI Read response when error has occurred (MSB) */ +#define JPEGDMA_STS_WRERR ((uint32_t)0x00004000U) /* MSB)(AXI Write response when error has occurred (MSB) */ +#define JPEGDMA_STS_WDATAERR ((uint32_t)0x00002000U) /* AXI MM Write Error when writing data */ +#define JPEGDMA_STS_RDATAERR ((uint32_t)0x00001000U) /* AXI MM Read Error when reading data */ +#define JPEGDMA_STS_WDESCERR ((uint32_t)0x00000800U) /* AXI MM Write Error when writing a descriptor */ +#define JPEGDMA_STS_RDESCERR ((uint32_t)0x00000400U) /* AXI MM Read Error when reading a descriptor */ +#define JPEGDMA_STS_FIFOFULL ((uint32_t)0x00000100U) /* Data FIFO is full */ +#define JPEGDMA_STS_FIFOEMPTY ((uint32_t)0x00000080U) /* Data FIFO is empty */ +#define JPEGDMA_STS_EOD ((uint32_t)0x00000040U) /* End-Of-Descriptor */ +#define JPEGDMA_STS_AOOD ((uint32_t)0x00000020U) /* Channel is Almost Out of Descriptors */ +#define JPEGDMA_STS_OOD ((uint32_t)0x00000010U) /* Out Of Descriptors */ +#define JPEGDMA_STS_EOFIN ((uint32_t)0x00000008U) /* End-Of-Frame sampled at the input of the channel */ +#define JPEGDMA_STS_EOFOUT ((uint32_t)0x00000004U) /* End-Of-Frame sampled at the output of the channel */ +#define JPEGDMA_STS_GINT ((uint32_t)0x00000002U) /* Global interrupt status bit for the Channel */ +#define JPEGDMA_STS_BUSY ((uint32_t)0x00000001U) /* H2P/P2H is processing a transfer */ + +/** Bit definition for JPEGDMA_IE register **/ +#define JPEGDMA_IE_WDATAERREN ((uint32_t)0x00002000U) /* Enable interrupt on AXI MM Write Error when writing data */ +#define JPEGDMA_IE_RDATAERREN ((uint32_t)0x00001000U) /* Enable interrupt on AXI MM Read Error when reading data */ +#define JPEGDMA_IE_WDESCERREN ((uint32_t)0x00000800U) /* Enable interrupt on AXI MM Write Error when writing a descriptor */ +#define JPEGDMA_IE_RDESCERREN ((uint32_t)0x00000400U) /* Enable interrupt on AXI MM Read Error when reading a descriptor */ +#define JPEGDMA_IE_EODINTEN ((uint32_t)0x00000040U) /* Enable for the End of Descriptor interrupt */ +#define JPEGDMA_IE_AOODINTEN ((uint32_t)0x00000020U) /* Enable for the Almost Out of Descriptors interrupt */ +#define JPEGDMA_IE_OODINTEN ((uint32_t)0x00000010U) /* Enable for the Out of Descriptors interrupt */ +#define JPEGDMA_IE_EOFININTEN ((uint32_t)0x00000008U) /* Enable for the input EOF interrupt */ +#define JPEGDMA_IE_EOFOUTINTEN ((uint32_t)0x00000004U) /* Enable for the output EOF interrupt */ +#define JPEGDMA_IE_GINTEN ((uint32_t)0x00000002U) /* Global interrupt enable for the Channel */ + +/** Bit definition for JPEGDMA_INTSTS register **/ +#define JPEGDMA_INTSTS_WDATAERR ((uint32_t)0x00002000U) /* AXI MM Write Error when writing data */ +#define JPEGDMA_INTSTS_RDATAERR ((uint32_t)0x00001000U) /* AXI MM Read Error when reading data */ +#define JPEGDMA_INTSTS_WDESCERR ((uint32_t)0x00000800U) /* AXI MM Write Error when writing a descriptor */ +#define JPEGDMA_INTSTS_RDESCERR ((uint32_t)0x00000400U) /* AXI MM Read Error when reading a descriptor */ +#define JPEGDMA_INTSTS_EOD ((uint32_t)0x00000040U) /* End-Of-Descriptor */ +#define JPEGDMA_INTSTS_AOOD ((uint32_t)0x00000020U) /* Channel is Almost Out of Descriptors */ +#define JPEGDMA_INTSTS_OOD ((uint32_t)0x00000010U) /* Out Of Descriptors */ +#define JPEGDMA_INTSTS_EOFIN ((uint32_t)0x00000008U) /* End-Of-Frame sampled at the input of the channel */ +#define JPEGDMA_INTSTS_EOFOUT ((uint32_t)0x00000004U) /* End-Of-Frame sampled at the output of the channel */ +#define JPEGDMA_INTSTS_GINT ((uint32_t)0x00000002U) /* Global interrupt status bit for the Channel */ + +/** Bit definition for JPEGDMA_AOODT register **/ +#define JPEGDMA_AOODT_VALUE ((uint32_t)0xFFFFFFFFU) /* Almost Out Of Descriptors Threshold */ +#define JPEGDMA_AOODT_VALUE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_AOODT_VALUE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_AOODT_VALUE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_AOODT_VALUE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_AOODT_VALUE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_AOODT_VALUE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_AOODT_VALUE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_AOODT_VALUE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_AOODT_VALUE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_AOODT_VALUE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_AOODT_VALUE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_AOODT_VALUE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_AOODT_VALUE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_AOODT_VALUE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_AOODT_VALUE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_AOODT_VALUE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_AOODT_VALUE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_AOODT_VALUE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_AOODT_VALUE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_AOODT_VALUE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_AOODT_VALUE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_AOODT_VALUE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_AOODT_VALUE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_AOODT_VALUE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_AOODT_VALUE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_AOODT_VALUE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_AOODT_VALUE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_AOODT_VALUE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_AOODT_VALUE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_AOODT_VALUE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_AOODT_VALUE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_AOODT_VALUE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_MBSIZE register **/ +#define JPEGDMA_MBSIZE_SIZE ((uint32_t)0xFFFFFFFFU) /* Maximum allowed size for an AXI4 MM burst */ +#define JPEGDMA_MBSIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_MBSIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_MBSIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_MBSIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_MBSIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_MBSIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_MBSIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_MBSIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_MBSIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_MBSIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_MBSIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_MBSIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_MBSIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_MBSIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_MBSIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_MBSIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_MBSIZE_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_MBSIZE_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_MBSIZE_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_MBSIZE_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_MBSIZE_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_MBSIZE_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_MBSIZE_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_MBSIZE_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_MBSIZE_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_MBSIZE_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_MBSIZE_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_MBSIZE_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_MBSIZE_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_MBSIZE_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_MBSIZE_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_MBSIZE_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_SGLPL register **/ +#define JPEGDMA_SGLPL_ADDR ((uint32_t)0xFFFFFFFFU) /* Scatter-Gather List Pointer LSB */ +#define JPEGDMA_SGLPL_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_SGLPL_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_SGLPL_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_SGLPL_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_SGLPL_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_SGLPL_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_SGLPL_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_SGLPL_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_SGLPL_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_SGLPL_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_SGLPL_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_SGLPL_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_SGLPL_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_SGLPL_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_SGLPL_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_SGLPL_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_SGLPL_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_SGLPL_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_SGLPL_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_SGLPL_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_SGLPL_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_SGLPL_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_SGLPL_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_SGLPL_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_SGLPL_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_SGLPL_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_SGLPL_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_SGLPL_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_SGLPL_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_SGLPL_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_SGLPL_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_SGLPL_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_SGLPM register **/ +#define JPEGDMA_SGLPM_ADDR ((uint32_t)0xFFFFFFFFU) /* Scatter-Gather List Pointer MSB */ +#define JPEGDMA_SGLPM_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_SGLPM_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_SGLPM_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_SGLPM_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_SGLPM_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_SGLPM_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_SGLPM_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_SGLPM_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_SGLPM_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_SGLPM_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_SGLPM_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_SGLPM_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_SGLPM_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_SGLPM_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_SGLPM_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_SGLPM_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_SGLPM_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_SGLPM_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_SGLPM_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_SGLPM_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_SGLPM_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_SGLPM_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_SGLPM_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_SGLPM_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_SGLPM_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_SGLPM_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_SGLPM_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_SGLPM_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_SGLPM_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_SGLPM_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_SGLPM_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_SGLPM_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_SGL_SIZE register **/ +#define JPEGDMA_SGL_SIZE_SIZE ((uint32_t)0xFFFFFFFFU) /* Scatter-Gather List Size */ +#define JPEGDMA_SGL_SIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_SGL_SIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_SGL_SIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_SGL_SIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_SGL_SIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_SGL_SIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_SGL_SIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_SGL_SIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_SGL_SIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_SGL_SIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_SGL_SIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_SGL_SIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_SGL_SIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_SGL_SIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_SGL_SIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_SGL_SIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_SGL_SIZE_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_SGL_SIZE_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_SGL_SIZE_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_SGL_SIZE_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_SGL_SIZE_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_SGL_SIZE_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_SGL_SIZE_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_SGL_SIZE_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_SGL_SIZE_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_SGL_SIZE_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_SGL_SIZE_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_SGL_SIZE_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_SGL_SIZE_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_SGL_SIZE_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_SGL_SIZE_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_SGL_SIZE_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_SGL_HEAD register **/ +#define JPEGDMA_SGL_HEAD_POS ((uint32_t)0xFFFFFFFFU) /* Scatter-Gather List Head index pointer defines the position of the Head pointer in the list/ring */ +#define JPEGDMA_SGL_HEAD_POS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_SGL_HEAD_POS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_SGL_HEAD_POS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_SGL_HEAD_POS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_SGL_HEAD_POS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_SGL_HEAD_POS_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_SGL_HEAD_POS_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_SGL_HEAD_POS_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_SGL_HEAD_POS_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_SGL_HEAD_POS_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_SGL_HEAD_POS_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_SGL_HEAD_POS_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_SGL_HEAD_POS_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_SGL_HEAD_POS_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_SGL_HEAD_POS_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_SGL_HEAD_POS_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_SGL_HEAD_POS_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_SGL_HEAD_POS_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_SGL_HEAD_POS_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_SGL_HEAD_POS_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_SGL_HEAD_POS_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_SGL_HEAD_POS_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_SGL_HEAD_POS_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_SGL_HEAD_POS_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_SGL_HEAD_POS_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_SGL_HEAD_POS_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_SGL_HEAD_POS_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_SGL_HEAD_POS_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_SGL_HEAD_POS_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_SGL_HEAD_POS_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_SGL_HEAD_POS_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_SGL_HEAD_POS_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_SGL_TAIL register **/ +#define JPEGDMA_SGL_TAIL_POS ((uint32_t)0xFFFFFFFFU) /* Scatter-Gather List Tail index pointer defines the position of the tail pointer in the list/ring */ +#define JPEGDMA_SGL_TAIL_POS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_SGL_TAIL_POS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_SGL_TAIL_POS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_SGL_TAIL_POS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_SGL_TAIL_POS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_SGL_TAIL_POS_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_SGL_TAIL_POS_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_SGL_TAIL_POS_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_SGL_TAIL_POS_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_SGL_TAIL_POS_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_SGL_TAIL_POS_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_SGL_TAIL_POS_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_SGL_TAIL_POS_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_SGL_TAIL_POS_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_SGL_TAIL_POS_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_SGL_TAIL_POS_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_SGL_TAIL_POS_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_SGL_TAIL_POS_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_SGL_TAIL_POS_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_SGL_TAIL_POS_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_SGL_TAIL_POS_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_SGL_TAIL_POS_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_SGL_TAIL_POS_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_SGL_TAIL_POS_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_SGL_TAIL_POS_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_SGL_TAIL_POS_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_SGL_TAIL_POS_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_SGL_TAIL_POS_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_SGL_TAIL_POS_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_SGL_TAIL_POS_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_SGL_TAIL_POS_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_SGL_TAIL_POS_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_MRADDL register **/ +#define JPEGDMA_MRADDL_ADDR ((uint32_t)0xFFFFFFFFU) /* AXI memory read address reports the current address LSB of the AXI MM interface's read channel accesses */ +#define JPEGDMA_MRADDL_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_MRADDL_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_MRADDL_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_MRADDL_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_MRADDL_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_MRADDL_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_MRADDL_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_MRADDL_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_MRADDL_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_MRADDL_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_MRADDL_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_MRADDL_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_MRADDL_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_MRADDL_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_MRADDL_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_MRADDL_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_MRADDL_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_MRADDL_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_MRADDL_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_MRADDL_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_MRADDL_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_MRADDL_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_MRADDL_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_MRADDL_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_MRADDL_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_MRADDL_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_MRADDL_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_MRADDL_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_MRADDL_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_MRADDL_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_MRADDL_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_MRADDL_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_MRADDM register **/ +#define JPEGDMA_MRADDM_ADDR ((uint32_t)0xFFFFFFFFU) /* AXI memory read address reports the current address MSB of the AXI MM interface's read channel accesses */ +#define JPEGDMA_MRADDM_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_MRADDM_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_MRADDM_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_MRADDM_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_MRADDM_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_MRADDM_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_MRADDM_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_MRADDM_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_MRADDM_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_MRADDM_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_MRADDM_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_MRADDM_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_MRADDM_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_MRADDM_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_MRADDM_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_MRADDM_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_MRADDM_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_MRADDM_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_MRADDM_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_MRADDM_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_MRADDM_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_MRADDM_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_MRADDM_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_MRADDM_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_MRADDM_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_MRADDM_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_MRADDM_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_MRADDM_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_MRADDM_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_MRADDM_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_MRADDM_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_MRADDM_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_MWADDL register **/ +#define JPEGDMA_MWADDL_ADDR ((uint32_t)0xFFFFFFFFU) /* AXI memory write address reports the current address LSB of the AXI MM interface's read channel accesses */ +#define JPEGDMA_MWADDL_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_MWADDL_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_MWADDL_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_MWADDL_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_MWADDL_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_MWADDL_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_MWADDL_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_MWADDL_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_MWADDL_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_MWADDL_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_MWADDL_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_MWADDL_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_MWADDL_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_MWADDL_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_MWADDL_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_MWADDL_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_MWADDL_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_MWADDL_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_MWADDL_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_MWADDL_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_MWADDL_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_MWADDL_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_MWADDL_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_MWADDL_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_MWADDL_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_MWADDL_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_MWADDL_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_MWADDL_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_MWADDL_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_MWADDL_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_MWADDL_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_MWADDL_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_MWADDM register **/ +#define JPEGDMA_MWADDM_ADDR ((uint32_t)0xFFFFFFFFU) /* AXI memory write address reports the current address MSB of the AXI MM interface's read channel accesses */ +#define JPEGDMA_MWADDM_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_MWADDM_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_MWADDM_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_MWADDM_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_MWADDM_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_MWADDM_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_MWADDM_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_MWADDM_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_MWADDM_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_MWADDM_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_MWADDM_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_MWADDM_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_MWADDM_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_MWADDM_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_MWADDM_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_MWADDM_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_MWADDM_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_MWADDM_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_MWADDM_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_MWADDM_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_MWADDM_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_MWADDM_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_MWADDM_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_MWADDM_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_MWADDM_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_MWADDM_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_MWADDM_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_MWADDM_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_MWADDM_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_MWADDM_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_MWADDM_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_MWADDM_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_DESCF register **/ +#define JPEGDMA_DESCF_LINKE ((uint32_t)0x00000001U) /* Link Enable */ +#define JPEGDMA_DESCF_START ((uint32_t)0x00000002U) /* Start of Frame */ +#define JPEGDMA_DESCF_END ((uint32_t)0x00000004U) /* End of Frame */ +#define JPEGDMA_DESCF_DESCCON ((uint32_t)0x00000008U) /* Descriptor Consumed */ + +/** Bit definition for JPEGDMA_DESC_MBSIZE register **/ +#define JPEGDMA_DESC_MBSIZE_SIZE ((uint32_t)0xFFFFFFFFU) /* Descriptor Memory Block Size */ +#define JPEGDMA_DESC_MBSIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_DESC_MBSIZE_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_DESC_MUS register **/ +#define JPEGDMA_DESC_MUS_SIZE ((uint32_t)0xFFFFFFFFU) /* Descriptor Memory Used Space */ +#define JPEGDMA_DESC_MUS_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_DESC_MUS_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_DESC_MUS_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_DESC_MUS_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_DESC_MUS_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_DESC_MUS_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_DESC_MUS_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_DESC_MUS_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_DESC_MUS_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_DESC_MUS_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_DESC_MUS_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_DESC_MUS_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_DESC_MUS_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_DESC_MUS_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_DESC_MUS_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_DESC_MUS_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_DESC_MUS_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_DESC_MUS_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_DESC_MUS_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_DESC_MUS_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_DESC_MUS_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_DESC_MUS_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_DESC_MUS_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_DESC_MUS_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_DESC_MUS_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_DESC_MUS_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_DESC_MUS_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_DESC_MUS_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_DESC_MUS_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_DESC_MUS_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_DESC_MUS_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_DESC_MUS_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_DESC_MBADDL register **/ +#define JPEGDMA_DESC_MBADDL_ADDR ((uint32_t)0xFFFFFFFFU) /* Descriptor Memory Block Address LSB */ +#define JPEGDMA_DESC_MBADDL_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_DESC_MBADDL_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_DESC_MBADDL_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_DESC_MBADDL_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_DESC_MBADDL_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_DESC_MBADDL_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_DESC_MBADDL_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_DESC_MBADDL_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_DESC_MBADDL_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_DESC_MBADDL_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_DESC_MBADDL_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_DESC_MBADDL_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_DESC_MBADDL_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_DESC_MBADDL_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_DESC_MBADDL_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_DESC_MBADDL_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_DESC_MBADDL_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_DESC_MBADDL_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_DESC_MBADDL_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_DESC_MBADDL_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_DESC_MBADDL_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_DESC_MBADDL_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_DESC_MBADDL_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_DESC_MBADDL_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_DESC_MBADDL_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_DESC_MBADDL_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_DESC_MBADDL_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_DESC_MBADDL_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_DESC_MBADDL_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_DESC_MBADDL_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_DESC_MBADDL_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_DESC_MBADDL_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_DESC_MBADDH register **/ +#define JPEGDMA_DESC_MBADDH_ADDR ((uint32_t)0xFFFFFFFFU) /* Descriptor Memory Block Address MSB */ +#define JPEGDMA_DESC_MBADDH_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_DESC_MBADDH_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_DESC_MBADDH_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_DESC_MBADDH_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_DESC_MBADDH_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_DESC_MBADDH_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_DESC_MBADDH_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_DESC_MBADDH_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_DESC_MBADDH_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_DESC_MBADDH_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_DESC_MBADDH_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_DESC_MBADDH_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_DESC_MBADDH_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_DESC_MBADDH_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_DESC_MBADDH_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_DESC_MBADDH_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_DESC_MBADDH_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_DESC_MBADDH_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_DESC_MBADDH_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_DESC_MBADDH_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_DESC_MBADDH_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_DESC_MBADDH_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_DESC_MBADDH_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_DESC_MBADDH_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_DESC_MBADDH_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_DESC_MBADDH_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_DESC_MBADDH_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_DESC_MBADDH_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_DESC_MBADDH_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_DESC_MBADDH_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_DESC_MBADDH_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_DESC_MBADDH_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_DESC_LINKL register **/ +#define JPEGDMA_DESC_LINKL_ADDR ((uint32_t)0xFFFFFFFFU) /* Descriptor Link Address LSB - link to the next descriptor */ +#define JPEGDMA_DESC_LINKL_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_DESC_LINKL_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_DESC_LINKL_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_DESC_LINKL_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_DESC_LINKL_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_DESC_LINKL_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_DESC_LINKL_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_DESC_LINKL_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_DESC_LINKL_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_DESC_LINKL_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_DESC_LINKL_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_DESC_LINKL_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_DESC_LINKL_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_DESC_LINKL_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_DESC_LINKL_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_DESC_LINKL_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_DESC_LINKL_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_DESC_LINKL_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_DESC_LINKL_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_DESC_LINKL_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_DESC_LINKL_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_DESC_LINKL_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_DESC_LINKL_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_DESC_LINKL_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_DESC_LINKL_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_DESC_LINKL_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_DESC_LINKL_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_DESC_LINKL_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_DESC_LINKL_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_DESC_LINKL_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_DESC_LINKL_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_DESC_LINKL_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_DESC_LINKH register **/ +#define JPEGDMA_DESC_LINKH_ADDR ((uint32_t)0xFFFFFFFFU) /* Descriptor Link Address MSB - link to the next descriptor */ +#define JPEGDMA_DESC_LINKH_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_DESC_LINKH_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_DESC_LINKH_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_DESC_LINKH_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_DESC_LINKH_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_DESC_LINKH_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_DESC_LINKH_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_DESC_LINKH_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_DESC_LINKH_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_DESC_LINKH_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_DESC_LINKH_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_DESC_LINKH_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_DESC_LINKH_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_DESC_LINKH_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_DESC_LINKH_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_DESC_LINKH_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_DESC_LINKH_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_DESC_LINKH_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_DESC_LINKH_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_DESC_LINKH_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_DESC_LINKH_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_DESC_LINKH_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_DESC_LINKH_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_DESC_LINKH_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_DESC_LINKH_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_DESC_LINKH_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_DESC_LINKH_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_DESC_LINKH_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_DESC_LINKH_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_DESC_LINKH_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_DESC_LINKH_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_DESC_LINKH_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDMA_PARACFG register **/ +#define JPEGDMA_PARACFG_ALIGNEN ((uint32_t)0x00000004U) /* Instance alignment */ +#define JPEGDMA_PARACFG_DESCSIZE ((uint32_t)0x00000002U) /* Size of descriptor */ +#define JPEGDMA_PARACFG_DTYPE ((uint32_t)0x00000001U) /* Type of DMA Channel */ + +/** Bit definition for JPEGDMA_FIFODP register **/ +#define JPEGDMA_FIFODP_DEPTH ((uint32_t)0xFFFFFFFFU) /* Field mirroring the DATA_FIFO_DEPTH parameter */ +#define JPEGDMA_FIFODP_DEPTH_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDMA_FIFODP_DEPTH_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDMA_FIFODP_DEPTH_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDMA_FIFODP_DEPTH_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDMA_FIFODP_DEPTH_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDMA_FIFODP_DEPTH_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDMA_FIFODP_DEPTH_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDMA_FIFODP_DEPTH_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDMA_FIFODP_DEPTH_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDMA_FIFODP_DEPTH_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDMA_FIFODP_DEPTH_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDMA_FIFODP_DEPTH_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDMA_FIFODP_DEPTH_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDMA_FIFODP_DEPTH_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDMA_FIFODP_DEPTH_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDMA_FIFODP_DEPTH_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDMA_FIFODP_DEPTH_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDMA_FIFODP_DEPTH_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDMA_FIFODP_DEPTH_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDMA_FIFODP_DEPTH_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDMA_FIFODP_DEPTH_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDMA_FIFODP_DEPTH_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDMA_FIFODP_DEPTH_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDMA_FIFODP_DEPTH_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDMA_FIFODP_DEPTH_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDMA_FIFODP_DEPTH_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDMA_FIFODP_DEPTH_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDMA_FIFODP_DEPTH_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDMA_FIFODP_DEPTH_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDMA_FIFODP_DEPTH_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDMA_FIFODP_DEPTH_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDMA_FIFODP_DEPTH_31 ((uint32_t)0x80000000U) /* Bit31*/ + + +/*** JPEG DEC controller ***/ +/** Bit definition for JPEGDEC_MODE register **/ +#define JPEGDEC_MODE_EN ((uint32_t)0x00000001U) /* Enable the decode mode */ + +/** Bit definition for JPEGDEC_ERROR register **/ +#define JPEGDEC_ERROR_HTERR ((uint32_t)0x00000020U) /* A Huffman table referenced in a scan (SOS header) is invalid */ +#define JPEGDEC_ERROR_QTERR ((uint32_t)0x00000010U) /* A Quantisation table referenced in a component referenced in a scan (SOS header) selected an invalid Quantisation table */ +#define JPEGDEC_ERROR_CERR ((uint32_t)0x00000008U) /* A component referenced in the scan header (SOS) was not defined in the previous frame header (SOF) */ +#define JPEGDEC_ERROR_HUF ((uint32_t)0x00000004U) /* Huffman decode error detected */ +#define JPEGDEC_ERROR_UNEXP ((uint32_t)0x00000002U) /* Unexpected marker detected */ +#define JPEGDEC_ERROR_UNK ((uint32_t)0x00000001U) /* Unknown marker detected */ + +/** Bit definition for JPEGDEC_UNLOC register **/ +#define JPEGDEC_UNLOC_POS ((uint32_t)0xFFFFFFFFU) /* Unknown marker error location */ +#define JPEGDEC_UNLOC_POS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_UNLOC_POS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_UNLOC_POS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_UNLOC_POS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_UNLOC_POS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_UNLOC_POS_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_UNLOC_POS_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_UNLOC_POS_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_UNLOC_POS_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_UNLOC_POS_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_UNLOC_POS_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_UNLOC_POS_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_UNLOC_POS_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_UNLOC_POS_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_UNLOC_POS_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_UNLOC_POS_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDEC_UNLOC_POS_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_UNLOC_POS_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_UNLOC_POS_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_UNLOC_POS_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_UNLOC_POS_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_UNLOC_POS_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_UNLOC_POS_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_UNLOC_POS_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_UNLOC_POS_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_UNLOC_POS_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_UNLOC_POS_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_UNLOC_POS_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_UNLOC_POS_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_UNLOC_POS_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_UNLOC_POS_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_UNLOC_POS_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDEC_UELOC register **/ +#define JPEGDEC_UELOC_POS ((uint32_t)0xFFFFFFFFU) /* Unexpected marker error location */ +#define JPEGDEC_UELOC_POS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_UELOC_POS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_UELOC_POS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_UELOC_POS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_UELOC_POS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_UELOC_POS_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_UELOC_POS_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_UELOC_POS_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_UELOC_POS_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_UELOC_POS_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_UELOC_POS_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_UELOC_POS_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_UELOC_POS_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_UELOC_POS_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_UELOC_POS_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_UELOC_POS_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDEC_UELOC_POS_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_UELOC_POS_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_UELOC_POS_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_UELOC_POS_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_UELOC_POS_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_UELOC_POS_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_UELOC_POS_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_UELOC_POS_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_UELOC_POS_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_UELOC_POS_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_UELOC_POS_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_UELOC_POS_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_UELOC_POS_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_UELOC_POS_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_UELOC_POS_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_UELOC_POS_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDEC_HESYM register **/ +#define JPEGDEC_HESYM_HESYM ((uint32_t)0x0000FFFFU) /* The Huffman symbol that is in error */ +#define JPEGDEC_HESYM_HESYM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HESYM_HESYM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HESYM_HESYM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HESYM_HESYM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HESYM_HESYM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HESYM_HESYM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HESYM_HESYM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HESYM_HESYM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HESYM_HESYM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HESYM_HESYM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HESYM_HESYM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HESYM_HESYM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HESYM_HESYM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HESYM_HESYM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HESYM_HESYM_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HESYM_HESYM_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGDEC_HESYMECS register **/ +#define JPEGDEC_HESYMECS_NUM ((uint32_t)0xFFFFFFFFU) /* Huffman ECS Number Symbol */ +#define JPEGDEC_HESYMECS_NUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HESYMECS_NUM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HESYMECS_NUM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HESYMECS_NUM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HESYMECS_NUM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HESYMECS_NUM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HESYMECS_NUM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HESYMECS_NUM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HESYMECS_NUM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HESYMECS_NUM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HESYMECS_NUM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HESYMECS_NUM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HESYMECS_NUM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HESYMECS_NUM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HESYMECS_NUM_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HESYMECS_NUM_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDEC_HESYMECS_NUM_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HESYMECS_NUM_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HESYMECS_NUM_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HESYMECS_NUM_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HESYMECS_NUM_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HESYMECS_NUM_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HESYMECS_NUM_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HESYMECS_NUM_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HESYMECS_NUM_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HESYMECS_NUM_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HESYMECS_NUM_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HESYMECS_NUM_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HESYMECS_NUM_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HESYMECS_NUM_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HESYMECS_NUM_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HESYMECS_NUM_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDEC_HUF_SELOC register **/ +#define JPEGDEC_HUF_SELOC_POS ((uint32_t)0xFFFFFFFFU) /* Huffman ECS Number Symbol Error location */ +#define JPEGDEC_HUF_SELOC_POS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUF_SELOC_POS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUF_SELOC_POS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUF_SELOC_POS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUF_SELOC_POS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUF_SELOC_POS_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUF_SELOC_POS_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUF_SELOC_POS_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUF_SELOC_POS_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUF_SELOC_POS_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUF_SELOC_POS_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUF_SELOC_POS_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUF_SELOC_POS_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUF_SELOC_POS_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUF_SELOC_POS_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUF_SELOC_POS_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDEC_HUF_SELOC_POS_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUF_SELOC_POS_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUF_SELOC_POS_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUF_SELOC_POS_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUF_SELOC_POS_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUF_SELOC_POS_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUF_SELOC_POS_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUF_SELOC_POS_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUF_SELOC_POS_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUF_SELOC_POS_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUF_SELOC_POS_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUF_SELOC_POS_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUF_SELOC_POS_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUF_SELOC_POS_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUF_SELOC_POS_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUF_SELOC_POS_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDEC_TAB_ACCREQ register **/ +#define JPEGDEC_TAB_ACCREQ_AOK ((uint32_t)0x00000002U) /* Table access flag */ +#define JPEGDEC_TAB_ACCREQ_AQEQ ((uint32_t)0x00000001U) /* Table access request */ + +/** Bit definition for JPEGDEC_HUFTAB0_EOB register **/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M ((uint32_t)0xFFFF0000U) /* Contains the EOB symbol mask for Huffman table 0 */ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_9 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_10 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_11 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_12 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_13 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_14 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0M_15 ((uint32_t)0x80000000U) /* Bit31*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C ((uint32_t)0x0000FFFFU) /* Contains the EOB symbol for Huffman table 0 */ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUFTAB0_EOB_EOB0C_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGDEC_HUFTAB1_EOB register **/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M ((uint32_t)0xFFFF0000U) /* Contains the EOB symbol mask for Huffman table 1 */ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_9 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_10 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_11 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_12 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_13 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_14 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1M_15 ((uint32_t)0x80000000U) /* Bit31*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C ((uint32_t)0x0000FFFFU) /* Contains the EOB symbol for Huffman table 1 */ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUFTAB1_EOB_EOB1C_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGDEC_HUFTAB2_EOB register **/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M ((uint32_t)0xFFFF0000U) /* Contains the EOB symbol mask for Huffman table 2 */ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_9 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_10 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_11 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_12 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_13 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_14 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2M_15 ((uint32_t)0x80000000U) /* Bit31*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C ((uint32_t)0x0000FFFFU) /* Contains the EOB symbol for Huffman table 2 */ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUFTAB2_EOB_EOB2C_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGDEC_HUFTAB3_EOB register **/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M ((uint32_t)0xFFFF0000U) /* Contains the EOB symbol mask for Huffman table 3 */ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_9 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_10 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_11 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_12 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_13 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_14 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3M_15 ((uint32_t)0x80000000U) /* Bit31*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C ((uint32_t)0x0000FFFFU) /* Contains the EOB symbol for Huffman table 3 */ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUFTAB3_EOB_EOB3C_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/** Bit definition for JPEGDEC_HUF_ADDR register **/ +#define JPEGDEC_HUF_ADDR_TABLE ((uint32_t)0x00000300U) /* Selects which table to access */ +#define JPEGDEC_HUF_ADDR_TABLE_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUF_ADDR_TABLE_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUF_ADDR_ACDC ((uint32_t)0x00000010U) /* AC/DC table selector encoded */ +#define JPEGDEC_HUF_ADDR_HNUM ((uint32_t)0x00000003U) /* Selects which Huffman table to access */ +#define JPEGDEC_HUF_ADDR_HNUM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUF_ADDR_HNUM_1 ((uint32_t)0x00000002U) /* Bit1*/ + +/** Bit definition for JPEGDEC_HUF_DATA register **/ +#define JPEGDEC_HUF_DATA_HDATA ((uint32_t)0xFFFFFFFFU) /* Huffman table access data */ +#define JPEGDEC_HUF_DATA_HDATA_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUF_DATA_HDATA_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUF_DATA_HDATA_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUF_DATA_HDATA_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUF_DATA_HDATA_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUF_DATA_HDATA_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUF_DATA_HDATA_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUF_DATA_HDATA_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUF_DATA_HDATA_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUF_DATA_HDATA_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUF_DATA_HDATA_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUF_DATA_HDATA_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUF_DATA_HDATA_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUF_DATA_HDATA_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUF_DATA_HDATA_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUF_DATA_HDATA_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDEC_HUF_DATA_HDATA_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUF_DATA_HDATA_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUF_DATA_HDATA_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUF_DATA_HDATA_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUF_DATA_HDATA_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUF_DATA_HDATA_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUF_DATA_HDATA_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUF_DATA_HDATA_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUF_DATA_HDATA_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUF_DATA_HDATA_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUF_DATA_HDATA_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUF_DATA_HDATA_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUF_DATA_HDATA_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUF_DATA_HDATA_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUF_DATA_HDATA_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUF_DATA_HDATA_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDEC_HUF_REM register **/ +#define JPEGDEC_HUF_REM_HREM ((uint32_t)0xFFFFFFFFU) /* Huffman table access number of words remaining */ +#define JPEGDEC_HUF_REM_HREM_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_HUF_REM_HREM_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_HUF_REM_HREM_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_HUF_REM_HREM_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_HUF_REM_HREM_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_HUF_REM_HREM_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_HUF_REM_HREM_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_HUF_REM_HREM_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGDEC_HUF_REM_HREM_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGDEC_HUF_REM_HREM_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGDEC_HUF_REM_HREM_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGDEC_HUF_REM_HREM_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGDEC_HUF_REM_HREM_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGDEC_HUF_REM_HREM_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGDEC_HUF_REM_HREM_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGDEC_HUF_REM_HREM_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGDEC_HUF_REM_HREM_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGDEC_HUF_REM_HREM_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGDEC_HUF_REM_HREM_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGDEC_HUF_REM_HREM_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGDEC_HUF_REM_HREM_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGDEC_HUF_REM_HREM_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGDEC_HUF_REM_HREM_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGDEC_HUF_REM_HREM_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGDEC_HUF_REM_HREM_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGDEC_HUF_REM_HREM_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGDEC_HUF_REM_HREM_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGDEC_HUF_REM_HREM_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGDEC_HUF_REM_HREM_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGDEC_HUF_REM_HREM_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGDEC_HUF_REM_HREM_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGDEC_HUF_REM_HREM_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGDEC_QT0 register **/ +#define JPEGDEC_QT0_QT0 ((uint32_t)0x000000FFU) /* 8-bits of the quantisation value */ +#define JPEGDEC_QT0_QT0_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_QT0_QT0_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_QT0_QT0_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_QT0_QT0_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_QT0_QT0_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_QT0_QT0_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_QT0_QT0_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_QT0_QT0_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGDEC_QT1 register **/ +#define JPEGDEC_QT1_QT1 ((uint32_t)0x000000FFU) /* 8-bits of the quantisation value */ +#define JPEGDEC_QT1_QT1_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_QT1_QT1_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_QT1_QT1_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_QT1_QT1_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_QT1_QT1_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_QT1_QT1_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_QT1_QT1_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_QT1_QT1_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGDEC_QT2 register **/ +#define JPEGDEC_QT2_QT2 ((uint32_t)0x000000FFU) /* 8-bits of the quantisation value */ +#define JPEGDEC_QT2_QT2_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_QT2_QT2_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_QT2_QT2_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_QT2_QT2_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_QT2_QT2_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_QT2_QT2_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_QT2_QT2_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_QT2_QT2_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGDEC_QT3 register **/ +#define JPEGDEC_QT3_QT3 ((uint32_t)0x000000FFU) /* 8-bits of the quantisation value */ +#define JPEGDEC_QT3_QT3_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGDEC_QT3_QT3_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGDEC_QT3_QT3_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGDEC_QT3_QT3_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGDEC_QT3_QT3_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGDEC_QT3_QT3_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGDEC_QT3_QT3_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGDEC_QT3_QT3_7 ((uint32_t)0x00000080U) /* Bit7*/ + + +/*** JPEG ENC controller ***/ +/** Bit definition for JPEGENC_QT0 register **/ +#define JPEGENC_QT0_QT0 ((uint32_t)0x000000FFU) /* Quantisation Table 0 */ +#define JPEGENC_QT0_QT0_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_QT0_QT0_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_QT0_QT0_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_QT0_QT0_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_QT0_QT0_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_QT0_QT0_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_QT0_QT0_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_QT0_QT0_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGENC_QT1 register **/ +#define JPEGENC_QT1_QT1 ((uint32_t)0x000000FFU) /* Quantisation Table 1 */ +#define JPEGENC_QT1_QT1_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_QT1_QT1_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_QT1_QT1_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_QT1_QT1_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_QT1_QT1_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_QT1_QT1_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_QT1_QT1_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_QT1_QT1_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGENC_QT2 register **/ +#define JPEGENC_QT2_QT2 ((uint32_t)0x000000FFU) /* Quantisation Table 2 */ +#define JPEGENC_QT2_QT2_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_QT2_QT2_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_QT2_QT2_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_QT2_QT2_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_QT2_QT2_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_QT2_QT2_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_QT2_QT2_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_QT2_QT2_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGENC_QT3 register **/ +#define JPEGENC_QT3_QT3 ((uint32_t)0x000000FFU) /* Quantisation Table 3 */ +#define JPEGENC_QT3_QT3_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_QT3_QT3_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_QT3_QT3_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_QT3_QT3_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_QT3_QT3_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_QT3_QT3_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_QT3_QT3_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_QT3_QT3_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for JPEGENC_HEADD register **/ +#define JPEGENC_HEADD_ADDR ((uint32_t)0x000007FFU) /* End address of JPEG footer */ +#define JPEGENC_HEADD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_HEADD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_HEADD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_HEADD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_HEADD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_HEADD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_HEADD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_HEADD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_HEADD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_HEADD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_HEADD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ + +/** Bit definition for JPEGENC_HUFTAB0E register **/ +#define JPEGENC_HUFTAB0E_ADDR ((uint32_t)0x000007FFU) /* End address of JPEG Huffman table 0 */ +#define JPEGENC_HUFTAB0E_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_HUFTAB0E_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_HUFTAB0E_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_HUFTAB0E_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_HUFTAB0E_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_HUFTAB0E_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_HUFTAB0E_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_HUFTAB0E_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_HUFTAB0E_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_HUFTAB0E_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_HUFTAB0E_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ + +/** Bit definition for JPEGENC_HUFTAB1E register **/ +#define JPEGENC_HUFTAB1E_ADDR ((uint32_t)0x000007FFU) /* End address of JPEG Huffman table 1 */ +#define JPEGENC_HUFTAB1E_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_HUFTAB1E_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_HUFTAB1E_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_HUFTAB1E_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_HUFTAB1E_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_HUFTAB1E_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_HUFTAB1E_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_HUFTAB1E_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_HUFTAB1E_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_HUFTAB1E_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_HUFTAB1E_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ + +/** Bit definition for JPEGENC_HUFTAB2E register **/ +#define JPEGENC_HUFTAB2E_ADDR ((uint32_t)0x000007FFU) /* End address of JPEG Huffman table 2 */ +#define JPEGENC_HUFTAB2E_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_HUFTAB2E_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_HUFTAB2E_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_HUFTAB2E_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_HUFTAB2E_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_HUFTAB2E_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_HUFTAB2E_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_HUFTAB2E_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_HUFTAB2E_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_HUFTAB2E_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_HUFTAB2E_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ + +/** Bit definition for JPEGENC_HUFTAB3E register **/ +#define JPEGENC_HUFTAB3E_ADDR ((uint32_t)0x000007FFU) /* End address of JPEG Huffman table 3 */ +#define JPEGENC_HUFTAB3E_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_HUFTAB3E_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_HUFTAB3E_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_HUFTAB3E_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_HUFTAB3E_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_HUFTAB3E_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_HUFTAB3E_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_HUFTAB3E_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_HUFTAB3E_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_HUFTAB3E_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_HUFTAB3E_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ + +/** Bit definition for JPEGENC_FEADD register **/ +#define JPEGENC_FEADD_ADDR ((uint32_t)0x000007FFU) /* End address of JPEG footer */ +#define JPEGENC_FEADD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_FEADD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_FEADD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_FEADD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_FEADD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_FEADD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_FEADD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_FEADD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_FEADD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_FEADD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_FEADD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ + +/** Bit definition for JPEGENC_CTRL register **/ +#define JPEGENC_CTRL_QT3 ((uint32_t)0x000C0000U) /* Quantisation table selector for component 3 */ +#define JPEGENC_CTRL_QT3_0 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGENC_CTRL_QT3_1 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGENC_CTRL_QT2 ((uint32_t)0x00030000U) /* Quantisation table selector for component 2 */ +#define JPEGENC_CTRL_QT2_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGENC_CTRL_QT2_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGENC_CTRL_QT1 ((uint32_t)0x0000C000U) /* Quantisation table selector for component 1 */ +#define JPEGENC_CTRL_QT1_0 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGENC_CTRL_QT1_1 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGENC_CTRL_QT0 ((uint32_t)0x00003000U) /* Quantisation table selector for component 0 */ +#define JPEGENC_CTRL_QT0_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGENC_CTRL_QT0_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGENC_CTRL_HUF3 ((uint32_t)0x00000C00U) /* Huffman table selector for component 3 */ +#define JPEGENC_CTRL_HUF3_0 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGENC_CTRL_HUF3_1 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGENC_CTRL_HUF2 ((uint32_t)0x00000300U) /* Huffman table selector for component 2 */ +#define JPEGENC_CTRL_HUF2_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_CTRL_HUF2_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_CTRL_HUF1 ((uint32_t)0x000000C0U) /* Huffman table selector for component 1 */ +#define JPEGENC_CTRL_HUF1_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_CTRL_HUF1_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_CTRL_HUF0 ((uint32_t)0x00000030U) /* Huffman table selector for component 0 */ +#define JPEGENC_CTRL_HUF0_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_CTRL_HUF0_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_CTRL_ERST ((uint32_t)0x00000002U) /* Core reset */ +#define JPEGENC_CTRL_EN ((uint32_t)0x00000001U) /* Core enable */ + +/** Bit definition for JPEGENC_DYNRCFG register **/ +#define JPEGENC_DYNRCFG_HSAFE ((uint32_t)0x00000004U) /* change the contents of the Header/Footer buffer */ +#define JPEGENC_DYNRCFG_DYNF ((uint32_t)0x00000002U) /* state of the pipeline */ +#define JPEGENC_DYNRCFG_DYNEN ((uint32_t)0x00000001U) /* Dynamic enable */ + +/** Bit definition for JPEGENC_HSEL register **/ +#define JPEGENC_HSEL_ATF ((uint32_t)0x00000200U) /* ATF */ +#define JPEGENC_HSEL_NFD ((uint32_t)0x00000100U) /* NFD */ +#define JPEGENC_HSEL_HT3 ((uint32_t)0x00000080U) /* Ouptut Huffman table 3 in output stream */ +#define JPEGENC_HSEL_HT2 ((uint32_t)0x00000040U) /* Ouptut Huffman table 2 in output stream */ +#define JPEGENC_HSEL_HT1 ((uint32_t)0x00000020U) /* Ouptut Huffman table 1 in output stream */ +#define JPEGENC_HSEL_HT0 ((uint32_t)0x00000010U) /* Ouptut Huffman table 0 in output stream */ +#define JPEGENC_HSEL_QT3 ((uint32_t)0x00000008U) /* Ouptut quantisation table 3 in output stream */ +#define JPEGENC_HSEL_QT2 ((uint32_t)0x00000004U) /* Ouptut quantisation table 2 in output stream */ +#define JPEGENC_HSEL_QT1 ((uint32_t)0x00000002U) /* Ouptut quantisation table 1 in output stream */ +#define JPEGENC_HSEL_QT0 ((uint32_t)0x00000001U) /* Ouptut quantisation table 0 in output stream */ + +/** Bit definition for JPEGENC_PIPESTS register **/ +#define JPEGENC_PIPESTS_OOVF ((uint32_t)0x00000001U) /* Assembly buffer overflow */ + +/** Bit definition for JPEGENC_RICTRL register **/ +#define JPEGENC_RICTRL_RIEN ((uint32_t)0x10000000U) /* Enable restart marker generation */ +#define JPEGENC_RICTRL_BRI ((uint32_t)0x0FFFFFFFU) /* Number of blocks per restart interval minus one */ +#define JPEGENC_RICTRL_BRI_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_RICTRL_BRI_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_RICTRL_BRI_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_RICTRL_BRI_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_RICTRL_BRI_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_RICTRL_BRI_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_RICTRL_BRI_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_RICTRL_BRI_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_RICTRL_BRI_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_RICTRL_BRI_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_RICTRL_BRI_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGENC_RICTRL_BRI_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGENC_RICTRL_BRI_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGENC_RICTRL_BRI_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGENC_RICTRL_BRI_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGENC_RICTRL_BRI_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGENC_RICTRL_BRI_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGENC_RICTRL_BRI_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGENC_RICTRL_BRI_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGENC_RICTRL_BRI_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGENC_RICTRL_BRI_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGENC_RICTRL_BRI_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGENC_RICTRL_BRI_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGENC_RICTRL_BRI_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGENC_RICTRL_BRI_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGENC_RICTRL_BRI_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGENC_RICTRL_BRI_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGENC_RICTRL_BRI_27 ((uint32_t)0x08000000U) /* Bit27*/ + +/** Bit definition for JPEGENC_HFSIZE register **/ +#define JPEGENC_HFSIZE_SIZE ((uint32_t)0xFFFFFFFFU) /* Header/footer RAM size in bytes */ +#define JPEGENC_HFSIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_HFSIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_HFSIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_HFSIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_HFSIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_HFSIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_HFSIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_HFSIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_HFSIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_HFSIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_HFSIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGENC_HFSIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGENC_HFSIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGENC_HFSIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGENC_HFSIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGENC_HFSIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGENC_HFSIZE_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGENC_HFSIZE_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGENC_HFSIZE_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGENC_HFSIZE_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGENC_HFSIZE_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGENC_HFSIZE_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGENC_HFSIZE_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGENC_HFSIZE_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGENC_HFSIZE_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGENC_HFSIZE_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGENC_HFSIZE_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGENC_HFSIZE_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGENC_HFSIZE_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGENC_HFSIZE_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGENC_HFSIZE_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGENC_HFSIZE_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGENC_PBSIZE register **/ +#define JPEGENC_PBSIZE_PBSIZE ((uint32_t)0xFFFFFFFFU) /* Pipe buffer size */ +#define JPEGENC_PBSIZE_PBSIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_PBSIZE_PBSIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_PBSIZE_PBSIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_PBSIZE_PBSIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_PBSIZE_PBSIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_PBSIZE_PBSIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_PBSIZE_PBSIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_PBSIZE_PBSIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_PBSIZE_PBSIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_PBSIZE_PBSIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_PBSIZE_PBSIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGENC_PBSIZE_PBSIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGENC_PBSIZE_PBSIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGENC_PBSIZE_PBSIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGENC_PBSIZE_PBSIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGENC_PBSIZE_PBSIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGENC_PBSIZE_PBSIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGENC_PBSIZE_PBSIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGENC_PBSIZE_PBSIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGENC_PBSIZE_PBSIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGENC_PBSIZE_PBSIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGENC_PBSIZE_PBSIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGENC_PBSIZE_PBSIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGENC_PBSIZE_PBSIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGENC_PBSIZE_PBSIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGENC_PBSIZE_PBSIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGENC_PBSIZE_PBSIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGENC_PBSIZE_PBSIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGENC_PBSIZE_PBSIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGENC_PBSIZE_PBSIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGENC_PBSIZE_PBSIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGENC_PBSIZE_PBSIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for JPEGENC_OBSIZE register **/ +#define JPEGENC_OBSIZE_SIZE ((uint32_t)0xFFFFFFFFU) /* Output Buffer size */ +#define JPEGENC_OBSIZE_SIZE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define JPEGENC_OBSIZE_SIZE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define JPEGENC_OBSIZE_SIZE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define JPEGENC_OBSIZE_SIZE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define JPEGENC_OBSIZE_SIZE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define JPEGENC_OBSIZE_SIZE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define JPEGENC_OBSIZE_SIZE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define JPEGENC_OBSIZE_SIZE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define JPEGENC_OBSIZE_SIZE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define JPEGENC_OBSIZE_SIZE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define JPEGENC_OBSIZE_SIZE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define JPEGENC_OBSIZE_SIZE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define JPEGENC_OBSIZE_SIZE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define JPEGENC_OBSIZE_SIZE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define JPEGENC_OBSIZE_SIZE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define JPEGENC_OBSIZE_SIZE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define JPEGENC_OBSIZE_SIZE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define JPEGENC_OBSIZE_SIZE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define JPEGENC_OBSIZE_SIZE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define JPEGENC_OBSIZE_SIZE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define JPEGENC_OBSIZE_SIZE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define JPEGENC_OBSIZE_SIZE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define JPEGENC_OBSIZE_SIZE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define JPEGENC_OBSIZE_SIZE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define JPEGENC_OBSIZE_SIZE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define JPEGENC_OBSIZE_SIZE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define JPEGENC_OBSIZE_SIZE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define JPEGENC_OBSIZE_SIZE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define JPEGENC_OBSIZE_SIZE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define JPEGENC_OBSIZE_SIZE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define JPEGENC_OBSIZE_SIZE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define JPEGENC_OBSIZE_SIZE_31 ((uint32_t)0x80000000U) /* Bit31*/ + + +/*** Digital Video Port controller ***/ + +/** Bit definition for DVP_CTRL register **/ +#define DVP_CTRL_DVPEN ((uint32_t)0x00000001U) /* DVP port enable bit. */ +#define DVP_CTRL_CM ((uint32_t)0x00000002U) /* Capture Mode Control. */ +#define DVP_CTRL_CROPEN ((uint32_t)0x00000100U) /* Cropping Feature Enable bit */ +#define DVP_CTRL_VBFLT ((uint32_t)0xF0000000U) /* VSYNC blanking glitch filtering control */ +#define DVP_CTRL_VBFLT_BIT0 ((uint32_t)0x10000000U) /* BIT0 */ +#define DVP_CTRL_VBFLT_BIT1 ((uint32_t)0x20000000U) /* BIT1 */ +#define DVP_CTRL_VBFLT_BIT2 ((uint32_t)0x40000000U) /* BIT2 */ +#define DVP_CTRL_VBFLT_BIT3 ((uint32_t)0x80000000U) /* BIT3 */ + +/** Bit definition for DVP_INTEN register **/ +#define DVP_INTEN_M1SIE ((uint32_t)0x00000001U) /* Frame Buffer 1 is started to receive image data interrupt enable bit */ +#define DVP_INTEN_M2SIE ((uint32_t)0x00000002U) /* Frame Buffer 2 is started to receive image data interrupt enable bit. */ +#define DVP_INTEN_M1TCIE ((uint32_t)0x00000004U) /* Image data to Frame Buffer 1 transfer complete interrupt enable bit. */ +#define DVP_INTEN_M2TCIE ((uint32_t)0x00000008U) /* Image data to Frame Buffer 2 transfer complete interrupt enable bit. */ +#define DVP_INTEN_FOIE ((uint32_t)0x00000020U) /* Data FIFO Over Flow interrupt enable bit. */ +#define DVP_INTEN_AHBERR ((uint32_t)0x00000080U) /* AHB bus error response interrupt enable bit. */ +#define DVP_INTEN_MOIE ((uint32_t)0x00000100U) /* Frame Buffer Over Flow interrupt enable bit. */ +#define DVP_INTEN_SKIPIE ((uint32_t)0x00010000U) /* Frame skipping interrupt enable bit. */ +#define DVP_INTEN_CERRIE ((uint32_t)0x00020000U) /* SYNC Code mismatch detected interrupt enable bit. */ +#define DVP_INTEN_SERRIE ((uint32_t)0x00040000U) /* SYNC Code error sequence detected interrupt enable bit. */ +#define DVP_INTEN_FMSIE ((uint32_t)0x00080000U) /* Start of Frame detection interrupt Enable bit. */ + +/** Bit definition for DVP_INTSTS register **/ +#define DVP_INTSTS_M1SF ((uint32_t)0x00000001U) /* Data to Frame Buffer 1 start flag */ +#define DVP_INTSTS_M2SF ((uint32_t)0x00000002U) /* Data to Frame Buffer 2 start flag. */ +#define DVP_INTSTS_M1TCF ((uint32_t)0x00000004U) /* Data to Frame Buffer 1 completion flag. */ +#define DVP_INTSTS_M2TCF ((uint32_t)0x00000008U) /* Data to Frame Buffer 2 completion flag. */ +#define DVP_INTSTS_M1FOF ((uint32_t)0x00000010U) /* Frame Buffer 1 FIFO over flow flag. */ +#define DVP_INTSTS_M2FOF ((uint32_t)0x00000020U) /* Frame Buffer 2 FIFO over flow flag. */ +#define DVP_INTSTS_AHBERR1F ((uint32_t)0x00000040U) /* Receiving AHB bus error response on accessing to Frame Buffer 1 flag. */ +#define DVP_INTSTS_AHBERR2F ((uint32_t)0x00000080U) /* Receiving AHB bus error response on accessing to Frame Buffer 2 flag. */ +#define DVP_INTSTS_M1OF ((uint32_t)0x00000100U) /* Frame Buffer 1 Over Flow */ +#define DVP_INTSTS_M2OF ((uint32_t)0x00000200U) /* Frame Buffer 2 Over Flow */ +#define DVP_INTSTS_SKIPF ((uint32_t)0x00010000U) /* Frame skipping detected flag. */ +#define DVP_INTSTS_CERRF ((uint32_t)0x00020000U) /* SYNC Code mismatch error detected flag. */ +#define DVP_INTSTS_SERRF ((uint32_t)0x00040000U) /* SYNC Code sequence error detected flag. */ +#define DVP_INTSTS_FMSF ((uint32_t)0x00080000U) /* Start of Frame detected flag. */ +#define DVP_INTSTS_DVPDIS ((uint32_t)0x01000000U) /* SDVP port disable bit. */ + +/** Bit definition for DVP_PORTCFG register **/ +#define DVP_PORTCFG_PCLKPOL ((uint32_t)0x00000001U) /* DVP port pixel clock polarity control. */ +#define DVP_PORTCFG_HSPOL ((uint32_t)0x00000002U) /* HSYNC polarity control. */ +#define DVP_PORTCFG_VSPOL ((uint32_t)0x00000004U) /* VSYNC polarity control. */ +#define DVP_PORTCFG_DATINV ((uint32_t)0x00000008U) /* Data bit inversion. */ +#define DVP_PORTCFG_DATRVS ((uint32_t)0x00000010U) /* To reverse data bit order. */ +#define DVP_PORTCFG_SLC ((uint32_t)0x00000040U) /* Embedded Synchronization Code Position. */ +#define DVP_PORTCFG_EMBSEN ((uint32_t)0x00000080U) /* Embedded Synchronization Mode enable bit. */ +#define DVP_PORTCFG_DBIT ((uint32_t)0x00000700U) /* DVP data port mode. */ +#define DVP_PORTCFG_DBIT0 ((uint32_t)0x00000100U) /* BIT0. */ +#define DVP_PORTCFG_DBIT1 ((uint32_t)0x00000200U) /* BIT1. */ +#define DVP_PORTCFG_DBIT2 ((uint32_t)0x00000400U) /* BIT2. */ +#define DVP_PORTCFG_PIXELDB ((uint32_t)0x00001000U) /* 2 bytes per pixel */ +#define DVP_PORTCFG_BMAP ((uint32_t)0x00FF0000U) /* Received pixel data to Frame Buffer mapping. */ +#define DVP_PORTCFG_BMAP0 ((uint32_t)0x00010000U) /* BIT0. */ +#define DVP_PORTCFG_BMAP1 ((uint32_t)0x00020000U) /* BIT1. */ +#define DVP_PORTCFG_BMAP2 ((uint32_t)0x00040000U) /* BIT2. */ +#define DVP_PORTCFG_BMAP3 ((uint32_t)0x00080000U) /* BIT3. */ +#define DVP_PORTCFG_BMAP4 ((uint32_t)0x00100000U) /* BIT4. */ +#define DVP_PORTCFG_BMAP5 ((uint32_t)0x00200000U) /* BIT5. */ +#define DVP_PORTCFG_BMAP6 ((uint32_t)0x00400000U) /* BIT6. */ +#define DVP_PORTCFG_BMAP7 ((uint32_t)0x00800000U) /* BIT7. */ +#define DVP_PORTCFG_HISKIP ((uint32_t)0x0F000000U) /* Initial Frame Line Skip Control */ +#define DVP_PORTCFG_HRSKIP ((uint32_t)0xF0000000U) /* Repeat Line Skip Pattern Control (include even/odd line capturing) */ + +/** Bit definition for DVP_FIFOCFG register **/ +#define DVP_FIFOCFG_M1ADDREN ((uint32_t)0x00000001U) /* DVP frame buffer 1 enable control. */ +#define DVP_FIFOCFG_M2ADDREN ((uint32_t)0x00000002U) /* DVP frame buffer 2 enable control. */ +#define DVP_FIFOCFG_DISPMODE ((uint32_t)0x00000010U) /* DVP show current frame buffer status. */ +#define DVP_FIFOCFG_EN1KBD ((uint32_t)0x00000020U) /* DVP bursting across 1K boundary control. */ +#define DVP_FIFOCFG_TXFTH ((uint32_t)0x00000700U) /* DVP FIFO transmit threshold setting. */ +#define DVP_FIFOCFG_TXFTH0 ((uint32_t)0x00000100U) /* BIT0. */ +#define DVP_FIFOCFG_TXFTH1 ((uint32_t)0x00000200U) /* BIT1. */ +#define DVP_FIFOCFG_TXFTH2 ((uint32_t)0x00000400U) /* BIT2. */ +#define DVP_FIFOCFG_TXBURSZ ((uint32_t)0x00070000U) /* DVP AHB master data burst setting. */ +#define DVP_FIFOCFG_TXBURSZ0 ((uint32_t)0x00010000U) /* BIT0. */ +#define DVP_FIFOCFG_TXBURSZ1 ((uint32_t)0x00020000U) /* BIT1. */ +#define DVP_FIFOCFG_TXBURSZ2 ((uint32_t)0x00040000U) /* BIT2. */ + +/** Bit definition for DVP_SMADDR1 register **/ +#define DVP_SMADDR1_MADDR ((uint32_t)0xFFFFFFFFU) /* Frame Buffer 1 Start Address. */ + +/** Bit definition for DVP_SMADDR2 register **/ +#define DVP_SMADDR2_MADDR ((uint32_t)0xFFFFFFFFU) /* Frame Buffer 2 Start Address. */ + +/** Bit definition for DVP_FBS register **/ +#define DVP_FBS_FMSIZE ((uint32_t)0x003FFFFFU) /* Frame Buffer Size. */ + +/** Bit definition for DVP_CSXY register **/ +#define DVP_CSXY_CSTAX ((uint32_t)0x000007FFU) /* X-coordinate of crop image start point. */ +#define DVP_CSXY_CSTAY ((uint32_t)0x07FF0000U) /* Y-coordinate of crop image start point.*/ + +/** Bit definition for DVP_CEXY register **/ +#define DVP_CEXY_CENDX ((uint32_t)0x000007FFU) /* X-coordinate of crop image end point. */ +#define DVP_CEXY_CENDY ((uint32_t)0x07FF0000U) /* Y-coordinate of crop image end point.*/ + +/** Bit definition for DVP_EMSC register **/ +#define DVP_EMSC_VS_PTTN ((uint32_t)0x000000FFU) /* Frame start synchronization code. */ +#define DVP_EMSC_VE_PTTN ((uint32_t)0x0000FF00U) /* Frame end synchronization code. */ +#define DVP_EMSC_HS_PTTN ((uint32_t)0x00FF0000U) /* Active line start synchronization code. */ +#define DVP_EMSC_HE_PTTN ((uint32_t)0xFF000000U) /* Active line end synchronization code. */ + +/** Bit definition for DVP_EMSCM register **/ +#define DVP_EMSCM_VS_MASK ((uint32_t)0x000000FFU) /* Frame start synchronization code Mask. */ +#define DVP_EMSCM_VE_MASK ((uint32_t)0x0000FF00U) /* Frame end synchronization code Mask. */ +#define DVP_EMSCM_HS_MASK ((uint32_t)0x00FF0000U) /* Active line start synchronization code Mask. */ +#define DVP_EMSCM_HE_MASK ((uint32_t)0xFF000000U) /* Active line end synchronization code Mask. */ + + +/*** Ethernet MAC ***/ + +/** Bit definition for ETH_MACCFG register **/ +#define ETH_MACCFG_RE ((uint32_t)0x00000001U) /* Receiver Enable */ +#define ETH_MACCFG_TE ((uint32_t)0x00000002U) /* Transmitter Enable */ +#define ETH_MACCFG_PRELEN ((uint32_t)0x0000000CU) /* PRELEN[1:0]: Preamble Length for Transmit packets */ +#define ETH_MACCFG_PRELEN_0 ((uint32_t)0x00000004U) /* PRELEN bit 0 */ +#define ETH_MACCFG_PRELEN_1 ((uint32_t)0x00000008U) /* PRELEN bit 1 */ +#define ETH_MACCFG_DC ((uint32_t)0x00000010U) /* Deferral Check */ +#define ETH_MACCFG_BL ((uint32_t)0x00000060U) /* BL[1:0]: Back-Off Limit */ +#define ETH_MACCFG_BL_0 ((uint32_t)0x00000020U) /* BL bit 0 */ +#define ETH_MACCFG_BL_1 ((uint32_t)0x00000040U) /* BL bit 1 */ +#define ETH_MACCFG_DR ((uint32_t)0x00000100U) /* Disable Retry */ +#define ETH_MACCFG_DCRS ((uint32_t)0x00000200U) /* Disable Carrier Sense During Transmission */ +#define ETH_MACCFG_DO ((uint32_t)0x00000400U) /* Disable Receive Own */ +#define ETH_MACCFG_ECRSFD ((uint32_t)0x00000800U) /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */ +#define ETH_MACCFG_LM ((uint32_t)0x00001000U) /* Loopback Mode */ +#define ETH_MACCFG_DM ((uint32_t)0x00002000U) /* Duplex Mode (0: Half-duplex, 1: Full-duplex) */ +#define ETH_MACCFG_FES ((uint32_t)0x00004000U) /* Speed (0: 10Mbps, 1: 100Mbps) */ +#define ETH_MACCFG_PS ((uint32_t)0x00008000U) /* Port Select (0: 1000Mbps, 1: 10 or 100Mbps) */ +#define ETH_MACCFG_JE ((uint32_t)0x00010000U) /* Jumbo Packet Enable */ +#define ETH_MACCFG_JD ((uint32_t)0x00020000U) /* Jabber Disable */ +#define ETH_MACCFG_BE ((uint32_t)0x00040000U) /* Packet Burst Enable (Note: ETH2 does not support this bit) */ +#define ETH_MACCFG_WD ((uint32_t)0x00080000U) /* Watchdog Disable */ +#define ETH_MACCFG_ACS ((uint32_t)0x00100000U) /* Automatic Pad or CRC Stripping */ +#define ETH_MACCFG_CST ((uint32_t)0x00200000U) /* CRC stripping for Type packets */ +#define ETH_MACCFG_S2KP ((uint32_t)0x00400000U) /* IEEE 802.3as Support for 2K Packets */ +#define ETH_MACCFG_GPSLCE ((uint32_t)0x00800000U) /* Giant Packet Size Limit Control Enable */ +#define ETH_MACCFG_IPG ((uint32_t)0x07000000U) /* IPG[2:0]: Inter-Packet Gap */ +#define ETH_MACCFG_IPG_0 ((uint32_t)0x01000000U) /* IPG bit 0 */ +#define ETH_MACCFG_IPG_1 ((uint32_t)0x02000000U) /* IPG bit 1 */ +#define ETH_MACCFG_IPG_2 ((uint32_t)0x04000000U) /* IPG bit 2 */ +#define ETH_MACCFG_CSO ((uint32_t)0x08000000U) /* Checksum Offload */ +#define ETH_MACCFG_SARC ((uint32_t)0x70000000U) /* SARC[2:0]: Source Address Insertion or Replacement Control */ +#define ETH_MACCFG_SARC_0 ((uint32_t)0x10000000U) /* SARC bit 0 */ +#define ETH_MACCFG_SARC_1 ((uint32_t)0x20000000U) /* SARC bit 1 */ +#define ETH_MACCFG_SARC_2 ((uint32_t)0x40000000U) /* SARC bit 2 */ +#define ETH_MACCFG_ARPEN ((uint32_t)0x80000000U) /* ARP Offload Enable */ + +/** Bit definition for ETH_MACEXTCFG register **/ +#define ETH_MACEXTCFG_GPSL ((uint32_t)0x00003FFFU) /* Giant Packet Size Limit */ +#define ETH_MACEXTCFG_DCRCC ((uint32_t)0x00010000U) /* Disable CRC Checking for Received Packets */ +#define ETH_MACEXTCFG_SPEN ((uint32_t)0x00020000U) /* Slow Protocol Detection Enable */ +#define ETH_MACEXTCFG_USP ((uint32_t)0x00040000U) /* Unicast Slow Protocol Packet Detect */ +#define ETH_MACEXTCFG_EIPGEN ((uint32_t)0x01000000U) /* Extended Inter-Packet Gap Enable */ +#define ETH_MACEXTCFG_EIPG ((uint32_t)0x3E000000U) /* EIPG[4:0]: Extended Inter-Packet Gap */ +#define ETH_MACEXTCFG_EIPG_0 ((uint32_t)0x02000000U) /* EIPG bit 0 */ +#define ETH_MACEXTCFG_EIPG_1 ((uint32_t)0x04000000U) /* EIPG bit 1 */ +#define ETH_MACEXTCFG_EIPG_2 ((uint32_t)0x08000000U) /* EIPG bit 2 */ +#define ETH_MACEXTCFG_EIPG_3 ((uint32_t)0x10000000U) /* EIPG bit 3 */ +#define ETH_MACEXTCFG_EIPG_4 ((uint32_t)0x20000000U) /* EIPG bit 4 */ +#define ETH_MACEXTCFG_APDIM ((uint32_t)0x40000000U) /* ARP Packet Drop if IP Address Mismatch */ + +/** Bit definition for ETH_MACPFLT register **/ +#define ETH_MACPFLT_PM ((uint32_t)0x00000001U) /* Promiscuous Mode */ +#define ETH_MACPFLT_HUC ((uint32_t)0x00000002U) /* Hash Unicast */ +#define ETH_MACPFLT_HMC ((uint32_t)0x00000004U) /* Hash Multicast */ +#define ETH_MACPFLT_DAIF ((uint32_t)0x00000008U) /* DA Inverse Filtering */ +#define ETH_MACPFLT_PAM ((uint32_t)0x00000010U) /* Pass All Multicast */ +#define ETH_MACPFLT_DBP ((uint32_t)0x00000020U) /* Disable Broadcast Packets */ +#define ETH_MACPFLT_PCP ((uint32_t)0x000000C0U) /* PCF[1:0]: Pass Control Packets */ +#define ETH_MACPFLT_PCP_0 ((uint32_t)0x00000040U) /* PCF bit 0 */ +#define ETH_MACPFLT_PCP_1 ((uint32_t)0x00000080U) /* PCF bit 1 */ +#define ETH_MACPFLT_SAIF ((uint32_t)0x00000100U) /* SA Inverse Filtering */ +#define ETH_MACPFLT_SAF ((uint32_t)0x00000200U) /* SA Filter Enable */ +#define ETH_MACPFLT_HPF ((uint32_t)0x00000400U) /* Hash or Perfect Filter */ +#define ETH_MACPFLT_VTFE ((uint32_t)0x00010000U) /* VLAN Tag Filter Enable */ +#define ETH_MACPFLT_IPFE ((uint32_t)0x00100000U) /* Layer 3 and Layer 4 Filter Enable */ +#define ETH_MACPFLT_DNTU ((uint32_t)0x00200000U) /* Drop Non-TCP/UDP over IP Packets */ +#define ETH_MACPFLT_RA ((uint32_t)0x80000000U) /* Receive All */ + +/** Bit definition for ETH_MACWDGTO register **/ +#define ETH_MACWDGTO_WTO ((uint32_t)0x0000000FU) /* WTO[3:0]: Watchdog Timeout */ +#define ETH_MACWDGTO_WTO_0 ((uint32_t)0x00000001U) /* WTO bit 0 */ +#define ETH_MACWDGTO_WTO_1 ((uint32_t)0x00000002U) /* WTO bit 1 */ +#define ETH_MACWDGTO_WTO_2 ((uint32_t)0x00000004U) /* WTO bit 2 */ +#define ETH_MACWDGTO_WTO_3 ((uint32_t)0x00000008U) /* WTO bit 3 */ +#define ETH_MACWDGTO_PWE ((uint32_t)0x00000100U) /* Programmable Watchdog Enable */ + +/** Bit definition for ETH_MACHASHTR0 register **/ +#define ETH_MACHASHTR0_HT31T0 ((uint32_t)0xFFFFFFFFU) /* MAC Hash Table First 32 Bits */ + +/** Bit definition for ETH_MACHASHTR1 register **/ +#define ETH_MACHASHTR1_HT63T32 ((uint32_t)0xFFFFFFFFU) /* MAC Hash Table Second 32 Bits */ + +/** Bit definition for ETH_MACVLANTAG register **/ +#define ETH_MACVLANTAG_VL ((uint32_t)0x0000FFFFU) /* VLAN Tag Identifier for Receive Packets */ +#define ETH_MACVLANTAG_VL_UP ((uint32_t)0x0000E000U) /* VL[15:13]: User Priority */ +#define ETH_MACVLANTAG_VL_UP_0 ((uint32_t)0x00002000U) /* VL_UP bit 0 */ +#define ETH_MACVLANTAG_VL_UP_1 ((uint32_t)0x00004000U) /* VL_UP bit 1 */ +#define ETH_MACVLANTAG_VL_UP_2 ((uint32_t)0x00008000U) /* VL_UP bit 2 */ +#define ETH_MACVLANTAG_VL_CFIDEI ((uint32_t)0x00001000U) /* VL[12]: Canonical Format Indicator (CFI) or \ + Drop Eligible Indicator (DEI) */ +#define ETH_MACVLANTAG_VL_VID ((uint32_t)0x00000FFFU) /* VL[11:0]: VLAN Identifier field of VLAN tag */ +#define ETH_MACVLANTAG_ETV ((uint32_t)0x00010000U) /* Enable 12-Bit VLAN Tag Comparison */ +#define ETH_MACVLANTAG_VTIM ((uint32_t)0x00020000U) /* VLAN Tag Inverse Match Enable */ +#define ETH_MACVLANTAG_ESVL ((uint32_t)0x00040000U) /* Enable S-VLAN */ +#define ETH_MACVLANTAG_ERSVLM ((uint32_t)0x00080000U) /* Enable Receive S-VLAN Match */ +#define ETH_MACVLANTAG_DOVLTC ((uint32_t)0x00100000U) /* Disable VLAN Type Check */ +#define ETH_MACVLANTAG_EVLS ((uint32_t)0x00600000U) /* EVLS[1:0]: Enable VLAN Tag Stripping on Receive */ +#define ETH_MACVLANTAG_EVLS_0 ((uint32_t)0x00200000U) /* EVLS bit 0 */ +#define ETH_MACVLANTAG_EVLS_1 ((uint32_t)0x00400000U) /* EVLS bit 1 */ +#define ETH_MACVLANTAG_EVLRXS ((uint32_t)0x01000000U) /* Enable VLAN Tag in Rx status */ +#define ETH_MACVLANTAG_VTHM ((uint32_t)0x02000000U) /* VLAN Tag Hash Table Match Enable */ +#define ETH_MACVLANTAG_EDVLP ((uint32_t)0x04000000U) /* Enable Double VLAN Processing */ +#define ETH_MACVLANTAG_ERIVLT ((uint32_t)0x08000000U) /* Enable Inner VLAN Tag */ +#define ETH_MACVLANTAG_EIVLS ((uint32_t)0x30000000U) /* EIVLS[1:0]: Enable Inner VLAN Tag Stripping on Receive */ +#define ETH_MACVLANTAG_EIVLS_0 ((uint32_t)0x10000000U) /* EIVLS bit 0 */ +#define ETH_MACVLANTAG_EIVLS_1 ((uint32_t)0x20000000U) /* EIVLS bit 1 */ +#define ETH_MACVLANTAG_EIVLRXS ((uint32_t)0x80000000U) /* Enable Inner VLAN Tag in Rx Status */ + +/** Bit definition for ETH_MACVHASHT register **/ +#define ETH_MACVHASHT_VLHT ((uint32_t)0x0000FFFFU) /* VLAN Hash Table */ + +/** Bit definition for ETH_MACVLANINC register **/ +#define ETH_MACVLANINC_VLT ((uint32_t)0x0000FFFFU) /* VLAN Tag for Transmit Packets */ +#define ETH_MACVLANINC_VLC ((uint32_t)0x00030000U) /* VLC[1:0]: VLAN Tag Control in Transmit Packets */ +#define ETH_MACVLANINC_VLC_0 ((uint32_t)0x00010000U) /* VLC bit 0 */ +#define ETH_MACVLANINC_VLC_1 ((uint32_t)0x00020000U) /* VLC bit 1 */ +#define ETH_MACVLANINC_VLP ((uint32_t)0x00040000U) /* VLAN Priority Control */ +#define ETH_MACVLANINC_CSVL ((uint32_t)0x00080000U) /* C-VLAN or S-VLAN */ +#define ETH_MACVLANINC_VLTI ((uint32_t)0x00100000U) /* VLAN Tag Input */ + +/** Bit definition for ETH_MACIVLANINC register **/ +#define ETH_MACIVLANINC_VLT ((uint32_t)0x0000FFFFU) /* VLAN Tag for Transmit Packets */ +#define ETH_MACIVLANINC_VLC ((uint32_t)0x00030000U) /* VLC[1:0]: VLAN Tag Control in Transmit Packets */ +#define ETH_MACIVLANINC_VLC_0 ((uint32_t)0x00010000U) /* VLC bit 0 */ +#define ETH_MACIVLANINC_VLC_1 ((uint32_t)0x00020000U) /* VLC bit 1 */ +#define ETH_MACIVLANINC_VLP ((uint32_t)0x00040000U) /* VLAN Priority Control */ +#define ETH_MACIVLANINC_CSVL ((uint32_t)0x00080000U) /* C-VLAN or S-VLAN */ +#define ETH_MACIVLANINC_VLTI ((uint32_t)0x00100000U) /* VLAN Tag Input */ + +/** Bit definition for ETH_MACTXFLWCTRL register **/ +#define ETH_MACTXFLWCTRL_FCB ((uint32_t)0x00000001U) /* Flow Control Busy */ +#define ETH_MACTXFLWCTRL_BPA ((uint32_t)0x00000001U) /* Backpressure Activate */ +#define ETH_MACTXFLWCTRL_TFE ((uint32_t)0x00000002U) /* Transmit Flow Control Enable */ +#define ETH_MACTXFLWCTRL_PLT ((uint32_t)0x00000070U) /* PLT[2:0]: Pause Low Threshold */ +#define ETH_MACTXFLWCTRL_PLT_0 ((uint32_t)0x00000010U) /* PLT bit 0 */ +#define ETH_MACTXFLWCTRL_PLT_1 ((uint32_t)0x00000020U) /* PLT bit 1 */ +#define ETH_MACTXFLWCTRL_PLT_2 ((uint32_t)0x00000040U) /* PLT bit 2 */ +#define ETH_MACTXFLWCTRL_DZPQ ((uint32_t)0x00000080U) /* Disable Zero-Quanta Pause */ +#define ETH_MACTXFLWCTRL_PT ((uint32_t)0xFFFF0000U) /* Pause Time */ + +/** Bit definition for ETH_MACRXFLWCTRL register **/ +#define ETH_MACRXFLWCTRL_RFE ((uint32_t)0x00000001U) /* Receive Flow Control Enable */ +#define ETH_MACRXFLWCTRL_UP ((uint32_t)0x00000002U) /* Unicast Pause Packet Detect */ + +/** Bit definition for ETH_MACINTSTS register **/ +#define ETH_MACINTSTS_PHYIS ((uint32_t)0x00000008U) /* PHY Interrupt */ +#define ETH_MACINTSTS_PMTIS ((uint32_t)0x00000010U) /* PMT Interrupt Status */ +#define ETH_MACINTSTS_LPIIS ((uint32_t)0x00000020U) /* LPI Interrupt Status */ +#define ETH_MACINTSTS_MMCIS ((uint32_t)0x00000100U) /* MMC Interrupt Status */ +#define ETH_MACINTSTS_MMCRXIS ((uint32_t)0x00000200U) /* MMC Receive Interrupt Status */ +#define ETH_MACINTSTS_MMCTXIS ((uint32_t)0x00000400U) /* MMC Transmit Interrupt Status */ +#define ETH_MACINTSTS_MMCRXIPIS ((uint32_t)0x00000800U) /* MMC Receive Checksum Offload Interrupt Status */ +#define ETH_MACINTSTS_TSIS ((uint32_t)0x00001000U) /* Timestamp Interrupt Status */ +#define ETH_MACINTSTS_TXSTSIS ((uint32_t)0x00002000U) /* Transmit Status Interrupt */ +#define ETH_MACINTSTS_RXSTSIS ((uint32_t)0x00004000U) /* Receive Status Interrupt */ +#define ETH_MACINTSTS_MDIOIS ((uint32_t)0x00040000U) /* MDIO Interrupt Status */ + +/** Bit definition for ETH_MACINTEN register **/ +#define ETH_MACINTEN_PHYIE ((uint32_t)0x00000008U) /* PHY Interrupt Enable */ +#define ETH_MACINTEN_PMTIE ((uint32_t)0x00000010U) /* PMT Interrupt Enable */ +#define ETH_MACINTEN_LPIIE ((uint32_t)0x00000020U) /* LPI Interrupt Enable */ +#define ETH_MACINTEN_TSIE ((uint32_t)0x00001000U) /* Timestamp Interrupt Enable */ +#define ETH_MACINTEN_TXSTSIE ((uint32_t)0x00002000U) /* Transmit Status Interrupt Enable */ +#define ETH_MACINTEN_RXSTSIE ((uint32_t)0x00004000U) /* Receive Status Interrupt Enable */ +#define ETH_MACINTEN_MDIOIE ((uint32_t)0x00040000U) /* MDIO Interrupt Enable */ + +/** Bit definition for ETH_MACRXTXSTS register **/ +#define ETH_MACRXTXSTS_TJT ((uint32_t)0x00000001U) /* Transmit Jabber Timeout */ +#define ETH_MACRXTXSTS_NCARR ((uint32_t)0x00000002U) /* No Carrier */ +#define ETH_MACRXTXSTS_LCARR ((uint32_t)0x00000004U) /* Loss of Carrier */ +#define ETH_MACRXTXSTS_EXDEF ((uint32_t)0x00000008U) /* Excessive Deferral */ +#define ETH_MACRXTXSTS_LCOL ((uint32_t)0x00000010U) /* Late Collision */ +#define ETH_MACRXTXSTS_EXCOL ((uint32_t)0x00000020U) /* Excessive Collisions */ +#define ETH_MACRXTXSTS_RWT ((uint32_t)0x00000100U) /* Receive Watchdog Timeout */ + +/** Bit definition for ETH_MACPMTCTRLSTS register **/ +#define ETH_MACPMTCTRLSTS_PWRDWN ((uint32_t)0x00000001U) /* Power Down */ +#define ETH_MACPMTCTRLSTS_MGKPKTEN ((uint32_t)0x00000002U) /* Magic Packet Enable */ +#define ETH_MACPMTCTRLSTS_RWKPKTEN ((uint32_t)0x00000004U) /* Remote Wake-Up Packet Enable */ +#define ETH_MACPMTCTRLSTS_MGKPRCVD ((uint32_t)0x00000020U) /* Magic Packet Received */ +#define ETH_MACPMTCTRLSTS_RWKPRCVD ((uint32_t)0x00000040U) /* Remote Wake-Up Packet Received */ +#define ETH_MACPMTCTRLSTS_GLBLUCAST ((uint32_t)0x00000200U) /* Global Unicast */ +#define ETH_MACPMTCTRLSTS_RWKPFE ((uint32_t)0x00000400U) /* Remote Wake-up Packet Forwarding Enable */ +#define ETH_MACPMTCTRLSTS_RWKPTR ((uint32_t)0x1F000000U) /* Remote Wake-up FIFO Pointer */ +#define ETH_MACPMTCTRLSTS_RWKFILTRST ((uint32_t)0x80000000U) /* Remote Wake-Up Packet Filter Register Pointer Reset */ + +/** Bit definition for ETH_MACRWUPFLT register **/ +#define ETH_MACRWUPFLT_WKUPFRMFTR ((uint32_t)0xFFFFFFFFU) /* RWK Packet Filter */ + +/** Bit definition for ETH_MACLPICTRLSTS register **/ +#define ETH_MACLPICTRLSTS_TLPIEN ((uint32_t)0x00000001U) /* Transmit LPI Entry */ +#define ETH_MACLPICTRLSTS_TLPIEX ((uint32_t)0x00000002U) /* Transmit LPI Exit */ +#define ETH_MACLPICTRLSTS_RLPIEN ((uint32_t)0x00000004U) /* Receive LPI Entry */ +#define ETH_MACLPICTRLSTS_RLPIEX ((uint32_t)0x00000008U) /* Receive LPI Exit */ +#define ETH_MACLPICTRLSTS_TLPIST ((uint32_t)0x00000100U) /* Transmit LPI State */ +#define ETH_MACLPICTRLSTS_RLPIST ((uint32_t)0x00000200U) /* Receive LPI State */ +#define ETH_MACLPICTRLSTS_LPIEN ((uint32_t)0x00010000U) /* LPI Enable */ +#define ETH_MACLPICTRLSTS_PLS ((uint32_t)0x00020000U) /* PHY Link Status */ +#define ETH_MACLPICTRLSTS_LPITXA ((uint32_t)0x00080000U) /* LPI Tx Automate */ +#define ETH_MACLPICTRLSTS_LPIATE ((uint32_t)0x00100000U) /* LPI Timer Enable */ +#define ETH_MACLPICTRLSTS_LPITCSE ((uint32_t)0x00200000U) /* LPI Tx Clock Stop Enable */ + +/** Bit definition for ETH_MACLPITIMCTRL register **/ +#define ETH_MACLPITIMCTRL_TWT ((uint32_t)0x0000FFFFU) /* LPI TW Timer */ +#define ETH_MACLPITIMCTRL_LST ((uint32_t)0x03FF0000U) /* LPI LS Timer */ + +/** Bit definition for ETH_MACLPIETYTIM register **/ +#define ETH_MACLPIETYTIM_LPIET ((uint32_t)0x000FFFF8U) /* LPI Entry Timer */ + +/** Bit definition for ETH_MAC1USTICCNT register **/ +#define ETH_MAC1USTICCNT_TIC1USCNTR ((uint32_t)0x00000FFFU) /* 1US Tick Counter */ + +/** Bit definition for ETH_MACVER register **/ +#define ETH_MACVER_SNPSVER ((uint32_t)0x000000FFU) /* Synopsys-defined Version */ +#define ETH_MACVER_USERVER ((uint32_t)0x0000FF00U) /* User-defined Version */ + +/** Bit definition for ETH_MACDBG register **/ +#define ETH_MACDBG_RPESTS ((uint32_t)0x00000001U) /* MAC GMII or MII Receive Protocol Engine Status */ +#define ETH_MACDBG_RFCFCSTS ((uint32_t)0x00000006U) /* RFCFCSTS[1:0]: MAC Receive Packet Controller FIFO Status */ +#define ETH_MACDBG_RFCFCSTS_0 ((uint32_t)0x00000002U) /* RFCFCSTS bit 0 */ +#define ETH_MACDBG_RFCFCSTS_1 ((uint32_t)0x00000004U) /* RFCFCSTS bit 1 */ +#define ETH_MACDBG_TPESTS ((uint32_t)0x00010000U) /* MAC GMII or MII Transmit Protocol Engine Status */ +#define ETH_MACDBG_TFCSTS ((uint32_t)0x00060000U) /* TFCSTS[1:0]: MAC Transmit Packet Controller Status */ +#define ETH_MACDBG_TFCSTS_0 ((uint32_t)0x00020000U) /* TFCSTS bit 0 */ +#define ETH_MACDBG_TFCSTS_1 ((uint32_t)0x00040000U) /* TFCSTS bit 1 */ + +/** Bit definition for ETH_MACHWF0 register **/ +#define ETH_MACHWF0_MIISEL ((uint32_t)0x00000001U) /* 10 or 100 Mbps Support */ +#define ETH_MACHWF0_GMIISEL ((uint32_t)0x00000002U) /* 1000 Mbps Support */ +#define ETH_MACHWF0_HDSEL ((uint32_t)0x00000004U) /* Half-duplex Support */ +#define ETH_MACHWF0_VLHASH ((uint32_t)0x00000010U) /* VLAN Hash Filter Selected */ +#define ETH_MACHWF0_SMASEL ((uint32_t)0x00000020U) /* SMA (MDIO) Interface */ +#define ETH_MACHWF0_RWKSEL ((uint32_t)0x00000040U) /* PMT Remote Wake-up Packet Enable */ +#define ETH_MACHWF0_MGKSEL ((uint32_t)0x00000080U) /* PMT Magic Packet Enable */ +#define ETH_MACHWF0_MMCSEL ((uint32_t)0x00000100U) /* RMON Module Enable */ +#define ETH_MACHWF0_ARPOFFSEL ((uint32_t)0x00000200U) /* ARP Offload Enabled */ +#define ETH_MACHWF0_TSSEL ((uint32_t)0x00001000U) /* IEEE 1588-2008 Timestamp Enabled */ +#define ETH_MACHWF0_EEESEL ((uint32_t)0x00002000U) /* Energy Efficient Ethernet Enabled */ +#define ETH_MACHWF0_TXCOESEL ((uint32_t)0x00004000U) /* Transmit Checksum Offload Enabled */ +#define ETH_MACHWF0_RXCOESEL ((uint32_t)0x00010000U) /* Receive Checksum Offload Enabled */ +#define ETH_MACHWF0_ADDMACADRSEL ((uint32_t)0x007C0000U) /* MAC Addresses 1-31 Selected */ +#define ETH_MACHWF0_MACADR32SEL ((uint32_t)0x00800000U) /* MAC Addresses 32-63 Selected */ +#define ETH_MACHWF0_MACADR64SEL ((uint32_t)0x01000000U) /* MAC Addresses 64-127 Selected */ +#define ETH_MACHWF0_TSSTSSEL ((uint32_t)0x06000000U) /* Timestamp System Time Source */ +#define ETH_MACHWF0_SAVLANINS ((uint32_t)0x08000000U) /* Source Address or VLAN Insertion Enable */ +#define ETH_MACHWF0_ACTPHYSEL ((uint32_t)0x70000000U) /* Active PHY Selected */ + +/** Bit definition for ETH_MACHWF1 register **/ +#define ETH_MACHWF1_RXFIFOSIZE ((uint32_t)0x0000001FU) /* MTL Receive FIFO Size */ +#define ETH_MACHWF1_SPRAM ((uint32_t)0x00000020U) /* Single Port RAM Enable */ +#define ETH_MACHWF1_TXFIFOSIZE ((uint32_t)0x000007C0U) /* MTL Transmit FIFO Size */ +#define ETH_MACHWF1_OSTEN ((uint32_t)0x00000800U) /* One-Step Timestamping Enable */ +#define ETH_MACHWF1_PTOEN ((uint32_t)0x00001000U) /* PTP Offload Enable */ +#define ETH_MACHWF1_ADVTHWORD ((uint32_t)0x00002000U) /* IEEE 1588 High Word Register Enable */ +#define ETH_MACHWF1_ADDR64 ((uint32_t)0x0000C000U) /* Address Width */ +#define ETH_MACHWF1_DCBEN ((uint32_t)0x00010000U) /* DCB Feature Enable */ +#define ETH_MACHWF1_SPHEN ((uint32_t)0x00020000U) /* Split Header Feature Enable */ +#define ETH_MACHWF1_TSOEN ((uint32_t)0x00040000U) /* TCP Segmentation Offload Enable */ +#define ETH_MACHWF1_DBGMEMA ((uint32_t)0x00080000U) /* DMA Debug Registers Enable */ +#define ETH_MACHWF1_AVSEL ((uint32_t)0x00100000U) /* AV Feature Enable */ +#define ETH_MACHWF1_RAVSEL ((uint32_t)0x00200000U) /* Rx Side Only AV Feature Enable */ +#define ETH_MACHWF1_POUOST ((uint32_t)0x00800000U) /* One Step for PTP over UDP/IP Feature Enable */ +#define ETH_MACHWF1_HASHTBLSZ ((uint32_t)0x03000000U) /* Hash Table Size */ +#define ETH_MACHWF1_L3L4FNUM ((uint32_t)0x78000000U) /* Total number of L3 or L4 Filters */ + +/** Bit definition for ETH_MACHWF2 register **/ +#define ETH_MACHWF2_RXQCNT ((uint32_t)0x0000000FU) /* Number of MTL Receive Queues */ +#define ETH_MACHWF2_TXQCNT ((uint32_t)0x000003C0U) /* Number of MTL Transmit Queues */ +#define ETH_MACHWF2_RXCHCNT ((uint32_t)0x0000F000U) /* Number of DMA Receive Channels */ +#define ETH_MACHWF2_RDCSZ ((uint32_t)0x00030000U) /* Rx DMA Descriptor Cache Size in terms of \ + 16 bytes descriptors */ +#define ETH_MACHWF2_TXCHCNT ((uint32_t)0x003C0000U) /* Number of DMA Transmit Channels */ +#define ETH_MACHWF2_TDCSZ ((uint32_t)0x00C00000U) /* Tx DMA Descriptor Cache Size in terms of \ + 16 bytes descriptors */ +#define ETH_MACHWF2_PPSOUTNUM ((uint32_t)0x03000000U) /* Number of PPS Outputs */ +#define ETH_MACHWF2_AUXSNAPNUM ((uint32_t)0x70000000U) /* Number of Auxiliary Snapshot Inputs */ + +/** Bit definition for ETH_MACHWF3 register **/ +#define ETH_MACHWF3_NRVF ((uint32_t)0x00000007U) /* Number of Extended VLAN Tag Filters Enabled */ +#define ETH_MACHWF3_CBTISEL ((uint32_t)0x00000010U) /* Queue/Channel based VLAN tag insertion on Tx Enable */ +#define ETH_MACHWF3_DVLAN ((uint32_t)0x00000020U) /* Double VLAN Tag Processing Selected */ +#define ETH_MACHWF3_PDUPSEL ((uint32_t)0x00000200U) /* Broadcast/Multicast Packet Duplication */ +#define ETH_MACHWF3_FRPSEL ((uint32_t)0x00000200U) /* Flexible Receive Parser Selected */ +#define ETH_MACHWF3_FRPBS ((uint32_t)0x00001800U) /* Flexible Receive Parser Buffer size */ +#define ETH_MACHWF3_FRPES ((uint32_t)0x00006000U) /* Flexible Receive Parser Table Entries size */ +#define ETH_MACHWF3_ESTSEL ((uint32_t)0x00010000U) /* Enhancements to Scheduled Traffic Enable */ +#define ETH_MACHWF3_ESTDEP ((uint32_t)0x000E0000U) /* Depth of the Gate Control List */ +#define ETH_MACHWF3_ESTWID ((uint32_t)0x00300000U) /* Width of the Time Interval field in the Gate Control List */ +#define ETH_MACHWF3_FPESEL ((uint32_t)0x04000000U) /* Frame Preemption Enable */ +#define ETH_MACHWF3_TBSSEL ((uint32_t)0x08000000U) /* Time Based Scheduling Enable */ +#define ETH_MACHWF3_ASP ((uint32_t)0x30000000U) /* Automotive Safety Package */ + +/** Bit definition for ETH_MACMDIOADDR register **/ +#define ETH_MACMDIOADDR_GB ((uint32_t)0x00000001U) /* GMII/MII Busy */ +#define ETH_MACMDIOADDR_C45E ((uint32_t)0x00000002U) /* Clause 45 PHY Enable */ +#define ETH_MACMDIOADDR_GOC ((uint32_t)0x0000000CU) /* GMII/MII Operation Command */ +#define ETH_MACMDIOADDR_GOC0 ((uint32_t)0x00000004U) /* GMII/MII Operation Command 0 */ +#define ETH_MACMDIOADDR_GOC1 ((uint32_t)0x00000008U) /* GMII/MII Operation Command 1 */ +#define ETH_MACMDIOADDR_SKAP ((uint32_t)0x00000010U) /* Skip Address Packet */ +#define ETH_MACMDIOADDR_CR ((uint32_t)0x00000F00U) /* CR[3:0]: CSR Clock Range */ +#define ETH_MACMDIOADDR_CR_0 ((uint32_t)0x00000100U) /* CR bit 0 */ +#define ETH_MACMDIOADDR_CR_1 ((uint32_t)0x00000200U) /* CR bit 1 */ +#define ETH_MACMDIOADDR_CR_2 ((uint32_t)0x00000400U) /* CR bit 2 */ +#define ETH_MACMDIOADDR_CR_3 ((uint32_t)0x00000800U) /* CR bit 3 */ +#define ETH_MACMDIOADDR_NTC ((uint32_t)0x00007000U) /* Number of Trailing Clocks */ +#define ETH_MACMDIOADDR_RDA ((uint32_t)0x001F0000U) /* Register/Device Address */ +#define ETH_MACMDIOADDR_PA ((uint32_t)0x003E0000U) /* Physical Layer Address */ +#define ETH_MACMDIOADDR_BTB ((uint32_t)0x04000000U) /* Back to Back transactions */ +#define ETH_MACMDIOADDR_PSE ((uint32_t)0x08000000U) /* Preamble Suppression Enable */ + +/** Bit definition for ETH_MACMDIODATA register **/ +#define ETH_MACMDIODATA_GD ((uint32_t)0x0000FFFFU) /* GMII/MII Data */ +#define ETH_MACMDIODATA_RA ((uint32_t)0xFFFF0000U) /* Register Address */ + +/** Bit definition for ETH_MACARPADDR register **/ +#define ETH_MACARPADDR_ARPPA ((uint32_t)0xFFFFFFFFU) /* ARP Protocol Address */ + +/** Bit definition for ETH_MACCSRSWCTRL register **/ +#define ETH_MACCSRSWCTRL_RCWE ((uint32_t)0x00000001U) /* Register Clear on Write 1 Enable */ +#define ETH_MACCSRSWCTRL_SEEN ((uint32_t)0x00000100U) /* Slave Error Response Enable */ + +/** Bit definition for ETH_MACPTNS register **/ +#define ETH_MACPTNS_MPTN ((uint32_t)0xFFFFFFFFU) /* MAC 1722 Presentation Time in ns */ + +/** Bit definition for ETH_MACPTUPDT register **/ +#define ETH_MACPTUPDT_MPTN ((uint32_t)0xFFFFFFFFU) /* MAC 1722 Presentation Time Update */ + +/** Bit definition for ETH_MACADDR0H register **/ +#define ETH_MACADDR0H_ADDRHI ((uint32_t)0x0000FFFFU) /* MAC Address0[47:32] */ +#define ETH_MACADDR0H_AE ((uint32_t)0x80000000U) /* Address Enable */ + +/** Bit definition for ETH_MACADDR0L register **/ +#define ETH_MACADDR0L_ADDRLO ((uint32_t)0xFFFFFFFFU) /* MAC Address0[31:0] */ + +/** Bit definition for ETH_MACADDR1H register **/ +#define ETH_MACADDR1H_ADDRHI ((uint32_t)0x0000FFFFU) /* MAC Address1[47:32] */ +#define ETH_MACADDR1H_MBC ((uint32_t)0x3F000000U) /* MBC[5:0]: Mask Byte Control */ +#define ETH_MACADDR1H_MBC_0 ((uint32_t)0x01000000U) /* MBC bit 0 */ +#define ETH_MACADDR1H_MBC_1 ((uint32_t)0x02000000U) /* MBC bit 1 */ +#define ETH_MACADDR1H_MBC_2 ((uint32_t)0x04000000U) /* MBC bit 2 */ +#define ETH_MACADDR1H_MBC_3 ((uint32_t)0x08000000U) /* MBC bit 3 */ +#define ETH_MACADDR1H_MBC_4 ((uint32_t)0x10000000U) /* MBC bit 4 */ +#define ETH_MACADDR1H_MBC_5 ((uint32_t)0x20000000U) /* MBC bit 5 */ +#define ETH_MACADDR1H_SA ((uint32_t)0x40000000U) /* Source Address */ +#define ETH_MACADDR1H_AE ((uint32_t)0x80000000U) /* Address Enable */ + +/** Bit definition for ETH_MACADDR1L register **/ +#define ETH_MACADDR1L_ADDRLO ((uint32_t)0xFFFFFFFFU) /* MAC Address1[31:0] */ + +/** Bit definition for ETH_MACADDR2H register **/ +#define ETH_MACADDR2H_ADDRHI ((uint32_t)0x0000FFFFU) /* MAC Address2[47:32] */ +#define ETH_MACADDR2H_MBC ((uint32_t)0x3F000000U) /* MBC[5:0]: Mask Byte Control */ +#define ETH_MACADDR2H_MBC_0 ((uint32_t)0x01000000U) /* MBC bit 0 */ +#define ETH_MACADDR2H_MBC_1 ((uint32_t)0x02000000U) /* MBC bit 1 */ +#define ETH_MACADDR2H_MBC_2 ((uint32_t)0x04000000U) /* MBC bit 2 */ +#define ETH_MACADDR2H_MBC_3 ((uint32_t)0x08000000U) /* MBC bit 3 */ +#define ETH_MACADDR2H_MBC_4 ((uint32_t)0x10000000U) /* MBC bit 4 */ +#define ETH_MACADDR2H_MBC_5 ((uint32_t)0x20000000U) /* MBC bit 5 */ +#define ETH_MACADDR2H_SA ((uint32_t)0x40000000U) /* Source Address */ +#define ETH_MACADDR2H_AE ((uint32_t)0x80000000U) /* Address Enable */ + +/** Bit definition for ETH_MACADDR2L register **/ +#define ETH_MACADDR2L_ADDRLO ((uint32_t)0xFFFFFFFFU) /* MAC Address2[31:0] */ + +/** Bit definition for ETH_MACADDR3H register **/ +#define ETH_MACADDR3H_ADDRHI ((uint32_t)0x0000FFFFU) /* MAC Address3[47:32] */ +#define ETH_MACADDR3H_MBC ((uint32_t)0x3F000000U) /* MBC[5:0]: Mask Byte Control */ +#define ETH_MACADDR3H_MBC_0 ((uint32_t)0x01000000U) /* MBC bit 0 */ +#define ETH_MACADDR3H_MBC_1 ((uint32_t)0x02000000U) /* MBC bit 1 */ +#define ETH_MACADDR3H_MBC_2 ((uint32_t)0x04000000U) /* MBC bit 2 */ +#define ETH_MACADDR3H_MBC_3 ((uint32_t)0x08000000U) /* MBC bit 3 */ +#define ETH_MACADDR3H_MBC_4 ((uint32_t)0x10000000U) /* MBC bit 4 */ +#define ETH_MACADDR3H_MBC_5 ((uint32_t)0x20000000U) /* MBC bit 5 */ +#define ETH_MACADDR3H_SA ((uint32_t)0x40000000U) /* Source Address */ +#define ETH_MACADDR3H_AE ((uint32_t)0x80000000U) /* Address Enable */ + +/** Bit definition for ETH_MACADDR3L register **/ +#define ETH_MACADDR3L_ADDRLO ((uint32_t)0xFFFFFFFFU) /* MAC Address3[31:0] */ + +/** Bit definition for ETH_MMCCTRL register **/ +#define ETH_MMCCTRL_CNTRST ((uint32_t)0x00000001U) /* Counters Reset */ +#define ETH_MMCCTRL_CNTSTOPRO ((uint32_t)0x00000002U) /* Counter Stop Rollover */ +#define ETH_MMCCTRL_RSTONRD ((uint32_t)0x00000004U) /* Reset on Read */ +#define ETH_MMCCTRL_CNTFREEZ ((uint32_t)0x00000008U) /* MMC Counter Freeze */ +#define ETH_MMCCTRL_CNTPRST ((uint32_t)0x00000010U) /* Counters Preset */ +#define ETH_MMCCTRL_CNTPRSTLVL ((uint32_t)0x00000020U) /* Full-Half Preset */ +#define ETH_MMCCTRL_UCDBC ((uint32_t)0x00000100U) /* Update MMC Counters for Dropped Broadcast Packets */ + +/** Bit definition for ETH_MMCRXINT register **/ +#define ETH_MMCRXINT_RXBCGPIS ((uint32_t)0x00000008U) /* MMC RX Broadcast Good Packet Counter Interrupt Status */ +#define ETH_MMCRXINT_RXMCGPIS ((uint32_t)0x00000010U) /* MMC RX Multicast Good Packet Counter Interrupt Status */ +#define ETH_MMCRXINT_RXCRCERPIS ((uint32_t)0x00000020U) /* MMC RX CRC Error Packet Counter Interrupt Status */ +#define ETH_MMCRXINT_RXALGNERPIS ((uint32_t)0x00000040U) /* MMC RX Alignment Error Packet Counter Interrupt Status */ +#define ETH_MMCRXINT_RXUCGPIS ((uint32_t)0x00020000U) /* MMC RX Unicast Good Packet Counter Interrupt Status */ +#define ETH_MMCRXINT_RXLPIUSCIS ((uint32_t)0x04000000U) /* MMC Receive LPI microsecond counter interrupt status */ +#define ETH_MMCRXINT_RXLPITRCIS ((uint32_t)0x08000000U) /* MMC Receive LPI transition counter interrupt status */ + +/** Bit definition for ETH_MMCTXINT register **/ +#define ETH_MMCTXINT_TXSCOLGPIS ((uint32_t)0x00004000U) /* MMC TX Single Collision Good Packet Counter Interrupt Status */ +#define ETH_MMCTXINT_TXMCOLGPIS ((uint32_t)0x00008000U) /* MMC TX Multiple Collision Good Packet Counter Interrupt Status */ +#define ETH_MMCTXINT_TXGPKTIS ((uint32_t)0x00200000U) /* MMC TX Good Packet Counter Interrupt Status */ +#define ETH_MMCTXINT_TXLPIUSCIS ((uint32_t)0x04000000U) /* MMC Transmit LPI microsecond counter interrupt status */ +#define ETH_MMCTXINT_TXLPITRCIS ((uint32_t)0x08000000U) /* MMC Transmit LPI transition counter interrupt status */ + +/** Bit definition for ETH_MMCRXINTMSK register **/ +#define ETH_MMCRXINTMSK_RXBCGPIM ((uint32_t)0x00000008U) /* MMC RX Broadcast Good Packet Counter Interrupt Mask */ +#define ETH_MMCRXINTMSK_RXMCGPIM ((uint32_t)0x00000010U) /* MMC RX Multicast Good Packet Counter Interrupt Mask */ +#define ETH_MMCRXINTMSK_RXCRCERPIM ((uint32_t)0x00000020U) /* MMC RX CRC Error Packet Counter Interrupt Mask */ +#define ETH_MMCRXINTMSK_RXALGNERPIM ((uint32_t)0x00000040U) /* MMC RX Alignment Error Packet Counter Interrupt Mask */ +#define ETH_MMCRXINTMSK_RXUCGPIM ((uint32_t)0x00020000U) /* MMC RX Unicast Good Packet Counter Interrupt Mask */ +#define ETH_MMCRXINTMSK_RXLPIUSCIM ((uint32_t)0x04000000U) /* MMC Receive LPI microsecond counter interrupt Mask */ +#define ETH_MMCRXINTMSK_RXLPITRCIM ((uint32_t)0x08000000U) /* MMC Receive LPI transition counter interrupt Mask */ + +/** Bit definition for ETH_MMCTXINTMSK register **/ +#define ETH_MMCTXINTMSK_TXSCOLGPIM ((uint32_t)0x00004000U) /* MMC TX Single Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMCTXINTMSK_TXMCOLGPIM ((uint32_t)0x00008000U) /* MMC TX Multiple Collision Good Packet Counter Interrupt Mask */ +#define ETH_MMCTXINTMSK_TXGPKTIM ((uint32_t)0x00200000U) /* MMC TX Good Packet Counter Interrupt Mask */ +#define ETH_MMCTXINTMSK_TXLPIUSCIM ((uint32_t)0x04000000U) /* MMC Transmit LPI microsecond counter interrupt Mask */ +#define ETH_MMCTXINTMSK_TXLPITRCIM ((uint32_t)0x08000000U) /* MMC Transmit LPI transition counter interrupt Mask */ + +/** Bit definition for ETH_MMCTXSCGP register **/ +#define ETH_MMCTXSCGP_TXSNGLCOLG ((uint32_t)0xFFFFFFFFU) /* Tx Single Collision Good Packets */ + +/** Bit definition for ETH_MMCTXMCGP register **/ +#define ETH_MMCTXMCGP_TXMULTCOLG ((uint32_t)0xFFFFFFFFU) /* Tx Multiple Collision Good Packets */ + +/** Bit definition for ETH_MMCTXPCG register **/ +#define ETH_MMCTXPCG_TXPKTG ((uint32_t)0xFFFFFFFFU) /* Tx Packet Count Good */ + +/** Bit definition for ETH_MMCRXBPG register **/ +#define ETH_MMCRXBPG_RXBCASTG ((uint32_t)0xFFFFFFFFU) /* Rx Broadcast Packets Good */ + +/** Bit definition for ETH_MMCRXMPG register **/ +#define ETH_MMCRXMPG_RXMCASTG ((uint32_t)0xFFFFFFFFU) /* Rx Multicast Packets Good */ + +/** Bit definition for ETH_MMCRXCRCEP register **/ +#define ETH_MMCRXCRCEP_RXCRCERR ((uint32_t)0xFFFFFFFFU) /* Rx CRC Error Packets */ + +/** Bit definition for ETH_MMCRXAEP register **/ +#define ETH_MMCRXAEP_RXALGNERR ((uint32_t)0xFFFFFFFFU) /* Rx Alignment Error Packets */ + +/** Bit definition for ETH_MMCRXUPG register **/ +#define ETH_MMCRXUPG_RXUCASTG ((uint32_t)0xFFFFFFFFU) /* Rx Unicast Packets Good */ + +/** Bit definition for ETH_MMCTXLPIUS register **/ +#define ETH_MMCTXLPIUS_TXLPIUSC ((uint32_t)0xFFFFFFFFU) /* Tx LPI Microseconds Counter */ + +/** Bit definition for ETH_MMCTXLPITRAN register **/ +#define ETH_MMCTXLPITRAN_TXLPITRC ((uint32_t)0xFFFFFFFFU) /* Tx LPI Transition Counter */ + +/** Bit definition for ETH_MMCRXLPIUS register **/ +#define ETH_MMCRXLPIUS_RXLPIUSC ((uint32_t)0xFFFFFFFFU) /* Rx LPI Microseconds Counter */ + +/** Bit definition for ETH_MMCRXLPITRAN register **/ +#define ETH_MMCRXLPITRAN_RXLPITRC ((uint32_t)0xFFFFFFFFU) /* Rx LPI Transition Counter */ + +/** Bit definition for ETH_MMCIPCRXINTMSK register **/ +#define ETH_MMCIPCRXINTMSK_RXIPV4GPIM ((uint32_t)0x00000001U) /* MMC Receive IPV4 Good Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXIPV6GPIM ((uint32_t)0x00000020U) /* MMC Receive IPV6 Good Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXUDPGPIM ((uint32_t)0x00000100U) /* MMC Receive UDP Good Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXUDPERPIM ((uint32_t)0x00000200U) /* MMC Receive UDP Error Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXTCPGPIM ((uint32_t)0x00000400U) /* MMC Receive TCP Good Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXTCPERPIM ((uint32_t)0x00000800U) /* MMC Receive TCP Error Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXICMPGPIM ((uint32_t)0x00001000U) /* MMC Receive ICMP Good Packet Counter Interrupt Mask */ +#define ETH_MMCIPCRXINTMSK_RXICMPERPIM ((uint32_t)0x00002000U) /* MMC Receive ICMP Error Packet Counter Interrupt Mask */ + +/** Bit definition for ETH_MMCIPCRXINT register **/ +#define ETH_MMCIPCRXINT_RXIPV4GPIS ((uint32_t)0x00000001U) /* MMC Receive IPV4 Good Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXIPV6GPIS ((uint32_t)0x00000020U) /* MMC Receive IPV6 Good Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXUDPGPIS ((uint32_t)0x00000100U) /* MMC Receive UDP Good Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXUDPERPIS ((uint32_t)0x00000200U) /* MMC Receive UDP Error Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXTCPGPIS ((uint32_t)0x00000400U) /* MMC Receive TCP Good Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXTCPERPIS ((uint32_t)0x00000800U) /* MMC Receive TCP Error Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXICMPGPIS ((uint32_t)0x00001000U) /* MMC Receive ICMP Good Packet Counter Interrupt Status */ +#define ETH_MMCIPCRXINT_RXICMPERPIS ((uint32_t)0x00002000U) /* MMC Receive ICMP Error Packet Counter Interrupt Status */ + +/** Bit definition for ETH_MMCRXIPV4GP register **/ +#define ETH_MMCRXIPV4GP_RXIPV4GDPKT ((uint32_t)0xFFFFFFFFU) /* RxIPv4 Good Packets */ + +/** Bit definition for ETH_MMCRXIPV6GP register **/ +#define ETH_MMCRXIPV6GP_RXIPV6GDPKT ((uint32_t)0xFFFFFFFFU) /* RxIPv6 Good Packets */ + +/** Bit definition for ETH_MMCRXUDPGP register **/ +#define ETH_MMCRXUDPGP_RXUDPGDPKT ((uint32_t)0xFFFFFFFFU) /* RxUDP Good Packets */ + +/** Bit definition for ETH_MMCRXUDPEP register **/ +#define ETH_MMCRXUDPEP_RXUDPERRPKT ((uint32_t)0xFFFFFFFFU) /* RxUDP Error Packets */ + +/** Bit definition for ETH_MMCRXTCPGP register **/ +#define ETH_MMCRXTCPGP_RXTCPGDPKT ((uint32_t)0xFFFFFFFFU) /* RxTCP Good Packets */ + +/** Bit definition for ETH_MMCRXTCPEP register **/ +#define ETH_MMCRXTCPEP_RXTCPERRPKT ((uint32_t)0xFFFFFFFFU) /* RxTCP Error Packets */ + +/** Bit definition for ETH_MMCRXICMPGP register **/ +#define ETH_MMCRXICMPGP_RXICMPGDPKT ((uint32_t)0xFFFFFFFFU) /* RxICMP Good Packets */ + +/** Bit definition for ETH_MMCRXICMPEP register **/ +#define ETH_MMCRXICMPEP_RXICMPERRPKT ((uint32_t)0xFFFFFFFFU) /* RxICMP Error Packets */ + +/** Bit definition for ETH_MACL3L4F0CTRL register **/ +#define ETH_MACL3L4F0CTRL_L3PEN ((uint32_t)0x00000001U) /* Layer 3 Protocol Enable */ +#define ETH_MACL3L4F0CTRL_L3SAM ((uint32_t)0x00000004U) /* Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4F0CTRL_L3SAIM ((uint32_t)0x00000008U) /* Layer 3 IP SA Inverse Match Enable */ +#define ETH_MACL3L4F0CTRL_L3DAM ((uint32_t)0x00000010U) /* Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4F0CTRL_L3DAIM ((uint32_t)0x00000020U) /* Layer 3 IP DA Inverse Match Enable */ +#define ETH_MACL3L4F0CTRL_L3HSBM ((uint32_t)0x000007C0U) /* L3HSBM[4:0]: Layer 3 IP SA Higher Bits Match */ +#define ETH_MACL3L4F0CTRL_L3HSBM_0 ((uint32_t)0x00000040U) /* L3HSBM bit 0 */ +#define ETH_MACL3L4F0CTRL_L3HSBM_1 ((uint32_t)0x00000080U) /* L3HSBM bit 1 */ +#define ETH_MACL3L4F0CTRL_L3HSBM_2 ((uint32_t)0x00000100U) /* L3HSBM bit 2 */ +#define ETH_MACL3L4F0CTRL_L3HSBM_3 ((uint32_t)0x00000200U) /* L3HSBM bit 3 */ +#define ETH_MACL3L4F0CTRL_L3HSBM_4 ((uint32_t)0x00000400U) /* L3HSBM bit 4 */ +#define ETH_MACL3L4F0CTRL_L3HDBM ((uint32_t)0x0000F800U) /* L3HDBM[4:0]: Layer 3 IP DA Higher Bits Match */ +#define ETH_MACL3L4F0CTRL_L3HDBM_0 ((uint32_t)0x00000800U) /* L3HDBM bit 0 */ +#define ETH_MACL3L4F0CTRL_L3HDBM_1 ((uint32_t)0x00001000U) /* L3HDBM bit 1 */ +#define ETH_MACL3L4F0CTRL_L3HDBM_2 ((uint32_t)0x00002000U) /* L3HDBM bit 2 */ +#define ETH_MACL3L4F0CTRL_L3HDBM_3 ((uint32_t)0x00004000U) /* L3HDBM bit 3 */ +#define ETH_MACL3L4F0CTRL_L3HDBM_4 ((uint32_t)0x00008000U) /* L3HDBM bit 4 */ +#define ETH_MACL3L4F0CTRL_L4PEN ((uint32_t)0x00010000U) /* Layer 4 Protocol Enable */ +#define ETH_MACL3L4F0CTRL_L4SPM ((uint32_t)0x00040000U) /* Layer 4 Source Port Match Enable */ +#define ETH_MACL3L4F0CTRL_L4SPIM ((uint32_t)0x00080000U) /* Layer 4 Source Port Inverse Match Enable */ +#define ETH_MACL3L4F0CTRL_L4DPM ((uint32_t)0x00100000U) /* Layer 4 Destination Port Match Enable */ +#define ETH_MACL3L4F0CTRL_L4DPIM ((uint32_t)0x00200000U) /* Layer 4 Destination Port Inverse Match Enable */ + +/** Bit definition for ETH_MACL4F0PORT register **/ +#define ETH_MACL4F0PORT_L4SP ((uint32_t)0x0000FFFFU) /* Layer 4 Source Port Number Field */ +#define ETH_MACL4F0PORT_L4DP ((uint32_t)0xFFFF0000U) /* Layer 4 Destination Port Number Field */ + +/** Bit definition for ETH_MACL3F0ADDR0 register **/ +#define ETH_MACL3F0ADDR0_L3A0 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 0 Field */ + +/** Bit definition for ETH_MACL3F0ADDR1 register **/ +#define ETH_MACL3F0ADDR1_L3A1 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 1 Field */ + +/** Bit definition for ETH_MACL3F0ADDR2 register **/ +#define ETH_MACL3F0ADDR2_L3A2 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 2 Field */ + +/** Bit definition for ETH_MACL3F0ADDR3 register **/ +#define ETH_MACL3F0ADDR3_L3A3 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 3 Field */ + +/** Bit definition for ETH_MACL3L4F1CTRL register **/ +#define ETH_MACL3L4F1CTRL_L3PEN ((uint32_t)0x00000001U) /* Layer 3 Protocol Enable */ +#define ETH_MACL3L4F1CTRL_L3SAM ((uint32_t)0x00000004U) /* Layer 3 IP SA Match Enable */ +#define ETH_MACL3L4F1CTRL_L3SAIM ((uint32_t)0x00000008U) /* Layer 3 IP SA Inverse Match Enable */ +#define ETH_MACL3L4F1CTRL_L3DAM ((uint32_t)0x00000010U) /* Layer 3 IP DA Match Enable */ +#define ETH_MACL3L4F1CTRL_L3DAIM ((uint32_t)0x00000020U) /* Layer 3 IP DA Inverse Match Enable */ +#define ETH_MACL3L4F1CTRL_L3HSBM ((uint32_t)0x000007C0U) /* L3HSBM[4:0]: Layer 3 IP SA Higher Bits Match */ +#define ETH_MACL3L4F1CTRL_L3HSBM_0 ((uint32_t)0x00000040U) /* L3HSBM bit 0 */ +#define ETH_MACL3L4F1CTRL_L3HSBM_1 ((uint32_t)0x00000080U) /* L3HSBM bit 1 */ +#define ETH_MACL3L4F1CTRL_L3HSBM_2 ((uint32_t)0x00000100U) /* L3HSBM bit 2 */ +#define ETH_MACL3L4F1CTRL_L3HSBM_3 ((uint32_t)0x00000200U) /* L3HSBM bit 3 */ +#define ETH_MACL3L4F1CTRL_L3HSBM_4 ((uint32_t)0x00000400U) /* L3HSBM bit 4 */ +#define ETH_MACL3L4F1CTRL_L3HDBM ((uint32_t)0x0000F800U) /* L3HDBM[4:0]: Layer 3 IP DA Higher Bits Match */ +#define ETH_MACL3L4F1CTRL_L3HDBM_0 ((uint32_t)0x00000800U) /* L3HDBM bit 0 */ +#define ETH_MACL3L4F1CTRL_L3HDBM_1 ((uint32_t)0x00001000U) /* L3HDBM bit 1 */ +#define ETH_MACL3L4F1CTRL_L3HDBM_2 ((uint32_t)0x00002000U) /* L3HDBM bit 2 */ +#define ETH_MACL3L4F1CTRL_L3HDBM_3 ((uint32_t)0x00004000U) /* L3HDBM bit 3 */ +#define ETH_MACL3L4F1CTRL_L3HDBM_4 ((uint32_t)0x00008000U) /* L3HDBM bit 4 */ +#define ETH_MACL3L4F1CTRL_L4PEN ((uint32_t)0x00010000U) /* Layer 4 Protocol Enable */ +#define ETH_MACL3L4F1CTRL_L4SPM ((uint32_t)0x00040000U) /* Layer 4 Source Port Match Enable */ +#define ETH_MACL3L4F1CTRL_L4SPIM ((uint32_t)0x00080000U) /* Layer 4 Source Port Inverse Match Enable */ +#define ETH_MACL3L4F1CTRL_L4DPM ((uint32_t)0x00100000U) /* Layer 4 Destination Port Match Enable */ +#define ETH_MACL3L4F1CTRL_L4DPIM ((uint32_t)0x00200000U) /* Layer 4 Destination Port Inverse Match Enable */ + +/** Bit definition for ETH_MACL4F1PORT register **/ +#define ETH_MACL4F1PORT_L4SP ((uint32_t)0x0000FFFFU) /* Layer 4 Source Port Number Field */ +#define ETH_MACL4F1PORT_L4DP ((uint32_t)0xFFFF0000U) /* Layer 4 Destination Port Number Field */ + +/** Bit definition for ETH_MACL3F1ADDR0 register **/ +#define ETH_MACL3F1ADDR0_L3A0 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 0 Field */ + +/** Bit definition for ETH_MACL3F1ADDR1 register **/ +#define ETH_MACL3F1ADDR1_L3A1 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 1 Field */ + +/** Bit definition for ETH_MACL3F1ADDR2 register **/ +#define ETH_MACL3F1ADDR2_L3A2 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 2 Field */ + +/** Bit definition for ETH_MACL3F1ADDR3 register **/ +#define ETH_MACL3F1ADDR3_L3A3 ((uint32_t)0xFFFFFFFFU) /* Layer 3 Address 3 Field */ + +/** Bit definition for ETH_MACTSCTRL register **/ +#define ETH_MACTSCTRL_TSENA ((uint32_t)0x00000001U) /* Enable Timestamp */ +#define ETH_MACTSCTRL_TSCFUPDT ((uint32_t)0x00000002U) /* Fine or Coarse Timestamp Update */ +#define ETH_MACTSCTRL_TSINIT ((uint32_t)0x00000004U) /* Initialize Timestamp */ +#define ETH_MACTSCTRL_TSUPDT ((uint32_t)0x00000008U) /* Update Timestamp */ +#define ETH_MACTSCTRL_TSADDREG ((uint32_t)0x00000020U) /* Update Addend Register */ +#define ETH_MACTSCTRL_PTGE ((uint32_t)0x00000040U) /* Presentation Time Generation Enable */ +#define ETH_MACTSCTRL_TSENALL ((uint32_t)0x00000100U) /* Enable Timestamp for All Packets */ +#define ETH_MACTSCTRL_TSCTRLSSR ((uint32_t)0x00000200U) /* Timestamp Digital or Binary Rollover Control */ +#define ETH_MACTSCTRL_TSVER2ENA ((uint32_t)0x00000400U) /* Enable PTP Packet Processing for Version 2 Format */ +#define ETH_MACTSCTRL_TSIPENA ((uint32_t)0x00000800U) /* Enable Processing of PTP over Ethernet Packets */ +#define ETH_MACTSCTRL_TSIPV6ENA ((uint32_t)0x00001000U) /* Enable Processing of PTP Packets Sent over IPv6-UDP */ +#define ETH_MACTSCTRL_TSIPV4ENA ((uint32_t)0x00002000U) /* Enable Processing of PTP Packets Sent over IPv4-UDP */ +#define ETH_MACTSCTRL_TSEVNTENA ((uint32_t)0x00004000U) /* Enable Timestamp Snapshot for Event Messages */ +#define ETH_MACTSCTRL_TSMSTRENA ((uint32_t)0x00008000U) /* Enable Snapshot for Messages Relevant to Master */ +#define ETH_MACTSCTRL_SNAPTYPSEL ((uint32_t)0x00030000U) /* Select PTP packets for Taking Snapshots */ +#define ETH_MACTSCTRL_TSENMACADDR ((uint32_t)0x00040000U) /* Enable MAC Address for PTP Packet Filtering */ +#define ETH_MACTSCTRL_TXTSSTSM ((uint32_t)0x01000000U) /* Transmit Timestamp Status Mode */ +#define ETH_MACTSCTRL_AV8021ASMEN ((uint32_t)0x10000000U) /* AV 802.1AS Mode Enable */ + +/** Bit definition for ETH_MACSUBSINC register **/ +#define ETH_MACSUBSINC_SSINC ((uint32_t)0x00FF0000U) /* Sub-second Increment Value */ + +/** Bit definition for ETH_MACSYSTS register **/ +#define ETH_MACSYSTS_TSS ((uint32_t)0xFFFFFFFFU) /* Timestamp Second */ + +/** Bit definition for ETH_MACSYSTNS register **/ +#define ETH_MACSYSTNS_TSSS ((uint32_t)0x7FFFFFFFU) /* Timestamp Sub Seconds */ + +/** Bit definition for ETH_MACSYSTSUP register **/ +#define ETH_MACSYSTSUP_TSS ((uint32_t)0xFFFFFFFFU) /* Timestamp Seconds */ + +/** Bit definition for ETH_MACSYSTNSUP register **/ +#define ETH_MACSYSTNSUP_TSSS ((uint32_t)0x7FFFFFFFU) /* Timestamp Sub Seconds */ +#define ETH_MACSYSTNSUP_ADDSUB ((uint32_t)0x80000000U) /* Add or Subtract Time */ + +/** Bit definition for ETH_MACTSADD register **/ +#define ETH_MACTSADD_TSAR ((uint32_t)0xFFFFFFFFU) /* Timestamp Addend Register */ + +/** Bit definition for ETH_MACSYSTHWS register **/ +#define ETH_MACSYSTHWS_TSHWR ((uint32_t)0x0000FFFFU) /* Timestamp Higher Word Register */ + +/** Bit definition for ETH_MACTSSTS register **/ +#define ETH_MACTSSTS_TSSOVF ((uint32_t)0x00000001U) /* Timestamp Seconds Overflow */ +#define ETH_MACTSSTS_TSTARGT0 ((uint32_t)0x00000002U) /* Timestamp Target Time Reached */ +#define ETH_MACTSSTS_AUXTSTRIG ((uint32_t)0x00000004U) /* Auxiliary Timestamp Trigger Snapshot */ +#define ETH_MACTSSTS_TSTRGTERR0 ((uint32_t)0x00000008U) /* Timestamp Target Time Error */ +#define ETH_MACTSSTS_TXTSSIS ((uint32_t)0x00008000U) /* Tx Timestamp Status Interrupt Status */ +#define ETH_MACTSSTS_ATSSTN ((uint32_t)0x000F0000U) /* ATSSTN[3:0]: Auxiliary Timestamp Snapshot Trigger Identifier */ +#define ETH_MACTSSTS_ATSSTN_0 ((uint32_t)0x00010000U) /* ATSSTN bit 0 */ +#define ETH_MACTSSTS_ATSSTN_1 ((uint32_t)0x00020000U) /* ATSSTN bit 1 */ +#define ETH_MACTSSTS_ATSSTN_2 ((uint32_t)0x00040000U) /* ATSSTN bit 2 */ +#define ETH_MACTSSTS_ATSSTN_3 ((uint32_t)0x00080000U) /* ATSSTN bit 3 */ +#define ETH_MACTSSTS_ATSSTM ((uint32_t)0x01000000U) /* Auxiliary Timestamp Snapshot Trigger Missed */ +#define ETH_MACTSSTS_ATSNS ((uint32_t)0x3E000000U) /* Number of Auxiliary Timestamp Snapshots */ + +/** Bit definition for ETH_MACTXTSSTSNS register **/ +#define ETH_MACTXTSSTSNS_TXTSSLO ((uint32_t)0x7FFFFFFFU) /* Number of Auxiliary Timestamp Snapshots */ +#define ETH_MACTXTSSTSNS_TXTSSMIS ((uint32_t)0x80000000U) /* Transmit Timestamp Status Missed */ + +/** Bit definition for ETH_MACTXTSSTSS register **/ +#define ETH_MACTXTSSTSS_TXTSSHI ((uint32_t)0xFFFFFFFFU) /* Transmit Timestamp Status High */ + +/** Bit definition for ETH_MACAUXCTRL register **/ +#define ETH_MACAUXCTRL_ATSFC ((uint32_t)0x00000001U) /* Auxiliary Snapshot FIFO Clear */ +#define ETH_MACAUXCTRL_ATSEN0 ((uint32_t)0x00000010U) /* Auxiliary Snapshot 0 Enable */ +#define ETH_MACAUXCTRL_ATSEN1 ((uint32_t)0x00000020U) /* Auxiliary Snapshot 1 Enable */ +#define ETH_MACAUXCTRL_ATSEN2 ((uint32_t)0x00000040U) /* Auxiliary Snapshot 2 Enable */ +#define ETH_MACAUXCTRL_ATSEN3 ((uint32_t)0x00000080U) /* Auxiliary Snapshot 3 Enable */ + +/** Bit definition for ETH_MACAUXTSNS register **/ +#define ETH_MACAUXTSNS_AUXTSLO ((uint32_t)0x7FFFFFFFU) /* Auxiliary Timestamp Nanoseconds */ + +/** Bit definition for ETH_MACAUXTSS register **/ +#define ETH_MACAUXTSS_AUXTSHI ((uint32_t)0xFFFFFFFFU) /* Auxiliary Timestamp Seconds */ + +/** Bit definition for ETH_MACTSIGASYC register **/ +#define ETH_MACTSIGASYC_OSTIAC ((uint32_t)0xFFFFFFFFU) /* One-Step Timestamp Ingress Asymmetry Correction */ + +/** Bit definition for ETH_MACTSEGASYC register **/ +#define ETH_MACTSEGASYC_OSTEAC ((uint32_t)0xFFFFFFFFU) /* One-Step Timestamp Egress Asymmetry Correction */ + +/** Bit definition for ETH_MACTSIGCNS register **/ +#define ETH_MACTSIGCNS_TSIC ((uint32_t)0xFFFFFFFFU) /* Timestamp Ingress Correction */ + +/** Bit definition for ETH_MACTSEGCNS register **/ +#define ETH_MACTSEGCNS_TSEC ((uint32_t)0xFFFFFFFFU) /* Timestamp Egress Correction */ + +/** Bit definition for ETH_MACTSIGLAT register **/ +#define ETH_MACTSIGLAT_ITLSNS ((uint32_t)0x0000FF00U) /* Ingress Timestamp Latency, in sub-nanoseconds */ +#define ETH_MACTSIGLAT_ITLNS ((uint32_t)0x0FFF0000U) /* Ingress Timestamp Latency, in nanoseconds */ + +/** Bit definition for ETH_MACTSEGLAT register **/ +#define ETH_MACTSEGLAT_ETLSNS ((uint32_t)0x0000FF00U) /* Egress Timestamp Latency, in sub-nanoseconds */ +#define ETH_MACTSEGLAT_ETLNS ((uint32_t)0x0FFF0000U) /* Egress Timestamp Latency, in nanoseconds */ + +/** Bit definition for ETH_MACPPSCTRL register **/ +#define ETH_MACPPSCTRL_PPSCTRL ((uint32_t)0x0000000FU) /* PPSCTRL[3:0]: PPS Output Frequency Control */ +#define ETH_MACPPSCTRL_PPSCTRL_0 ((uint32_t)0x00000001U) /* PPSCTRL bit 0 */ +#define ETH_MACPPSCTRL_PPSCTRL_1 ((uint32_t)0x00000002U) /* PPSCTRL bit 1 */ +#define ETH_MACPPSCTRL_PPSCTRL_2 ((uint32_t)0x00000004U) /* PPSCTRL bit 2 */ +#define ETH_MACPPSCTRL_PPSCTRL_3 ((uint32_t)0x00000008U) /* PPSCTRL bit 3 */ +#define ETH_MACPPSCTRL_PPSCMD ((uint32_t)0x0000000FU) /* PPSCMD[3:0]: Flexible PPS Output (ptp_pps_o [0]) Control, Presentation Time Control */ +#define ETH_MACPPSCTRL_PPSCMD_0 ((uint32_t)0x00000001U) /* PPSCMD bit 0 */ +#define ETH_MACPPSCTRL_PPSCMD_1 ((uint32_t)0x00000002U) /* PPSCMD bit 1 */ +#define ETH_MACPPSCTRL_PPSCMD_2 ((uint32_t)0x00000004U) /* PPSCMD bit 2 */ +#define ETH_MACPPSCTRL_PPSCMD_3 ((uint32_t)0x00000008U) /* PPSCMD bit 3 */ +#define ETH_MACPPSCTRL_PPSEN0 ((uint32_t)0x00000010U) /* Flexible PPS Output Mode Enable */ +#define ETH_MACPPSCTRL_TRGTMODSEL0 ((uint32_t)0x00000060U) /* TRGTMODSEL0[3:0]: Target Time Register Mode for PPS0 Output */ +#define ETH_MACPPSCTRL_TRGTMODSEL0_0 ((uint32_t)0x00000020U) /* TRGTMODSEL0 bit 0 */ +#define ETH_MACPPSCTRL_TRGTMODSEL0_1 ((uint32_t)0x00000040U) /* TRGTMODSEL0 bit 1 */ +#define ETH_MACPPSCTRL_MCGREN0 ((uint32_t)0x00000080U) /* MCGR Mode Enable for PPS0 Output */ +#define ETH_MACPPSCTRL_TIMESEL ((uint32_t)0x10000000U) /* Time Select */ + +/** Bit definition for ETH_MACPPSTTS register **/ +#define ETH_MACPPSTTS_TSTRH0 ((uint32_t)0xFFFFFFFFU) /* PPS Target Time Seconds Register */ + +/** Bit definition for ETH_MACPPSTTNS register **/ +#define ETH_MACPPSTTNS_TTSL0 ((uint32_t)0x7FFFFFFFU) /* Target Time Low for PPS Register */ +#define ETH_MACPPSTTNS_TRGTBUSY0 ((uint32_t)0x80000000U) /* PPS Target Time Register Busy */ + +/** Bit definition for ETH_MACPPSINTE register **/ +#define ETH_MACPPSINTE_PPSINT0 ((uint32_t)0xFFFFFFFFU) /* PPS Output Signal Interval */ + +/** Bit definition for ETH_MACPPSWID register **/ +#define ETH_MACPPSWID_PPSWIDTH0 ((uint32_t)0xFFFFFFFFU) /* PPS Output Signal Width */ + +/** Bit definition for ETH_MACPTOCTRL register **/ +#define ETH_MACPTOCTRL_PTOEN ((uint32_t)0x00000001U) /* PTP Offload Enable */ +#define ETH_MACPTOCTRL_ASYNCEN ((uint32_t)0x00000002U) /* Automatic PTP SYNC message Enable */ +#define ETH_MACPTOCTRL_APDREQEN ((uint32_t)0x00000004U) /* Automatic PTP Pdelay_Req message Enable */ +#define ETH_MACPTOCTRL_ASYNCTRIG ((uint32_t)0x00000010U) /* Automatic PTP SYNC message Trigger */ +#define ETH_MACPTOCTRL_APDREQTRIG ((uint32_t)0x00000020U) /* Automatic PTP Pdelay_Req message Trigger */ +#define ETH_MACPTOCTRL_DRRDIS ((uint32_t)0x00000040U) /* Disable PTO Delay Request/Response response generation */ +#define ETH_MACPTOCTRL_PDRDIS ((uint32_t)0x00000080U) /* Disable Peer Delay Response response generation */ +#define ETH_MACPTOCTRL_DN ((uint32_t)0x0000FF00U) /* Domain Number */ + +/** Bit definition for ETH_MACSRCPID0 register **/ +#define ETH_MACSRCPID0_SPI0 ((uint32_t)0xFFFFFFFFU) /* Source Port Identity 0 */ + +/** Bit definition for ETH_MACSRCPID1 register **/ +#define ETH_MACSRCPID1_SPI1 ((uint32_t)0xFFFFFFFFU) /* Source Port Identity 1 */ + +/** Bit definition for ETH_MACSRCPID2 register **/ +#define ETH_MACSRCPID2_SPI2 ((uint32_t)0x0000FFFFU) /* Source Port Identity 2 */ + +/** Bit definition for ETH_MACLOGMINTE register **/ +#define ETH_MACLOGMINTE_LSI ((uint32_t)0x000000FFU) /* Log Sync Interval */ +#define ETH_MACLOGMINTE_DRSYNCR ((uint32_t)0x00000700U) /* DRSYNCR[2:0]: Delay_Req to SYNC Ratio */ +#define ETH_MACLOGMINTE_DRSYNCR_0 ((uint32_t)0x00000100U) /* DRSYNCR bit 0 */ +#define ETH_MACLOGMINTE_DRSYNCR_1 ((uint32_t)0x00000200U) /* DRSYNCR bit 1 */ +#define ETH_MACLOGMINTE_DRSYNCR_2 ((uint32_t)0x00000400U) /* DRSYNCR bit 2 */ +#define ETH_MACLOGMINTE_LMPDRI ((uint32_t)0xFF000000U) /* Log Min Pdelay_Req Interval */ + + +/*** Ethernet MTL ***/ + +/** Bit definition for ETH_MTLOPMOD register **/ +#define ETH_MTLOPMOD_DTXSTS ((uint32_t)0x00000002U) /* Drop Transmit Status */ +#define ETH_MTLOPMOD_CNTPRST ((uint32_t)0x00000100U) /* Counters Preset */ +#define ETH_MTLOPMOD_CNTCLR ((uint32_t)0x00000200U) /* Counters Reset */ + +/** Bit definition for ETH_MTLINTSTS register **/ +#define ETH_MTLINTSTS_Q0IS ((uint32_t)0x00000001U) /* Queue 0 Interrupt status */ + + +/*** Ethernet MTL Queue ***/ + +/** Bit definition for ETH_MTLTXQOPMOD register **/ +#define ETH_MTLTXQOPMOD_FTQ ((uint32_t)0x00000001U) /* Flush Transmit Queue */ +#define ETH_MTLTXQOPMOD_TSF ((uint32_t)0x00000002U) /* Transmit Store and Forward */ +#define ETH_MTLTXQOPMOD_TTC ((uint32_t)0x00000070U) /* TTC[2:0]: Transmit Threshold Control */ +#define ETH_MTLTXQOPMOD_TTC_0 ((uint32_t)0x00000010U) /* TTC bit 0 */ +#define ETH_MTLTXQOPMOD_TTC_1 ((uint32_t)0x00000020U) /* TTC bit 1 */ +#define ETH_MTLTXQOPMOD_TTC_2 ((uint32_t)0x00000040U) /* TTC bit 2 */ + +/** Bit definition for ETH_MTLTXQUDF register **/ +#define ETH_MTLTXQUDF_UFFRMCNT ((uint32_t)0x000007FFU) /* Underflow Packet Counter */ +#define ETH_MTLTXQUDF_UFCNTOVF ((uint32_t)0x00000800U) /* Overflow Bit for Underflow Packet Counter */ + +/** Bit definition for ETH_MTLTXQDBG register **/ +#define ETH_MTLTXQDBG_TXQPAUSED ((uint32_t)0x00000001U) /* Transmit Queue in Pause */ +#define ETH_MTLTXQDBG_TRCSTS ((uint32_t)0x00000006U) /* TRCSTS[1:0]: MTL Tx Queue Read Controller Status */ +#define ETH_MTLTXQDBG_TRCSTS_0 ((uint32_t)0x00000002U) /* TRCSTS bit 0 */ +#define ETH_MTLTXQDBG_TRCSTS_1 ((uint32_t)0x00000004U) /* TRCSTS bit 1 */ +#define ETH_MTLTXQDBG_TWCSTS ((uint32_t)0x00000008U) /* MTL Tx Queue Write Controller Status */ +#define ETH_MTLTXQDBG_TXQSTS ((uint32_t)0x00000010U) /* MTL Tx Queue Not Empty Status */ +#define ETH_MTLTXQDBG_TXSTSFSTS ((uint32_t)0x00000020U) /* MTL Tx Status FIFO Full Status */ +#define ETH_MTLTXQDBG_PTXQ ((uint32_t)0x00070000U) /* Number of Packets in the Transmit Queue */ +#define ETH_MTLTXQDBG_STXSTSF ((uint32_t)0x00700000U) /* Number of Status Words in Tx Status FIFO of Queue */ + +/** Bit definition for ETH_MTLQINTCTRLSTS register **/ +#define ETH_MTLQINTCTRLSTS_TXUNFIS ((uint32_t)0x00000001U) /* Transmit Queue Underflow Interrupt Status */ +#define ETH_MTLQINTCTRLSTS_TXUIE ((uint32_t)0x00000100U) /* Transmit Queue Underflow Interrupt Enable */ +#define ETH_MTLQINTCTRLSTS_RXOVFIS ((uint32_t)0x00010000U) /* Receive Queue Overflow Interrupt Status */ +#define ETH_MTLQINTCTRLSTS_RXOIE ((uint32_t)0x01000000U) /* Receive Queue Overflow Interrupt Enable */ + +/** Bit definition for ETH_MTLRXQOPMOD register **/ +#define ETH_MTLRXQOPMOD_RTC ((uint32_t)0x00000003U) /* RTC[1:0]: Receive Queue Threshold Control */ +#define ETH_MTLRXQOPMOD_RTC_0 ((uint32_t)0x00000001U) /* RTC bit 0 */ +#define ETH_MTLRXQOPMOD_RTC_1 ((uint32_t)0x00000002U) /* RTC bit 1 */ +#define ETH_MTLRXQOPMOD_FUP ((uint32_t)0x00000008U) /* Forward Undersized Good Packets */ +#define ETH_MTLRXQOPMOD_FEP ((uint32_t)0x00000010U) /* Forward Error Packets */ +#define ETH_MTLRXQOPMOD_RSF ((uint32_t)0x00000020U) /* Receive Queue Store and Forward */ +#define ETH_MTLRXQOPMOD_DISTCPEF ((uint32_t)0x00000040U) /* Disable Dropping of TCP/IP Checksum Error Packets */ + +/** Bit definition for ETH_MTLRXQMPOFCNT register **/ +#define ETH_MTLRXQMPOFCNT_OVFPKTCNT ((uint32_t)0x000007FFU) /* Overflow Packet Counter */ +#define ETH_MTLRXQMPOFCNT_OVFCNTOVF ((uint32_t)0x00000800U) /* Overflow Counter Overflow Bit */ +#define ETH_MTLRXQMPOFCNT_MISPKTCNT ((uint32_t)0x07FF0000U) /* Missed Packet Counter */ +#define ETH_MTLRXQMPOFCNT_MISCNTOVF ((uint32_t)0x08000000U) /* Missed Packet Counter Overflow Bit */ + +/** Bit definition for ETH_MTLRXQDBG register **/ +#define ETH_MTLRXQDBG_RWCSTS ((uint32_t)0x00000001U) /* MTL Rx Queue Write Controller Active Status */ +#define ETH_MTLRXQDBG_RRCSTS ((uint32_t)0x00000006U) /* RRCSTS[1:0]: MTL Rx Queue Read Controller State */ +#define ETH_MTLRXQDBG_RRCSTS_0 ((uint32_t)0x00000002U) /* RRCSTS bit 0 */ +#define ETH_MTLRXQDBG_RRCSTS_1 ((uint32_t)0x00000004U) /* RRCSTS bit 1 */ +#define ETH_MTLRXQDBG_RXQSTS ((uint32_t)0x00000030U) /* RXQSTS[1:0]: MTL Rx Queue Fill-Level Status */ +#define ETH_MTLRXQDBG_RXQSTS_0 ((uint32_t)0x00000010U) /* RXQSTS bit 0 */ +#define ETH_MTLRXQDBG_RXQSTS_1 ((uint32_t)0x00000020U) /* RXQSTS bit 1 */ +#define ETH_MTLRXQDBG_PRXQ ((uint32_t)0x3FFF0000U) /* Number of Packets in Receive Queue */ + + +/*** Ethernet DMA ***/ + +/** Bit definition for ETH_DMAMODE register **/ +#define ETH_DMAMODE_SWR ((uint32_t)0x00000001U) /* Software Reset */ +#define ETH_DMAMODE_DA ((uint32_t)0x00000002U) /* DMA Tx or Rx Arbitration Scheme */ +#define ETH_DMAMODE_TXPR ((uint32_t)0x00000800U) /* Transmit Priority */ +#define ETH_DMAMODE_PR ((uint32_t)0x00007000U) /* PR[2:0]: Priority Ratio */ +#define ETH_DMAMODE_PR_0 ((uint32_t)0x00001000U) /* PR bit 0 */ +#define ETH_DMAMODE_PR_1 ((uint32_t)0x00002000U) /* PR bit 1 */ +#define ETH_DMAMODE_PR_2 ((uint32_t)0x00004000U) /* PR bit 2 */ +#define ETH_DMAMODE_INTM ((uint32_t)0x00030000U) /* INTM[1:0]: Interrupt Mode */ +#define ETH_DMAMODE_INTM_0 ((uint32_t)0x00010000U) /* INTM bit 0 */ +#define ETH_DMAMODE_INTM_1 ((uint32_t)0x00020000U) /* INTM bit 1 */ +#define ETH_DMAMODE_DCHE ((uint32_t)0x00080000U) /* Descriptor Cache Enable */ +#define ETH_DMAMODE_TNDF ((uint32_t)0x00300000U) /* TNDF[1:0]: Tx DMA鈥檚 Maximum Number of Descriptors to be fetched in a burst */ +#define ETH_DMAMODE_TNDF_0 ((uint32_t)0x00100000U) /* TNDF bit 0 */ +#define ETH_DMAMODE_TNDF_1 ((uint32_t)0x00200000U) /* TNDF bit 1 */ +#define ETH_DMAMODE_RNDF ((uint32_t)0x00C00000U) /* RNDF[1:0]: Rx DMA鈥檚 Maximum Number of Descriptors to be fetched in a burst */ +#define ETH_DMAMODE_RNDF_0 ((uint32_t)0x00400000U) /* RNDF bit 0 */ +#define ETH_DMAMODE_RNDF_1 ((uint32_t)0x00800000U) /* RNDF bit 1 */ + +/** Bit definition for ETH_DMASBMODE register **/ +#define ETH_DMASBMODE_FB ((uint32_t)0x00000001U) /* Fixed Burst Length */ +#define ETH_DMASBMODE_AAL ((uint32_t)0x00001000U) /* Address-Aligned Beats */ +#define ETH_DMASBMODE_MB ((uint32_t)0x00004000U) /* Mixed Burst */ +#define ETH_DMASBMODE_RB ((uint32_t)0x00008000U) /* Rebuild INCRx Burst */ + +/** Bit definition for ETH_DMAINTSTS register **/ +#define ETH_DMAINTSTS_DC0IS ((uint32_t)0x00000001U) /* DMA Channel 0 Interrupt Status */ +#define ETH_DMAINTSTS_MTLIS ((uint32_t)0x00010000U) /* MTL Interrupt Status */ +#define ETH_DMAINTSTS_MACIS ((uint32_t)0x00020000U) /* MAC Interrupt Status */ + +/** Bit definition for ETH_DMADBGSTS register **/ +#define ETH_DMADBGSTS_AHBMS ((uint32_t)0x00000001U) /* AHB Master Status */ +#define ETH_DMADBGSTS_RPS0 ((uint32_t)0x00000F00U) /* RPS0[3:0]: DMA Channel 0 Receive Process State */ +#define ETH_DMADBGSTS_RPS0_0 ((uint32_t)0x00000100U) /* RPS0 bit 0 */ +#define ETH_DMADBGSTS_RPS0_1 ((uint32_t)0x00000200U) /* RPS0 bit 1 */ +#define ETH_DMADBGSTS_RPS0_2 ((uint32_t)0x00000400U) /* RPS0 bit 2 */ +#define ETH_DMADBGSTS_RPS0_3 ((uint32_t)0x00000800U) /* RPS0 bit 3 */ +#define ETH_DMADBGSTS_TPS0 ((uint32_t)0x0000F000U) /* TPS0[3:0]: DMA Channel 0 Transmit Process State */ +#define ETH_DMADBGSTS_TPS0_0 ((uint32_t)0x00001000U) /* TPS0 bit 0 */ +#define ETH_DMADBGSTS_TPS0_1 ((uint32_t)0x00002000U) /* TPS0 bit 1 */ +#define ETH_DMADBGSTS_TPS0_2 ((uint32_t)0x00004000U) /* TPS0 bit 2 */ +#define ETH_DMADBGSTS_TPS0_3 ((uint32_t)0x00008000U) /* TPS0 bit 3 */ + + +/*** Ethernet DMA Channel 0 ***/ + +/** Bit definition for ETH_DMACH0CTRL register **/ +#define ETH_DMACH0CTRL_MSS ((uint32_t)0x00003FFFU) /* Maximum Segment Size */ +#define ETH_DMACH0CTRL_PBLx8 ((uint32_t)0x00010000U) /* 8xPBL mode */ +#define ETH_DMACH0CTRL_DSL ((uint32_t)0x001C0000U) /* DSL[2:0]: Descriptor Skip Length */ +#define ETH_DMACH0CTRL_DSL_0 ((uint32_t)0x00040000U) /* DSL bit 0 */ +#define ETH_DMACH0CTRL_DSL_1 ((uint32_t)0x00080000U) /* DSL bit 1 */ +#define ETH_DMACH0CTRL_DSL_2 ((uint32_t)0x00100000U) /* DSL bit 2 */ + +/** Bit definition for ETH_DMACH0TXCTRL register **/ +#define ETH_DMACH0TXCTRL_ST ((uint32_t)0x00000001U) /* Start or Stop Transmission Command */ +#define ETH_DMACH0TXCTRL_OSF ((uint32_t)0x00000010U) /* Operate on Second Packet */ +#define ETH_DMACH0TXCTRL_TSE ((uint32_t)0x00001000U) /* TCP Segmentation Enabled */ +#define ETH_DMACH0TXCTRL_TxPBL ((uint32_t)0x003F0000U) /* TxPBL[5:0]: Transmit Programmable Burst Length */ +#define ETH_DMACH0TXCTRL_TxPBL_0 ((uint32_t)0x00010000U) /* TxPBL bit 0 */ +#define ETH_DMACH0TXCTRL_TxPBL_1 ((uint32_t)0x00020000U) /* TxPBL bit 1 */ +#define ETH_DMACH0TXCTRL_TxPBL_2 ((uint32_t)0x00040000U) /* TxPBL bit 2 */ +#define ETH_DMACH0TXCTRL_TxPBL_3 ((uint32_t)0x00080000U) /* TxPBL bit 3 */ +#define ETH_DMACH0TXCTRL_TxPBL_4 ((uint32_t)0x00100000U) /* TxPBL bit 4 */ +#define ETH_DMACH0TXCTRL_TxPBL_5 ((uint32_t)0x00200000U) /* TxPBL bit 5 */ +#define ETH_DMACH0TXCTRL_ETIC ((uint32_t)0x00400000U) /* Early Transmit Interrupt Control */ + +/** Bit definition for ETH_DMACH0RXCTRL register **/ +#define ETH_DMACH0RXCTRL_SR ((uint32_t)0x00000001U) /* Start or Stop Receive Command */ +#define ETH_DMACH0RXCTRL_RBSZL ((uint32_t)0x00000006U) /* Receive Buffer size Low */ +#define ETH_DMACH0RXCTRL_RBSZH ((uint32_t)0x00007FF8U) /* Receive Buffer size High */ +#define ETH_DMACH0RXCTRL_RxPBL ((uint32_t)0x003F0000U) /* RxPBL[5:0]: Receive Programmable Burst Length */ +#define ETH_DMACH0RXCTRL_RxPBL_0 ((uint32_t)0x00010000U) /* RxPBL bit 0 */ +#define ETH_DMACH0RXCTRL_RxPBL_1 ((uint32_t)0x00020000U) /* RxPBL bit 1 */ +#define ETH_DMACH0RXCTRL_RxPBL_2 ((uint32_t)0x00040000U) /* RxPBL bit 2 */ +#define ETH_DMACH0RXCTRL_RxPBL_3 ((uint32_t)0x00080000U) /* RxPBL bit 3 */ +#define ETH_DMACH0RXCTRL_RxPBL_4 ((uint32_t)0x00100000U) /* RxPBL bit 4 */ +#define ETH_DMACH0RXCTRL_RxPBL_5 ((uint32_t)0x00200000U) /* RxPBL bit 5 */ +#define ETH_DMACH0RXCTRL_ERIC ((uint32_t)0x00400000U) /* Early Receive Interrupt Control */ +#define ETH_DMACH0RXCTRL_RPF ((uint32_t)0x80000000U) /* Rx Packet Flush */ + +/** Bit definition for ETH_DMACH0TXDLA register **/ +#define ETH_DMACH0TXDLA_TDESLA ((uint32_t)0xFFFFFFFCU) /* Start of Transmit List */ + +/** Bit definition for ETH_DMACH0RXDLA register **/ +#define ETH_DMACH0RXDLA_RDESLA ((uint32_t)0xFFFFFFFCU) /* Start of Receive List */ + +/** Bit definition for ETH_DMACH0TXDTP register **/ +#define ETH_DMACH0TXDTP_TDTP ((uint32_t)0xFFFFFFFCU) /* Transmit Descriptor Tail Pointer */ + +/** Bit definition for ETH_DMACH0RXDTP register **/ +#define ETH_DMACH0RXDTP_RDTP ((uint32_t)0xFFFFFFFCU) /* Receive Descriptor Tail Pointer */ + +/** Bit definition for ETH_DMACH0TXDRLEN register **/ +#define ETH_DMACH0TXDRLEN_TDRL ((uint32_t)0x000003FFU) /* Transmit Descriptor Ring Length */ + +/** Bit definition for ETH_DMACH0RXCTRL2 register **/ +#define ETH_DMACH0RXCTRL2_RDRL ((uint32_t)0x000003FFU) /* Receive Descriptor Ring Length */ +#define ETH_DMACH0RXCTRL2_ARBS ((uint32_t)0x00FF0000U) /* Alternate Receive Buffer Size */ + +/** Bit definition for ETH_DMACH0INTEN register **/ +#define ETH_DMACH0INTEN_TIE ((uint32_t)0x00000001U) /* Transmit Interrupt Enable */ +#define ETH_DMACH0INTEN_TXSE ((uint32_t)0x00000002U) /* Transmit Stopped Enable */ +#define ETH_DMACH0INTEN_TBUE ((uint32_t)0x00000004U) /* Transmit Buffer Unavailable Enable */ +#define ETH_DMACH0INTEN_RIE ((uint32_t)0x00000040U) /* Receive Interrupt Enable */ +#define ETH_DMACH0INTEN_RBUE ((uint32_t)0x00000080U) /* Receive Buffer Unavailable Enable */ +#define ETH_DMACH0INTEN_RSE ((uint32_t)0x00000100U) /* Receive Stopped Enable */ +#define ETH_DMACH0INTEN_RWTE ((uint32_t)0x00000200U) /* Receive Watchdog Timeout Enable */ +#define ETH_DMACH0INTEN_ETIE ((uint32_t)0x00000400U) /* Early Transmit Interrupt Enable */ +#define ETH_DMACH0INTEN_ERIE ((uint32_t)0x00000800U) /* Early Receive Interrupt Enable */ +#define ETH_DMACH0INTEN_FBEE ((uint32_t)0x00001000U) /* Fatal Bus Error Enable */ +#define ETH_DMACH0INTEN_CDEE ((uint32_t)0x00002000U) /* Context Descriptor Error Enable */ +#define ETH_DMACH0INTEN_AIE ((uint32_t)0x00004000U) /* Abnormal Interrupt Summary Enable */ +#define ETH_DMACH0INTEN_NIE ((uint32_t)0x00008000U) /* Normal Interrupt Summary Enable */ + +/** Bit definition for ETH_DMACH0RXINTWT register **/ +#define ETH_DMACH0RXINTWT_RWT ((uint32_t)0x000000FFU) /* Receive Interrupt Watchdog Timer Count */ +#define ETH_DMACH0RXINTWT_RWTU ((uint32_t)0x00030000U) /* RWTU[1:0]: Receive Interrupt Watchdog Timer \ + Count Units */ +#define ETH_DMACH0RXINTWT_RWTU_0 ((uint32_t)0x00010000U) /* RWTU bit 0 */ +#define ETH_DMACH0RXINTWT_RWTU_1 ((uint32_t)0x00020000U) /* RWTU bit 1 */ + +/** Bit definition for ETH_DMACH0CATXD register **/ +#define ETH_DMACH0CATXD_CURTDESAPTR ((uint32_t)0xFFFFFFFFU) /* Application Transmit Descriptor Address Pointer */ + +/** Bit definition for ETH_DMACH0CARXD register **/ +#define ETH_DMACH0CARXD_CURRDESAPTR ((uint32_t)0xFFFFFFFFU) /* Application Receive Descriptor Address Pointer */ + +/** Bit definition for ETH_DMACH0CATXB register **/ +#define ETH_DMACH0CATXB_CURTBUFAPTR ((uint32_t)0xFFFFFFFFU) /* Application Transmit Buffer Address Pointer */ + +/** Bit definition for ETH_DMACH0CARXB register **/ +#define ETH_DMACH0CARXB_CURRBUFAPTR ((uint32_t)0xFFFFFFFFU) /* Application Receive Buffer Address Pointer */ + +/** Bit definition for ETH_DMACH0STS register **/ +#define ETH_DMACH0STS_TI ((uint32_t)0x00000001U) /* Transmit Interrupt */ +#define ETH_DMACH0STS_TPS ((uint32_t)0x00000002U) /* Transmit Process Stopped */ +#define ETH_DMACH0STS_TBU ((uint32_t)0x00000004U) /* Transmit Buffer Unavailable */ +#define ETH_DMACH0STS_RI ((uint32_t)0x00000040U) /* Receive Interrupt */ +#define ETH_DMACH0STS_RBU ((uint32_t)0x00000080U) /* Receive Buffer Unavailable */ +#define ETH_DMACH0STS_RPS ((uint32_t)0x00000100U) /* Receive Process Stopped */ +#define ETH_DMACH0STS_RWT ((uint32_t)0x00000200U) /* Receive Watchdog Timeout */ +#define ETH_DMACH0STS_ETI ((uint32_t)0x00000400U) /* Early Transmit Interrupt */ +#define ETH_DMACH0STS_ERI ((uint32_t)0x00000800U) /* Early Receive Interrupt */ +#define ETH_DMACH0STS_FBE ((uint32_t)0x00001000U) /* Fatal Bus Error */ +#define ETH_DMACH0STS_CDE ((uint32_t)0x00002000U) /* Context Descriptor Error */ +#define ETH_DMACH0STS_AIS ((uint32_t)0x00004000U) /* Abnormal Interrupt Summary */ +#define ETH_DMACH0STS_NIS ((uint32_t)0x00008000U) /* Normal Interrupt Summary */ +#define ETH_DMACH0STS_TEB ((uint32_t)0x00070000U) /* TEB[2:0]: Tx DMA Error Bits */ +#define ETH_DMACH0STS_TEB_0 ((uint32_t)0x00010000U) /* TEB bit 0 */ +#define ETH_DMACH0STS_TEB_1 ((uint32_t)0x00020000U) /* TEB bit 1 */ +#define ETH_DMACH0STS_TEB_2 ((uint32_t)0x00040000U) /* TEB bit 2 */ +#define ETH_DMACH0STS_REB ((uint32_t)0x00380000U) /* REB[2:0]: Rx DMA Error Bits */ +#define ETH_DMACH0STS_REB_0 ((uint32_t)0x00080000U) /* REB bit 0 */ +#define ETH_DMACH0STS_REB_1 ((uint32_t)0x00100000U) /* REB bit 1 */ +#define ETH_DMACH0STS_REB_2 ((uint32_t)0x00200000U) /* REB bit 2 */ + +/** Bit definition for ETH_DMACH0DPCNT register **/ +#define ETH_DMACH0DPCNT_DPC ((uint32_t)0x000007FFU) /* Dropped Packet Counters */ +#define ETH_DMACH0DPCNT_DPCO ((uint32_t)0x00008000U) /* Overflow status of the DPC Counter */ + +/** Bit definition for ETH_DMACH0RXERICNT register **/ +#define ETH_DMACH0RXERICNT_ECNT ((uint32_t)0x00000FFFU) /* ERI Counter */ + + +/*** DMA Controller on AHB Bus (DMA1,DMA2,DMA3) ***/ + +/** Bit definition for DMA_CHNSA register **/ +#define DMA_CHNSA_ADDR ((uint32_t)0xFFFFFFFFU) /* Current Source Address of DMA transfer */ + +/** Bit definition for DMA_CHNDA register **/ +#define DMA_CHNDA_ADDR ((uint32_t)0xFFFFFFFFU) /* Current Destination Address of DMA transfer */ + +/** Bit definition for DMA_CHNLLP register **/ +#define DMA_CHNLLP_LOC ((uint32_t)0xFFFFFFFCU) /* Starting Address In Memory of next LLI if block chaining is enabled */ +#define DMA_CHNLLP_LMS ((uint32_t)0x00000003U) /* LMS[1:0] bits (List Master Select) */ +#define DMA_CHNLLP_LMS_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define DMA_CHNLLP_LMS_1 ((uint32_t)0x00000002U) /* Bit 1 */ + +/** Bit definition for DMA_CHNCTRL register **/ +#define DMA_CHNCTRL_DONE ((uint64_t)0x100000000000U) /* Done bit */ +#define DMA_CHNCTRL_BTS ((uint64_t)0x0FFF00000000U) /* Block Transfer Size */ +#define DMA_CHNCTRL_LLPSRCEN ((uint64_t)0x000010000000U) /* Linked List Pointer for Source Enable */ +#define DMA_CHNCTRL_LLPDSTEN ((uint64_t)0x000008000000U) /* Linked List Pointer for Destination Enable */ +#define DMA_CHNCTRL_SMS ((uint64_t)0x000006000000U) /* Source Master Select */ +#define DMA_CHNCTRL_SMS_1 ((uint64_t)0x000004000000U) /* Bit 1 */ +#define DMA_CHNCTRL_SMS_0 ((uint64_t)0x000002000000U) /* Bit 0 */ +#define DMA_CHNCTRL_DMS ((uint64_t)0x000001800000U) /* Destination Master Select */ +#define DMA_CHNCTRL_DMS_1 ((uint64_t)0x000001000000U) /* Bit 1 */ +#define DMA_CHNCTRL_DMS_0 ((uint64_t)0x000000800000U) /* Bit 0 */ +#define DMA_CHNCTRL_TTFC ((uint64_t)0x000000700000U) /* Transfer Type and Flow Control */ +#define DMA_CHNCTRL_TTFC_2 ((uint64_t)0x000000400000U) /* Bit 2 */ +#define DMA_CHNCTRL_TTFC_1 ((uint64_t)0x000000200000U) /* Bit 1 */ +#define DMA_CHNCTRL_TTFC_0 ((uint64_t)0x000000100000U) /* Bit 0 */ +#define DMA_CHNCTRL_DSTSCAEN ((uint64_t)0x000000040000U) /* Destination scatter enable */ +#define DMA_CHNCTRL_SRCGATEN ((uint64_t)0x000000020000U) /* Source gather enable */ +#define DMA_CHNCTRL_SRCMSIZE ((uint64_t)0x00000001C000U) /* Source Burst Transaction Length */ +#define DMA_CHNCTRL_SRCMSIZE_2 ((uint64_t)0x000000010000U) /* Bit 2 */ +#define DMA_CHNCTRL_SRCMSIZE_1 ((uint64_t)0x000000008000U) /* Bit 1 */ +#define DMA_CHNCTRL_SRCMSIZE_0 ((uint64_t)0x000000004000U) /* Bit 0 */ +#define DMA_CHNCTRL_DSTMSIZE ((uint64_t)0x000000003800U) /* Destination Burst Transaction Length */ +#define DMA_CHNCTRL_DSTMSIZE_2 ((uint64_t)0x000000002000U) /* Bit 2 */ +#define DMA_CHNCTRL_DSTMSIZE_1 ((uint64_t)0x000000001000U) /* Bit 1 */ +#define DMA_CHNCTRL_DSTMSIZE_0 ((uint64_t)0x000000000800U) /* Bit 0 */ +#define DMA_CHNCTRL_SINC ((uint64_t)0x000000000600U) /* Source Address Increment */ +#define DMA_CHNCTRL_SINC_1 ((uint64_t)0x000000000400U) /* Bit 1 */ +#define DMA_CHNCTRL_SINC_0 ((uint64_t)0x000000000200U) /* Bit 0 */ +#define DMA_CHNCTRL_DINC ((uint64_t)0x000000000180U) /* Destination Address Increment */ +#define DMA_CHNCTRL_DINC_1 ((uint64_t)0x000000000100U) /* Bit 1 */ +#define DMA_CHNCTRL_DINC_0 ((uint64_t)0x000000000080U) /* Bit 0 */ +#define DMA_CHNCTRL_STW ((uint64_t)0x000000000070U) /* Source Transfer Width */ +#define DMA_CHNCTRL_STW_2 ((uint64_t)0x000000000040U) /* Bit 2 */ +#define DMA_CHNCTRL_STW_1 ((uint64_t)0x000000000020U) /* Bit 1 */ +#define DMA_CHNCTRL_STW_0 ((uint64_t)0x000000000010U) /* Bit 0 */ +#define DMA_CHNCTRL_DTW ((uint64_t)0x00000000000EU) /* Destination Transfer Width */ +#define DMA_CHNCTRL_DTW_2 ((uint64_t)0x000000000008U) /* Bit 2 */ +#define DMA_CHNCTRL_DTW_1 ((uint64_t)0x000000000004U) /* Bit 1 */ +#define DMA_CHNCTRL_DTW_0 ((uint64_t)0x000000000002U) /* Bit 0 */ +#define DMA_CHNCTRL_INTEN ((uint64_t)0x000000000001U) /* Interrupt Enable Bit */ + +/** Bit definition for DMA_CHNCFG register **/ +#define DMA_CHNCFG_DSTPER ((uint64_t)0x380000000000U) /* Destination Peripheral hardware interface */ +#define DMA_CHNCFG_DSTPER_2 ((uint64_t)0x200000000000U) /* Bit 2 */ +#define DMA_CHNCFG_DSTPER_1 ((uint64_t)0x100000000000U) /* Bit 1 */ +#define DMA_CHNCFG_DSTPER_0 ((uint64_t)0x080000000000U) /* Bit 0 */ +#define DMA_CHNCFG_SRCPER ((uint64_t)0x038000000000U) /* Source Peripheral hardware interface */ +#define DMA_CHNCFG_SRCPER_2 ((uint64_t)0x020000000000U) /* Bit 2 */ +#define DMA_CHNCFG_SRCPER_1 ((uint64_t)0x010000000000U) /* Bit 1 */ +#define DMA_CHNCFG_SRCPER_0 ((uint64_t)0x008000000000U) /* Bit 0 */ +#define DMA_CHNCFG_PROTCTL ((uint64_t)0x001C00000000U) /* Protection Control */ +#define DMA_CHNCFG_PROTCTL_2 ((uint64_t)0x001000000000U) /* Bit 2 */ +#define DMA_CHNCFG_PROTCTL_1 ((uint64_t)0x000800000000U) /* Bit 1 */ +#define DMA_CHNCFG_PROTCTL_0 ((uint64_t)0x000400000000U) /* Bit 0 */ +#define DMA_CHNCFG_FIFOMS ((uint64_t)0x000200000000U) /* FIFO Mode Select */ +#define DMA_CHNCFG_FCM ((uint64_t)0x000100000000U) /* Flow Control Mode */ +#define DMA_CHNCFG_ADR ((uint64_t)0x000080000000U) /* Automatic Destination Reload */ +#define DMA_CHNCFG_ASR ((uint64_t)0x000040000000U) /* Automatic Source Reload */ +#define DMA_CHNCFG_MAMBABL ((uint64_t)0x00003FF00000U) /* Maximum AMBA Burst Length */ +#define DMA_CHNCFG_SRCHSPOL ((uint64_t)0x000000080000U) /* Source Handshaking Interface Polarity */ +#define DMA_CHNCFG_DSTHSPOL ((uint64_t)0x000000040000U) /* Destination Handshaking Interface Polarity */ +#define DMA_CHNCFG_LOCKB ((uint64_t)0x000000020000U) /* Bus Lock Bit */ +#define DMA_CHNCFG_LOCKCH ((uint64_t)0x000000010000U) /* Channel Lock Bit */ +#define DMA_CHNCFG_LOCKBL ((uint64_t)0x00000000C000U) /* Bus lock level */ +#define DMA_CHNCFG_LOCKBL_1 ((uint64_t)0x000000008000U) /* Bit 1 */ +#define DMA_CHNCFG_LOCKBL_0 ((uint64_t)0x000000004000U) /* Bit 0 */ +#define DMA_CHNCFG_LOCKCHL ((uint64_t)0x000000003000U) /* Channel lock level */ +#define DMA_CHNCFG_LOCKCHL_1 ((uint64_t)0x000000002000U) /* Bit 1 */ +#define DMA_CHNCFG_LOCKCHL_0 ((uint64_t)0x000000001000U) /* Bit 0 */ +#define DMA_CHNCFG_HSSELSRC ((uint64_t)0x000000000800U) /* Source Software or Hardware Handshaking Select */ +#define DMA_CHNCFG_HSSELDST ((uint64_t)0x000000000400U) /* Destination Software or Hardware Handshaking Select */ +#define DMA_CHNCFG_FIFOEMPTY ((uint64_t)0x000000000200U) /* Channel FIFO status */ +#define DMA_CHNCFG_CHSUSP ((uint64_t)0x000000000100U) /* Channel Suspend */ +#define DMA_CHNCFG_CHPRIOR ((uint64_t)0x0000000000E0U) /* Channel Priority */ +#define DMA_CHNCFG_CHPRIOR_2 ((uint64_t)0x000000000080U) /* Bit 2 */ +#define DMA_CHNCFG_CHPRIOR_1 ((uint64_t)0x000000000040U) /* Bit 1 */ +#define DMA_CHNCFG_CHPRIOR_0 ((uint64_t)0x000000000020U) /* Bit 0 */ + +/** Bit definition for DMA_CHNSG register **/ +#define DMA_CHNSG_SGC ((uint32_t)0x1FF00000U) /* Source Gather Count */ +#define DMA_CHNSG_SGI ((uint32_t)0x000FFFFFU) /* Source Gather Interval */ + +/** Bit definition for DMA_CHNDS register **/ +#define DMA_CHNDS_DSC ((uint32_t)0x1FF00000U) /* Destination Gather Count */ +#define DMA_CHNDS_DSI ((uint32_t)0x000FFFFFU) /* Destination Gather Interval */ + +/** Bit definition for DMA_RAWTCINTSTS register **/ +#define DMA_RAWTCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Raw Status for IntTfr Interrupt */ +#define DMA_RAWTCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Raw Status for IntTfr Interrupt */ + +/** Bit definition for DMA_RAWBTCINTSTS register **/ +#define DMA_RAWBTCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Raw Status for IntBlock Interrupt */ +#define DMA_RAWBTCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Raw Status for IntBlock Interrupt */ + +/** Bit definition for DMA_RAWSTCINTSTS register **/ +#define DMA_RAWSTCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Raw Status for IntSrcTran Interrupt */ +#define DMA_RAWSTCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Raw Status for IntSrcTran Interrupt */ + +/** Bit definition for DMA_RAWDTCINTSTS register **/ +#define DMA_RAWDTCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Raw Status for IntDstTran Interrupt */ +#define DMA_RAWDTCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Raw Status for IntDstTran Interrupt */ + +/** Bit definition for DMA_RAWERRINTSTS register **/ +#define DMA_RAWERRINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Raw Status for IntErr Interrupt */ +#define DMA_RAWERRINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Raw Status for IntErr Interrupt */ + +/** Bit definition for DMA_TCINTSTS register **/ +#define DMA_TCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Status for IntTfr Interrupt */ +#define DMA_TCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Status for IntTfr Interrupt */ + +/** Bit definition for DMA_BTCINTSTS register **/ +#define DMA_BTCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Status for IntBlock Interrupt */ +#define DMA_BTCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Status for IntBlock Interrupt */ + +/** Bit definition for DMA_STCINTSTS register **/ +#define DMA_STCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Status for IntSrcTran Interrupt */ +#define DMA_STCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Status for IntSrcTran Interrupt */ + +/** Bit definition for DMA_DTCINTSTS register **/ +#define DMA_DTCINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Status for IntDstTran Interrupt */ +#define DMA_DTCINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Status for IntDstTran Interrupt */ + +/** Bit definition for DMA_ERRINTSTS register **/ +#define DMA_ERRINTSTS_CH7 ((uint32_t)0x00000080U) /* Channel 7 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH6 ((uint32_t)0x00000040U) /* Channel 6 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH5 ((uint32_t)0x00000020U) /* Channel 5 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH4 ((uint32_t)0x00000010U) /* Channel 4 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH3 ((uint32_t)0x00000008U) /* Channel 3 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH2 ((uint32_t)0x00000004U) /* Channel 2 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH1 ((uint32_t)0x00000002U) /* Channel 1 Status for IntErr Interrupt */ +#define DMA_ERRINTSTS_CH0 ((uint32_t)0x00000001U) /* Channel 0 Status for IntErr Interrupt */ + +/** Bit definition for DMA_TCINTMSK register **/ +#define DMA_TCINTMSK_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Interrupt Mask Write Enable */ +#define DMA_TCINTMSK_CH7 ((uint32_t)0x00000080U) /* Channel 7 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH6 ((uint32_t)0x00000040U) /* Channel 6 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH5 ((uint32_t)0x00000020U) /* Channel 5 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH4 ((uint32_t)0x00000010U) /* Channel 4 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH3 ((uint32_t)0x00000008U) /* Channel 3 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH2 ((uint32_t)0x00000004U) /* Channel 2 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH1 ((uint32_t)0x00000002U) /* Channel 1 IntTfr Interrupt Mask */ +#define DMA_TCINTMSK_CH0 ((uint32_t)0x00000001U) /* Channel 0 IntTfr Interrupt Mask */ + +/** Bit definition for DMA_BTCINTMSK register **/ +#define DMA_BTCINTMSK_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Interrupt Mask Write Enable */ +#define DMA_BTCINTMSK_CH7 ((uint32_t)0x00000080U) /* Channel 7 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH6 ((uint32_t)0x00000040U) /* Channel 6 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH5 ((uint32_t)0x00000020U) /* Channel 5 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH4 ((uint32_t)0x00000010U) /* Channel 4 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH3 ((uint32_t)0x00000008U) /* Channel 3 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH2 ((uint32_t)0x00000004U) /* Channel 2 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH1 ((uint32_t)0x00000002U) /* Channel 1 IntBlock Interrupt Mask */ +#define DMA_BTCINTMSK_CH0 ((uint32_t)0x00000001U) /* Channel 0 IntBlock Interrupt Mask */ + +/** Bit definition for DMA_STCINTMSK register **/ +#define DMA_STCINTMSK_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Interrupt Mask Write Enable */ +#define DMA_STCINTMSK_CH7 ((uint32_t)0x00000080U) /* Channel 7 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH6 ((uint32_t)0x00000040U) /* Channel 6 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH5 ((uint32_t)0x00000020U) /* Channel 5 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH4 ((uint32_t)0x00000010U) /* Channel 4 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH3 ((uint32_t)0x00000008U) /* Channel 3 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH2 ((uint32_t)0x00000004U) /* Channel 2 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH1 ((uint32_t)0x00000002U) /* Channel 1 IntSrcTran Interrupt Mask */ +#define DMA_STCINTMSK_CH0 ((uint32_t)0x00000001U) /* Channel 0 IntSrcTran Interrupt Mask */ + +/** Bit definition for DMA_DTCINTMSK register **/ +#define DMA_DTCINTMSK_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Interrupt Mask Write Enable */ +#define DMA_DTCINTMSK_CH7 ((uint32_t)0x00000080U) /* Channel 7 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH6 ((uint32_t)0x00000040U) /* Channel 6 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH5 ((uint32_t)0x00000020U) /* Channel 5 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH4 ((uint32_t)0x00000010U) /* Channel 4 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH3 ((uint32_t)0x00000008U) /* Channel 3 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH2 ((uint32_t)0x00000004U) /* Channel 2 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH1 ((uint32_t)0x00000002U) /* Channel 1 IntDstTran Interrupt Mask */ +#define DMA_DTCINTMSK_CH0 ((uint32_t)0x00000001U) /* Channel 0 IntDstTran Interrupt Mask */ + +/** Bit definition for DMA_ERRINTMSK register **/ +#define DMA_ERRINTMSK_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Interrupt Mask Write Enable */ +#define DMA_ERRINTMSK_CH7 ((uint32_t)0x00000080U) /* Channel 7 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH6 ((uint32_t)0x00000040U) /* Channel 6 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH5 ((uint32_t)0x00000020U) /* Channel 5 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH4 ((uint32_t)0x00000010U) /* Channel 4 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH3 ((uint32_t)0x00000008U) /* Channel 3 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH2 ((uint32_t)0x00000004U) /* Channel 2 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH1 ((uint32_t)0x00000002U) /* Channel 1 IntErr Interrupt Mask */ +#define DMA_ERRINTMSK_CH0 ((uint32_t)0x00000001U) /* Channel 0 IntErr Interrupt Mask */ + +/** Bit definition for DMA_TCINTCLR register **/ +#define DMA_TCINTCLR_CH7 ((uint32_t)0x00000080U) /* Channel 7 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH6 ((uint32_t)0x00000040U) /* Channel 6 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH5 ((uint32_t)0x00000020U) /* Channel 5 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH4 ((uint32_t)0x00000010U) /* Channel 4 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH3 ((uint32_t)0x00000008U) /* Channel 3 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH2 ((uint32_t)0x00000004U) /* Channel 2 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH1 ((uint32_t)0x00000002U) /* Channel 1 Clear for IntTfr Interrupt */ +#define DMA_TCINTCLR_CH0 ((uint32_t)0x00000001U) /* Channel 0 Clear for IntTfr Interrupt */ + +/** Bit definition for DMA_BTCINTCLR register **/ +#define DMA_BTCINTCLR_CH7 ((uint32_t)0x00000080U) /* Channel 7 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH6 ((uint32_t)0x00000040U) /* Channel 6 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH5 ((uint32_t)0x00000020U) /* Channel 5 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH4 ((uint32_t)0x00000010U) /* Channel 4 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH3 ((uint32_t)0x00000008U) /* Channel 3 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH2 ((uint32_t)0x00000004U) /* Channel 2 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH1 ((uint32_t)0x00000002U) /* Channel 1 Clear for IntBlock Interrupt */ +#define DMA_BTCINTCLR_CH0 ((uint32_t)0x00000001U) /* Channel 0 Clear for IntBlock Interrupt */ + +/** Bit definition for DMA_STCINTCLR register **/ +#define DMA_STCINTCLR_CH7 ((uint32_t)0x00000080U) /* Channel 7 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH6 ((uint32_t)0x00000040U) /* Channel 6 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH5 ((uint32_t)0x00000020U) /* Channel 5 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH4 ((uint32_t)0x00000010U) /* Channel 4 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH3 ((uint32_t)0x00000008U) /* Channel 3 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH2 ((uint32_t)0x00000004U) /* Channel 2 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH1 ((uint32_t)0x00000002U) /* Channel 1 Clear for IntSrcTran Interrupt */ +#define DMA_STCINTCLR_CH0 ((uint32_t)0x00000001U) /* Channel 0 Clear for IntSrcTran Interrupt */ + +/** Bit definition for DMA_DTCINTCLR register **/ +#define DMA_DTCINTCLR_CH7 ((uint32_t)0x00000080U) /* Channel 7 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH6 ((uint32_t)0x00000040U) /* Channel 6 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH5 ((uint32_t)0x00000020U) /* Channel 5 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH4 ((uint32_t)0x00000010U) /* Channel 4 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH3 ((uint32_t)0x00000008U) /* Channel 3 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH2 ((uint32_t)0x00000004U) /* Channel 2 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH1 ((uint32_t)0x00000002U) /* Channel 1 Clear for IntDstTran Interrupt */ +#define DMA_DTCINTCLR_CH0 ((uint32_t)0x00000001U) /* Channel 0 Clear for IntDstTran Interrupt */ + +/** Bit definition for DMA_ERRINTCLR register **/ +#define DMA_ERRINTCLR_CH7 ((uint32_t)0x00000080U) /* Channel 7 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH6 ((uint32_t)0x00000040U) /* Channel 6 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH5 ((uint32_t)0x00000020U) /* Channel 5 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH4 ((uint32_t)0x00000010U) /* Channel 4 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH3 ((uint32_t)0x00000008U) /* Channel 3 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH2 ((uint32_t)0x00000004U) /* Channel 2 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH1 ((uint32_t)0x00000002U) /* Channel 1 Clear for IntErr Interrupt */ +#define DMA_ERRINTCLR_CH0 ((uint32_t)0x00000001U) /* Channel 0 Clear for IntErr Interrupt */ + +/** Bit definition for DMA_INTCBESTS register **/ +#define DMA_INTCBESTS_ERR ((uint32_t)0x00000010U) /* OR of the contents of DMA_ERRINTSTS register */ +#define DMA_INTCBESTS_DSTT ((uint32_t)0x00000008U) /* OR of the contents of DMA_DTCINTSTS register */ +#define DMA_INTCBESTS_SRCT ((uint32_t)0x00000004U) /* OR of the contents of DMA_STCINTSTS register */ +#define DMA_INTCBESTS_BLOCK ((uint32_t)0x00000002U) /* OR of the contents of DMA_BTCINTSTS register */ +#define DMA_INTCBESTS_TFR ((uint32_t)0x00000001U) /* OR of the contents of DMA_TCINTSTS register */ + +/** Bit definition for DMA_SRCSWTREQ register **/ +#define DMA_SRCSWTREQ_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Source Software Transaction Request write enable */ +#define DMA_SRCSWTREQ_CH7 ((uint32_t)0x00000080U) /* Channel 7 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH6 ((uint32_t)0x00000040U) /* Channel 6 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH5 ((uint32_t)0x00000020U) /* Channel 5 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH4 ((uint32_t)0x00000010U) /* Channel 4 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH3 ((uint32_t)0x00000008U) /* Channel 3 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH2 ((uint32_t)0x00000004U) /* Channel 2 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH1 ((uint32_t)0x00000002U) /* Channel 1 Source Software Transaction Request */ +#define DMA_SRCSWTREQ_CH0 ((uint32_t)0x00000001U) /* Channel 0 Source Software Transaction Request */ + +/** Bit definition for DMA_DSTSWTREQ register **/ +#define DMA_DSTSWTREQ_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Destination Software Transaction Request write enable */ +#define DMA_DSTSWTREQ_CH7 ((uint32_t)0x00000080U) /* Channel 7 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH6 ((uint32_t)0x00000040U) /* Channel 6 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH5 ((uint32_t)0x00000020U) /* Channel 5 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH4 ((uint32_t)0x00000010U) /* Channel 4 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH3 ((uint32_t)0x00000008U) /* Channel 3 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH2 ((uint32_t)0x00000004U) /* Channel 2 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH1 ((uint32_t)0x00000002U) /* Channel 1 Destination Software Transaction Request */ +#define DMA_DSTSWTREQ_CH0 ((uint32_t)0x00000001U) /* Channel 0 Destination Software Transaction Request */ + +/** Bit definition for DMA_SRCSGTREQ register **/ +#define DMA_SRCSGTREQ_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Source Single Transaction Request write enable */ +#define DMA_SRCSGTREQ_CH7 ((uint32_t)0x00000080U) /* Channel 7 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH6 ((uint32_t)0x00000040U) /* Channel 6 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH5 ((uint32_t)0x00000020U) /* Channel 5 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH4 ((uint32_t)0x00000010U) /* Channel 4 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH3 ((uint32_t)0x00000008U) /* Channel 3 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH2 ((uint32_t)0x00000004U) /* Channel 2 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH1 ((uint32_t)0x00000002U) /* Channel 1 Source Single Transaction Request */ +#define DMA_SRCSGTREQ_CH0 ((uint32_t)0x00000001U) /* Channel 0 Source Single Transaction Request */ + +/** Bit definition for DMA_DSTSGTREQ register **/ +#define DMA_DSTSGTREQ_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Destination Single Transaction Request write enable */ +#define DMA_DSTSGTREQ_CH7 ((uint32_t)0x00000080U) /* Channel 7 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH6 ((uint32_t)0x00000040U) /* Channel 6 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH5 ((uint32_t)0x00000020U) /* Channel 5 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH4 ((uint32_t)0x00000010U) /* Channel 4 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH3 ((uint32_t)0x00000008U) /* Channel 3 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH2 ((uint32_t)0x00000004U) /* Channel 2 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH1 ((uint32_t)0x00000002U) /* Channel 1 Destination Single Transaction Request */ +#define DMA_DSTSGTREQ_CH0 ((uint32_t)0x00000001U) /* Channel 0 Destination Single Transaction Request */ + +/** Bit definition for DMA_SRCLTREQ register **/ +#define DMA_SRCLTREQ_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Source Last Transaction Request write enable */ +#define DMA_SRCLTREQ_CH7 ((uint32_t)0x00000080U) /* Channel 7 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH6 ((uint32_t)0x00000040U) /* Channel 6 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH5 ((uint32_t)0x00000020U) /* Channel 5 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH4 ((uint32_t)0x00000010U) /* Channel 4 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH3 ((uint32_t)0x00000008U) /* Channel 3 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH2 ((uint32_t)0x00000004U) /* Channel 2 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH1 ((uint32_t)0x00000002U) /* Channel 1 Source Last Transaction Request */ +#define DMA_SRCLTREQ_CH0 ((uint32_t)0x00000001U) /* Channel 0 Source Last Transaction Request */ + +/** Bit definition for DMA_DSTLTREQ register **/ +#define DMA_DSTLTREQ_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Destination Last Transaction Request write enable */ +#define DMA_DSTLTREQ_CH7 ((uint32_t)0x00000080U) /* Channel 7 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH6 ((uint32_t)0x00000040U) /* Channel 6 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH5 ((uint32_t)0x00000020U) /* Channel 5 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH4 ((uint32_t)0x00000010U) /* Channel 4 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH3 ((uint32_t)0x00000008U) /* Channel 3 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH2 ((uint32_t)0x00000004U) /* Channel 2 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH1 ((uint32_t)0x00000002U) /* Channel 1 Destination Last Transaction Request */ +#define DMA_DSTLTREQ_CH0 ((uint32_t)0x00000001U) /* Channel 0 Destination Last Transaction Request */ + +/** Bit definition for DMA_CFG ENister **/ +#define DMA_CFG_EN ((uint32_t)0x00000001U) /* DMA Enable bit */ + +/** Bit definition for DMA_CHEN register **/ +#define DMA_CHEN_CH7WEN ((uint32_t)0x00008000U) /* Channel 7 Enable bit write enable */ +#define DMA_CHEN_CH6WEN ((uint32_t)0x00004000U) /* Channel 6 Enable bit write enable */ +#define DMA_CHEN_CH5WEN ((uint32_t)0x00002000U) /* Channel 5 Enable bit write enable */ +#define DMA_CHEN_CH4WEN ((uint32_t)0x00001000U) /* Channel 4 Enable bit write enable */ +#define DMA_CHEN_CH3WEN ((uint32_t)0x00000800U) /* Channel 3 Enable bit write enable */ +#define DMA_CHEN_CH2WEN ((uint32_t)0x00000400U) /* Channel 2 Enable bit write enable */ +#define DMA_CHEN_CH1WEN ((uint32_t)0x00000200U) /* Channel 1 Enable bit write enable */ +#define DMA_CHEN_CH0WEN ((uint32_t)0x00000100U) /* Channel 0 Enable bit write enable */ +#define DMA_CHEN_CH7 ((uint32_t)0x00000080U) /* Channel 7 Enable bit */ +#define DMA_CHEN_CH6 ((uint32_t)0x00000040U) /* Channel 6 Enable bit */ +#define DMA_CHEN_CH5 ((uint32_t)0x00000020U) /* Channel 5 Enable bit */ +#define DMA_CHEN_CH4 ((uint32_t)0x00000010U) /* Channel 4 Enable bit */ +#define DMA_CHEN_CH3 ((uint32_t)0x00000008U) /* Channel 3 Enable bit */ +#define DMA_CHEN_CH2 ((uint32_t)0x00000004U) /* Channel 2 Enable bit */ +#define DMA_CHEN_CH1 ((uint32_t)0x00000002U) /* Channel 1 Enable bit */ +#define DMA_CHEN_CH0 ((uint32_t)0x00000001U) /* Channel 0 Enable bit */ + +/** Bit definition for DMA_ID ENister **/ +#define DMA_ID_VALUE ((uint32_t)0xFFFFFFFFU) /* Hardcoded DMA peripheral ID */ + +/** Bit definition for DMA_LPTIMEOUT ENister **/ +#define DMA_LPTIMEOUT_VALUE ((uint32_t)0xFFFFFFFFU) /* Timeout value of low power counter register */ + + + +/*** DMA AXI Bus Controller (MDMA) ***/ + +/** Bit definition for MDMA_ID register **/ +#define MDMA_ID_NBR ((uint32_t)0xFFFFFFFFU) /* MDMA Component ID Number */ + +/** Bit definition for MDMA_VERSION register **/ +#define MDMA_VERSION_NBR ((uint32_t)0xFFFFFFFFU) /* MDMA Component Version Number */ + +/** Bit definition for MDMA_CFG register **/ +#define MDMA_CFG_GLBINTEN ((uint32_t)0x00000002U) /* Global interrupt generation enable bit */ +#define MDMA_CFG_EN ((uint32_t)0x00000001U) /* MDMA enable bit */ + +/** Bit definition for MDMA_CHEN register **/ +#define MDMA_CHEN_CH15WEN ((uint32_t)0x80000000U) /* Channel 15 Enable bit write enable */ +#define MDMA_CHEN_CH14WEN ((uint32_t)0x40000000U) /* Channel 14 Enable bit write enable */ +#define MDMA_CHEN_CH13WEN ((uint32_t)0x20000000U) /* Channel 13 Enable bit write enable */ +#define MDMA_CHEN_CH12WEN ((uint32_t)0x10000000U) /* Channel 12 Enable bit write enable */ +#define MDMA_CHEN_CH11WEN ((uint32_t)0x08000000U) /* Channel 11 Enable bit write enable */ +#define MDMA_CHEN_CH10WEN ((uint32_t)0x04000000U) /* Channel 10 Enable bit write enable */ +#define MDMA_CHEN_CH9WEN ((uint32_t)0x02000000U) /* Channel 9 Enable bit write enable */ +#define MDMA_CHEN_CH8WEN ((uint32_t)0x01000000U) /* Channel 8 Enable bit write enable */ +#define MDMA_CHEN_CH7WEN ((uint32_t)0x00800000U) /* Channel 7 Enable bit write enable */ +#define MDMA_CHEN_CH6WEN ((uint32_t)0x00400000U) /* Channel 6 Enable bit write enable */ +#define MDMA_CHEN_CH5WEN ((uint32_t)0x00200000U) /* Channel 5 Enable bit write enable */ +#define MDMA_CHEN_CH4WEN ((uint32_t)0x00100000U) /* Channel 4 Enable bit write enable */ +#define MDMA_CHEN_CH3WEN ((uint32_t)0x00080000U) /* Channel 3 Enable bit write enable */ +#define MDMA_CHEN_CH2WEN ((uint32_t)0x00040000U) /* Channel 2 Enable bit write enable */ +#define MDMA_CHEN_CH1WEN ((uint32_t)0x00020000U) /* Channel 1 Enable bit write enable */ +#define MDMA_CHEN_CH0WEN ((uint32_t)0x00010000U) /* Channel 0 Enable bit write enable */ +#define MDMA_CHEN_CH15 ((uint32_t)0x00008000U) /* Channel 15 Enable bit */ +#define MDMA_CHEN_CH14 ((uint32_t)0x00004000U) /* Channel 14 Enable bit */ +#define MDMA_CHEN_CH13 ((uint32_t)0x00002000U) /* Channel 13 Enable bit */ +#define MDMA_CHEN_CH12 ((uint32_t)0x00001000U) /* Channel 12 Enable bit */ +#define MDMA_CHEN_CH11 ((uint32_t)0x00000800U) /* Channel 11 Enable bit */ +#define MDMA_CHEN_CH10 ((uint32_t)0x00000400U) /* Channel 10 Enable bit */ +#define MDMA_CHEN_CH9 ((uint32_t)0x00000200U) /* Channel 9 Enable bit */ +#define MDMA_CHEN_CH8 ((uint32_t)0x00000100U) /* Channel 8 Enable bit */ +#define MDMA_CHEN_CH7 ((uint32_t)0x00000080U) /* Channel 7 Enable bit */ +#define MDMA_CHEN_CH6 ((uint32_t)0x00000040U) /* Channel 6 Enable bit */ +#define MDMA_CHEN_CH5 ((uint32_t)0x00000020U) /* Channel 5 Enable bit */ +#define MDMA_CHEN_CH4 ((uint32_t)0x00000010U) /* Channel 4 Enable bit */ +#define MDMA_CHEN_CH3 ((uint32_t)0x00000008U) /* Channel 3 Enable bit */ +#define MDMA_CHEN_CH2 ((uint32_t)0x00000004U) /* Channel 2 Enable bit */ +#define MDMA_CHEN_CH1 ((uint32_t)0x00000002U) /* Channel 1 Enable bit */ +#define MDMA_CHEN_CH0 ((uint32_t)0x00000001U) /* Channel 0 Enable bit */ + +/** Bit definition for MDMA_CHSUSP register **/ +#define MDMA_CHSUSP_CH15WEN ((uint32_t)0x80000000U) /* Channel 15 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH14WEN ((uint32_t)0x40000000U) /* Channel 14 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH13WEN ((uint32_t)0x20000000U) /* Channel 13 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH12WEN ((uint32_t)0x10000000U) /* Channel 12 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH11WEN ((uint32_t)0x08000000U) /* Channel 11 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH10WEN ((uint32_t)0x04000000U) /* Channel 10 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH9WEN ((uint32_t)0x02000000U) /* Channel 9 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH8WEN ((uint32_t)0x01000000U) /* Channel 8 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH7WEN ((uint32_t)0x00800000U) /* Channel 7 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH6WEN ((uint32_t)0x00400000U) /* Channel 6 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH5WEN ((uint32_t)0x00200000U) /* Channel 5 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH4WEN ((uint32_t)0x00100000U) /* Channel 4 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH3WEN ((uint32_t)0x00080000U) /* Channel 3 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH2WEN ((uint32_t)0x00040000U) /* Channel 2 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH1WEN ((uint32_t)0x00020000U) /* Channel 1 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH0WEN ((uint32_t)0x00010000U) /* Channel 0 Suspend Request bit write enable */ +#define MDMA_CHSUSP_CH15 ((uint32_t)0x00008000U) /* Channel 15 Suspend Request bit */ +#define MDMA_CHSUSP_CH14 ((uint32_t)0x00004000U) /* Channel 14 Suspend Request bit */ +#define MDMA_CHSUSP_CH13 ((uint32_t)0x00002000U) /* Channel 13 Suspend Request bit */ +#define MDMA_CHSUSP_CH12 ((uint32_t)0x00001000U) /* Channel 12 Suspend Request bit */ +#define MDMA_CHSUSP_CH11 ((uint32_t)0x00000800U) /* Channel 11 Suspend Request bit */ +#define MDMA_CHSUSP_CH10 ((uint32_t)0x00000400U) /* Channel 10 Suspend Request bit */ +#define MDMA_CHSUSP_CH9 ((uint32_t)0x00000200U) /* Channel 9 Suspend Request bit */ +#define MDMA_CHSUSP_CH8 ((uint32_t)0x00000100U) /* Channel 8 Suspend Request bit */ +#define MDMA_CHSUSP_CH7 ((uint32_t)0x00000080U) /* Channel 7 Suspend Request bit */ +#define MDMA_CHSUSP_CH6 ((uint32_t)0x00000040U) /* Channel 6 Suspend Request bit */ +#define MDMA_CHSUSP_CH5 ((uint32_t)0x00000020U) /* Channel 5 Suspend Request bit */ +#define MDMA_CHSUSP_CH4 ((uint32_t)0x00000010U) /* Channel 4 Suspend Request bit */ +#define MDMA_CHSUSP_CH3 ((uint32_t)0x00000008U) /* Channel 3 Suspend Request bit */ +#define MDMA_CHSUSP_CH2 ((uint32_t)0x00000004U) /* Channel 2 Suspend Request bit */ +#define MDMA_CHSUSP_CH1 ((uint32_t)0x00000002U) /* Channel 1 Suspend Request bit */ +#define MDMA_CHSUSP_CH0 ((uint32_t)0x00000001U) /* Channel 0 Suspend Request bit */ + +/** Bit definition for MDMA_INTSTS register **/ +#define MDMA_INTSTS_COMREG ((uint64_t)0x100000000UL) /* Common register interrupt status bit */ +#define MDMA_INTSTS_CH15 ((uint64_t)0x000008000UL) /* Channel 15 interrupt status bit */ +#define MDMA_INTSTS_CH14 ((uint64_t)0x000004000UL) /* Channel 14 interrupt status bit */ +#define MDMA_INTSTS_CH13 ((uint64_t)0x000002000UL) /* Channel 13 interrupt status bit */ +#define MDMA_INTSTS_CH12 ((uint64_t)0x000001000UL) /* Channel 12 interrupt status bit */ +#define MDMA_INTSTS_CH11 ((uint64_t)0x000000800UL) /* Channel 11 interrupt status bit */ +#define MDMA_INTSTS_CH10 ((uint64_t)0x000000400UL) /* Channel 10 interrupt status bit */ +#define MDMA_INTSTS_CH9 ((uint64_t)0x000000200UL) /* Channel 9 interrupt status bit */ +#define MDMA_INTSTS_CH8 ((uint64_t)0x000000100UL) /* Channel 8 interrupt status bit */ +#define MDMA_INTSTS_CH7 ((uint64_t)0x000000080UL) /* Channel 7 interrupt status bit */ +#define MDMA_INTSTS_CH6 ((uint64_t)0x000000040UL) /* Channel 6 interrupt status bit */ +#define MDMA_INTSTS_CH5 ((uint64_t)0x000000020UL) /* Channel 5 interrupt status bit */ +#define MDMA_INTSTS_CH4 ((uint64_t)0x000000010UL) /* Channel 4 interrupt status bit */ +#define MDMA_INTSTS_CH3 ((uint64_t)0x000000008UL) /* Channel 3 interrupt status bit */ +#define MDMA_INTSTS_CH2 ((uint64_t)0x000000004UL) /* Channel 2 interrupt status bit */ +#define MDMA_INTSTS_CH1 ((uint64_t)0x000000002UL) /* Channel 1 interrupt status bit */ +#define MDMA_INTSTS_CH0 ((uint64_t)0x000000001UL) /* Channel 0 interrupt status bit */ + +/** Bit definition for MDMA_CRINTCLR register **/ +#define MDMA_CRINTCLR_SIURDEIC ((uint32_t)0x00000100U) /* Slave Interface Undefined Register Decode Error Interrupt Clear bit */ +#define MDMA_CRINTCLR_SICRWOHEIC ((uint32_t)0x00000008U) /* Slave Interface Common Register Write On Hold Error Interrupt Clear bit */ +#define MDMA_CRINTCLR_SICRR2WOEIC ((uint32_t)0x00000004U) /* Slave Interface Common Register Read to Write Only Error Interrupt Clear bit */ +#define MDMA_CRINTCLR_SICRW2ROEIC ((uint32_t)0x00000002U) /* Slave Interface Common Register Write to Read Only Error Interrupt Clear bit */ +#define MDMA_CRINTCLR_SICRDEIC ((uint32_t)0x00000001U) /* Slave Interface Common Register Decode Error Interrupt Clear bit */ + +/** Bit definition for MDMA_CRINTSTSEN register **/ +#define MDMA_CRINTSTSEN_SIURDEIS ((uint32_t)0x00000100U) /* Slave Interface Undefined Register Decode Error Interrupt Status bit */ +#define MDMA_CRINTSTSEN_SICRWOHEIS ((uint32_t)0x00000008U) /* Slave Interface Common Register Write On Hold Error Interrupt Status bit */ +#define MDMA_CRINTSTSEN_SICRR2WOEIS ((uint32_t)0x00000004U) /* Slave Interface Common Register Read to Write Only Error Interrupt Status bit */ +#define MDMA_CRINTSTSEN_SICRW2ROEIS ((uint32_t)0x00000002U) /* Slave Interface Common Register Write to Read Only Error Interrupt Status bit */ +#define MDMA_CRINTSTSEN_SICRDEIS ((uint32_t)0x00000001U) /* Slave Interface Common Register Decode Error Interrupt Status bit */ + +/** Bit definition for MDMA_CRINTSGLEN register **/ +#define MDMA_CRINTSGLEN_SIURDEIS ((uint32_t)0x00000100U) /* Slave Interface Undefined Register Decode Error Interrupt Status bit */ +#define MDMA_CRINTSGLEN_SICRWOHEIS ((uint32_t)0x00000008U) /* Slave Interface Common Register Write On Hold Error Interrupt Status bit */ +#define MDMA_CRINTSGLEN_SICRR2WOEIS ((uint32_t)0x00000004U) /* Slave Interface Common Register Read to Write Only Error Interrupt Status bit */ +#define MDMA_CRINTSGLEN_SICRW2ROEIS ((uint32_t)0x00000002U) /* Slave Interface Common Register Write to Read Only Error Interrupt Status bit */ +#define MDMA_CRINTSGLEN_SICRDEIS ((uint32_t)0x00000001U) /* Slave Interface Common Register Decode Error Interrupt Status bit */ + +/** Bit definition for MDMA_CRINTSTS register **/ +#define MDMA_CRINTSTS_SIURDEIS ((uint32_t)0x00000100U) /* Slave Interface Undefined Register Decode Error Interrupt Status bit */ +#define MDMA_CRINTSTS_SICRWOHEIS ((uint32_t)0x00000008U) /* Slave Interface Common Register Write On Hold Error Interrupt Status bit */ +#define MDMA_CRINTSTS_SICRR2WOEIS ((uint32_t)0x00000004U) /* Slave Interface Common Register Read to Write Only Error Interrupt Status bit */ +#define MDMA_CRINTSTS_SICRW2ROEIS ((uint32_t)0x00000002U) /* Slave Interface Common Register Write to Read Only Error Interrupt Status bit */ +#define MDMA_CRINTSTS_SICRDEIS ((uint32_t)0x00000001U) /* Slave Interface Common Register Decode Error Interrupt Status bit */ + +/** Bit definition for MDMA_SWRST register **/ +#define MDMA_SWRST_RSTREQ ((uint32_t)0x00000001U) /* MDMA Reset Request bit */ + +/** Bit definition for MDMA_LPCFG register **/ +#define MDMA_LPCFG_MXIFLPDLY ((uint64_t)0xFF000000000000UL) /* Bit55:48 */ +#define MDMA_LPCFG_SBIULPDLY ((uint64_t)0x00FF0000000000UL) /* Bit47:40 */ +#define MDMA_LPCFG_GLCHLPDLY ((uint64_t)0x0000FF00000000UL) /* Bit39:32 */ +#define MDMA_LPCFG_MXIFCSLPEN ((uint64_t)0x00000000000008UL) /* AXI Master Interface Context Sensitive Low Power feature enable */ +#define MDMA_LPCFG_SBIUCSLPEN ((uint64_t)0x00000000000004UL) /* SBIU Context Sensitive Low Power feature enable */ +#define MDMA_LPCFG_CHCSLPEN ((uint64_t)0x00000000000002UL) /* MDMA Channel Context Sensitive Low Power feature enable */ +#define MDMA_LPCFG_GBLCSLPEN ((uint64_t)0x00000000000001UL) /* Global Context Sensitive Low Power feature enable */ + +/** Bit definition for MDMA_CHNSA register **/ +#define MDMA_CHNSA_ADDR ((uint64_t)0xFFFFFFFFFFFFFFFFUL) /* Current Source Address of MDMA transfer */ + +/** Bit definition for MDMA_CHNDA register **/ +#define MDMA_CHNDA_ADDR ((uint64_t)0xFFFFFFFFFFFFFFFFUL) /* Current Destination Address of MDMA transfer */ + +/** Bit definition for MDMA_CHNBTS register **/ +#define MDMA_CHNBTS_NUM ((uint32_t)0x003FFFFFU) /* Block Transfer Size */ + +/** Bit definition for MDMA_CHNCTRL register **/ +#define MDMA_CHNCTRL_SRLLI ((uint64_t)0x8000000000000000UL) /* Linked List Item (LLI) valid */ +#define MDMA_CHNCTRL_LSRLLI ((uint64_t)0x4000000000000000UL) /* Linked List Item (LLI) */ +#define MDMA_CHNCTRL_BTIOC ((uint64_t)0x0400000000000000UL) /* Interrupt On Completion of Block Transfer */ +#define MDMA_CHNCTRL_DBL ((uint64_t)0x00FF000000000000UL) /* Destination Burst Length */ +#define MDMA_CHNCTRL_DBLEN ((uint64_t)0x0000800000000000UL) /* Destination Burst Length Enable */ +#define MDMA_CHNCTRL_SBL ((uint64_t)0x00007F8000000000UL) /* Source Burst Length */ +#define MDMA_CHNCTRL_SBLEN ((uint64_t)0x0000004000000000UL) /* Source Burst Length Enable */ +#define MDMA_CHNCTRL_NPLWEN ((uint64_t)0x0000000040000000UL) /* Non Posted Last Write Enable */ +#define MDMA_CHNCTRL_DSTMSIZE ((uint64_t)0x00000000003C0000UL) /* Destination Burst Transaction Length */ +#define MDMA_CHNCTRL_DSTMSIZE_0 ((uint64_t)0x0000000000040000UL) /* Bit18 */ +#define MDMA_CHNCTRL_DSTMSIZE_1 ((uint64_t)0x0000000000080000UL) /* Bit19 */ +#define MDMA_CHNCTRL_DSTMSIZE_2 ((uint64_t)0x0000000000100000UL) /* Bit20 */ +#define MDMA_CHNCTRL_DSTMSIZE_3 ((uint64_t)0x0000000000200000UL) /* Bit21 */ +#define MDMA_CHNCTRL_SRCMSIZE ((uint64_t)0x000000000003C000UL) /* Source Burst Transaction Length */ +#define MDMA_CHNCTRL_SRCMSIZE_0 ((uint64_t)0x0000000000004000UL) /* Bit14 */ +#define MDMA_CHNCTRL_SRCMSIZE_1 ((uint64_t)0x0000000000008000UL) /* Bit15 */ +#define MDMA_CHNCTRL_SRCMSIZE_2 ((uint64_t)0x0000000000010000UL) /* Bit16 */ +#define MDMA_CHNCTRL_SRCMSIZE_3 ((uint64_t)0x0000000000020000UL) /* Bit17 */ +#define MDMA_CHNCTRL_DTW ((uint64_t)0x0000000000003800UL) /* Destination Transfer Width */ +#define MDMA_CHNCTRL_DTW_0 ((uint64_t)0x0000000000000800UL) /* Bit11 */ +#define MDMA_CHNCTRL_DTW_1 ((uint64_t)0x0000000000001000UL) /* Bit12 */ +#define MDMA_CHNCTRL_DTW_2 ((uint64_t)0x0000000000002000UL) /* Bit13 */ +#define MDMA_CHNCTRL_STW ((uint64_t)0x0000000000000700UL) /* Source Transfer Width */ +#define MDMA_CHNCTRL_STW_0 ((uint64_t)0x0000000000000100UL) /* Bit8 */ +#define MDMA_CHNCTRL_STW_1 ((uint64_t)0x0000000000000200UL) /* Bit9 */ +#define MDMA_CHNCTRL_STW_2 ((uint64_t)0x0000000000000400UL) /* Bit10 */ +#define MDMA_CHNCTRL_DINC ((uint64_t)0x0000000000000040UL) /* Destination Address Increment */ +#define MDMA_CHNCTRL_SINC ((uint64_t)0x0000000000000010UL) /* Source Address Increment */ +#define MDMA_CHNCTRL_DMS ((uint64_t)0x0000000000000004UL) /* Destination Master Select */ +#define MDMA_CHNCTRL_SMS ((uint64_t)0x0000000000000001UL) /* Source Master Select */ + +/** Bit definition for MDMA_CHNCFG register **/ +#define MDMA_CHNCFG_DSTOSRLMT ((uint64_t)0x7800000000000000UL) /* Destination Outstanding Request Limit */ +#define MDMA_CHNCFG_DSTOSRLMT_0 ((uint64_t)0x0000000000000000UL) /* Bit59*/ +#define MDMA_CHNCFG_DSTOSRLMT_1 ((uint64_t)0x0000000000000000UL) /* Bit60*/ +#define MDMA_CHNCFG_DSTOSRLMT_2 ((uint64_t)0x0000000000000000UL) /* Bit61*/ +#define MDMA_CHNCFG_DSTOSRLMT_3 ((uint64_t)0x0000000000000000UL) /* Bit62*/ +#define MDMA_CHNCFG_SRCOSRLMT ((uint64_t)0x0780000000000000UL) /* Source Outstanding Request Limit */ +#define MDMA_CHNCFG_SRCOSRLMT_0 ((uint64_t)0x0000000000000000UL) /* Bit55*/ +#define MDMA_CHNCFG_SRCOSRLMT_1 ((uint64_t)0x0000000000000000UL) /* Bit56*/ +#define MDMA_CHNCFG_SRCOSRLMT_2 ((uint64_t)0x0000000000000000UL) /* Bit57*/ +#define MDMA_CHNCFG_SRCOSRLMT_3 ((uint64_t)0x0000000000000000UL) /* Bit58*/ +#define MDMA_CHNCFG_CHPRIOR ((uint64_t)0x000F800000000000UL) /* Channel Priority */ +#define MDMA_CHNCFG_DSTHHIPOL ((uint64_t)0x0000004000000000UL) /* Destination Hardware Handshaking Interface Polarity */ +#define MDMA_CHNCFG_SRCHHIPOL ((uint64_t)0x0000002000000000UL) /* Source Hardware Handshaking Interface Polarity */ +#define MDMA_CHNCFG_HSSELDST ((uint64_t)0x0000001000000000UL) /* Destination Software or Hardware Handshaking Select */ +#define MDMA_CHNCFG_HSSELSRC ((uint64_t)0x0000000800000000UL) /* Source Software or Hardware Handshaking Select */ +#define MDMA_CHNCFG_TTFC ((uint64_t)0x0000000700000000UL) /* Transfer Type and Flow Control */ +#define MDMA_CHNCFG_TTFC_0 ((uint64_t)0x0000000100000000UL) /* Bit32*/ +#define MDMA_CHNCFG_TTFC_1 ((uint64_t)0x0000000200000000UL) /* Bit33*/ +#define MDMA_CHNCFG_TTFC_2 ((uint64_t)0x0000000400000000UL) /* Bit34*/ +#define MDMA_CHNCFG_WRUID ((uint64_t)0x000000001E000000UL) /* Defines the number of AXI Unique ID's supported for the AXI Write Channel */ +#define MDMA_CHNCFG_RDUID ((uint64_t)0x00000000003C0000UL) /* Defines the number of AXI Unique ID's supported for the AXI Read Channel */ +#define MDMA_CHNCFG_DSTPER ((uint64_t)0x0000000000007800UL) /* Bit14:11 */ +#define MDMA_CHNCFG_SRCPER ((uint64_t)0x00000000000000F0UL) /* Bit7:4 */ +#define MDMA_CHNCFG_DMBTT ((uint64_t)0x000000000000000CUL) /* Destination Multi Block Transfer Type */ +#define MDMA_CHNCFG_DMBTT_0 ((uint64_t)0x0000000000000004UL) /* Bit2*/ +#define MDMA_CHNCFG_DMBTT_1 ((uint64_t)0x0000000000000008UL) /* Bit3*/ +#define MDMA_CHNCFG_SMBTT ((uint64_t)0x0000000000000003UL) /* Source Multi Block Transfer Type */ +#define MDMA_CHNCFG_SMBTT_0 ((uint64_t)0x0000000000000001UL) /* Bit0*/ +#define MDMA_CHNCFG_SMBTT_1 ((uint64_t)0x0000000000000002UL) /* Bit1*/ + +/** Bit definition for MDMA_CHNLLP register **/ +#define MDMA_CHNLLP_ADDR ((uint64_t)0xFFFFFFFFFFFFFFC0UL) /* Starting Address Memory of LLI block */ +#define MDMA_CHNLLP_LMS ((uint64_t)0x0000000000000001UL) /* LLI master Select */ + +/** Bit definition for MDMA_CHNSTS register **/ +#define MDMA_CHNSTS_LEFTDATA ((uint64_t)0x7FFF00000000UL) /* Data Left in FIFO */ +#define MDMA_CHNSTS_CBTSIZE ((uint64_t)0x0000003FFFFFUL) /* Completed Block Transfer Size */ + +/** Bit definition for MDMA_CHNSHSRC register **/ +#define MDMA_CHNSHSRC_SHLRWE ((uint32_t)0x00000020U) /* Write Enable bit for Software Handshake Last Request for Channel Source */ +#define MDMA_CHNSHSRC_SHLR ((uint32_t)0x00000010U) /* Software Handshake Last Request for Channel Source */ +#define MDMA_CHNSHSRC_SHSRWE ((uint32_t)0x00000008U) /* Write Enable bit for Software Handshake Single Request for Channel Source */ +#define MDMA_CHNSHSRC_SHSR ((uint32_t)0x00000004U) /* Software Handshake Single Request for Channel Source */ +#define MDMA_CHNSHSRC_SHRWE ((uint32_t)0x00000002U) /* Write Enable bit for Software Handshake Request for Channel Source */ +#define MDMA_CHNSHSRC_SHR ((uint32_t)0x00000001U) /* Software Handshake Request for Channel Source */ + +/** Bit definition for MDMA_CHNSHDST register **/ +#define MDMA_CHNSHDST_SHLRWE ((uint32_t)0x00000020U) /* Write Enable bit for Software Handshake Last Request for Channel Destination */ +#define MDMA_CHNSHDST_SHLR ((uint32_t)0x00000010U) /* Software Handshake Last Request for Channel Destination */ +#define MDMA_CHNSHDST_SHSRWE ((uint32_t)0x00000008U) /* Write Enable bit for Software Handshake Single Request for Channel Destination */ +#define MDMA_CHNSHDST_SHSR ((uint32_t)0x00000004U) /* Software Handshake Single Request for Channel Destination */ +#define MDMA_CHNSHDST_SHRWE ((uint32_t)0x00000002U) /* Write Enable bit for Software Handshake Request for Channel Destination */ +#define MDMA_CHNSHDST_SHR ((uint32_t)0x00000001U) /* Software Handshake Request for Channel Destination */ + +/** Bit definition for MDMA_CHNBTRR register **/ +#define MDMA_CHNBTRR_RESREQ ((uint32_t)0x00000001U) /* Block Transfer Resume Request during Linked-List-based multi-block transfer */ + +/** Bit definition for MDMA_CHNAXIQOS register **/ +#define MDMA_CHNAXIQOS_ARQOS ((uint32_t)0x000000F0U) /* AXI ARQOS */ +#define MDMA_CHNAXIQOS_AWQOS ((uint32_t)0x0000000FU) /* AXI AWQOS */ + +/** Bit definition for MDMA_CHNINTSTSEN register **/ +#define MDMA_CHNINTSTSEN_CHA ((uint32_t)0x80000000U) /* Channel Aborted */ +#define MDMA_CHNINTSTSEN_CHD ((uint32_t)0x40000000U) /* Channel Disabled */ +#define MDMA_CHNINTSTSEN_CHS ((uint32_t)0x20000000U) /* Channel Suspended */ +#define MDMA_CHNINTSTSEN_CHSS ((uint32_t)0x10000000U) /* Channel Source Suspended */ +#define MDMA_CHNINTSTSEN_CHLC ((uint32_t)0x08000000U) /* Channel Lock Cleared */ +#define MDMA_CHNINTSTSEN_SIWOHE ((uint32_t)0x00200000U) /* Slave Interface Write On Hold Error */ +#define MDMA_CHNINTSTSEN_SIWOCEE ((uint32_t)0x00080000U) /* Slave Interface Write On Channel Enabled Error */ +#define MDMA_CHNINTSTSEN_SIRTWOE ((uint32_t)0x00040000U) /* Slave Interface Read to Write Only Error */ +#define MDMA_CHNINTSTSEN_SIWTROE ((uint32_t)0x00020000U) /* Slave Interface Write to Read Only Error */ +#define MDMA_CHNINTSTSEN_SIDE ((uint32_t)0x00010000U) /* Slave Interface Decode Error */ +#define MDMA_CHNINTSTSEN_SIMBTE ((uint32_t)0x00004000U) /* Slave Interface Multi Block Type Error */ +#define MDMA_CHNINTSTSEN_SLIE ((uint32_t)0x00002000U) /* LLI Invalid Error */ +#define MDMA_CHNINTSTSEN_LWSE ((uint32_t)0x00001000U) /* LLI Write Slave Error */ +#define MDMA_CHNINTSTSEN_LRSE ((uint32_t)0x00000800U) /* LLI Read Slave Error */ +#define MDMA_CHNINTSTSEN_LWDE ((uint32_t)0x00000400U) /* LLI Write Decode Error */ +#define MDMA_CHNINTSTSEN_LRDE ((uint32_t)0x00000200U) /* LLI Read Decode Error */ +#define MDMA_CHNINTSTSEN_DSTSE ((uint32_t)0x00000100U) /* Destination Slave Error */ +#define MDMA_CHNINTSTSEN_SRCSE ((uint32_t)0x00000080U) /* Source Slave Error */ +#define MDMA_CHNINTSTSEN_DSTDE ((uint32_t)0x00000040U) /* Destination Decode Error */ +#define MDMA_CHNINTSTSEN_SRCDE ((uint32_t)0x00000020U) /* Source Decode Error */ +#define MDMA_CHNINTSTSEN_DSTTC ((uint32_t)0x00000010U) /* Destination Transaction Completed */ +#define MDMA_CHNINTSTSEN_SRCTC ((uint32_t)0x00000008U) /* Source Transaction Completed */ +#define MDMA_CHNINTSTSEN_DMATD ((uint32_t)0x00000002U) /* DMA Transfer Done */ +#define MDMA_CHNINTSTSEN_BLKTD ((uint32_t)0x00000001U) /* Block Transfer Done */ + +/** Bit definition for MDMA_CHNINTSTS register **/ +#define MDMA_CHNINTSTS_CHA ((uint32_t)0x80000000U) /* Channel Aborted */ +#define MDMA_CHNINTSTS_CHD ((uint32_t)0x40000000U) /* Channel Disabled */ +#define MDMA_CHNINTSTS_CHS ((uint32_t)0x20000000U) /* Channel Suspended */ +#define MDMA_CHNINTSTS_CHSS ((uint32_t)0x10000000U) /* Channel Source Suspended */ +#define MDMA_CHNINTSTS_CHLC ((uint32_t)0x08000000U) /* Channel Lock Cleared */ +#define MDMA_CHNINTSTS_SIWOHE ((uint32_t)0x00200000U) /* Slave Interface Write On Hold Error */ +#define MDMA_CHNINTSTS_SIWOCEE ((uint32_t)0x00080000U) /* Slave Interface Write On Channel Enabled Error */ +#define MDMA_CHNINTSTS_SIRTWOE ((uint32_t)0x00040000U) /* Slave Interface Read to Write Only Error */ +#define MDMA_CHNINTSTS_SIWTROE ((uint32_t)0x00020000U) /* Slave Interface Write to Read Only Error */ +#define MDMA_CHNINTSTS_SIDE ((uint32_t)0x00010000U) /* Slave Interface Decode Error */ +#define MDMA_CHNINTSTS_SIMBTE ((uint32_t)0x00004000U) /* Slave Interface Multi Block Type Error */ +#define MDMA_CHNINTSTS_SLIE ((uint32_t)0x00002000U) /* LLI Invalid Error */ +#define MDMA_CHNINTSTS_LWSE ((uint32_t)0x00001000U) /* LLI Write Slave Error */ +#define MDMA_CHNINTSTS_LRSE ((uint32_t)0x00000800U) /* LLI Read Slave Error */ +#define MDMA_CHNINTSTS_LWDE ((uint32_t)0x00000400U) /* LLI Write Decode Error */ +#define MDMA_CHNINTSTS_LRDE ((uint32_t)0x00000200U) /* LLI Read Decode Error */ +#define MDMA_CHNINTSTS_DSTSE ((uint32_t)0x00000100U) /* Destination Slave Error */ +#define MDMA_CHNINTSTS_SRCSE ((uint32_t)0x00000080U) /* Source Slave Error */ +#define MDMA_CHNINTSTS_DSTDE ((uint32_t)0x00000040U) /* Destination Decode Error */ +#define MDMA_CHNINTSTS_SRCDE ((uint32_t)0x00000020U) /* Source Decode Error */ +#define MDMA_CHNINTSTS_DSTTC ((uint32_t)0x00000010U) /* Destination Transaction Completed */ +#define MDMA_CHNINTSTS_SRCTC ((uint32_t)0x00000008U) /* Source Transaction Completed */ +#define MDMA_CHNINTSTS_DMATD ((uint32_t)0x00000002U) /* DMA Transfer Done */ +#define MDMA_CHNINTSTS_BLKTD ((uint32_t)0x00000001U) /* Block Transfer Done */ + +/** Bit definition for MDMA_CHNINTSGLEN register **/ +#define MDMA_CHNINTSGLEN_CHA ((uint32_t)0x80000000U) /* Channel Aborted */ +#define MDMA_CHNINTSGLEN_CHD ((uint32_t)0x40000000U) /* Channel Disabled */ +#define MDMA_CHNINTSGLEN_CHS ((uint32_t)0x20000000U) /* Channel Suspended */ +#define MDMA_CHNINTSGLEN_CHSS ((uint32_t)0x10000000U) /* Channel Source Suspended */ +#define MDMA_CHNINTSGLEN_CHLC ((uint32_t)0x08000000U) /* Channel Lock Cleared */ +#define MDMA_CHNINTSGLEN_SIWOHE ((uint32_t)0x00200000U) /* Slave Interface Write On Hold Error */ +#define MDMA_CHNINTSGLEN_SIWOCEE ((uint32_t)0x00080000U) /* Slave Interface Write On Channel Enabled Error */ +#define MDMA_CHNINTSGLEN_SIRTWOE ((uint32_t)0x00040000U) /* Slave Interface Read to Write Only Error */ +#define MDMA_CHNINTSGLEN_SIWTROE ((uint32_t)0x00020000U) /* Slave Interface Write to Read Only Error */ +#define MDMA_CHNINTSGLEN_SIDE ((uint32_t)0x00010000U) /* Slave Interface Decode Error */ +#define MDMA_CHNINTSGLEN_SIMBTE ((uint32_t)0x00004000U) /* Slave Interface Multi Block Type Error */ +#define MDMA_CHNINTSGLEN_SLIE ((uint32_t)0x00002000U) /* LLI Invalid Error */ +#define MDMA_CHNINTSGLEN_LWSE ((uint32_t)0x00001000U) /* LLI Write Slave Error */ +#define MDMA_CHNINTSGLEN_LRSE ((uint32_t)0x00000800U) /* LLI Read Slave Error */ +#define MDMA_CHNINTSGLEN_LWDE ((uint32_t)0x00000400U) /* LLI Write Decode Error */ +#define MDMA_CHNINTSGLEN_LRDE ((uint32_t)0x00000200U) /* LLI Read Decode Error */ +#define MDMA_CHNINTSGLEN_DSTSE ((uint32_t)0x00000100U) /* Destination Slave Error */ +#define MDMA_CHNINTSGLEN_SRCSE ((uint32_t)0x00000080U) /* Source Slave Error */ +#define MDMA_CHNINTSGLEN_DSTDE ((uint32_t)0x00000040U) /* Destination Decode Error */ +#define MDMA_CHNINTSGLEN_SRCDE ((uint32_t)0x00000020U) /* Source Decode Error */ +#define MDMA_CHNINTSGLEN_DSTTC ((uint32_t)0x00000010U) /* Destination Transaction Completed */ +#define MDMA_CHNINTSGLEN_SRCTC ((uint32_t)0x00000008U) /* Source Transaction Completed */ +#define MDMA_CHNINTSGLEN_DMATD ((uint32_t)0x00000002U) /* DMA Transfer Done */ +#define MDMA_CHNINTSGLEN_BLKTD ((uint32_t)0x00000001U) /* Block Transfer Done */ + +/** Bit definition for MDMA_CHNINTCLR register **/ +#define MDMA_CHNINTCLR_CHA ((uint32_t)0x80000000U) /* Channel Aborted */ +#define MDMA_CHNINTCLR_CHD ((uint32_t)0x40000000U) /* Channel Disabled */ +#define MDMA_CHNINTCLR_CHS ((uint32_t)0x20000000U) /* Channel Suspended */ +#define MDMA_CHNINTCLR_CHSS ((uint32_t)0x10000000U) /* Channel Source Suspended */ +#define MDMA_CHNINTCLR_CHLC ((uint32_t)0x08000000U) /* Channel Lock Cleared */ +#define MDMA_CHNINTCLR_SIWOHE ((uint32_t)0x00200000U) /* Slave Interface Write On Hold Error */ +#define MDMA_CHNINTCLR_SIWOCEE ((uint32_t)0x00080000U) /* Slave Interface Write On Channel Enabled Error */ +#define MDMA_CHNINTCLR_SIRTWOE ((uint32_t)0x00040000U) /* Slave Interface Read to Write Only Error */ +#define MDMA_CHNINTCLR_SIWTROE ((uint32_t)0x00020000U) /* Slave Interface Write to Read Only Error */ +#define MDMA_CHNINTCLR_SIDE ((uint32_t)0x00010000U) /* Slave Interface Decode Error */ +#define MDMA_CHNINTCLR_SIMBTE ((uint32_t)0x00004000U) /* Slave Interface Multi Block Type Error */ +#define MDMA_CHNINTCLR_SLIE ((uint32_t)0x00002000U) /* LLI Invalid Error */ +#define MDMA_CHNINTCLR_LWSE ((uint32_t)0x00001000U) /* LLI Write Slave Error */ +#define MDMA_CHNINTCLR_LRSE ((uint32_t)0x00000800U) /* LLI Read Slave Error */ +#define MDMA_CHNINTCLR_LWDE ((uint32_t)0x00000400U) /* LLI Write Decode Error */ +#define MDMA_CHNINTCLR_LRDE ((uint32_t)0x00000200U) /* LLI Read Decode Error */ +#define MDMA_CHNINTCLR_DSTSE ((uint32_t)0x00000100U) /* Destination Slave Error */ +#define MDMA_CHNINTCLR_SRCSE ((uint32_t)0x00000080U) /* Source Slave Error */ +#define MDMA_CHNINTCLR_DSTDE ((uint32_t)0x00000040U) /* Destination Decode Error */ +#define MDMA_CHNINTCLR_SRCDE ((uint32_t)0x00000020U) /* Source Decode Error */ +#define MDMA_CHNINTCLR_DSTTC ((uint32_t)0x00000010U) /* Destination Transaction Completed */ +#define MDMA_CHNINTCLR_SRCTC ((uint32_t)0x00000008U) /* Source Transaction Completed */ +#define MDMA_CHNINTCLR_DMATD ((uint32_t)0x00000002U) /* DMA Transfer Done */ +#define MDMA_CHNINTCLR_BLKTD ((uint32_t)0x00000001U) /* Block Transfer Done */ + + + + + +/******************************************************************************/ +/* */ +/* DMAMUX */ +/* */ +/******************************************************************************/ + + +/******** Bit definition for DMAMUX_CHxCTRL register ********/ +#define DMAMUX_CHxCTRL_SYID_MASK ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define DMAMUX_CHxCTRL_SYID_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define DMAMUX_CHxCTRL_SYID_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define DMAMUX_CHxCTRL_SYID_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define DMAMUX_CHxCTRL_SYID_3 ((uint32_t)0x08000000U) /* Bit27*/ + +#define DMAMUX_CHxCTRL_NUMREQ_MASK ((uint32_t)0x00F80000U) /* Bit[23:19] */ +#define DMAMUX_CHxCTRL_NUMREQ_0 ((uint32_t)0x00080000U) /* Bit19*/ +#define DMAMUX_CHxCTRL_NUMREQ_1 ((uint32_t)0x00100000U) /* Bit20*/ +#define DMAMUX_CHxCTRL_NUMREQ_2 ((uint32_t)0x00200000U) /* Bit21*/ +#define DMAMUX_CHxCTRL_NUMREQ_3 ((uint32_t)0x00400000U) /* Bit22*/ +#define DMAMUX_CHxCTRL_NUMREQ_4 ((uint32_t)0x00800000U) /* Bit23*/ + +#define DMAMUX_CHxCTRL_SYPOL_MASK ((uint32_t)0x00060000U) /* Bit[18:17] */ +#define DMAMUX_CHxCTRL_SYPOL_0 ((uint32_t)0x00020000U) /* Bit17*/ +#define DMAMUX_CHxCTRL_SYPOL_1 ((uint32_t)0x00040000U) /* Bit18*/ +#define DMAMUX_CHxCTRL_SYEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define DMAMUX_CHxCTRL_EVEGEN ((uint32_t)0x00000200U) /* Bit[9] */ +#define DMAMUX_CHxCTRL_SOIEN ((uint32_t)0x00000100U) /* Bit[8] */ + +#define DMAMUX_CHxCTRL_REQID_MASK ((uint32_t)0x000000FFU) /* Bit[7:0] */ +#define DMAMUX_CHxCTRL_REQID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define DMAMUX_CHxCTRL_REQID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define DMAMUX_CHxCTRL_REQID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define DMAMUX_CHxCTRL_REQID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define DMAMUX_CHxCTRL_REQID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define DMAMUX_CHxCTRL_REQID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define DMAMUX_CHxCTRL_REQID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define DMAMUX_CHxCTRL_REQID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for DMAMUX_STS register ********/ +#define DMAMUX_STS_SOFx ((uint32_t)0x00FFFFFFU) /* Bit[23:0] */ + +/******** Bit definition for DMAMUX_CLR register ********/ +#define DMAMUX_CLR_CSOFx ((uint32_t)0x00FFFFFFU) /* Bit[23:0] */ + +/******** Bit definition for DMAMUX_CHxCFG register ********/ +#define DMAMUX_CHxCFG_GNUMREQ_MASK ((uint32_t)0x00F80000U) /* Bit[23:19] */ +#define DMAMUX_CHxCFG_GNUMREQ_0 ((uint32_t)0x00080000U) /* Bit19*/ +#define DMAMUX_CHxCFG_GNUMREQ_1 ((uint32_t)0x00100000U) /* Bit20*/ +#define DMAMUX_CHxCFG_GNUMREQ_2 ((uint32_t)0x00200000U) /* Bit21*/ +#define DMAMUX_CHxCFG_GNUMREQ_3 ((uint32_t)0x00400000U) /* Bit22*/ +#define DMAMUX_CHxCFG_GNUMREQ_4 ((uint32_t)0x00800000U) /* Bit23*/ + +#define DMAMUX_CHxCFG_GPOL_MASK ((uint32_t)0x00060000U) /* Bit[18:17] */ +#define DMAMUX_CHxCFG_GPOL_0 ((uint32_t)0x00020000U) /* Bit17*/ +#define DMAMUX_CHxCFG_GPOL_1 ((uint32_t)0x00040000U) /* Bit18*/ + +#define DMAMUX_CHxCFG_GEN ((uint32_t)0x00010000U) /* Bit[16] */ +#define DMAMUX_CHxCFG_TOVIEN ((uint32_t)0x00000100U) /* Bit[8] */ + +#define DMAMUX_CHxCFG_SYID_MASK ((uint32_t)0x0000003FU) /* Bit[5:0] */ +#define DMAMUX_CHxCFG_SYID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define DMAMUX_CHxCFG_SYID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define DMAMUX_CHxCFG_SYID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define DMAMUX_CHxCFG_SYID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define DMAMUX_CHxCFG_SYID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define DMAMUX_CHxCFG_SYID_5 ((uint32_t)0x00000020U) /* Bit5*/ + +/******** Bit definition for DMAMUX_RGSTS register ********/ +#define DMAMUX_RGSTS_OFx ((uint32_t)0x0000FFFF) /* Bit[15:0] */ + +/******** Bit definition for DMAMUX_RGCLR register ********/ +#define DMAMUX_RGCLR_COFx ((uint32_t)0x0000FFFF) /* Bit[15:0] */ + + + +/******************************************************************************/ +/* */ +/* DCMU Dualcore Messaging Unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for DCMU_STS register ********************/ +#define DCMU_STS_RCVFN0_Pos (0U) +#define DCMU_STS_RCVFN0 ((uint32_t)0x00000001U) /* dualcore messaging status register flag 0 bit */ +#define DCMU_STS_RCVFN1 ((uint32_t)0x00000002U) /* dualcore messaging status register flag 1 bit */ +#define DCMU_STS_RCVFN2 ((uint32_t)0x00000004U) /* dualcore messaging status register flag 2 bit */ +#define DCMU_STS_EPF ((uint32_t)0x00000010U) /* dualcore messaging status register event pending flag bit */ +#define DCMU_STS_RSTF ((uint32_t)0x00000080U) /* dualcore messaging status register other core reset status bit */ +#define DCMU_STS_FUPF ((uint32_t)0x00000100U) /* dualcore messaging status register flag update pending flag bit */ +#define DCMU_STS_TEF3_Pos (20U) +#define DCMU_STS_TEF3 ((uint32_t)0x00100000U) /* dualcore messaging status register transmit 3 empty bit */ +#define DCMU_STS_TEF2 ((uint32_t)0x00200000U) /* dualcore messaging status register transmit 2 empty bit */ +#define DCMU_STS_TEF1 ((uint32_t)0x00400000U) /* dualcore messaging status register transmit 1 empty bit */ +#define DCMU_STS_TEF0 ((uint32_t)0x00800000U) /* dualcore messaging status register transmit 0 empty bit */ +#define DCMU_STS_RFF3_Pos (24U) +#define DCMU_STS_RFF3 ((uint32_t)0x01000000U) /* dualcore messaging status register receive 3 full bit */ +#define DCMU_STS_RFF2 ((uint32_t)0x02000000U) /* dualcore messaging status register receive 2 full bit */ +#define DCMU_STS_RFF1 ((uint32_t)0x04000000U) /* dualcore messaging status register receive 1 full bit */ +#define DCMU_STS_RFF0 ((uint32_t)0x08000000U) /* dualcore messaging status register receive 0 full bit */ +#define DCMU_STS_GPIF3_Pos (28U) +#define DCMU_STS_GPIF3 ((uint32_t)0x10000000U) /* dualcore messaging status register general interrupt from other core request 3 pending bit */ +#define DCMU_STS_GPIF2 ((uint32_t)0x20000000U) /* dualcore messaging status register general interrupt from other core request 2 pending bit */ +#define DCMU_STS_GPIF1 ((uint32_t)0x40000000U) /* dualcore messaging status register general interrupt from other core request 1 pending bit */ +#define DCMU_STS_GPIF0 ((uint32_t)0x80000000U) /* dualcore messaging status register general interrupt from other core request 0 pending bit */ + +/******************* Bit definition for DCMU_CTRL register ********************/ +#define DCMU_CTRL_TXFN0_Pos (0U) +#define DCMU_CTRL_TXFN0 ((uint32_t)0x00000001U) /* dualcore messaging control register flag 0 bit */ +#define DCMU_CTRL_TXFN1 ((uint32_t)0x00000002U) /* dualcore messaging control register flag 1 bit */ +#define DCMU_CTRL_TXFN2 ((uint32_t)0x00000004U) /* dualcore messaging control register flag 2 bit */ +#if defined(CORE_CM7) +#define DCMU_CTRL_RST ((uint32_t)0x00000020U) /* dualcore messaging control register reset both cores bit */ +#endif +#define DCMU_CTRL_GPIR3_Pos (16U) +#define DCMU_CTRL_GPIR3 ((uint32_t)0x00010000U) /* dualcore messaging control register general interrupt to other core request 3 pending bit */ +#define DCMU_CTRL_GPIR2 ((uint32_t)0x00020000U) /* dualcore messaging control register general interrupt to other core request 2 pending bit */ +#define DCMU_CTRL_GPIR1 ((uint32_t)0x00040000U) /* dualcore messaging control register general interrupt to other core request 1 pending bit */ +#define DCMU_CTRL_GPIR0 ((uint32_t)0x00080000U) /* dualcore messaging control register general interrupt to other core request 0 pending bit */ +#define DCMU_CTRL_TEIE3_Pos (20U) +#define DCMU_CTRL_TEIE3 ((uint32_t)0x00100000U) /* dualcore messaging control register transmit 3 interrupt enable bit */ +#define DCMU_CTRL_TEIE2 ((uint32_t)0x00200000U) /* dualcore messaging control register transmit 2 interrupt enable bit */ +#define DCMU_CTRL_TEIE1 ((uint32_t)0x00400000U) /* dualcore messaging control register transmit 1 interrupt enable bit */ +#define DCMU_CTRL_TEIE0 ((uint32_t)0x00800000U) /* dualcore messaging control register transmit 0 interrupt enable bit */ +#define DCMU_CTRL_RFIE3_Pos (24U) +#define DCMU_CTRL_RFIE3 ((uint32_t)0x01000000U) /* dualcore messaging control register receive 3 interrupt enable bit */ +#define DCMU_CTRL_RFIE2 ((uint32_t)0x02000000U) /* dualcore messaging control register receive 2 interrupt enable bit */ +#define DCMU_CTRL_RFIE1 ((uint32_t)0x04000000U) /* dualcore messaging control register receive 1 interrupt enable bit */ +#define DCMU_CTRL_RFIE0 ((uint32_t)0x08000000U) /* dualcore messaging control register receive 0 interrupt enable bit */ +#define DCMU_CTRL_GPIE3_Pos (28U) +#define DCMU_CTRL_GPIE3 ((uint32_t)0x10000000U) /* dualcore messaging control register general purpose 3 interrupt enable bit */ +#define DCMU_CTRL_GPIE2 ((uint32_t)0x20000000U) /* dualcore messaging control register general purpose 2 interrupt enable bit */ +#define DCMU_CTRL_GPIE1 ((uint32_t)0x40000000U) /* dualcore messaging control register general purpose 1 interrupt enable bit */ +#define DCMU_CTRL_GPIE0 ((uint32_t)0x80000000U) /* dualcore messaging control register general purpose 0 interrupt enable bit */ + +/******************************************************************************/ +/* */ +/* SEMA4 HW Semaphore */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for SEMA4_R register ********************/ +#define SEMA4_R_PROCID_Pos (0U) +#define SEMA4_R_PROCID ((uint32_t)0x000000FFU) /* Semaphore ProcessID */ +#define SEMA4_R_COREID_Pos (8U) +#define SEMA4_R_COREID ((uint32_t)0x0000FF00U) /* Semaphore CoreID. */ +#define SEMA4_R_LOCK ((uint32_t)0x80000000U) /* Lock indication. */ + +/******************** Bit definition for SEMA4_RL register ******************/ +#define SEMA4_RL_PROCID_Pos (0U) +#define SEMA4_RL_PROCID ((uint32_t)0x000000FFU) /* Semaphore ProcessID */ +#define SEMA4_RL_COREID_Pos (8U) +#define SEMA4_RL_COREID ((uint32_t)0x0000FF00U) /* Semaphore CoreID. */ +#define SEMA4_RL_LOCK_Pos (31U) +#define SEMA4_RL_LOCK ((uint32_t)0x80000000U) /* Lock indication. */ + +/******************** Bit definition for SEMA4_CLR register *****************/ +#define SEMA4_CLR_COREID_OFFSET (8U) +#define SEMA4_CLR_COREID ((uint32_t)0x0000FF00U) /* CoreID of semaphores to be cleared. */ +#define SEMA4_CLR_KEY_OFFSET (16U) +#define SEMA4_CLR_KEY ((uint32_t)0xFFFF0000U) /* semaphores clear key. */ + +/******************** Bit definition for SEMA4_KEYCLR register *****************/ +#define SEMA4_KEYR_KEY_OFFSET (16U) +#define SEMA4_KEYCLR_KEY ((uint32_t)0xFFFF0000U) /* semaphores clear key. */ + +/*** CORDIC Processors ***/ + +/** Bit definition for CORDIC_CTRLSTS register **/ +#define CORDIC_CTRLSTS_FUNC ((uint32_t)0x0000000FU) /* bit[3:0] Function bits[3:0] */ +#define CORDIC_CTRLSTS_FUNC_0 ((uint32_t)0x00000001U) /* bit[0] Function bit 0 */ +#define CORDIC_CTRLSTS_FUNC_1 ((uint32_t)0x00000002U) /* bit[1] Function bit 1 */ +#define CORDIC_CTRLSTS_FUNC_2 ((uint32_t)0x00000004U) /* bit[2] Function bit 2 */ +#define CORDIC_CTRLSTS_FUNC_3 ((uint32_t)0x00000008U) /* bit[3] Function bit 3 */ + +#define CORDIC_CTRLSTS_PRECISION ((uint32_t)0x000000F0U) /* bit[7:4] Precision required (number of iterations) bits[3:0] */ +#define CORDIC_CTRLSTS_PRECISION_0 ((uint32_t)0x00000010U) /* bit[4] Precision bit 0 */ +#define CORDIC_CTRLSTS_PRECISION_1 ((uint32_t)0x00000020U) /* bit[5] Precision bit 1 */ +#define CORDIC_CTRLSTS_PRECISION_2 ((uint32_t)0x00000040U) /* bit[6] Precision bit 2 */ +#define CORDIC_CTRLSTS_PRECISION_3 ((uint32_t)0x00000080U) /* bit[7] Precision bit 3 */ + +#define CORDIC_CTRLSTS_SCALE ((uint32_t)0x00000700U) /* bit[10:8] Scaling factor bits[2:0] */ +#define CORDIC_CTRLSTS_SCALE_0 ((uint32_t)0x00000100U) /* bit[4] Scaling bit 0 */ +#define CORDIC_CTRLSTS_SCALE_1 ((uint32_t)0x00000200U) /* bit[5] Scaling bit 1 */ +#define CORDIC_CTRLSTS_SCALE_2 ((uint32_t)0x00000400U) /* bit[6] Scaling bit 2 */ + +#define CORDIC_CTRLSTS_INTEN ((uint32_t)0x00010000U) /* bit[16] Interrupt Enable */ +#define CORDIC_CTRLSTS_DMAREN ((uint32_t)0x00020000U) /* bit[17] DMA read Enable */ +#define CORDIC_CTRLSTS_DMAWEN ((uint32_t)0x00040000U) /* bit[18] DMA write Enable */ +#define CORDIC_CTRLSTS_NUMREAD ((uint32_t)0x00080000U) /* bit[19] Number of results in the CORDIC_RDATA register */ +#define CORDIC_CTRLSTS_NUMWRITE ((uint32_t)0x00100000U) /* bit[20] Number of arguments expected by the CORDIC_WDATA register */ +#define CORDIC_CTRLSTS_OUTSIZE ((uint32_t)0x00200000U) /* bit[21] Size of output data */ +#define CORDIC_CTRLSTS_INSIZE ((uint32_t)0x00400000U) /* bit[22] Size of input data */ +#define CORDIC_CTRLSTS_FLOATIN ((uint32_t)0x00800000U) /* bit[23] Floating-point fixed-point input control */ +#define CORDIC_CTRLSTS_FLOATOUT ((uint32_t)0x01000000U) /* bit[24] Floating-point fixed-point output control */ +#define CORDIC_CTRLSTS_PHASELIMIT ((uint32_t)0x02000000U) /* bit[25] Phase Output Limit Control */ +#define CORDIC_CTRLSTS_CODINLIMIT ((uint32_t)0x04000000U) /* bit[26] Coordinate output limit control */ +#define CORDIC_CTRLSTS_INOVINTEN ((uint32_t)0x08000000U) /* bit[27] Input parameter overflow interrupt control bit */ +#define CORDIC_CTRLSTS_INOVF ((uint32_t)0x40000000U) /* bit[30] Input parameter overflow flag */ +#define CORDIC_CTRLSTS_RRF ((uint32_t)0x80000000U) /* bit[31] Result ready flag */ + +/** Bit definition for CORDIC_WDAT register **/ +#define CORDIC_WDAT_WDAT ((uint32_t)0xFFFFFFFFU) /* bit[31:0] Write data */ + +/** Bit definition for CORDIC_RDAT register **/ +#define CORDIC_RDAT_RDAT ((uint32_t)0xFFFFFFFFU) /* bit[31:0] Read data */ + +/*** Digital filter for Sigma delta modulators(DSMU) ***/ +/** Bit definition for DSMU_CHYCFG1 register **/ +#define DSMU_CHYCFG1_DSMUEN ((uint32_t)0x80000000U) /* Bit[31] DSMU interface global enable */ +#define DSMU_CHYCFG1_CLKOUTSRC ((uint32_t)0x40000000U) /* Bit[30] Output serial clock source selection */ + +#define DSMU_CHYCFG1_CLKOUTDIV ((uint32_t)0x00FF0000U) /* Bit[23:16] Output serial clock divider */ +#define DSMU_CHYCFG1_CLKOUTDIV_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_CHYCFG1_CLKOUTDIV_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_CHYCFG1_CLKOUTDIV_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_CHYCFG1_CLKOUTDIV_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_CHYCFG1_CLKOUTDIV_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_CHYCFG1_CLKOUTDIV_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_CHYCFG1_CLKOUTDIV_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_CHYCFG1_CLKOUTDIV_7 ((uint32_t)0x00800000U) /* Bit23 */ + +#define DSMU_CHYCFG1_DATPACK ((uint32_t)0x0000C000U) /* Bit[15:14] Data packing config in DSMU_CHYDATIN register */ +#define DSMU_CHYCFG1_DATPACK_0 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_CHYCFG1_DATPACK_1 ((uint32_t)0x00008000U) /* Bit15 */ + +#define DSMU_CHYCFG1_DATMUX ((uint32_t)0x00003000U) /* Bit[13:12] Data input multiplexer for channel y */ +#define DSMU_CHYCFG1_DATMUX_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_CHYCFG1_DATMUX_1 ((uint32_t)0x00002000U) /* Bit13 */ + +#define DSMU_CHYCFG1_CHINSEL ((uint32_t)0x00000100U) /* Bit[8] Channel inputs selection */ +#define DSMU_CHYCFG1_CHEN ((uint32_t)0x00000080U) /* Bit[7] channel y enable */ +#define DSMU_CHYCFG1_CLKABEN ((uint32_t)0x00000040U) /* Bit[6] Clock absence detector enable on channel y */ +#define DSMU_CHYCFG1_SCDETEN ((uint32_t)0x00000020U) /* Bit[5] Short-circuit detector enable on channel y */ + +#define DSMU_CHYCFG1_SPICLKSEL ((uint32_t)0x0000000CU) /* Bit[3:2] SPI clock source config for channel y */ +#define DSMU_CHYCFG1_SPICLKSEL_0 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_CHYCFG1_SPICLKSEL_1 ((uint32_t)0x00000008U) /* Bit3 */ + +#define DSMU_CHYCFG1_SITP ((uint32_t)0x00000003U) /* Bit[1:0] Serial interface type for channel y */ +#define DSMU_CHYCFG1_SITP_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_CHYCFG1_SITP_1 ((uint32_t)0x00000002U) /* Bit1 */ + +/** Bit definition for DSMU_CHYCFG2 register **/ +#define DSMU_CHYCFG2_CALOFFSET ((uint32_t)0xFFFFFF00U) /* Bit[31:8] channel y 24-bit calibration CALOFFSET value. */ +#define DSMU_CHYCFG2_CALOFFSET_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_CHYCFG2_CALOFFSET_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_CHYCFG2_CALOFFSET_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_CHYCFG2_CALOFFSET_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_CHYCFG2_CALOFFSET_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_CHYCFG2_CALOFFSET_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_CHYCFG2_CALOFFSET_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_CHYCFG2_CALOFFSET_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_CHYCFG2_CALOFFSET_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_CHYCFG2_CALOFFSET_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_CHYCFG2_CALOFFSET_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_CHYCFG2_CALOFFSET_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_CHYCFG2_CALOFFSET_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_CHYCFG2_CALOFFSET_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_CHYCFG2_CALOFFSET_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_CHYCFG2_CALOFFSET_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_CHYCFG2_CALOFFSET_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_CHYCFG2_CALOFFSET_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_CHYCFG2_CALOFFSET_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_CHYCFG2_CALOFFSET_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_CHYCFG2_CALOFFSET_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_CHYCFG2_CALOFFSET_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_CHYCFG2_CALOFFSET_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_CHYCFG2_CALOFFSET_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_CHYCFG2_DATRBS ((uint32_t)0x000000F8U) /* Bit[7:3] channel y data right bit-shift value */ +#define DSMU_CHYCFG2_DATRBS_0 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_CHYCFG2_DATRBS_1 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_CHYCFG2_DATRBS_2 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_CHYCFG2_DATRBS_3 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_CHYCFG2_DATRBS_4 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for DSMU_CHYAWDSCDET register **/ +#define DSMU_CHYAWDSCDET_AWDFORD ((uint32_t)0x00C00000U) /* Bit[23:22] Analog watchdog Sinc filter order on channel y */ +#define DSMU_CHYAWDSCDET_AWDFORD_0 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_CHYAWDSCDET_AWDFORD_1 ((uint32_t)0x00800000U) /* Bit23 */ + +#define DSMU_CHYAWDSCDET_AWDFOSR ((uint32_t)0x001F0000U) /* Bit[20:16] Analog watchdog filter oversampling ratio (decimation rate) on channel y */ +#define DSMU_CHYAWDSCDET_AWDFOSR_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_CHYAWDSCDET_AWDFOSR_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_CHYAWDSCDET_AWDFOSR_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_CHYAWDSCDET_AWDFOSR_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_CHYAWDSCDET_AWDFOSR_4 ((uint32_t)0x00100000U) /* Bit20 */ + +#define DSMU_CHYAWDSCDET_BKSCDET ((uint32_t)0x0000F000U) /* Bit[15:12] Break signal assignment for short-circuit detector on channel y */ +#define DSMU_CHYAWDSCDET_BKSCDET_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_CHYAWDSCDET_BKSCDET_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_CHYAWDSCDET_BKSCDET_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_CHYAWDSCDET_BKSCDET_3 ((uint32_t)0x00008000U) /* Bit15 */ + +#define DSMU_CHYAWDSCDET_SCDETTH ((uint32_t)0x000000FFU) /* Bit[7:0] short-circuit detector threshold value for channel y */ +#define DSMU_CHYAWDSCDET_SCDETTH_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_CHYAWDSCDET_SCDETTH_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_CHYAWDSCDET_SCDETTH_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_CHYAWDSCDET_SCDETTH_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_CHYAWDSCDET_SCDETTH_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_CHYAWDSCDET_SCDETTH_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_CHYAWDSCDET_SCDETTH_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_CHYAWDSCDET_SCDETTH_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for DSMU_CHYAWDDAT register **/ +#define DSMU_CHYAWDDAT_AWDDAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Input channel y watchdog data */ +#define DSMU_CHYAWDDAT_AWDDAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_CHYAWDDAT_AWDDAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_CHYAWDDAT_AWDDAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_CHYAWDDAT_AWDDAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_CHYAWDDAT_AWDDAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_CHYAWDDAT_AWDDAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_CHYAWDDAT_AWDDAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_CHYAWDDAT_AWDDAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define DSMU_CHYAWDDAT_AWDDAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_CHYAWDDAT_AWDDAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_CHYAWDDAT_AWDDAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_CHYAWDDAT_AWDDAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_CHYAWDDAT_AWDDAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_CHYAWDDAT_AWDDAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_CHYAWDDAT_AWDDAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_CHYAWDDAT_AWDDAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for DSMU_CHYDATIN register **/ +#define DSMU_CHYDATIN_INDATAT1 ((uint32_t)0xFFFF0000U) /* Bit[31:16] Input data for channel y or channel y+1 */ +#define DSMU_CHYDATIN_INDATAT1_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_CHYDATIN_INDATAT1_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_CHYDATIN_INDATAT1_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_CHYDATIN_INDATAT1_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_CHYDATIN_INDATAT1_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_CHYDATIN_INDATAT1_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_CHYDATIN_INDATAT1_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_CHYDATIN_INDATAT1_7 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_CHYDATIN_INDATAT1_8 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_CHYDATIN_INDATAT1_9 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_CHYDATIN_INDATAT1_10 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_CHYDATIN_INDATAT1_11 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_CHYDATIN_INDATAT1_12 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_CHYDATIN_INDATAT1_13 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_CHYDATIN_INDATAT1_14 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_CHYDATIN_INDATAT1_15 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_CHYDATIN_INDATAT0 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Input data for channel y */ +#define DSMU_CHYDATIN_INDATAT0_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_CHYDATIN_INDATAT0_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_CHYDATIN_INDATAT0_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_CHYDATIN_INDATAT0_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_CHYDATIN_INDATAT0_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_CHYDATIN_INDATAT0_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_CHYDATIN_INDATAT0_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_CHYDATIN_INDATAT0_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define DSMU_CHYDATIN_INDATAT0_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_CHYDATIN_INDATAT0_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_CHYDATIN_INDATAT0_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_CHYDATIN_INDATAT0_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_CHYDATIN_INDATAT0_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_CHYDATIN_INDATAT0_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_CHYDATIN_INDATAT0_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_CHYDATIN_INDATAT0_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for DSMU_FLTXCTRL1 register **/ +#define DSMU_FLTXCTRL1_AWDFSEL ((uint32_t)0x40000000U) /* Bit[30] Analog watchdog input data selection */ +#define DSMU_FLTXCTRL1_FAST ((uint32_t)0x20000000U) /* Bit[29] Fast conversion mode selection for regular conversions */ + +#define DSMU_FLTXCTRL1_RCH ((uint32_t)0x07000000U) /* Bit[26:24] Regular conversion channel */ +#define DSMU_FLTXCTRL1_RCH_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXCTRL1_RCH_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXCTRL1_RCH_2 ((uint32_t)0x04000000U) /* Bit26 */ + +#define DSMU_FLTXCTRL1_RDMAEN ((uint32_t)0x00200000U) /* Bit[21] DMA channel enabled to read regular conversion data */ +#define DSMU_FLTXCTRL1_RSYNC ((uint32_t)0x00080000U) /* Bit[19] Launch regular conversion synchronously with DSMU_FLTX */ +#define DSMU_FLTXCTRL1_RCONT ((uint32_t)0x00040000U) /* Bit[18] Continuous mode config for regular conversions */ +#define DSMU_FLTXCTRL1_RSWSTART ((uint32_t)0x00020000U) /* Bit[17] Software trigger of a conversion on the regular channel */ + +#define DSMU_FLTXCTRL1_JEXTEN ((uint32_t)0x00006000U) /* Bit[14:13] External trigger enable and trigger active edge selection for injected conversions */ +#define DSMU_FLTXCTRL1_JEXTEN_0 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXCTRL1_JEXTEN_1 ((uint32_t)0x00004000U) /* Bit14 */ + +#define DSMU_FLTXCTRL1_JEXTSEL ((uint32_t)0x00001F00U) /* Bit[12:8] External trigger signal selection for launching injected conversions */ +#define DSMU_FLTXCTRL1_JEXTSEL_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXCTRL1_JEXTSEL_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXCTRL1_JEXTSEL_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXCTRL1_JEXTSEL_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXCTRL1_JEXTSEL_4 ((uint32_t)0x00001000U) /* Bit12 */ + +#define DSMU_FLTXCTRL1_JDMAEN ((uint32_t)0x00000020U) /* Bit[5] DMA channel enabled to read data for the injected conversion */ +#define DSMU_FLTXCTRL1_JSCAN ((uint32_t)0x00000010U) /* Bit[4] Injected scanning conversion mode */ +#define DSMU_FLTXCTRL1_JSYNC ((uint32_t)0x00000008U) /* Bit[3] Launch an injected conversion synchronously with the DSMU_FLTX JSWSTART event */ +#define DSMU_FLTXCTRL1_JSWSTART ((uint32_t)0x00000002U) /* Bit[1] Start a conversion of the injected group of channels */ +#define DSMU_FLTXCTRL1_DFLTEN ((uint32_t)0x00000001U) /* Bit[0] DSMU_FLTX enable */ + +/** Bit definition for DSMU_FLTXCTRL2 register **/ +#define DSMU_FLTXCTRL2_AWDCH ((uint32_t)0x00FF0000U) /* Bit[23:16] Analog watchdog channel selection */ +#define DSMU_FLTXCTRL2_AWDCH_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXCTRL2_AWDCH_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXCTRL2_AWDCH_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXCTRL2_AWDCH_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXCTRL2_AWDCH_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXCTRL2_AWDCH_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXCTRL2_AWDCH_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXCTRL2_AWDCH_7 ((uint32_t)0x00800000U) /* Bit23 */ + +#define DSMU_FLTXCTRL2_EXDETCH ((uint32_t)0x0000FF00U) /* Bit[15:8] Extremes detector channel selection */ +#define DSMU_FLTXCTRL2_EXDETCH_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXCTRL2_EXDETCH_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXCTRL2_EXDETCH_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXCTRL2_EXDETCH_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXCTRL2_EXDETCH_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXCTRL2_EXDETCH_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXCTRL2_EXDETCH_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXCTRL2_EXDETCH_7 ((uint32_t)0x00008000U) /* Bit15 */ + +#define DSMU_FLTXCTRL2_CLKABIEN ((uint32_t)0x00000040U) /* Bit[6] Clock absence interrupt enable */ +#define DSMU_FLTXCTRL2_SCDETIEN ((uint32_t)0x00000020U) /* Bit[5] Short-circuit detector interrupt enable */ +#define DSMU_FLTXCTRL2_AWDIEN ((uint32_t)0x00000010U) /* Bit[4] Analog watchdog interrupt enable */ +#define DSMU_FLTXCTRL2_ROVRIEN ((uint32_t)0x00000008U) /* Bit[3] Regular data overrun interrupt enable */ +#define DSMU_FLTXCTRL2_JOVRIEN ((uint32_t)0x00000004U) /* Bit[2] Injected data overrun interrupt enable */ +#define DSMU_FLTXCTRL2_REOCIEN ((uint32_t)0x00000002U) /* Bit[1] Regular conversion end interrupt enable */ +#define DSMU_FLTXCTRL2_JEOCIEN ((uint32_t)0x00000001U) /* Bit[0] Injected conversion end interrupt enable */ + +/** Bit definition for DSMU_FLTXSTS register **/ +#define DSMU_FLTXSTS_SCDETF ((uint32_t)0xFF000000U) /* Bit[31:24] short-circuit event flag */ +#define DSMU_FLTXSTS_SCDETF_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXSTS_SCDETF_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXSTS_SCDETF_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXSTS_SCDETF_3 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXSTS_SCDETF_4 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXSTS_SCDETF_5 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXSTS_SCDETF_6 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXSTS_SCDETF_7 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXSTS_CLKABF ((uint32_t)0x00FF0000U) /* Bit[23:16] Clock absence event flag */ +#define DSMU_FLTXSTS_CLKABF_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXSTS_CLKABF_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXSTS_CLKABF_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXSTS_CLKABF_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXSTS_CLKABF_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXSTS_CLKABF_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXSTS_CLKABF_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXSTS_CLKABF_7 ((uint32_t)0x00800000U) /* Bit23 */ + +#define DSMU_FLTXSTS_RCIP ((uint32_t)0x00004000U) /* Bit[14] Regular conversion active status */ +#define DSMU_FLTXSTS_JCIP ((uint32_t)0x00002000U) /* Bit[13] Injected conversion active status */ +#define DSMU_FLTXSTS_AWDF ((uint32_t)0x00000010U) /* Bit[4] Analog watchdog event flag */ +#define DSMU_FLTXSTS_ROVRF ((uint32_t)0x00000008U) /* Bit[3] Regular conversion overrun flag */ +#define DSMU_FLTXSTS_JOVRF ((uint32_t)0x00000004U) /* Bit[2] Injected conversion overrun flag */ +#define DSMU_FLTXSTS_REOCF ((uint32_t)0x00000002U) /* Bit[1] Regular conversion end event flag */ +#define DSMU_FLTXSTS_JEOCF ((uint32_t)0x00000001U) /* Bit[0] Injected conversion end event flag */ + +/** Bit definition for DSMU_FLTXINTCLR register **/ +#define DSMU_FLTXINTCLR_CLRSCDETF ((uint32_t)0xFF000000U) /* Bit[31:24] Clear the short-circuit event flag */ +#define DSMU_FLTXINTCLR_CLRSCDETF_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_3 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_4 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_5 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_6 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXINTCLR_CLRSCDETF_7 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXINTCLR_CLRCLKABF ((uint32_t)0x00FF0000U) /* Bit[23:16] Clear the clock absence flag */ +#define DSMU_FLTXINTCLR_CLRCLKABF_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXINTCLR_CLRCLKABF_7 ((uint32_t)0x00800000U) /* Bit23 */ + +#define DSMU_FLTXINTCLR_CLRROVRF ((uint32_t)0x00000008U) /* Bit[3] Clear the regular conversion overrun flag */ +#define DSMU_FLTXINTCLR_CLRJOVRF ((uint32_t)0x00000004U) /* Bit[2] Clear the injected conversion overrun flag */ + +/** Bit definition for DSMU_FLTXJCHG register **/ +#define DSMU_FLTXJCHG_JCHG ((uint32_t)0x000000FFU) /* Bit[7:0] Injected channel group selection */ +#define DSMU_FLTXJCHG_JCHG_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXJCHG_JCHG_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXJCHG_JCHG_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_FLTXJCHG_JCHG_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_FLTXJCHG_JCHG_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_FLTXJCHG_JCHG_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_FLTXJCHG_JCHG_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_FLTXJCHG_JCHG_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for DSMU_FLTXFCTRL register **/ +#define DSMU_FLTXFCTRL_FORD ((uint32_t)0xE0000000U) /* Bit[31:29] Sinc filter order */ +#define DSMU_FLTXFCTRL_FORD_0 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXFCTRL_FORD_1 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXFCTRL_FORD_2 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXFCTRL_FOSR ((uint32_t)0x03FF0000U) /* Bit[25:16] Sinc filter oversampling ratio (decimation rate) */ +#define DSMU_FLTXFCTRL_FOSR_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXFCTRL_FOSR_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXFCTRL_FOSR_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXFCTRL_FOSR_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXFCTRL_FOSR_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXFCTRL_FOSR_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXFCTRL_FOSR_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXFCTRL_FOSR_7 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXFCTRL_FOSR_8 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXFCTRL_FOSR_9 ((uint32_t)0x02000000U) /* Bit25 */ + +#define DSMU_FLTXFCTRL_IOSR ((uint32_t)0x000000FFU) /* Bit[7:0] Integrator oversampling ratio (averaging length) */ +#define DSMU_FLTXFCTRL_IOSR_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXFCTRL_IOSR_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXFCTRL_IOSR_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_FLTXFCTRL_IOSR_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_FLTXFCTRL_IOSR_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_FLTXFCTRL_IOSR_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_FLTXFCTRL_IOSR_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_FLTXFCTRL_IOSR_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for DSMU_FLTXJDAT register **/ +#define DSMU_FLTXJDAT_JDAT ((uint32_t)0xFFFFFF00U) /* Bit[31:8] Injected group conversion data */ +#define DSMU_FLTXJDAT_JDAT_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXJDAT_JDAT_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXJDAT_JDAT_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXJDAT_JDAT_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXJDAT_JDAT_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXJDAT_JDAT_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXJDAT_JDAT_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXJDAT_JDAT_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXJDAT_JDAT_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXJDAT_JDAT_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXJDAT_JDAT_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXJDAT_JDAT_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXJDAT_JDAT_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXJDAT_JDAT_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXJDAT_JDAT_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXJDAT_JDAT_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXJDAT_JDAT_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXJDAT_JDAT_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXJDAT_JDAT_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXJDAT_JDAT_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXJDAT_JDAT_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXJDAT_JDAT_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXJDAT_JDAT_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXJDAT_JDAT_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXJDAT_JDATCH ((uint32_t)0x00000007U) /* Bit[2:0] Injected channel most recently converted */ +#define DSMU_FLTXJDAT_JDATCH_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXJDAT_JDATCH_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXJDAT_JDATCH_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for DSMU_FLTXRDAT register **/ +#define DSMU_FLTXRDAT_RDAT ((uint32_t)0xFFFFFF00U) /* Bit[31:8] Regular channel conversion data */ +#define DSMU_FLTXRDAT_RDAT_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXRDAT_RDAT_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXRDAT_RDAT_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXRDAT_RDAT_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXRDAT_RDAT_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXRDAT_RDAT_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXRDAT_RDAT_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXRDAT_RDAT_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXRDAT_RDAT_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXRDAT_RDAT_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXRDAT_RDAT_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXRDAT_RDAT_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXRDAT_RDAT_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXRDAT_RDAT_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXRDAT_RDAT_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXRDAT_RDAT_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXRDAT_RDAT_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXRDAT_RDAT_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXRDAT_RDAT_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXRDAT_RDAT_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXRDAT_RDAT_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXRDAT_RDAT_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXRDAT_RDAT_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXRDAT_RDAT_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXRDAT_RPEND ((uint32_t)0x00000010U) /* Bit[4] Regular channel pending data */ + +#define DSMU_FLTXRDAT_RDATCH ((uint32_t)0x00000007U) /* Bit[2:0] Regular channel most recently converted */ +#define DSMU_FLTXRDAT_RDATCH_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXRDAT_RDATCH_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXRDAT_RDATCH_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for DSMU_FLTXAWDHT register **/ +#define DSMU_FLTXAWDHT_AWDHT ((uint32_t)0xFFFFFF00U) /* Bit[31:8] Analog watchdog threshold high */ +#define DSMU_FLTXAWDHT_AWDHT_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXAWDHT_AWDHT_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXAWDHT_AWDHT_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXAWDHT_AWDHT_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXAWDHT_AWDHT_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXAWDHT_AWDHT_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXAWDHT_AWDHT_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXAWDHT_AWDHT_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXAWDHT_AWDHT_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXAWDHT_AWDHT_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXAWDHT_AWDHT_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXAWDHT_AWDHT_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXAWDHT_AWDHT_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXAWDHT_AWDHT_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXAWDHT_AWDHT_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXAWDHT_AWDHT_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXAWDHT_AWDHT_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXAWDHT_AWDHT_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXAWDHT_AWDHT_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXAWDHT_AWDHT_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXAWDHT_AWDHT_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXAWDHT_AWDHT_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXAWDHT_AWDHT_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXAWDHT_AWDHT_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXAWDHT_BKAWDHT ((uint32_t)0x0000000FU) /* Bit[3:0] Break signal assignment to analog watchdog threshold high event */ +#define DSMU_FLTXAWDHT_BKAWDHT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXAWDHT_BKAWDHT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXAWDHT_BKAWDHT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_FLTXAWDHT_BKAWDHT_3 ((uint32_t)0x00000008U) /* Bit3 */ + +/** Bit definition for DSMU_FLTXAWDLT register **/ +#define DSMU_FLTXAWDLT_AWDLT ((uint32_t)0xFFFFFF00U) /* Bit[31:8] Analog watchdog threshold low */ +#define DSMU_FLTXAWDLT_AWDLT_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXAWDLT_AWDLT_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXAWDLT_AWDLT_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXAWDLT_AWDLT_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXAWDLT_AWDLT_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXAWDLT_AWDLT_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXAWDLT_AWDLT_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXAWDLT_AWDLT_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXAWDLT_AWDLT_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXAWDLT_AWDLT_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXAWDLT_AWDLT_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXAWDLT_AWDLT_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXAWDLT_AWDLT_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXAWDLT_AWDLT_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXAWDLT_AWDLT_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXAWDLT_AWDLT_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXAWDLT_AWDLT_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXAWDLT_AWDLT_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXAWDLT_AWDLT_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXAWDLT_AWDLT_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXAWDLT_AWDLT_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXAWDLT_AWDLT_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXAWDLT_AWDLT_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXAWDLT_AWDLT_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXAWDLT_BKAWDLT ((uint32_t)0x0000000FU) /* Bit[3:0] Break signal assignment to analog watchdog threshold low event */ +#define DSMU_FLTXAWDLT_BKAWDLT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXAWDLT_BKAWDLT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXAWDLT_BKAWDLT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_FLTXAWDLT_BKAWDLT_3 ((uint32_t)0x00000008U) /* Bit3 */ + +/** Bit definition for DSMU_FLTXAWDSTS register **/ +#define DSMU_FLTXAWDSTS_AWDHTF ((uint32_t)0x0000FF00U) /* Bit[15:8] Analog watchdog threshold high flag */ +#define DSMU_FLTXAWDSTS_AWDHTF_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXAWDSTS_AWDHTF_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXAWDSTS_AWDHTF_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXAWDSTS_AWDHTF_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXAWDSTS_AWDHTF_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXAWDSTS_AWDHTF_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXAWDSTS_AWDHTF_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXAWDSTS_AWDHTF_7 ((uint32_t)0x00008000U) /* Bit15 */ + +#define DSMU_FLTXAWDSTS_AWDLTF ((uint32_t)0x000000FFU) /* Bit[7:0] Analog watchdog threshold low flag */ +#define DSMU_FLTXAWDSTS_AWDLTF_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXAWDSTS_AWDLTF_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXAWDSTS_AWDLTF_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_FLTXAWDSTS_AWDLTF_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_FLTXAWDSTS_AWDLTF_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_FLTXAWDSTS_AWDLTF_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_FLTXAWDSTS_AWDLTF_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_FLTXAWDSTS_AWDLTF_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for DSMU_FLTXAWDCLR register **/ +#define DSMU_FLTXAWDCLR_CLRAWDHTF ((uint32_t)0x0000FF00U) /* Bit[15:8] Clear the analog watchdog threshold high flag */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXAWDCLR_CLRAWDHTF_7 ((uint32_t)0x00008000U) /* Bit15 */ + +#define DSMU_FLTXAWDCLR_CLRAWDLTF ((uint32_t)0x000000FFU) /* Bit[7:0] Clear the analog watchdog threshold low flag */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_FLTXAWDCLR_CLRAWDLTF_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for DSMU_FLTXEXDETMAX register **/ +#define DSMU_FLTXEXDETMAX_EXDETMAX ((uint32_t)0xFFFFFF00U) /* Bit[31:8] Extremes detector maximum value */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXEXDETMAX_EXDETMAX_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXEXDETMAX_EXDETMAXCH ((uint32_t)0x00000007U) /* Bit[2:0] Extremes detector maximum data channel. */ +#define DSMU_FLTXEXDETMAX_EXDETMAXCH_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXEXDETMAX_EXDETMAXCH_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXEXDETMAX_EXDETMAXCH_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for DSMU_FLTXEXDETMIN register **/ +#define DSMU_FLTXEXDETMIN_EXDETMIN ((uint32_t)0xFFFFFF00U) /* Bit[31:8] Extremes detector minimum value */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_6 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_7 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_8 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_9 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_10 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_11 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_12 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_13 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_14 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_15 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_16 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_17 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_18 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_19 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_20 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_21 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_22 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXEXDETMIN_EXDETMIN_23 ((uint32_t)0x80000000U) /* Bit31 */ + +#define DSMU_FLTXEXDETMIN_EXDETMINCH ((uint32_t)0x00000007U) /* Bit[2:0] Extremes detector minimum data channel */ +#define DSMU_FLTXEXDETMIN_EXDETMINCH_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define DSMU_FLTXEXDETMIN_EXDETMINCH_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define DSMU_FLTXEXDETMIN_EXDETMINCH_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for DSMU_FLTXCOVTIM register **/ +#define DSMU_FLTXCOVTIM_COVCNT ((uint32_t)0xFFFFFFF0U) /* Bit[31:4] 28-bit timer counting conversion time t = CNVCNT[27:0] / fDSMUCLK */ +#define DSMU_FLTXCOVTIM_COVCNT_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define DSMU_FLTXCOVTIM_COVCNT_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define DSMU_FLTXCOVTIM_COVCNT_2 ((uint32_t)0x00000040U) /* Bit6 */ +#define DSMU_FLTXCOVTIM_COVCNT_3 ((uint32_t)0x00000080U) /* Bit7 */ +#define DSMU_FLTXCOVTIM_COVCNT_4 ((uint32_t)0x00000100U) /* Bit8 */ +#define DSMU_FLTXCOVTIM_COVCNT_5 ((uint32_t)0x00000200U) /* Bit9 */ +#define DSMU_FLTXCOVTIM_COVCNT_6 ((uint32_t)0x00000400U) /* Bit10 */ +#define DSMU_FLTXCOVTIM_COVCNT_7 ((uint32_t)0x00000800U) /* Bit11 */ +#define DSMU_FLTXCOVTIM_COVCNT_8 ((uint32_t)0x00001000U) /* Bit12 */ +#define DSMU_FLTXCOVTIM_COVCNT_9 ((uint32_t)0x00002000U) /* Bit13 */ +#define DSMU_FLTXCOVTIM_COVCNT_10 ((uint32_t)0x00004000U) /* Bit14 */ +#define DSMU_FLTXCOVTIM_COVCNT_11 ((uint32_t)0x00008000U) /* Bit15 */ +#define DSMU_FLTXCOVTIM_COVCNT_12 ((uint32_t)0x00010000U) /* Bit16 */ +#define DSMU_FLTXCOVTIM_COVCNT_13 ((uint32_t)0x00020000U) /* Bit17 */ +#define DSMU_FLTXCOVTIM_COVCNT_14 ((uint32_t)0x00040000U) /* Bit18 */ +#define DSMU_FLTXCOVTIM_COVCNT_15 ((uint32_t)0x00080000U) /* Bit19 */ +#define DSMU_FLTXCOVTIM_COVCNT_16 ((uint32_t)0x00100000U) /* Bit20 */ +#define DSMU_FLTXCOVTIM_COVCNT_17 ((uint32_t)0x00200000U) /* Bit21 */ +#define DSMU_FLTXCOVTIM_COVCNT_18 ((uint32_t)0x00400000U) /* Bit22 */ +#define DSMU_FLTXCOVTIM_COVCNT_19 ((uint32_t)0x00800000U) /* Bit23 */ +#define DSMU_FLTXCOVTIM_COVCNT_20 ((uint32_t)0x01000000U) /* Bit24 */ +#define DSMU_FLTXCOVTIM_COVCNT_21 ((uint32_t)0x02000000U) /* Bit25 */ +#define DSMU_FLTXCOVTIM_COVCNT_22 ((uint32_t)0x04000000U) /* Bit26 */ +#define DSMU_FLTXCOVTIM_COVCNT_23 ((uint32_t)0x08000000U) /* Bit27 */ +#define DSMU_FLTXCOVTIM_COVCNT_24 ((uint32_t)0x10000000U) /* Bit28 */ +#define DSMU_FLTXCOVTIM_COVCNT_25 ((uint32_t)0x20000000U) /* Bit29 */ +#define DSMU_FLTXCOVTIM_COVCNT_26 ((uint32_t)0x40000000U) /* Bit30 */ +#define DSMU_FLTXCOVTIM_COVCNT_27 ((uint32_t)0x80000000U) /* Bit31 */ + +/*** Flexible Extended Memory Controller ***/ + +/** Bit definition for FEMC_STS register **/ +#define FEMC_STS_RECCINTF ((uint32_t)0x00001000U) +#define FEMC_STS_ECCINTF ((uint32_t)0x00000400U) +#define FEMC_STS_ECCINTENF ((uint32_t)0x00000100U) +#define FEMC_STS_RINT1F ((uint32_t)0x00000040U) +#define FEMC_STS_RINT0F ((uint32_t)0x00000020U) +#define FEMC_STS_INT1F ((uint32_t)0x00000010U) +#define FEMC_STS_INT0F ((uint32_t)0x00000008U) +#define FEMC_STS_INT1ENF ((uint32_t)0x00000004U) +#define FEMC_STS_INT0ENF ((uint32_t)0x00000002U) +#define FEMC_STS_LPSTS ((uint32_t)0x00000001U) + +/** Bit definition for FEMC_STS1 register **/ +#define FEMC_STS1_M0TYPE ((uint32_t)0x00000003U) +#define FEMC_STS1_M0TYPE_0 ((uint32_t)0x00000001U) +#define FEMC_STS1_M0TYPE_1 ((uint32_t)0x00000002U) + +/** Bit definition for FEMC_CFG register **/ +#define FEMC_CFG_ASYNCADV ((uint32_t)0x00000100U) +#define FEMC_CFG_ECCINTEN ((uint32_t)0x00000040U) +#define FEMC_CFG_INT1EN ((uint32_t)0x00000002U) +#define FEMC_CFG_INT0EN ((uint32_t)0x00000001U) + +/** Bit definition for FEMC_CCFG register **/ +#define FEMC_CCFG_ASYNCADVDIS ((uint32_t)0x00000100U) +#define FEMC_CCFG_ECCINTDIS ((uint32_t)0x00000040U) +#define FEMC_CCFG_INT1CLR ((uint32_t)0x00000010U) +#define FEMC_CCFG_INT0CLR ((uint32_t)0x00000008U) +#define FEMC_CCFG_INT1DIS ((uint32_t)0x00000002U) +#define FEMC_CCFG_INT0DIS ((uint32_t)0x00000001U) + +/** Bit definition for FEMC_CTRL register **/ +#define FEMC_CTRL_CHIPNUM ((uint32_t)0x03800000U) +#define FEMC_CTRL_CHIPNUM_0 ((uint32_t)0x00800000U) +#define FEMC_CTRL_CHIPNUM_1 ((uint32_t)0x01000000U) +#define FEMC_CTRL_CHIPNUM_2 ((uint32_t)0x02000000U) +#define FEMC_CTRL_CMDTYPE ((uint32_t)0x00600000U) +#define FEMC_CTRL_CMDTYPE_0 ((uint32_t)0x00200000U) +#define FEMC_CTRL_CMDTYPE_1 ((uint32_t)0x00400000U) +#define FEMC_CTRL_CREPOL ((uint32_t)0x00100000U) +#define FEMC_CTRL_ADDR ((uint32_t)0x000FFFFFU) + +/** Bit definition for FEMC_TCFG register **/ +#define FEMC_TCFG_WERR ((uint32_t)0x00700000U) +#define FEMC_TCFG_TRAR ((uint32_t)0x000E0000U) +#define FEMC_TCFG_PCCLR ((uint32_t)0x0001C000U) +#define FEMC_TCFG_WP ((uint32_t)0x00003800U) +#define FEMC_TCFG_CERE ((uint32_t)0x00000700U) +#define FEMC_TCFG_WC ((uint32_t)0x000000F0U) +#define FEMC_TCFG_RC ((uint32_t)0x0000000FU) + +/** Bit definition for FEMC_OMCFG register **/ +#define FEMC_OMCFG_BSTAGN ((uint32_t)0x0000E000U) +#define FEMC_OMCFG_BSTAGN_0 ((uint32_t)0x00002000U) +#define FEMC_OMCFG_BSTAGN_1 ((uint32_t)0x00004000U) +#define FEMC_OMCFG_BSTAGN_2 ((uint32_t)0x00008000U) +#define FEMC_OMCFG_BLSS ((uint32_t)0x00001000U) +#define FEMC_OMCFG_ADV ((uint32_t)0x00000800U) +#define FEMC_OMCFG_BAA ((uint32_t)0x00000400U) +#define FEMC_OMCFG_WRBL ((uint32_t)0x00000380U) +#define FEMC_OMCFG_WRBL_0 ((uint32_t)0x00000080U) +#define FEMC_OMCFG_WRBL_1 ((uint32_t)0x00000100U) +#define FEMC_OMCFG_WRBL_2 ((uint32_t)0x00002000U) +#define FEMC_OMCFG_WRSYN ((uint32_t)0x00000040U) +#define FEMC_OMCFG_RDBL ((uint32_t)0x00000038U) +#define FEMC_OMCFG_RDBL_0 ((uint32_t)0x00000008U) +#define FEMC_OMCFG_RDBL_1 ((uint32_t)0x00000010U) +#define FEMC_OMCFG_RDBL_2 ((uint32_t)0x00000020U) +#define FEMC_OMCFG_RDSYN ((uint32_t)0x00000004U) +#define FEMC_OMCFG_MDBW ((uint32_t)0x00000003U) +#define FEMC_OMCFG_MDBW_0 ((uint32_t)0x00000001U) +#define FEMC_OMCFG_MDBW_1 ((uint32_t)0x00000002U) + +/** Bit definition for FEMC_RPE register **/ +#define FEMC_RPE_REFPRD ((uint32_t)0x0000000FU) + +/** Bit definition for FEMC_SNTSTS1/2/3/4 register **/ +#define FEMC_SNTSTS_WECS ((uint32_t)0x00100000U) +#define FEMC_SNTSTS_TR ((uint32_t)0x000E0000U) +#define FEMC_SNTSTS_PC ((uint32_t)0x0001C000U) +#define FEMC_SNTSTS_WP ((uint32_t)0x00003800U) +#define FEMC_SNTSTS_CEOE ((uint32_t)0x00000700U) +#define FEMC_SNTSTS_WC ((uint32_t)0x000000F0U) +#define FEMC_SNTSTS_RC ((uint32_t)0x0000000FU) + +/** Bit definition for FEMC_SNOMSTS1/2/3/4 register **/ +#define FEMC_SNOMSTS_ADDRMCH ((uint32_t)0xFF000000U) +#define FEMC_SNOMSTS_ADDRMSK ((uint32_t)0x00FF0000U) +#define FEMC_SNOMSTS_BSTAGN ((uint32_t)0x0000E000U) +#define FEMC_SNOMSTS_BSTAGN_0 ((uint32_t)0x00002000U) +#define FEMC_SNOMSTS_BSTAGN_1 ((uint32_t)0x00004000U) +#define FEMC_SNOMSTS_BSTAGN_2 ((uint32_t)0x00008000U) +#define FEMC_SNOMSTS_BLSS ((uint32_t)0x00001000U) +#define FEMC_SNOMSTS_ADV ((uint32_t)0x00000800U) +#define FEMC_SNOMSTS_BAA ((uint32_t)0x00000400U) +#define FEMC_SNOMSTS_WRBL ((uint32_t)0x00000380U) +#define FEMC_SNOMSTS_WRBL_0 ((uint32_t)0x00000080U) +#define FEMC_SNOMSTS_WRBL_1 ((uint32_t)0x00000100U) +#define FEMC_SNOMSTS_WRBL_2 ((uint32_t)0x00002000U) +#define FEMC_SNOMSTS_WRSYN ((uint32_t)0x00000040U) +#define FEMC_SNOMSTS_RDBL ((uint32_t)0x00000038U) +#define FEMC_SNOMSTS_RDBL_0 ((uint32_t)0x00000008U) +#define FEMC_SNOMSTS_RDBL_1 ((uint32_t)0x00000010U) +#define FEMC_SNOMSTS_RDBL_2 ((uint32_t)0x00000020U) +#define FEMC_SNOMCFG_RDSYN ((uint32_t)0x00000004U) +#define FEMC_SNOMSTS_MDBW ((uint32_t)0x00000003U) +#define FEMC_SNOMSTS_MDBW_0 ((uint32_t)0x00000001U) +#define FEMC_SNOMSTS_MDBW_1 ((uint32_t)0x00000002U) + +/** Bit definition for FEMC_NTSTS1/2 register **/ +#define FEMC_NTSTS_RR ((uint32_t)0x00700000U) +#define FEMC_NTSTS_AR ((uint32_t)0x000E0000U) +#define FEMC_NTSTS_CLR ((uint32_t)0x0001C000U) +#define FEMC_NTSTS_WP ((uint32_t)0x00003800U) +#define FEMC_NTSTS_REA ((uint32_t)0x00000700U) +#define FEMC_NTSTS_WC ((uint32_t)0x000000F0U) +#define FEMC_NTSTS_RC ((uint32_t)0x0000000FU) + +/** Bit definition for FEMC_NOMSTS1/2 register **/ +#define FEMC_SNOMSTS_ADDRMCH ((uint32_t)0xFF000000U) +#define FEMC_SNOMSTS_ADDRMSK ((uint32_t)0x00FF0000U) +#define FEMC_SNOMSTS_MDBW ((uint32_t)0x00000003U) +#define FEMC_SNOMSTS_MDBW_0 ((uint32_t)0x00000001U) +#define FEMC_SNOMSTS_MDBW_1 ((uint32_t)0x00000002U) + +/** Bit definition for FEMC_USTS register **/ +#define FEMC_USTS_USER ((uint32_t)0x000000FFU) + +/** Bit definition for FEMC_CFG register **/ +#define FEMC_CFG_USER ((uint32_t)0x000000FFU) + +/** Bit definition for FEMC_ECCSTS register **/ +#define FEMC_ECCSTS_RDF ((uint32_t)0x3E000000U) +#define FEMC_ECCSTS_RDF_0 ((uint32_t)0x02000000U) +#define FEMC_ECCSTS_RDF_1 ((uint32_t)0x04000000U) +#define FEMC_ECCSTS_RDF_2 ((uint32_t)0x08000000U) +#define FEMC_ECCSTS_RDF_3 ((uint32_t)0x10000000U) +#define FEMC_ECCSTS_RDF_4 ((uint32_t)0x20000000U) +#define FEMC_ECCSTS_CORCTF ((uint32_t)0x01F00000U) +#define FEMC_ECCSTS_CORCTF_0 ((uint32_t)0x00100000U) +#define FEMC_ECCSTS_CORCTF_1 ((uint32_t)0x00200000U) +#define FEMC_ECCSTS_CORCTF_2 ((uint32_t)0x00400000U) +#define FEMC_ECCSTS_CORCTF_3 ((uint32_t)0x00800000U) +#define FEMC_ECCSTS_CORCTF_4 ((uint32_t)0x01000000U) +#define FEMC_ECCSTS_FAILF ((uint32_t)0x000F8000U) +#define FEMC_ECCSTS_FAILF_0 ((uint32_t)0x00008000U) +#define FEMC_ECCSTS_FAILF_1 ((uint32_t)0x00010000U) +#define FEMC_ECCSTS_FAILF_2 ((uint32_t)0x00020000U) +#define FEMC_ECCSTS_FAILF_3 ((uint32_t)0x00040000U) +#define FEMC_ECCSTS_FAILF_4 ((uint32_t)0x00080000U) +#define FEMC_ECCSTS_VLDF ((uint32_t)0x00007C00U) +#define FEMC_ECCSTS_VLDF_0 ((uint32_t)0x00000400U) +#define FEMC_ECCSTS_VLDF_1 ((uint32_t)0x00000800U) +#define FEMC_ECCSTS_VLDF_2 ((uint32_t)0x00001000U) +#define FEMC_ECCSTS_VLDF_3 ((uint32_t)0x00002000U) +#define FEMC_ECCSTS_VLDF_4 ((uint32_t)0x00004000U) +#define FEMC_ECCSTS_WRF ((uint32_t)0x00000200U) +#define FEMC_ECCSTS_LASTS ((uint32_t)0x00000180U) +#define FEMC_ECCSTS_LASTS_0 ((uint32_t)0x00000080U) +#define FEMC_ECCSTS_LASTS_1 ((uint32_t)0x00000100U) +#define FEMC_ECCSTS_BUSY ((uint32_t)0x00000040U) +#define FEMC_ECCSTS_INTF ((uint32_t)0x0000003FU) +#define FEMC_ECCSTS_INTF_0 ((uint32_t)0x00000001U) +#define FEMC_ECCSTS_INTF_1 ((uint32_t)0x00000002U) +#define FEMC_ECCSTS_INTF_2 ((uint32_t)0x00000004U) +#define FEMC_ECCSTS_INTF_3 ((uint32_t)0x00000008U) +#define FEMC_ECCSTS_INTF_4 ((uint32_t)0x00000010U) +#define FEMC_ECCSTS_INTF_5 ((uint32_t)0x00000020U) + +/** Bit definition for FEMC_ECCCFG register **/ +#define FEMC_ECCCFG_EBLKSIZ ((uint32_t)0x00001800U) +#define FEMC_ECCCFG_EBLKSIZ_0 ((uint32_t)0x00000800U) +#define FEMC_ECCCFG_EBLKSIZ_1 ((uint32_t)0x00001000U) +#define FEMC_ECCCFG_EBLKEN ((uint32_t)0x00000400U) +#define FEMC_ECCCFG_ABTINT ((uint32_t)0x00000200U) +#define FEMC_ECCCFG_RDCINT ((uint32_t)0x00000100U) +#define FEMC_ECCCFG_A8OUTMSK ((uint32_t)0x00000080U) +#define FEMC_ECCCFG_JUMP ((uint32_t)0x00000060U) +#define FEMC_ECCCFG_JUMP_0 ((uint32_t)0x00000020U) +#define FEMC_ECCCFG_JUMP_1 ((uint32_t)0x00000040U) +#define FEMC_ECCCFG_RMOD ((uint32_t)0x00000010U) +#define FEMC_ECCCFG_MOD ((uint32_t)0x0000000CU) +#define FEMC_ECCCFG_MOD_0 ((uint32_t)0x00000004U) +#define FEMC_ECCCFG_MOD_1 ((uint32_t)0x00000008U) +#define FEMC_ECCCFG_BLKNUM ((uint32_t)0x00000003U) +#define FEMC_ECCCFG_BLKNUM_0 ((uint32_t)0x00000001U) +#define FEMC_ECCCFG_BLKNUM_1 ((uint32_t)0x00000002U) + +/** Bit definition for FEMC_ECCMD0 register **/ +#define FEMC_ECCMD0_UEND ((uint32_t)0x01000000U) +#define FEMC_ECCMD0_RDEND ((uint32_t)0x00FF0000U) +#define FEMC_ECCMD0_RD ((uint32_t)0x0000FF00U) +#define FEMC_ECCMD0_WR ((uint32_t)0x000000FFU) + +/** Bit definition for FEMC_ECCMD1 register **/ +#define FEMC_ECCMD1_UEND ((uint32_t)0x01000000U) +#define FEMC_ECCMD1_RDCOLEND ((uint32_t)0x00FF0000U) +#define FEMC_ECCMD1_RDCOL ((uint32_t)0x0000FF00U) +#define FEMC_ECCMD1_WRCOL ((uint32_t)0x000000FFU) + +/** Bit definition for FEMC_ECCADDR0 register **/ +#define FEMC_ECCADDR0_ADDR ((uint32_t)0xFFFFFFFFU) + +/** Bit definition for FEMC_ECCADDR1 register **/ +#define FEMC_ECCADDR1_ADDR ((uint32_t)0x00FFFFFFU) + +/** Bit definition for FEMC_ECCBLK0/1/2/3 and FEMC_ECCEBLK register **/ +#define FEMC_ECCBLK_INTF ((uint32_t)0x80000000U) +#define FEMC_ECCBLK_VALDF ((uint32_t)0x40000000U) +#define FEMC_ECCBLK_RDF ((uint32_t)0x20000000U) +#define FEMC_ECCBLK_ERRF ((uint32_t)0x10000000U) +#define FEMC_ECCBLK_CRTF ((uint32_t)0x08000000U) +#define FEMC_ECCBLK_VAL ((uint32_t)0x00FFFFFFU) + +/** Bit definition for FEMC_SNADDR1/2/3/4 register **/ +#define FEMC_SNADDR_ADDRMCH ((uint32_t)0xFF000000U) +#define FEMC_SNADDR_ADDRMSK ((uint32_t)0x00FF0000U) + +/** Bit definition for FEMC_NADDR1/2 register **/ +#define FEMC_NADDR_ADDRMCH ((uint32_t)0xFF000000U) +#define FEMC_NADDR_ADDRMSK ((uint32_t)0x00FF0000U) + +/** Bit definition for FEMC_SNMOD register **/ +#define FEMC_SNMOD_MUXEN ((uint32_t)0x00000020U) +#define FEMC_SNMOD_AGTM ((uint32_t)0x00000010U) +#define FEMC_SNMOD_SYNC ((uint32_t)0x00000008U) + +/** Bit definition for FEMC_NMOD register **/ +#define FEMC_NMOD_CSL ((uint32_t)0x00000040U) +#define FEMC_NMOD_AGTM ((uint32_t)0x00000010U) +#define FEMC_NMOD_SYNC ((uint32_t)0x00000008U) + +/** Bit definition for FEMC_REMAP register **/ +#define FEMC_REMAP_REMAP ((uint32_t)0x00000001U) + +/*** Real-Time Clock (RTC) ***/ +/** Bits definition for RTC_TSH register **/ +#define RTC_TSH_APM ((uint32_t)0x00400000) +#define RTC_TSH_HOT ((uint32_t)0x00300000) +#define RTC_TSH_HOT_0 ((uint32_t)0x00100000) +#define RTC_TSH_HOT_1 ((uint32_t)0x00200000) +#define RTC_TSH_HOU ((uint32_t)0x000F0000) +#define RTC_TSH_HOU_0 ((uint32_t)0x00010000) +#define RTC_TSH_HOU_1 ((uint32_t)0x00020000) +#define RTC_TSH_HOU_2 ((uint32_t)0x00040000) +#define RTC_TSH_HOU_3 ((uint32_t)0x00080000) +#define RTC_TSH_MIT ((uint32_t)0x00007000) +#define RTC_TSH_MIT_0 ((uint32_t)0x00001000) +#define RTC_TSH_MIT_1 ((uint32_t)0x00002000) +#define RTC_TSH_MIT_2 ((uint32_t)0x00004000) +#define RTC_TSH_MIU ((uint32_t)0x00000F00) +#define RTC_TSH_MIU_0 ((uint32_t)0x00000100) +#define RTC_TSH_MIU_1 ((uint32_t)0x00000200) +#define RTC_TSH_MIU_2 ((uint32_t)0x00000400) +#define RTC_TSH_MIU_3 ((uint32_t)0x00000800) +#define RTC_TSH_SCT ((uint32_t)0x00000070) +#define RTC_TSH_SCT_0 ((uint32_t)0x00000010) +#define RTC_TSH_SCT_1 ((uint32_t)0x00000020) +#define RTC_TSH_SCT_2 ((uint32_t)0x00000040) +#define RTC_TSH_SCU ((uint32_t)0x0000000F) +#define RTC_TSH_SCU_0 ((uint32_t)0x00000001) +#define RTC_TSH_SCU_1 ((uint32_t)0x00000002) +#define RTC_TSH_SCU_2 ((uint32_t)0x00000004) +#define RTC_TSH_SCU_3 ((uint32_t)0x00000008) + +/** Bits definition for RTC_DATE register **/ +#define RTC_DATE_YRT ((uint32_t)0x00F00000) +#define RTC_DATE_YRT_0 ((uint32_t)0x00100000) +#define RTC_DATE_YRT_1 ((uint32_t)0x00200000) +#define RTC_DATE_YRT_2 ((uint32_t)0x00400000) +#define RTC_DATE_YRT_3 ((uint32_t)0x00800000) +#define RTC_DATE_YRU ((uint32_t)0x000F0000) +#define RTC_DATE_YRU_0 ((uint32_t)0x00010000) +#define RTC_DATE_YRU_1 ((uint32_t)0x00020000) +#define RTC_DATE_YRU_2 ((uint32_t)0x00040000) +#define RTC_DATE_YRU_3 ((uint32_t)0x00080000) +#define RTC_DATE_WDU ((uint32_t)0x0000E000) +#define RTC_DATE_WDU_0 ((uint32_t)0x00002000) +#define RTC_DATE_WDU_1 ((uint32_t)0x00004000) +#define RTC_DATE_WDU_2 ((uint32_t)0x00008000) +#define RTC_DATE_MOT ((uint32_t)0x00001000) +#define RTC_DATE_MOU ((uint32_t)0x00000F00) +#define RTC_DATE_MOU_0 ((uint32_t)0x00000100) +#define RTC_DATE_MOU_1 ((uint32_t)0x00000200) +#define RTC_DATE_MOU_2 ((uint32_t)0x00000400) +#define RTC_DATE_MOU_3 ((uint32_t)0x00000800) +#define RTC_DATE_DAT ((uint32_t)0x00000030) +#define RTC_DATE_DAT_0 ((uint32_t)0x00000010) +#define RTC_DATE_DAT_1 ((uint32_t)0x00000020) +#define RTC_DATE_DAU ((uint32_t)0x0000000F) +#define RTC_DATE_DAU_0 ((uint32_t)0x00000001) +#define RTC_DATE_DAU_1 ((uint32_t)0x00000002) +#define RTC_DATE_DAU_2 ((uint32_t)0x00000004) +#define RTC_DATE_DAU_3 ((uint32_t)0x00000008) + +/** Bits definition for RTC_CTRL register **/ +#define RTC_CTRL_CAOVIEN ((uint32_t)0x08000000) +#define RTC_CTRL_TAMPOE ((uint32_t)0x04000000) +#define RTC_CTRL_IETSEN ((uint32_t)0x01000000) +#define RTC_CTRL_COEN ((uint32_t)0x00800000) +#define RTC_CTRL_OUTSEL ((uint32_t)0x00600000) +#define RTC_CTRL_OUTSEL_0 ((uint32_t)0x00200000) +#define RTC_CTRL_OUTSEL_1 ((uint32_t)0x00400000) +#define RTC_CTRL_OPOL ((uint32_t)0x00100000) +#define RTC_CTRL_CALOSEL ((uint32_t)0x00080000) +#define RTC_CTRL_BAKP ((uint32_t)0x00040000) +#define RTC_CTRL_SU1H ((uint32_t)0x00020000) +#define RTC_CTRL_AD1H ((uint32_t)0x00010000) +#define RTC_CTRL_TSIEN ((uint32_t)0x00008000) +#define RTC_CTRL_WTIEN ((uint32_t)0x00004000) +#define RTC_CTRL_ALBIEN ((uint32_t)0x00002000) +#define RTC_CTRL_ALAIEN ((uint32_t)0x00001000) +#define RTC_CTRL_TSEN ((uint32_t)0x00000800) +#define RTC_CTRL_WTEN ((uint32_t)0x00000400) +#define RTC_CTRL_ALBEN ((uint32_t)0x00000200) +#define RTC_CTRL_ALAEN ((uint32_t)0x00000100) +#define RTC_CTRL_CAOVEN ((uint32_t)0x00000080) + +#define RTC_CTRL_HFMT ((uint32_t)0x00000040) +#define RTC_CTRL_BYPS ((uint32_t)0x00000020) +#define RTC_CTRL_REFCLKEN ((uint32_t)0x00000010) +#define RTC_CTRL_TEDGE ((uint32_t)0x00000008) +#define RTC_CTRL_WKUPSEL ((uint32_t)0x00000007) +#define RTC_CTRL_WKUPSEL_0 ((uint32_t)0x00000001) +#define RTC_CTRL_WKUPSEL_1 ((uint32_t)0x00000002) +#define RTC_CTRL_WKUPSEL_2 ((uint32_t)0x00000004) + +/** Bits definition for RTC_INITSTS register **/ +#define RTC_INITSTS_BKSRAMREF ((uint32_t)0x01000000) +#define RTC_INITSTS_IETSF ((uint32_t)0x00800000) +#define RTC_INITSTS_CAOVF ((uint32_t)0x00400000) +#define RTC_INITSTS_TAM8F ((uint32_t)0x00200000) +#define RTC_INITSTS_TAM7F ((uint32_t)0x00100000) +#define RTC_INITSTS_TAM6F ((uint32_t)0x00080000) +#define RTC_INITSTS_TAM5F ((uint32_t)0x00040000) +#define RTC_INITSTS_TAM4F ((uint32_t)0x00020000) +#define RTC_INITSTS_RECPF ((uint32_t)0x00010000) +#define RTC_INITSTS_TAM3F ((uint32_t)0x00008000) +#define RTC_INITSTS_TAM2F ((uint32_t)0x00004000) +#define RTC_INITSTS_TAM1F ((uint32_t)0x00002000) +#define RTC_INITSTS_TISOVF ((uint32_t)0x00001000) +#define RTC_INITSTS_TISF ((uint32_t)0x00000800) +#define RTC_INITSTS_WTF ((uint32_t)0x00000400) +#define RTC_INITSTS_ALBF ((uint32_t)0x00000200) +#define RTC_INITSTS_ALAF ((uint32_t)0x00000100) +#define RTC_INITSTS_INITM ((uint32_t)0x00000080) +#define RTC_INITSTS_INITF ((uint32_t)0x00000040) +#define RTC_INITSTS_RSYF ((uint32_t)0x00000020) +#define RTC_INITSTS_INITSF ((uint32_t)0x00000010) +#define RTC_INITSTS_SHOPF ((uint32_t)0x00000008) +#define RTC_INITSTS_WTWF ((uint32_t)0x00000004) +#define RTC_INITSTS_ALBWF ((uint32_t)0x00000002) +#define RTC_INITSTS_ALAWF ((uint32_t)0x00000001) + +/** Bits definition for RTC_PRE register **/ +#define RTC_PRE_DIVA ((uint32_t)0x007F0000) +#define RTC_PRE_DIVS ((uint32_t)0x00007FFF) + +/** Bits definition for RTC_WKUPT register **/ +#define RTC_WKUPT_WKUPT ((uint32_t)0x0000FFFF) + + +/** Bits definition for RTC_ALARMA register **/ +#define RTC_ALARMA_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMA_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMA_DTT ((uint32_t)0x30000000) +#define RTC_ALARMA_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMA_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMA_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMA_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMA_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMA_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMA_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMA_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMA_APM ((uint32_t)0x00400000) +#define RTC_ALARMA_HOT ((uint32_t)0x00300000) +#define RTC_ALARMA_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMA_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMA_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMA_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMA_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMA_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMA_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMA_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMA_MIT ((uint32_t)0x00007000) +#define RTC_ALARMA_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMA_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMA_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMA_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMA_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMA_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMA_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMA_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMA_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMA_SET ((uint32_t)0x00000070) +#define RTC_ALARMA_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMA_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMA_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMA_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMA_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMA_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMA_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMA_SEU_3 ((uint32_t)0x00000008) + +/** Bits definition for RTC_ALARMB register **/ +#define RTC_ALARMB_MASK4 ((uint32_t)0x80000000) +#define RTC_ALARMB_WKDSEL ((uint32_t)0x40000000) +#define RTC_ALARMB_DTT ((uint32_t)0x30000000) +#define RTC_ALARMB_DTT_0 ((uint32_t)0x10000000) +#define RTC_ALARMB_DTT_1 ((uint32_t)0x20000000) +#define RTC_ALARMB_DTU ((uint32_t)0x0F000000) +#define RTC_ALARMB_DTU_0 ((uint32_t)0x01000000) +#define RTC_ALARMB_DTU_1 ((uint32_t)0x02000000) +#define RTC_ALARMB_DTU_2 ((uint32_t)0x04000000) +#define RTC_ALARMB_DTU_3 ((uint32_t)0x08000000) +#define RTC_ALARMB_MASK3 ((uint32_t)0x00800000) +#define RTC_ALARMB_APM ((uint32_t)0x00400000) +#define RTC_ALARMB_HOT ((uint32_t)0x00300000) +#define RTC_ALARMB_HOT_0 ((uint32_t)0x00100000) +#define RTC_ALARMB_HOT_1 ((uint32_t)0x00200000) +#define RTC_ALARMB_HOU ((uint32_t)0x000F0000) +#define RTC_ALARMB_HOU_0 ((uint32_t)0x00010000) +#define RTC_ALARMB_HOU_1 ((uint32_t)0x00020000) +#define RTC_ALARMB_HOU_2 ((uint32_t)0x00040000) +#define RTC_ALARMB_HOU_3 ((uint32_t)0x00080000) +#define RTC_ALARMB_MASK2 ((uint32_t)0x00008000) +#define RTC_ALARMB_MIT ((uint32_t)0x00007000) +#define RTC_ALARMB_MIT_0 ((uint32_t)0x00001000) +#define RTC_ALARMB_MIT_1 ((uint32_t)0x00002000) +#define RTC_ALARMB_MIT_2 ((uint32_t)0x00004000) +#define RTC_ALARMB_MIU ((uint32_t)0x00000F00) +#define RTC_ALARMB_MIU_0 ((uint32_t)0x00000100) +#define RTC_ALARMB_MIU_1 ((uint32_t)0x00000200) +#define RTC_ALARMB_MIU_2 ((uint32_t)0x00000400) +#define RTC_ALARMB_MIU_3 ((uint32_t)0x00000800) +#define RTC_ALARMB_MASK1 ((uint32_t)0x00000080) +#define RTC_ALARMB_SET ((uint32_t)0x00000070) +#define RTC_ALARMB_SET_0 ((uint32_t)0x00000010) +#define RTC_ALARMB_SET_1 ((uint32_t)0x00000020) +#define RTC_ALARMB_SET_2 ((uint32_t)0x00000040) +#define RTC_ALARMB_SEU ((uint32_t)0x0000000F) +#define RTC_ALARMB_SEU_0 ((uint32_t)0x00000001) +#define RTC_ALARMB_SEU_1 ((uint32_t)0x00000002) +#define RTC_ALARMB_SEU_2 ((uint32_t)0x00000004) +#define RTC_ALARMB_SEU_3 ((uint32_t)0x00000008) + +/** Bits definition for RTC_WRP register **/ +#define RTC_WRP_PKEY ((uint32_t)0x000000FF) + +/** Bits definition for RTC_SUBS register **/ +#define RTC_SUBS_SS ((uint32_t)0x0000FFFF) + +/** Bits definition for RTC_SCTRL register **/ +#define RTC_SCTRL_AD1S ((uint32_t)0x80000000) +#define RTC_SCTRL_SUBF ((uint32_t)0x00007FFF) + + + +/** Bits definition for RTC_TST register **/ +#define RTC_TST_APM ((uint32_t)0x00400000) +#define RTC_TST_HOT ((uint32_t)0x00300000) +#define RTC_TST_HOT_0 ((uint32_t)0x00100000) +#define RTC_TST_HOT_1 ((uint32_t)0x00200000) +#define RTC_TST_HOU ((uint32_t)0x000F0000) +#define RTC_TST_HOU_0 ((uint32_t)0x00010000) +#define RTC_TST_HOU_1 ((uint32_t)0x00020000) +#define RTC_TST_HOU_2 ((uint32_t)0x00040000) +#define RTC_TST_HOU_3 ((uint32_t)0x00080000) +#define RTC_TST_MIT ((uint32_t)0x00007000) +#define RTC_TST_MIT_0 ((uint32_t)0x00001000) +#define RTC_TST_MIT_1 ((uint32_t)0x00002000) +#define RTC_TST_MIT_2 ((uint32_t)0x00004000) +#define RTC_TST_MIU ((uint32_t)0x00000F00) +#define RTC_TST_MIU_0 ((uint32_t)0x00000100) +#define RTC_TST_MIU_1 ((uint32_t)0x00000200) +#define RTC_TST_MIU_2 ((uint32_t)0x00000400) +#define RTC_TST_MIU_3 ((uint32_t)0x00000800) +#define RTC_TST_SET ((uint32_t)0x00000070) +#define RTC_TST_SET_0 ((uint32_t)0x00000010) +#define RTC_TST_SET_1 ((uint32_t)0x00000020) +#define RTC_TST_SET_2 ((uint32_t)0x00000040) +#define RTC_TST_SEU ((uint32_t)0x0000000F) +#define RTC_TST_SEU_0 ((uint32_t)0x00000001) +#define RTC_TST_SEU_1 ((uint32_t)0x00000002) +#define RTC_TST_SEU_2 ((uint32_t)0x00000004) +#define RTC_TST_SEU_3 ((uint32_t)0x00000008) + +/** Bits definition for RTC_TSD register **/ +#define RTC_TSD_YRT ((uint32_t)0x00F00000) +#define RTC_TSD_YRT_0 ((uint32_t)0x00100000) +#define RTC_TSD_YRT_1 ((uint32_t)0x00200000) +#define RTC_TSD_YRT_2 ((uint32_t)0x00400000) +#define RTC_TSD_YRT_3 ((uint32_t)0x00800000) +#define RTC_TSD_YRU ((uint32_t)0x000F0000) +#define RTC_TSD_YRU_0 ((uint32_t)0x00010000) +#define RTC_TSD_YRU_1 ((uint32_t)0x00020000) +#define RTC_TSD_YRU_2 ((uint32_t)0x00040000) +#define RTC_TSD_YRU_3 ((uint32_t)0x00080000) + +#define RTC_TSD_WDU ((uint32_t)0x0000E000) +#define RTC_TSD_WDU_0 ((uint32_t)0x00002000) +#define RTC_TSD_WDU_1 ((uint32_t)0x00004000) +#define RTC_TSD_WDU_2 ((uint32_t)0x00008000) +#define RTC_TSD_MOT ((uint32_t)0x00001000) +#define RTC_TSD_MOU ((uint32_t)0x00000F00) +#define RTC_TSD_MOU_0 ((uint32_t)0x00000100) +#define RTC_TSD_MOU_1 ((uint32_t)0x00000200) +#define RTC_TSD_MOU_2 ((uint32_t)0x00000400) +#define RTC_TSD_MOU_3 ((uint32_t)0x00000800) +#define RTC_TSD_DAT ((uint32_t)0x00000030) +#define RTC_TSD_DAT_0 ((uint32_t)0x00000010) +#define RTC_TSD_DAT_1 ((uint32_t)0x00000020) +#define RTC_TSD_DAU ((uint32_t)0x0000000F) +#define RTC_TSD_DAU_0 ((uint32_t)0x00000001) +#define RTC_TSD_DAU_1 ((uint32_t)0x00000002) +#define RTC_TSD_DAU_2 ((uint32_t)0x00000004) +#define RTC_TSD_DAU_3 ((uint32_t)0x00000008) + +/** Bits definition for RTC_TSSS register **/ +#define RTC_TSSS_SSE ((uint32_t)0x0000FFFF) + +/** Bits definition for RTC_CALIB register **/ +#define RTC_CALIB_CP ((uint32_t)0x00008000) +#define RTC_CALIB_CW8 ((uint32_t)0x00004000) +#define RTC_CALIB_CW16 ((uint32_t)0x00002000) +#define RTC_CALIB_CM ((uint32_t)0x000001FF) +#define RTC_CALIB_CM_0 ((uint32_t)0x00000001) +#define RTC_CALIB_CM_1 ((uint32_t)0x00000002) +#define RTC_CALIB_CM_2 ((uint32_t)0x00000004) +#define RTC_CALIB_CM_3 ((uint32_t)0x00000008) +#define RTC_CALIB_CM_4 ((uint32_t)0x00000010) +#define RTC_CALIB_CM_5 ((uint32_t)0x00000020) +#define RTC_CALIB_CM_6 ((uint32_t)0x00000040) +#define RTC_CALIB_CM_7 ((uint32_t)0x00000080) +#define RTC_CALIB_CM_8 ((uint32_t)0x00000100) + +/** Bits definition for RTC_ALRMASS register **/ +#define RTC_ALRMASS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMASS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMASS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMASS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMASS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMASS_SSV ((uint32_t)0x00007FFF) + +/** Bits definition for RTC_ALRMBSS register **/ +#define RTC_ALRMBSS_MASKSSB ((uint32_t)0x0F000000) +#define RTC_ALRMBSS_MASKSSB_0 ((uint32_t)0x01000000) +#define RTC_ALRMBSS_MASKSSB_1 ((uint32_t)0x02000000) +#define RTC_ALRMBSS_MASKSSB_2 ((uint32_t)0x04000000) +#define RTC_ALRMBSS_MASKSSB_3 ((uint32_t)0x08000000) +#define RTC_ALRMBSS_SSV ((uint32_t)0x00007FFF) + +/** Bits definition for RTC_OPT register **/ +#define RTC_OPT_OPDC ((uint32_t)0x00000080) +#define RTC_OPT_OUTMAP ((uint32_t)0x00000008) +#define RTC_OPT_OUTPU ((uint32_t)0x00000004) +#define RTC_OPT_PWREST ((uint32_t)0x00000002) +#define RTC_OPT_TYPE ((uint32_t)0x00000001) + +/** Bits definition for RTC_BKP1 register **/ +#define RTC_BKP1 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP2 register **/ +#define RTC_BKP2 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP3 register **/ +#define RTC_BKP3 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP4 register **/ +#define RTC_BKP4 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP5 register **/ +#define RTC_BKP5 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP6 register **/ +#define RTC_BKP6 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP7 register **/ +#define RTC_BKP7 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP8 register **/ +#define RTC_BKP8 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP9 register **/ +#define RTC_BKP9 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP10 register **/ +#define RTC_BKP10 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP11 register **/ +#define RTC_BKP11 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP12register **/ +#define RTC_BKP12 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP13 register **/ +#define RTC_BKP13 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP14 register **/ +#define RTC_BKP14 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP15 register **/ +#define RTC_BKP15 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP16 register **/ +#define RTC_BKP16 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP17register **/ +#define RTC_BKP17 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP18 register **/ +#define RTC_BKP18 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP19 register **/ +#define RTC_BKP19 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP20 register **/ +#define RTC_BKP20 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP21 register **/ +#define RTC_BKP21 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP22 register **/ +#define RTC_BKP22 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP23 register **/ +#define RTC_BKP23 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP24 register **/ +#define RTC_BKP24 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP25 register **/ +#define RTC_BKP25 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP26 register **/ +#define RTC_BKP26 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP27 register **/ +#define RTC_BKP27 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP28 register **/ +#define RTC_BKP28 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP29 register **/ +#define RTC_BKP29 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP30 register **/ +#define RTC_BKP30 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP31 register **/ +#define RTC_BKP31 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_BKP32 register **/ +#define RTC_BKP32 ((uint32_t)0xFFFFFFFF) + +/** Bits definition for RTC_TMPCFG register **/ +#define RTC_TMPCFG_TPPUDIS ((uint32_t)0x00008000) +#define RTC_TMPCFG_TPPRCH ((uint32_t)0x00006000) +#define RTC_TMPCFG_TPPRCH_0 ((uint32_t)0x00002000) +#define RTC_TMPCFG_TPPRCH_1 ((uint32_t)0x00004000) +#define RTC_TMPCFG_TPFLT ((uint32_t)0x00001800) +#define RTC_TMPCFG_TPFLT_0 ((uint32_t)0x00000800) +#define RTC_TMPCFG_TPFLT_1 ((uint32_t)0x00001000) +#define RTC_TMPCFG_TPFREQ ((uint32_t)0x00000700) +#define RTC_TMPCFG_TPFREQ_0 ((uint32_t)0x00000100) +#define RTC_TMPCFG_TPFREQ_1 ((uint32_t)0x00000200) +#define RTC_TMPCFG_TPFREQ_2 ((uint32_t)0x00000400) +#define RTC_TMPCFG_TPTS ((uint32_t)0x00000080) +#define RTC_TMPCFG_TPINIEN ((uint32_t)0x00000004) + +/** Bits definition for RTC_TMPCTRL1/2/3/4/5/6/7/8 register **/ +#define RTC_TMPCTRL_TPMF ((uint32_t)0x00000010) +#define RTC_TMPCTRL_TPNOE ((uint32_t)0x00000008) +#define RTC_TMPCTRL_TPINTEN ((uint32_t)0x00000004) +#define RTC_TMPCTRL_TPTRG ((uint32_t)0x00000002) +#define RTC_TMPCTRL_TPEN ((uint32_t)0x00000001) + + +/*** FMAC ***/ +/*** Filter Math Accelerator (FMAC) ***/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1BASE ((uint32_t)0x000000FFU) /* bit[7:0] X1 buffer Base address bits[7:0] */ +#define FMAC_X1BUFCFG_X1BUFSIZE ((uint32_t)0x0000FF00U) /* bit[15:8] X1 buffer size(16-bit words) bits[7:0] */ +#define FMAC_X1BUFCFG_X1BUFWM ((uint32_t)0x03000000U) /* bit[25:24] X1 buffer full watermark size bits[1:0] */ +#define FMAC_X1BUFCFG_X1BUFWM_0 ((uint32_t)0x01000000U) /* bit[24] Watermark bit 0 */ +#define FMAC_X1BUFCFG_X1BUFWM_1 ((uint32_t)0x02000000U) /* bit[25] Watermark bit 1 */ + +/***************** Bit definition for FMAC_X2BUFCFG register ************/ +#define FMAC_X2BUFCFG_X2BASE ((uint32_t)0x000000FFU) /* bit[7:0] X2 buffer Base address bits[7:0] */ +#define FMAC_X2BUFCFG_X2BUFSIZE ((uint32_t)0x0000FF00U) /* bit[15:8] X2 buffer size(16-bit words) bits[7:0] */ + +/***************** Bit definition for FMAC_YBUFCFG register *************/ +#define FMAC_YBUFCFG_YBASE ((uint32_t)0x000000FFU) /* bit[7:0] Y buffer Base address bits[7:0] */ +#define FMAC_YBUFCFG_YBUFSIZE ((uint32_t)0x0000FF00U) /* bit[15:8] Y buffer size(16-bit words) bits[7:0] */ +#define FMAC_YBUFCFG_YBUFWM ((uint32_t)0x03000000U) /* bit[25:24] Y buffer full watermark size bits[1:0] */ +#define FMAC_YBUFCFG_YBUFWM_0 ((uint32_t)0x01000000U) /* bit[24] Watermark bit 0 */ +#define FMAC_YBUFCFG_YBUFWM_1 ((uint32_t)0x02000000U) /* bit[25] Watermark bit 1 */ + +/****************** Bit definition for FMAC_PARAMCFG register **************/ +#define FMAC_PARAMCFG_P ((uint32_t)0x000000FFU) /* bit[ 7: 0] Input parameter P bits[7:0] */ +#define FMAC_PARAMCFG_Q ((uint32_t)0x0000FF00U) /* bit[15: 8] Input parameter Q bits[7:0] */ +#define FMAC_PARAMCFG_R ((uint32_t)0x00FF0000U) /* bit[23:16] Input parameter R bits[7:0] */ +#define FMAC_PARAMCFG_FUNC ((uint32_t)0x7F000000U) /* bit[30:24] Function bits[6:0] */ +#define FMAC_PARAMCFG_START ((uint32_t)0x80000000U) /* bit[31] Enable execution bit */ + +/******************** Bit definition for FMAC_CTRL register ***************/ +#define FMAC_CTRL_RINTEN ((uint32_t)0x00000001U) /* bit[0] Enable read interrupt */ +#define FMAC_CTRL_WIINEN ((uint32_t)0x00000002U) /* bit[1] Enable write interrupt */ +#define FMAC_CTRL_OVINTEN ((uint32_t)0x00000004U) /* bit[2] Enable overflow error interrupts */ +#define FMAC_CTRL_UNINTEN ((uint32_t)0x00000008U) /* bit[3] Enable underflow error interrupts */ +#define FMAC_CTRL_SATINTEN ((uint32_t)0x00000010U) /* bit[4] Enable saturation error interrupts */ +#define FMAC_CTRL_DMAREN ((uint32_t)0x00000100U) /* bit[8] Enable DMA read channel requests */ +#define FMAC_CTRL_DMAWEN ((uint32_t)0x00000200U) /* bit[9] Enable DMA write channel requests */ +#define FMAC_CTRL_LIMITEN ((uint32_t)0x00008000U) /* bit[15] Enable limit */ +#define FMAC_CTRL_RESET ((uint32_t)0x00010000U) /* bit[16] Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_STS register ****************/ +#define FMAC_STS_YBUFEF ((uint32_t)0x00000001U) /* bit[0] Y buffer empty flag */ +#define FMAC_STS_X1BUFFF ((uint32_t)0x00000002U) /* bit[1] X1 buffer full flag */ +#define FMAC_STS_OVF ((uint32_t)0x00000100U) /* bit[8] Overflow error flag */ +#define FMAC_STS_UNF ((uint32_t)0x00000200U) /* bit[9] Underflow error flag */ +#define FMAC_STS_SATF ((uint32_t)0x00000400U) /* bit[10] Saturation error flag */ + +/****************** Bit definition for FMAC_WDAT register **************/ +#define FMAC_WDAT_WDAT ((uint32_t)0x0000FFFFU) /* bit[15:0] Write data */ + +/****************** Bit definition for FMACX_RDAT register *************/ +#define FMAC_RDAT_RDAT ((uint32_t)0x0000FFFFU) /* bit[15:0] Read data */ + + +/** Bit definition for SHRTIM_MCTRL register **/ +#define SHRTIM_MCTRL_BRSTDMA ((uint32_t)0xC0000000U) /* Bit[31:30] Burst DMA update */ +#define SHRTIM_MCTRL_BRSTDMA_0 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_MCTRL_BRSTDMA_1 ((uint32_t)0x80000000U) /* Bit31 */ +#define SHRTIM_MCTRL_MREPTUEN ((uint32_t)0x20000000U) /* Bit[29] Master timer repetitiion update */ +#define SHRTIM_MCTRL_PLEN ((uint32_t)0x08000000U) /* Bit[27] Preload enable */ +#define SHRTIM_MCTRL_DACTRIG ((uint32_t)0x06000000U) /* Bit[26:25] DAC synchronization trigger */ +#define SHRTIM_MCTRL_DACTRIG_0 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_MCTRL_DACTRIG_1 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_MCTRL_TFCNTEN ((uint32_t)0x00400000U) /* Bit[22] Timer F counter enable */ +#define SHRTIM_MCTRL_TECNTEN ((uint32_t)0x00200000U) /* Bit[21] Timer E counter enable */ +#define SHRTIM_MCTRL_TDCNTEN ((uint32_t)0x00100000U) /* Bit[20] Timer D counter enable */ +#define SHRTIM_MCTRL_TCCNTEN ((uint32_t)0x00080000U) /* Bit[19] Timer C counter enable */ +#define SHRTIM_MCTRL_TBCNTEN ((uint32_t)0x00040000U) /* Bit[18] Timer B counter enable */ +#define SHRTIM_MCTRL_TACNTEN ((uint32_t)0x00020000U) /* Bit[17] Timer A counter enable */ +#define SHRTIM_MCTRL_MCNTEN ((uint32_t)0x00010000U) /* Bit[16] Master timer counter enable */ +#define SHRTIM_MCTRL_SYNCOSRC ((uint32_t)0x0000C000U) /* Bit[15:14] Synchronization source */ +#define SHRTIM_MCTRL_SYNCOSRC_0 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MCTRL_SYNCOSRC_1 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_MCTRL_SYNCSTRT ((uint32_t)0x00002000U) /* Bit[13] Synchronization to allow master start */ +#define SHRTIM_MCTRL_SYNCRST ((uint32_t)0x00001000U) /* Bit[12] Synchronization to allow master reset */ +#define SHRTIM_MCTRL_SYNCIN ((uint32_t)0x00000700U) /* Bit[10:8] Synchronization input */ +#define SHRTIM_MCTRL_SYNCIN_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MCTRL_SYNCIN_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MCTRL_SYNCIN_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MCTRL_ILV ((uint32_t)0x000000C0U) /* Bit[7:6] Master interleaved mode */ +#define SHRTIM_MCTRL_ILV_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MCTRL_ILV_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MCTRL_HLF ((uint32_t)0x00000020U) /* Bit[5] Half mode. */ +#define SHRTIM_MCTRL_RTG ((uint32_t)0x00000010U) /* Bit[4] Master retrigger mode */ +#define SHRTIM_MCTRL_CONT ((uint32_t)0x00000008U) /* Bit[3] Master continues mode */ +#define SHRTIM_MCTRL_CKPSC ((uint32_t)0x00000007U) /* Bit[2:0] Master clock prescaler */ +#define SHRTIM_MCTRL_CKPSC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MCTRL_CKPSC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MCTRL_CKPSC_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for SHRTIM_MINTSTS register **/ +#define SHRTIM_MINTSTS_MUPDITF ((uint32_t)0x00000040U) /* Bit[6] Master registers update interrupt flag */ +#define SHRTIM_MINTSTS_SYNCINITF ((uint32_t)0x00000020U) /* Bit[5] Synchronization input interrupt flag */ +#define SHRTIM_MINTSTS_MREPTITF ((uint32_t)0x00000010U) /* Bit[4] Master repetition interrupt flag */ +#define SHRTIM_MINTSTS_MCMP4ITF ((uint32_t)0x00000008U) /* Bit[3] Master timer compare 4 interrupt flag */ +#define SHRTIM_MINTSTS_MCMP3ITF ((uint32_t)0x00000004U) /* Bit[2] Master timer compare 3 interrupt flag */ +#define SHRTIM_MINTSTS_MCMP2ITF ((uint32_t)0x00000002U) /* Bit[1] Master timer compare 2 interrupt flag */ +#define SHRTIM_MINTSTS_MCMP1ITF ((uint32_t)0x00000001U) /* Bit[0] Master timer compare 1 interrupt flag */ + +/** Bit definition for SHRTIM_MINTCLR register **/ +#define SHRTIM_MINTCLR_MUPDIC ((uint32_t)0x00000040U) /* Bit[6] Master update interrupt flag clear */ +#define SHRTIM_MINTCLR_SYNCINIC ((uint32_t)0x00000020U) /* Bit[5] Master sync interrupt flag clear */ +#define SHRTIM_MINTCLR_MREPTIC ((uint32_t)0x00000010U) /* Bit[4] Master repetition interrupt flag clear */ +#define SHRTIM_MINTCLR_MCMP4IC ((uint32_t)0x00000008U) /* Bit[3] Master compare4 interrupt flag clear */ +#define SHRTIM_MINTCLR_MCMP3IC ((uint32_t)0x00000004U) /* Bit[2] Master compare3 interrupt flag clear */ +#define SHRTIM_MINTCLR_MCMP2IC ((uint32_t)0x00000002U) /* Bit[1] Master compare2 interrupt flag clear */ +#define SHRTIM_MINTCLR_MCMP1IC ((uint32_t)0x00000001U) /* Bit[0] Master compare1 interrupt flag clear */ + +/** Bit definition for SHRTIM_MIDEN register **/ +#define SHRTIM_MIDEN_MUPDDEN ((uint32_t)0x00400000U) /* Bit[22] Master registers update DMA request enable */ +#define SHRTIM_MIDEN_SYNCINDEN ((uint32_t)0x00200000U) /* Bit[21] Synchronization input DMA request enable */ +#define SHRTIM_MIDEN_MREPTDEN ((uint32_t)0x00100000U) /* Bit[20] Master repetition counter DMA request enable */ +#define SHRTIM_MIDEN_MCMP4DEN ((uint32_t)0x00080000U) /* Bit[19] Master timer compare 4 DMA request enable */ +#define SHRTIM_MIDEN_MCMP3DEN ((uint32_t)0x00040000U) /* Bit[18] Master timer compare 3 DMA request enable */ +#define SHRTIM_MIDEN_MCMP2DEN ((uint32_t)0x00020000U) /* Bit[17] Master timer compare 2 DMA request enable */ +#define SHRTIM_MIDEN_MCMP1DEN ((uint32_t)0x00010000U) /* Bit[16] Master timer compare 1 DMA request enable */ +#define SHRTIM_MIDEN_MUPDIEN ((uint32_t)0x00000040U) /* Bit[6] Master registers update interrupt request enable */ +#define SHRTIM_MIDEN_SYNCINIEN ((uint32_t)0x00000020U) /* Bit[5] Synchronization input interrupt request enable */ +#define SHRTIM_MIDEN_MREPTIEN ((uint32_t)0x00000010U) /* Bit[4] Master repetition counter interrupt request enable */ +#define SHRTIM_MIDEN_MCMP4IEN ((uint32_t)0x00000008U) /* Bit[3] Master timer compare 4 interrupt request enable */ +#define SHRTIM_MIDEN_MCMP3IEN ((uint32_t)0x00000004U) /* Bit[2] Master timer compare 3 interrupt request enable */ +#define SHRTIM_MIDEN_MCMP2IEN ((uint32_t)0x00000002U) /* Bit[1] Master timer compare 2 interrupt request enable */ +#define SHRTIM_MIDEN_MCMP1IEN ((uint32_t)0x00000001U) /* Bit[0] Master timer compare 1 interrupt request enable */ + +/** Bit definition for SHRTIM_MCNT register **/ +#define SHRTIM_MCNT_MCOUNT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Master timer counter */ +#define SHRTIM_MCNT_MCOUNT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MCNT_MCOUNT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MCNT_MCOUNT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MCNT_MCOUNT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MCNT_MCOUNT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MCNT_MCOUNT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MCNT_MCOUNT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MCNT_MCOUNT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MCNT_MCOUNT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MCNT_MCOUNT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MCNT_MCOUNT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MCNT_MCOUNT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_MCNT_MCOUNT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_MCNT_MCOUNT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_MCNT_MCOUNT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MCNT_MCOUNT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_MPRD register **/ +#define SHRTIM_MPRD_MPRD ((uint32_t)0x0000FFFFU) /* Bit[15:0] Master timer period */ +#define SHRTIM_MPRD_MPRD_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MPRD_MPRD_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MPRD_MPRD_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MPRD_MPRD_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MPRD_MPRD_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MPRD_MPRD_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MPRD_MPRD_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MPRD_MPRD_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MPRD_MPRD_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MPRD_MPRD_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MPRD_MPRD_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MPRD_MPRD_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_MPRD_MPRD_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_MPRD_MPRD_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_MPRD_MPRD_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MPRD_MPRD_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_MREPT register **/ +#define SHRTIM_MREPT_MREPT ((uint32_t)0x000000FFU) /* Bit[7:0] Master timer repetition period */ +#define SHRTIM_MREPT_MREPT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MREPT_MREPT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MREPT_MREPT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MREPT_MREPT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MREPT_MREPT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MREPT_MREPT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MREPT_MREPT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MREPT_MREPT_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for SHRTIM_MCMP1DAT register **/ +#define SHRTIM_MCMP1DAT_MCMP1DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Master timer compare 1 data */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MCMP1DAT_MCMP1DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_MCMP2DAT register **/ +#define SHRTIM_MCMP2DAT_MCMP2DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Master timer compare 2 data */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MCMP2DAT_MCMP2DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_MCMP3DAT register **/ +#define SHRTIM_MCMP3DAT_MCMP3DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Master timer compare 3 data */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MCMP3DAT_MCMP3DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_MCMP4DAT register **/ +#define SHRTIM_MCMP4DAT_MCMP4DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Master timer compare 4 data */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_MCMP4DAT_MCMP4DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_SYNCOUT register **/ +#define SHRTIM_SYNCOUT_SYNCOUTPUS ((uint32_t)0x00000003U) /* Bit[1:0] These bitfield define the polarity of synchronization output. */ +#define SHRTIM_SYNCOUT_SYNCOUTPUS_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_SYNCOUT_SYNCOUTPUS_1 ((uint32_t)0x00000002U) /* Bit1 */ + +/** Bit definition for SHRTIM_FRZDIS register **/ +#define SHRTIM_FRZDIS_ALLTIMDBGEN ((uint32_t)0x00000080U) /* Bit[7] Debug freeze bit used to hault all timers (master + slave) while in debug mode */ +#define SHRTIM_FRZDIS_TFDBGEN ((uint32_t)0x00000040U) /* Bit[6] Debug freeze bit used to skip haulting the timer F while in debug mode */ +#define SHRTIM_FRZDIS_TEDBGEN ((uint32_t)0x00000020U) /* Bit[5] Debug freeze bit used to skip haulting the timer E while in debug mode */ +#define SHRTIM_FRZDIS_TDDBGEN ((uint32_t)0x00000010U) /* Bit[4] Debug freeze bit used to skip haulting the timer D while in debug mode */ +#define SHRTIM_FRZDIS_TCDBGEN ((uint32_t)0x00000008U) /* Bit[3] Debug freeze bit used to skip haulting the timer C while in debug mode */ +#define SHRTIM_FRZDIS_TBDBGEN ((uint32_t)0x00000004U) /* Bit[2] Debug freeze bit used to skip haulting the timer B while in debug mode */ +#define SHRTIM_FRZDIS_TADBGEN ((uint32_t)0x00000002U) /* Bit[1] Debug freeze bit used to skip haulting the timer A while in debug mode */ +#define SHRTIM_FRZDIS_MDBGEN ((uint32_t)0x00000001U) /* Bit[0] Debug freeze bit used to skip haulting the master timer while in debug mode */ + +/** Bit definition for SHRTIM_TXCTRL register **/ +#define SHRTIM_TXCTRL_UPDGAT ((uint32_t)0xF0000000U) /* Bit[31:28] Register update events for timer x */ +#define SHRTIM_TXCTRL_UPDGAT_0 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_TXCTRL_UPDGAT_1 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_TXCTRL_UPDGAT_2 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_TXCTRL_UPDGAT_3 ((uint32_t)0x80000000U) /* Bit31 */ +#define SHRTIM_TXCTRL_PLEN ((uint32_t)0x08000000U) /* Bit[27] timer x preload enable */ +#define SHRTIM_TXCTRL_DACTRIG ((uint32_t)0x06000000U) /* Bit[26:25] The update event can be used to generate a DAC synchronization. The active output is chosen based on this register configuration. */ +#define SHRTIM_TXCTRL_DACTRIG_0 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_TXCTRL_DACTRIG_1 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_TXCTRL_MUEN ((uint32_t)0x01000000U) /* Bit[24] Master timer update */ +#define SHRTIM_TXCTRL_TEUEN ((uint32_t)0x00800000U) /* Bit[23] Timer E update */ +#define SHRTIM_TXCTRL_TDUEN ((uint32_t)0x00400000U) /* Bit[22] Timer D update */ +#define SHRTIM_TXCTRL_TCUEN ((uint32_t)0x00200000U) /* Bit[21] Timer C update */ +#define SHRTIM_TXCTRL_TBUEN ((uint32_t)0x00100000U) /* Bit[20] Timer B update */ +#define SHRTIM_TXCTRL_TAUEN ((uint32_t)0x00080000U) /* Bit[19] Timer A update */ +#define SHRTIM_TXCTRL_RSTROUEN ((uint32_t)0x00040000U) /* Bit[18] Timer A reset update */ +#define SHRTIM_TXCTRL_REPTUEN ((uint32_t)0x00020000U) /* Bit[17] Timer A repetitiion update */ +#define SHRTIM_TXCTRL_TFUEN ((uint32_t)0x00010000U) /* Bit[16] Timer F update */ +#define SHRTIM_TXCTRL_DELCMP4M ((uint32_t)0x0000C000U) /* Bit[15:14] CMP4 delayed mode */ +#define SHRTIM_TXCTRL_DELCMP4M_0 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCTRL_DELCMP4M_1 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_TXCTRL_DELCMP2M ((uint32_t)0x00003000U) /* Bit[13:12] CMP2 delayed mode */ +#define SHRTIM_TXCTRL_DELCMP2M_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCTRL_DELCMP2M_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCTRL_SYNCSTRT ((uint32_t)0x00000800U) /* Bit[11] Synchronizationto allow timer x start */ +#define SHRTIM_TXCTRL_SYNCRST ((uint32_t)0x00000400U) /* Bit[10] Synchronizationto allow timer x reset */ +#define SHRTIM_TXCTRL_RSYNCUPD ((uint32_t)0x00000200U) /* Bit[9] Update on resynchronization */ +#define SHRTIM_TXCTRL_ILV ((uint32_t)0x00000180U) /* Bit[8:7] Timer A interleaved mode */ +#define SHRTIM_TXCTRL_ILV_0 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCTRL_ILV_1 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCTRL_PP ((uint32_t)0x00000040U) /* Bit[6] Push pull mode enable */ +#define SHRTIM_TXCTRL_HLF ((uint32_t)0x00000020U) /* Bit[5] Half mode. */ +#define SHRTIM_TXCTRL_RTG ((uint32_t)0x00000010U) /* Bit[4] Retrigger mode */ +#define SHRTIM_TXCTRL_CONT ((uint32_t)0x00000008U) /* Bit[3] Continuous mode */ +#define SHRTIM_TXCTRL_CKPSC ((uint32_t)0x00000007U) /* Bit[2:0] Clock prescaler */ +#define SHRTIM_TXCTRL_CKPSC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCTRL_CKPSC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCTRL_CKPSC_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for SHRTIM_TXINTSTS register **/ +#define SHRTIM_TXINTSTS_O2BCKUP ((uint32_t)0x00200000U) /* Bit[21] Timer x channel 2 output backup. */ +#define SHRTIM_TXINTSTS_O1BCKUP ((uint32_t)0x00100000U) /* Bit[20] Timer x channel 2 output backup. */ +#define SHRTIM_TXINTSTS_O2DIPSTS ((uint32_t)0x00080000U) /* Bit[19] Timer x channnel 2 delayed idle protection status. */ +#define SHRTIM_TXINTSTS_O1DIPSTS ((uint32_t)0x00040000U) /* Bit[18] Timer x channnel 1 delayed idle protection status. */ +#define SHRTIM_TXINTSTS_IPPSTS ((uint32_t)0x00020000U) /* Bit[17] Idle push pull status. */ +#define SHRTIM_TXINTSTS_CPPSTS ((uint32_t)0x00010000U) /* Bit[16] Push pull status */ +#define SHRTIM_TXINTSTS_DPITF ((uint32_t)0x00004000U) /* Bit[14] Delayed protection interrupt flag */ +#define SHRTIM_TXINTSTS_RSTROITF ((uint32_t)0x00002000U) /* Bit[13] Counter reset or roll-over status */ +#define SHRTIM_TXINTSTS_RST2ITF ((uint32_t)0x00001000U) /* Bit[12] Output 2 reset interrupt flag */ +#define SHRTIM_TXINTSTS_SET2ITF ((uint32_t)0x00000800U) /* Bit[11] Output 2 set interrupt flag */ +#define SHRTIM_TXINTSTS_RST1ITF ((uint32_t)0x00000400U) /* Bit[10] Output 1 reset interrupt flag */ +#define SHRTIM_TXINTSTS_SET1ITF ((uint32_t)0x00000200U) /* Bit[9] Output 1 set interrupt flag */ +#define SHRTIM_TXINTSTS_CPT2ITF ((uint32_t)0x00000100U) /* Bit[8] Capture 2 interrupt flag */ +#define SHRTIM_TXINTSTS_CPT1ITF ((uint32_t)0x00000080U) /* Bit[7] Capture 1 interrupt flag */ +#define SHRTIM_TXINTSTS_UPDITF ((uint32_t)0x00000040U) /* Bit[6] Update interrupt flag */ +#define SHRTIM_TXINTSTS_REPTITF ((uint32_t)0x00000020U) /* Bit[5] Repetition interrupt flag */ +#define SHRTIM_TXINTSTS_CMP5ITF ((uint32_t)0x00000010U) /* Bit[4] Compare 5 flag */ +#define SHRTIM_TXINTSTS_CMP4ITF ((uint32_t)0x00000008U) /* Bit[3] Compare 4 interrupt flag */ +#define SHRTIM_TXINTSTS_CMP3ITF ((uint32_t)0x00000004U) /* Bit[2] Compare 3 interrupt flag */ +#define SHRTIM_TXINTSTS_CMP2ITF ((uint32_t)0x00000002U) /* Bit[1] Compare 2 interrupt flag */ +#define SHRTIM_TXINTSTS_CMP1ITF ((uint32_t)0x00000001U) /* Bit[0] Compare 1 interrupt flag */ + +/** Bit definition for SHRTIM_TXINTCLR register **/ +#define SHRTIM_TXINTCLR_DPIC ((uint32_t)0x00004000U) /* Bit[14] Delayed protection interrupt flag clear */ +#define SHRTIM_TXINTCLR_RSTROIC ((uint32_t)0x00002000U) /* Bit[13] Reset and/or roll-over interrupt flag clear */ +#define SHRTIM_TXINTCLR_RST2IC ((uint32_t)0x00001000U) /* Bit[12] Output channel 2 reset interrupt flag clear */ +#define SHRTIM_TXINTCLR_SET2IC ((uint32_t)0x00000800U) /* Bit[11] Output channel 2 set interrupt flag clear */ +#define SHRTIM_TXINTCLR_RST1IC ((uint32_t)0x00000400U) /* Bit[10] Output channel 2 reset interrupt flag clear */ +#define SHRTIM_TXINTCLR_SET1IC ((uint32_t)0x00000200U) /* Bit[9] Output channel 2 set interrupt flag clear */ +#define SHRTIM_TXINTCLR_CPT2IC ((uint32_t)0x00000100U) /* Bit[8] Capture 2 interrupt flag clear */ +#define SHRTIM_TXINTCLR_CPT1IC ((uint32_t)0x00000080U) /* Bit[7] Capture 1 interrupt flag clear */ +#define SHRTIM_TXINTCLR_UPDIC ((uint32_t)0x00000040U) /* Bit[6] Update interrupt flag clear */ +#define SHRTIM_TXINTCLR_REPTIC ((uint32_t)0x00000020U) /* Bit[5] Repetition interrupt flag clear */ +#define SHRTIM_TXINTCLR_CMP5IC ((uint32_t)0x00000010U) /* Bit[4] Compare 5 flag clear */ +#define SHRTIM_TXINTCLR_CMP4IC ((uint32_t)0x00000008U) /* Bit[3] Compare 4 interrupt flag clear */ +#define SHRTIM_TXINTCLR_CMP3IC ((uint32_t)0x00000004U) /* Bit[2] Compare 3 interrupt flag clear */ +#define SHRTIM_TXINTCLR_CMP2IC ((uint32_t)0x00000002U) /* Bit[1] Compare 2 interrupt flag clear */ +#define SHRTIM_TXINTCLR_CMP1IC ((uint32_t)0x00000001U) /* Bit[0] Compare 1 interrupt flag clear */ + +/** Bit definition for SHRTIM_TXIDEN register **/ +#define SHRTIM_TXIDEN_DPDEN ((uint32_t)0x40000000U) /* Bit[30] Reserved, must be kept at reset value */ +#define SHRTIM_TXIDEN_RSTRODEN ((uint32_t)0x20000000U) /* Bit[29] Reset/roll-over DMA request enable */ +#define SHRTIM_TXIDEN_RST2DEN ((uint32_t)0x10000000U) /* Bit[28] Output 2 reset DMA request enable */ +#define SHRTIM_TXIDEN_SET2DEN ((uint32_t)0x08000000U) /* Bit[27] Output 2 set DMA request enable */ +#define SHRTIM_TXIDEN_RST1DEN ((uint32_t)0x04000000U) /* Bit[26] Output 1 reset DMA request enable */ +#define SHRTIM_TXIDEN_SET1DEN ((uint32_t)0x02000000U) /* Bit[25] Output 1 set DMA request enable */ +#define SHRTIM_TXIDEN_CPT2DEN ((uint32_t)0x01000000U) /* Bit[24] Capture 2 DMA request enable */ +#define SHRTIM_TXIDEN_CPT1DEN ((uint32_t)0x00800000U) /* Bit[23] Capture 1 DMA request enable */ +#define SHRTIM_TXIDEN_UPDDEN ((uint32_t)0x00400000U) /* Bit[22] Update DMA request enable */ +#define SHRTIM_TXIDEN_REPTDEN ((uint32_t)0x00100000U) /* Bit[20] Repetition DMA request enable */ +#define SHRTIM_TXIDEN_CMP4DEN ((uint32_t)0x00080000U) /* Bit[19] Compare 4 DMA request enable */ +#define SHRTIM_TXIDEN_CMP3DEN ((uint32_t)0x00040000U) /* Bit[18] Compare 3 DMA request enable */ +#define SHRTIM_TXIDEN_CMP2DEN ((uint32_t)0x00020000U) /* Bit[17] Compare 2 DMA request enable */ +#define SHRTIM_TXIDEN_CMP1DEN ((uint32_t)0x00010000U) /* Bit[16] Compare 1 DMA request enable */ +#define SHRTIM_TXIDEN_DPIEN ((uint32_t)0x00004000U) /* Bit[14] Delayed protection interrupt enable */ +#define SHRTIM_TXIDEN_RSTROIEN ((uint32_t)0x00002000U) /* Bit[13] Reset/roll-over interrupt enable */ +#define SHRTIM_TXIDEN_RST2IEN ((uint32_t)0x00001000U) /* Bit[12] Output 2 reset interrupt enable */ +#define SHRTIM_TXIDEN_SET2IEN ((uint32_t)0x00000800U) /* Bit[11] Output 2 set interrupt enable */ +#define SHRTIM_TXIDEN_RST1IEN ((uint32_t)0x00000400U) /* Bit[10] Output 1 reset interrupt enable */ +#define SHRTIM_TXIDEN_SET1IEN ((uint32_t)0x00000200U) /* Bit[9] Output 1 set interrupt enable */ +#define SHRTIM_TXIDEN_CPT2IEN ((uint32_t)0x00000100U) /* Bit[8] Capture interrupt enable */ +#define SHRTIM_TXIDEN_CPT1IEN ((uint32_t)0x00000080U) /* Bit[7] Capture interrupt enable */ +#define SHRTIM_TXIDEN_UPDIEN ((uint32_t)0x00000040U) /* Bit[6] Update interrupt enable */ +#define SHRTIM_TXIDEN_REPTIEN ((uint32_t)0x00000020U) /* Bit[5] Repetition interrupt enable */ +#define SHRTIM_TXIDEN_CMP4IEN ((uint32_t)0x00000008U) /* Bit[3] Compare 4 interrupt enable */ +#define SHRTIM_TXIDEN_CMP3IEN ((uint32_t)0x00000004U) /* Bit[2] Compare 3 interrupt enable */ +#define SHRTIM_TXIDEN_CMP2IEN ((uint32_t)0x00000002U) /* Bit[1] Compare 2 interrupt enable */ +#define SHRTIM_TXIDEN_CMP1IEN ((uint32_t)0x00000001U) /* Bit[0] Compare 1 interrupt enable */ + +/** Bit definition for SHRTIM_TXCNT register **/ +#define SHRTIM_TXCNT_COUNT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x counter value */ +#define SHRTIM_TXCNT_COUNT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCNT_COUNT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCNT_COUNT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCNT_COUNT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCNT_COUNT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCNT_COUNT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCNT_COUNT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCNT_COUNT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCNT_COUNT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCNT_COUNT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCNT_COUNT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCNT_COUNT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCNT_COUNT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCNT_COUNT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCNT_COUNT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCNT_COUNT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXPRD register **/ +#define SHRTIM_TXPRD_PRD ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x period value */ +#define SHRTIM_TXPRD_PRD_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXPRD_PRD_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXPRD_PRD_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXPRD_PRD_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXPRD_PRD_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXPRD_PRD_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXPRD_PRD_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXPRD_PRD_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXPRD_PRD_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXPRD_PRD_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXPRD_PRD_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXPRD_PRD_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXPRD_PRD_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXPRD_PRD_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXPRD_PRD_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXPRD_PRD_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXREPT register **/ +#define SHRTIM_TXREPT_REPT ((uint32_t)0x000000FFU) /* Bit[7:0] Timer x repetition period value */ +#define SHRTIM_TXREPT_REPT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXREPT_REPT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXREPT_REPT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXREPT_REPT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXREPT_REPT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXREPT_REPT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXREPT_REPT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXREPT_REPT_7 ((uint32_t)0x00000080U) /* Bit7 */ + +/** Bit definition for SHRTIM_TXCMP1DAT register **/ +#define SHRTIM_TXCMP1DAT_CMP1DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x compare 1 value */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCMP1DAT_CMP1DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXRCMP1DAT register **/ +#define SHRTIM_TXRCMP1DAT_REPT ((uint32_t)0x00FF0000U) /* Bit[23:16] Timer x repetititon counter alias */ +#define SHRTIM_TXRCMP1DAT_REPT_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_TXRCMP1DAT_REPT_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_TXRCMP1DAT_REPT_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_TXRCMP1DAT_REPT_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_TXRCMP1DAT_REPT_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_TXRCMP1DAT_REPT_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_TXRCMP1DAT_REPT_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_TXRCMP1DAT_REPT_7 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x compare 1 data */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXRCMP1DAT_CMP1DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TxCMP2DAT register **/ +#define SHRTIM_TXCMP2DAT_CMP2DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x compare 2 data */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCMP2DAT_CMP2DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXCMP3DAT register **/ +#define SHRTIM_TXCMP3DAT_CMP3DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x compare 3 data */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCMP3DAT_CMP3DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXCMP4DAT register **/ +#define SHRTIM_TXCMP4DAT_CMP4DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x compare 4 data */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCMP4DAT_CMP4DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXCPT1 register **/ +#define SHRTIM_TXCPT1_UDSTS1 ((uint32_t)0x00010000U) /* Bit[16] Status for timer x counting direction while capture 1 happened */ +#define SHRTIM_TXCPT1_CPT1 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x capture 1 data */ +#define SHRTIM_TXCPT1_CPT1_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCPT1_CPT1_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCPT1_CPT1_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCPT1_CPT1_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCPT1_CPT1_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCPT1_CPT1_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCPT1_CPT1_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCPT1_CPT1_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCPT1_CPT1_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCPT1_CPT1_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCPT1_CPT1_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCPT1_CPT1_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCPT1_CPT1_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCPT1_CPT1_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCPT1_CPT1_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCPT1_CPT1_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXCPT2 register **/ +#define SHRTIM_TXCPT2_UDSTS2 ((uint32_t)0x00010000U) /* Bit[16] Status for timer x counting direction while capture 2 happened */ +#define SHRTIM_TXCPT2_CPT2 ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer x capture 2 data */ +#define SHRTIM_TXCPT2_CPT2_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCPT2_CPT2_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCPT2_CPT2_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCPT2_CPT2_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCPT2_CPT2_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCPT2_CPT2_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCPT2_CPT2_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCPT2_CPT2_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCPT2_CPT2_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCPT2_CPT2_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCPT2_CPT2_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCPT2_CPT2_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCPT2_CPT2_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCPT2_CPT2_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCPT2_CPT2_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCPT2_CPT2_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_TXDT register **/ +#define SHRTIM_TXDT_DTFLCK ((uint32_t)0x80000000U) /* Bit[31] Deadtime falling lock */ +#define SHRTIM_TXDT_DTFSLCK ((uint32_t)0x40000000U) /* Bit[30] Deadtime falling sign lock */ +#define SHRTIM_TXDT_SDTF ((uint32_t)0x02000000U) /* Bit[25] Sign deadtime falling value */ +#define SHRTIM_TXDT_DTF ((uint32_t)0x01FF0000U) /* Bit[24:16] Deadtime falling value */ +#define SHRTIM_TXDT_DTF_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_TXDT_DTF_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_TXDT_DTF_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_TXDT_DTF_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_TXDT_DTF_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_TXDT_DTF_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_TXDT_DTF_6 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_TXDT_DTF_7 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_TXDT_DTF_8 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_TXDT_DTRLCK ((uint32_t)0x00008000U) /* Bit[15] Deadtime rising lock */ +#define SHRTIM_TXDT_DTRSLCK ((uint32_t)0x00004000U) /* Bit[14] Deadtime rising sign lock */ +#define SHRTIM_TXDT_DTPSC ((uint32_t)0x00001C00U) /* Bit[12:10] Deadtime prescaler */ +#define SHRTIM_TXDT_DTPSC_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXDT_DTPSC_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXDT_DTPSC_2 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXDT_SDTR ((uint32_t)0x00000200U) /* Bit[9] Sign deadtime rising value */ +#define SHRTIM_TXDT_DTR ((uint32_t)0x000001FFU) /* Bit[8:0] Deadtime rising value */ +#define SHRTIM_TXDT_DTR_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXDT_DTR_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXDT_DTR_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXDT_DTR_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXDT_DTR_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXDT_DTR_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXDT_DTR_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXDT_DTR_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXDT_DTR_8 ((uint32_t)0x00000100U) /* Bit8 */ + +/** Bit definition for SHRTIM_TXSET1 register **/ +#define SHRTIM_TXSET1_UPD ((uint32_t)0x80000000U) /* Bit[31] Registers update (transfer preload to active) */ +#define SHRTIM_TXSET1_EXEV10 ((uint32_t)0x40000000U) /* Bit[30] External event 10 */ +#define SHRTIM_TXSET1_EXEV9 ((uint32_t)0x20000000U) /* Bit[29] External event 9 */ +#define SHRTIM_TXSET1_EXEV8 ((uint32_t)0x10000000U) /* Bit[28] External event 8 */ +#define SHRTIM_TXSET1_EXEV7 ((uint32_t)0x08000000U) /* Bit[27] External event 7 */ +#define SHRTIM_TXSET1_EXEV6 ((uint32_t)0x04000000U) /* Bit[26] External event 6 */ +#define SHRTIM_TXSET1_EXEV5 ((uint32_t)0x02000000U) /* Bit[25] External event 5 */ +#define SHRTIM_TXSET1_EXEV4 ((uint32_t)0x01000000U) /* Bit[24] External event 4 */ +#define SHRTIM_TXSET1_EXEV3 ((uint32_t)0x00800000U) /* Bit[23] External event 3 */ +#define SHRTIM_TXSET1_EXEV2 ((uint32_t)0x00400000U) /* Bit[22] External event 2 */ +#define SHRTIM_TXSET1_EXEV1 ((uint32_t)0x00200000U) /* Bit[21] External event 1 */ +#define SHRTIM_TXSET1_TIMEV9 ((uint32_t)0x00100000U) /* Bit[20] Timer event 9 */ +#define SHRTIM_TXSET1_TIMEV8 ((uint32_t)0x00080000U) /* Bit[19] Timer event 8 */ +#define SHRTIM_TXSET1_TIMEV7 ((uint32_t)0x00040000U) /* Bit[18] Timer event 7 */ +#define SHRTIM_TXSET1_TIMEV6 ((uint32_t)0x00020000U) /* Bit[17] Timer event 6 */ +#define SHRTIM_TXSET1_TIMEV5 ((uint32_t)0x00010000U) /* Bit[16] Timer event 5 */ +#define SHRTIM_TXSET1_TIMEV4 ((uint32_t)0x00008000U) /* Bit[15] Timer event 4 */ +#define SHRTIM_TXSET1_TIMEV3 ((uint32_t)0x00004000U) /* Bit[14] Timer event 3 */ +#define SHRTIM_TXSET1_TIMEV2 ((uint32_t)0x00002000U) /* Bit[13] Timer event 2 */ +#define SHRTIM_TXSET1_TIMEV1 ((uint32_t)0x00001000U) /* Bit[12] Timer event 1 */ +#define SHRTIM_TXSET1_MCMP4 ((uint32_t)0x00000800U) /* Bit[11] Master compare 4 */ +#define SHRTIM_TXSET1_MCMP3 ((uint32_t)0x00000400U) /* Bit[10] Master compare 3 */ +#define SHRTIM_TXSET1_MCMP2 ((uint32_t)0x00000200U) /* Bit[9] Master compare 2 */ +#define SHRTIM_TXSET1_MCMP1 ((uint32_t)0x00000100U) /* Bit[8] Master compare 1 */ +#define SHRTIM_TXSET1_MPRD ((uint32_t)0x00000080U) /* Bit[7] Master period */ +#define SHRTIM_TXSET1_CMP4 ((uint32_t)0x00000040U) /* Bit[6] Timer x compare 4 */ +#define SHRTIM_TXSET1_CMP3 ((uint32_t)0x00000020U) /* Bit[5] Timer x compare 3 */ +#define SHRTIM_TXSET1_CMP2 ((uint32_t)0x00000010U) /* Bit[4] Timer x compare 2 */ +#define SHRTIM_TXSET1_CMP1 ((uint32_t)0x00000008U) /* Bit[3] Timer x compare 1 */ +#define SHRTIM_TXSET1_PRD ((uint32_t)0x00000004U) /* Bit[2] Timer x period */ +#define SHRTIM_TXSET1_RSYNC ((uint32_t)0x00000002U) /* Bit[1] Timer x resynchronization */ +#define SHRTIM_TXSET1_SWT ((uint32_t)0x00000001U) /* Bit[0] Software set trigger */ + +/** Bit definition for SHRTIM_TXRST1 register **/ +#define SHRTIM_TXRST1_UPD ((uint32_t)0x80000000U) /* Bit[31] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV10 ((uint32_t)0x40000000U) /* Bit[30] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV9 ((uint32_t)0x20000000U) /* Bit[29] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV8 ((uint32_t)0x10000000U) /* Bit[28] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV7 ((uint32_t)0x08000000U) /* Bit[27] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV6 ((uint32_t)0x04000000U) /* Bit[26] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV5 ((uint32_t)0x02000000U) /* Bit[25] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV4 ((uint32_t)0x01000000U) /* Bit[24] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV3 ((uint32_t)0x00800000U) /* Bit[23] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV2 ((uint32_t)0x00400000U) /* Bit[22] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_EXEV1 ((uint32_t)0x00200000U) /* Bit[21] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV9 ((uint32_t)0x00100000U) /* Bit[20] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV8 ((uint32_t)0x00080000U) /* Bit[19] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV7 ((uint32_t)0x00040000U) /* Bit[18] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV6 ((uint32_t)0x00020000U) /* Bit[17] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV5 ((uint32_t)0x00010000U) /* Bit[16] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV4 ((uint32_t)0x00008000U) /* Bit[15] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV3 ((uint32_t)0x00004000U) /* Bit[14] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV2 ((uint32_t)0x00002000U) /* Bit[13] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_TIMEV1 ((uint32_t)0x00001000U) /* Bit[12] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_MCMP4 ((uint32_t)0x00000800U) /* Bit[11] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_MCMP3 ((uint32_t)0x00000400U) /* Bit[10] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_MCMP2 ((uint32_t)0x00000200U) /* Bit[9] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_MCMP1 ((uint32_t)0x00000100U) /* Bit[8] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_MPRD ((uint32_t)0x00000080U) /* Bit[7] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_CMP4 ((uint32_t)0x00000040U) /* Bit[6] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_CMP3 ((uint32_t)0x00000020U) /* Bit[5] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_CMP2 ((uint32_t)0x00000010U) /* Bit[4] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_CMP1 ((uint32_t)0x00000008U) /* Bit[3] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_PRD ((uint32_t)0x00000004U) /* Bit[2] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_RSYNC ((uint32_t)0x00000002U) /* Bit[1] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXRST1_SWT ((uint32_t)0x00000001U) /* Bit[0] Refer to SHRTIM_TASET1 bits description. */ + +/** Bit definition for SHRTIM_TXSET2 register **/ +#define SHRTIM_TXSET2_UPD ((uint32_t)0x80000000U) /* Bit[31] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXSET2_EXEV10 ((uint32_t)0x40000000U) /* Bit[30] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXSET2_EXEV9 ((uint32_t)0x20000000U) /* Bit[29] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXSET2_EXEV8 ((uint32_t)0x10000000U) /* Bit[28] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXSET2_EXEV7 ((uint32_t)0x08000000U) /* Bit[27] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXSET2_EXEV6 ((uint32_t)0x04000000U) /* Bit[26] Refer to SHRTIM_TASET1 bits description. */ +#define SHRTIM_TXSET2_EXEV5 ((uint32_t)0x02000000U) /* Bit[25] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_EXEV4 ((uint32_t)0x01000000U) /* Bit[24] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_EXEV3 ((uint32_t)0x00800000U) /* Bit[23] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_EXEV2 ((uint32_t)0x00400000U) /* Bit[22] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_EXEV1 ((uint32_t)0x00200000U) /* Bit[21] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV9 ((uint32_t)0x00100000U) /* Bit[20] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV8 ((uint32_t)0x00080000U) /* Bit[19] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV7 ((uint32_t)0x00040000U) /* Bit[18] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV6 ((uint32_t)0x00020000U) /* Bit[17] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV5 ((uint32_t)0x00010000U) /* Bit[16] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV4 ((uint32_t)0x00008000U) /* Bit[15] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV3 ((uint32_t)0x00004000U) /* Bit[14] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV2 ((uint32_t)0x00002000U) /* Bit[13] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_TIMEV1 ((uint32_t)0x00001000U) /* Bit[12] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_MCMP4 ((uint32_t)0x00000800U) /* Bit[11] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_MCMP3 ((uint32_t)0x00000400U) /* Bit[10] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_MCMP2 ((uint32_t)0x00000200U) /* Bit[9] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_MCMP1 ((uint32_t)0x00000100U) /* Bit[8] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_MPRD ((uint32_t)0x00000080U) /* Bit[7] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_CMP4 ((uint32_t)0x00000040U) /* Bit[6] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_CMP3 ((uint32_t)0x00000020U) /* Bit[5] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_CMP2 ((uint32_t)0x00000010U) /* Bit[4] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_CMP1 ((uint32_t)0x00000008U) /* Bit[3] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_PRD ((uint32_t)0x00000004U) /* Bit[2] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_RSYNC ((uint32_t)0x00000002U) /* Bit[1] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXSET2_SWT ((uint32_t)0x00000001U) /* Bit[0] Refer to SHRTIM_TASET bits description. */ + +/** Bit definition for SHRTIM_TXRST2 register **/ +#define SHRTIM_TXRST2_UPD ((uint32_t)0x80000000U) /* Bit[31] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV10 ((uint32_t)0x40000000U) /* Bit[30] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV9 ((uint32_t)0x20000000U) /* Bit[29] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV8 ((uint32_t)0x10000000U) /* Bit[28] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV7 ((uint32_t)0x08000000U) /* Bit[27] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV6 ((uint32_t)0x04000000U) /* Bit[26] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV5 ((uint32_t)0x02000000U) /* Bit[25] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV4 ((uint32_t)0x01000000U) /* Bit[24] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV3 ((uint32_t)0x00800000U) /* Bit[23] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV2 ((uint32_t)0x00400000U) /* Bit[22] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_EXEV1 ((uint32_t)0x00200000U) /* Bit[21] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV9 ((uint32_t)0x00100000U) /* Bit[20] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV8 ((uint32_t)0x00080000U) /* Bit[19] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV7 ((uint32_t)0x00040000U) /* Bit[18] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV6 ((uint32_t)0x00020000U) /* Bit[17] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV5 ((uint32_t)0x00010000U) /* Bit[16] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV4 ((uint32_t)0x00008000U) /* Bit[15] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV3 ((uint32_t)0x00004000U) /* Bit[14] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV2 ((uint32_t)0x00002000U) /* Bit[13] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_TIMEV1 ((uint32_t)0x00001000U) /* Bit[12] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_MCMP4 ((uint32_t)0x00000800U) /* Bit[11] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_MCMP3 ((uint32_t)0x00000400U) /* Bit[10] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_MCMP2 ((uint32_t)0x00000200U) /* Bit[9] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_MCMP1 ((uint32_t)0x00000100U) /* Bit[8] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_MPRD ((uint32_t)0x00000080U) /* Bit[7] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_CMP4 ((uint32_t)0x00000040U) /* Bit[6] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_CMP3 ((uint32_t)0x00000020U) /* Bit[5] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_CMP2 ((uint32_t)0x00000010U) /* Bit[4] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_CMP1 ((uint32_t)0x00000008U) /* Bit[3] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_PRD ((uint32_t)0x00000004U) /* Bit[2] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_RSYNC ((uint32_t)0x00000002U) /* Bit[1] Refer to SHRTIM_TASET bits description. */ +#define SHRTIM_TXRST2_SWT ((uint32_t)0x00000001U) /* Bit[0] Refer to SHRTIM_TASET bits description. */ + +/** Bit definition for SHRTIM_TXEXEVFLT1 register **/ +#define SHRTIM_TXEXEVFLT1_EXEVWINSEL ((uint32_t)0x80000000U) /* Bit 31 External event window selection */ +#define SHRTIM_TXEXEVFLT1_EXEV5FLT ((uint32_t)0x1E000000U) /* Bit[28:25] External event 5 filter */ +#define SHRTIM_TXEXEVFLT1_EXEV5FLT_0 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_TXEXEVFLT1_EXEV5FLT_1 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_TXEXEVFLT1_EXEV5FLT_2 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_TXEXEVFLT1_EXEV5FLT_3 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_TXEXEVFLT1_EXEV5LATCH ((uint32_t)0x01000000U) /* Bit[24] External event 5 latch */ +#define SHRTIM_TXEXEVFLT1_EXEV4FLT ((uint32_t)0x00780000U) /* Bit[22:19] External event 4 filter */ +#define SHRTIM_TXEXEVFLT1_EXEV4FLT_0 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_TXEXEVFLT1_EXEV4FLT_1 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_TXEXEVFLT1_EXEV4FLT_2 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_TXEXEVFLT1_EXEV4FLT_3 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_TXEXEVFLT1_EXEV4LATCH ((uint32_t)0x00040000U) /* Bit[18] External event 4 latch */ +#define SHRTIM_TXEXEVFLT1_EXEV3FLT ((uint32_t)0x0001E000U) /* Bit[16:13] External event 3 filter */ +#define SHRTIM_TXEXEVFLT1_EXEV3FLT_0 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXEXEVFLT1_EXEV3FLT_1 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXEXEVFLT1_EXEV3FLT_2 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_TXEXEVFLT1_EXEV3FLT_3 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_TXEXEVFLT1_EXEV3LATCH ((uint32_t)0x00001000U) /* Bit[12] External event 3 latch */ +#define SHRTIM_TXEXEVFLT1_EXEV2FLT ((uint32_t)0x00000780U) /* Bit[10:7] External event 2 filter */ +#define SHRTIM_TXEXEVFLT1_EXEV2FLT_0 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXEXEVFLT1_EXEV2FLT_1 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXEXEVFLT1_EXEV2FLT_2 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXEXEVFLT1_EXEV2FLT_3 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXEXEVFLT1_EXEV2LATCH ((uint32_t)0x00000040U) /* Bit[6] External event 2 latch */ +#define SHRTIM_TXEXEVFLT1_EXEV1FLT ((uint32_t)0x0000001EU) /* Bit[4:1] External event 1 filter */ +#define SHRTIM_TXEXEVFLT1_EXEV1FLT_0 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXEXEVFLT1_EXEV1FLT_1 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXEXEVFLT1_EXEV1FLT_2 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXEXEVFLT1_EXEV1FLT_3 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXEXEVFLT1_EXEV1LATCH ((uint32_t)0x00000001U) /* Bit[0] External event 1 LATCH */ + +/** Bit definition for SHRTIM_TXEXEVFLT2 register **/ +#define SHRTIM_TXEXEVFLT2_EXEV10FLT ((uint32_t)0x1E000000U) /* Bit[28:25] External event 10 filter */ +#define SHRTIM_TXEXEVFLT2_EXEV10FLT_0 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_TXEXEVFLT2_EXEV10FLT_1 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_TXEXEVFLT2_EXEV10FLT_2 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_TXEXEVFLT2_EXEV10FLT_3 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_TXEXEVFLT2_EXEV10LATCH ((uint32_t)0x01000000U) /* Bit[24] External event 10 latch */ +#define SHRTIM_TXEXEVFLT2_EXE9VFLT ((uint32_t)0x00780000U) /* Bit[22:19] External event 9 filter */ +#define SHRTIM_TXEXEVFLT2_EXE9VFLT_0 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_TXEXEVFLT2_EXE9VFLT_1 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_TXEXEVFLT2_EXE9VFLT_2 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_TXEXEVFLT2_EXE9VFLT_3 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_TXEXEVFLT2_EXEV9LATCH ((uint32_t)0x00040000U) /* Bit[18] External event 9 latch */ +#define SHRTIM_TXEXEVFLT2_EXE8VFLT ((uint32_t)0x0001E000U) /* Bit[16:13] External event 8 filter */ +#define SHRTIM_TXEXEVFLT2_EXE8VFLT_0 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXEXEVFLT2_EXE8VFLT_1 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXEXEVFLT2_EXE8VFLT_2 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_TXEXEVFLT2_EXE8VFLT_3 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_TXEXEVFLT2_EXEV8LATCH ((uint32_t)0x00001000U) /* Bit[12] External event 8 latch */ +#define SHRTIM_TXEXEVFLT2_EXE7VFLT ((uint32_t)0x00000780U) /* Bit[10:7] External event 7 filter */ +#define SHRTIM_TXEXEVFLT2_EXE7VFLT_0 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXEXEVFLT2_EXE7VFLT_1 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXEXEVFLT2_EXE7VFLT_2 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXEXEVFLT2_EXE7VFLT_3 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXEXEVFLT2_EXEV7LATCH ((uint32_t)0x00000040U) /* Bit[6] External event 7 latch */ +#define SHRTIM_TXEXEVFLT2_EXE6VFLT ((uint32_t)0x0000001EU) /* Bit[4:1] External event 6 filter */ +#define SHRTIM_TXEXEVFLT2_EXE6VFLT_0 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXEXEVFLT2_EXE6VFLT_1 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXEXEVFLT2_EXE6VFLT_2 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXEXEVFLT2_EXE6VFLT_3 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXEXEVFLT2_EXEV6LATCH ((uint32_t)0x00000001U) /* Bit[0] External event 6 latch */ + +/** Bit definition for SHRTIM_TACNTRST register **/ +#define SHRTIM_TACNTRST_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TACNTRST_TECMP4 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 4 */ +#define SHRTIM_TACNTRST_TECMP2 ((uint32_t)0x20000000U) /* Bit[29] Timer E compare 2 */ +#define SHRTIM_TACNTRST_TECMP1 ((uint32_t)0x10000000U) /* Bit[28] Timer E compare 1 */ +#define SHRTIM_TACNTRST_TDCMP4 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 4 */ +#define SHRTIM_TACNTRST_TDCMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 2 */ +#define SHRTIM_TACNTRST_TDCMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer D compare 1 */ +#define SHRTIM_TACNTRST_TCCMP4 ((uint32_t)0x01000000U) /* Bit[24] Timer C compare 4 */ +#define SHRTIM_TACNTRST_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TACNTRST_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TACNTRST_TBCMP4 ((uint32_t)0x00200000U) /* Bit[21] Timer B compare 4 */ +#define SHRTIM_TACNTRST_TBCMP2 ((uint32_t)0x00100000U) /* Bit[20] Timer B compare 2 */ +#define SHRTIM_TACNTRST_TBCMP1 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 1 */ +#define SHRTIM_TACNTRST_EXEV10 ((uint32_t)0x00040000U) /* Bit[18] External event 10 */ +#define SHRTIM_TACNTRST_EXEV9 ((uint32_t)0x00020000U) /* Bit[17] External event 9 */ +#define SHRTIM_TACNTRST_EXEV8 ((uint32_t)0x00010000U) /* Bit[16] External event 8 */ +#define SHRTIM_TACNTRST_EXEV7 ((uint32_t)0x00008000U) /* Bit[15] External event 7 */ +#define SHRTIM_TACNTRST_EXEV6 ((uint32_t)0x00004000U) /* Bit[14] External event 6 */ +#define SHRTIM_TACNTRST_EXEV5 ((uint32_t)0x00002000U) /* Bit[13] External event 5 */ +#define SHRTIM_TACNTRST_EXEV4 ((uint32_t)0x00001000U) /* Bit[12] External event 4 */ +#define SHRTIM_TACNTRST_EXEV3 ((uint32_t)0x00000800U) /* Bit[11] External event 3 */ +#define SHRTIM_TACNTRST_EXEV2 ((uint32_t)0x00000400U) /* Bit[10] External event 2 */ +#define SHRTIM_TACNTRST_EXEV1 ((uint32_t)0x00000200U) /* Bit[9] External event 1 */ +#define SHRTIM_TACNTRST_MCMP4 ((uint32_t)0x00000100U) /* Bit[8] Master compare 4 */ +#define SHRTIM_TACNTRST_MCMP3 ((uint32_t)0x00000080U) /* Bit[7] Master compare 3 */ +#define SHRTIM_TACNTRST_MCMP2 ((uint32_t)0x00000040U) /* Bit[6] Master compare 2 */ +#define SHRTIM_TACNTRST_MCMP1 ((uint32_t)0x00000020U) /* Bit[5] Master compare 1 */ +#define SHRTIM_TACNTRST_MPRD ((uint32_t)0x00000010U) /* Bit[4] Master timer period */ +#define SHRTIM_TACNTRST_CMP4 ((uint32_t)0x00000008U) /* Bit[3] Timer A compare 4 reset */ +#define SHRTIM_TACNTRST_CMP2 ((uint32_t)0x00000004U) /* Bit[2] Timer A compare 2 reset */ +#define SHRTIM_TACNTRST_UPD ((uint32_t)0x00000002U) /* Bit[1] Timer A update reset */ +#define SHRTIM_TACNTRST_TFCMP1 ((uint32_t)0x00000001U) /* Bit[0] Timer F compare 1 */ + +/** Bit definition for SHRTIM_TBCNTRST register **/ +#define SHRTIM_TBCNTRST_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TBCNTRST_TECMP4 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 4 */ +#define SHRTIM_TBCNTRST_TECMP2 ((uint32_t)0x20000000U) /* Bit[29] Timer E compare 2 */ +#define SHRTIM_TBCNTRST_TECMP1 ((uint32_t)0x10000000U) /* Bit[28] Timer E compare 1 */ +#define SHRTIM_TBCNTRST_TDCMP4 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 4 */ +#define SHRTIM_TBCNTRST_TDCMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 2 */ +#define SHRTIM_TBCNTRST_TDCMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer D compare 1 */ +#define SHRTIM_TBCNTRST_TCCMP4 ((uint32_t)0x01000000U) /* Bit[24] Timer C compare 4 */ +#define SHRTIM_TBCNTRST_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TBCNTRST_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TBCNTRST_TACMP4 ((uint32_t)0x00200000U) /* Bit[21] Timer B compare 4 */ +#define SHRTIM_TBCNTRST_TACMP2 ((uint32_t)0x00100000U) /* Bit[20] Timer B compare 2 */ +#define SHRTIM_TBCNTRST_TACMP1 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 1 */ +#define SHRTIM_TBCNTRST_EXEV10 ((uint32_t)0x00040000U) /* Bit[18] External event 10 */ +#define SHRTIM_TBCNTRST_EXEV9 ((uint32_t)0x00020000U) /* Bit[17] External event 9 */ +#define SHRTIM_TBCNTRST_EXEV8 ((uint32_t)0x00010000U) /* Bit[16] External event 8 */ +#define SHRTIM_TBCNTRST_EXEV7 ((uint32_t)0x00008000U) /* Bit[15] External event 7 */ +#define SHRTIM_TBCNTRST_EXEV6 ((uint32_t)0x00004000U) /* Bit[14] External event 6 */ +#define SHRTIM_TBCNTRST_EXEV5 ((uint32_t)0x00002000U) /* Bit[13] External event 5 */ +#define SHRTIM_TBCNTRST_EXEV4 ((uint32_t)0x00001000U) /* Bit[12] External event 4 */ +#define SHRTIM_TBCNTRST_EXEV3 ((uint32_t)0x00000800U) /* Bit[11] External event 3 */ +#define SHRTIM_TBCNTRST_EXEV2 ((uint32_t)0x00000400U) /* Bit[10] External event 2 */ +#define SHRTIM_TBCNTRST_EXEV1 ((uint32_t)0x00000200U) /* Bit[9] External event 1 */ +#define SHRTIM_TBCNTRST_MCMP4 ((uint32_t)0x00000100U) /* Bit[8] Master compare 4 */ +#define SHRTIM_TBCNTRST_MCMP3 ((uint32_t)0x00000080U) /* Bit[7] Master compare 3 */ +#define SHRTIM_TBCNTRST_MCMP2 ((uint32_t)0x00000040U) /* Bit[6] Master compare 2 */ +#define SHRTIM_TBCNTRST_MCMP1 ((uint32_t)0x00000020U) /* Bit[5] Master compare 1 */ +#define SHRTIM_TBCNTRST_MPRD ((uint32_t)0x00000010U) /* Bit[4] Master timer period */ +#define SHRTIM_TBCNTRST_CMP4 ((uint32_t)0x00000008U) /* Bit[3] Timer B compare 4 reset */ +#define SHRTIM_TBCNTRST_CMP2 ((uint32_t)0x00000004U) /* Bit[2] Timer B compare 2 reset */ +#define SHRTIM_TBCNTRST_UPD ((uint32_t)0x00000002U) /* Bit[1] Timer B update reset */ +#define SHRTIM_TBCNTRST_TFCMP1 ((uint32_t)0x00000001U) /* Bit[0] Timer F compare 1 */ + +/** Bit definition for SHRTIM_TCCNTRST register **/ +#define SHRTIM_TCCNTRST_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TCCNTRST_TECMP4 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 4 */ +#define SHRTIM_TCCNTRST_TECMP2 ((uint32_t)0x20000000U) /* Bit[29] Timer E compare 2 */ +#define SHRTIM_TCCNTRST_TECMP1 ((uint32_t)0x10000000U) /* Bit[28] Timer E compare 1 */ +#define SHRTIM_TCCNTRST_TDCMP4 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 4 */ +#define SHRTIM_TCCNTRST_TDCMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 2 */ +#define SHRTIM_TCCNTRST_TDCMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer D compare 1 */ +#define SHRTIM_TCCNTRST_TBCMP4 ((uint32_t)0x01000000U) /* Bit[24] Timer C compare 4 */ +#define SHRTIM_TCCNTRST_TBCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TCCNTRST_TBCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TCCNTRST_TACMP4 ((uint32_t)0x00200000U) /* Bit[21] Timer B compare 4 */ +#define SHRTIM_TCCNTRST_TACMP2 ((uint32_t)0x00100000U) /* Bit[20] Timer B compare 2 */ +#define SHRTIM_TCCNTRST_TACMP1 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 1 */ +#define SHRTIM_TCCNTRST_EXEV10 ((uint32_t)0x00040000U) /* Bit[18] External event */ +#define SHRTIM_TCCNTRST_EXEV9 ((uint32_t)0x00020000U) /* Bit[17] External event */ +#define SHRTIM_TCCNTRST_EXEV8 ((uint32_t)0x00010000U) /* Bit[16] External event */ +#define SHRTIM_TCCNTRST_EXEV7 ((uint32_t)0x00008000U) /* Bit[15] External event */ +#define SHRTIM_TCCNTRST_EXEV6 ((uint32_t)0x00004000U) /* Bit[14] External event */ +#define SHRTIM_TCCNTRST_EXEV5 ((uint32_t)0x00002000U) /* Bit[13] External event */ +#define SHRTIM_TCCNTRST_EXEV4 ((uint32_t)0x00001000U) /* Bit[12] External event */ +#define SHRTIM_TCCNTRST_EXEV3 ((uint32_t)0x00000800U) /* Bit[11] External event */ +#define SHRTIM_TCCNTRST_EXEV2 ((uint32_t)0x00000400U) /* Bit[10] External event */ +#define SHRTIM_TCCNTRST_EXEV1 ((uint32_t)0x00000200U) /* Bit[9] External event */ +#define SHRTIM_TCCNTRST_MCMP4 ((uint32_t)0x00000100U) /* Bit[8] Master compare 4 */ +#define SHRTIM_TCCNTRST_MCMP3 ((uint32_t)0x00000080U) /* Bit[7] Master compare 3 */ +#define SHRTIM_TCCNTRST_MCMP2 ((uint32_t)0x00000040U) /* Bit[6] Master compare 2 */ +#define SHRTIM_TCCNTRST_MCMP1 ((uint32_t)0x00000020U) /* Bit[5] Master compare 1 */ +#define SHRTIM_TCCNTRST_MPRD ((uint32_t)0x00000010U) /* Bit[4] Master timer period */ +#define SHRTIM_TCCNTRST_CMP4 ((uint32_t)0x00000008U) /* Bit[3] Timer C compare 4 reset */ +#define SHRTIM_TCCNTRST_CMP2 ((uint32_t)0x00000004U) /* Bit[2] Timer C compare 2 reset */ +#define SHRTIM_TCCNTRST_UPD ((uint32_t)0x00000002U) /* Bit[1] Timer C update reset */ +#define SHRTIM_TCCNTRST_TFCMP1 ((uint32_t)0x00000001U) /* Bit[0] Timer F compare 1 */ + +/** Bit definition for SHRTIM_TDCNTRST register **/ +#define SHRTIM_TDCNTRST_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TDCNTRST_TECMP4 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 4 */ +#define SHRTIM_TDCNTRST_TECMP2 ((uint32_t)0x20000000U) /* Bit[29] Timer E compare 2 */ +#define SHRTIM_TDCNTRST_TECMP1 ((uint32_t)0x10000000U) /* Bit[28] Timer E compare 1 */ +#define SHRTIM_TDCNTRST_TCCMP4 ((uint32_t)0x08000000U) /* Bit[27] Timer C compare 4 */ +#define SHRTIM_TDCNTRST_TCCMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer C compare 2 */ +#define SHRTIM_TDCNTRST_TCCMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer C compare 1 */ +#define SHRTIM_TDCNTRST_TBCMP4 ((uint32_t)0x01000000U) /* Bit[24] Timer D compare 4 */ +#define SHRTIM_TDCNTRST_TBCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer D compare 2 */ +#define SHRTIM_TDCNTRST_TBCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer D compare 1 */ +#define SHRTIM_TDCNTRST_TACMP4 ((uint32_t)0x00200000U) /* Bit[21] Timer B compare 4 */ +#define SHRTIM_TDCNTRST_TACMP2 ((uint32_t)0x00100000U) /* Bit[20] Timer B compare 2 */ +#define SHRTIM_TDCNTRST_TACMP1 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 1 */ +#define SHRTIM_TDCNTRST_EXEV10 ((uint32_t)0x00040000U) /* Bit[18] External event */ +#define SHRTIM_TDCNTRST_EXEV9 ((uint32_t)0x00020000U) /* Bit[17] External event */ +#define SHRTIM_TDCNTRST_EXEV8 ((uint32_t)0x00010000U) /* Bit[16] External event */ +#define SHRTIM_TDCNTRST_EXEV7 ((uint32_t)0x00008000U) /* Bit[15] External event */ +#define SHRTIM_TDCNTRST_EXEV6 ((uint32_t)0x00004000U) /* Bit[14] External event */ +#define SHRTIM_TDCNTRST_EXEV5 ((uint32_t)0x00002000U) /* Bit[13] External event */ +#define SHRTIM_TDCNTRST_EXEV4 ((uint32_t)0x00001000U) /* Bit[12] External event */ +#define SHRTIM_TDCNTRST_EXEV3 ((uint32_t)0x00000800U) /* Bit[11] External event */ +#define SHRTIM_TDCNTRST_EXEV2 ((uint32_t)0x00000400U) /* Bit[10] External event */ +#define SHRTIM_TDCNTRST_EXEV1 ((uint32_t)0x00000200U) /* Bit[9] External event */ +#define SHRTIM_TDCNTRST_MCMP4 ((uint32_t)0x00000100U) /* Bit[8] Master compare 4 */ +#define SHRTIM_TDCNTRST_MCMP3 ((uint32_t)0x00000080U) /* Bit[7] Master compare 3 */ +#define SHRTIM_TDCNTRST_MCMP2 ((uint32_t)0x00000040U) /* Bit[6] Master compare 2 */ +#define SHRTIM_TDCNTRST_MCMP1 ((uint32_t)0x00000020U) /* Bit[5] Master compare 1 */ +#define SHRTIM_TDCNTRST_MPRD ((uint32_t)0x00000010U) /* Bit[4] Master timer period */ +#define SHRTIM_TDCNTRST_CMP4 ((uint32_t)0x00000008U) /* Bit[3] Timer D compare 4 reset */ +#define SHRTIM_TDCNTRST_CMP2 ((uint32_t)0x00000004U) /* Bit[2] Timer D compare 2 reset */ +#define SHRTIM_TDCNTRST_UPD ((uint32_t)0x00000002U) /* Bit[1] Timer D update reset */ +#define SHRTIM_TDCNTRST_TFCMP1 ((uint32_t)0x00000001U) /* Bit[0] Timer F compare 1 */ + +/** Bit definition for SHRTIM_TECNTRST register **/ +#define SHRTIM_TECNTRST_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TECNTRST_TDCMP4 ((uint32_t)0x40000000U) /* Bit[30] Timer D compare 4 */ +#define SHRTIM_TECNTRST_TDCMP2 ((uint32_t)0x20000000U) /* Bit[29] Timer D compare 2 */ +#define SHRTIM_TECNTRST_TDCMP1 ((uint32_t)0x10000000U) /* Bit[28] Timer D compare 1 */ +#define SHRTIM_TECNTRST_TCCMP4 ((uint32_t)0x08000000U) /* Bit[27] Timer C compare 4 */ +#define SHRTIM_TECNTRST_TCCMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer C compare 2 */ +#define SHRTIM_TECNTRST_TCCMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer C compare 1 */ +#define SHRTIM_TECNTRST_TBCMP4 ((uint32_t)0x01000000U) /* Bit[24] Timer E compare 4 */ +#define SHRTIM_TECNTRST_TBCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer E compare 2 */ +#define SHRTIM_TECNTRST_TBCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer E compare 1 */ +#define SHRTIM_TECNTRST_TACMP4 ((uint32_t)0x00200000U) /* Bit[21] Timer B compare 4 */ +#define SHRTIM_TECNTRST_TACMP2 ((uint32_t)0x00100000U) /* Bit[20] Timer B compare 2 */ +#define SHRTIM_TECNTRST_TACMP1 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 1 */ +#define SHRTIM_TECNTRST_EXEV10 ((uint32_t)0x00040000U) /* Bit[18] External event */ +#define SHRTIM_TECNTRST_EXEV9 ((uint32_t)0x00020000U) /* Bit[17] External event */ +#define SHRTIM_TECNTRST_EXEV8 ((uint32_t)0x00010000U) /* Bit[16] External event */ +#define SHRTIM_TECNTRST_EXEV7 ((uint32_t)0x00008000U) /* Bit[15] External event */ +#define SHRTIM_TECNTRST_EXEV6 ((uint32_t)0x00004000U) /* Bit[14] External event */ +#define SHRTIM_TECNTRST_EXEV5 ((uint32_t)0x00002000U) /* Bit[13] External event */ +#define SHRTIM_TECNTRST_EXEV4 ((uint32_t)0x00001000U) /* Bit[12] External event */ +#define SHRTIM_TECNTRST_EXEV3 ((uint32_t)0x00000800U) /* Bit[11] External event */ +#define SHRTIM_TECNTRST_EXEV2 ((uint32_t)0x00000400U) /* Bit[10] External event */ +#define SHRTIM_TECNTRST_EXEV1 ((uint32_t)0x00000200U) /* Bit[9] External event */ +#define SHRTIM_TECNTRST_MCMP4 ((uint32_t)0x00000100U) /* Bit[8] Master compare 4 */ +#define SHRTIM_TECNTRST_MCMP3 ((uint32_t)0x00000080U) /* Bit[7] Master compare 3 */ +#define SHRTIM_TECNTRST_MCMP2 ((uint32_t)0x00000040U) /* Bit[6] Master compare 2 */ +#define SHRTIM_TECNTRST_MCMP1 ((uint32_t)0x00000020U) /* Bit[5] Master compare 1 */ +#define SHRTIM_TECNTRST_MPRD ((uint32_t)0x00000010U) /* Bit[4] Master timer period */ +#define SHRTIM_TECNTRST_CMP4 ((uint32_t)0x00000008U) /* Bit[3] Timer E compare 4 reset */ +#define SHRTIM_TECNTRST_CMP2 ((uint32_t)0x00000004U) /* Bit[2] Timer E compare 2 reset */ +#define SHRTIM_TECNTRST_UPD ((uint32_t)0x00000002U) /* Bit[1] Timer E update reset */ +#define SHRTIM_TECNTRST_TFCMP1 ((uint32_t)0x00000001U) /* Bit[0] Timer F compare 1 */ + +/** Bit definition for SHRTIM_TFCNTRST register **/ +#define SHRTIM_TFCNTRST_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TFCNTRST_TDCMP4 ((uint32_t)0x40000000U) /* Bit[30] Timer D compare 4 */ +#define SHRTIM_TFCNTRST_TDCMP2 ((uint32_t)0x20000000U) /* Bit[29] Timer D compare 2 */ +#define SHRTIM_TFCNTRST_TDCMP1 ((uint32_t)0x10000000U) /* Bit[28] Timer D compare 1 */ +#define SHRTIM_TFCNTRST_TCCMP4 ((uint32_t)0x08000000U) /* Bit[27] Timer C compare 4 */ +#define SHRTIM_TFCNTRST_TCCMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer C compare 2 */ +#define SHRTIM_TFCNTRST_TCCMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer C compare 1 */ +#define SHRTIM_TFCNTRST_TBCMP4 ((uint32_t)0x01000000U) /* Bit[24] Timer F compare 4 */ +#define SHRTIM_TFCNTRST_TBCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer F compare 2 */ +#define SHRTIM_TFCNTRST_TBCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer F compare 1 */ +#define SHRTIM_TFCNTRST_TACMP4 ((uint32_t)0x00200000U) /* Bit[21] Timer B compare 4 */ +#define SHRTIM_TFCNTRST_TACMP2 ((uint32_t)0x00100000U) /* Bit[20] Timer B compare 2 */ +#define SHRTIM_TFCNTRST_TACMP1 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 1 */ +#define SHRTIM_TFCNTRST_EXEV10 ((uint32_t)0x00040000U) /* Bit[18] External event */ +#define SHRTIM_TFCNTRST_EXEV9 ((uint32_t)0x00020000U) /* Bit[17] External event */ +#define SHRTIM_TFCNTRST_EXEV8 ((uint32_t)0x00010000U) /* Bit[16] External event */ +#define SHRTIM_TFCNTRST_EXEV7 ((uint32_t)0x00008000U) /* Bit[15] External event */ +#define SHRTIM_TFCNTRST_EXEV6 ((uint32_t)0x00004000U) /* Bit[14] External event */ +#define SHRTIM_TFCNTRST_EXEV5 ((uint32_t)0x00002000U) /* Bit[13] External event */ +#define SHRTIM_TFCNTRST_EXEV4 ((uint32_t)0x00001000U) /* Bit[12] External event */ +#define SHRTIM_TFCNTRST_EXEV3 ((uint32_t)0x00000800U) /* Bit[11] External event */ +#define SHRTIM_TFCNTRST_EXEV2 ((uint32_t)0x00000400U) /* Bit[10] External event */ +#define SHRTIM_TFCNTRST_EXEV1 ((uint32_t)0x00000200U) /* Bit[9] External event */ +#define SHRTIM_TFCNTRST_MCMP4 ((uint32_t)0x00000100U) /* Bit[8] Master compare 4 */ +#define SHRTIM_TFCNTRST_MCMP3 ((uint32_t)0x00000080U) /* Bit[7] Master compare 3 */ +#define SHRTIM_TFCNTRST_MCMP2 ((uint32_t)0x00000040U) /* Bit[6] Master compare 2 */ +#define SHRTIM_TFCNTRST_MCMP1 ((uint32_t)0x00000020U) /* Bit[5] Master compare 1 */ +#define SHRTIM_TFCNTRST_MPRD ((uint32_t)0x00000010U) /* Bit[4] Master timer period */ +#define SHRTIM_TFCNTRST_CMP4 ((uint32_t)0x00000008U) /* Bit[3] Timer F compare 4 reset */ +#define SHRTIM_TFCNTRST_CMP2 ((uint32_t)0x00000004U) /* Bit[2] Timer F compare 2 reset */ +#define SHRTIM_TFCNTRST_UPD ((uint32_t)0x00000002U) /* Bit[1] Timer F update reset */ +#define SHRTIM_TFCNTRST_TECMP1 ((uint32_t)0x00000001U) /* Bit[0] Timer E compare 1 */ + +/** Bit definition for SHRTIM_TXCHOP register **/ +#define SHRTIM_TXCHOP_STARTPW ((uint32_t)0x00000780U) /* Bit[10:7] Timer x start pulse width */ +#define SHRTIM_TXCHOP_STARTPW_0 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCHOP_STARTPW_1 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCHOP_STARTPW_2 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCHOP_STARTPW_3 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCHOP_CARDCY ((uint32_t)0x00000070U) /* Bit[6:4] Timer x chopper duty cycle value */ +#define SHRTIM_TXCHOP_CARDCY_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCHOP_CARDCY_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCHOP_CARDCY_2 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCHOP_CARFRQ ((uint32_t)0x0000000FU) /* Bit[3:0] Timer x carrier frequency value */ +#define SHRTIM_TXCHOP_CARFRQ_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCHOP_CARFRQ_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCHOP_CARFRQ_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCHOP_CARFRQ_3 ((uint32_t)0x00000008U) /* Bit3 */ + +/** Bit definition for SHRTIM_TACPT1CTRL register **/ +#define SHRTIM_TACPT1CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TACPT1CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TACPT1CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TACPT1CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TACPT1CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TACPT1CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TACPT1CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TACPT1CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TACPT1CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TACPT1CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TACPT1CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TACPT1CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TACPT1CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TACPT1CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TACPT1CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TACPT1CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TACPT1CTRL_TFCMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer F compare 2 */ +#define SHRTIM_TACPT1CTRL_TFCMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer F compare 1 */ +#define SHRTIM_TACPT1CTRL_TF1RST ((uint32_t)0x00002000U) /* Bit[13] Timer F output 1 reset */ +#define SHRTIM_TACPT1CTRL_TF1SET ((uint32_t)0x00001000U) /* Bit[12] Timer F output 1 reset */ +#define SHRTIM_TACPT1CTRL_EXEV10 ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TACPT1CTRL_EXEV9 ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TACPT1CTRL_EXEV8 ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TACPT1CTRL_EXEV7 ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TACPT1CTRL_EXEV6 ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TACPT1CTRL_EXEV5 ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TACPT1CTRL_EXEV4 ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TACPT1CTRL_EXEV3 ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TACPT1CTRL_EXEV2 ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TACPT1CTRL_EXEV1 ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TACPT1CTRL_UPD ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TACPT1CTRL_SW ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TACPT2CTRL register **/ +#define SHRTIM_TACPT2CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TACPT2CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TACPT2CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TACPT2CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TACPT2CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TACPT2CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TACPT2CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TACPT2CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TACPT2CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TACPT2CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TACPT2CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TACPT2CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TACPT2CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TACPT2CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TACPT2CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TACPT2CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TACPT2CTRL_TFCMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer F compare 2 */ +#define SHRTIM_TACPT2CTRL_TFCMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer F compare 1 */ +#define SHRTIM_TACPT2CTRL_TF1RST ((uint32_t)0x00002000U) /* Bit[13] Timer F output 1 reset */ +#define SHRTIM_TACPT2CTRL_TF1SET ((uint32_t)0x00001000U) /* Bit[12] Timer F output 1 reset */ +#define SHRTIM_TACPT2CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TACPT2CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TACPT2CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TACPT2CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TACPT2CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TACPT2CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TACPT2CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TACPT2CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TACPT2CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TACPT2CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TACPT2CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TACPT2CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TBCPT1CTRL register **/ +#define SHRTIM_TBCPT1CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TBCPT1CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TBCPT1CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TBCPT1CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TBCPT1CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TBCPT1CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TBCPT1CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TFCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer F compare 2 */ +#define SHRTIM_TBCPT1CTRL_TFCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer F compare 1 */ +#define SHRTIM_TBCPT1CTRL_TF1RST ((uint32_t)0x00020000U) /* Bit[17] Timer F output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TF1SET ((uint32_t)0x00010000U) /* Bit[16] Timer F output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TBCPT1CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TBCPT1CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TBCPT1CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TBCPT1CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TBCPT1CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TBCPT1CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TBCPT1CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TBCPT2CTRL register **/ +#define SHRTIM_TBCPT2CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TBCPT2CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TBCPT2CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TBCPT2CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TBCPT2CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TBCPT2CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TBCPT2CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TFCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer F compare 2 */ +#define SHRTIM_TBCPT2CTRL_TFCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer F compare 1 */ +#define SHRTIM_TBCPT2CTRL_TF1RST ((uint32_t)0x00020000U) /* Bit[17] Timer F output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TF1SET ((uint32_t)0x00010000U) /* Bit[16] Timer F output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TBCPT2CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TBCPT2CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TBCPT2CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TBCPT2CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TBCPT2CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TBCPT2CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TBCPT2CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TCCPT1CTRL register **/ +#define SHRTIM_TCCPT1CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TCCPT1CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TCCPT1CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TCCPT1CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TCCPT1CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TFCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer F compare 2 */ +#define SHRTIM_TCCPT1CTRL_TFCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer F compare 1 */ +#define SHRTIM_TCCPT1CTRL_TF1RST ((uint32_t)0x00200000U) /* Bit[21] Timer F output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TF1SET ((uint32_t)0x00100000U) /* Bit[20] Timer F output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TCCPT1CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TCCPT1CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TCCPT1CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TCCPT1CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TCCPT1CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TCCPT1CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TCCPT1CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TCCPT1CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TCCPT1CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TCCPT2CTRL register **/ +#define SHRTIM_TCCPT2CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TCCPT2CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TCCPT2CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TCCPT2CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TCCPT2CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TFCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer F compare 2 */ +#define SHRTIM_TCCPT2CTRL_TFCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer F compare 1 */ +#define SHRTIM_TCCPT2CTRL_TF1RST ((uint32_t)0x00200000U) /* Bit[21] Timer F output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TF1SET ((uint32_t)0x00100000U) /* Bit[20] Timer F output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TCCPT2CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TCCPT2CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TCCPT2CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TCCPT2CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TCCPT2CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TCCPT2CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TCCPT2CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TCCPT2CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TCCPT2CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TDCPT1CTRL register **/ +#define SHRTIM_TDCPT1CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TDCPT1CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TDCPT1CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TFCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer F compare 2 */ +#define SHRTIM_TDCPT1CTRL_TFCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer F compare 1 */ +#define SHRTIM_TDCPT1CTRL_TF1RST ((uint32_t)0x02000000U) /* Bit[25] Timer F output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TF1SET ((uint32_t)0x01000000U) /* Bit[24] Timer F output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TDCPT1CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TDCPT1CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TDCPT1CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TDCPT1CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TDCPT1CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TDCPT1CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TDCPT1CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TDCPT1CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TDCPT1CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TDCPT1CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TDCPT1CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TDCPT2CTRL register **/ +#define SHRTIM_TDCPT2CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TDCPT2CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TDCPT2CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TFCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer F compare 2 */ +#define SHRTIM_TDCPT2CTRL_TFCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer F compare 1 */ +#define SHRTIM_TDCPT2CTRL_TF1RST ((uint32_t)0x02000000U) /* Bit[25] Timer F output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TF1SET ((uint32_t)0x01000000U) /* Bit[24] Timer F output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TDCPT2CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TDCPT2CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TDCPT2CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TDCPT2CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TDCPT2CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TDCPT2CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TDCPT2CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TDCPT2CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TDCPT2CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TDCPT2CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TDCPT2CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TECPT1CTRL register **/ +#define SHRTIM_TECPT1CTRL_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TECPT1CTRL_TFCMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer F compare 1 */ +#define SHRTIM_TECPT1CTRL_TF1RST ((uint32_t)0x20000000U) /* Bit[29] Timer F output 1 reset */ +#define SHRTIM_TECPT1CTRL_TF1SET ((uint32_t)0x10000000U) /* Bit[28] Timer F output 1 reset */ +#define SHRTIM_TECPT1CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TECPT1CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TECPT1CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TECPT1CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TECPT1CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TECPT1CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TECPT1CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TECPT1CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TECPT1CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TECPT1CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TECPT1CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TECPT1CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TECPT1CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TECPT1CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TECPT1CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TECPT1CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TECPT1CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TECPT1CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TECPT1CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TECPT1CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TECPT1CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TECPT1CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TECPT1CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TECPT1CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TECPT1CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TECPT1CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TECPT1CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TECPT1CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TECPT2CTRL register **/ +#define SHRTIM_TECPT2CTRL_TFCMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer F compare 2 */ +#define SHRTIM_TECPT2CTRL_TFCMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer F compare 1 */ +#define SHRTIM_TECPT2CTRL_TF1RST ((uint32_t)0x20000000U) /* Bit[29] Timer F output 1 reset */ +#define SHRTIM_TECPT2CTRL_TF1SET ((uint32_t)0x10000000U) /* Bit[28] Timer F output 1 reset */ +#define SHRTIM_TECPT2CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TECPT2CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TECPT2CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TECPT2CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TECPT2CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TECPT2CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TECPT2CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TECPT2CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TECPT2CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TECPT2CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TECPT2CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TECPT2CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TECPT2CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TECPT2CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TECPT2CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TECPT2CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TECPT2CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TECPT2CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TECPT2CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TECPT2CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TECPT2CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TECPT2CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TECPT2CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TECPT2CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TECPT2CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TECPT2CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TECPT2CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TECPT2CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TFCPT1CTRL register **/ +#define SHRTIM_TFCPT1CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TFCPT1CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TFCPT1CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TFCPT1CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TFCPT1CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TFCPT1CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TFCPT1CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TFCPT1CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TFCPT1CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TFCPT1CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TFCPT1CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TFCPT1CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TFCPT1CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TFCPT1CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TFCPT1CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TFCPT1CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TFCPT2CTRL register **/ +#define SHRTIM_TFCPT2CTRL_TECMP2 ((uint32_t)0x80000000U) /* Bit[31] Timer E compare 2 */ +#define SHRTIM_TFCPT2CTRL_TECMP1 ((uint32_t)0x40000000U) /* Bit[30] Timer E compare 1 */ +#define SHRTIM_TFCPT2CTRL_TE1RST ((uint32_t)0x20000000U) /* Bit[29] Timer E output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TE1SET ((uint32_t)0x10000000U) /* Bit[28] Timer E output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TDCMP2 ((uint32_t)0x08000000U) /* Bit[27] Timer D compare 2 */ +#define SHRTIM_TFCPT2CTRL_TDCMP1 ((uint32_t)0x04000000U) /* Bit[26] Timer D compare 1 */ +#define SHRTIM_TFCPT2CTRL_TD1RST ((uint32_t)0x02000000U) /* Bit[25] Timer D output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TD1SET ((uint32_t)0x01000000U) /* Bit[24] Timer D output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TCCMP2 ((uint32_t)0x00800000U) /* Bit[23] Timer C compare 2 */ +#define SHRTIM_TFCPT2CTRL_TCCMP1 ((uint32_t)0x00400000U) /* Bit[22] Timer C compare 1 */ +#define SHRTIM_TFCPT2CTRL_TC1RST ((uint32_t)0x00200000U) /* Bit[21] Timer C output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TC1SET ((uint32_t)0x00100000U) /* Bit[20] Timer C output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TBCMP2 ((uint32_t)0x00080000U) /* Bit[19] Timer B compare 2 */ +#define SHRTIM_TFCPT2CTRL_TBCMP1 ((uint32_t)0x00040000U) /* Bit[18] Timer B compare 1 */ +#define SHRTIM_TFCPT2CTRL_TB1RST ((uint32_t)0x00020000U) /* Bit[17] Timer B output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TB1SET ((uint32_t)0x00010000U) /* Bit[16] Timer B output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TACMP2 ((uint32_t)0x00008000U) /* Bit[15] Timer A compare 2 */ +#define SHRTIM_TFCPT2CTRL_TACMP1 ((uint32_t)0x00004000U) /* Bit[14] Timer A compare 1 */ +#define SHRTIM_TFCPT2CTRL_TA1RST ((uint32_t)0x00002000U) /* Bit[13] Timer A output 1 reset */ +#define SHRTIM_TFCPT2CTRL_TA1SET ((uint32_t)0x00001000U) /* Bit[12] Timer A output 1 reset */ +#define SHRTIM_TFCPT2CTRL_EXEV10CPT ((uint32_t)0x00000800U) /* Bit[11] External event 10 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV9CPT ((uint32_t)0x00000400U) /* Bit[10] External event 9 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV8CPT ((uint32_t)0x00000200U) /* Bit[9] External event 8 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV7CPT ((uint32_t)0x00000100U) /* Bit[8] External event 7 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV6CPT ((uint32_t)0x00000080U) /* Bit[7] External event 6 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV5CPT ((uint32_t)0x00000040U) /* Bit[6] External event 5 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV4CPT ((uint32_t)0x00000020U) /* Bit[5] External event 4 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV3CPT ((uint32_t)0x00000010U) /* Bit[4] External event 3 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV2CPT ((uint32_t)0x00000008U) /* Bit[3] External event 2 capture */ +#define SHRTIM_TFCPT2CTRL_EXEV1CPT ((uint32_t)0x00000004U) /* Bit[2] External event 1 capture */ +#define SHRTIM_TFCPT2CTRL_UPDCPT ((uint32_t)0x00000002U) /* Bit[1] Update capture */ +#define SHRTIM_TFCPT2CTRL_SWCPT ((uint32_t)0x00000001U) /* Bit[0] Software capture */ + +/** Bit definition for SHRTIM_TXOUT register **/ +#define SHRTIM_TXOUT_DIDL2 ((uint32_t)0x00800000U) /* Bit[23] Output2 deadtime upon burst mode idle entry */ +#define SHRTIM_TXOUT_CHP2 ((uint32_t)0x00400000U) /* Bit[22] Output2 chopper enable */ +#define SHRTIM_TXOUT_FALT2 ((uint32_t)0x00300000U) /* Bit[21:20] Output timer x channel 2 fault state */ +#define SHRTIM_TXOUT_FALT2_0 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_TXOUT_FALT2_1 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_TXOUT_IDLES2 ((uint32_t)0x00080000U) /* Bit[19] Output 2 idle state */ +#define SHRTIM_TXOUT_IDLEM2 ((uint32_t)0x00040000U) /* Bit[18] Output channel 2 idle mode */ +#define SHRTIM_TXOUT_POL2 ((uint32_t)0x00020000U) /* Bit[17] Output1 polarity */ +#define SHRTIM_TXOUT_BIAR ((uint32_t)0x00004000U) /* Bit[14] Balanced idle automatic resume */ +#define SHRTIM_TXOUT_DP ((uint32_t)0x00001C00U) /* Bit[12:10] Delay protection source and output */ +#define SHRTIM_TXOUT_DP_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXOUT_DP_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXOUT_DP_2 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXOUT_DPEN ((uint32_t)0x00000200U) /* Bit[9] Delayed protection enable */ +#define SHRTIM_TXOUT_DTEN ((uint32_t)0x00000100U) /* Bit[8] Deadtime enable */ +#define SHRTIM_TXOUT_DIDL1 ((uint32_t)0x00000080U) /* Bit[7] Output 1 deadtime upon burst mode idle entry */ +#define SHRTIM_TXOUT_CHP1 ((uint32_t)0x00000040U) /* Bit[6] Output 1 chopper enable */ +#define SHRTIM_TXOUT_FALT1 ((uint32_t)0x00000030U) /* Bit[5:4] Output channel 1 fault state */ +#define SHRTIM_TXOUT_FALT1_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXOUT_FALT1_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXOUT_IDLES1 ((uint32_t)0x00000008U) /* Bit[3] Output channel 1 idle state */ +#define SHRTIM_TXOUT_IDLEM1 ((uint32_t)0x00000004U) /* Bit[2] Output channel 1 idle mode */ +#define SHRTIM_TXOUT_POL1 ((uint32_t)0x00000002U) /* Bit[1] Output 1 polarity */ + +/** Bit definition for SHRTIM_TXFALT register **/ +#define SHRTIM_TXFALT_FALTLCK ((uint32_t)0x80000000U) /* Bit[31] Fault sources lock */ +#define SHRTIM_TXFALT_FALT6EN ((uint32_t)0x00000020U) /* Bit[5] Fault 6 enable */ +#define SHRTIM_TXFALT_FALT5EN ((uint32_t)0x00000010U) /* Bit[4] Fault 5 enable */ +#define SHRTIM_TXFALT_FALT4EN ((uint32_t)0x00000008U) /* Bit[3] Fault 4 enable */ +#define SHRTIM_TXFALT_FALT3EN ((uint32_t)0x00000004U) /* Bit[2] Fault 3 enable */ +#define SHRTIM_TXFALT_FALT2EN ((uint32_t)0x00000002U) /* Bit[1] Fault 2 enable */ +#define SHRTIM_TXFALT_FALT1EN ((uint32_t)0x00000001U) /* Bit[0] Fault 1 enable */ + +/** Bit definition for SHRTIM_TXCTRL2 register **/ +#define SHRTIM_TXCTRL2_TRGHLF ((uint32_t)0x00100000U) /* Bit[20] Triggered-half mode */ +#define SHRTIM_TXCTRL2_GTCMP3 ((uint32_t)0x00020000U) /* Bit[17] Greater than compare 3 PWM mode */ +#define SHRTIM_TXCTRL2_GTCMP1 ((uint32_t)0x00010000U) /* Bit[16] Greater than compare 1 PWM mode */ +#define SHRTIM_TXCTRL2_FEROM ((uint32_t)0x0000C000U) /* Bit[15:14] Fault and event roll-over mode */ +#define SHRTIM_TXCTRL2_FEROM_0 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCTRL2_FEROM_1 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_TXCTRL2_BMROM ((uint32_t)0x00003000U) /* Bit[13:12] Burst mode roll-over mode */ +#define SHRTIM_TXCTRL2_BMROM_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCTRL2_BMROM_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCTRL2_ADCROM ((uint32_t)0x00000C00U) /* Bit[11:10] ADC roll-over mode */ +#define SHRTIM_TXCTRL2_ADCROM_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCTRL2_ADCROM_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCTRL2_OUTROM ((uint32_t)0x00000300U) /* Bit[9:8] Output roll-over mode */ +#define SHRTIM_TXCTRL2_OUTROM_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCTRL2_OUTROM_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCTRL2_ROM ((uint32_t)0x000000C0U) /* Bit[7:6] Roll-over mode */ +#define SHRTIM_TXCTRL2_ROM_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCTRL2_ROM_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCTRL2_UPDOWNM ((uint32_t)0x00000010U) /* Bit[4] Up-down mode */ +#define SHRTIM_TXCTRL2_DUDACRST ((uint32_t)0x00000004U) /* Bit[2] Dual DAC reset trigger */ +#define SHRTIM_TXCTRL2_DUDACSTEP ((uint32_t)0x00000002U) /* Bit[1] The trigger is generated on compare 2 event */ +#define SHRTIM_TXCTRL2_DUDACEN ((uint32_t)0x00000001U) /* Bit[0] Dual DAC trigger enable */ + +/** Bit definition for SHRTIM_TXEXEVFLT3 register **/ +#define SHRTIM_TXEXEVFLT3_EXEVCNT ((uint32_t)0x00003F00U) /* Bit[13:8] External event A counter */ +#define SHRTIM_TXEXEVFLT3_EXEVCNT_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXEXEVFLT3_EXEVCNT_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXEXEVFLT3_EXEVCNT_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXEXEVFLT3_EXEVCNT_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXEXEVFLT3_EXEVCNT_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXEXEVFLT3_EXEVCNT_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXEXEVFLT3_EXEVSEL ((uint32_t)0x000000F0U) /* Bit[7:4] External event A selection */ +#define SHRTIM_TXEXEVFLT3_EXEVSEL_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXEXEVFLT3_EXEVSEL_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXEXEVFLT3_EXEVSEL_2 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXEXEVFLT3_EXEVSEL_3 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXEXEVFLT3_EXEVRSTM ((uint32_t)0x00000004U) /* Bit[2] External event A reset mode */ +#define SHRTIM_TXEXEVFLT3_EXEVCNTRST ((uint32_t)0x00000002U) /* Bit[1] External event A counter reset */ +#define SHRTIM_TXEXEVFLT3_EXEVCNTEN ((uint32_t)0x00000001U) /* Bit[0] External event A counter enable */ + +/** Bit definition for SHRTIM_TXCMP5DAT register **/ +#define SHRTIM_TXCMP5DAT_CMP5DAT ((uint32_t)0x0000FFFFU) /* Bit[15:0] Timer A compare 5 value */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_TXCMP5DAT_CMP5DAT_15 ((uint32_t)0x00008000U) /* Bit15 */ + +/** Bit definition for SHRTIM_CTRL1 register **/ +#define SHRTIM_CTRL1_ADTG4UPDSRC ((uint32_t)0x0E000000U) /* Bit[27:25] ADC trigger update source 4 */ +#define SHRTIM_CTRL1_ADTG4UPDSRC_0 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_CTRL1_ADTG4UPDSRC_1 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_CTRL1_ADTG4UPDSRC_2 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_CTRL1_ADTG3UPDSRC ((uint32_t)0x01C00000U) /* Bit[24:22] ADC trigger update source 3 */ +#define SHRTIM_CTRL1_ADTG3UPDSRC_0 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_CTRL1_ADTG3UPDSRC_1 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_CTRL1_ADTG3UPDSRC_2 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_CTRL1_ADTG2UPDSRC ((uint32_t)0x00380000U) /* Bit[21:19] ADC trigger update source 2 */ +#define SHRTIM_CTRL1_ADTG2UPDSRC_0 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_CTRL1_ADTG2UPDSRC_1 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_CTRL1_ADTG2UPDSRC_2 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_CTRL1_ADTG1UPDSRC ((uint32_t)0x00070000U) /* Bit[18:16] ADC trigger update source 1 */ +#define SHRTIM_CTRL1_ADTG1UPDSRC_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_CTRL1_ADTG1UPDSRC_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_CTRL1_ADTG1UPDSRC_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_CTRL1_TFUPDDIS ((uint32_t)0x00000040U) /* Bit[6] Timer F update disable */ +#define SHRTIM_CTRL1_TEUPDDIS ((uint32_t)0x00000020U) /* Bit[5] Timer E update disable */ +#define SHRTIM_CTRL1_TDUPDDIS ((uint32_t)0x00000010U) /* Bit[4] Timer D update disable */ +#define SHRTIM_CTRL1_TCUPDDIS ((uint32_t)0x00000008U) /* Bit[3] Timer C update disable */ +#define SHRTIM_CTRL1_TBUPDDIS ((uint32_t)0x00000004U) /* Bit[2] Timer B update disable */ +#define SHRTIM_CTRL1_TAUPDDIS ((uint32_t)0x00000002U) /* Bit[1] Timer A update disable */ +#define SHRTIM_CTRL1_MUPDDIS ((uint32_t)0x00000001U) /* Bit[0] Master update disable */ + +/** Bit definition for SHRTIM_CTRL2 register **/ +#define SHRTIM_CTRL2_SWAPF ((uint32_t)0x00200000U) /* Bit[21] Timer F output swap */ +#define SHRTIM_CTRL2_SWAPE ((uint32_t)0x00100000U) /* Bit[20] Timer E output swap */ +#define SHRTIM_CTRL2_SWAPD ((uint32_t)0x00080000U) /* Bit[19] Timer D output swap */ +#define SHRTIM_CTRL2_SWAPC ((uint32_t)0x00040000U) /* Bit[18] Timer C output swap */ +#define SHRTIM_CTRL2_SWAPB ((uint32_t)0x00020000U) /* Bit[17] Timer B output swap */ +#define SHRTIM_CTRL2_SWAPA ((uint32_t)0x00010000U) /* Bit[16] Timer A output swap */ +#define SHRTIM_CTRL2_TFSWCNTRST ((uint32_t)0x00004000U) /* Bit[14] Software counter reset for timer F */ +#define SHRTIM_CTRL2_TESWCNTRST ((uint32_t)0x00002000U) /* Bit[13] Software counter reset for timer E */ +#define SHRTIM_CTRL2_TDSWCNTRST ((uint32_t)0x00001000U) /* Bit[12] Software counter reset for timer D */ +#define SHRTIM_CTRL2_TCSWCNTRST ((uint32_t)0x00000800U) /* Bit[11] Software counter reset for timer C */ +#define SHRTIM_CTRL2_TBSWCNTRST ((uint32_t)0x00000400U) /* Bit[10] Software counter reset for timer B */ +#define SHRTIM_CTRL2_TASWCNTRST ((uint32_t)0x00000200U) /* Bit[9] Software counter reset for timer A */ +#define SHRTIM_CTRL2_MSWCNTRST ((uint32_t)0x00000100U) /* Bit[8] Software counter reset for master timer */ +#define SHRTIM_CTRL2_TFSWUPD ((uint32_t)0x00000040U) /* Bit[6] Software update timer F */ +#define SHRTIM_CTRL2_TESWUPD ((uint32_t)0x00000020U) /* Bit[5] Software update timer E */ +#define SHRTIM_CTRL2_TDSWUPD ((uint32_t)0x00000010U) /* Bit[4] Software update timer D */ +#define SHRTIM_CTRL2_TCSWUPD ((uint32_t)0x00000008U) /* Bit[3] Software update timer C */ +#define SHRTIM_CTRL2_TBSWUPD ((uint32_t)0x00000004U) /* Bit[2] Software update timer B */ +#define SHRTIM_CTRL2_TASWUPD ((uint32_t)0x00000002U) /* Bit[1] Software update timer A */ +#define SHRTIM_CTRL2_MSWUPD ((uint32_t)0x00000001U) /* Bit[0] Software update master timer */ + +/** Bit definition for SHRTIM_INTSTS register **/ +#define SHRTIM_INTSTS_BMPRDITF ((uint32_t)0x00020000U) /* Bit[17] Burst mode period interrupt flag */ +#define SHRTIM_INTSTS_FALT6ITF ((uint32_t)0x00000040U) /* Bit[6] Fault 6 interrupt flag */ +#define SHRTIM_INTSTS_SYSFALTITF ((uint32_t)0x00000020U) /* Bit[5] System fault interrupt flag */ +#define SHRTIM_INTSTS_FALT5ITF ((uint32_t)0x00000010U) /* Bit[4] Fault 5 interrupt flag */ +#define SHRTIM_INTSTS_FALT4ITF ((uint32_t)0x00000008U) /* Bit[3] Fault 4 interrupt flag */ +#define SHRTIM_INTSTS_FALT3ITF ((uint32_t)0x00000004U) /* Bit[2] Fault 3 interrupt flag */ +#define SHRTIM_INTSTS_FALT2ITF ((uint32_t)0x00000002U) /* Bit[1] Fault 2 interrupt flag */ +#define SHRTIM_INTSTS_FALT1ITF ((uint32_t)0x00000001U) /* Bit[0] Fault 1 interrupt flag */ + +/** Bit definition for SHRTIM_INTCLR register **/ +#define SHRTIM_INTCLR_BMPRDIC ((uint32_t)0x00020000U) /* Bit[17] Burst mode period flag clear */ +#define SHRTIM_INTCLR_FALT6IC ((uint32_t)0x00000040U) /* Bit[6] Fault 6 interrupt flag clear */ +#define SHRTIM_INTCLR_SYSFALTIC ((uint32_t)0x00000020U) /* Bit[5] System fault interrupt flag clear */ +#define SHRTIM_INTCLR_FALT5IC ((uint32_t)0x00000010U) /* Bit[4] Fault 5 interrupt flag clear */ +#define SHRTIM_INTCLR_FALT4IC ((uint32_t)0x00000008U) /* Bit[3] Fault 4 interrupt flag clear */ +#define SHRTIM_INTCLR_FALT3IC ((uint32_t)0x00000004U) /* Bit[2] Fault 3 interrupt flag clear */ +#define SHRTIM_INTCLR_FALT2IC ((uint32_t)0x00000002U) /* Bit[1] Fault 2 interrupt flag clear */ +#define SHRTIM_INTCLR_FALT1IC ((uint32_t)0x00000001U) /* Bit[0] Fault 1 interrupt flag clear */ + +/** Bit definition for SHRTIM_INTEN register **/ +#define SHRTIM_INTEN_BMPRDIEN ((uint32_t)0x00020000U) /* Bit[17] Burst mode period interrupt enable */ +#define SHRTIM_INTEN_FALT6IEN ((uint32_t)0x00000040U) /* Bit[6] Fault 6 interrupt enable */ +#define SHRTIM_INTEN_SYSFALTIEN ((uint32_t)0x00000020U) /* Bit[5] System fault interrupt enable */ +#define SHRTIM_INTEN_FALT5IEN ((uint32_t)0x00000010U) /* Bit[4] Fault 5 interrupt enable */ +#define SHRTIM_INTEN_FALT4IEN ((uint32_t)0x00000008U) /* Bit[3] Fault 4 interrupt enable */ +#define SHRTIM_INTEN_FALT3IEN ((uint32_t)0x00000004U) /* Bit[2] Fault 3 interrupt enable */ +#define SHRTIM_INTEN_FALT2IEN ((uint32_t)0x00000002U) /* Bit[1] Fault 2 interrupt enable */ +#define SHRTIM_INTEN_FALT1IEN ((uint32_t)0x00000001U) /* Bit[0] Fault 1 interrupt enable */ + +/** Bit definition for SHRTIM_OEN register **/ +#define SHRTIM_OEN_TF2OEN ((uint32_t)0x00000800U) /* Bit[11] Timer F output 2 enable */ +#define SHRTIM_OEN_TF1OEN ((uint32_t)0x00000400U) /* Bit[10] Timer F output 1 enable */ +#define SHRTIM_OEN_TE2OEN ((uint32_t)0x00000200U) /* Bit[9] Timer E output 2 enable */ +#define SHRTIM_OEN_TE1OEN ((uint32_t)0x00000100U) /* Bit[8] Timer E output 1 enable */ +#define SHRTIM_OEN_TD2OEN ((uint32_t)0x00000080U) /* Bit[7] Timer D output 2 enable */ +#define SHRTIM_OEN_TD1OEN ((uint32_t)0x00000040U) /* Bit[6] Timer D output 1 enable */ +#define SHRTIM_OEN_TC2OEN ((uint32_t)0x00000020U) /* Bit[5] Timer C output 2 enable */ +#define SHRTIM_OEN_TC1OEN ((uint32_t)0x00000010U) /* Bit[4] Timer C output 1 enable */ +#define SHRTIM_OEN_TB2OEN ((uint32_t)0x00000008U) /* Bit[3] Timer B output 2 enable */ +#define SHRTIM_OEN_TB1OEN ((uint32_t)0x00000004U) /* Bit[2] Timer B output 1 enable */ +#define SHRTIM_OEN_TA2OEN ((uint32_t)0x00000002U) /* Bit[1] Timer A output 2 enable */ +#define SHRTIM_OEN_TA1OEN ((uint32_t)0x00000001U) /* Bit[0] Timer A output 1 enable */ + +/** Bit definition for SHRTIM_ODIS register **/ +#define SHRTIM_ODIS_TF2ODIS ((uint32_t)0x00000800U) /* Bit[11] Timer F output 2 disable */ +#define SHRTIM_ODIS_TF1ODIS ((uint32_t)0x00000400U) /* Bit[10] Timer F output 1 disable */ +#define SHRTIM_ODIS_TE2ODIS ((uint32_t)0x00000200U) /* Bit[9] Timer E output 2 disable */ +#define SHRTIM_ODIS_TE1ODIS ((uint32_t)0x00000100U) /* Bit[8] Timer E output 1 disable */ +#define SHRTIM_ODIS_TD2ODIS ((uint32_t)0x00000080U) /* Bit[7] Timer D output 2 disable */ +#define SHRTIM_ODIS_TD1ODIS ((uint32_t)0x00000040U) /* Bit[6] Timer D output 1 disable */ +#define SHRTIM_ODIS_TC2ODIS ((uint32_t)0x00000020U) /* Bit[5] Timer C output 2 disable */ +#define SHRTIM_ODIS_TC1ODIS ((uint32_t)0x00000010U) /* Bit[4] Timer C output 1 disable */ +#define SHRTIM_ODIS_TB2ODIS ((uint32_t)0x00000008U) /* Bit[3] Timer B output 2 disable */ +#define SHRTIM_ODIS_TB1ODIS ((uint32_t)0x00000004U) /* Bit[2] Timer B output 1 disable */ +#define SHRTIM_ODIS_TA2ODIS ((uint32_t)0x00000002U) /* Bit[1] Timer A output 2 disable */ +#define SHRTIM_ODIS_TA1ODIS ((uint32_t)0x00000001U) /* Bit[0] Timer A output 1 disable */ + +/** Bit definition for SHRTIM_ODISSTS register **/ +#define SHRTIM_ODISSTS_TF2ODISSTS ((uint32_t)0x00000800U) /* Bit[11] Timer F output 2 disable status */ +#define SHRTIM_ODISSTS_TF1ODISSTS ((uint32_t)0x00000400U) /* Bit[10] Timer F output 1 disable status */ +#define SHRTIM_ODISSTS_TE2ODISSTS ((uint32_t)0x00000200U) /* Bit[9] Timer E output 2 disable status */ +#define SHRTIM_ODISSTS_TE1ODISSTS ((uint32_t)0x00000100U) /* Bit[8] Timer E output 1 disable status */ +#define SHRTIM_ODISSTS_TD2ODISSTS ((uint32_t)0x00000080U) /* Bit[7] Timer D output 2 disable status */ +#define SHRTIM_ODISSTS_TD1ODISSTS ((uint32_t)0x00000040U) /* Bit[6] Timer D output 1 disable status */ +#define SHRTIM_ODISSTS_TC2ODISSTS ((uint32_t)0x00000020U) /* Bit[5] Timer C output 2 disable status */ +#define SHRTIM_ODISSTS_TC1ODISSTS ((uint32_t)0x00000010U) /* Bit[4] Timer C output 1 disable status */ +#define SHRTIM_ODISSTS_TB2ODISSTS ((uint32_t)0x00000008U) /* Bit[3] Timer B output 2 disable status */ +#define SHRTIM_ODISSTS_TB1ODISSTS ((uint32_t)0x00000004U) /* Bit[2] Timer B output 1 disable status */ +#define SHRTIM_ODISSTS_TA2ODISSTS ((uint32_t)0x00000002U) /* Bit[1] Timer A output 2 disable status */ +#define SHRTIM_ODISSTS_TA1ODISSTS ((uint32_t)0x00000001U) /* Bit[0] Timer A output 1 disable status */ + +/** Bit definition for SHRTIM_BMCTRL register **/ +#define SHRTIM_BMCTRL_BMSTS ((uint32_t)0x80000000U) /* Bit[31] Burst mode operation status */ +#define SHRTIM_BMCTRL_TFBM ((uint32_t)0x00400000U) /* Bit[22] Timer F burst mode */ +#define SHRTIM_BMCTRL_TEBM ((uint32_t)0x00200000U) /* Bit[21] Timer E burst mode */ +#define SHRTIM_BMCTRL_TDBM ((uint32_t)0x00100000U) /* Bit[20] Timer D burst mode */ +#define SHRTIM_BMCTRL_TCBM ((uint32_t)0x00080000U) /* Bit[19] Timer C burst mode */ +#define SHRTIM_BMCTRL_TBBM ((uint32_t)0x00040000U) /* Bit[18] Timer B burst mode */ +#define SHRTIM_BMCTRL_TABM ((uint32_t)0x00020000U) /* Bit[17] Timer A burst mode */ +#define SHRTIM_BMCTRL_MBM ((uint32_t)0x00010000U) /* Bit[16] Master timer burst mode */ +#define SHRTIM_BMCTRL_BMPLEN ((uint32_t)0x00000400U) /* Bit[10] Burst mode preload enable */ +#define SHRTIM_BMCTRL_BMPSC ((uint32_t)0x000003C0U) /* Bit[9:6] Burst mode prescaler */ +#define SHRTIM_BMCTRL_BMPSC_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_BMCTRL_BMPSC_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_BMCTRL_BMPSC_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_BMCTRL_BMPSC_3 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_BMCTRL_BMCK ((uint32_t)0x0000003CU) /* Bit[5:2] Burst mode clock source */ +#define SHRTIM_BMCTRL_BMCK_0 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_BMCTRL_BMCK_1 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_BMCTRL_BMCK_2 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_BMCTRL_BMCK_3 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_BMCTRL_BMOM ((uint32_t)0x00000002U) /* Bit[1] Burst mode operating mode */ +#define SHRTIM_BMCTRL_BMEN ((uint32_t)0x00000001U) /* Bit[0] Burst mode enable */ + +/** Bit definition for SHRTIM_BMTG register **/ +#define SHRTIM_BMTG_OCEV ((uint32_t)0x80000000U) /* Bit[31] On-chip event */ +#define SHRTIM_BMTG_EXEV8 ((uint32_t)0x40000000U) /* Bit[30] External event 8 (TIMD filters applied) */ +#define SHRTIM_BMTG_EXEV7 ((uint32_t)0x20000000U) /* Bit[29] External event 7 (TIMA filters applied) */ +#define SHRTIM_BMTG_TDPRDEXEV8 ((uint32_t)0x10000000U) /* Bit[28] Timer D period following external event 8 */ +#define SHRTIM_BMTG_TAPRDEXEV7 ((uint32_t)0x08000000U) /* Bit[27] Timer A period following external event 7 */ +#define SHRTIM_BMTG_TECMP2 ((uint32_t)0x04000000U) /* Bit[26] Timer E compare 2 event */ +#define SHRTIM_BMTG_TECMP1 ((uint32_t)0x02000000U) /* Bit[25] Timer E compare 1 event */ +#define SHRTIM_BMTG_TEREPT ((uint32_t)0x01000000U) /* Bit[24] Timer E repetition */ +#define SHRTIM_BMTG_TFCMP1 ((uint32_t)0x00800000U) /* Bit[23] Timer F compare 1 event */ +#define SHRTIM_BMTG_TDCMP2 ((uint32_t)0x00400000U) /* Bit[22] Timer D compare 2 event */ +#define SHRTIM_BMTG_TFREPT ((uint32_t)0x00200000U) /* Bit[21] Timer F repetition */ +#define SHRTIM_BMTG_TDREPT ((uint32_t)0x00100000U) /* Bit[20] Timer D repetition */ +#define SHRTIM_BMTG_TDRSTRO ((uint32_t)0x00080000U) /* Bit[19] Timer D reset or roll-over */ +#define SHRTIM_BMTG_TFRSTRO ((uint32_t)0x00040000U) /* Bit[18] Timer F reset or roll-over */ +#define SHRTIM_BMTG_TCCMP1 ((uint32_t)0x00020000U) /* Bit[17] Timer C compare 1 event */ +#define SHRTIM_BMTG_TCREPT ((uint32_t)0x00010000U) /* Bit[16] Timer C repetition */ +#define SHRTIM_BMTG_TCRSTRO ((uint32_t)0x00008000U) /* Bit[15] Timer C reset or roll-over */ +#define SHRTIM_BMTG_TBCMP2 ((uint32_t)0x00004000U) /* Bit[14] Timer B compare 2 event */ +#define SHRTIM_BMTG_TBCMP1 ((uint32_t)0x00002000U) /* Bit[13] Timer B compare 1 event */ +#define SHRTIM_BMTG_TBREPT ((uint32_t)0x00001000U) /* Bit[12] Timer B repetition */ +#define SHRTIM_BMTG_TBRSTRO ((uint32_t)0x00000800U) /* Bit[11] Timer B reset or roll-over */ +#define SHRTIM_BMTG_TACMP2 ((uint32_t)0x00000400U) /* Bit[10] Timer A compare 2 event */ +#define SHRTIM_BMTG_TACMP1 ((uint32_t)0x00000200U) /* Bit[9] Timer A compare 1 event */ +#define SHRTIM_BMTG_TAREPT ((uint32_t)0x00000100U) /* Bit[8] Timer A repetition */ +#define SHRTIM_BMTG_TARSTRO ((uint32_t)0x00000080U) /* Bit[7] Timer A reset or roll-over */ +#define SHRTIM_BMTG_MCMP4 ((uint32_t)0x00000040U) /* Bit[6] Master compare 4 */ +#define SHRTIM_BMTG_MCMP3 ((uint32_t)0x00000020U) /* Bit[5] Master compare 3 */ +#define SHRTIM_BMTG_MCMP2 ((uint32_t)0x00000010U) /* Bit[4] Master compare 2 */ +#define SHRTIM_BMTG_MCMP1 ((uint32_t)0x00000008U) /* Bit[3] Master compare 1 */ +#define SHRTIM_BMTG_MREPT ((uint32_t)0x00000004U) /* Bit[2] Master repetition */ +#define SHRTIM_BMTG_MRSTRO ((uint32_t)0x00000002U) /* Bit[1] Master reset or roll-over */ +#define SHRTIM_BMTG_SWSTRT ((uint32_t)0x00000001U) /* Bit[0] Software start */ + +/** Bit definition for SHRTIM_BMCMP register **/ +#define SHRTIM_BMCMP_BMCMP ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Compare value while in burst mode */ +#define SHRTIM_BMCMP_BMCMP_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_BMCMP_BMCMP_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_BMCMP_BMCMP_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_BMCMP_BMCMP_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_BMCMP_BMCMP_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_BMCMP_BMCMP_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_BMCMP_BMCMP_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_BMCMP_BMCMP_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_BMCMP_BMCMP_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_BMCMP_BMCMP_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_BMCMP_BMCMP_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_BMCMP_BMCMP_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_BMCMP_BMCMP_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_BMCMP_BMCMP_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_BMCMP_BMCMP_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_BMCMP_BMCMP_15 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_BMCMP_BMCMP_16 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_BMCMP_BMCMP_17 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_BMCMP_BMCMP_18 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_BMCMP_BMCMP_19 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_BMCMP_BMCMP_20 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_BMCMP_BMCMP_21 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_BMCMP_BMCMP_22 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_BMCMP_BMCMP_23 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_BMCMP_BMCMP_24 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_BMCMP_BMCMP_25 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_BMCMP_BMCMP_26 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_BMCMP_BMCMP_27 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_BMCMP_BMCMP_28 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_BMCMP_BMCMP_29 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_BMCMP_BMCMP_30 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_BMCMP_BMCMP_31 ((uint32_t)0x80000000U) /* Bit31 */ + +/** Bit definition for SHRTIM_BMPRD register **/ +#define SHRTIM_BMPRD_BMPRD ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Period value while in burst mode */ +#define SHRTIM_BMPRD_BMPRD_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_BMPRD_BMPRD_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_BMPRD_BMPRD_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_BMPRD_BMPRD_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_BMPRD_BMPRD_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_BMPRD_BMPRD_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_BMPRD_BMPRD_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_BMPRD_BMPRD_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_BMPRD_BMPRD_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_BMPRD_BMPRD_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_BMPRD_BMPRD_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_BMPRD_BMPRD_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_BMPRD_BMPRD_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_BMPRD_BMPRD_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_BMPRD_BMPRD_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_BMPRD_BMPRD_15 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_BMPRD_BMPRD_16 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_BMPRD_BMPRD_17 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_BMPRD_BMPRD_18 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_BMPRD_BMPRD_19 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_BMPRD_BMPRD_20 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_BMPRD_BMPRD_21 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_BMPRD_BMPRD_22 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_BMPRD_BMPRD_23 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_BMPRD_BMPRD_24 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_BMPRD_BMPRD_25 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_BMPRD_BMPRD_26 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_BMPRD_BMPRD_27 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_BMPRD_BMPRD_28 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_BMPRD_BMPRD_29 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_BMPRD_BMPRD_30 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_BMPRD_BMPRD_31 ((uint32_t)0x80000000U) /* Bit31 */ + +/** Bit definition for SHRTIM_EXEVCTRL1 register **/ +#define SHRTIM_EXEVCTRL1_EXEV5SENS ((uint32_t)0x30000000U) /* Bit[29:28] External event 5 sensitivity */ +#define SHRTIM_EXEVCTRL1_EXEV5SENS_0 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_EXEVCTRL1_EXEV5SENS_1 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_EXEVCTRL1_EXEV5POL ((uint32_t)0x08000000U) /* Bit[27] External event 5 polarity */ +#define SHRTIM_EXEVCTRL1_EXEV5SRC ((uint32_t)0x07000000U) /* Bit[26:24] External event 5 source */ +#define SHRTIM_EXEVCTRL1_EXEV5SRC_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_EXEVCTRL1_EXEV5SRC_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_EXEVCTRL1_EXEV5SRC_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_EXEVCTRL1_EXEV4SENS ((uint32_t)0x00C00000U) /* Bit[23:22] External event 4 sensitivity */ +#define SHRTIM_EXEVCTRL1_EXEV4SENS_0 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_EXEVCTRL1_EXEV4SENS_1 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_EXEVCTRL1_EXEV4POL ((uint32_t)0x00200000U) /* Bit[21] External event 4 polarity */ +#define SHRTIM_EXEVCTRL1_EXEV4SRC ((uint32_t)0x001C0000U) /* Bit[20:18] External event 4 source */ +#define SHRTIM_EXEVCTRL1_EXEV4SRC_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_EXEVCTRL1_EXEV4SRC_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_EXEVCTRL1_EXEV4SRC_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_EXEVCTRL1_EXEV3SENS ((uint32_t)0x00030000U) /* Bit[17:16] External event 3 sensitivity */ +#define SHRTIM_EXEVCTRL1_EXEV3SENS_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_EXEVCTRL1_EXEV3SENS_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_EXEVCTRL1_EXEV3POL ((uint32_t)0x00008000U) /* Bit[15] External event 3 polarity */ +#define SHRTIM_EXEVCTRL1_EXEV3SRC ((uint32_t)0x00007000U) /* Bit[14:12] External event 3 source */ +#define SHRTIM_EXEVCTRL1_EXEV3SRC_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_EXEVCTRL1_EXEV3SRC_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_EXEVCTRL1_EXEV3SRC_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_EXEVCTRL1_EXEV2SENS ((uint32_t)0x00000C00U) /* Bit[11:10] External event 2 sensitivity */ +#define SHRTIM_EXEVCTRL1_EXEV2SENS_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_EXEVCTRL1_EXEV2SENS_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_EXEVCTRL1_EXEV2POL ((uint32_t)0x00000200U) /* Bit[9] External event 2 polarity */ +#define SHRTIM_EXEVCTRL1_EXEV2SRC ((uint32_t)0x000001C0U) /* Bit[8:6] External event 2 source */ +#define SHRTIM_EXEVCTRL1_EXEV2SRC_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_EXEVCTRL1_EXEV2SRC_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_EXEVCTRL1_EXEV2SRC_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_EXEVCTRL1_EXEV1SENS ((uint32_t)0x00000030U) /* Bit[5:4] External event 1 sensitivity */ +#define SHRTIM_EXEVCTRL1_EXEV1SENS_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_EXEVCTRL1_EXEV1SENS_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_EXEVCTRL1_EXEV1POL ((uint32_t)0x00000008U) /* Bit[3] External event 1 polarity */ +#define SHRTIM_EXEVCTRL1_EXEV1SRC ((uint32_t)0x00000007U) /* Bit[2:0] External event 1 source */ +#define SHRTIM_EXEVCTRL1_EXEV1SRC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_EXEVCTRL1_EXEV1SRC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_EXEVCTRL1_EXEV1SRC_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for SHRTIM_EXEVCTRL2 register **/ +#define SHRTIM_EXEVCTRL2_EXEV10SENS ((uint32_t)0x30000000U) /* Bit[29:28] External event 10 sensitivity */ +#define SHRTIM_EXEVCTRL2_EXEV10SENS_0 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_EXEVCTRL2_EXEV10SENS_1 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_EXEVCTRL2_EXEV10POL ((uint32_t)0x08000000U) /* Bit[27] External event 10 polarity */ +#define SHRTIM_EXEVCTRL2_EXEV10SRC ((uint32_t)0x07000000U) /* Bit[26:24] External event 10 source */ +#define SHRTIM_EXEVCTRL2_EXEV10SRC_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_EXEVCTRL2_EXEV10SRC_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_EXEVCTRL2_EXEV10SRC_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_EXEVCTRL2_EXEV9SENS ((uint32_t)0x00C00000U) /* Bit[23:22] External event 9 sensitivity */ +#define SHRTIM_EXEVCTRL2_EXEV9SENS_0 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_EXEVCTRL2_EXEV9SENS_1 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_EXEVCTRL2_EXEV9POL ((uint32_t)0x00200000U) /* Bit[21] External event 9 polarity */ +#define SHRTIM_EXEVCTRL2_EXEV9SRC ((uint32_t)0x001C0000U) /* Bit[20:18] External event 9 source */ +#define SHRTIM_EXEVCTRL2_EXEV9SRC_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_EXEVCTRL2_EXEV9SRC_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_EXEVCTRL2_EXEV9SRC_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_EXEVCTRL2_EXEV8SENS ((uint32_t)0x00030000U) /* Bit[17:16] External event 8 sensitivity */ +#define SHRTIM_EXEVCTRL2_EXEV8SENS_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_EXEVCTRL2_EXEV8SENS_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_EXEVCTRL2_EXEV8POL ((uint32_t)0x00008000U) /* Bit[15] External event 8 polarity */ +#define SHRTIM_EXEVCTRL2_EXEV8SRC ((uint32_t)0x00007000U) /* Bit[14:12] External event 8 source */ +#define SHRTIM_EXEVCTRL2_EXEV8SRC_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_EXEVCTRL2_EXEV8SRC_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_EXEVCTRL2_EXEV8SRC_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_EXEVCTRL2_EXEV7SENS ((uint32_t)0x00000C00U) /* Bit[11:10] External event 7 sensitivity */ +#define SHRTIM_EXEVCTRL2_EXEV7SENS_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_EXEVCTRL2_EXEV7SENS_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_EXEVCTRL2_EXEV7POL ((uint32_t)0x00000200U) /* Bit[9] External event 7 polarity */ +#define SHRTIM_EXEVCTRL2_EXEV7SRC ((uint32_t)0x000001C0U) /* Bit[8:6] External event 7 source */ +#define SHRTIM_EXEVCTRL2_EXEV7SRC_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_EXEVCTRL2_EXEV7SRC_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_EXEVCTRL2_EXEV7SRC_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_EXEVCTRL2_EXEV6SENS ((uint32_t)0x00000030U) /* Bit[5:4] External event 6 sensitivity */ +#define SHRTIM_EXEVCTRL2_EXEV6SENS_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_EXEVCTRL2_EXEV6SENS_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_EXEVCTRL2_EXEV6POL ((uint32_t)0x00000008U) /* Bit[3] External event 6 polarity */ +#define SHRTIM_EXEVCTRL2_EXEV6SRC ((uint32_t)0x00000007U) /* Bit[2:0] External event 6 source */ +#define SHRTIM_EXEVCTRL2_EXEV6SRC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_EXEVCTRL2_EXEV6SRC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_EXEVCTRL2_EXEV6SRC_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for SHRTIM_EXEVCTRL3 register **/ +#define SHRTIM_EXEVCTRL3_EXEV5FM ((uint32_t)0x10000000U) /* Bit[28] External event 5 fast mode */ +#define SHRTIM_EXEVCTRL3_EXEV5F ((uint32_t)0x0F000000U) /* Bit[27:24] External event 5 filter */ +#define SHRTIM_EXEVCTRL3_EXEV5F_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_EXEVCTRL3_EXEV5F_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_EXEVCTRL3_EXEV5F_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_EXEVCTRL3_EXEV5F_3 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_EXEVCTRL3_EXEV4FM ((uint32_t)0x00400000U) /* Bit[22] External event 4 fast mode */ +#define SHRTIM_EXEVCTRL3_EXEV4F ((uint32_t)0x003C0000U) /* Bit[21:18] External event 4 filter */ +#define SHRTIM_EXEVCTRL3_EXEV4F_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_EXEVCTRL3_EXEV4F_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_EXEVCTRL3_EXEV4F_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_EXEVCTRL3_EXEV4F_3 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_EXEVCTRL3_EXEV3FM ((uint32_t)0x00010000U) /* Bit[16] External event 3 fast mode */ +#define SHRTIM_EXEVCTRL3_EXEV3F ((uint32_t)0x0000F000U) /* Bit[15:12] External event 3 filter */ +#define SHRTIM_EXEVCTRL3_EXEV3F_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_EXEVCTRL3_EXEV3F_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_EXEVCTRL3_EXEV3F_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_EXEVCTRL3_EXEV3F_3 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_EXEVCTRL3_EXEV2FM ((uint32_t)0x00000400U) /* Bit[10] External event 2 fast mode */ +#define SHRTIM_EXEVCTRL3_EXEV2F ((uint32_t)0x000003C0U) /* Bit[9:6] External event 2 filter */ +#define SHRTIM_EXEVCTRL3_EXEV2F_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_EXEVCTRL3_EXEV2F_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_EXEVCTRL3_EXEV2F_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_EXEVCTRL3_EXEV2F_3 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_EXEVCTRL3_EXEV1FM ((uint32_t)0x00000010U) /* Bit[4] External event 1 fast mode */ +#define SHRTIM_EXEVCTRL3_EXEV1F ((uint32_t)0x0000000FU) /* Bit[3:0] External event 1 filter */ +#define SHRTIM_EXEVCTRL3_EXEV1F_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_EXEVCTRL3_EXEV1F_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_EXEVCTRL3_EXEV1F_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_EXEVCTRL3_EXEV1F_3 ((uint32_t)0x00000008U) /* Bit3 */ + +/** Bit definition for SHRTIM_EXEVCTRL4 register **/ +#define SHRTIM_EXEVCTRL4_EXEVSCD ((uint32_t)0xC0000000U) /* Bit[31:30] External event sampling clock division */ +#define SHRTIM_EXEVCTRL4_EXEVSCD_0 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_EXEVCTRL4_EXEVSCD_1 ((uint32_t)0x80000000U) /* Bit31 */ +#define SHRTIM_EXEVCTRL4_EXEV10FM ((uint32_t)0x10000000U) /* Bit[28] External event10 fast mode */ +#define SHRTIM_EXEVCTRL4_EXEV10F ((uint32_t)0x0F000000U) /* Bit[27:24] External event 10 filter */ +#define SHRTIM_EXEVCTRL4_EXEV10F_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_EXEVCTRL4_EXEV10F_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_EXEVCTRL4_EXEV10F_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_EXEVCTRL4_EXEV10F_3 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_EXEVCTRL4_EXEV9FM ((uint32_t)0x00400000U) /* Bit[22] External event9 fast mode */ +#define SHRTIM_EXEVCTRL4_EXEV9F ((uint32_t)0x003C0000U) /* Bit[21:18] External event 9 filter */ +#define SHRTIM_EXEVCTRL4_EXEV9F_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_EXEVCTRL4_EXEV9F_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_EXEVCTRL4_EXEV9F_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_EXEVCTRL4_EXEV9F_3 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_EXEVCTRL4_EXEV8FM ((uint32_t)0x00010000U) /* Bit[16] External event 8 fast mode */ +#define SHRTIM_EXEVCTRL4_EXEV8F ((uint32_t)0x0000F000U) /* Bit[15:12] External event 8 filter */ +#define SHRTIM_EXEVCTRL4_EXEV8F_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_EXEVCTRL4_EXEV8F_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_EXEVCTRL4_EXEV8F_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_EXEVCTRL4_EXEV8F_3 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_EXEVCTRL4_EXEV7FM ((uint32_t)0x00000400U) /* Bit[10] External event7 fast mode */ +#define SHRTIM_EXEVCTRL4_EXEV7F ((uint32_t)0x000003C0U) /* Bit[9:6] External event 7 filter */ +#define SHRTIM_EXEVCTRL4_EXEV7F_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_EXEVCTRL4_EXEV7F_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_EXEVCTRL4_EXEV7F_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_EXEVCTRL4_EXEV7F_3 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_EXEVCTRL4_EXEV6FM ((uint32_t)0x00000010U) /* Bit[4] External event6 fast mode */ +#define SHRTIM_EXEVCTRL4_EXEV6F ((uint32_t)0x0000000FU) /* Bit[3:0] External event 6 filter */ +#define SHRTIM_EXEVCTRL4_EXEV6F_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_EXEVCTRL4_EXEV6F_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_EXEVCTRL4_EXEV6F_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_EXEVCTRL4_EXEV6F_3 ((uint32_t)0x00000008U) /* Bit3 */ + +/** Bit definition for SHRTIM_ADTG1SRC1 register **/ +#define SHRTIM_ADTG1SRC1_ADTG1TCPRD ((uint32_t)0x04000000U) /* Bit[26] ADC trigger 1 driven by timer C period event */ +#define SHRTIM_ADTG1SRC1_ADTG1TCCMP5 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 1 driven by timer C compare 5 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TCCMP4 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 1 driven by timer C compare 4 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TCCMP3 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 1 driven by timer C compare 3 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TCCMP2 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 1 driven by timer C compare 2 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TCCMP1 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 1 driven by timer C compare 1 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TBRSTRO ((uint32_t)0x00100000U) /* Bit[20] ADC trigger 1 driven by timer B reset and roll-over events */ +#define SHRTIM_ADTG1SRC1_ADTG1TBPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 1 driven by timer B period event */ +#define SHRTIM_ADTG1SRC1_ADTG1TBCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 1 driven by timer B compare 5 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TBCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 1 driven by timer B compare 4 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TBCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 1 driven by timer B compare 3 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TBCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 1 driven by timer B compare 2 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TBCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 1 driven by timer B compare 1 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TARSTRO ((uint32_t)0x00002000U) /* Bit[13] ADC trigger 1 driven by timer A reset and roll-over events */ +#define SHRTIM_ADTG1SRC1_ADTG1TAPRD ((uint32_t)0x00001000U) /* Bit[12] ADC trigger 1 driven by timer A period event */ +#define SHRTIM_ADTG1SRC1_ADTG1TACMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 1 driven by timer A compare 5 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TACMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 1 driven by timer A compare 4 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TACMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 1 driven by timer A compare 3 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TACMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 1 driven by timer A compare 2 event */ +#define SHRTIM_ADTG1SRC1_ADTG1TACMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 1 driven by timer A compare 1 event */ +#define SHRTIM_ADTG1SRC1_ADTG1MPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 1 driven by master period event */ +#define SHRTIM_ADTG1SRC1_ADTG1MCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 1 driven by master compare 4 event */ +#define SHRTIM_ADTG1SRC1_ADTG1MCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 1 driven by master compare 3 event */ +#define SHRTIM_ADTG1SRC1_ADTG1MCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 1 driven by master compare 2 event */ +#define SHRTIM_ADTG1SRC1_ADTG1MCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 1 driven by master compare 1 event */ + +/** Bit definition for SHRTIM_ADTG1SRC2 register **/ +#define SHRTIM_ADTG1SRC2_ADTG1EXEV5 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 1 driven by external event 5 */ +#define SHRTIM_ADTG1SRC2_ADTG1EXEV4 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 1 driven by external event 4 */ +#define SHRTIM_ADTG1SRC2_ADTG1EXEV3 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 1 driven by external event 3 */ +#define SHRTIM_ADTG1SRC2_ADTG1EXEV2 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 1 driven by external event 2 */ +#define SHRTIM_ADTG1SRC2_ADTG1EXEV1 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 1 driven by external event 1 */ +#define SHRTIM_ADTG1SRC2_ADTG1TFRSTRO ((uint32_t)0x00100000U) /* Bit[20] ADC trigger 1 driven by timer F reset and roll-over events */ +#define SHRTIM_ADTG1SRC2_ADTG1TFPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 1 driven by timer F period event */ +#define SHRTIM_ADTG1SRC2_ADTG1TFCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 1 driven by timer F compare 5 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TFCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 1 driven by timer F compare 4 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TFCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 1 driven by timer F compare 3 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TFCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 1 driven by timer F compare 2 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TFCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 1 driven by timer F compare 1 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TEPRD ((uint32_t)0x00001000U) /* Bit[12] ADC trigger 1 driven by timer E period event */ +#define SHRTIM_ADTG1SRC2_ADTG1TECMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 1 driven by timer E compare 5 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TECMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 1 driven by timer E compare 4 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TECMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 1 driven by timer E compare 3 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TECMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 1 driven by timer E compare 2 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TECMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 1 driven by timer E compare 1 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TDPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 1 driven by timer D period event */ +#define SHRTIM_ADTG1SRC2_ADTG1TDCMP5 ((uint32_t)0x00000010U) /* Bit[4] ADC trigger 1 driven by timer D compare 5 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TDCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 1 driven by timer D compare 4 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TDCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 1 driven by timer D compare 3 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TDCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 1 driven by timer D compare 2 event */ +#define SHRTIM_ADTG1SRC2_ADTG1TDCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 1 driven by timer D compare 1 event */ + +/** Bit definition for SHRTIM_ADTG2SRC1 register **/ +#define SHRTIM_ADTG2SRC1_ADTG2TCRSTRO ((uint32_t)0x08000000U) /* Bit[27] ADC trigger 2 driven by timer C reset and roll-over events */ +#define SHRTIM_ADTG2SRC1_ADTG2TCPRD ((uint32_t)0x04000000U) /* Bit[26] ADC trigger 2 driven by timer C period event */ +#define SHRTIM_ADTG2SRC1_ADTG2TCCMP5 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 2 driven by timer C compare 5 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TCCMP4 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 2 driven by timer C compare 4 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TCCMP3 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 2 driven by timer C compare 3 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TCCMP2 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 2 driven by timer C compare 2 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TCCMP1 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 2 driven by timer C compare 1 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TBPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 2 driven by timer B period event */ +#define SHRTIM_ADTG2SRC1_ADTG2TBCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 2 driven by timer B compare 5 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TBCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 2 driven by timer B compare 4 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TBCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 2 driven by timer B compare 3 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TBCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 2 driven by timer B compare 2 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TBCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 2 driven by timer B compare 1 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TAPRD ((uint32_t)0x00001000U) /* Bit[12] ADC trigger 2 driven by timer A period event */ +#define SHRTIM_ADTG2SRC1_ADTG2TACMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 2 driven by timer A compare 5 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TACMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 2 driven by timer A compare 4 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TACMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 2 driven by timer A compare 3 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TACMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 2 driven by timer A compare 2 event */ +#define SHRTIM_ADTG2SRC1_ADTG2TACMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 2 driven by timer A compare 1 event */ +#define SHRTIM_ADTG2SRC1_ADTG2MPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 2 driven by master period event */ +#define SHRTIM_ADTG2SRC1_ADTG2MCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 2 driven by master compare 4 event */ +#define SHRTIM_ADTG2SRC1_ADTG2MCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 2 driven by master compare 3 event */ +#define SHRTIM_ADTG2SRC1_ADTG2MCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 2 driven by master compare 2 event */ +#define SHRTIM_ADTG2SRC1_ADTG2MCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 2 driven by master compare 1 event */ + +/** Bit definition for SHRTIM_ADTG2SRC2 register **/ +#define SHRTIM_ADTG2SRC2_ADTG2EXEV10 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 2 driven by external event 10 */ +#define SHRTIM_ADTG2SRC2_ADTG2EXEV9 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 2 driven by external event 9 */ +#define SHRTIM_ADTG2SRC2_ADTG2EXEV8 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 2 driven by external event 8 */ +#define SHRTIM_ADTG2SRC2_ADTG2EXEV7 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 2 driven by external event 7 */ +#define SHRTIM_ADTG2SRC2_ADTG2EXEV6 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 2 driven by external event 6 */ +#define SHRTIM_ADTG2SRC2_ADTG2TFPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 2 driven by timer F period event */ +#define SHRTIM_ADTG2SRC2_ADTG2TFCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 2 driven by timer F compare 5 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TFCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 2 driven by timer F compare 4 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TFCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 2 driven by timer F compare 3 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TFCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 2 driven by timer F compare 2 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TFCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 2 driven by timer F compare 1 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TERSTRO ((uint32_t)0x00002000U) /* Bit[13] ADC trigger 2 driven by timer E reset and roll-over events */ +#define SHRTIM_ADTG2SRC2_ADTG2TECMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 2 driven by timer E compare 5 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TECMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 2 driven by timer E compare 4 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TECMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 2 driven by timer E compare 3 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TECMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 2 driven by timer E compare 2 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TECMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 2 driven by timer E compare 1 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TDRSTRO ((uint32_t)0x00000040U) /* Bit[6] ADC trigger 2 driven by timer D reset and roll-over events */ +#define SHRTIM_ADTG2SRC2_ADTG2TDPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 2 driven by timer D period event */ +#define SHRTIM_ADTG2SRC2_ADTG2TDCMP5 ((uint32_t)0x00000010U) /* Bit[4] ADC trigger 2 driven by timer D compare 5 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TDCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 2 driven by timer D compare 4 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TDCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 2 driven by timer D compare 3 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TDCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 2 driven by timer D compare 2 event */ +#define SHRTIM_ADTG2SRC2_ADTG2TDCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 2 driven by timer D compare 1 event */ + +/** Bit definition for SHRTIM_ADTG3SRC1 register **/ +#define SHRTIM_ADTG3SRC1_ADTG3TCPRD ((uint32_t)0x04000000U) /* Bit[26] ADC trigger 3 driven by timer C period event */ +#define SHRTIM_ADTG3SRC1_ADTG3TCCMP5 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 3 driven by timer C compare 5 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TCCMP4 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 3 driven by timer C compare 4 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TCCMP3 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 3 driven by timer C compare 3 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TCCMP2 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 3 driven by timer C compare 2 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TCCMP1 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 3 driven by timer C compare 1 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TBRSTRO ((uint32_t)0x00100000U) /* Bit[20] ADC trigger 3 driven by timer B reset and roll-over events */ +#define SHRTIM_ADTG3SRC1_ADTG3TBPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 3 driven by timer B period event */ +#define SHRTIM_ADTG3SRC1_ADTG3TBCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 3 driven by timer B compare 5 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TBCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 3 driven by timer B compare 4 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TBCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 3 driven by timer B compare 3 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TBCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 3 driven by timer B compare 2 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TBCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 3 driven by timer B compare 1 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TARSTRO ((uint32_t)0x00002000U) /* Bit[13] ADC trigger 3 driven by timer A reset and roll-over events */ +#define SHRTIM_ADTG3SRC1_ADTG3TAPRD ((uint32_t)0x00001000U) /* Bit[12] ADC trigger 3 driven by timer A period event */ +#define SHRTIM_ADTG3SRC1_ADTG3TACMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 3 driven by timer A compare 5 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TACMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 3 driven by timer A compare 4 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TACMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 3 driven by timer A compare 3 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TACMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 3 driven by timer A compare 2 event */ +#define SHRTIM_ADTG3SRC1_ADTG3TACMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 3 driven by timer A compare 1 event */ +#define SHRTIM_ADTG3SRC1_ADTG3MPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 3 driven by master period event */ +#define SHRTIM_ADTG3SRC1_ADTG3MCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 3 driven by master compare 4 event */ +#define SHRTIM_ADTG3SRC1_ADTG3MCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 3 driven by master compare 3 event */ +#define SHRTIM_ADTG3SRC1_ADTG3MCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 3 driven by master compare 2 event */ +#define SHRTIM_ADTG3SRC1_ADTG3MCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 3 driven by master compare 1 event */ + +/** Bit definition for SHRTIM_ADTG3SRC2 register **/ +#define SHRTIM_ADTG3SRC2_ADTG3EXEV5 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 3 driven by external event 5 */ +#define SHRTIM_ADTG3SRC2_ADTG3EXEV4 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 3 driven by external event 4 */ +#define SHRTIM_ADTG3SRC2_ADTG3EXEV3 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 3 driven by external event 3 */ +#define SHRTIM_ADTG3SRC2_ADTG3EXEV2 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 3 driven by external event 2 */ +#define SHRTIM_ADTG3SRC2_ADTG3EXEV1 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 3 driven by external event 1 */ +#define SHRTIM_ADTG3SRC2_ADTG3TFRSTRO ((uint32_t)0x00100000U) /* Bit[20] ADC trigger 3 driven by timer F reset and roll-over events */ +#define SHRTIM_ADTG3SRC2_ADTG3TFPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 3 driven by timer F period event */ +#define SHRTIM_ADTG3SRC2_ADTG3TFCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 3 driven by timer F compare 5 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TFCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 3 driven by timer F compare 4 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TFCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 3 driven by timer F compare 3 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TFCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 3 driven by timer F compare 2 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TFCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 3 driven by timer F compare 1 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TEPRD ((uint32_t)0x00001000U) /* Bit[12] ADC trigger 3 driven by timer E period event */ +#define SHRTIM_ADTG3SRC2_ADTG3TECMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 3 driven by timer E compare 5 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TECMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 3 driven by timer E compare 4 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TECMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 3 driven by timer E compare 3 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TECMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 3 driven by timer E compare 2 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TECMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 3 driven by timer E compare 1 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TDPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 3 driven by timer D period event */ +#define SHRTIM_ADTG3SRC2_ADTG3TDCMP5 ((uint32_t)0x00000010U) /* Bit[4] ADC trigger 3 driven by timer D compare 5 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TDCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 3 driven by timer D compare 4 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TDCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 3 driven by timer D compare 3 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TDCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 3 driven by timer D compare 2 event */ +#define SHRTIM_ADTG3SRC2_ADTG3TDCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 3 driven by timer D compare 1 event */ + +/** Bit definition for SHRTIM_ADTG4SRC1 register **/ +#define SHRTIM_ADTG4SRC1_ADTG4TCRSTRO ((uint32_t)0x08000000U) /* Bit[27] ADC trigger 4 driven by timer C reset and roll-over events */ +#define SHRTIM_ADTG4SRC1_ADTG4TCPRD ((uint32_t)0x04000000U) /* Bit[26] ADC trigger 4 driven by timer C period event */ +#define SHRTIM_ADTG4SRC1_ADTG4TCCMP5 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 4 driven by timer C compare 5 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TCCMP4 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 4 driven by timer C compare 4 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TCCMP3 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 4 driven by timer C compare 3 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TCCMP2 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 4 driven by timer C compare 2 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TCCMP1 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 4 driven by timer C compare 1 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TBPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 4 driven by timer B period event */ +#define SHRTIM_ADTG4SRC1_ADTG4TBCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 4 driven by timer B compare 5 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TBCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 4 driven by timer B compare 4 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TBCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 4 driven by timer B compare 3 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TBCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 4 driven by timer B compare 2 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TBCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 4 driven by timer B compare 1 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TAPRD ((uint32_t)0x00001000U) /* Bit[12] ADC trigger 4 driven by timer A period event */ +#define SHRTIM_ADTG4SRC1_ADTG4TACMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 4 driven by timer A compare 5 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TACMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 4 driven by timer A compare 4 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TACMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 4 driven by timer A compare 3 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TACMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 4 driven by timer A compare 2 event */ +#define SHRTIM_ADTG4SRC1_ADTG4TACMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 4 driven by timer A compare 1 event */ +#define SHRTIM_ADTG4SRC1_ADTG4MPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 4 driven by master period event */ +#define SHRTIM_ADTG4SRC1_ADTG4MCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 4 driven by master compare 4 event */ +#define SHRTIM_ADTG4SRC1_ADTG4MCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 4 driven by master compare 3 event */ +#define SHRTIM_ADTG4SRC1_ADTG4MCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 4 driven by master compare 2 event */ +#define SHRTIM_ADTG4SRC1_ADTG4MCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 4 driven by master compare 1 event */ + +/** Bit definition for SHRTIM_ADTG4SRC2 register **/ +#define SHRTIM_ADTG4SRC2_ADTG4EXEV10 ((uint32_t)0x02000000U) /* Bit[25] ADC trigger 4 driven by external event 10 */ +#define SHRTIM_ADTG4SRC2_ADTG4EXEV9 ((uint32_t)0x01000000U) /* Bit[24] ADC trigger 4 driven by external event 9 */ +#define SHRTIM_ADTG4SRC2_ADTG4EXEV8 ((uint32_t)0x00800000U) /* Bit[23] ADC trigger 4 driven by external event 8 */ +#define SHRTIM_ADTG4SRC2_ADTG4EXEV7 ((uint32_t)0x00400000U) /* Bit[22] ADC trigger 4 driven by external event 7 */ +#define SHRTIM_ADTG4SRC2_ADTG4EXEV6 ((uint32_t)0x00200000U) /* Bit[21] ADC trigger 4 driven by external event 6 */ +#define SHRTIM_ADTG4SRC2_ADTG4TFPRD ((uint32_t)0x00080000U) /* Bit[19] ADC trigger 4 driven by timer F period event */ +#define SHRTIM_ADTG4SRC2_ADTG4TFCMP5 ((uint32_t)0x00040000U) /* Bit[18] ADC trigger 4 driven by timer F compare 5 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TFCMP4 ((uint32_t)0x00020000U) /* Bit[17] ADC trigger 4 driven by timer F compare 4 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TFCMP3 ((uint32_t)0x00010000U) /* Bit[16] ADC trigger 4 driven by timer F compare 3 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TFCMP2 ((uint32_t)0x00008000U) /* Bit[15] ADC trigger 4 driven by timer F compare 2 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TFCMP1 ((uint32_t)0x00004000U) /* Bit[14] ADC trigger 4 driven by timer F compare 1 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TERSTRO ((uint32_t)0x00002000U) /* Bit[13] ADC trigger 4 driven by timer E reset and roll-over events */ +#define SHRTIM_ADTG4SRC2_ADTG4TECMP5 ((uint32_t)0x00000800U) /* Bit[11] ADC trigger 4 driven by timer E compare 5 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TECMP4 ((uint32_t)0x00000400U) /* Bit[10] ADC trigger 4 driven by timer E compare 4 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TECMP3 ((uint32_t)0x00000200U) /* Bit[9] ADC trigger 4 driven by timer E compare 3 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TECMP2 ((uint32_t)0x00000100U) /* Bit[8] ADC trigger 4 driven by timer E compare 2 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TECMP1 ((uint32_t)0x00000080U) /* Bit[7] ADC trigger 4 driven by timer E compare 1 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TDRSTRO ((uint32_t)0x00000040U) /* Bit[6] ADC trigger 4 driven by timer D reset and roll-over events */ +#define SHRTIM_ADTG4SRC2_ADTG4TDPRD ((uint32_t)0x00000020U) /* Bit[5] ADC trigger 4 driven by timer D period event */ +#define SHRTIM_ADTG4SRC2_ADTG4TDCMP5 ((uint32_t)0x00000010U) /* Bit[4] ADC trigger 4 driven by timer D compare 5 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TDCMP4 ((uint32_t)0x00000008U) /* Bit[3] ADC trigger 4 driven by timer D compare 4 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TDCMP3 ((uint32_t)0x00000004U) /* Bit[2] ADC trigger 4 driven by timer D compare 3 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TDCMP2 ((uint32_t)0x00000002U) /* Bit[1] ADC trigger 4 driven by timer D compare 2 event */ +#define SHRTIM_ADTG4SRC2_ADTG4TDCMP1 ((uint32_t)0x00000001U) /* Bit[0] ADC trigger 4 driven by timer D compare 1 event */ + +/** Bit definition for SHRTIM_FALTIN1 register **/ +#define SHRTIM_FALTIN1_FALT4LCK ((uint32_t)0x80000000U) /* Bit[31] Fault 4 lock */ +#define SHRTIM_FALTIN1_FALT4FLT ((uint32_t)0x78000000U) /* Bit[30:27] Fault 4 filter */ +#define SHRTIM_FALTIN1_FALT4FLT_0 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_FALTIN1_FALT4FLT_1 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_FALTIN1_FALT4FLT_2 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_FALTIN1_FALT4FLT_3 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_FALTIN1_FALT4SRC0 ((uint32_t)0x04000000U) /* Bit[26] Fault 4 source bit 0 */ +#define SHRTIM_FALTIN1_FALT4POL ((uint32_t)0x02000000U) /* Bit[25] Fault 4 polarity */ +#define SHRTIM_FALTIN1_FALT4E ((uint32_t)0x01000000U) /* Bit[24] Fault 4 enable */ +#define SHRTIM_FALTIN1_FALT3LCK ((uint32_t)0x00800000U) /* Bit[23] Fault 3 lock */ +#define SHRTIM_FALTIN1_FALT3FLT ((uint32_t)0x00780000U) /* Bit[22:19] Fault 3 filter */ +#define SHRTIM_FALTIN1_FALT3FLT_0 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_FALTIN1_FALT3FLT_1 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_FALTIN1_FALT3FLT_2 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_FALTIN1_FALT3FLT_3 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_FALTIN1_FALT3SRC0 ((uint32_t)0x00040000U) /* Bit[18] Fault 3 source bit 0 */ +#define SHRTIM_FALTIN1_FALT3POL ((uint32_t)0x00020000U) /* Bit[17] Fault 3 polarity */ +#define SHRTIM_FALTIN1_FALT3E ((uint32_t)0x00010000U) /* Bit[16] Fault 3 enable */ +#define SHRTIM_FALTIN1_FALT2LCK ((uint32_t)0x00008000U) /* Bit[15] Fault 2 lock */ +#define SHRTIM_FALTIN1_FALT2FLT ((uint32_t)0x00007800U) /* Bit[14:11] Fault 2 filter */ +#define SHRTIM_FALTIN1_FALT2FLT_0 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_FALTIN1_FALT2FLT_1 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_FALTIN1_FALT2FLT_2 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_FALTIN1_FALT2FLT_3 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_FALTIN1_FALT2SRC0 ((uint32_t)0x00000400U) /* Bit[10] Fault 2 source bit 0 */ +#define SHRTIM_FALTIN1_FALT2POL ((uint32_t)0x00000200U) /* Bit[9] Fault 2 polarity */ +#define SHRTIM_FALTIN1_FALT2E ((uint32_t)0x00000100U) /* Bit[8] Fault 2 enable */ +#define SHRTIM_FALTIN1_FALT1LCK ((uint32_t)0x00000080U) /* Bit[7] Fault 1 lock */ +#define SHRTIM_FALTIN1_FALT1FLT ((uint32_t)0x00000078U) /* Bit[6:3] Fault 1 filter */ +#define SHRTIM_FALTIN1_FALT1FLT_0 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_FALTIN1_FALT1FLT_1 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_FALTIN1_FALT1FLT_2 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_FALTIN1_FALT1FLT_3 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_FALTIN1_FALT1SRC0 ((uint32_t)0x00000004U) /* Bit[2] Fault 1 source bit 0 */ +#define SHRTIM_FALTIN1_FALT1POL ((uint32_t)0x00000002U) /* Bit[1] Fault 1 polarity */ +#define SHRTIM_FALTIN1_FALT1E ((uint32_t)0x00000001U) /* Bit[0] Fault 1 enable */ + +/** Bit definition for SHRTIM_FALTIN2 register **/ +#define SHRTIM_FALTIN2_SFALTSPLLEN ((uint32_t)0x80000000U) /* Bit[31] The SHRPLL lock fault as SHRTIM system fault input enable */ +#define SHRTIM_FALTIN2_SFALTPVDEN ((uint32_t)0x40000000U) /* Bit[30] The PVD error as SHRTIM system fault input enable */ +#define SHRTIM_FALTIN2_SFALTLOCKUPEN ((uint32_t)0x20000000U) /* Bit[29] The core lockup as SHRTIM system fault input enable */ +#define SHRTIM_FALTIN2_SFALTSMPAREN ((uint32_t)0x10000000U) /* Bit[28] The sram parity error as SHRTIM system fault input enable */ +#define SHRTIM_FALTIN2_SFALTSMECCEN ((uint32_t)0x08000000U) /* Bit[27] The sram ECC error as SHRTIM system fault input enable */ +#define SHRTIM_FALTIN2_SFALTCKSECEN ((uint32_t)0x04000000U) /* Bit[26] The clock security system error as SHRTIM system fault input enable */ +#define SHRTIM_FALTIN2_FALTSCD ((uint32_t)0x03000000U) /* Bit[25:24] Fault sampling clock division */ +#define SHRTIM_FALTIN2_FALTSCD_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_FALTIN2_FALTSCD_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_FALTIN2_FALT6SRC1 ((uint32_t)0x00200000U) /* Bit[21] Fault 6 source bit 1 */ +#define SHRTIM_FALTIN2_FALT5SRC1 ((uint32_t)0x00100000U) /* Bit[20] Fault 5 source bit 1 */ +#define SHRTIM_FALTIN2_FALT4SRC1 ((uint32_t)0x00080000U) /* Bit[19] Fault 4 source bit 1 */ +#define SHRTIM_FALTIN2_FALT3SRC1 ((uint32_t)0x00040000U) /* Bit[18] Fault 3 source bit 1 */ +#define SHRTIM_FALTIN2_FALT2SRC1 ((uint32_t)0x00020000U) /* Bit[17] Fault 2 source bit 1 */ +#define SHRTIM_FALTIN2_FALT1SRC1 ((uint32_t)0x00010000U) /* Bit[16] Fault 1 source bit 1 */ +#define SHRTIM_FALTIN2_FALT6LCK ((uint32_t)0x00008000U) /* Bit[15] Fault 6 lock */ +#define SHRTIM_FALTIN2_FALT6FLT ((uint32_t)0x00007800U) /* Bit[14:11] Fault 6 filter */ +#define SHRTIM_FALTIN2_FALT6FLT_0 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_FALTIN2_FALT6FLT_1 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_FALTIN2_FALT6FLT_2 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_FALTIN2_FALT6FLT_3 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_FALTIN2_FALT6SRC0 ((uint32_t)0x00000400U) /* Bit[10] Fault 6 source bit 0 */ +#define SHRTIM_FALTIN2_FALT6POL ((uint32_t)0x00000200U) /* Bit[9] Fault 6 polarity */ +#define SHRTIM_FALTIN2_FALT6E ((uint32_t)0x00000100U) /* Bit[8] Fault 6 enable */ +#define SHRTIM_FALTIN2_FALT5LCK ((uint32_t)0x00000080U) /* Bit[7] Fault 5 lock */ +#define SHRTIM_FALTIN2_FALT5FLT ((uint32_t)0x00000078U) /* Bit[6:3] Fault 5 filter */ +#define SHRTIM_FALTIN2_FALT5FLT_0 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_FALTIN2_FALT5FLT_1 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_FALTIN2_FALT5FLT_2 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_FALTIN2_FALT5FLT_3 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_FALTIN2_FALT5SRC0 ((uint32_t)0x00000004U) /* Bit[2] Fault 5 source bit 0 */ +#define SHRTIM_FALTIN2_FALT5POL ((uint32_t)0x00000002U) /* Bit[1] Fault 5 polarity */ +#define SHRTIM_FALTIN2_FALT5E ((uint32_t)0x00000001U) /* Bit[0] Fault 5 enable */ + +/** Bit definition for SHRTIM_FALTIN3 register **/ +#define SHRTIM_FALTIN3_FALT4RSTM ((uint32_t)0x80000000U) /* Bit[31] Fault 4 reset mode */ +#define SHRTIM_FALTIN3_FALT4CRST ((uint32_t)0x40000000U) /* Bit[30] Fault 4 counter reset */ +#define SHRTIM_FALTIN3_FALT4CNT ((uint32_t)0x3C000000U) /* Bit[29:26] Fault 4 counter */ +#define SHRTIM_FALTIN3_FALT4CNT_0 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_FALTIN3_FALT4CNT_1 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_FALTIN3_FALT4CNT_2 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_FALTIN3_FALT4CNT_3 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_FALTIN3_FALT4BLKS ((uint32_t)0x02000000U) /* Bit[25] Fault 4 blanking source */ +#define SHRTIM_FALTIN3_FALT4BLKEN ((uint32_t)0x01000000U) /* Bit[24] Fault 4 blanking enable */ +#define SHRTIM_FALTIN3_FALT3RSTM ((uint32_t)0x00800000U) /* Bit[23] Fault 3 reset mode */ +#define SHRTIM_FALTIN3_FALT3CRST ((uint32_t)0x00400000U) /* Bit[22] Fault 3 counter reset */ +#define SHRTIM_FALTIN3_FALT3CNT ((uint32_t)0x003C0000U) /* Bit[21:18] Fault 3 counter */ +#define SHRTIM_FALTIN3_FALT3CNT_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_FALTIN3_FALT3CNT_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_FALTIN3_FALT3CNT_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_FALTIN3_FALT3CNT_3 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_FALTIN3_FALT3BLKS ((uint32_t)0x00020000U) /* Bit[17] Fault 3 blanking source */ +#define SHRTIM_FALTIN3_FALT3BLKEN ((uint32_t)0x00010000U) /* Bit[16] Fault 3 blanking enable */ +#define SHRTIM_FALTIN3_FALT2RSTM ((uint32_t)0x00008000U) /* Bit[15] Fault 2 reset mode */ +#define SHRTIM_FALTIN3_FALT2CRST ((uint32_t)0x00004000U) /* Bit[14] Fault 2 counter reset */ +#define SHRTIM_FALTIN3_FALT2CNT ((uint32_t)0x00003C00U) /* Bit[13:10] Fault 2 counter */ +#define SHRTIM_FALTIN3_FALT2CNT_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_FALTIN3_FALT2CNT_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_FALTIN3_FALT2CNT_2 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_FALTIN3_FALT2CNT_3 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_FALTIN3_FALT2BLKS ((uint32_t)0x00000200U) /* Bit[9] Fault 2 blanking source */ +#define SHRTIM_FALTIN3_FALT2BLKEN ((uint32_t)0x00000100U) /* Bit[8] Fault 2 blanking enable */ +#define SHRTIM_FALTIN3_FALT1RSTM ((uint32_t)0x00000080U) /* Bit[7] Fault 1 reset mode */ +#define SHRTIM_FALTIN3_FALT1CRST ((uint32_t)0x00000040U) /* Bit[6] Fault 1 counter reset */ +#define SHRTIM_FALTIN3_FALT1CNT ((uint32_t)0x0000003CU) /* Bit[5:2] Fault 1 counter */ +#define SHRTIM_FALTIN3_FALT1CNT_0 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_FALTIN3_FALT1CNT_1 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_FALTIN3_FALT1CNT_2 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_FALTIN3_FALT1CNT_3 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_FALTIN3_FALT1BLKS ((uint32_t)0x00000002U) /* Bit[1] Fault 1 blanking source */ +#define SHRTIM_FALTIN3_FALT1BLKEN ((uint32_t)0x00000001U) /* Bit[0] Fault 1 blanking enable */ + +/** Bit definition for SHRTIM_FALTIN4 register **/ +#define SHRTIM_FALTIN4_FALT6RSTM ((uint32_t)0x00008000U) /* Bit[15] Fault 6 reset mode */ +#define SHRTIM_FALTIN4_FALT6CRST ((uint32_t)0x00004000U) /* Bit[14] Fault 6 counter reset */ +#define SHRTIM_FALTIN4_FALT6CNT ((uint32_t)0x00003C00U) /* Bit[13:10] Fault 6 counter */ +#define SHRTIM_FALTIN4_FALT6CNT_0 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_FALTIN4_FALT6CNT_1 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_FALTIN4_FALT6CNT_2 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_FALTIN4_FALT6CNT_3 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_FALTIN4_FALT6BLKS ((uint32_t)0x00000200U) /* Bit[9] Fault 6 blanking source */ +#define SHRTIM_FALTIN4_FALT6BLKEN ((uint32_t)0x00000100U) /* Bit[8] Fault 6 blanking enable */ +#define SHRTIM_FALTIN4_FALT5RSTM ((uint32_t)0x00000080U) /* Bit[7] Fault 5 reset mode */ +#define SHRTIM_FALTIN4_FALT5CRST ((uint32_t)0x00000040U) /* Bit[6] Fault 5 counter reset */ +#define SHRTIM_FALTIN4_FALT5CNT ((uint32_t)0x0000003CU) /* Bit[5:2] Fault 5 counter */ +#define SHRTIM_FALTIN4_FALT5CNT_0 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_FALTIN4_FALT5CNT_1 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_FALTIN4_FALT5CNT_2 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_FALTIN4_FALT5CNT_3 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_FALTIN4_FALT5BLKS ((uint32_t)0x00000002U) /* Bit[1] Fault 5 blanking source */ +#define SHRTIM_FALTIN4_FALT5BLKEN ((uint32_t)0x00000001U) /* Bit[0] Fault 5 blanking enable */ + +/** Bit definition for SHRTIM_BDMTUPD register **/ +#define SHRTIM_BDMTUPD_MCMPDAT4 ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_MCMP4DAT register update enable */ +#define SHRTIM_BDMTUPD_MCMPDAT3 ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_MCMP3DAT register update enable */ +#define SHRTIM_BDMTUPD_MCMPDAT2 ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_MCMP2DAT register update enable */ +#define SHRTIM_BDMTUPD_MCMPDAT1 ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_MCMP1DAT regiser update enable */ +#define SHRTIM_BDMTUPD_MREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_MREPT register update enable */ +#define SHRTIM_BDMTUPD_MPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_MPRD register update enable */ +#define SHRTIM_BDMTUPD_MCNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_MCNT register update enable */ +#define SHRTIM_BDMTUPD_MIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_MIDEN register update enable */ +#define SHRTIM_BDMTUPD_MINTCLR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_MINTCLR register update enable */ +#define SHRTIM_BDMTUPD_MCTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_CTRL register update enable */ + +/** Bit definition for SHRTIM_BDTAUPD register **/ +#define SHRTIM_BDTAUPD_TAEXEVFLT3 ((uint32_t)0x00400000U) /* Bit[22] SHRTIM_TAEXEVFLT3 register update enable. */ +#define SHRTIM_BDTAUPD_TACTRL2 ((uint32_t)0x00200000U) /* Bit[21] SHRTIM_TACTRL2 register update enable. */ +#define SHRTIM_BDTAUPD_TAFALT ((uint32_t)0x00100000U) /* Bit[20] SHRTIM_TAFAULT register update enable. */ +#define SHRTIM_BDTAUPD_TAOUT ((uint32_t)0x00080000U) /* Bit[19] SHRTIM_TAOUT register update enable. */ +#define SHRTIM_BDTAUPD_TACHOP ((uint32_t)0x00040000U) /* Bit[18] SHRTIM_TACHOP register update enable. */ +#define SHRTIM_BDTAUPD_TACNTRST ((uint32_t)0x00020000U) /* Bit[17] SHRTIM_TACNTRST register update enable */ +#define SHRTIM_BDTAUPD_TAEXEVFLT2 ((uint32_t)0x00010000U) /* Bit[16] SHRTIM_TAEXEVFLT2 register update enable. */ +#define SHRTIM_BDTAUPD_TAEXEVFLT1 ((uint32_t)0x00008000U) /* Bit[15] SHRTIM_TAEXEVFLT1 register update enable. */ +#define SHRTIM_BDTAUPD_TARST2 ((uint32_t)0x00004000U) /* Bit[14] SHRTIM_TARST2 register update enable. */ +#define SHRTIM_BDTAUPD_TASET2 ((uint32_t)0x00002000U) /* Bit[13] SHRTIM_TASET2 register update enable. */ +#define SHRTIM_BDTAUPD_TARST1 ((uint32_t)0x00001000U) /* Bit[12] SHRTIM_TARST1 register update enable. */ +#define SHRTIM_BDTAUPD_TASET1 ((uint32_t)0x00000800U) /* Bit[11] SHRTIM_TASET1 register update enable. */ +#define SHRTIM_BDTAUPD_TADT ((uint32_t)0x00000400U) /* Bit[10] SHRTIM_TADT register update enable. */ +#define SHRTIM_BDTAUPD_TACMP4DAT ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_TACMP4DAT register update enable. */ +#define SHRTIM_BDTAUPD_TACMP3DAT ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_TACMP3DAT register update enable. */ +#define SHRTIM_BDTAUPD_TACMP2DAT ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_TACMP2DAT register update enable. */ +#define SHRTIM_BDTAUPD_TACMP1DAT ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_TACMP1DAT register update enable. */ +#define SHRTIM_BDTAUPD_TAREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_TAREPT register update enable. */ +#define SHRTIM_BDTAUPD_TAPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_TAPRD register update enable. */ +#define SHRTIM_BDTAUPD_TACNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_TACNT register update enable. */ +#define SHRTIM_BDTAUPD_TAIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_TAIDEN register update enable. */ +#define SHRTIM_BDTAUPD_TAINTCLR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_TAINTCLR register update enable. */ +#define SHRTIM_BDTAUPD_TACTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_TIMACTRL register update enable. */ + +/** Bit definition for SHRTIM_BDTBUPD register **/ +#define SHRTIM_BDTBUPD_TBEXEVFLT3 ((uint32_t)0x00400000U) /* Bit[22] SHRTIM_TBEXEVFLT3 register update enable. */ +#define SHRTIM_BDTBUPD_TBCTRL2 ((uint32_t)0x00200000U) /* Bit[21] SHRTIM_TBCTRL2 register update enable. */ +#define SHRTIM_BDTBUPD_TBFALT ((uint32_t)0x00100000U) /* Bit[20] SHRTIM_TBFAULT register update enable. */ +#define SHRTIM_BDTBUPD_TBOUT ((uint32_t)0x00080000U) /* Bit[19] SHRTIM_TBOUT register update enable. */ +#define SHRTIM_BDTBUPD_TBCHOP ((uint32_t)0x00040000U) /* Bit[18] SHRTIM_TBCHOP register update enable. */ +#define SHRTIM_BDTBUPD_TBCNTRST ((uint32_t)0x00020000U) /* Bit[17] SHRTIM_TBCNTRST register update enable */ +#define SHRTIM_BDTBUPD_TBEXEVFLT2 ((uint32_t)0x00010000U) /* Bit[16] SHRTIM_TBEXEVFLT2 register update enable. */ +#define SHRTIM_BDTBUPD_TBEXEVFLT1 ((uint32_t)0x00008000U) /* Bit[15] SHRTIM_TBEXEVFLT1 register update enable. */ +#define SHRTIM_BDTBUPD_TBRST2 ((uint32_t)0x00004000U) /* Bit[14] SHRTIM_TBRST2 register update enable. */ +#define SHRTIM_BDTBUPD_TBSET2 ((uint32_t)0x00002000U) /* Bit[13] SHRTIM_TBSET2 register update enable. */ +#define SHRTIM_BDTBUPD_TBRST1 ((uint32_t)0x00001000U) /* Bit[12] SHRTIM_TBRST1 register update enable. */ +#define SHRTIM_BDTBUPD_TBSET1 ((uint32_t)0x00000800U) /* Bit[11] SHRTIM_TBSET1 register update enable. */ +#define SHRTIM_BDTBUPD_TBDT ((uint32_t)0x00000400U) /* Bit[10] SHRTIM_TBDT register update enable. */ +#define SHRTIM_BDTBUPD_TBCMP4DAT ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_TBCMP4DAT register update enable. */ +#define SHRTIM_BDTBUPD_TBCMP3DAT ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_TBCMP3DAT register update enable. */ +#define SHRTIM_BDTBUPD_TBCMP2DAT ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_TBCMP2DAT register update enable. */ +#define SHRTIM_BDTBUPD_TBCMP1DAT ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_TBCMP1DAT register update enable. */ +#define SHRTIM_BDTBUPD_TBREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_TBREPT register update enable. */ +#define SHRTIM_BDTBUPD_TBPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_TBPRD register update enable. */ +#define SHRTIM_BDTBUPD_TBCNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_TBCNT register update enable. */ +#define SHRTIM_BDTBUPD_TBIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_TBIDEN register update enable. */ +#define SHRTIM_BDTBUPD_TBINTCLR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_TBINTCLR register update enable. */ +#define SHRTIM_BDTBUPD_TBCTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_TACTRL register update enable. */ + +/** Bit definition for SHRTIM_BDTCUPD register **/ +#define SHRTIM_BDTCUPD_TCEXEVFLT3 ((uint32_t)0x00400000U) /* Bit[22] SHRTIM_TCEXEVFLT3 register update enable. */ +#define SHRTIM_BDTCUPD_TCCTRL2 ((uint32_t)0x00200000U) /* Bit[21] SHRTIM_TCCTRL2 register update enable. */ +#define SHRTIM_BDTCUPD_TCFALT ((uint32_t)0x00100000U) /* Bit[20] SHRTIM_TCFAULT register update enable. */ +#define SHRTIM_BDTCUPD_TCOUT ((uint32_t)0x00080000U) /* Bit[19] SHRTIM_TCOUT register update enable. */ +#define SHRTIM_BDTCUPD_TCCHOP ((uint32_t)0x00040000U) /* Bit[18] SHRTIM_TCCHOP register update enable. */ +#define SHRTIM_BDTCUPD_TCCNTRST ((uint32_t)0x00020000U) /* Bit[17] SHRTIM_TCCNTRST register update enable */ +#define SHRTIM_BDTCUPD_TCEXEVFLT2 ((uint32_t)0x00010000U) /* Bit[16] SHRTIM_TCEXEVFLT2 register update enable. */ +#define SHRTIM_BDTCUPD_TCEXEVFLT1 ((uint32_t)0x00008000U) /* Bit[15] SHRTIM_TCEXEVFLT1 register update enable. */ +#define SHRTIM_BDTCUPD_TCRST2 ((uint32_t)0x00004000U) /* Bit[14] SHRTIM_TCRST2 register update enable. */ +#define SHRTIM_BDTCUPD_TCSET2 ((uint32_t)0x00002000U) /* Bit[13] SHRTIM_TCSET2 register update enable. */ +#define SHRTIM_BDTCUPD_TCRST1 ((uint32_t)0x00001000U) /* Bit[12] SHRTIM_TCRST1 register update enable. */ +#define SHRTIM_BDTCUPD_TCSET1 ((uint32_t)0x00000800U) /* Bit[11] SHRTIM_TCSET1 register update enable. */ +#define SHRTIM_BDTCUPD_TCDT ((uint32_t)0x00000400U) /* Bit[10] SHRTIM_TCDT register update enable. */ +#define SHRTIM_BDTCUPD_TCCMP4DAT ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_TCCMP4DAT register update enable. */ +#define SHRTIM_BDTCUPD_TCCMP3DAT ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_TCCMP3DAT register update enable. */ +#define SHRTIM_BDTCUPD_TCCMP2DAT ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_TCCMP2DAT register update enable. */ +#define SHRTIM_BDTCUPD_TCCMP1DAT ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_TCCMP1DAT register update enable. */ +#define SHRTIM_BDTCUPD_TCREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_TCREPT register update enable. */ +#define SHRTIM_BDTCUPD_TCPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_TCPRD register update enable. */ +#define SHRTIM_BDTCUPD_TCCNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_TCCNT register update enable. */ +#define SHRTIM_BDTCUPD_TCIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_TCIDEN register update enable. */ +#define SHRTIM_BDTCUPD_TCINTCLR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_TCINTCLR register update enable. */ +#define SHRTIM_BDTCUPD_TCCTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_TCCTRL register update enable. */ + +/** Bit definition for SHRTIM_BDTDUPD register **/ +#define SHRTIM_BDTDUPD_TDEXEVFLT3 ((uint32_t)0x00400000U) /* Bit[22] SHRTIM_TDEXEVFLT3 register update enable. */ +#define SHRTIM_BDTDUPD_TDCTRL2 ((uint32_t)0x00200000U) /* Bit[21] SHRTIM_TDCTRL2 register update enable. */ +#define SHRTIM_BDTDUPD_TDFALT ((uint32_t)0x00100000U) /* Bit[20] SHRTIM_TDFAULT register update enable. */ +#define SHRTIM_BDTDUPD_TDOUT ((uint32_t)0x00080000U) /* Bit[19] SHRTIM_TDOUT register update enable. */ +#define SHRTIM_BDTDUPD_TDCHOP ((uint32_t)0x00040000U) /* Bit[18] SHRTIM_TDCHOP register update enable. */ +#define SHRTIM_BDTDUPD_TDCNTRST ((uint32_t)0x00020000U) /* Bit[17] SHRTIM_TDCNTRST register update enable */ +#define SHRTIM_BDTDUPD_TDEXEVFLT2 ((uint32_t)0x00010000U) /* Bit[16] SHRTIM_TDEXEVFLT2 register update enable. */ +#define SHRTIM_BDTDUPD_TDEXEVFLT1 ((uint32_t)0x00008000U) /* Bit[15] SHRTIM_TDEXEVFLT1 register update enable. */ +#define SHRTIM_BDTDUPD_TDRST2 ((uint32_t)0x00004000U) /* Bit[14] SHRTIM_TDRST2 register update enable. */ +#define SHRTIM_BDTDUPD_TDSET2 ((uint32_t)0x00002000U) /* Bit[13] SHRTIM_TDSET2 register update enable. */ +#define SHRTIM_BDTDUPD_TDRST1 ((uint32_t)0x00001000U) /* Bit[12] SHRTIM_TDRST1 register update enable. */ +#define SHRTIM_BDTDUPD_TDSET1 ((uint32_t)0x00000800U) /* Bit[11] SHRTIM_TDSET1 register update enable. */ +#define SHRTIM_BDTDUPD_TDDT ((uint32_t)0x00000400U) /* Bit[10] SHRTIM_TDDT register update enable. */ +#define SHRTIM_BDTDUPD_TDCMP4DAT ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_TDCMP4DAT register update enable. */ +#define SHRTIM_BDTDUPD_TDCMP3DAT ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_TDCMP3DAT register update enable. */ +#define SHRTIM_BDTDUPD_TDCMP2DAT ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_TDCMP2DAT register update enable. */ +#define SHRTIM_BDTDUPD_TDCMP1DAT ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_TDCMP1DAT register update enable. */ +#define SHRTIM_BDTDUPD_TDREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_TDREPT register update enable. */ +#define SHRTIM_BDTDUPD_TDPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_TDPRD register update enable. */ +#define SHRTIM_BDTDUPD_TDCNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_TDCNT register update enable. */ +#define SHRTIM_BDTDUPD_TDIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_TDIDEN register update enable. */ +#define SHRTIM_BDTDUPD_TDINTDLR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_TDINTDLR register update enable. */ +#define SHRTIM_BDTDUPD_TDCTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_TDCTRL register update enable. */ + +/** Bit definition for SHRTIM_BDTEUPD register **/ +#define SHRTIM_BDTEUPD_TEEXEVFLT3 ((uint32_t)0x00400000U) /* Bit[22] SHRTIM_TEEXEVFLT3 register update enable. */ +#define SHRTIM_BDTEUPD_TECTRL2 ((uint32_t)0x00200000U) /* Bit[21] SHRTIM_TECTRL2 register update enable. */ +#define SHRTIM_BDTEUPD_TEFALT ((uint32_t)0x00100000U) /* Bit[20] SHRTIM_TEFAULT register update enable. */ +#define SHRTIM_BDTEUPD_TEOUT ((uint32_t)0x00080000U) /* Bit[19] SHRTIM_TEOUT register update enable. */ +#define SHRTIM_BDTEUPD_TECHOP ((uint32_t)0x00040000U) /* Bit[18] SHRTIM_TECHOP register update enable. */ +#define SHRTIM_BDTEUPD_TECNTRST ((uint32_t)0x00020000U) /* Bit[17] SHRTIM_TECNTRST register update enable */ +#define SHRTIM_BDTEUPD_TEEXEVFLT2 ((uint32_t)0x00010000U) /* Bit[16] SHRTIM_TEEXEVFLT2 register update enable. */ +#define SHRTIM_BDTEUPD_TEEXEVFLT1 ((uint32_t)0x00008000U) /* Bit[15] SHRTIM_TEEXEVFLT1 register update enable. */ +#define SHRTIM_BDTEUPD_TERST2 ((uint32_t)0x00004000U) /* Bit[14] SHRTIM_TERST2 register update enable. */ +#define SHRTIM_BDTEUPD_TESET2 ((uint32_t)0x00002000U) /* Bit[13] SHRTIM_TESET2 register update enable. */ +#define SHRTIM_BDTEUPD_TERST1 ((uint32_t)0x00001000U) /* Bit[12] SHRTIM_TERST1 register update enable. */ +#define SHRTIM_BDTEUPD_TESET1 ((uint32_t)0x00000800U) /* Bit[11] SHRTIM_TESET1 register update enable. */ +#define SHRTIM_BDTEUPD_TEDT ((uint32_t)0x00000400U) /* Bit[10] SHRTIM_TEDT register update enable. */ +#define SHRTIM_BDTEUPD_TECMP4DAT ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_TECMP4DAT register update enable. */ +#define SHRTIM_BDTEUPD_TECMP3DAT ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_TECMP3DAT register update enable. */ +#define SHRTIM_BDTEUPD_TECMP2DAT ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_TECMP2DAT register update enable. */ +#define SHRTIM_BDTEUPD_TECMP1DAT ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_TECMP1DAT register update enable. */ +#define SHRTIM_BDTEUPD_TEREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_TEREPT register update enable. */ +#define SHRTIM_BDTEUPD_TEPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_TEPRD register update enable. */ +#define SHRTIM_BDTEUPD_TECNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_TECNT register update enable. */ +#define SHRTIM_BDTEUPD_TEIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_TEIDEN register update enable. */ +#define SHRTIM_BDTEUPD_TEINTELR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_TEINTELR register update enable. */ +#define SHRTIM_BDTEUPD_TECTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_TECTRL register update enable. */ + +/** Bit definition for SHRTIM_BDTFUPD register **/ +#define SHRTIM_BDTFUPD_TFEXEVFLT3 ((uint32_t)0x00400000U) /* Bit[22] SHRTIM_TFEXEVFLT3 register update enable. */ +#define SHRTIM_BDTFUPD_TFCTRL2 ((uint32_t)0x00200000U) /* Bit[21] SHRTIM_TFCTRL2 register update enable. */ +#define SHRTIM_BDTFUPD_TFFALT ((uint32_t)0x00100000U) /* Bit[20] SHRTIM_TFFAULT register update enable. */ +#define SHRTIM_BDTFUPD_TFOUT ((uint32_t)0x00080000U) /* Bit[19] SHRTIM_TFOUT register update enable. */ +#define SHRTIM_BDTFUPD_TFCHOP ((uint32_t)0x00040000U) /* Bit[18] SHRTIM_TFCHOP register update enable. */ +#define SHRTIM_BDTFUPD_TFCNTRST ((uint32_t)0x00020000U) /* Bit[17] SHRTIM_TFCNTRST register update enable */ +#define SHRTIM_BDTFUPD_TFEXEVFLT2 ((uint32_t)0x00010000U) /* Bit[16] SHRTIM_TFEXEVFLT2 register update enable. */ +#define SHRTIM_BDTFUPD_TFEXEVFLT1 ((uint32_t)0x00008000U) /* Bit[15] SHRTIM_TFEXEVFLT1 register update enable. */ +#define SHRTIM_BDTFUPD_TFRST2 ((uint32_t)0x00004000U) /* Bit[14] SHRTIM_TFRST2 register update enable. */ +#define SHRTIM_BDTFUPD_TFSET2 ((uint32_t)0x00002000U) /* Bit[13] SHRTIM_TFSET2 register update enable. */ +#define SHRTIM_BDTFUPD_TFRST1 ((uint32_t)0x00001000U) /* Bit[12] SHRTIM_TFRST1 register update enable. */ +#define SHRTIM_BDTFUPD_TFSET1 ((uint32_t)0x00000800U) /* Bit[11] SHRTIM_TFSET1 register update enable. */ +#define SHRTIM_BDTFUPD_TFDT ((uint32_t)0x00000400U) /* Bit[10] SHRTIM_TFDT register update enable. */ +#define SHRTIM_BDTFUPD_TFCMP4DAT ((uint32_t)0x00000200U) /* Bit[9] SHRTIM_TFCMP4DAT register update enable. */ +#define SHRTIM_BDTFUPD_TFCMP3DAT ((uint32_t)0x00000100U) /* Bit[8] SHRTIM_TFCMP3DAT register update enable. */ +#define SHRTIM_BDTFUPD_TFCMP2DAT ((uint32_t)0x00000080U) /* Bit[7] SHRTIM_TFCMP2DAT register update enable. */ +#define SHRTIM_BDTFUPD_TFCMP1DAT ((uint32_t)0x00000040U) /* Bit[6] SHRTIM_TFCMP1DAT register update enable. */ +#define SHRTIM_BDTFUPD_TFREPT ((uint32_t)0x00000020U) /* Bit[5] SHRTIM_TFREPT register update enable. */ +#define SHRTIM_BDTFUPD_TFPRD ((uint32_t)0x00000010U) /* Bit[4] SHRTIM_TFPRD register update enable. */ +#define SHRTIM_BDTFUPD_TFCNT ((uint32_t)0x00000008U) /* Bit[3] SHRTIM_TFCNT register update enable. */ +#define SHRTIM_BDTFUPD_TFIDEN ((uint32_t)0x00000004U) /* Bit[2] SHRTIM_TFIDEN register update enable. */ +#define SHRTIM_BDTFUPD_TFINTFLR ((uint32_t)0x00000002U) /* Bit[1] SHRTIM_TFINTFLR register update enable. */ +#define SHRTIM_BDTFUPD_TFCTRL ((uint32_t)0x00000001U) /* Bit[0] SHRTIM_TFCTRL register update enable. */ + +/** Bit definition for SHRTIM_BDDAT register **/ +#define SHRTIM_BDDAT_BDMADATA ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Burst DMA data register */ +#define SHRTIM_BDDAT_BDMADATA_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_BDDAT_BDMADATA_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_BDDAT_BDMADATA_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_BDDAT_BDMADATA_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_BDDAT_BDMADATA_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_BDDAT_BDMADATA_5 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_BDDAT_BDMADATA_6 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_BDDAT_BDMADATA_7 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_BDDAT_BDMADATA_8 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_BDDAT_BDMADATA_9 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_BDDAT_BDMADATA_10 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_BDDAT_BDMADATA_11 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_BDDAT_BDMADATA_12 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_BDDAT_BDMADATA_13 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_BDDAT_BDMADATA_14 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_BDDAT_BDMADATA_15 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_BDDAT_BDMADATA_16 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_BDDAT_BDMADATA_17 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_BDDAT_BDMADATA_18 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_BDDAT_BDMADATA_19 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_BDDAT_BDMADATA_20 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_BDDAT_BDMADATA_21 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_BDDAT_BDMADATA_22 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_BDDAT_BDMADATA_23 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_BDDAT_BDMADATA_24 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_BDDAT_BDMADATA_25 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_BDDAT_BDMADATA_26 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_BDDAT_BDMADATA_27 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_BDDAT_BDMADATA_28 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_BDDAT_BDMADATA_29 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_BDDAT_BDMADATA_30 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_BDDAT_BDMADATA_31 ((uint32_t)0x80000000U) /* Bit31 */ + +/** Bit definition for SHRTIM_ADTGEX1 register **/ +#define SHRTIM_ADTGEX1_ADTG9SRC ((uint32_t)0x003F0000U) /* Bit[21:16] Description */ +#define SHRTIM_ADTGEX1_ADTG9SRC_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_ADTGEX1_ADTG9SRC_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_ADTGEX1_ADTG9SRC_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_ADTGEX1_ADTG9SRC_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_ADTGEX1_ADTG9SRC_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_ADTGEX1_ADTG9SRC_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_ADTGEX1_ADTG7SRC ((uint32_t)0x00003F00U) /* Bit[13:8] Description */ +#define SHRTIM_ADTGEX1_ADTG7SRC_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_ADTGEX1_ADTG7SRC_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_ADTGEX1_ADTG7SRC_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_ADTGEX1_ADTG7SRC_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_ADTGEX1_ADTG7SRC_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_ADTGEX1_ADTG7SRC_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_ADTGEX1_ADTG5SRC ((uint32_t)0x0000003FU) /* Bit[5:0] Trigger on master compare 1 */ +#define SHRTIM_ADTGEX1_ADTG5SRC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_ADTGEX1_ADTG5SRC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_ADTGEX1_ADTG5SRC_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_ADTGEX1_ADTG5SRC_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_ADTGEX1_ADTG5SRC_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_ADTGEX1_ADTG5SRC_5 ((uint32_t)0x00000020U) /* Bit5 */ + +/** Bit definition for SHRTIM_ADTGEX2 register **/ +#define SHRTIM_ADTGEX2_ADTG10SRC ((uint32_t)0x003F0000U) /* Bit[21:16] Description */ +#define SHRTIM_ADTGEX2_ADTG10SRC_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_ADTGEX2_ADTG10SRC_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_ADTGEX2_ADTG10SRC_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_ADTGEX2_ADTG10SRC_3 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_ADTGEX2_ADTG10SRC_4 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_ADTGEX2_ADTG10SRC_5 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_ADTGEX2_ADTG8SRC ((uint32_t)0x00003F00U) /* Bit[13:8] Description */ +#define SHRTIM_ADTGEX2_ADTG8SRC_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_ADTGEX2_ADTG8SRC_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_ADTGEX2_ADTG8SRC_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_ADTGEX2_ADTG8SRC_3 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_ADTGEX2_ADTG8SRC_4 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_ADTGEX2_ADTG8SRC_5 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_ADTGEX2_ADTG6SRC ((uint32_t)0x0000003FU) /* Bit[5:0] Trigger on master compare 1 */ +#define SHRTIM_ADTGEX2_ADTG6SRC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_ADTGEX2_ADTG6SRC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_ADTGEX2_ADTG6SRC_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_ADTGEX2_ADTG6SRC_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_ADTGEX2_ADTG6SRC_4 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_ADTGEX2_ADTG6SRC_5 ((uint32_t)0x00000020U) /* Bit5 */ + +/** Bit definition for SHRTIM_ADTGUPD register **/ +#define SHRTIM_ADTGUPD_ADTG10UPDSRC ((uint32_t)0x00700000U) /* Bit[22:20] ADC trigger 10 update source */ +#define SHRTIM_ADTGUPD_ADTG10UPDSRC_0 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_ADTGUPD_ADTG10UPDSRC_1 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_ADTGUPD_ADTG10UPDSRC_2 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_ADTGUPD_ADTG9UPDSRC ((uint32_t)0x00070000U) /* Bit[18:16] ADC trigger 9 update source */ +#define SHRTIM_ADTGUPD_ADTG9UPDSRC_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_ADTGUPD_ADTG9UPDSRC_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_ADTGUPD_ADTG9UPDSRC_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_ADTGUPD_ADTG8UPDSRC ((uint32_t)0x00007000U) /* Bit[14:12] ADC trigger 8 update source */ +#define SHRTIM_ADTGUPD_ADTG8UPDSRC_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_ADTGUPD_ADTG8UPDSRC_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_ADTGUPD_ADTG8UPDSRC_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_ADTGUPD_ADTG7UPDSRC ((uint32_t)0x00000700U) /* Bit[10:8] ADC trigger 7 update source */ +#define SHRTIM_ADTGUPD_ADTG7UPDSRC_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_ADTGUPD_ADTG7UPDSRC_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_ADTGUPD_ADTG7UPDSRC_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_ADTGUPD_ADTG6UPDSRC ((uint32_t)0x00000070U) /* Bit[6:4] ADC trigger 6 update source */ +#define SHRTIM_ADTGUPD_ADTG6UPDSRC_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_ADTGUPD_ADTG6UPDSRC_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_ADTGUPD_ADTG6UPDSRC_2 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_ADTGUPD_ADTG5UPDSRC ((uint32_t)0x00000007U) /* Bit[2:0] ADC trigger 5 update source */ +#define SHRTIM_ADTGUPD_ADTG5UPDSRC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_ADTGUPD_ADTG5UPDSRC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_ADTGUPD_ADTG5UPDSRC_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for SHRTIM_ADCPSC1 register **/ +#define SHRTIM_ADCPSC1_ADC5PSC ((uint32_t)0x1F000000U) /* Bit[28:24] ADC trigger 5 post scaler */ +#define SHRTIM_ADCPSC1_ADC5PSC_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_ADCPSC1_ADC5PSC_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_ADCPSC1_ADC5PSC_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_ADCPSC1_ADC5PSC_3 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_ADCPSC1_ADC5PSC_4 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_ADCPSC1_ADC4PSC ((uint32_t)0x007C0000U) /* Bit[22:18] ADC trigger 4 post scaler */ +#define SHRTIM_ADCPSC1_ADC4PSC_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_ADCPSC1_ADC4PSC_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_ADCPSC1_ADC4PSC_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_ADCPSC1_ADC4PSC_3 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_ADCPSC1_ADC4PSC_4 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_ADCPSC1_ADC3PSC ((uint32_t)0x0001F000U) /* Bit[16:12] ADC trigger 3 post scaler */ +#define SHRTIM_ADCPSC1_ADC3PSC_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_ADCPSC1_ADC3PSC_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_ADCPSC1_ADC3PSC_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_ADCPSC1_ADC3PSC_3 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_ADCPSC1_ADC3PSC_4 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_ADCPSC1_ADC2PSC ((uint32_t)0x000007C0U) /* Bit[10:6] ADC trigger 2 post scaler */ +#define SHRTIM_ADCPSC1_ADC2PSC_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_ADCPSC1_ADC2PSC_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_ADCPSC1_ADC2PSC_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_ADCPSC1_ADC2PSC_3 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_ADCPSC1_ADC2PSC_4 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_ADCPSC1_ADC1PSC ((uint32_t)0x0000001FU) /* Bit[4:0] ADC trigger 1 post scaler */ +#define SHRTIM_ADCPSC1_ADC1PSC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_ADCPSC1_ADC1PSC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_ADCPSC1_ADC1PSC_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_ADCPSC1_ADC1PSC_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_ADCPSC1_ADC1PSC_4 ((uint32_t)0x00000010U) /* Bit4 */ + +/** Bit definition for SHRTIM_ADCPSC2 register **/ +#define SHRTIM_ADCPSC2_ADC10PSC ((uint32_t)0x1F000000U) /* Bit[28:24] ADC trigger 10 post scaler */ +#define SHRTIM_ADCPSC2_ADC10PSC_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_ADCPSC2_ADC10PSC_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_ADCPSC2_ADC10PSC_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_ADCPSC2_ADC10PSC_3 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_ADCPSC2_ADC10PSC_4 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_ADCPSC2_ADC9PSC ((uint32_t)0x007C0000U) /* Bit[22:18] ADC trigger 9 post scaler */ +#define SHRTIM_ADCPSC2_ADC9PSC_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_ADCPSC2_ADC9PSC_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_ADCPSC2_ADC9PSC_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_ADCPSC2_ADC9PSC_3 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_ADCPSC2_ADC9PSC_4 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_ADCPSC2_ADC8PSC ((uint32_t)0x0001F000U) /* Bit[16:12] ADC trigger 8 post scaler */ +#define SHRTIM_ADCPSC2_ADC8PSC_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_ADCPSC2_ADC8PSC_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_ADCPSC2_ADC8PSC_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_ADCPSC2_ADC8PSC_3 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_ADCPSC2_ADC8PSC_4 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_ADCPSC2_ADC7PSC ((uint32_t)0x000007C0U) /* Bit[10:6] ADC trigger 7 post scaler */ +#define SHRTIM_ADCPSC2_ADC7PSC_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_ADCPSC2_ADC7PSC_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_ADCPSC2_ADC7PSC_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_ADCPSC2_ADC7PSC_3 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_ADCPSC2_ADC7PSC_4 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_ADCPSC2_ADC6PSC ((uint32_t)0x0000001FU) /* Bit[4:0] ADC trigger 6 post scaler */ +#define SHRTIM_ADCPSC2_ADC6PSC_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_ADCPSC2_ADC6PSC_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_ADCPSC2_ADC6PSC_2 ((uint32_t)0x00000004U) /* Bit2 */ +#define SHRTIM_ADCPSC2_ADC6PSC_3 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_ADCPSC2_ADC6PSC_4 ((uint32_t)0x00000010U) /* Bit4 */ + +/** Bit definition for SHRTIM_SFTFALT register **/ +#define SHRTIM_SFTFALT_SFTFALT6 ((uint32_t)0x00000020U) /* Bit[5] Software fault 6 */ +#define SHRTIM_SFTFALT_SFTFALT5 ((uint32_t)0x00000010U) /* Bit[4] Software fault 5 */ +#define SHRTIM_SFTFALT_SFTFALT4 ((uint32_t)0x00000008U) /* Bit[3] Software fault 4 */ +#define SHRTIM_SFTFALT_SFTFALT3 ((uint32_t)0x00000004U) /* Bit[2] Software fault 3 */ +#define SHRTIM_SFTFALT_SFTFALT2 ((uint32_t)0x00000002U) /* Bit[1] Software fault 2 */ +#define SHRTIM_SFTFALT_SFTFALT1 ((uint32_t)0x00000001U) /* Bit[0] Software fault 1 */ + +/** Bit definition for SHRTIM_SFTDP register **/ +#define SHRTIM_SFTDP_SFTDPF2 ((uint32_t)0x00000800U) /* Bit[11] Software delay protection F for channel 2 */ +#define SHRTIM_SFTDP_SFTDPE2 ((uint32_t)0x00000400U) /* Bit[10] Software delay protection E for channel 2 */ +#define SHRTIM_SFTDP_SFTDPD2 ((uint32_t)0x00000200U) /* Bit[9] Software delay protection D for channel 2 */ +#define SHRTIM_SFTDP_SFTDPC2 ((uint32_t)0x00000100U) /* Bit[8] Software delay protection C for channel 2 */ +#define SHRTIM_SFTDP_SFTDPB2 ((uint32_t)0x00000080U) /* Bit[7] Software delay protection B for channel 2 */ +#define SHRTIM_SFTDP_SFTDPA2 ((uint32_t)0x00000040U) /* Bit[6] Software delay protection A for channel 2 */ +#define SHRTIM_SFTDP_SFTDPF1 ((uint32_t)0x00000020U) /* Bit[5] Software delay protection F for channel 1 */ +#define SHRTIM_SFTDP_SFTDPE1 ((uint32_t)0x00000010U) /* Bit[4] Software delay protection E for channel 1 */ +#define SHRTIM_SFTDP_SFTDPD1 ((uint32_t)0x00000008U) /* Bit[3] Software delay protection D for channel 1 */ +#define SHRTIM_SFTDP_SFTDPC1 ((uint32_t)0x00000004U) /* Bit[2] Software delay protection C for channel 1 */ +#define SHRTIM_SFTDP_SFTDPB1 ((uint32_t)0x00000002U) /* Bit[1] Software delay protection B for channel 1 */ +#define SHRTIM_SFTDP_SFTDPA1 ((uint32_t)0x00000001U) /* Bit[0] Software delay protection A for channel 1 */ + +/** Bit definition for SHRTIM_FALTIN5 register **/ +#define SHRTIM_FALTIN5_FALT6CSEL ((uint32_t)0x00700000U) /* Bit[22:20] Analog comp x sellect for fault 6 */ +#define SHRTIM_FALTIN5_FALT6CSEL_0 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_FALTIN5_FALT6CSEL_1 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_FALTIN5_FALT6CSEL_2 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_FALTIN5_FALT5CSEL ((uint32_t)0x00070000U) /* Bit[18:16] Analog comp x sellect for fault5 */ +#define SHRTIM_FALTIN5_FALT5CSEL_0 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_FALTIN5_FALT5CSEL_1 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_FALTIN5_FALT5CSEL_2 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_FALTIN5_FALT4CSEL ((uint32_t)0x00007000U) /* Bit[14:12] Analog comp x sellect for fault 4 */ +#define SHRTIM_FALTIN5_FALT4CSEL_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_FALTIN5_FALT4CSEL_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_FALTIN5_FALT4CSEL_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_FALTIN5_FALT3CSEL ((uint32_t)0x00000700U) /* Bit[10:8] Analog comp x sellect for fault3 */ +#define SHRTIM_FALTIN5_FALT3CSEL_0 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_FALTIN5_FALT3CSEL_1 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_FALTIN5_FALT3CSEL_2 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_FALTIN5_FALT2CSEL ((uint32_t)0x00000070U) /* Bit[6:4] Analog comp x sellect for fault2 */ +#define SHRTIM_FALTIN5_FALT2CSEL_0 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_FALTIN5_FALT2CSEL_1 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_FALTIN5_FALT2CSEL_2 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_FALTIN5_FALT1CSEL ((uint32_t)0x00000007U) /* Bit[2:0] Analog comp x sellect for fault1 */ +#define SHRTIM_FALTIN5_FALT1CSEL_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_FALTIN5_FALT1CSEL_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_FALTIN5_FALT1CSEL_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/** Bit definition for SHRTIM_EXEVCTRL5 register **/ +#define SHRTIM_EXEVCTRL5_EXEV10CSEL ((uint32_t)0x38000000U) /* Bit[29:27] Analog comp x sellect for external event 10 */ +#define SHRTIM_EXEVCTRL5_EXEV10CSEL_0 ((uint32_t)0x08000000U) /* Bit27 */ +#define SHRTIM_EXEVCTRL5_EXEV10CSEL_1 ((uint32_t)0x10000000U) /* Bit28 */ +#define SHRTIM_EXEVCTRL5_EXEV10CSEL_2 ((uint32_t)0x20000000U) /* Bit29 */ +#define SHRTIM_EXEVCTRL5_EXEV9CSEL ((uint32_t)0x07000000U) /* Bit[26:24] Analog comp x sellect for external event 9 */ +#define SHRTIM_EXEVCTRL5_EXEV9CSEL_0 ((uint32_t)0x01000000U) /* Bit24 */ +#define SHRTIM_EXEVCTRL5_EXEV9CSEL_1 ((uint32_t)0x02000000U) /* Bit25 */ +#define SHRTIM_EXEVCTRL5_EXEV9CSEL_2 ((uint32_t)0x04000000U) /* Bit26 */ +#define SHRTIM_EXEVCTRL5_EXEV8CSEL ((uint32_t)0x00E00000U) /* Bit[23:21] Analog comp x sellect for external event 8 */ +#define SHRTIM_EXEVCTRL5_EXEV8CSEL_0 ((uint32_t)0x00200000U) /* Bit21 */ +#define SHRTIM_EXEVCTRL5_EXEV8CSEL_1 ((uint32_t)0x00400000U) /* Bit22 */ +#define SHRTIM_EXEVCTRL5_EXEV8CSEL_2 ((uint32_t)0x00800000U) /* Bit23 */ +#define SHRTIM_EXEVCTRL5_EXEV7CSEL ((uint32_t)0x001C0000U) /* Bit[20:18] Analog comp x sellect for external event 7 */ +#define SHRTIM_EXEVCTRL5_EXEV7CSEL_0 ((uint32_t)0x00040000U) /* Bit18 */ +#define SHRTIM_EXEVCTRL5_EXEV7CSEL_1 ((uint32_t)0x00080000U) /* Bit19 */ +#define SHRTIM_EXEVCTRL5_EXEV7CSEL_2 ((uint32_t)0x00100000U) /* Bit20 */ +#define SHRTIM_EXEVCTRL5_EXEV6CSEL ((uint32_t)0x00038000U) /* Bit[17:15] Analog comp x sellect for external event 6 */ +#define SHRTIM_EXEVCTRL5_EXEV6CSEL_0 ((uint32_t)0x00008000U) /* Bit15 */ +#define SHRTIM_EXEVCTRL5_EXEV6CSEL_1 ((uint32_t)0x00010000U) /* Bit16 */ +#define SHRTIM_EXEVCTRL5_EXEV6CSEL_2 ((uint32_t)0x00020000U) /* Bit17 */ +#define SHRTIM_EXEVCTRL5_EXEV5CSEL ((uint32_t)0x00007000U) /* Bit[14:12] Analog comp x sellect for external event 5 */ +#define SHRTIM_EXEVCTRL5_EXEV5CSEL_0 ((uint32_t)0x00001000U) /* Bit12 */ +#define SHRTIM_EXEVCTRL5_EXEV5CSEL_1 ((uint32_t)0x00002000U) /* Bit13 */ +#define SHRTIM_EXEVCTRL5_EXEV5CSEL_2 ((uint32_t)0x00004000U) /* Bit14 */ +#define SHRTIM_EXEVCTRL5_EXEV4CSEL ((uint32_t)0x00000E00U) /* Bit[11:9] Analog comp x sellect for external event 4 */ +#define SHRTIM_EXEVCTRL5_EXEV4CSEL_0 ((uint32_t)0x00000200U) /* Bit9 */ +#define SHRTIM_EXEVCTRL5_EXEV4CSEL_1 ((uint32_t)0x00000400U) /* Bit10 */ +#define SHRTIM_EXEVCTRL5_EXEV4CSEL_2 ((uint32_t)0x00000800U) /* Bit11 */ +#define SHRTIM_EXEVCTRL5_EXEV3CSEL ((uint32_t)0x000001C0U) /* Bit[8:6] Analog comp x sellect for external event 3 */ +#define SHRTIM_EXEVCTRL5_EXEV3CSEL_0 ((uint32_t)0x00000040U) /* Bit6 */ +#define SHRTIM_EXEVCTRL5_EXEV3CSEL_1 ((uint32_t)0x00000080U) /* Bit7 */ +#define SHRTIM_EXEVCTRL5_EXEV3CSEL_2 ((uint32_t)0x00000100U) /* Bit8 */ +#define SHRTIM_EXEVCTRL5_EXEV2CSEL ((uint32_t)0x00000038U) /* Bit[5:3] Analog comp x sellect for external event 2 */ +#define SHRTIM_EXEVCTRL5_EXEV2CSEL_0 ((uint32_t)0x00000008U) /* Bit3 */ +#define SHRTIM_EXEVCTRL5_EXEV2CSEL_1 ((uint32_t)0x00000010U) /* Bit4 */ +#define SHRTIM_EXEVCTRL5_EXEV2CSEL_2 ((uint32_t)0x00000020U) /* Bit5 */ +#define SHRTIM_EXEVCTRL5_EXEV1CSEL ((uint32_t)0x00000007U) /* Bit[2:0] Analog comp x sellect for external event 1 */ +#define SHRTIM_EXEVCTRL5_EXEV1CSEL_0 ((uint32_t)0x00000001U) /* Bit0 */ +#define SHRTIM_EXEVCTRL5_EXEV1CSEL_1 ((uint32_t)0x00000002U) /* Bit1 */ +#define SHRTIM_EXEVCTRL5_EXEV1CSEL_2 ((uint32_t)0x00000004U) /* Bit2 */ + +/* Bit definition for SHRTIM_EXTEND register */ +#define SHRTIM_EXTEND_AUXBYPA ((uint32_t)0xC0000000U) /* Bit[31:30] Auxiliary output bypass */ +#define SHRTIM_EXTEND_AUXBYPA_0 ((uint32_t)0x40000000U) /* Bit30 */ +#define SHRTIM_EXTEND_AUXBYPA_1 ((uint32_t)0x80000000U) /* Bit31 */ + +/*** Low-Power Timer ***/ + +/** Bit definition for LPTIM_INTSTS register **/ +#define LPTIM_INTSTS_CMPM ((uint32_t)0x00000001U) /* Compare match */ +#define LPTIM_INTSTS_ARRM ((uint32_t)0x00000002U) /* Autoreload match */ +#define LPTIM_INTSTS_EXTRIG ((uint32_t)0x00000004U) /* External trigger edge event */ +#define LPTIM_INTSTS_CMPUPD ((uint32_t)0x00000008U) /* Compare register update OK */ +#define LPTIM_INTSTS_ARRUPD ((uint32_t)0x00000010U) /* Autoreload register update OK */ +#define LPTIM_INTSTS_UP ((uint32_t)0x00000020U) /* Counter direction change down to up */ +#define LPTIM_INTSTS_DOWN ((uint32_t)0x00000040U) /* Counter direction change up to down */ + +/** Bit definition for LPTIM_INTCLR register **/ +#define LPTIM_INTCLR_CMPMCF ((uint32_t)0x00000001U) /* Compare match Clear Flag */ +#define LPTIM_INTCLR_ARRMCF ((uint32_t)0x00000002U) /* Autoreload match Clear Flag */ +#define LPTIM_INTCLR_EXTRIGCF ((uint32_t)0x00000004U) /* External trigger edge event Clear Flag */ +#define LPTIM_INTCLR_CMPUPDCF ((uint32_t)0x00000008U) /* Compare register update OK Clear Flag */ +#define LPTIM_INTCLR_ARRUPDCF ((uint32_t)0x00000010U) /* Autoreload register update OK Clear Flag */ +#define LPTIM_INTCLR_UPCF ((uint32_t)0x00000020U) /* Counter direction change down to up Clear Flag */ +#define LPTIM_INTCLR_DOWNCF ((uint32_t)0x00000040U) /* Counter direction change up to down Clear Flag */ + +/** Bit definition for LPTIM_INTEN register **/ +#define LPTIM_INTEN_CMPMIE ((uint32_t)0x00000001U) /* Compare match Interrupt Enable */ +#define LPTIM_INTEN_ARRMIE ((uint32_t)0x00000002U) /* Autoreload match Interrupt Enable */ +#define LPTIM_INTEN_EXTRIGIE ((uint32_t)0x00000004U) /* External trigger edge event Interrupt Enable */ +#define LPTIM_INTEN_CMPUPDIE ((uint32_t)0x00000008U) /* Compare register update OK Interrupt Enable */ +#define LPTIM_INTEN_ARRUPDIE ((uint32_t)0x00000010U) /* Autoreload register update OK Interrupt Enable */ +#define LPTIM_INTEN_UPIE ((uint32_t)0x00000020U) /* Counter direction change down to up Interrupt Enable */ +#define LPTIM_INTEN_DOWNIE ((uint32_t)0x00000040U) /* Counter direction change up to down Interrupt Enable */ + +/** Bit definition for LPTIM_CFG register **/ +#define LPTIM_CFG_CLKSEL ((uint32_t)0x00000001U) /* Clock selector */ + +#define LPTIM_CFG_CLKPOL ((uint32_t)0x00000006U) /* CLKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFG_CLKPOL_0 ((uint32_t)0x00000002U) /* CLKPOL bit 0 */ +#define LPTIM_CFG_CLKPOL_1 ((uint32_t)0x00000004U) /* CLKPOL bit 1 */ + +#define LPTIM_CFG_CLKFLT ((uint32_t)0x00000018U) /* CLKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFG_CLKFLT_0 ((uint32_t)0x00000008U) /* CLKFLT bit 0 */ +#define LPTIM_CFG_CLKFLT_1 ((uint32_t)0x00000010U) /* CLKFLT bit 1 */ + +#define LPTIM_CFG_TRIGFLT ((uint32_t)0x000000C0U) /* TRIGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFG_TRIGFLT_0 ((uint32_t)0x00000040U) /* TRIGFLT bit 0 */ +#define LPTIM_CFG_TRIGFLT_1 ((uint32_t)0x00000080U) /* TRIGFLT bit 1 */ + +#define LPTIM_CFG_CLKPRE ((uint32_t)0x00000E00U) /* CLKPRE[2:0] bits (Clock prescaler) */ +#define LPTIM_CFG_CLKPRE_0 ((uint32_t)0x00000200U) /* CLKPRE bit 0 */ +#define LPTIM_CFG_CLKPRE_1 ((uint32_t)0x00000400U) /* CLKPRE bit 1 */ +#define LPTIM_CFG_CLKPRE_2 ((uint32_t)0x00000800U) /* CLKPRE bit 2 */ + +#define LPTIM_CFG_TRGSEL ((uint32_t)0x0001E000U) /* TRGSEL[3:0]] bits (Trigger selector) */ +#define LPTIM_CFG_TRGSEL_0 ((uint32_t)0x00002000U) /* TRGSEL bit 0 */ +#define LPTIM_CFG_TRGSEL_1 ((uint32_t)0x00004000U) /* TRGSEL bit 1 */ +#define LPTIM_CFG_TRGSEL_2 ((uint32_t)0x00008000U) /* TRGSEL bit 2 */ +#define LPTIM_CFG_TRGSEL_3 ((uint32_t)0x00010000U) /* TRGSEL bit 3 */ + +#define LPTIM_CFG_TRGEN ((uint32_t)0x00060000U) /* TRGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFG_TRGEN_0 ((uint32_t)0x00020000U) /* TRGEN bit 0 */ +#define LPTIM_CFG_TRGEN_1 ((uint32_t)0x00040000U) /* TRGEN bit 1 */ + +#define LPTIM_CFG_TIMOUTEN ((uint32_t)0x00080000U) /* Timout enable */ +#define LPTIM_CFG_WAVE ((uint32_t)0x00100000U) /* Waveform shape */ +#define LPTIM_CFG_WAVEPOL ((uint32_t)0x00200000U) /* Waveform shape polarity */ +#define LPTIM_CFG_RELOAD ((uint32_t)0x00400000U) /* Reg update mode */ +#define LPTIM_CFG_CNTMEN ((uint32_t)0x00800000U) /* Counter mode enable */ +#define LPTIM_CFG_ENC ((uint32_t)0x01000000U) /* Encoder mode enable */ +#define LPTIM_CFG_NENC ((uint32_t)0x02000000U) /* NONEncoder mode enable */ + +/** Bit definition for LPTIM_CTRL register **/ +#define LPTIM_CTRL_LPTIMEN ((uint32_t)0x00000001U) /* LPTIMer enable */ +#define LPTIM_CTRL_SNGMST ((uint32_t)0x00000002U) /* Timer start in single mode */ +#define LPTIM_CTRL_TSTCM ((uint32_t)0x00000004U) /* Timer start in continuous mode */ + +/** Bit definition for LPTIM_CMP register **/ +#define LPTIM_CMP_CMPVAL ((uint16_t)0xFFFFU) /* Compare register */ + +/** Bit definition for LPTIM_ARR register **/ +#define LPTIM_ARR_ARRVAL ((uint16_t)0xFFFFU) /* Auto reload register */ + +/** Bit definition for LPTIM_CNT register **/ +#define LPTIM_CNT_CNTVAL ((uint16_t)0xFFFFU) /* Counter register */ + +/** Bit definition for LPTIM_OPT register **/ +#define LPTIM_OPT_OPT1 ((uint32_t)0x00000007U) /* OPT1[2:0]] bits (LPTIM input1 connection option bits) */ +#define LPTIM_OPT_OPT1_0 ((uint32_t)0x00000001U) /* OPT1 bit 0 */ +#define LPTIM_OPT_OPT1_1 ((uint32_t)0x00000002U) /* OPT1 bit 1 */ +#define LPTIM_OPT_OPT1_2 ((uint32_t)0x00000004U) /* OPT1 bit 2 */ +#define LPTIM_OPT_OPT2 ((uint32_t)0x00000038U) /* OPT2[2:0]] bits (LPTIM input2 connection option bits) */ +#define LPTIM_OPT_OPT2_0 ((uint32_t)0x00000008U) /* OPT2 bit 0 */ +#define LPTIM_OPT_OPT2_1 ((uint32_t)0x00000010U) /* OPT2 bit 1 */ +#define LPTIM_OPT_OPT2_2 ((uint32_t)0x00000020U) /* OPT2 bit 2 */ + + +/******** Bit definition for XSPI_CTRL0 register ********/ +#define XSPI_CTRL0_MST ((uint32_t)0x80000000U) /* Bit[31] */ +#define XSPI_CTRL0_MST_MASTER ((uint32_t)0x80000000U) +#define XSPI_CTRL0_MST_SLAVE ((uint32_t)0x00000000U) +#define XSPI_CTRL0_DWSEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define XSPI_CTRL0_SPIHYPEEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define XSPI_CTRL0_SPIFRF ((uint32_t)0x00C00000U) /* Bit[23:22] */ +#define XSPI_CTRL0_SPIFRF_0 ((uint32_t)0x00400000U) /* Bit22*/ +#define XSPI_CTRL0_SPIFRF_1 ((uint32_t)0x00800000U) /* Bit23*/ +#define XSPI_CTRL0_SPIFRF_STANDARD_FORMAT ((uint32_t)0x00000000U) +#define XSPI_CTRL0_SPIFRF_DUAL_FORMAT ((uint32_t)0x00400000U) +#define XSPI_CTRL0_SPIFRF_QUAD_FORMAT ((uint32_t)0x00800000U) +#define XSPI_CTRL0_SPIFRF_OCTAL_FORMAT ((uint32_t)0x00C00000U) + +#define XSPI_CTRL0_CFS ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define XSPI_CTRL0_CFS_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_CTRL0_CFS_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_CTRL0_CFS_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_CTRL0_CFS_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_CTRL0_CFS_1_BIT ((uint32_t)0x00000000U) +#define XSPI_CTRL0_CFS_2_BIT ((uint32_t)0x00010000U) +#define XSPI_CTRL0_CFS_3_BIT ((uint32_t)0x00020000U) +#define XSPI_CTRL0_CFS_4_BIT ((uint32_t)0x00030000U) +#define XSPI_CTRL0_CFS_5_BIT ((uint32_t)0x00040000U) +#define XSPI_CTRL0_CFS_6_BIT ((uint32_t)0x00050000U) +#define XSPI_CTRL0_CFS_7_BIT ((uint32_t)0x00060000U) +#define XSPI_CTRL0_CFS_8_BIT ((uint32_t)0x00070000U) +#define XSPI_CTRL0_CFS_9_BIT ((uint32_t)0x00080000U) +#define XSPI_CTRL0_CFS_10_BIT ((uint32_t)0x00090000U) +#define XSPI_CTRL0_CFS_11_BIT ((uint32_t)0x000A0000U) +#define XSPI_CTRL0_CFS_12_BIT ((uint32_t)0x000B0000U) +#define XSPI_CTRL0_CFS_13_BIT ((uint32_t)0x000C0000U) +#define XSPI_CTRL0_CFS_14_BIT ((uint32_t)0x000D0000U) +#define XSPI_CTRL0_CFS_15_BIT ((uint32_t)0x000E0000U) +#define XSPI_CTRL0_CFS_16_BIT ((uint32_t)0x000F0000U) + +#define XSPI_CTRL0_SSTE ((uint32_t)0x00004000U) /* Bit[14] */ +#define XSPI_CTRL0_SSTE_EN ((uint32_t)0x00004000U) /* SSTE(Slave Select Toggle Enable) */ +#define XSPI_CTRL0_SSTE_DISABLE ((uint32_t)0x00000000U) +#define XSPI_CTRL0_SRL ((uint32_t)0x00002000U) /* Bit[13] */ +#define XSPI_CTRL0_SRL_EN ((uint32_t)0x00002000U) /* SRL (Shift Register Loop) */ +#define XSPI_CTRL0_SLVOE ((uint32_t)0x00001000U) /* Bit[12] */ + +#define XSPI_CTRL0_TMOD ((uint32_t)0x00000C00U) /* Bit[11:10] */ +#define XSPI_CTRL0_TMOD_0 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_CTRL0_TMOD_1 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_CTRL0_TMOD_TX_AND_RX ((uint32_t)0x00000000U) +#define XSPI_CTRL0_TMOD_TX_ONLY ((uint32_t)0x00000400U) +#define XSPI_CTRL0_TMOD_RX_ONLY ((uint32_t)0x00000800U) +#define XSPI_CTRL0_TMOD_EEPROM_READ ((uint32_t)0x00000C00U) + +#define XSPI_CTRL0_SCPOL ((uint32_t)0x00000200U) /* Bit[9] */ +#define XSPI_CTRL0_SCPOL_LOW ((uint32_t)0x00000000U) +#define XSPI_CTRL0_SCPOL_HIGH ((uint32_t)0x00000200U) + +#define XSPI_CTRL0_SCPH ((uint32_t)0x00000100U) /* Bit[8] */ +#define XSPI_CTRL0_SCPH_FIRST_EDGE ((uint32_t)0x00000000U) +#define XSPI_CTRL0_SCPH_SECOND_EDGE ((uint32_t)0x00000100U) + +#define XSPI_CTRL0_FRF ((uint32_t)0x000000C0U) /* Bit[7:6] */ +#define XSPI_CTRL0_FRF_0 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_CTRL0_FRF_1 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_CTRL0_FRF_MOTOROLA ((uint32_t)0x00000000U) +#define XSPI_CTRL0_FRF_TI ((uint32_t)0x00000040U) +#define XSPI_CTRL0_FRF_MICROWIRE ((uint32_t)0x00000080U) + +#define XSPI_CTRL0_DFS ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define XSPI_CTRL0_DFS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_CTRL0_DFS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_CTRL0_DFS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_CTRL0_DFS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_CTRL0_DFS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_CTRL0_DFS_4_BIT ((uint32_t)0x00000003U) +#define XSPI_CTRL0_DFS_5_BIT ((uint32_t)0x00000004U) +#define XSPI_CTRL0_DFS_6_BIT ((uint32_t)0x00000005U) +#define XSPI_CTRL0_DFS_7_BIT ((uint32_t)0x00000006U) +#define XSPI_CTRL0_DFS_8_BIT ((uint32_t)0x00000007U) +#define XSPI_CTRL0_DFS_9_BIT ((uint32_t)0x00000008U) +#define XSPI_CTRL0_DFS_10_BIT ((uint32_t)0x00000009U) +#define XSPI_CTRL0_DFS_11_BIT ((uint32_t)0x0000000AU) +#define XSPI_CTRL0_DFS_12_BIT ((uint32_t)0x0000000BU) +#define XSPI_CTRL0_DFS_13_BIT ((uint32_t)0x0000000CU) +#define XSPI_CTRL0_DFS_14_BIT ((uint32_t)0x0000000DU) +#define XSPI_CTRL0_DFS_15_BIT ((uint32_t)0x0000000EU) +#define XSPI_CTRL0_DFS_16_BIT ((uint32_t)0x0000000FU) +#define XSPI_CTRL0_DFS_17_BIT ((uint32_t)0x00000010U) +#define XSPI_CTRL0_DFS_18_BIT ((uint32_t)0x00000011U) +#define XSPI_CTRL0_DFS_19_BIT ((uint32_t)0x00000012U) +#define XSPI_CTRL0_DFS_20_BIT ((uint32_t)0x00000013U) +#define XSPI_CTRL0_DFS_21_BIT ((uint32_t)0x00000014U) +#define XSPI_CTRL0_DFS_22_BIT ((uint32_t)0x00000015U) +#define XSPI_CTRL0_DFS_23_BIT ((uint32_t)0x00000016U) +#define XSPI_CTRL0_DFS_24_BIT ((uint32_t)0x00000017U) +#define XSPI_CTRL0_DFS_25_BIT ((uint32_t)0x00000018U) +#define XSPI_CTRL0_DFS_26_BIT ((uint32_t)0x00000019U) +#define XSPI_CTRL0_DFS_27_BIT ((uint32_t)0x0000001AU) +#define XSPI_CTRL0_DFS_28_BIT ((uint32_t)0x0000001BU) +#define XSPI_CTRL0_DFS_29_BIT ((uint32_t)0x0000001CU) +#define XSPI_CTRL0_DFS_30_BIT ((uint32_t)0x0000001DU) +#define XSPI_CTRL0_DFS_31_BIT ((uint32_t)0x0000001EU) +#define XSPI_CTRL0_DFS_32_BIT ((uint32_t)0x0000001FU) + +/******** Bit definition for XSPI_CTRL1 register ********/ +#define XSPI_CTRL1_NDF ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define XSPI_CTRL1_NDF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_CTRL1_NDF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_CTRL1_NDF_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_CTRL1_NDF_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_CTRL1_NDF_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_CTRL1_NDF_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_CTRL1_NDF_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_CTRL1_NDF_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_CTRL1_NDF_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_CTRL1_NDF_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_CTRL1_NDF_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_CTRL1_NDF_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_CTRL1_NDF_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_CTRL1_NDF_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_CTRL1_NDF_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_CTRL1_NDF_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_EN register ********/ +#define XSPI_EN_XSPIEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_MW_CTRL register ********/ +#define XSPI_MW_CTRL_MHSEN ((uint32_t)0x00000004U) /* Bit[2] */ + +#define XSPI_MW_CTRL_MCDIR ((uint32_t)0x00000002U) /* Bit[1] */ +#define XSPI_MW_CTRL_MCDIR_RX ((uint32_t)0x00000000U) +#define XSPI_MW_CTRL_MCDIR_TX ((uint32_t)0x00000002U) + +#define XSPI_MW_CTRL_MWMOD ((uint32_t)0x00000001U) /* Bit[0] */ +#define XSPI_MW_CTRL_MWMOD_UNSEQUENTIAL ((uint32_t)0x00000000U) +#define XSPI_MW_CTRL_MWMOD_SEQUENTIAL ((uint32_t)0x00000001U) + +/******** Bit definition for XSPI_SLAVE_EN register ********/ +#define XSPI_SLAVE_EN_SEN ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define XSPI_SLAVE_EN_SEN_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_SLAVE_EN_SEN_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_SLAVE_EN_SEN_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_SLAVE_EN_SEN_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for XSPI_BAUD register ********/ +#define XSPI_BAUD_CLKDIV ((uint32_t)0x0000FFFEU) /* Bit[15:1] */ +#define XSPI_BAUD_CLKDIV_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_BAUD_CLKDIV_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_BAUD_CLKDIV_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_BAUD_CLKDIV_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_BAUD_CLKDIV_4 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_BAUD_CLKDIV_5 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_BAUD_CLKDIV_6 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_BAUD_CLKDIV_7 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_BAUD_CLKDIV_8 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_BAUD_CLKDIV_9 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_BAUD_CLKDIV_10 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_BAUD_CLKDIV_11 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_BAUD_CLKDIV_12 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_BAUD_CLKDIV_13 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_BAUD_CLKDIV_14 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_TXFT register ********/ +#define XSPI_TXFT_TXFTST ((uint32_t)0x001F0000U) /* Bit[20:16] */ +#define XSPI_TXFT_TXFTST_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_TXFT_TXFTST_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_TXFT_TXFTST_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_TXFT_TXFTST_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_TXFT_TXFTST_4 ((uint32_t)0x00100000U) /* Bit20*/ + +#define XSPI_TXFT_TXFTTEI ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define XSPI_TXFT_TXFTTEI_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_TXFT_TXFTTEI_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_TXFT_TXFTTEI_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_TXFT_TXFTTEI_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_TXFT_TXFTTEI_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for XSPI_RXFT register ********/ +#define XSPI_RXFT_RXFTTFI ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define XSPI_RXFT_RXFTTFI_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_RXFT_RXFTTFI_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_RXFT_RXFTTFI_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_RXFT_RXFTTFI_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_RXFT_RXFTTFI_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for XSPI_TXFN register ********/ +#define XSPI_TXFN_TXFN ((uint32_t)0x0000003FU) /* Bit[5:0] */ +#define XSPI_TXFN_TXFN_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_TXFN_TXFN_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_TXFN_TXFN_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_TXFN_TXFN_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_TXFN_TXFN_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_TXFN_TXFN_5 ((uint32_t)0x00000020U) /* Bit5*/ + +/******** Bit definition for XSPI_RXFN register ********/ +#define XSPI_RXFN_RXFN ((uint32_t)0x0000003FU) /* Bit[5:0] */ +#define XSPI_RXFN_RXFN_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_RXFN_RXFN_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_RXFN_RXFN_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_RXFN_RXFN_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_RXFN_RXFN_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_RXFN_RXFN_5 ((uint32_t)0x00000020U) /* Bit5*/ + +/******** Bit definition for XSPI_STS register ********/ +#define XSPI_STS_CMPLTDDF ((uint32_t)0xFFFF8000U) /* Bit[31:15] */ +#define XSPI_STS_CMPLTDDF_0 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_STS_CMPLTDDF_1 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_STS_CMPLTDDF_2 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_STS_CMPLTDDF_3 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_STS_CMPLTDDF_4 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_STS_CMPLTDDF_5 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_STS_CMPLTDDF_6 ((uint32_t)0x00200000U) /* Bit21*/ +#define XSPI_STS_CMPLTDDF_7 ((uint32_t)0x00400000U) /* Bit22*/ +#define XSPI_STS_CMPLTDDF_8 ((uint32_t)0x00800000U) /* Bit23*/ +#define XSPI_STS_CMPLTDDF_9 ((uint32_t)0x01000000U) /* Bit24*/ +#define XSPI_STS_CMPLTDDF_10 ((uint32_t)0x02000000U) /* Bit25*/ +#define XSPI_STS_CMPLTDDF_11 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_STS_CMPLTDDF_12 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_STS_CMPLTDDF_13 ((uint32_t)0x10000000U) /* Bit28*/ +#define XSPI_STS_CMPLTDDF_14 ((uint32_t)0x20000000U) /* Bit29*/ +#define XSPI_STS_CMPLTDDF_15 ((uint32_t)0x40000000U) /* Bit30*/ +#define XSPI_STS_CMPLTDDF_16 ((uint32_t)0x80000000U) /* Bit31*/ + +#define XSPI_STS ((uint32_t)0x0000007FU) /* STS[6:0] (status flag) */ +#define XSPI_STS_DCERR ((uint32_t)0x00000040U) /* Bit[6] DCERR (Data Conflict Error)*/ +#define XSPI_STS_TXE ((uint32_t)0x00000020U) /* Bit[5] TXE (Transmit FIFO error)*/ +#define XSPI_STS_RXFF ((uint32_t)0x00000010U) /* Bit[4] RXFF (Receive FIFO not Full)*/ +#define XSPI_STS_RXFNE ((uint32_t)0x00000008U) /* Bit[3] RXFNE (Receive FIFO not Empty)*/ +#define XSPI_STS_TXFE ((uint32_t)0x00000004U) /* Bit[2] TXFE (Transmit FIFO not Empty)*/ +#define XSPI_STS_TXFNF ((uint32_t)0x00000002U) /* Bit[1] TXFNF (Transmit FIFO not Full)*/ +#define XSPI_STS_BUSY ((uint32_t)0x00000001U) /* Bit[0] BUSY (Transfer Busy Flag) */ + +/******** Bit definition for XSPI_IMASK register ********/ +#define XSPI_IMASK_DONEIM ((uint32_t)0x00000800U) /* Bit[11] */ +#define XSPI_IMASK_SPITEIM ((uint32_t)0x00000400U) /* Bit[10] */ +#define XSPI_IMASK_AXIEIM ((uint32_t)0x00000100U) /* Bit[8] */ +#define XSPI_IMASK_TXUIM ((uint32_t)0x00000080U) /* Bit[7] */ + +#define XSPI_IMASK ((uint32_t)0x0000007FU) /* IMASK[6:0] (Interrupt of Mask) */ +#define XSPI_IMASK_XRXOIM ((uint32_t)0x00000040U) /* Bit[6] */ +#define XSPI_IMASK_MMCIM ((uint32_t)0x00000020U) /* Bit[5] */ +#define XSPI_IMASK_RXFFIM ((uint32_t)0x00000010U) /* Bit[4] */ +#define XSPI_IMASK_RXFOIM ((uint32_t)0x00000008U) /* Bit[3] */ +#define XSPI_IMASK_RXFUIM ((uint32_t)0x00000004U) /* Bit[2] */ +#define XSPI_IMASK_TXFOIM ((uint32_t)0x00000002U) /* Bit[1] */ +#define XSPI_IMASK_TXFEIM ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_ISTS register ********/ +#define XSPI_ISTS_DONEIS ((uint32_t)0x00000800U) /* Bit[11] */ +#define XSPI_ISTS_SPITEIS ((uint32_t)0x00000400U) /* Bit[10] */ +#define XSPI_ISTS_AXIEIS ((uint32_t)0x00000100U) /* Bit[8] */ +#define XSPI_ISTS_TXUIS ((uint32_t)0x00000080U) /* Bit[7] */ + +#define XSPI_ISTS ((uint32_t)0x0000007FU) /* All bits of interrupt stasus */ +#define XSPI_ISTS_XRXOIS ((uint32_t)0x00000040U) /* Bit[6] */ +#define XSPI_ISTS_MMCIS ((uint32_t)0x00000020U) /* Bit[5] */ +#define XSPI_ISTS_RXFFIS ((uint32_t)0x00000010U) /* Bit[4] */ +#define XSPI_ISTS_RXFOIS ((uint32_t)0x00000008U) /* Bit[3] */ +#define XSPI_ISTS_RXFUIS ((uint32_t)0x00000004U) /* Bit[2] */ +#define XSPI_ISTS_TXFOIS ((uint32_t)0x00000002U) /* Bit[1] */ +#define XSPI_ISTS_TXFEIS ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_RISTS register ********/ +#define XSPI_RISTS_DONEIR ((uint32_t)0x00000800U) /* Bit[11] */ +#define XSPI_RISTS_SPITEIR ((uint32_t)0x00000400U) /* Bit[10] */ +#define XSPI_RISTS_AXIEIR ((uint32_t)0x00000100U) /* Bit[8] */ +#define XSPI_RISTS_TXUIR ((uint32_t)0x00000080U) /* Bit[7] */ + +#define XSPI_RISTS ((uint32_t)0x0000007FU) /* All bits of raw interrupt stasus */ +#define XSPI_RISTS_XRXORIS ((uint32_t)0x00000040U) /* Bit[6] */ +#define XSPI_RISTS_MMCRIS ((uint32_t)0x00000020U) /* Bit[5] */ +#define XSPI_RISTS_RXFFRIS ((uint32_t)0x00000010U) /* Bit[4] */ +#define XSPI_RISTS_RXFORIS ((uint32_t)0x00000008U) /* Bit[3] */ +#define XSPI_RISTS_RXFURIS ((uint32_t)0x00000004U) /* Bit[2] */ +#define XSPI_RISTS_TXFORIS ((uint32_t)0x00000002U) /* Bit[1] */ +#define XSPI_RISTS_TXFERIS ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_TXEICR_CLR register ********/ +#define XSPI_TXEICR_CLR_TXEICR ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_RXFOI_CLR register ********/ +#define XSPI_RXFOI_CLR_RXFOIC ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_RXFUI_CLR register ********/ +#define XSPI_RXFUI_CLR_RXFUIC ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_MMC_CLR register ********/ +#define XSPI_MMC_CLR_MMCIC ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_ICLR register ********/ +#define XSPI_ICLR_INTC ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_DMA_CTRL register ********/ +#define XSPI_DMA_CTRL_AID ((uint32_t)0x001F8000U) /* Bit[20:15] */ +#define XSPI_DMA_CTRL_AID_0 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_DMA_CTRL_AID_1 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_DMA_CTRL_AID_2 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_DMA_CTRL_AID_3 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_DMA_CTRL_AID_4 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_DMA_CTRL_AID_5 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_DMA_CTRL_APROT ((uint32_t)0x00007000U) /* Bit[14:12] */ +#define XSPI_DMA_CTRL_APROT_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_DMA_CTRL_APROT_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_DMA_CTRL_APROT_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_DMA_CTRL_ACACHE ((uint32_t)0x00000F00U) /* Bit[11:8] */ +#define XSPI_DMA_CTRL_ACACHE_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_DMA_CTRL_ACACHE_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_DMA_CTRL_ACACHE_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_DMA_CTRL_ACACHE_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_DMA_CTRL_AINC ((uint32_t)0x00000040U) /* Bit[6] */ +#define XSPI_DMA_CTRL_ATW ((uint32_t)0x00000018U) /* Bit[4:3] */ +#define XSPI_DMA_CTRL_ATW_0 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_DMA_CTRL_ATW_1 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_DMA_CTRL_IDMAE ((uint32_t)0x00000004U) /* Bit[2] */ +#define XSPI_DMA_CTRL_TXDMAEN ((uint32_t)0x00000002U) /* Bit[1] */ +#define XSPI_DMA_CTRL_RXDMAEN ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_DMATDL_CTRL register ********/ +#define XSPI_DMATDL_CTRL_DMATDL ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define XSPI_DMATDL_CTRL_DMATDL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_DMATDL_CTRL_DMATDL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_DMATDL_CTRL_DMATDL_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_DMATDL_CTRL_DMATDL_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_DMATDL_CTRL_DMATDL_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for XSPI_DMARDL_CTRL register ********/ +#define XSPI_DMARDL_CTRL_DMARDL ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define XSPI_DMARDL_CTRL_DMARDL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_DMARDL_CTRL_DMARDL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_DMARDL_CTRL_DMARDL_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_DMARDL_CTRL_DMARDL_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_DMARDL_CTRL_DMARDL_4 ((uint32_t)0x00000010U) /* Bit4*/ + +/******** Bit definition for XSPI_IDR register ********/ +#define XSPI_IDR_IDCODE ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define XSPI_IDR_IDCODE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_IDR_IDCODE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_IDR_IDCODE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_IDR_IDCODE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_IDR_IDCODE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_IDR_IDCODE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_IDR_IDCODE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_IDR_IDCODE_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_IDR_IDCODE_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_IDR_IDCODE_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_IDR_IDCODE_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_IDR_IDCODE_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_IDR_IDCODE_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_IDR_IDCODE_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_IDR_IDCODE_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_IDR_IDCODE_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_IDR_IDCODE_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_IDR_IDCODE_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_IDR_IDCODE_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_IDR_IDCODE_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_IDR_IDCODE_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_IDR_IDCODE_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define XSPI_IDR_IDCODE_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define XSPI_IDR_IDCODE_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define XSPI_IDR_IDCODE_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define XSPI_IDR_IDCODE_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define XSPI_IDR_IDCODE_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_IDR_IDCODE_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_IDR_IDCODE_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define XSPI_IDR_IDCODE_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define XSPI_IDR_IDCODE_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define XSPI_IDR_IDCODE_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for XSPI_VERSION_ID register ********/ +#define XSPI_VERSION_ID_VERSION ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define XSPI_VERSION_ID_VERSION_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_VERSION_ID_VERSION_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_VERSION_ID_VERSION_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_VERSION_ID_VERSION_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_VERSION_ID_VERSION_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_VERSION_ID_VERSION_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_VERSION_ID_VERSION_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_VERSION_ID_VERSION_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_VERSION_ID_VERSION_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_VERSION_ID_VERSION_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_VERSION_ID_VERSION_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_VERSION_ID_VERSION_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_VERSION_ID_VERSION_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_VERSION_ID_VERSION_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_VERSION_ID_VERSION_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_VERSION_ID_VERSION_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_VERSION_ID_VERSION_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_VERSION_ID_VERSION_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_VERSION_ID_VERSION_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_VERSION_ID_VERSION_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_VERSION_ID_VERSION_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_VERSION_ID_VERSION_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define XSPI_VERSION_ID_VERSION_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define XSPI_VERSION_ID_VERSION_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define XSPI_VERSION_ID_VERSION_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define XSPI_VERSION_ID_VERSION_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define XSPI_VERSION_ID_VERSION_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_VERSION_ID_VERSION_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_VERSION_ID_VERSION_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define XSPI_VERSION_ID_VERSION_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define XSPI_VERSION_ID_VERSION_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define XSPI_VERSION_ID_VERSION_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for XSPI_DATx register ********/ +#define XSPI_DATx_DATx ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define XSPI_DATx_DATx_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_DATx_DATx_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_DATx_DATx_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_DATx_DATx_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_DATx_DATx_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_DATx_DATx_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_DATx_DATx_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_DATx_DATx_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_DATx_DATx_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_DATx_DATx_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_DATx_DATx_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_DATx_DATx_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_DATx_DATx_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_DATx_DATx_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_DATx_DATx_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_DATx_DATx_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_DATx_DATx_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_DATx_DATx_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_DATx_DATx_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_DATx_DATx_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_DATx_DATx_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_DATx_DATx_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define XSPI_DATx_DATx_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define XSPI_DATx_DATx_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define XSPI_DATx_DATx_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define XSPI_DATx_DATx_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define XSPI_DATx_DATx_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_DATx_DATx_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_DATx_DATx_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define XSPI_DATx_DATx_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define XSPI_DATx_DATx_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define XSPI_DATx_DATx_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for XSPI_RX_DELAY register ********/ +#define XSPI_RX_DELAY_SES ((uint32_t)0x00010000U) /* Bit[16] */ +#define XSPI_RX_DELAY_SES_RISING_EDGE ((uint32_t)0x00000000U) +#define XSPI_RX_DELAY_SES_FALLING_EDGE ((uint32_t)0x00010000U) + +#define XSPI_RX_DELAY_SDCN ((uint32_t)0x000000FFU) /* Bit[7:0] */ +#define XSPI_RX_DELAY_SDCN_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_RX_DELAY_SDCN_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_RX_DELAY_SDCN_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_RX_DELAY_SDCN_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_RX_DELAY_SDCN_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_RX_DELAY_SDCN_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_RX_DELAY_SDCN_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_RX_DELAY_SDCN_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_RX_DELAY_SDCN_0_CYCLES ((uint32_t)0x00000000U) +#define XSPI_RX_DELAY_SDCN_1_CYCLES ((uint32_t)0x00000001U) +#define XSPI_RX_DELAY_SDCN_2_CYCLES ((uint32_t)0x00000002U) +#define XSPI_RX_DELAY_SDCN_3_CYCLES ((uint32_t)0x00000003U) +#define XSPI_RX_DELAY_SDCN_4_CYCLES ((uint32_t)0x00000004U) +#define XSPI_RX_DELAY_SDCN_5_CYCLES ((uint32_t)0x00000005U) +#define XSPI_RX_DELAY_SDCN_6_CYCLES ((uint32_t)0x00000006U) + +/******** Bit definition for XSPI_ENH_CTRL0 register ********/ +#define XSPI_ENH_CTRL0_CLKSTREN ((uint32_t)0x40000000U) /* Bit[30] */ +#define XSPI_ENH_CTRL0_XIPPREEN ((uint32_t)0x20000000U) /* Bit[29] */ +#define XSPI_ENH_CTRL0_XIPMBL ((uint32_t)0x0C000000U) /* Bit[27:26] */ +#define XSPI_ENH_CTRL0_XIPMBL_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_ENH_CTRL0_XIPMBL_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_ENH_CTRL0_RXDSSIGEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define XSPI_ENH_CTRL0_SPIDMEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define XSPI_ENH_CTRL0_XIPCTEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define XSPI_ENH_CTRL0_XIPINSTEN ((uint32_t)0x00100000U) /* Bit[20] */ +#define XSPI_ENH_CTRL0_XIPDFSHC ((uint32_t)0x00080000U) /* Bit[19] */ + +#define XSPI_ENH_CTRL0_SPIRXDSEN ((uint32_t)0x00040000U) /* Bit[18] */ +#define XSPI_ENH_CTRL0_WRINDDREN ((uint32_t)0x00020000U) /* Bit[17] */ +#define XSPI_ENH_CTRL0_WRSPIDDREN ((uint32_t)0x00010000U) /* Bit[16] */ + +#define XSPI_ENH_CTRL0_WAITCYCLES ((uint32_t)0x0000F800U) /* Bit[15:11] */ +#define XSPI_ENH_CTRL0_WAITCYCLES_0 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_ENH_CTRL0_WAITCYCLES_1 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_ENH_CTRL0_WAITCYCLES_2 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_ENH_CTRL0_WAITCYCLES_3 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_ENH_CTRL0_WAITCYCLES_4 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_ENH_CTRL0_WAIT_1CYCLES ((uint32_t)0x00000800U) +#define XSPI_ENH_CTRL0_WAIT_2CYCLES ((uint32_t)0x00001000U) +#define XSPI_ENH_CTRL0_WAIT_3CYCLES ((uint32_t)0x00001800U) +#define XSPI_ENH_CTRL0_WAIT_4CYCLES ((uint32_t)0x00002000U) +#define XSPI_ENH_CTRL0_WAIT_5CYCLES ((uint32_t)0x00002800U) +#define XSPI_ENH_CTRL0_WAIT_6CYCLES ((uint32_t)0x00003000U) +#define XSPI_ENH_CTRL0_WAIT_7CYCLES ((uint32_t)0x00003800U) +#define XSPI_ENH_CTRL0_WAIT_8CYCLES ((uint32_t)0x00004000U) +#define XSPI_ENH_CTRL0_WAIT_9CYCLES ((uint32_t)0x00004800U) +#define XSPI_ENH_CTRL0_WAIT_10CYCLES ((uint32_t)0x00005000U) +#define XSPI_ENH_CTRL0_WAIT_11CYCLES ((uint32_t)0x00005800U) +#define XSPI_ENH_CTRL0_WAIT_12CYCLES ((uint32_t)0x00006000U) +#define XSPI_ENH_CTRL0_WAIT_13CYCLES ((uint32_t)0x00006800U) +#define XSPI_ENH_CTRL0_WAIT_14CYCLES ((uint32_t)0x00007000U) +#define XSPI_ENH_CTRL0_WAIT_15CYCLES ((uint32_t)0x00007800U) +#define XSPI_ENH_CTRL0_WAIT_16CYCLES ((uint32_t)0x00008000U) +#define XSPI_ENH_CTRL0_WAIT_17CYCLES ((uint32_t)0x00008800U) +#define XSPI_ENH_CTRL0_WAIT_18CYCLES ((uint32_t)0x00009000U) +#define XSPI_ENH_CTRL0_WAIT_19CYCLES ((uint32_t)0x00009800U) +#define XSPI_ENH_CTRL0_WAIT_20CYCLES ((uint32_t)0x0000A000U) +#define XSPI_ENH_CTRL0_WAIT_21CYCLES ((uint32_t)0x0000A800U) +#define XSPI_ENH_CTRL0_WAIT_22CYCLES ((uint32_t)0x0000B000U) +#define XSPI_ENH_CTRL0_WAIT_23CYCLES ((uint32_t)0x0000B800U) +#define XSPI_ENH_CTRL0_WAIT_24CYCLES ((uint32_t)0x0000C000U) +#define XSPI_ENH_CTRL0_WAIT_25CYCLES ((uint32_t)0x0000C800U) +#define XSPI_ENH_CTRL0_WAIT_26CYCLES ((uint32_t)0x0000D000U) +#define XSPI_ENH_CTRL0_WAIT_27CYCLES ((uint32_t)0x0000D800U) +#define XSPI_ENH_CTRL0_WAIT_28CYCLES ((uint32_t)0x0000E000U) +#define XSPI_ENH_CTRL0_WAIT_29CYCLES ((uint32_t)0x0000E800U) +#define XSPI_ENH_CTRL0_WAIT_30CYCLES ((uint32_t)0x0000F000U) +#define XSPI_ENH_CTRL0_WAIT_31CYCLES ((uint32_t)0x0000F800U) + +#define XSPI_ENH_CTRL0_INSTL ((uint32_t)0x00000300U) /* Bit[9:8] */ +#define XSPI_ENH_CTRL0_INSTL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_ENH_CTRL0_INSTL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_ENH_CTRL0_INST_L_0_LINE ((uint32_t)0x00000000U) +#define XSPI_ENH_CTRL0_INST_L_4_LINE ((uint32_t)0x00000100U) +#define XSPI_ENH_CTRL0_INST_L_8_LINE ((uint32_t)0x00000200U) +#define XSPI_ENH_CTRL0_INST_L_16_LINE ((uint32_t)0x00000300U) + +#define XSPI_ENH_CTRL0_XIPMDBEN ((uint32_t)0x00000080U) /* Bit[7] */ + +#define XSPI_ENH_CTRL0_ADDRLEN ((uint32_t)0x0000003CU) /* Bit[5:2] */ +#define XSPI_ENH_CTRL0_ADDRLEN_0 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_ENH_CTRL0_ADDRLEN_1 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_ENH_CTRL0_ADDRLEN_2 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_ENH_CTRL0_ADDRLEN_3 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_ENH_CTRL0_ADDRLEN_4_BIT ((uint32_t)0x00000004U) +#define XSPI_ENH_CTRL0_ADDRLEN_8_BIT ((uint32_t)0x00000008U) +#define XSPI_ENH_CTRL0_ADDRLEN_12_BIT ((uint32_t)0x0000000CU) +#define XSPI_ENH_CTRL0_ADDRLEN_16_BIT ((uint32_t)0x00000010U) +#define XSPI_ENH_CTRL0_ADDRLEN_20_BIT ((uint32_t)0x00000014U) +#define XSPI_ENH_CTRL0_ADDRLEN_24_BIT ((uint32_t)0x00000018U) +#define XSPI_ENH_CTRL0_ADDRLEN_28_BIT ((uint32_t)0x0000001CU) +#define XSPI_ENH_CTRL0_ADDRLEN_32_BIT ((uint32_t)0x00000020U) +#define XSPI_ENH_CTRL0_ADDRLEN_36_BIT ((uint32_t)0x00000024U) +#define XSPI_ENH_CTRL0_ADDRLEN_40_BIT ((uint32_t)0x00000028U) +#define XSPI_ENH_CTRL0_ADDRLEN_44_BIT ((uint32_t)0x0000002CU) +#define XSPI_ENH_CTRL0_ADDRLEN_48_BIT ((uint32_t)0x00000030U) +#define XSPI_ENH_CTRL0_ADDRLEN_52_BIT ((uint32_t)0x00000034U) +#define XSPI_ENH_CTRL0_ADDRLEN_56_BIT ((uint32_t)0x00000038U) +#define XSPI_ENH_CTRL0_ADDRLEN_60_BIT ((uint32_t)0x0000003CU) + +#define XSPI_ENH_CTRL0_TRANSTYPE ((uint32_t)0x00000003U) /* Bit[1:0] */ +#define XSPI_ENH_CTRL0_TRANSTYPE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_ENH_CTRL0_TRANSTYPE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_ENH_CTRL0_TRANSTYPE_STANDARD ((uint32_t)0x00000000U) +#define XSPI_ENH_CTRL0_TRANSTYPE_ADDRESS_BY_FRF ((uint32_t)0x00000001U) +#define XSPI_ENH_CTRL0_TRANSTYPE_ALL_BY_FRF ((uint32_t)0x00000002U) +/******** Bit definition for XSPI_DDR_TXDE register ********/ +#define XSPI_DDR_TXDE_TXDE ((uint32_t)0x000000FFU) /* Bit[7:0] */ +#define XSPI_DDR_TXDE_TXDE_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_DDR_TXDE_TXDE_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_DDR_TXDE_TXDE_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_DDR_TXDE_TXDE_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_DDR_TXDE_TXDE_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_DDR_TXDE_TXDE_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_DDR_TXDE_TXDE_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_DDR_TXDE_TXDE_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for XSPI_XIP_MODE register ********/ +#define XSPI_XIP_MODE_XIPMDBITS ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define XSPI_XIP_MODE_XIPMDBITS_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_MODE_XIPMDBITS_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_MODE_XIPMDBITS_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_MODE_XIPMDBITS_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_MODE_XIPMDBITS_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_MODE_XIPMDBITS_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_MODE_XIPMDBITS_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_MODE_XIPMDBITS_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_MODE_XIPMDBITS_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_MODE_XIPMDBITS_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_MODE_XIPMDBITS_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_MODE_XIPMDBITS_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_XIP_MODE_XIPMDBITS_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_XIP_MODE_XIPMDBITS_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_MODE_XIPMDBITS_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_MODE_XIPMDBITS_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_XIP_INCR_TOC register ********/ +#define XSPI_XIP_INCR_TOC_ITOC ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define XSPI_XIP_INCR_TOC_ITOC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_INCR_TOC_ITOC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_INCR_TOC_ITOC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_INCR_TOC_ITOC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_INCR_TOC_ITOC_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_INCR_TOC_ITOC_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_INCR_TOC_ITOC_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_INCR_TOC_ITOC_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_INCR_TOC_ITOC_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_INCR_TOC_ITOC_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_INCR_TOC_ITOC_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_INCR_TOC_ITOC_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_XIP_INCR_TOC_ITOC_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_XIP_INCR_TOC_ITOC_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_INCR_TOC_ITOC_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_INCR_TOC_ITOC_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_XIP_WRAP_TOC register ********/ +#define XSPI_XIP_WRAP_TOC_WTOC ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define XSPI_XIP_WRAP_TOC_WTOC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_WRAP_TOC_WTOC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_WRAP_TOC_WTOC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_WRAP_TOC_WTOC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_WRAP_TOC_WTOC_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_WRAP_TOC_WTOC_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_WRAP_TOC_WTOC_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_WRAP_TOC_WTOC_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_WRAP_TOC_WTOC_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_WRAP_TOC_WTOC_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_WRAP_TOC_WTOC_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_WRAP_TOC_WTOC_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_XIP_WRAP_TOC_WTOC_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_XIP_WRAP_TOC_WTOC_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_WRAP_TOC_WTOC_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_WRAP_TOC_WTOC_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_XIP_CTRL register ********/ +#define XSPI_XIP_CTRL_XIPPREEN ((uint32_t)0x20000000U) /* Bit[29] */ + +#define XSPI_XIP_CTRL_XIPMBL ((uint32_t)0x0C000000U) /* Bit[27:26] */ +#define XSPI_XIP_CTRL_XIPMBL_0 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_XIP_CTRL_XIPMBL_1 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_XIP_CTRL_XIPMBL_LEN_2_BIT ((uint32_t)0x00000000U) +#define XSPI_XIP_CTRL_XIPMBL_LEN_4_BIT ((uint32_t)0x04000000U) +#define XSPI_XIP_CTRL_XIPMBL_LEN_8_BIT ((uint32_t)0x08000000U) +#define XSPI_XIP_CTRL_XIPMBL_LEN_16_BIT ((uint32_t)0x0C000000U) + +#define XSPI_XIP_CTRL_RXDSSIGEN ((uint32_t)0x02000000U) /* Bit[25] */ +#define XSPI_XIP_CTRL_XIPHYPEEN ((uint32_t)0x01000000U) /* Bit[24] */ +#define XSPI_XIP_CTRL_XIPCTEN ((uint32_t)0x00800000U) /* Bit[23] */ +#define XSPI_XIP_CTRL_XIPINSTEN ((uint32_t)0x00400000U) /* Bit[22] */ +#define XSPI_XIP_CTRL_RXDSEN ((uint32_t)0x00200000U) /* Bit[21] */ +#define XSPI_XIP_CTRL_WRINDDREN ((uint32_t)0x00100000U) /* Bit[20] */ +#define XSPI_XIP_CTRL_DDREN ((uint32_t)0x00080000U) /* Bit[19] */ +#define XSPI_XIP_CTRL_DFSHC ((uint32_t)0x00040000U) /* Bit[18] */ + +#define XSPI_XIP_CTRL_WAITCYCLES ((uint32_t)0x0003E000U) /* Bit[17:13] */ +#define XSPI_XIP_CTRL_WAITCYCLES_0 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_CTRL_WAITCYCLES_1 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_CTRL_WAITCYCLES_2 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_XIP_CTRL_WAITCYCLES_3 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_XIP_CTRL_WAITCYCLES_4 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_XIP_CTRL_WAIT_1CYCLES ((uint32_t)0x00002000U) +#define XSPI_XIP_CTRL_WAIT_2CYCLES ((uint32_t)0x00004000U) +#define XSPI_XIP_CTRL_WAIT_3CYCLES ((uint32_t)0x00006000U) +#define XSPI_XIP_CTRL_WAIT_4CYCLES ((uint32_t)0x00008000U) +#define XSPI_XIP_CTRL_WAIT_5CYCLES ((uint32_t)0x0000A000U) +#define XSPI_XIP_CTRL_WAIT_6CYCLES ((uint32_t)0x0000C000U) +#define XSPI_XIP_CTRL_WAIT_7CYCLES ((uint32_t)0x0000E000U) +#define XSPI_XIP_CTRL_WAIT_8CYCLES ((uint32_t)0x00010000U) +#define XSPI_XIP_CTRL_WAIT_9CYCLES ((uint32_t)0x00012000U) +#define XSPI_XIP_CTRL_WAIT_10CYCLES ((uint32_t)0x00014000U) +#define XSPI_XIP_CTRL_WAIT_11CYCLES ((uint32_t)0x00016000U) +#define XSPI_XIP_CTRL_WAIT_12CYCLES ((uint32_t)0x00018000U) +#define XSPI_XIP_CTRL_WAIT_13CYCLES ((uint32_t)0x0001A000U) +#define XSPI_XIP_CTRL_WAIT_14CYCLES ((uint32_t)0x0001C000U) +#define XSPI_XIP_CTRL_WAIT_15CYCLES ((uint32_t)0x0001E000U) +#define XSPI_XIP_CTRL_WAIT_16CYCLES ((uint32_t)0x00020000U) +#define XSPI_XIP_CTRL_WAIT_17CYCLES ((uint32_t)0x00022000U) +#define XSPI_XIP_CTRL_WAIT_18CYCLES ((uint32_t)0x00024000U) +#define XSPI_XIP_CTRL_WAIT_19CYCLES ((uint32_t)0x00026000U) +#define XSPI_XIP_CTRL_WAIT_20CYCLES ((uint32_t)0x00028000U) +#define XSPI_XIP_CTRL_WAIT_21CYCLES ((uint32_t)0x0002A000U) +#define XSPI_XIP_CTRL_WAIT_22CYCLES ((uint32_t)0x0002C000U) +#define XSPI_XIP_CTRL_WAIT_23CYCLES ((uint32_t)0x0002E000U) +#define XSPI_XIP_CTRL_WAIT_24CYCLES ((uint32_t)0x00030000U) +#define XSPI_XIP_CTRL_WAIT_25CYCLES ((uint32_t)0x00032000U) +#define XSPI_XIP_CTRL_WAIT_26CYCLES ((uint32_t)0x00034000U) +#define XSPI_XIP_CTRL_WAIT_27CYCLES ((uint32_t)0x00036000U) +#define XSPI_XIP_CTRL_WAIT_28CYCLES ((uint32_t)0x00038000U) +#define XSPI_XIP_CTRL_WAIT_29CYCLES ((uint32_t)0x0003A000U) +#define XSPI_XIP_CTRL_WAIT_30CYCLES ((uint32_t)0x0003C000U) +#define XSPI_XIP_CTRL_WAIT_31CYCLES ((uint32_t)0x0003E000U) + +#define XSPI_XIP_CTRL_MDBITSEN ((uint32_t)0x00001000U) /* Bit[12] */ + +#define XSPI_XIP_CTRL_INSTL ((uint32_t)0x00000600U) /* Bit[10:9] */ +#define XSPI_XIP_CTRL_INSTL_0 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_CTRL_INSTL_1 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_CTRL_INSTL_0_LINE ((uint32_t)0x00000000U) +#define XSPI_XIP_CTRL_INSTL_4_LINE ((uint32_t)0x00000200U) +#define XSPI_XIP_CTRL_INSTL_8_LINE ((uint32_t)0x00000400U) +#define XSPI_XIP_CTRL_INSTL_16_LINE ((uint32_t)0x00000600U) + +#define XSPI_XIP_CTRL_ADDRL ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define XSPI_XIP_CTRL_ADDRL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_CTRL_ADDRL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_CTRL_ADDRL_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_CTRL_ADDRL_3 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_CTRL_ADDR_4BIT ((uint32_t)0x00000010U) +#define XSPI_XIP_CTRL_ADDR_8BIT ((uint32_t)0x00000020U) +#define XSPI_XIP_CTRL_ADDR_12BIT ((uint32_t)0x00000030U) +#define XSPI_XIP_CTRL_ADDR_16BIT ((uint32_t)0x00000040U) +#define XSPI_XIP_CTRL_ADDR_20BIT ((uint32_t)0x00000050U) +#define XSPI_XIP_CTRL_ADDR_24BIT ((uint32_t)0x00000060U) +#define XSPI_XIP_CTRL_ADDR_28BIT ((uint32_t)0x00000070U) +#define XSPI_XIP_CTRL_ADDR_32BIT ((uint32_t)0x00000080U) +#define XSPI_XIP_CTRL_ADDR_36BIT ((uint32_t)0x00000090U) +#define XSPI_XIP_CTRL_ADDR_40BIT ((uint32_t)0x000000A0U) +#define XSPI_XIP_CTRL_ADDR_44BIT ((uint32_t)0x000000B0U) +#define XSPI_XIP_CTRL_ADDR_48BIT ((uint32_t)0x000000C0U) +#define XSPI_XIP_CTRL_ADDR_52BIT ((uint32_t)0x000000D0U) +#define XSPI_XIP_CTRL_ADDR_56BIT ((uint32_t)0x000000E0U) +#define XSPI_XIP_CTRL_ADDR_60BIT ((uint32_t)0x000000F0U) + +#define XSPI_XIP_CTRL_TRANSTYPE ((uint32_t)0x0000000CU) /* Bit[3:2] */ +#define XSPI_XIP_CTRL_TRANSTYPE_0 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_CTRL_TRANSTYPE_1 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_CTRL_TRANSTYPE_STANDARD_SPI ((uint32_t)0x00000000U) +#define XSPI_XIP_CTRL_TRANSTYPE_ADDRESS_BY_XIP_FRF ((uint32_t)0x00000004U) +#define XSPI_XIP_CTRL_TRANSTYPE_INSTRUCT_BY_XIP_FRF ((uint32_t)0x00000008U) + +#define XSPI_XIP_CTRL_FRF ((uint32_t)0x00000003U) /* Bit[1:0] */ +#define XSPI_XIP_CTRL_FRF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_CTRL_FRF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_CTRL_FRF_2_LINE ((uint32_t)0x00000001U) +#define XSPI_XIP_CTRL_FRF_4_LINE ((uint32_t)0x00000002U) + +/******** Bit definition for XSPI_XIP_SLAVE_EN register ********/ +#define XSPI_XIP_SLAVE_EN_SEN ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define XSPI_XIP_SLAVE_EN_SEN_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_SLAVE_EN_SEN_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_SLAVE_EN_SEN_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_SLAVE_EN_SEN_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for XSPI_XIP_RXFOI_CLR register ********/ +#define XSPI_XIP_RXFOI_CLR_XRXFOIC ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for XSPI_XIP_TOUT register ********/ +#define XSPI_XIP_TOUT_XTOUT ((uint32_t)0x000000FFU) /* Bit[7:0] */ +#define XSPI_XIP_TOUT_XTOUT_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_TOUT_XTOUT_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_TOUT_XTOUT_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_TOUT_XTOUT_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_TOUT_XTOUT_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_TOUT_XTOUT_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_TOUT_XTOUT_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_TOUT_XTOUT_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for XSPI_XIP_WRITE_INCR_INST register ********/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_WRITE_INCR_INST_INCRWRINST_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_XIP_WRITE_WRAP_INST register ********/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_WRITE_WRAP_INST_WRAPWRINST_15 ((uint32_t)0x00008000U) /* Bit15*/ + +/******** Bit definition for XSPI_XIP_WRITE_CTRL register ********/ +#define XSPI_XIP_WRITE_CTRL_XIPWRWCY ((uint32_t)0x001F0000U) /* Bit[20:16] */ +#define XSPI_XIP_WRITE_CTRL_XIPWRWCY_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_XIP_WRITE_CTRL_XIPWRWCY_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_XIP_WRITE_CTRL_XIPWRWCY_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_XIP_WRITE_CTRL_XIPWRWCY_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_XIP_WRITE_CTRL_XIPWRWCY_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_XIP_WRITE_CTRL_WAIT_1CYCLES ((uint32_t)0x00010000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_2CYCLES ((uint32_t)0x00020000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_3CYCLES ((uint32_t)0x00030000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_4CYCLES ((uint32_t)0x00040000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_5CYCLES ((uint32_t)0x00050000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_6CYCLES ((uint32_t)0x00060000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_7CYCLES ((uint32_t)0x00070000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_8CYCLES ((uint32_t)0x00080000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_9CYCLES ((uint32_t)0x00090000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_10CYCLES ((uint32_t)0x000A0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_11CYCLES ((uint32_t)0x000B0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_12CYCLES ((uint32_t)0x000C0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_13CYCLES ((uint32_t)0x000D0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_14CYCLES ((uint32_t)0x000E0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_15CYCLES ((uint32_t)0x000F0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_16CYCLES ((uint32_t)0x00100000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_17CYCLES ((uint32_t)0x00110000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_18CYCLES ((uint32_t)0x00120000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_19CYCLES ((uint32_t)0x00130000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_20CYCLES ((uint32_t)0x00140000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_21CYCLES ((uint32_t)0x00150000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_22CYCLES ((uint32_t)0x00160000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_23CYCLES ((uint32_t)0x00170000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_24CYCLES ((uint32_t)0x00180000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_25CYCLES ((uint32_t)0x00190000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_26CYCLES ((uint32_t)0x001A0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_27CYCLES ((uint32_t)0x001B0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_28CYCLES ((uint32_t)0x001C0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_29CYCLES ((uint32_t)0x001D0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_30CYCLES ((uint32_t)0x001E0000U) +#define XSPI_XIP_WRITE_CTRL_WAIT_31CYCLES ((uint32_t)0x001F0000U) + +#define XSPI_XIP_WRITE_CTRL_XIPWRRXDSSIGEN ((uint32_t)0x00002000U) /* Bit[13] */ +#define XSPI_XIP_WRITE_CTRL_XIPWRHYPEEN ((uint32_t)0x00001000U) /* Bit[12] */ + +#define XSPI_XIP_WRITE_CTRL_WRINDDREN ((uint32_t)0x00000800U) /* Bit[11] */ +#define XSPI_XIP_WRITE_CTRL_WRSPIDDREN ((uint32_t)0x00000400U) /* Bit[10] */ + +#define XSPI_XIP_WRITE_CTRL_WRINSTL ((uint32_t)0x00000300U) /* Bit[9:8] */ +#define XSPI_XIP_WRITE_CTRL_WRINSTL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_WRITE_CTRL_WRINSTL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_WRITE_CTRL_WRINSTL_0_LINE ((uint32_t)0x00000000U) +#define XSPI_XIP_WRITE_CTRL_WRINSTL_4_LINE ((uint32_t)0x00000200U) +#define XSPI_XIP_WRITE_CTRL_WRINSTL_8_LINE ((uint32_t)0x00000400U) +#define XSPI_XIP_WRITE_CTRL_WRINSTL_16_LINE ((uint32_t)0x00000600U) + +#define XSPI_XIP_WRITE_CTRL_WRADDRL ((uint32_t)0x000000F0U) /* Bit[7:4] */ +#define XSPI_XIP_WRITE_CTRL_WRADDRL_0 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_WRITE_CTRL_WRADDRL_1 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_WRITE_CTRL_WRADDRL_2 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_WRITE_CTRL_WRADDRL_3 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_WRITE_CTRL_WRADDRL_4BIT ((uint32_t)0x00000010U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_8BIT ((uint32_t)0x00000020U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_12BIT ((uint32_t)0x00000030U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_16BIT ((uint32_t)0x00000040U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_20BIT ((uint32_t)0x00000050U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_24BIT ((uint32_t)0x00000060U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_28BIT ((uint32_t)0x00000070U) +#define XSPI_XIP_WRITE_CTRL_WRADDRL_32BIT ((uint32_t)0x00000080U) + +#define XSPI_XIP_WRITE_CTRL_WRTRTYPE ((uint32_t)0x0000000CU) /* Bit[3:2] */ +#define XSPI_XIP_WRITE_CTRL_WRTRTYPE_0 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_WRITE_CTRL_WRTRTYPE_1 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_WRITE_CTRL_WRTRTYPE_STANDARD_SPI ((uint32_t)0x00000000U) +#define XSPI_XIP_WRITE_CTRL_WRTRTYPE_ADDRESS_BY_XIP_WRITE_WRFRF ((uint32_t)0x00000004U) +#define XSPI_XIP_WRITE_CTRL_WRTRTYPE_INSTRUCT_BY_XIP_WRITE_WRFRF ((uint32_t)0x00000008U) + + +#define XSPI_XIP_WRITE_CTRL_WRFRF ((uint32_t)0x00000003U) /* Bit[1:0] */ +#define XSPI_XIP_WRITE_CTRL_WRFRF_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_WRITE_CTRL_WRFRF_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_WRITE_CTRL_WRFRF_2_LINE ((uint32_t)0x00000001U) +#define XSPI_XIP_WRITE_CTRL_WRFRF_4_LINE ((uint32_t)0x00000002U) +#define XSPI_XIP_WRITE_CTRL_WRFRF_8_LINE ((uint32_t)0x00000003U) +/******** Bit definition for XSPI_XIP_WRITE_TIMING register ********/ +#define XSPI_XIP_WRITE_TIMING_TPP ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ +#define XSPI_XIP_WRITE_TIMING_TPP_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_XIP_WRITE_TIMING_TPP_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_XIP_WRITE_TIMING_TPP_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_XIP_WRITE_TIMING_TPP_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define XSPI_XIP_WRITE_TIMING_TPP_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define XSPI_XIP_WRITE_TIMING_TPP_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define XSPI_XIP_WRITE_TIMING_TPP_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define XSPI_XIP_WRITE_TIMING_TPP_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define XSPI_XIP_WRITE_TIMING_TPP_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define XSPI_XIP_WRITE_TIMING_TPP_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define XSPI_XIP_WRITE_TIMING_TPP_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define XSPI_XIP_WRITE_TIMING_TPP_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define XSPI_XIP_WRITE_TIMING_TPP_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define XSPI_XIP_WRITE_TIMING_TPP_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define XSPI_XIP_WRITE_TIMING_TPP_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define XSPI_XIP_WRITE_TIMING_TPP_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define XSPI_XIP_WRITE_TIMING_TPP_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define XSPI_XIP_WRITE_TIMING_TPP_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define XSPI_XIP_WRITE_TIMING_TPP_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define XSPI_XIP_WRITE_TIMING_TPP_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define XSPI_XIP_WRITE_TIMING_TPP_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define XSPI_XIP_WRITE_TIMING_TPP_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define XSPI_XIP_WRITE_TIMING_TPP_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define XSPI_XIP_WRITE_TIMING_TPP_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define XSPI_XIP_WRITE_TIMING_TPP_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define XSPI_XIP_WRITE_TIMING_TPP_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define XSPI_XIP_WRITE_TIMING_TPP_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define XSPI_XIP_WRITE_TIMING_TPP_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define XSPI_XIP_WRITE_TIMING_TPP_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define XSPI_XIP_WRITE_TIMING_TPP_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define XSPI_XIP_WRITE_TIMING_TPP_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define XSPI_XIP_WRITE_TIMING_TPP_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/******** Bit definition for XSPI_RXDS_DELAY_CTRL register ********/ +#define XSPI_RXDS_DELAY_CTRL_RXDSDELAYEN ((uint32_t)0x00000010U) /* Bit[4] */ +#define XSPI_RXDS_DELAY_CTRL_RXDSTAPDELAY ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define XSPI_RXDS_DELAY_CTRL_RXDSTAPDELAY_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define XSPI_RXDS_DELAY_CTRL_RXDSTAPDELAY_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define XSPI_RXDS_DELAY_CTRL_RXDSTAPDELAY_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define XSPI_RXDS_DELAY_CTRL_RXDSTAPDELAY_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/** Bit definition for SPI_CTRL1 register **/ +#define SPI_CTRL1_BR ((uint16_t)0x0007U) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTRL1_BR0 ((uint16_t)0x0001U) /* Bit 0 */ +#define SPI_CTRL1_BR1 ((uint16_t)0x0002U) /* Bit 1 */ +#define SPI_CTRL1_BR2 ((uint16_t)0x0004U) /* Bit 2 */ + +#define SPI_CTRL1_CLKPOL ((uint16_t)0x0010U) /* Clock Polarity */ +#define SPI_CTRL1_CLKPHA ((uint16_t)0x0020U) /* Clock Phase */ + +#define SPI_CTRL1_MSEL ((uint16_t)0x0040U) /* Master Selection */ +#define SPI_CTRL1_LSBFF ((uint16_t)0x0080U) /* Frame Format */ +#define SPI_CTRL1_DATFF ((uint16_t)0x0100U) /* Data Frame Format */ +#define SPI_CTRL1_CRCNEXT ((uint16_t)0x0200U) /* Transmit CRC next Software slave management */ +#define SPI_CTRL1_SSOEN ((uint16_t)0x0400U) /* SS Output Enable */ +#define SPI_CTRL1_SSEL ((uint16_t)0x0800U) /* Internal slave select */ +#define SPI_CTRL1_SSMEN ((uint16_t)0x1000U) /* Software slave management */ +#define SPI_CTRL1_RONLY ((uint16_t)0x2000U) /* Receive only */ +#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000U) /* Output enable in bidirectional mode */ +#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000U) /* Bidirectional data mode enable */ + +/** Bit definition for SPI_CTRL2 register **/ +#define SPI_CTRL2_SPIEN ((uint16_t)0x0001U) /* SPI enable */ +#define SPI_CTRL2_RDMAEN ((uint16_t)0x0002U) /* Rx buffer DMA enable */ +#define SPI_CTRL2_TDMAEN ((uint16_t)0x0004U) /* Tx buffer DMA enable */ +#define SPI_CTRL2_CRCEN ((uint16_t)0x0008U) /* Hardware CRC calculation enable */ +#define SPI_CTRL2_TEINTEN ((uint16_t)0x0010U) /* Tx buffer empty interrupt enable */ +#define SPI_CTRL2_RNEINTEN ((uint16_t)0x0020U) /* RX buffer not empty interrupt enable */ +#define SPI_CTRL2_ERRINTEN ((uint16_t)0x0040U) /* Error interrupt enable */ +#define SPI_CTRL2_SS_POL ((uint16_t)0x0080U) /* NSS polarity control */ +#define SPI_CTRL2_FIFOEN ((uint16_t)0x0100U) /* FIFO mode enable */ +#define SPI_CTRL2_FIFOCLR ((uint16_t)0x0200U) /* FIFO clear enable */ +#define SPI_CTRL2_TXFHEINTEN ((uint16_t)0x0400U) /* Send FIFO half empty interrupt enable */ +#define SPI_CTRL2_RXFHFINTEN ((uint16_t)0x0800U) /* Receive FIFO half full interrupt enable */ +#define SPI_CTRL2_RXFFUINTEN ((uint16_t)0x1000U) /* Receive FIFO full interrupt enable */ +#define SPI_CTRL2_CRCNMISEN ((uint16_t)0x2000U) /* CRC stop calculation enable */ +#define SPI_CTRL2_RXCPINTEN ((uint16_t)0x4000U) /* Receive transfer complete interrupt enable */ +#define SPI_CTRL2_RNEDMABYPASS ((uint16_t)0x8000U) /* rxne for dma is bypass */ + +/** Bit definition for SPI_STS register **/ +#define SPI_STS_TE ((uint16_t)0x0001U) /* Transmit buffer Empty */ +#define SPI_STS_RNE ((uint16_t)0x0002U) /* Receive buffer Not Empty */ +#define SPI_STS_BUSY ((uint16_t)0x0004U) /* Busy flag */ +#define SPI_STS_CRCERR ((uint16_t)0x0008U) /* CRC Error flag */ +#define SPI_STS_MODERR ((uint16_t)0x0010U) /* Mode fault */ +#define SPI_STS_OVER ((uint16_t)0x0020U) /* Overrun flag */ +#define SPI_STS_UNDER ((uint16_t)0x0040U) /* Underrun flag */ +#define SPI_STS_CHSIDE ((uint16_t)0x0080U) /* Channel side */ +#define SPI_STS_TXFIFHE ((uint16_t)0x0100U) /* TX FIFO half empty flag */ +#define SPI_STS_RXFIFHF ((uint16_t)0x0200U) /* RX FIFO half empty flag */ +#define SPI_STS_TXFIFFU ((uint16_t)0x0400U) /* TX FIFO full flag */ +#define SPI_STS_RXFIFFU ((uint16_t)0x0800U) /* RX FIFO full flag */ +#define SPI_STS_RXTSCP ((uint16_t)0x1000U) /* In receive-only mode, the transmission complete status */ + +/** Bit definition for SPI_DAT register **/ +#define SPI_DAT_DAT ((uint16_t)0xFFFFU) /* Data Register */ + +/** Bit definition for SPI_CRCTDAT register **/ +#define SPI_CRCTDAT_CRCTDAT ((uint16_t)0xFFFFU) /* Tx CRC Register */ + +/** Bit definition for SPI_CRCRDAT register **/ +#define SPI_CRCRDAT_CRCRDAT ((uint16_t)0xFFFFU) /* Rx CRC Register */ + +/** Bit definition for SPI_CRCPOLY register **/ +#define SPI_CRCPOLY_CRCPOLY ((uint16_t)0xFFFFU) /* CRC polynomial register */ + +/** Bit definition for SPI_I2SCFG register **/ +#define SPI_I2SCFG_I2SEN ((uint16_t)0x0001U) /* I2S Enable */ +#define SPI_I2SCFG_I2SMOD ((uint16_t)0x0002U) /* I2S mode selection */ +#define SPI_I2SCFG_I2SSTD ((uint16_t)0x000CU) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFG_I2SSTD0 ((uint16_t)0x0004U) /* Bit 0 */ +#define SPI_I2SCFG_I2SSTD1 ((uint16_t)0x0008U) /* Bit 1 */ +#define SPI_I2SCFG_I2SCFG ((uint16_t)0x0030U) /* I2SCFG[1:0] bits (I2S mode setting) */ +#define SPI_I2SCFG_I2SCFG0 ((uint16_t)0x0010U) /* Bit 0 */ +#define SPI_I2SCFG_I2SCFG1 ((uint16_t)0x0020U) /* Bit 1 */ +#define SPI_I2SCFG_DATLEN ((uint16_t)0x00C0U) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFG_DATLEN0 ((uint16_t)0x0040U) /* Bit 0 */ +#define SPI_I2SCFG_DATLEN1 ((uint16_t)0x0080U) /* Bit 1 */ +#define SPI_I2SCFG_CHLEN ((uint16_t)0x0100U) /* Channel length (number of bits per audio channel) */ +#define SPI_I2SCFG_PCMFSYNC ((uint16_t)0x0200U) /* PCM frame synchronization */ +#define SPI_I2SCFG_CLKPOL ((uint16_t)0x0400U) /* steady state clock polarity */ +#define SPI_I2SCFG_PCMBYPASS ((uint16_t)0x0800U) /* pcm long for 13bit is bypass */ + +/** Bit definition for SPI_I2SPREDIV register **/ +#define SPI_I2SPREDIV_LDIV ((uint16_t)0x03FFU) /* I2S Linear prescaler */ +#define SPI_I2SPREDIV_ODDEVEN ((uint16_t)0x0400U) /* Odd factor for the prescaler */ +#define SPI_I2SPREDIV_MCLKOEN ((uint16_t)0x0800U) /* Master Clock Output Enable */ + +/** Bit definition for SPI_RX_FIFO register **/ +#define SPI_RXFIFDAT ((uint16_t)0xFFFFU) /* RX FIFO Data Register */ + +/** Bit definition for SPI_FIFO_NUM register **/ +#define SPI_FIFO_NUM_TXFBSNUM ((uint16_t)0x0007U) /* FIFO_NUM [2:0] bits (TX FIFO half empty NUM configuration) */ +#define SPI_FIFO_NUM_TXFBSNUM0 ((uint16_t)0x0001U) /* Bit 0 */ +#define SPI_FIFO_NUM_TXFBSNUM1 ((uint16_t)0x0002U) /* Bit 1 */ +#define SPI_FIFO_NUM_TXFBSNUM2 ((uint16_t)0x0004U) /* Bit 2*/ +#define SPI_FIFO_NUM_RXFBSNUM ((uint16_t)0x0070U) /* FIFO_NUM [2:0] bits (RX FIFO half full NUM configuration) */ +#define SPI_FIFO_NUM_RXFBSNUM0 ((uint16_t)0x0010U) /* Bit 0 */ +#define SPI_FIFO_NUM_RXFBSNUM1 ((uint16_t)0x0020U) /* Bit 1 */ +#define SPI_FIFO_NUM_RXFBSNUM2 ((uint16_t)0x0040U) /* Bit 2*/ + +/** Bit definition for SPI_FIFO_CNT register **/ +#define SPI_FIFO_CNT_TXFIFCNT ((uint16_t)0x000FU) /* FIFO_CNT[3:0] bits (TX FIFO Valid number) */ +#define SPI_FIFO_CNT_TXFIFCNT0 ((uint16_t)0x0001U) /* Bit 0 */ +#define SPI_FIFO_CNT_TXFIFCNT1 ((uint16_t)0x0002U) /* Bit 1 */ +#define SPI_FIFO_CNT_TXFIFCNT2 ((uint16_t)0x0004U) /* Bit 2*/ +#define SPI_FIFO_CNT_TXFIFCNT3 ((uint16_t)0x0008U) /* Bit 3*/ +#define SPI_FIFO_CNT_RXFIFCNT ((uint16_t)0x00F0U) /* FIFO_CNT [3:0] bits (RX FIFO Valid number) */ +#define SPI_FIFO_CNT_RXFIFCNT0 ((uint16_t)0x0010U) /* Bit 0 */ +#define SPI_FIFO_CNT_RXFIFCNT1 ((uint16_t)0x0020U) /* Bit 1 */ +#define SPI_FIFO_CNT_RXFIFCNT2 ((uint16_t)0x0040U) /* Bit 2*/ +#define SPI_FIFO_CNT_RXFIFCNT3 ((uint16_t)0x0080U) /* Bit 3*/ + +/** Bit definition for SPI_TRANS_NUM register **/ +#define SPI_TRANS_NUM_TRANSNUM ((uint16_t)0xFFFFU) /* RX FIFO Data Register */ + +/** Bit definition for SPI_CR3 register **/ +#define SPI_CR3_DELAYTIME ((uint16_t)0x000FU) /* CR[3:0] bits (Clock Sample Delay Register) */ +#define SPI_CR3_DELAYTIME0 ((uint16_t)0x0001U) /* Bit 0 */ +#define SPI_CR3_DELAYTIME1 ((uint16_t)0x0002U) /* Bit 1 */ +#define SPI_CR3_DELAYTIME2 ((uint16_t)0x0004U) /* Bit 2 */ +#define SPI_CR3_DELAYTIME3 ((uint16_t)0x0008U) /* Bit 3 */ + +/** Bit definition for I2SEXT_CTRL2 register **/ +#define I2SEXT_CTRL2_RDMAEN ((uint16_t)0x0002U) /* Rx buffer DMA enable */ +#define I2SEXT_CTRL2_TDMAEN ((uint16_t)0x0004U) /* Tx buffer DMA enable */ +#define I2SEXT_CTRL2_TEINTEN ((uint16_t)0x0010U) /* Tx buffer empty interrupt enable */ +#define I2SEXT_CTRL2_RNEINTEN ((uint16_t)0x0020U) /* RX buffer not empty interrupt enable */ +#define I2SEXT_CTRL2_ERRINTEN ((uint16_t)0x0040U) /* Error interrupt enable */ +#define I2SEXT_CTRL2_RXNEDMABYPASS ((uint16_t)0x8000U) /* rxne for dma is bypass */ + +/** Bit definition for I2SEXT_STS register **/ +#define I2SEXT_STS_TE ((uint16_t)0x0001U) /* Transmit buffer Empty */ +#define I2SEXT_STS_RNE ((uint16_t)0x0002U) /* Receive buffer Not Empty */ +#define I2SEXT_STS_BUSY ((uint16_t)0x0004U) /* Busy flag */ +#define I2SEXT_STS_OVER ((uint16_t)0x0020U) /* Overrun flag */ +#define I2SEXT_STS_UNDER ((uint16_t)0x0040U) /* Underrun flag */ +#define I2SEXT_STS_CHSIDE ((uint16_t)0x0080U) /* Channel side */ + +/** Bit definition for I2SEXT_DAT register **/ +#define I2SEXT_DAT_DAT ((uint16_t)0xFFFFU) /* Data Register */ + +/** Bit definition for I2SEXT_I2SCFG register **/ +#define I2SEXT_I2SCFG_I2SEN ((uint16_t)0x0001U) /* I2S Enable */ +#define I2SEXT_I2SCFG_I2SMOD ((uint16_t)0x0002U) /* I2S mode selection */ +#define I2SEXT_I2SCFG_I2SSTD ((uint16_t)0x000CU) /* STDSEL[1:0] bits (I2S standard selection) */ +#define I2SEXT_I2SCFG_I2SSTD0 ((uint16_t)0x0004U) /* Bit 0 */ +#define I2SEXT_I2SCFG_I2SSTD1 ((uint16_t)0x0008U) /* Bit 1 */ +#define I2SEXT_I2SCFG_I2SCFG ((uint16_t)0x0030U) /* MODCFG[1:0] bits (I2S configuration mode) */ +#define I2SEXT_I2SCFG_I2SCFG0 ((uint16_t)0x0010U) /* Bit 0 */ +#define I2SEXT_I2SCFG_I2SCFG1 ((uint16_t)0x0020U) /* Bit 1 */ +#define I2SEXT_I2SCFG_DATLEN ((uint16_t)0x00C0U) /* TDATLEN[1:0] bits (Data length to be transferred) */ +#define I2SEXT_I2SCFG_DATLEN0 ((uint16_t)0x0040U) /* Bit 0 */ +#define I2SEXT_I2SCFG_DATLEN1 ((uint16_t)0x0080U) /* Bit 1 */ +#define I2SEXT_I2SCFG_CHLEN ((uint16_t)0x0100U) /* Channel length (number of bits per audio channel) */ +#define I2SEXT_I2SCFG_PCMFSYNC ((uint16_t)0x0200U) /* PCM frame synchronization */ +#define I2SEXT_I2SCFG_CLKPOL ((uint16_t)0x0400U) /* steady state clock polarity */ +#define I2SEXT_I2SCFG_PCMLBYPASS ((uint16_t)0x0800U) /* pcm long for 13bit is bypass */ + +/******** Bit definition for I2C_CTRL1 register ********/ +#define I2C_CTRL1_FTXIE ((uint32_t)0x80000000U) /* FTXIE enable */ +#define I2C_CTRL1_FRXIE ((uint32_t)0x40000000U) /* FRXIE enable */ +#define I2C_CTRL1_DFX ((uint32_t)0x3F000000U) /* DFX enable */ +#define I2C_CTRL1_DFX_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define I2C_CTRL1_DFX_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define I2C_CTRL1_DFX_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define I2C_CTRL1_DFX_3 ((uint32_t)0x08000000U) /* Bit27*/ +#define I2C_CTRL1_DFX_4 ((uint32_t)0x10000000U) /* Bit28*/ +#define I2C_CTRL1_DFX_5 ((uint32_t)0x20000000U) /* Bit29*/ +#define I2C_CTRL1_CRCEN ((uint32_t)0x00800000U) /* CRC enable */ +#define I2C_CTRL1_ALRTEN ((uint32_t)0x00400000U) /* SMBus alert enable */ +#define I2C_CTRL1_SMBD ((uint32_t)0x00200000U) /* SMBus host default address enable */ +#define I2C_CTRL1_SMBH ((uint32_t)0x00100000U) /* SMBus host address enable */ +#define I2C_CTRL1_GENC ((uint32_t)0x00080000U) /* General call enable */ +#define I2C_CTRL1_NOSTRCH ((uint32_t)0x00020000U) /* Clock stretching disable */ +#define I2C_CTRL1_SBCTL ((uint32_t)0x00010000U) /* Slave byte control */ +#define I2C_CTRL1_DMARDEN ((uint32_t)0x00008000U) /* DMA reception requests enable */ +#define I2C_CTRL1_DMAWREN ((uint32_t)0x00004000U) /* DMA transmission requests enable */ +#define I2C_CTRL1_AFOFF ((uint32_t)0x00001000U) /* Analog noise filter OFF */ +#define I2C_CTRL1_DF ((uint32_t)0x00000F00U) /* Digital noise filter */ +#define I2C_CTRL1_DF_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_CTRL1_DF_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define I2C_CTRL1_DF_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define I2C_CTRL1_DF_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define I2C_CTRL1_ERRIE ((uint32_t)0x00000080U) /* Errors interrupt enable */ +#define I2C_CTRL1_TFCIE ((uint32_t)0x00000040U) /* Transfer complete interrupt enable */ +#define I2C_CTRL1_STOPIE ((uint32_t)0x00000020U) /* STOP detection interrupt enable */ +#define I2C_CTRL1_NAKIE ((uint32_t)0x00000010U) /* NACK received interrupt enable */ +#define I2C_CTRL1_ADRIE ((uint32_t)0x00000008U) /* Address match interrupt enable */ +#define I2C_CTRL1_RDRIE ((uint32_t)0x00000004U) /* RX interrupt enable */ +#define I2C_CTRL1_WDRIE ((uint32_t)0x00000002U) /* TX interrupt enable */ +#define I2C_CTRL1_I2CEN ((uint32_t)0x00000001U) /* Peripheral enable */ + +/******** Bit definition for I2C_CTRL2 register ********/ +#define I2C_CTRL2_CRCBYTE ((uint32_t)0x04000000U) /* Packet error checking byte */ +#define I2C_CTRL2_AUTOSTOP ((uint32_t)0x02000000U) /* Automatic end mode (master mode) */ +#define I2C_CTRL2_REFILL ((uint32_t)0x01000000U) /* NBYTES reload mode */ +#define I2C_CTRL2_BYTECNT ((uint32_t)0x00FF0000U) /* Number of bytes */ +#define I2C_CTRL2_BYTECNT_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define I2C_CTRL2_BYTECNT_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define I2C_CTRL2_BYTECNT_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define I2C_CTRL2_BYTECNT_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define I2C_CTRL2_BYTECNT_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define I2C_CTRL2_BYTECNT_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define I2C_CTRL2_BYTECNT_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define I2C_CTRL2_BYTECNT_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define I2C_CTRL2_NAK ((uint32_t)0x00008000U) /* NACK generation (slave mode) */ +#define I2C_CTRL2_STOP ((uint32_t)0x00004000U) /* STOP generation (master mode) */ +#define I2C_CTRL2_START ((uint32_t)0x00002000U) /* START generation */ +#define I2C_CTRL2_HDR10 ((uint32_t)0x00001000U) /* 10-bit address header only read direction (master mode) */ +#define I2C_CTRL2_ADR10 ((uint32_t)0x00000800U) /* 10-bit addressing mode (master mode) */ +#define I2C_CTRL2_RWN ((uint32_t)0x00000400U) /* Transfer direction (master mode) */ +#define I2C_CTRL2_SADR ((uint32_t)0x000003FFU) /* Slave address (master mode) */ +#define I2C_CTRL2_SADR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define I2C_CTRL2_SADR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_CTRL2_SADR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_CTRL2_SADR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_CTRL2_SADR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_CTRL2_SADR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_CTRL2_SADR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_CTRL2_SADR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define I2C_CTRL2_SADR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_CTRL2_SADR_9 ((uint32_t)0x00000200U) /* Bit9*/ + +/******** Bit definition for I2C_ADR1 register ********/ +#define I2C_ADR1_AD1EN ((uint32_t)0x00008000U) /* Own address 1 enable */ +#define I2C_ADR1_AD1MODE ((uint32_t)0x00000400U) /* Own address 1 10-bit mode */ +#define I2C_ADR1_AD1 ((uint32_t)0x000003FFU) /* Interface own address 1 */ +#define I2C_ADR1_AD1_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define I2C_ADR1_AD1_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_ADR1_AD1_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_ADR1_AD1_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_ADR1_AD1_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_ADR1_AD1_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_ADR1_AD1_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_ADR1_AD1_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define I2C_ADR1_AD1_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_ADR1_AD1_9 ((uint32_t)0x00000200U) /* Bit9*/ + +/******** Bit definition for I2C_ADR2 register ********/ +#define I2C_ADR2_AD2EN ((uint32_t)0x00008000U) /* Own address 2 enable */ +#define I2C_ADR2_AD2MSK ((uint32_t)0x00000700U) /* AD2[7:1] is masked, No comparison is done */ +#define I2C_ADR2_AD2MSK_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_ADR2_AD2MSK_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define I2C_ADR2_AD2MSK_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define I2C_ADR2_AD2 ((uint32_t)0x000000FEU) /* Own address 2 masks */ +#define I2C_ADR2_AD2_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_ADR2_AD2_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_ADR2_AD2_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_ADR2_AD2_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_ADR2_AD2_4 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_ADR2_AD2_5 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_ADR2_AD2_6 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for I2C_BUSTM register ********/ +#define I2C_BUSTM_CKDIV ((uint32_t)0xF0000000U) /* Timings CK Divider */ +#define I2C_BUSTM_CKDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define I2C_BUSTM_CKDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define I2C_BUSTM_CKDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define I2C_BUSTM_CKDIV_3 ((uint32_t)0x80000000U) /* Bit31*/ +#define I2C_BUSTM_DSCL ((uint32_t)0x00F00000U) /* Data setup time */ +#define I2C_BUSTM_DSCL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define I2C_BUSTM_DSCL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define I2C_BUSTM_DSCL_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define I2C_BUSTM_DSCL_3 ((uint32_t)0x00800000U) /* Bit23*/ +#define I2C_BUSTM_DSDA ((uint32_t)0x000F0000U) /* Data hold time */ +#define I2C_BUSTM_DSDA_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define I2C_BUSTM_DSDA_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define I2C_BUSTM_DSDA_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define I2C_BUSTM_DSDA_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define I2C_BUSTM_HSCL ((uint32_t)0x0000FF00U) /* SCL high period (master mode) */ +#define I2C_BUSTM_HSCL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_BUSTM_HSCL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define I2C_BUSTM_HSCL_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define I2C_BUSTM_HSCL_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define I2C_BUSTM_HSCL_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define I2C_BUSTM_HSCL_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define I2C_BUSTM_HSCL_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define I2C_BUSTM_HSCL_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define I2C_BUSTM_LSCL ((uint32_t)0x000000FFU) /* SCL low period (master mode) */ +#define I2C_BUSTM_LSCL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define I2C_BUSTM_LSCL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_BUSTM_LSCL_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_BUSTM_LSCL_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_BUSTM_LSCL_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_BUSTM_LSCL_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_BUSTM_LSCL_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_BUSTM_LSCL_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for I2C_TMOUTR register ********/ +#define I2C_TMOUTR_TMEXTEN ((uint32_t)0x80000000U) /* Extended clock timeout enable */ +#define I2C_TMOUTR_TMOUTB ((uint32_t)0x0FFF0000U) /* Bus timeout B*/ +#define I2C_TMOUTR_TMOUTB_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define I2C_TMOUTR_TMOUTB_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define I2C_TMOUTR_TMOUTB_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define I2C_TMOUTR_TMOUTB_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define I2C_TMOUTR_TMOUTB_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define I2C_TMOUTR_TMOUTB_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define I2C_TMOUTR_TMOUTB_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define I2C_TMOUTR_TMOUTB_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define I2C_TMOUTR_TMOUTB_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define I2C_TMOUTR_TMOUTB_9 ((uint32_t)0x02000000U) /* Bit25*/ +#define I2C_TMOUTR_TMOUTB_10 ((uint32_t)0x04000000U) /* Bit26*/ +#define I2C_TMOUTR_TMOUTB_11 ((uint32_t)0x08000000U) /* Bit27*/ +#define I2C_TMOUTR_TMOUTEN ((uint32_t)0x00008000U) /* Clock timeout enable */ +#define I2C_TMOUTR_TMIDLE ((uint32_t)0x00001000U) /* Idle clock timeout detection */ +#define I2C_TMOUTR_TMOUTA ((uint32_t)0x00000FFFU) /* Bus timeout A */ +#define I2C_TMOUTR_TMOUTA_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define I2C_TMOUTR_TMOUTA_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_TMOUTR_TMOUTA_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_TMOUTR_TMOUTA_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_TMOUTR_TMOUTA_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_TMOUTR_TMOUTA_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_TMOUTR_TMOUTA_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_TMOUTR_TMOUTA_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define I2C_TMOUTR_TMOUTA_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_TMOUTR_TMOUTA_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define I2C_TMOUTR_TMOUTA_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define I2C_TMOUTR_TMOUTA_11 ((uint32_t)0x00000800U) /* Bit11*/ + +/******** Bit definition for I2C_STSINT register ********/ +#define I2C_STSINT_FTXIS ((uint32_t)0x80000000U) /* Bit[31] */ +#define I2C_STSINT_FRXNE ((uint32_t)0x40000000U) /* Bit[30] */ +#define I2C_STSINT_ADRRCV ((uint32_t)0x00FE0000U) /* Address match code (slave mode) */ +#define I2C_STSINT_ADRRCV_0 ((uint32_t)0x00020000U) /* Bit17*/ +#define I2C_STSINT_ADRRCV_1 ((uint32_t)0x00040000U) /* Bit18*/ +#define I2C_STSINT_ADRRCV_2 ((uint32_t)0x00080000U) /* Bit19*/ +#define I2C_STSINT_ADRRCV_3 ((uint32_t)0x00100000U) /* Bit20*/ +#define I2C_STSINT_ADRRCV_4 ((uint32_t)0x00200000U) /* Bit21*/ +#define I2C_STSINT_ADRRCV_5 ((uint32_t)0x00400000U) /* Bit22*/ +#define I2C_STSINT_ADRRCV_6 ((uint32_t)0x00800000U) /* Bit23*/ +#define I2C_STSINT_DIR ((uint32_t)0x00010000U) /* Transfer direction (slave mode) */ +#define I2C_STSINT_BUSY ((uint32_t)0x00008000U) /* Bus busy */ +#define I2C_STSINT_QADR ((uint32_t)0x00004000U) /* Quick command address matched */ +#define I2C_STSINT_ALRT ((uint32_t)0x00002000U) /* SMBus alert */ +#define I2C_STSINT_TMOUT ((uint32_t)0x00001000U) /* Timeout or Tlow detection flag */ +#define I2C_STSINT_CRCERR ((uint32_t)0x00000800U) /* PEC error in reception */ +#define I2C_STSINT_OVF ((uint32_t)0x00000400U) /* Overrun/Underrun */ +#define I2C_STSINT_ABLO ((uint32_t)0x00000200U) /* Arbitration lost */ +#define I2C_STSINT_BSER ((uint32_t)0x00000100U) /* Bus error */ +#define I2C_STSINT_TFCR ((uint32_t)0x00000080U) /* Transfer complete reload */ +#define I2C_STSINT_TFC ((uint32_t)0x00000040U) /* Transfer complete (master mode) */ +#define I2C_STSINT_STOPF ((uint32_t)0x00000020U) /* STOP detection flag */ +#define I2C_STSINT_NAKF ((uint32_t)0x00000010U) /* NACK received flag */ +#define I2C_STSINT_ADR ((uint32_t)0x00000008U) /* ADRess matched (slave mode)*/ +#define I2C_STSINT_RDAVL ((uint32_t)0x00000004U) /* Receive data register not empty */ +#define I2C_STSINT_WRAVL ((uint32_t)0x00000002U) /* Transmit interrupt status */ +#define I2C_STSINT_WRE ((uint32_t)0x00000001U) /* Transmit data register empty */ + +/******** Bit definition for I2C_INTCLR register ********/ +#define I2C_INTCLR_ALRTCLR ((uint32_t)0x00002000U) /* Alert clear flag */ +#define I2C_INTCLR_TMOUTCLR ((uint32_t)0x00001000U) /* Timeout clear flag */ +#define I2C_INTCLR_CRCCLR ((uint32_t)0x00000800U) /* PAC error clear flag */ +#define I2C_INTCLR_OVFCLR ((uint32_t)0x00000400U) /* Overrun/Underrun clear flag */ +#define I2C_INTCLR_ABLOCLR ((uint32_t)0x00000200U) /* Arbitration lost clear flag */ +#define I2C_INTCLR_BSERCLR ((uint32_t)0x00000100U) /* Bus error clear flag */ +#define I2C_INTCLR_STOPCLR ((uint32_t)0x00000020U) /* STOP detection clear flag */ +#define I2C_INTCLR_NAKCLR ((uint32_t)0x00000010U) /* NACK clear flag */ +#define I2C_INTCLR_ADRCLR ((uint32_t)0x00000008U) /* Address matched clear flag */ + +/******** Bit definition for I2C_CRCR register ********/ +#define I2C_CRCR_CRC ((uint32_t)0x000000FFU) /* CRC register */ + +/******** Bit definition for I2C_RDR register ********/ +#define I2C_RDR_RDAT ((uint32_t)0x000000FFU) /* 8-bit receive data */ + +/******** Bit definition for I2C_WDR register ********/ +#define I2C_WDR_WDAT ((uint32_t)0x000000FFU) /* 8-bit transmit data */ + +/******** Bit definition for I2C_HSBUSTM register ********/ +#define I2C_HSBUSTM_HSCKDIV ((uint32_t)0xF0000000U) /* High speed mode timing prescaler*/ +#define I2C_HSBUSTM_HSCKDIV_0 ((uint32_t)0x10000000U) /* Bit28*/ +#define I2C_HSBUSTM_HSCKDIV_1 ((uint32_t)0x20000000U) /* Bit29*/ +#define I2C_HSBUSTM_HSCKDIV_2 ((uint32_t)0x40000000U) /* Bit30*/ +#define I2C_HSBUSTM_HSCKDIV_3 ((uint32_t)0x80000000U) /* Bit31*/ +#define I2C_HSBUSTM_HSDSCL ((uint32_t)0x00F00000U) /* High speed mode Data setup time*/ +#define I2C_HSBUSTM_HSDSCL_0 ((uint32_t)0x00100000U) /* Bit20*/ +#define I2C_HSBUSTM_HSDSCL_1 ((uint32_t)0x00200000U) /* Bit21*/ +#define I2C_HSBUSTM_HSDSCL_2 ((uint32_t)0x00400000U) /* Bit22*/ +#define I2C_HSBUSTM_HSDSCL_3 ((uint32_t)0x00800000U) /* Bit23*/ +#define I2C_HSBUSTM_HSDSDA ((uint32_t)0x000F0000U) /* High speed mode Data hold time*/ +#define I2C_HSBUSTM_HSDSDA_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define I2C_HSBUSTM_HSDSDA_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define I2C_HSBUSTM_HSDSDA_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define I2C_HSBUSTM_HSDSDA_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define I2C_HSBUSTM_HSHSCL ((uint32_t)0x0000FF00U) /* High speed mode SCL High period */ +#define I2C_HSBUSTM_HSHSCL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_HSBUSTM_HSHSCL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define I2C_HSBUSTM_HSHSCL_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define I2C_HSBUSTM_HSHSCL_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define I2C_HSBUSTM_HSHSCL_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define I2C_HSBUSTM_HSHSCL_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define I2C_HSBUSTM_HSHSCL_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define I2C_HSBUSTM_HSHSCL_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define I2C_HSBUSTM_HSLSCL ((uint32_t)0x000000FFU) /* High speed mode SCL low period */ +#define I2C_HSBUSTM_HSLSCL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define I2C_HSBUSTM_HSLSCL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_HSBUSTM_HSLSCL_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_HSBUSTM_HSLSCL_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_HSBUSTM_HSLSCL_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_HSBUSTM_HSLSCL_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_HSBUSTM_HSLSCL_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_HSBUSTM_HSLSCL_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for I2C_FIFOCSR register ********/ +#define I2C_FIFOCSR_TFE ((uint32_t)0x80000000U) /* Set TX FIFO active*/ +#define I2C_FIFOCSR_RFE ((uint32_t)0x40000000U) /* Set RX FIFO active*/ +#define I2C_FIFOCSR_TXILEVEL ((uint32_t)0x0F000000U) /* Bit[27:24] */ +#define I2C_FIFOCSR_TXILEVEL_0 ((uint32_t)0x01000000U) /* Bit24*/ +#define I2C_FIFOCSR_TXILEVEL_1 ((uint32_t)0x02000000U) /* Bit25*/ +#define I2C_FIFOCSR_TXILEVEL_2 ((uint32_t)0x04000000U) /* Bit26*/ +#define I2C_FIFOCSR_TXILEVEL_3 ((uint32_t)0x08000000U) /* Bit27*/ +#define I2C_FIFOCSR_RXILEVEL ((uint32_t)0x000F0000U) /* Bit[19:16] */ +#define I2C_FIFOCSR_RXILEVEL_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define I2C_FIFOCSR_RXILEVEL_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define I2C_FIFOCSR_RXILEVEL_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define I2C_FIFOCSR_RXILEVEL_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define I2C_FIFOCSR_TXFLEVEL ((uint32_t)0x00000F00U) /* TX FIFO filled level*/ +#define I2C_FIFOCSR_TXFLEVEL_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_FIFOCSR_TXFLEVEL_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define I2C_FIFOCSR_TXFLEVEL_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define I2C_FIFOCSR_TXFLEVEL_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define I2C_FIFOCSR_RXFLEVEL ((uint32_t)0x0000000FU) /* RX FIFO filled level*/ +#define I2C_FIFOCSR_RXFLEVEL_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define I2C_FIFOCSR_RXFLEVEL_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_FIFOCSR_RXFLEVEL_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_FIFOCSR_RXFLEVEL_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/******** Bit definition for I2C_QCMD register ********/ +#define I2C_QCMD_QCMDEN ((uint32_t)0x00008000U) /* SMB Quick command enable*/ +#define I2C_QCMD_QCMDAD ((uint32_t)0x000000FEU) /* SMB Quick command address*/ +#define I2C_QCMD_QCMDAD_0 ((uint32_t)0x00000002U) /* Bit1*/ +#define I2C_QCMD_QCMDAD_1 ((uint32_t)0x00000004U) /* Bit2*/ +#define I2C_QCMD_QCMDAD_2 ((uint32_t)0x00000008U) /* Bit3*/ +#define I2C_QCMD_QCMDAD_3 ((uint32_t)0x00000010U) /* Bit4*/ +#define I2C_QCMD_QCMDAD_4 ((uint32_t)0x00000020U) /* Bit5*/ +#define I2C_QCMD_QCMDAD_5 ((uint32_t)0x00000040U) /* Bit6*/ +#define I2C_QCMD_QCMDAD_6 ((uint32_t)0x00000080U) /* Bit7*/ + +/******** Bit definition for I2C_GFLTRCTRL register ********/ +#define I2C_GFLTRCTRL_SCLAFENN ((uint32_t)0x00008000U) /* SCL analog filter enable*/ +#define I2C_GFLTRCTRL_SCLAFW ((uint32_t)0x00003000U) /* SCL analog filter adjustment range control*/ +#define I2C_GFLTRCTRL_SCLAFW_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define I2C_GFLTRCTRL_SCLAFW_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define I2C_GFLTRCTRL_SDAAFENN ((uint32_t)0x00000800U) /* SDA analog filter enable*/ +#define I2C_GFLTRCTRL_SDAAFW ((uint32_t)0x00000300U) /* SDA analog filter adjustment range control*/ +#define I2C_GFLTRCTRL_SDAAFW_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define I2C_GFLTRCTRL_SDAAFW_1 ((uint32_t)0x00000200U) /* Bit9*/ + + +/** Bit definition for USART_CTRL1 register **/ +#define USART_CTRL1_UEN ((uint32_t)0x00000001U) /* USART Enable */ +#define USART_CTRL1_RXEN ((uint32_t)0x00000002U) /* Receiver Enable */ +#define USART_CTRL1_TXEN ((uint32_t)0x00000004U) /* Transmitter Enable */ +#define USART_CTRL1_PSEL ((uint32_t)0x00000008U) /* Parity Selection */ +#define USART_CTRL1_PCEN ((uint32_t)0x00000010U) /* Parity Control Enable */ +#define USART_CTRL1_WL ((uint32_t)0x00000020U) /* Word length */ +#define USART_CTRL1_RCVWU ((uint32_t)0x00000040U) /* Receiver wakeup */ +#define USART_CTRL1_WUM ((uint32_t)0x00000080U) /* Wakeup method */ +#define USART_CTRL1_IDLEIEN ((uint32_t)0x00000100U) /* IDLE Interrupt Enable */ +#define USART_CTRL1_RXDNEIEN ((uint32_t)0x00000200U) /* RXNE Interrupt Enable */ +#define USART_CTRL1_TXDEIEN ((uint32_t)0x00000400U) /* TXE Interrupt Enable */ +#define USART_CTRL1_TXCIEN ((uint32_t)0x00000800U) /* Transmission Complete Interrupt Enable */ +#define USART_CTRL1_PEIEN ((uint32_t)0x00001000U) /* PE Interrupt Enable */ +#define USART_CTRL1_SDBRK ((uint32_t)0x00002000U) /* Send Break */ +#define USART_CTRL1_DEM ((uint32_t)0x00004000U) /* Driver enable mode */ +#define USART_CTRL1_DEP ((uint32_t)0x00008000U) /* Driver enable polarity selection */ +#define USART_CTRL1_DEDT_MASK ((uint32_t)0x001F0000U) /* Driver Enable deassertion time mask */ +#define USART_CTRL1_DEAT_MASK ((uint32_t)0x03E00000U) /* Driver Enable assertion time mask */ +#define USART_CTRL1_OSPM ((uint32_t)0x04000000U) /* Oversampling mode */ +#define USART_CTRL1_SWAP ((uint32_t)0x08000000U) /* Swap TX/RX pins */ +#define USART_CTRL1_IFCEN ((uint32_t)0x10000000U) /* Idle frame controllable enable */ + +/** Bit definition for USART_CTRL2 register **/ +#define USART_CTRL2_ADDR ((uint32_t)0x0000000FU) /* Address of the USART node */ +#define USART_CTRL2_STPB ((uint32_t)0x00000060U) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTRL2_STPB_0 ((uint32_t)0x00000020U) /* Bit 0 */ +#define USART_CTRL2_STPB_1 ((uint32_t)0x00000040U) /* Bit 1 */ +#define USART_CTRL2_CLKEN ((uint32_t)0x00000100U) /* Clock Enable */ +#define USART_CTRL2_CLKPOL ((uint32_t)0x00000200U) /* Clock Polarity */ +#define USART_CTRL2_CLKPHA ((uint32_t)0x00000400U) /* Clock Phase */ +#define USART_CTRL2_LBCLK ((uint32_t)0x00000800U) /* Last Bit Clock pulse */ +#define USART_CTRL2_LINMEN ((uint32_t)0x00001000U) /* LIN mode enable */ +#define USART_CTRL2_LINBDIEN ((uint32_t)0x00002000U) /* LIN Break Detection Interrupt Enable */ +#define USART_CTRL2_LINBDL ((uint32_t)0x00004000U) /* LIN Break Detection Length */ +#define USART_CTRL2_RTOEN ((uint32_t)0x00008000U) /* Receiver timeout enable */ +#define USART_CTRL2_RTOCF ((uint32_t)0x00010000U) /* Receiver timeout clear flag */ +#define USART_CTRL2_RTOIEN ((uint32_t)0x00020000U) /* Receiver timeout interrupt enable */ +#define USART_CTRL2_PEFLOSE ((uint32_t)0x00040000U) /* PEF Data Discard Enable Bit */ +#define USART_CTRL2_NEFLOSE ((uint32_t)0x00080000U) /* NEF Data Discard Enable Bit */ +#define USART_CTRL2_FEFLOSE ((uint32_t)0x00100000U) /* FEF Data Discard Enable Bit */ + +/** Bit definition for USART_CTRL3 register **/ +#define USART_CTRL3_CTSEN ((uint32_t)0x00000001U) /* CTS Enable */ +#define USART_CTRL3_CTSIEN ((uint32_t)0x00000002U) /* CTS Interrupt Enable */ +#define USART_CTRL3_RTSEN ((uint32_t)0x00000004U) /* RTS Enable */ +#define USART_CTRL3_HDMEN ((uint32_t)0x00000008U) /* Half-Duplex Selection */ +#define USART_CTRL3_DMATXEN ((uint32_t)0x00000010U) /* DMA Enable Transmitter */ +#define USART_CTRL3_DMARXEN ((uint32_t)0x00000020U) /* DMA Enable Receiver */ +#define USART_CTRL3_ERRIEN ((uint32_t)0x00000040U) /* Error Interrupt Enable */ +#define USART_CTRL3_IRDAMEN ((uint32_t)0x00000080U) /* IrDA mode Enable */ +#define USART_CTRL3_IRDALP ((uint32_t)0x00000100U) /* IrDA Low-Power */ +#define USART_CTRL3_SCMEN ((uint32_t)0x00000200U) /* Smartcard mode enable */ +#define USART_CTRL3_SCNACK ((uint32_t)0x00000400U) /* Smartcard NACK enable */ + +/** Bit definition for USART_STS register **/ +#define USART_STS_TXFF ((uint32_t)0x00000001U) /* Send FIFO full */ +#define USART_STS_RXFF ((uint32_t)0x00000002U) /* Receive FIFO full */ +#define USART_STS_TXFE ((uint32_t)0x00000004U) /* Send FIFO empty*/ +#define USART_STS_RXFE ((uint32_t)0x00000008U) /* Receive FIFO empty */ +#define USART_STS_RXFT ((uint32_t)0x00000010U) /* RX FIFO threshold */ +#define USART_STS_TXFT ((uint32_t)0x00000020U) /* TX FIFO threshold*/ +#define USART_STS_IDLEF ((uint32_t)0x00000040U) /* IDLE line detected */ +#define USART_STS_TXDE ((uint32_t)0x00000080U) /* Transmit Data Register Empty */ +#define USART_STS_TXC ((uint32_t)0x00000100U) /* Transmission Complete */ +#define USART_STS_RXDNE ((uint32_t)0x00000200U) /* Read Data Register Not Empty */ +#define USART_STS_CTSF ((uint32_t)0x00000400U) /* CTS Flag */ +#define USART_STS_LINBDF ((uint32_t)0x00000800U) /* LIN Break Detection Flag */ +#define USART_STS_PEF ((uint32_t)0x00001000U) /* Parity Error */ +#define USART_STS_OREF ((uint32_t)0x00002000U) /* OverRun Error */ +#define USART_STS_NEF ((uint32_t)0x00004000U) /* Noise Error Flag */ +#define USART_STS_FEF ((uint32_t)0x00008000U) /* Framing Error */ +#define USART_STS_RTOF ((uint32_t)0x00010000U) /* recevier timeout */ +#define USART_STS_PELOSEF ((uint32_t)0x00020000U) /* Received Data PE Error Discard Flag */ +#define USART_STS_NELOSEF ((uint32_t)0x00040000U) /* Received Data NE Error Discard Flag */ +#define USART_STS_FELOSEF ((uint32_t)0x00080000U) /* Received Data FE Error Discard Flag */ + +/** Bit definition for USART_DAT register **/ +#define USART_DAT_DATV ((uint32_t)0x000001FFU) /* Data value */ + +/** Bit definition for USART_BRCF register **/ +#define USART_BRCF_DIV_Decimal ((uint32_t)0x000FU) /* Fraction of USARTDIV */ +#define USART_BRCF_DIV_Integer ((uint32_t)0xFFF0U) /* Mantissa of USARTDIV */ + +/** Bit definition for USART_GTP register **/ +#define USART_GTP_PSCV ((uint32_t)0x00FFU) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GTP_PSCV_0 ((uint32_t)0x0001U) /* Bit 0 */ +#define USART_GTP_PSCV_1 ((uint32_t)0x0002U) /* Bit 1 */ +#define USART_GTP_PSCV_2 ((uint32_t)0x0004U) /* Bit 2 */ +#define USART_GTP_PSCV_3 ((uint32_t)0x0008U) /* Bit 3 */ +#define USART_GTP_PSCV_4 ((uint32_t)0x0010U) /* Bit 4 */ +#define USART_GTP_PSCV_5 ((uint32_t)0x0020U) /* Bit 5 */ +#define USART_GTP_PSCV_6 ((uint32_t)0x0040U) /* Bit 6 */ +#define USART_GTP_PSCV_7 ((uint32_t)0x0080U) /* Bit 7 */ + +#define USART_GTP_GTV ((uint32_t)0xFF00U) /* Guard time value */ + +/** Bit definition for USART_FIFO register **/ +#define USART_FIFO_EN ((uint32_t)0x00000001U) /* FIFO model enable */ +#define USART_FIFO_CLR ((uint32_t)0x00000002U) /* FIFO clear */ +#define USART_FIFO_TXFTCFG_MASK ((uint32_t)0x0000001CU) /* TXFIFO threshold configuration */ +#define USART_FIFO_RXFTCFG_MASK ((uint32_t)0x000000E0U) /* RXFIFO threshold configuration */ +#define USART_FIFO_TXFFIEN ((uint32_t)0x00000100U) /* TXFIFO full interrupt enable */ +#define USART_FIFO_RXFFIEN ((uint32_t)0x00000200U) /* RXFIFO full interrupt enable */ +#define USART_FIFO_TXFEIEN ((uint32_t)0x00000400U) /* TXFIFO empty interrupt enable */ +#define USART_FIFO_RXFEIEN ((uint32_t)0x00000800U) /* RXFIFO empty interrupt enable */ +#define USART_FIFO_RXFTIEN ((uint32_t)0x00001000U) /* RXFIFO threshold interrupt enable */ +#define USART_FIFO_TXFTIEN ((uint32_t)0x00002000U) /* TXFIFO threshold interrupt enable */ +#define USART_FIFO_RXCNT_MASK ((uint32_t)0x0003C000U) /* number of RXFIFO valid data mask */ +#define USART_FIFO_TXCNT_MASK ((uint32_t)0x003C0000U) /* number of TXFIFO valid data mask */ + +/** Bit definition for USART_IFW register **/ +#define USART_IFW_WIDTH_MASK ((uint32_t)0x0FFFFFFFU) /* Receiver timeout value */ + +/*** USB High Speed ***/ +/** Bit definition for USBHS_GCTRLSTS register **/ +#define USBHS_GCTRLSTS_VBVALOVEN_POS (2U) +#define USBHS_GCTRLSTS_VBVALOVEN ((uint32_t)0x00000004U) /* VBUS valid override enable */ +#define USBHS_GCTRLSTS_VBVALOVAL_POS (3U) +#define USBHS_GCTRLSTS_VBVALOVAL ((uint32_t)0x00000008U) /* VBUS valid override value */ +#define USBHS_GCTRLSTS_AVALOVEN_POS (4U) +#define USBHS_GCTRLSTS_AVALOVEN ((uint32_t)0x00000010U) /* A perpheral session valid override enable */ +#define USBHS_GCTRLSTS_AVALOVAL_POS (5U) +#define USBHS_GCTRLSTS_AVALOVAL ((uint32_t)0x00000020U) /* A perpheral session valid override value */ +#define USBHS_GCTRLSTS_BVALOVEN_POS (6U) +#define USBHS_GCTRLSTS_BVALOVEN ((uint32_t)0x00000040U) /* B perpheral session valid override enable */ +#define USBHS_GCTRLSTS_BVALOVAL_POS (7U) +#define USBHS_GCTRLSTS_BVALOVAL ((uint32_t)0x00000080U) /* B perpheral session valid override value */ +#define USBHS_GCTRLSTS_IDSTS_POS (16U) +#define USBHS_GCTRLSTS_IDSTS ((uint32_t)0x00010000U) /* ID pin status */ +#define USBHS_GCTRLSTS_DETIM_POS (17U) +#define USBHS_GCTRLSTS_DETIM ((uint32_t)0x00020000U) /* Debounce valid */ +#define USBHS_GCTRLSTS_ASVLD_POS (18U) +#define USBHS_GCTRLSTS_ASVLD ((uint32_t)0x00040000U) /* A session valid */ +#define USBHS_GCTRLSTS_BSVLD_POS (19U) +#define USBHS_GCTRLSTS_BSVLD ((uint32_t)0x00080000U) /* B session valid */ +#define USBHS_GCTRLSTS_CMODE_POS (21U) +#define USBHS_GCTRLSTS_CMODE ((uint32_t)0x00200000U) /* Current mode */ + + +/** Bit definition for USBHS_GAHBCFG register **/ +#define USBHS_GAHBCFG_GINTEN_POS (0U) +#define USBHS_GAHBCFG_GINTEN ((uint32_t)0x00000001U) +#define USBHS_GAHBCFG_BURSTTYP_POS (1U) +#define USBHS_GAHBCFG_BURSTTYP ((uint32_t)0x0000001EU) +#define USBHS_GAHBCFG_DMAEN_POS (5U) +#define USBHS_GAHBCFG_DMAEN ((uint32_t)0x00000020U) +#define USBHS_GAHBCFG_NPTXFETH_POS (7U) +#define USBHS_GAHBCFG_NPTXFETH ((uint32_t)0x00000080U) +#define USBHS_GAHBCFG_PTXFETH_POS (8U) +#define USBHS_GAHBCFG_PTXFETH ((uint32_t)0x00000100U) + +/** Bit definition for USBHS_GCFG register **/ +#define USBHS_GCFG_TOCAL_POS (0U) +#define USBHS_GCFG_TOCAL ((uint32_t)0x00000007U) +#define USBHS_GCFG_PHYIF_POS (3U) +#define USBHS_GCFG_PHYIF ((uint32_t)0x00000008U) +#define USBHS_GCFG_PHYSEL_POS (6U) +#define USBHS_GCFG_PHYSEL ((uint32_t)0x00000040U) +#define USBHS_GCFG_TRDTIM_POS (10U) +#define USBHS_GCFG_TRDTIM ((uint32_t)0x00003C00U) +#define USBHS_GCFG_FHMODE_POS (29U) +#define USBHS_GCFG_FHMODE ((uint32_t)0x20000000U) +#define USBHS_GCFG_FDMODE_POS (30U) +#define USBHS_GCFG_FDMODE ((uint32_t)0x40000000U) + +/** Bit definition for USBHS_GRSTCTRL register **/ +#define USBHS_GRSTCTRL_CSRST_POS (0U) +#define USBHS_GRSTCTRL_CSRST ((uint32_t)0x00000001U) +#define USBHS_GRSTCTRL_PFSSRST_POS (1U) +#define USBHS_GRSTCTRL_PFSSRST ((uint32_t)0x00000002U) +#define USBHS_GRSTCTRL_HFCRST_POS (2U) +#define USBHS_GRSTCTRL_HFCRST ((uint32_t)0x00000004U) +#define USBHS_GRSTCTRL_RXFFLSH_POS (4U) +#define USBHS_GRSTCTRL_RXFFLSH ((uint32_t)0x00000010U) +#define USBHS_GRSTCTRL_TXFFLSH_POS (5U) +#define USBHS_GRSTCTRL_TXFFLSH ((uint32_t)0x00000020U) +#define USBHS_GRSTCTRL_TXFNUM_POS (6U) +#define USBHS_GRSTCTRL_TXFNUM ((uint32_t)0x000007C0U) +#define USBHS_GRSTCTRL_SRSTDNE_POS (29U) +#define USBHS_GRSTCTRL_SRSTDNE ((uint32_t)0x20000000U) +#define USBHS_GRSTCTRL_DMAREQ_POS (30U) +#define USBHS_GRSTCTRL_DMAREQ ((uint32_t)0x40000000U) +#define USBHS_GRSTCTRL_AHBIDLE_POS (31U) +#define USBHS_GRSTCTRL_AHBIDLE ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_GINTSTS register **/ +#define USBHS_GINTSTS_CMODE_POS (0U) +#define USBHS_GINTSTS_CMODE ((uint32_t)0x00000001U) +#define USBHS_GINTSTS_MODMISIF_POS (1U) +#define USBHS_GINTSTS_MODMISIF ((uint32_t)0x00000002U) +#define USBHS_GINTSTS_SOFIF_POS (3U) +#define USBHS_GINTSTS_SOFIF ((uint32_t)0x00000008U) +#define USBHS_GINTSTS_RXFNEIF_POS (4U) +#define USBHS_GINTSTS_RXFNEIF ((uint32_t)0x00000010U) +#define USBHS_GINTSTS_NPTXFEIF_POS (5U) +#define USBHS_GINTSTS_NPTXFEIF ((uint32_t)0x00000020U) +#define USBHS_GINTSTS_GINNPNAKEIF_POS (6U) +#define USBHS_GINTSTS_GINNPNAKEIF ((uint32_t)0x00000040U) +#define USBHS_GINTSTS_GOUTNAKEIF_POS (7U) +#define USBHS_GINTSTS_GOUTNAKEIF ((uint32_t)0x00000080U) +#define USBHS_GINTSTS_ESUSPIF_POS (10U) +#define USBHS_GINTSTS_ESUSPIF ((uint32_t)0x00000400U) +#define USBHS_GINTSTS_USBSUSPIF_POS (11U) +#define USBHS_GINTSTS_USBSUSPIF ((uint32_t)0x00000800U) +#define USBHS_GINTSTS_USBRSTIF_POS (12U) +#define USBHS_GINTSTS_USBRSTIF ((uint32_t)0x00001000U) +#define USBHS_GINTSTS_ENUMDIF_POS (13U) +#define USBHS_GINTSTS_ENUMDIF ((uint32_t)0x00002000U) +#define USBHS_GINTSTS_ISOUTPDIF_POS (14U) +#define USBHS_GINTSTS_ISOUTPDIF ((uint32_t)0x00004000U) +#define USBHS_GINTSTS_EOPFIF_POS (15U) +#define USBHS_GINTSTS_EOPFIF ((uint32_t)0x00008000U) +#define USBHS_GINTSTS_INEPIF_POS (18U) +#define USBHS_GINTSTS_INEPIF ((uint32_t)0x00040000U) +#define USBHS_GINTSTS_OUTEPIF_POS (19U) +#define USBHS_GINTSTS_OUTEPIF ((uint32_t)0x00080000U) +#define USBHS_GINTSTS_ISOINCIF_POS (20U) +#define USBHS_GINTSTS_ISOINCIF ((uint32_t)0x00100000U) +#define USBHS_GINTSTS_PTNCIF_ISOUTNCIF_POS (21U) +#define USBHS_GINTSTS_PTNCIF_ISOUTNCIF ((uint32_t)0x00200000U) +#define USBHS_GINTSTS_FETSUSPIF_POS (22U) +#define USBHS_GINTSTS_FETSUSPIF ((uint32_t)0x00400000U) +#define USBHS_GINTSTS_RSTDIF_POS (23U) +#define USBHS_GINTSTS_RSTDIF ((uint32_t)0x00800000U) +#define USBHS_GINTSTS_HPIF_POS (24U) +#define USBHS_GINTSTS_HPIF ((uint32_t)0x01000000U) +#define USBHS_GINTSTS_HCHIF_POS (25U) +#define USBHS_GINTSTS_HCHIF ((uint32_t)0x02000000U) +#define USBHS_GINTSTS_PTXFEIF_POS (26U) +#define USBHS_GINTSTS_PTXFEIF ((uint32_t)0x04000000U) +#define USBHS_GINTSTS_IDSTSCIF_POS (28U) +#define USBHS_GINTSTS_IDSTSCIF ((uint32_t)0x10000000U) +#define USBHS_GINTSTS_DISCIF_POS (29U) +#define USBHS_GINTSTS_DISCIF ((uint32_t)0x20000000U) +#define USBHS_GINTSTS_WKUPIF_POS (31U) +#define USBHS_GINTSTS_WKUPIF ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_GINTEN register **/ +#define USBHS_GINTEN_MODMISIEN_POS (1U) +#define USBHS_GINTEN_MODMISIEN ((uint32_t)0x00000002U) +#define USBHS_GINTEN_USBHSIEN_POS (2U) +#define USBHS_GINTEN_USBHSIEN ((uint32_t)0x00000004U) +#define USBHS_GINTEN_SOFIEN_POS (3U) +#define USBHS_GINTEN_SOFIEN ((uint32_t)0x00000008U) +#define USBHS_GINTEN_RXFNEIEN_POS (4U) +#define USBHS_GINTEN_RXFNEIEN ((uint32_t)0x00000010U) +#define USBHS_GINTEN_NPTXFEIEN_POS (5U) +#define USBHS_GINTEN_NPTXFEIEN ((uint32_t)0x00000020U) +#define USBHS_GINTEN_GINNPNAKEIEN_POS (6U) +#define USBHS_GINTEN_GINNPNAKEIEN ((uint32_t)0x00000040U) +#define USBHS_GINTEN_GOUTNAKEIEN_POS (7U) +#define USBHS_GINTEN_GOUTNAKEIEN ((uint32_t)0x00000080U) +#define USBHS_GINTEN_ESUSPIEN_POS (10U) +#define USBHS_GINTEN_ESUSPIEN ((uint32_t)0x00000400U) +#define USBHS_GINTEN_USBSUSPIEN_POS (11U) +#define USBHS_GINTEN_USBSUSPIEN ((uint32_t)0x00000800U) +#define USBHS_GINTEN_USBRSTIEN_POS (12U) +#define USBHS_GINTEN_USBRSTIEN ((uint32_t)0x00001000U) +#define USBHS_GINTEN_ENUMDIEN_POS (13U) +#define USBHS_GINTEN_ENUMDIEN ((uint32_t)0x00002000U) +#define USBHS_GINTEN_ISOUTPDIEN_POS (14U) +#define USBHS_GINTEN_ISOUTPDIEN ((uint32_t)0x00004000U) +#define USBHS_GINTEN_EOPFIEN_POS (15U) +#define USBHS_GINTEN_EOPFIEN ((uint32_t)0x00008000U) +#define USBHS_GINTEN_INEPIEN_POS (18U) +#define USBHS_GINTEN_INEPIEN ((uint32_t)0x00040000U) +#define USBHS_GINTEN_OUTEPIEN_POS (19U) +#define USBHS_GINTEN_OUTEPIEN ((uint32_t)0x00080000U) +#define USBHS_GINTEN_ISOINCIEN_POS (20U) +#define USBHS_GINTEN_ISOINCIEN ((uint32_t)0x00100000U) +#define USBHS_GINTEN_PTNCIEN_ISOUTNCIEN_POS (21U) +#define USBHS_GINTEN_PTNCIEN_ISOUTNCIEN ((uint32_t)0x00200000U) +#define USBHS_GINTEN_FETSUSPIEN_POS (22U) +#define USBHS_GINTEN_FETSUSPIEN ((uint32_t)0x00400000U) +#define USBHS_GINTEN_RSTDIEN_POS (23U) +#define USBHS_GINTEN_RSTDIEN ((uint32_t)0x00800000U) +#define USBHS_GINTEN_HPIEN_POS (24U) +#define USBHS_GINTEN_HPIEN ((uint32_t)0x01000000U) +#define USBHS_GINTEN_HCHIEN_POS (25U) +#define USBHS_GINTEN_HCHIEN ((uint32_t)0x02000000U) +#define USBHS_GINTEN_PTXFEIEN_POS (26U) +#define USBHS_GINTEN_PTXFEIEN ((uint32_t)0x04000000U) +#define USBHS_GINTEN_IDSTSCIEN_POS (28U) +#define USBHS_GINTEN_IDSTSCIEN ((uint32_t)0x10000000U) +#define USBHS_GINTEN_DISCIEN_POS (29U) +#define USBHS_GINTEN_DISCIEN ((uint32_t)0x20000000U) +#define USBHS_GINTEN_VBUSVIF_POS (30U) +#define USBHS_GINTEN_VBUSVIF ((uint32_t)0x40000000U) +#define USBHS_GINTEN_WKUPIEN_POS (31U) +#define USBHS_GINTEN_WKUPIEN ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_GRXSTS/USBHS_GRXSTSP register **/ +#define USBHS_GRXSTS_CHEPNUM_POS (0U) +#define USBHS_GRXSTS_CHEPNUM ((uint32_t)0x0000000FU) +#define USBHS_GRXSTS_BCNT_POS (4U) +#define USBHS_GRXSTS_BCNT ((uint32_t)0x00007FF0U) +#define USBHS_GRXSTS_DPID_POS (15U) +#define USBHS_GRXSTS_DPID ((uint32_t)0x00018000U) +#define USBHS_GRXSTS_PKTSTS_POS (17U) +#define USBHS_GRXSTS_PKTSTS ((uint32_t)0x001E0000U) +#define USBHS_GRXSTS_FUNM_POS (21U) +#define USBHS_GRXSTS_FUNM ((uint32_t)0x01E00000U) + +/** Bit definition for USBHS_GRXFSIZ register **/ +#define USBHS_GRXFSIZ_RXFDEP ((uint32_t)0x000007FFU) + +/** Bit definition for USBHS_HNPTXFSIZ register **/ +#define USBHS_HNPTXFSIZ_NPTXFSADD_POS (0U) +#define USBHS_HNPTXFSIZ_NPTXFSADD ((uint32_t)0x000007FFU) +#define USBHS_HNPTXFSIZ_IEP0TXFDEP_POS (16U) +#define USBHS_HNPTXFSIZ_IEP0TXFDEP ((uint32_t)0x07FF0000U) + +/** Bit definition for USBHS_DINEP0TXSIZ register **/ +#define USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS (0U) +#define USBHS_DINEP0TXSIZ_IEP0TXFRSADD ((uint32_t)0x000007FFU) +#define USBHS_DINEP0TXSIZ_NPTXFDEP_POS (16U) +#define USBHS_DINEP0TXSIZ_NPTXFDEP ((uint32_t)0x07FF0000U) + +/** Bit definition for USBHS_GNPTXFSTS register **/ +#define USBHS_GNPTXFSTS_NPTXFSAV_POS (0U) +#define USBHS_GNPTXFSTS_NPTXFSAV ((uint32_t)0x0000FFFFU) +#define USBHS_GNPTXFSTS_NPTXRQSAV_POS (16U) +#define USBHS_GNPTXFSTS_NPTXRQSAV ((uint32_t)0x00FF0000U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_POS (24U) +#define USBHS_GNPTXFSTS_NPTXRQTOP ((uint32_t)0x7F000000U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_END_POS (24U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_END ((uint32_t)0x01000000U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_TOKEN_POS (25U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_TOKEN ((uint32_t)0x06000000U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_CHNUM_POS (27U) +#define USBHS_GNPTXFSTS_NPTXRQTOP_CHNUM ((uint32_t)0x78000000U) + +/** Bit definition for USBHS_CID register **/ +#define USBHS_CID ((uint32_t)0xFFFFFFFFU) + +/** Bit definition for USBHS_GPD register **/ +#define USBHS_GPD_LINSTSCHNGSTS_POS (7U) +#define USBHS_GPD_LINSTSCHNGSTS ((uint32_t)0x00000080U) +#define USBHS_GPD_LINSTSCHNGINTEN_POS (8U) +#define USBHS_GPD_LINSTSCHNGINTEN ((uint32_t)0x00000100U) +#define USBHS_GPD_RESTDETSTS_POS (9U) +#define USBHS_GPD_RESTDETSTS ((uint32_t)0x00000200U) +#define USBHS_GPD_RESTDETINTEN_POS (10U) +#define USBHS_GPD_RESTDETINTEN ((uint32_t)0x00000400U) +#define USBHS_GPD_DISCONNDETSTS_POS (11U) +#define USBHS_GPD_DISCONNDETSTS ((uint32_t)0x00000800U) +#define USBHS_GPD_DISCONNDETINTEN_POS (12U) +#define USBHS_GPD_DISCONNDETINTEN ((uint32_t)0x00001000U) +#define USBHS_GPD_CONNDETSTS_POS (13U) +#define USBHS_GPD_CONNDETSTS ((uint32_t)0x00002000U) +#define USBHS_GPD_CONNDETINTEN_POS (14U) +#define USBHS_GPD_CONNDETINTEN ((uint32_t)0x00004000U) +#define USBHS_GPD_STSCHNGINTSTS_POS (17U) +#define USBHS_GPD_STSCHNGINTSTS ((uint32_t)0x00020000U) +#define USBHS_GPD_STSCHNGINTEN_POS (18U) +#define USBHS_GPD_STSCHNGINTEN ((uint32_t)0x00040000U) +#define USBHS_GPD_LINSTS_POS (19U) +#define USBHS_GPD_LINSTS ((uint32_t)0x00180000U) +#define USBHS_GPD_IDDIG_POS (21U) +#define USBHS_GPD_IDDIG ((uint32_t)0x00200000U) + +/** Bit definition for USBHS_HPTXFSIZ register **/ +#define USBHS_HPTXFSIZ_HPTXFSADD_POS (0U) +#define USBHS_HPTXFSIZ_HPTXFSADD ((uint32_t)0x0000FFFFU) +#define USBHS_HPTXFSIZ_HPTXFDEP_POS (16U) +#define USBHS_HPTXFSIZ_HPTXFDEP ((uint32_t)0xFFFF0000U) + +/** Bit definition for USBHS_DINEPPTXFSIZ1/2/3/4/5/6/7/8 register **/ +#define USBHS_DINEPPTXFSIZ_INEPTXSADD_POS (0U) +#define USBHS_DINEPPTXFSIZ_INEPTXSADD ((uint32_t)0x0000FFFFU) +#define USBHS_DINEPPTXFSIZ_INEPTXFDEP_POS (16U) +#define USBHS_DINEPPTXFSIZ_INEPTXFDEP ((uint32_t)0xFFFF0000U) + +/** Bit definition for USBHS_HCFG register **/ +#define USBHS_HCFG_SPSEL_POS (2U) +#define USBHS_HCFG_SPSEL ((uint32_t)0x00000004U) + +/** Bit definition for USBHS_HFRI register **/ +#define USBHS_HFRI_FRI_POS (0U) +#define USBHS_HFRI_FRI ((uint32_t)0x0000FFFFU) +#define USBHS_HFRI_DRLDEN_POS (16U) +#define USBHS_HFRI_DRLDEN ((uint32_t)0x00010000U) + +/** Bit definition for USBHS_HFNUM register **/ +#define USBHS_HFNUM_FRNUM_POS (0U) +#define USBHS_HFNUM_FRNUM ((uint32_t)0x0000FFFFU) +#define USBHS_HFNUM_FRT_POS (16U) +#define USBHS_HFNUM_FRT ((uint32_t)0xFFFF0000U) + +/** Bit definition for USBHS_HPTXFQSTS register **/ +#define USBHS_HPTXFQSTS_PTXFSAVL_POS (0U) +#define USBHS_HPTXFQSTS_PTXFSAVL ((uint32_t)0x0000FFFFU) +#define USBHS_HPTXFQSTS_PTXRQSAV_POS (16U) +#define USBHS_HPTXFQSTS_PTXRQSAV ((uint32_t)0x007F0000U) +#define USBHS_HPTXFQSTS_PTXRQTOP_POS (23U) +#define USBHS_HPTXFQSTS_PTXRQTOP ((uint32_t)0xFF800000U) +#define USBHS_HPTXFQSTS_PTXRQTOP_END_POS (23U) +#define USBHS_HPTXFQSTS_PTXRQTOP_END ((uint32_t)0x00800000U) +#define USBHS_HPTXFQSTS_PTXRQTOP_PEND_POS (24U) +#define USBHS_HPTXFQSTS_PTXRQTOP_PEND ((uint32_t)0x01000000U) +#define USBHS_HPTXFQSTS_PTXRQTOP_TOKEN_POS (25U) +#define USBHS_HPTXFQSTS_PTXRQTOP_TOKEN ((uint32_t)0x06000000U) +#define USBHS_HPTXFQSTS_PTXRQTOP_CHNUM_POS (27U) +#define USBHS_HPTXFQSTS_PTXRQTOP_CHNUM ((uint32_t)0x78000000U) +#define USBHS_HPTXFQSTS_PTXRQTOP_OEFRM_POS (31U) +#define USBHS_HPTXFQSTS_PTXRQTOP_OEFRM ((uint32_t)0x80000000U) + + + +/** Bit definition for USBHS_HACHINT register **/ +#define USBHS_HACHINT_POS (0U) +#define USBHS_HACHINT ((uint32_t)0x0000FFFFU) + +/** Bit definition for USBHS_HACHINTEN register **/ +#define USBHS_HACHINTEN_POS (0U) +#define USBHS_HACHINTEN ((uint32_t)0x0000FFFFU) + +/** Bit definition for USBHS_HPCS register **/ +#define USBHS_HPCS_PCSTS_POS (0U) +#define USBHS_HPCS_PCSTS ((uint32_t)0x00000001U) +#define USBHS_HPCS_PCDET_POS (1U) +#define USBHS_HPCS_PCDET ((uint32_t)0x00000002U) +#define USBHS_HPCS_PEN_POS (2U) +#define USBHS_HPCS_PEN ((uint32_t)0x00000004U) +#define USBHS_HPCS_PENC_POS (3U) +#define USBHS_HPCS_PENC ((uint32_t)0x00000008U) +#define USBHS_HPCS_POCA_POS (4U) +#define USBHS_HPCS_POCA ((uint32_t)0x00000010U) +#define USBHS_HPCS_POCC_POS (5U) +#define USBHS_HPCS_POCC ((uint32_t)0x00000020U) +#define USBHS_HPCS_PRES_POS (6U) +#define USBHS_HPCS_PRES ((uint32_t)0x00000040U) +#define USBHS_HPCS_PSUSP_POS (7U) +#define USBHS_HPCS_PSUSP ((uint32_t)0x00000080U) +#define USBHS_HPCS_PRST_POS (8U) +#define USBHS_HPCS_PRST ((uint32_t)0x00000100U) +#define USBHS_HPCS_PLSTS_POS (10U) +#define USBHS_HPCS_PLSTS ((uint32_t)0x00000C00U) +#define USBHS_HPCS_PPWR_POS (12U) +#define USBHS_HPCS_PPWR ((uint32_t)0x00001000U) +#define USBHS_HPCS_PTCTRL_POS (13U) +#define USBHS_HPCS_PTCTRL ((uint32_t)0x0001E000U) +#define USBHS_HPCS_PSPD_POS (17U) +#define USBHS_HPCS_PSPD ((uint32_t)0x00060000U) + +/** Bit definition for USBHS_HCHCTRL(0~15) register **/ +#define USBHS_HCHCTRL_MPS_POS (0U) +#define USBHS_HCHCTRL_MPS ((uint32_t)0x000007FFU) +#define USBHS_HCHCTRL_EPNUM_POS (11U) +#define USBHS_HCHCTRL_EPNUM ((uint32_t)0x00007800U) +#define USBHS_HCHCTRL_EPDIR_POS (15U) +#define USBHS_HCHCTRL_EPDIR ((uint32_t)0x00008000U) +#define USBHS_HCHCTRL_LSPDDEV_POS (17U) +#define USBHS_HCHCTRL_LSPDDEV ((uint32_t)0x00020000U) +#define USBHS_HCHCTRL_EPTYPE_POS (18U) +#define USBHS_HCHCTRL_EPTYPE ((uint32_t)0x000C0000U) +#define USBHS_HCHCTRL_DEVADDR_POS (22U) +#define USBHS_HCHCTRL_DEVADR ((uint32_t)0x1FC00000U) +#define USBHS_HCHCTRL_ODDFRM_POS (29U) +#define USBHS_HCHCTRL_ODDFRM ((uint32_t)0x20000000U) +#define USBHS_HCHCTRL_CHDIS_POS (30U) +#define USBHS_HCHCTRL_CHDIS ((uint32_t)0x40000000U) +#define USBHS_HCHCTRL_CHEN_POS (31U) +#define USBHS_HCHCTRL_CHEN ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_HCHSCTRL(0~15) register **/ +#define USBHS_HCHSCTRL_PRTADD_POS (0U) +#define USBHS_HCHSCTRL_PRTADD ((uint32_t)0x0000007FU) +#define USBHS_HCHSCTRL_HUBADD_POS (7U) +#define USBHS_HCHSCTRL_HUBADD ((uint32_t)0x00003FC0U) +#define USBHS_HCHSCTRL_TRANPOS_POS (14U) +#define USBHS_HCHSCTRL_TRANPOS ((uint32_t)0x0000C000U) +#define USBHS_HCHSCTRL_COMPSPLF_POS (16U) +#define USBHS_HCHSCTRL_COMPSPLF ((uint32_t)0x00010000U) +#define USBHS_HCHCTRL_SPLEN_POS (31U) +#define USBHS_HCHCTRL_SPLEN ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_HCINTSTS(0~15) register **/ +#define USBHS_HCHINTSTS_TXCFIF_POS (0U) +#define USBHS_HCHINTSTS_TXCFIF ((uint32_t)0x00000001U) +#define USBHS_HCHINTSTS_CHHTDIF_POS (1U) +#define USBHS_HCHINTSTS_CHHTDIF ((uint32_t)0x00000002U) +#define USBHS_HCHINTSTS_AHBERRIF_POS (2U) +#define USBHS_HCHINTSTS_AHBERRIF ((uint32_t)0x00000004U) +#define USBHS_HCHINTSTS_STALLIF_POS (3U) +#define USBHS_HCHINTSTS_STALLIF ((uint32_t)0x00000008U) +#define USBHS_HCHINTSTS_NAKIF_POS (4U) +#define USBHS_HCHINTSTS_NAKIF ((uint32_t)0x00000010U) +#define USBHS_HCHINTSTS_ACKIF_POS (5U) +#define USBHS_HCHINTSTS_ACKIF ((uint32_t)0x00000020U) +#define USBHS_HCHINTSTS_NYETIF_POS (6U) +#define USBHS_HCHINTSTS_NYETIF ((uint32_t)0x00000040U) +#define USBHS_HCHINTSTS_TXERRIF_POS (7U) +#define USBHS_HCHINTSTS_TXERRIF ((uint32_t)0x00000080U) +#define USBHS_HCHINTSTS_BBERRIF_POS (8U) +#define USBHS_HCHINTSTS_BBERRIF ((uint32_t)0x00000100U) +#define USBHS_HCHINTSTS_FOVRIF_POS (9U) +#define USBHS_HCHINTSTS_FOVRIF ((uint32_t)0x00000200U) +#define USBHS_HCHINTSTS_DTERRIF_POS (10U) +#define USBHS_HCHINTSTS_DTERRIF ((uint32_t)0x00000400U) + +/** Bit definition for USBHS_HCHINTEN(0~15) register **/ +#define USBHS_HCHINTEN_TXCIEN_POS (0U) +#define USBHS_HCHINTEN_TXCIEN ((uint32_t)0x00000001U) +#define USBHS_HCHINTEN_CHHTDIEN_POS (1U) +#define USBHS_HCHINTEN_CHHTDIEN ((uint32_t)0x00000002U) +#define USBHS_HCHINTEN_AHBERRIEN_POS (2U) +#define USBHS_HCHINTEN_AHBERRIEN ((uint32_t)0x00000004U) +#define USBHS_HCHINTEN_STALLIEN_POS (3U) +#define USBHS_HCHINTEN_STALLIEN ((uint32_t)0x00000008U) +#define USBHS_HCHINTEN_NAKIEN_POS (4U) +#define USBHS_HCHINTEN_NAKIEN ((uint32_t)0x00000010U) +#define USBHS_HCHINTEN_ACKIEN_POS (5U) +#define USBHS_HCHINTEN_ACKIEN ((uint32_t)0x00000020U) +#define USBHS_HCHINTEN_NYETIEN_POS (6U) +#define USBHS_HCHINTEN_NYETIEN ((uint32_t)0x00000020U) +#define USBHS_HCHINTEN_TXERRIEN_POS (7U) +#define USBHS_HCHINTEN_TXERRIEN ((uint32_t)0x00000080U) +#define USBHS_HCHINTEN_BBERRIEN_POS (8U) +#define USBHS_HCHINTEN_BBERRIEN ((uint32_t)0x00000100U) +#define USBHS_HCHINTEN_FOVRIEN_POS (9U) +#define USBHS_HCHINTEN_FOVRIEN ((uint32_t)0x00000200U) +#define USBHS_HCHINTEN_DTERRIEN_POS (10U) +#define USBHS_HCHINTEN_DTERRIEN ((uint32_t)0x00000400U) + +/** Bit definition for USBHS_HCHTXSIZ(0~15) register **/ +#define USBHS_HCHTXSIZ_TXSIZ_POS (0U) +#define USBHS_HCHTXSIZ_TXSIZ ((uint32_t)0x0007FFFFU) +#define USBHS_HCHTXSIZ_PKCNT_POS (19U) +#define USBHS_HCHTXSIZ_PKCNT ((uint32_t)0x1FF80000U) +#define USBHS_HCHTXSIZ_PID_POS (29U) +#define USBHS_HCHTXSIZ_PID ((uint32_t)0x60000000U) +#define USBHS_HCHCTRL_DPING_POS (31U) +#define USBHS_HCHCTRL_DPING ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_HCDMA(0~15) register **/ +#define USBHS_HCDMA ((uint32_t)0xFFFFFFFFU) + +/** Bit definition for USBHS_DCFG register **/ +#define USBHS_DCFG_DEVSPD_POS (0U) +#define USBHS_DCFG_DEVSPD ((uint32_t)0x00000003U) +#define USBHS_DCFG_NZLSOUTHSK_POS (2U) +#define USBHS_DCFG_NZLSOUTHSK ((uint32_t)0x00000004U) +#define USBHS_DCFG_DEVARR_POS (4U) +#define USBHS_DCFG_DEVARR ((uint32_t)0x000007F0U) +#define USBHS_DCFG_PFRITVL_POS (11U) +#define USBHS_DCFG_PFRITVL ((uint32_t)0x00001800U) +#define USBHS_DCFG_XCVDRLY_POS (14U) +#define USBHS_DCFG_XCVDRLY ((uint32_t)0x00004000U) +#define USBHS_DCFG_EERRAIEN_POS (15U) +#define USBHS_DCFG_EERRAIEN ((uint32_t)0x00008000U) +#define USBHS_DCFG_PSITVL_POS (24U) +#define USBHS_DCFG_PSITVL ((uint32_t)0x03000000U) + +/** Bit definition for USBHS_DCTRL register **/ +#define USBHS_DCTRL_RMWKUP_POS (0U) +#define USBHS_DCTRL_RMWKUP ((uint32_t)0x00000001U) +#define USBHS_DCTRL_SFTDIS_POS (1U) +#define USBHS_DCTRL_SFTDIS ((uint32_t)0x00000002U) +#define USBHS_DCTRL_GINAKSTS_POS (2U) +#define USBHS_DCTRL_GINAKSTS ((uint32_t)0x00000004U) +#define USBHS_DCTRL_GONAKSTS_POS (3U) +#define USBHS_DCTRL_GONAKSTS ((uint32_t)0x00000008U) +#define USBHS_DCTRL_TSCTRL_POS (4U) +#define USBHS_DCTRL_TSCTRL ((uint32_t)0x00000070U) +#define USBHS_DCTRL_SGINAK_POS (7U) +#define USBHS_DCTRL_SGINAK ((uint32_t)0x00000080U) +#define USBHS_DCTRL_CGNPINAK_POS (8U) +#define USBHS_DCTRL_CGNPINAK ((uint32_t)0x00000100U) +#define USBHS_DCTRL_SGONAK_POS (9U) +#define USBHS_DCTRL_SGONAK ((uint32_t)0x00000200U) +#define USBHS_DCTRL_CGONAK_POS (10U) +#define USBHS_DCTRL_CGONAK ((uint32_t)0x00000400U) +#define USBHS_DCTRL_POPDNE_POS (11U) +#define USBHS_DCTRL_POPDNE ((uint32_t)0x00000800U) +#define USBHS_DCTRL_NAKOBBLE_POS (16U) +#define USBHS_DCTRL_NAKOBBLE ((uint32_t)0x00010000U) + +/** Bit definition for USBHS_DSTS register **/ +#define USBHS_DSTS_SUSPF_POS (0U) +#define USBHS_DSTS_SUSPF ((uint32_t)0x00000001U) +#define USBHS_DSTS_ENUMSPD_POS (1U) +#define USBHS_DSTS_ENUMSPD ((uint32_t)0x00000006U) +#define USBHS_DSTS_ERERRF_POS (3U) +#define USBHS_DSTS_ERERRF ((uint32_t)0x00000008U) +#define USBHS_DSTS_SOFFN_POS (8U) +#define USBHS_DSTS_SOFFN ((uint32_t)0x003FFF00U) +#define USBHS_DSTS_DEVLINSTS_POS (22U) +#define USBHS_DSTS_DEVLINSTS ((uint32_t)0x00C00000U) + +/** Bit definition for USBHS_DINEPINTEN register **/ +#define USBHS_DINEPINTEN_TXCIEN_POS (0U) +#define USBHS_DINEPINTEN_TXCIEN ((uint32_t)0x00000001U) +#define USBHS_DINEPINTEN_EPDIEN_POS (1U) +#define USBHS_DINEPINTEN_EPDIEN ((uint32_t)0x00000002U) +#define USBHS_DINEPINTEN_AHBERRIEN_POS (2U) +#define USBHS_DINEPINTEN_AHBERRIEN ((uint32_t)0x00000004U) +#define USBHS_DINEPINTEN_TOIEN_POS (3U) +#define USBHS_DINEPINTEN_TOIEN ((uint32_t)0x00000008U) +#define USBHS_DINEPINTEN_TXFERINTKIEN_POS (4U) +#define USBHS_DINEPINTEN_TXFERINTKIEN ((uint32_t)0x00000010U) +#define USBHS_DINEPINTEN_INTREPMISIEN_POS (5U) +#define USBHS_DINEPINTEN_INTREPMISIEN ((uint32_t)0x00000020U) +#define USBHS_DINEPINTEN_INEPNAKEIEN_POS (6U) +#define USBHS_DINEPINTEN_INEPNAKEIEN ((uint32_t)0x00000040U) +#define USBHS_DINEPINTEN_TXFUDIEN_POS (8U) +#define USBHS_DINEPINTEN_TXFUDIEN ((uint32_t)0x00000100U) +#define USBHS_DINEPINTEN_NAKIEN_POS (13U) +#define USBHS_DINEPINTEN_NAKIEN ((uint32_t)0x00002000U) + +/** Bit definition for USBHS_DOUTEPINTEN register **/ +#define USBHS_DOUTEPINTEN_TXCIEN_POS (0U) +#define USBHS_DOUTEPINTEN_TXCIEN ((uint32_t)0x00000001U) +#define USBHS_DOUTEPINTEN_EPDIEN_POS (1U) +#define USBHS_DOUTEPINTEN_EPDIEN ((uint32_t)0x00000002U) +#define USBHS_DOUTEPINTEN_AHBERRIEN_POS (2U) +#define USBHS_DOUTEPINTEN_AHBERRIEN ((uint32_t)0x00000004U) +#define USBHS_DOUTEPINTEN_STUPDNEIEN_POS (3U) +#define USBHS_DOUTEPINTEN_STUPDNEIEN ((uint32_t)0x00000008U) +#define USBHS_DOUTEPINTEN_EPDISROTIEN_POS (4U) +#define USBHS_DOUTEPINTEN_EPDISROTIEN ((uint32_t)0x00000010U) +#define USBHS_DOUTEPINTEN_B2BSTUPIEN_POS (6U) +#define USBHS_DOUTEPINTEN_B2BSTUPIEN ((uint32_t)0x00000040U) +#define USBHS_DOUTEPINTEN_OPERRIEN_POS (8U) +#define USBHS_DOUTEPINTEN_OPERRIEN ((uint32_t)0x00000100U) +#define USBHS_DOUTEPINTEN_BERRIEN_POS (12U) +#define USBHS_DOUTEPINTEN_BERRIEN ((uint32_t)0x00001000U) +#define USBHS_DOUTEPINTEN_NAKIEN_POS (13U) +#define USBHS_DOUTEPINTEN_NAKIEN ((uint32_t)0x00002000U) +#define USBHS_DOUTEPINTEN_NYETIEN_POS (14U) +#define USBHS_DOUTEPINTEN_NYETIEN ((uint32_t)0x00004000U) + +/** Bit definition for USBHS_DAEPINTSTS register **/ +#define USBHS_DAEPINTSTS_INEPINT_POS (0U) +#define USBHS_DAEPINTSTS_IEPINT ((uint32_t)0x000001FFU) +#define USBHS_DAEPINTSTS_OUTEPINT_POS (16U) +#define USBHS_DAEPINTSTS_OUTEPINT ((uint32_t)0x01FF0000U) + +/** Bit definition for USBHS_DAEPINTEN register **/ +#define USBHS_DAEPINTEN_INEPIEN_POS (0U) +#define USBHS_DAEPINTEN_INEPIEN ((uint32_t)0x000001FFU) +#define USBHS_DAEPINTEN_OUTEPIEN_POS (16U) +#define USBHS_DAEPINTEN_OUTEPIEN ((uint32_t)0x01FF0000U) + +/** Bit definition for USBHS_DTHRCTRL register **/ +#define USBHS_DTHRCTRL_NISOINEPTHREN_POS (0U) +#define USBHS_DTHRCTRL_NISOINEPTHREN ((uint32_t)0x00000001U) +#define USBHS_DTHRCTRL_ISOINEPTHREN_POS (1U) +#define USBHS_DTHRCTRL_ISOINEPTHREN ((uint32_t)0x00000002U) +#define USBHS_DTHRCTRL_TXTHRLEN_POS (2U) +#define USBHS_DTHRCTRL_TXTHRLEN ((uint32_t)0x000007FCU) +#define USBHS_DTHRCTRL_RXTHREN_POS (16U) +#define USBHS_DTHRCTRL_RXTHREN ((uint32_t)0x00010000U) +#define USBHS_DTHRCTRL_RXTHRLEN_POS (17U) +#define USBHS_DTHRCTRL_RXTHRLEN ((uint32_t)0x03FE0000U) +#define USBHS_DTHRCTRL_ARPEN_POS (27U) +#define USBHS_DTHRCTRL_ARPEN ((uint32_t)0x08000000U) + +/** Bit definition for USBHS_DINEPFEINTEN register **/ +#define USBHS_DINEPFEINTEN_INEPTXFEIEN ((uint32_t)0x0000FFFFU) + +/** Bit definition for USBHS_DEEPINTSTS register **/ +#define USBHS_DEEPINTSTS_INEPINT_POS (0U) +#define USBHS_DEEPINTSTS_IEPINT ((uint32_t)0x000000FFU) +#define USBHS_DEEPINTSTS_OUTEPINT_POS (16U) +#define USBHS_DEEPINTSTS_OUTEPINT ((uint32_t)0x00FF0000U) + +/** Bit definition for USBHS_DEEPINTEN register **/ +#define USBHS_DEEPINTEN_INEPIEN_POS (0U) +#define USBHS_DEEPINTEN_INEPIEN ((uint32_t)0x000000FFU) +#define USBHS_DEEPINTEN_OUTEPIEN_POS (16U) +#define USBHS_DEEPINTEN_OUTEPIEN ((uint32_t)0x00FF0000U) + +/** Bit definition for USBHS_DINEPXINTEN(0~8) register **/ +#define USBHS_DINEPXINTEN_TXCIEN_POS (0U) +#define USBHS_DINEPXINTEN_TXCIEN ((uint32_t)0x00000001U) +#define USBHS_DINEPXINTEN_EPDISIEN_POS (1U) +#define USBHS_DINEPXINTEN_EPDISIEN ((uint32_t)0x00000002U) +#define USBHS_DINEPXINTEN_AHBERRIEN_POS (2U) +#define USBHS_DINEPXINTEN_AHBERRIEN ((uint32_t)0x00000004U) +#define USBHS_DINEPXINTEN_TOIEN_POS (3U) +#define USBHS_DINEPXINTEN_TOIEN ((uint32_t)0x00000008U) +#define USBHS_DINEPXINTEN_TXFERINTKIEN_POS (4U) +#define USBHS_DINEPXINTEN_TXFERINTKIEN ((uint32_t)0x00000010U) +#define USBHS_DINEPXINTEN_INTREPMISIEN_POS (5U) +#define USBHS_DINEPXINTEN_INTREPMISIEN ((uint32_t)0x00000020U) +#define USBHS_DINEPXINTEN_INEPNAKEIEN_POS (6U) +#define USBHS_DINEPXINTEN_INEPNAKEIEN ((uint32_t)0x00000040U) +#define USBHS_DINEPXINTEN_TXFUDIEN_POS (8U) +#define USBHS_DINEPXINTEN_TXFUDIEN ((uint32_t)0x00000100U) +#define USBHS_DINEPXINTEN_NAKIEN_POS (13U) +#define USBHS_DINEPXINTEN_NAKIEN ((uint32_t)0x00002000U) + +/** Bit definition for USBHS_DOUTEPXINTEN(0~8) register **/ +#define USBHS_DOUTEPXINTEN_TXCIEN_POS (0U) +#define USBHS_DOUTEPXINTEN_TXCIEN ((uint32_t)0x00000001U) +#define USBHS_DOUTEPXINTEN_EPDIEN_POS (1U) +#define USBHS_DOUTEPXINTEN_EPDIEN ((uint32_t)0x00000002U) +#define USBHS_DOUTEPXINTEN_AHBERRIEN_POS (2U) +#define USBHS_DOUTEPXINTEN_AHBERRIEN ((uint32_t)0x00000004U) +#define USBHS_DOUTEPXINTEN_STUPDNEIEN_POS (3U) +#define USBHS_DOUTEPXINTEN_STUPDNEIEN ((uint32_t)0x00000008U) +#define USBHS_DOUTEPXINTEN_EPDISROTIEN_POS (4U) +#define USBHS_DOUTEPXINTEN_EPDISROTIEN ((uint32_t)0x00000010U) +#define USBHS_DOUTEPXINTEN_B2BSTUPIEN_POS (6U) +#define USBHS_DOUTEPXINTEN_B2BSTUPIEN ((uint32_t)0x00000040U) +#define USBHS_DOUTEPXINTEN_OPERRIEN_POS (8U) +#define USBHS_DOUTEPXINTEN_OPERRIEN ((uint32_t)0x00000100U) +#define USBHS_DOUTEPXINTEN_BERRIEN_POS (12U) +#define USBHS_DOUTEPXINTEN_BERRIEN ((uint32_t)0x00001000U) +#define USBHS_DOUTEPXINTEN_NAKIEN_POS (13U) +#define USBHS_DOUTEPXINTEN_NAKIEN ((uint32_t)0x00002000U) +#define USBHS_DOUTEPXINTEN_NYETIEN_POS (14U) +#define USBHS_DOUTEPXINTEN_NYETIEN ((uint32_t)0x00004000U) + +/** Bit definition for USBHS_DINEP0CTRL register **/ +#define USBHS_DINEP0CTRL_MPLEN_POS (0U) +#define USBHS_DINEP0CTRL_MPLEN ((uint32_t)0x00000003U) +#define USBHS_DINEP0CTRL_EPACT_POS (15U) +#define USBHS_DINEP0CTRL_EPACT ((uint32_t)0x00008000U) +#define USBHS_DINEP0CTRL_NAKSTS_POS (17U) +#define USBHS_DINEP0CTRL_NAKSTS ((uint32_t)0x00020000U) +#define USBHS_DINEP0CTRL_EPTYPE_POS (18U) +#define USBHS_DINEP0CTRL_EPTYPE ((uint32_t)0x000C0000U) +#define USBHS_DINEP0CTRL_STALL_POS (21U) +#define USBHS_DINEP0CTRL_STALL ((uint32_t)0x00200000U) +#define USBHS_DINEP0CTRL_TXFNUM_POS (22U) +#define USBHS_DINEP0CTRL_TXFNUM ((uint32_t)0x03C00000U) +#define USBHS_DINEP0CTRL_CNAK_POS (26U) +#define USBHS_DINEP0CTRL_CNAK ((uint32_t)0x04000000U) +#define USBHS_DINEP0CTRL_SNAK_POS (27U) +#define USBHS_DINEP0CTRL_SNAK ((uint32_t)0x08000000U) +#define USBHS_DINEP0CTRL_EPDIS_POS (30U) +#define USBHS_DINEP0CTRL_EPDIS ((uint32_t)0x40000000U) +#define USBHS_DINEP0CTRL_EPEN_POS (31U) +#define USBHS_DINEP0CTRL_EPEN ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_DINEPCTRL(1~8) register **/ +#define USBHS_DINEPCTRL_MPLEN_POS (0U) +#define USBHS_DINEPCTRL_MPLEN ((uint32_t)0x000007FFU) +#define USBHS_DINEPCTRL_EPACT_POS (15U) +#define USBHS_DINEPCTRL_EPACT ((uint32_t)0x00008000U) +#define USBHS_DINEPCTRL_EPDPID_EPEOFRM_POS (16U) +#define USBHS_DINEPCTRL_EPDPID_EPEOFRM ((uint32_t)0x00010000U) +#define USBHS_DINEPCTRL_NAKSTS_POS (17U) +#define USBHS_DINEPCTRL_NAKSTS ((uint32_t)0x00020000U) +#define USBHS_DINEPCTRL_EPTYPE_POS (18U) +#define USBHS_DINEPCTRL_EPTYPE ((uint32_t)0x000C0000U) +#define USBHS_DINEPCTRL_STALL_POS (21U) +#define USBHS_DINEPCTRL_STALL ((uint32_t)0x00200000U) +#define USBHS_DINEPCTRL_TXFNUM_POS (22U) +#define USBHS_DINEPCTRL_TXFNUM ((uint32_t)0x03C00000U) +#define USBHS_DINEPCTRL_CNAK_POS (26U) +#define USBHS_DINEPCTRL_CNAK ((uint32_t)0x04000000U) +#define USBHS_DINEPCTRL_SNAK_POS (27U) +#define USBHS_DINEPCTRL_SNAK ((uint32_t)0x08000000U) +#define USBHS_DINEPCTRL_SD0PID_SEVNFRM_POS (28U) +#define USBHS_DINEPCTRL_SD0PID_SEVNFRM ((uint32_t)0x10000000U) +#define USBHS_DINEPCTRL_SD1PID_SODDFRM_POS (29U) +#define USBHS_DINEPCTRL_SD1PID_SODDFRM ((uint32_t)0x20000000U) +#define USBHS_DINEPCTRL_EPDIS_POS (30U) +#define USBHS_DINEPCTRL_EPDIS ((uint32_t)0x40000000U) +#define USBHS_DINEPCTRL_EPEN_POS (31U) +#define USBHS_DINEPCTRL_EPEN ((uint32_t)0x80000000U) + +/** Bit definition for USBHS_DINEPINTSTS(0~8) register **/ +#define USBHS_DINEPINTSTS_TXCIF_POS (0U) +#define USBHS_DINEPINTSTS_TXCIF ((uint32_t)0x00000001U) +#define USBHS_DINEPINTSTS_EPDISIF_POS (1U) +#define USBHS_DINEPINTSTS_EPDISIF ((uint32_t)0x00000002U) +#define USBHS_DINEPINTSTS_AHBERRIF_POS (2U) +#define USBHS_DINEPINTSTS_AHBERRIF ((uint32_t)0x00000004U) +#define USBHS_DINEPINTSTS_TOUTIF_POS (3U) +#define USBHS_DINEPINTSTS_TOUTIF ((uint32_t)0x00000008U) +#define USBHS_DINEPINTSTS_TXFERINTIF_POS (4U) +#define USBHS_DINEPINTSTS_TXFERINTIF ((uint32_t)0x00000010U) +#define USBHS_DINEPINTSTS_INEPMISIF_POS (5U) +#define USBHS_DINEPINTSTS_INEPMISIF ((uint32_t)0x00000020U) +#define USBHS_DINEPINTSTS_INEPNAKEIF_POS (6U) +#define USBHS_DINEPINTSTS_INEPNAKEIF ((uint32_t)0x00000040U) +#define USBHS_DINEPINTSTS_TXFEIF_POS (7U) +#define USBHS_DINEPINTSTS_TXFEIF ((uint32_t)0x00000080U) +#define USBHS_DINEPINTSTS_TXFUDRIF_POS (8U) +#define USBHS_DINEPINTSTS_TXFUDRIF ((uint32_t)0x00000100U) +#define USBHS_DINEPINTSTS_PKDRPSTS_POS (11U) +#define USBHS_DINEPINTSTS_PKDRPSTS ((uint32_t)0x00000800U) +#define USBHS_DINEPINTSTS_BBERRIF_POS (12U) +#define USBHS_DINEPINTSTS_BBERRIF ((uint32_t)0x00001000U) +#define USBHS_DINEPINTSTS_NAKIF_POS (13U) +#define USBHS_DINEPINTSTS_NAKIF ((uint32_t)0x00002000U) +#define USBHS_DINEPINTSTS_NYETIF_POS (14U) +#define USBHS_DINEPINTSTS_NYETIF ((uint32_t)0x00004000U) + +/** Bit definition for USBHS_DINEP0TXSIZ register **/ +#define USBHS_DINEP0TXSIZ_TLEN_POS (0U) +#define USBHS_DINEP0TXSIZ_TLEN ((uint32_t)0x0000007FU) +#define USBHS_DINEP0TXSIZ_PKTCNT_POS (19U) +#define USBHS_DINEP0TXSIZ_PKTCNT ((uint32_t)0x00180000U) + +/** Bit definition for USBHS_DINEPTXSIZ(1~8) register **/ +#define USBHS_DINEPTXSIZ_TLEN_POS (0U) +#define USBHS_DINEPTXSIZ_TLEN ((uint32_t)0x0007FFFFU) +#define USBHS_DINEPTXSIZ_PKTCNT_POS (19U) +#define USBHS_DINEPTXSIZ_PKTCNT ((uint32_t)0x1FF80000U) +#define USBHS_DINEPTXSIZ_MCNT_POS (29U) +#define USBHS_DINEPTXSIZ_MCNT ((uint32_t)0x60000000U) + +/** Bit definition for USBHS_DIEPDMADD(0~8) register **/ +#define USBHS_DIEPDMADD_DMADD_POS (0U) +#define USBHS_DIEPDMADD_DMADD ((uint32_t)0xFFFFFFFFU) + +/** Bit definition for USBHS_DINEPTXFSTS(0~8) register **/ +#define USBHS_DINEPTXFSTS_TXFSPCAVL_POS (0U) +#define USBHS_DINEPTXFSTS_TXFSPCAVL ((uint32_t)0x0000FFFFU) + +/** Bit definition for USBHS_DOUTEP0CTRL register **/ +#define USBHS_DOUTEP0CTRL_MPLEN_POS (0U) +#define USBHS_DOUTEP0CTRL_MPLEN ((uint32_t)0x00000003U) +#define USBHS_DOUTEP0CTRL_EPACT_POS (15U) +#define USBHS_DOUTEP0CTRL_EPACT ((uint32_t)0x00008000U) +#define USBHS_DOUTEP0CTRL_NAKSTS_POS (17U) +#define USBHS_DOUTEP0CTRL_NAKSTS ((uint32_t)0x00020000U) +#define USBHS_DOUTEP0CTRL_EPTYPE_POS (18U) +#define USBHS_DOUTEP0CTRL_EPTYPE ((uint32_t)0x000C0000U) +#define USBHS_DOUTEP0CTRL_STALL_POS (21U) +#define USBHS_DOUTEP0CTRL_STALL ((uint32_t)0x00200000U) +#define USBHS_DOUTEP0CTRL_CNAK_POS (26U) +#define USBHS_DOUTEP0CTRL_CNAK ((uint32_t)0x04000000U) +#define USBHS_DOUTEP0CTRL_SNAK_POS (27U) +#define USBHS_DOUTEP0CTRL_SNAK ((uint32_t)0x08000000U) +#define USBHS_DOUTEP0CTRL_EPDIS_POS (30U) +#define USBHS_DOUTEP0CTRL_EPDIS ((uint32_t)0x40000000U) +#define USBHS_DOUTEP0CTRL_EPEN_POS (31U) +#define USBHS_DOUTEP0CTRL_EPEN ((uint32_t)0x80000000U) + + +/** Bit definition for USBHS_DOUTEPCTRL(1~8) register **/ +#define USBHS_DOUTEPCTRL_MPLEN_POS (0U) +#define USBHS_DOUTEPCTRL_MPLEN ((uint32_t)0x00000003U) +#define USBHS_DOUTEPCTRL_EPACT_POS (15U) +#define USBHS_DOUTEPCTRL_EPACT ((uint32_t)0x00008000U) +#define USBHS_DOUTEPCTRL_EPDPID_EPEOFRM_POS (16U) +#define USBHS_DOUTEPCTRL_EPDPID_EPEOFRM ((uint32_t)0x00010000U) +#define USBHS_DOUTEPCTRL_NAKSTS_POS (17U) +#define USBHS_DOUTEPCTRL_NAKSTS ((uint32_t)0x00020000U) +#define USBHS_DOUTEPCTRL_EPTYPE_POS (18U) +#define USBHS_DOUTEPCTRL_EPTYPE ((uint32_t)0x000C0000U) +#define USBHS_DOUTEPCTRL_STALL_POS (21U) +#define USBHS_DOUTEPCTRL_STALL ((uint32_t)0x00200000U) +#define USBHS_DOUTEPCTRL_CNAK_POS (26U) +#define USBHS_DOUTEPCTRL_CNAK ((uint32_t)0x04000000U) +#define USBHS_DOUTEPCTRL_SNAK_POS (27U) +#define USBHS_DOUTEPCTRL_SNAK ((uint32_t)0x08000000U) +#define USBHS_DOUTEPCTRL_SD0PID_SEVNFRM_POS (28U) +#define USBHS_DOUTEPCTRL_SD0PID_SEVNFRM ((uint32_t)0x10000000U) +#define USBHS_DOUTEPCTRL_SD1PID_SODDFRM_POS (29U) +#define USBHS_DOUTEPCTRL_SD1PID_SODDFRM ((uint32_t)0x20000000U) +#define USBHS_DOUTEPCTRL_EPDIS_POS (30U) +#define USBHS_DOUTEPCTRL_EPDIS ((uint32_t)0x40000000U) +#define USBHS_DOUTEPCTRL_EPEN_POS (31U) +#define USBHS_DOUTEPCTRL_EPEN ((uint32_t)0x80000000U) + + +/** Bit definition for USBHS_DOUTEPINTSTS(0~8) register **/ +#define USBHS_DOUTEPINTSTS_TXCIF_POS (0U) +#define USBHS_DOUTEPINTSTS_TXCIF ((uint32_t)0x00000001U) +#define USBHS_DOUTEPINTSTS_EPDISIF_POS (1U) +#define USBHS_DOUTEPINTSTS_EPDISIF ((uint32_t)0x00000002U) +#define USBHS_DOUTEPINTSTS_AHBERRIF_POS (2U) +#define USBHS_DOUTEPINTSTS_AHBERRIF ((uint32_t)0x00000004U) +#define USBHS_DOUTEPINTSTS_STUPPDNEIF_POS (3U) +#define USBHS_DOUTEPINTSTS_STUPPDNEIF ((uint32_t)0x00000008U) +#define USBHS_DOUTEPINTSTS_OUTTRXEPDISIF_POS (4U) +#define USBHS_DOUTEPINTSTS_OUTTRXEPDISIF ((uint32_t)0x00000010U) +#define USBHS_DOUTEPINTSTS_STSPRXIF_POS (5U) +#define USBHS_DOUTEPINTSTS_STSPRXIF ((uint32_t)0x00000020U) +#define USBHS_DOUTEPINTSTS_B2BSTUPRIF_POS (6U) +#define USBHS_DOUTEPINTSTS_B2BSTUPRIF ((uint32_t)0x00000040U) +#define USBHS_DOUTEPINTSTS_OUTPCKERRIF_POS (8U) +#define USBHS_DOUTEPINTSTS_OUTPCKERRIF ((uint32_t)0x00000100U) +#define USBHS_DOUTEPINTSTS_PKDRPSTS_POS (11U) +#define USBHS_DOUTEPINTSTS_PKDRPSTS ((uint32_t)0x00000800U) +#define USBHS_DOUTEPINTSTS_BBERRIF_POS (12U) +#define USBHS_DOUTEPINTSTS_BBERRIF ((uint32_t)0x00001000U) +#define USBHS_DOUTEPINTSTS_NAKIF_POS (13U) +#define USBHS_DOUTEPINTSTS_NAKIF ((uint32_t)0x00002000U) +#define USBHS_DOUTEPINTSTS_NYETIF_POS (14U) +#define USBHS_DOUTEPINTSTS_NYETIF ((uint32_t)0x00004000U) +#define USBHS_DOUTEPINTSTS_STUPPRXIF_POS (15U) +#define USBHS_DOUTEPINTSTS_STUPPRXIF ((uint32_t)0x00008000U) + + +/** Bit definition for USBHS_DOUTEP0TXSIZ register **/ +#define USBHS_DOUTEP0TXSIZ_TLEN_POS (0U) +#define USBHS_DOUTEP0TXSIZ_TLEN ((uint32_t)0x0000007FU) +#define USBHS_DOUTEP0TXSIZ_PKTCNT_POS (19U) +#define USBHS_DOUTEP0TXSIZ_PKTCNT ((uint32_t)0x00080000U) +#define USBHS_DOUTEP0TXSIZ_STUPPCNT_POS (29U) +#define USBHS_DOUTEP0TXSIZ_STUPPCNT ((uint32_t)0x60000000U) + +/** Bit definition for USBHS_DOUTEPTXSIZ(1~8) register **/ +#define USBHS_DOUTEPTXSIZ_TLEN_POS (0U) +#define USBHS_DOUTEPTXSIZ_TLEN ((uint32_t)0x0007FFFFU) +#define USBHS_DOUTEPTXSIZ_PKTCNT_POS (19U) +#define USBHS_DOUTEPTXSIZ_PKTCNT ((uint32_t)0x1FF80000U) +#define USBHS_DOUTEPTXSIZ_STUPPCNT_POS (29U) +#define USBHS_DOUTEPTXSIZ_STUPPCNT_RXDPID ((uint32_t)0x60000000U) + +/** Bit definition for USBHS_DINEPDMADD(0~8) register **/ +#define USBHS_DINEPDMADD_DMADD ((uint32_t)0xFFFFFFFFU) + +/** Bit definition for USBHS_PWRCTRL register **/ +#define USBHS_PWRCTRL_PHYSTP_POS (0U) +#define USBHS_PWRCTRL_PHYSTP ((uint32_t)0x00000001U) +#define USBHS_PWRCTRL_GATEHCLK_POS (1U) +#define USBHS_PWRCTRL_GATEHCLK ((uint32_t)0x00000002U) +#define USBHS_PWRCTRL_PDMRST_POS (3U) +#define USBHS_PWRCTRL_PDMRST ((uint32_t)0x00000008U) +#define USBHS_PWRCTRL_PHYSLEEP_POS (6U) +#define USBHS_PWRCTRL_PHYSLEEP ((uint32_t)0x00000040U) +#define USBHS_PWRCTRL_DSLEEP_POS (7U) +#define USBHS_PWRCTRL_DSLEEP ((uint32_t)0x00000080U) + +/** Bit definition for USBHS_PWRCTRL1 register **/ +#define USBHS_PWRCTRL1_GATEN_POS (0U) +#define USBHS_PWRCTRL1_GATEN ((uint32_t)0x00000001U) +#define USBHS_PWRCTRL1_CNT_POS (1U) +#define USBHS_PWRCTRL1_CNT ((uint32_t)0x00000006U) +#define USBHS_PWRCTRL1_RAMCLKEN_POS (3U) +#define USBHS_PWRCTRL1_RAMCLKEN ((uint32_t)0x00000008U) + +/** Bit definition for USBHS_WRPCTRL register **/ +#define USBHS_WRPCTRL_PINDETEN_POS (16U) +#define USBHS_WRPCTRL_PINDETEN ((uint32_t)0x00010000U) +#define USBHS_WRPCTRL_VBRMDETEN_POS (17U) +#define USBHS_WRPCTRL_VBRMDETEN ((uint32_t)0x00020000U) +#define USBHS_WRPCTRL_HDISCEN_POS (18U) +#define USBHS_WRPCTRL_HDISCEN ((uint32_t)0x00040000U) +#define USBHS_WRPCTRL_IDDETEN_POS (19U) +#define USBHS_WRPCTRL_IDDETEN ((uint32_t)0x00080000U) +#define USBHS_WRPCTRL_SUSPWKEN_POS (20U) +#define USBHS_WRPCTRL_SUSPWKEN ((uint32_t)0x00100000U) +#define USBHS_WRPCTRL_LSCHGEN_POS (21U) +#define USBHS_WRPCTRL_LSCHGEN ((uint32_t)0x00200000U) + +/** Bit definition for USBHS_WRPCFG register **/ +#define USBHS_WRPCFG_PHYCLKSEL_POS (0U) +#define USBHS_WRPCFG_PHYCLKSEL ((uint32_t)0x00000007U) +#define USBHS_WRPCFG_PHYCLKSEL_10M ((uint32_t)0x00000000)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_12M ((uint32_t)0x00000001)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_25M ((uint32_t)0x00000002)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_30M ((uint32_t)0x00000003)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_19_2M ((uint32_t)0x00000004)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_24M ((uint32_t)0x00000005)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_27M ((uint32_t)0x00000006)//[2:0] +#define USBHS_WRPCFG_PHYCLKSEL_40M ((uint32_t)0x00000007)//[2:0] + +#define USBHS_WRPCFG_PLLEN_POS (3U) +#define USBHS_WRPCFG_PLLEN ((uint32_t)0x00000008U) +#define USBHS_WRPCFG_IDEN_POS (9U) +#define USBHS_WRPCFG_IDEN ((uint32_t)0x00000200U) +#define USBHS_WRPCFG_LSEN_POS (10U) +#define USBHS_WRPCFG_LSEN ((uint32_t)0x00000400U) +#define USBHS_WRPCFG_SOFDEN_POS (11U) +#define USBHS_WRPCFG_SOFDEN ((uint32_t)0x00000800U) +#define USBHS_WRPCFG_IDSIG_POS (12U) +#define USBHS_WRPCFG_IDSIG ((uint32_t)0x00001000U) + +/*** MIPI DSI HOST ***/ + +/** Bit definition for DSI_Wrapper register **/ +/** Bit definition for DSI_WRPCTRL register **/ +#define DSI_WRPCTRL_ULPSCLEN ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_WRPCTRL_ULPSDLEN_POS (1) +#define DSI_WRPCTRL_ULPSDLEN ((uint32_t)0x0000001EU) /* Bit[4:1] */ +#define DSI_WRPCTRL_ULPSDLEN_0 ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_WRPCTRL_ULPSDLEN_1 ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_WRPCTRL_ULPSDLEN_2 ((uint32_t)0x00000008U) /* Bit 3 */ +#define DSI_WRPCTRL_ULPSDLEN_3 ((uint32_t)0x00000010U) /* Bit 4 */ +#define DSI_WRPCTRL_ISKEWCAL ((uint32_t)0x00000020U) /* Bit 5 */ +#define DSI_WRPCTRL_PSKEWCAL ((uint32_t)0x00000040U) /* Bit 6 */ +#define DSI_WRPCTRL_TRIGSEND_POS (7) +#define DSI_WRPCTRL_TRIGSEND ((uint32_t)0x00000180U) /* Bit[8:7] */ +#define DSI_WRPCTRL_TRIGSEND_0 ((uint32_t)0x00000080U) /* Bit 7 */ +#define DSI_WRPCTRL_TRIGSEND_1 ((uint32_t)0x00000100U) /* Bit 8 */ +#define DSI_WRPCTRL_TRIGREQ ((uint32_t)0x00000200U) /* Bit 9 */ +#define DSI_WRPCTRL_BLKEERIEN ((uint32_t)0x00000400U) /* Bit 10 */ +#define DSI_WRPCTRL_SPERRIEN ((uint32_t)0x00000800U) /* Bit 11 */ +#define DSI_WRPCTRL_OVERRIEN ((uint32_t)0x00001000U) /* Bit 12 */ +#define DSI_WRPCTRL_UNDERRIEN ((uint32_t)0x00002000U) /* Bit 13 */ + +/** Bit definition for DSI_WRPSTS register **/ +#define DSI_WRPSTS_ULPSCLACT ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_WRPSTS_ULPSDLACT_POS (1) +#define DSI_WRPSTS_ULPSDLACT ((uint32_t)0x0000001EU) /* Bit[4:1] */ +#define DSI_WRPSTS_ULPSDLEN_0 ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_WRPSTS_ULPSDLEN_1 ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_WRPSTS_ULPSDLEN_2 ((uint32_t)0x00000008U) /* Bit 3 */ +#define DSI_WRPSTS_ULPSDLEN_3 ((uint32_t)0x00000010U) /* Bit 4 */ +#define DSI_WRPSTS_ISKEWCALDN ((uint32_t)0x00000020U) /* Bit 5 */ +#define DSI_WRPSTS_PSKEWCALDN ((uint32_t)0x00000040U) /* Bit 6 */ +#define DSI_WRPSTS_TRIGACK ((uint32_t)0x00000080U) /* Bit 7 */ +#define DSI_WRPSTS_BLKERRF ((uint32_t)0x00000100U) /* Bit 8 */ +#define DSI_WRPSTS_SPERRIEN ((uint32_t)0x00000200U) /* Bit 9 */ +#define DSI_WRPSTS_OVERRIEN ((uint32_t)0x00000400U) /* Bit 10 */ +#define DSI_WRPSTS_UNDERRIEN ((uint32_t)0x00000800U) /* Bit 11 */ + +/** Bit definition for DSIPHY_CTRL1 register **/ +#define DSIPHY_CTRL1_HSDBW ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSIPHY_CTRL1_CKLANESET_POS (1) +#define DSIPHY_CTRL1_CKLANESET ((uint32_t)0x0000003EU) /* Bit[5:1] */ +#define DSIPHY_CTRL1_L4SEL_POS (6) +#define DSIPHY_CTRL1_L4SEL ((uint32_t)0x000001C0U) /* Bit[8:6] */ +#define DSIPHY_CTRL1_L3SEL_POS (9) +#define DSIPHY_CTRL1_L3SEL ((uint32_t)0x00000E00U) /* Bit[11:9] */ +#define DSIPHY_CTRL1_L2SEL_POS (12) +#define DSIPHY_CTRL1_L2SEL ((uint32_t)0x00007000U) /* Bit[14:12] */ +#define DSIPHY_CTRL1_L1SEL_POS (15) +#define DSIPHY_CTRL1_L1SEL ((uint32_t)0x00038000U) /* Bit[17:15] */ +#define DSIPHY_CTRL1_L0SEL_POS (18) +#define DSIPHY_CTRL1_L0SEL ((uint32_t)0x001C0000U) /* Bit[20:18] */ +#define DSIPHY_CTRL1_DPDNSEN_POS (21) +#define DSIPHY_CTRL1_DPDNSEN ((uint32_t)0x03E00000U) /* Bit[25:21] */ +#define DSIPHY_CTRL1_REFCKSEL_POS (26) +#define DSIPHY_CTRL1_REFCKSEL ((uint32_t)0x1C000000U) /* Bit[28:26] */ +#define DSIPHY_CTRL1_EXTDCYCEL_POS (29) +#define DSIPHY_CTRL1_EXTDCYCEL ((uint32_t)0xE0000000U) /* Bit[31:29] */ + +/** Bit definition for DSIPHY_CTRL2 register **/ +#define DSIPHY_CTRL2_DLPRET_POS (0) +#define DSIPHY_CTRL2_DLPRET ((uint32_t)0x000000FFU) /* Bit[7:0] */ +#define DSIPHY_CTRL2_DLZEROT_POS (8) +#define DSIPHY_CTRL2_DLZEROT ((uint32_t)0x0000FF00U) /* Bit[15:8] */ +#define DSIPHY_CTRL2_DLTRAT_POS (16) +#define DSIPHY_CTRL2_DLTRAT ((uint32_t)0x00FF0000U) /* Bit[23:16] */ +#define DSIPHY_CTRL2_CLPRET_POS (24) +#define DSIPHY_CTRL2_CLPRET ((uint32_t)0xFF000000U) /* Bit[31:24] */ + +/** Bit definition for DSIPHY_CTRL3 register **/ +#define DSIPHY_CTRL3_CLZEROT_POS (0) +#define DSIPHY_CTRL3_CLZEROT ((uint32_t)0x000000FFU) /* Bit[7:0] */ +#define DSIPHY_CTRL3_CLTRLT_POS (8) +#define DSIPHY_CTRL3_CLTRLT ((uint32_t)0x0000FF00U) /* Bit[15:8] */ +#define DSIPHY_CTRL3_CLCLKPRET_POS (16) +#define DSIPHY_CTRL3_CLCLKPRET ((uint32_t)0x00FF0000U) /* Bit[23:16] */ +#define DSIPHY_CTRL3_CLCLKPOST_POS (24) +#define DSIPHY_CTRL3_CLCLKPOST ((uint32_t)0xFF000000U) /* Bit[31:24] */ + +/** Bit definition for DSIPHY_CTRL4 register **/ +#define DSIPHY_CTRL4_VCTRL_POS (0) +#define DSIPHY_CTRL4_VCTRL ((uint32_t)0x0000001FU) /* Bit[4:0] */ + +/** Bit definition for DSIPHY_PLLCTRL1 register **/ +#define DSIPHY_PLLCTRL1_PLLFBKFRA_POS (0) +#define DSIPHY_PLLCTRL1_PLLFBKFRA ((uint32_t)0x00FFFFFFU) /* Bit[23:0] */ + +/** Bit definition for DSIPHY_PLLCTRL2 register **/ +#define DSIPHY_PLLCTRL2_FBKINT_POS (0) +#define DSIPHY_PLLCTRL2_FBKINT ((uint32_t)0x000001FFU) /* Bit[8:0] */ +#define DSIPHY_PLLCTRL2_PREDIV_POS (9) +#define DSIPHY_PLLCTRL2_PREDIV ((uint32_t)0x00000600U) /* Bit[10:9] */ +#define DSIPHY_PLLCTRL2_DOSTBEN ((uint32_t)0x00000800U) /* Bit 11 */ +#define DSIPHY_PLLCTRL2_SSCAMPOP_POS (12) +#define DSIPHY_PLLCTRL2_SSCAMPOP ((uint32_t)0x03FFF000U) /* Bit[29:12] */ + +/** Bit definition for DSIPHY_PLLCTRL3 register **/ +#define DSIPHY_PLLCTRL3_SSCAMPINIT_POS (0) +#define DSIPHY_PLLCTRL3_SSCAMPINIT ((uint32_t)0x00003FFFU) /* Bit[17:0] */ +#define DSIPHY_PLLCTRL3_SSCPRD_POS (18) +#define DSIPHY_PLLCTRL3_SSCPRD ((uint32_t)0x0FFC0000U) /* Bit[27:18] */ +#define DSIPHY_PLLCTRL3_SSCEN ((uint32_t)0x10000000U) /* Bit 28 */ +#define DSIPHY_PLLCTRL3_PLLFBKCHG ((uint32_t)0x20000000U) /* Bit 29 */ +#define DSIPHY_PLLCTRL3_PLLDOST_POS (30) +#define DSIPHY_PLLCTRL3_PLLDOST ((uint32_t)0xC0000000U) /* Bit[31:30] */ + +/** Bit definition for DSIPHY_PLLCTRL4 register **/ +#define DSIPHY_PLLCTRL4_L2NHTR_POS (0) +#define DSIPHY_PLLCTRL4_L2NHTR ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define DSIPHY_PLLCTRL4_L2PHTR_POS (5) +#define DSIPHY_PLLCTRL4_L2PHTR ((uint32_t)0x000003E0U) /* Bit[9:5] */ +#define DSIPHY_PLLCTRL4_L1NHTR_POS (10) +#define DSIPHY_PLLCTRL4_L1NHTR ((uint32_t)0x00007C00U) /* Bit[14:10] */ +#define DSIPHY_PLLCTRL4_L1PHTR_POS (15) +#define DSIPHY_PLLCTRL4_L1PHTR ((uint32_t)0x000F8000U) /* Bit[19:15] */ +#define DSIPHY_PLLCTRL4_L0NHTR_POS (20) +#define DSIPHY_PLLCTRL4_L0NHTR ((uint32_t)0x01F00000U) /* Bit[24:20] */ +#define DSIPHY_PLLCTRL4_L0PHTR_POS (25) +#define DSIPHY_PLLCTRL4_L0PHTR ((uint32_t)0x3E000000U) /* Bit[29:25] */ + +/** Bit definition for DSIPHY_PLLCTRL5 register **/ +#define DSIPHY_PLLCTRL5_L4NHTR_POS (0) +#define DSIPHY_PLLCTRL5_L4NHTR ((uint32_t)0x0000001FU) /* Bit[4:0] */ +#define DSIPHY_PLLCTRL5_L4PHTR_POS (5) +#define DSIPHY_PLLCTRL5_L4PHTR ((uint32_t)0x000003E0U) /* Bit[9:5] */ +#define DSIPHY_PLLCTRL5_L3NHTR_POS (10) +#define DSIPHY_PLLCTRL5_L3NHTR ((uint32_t)0x00007C00U) /* Bit[14:10] */ +#define DSIPHY_PLLCTRL5_L3PHTR_POS (15) +#define DSIPHY_PLLCTRL5_L3PHTR ((uint32_t)0x000F8000U) /* Bit[19:15] */ +#define DSIPHY_PLLCTRL5_PLLFMTOR_POS (20) +#define DSIPHY_PLLCTRL5_PLLFMTOR ((uint32_t)0x00300000U) /* Bit[21:20] */ +#define DSIPHY_PLLCTRL3_PLLWTGEN ((uint32_t)0x00400000U) /* Bit 22 */ +#define DSIPHY_PLLCTRL3_PLLFMEN ((uint32_t)0x00800000U) /* Bit 23 */ + +/** Bit definition for DSIPHY_PLLSTS register **/ +#define DSIPHY_PLLSTS_PLLUNLOCK ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSIPHY_PLLSTS_PLLFMCPLT ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSIPHY_PLLSTS_PLLFMUNDER ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSIPHY_PLLSTS_PLLFMOVER ((uint32_t)0x00000008U) /* Bit 3 */ +#define DSIPHY_PLLSTS_PLLDIGCKMISS ((uint32_t)0x00000010U) /* Bit 4 */ +#define DSIPHY_PLLSTS_PLLFBKCKMISS ((uint32_t)0x00000020U) /* Bit 5 */ +#define DSIPHY_PLLSTS_PLLREFCKMISS ((uint32_t)0x00000040U) /* Bit 6 */ +#define DSIPHY_PLLSTS_PHYREADY ((uint32_t)0x00000080U) /* Bit 7 */ + +/** Bit definition for DSI HOST Control register **/ +/** Bit definition for DSI_NUMLANES register **/ +#define DSI_NUMLANES_NUMLANES_POS (0) +#define DSI_NUMLANES_NUMLANES ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define DSI_NUMLANES_NUMLANES_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_NUMLANES_NUMLANES_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_NUMLANES_NUMLANES_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_NUMLANES_NUMLANES_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +/** Bit definition for DSI_CONTHSCLK register **/ +#define DSI_CONTHSCLK_CONTHSCLK_POS (0) +#define DSI_CONTHSCLK_CONTHSCLK ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for DSI_TPRE register **/ +#define DSI_TPRE_TPRE_POS (0) +#define DSI_TPRE_TPRE ((uint32_t)0x000000FFU) /* Bit[7:0] */ + +/** Bit definition for DSI_TPOST register **/ +#define DSI_TPOST_TPOST_POS (0) +#define DSI_TPOST_TPOST ((uint32_t)0x000000FFU) /* Bit[7:0] */ + +/** Bit definition for DSI_TXGAP register **/ +#define DSI_TXGAP_TXGAP_POS (0) +#define DSI_TXGAP_TXGAP ((uint32_t)0x000000FFU) /* Bit[7:0] */ + +/** Bit definition for DSI_AUTOINSERT_EOTP register **/ +#define DSI_AUTOINSERT_EOTP_AUTOINSEOTP ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for DSI_DISRXCRCCHK register **/ +#define DSI_DISRXCRCCHK_DISRXCRCCHK ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for DSI_HSTXTOCNT register **/ +#define DSI_HSTXTOCNT_HSTXTOCNT_POS (0) +#define DSI_HSTXTOCNT_HSTXTOCNT ((uint32_t)0x00FFFFFFU) /* Bit[23:0] */ + +/** Bit definition for DSI_LRXTOCNT register **/ +#define DSI_LRXTOCNT_LRXTOCNT_POS (0) +#define DSI_LRXTOCNT_LRXTOCNT ((uint32_t)0x00FFFFFFU) /* Bit[23:0] */ + +/** Bit definition for DSI_BTATOCNT register **/ +#define DSI_BTATOCNT_BTATOCNT_POS (0) +#define DSI_BTATOCNT_BTATOCNT ((uint32_t)0x00FFFFFFU) /* Bit[23:0] */ + +/** Bit definition for DSI_TWAKEUP register **/ +#define DSI_TWAKEUP_TWAKEUP_POS (0) +#define DSI_TWAKEUP_TWAKEUP ((uint32_t)0x0007FFFFU) /* Bit[18:0] */ + +/** Bit definition for DSI_DISBST register **/ +#define DSI_DISBST_DISBST ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for DSI_STS register **/ +#define DSI_STS_SOTERR ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_STS_SOTSYNCERR ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_STS_EOTSYNCERR ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_STS_ESCMODERR ((uint32_t)0x00000008U) /* Bit 3 */ +#define DSI_STS_LPTXSYNCERR ((uint32_t)0x00000010U) /* Bit 4 */ +#define DSI_STS_TOERR ((uint32_t)0x00000020U) /* Bit 5 */ +#define DSI_STS_FCTRLERR ((uint32_t)0x00000040U) /* Bit 6 */ +#define DSI_STS_COTDET ((uint32_t)0x00000080U) /* Bit 7 */ +#define DSI_STS_ECCSERR ((uint32_t)0x00000100U) /* Bit 8 */ +#define DSI_STS_ECCMERR ((uint32_t)0x00000200U) /* Bit 9 */ +#define DSI_STS_CRCERR ((uint32_t)0x00000400U) /* Bit 10 */ +#define DSI_STS_DATYPERR ((uint32_t)0x00000800U) /* Bit 11 */ +#define DSI_STS_VCIDINVLD ((uint32_t)0x00001000U) /* Bit 12 */ +#define DSI_STS_INVLDTXL ((uint32_t)0x00002000U) /* Bit 13 */ +#define DSI_STS_PROVILT ((uint32_t)0x00008000U) /* Bit 15 */ +#define DSI_STS_BIT0 ((uint32_t)0x00010000U) /* Bit 16 */ +#define DSI_STS_BIT1 ((uint32_t)0x00020000U) /* Bit 17 */ +#define DSI_STS_BIT2 ((uint32_t)0x00040000U) /* Bit 18 */ +#define DSI_STS_BIT3 ((uint32_t)0x00080000U) /* Bit 19 */ + +/** Bit definition for DSI_ERRSTS register **/ +#define DSI_ERRSTS_ECCSERR ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_ERRSTS_ECCMERR ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_ERRSTS_ECCERRBIT_POS (2) +#define DSI_ERRSTS_ECCERRBIT ((uint32_t)0x0000007CU) /* Bit [6:2] */ +#define DSI_ERRSTS_ECCERRBIT_0 ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_ERRSTS_ECCERRBIT_1 ((uint32_t)0x00000008U) /* Bit 3 */ +#define DSI_ERRSTS_ECCERRBIT_2 ((uint32_t)0x00000010U) /* Bit 4 */ +#define DSI_ERRSTS_ECCERRBIT_3 ((uint32_t)0x00000020U) /* Bit 5 */ +#define DSI_ERRSTS_ECCERRBIT_4 ((uint32_t)0x00000040U) /* Bit 6 */ +#define DSI_ERRSTS_CRCERR ((uint32_t)0x00000080U) /* Bit 7 */ +#define DSI_ERRSTS_HTXTOERR ((uint32_t)0x00000100U) /* Bit 8 */ +#define DSI_ERRSTS_LRXTOERR ((uint32_t)0x00000200U) /* Bit 9 */ +#define DSI_ERRSTS_BATTOERR ((uint32_t)0x00000400U) /* Bit 10 */ + +/** Bit definition for DSI_CLKLANEN register **/ +#define DSI_CLKLANEN_CLKLANEN ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for DSI_DATLANEN register **/ +#define DSI_DATLANEN_DATLANEN_POS (0) +#define DSI_DATLANEN_DATLANEN ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define DSI_DATLANEN_DATLANEN_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_DATLANEN_DATLANEN_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_DATLANEN_DATLANEN_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_DATLANEN_DATLANEN_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +/** Bit definition for DSI_SKEWCALTIMI register **/ +#define DSI_SKEWCALTIMI_SKEWVALTIMI_POS (0) +#define DSI_SKEWCALTIMI_SKEWVALTIMI ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for DSI_SKEWCALTIMP register **/ +#define DSI_SKEWCALTIMP_SKEWVALTIMP_POS (0) +#define DSI_SKEWCALTIMP_SKEWVALTIMP ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for DSI_ALTCALTIM register **/ +#define DSI_ALTCALTIM_ALTCALTIM_POS (0) +#define DSI_ALTCALTIM_ALTCALTIM ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for DSI_SKEWCALINE register **/ +#define DSI_SKEWCALINE_SKEWCALINE_POS (0) +#define DSI_SKEWCALINE_SKEWCALINE ((uint32_t)0x000000FFU) /* Bit[7:0] */ + +/** Bit definition for VID_EN register **/ +#define VID_EN_EN_POS (0) +#define VID_EN_EN ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_PIXPERPKT register **/ +#define VID_PIXPERPKT_PIXPERPKT_POS (0) +#define VID_PIXPERPKT_PIXPERPKT ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + + +/** Bit definition for VID_PIXPLDSIZ register **/ +#define VID_PIXPLDSIZ_PIXPLDSIZ_POS (0) +#define VID_PIXPLDSIZ_PIXPLDSIZ ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_PIXALIGN register **/ +#define VID_PIXALIGN_PIXALIGN_POS (0) +#define VID_PIXALIGN_PIXALIGN ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_PIXFMT register **/ +#define VID_PIXFMT_PIXFMT_POS (0) +#define VID_PIXFMT_PIXFMT ((uint32_t)0x0000003FU) /* Bit[5:0] */ + +/** Bit definition for VID_VSYNCPOL register **/ +#define VID_VSYNCPOL_VSYNCPOL_POS (0) +#define VID_VSYNCPOL_VSYNCPOL ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_HSYNCPOL register **/ +#define VID_HSYNCPOL_HSYNCPOL_POS (0) +#define VID_HSYNCPOL_HSYNCPOL ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_VIDEOMOD register **/ +#define VID_VIDEOMOD_VIDEOMOD_POS (0) +#define VID_VIDEOMOD_VIDEOMOD ((uint32_t)0x00000003U) /* Bit[1:0] */ +#define VID_VIDEOMOD_VIDEOMOD_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define VID_VIDEOMOD_VIDEOMOD_1 ((uint32_t)0x00000002U) /* Bit 1 */ + + +/** Bit definition for VID_OVERIDE register **/ +#define VID_OVERIDE_OVERIDE_POS (0) +#define VID_OVERIDE_OVERIDE ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_STD register **/ +#define VID_STD_STD_POS (0) +#define VID_STD_STD ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_HFP register **/ +#define VID_HFP_HFP_POS (0) +#define VID_HFP_HFP ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_HBP register **/ +#define VID_HBP_HBP_POS (0) +#define VID_HBP_HBP ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_HSA register **/ +#define VID_HSA_HSA_POS (0) +#define VID_HSA_HSA ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_PKTPERLINE register **/ +#define VID_PKTPERLINE_PKTPERLINE_POS (0) +#define VID_PKTPERLINE_PKTPERLINE ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define VID_PKTPERLINE_PKTPERLINE_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define VID_PKTPERLINE_PKTPERLINE_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define VID_PKTPERLINE_PKTPERLINE_2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define VID_PKTPERLINE_PKTPERLINE_3 ((uint32_t)0x00000008U) /* Bit 3 */ + +/** Bit definition for VID_VBP register **/ +#define VID_VBP_VBP_POS (0) +#define VID_VBP_VBP ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_VFP register **/ +#define VID_VFP_VFP_POS (0) +#define VID_VFP_VFP ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_BLLPMOD register **/ +#define VID_BLLPMOD_BLLPMOD_POS (0) +#define VID_BLLPMOD_BLLPMOD ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_NULLPKTBLLP register **/ +#define VID_NULLPKTBLLP_NULLPKTBLLP_POS (0) +#define VID_NULLPKTBLLP_NULLPKTBLLP ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for VID_VACT register **/ +#define VID_VACT_VACT_POS (0) +#define VID_VACT_VACT ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_VC register **/ +#define VID_VC_VC_POS (0) +#define VID_VC_VC ((uint32_t)0x00000003U) /* Bit[1:0] */ +#define VID_VC_VC_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define VID_VC_VC_1 ((uint32_t)0x00000002U) /* Bit 1 */ + +/** Bit definition for VID_EXTPKTEN register **/ +#define VID_EXTPKTEN_EXTPKTEN_POS (0) +#define VID_EXTPKTEN_EXTPKTEN ((uint32_t)0x0000000FU) /* Bit[3:0] */ +#define VID_EXTPKTEN_EXTPKTEN_0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define VID_EXTPKTEN_EXTPKTEN_1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define VID_EXTPKTEN_EXTPKTEN_2 ((uint32_t)0x00000003U) /* Bit 2 */ +#define VID_EXTPKTEN_EXTPKTEN_3 ((uint32_t)0x00000004U) /* Bit 3 */ + +/** Bit definition for VID_VSSPLD register **/ +#define VID_VSSPLD_VSSPLD_POS (0) +#define VID_VSSPLD_VSSPLD ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for VID_PLDPERPKT register **/ +#define VID_PLDPERPKT_PLLPERPKT_POS (0) +#define VID_PLDPERPKT_PLLPERPKT ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for DSI_TXPLD register **/ +#define DSI_TXPLD_TXPLD_POS (0) +#define DSI_TXPLD_TXPLD ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/** Bit definition for DSI_PKTCTRL register **/ +#define DSI_PKTCTRL_CNT_POS (0) +#define DSI_PKTCTRL_CNT ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define DSI_PKTCTRL_VC_POS (16) +#define DSI_PKTCTRL_VC ((uint32_t)0x00030000U) /* Bit[17:16] */ +#define DSI_PKTCTRL_VC_0 ((uint32_t)0x00010000U) /* Bit 16 */ +#define DSI_PKTCTRL_VC_1 ((uint32_t)0x00020000U) /* Bit 17 */ +#define DSI_PKTCTRL_HDTYP_POS (18) +#define DSI_PKTCTRL_HDTYP ((uint32_t)0x00FC0000U) /* Bit[23:18] */ +#define DSI_PKTCTRL_HDTYP_0 ((uint32_t)0x00040000U) /* Bit 18 */ +#define DSI_PKTCTRL_HDTYP_1 ((uint32_t)0x00080000U) /* Bit 19 */ +#define DSI_PKTCTRL_HDTYP_2 ((uint32_t)0x00100000U) /* Bit 20 */ +#define DSI_PKTCTRL_HDTYP_3 ((uint32_t)0x00200000U) /* Bit 21 */ +#define DSI_PKTCTRL_HDTYP_4 ((uint32_t)0x00400000U) /* Bit 22 */ +#define DSI_PKTCTRL_HDTYP_5 ((uint32_t)0x00800000U) /* Bit 23 */ +#define DSI_PKTCTRL_MOD ((uint32_t)0x01000000U) /* Bit 24 */ +#define DSI_PKTCTRL_BATIMM ((uint32_t)0x02000000U) /* Bit 25 */ +#define DSI_PKTCTRL_BATNOPKT ((uint32_t)0x04000000U) /* Bit 26 */ + +/** Bit definition for DSI_SENDPKT register **/ +#define DSI_SENDPKT_SENDPKT ((uint32_t)0x00000001U) /* Bit 0 */ + +/** Bit definition for DSI_PKTSTS register **/ +#define DSI_PKTSTS_NIDLE ((uint32_t)0x00000001U) /* Bit 0 */ +#define DSI_PKTSTS_TXD ((uint32_t)0x00000002U) /* Bit 1 */ +#define DSI_PKTSTS_DPHYDIR ((uint32_t)0x00000004U) /* Bit 2 */ +#define DSI_PKTSTS_TXFOVER ((uint32_t)0x00000008U) /* Bit 3 */ +#define DSI_PKTSTS_TXFUNDER ((uint32_t)0x00000010U) /* Bit 4 */ +#define DSI_PKTSTS_RXFOVER ((uint32_t)0x00000020U) /* Bit 5 */ +#define DSI_PKTSTS_RXFUNDER ((uint32_t)0x00000040U) /* Bit 6 */ +#define DSI_PKTSTS_RXPKTD ((uint32_t)0x00000080U) /* Bit 7 */ +#define DSI_PKTSTS_ALLRXPKTD ((uint32_t)0x00000100U) /* Bit 8 */ + +/** Bit definition for DSI_PKTFWRLVL register **/ +#define DSI_PKTFWRLVL_POS (0) +#define DSI_PKTFWRLVL_PKTFWRLVL ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for DSI_PKTFRDLVL register **/ +#define DSI_PKTFRDLVL_POS (0) +#define DSI_PKTFRDLVL_PKTFRDLVL ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ + +/** Bit definition for DSI_PKTRXPLD register **/ +#define DSI_PKTRXPLD_POS (0) +#define DSI_PKTRXPLD_PKTRXPLD ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] */ + +/** Bit definition for DSI_PKTRXHDR register **/ +#define DSI_PKTRXHDR_POS (0) +#define DSI_PKTRXHDR_CNT ((uint32_t)0x0000FFFFU) /* Bit[15:0] */ +#define DSI_PKTRXHDR_DATATYP_POS (16) +#define DSI_PKTRXHDR_DATATYP ((uint32_t)0x003F0000U) /* Bit[21:16] */ +#define DSI_PKTRXHDR_DATATYP_0 ((uint32_t)0x00010000U) /* Bit 16 */ +#define DSI_PKTRXHDR_DATATYP_1 ((uint32_t)0x00020000U) /* Bit 17 */ +#define DSI_PKTRXHDR_DATATYP_2 ((uint32_t)0x00040000U) /* Bit 18 */ +#define DSI_PKTRXHDR_DATATYP_3 ((uint32_t)0x00080000U) /* Bit 19 */ +#define DSI_PKTRXHDR_DATATYP_4 ((uint32_t)0x00100000U) /* Bit 20 */ +#define DSI_PKTRXHDR_DATATYP_5 ((uint32_t)0x00200000U) /* Bit 21 */ +#define DSI_PKTRXHDR_VCN_POS (22) +#define DSI_PKTRXHDR_VCN ((uint32_t)0x00C00000U) /* Bit[23:22] */ +#define DSI_PKTRXHDR_VCN_0 ((uint32_t)0x00400000U) /* Bit 22 */ +#define DSI_PKTRXHDR_VCN_1 ((uint32_t)0x00800000U) /* Bit 23 */ + +/** Bit definition for DSI_IFPRIOSEL register **/ +#define DSI_IFPRIOSEL_IFPRIOSEL ((uint32_t)0x0000FFFFU) /* Bit 0 */ + +/*** Window WATCHDOG ***/ + +/** Bit definition for WWDG_CFG register **/ +#define WWDG_CFG_W ((uint32_t)0x00003FFFU) /* W[13:0] bits (14-bit window value) */ +#define WWDG_CFG_W0 ((uint32_t)0x00000001U) /* Bit 0 */ +#define WWDG_CFG_W1 ((uint32_t)0x00000002U) /* Bit 1 */ +#define WWDG_CFG_W2 ((uint32_t)0x00000004U) /* Bit 2 */ +#define WWDG_CFG_W3 ((uint32_t)0x00000008U) /* Bit 3 */ +#define WWDG_CFG_W4 ((uint32_t)0x00000010U) /* Bit 4 */ +#define WWDG_CFG_W5 ((uint32_t)0x00000020U) /* Bit 5 */ +#define WWDG_CFG_W6 ((uint32_t)0x00000040U) /* Bit 6 */ +#define WWDG_CFG_W7 ((uint32_t)0x00000080U) /* Bit 7 */ +#define WWDG_CFG_W8 ((uint32_t)0x00000100U) /* Bit 8 */ +#define WWDG_CFG_W9 ((uint32_t)0x00000200U) /* Bit 9 */ +#define WWDG_CFG_W10 ((uint32_t)0x00000400U) /* Bit 10 */ +#define WWDG_CFG_W11 ((uint32_t)0x00000800U) /* Bit 11 */ +#define WWDG_CFG_W12 ((uint32_t)0x00001000U) /* Bit 12 */ +#define WWDG_CFG_W13 ((uint32_t)0x00002000U) /* Bit 13 */ + +#define WWDG_CFG_TIMERB ((uint32_t)0x0000C000U) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFG_TIMERB0 ((uint32_t)0x00004000U) /* Bit 0 */ +#define WWDG_CFG_TIMERB1 ((uint32_t)0x00008000U) /* Bit 1 */ + +#define WWDG_CFG_EWINT ((uint32_t)0x00010000U) /* Early Wakeup Interrupt */ + +/** Bit definition for WWDG_CTRL register **/ +#define WWDG_CTRL_T ((uint16_t)0x3FFFU) /*T[13:0] bits(14-bit counter (MSB to LSB)) */ +#define WWDG_CTRL_T0 ((uint16_t)0x0001U) /* Bit 0 */ +#define WWDG_CTRL_T1 ((uint16_t)0x0002U) /* Bit 1 */ +#define WWDG_CTRL_T2 ((uint16_t)0x0004U) /* Bit 2 */ +#define WWDG_CTRL_T3 ((uint16_t)0x0008U) /* Bit 3 */ +#define WWDG_CTRL_T4 ((uint16_t)0x0010U) /* Bit 4 */ +#define WWDG_CTRL_T5 ((uint16_t)0x0020U) /* Bit 5 */ +#define WWDG_CTRL_T6 ((uint16_t)0x0040U) /* Bit 6 */ +#define WWDG_CTRL_T7 ((uint16_t)0x0080U) /* Bit 7 */ +#define WWDG_CTRL_T8 ((uint16_t)0x0100U) /* Bit 8 */ +#define WWDG_CTRL_T9 ((uint16_t)0x0200U) /* Bit 9 */ +#define WWDG_CTRL_T10 ((uint16_t)0x0400U) /* Bit 10 */ +#define WWDG_CTRL_T11 ((uint16_t)0x0800U) /* Bit 11 */ +#define WWDG_CTRL_T12 ((uint16_t)0x1000U) /* Bit 12 */ +#define WWDG_CTRL_T13 ((uint16_t)0x2000U) /* Bit 13 */ + +#define WWDG_CTRL_ACTB ((uint16_t)0x4000U) /* Activation bit */ + +/** Bit definition for WWDG_STS register **/ +#define WWDG_STS_EWINTF ((uint8_t)0x01U) /* Early Wakeup Interrupt Flag */ + +/*** Independent watchdog ***/ + +/** Bit definition for IWDG_KEY register **/ +#define IWDG_KEY_KEYV ((uint16_t)0xFFFFU) /* Key value (write only, read 0000h) */ + +/** Bit definition for IWDG_STS register **/ +#define IWDG_STS_PVU ((uint8_t)0x01U) /* Watchdog prescaler value update */ +#define IWDG_STS_CRVU ((uint8_t)0x02U) /* Watchdog counter reload value update */ +#define IWDG_STS_FRZF ((uint8_t)0x04U) /* The freeze flag */ + +/** Bit definition for IWDG_PREDIV register **/ +#define IWDG_PREDIV_PD ((uint8_t)0x07U) /* PD[2:0] (Prescaler divider) */ +#define IWDG_PREDIV_PD0 ((uint8_t)0x01U) /* Bit 0 */ +#define IWDG_PREDIV_PD1 ((uint8_t)0x02U) /* Bit 1 */ +#define IWDG_PREDIV_PD2 ((uint8_t)0x04U) /* Bit 2 */ + +/** Bit definition for IWDG_RELV register **/ +#define IWDG_RELV_REL ((uint16_t)0x0FFFU) /* Watchdog counter reload value */ + + +/*** Flexible Datarate Controller Area Network ***/ + +/** Bit definition for FDCAN_CREL register **/ +#define FDCAN_CREL_DAY ((uint32_t)0x000000FFU) /* Timestamp Day bits */ +#define FDCAN_CREL_DAY_0 ((uint32_t)0x00000001U) /* Timestamp Day bit 0 */ +#define FDCAN_CREL_DAY_1 ((uint32_t)0x00000002U) /* Timestamp Day bit 1 */ +#define FDCAN_CREL_DAY_2 ((uint32_t)0x00000004U) /* Timestamp Day bit 2 */ +#define FDCAN_CREL_DAY_3 ((uint32_t)0x00000008U) /* Timestamp Day bit 3 */ +#define FDCAN_CREL_DAY_4 ((uint32_t)0x00000010U) /* Timestamp Day bit 4 */ +#define FDCAN_CREL_DAY_5 ((uint32_t)0x00000020U) /* Timestamp Day bit 5 */ +#define FDCAN_CREL_DAY_6 ((uint32_t)0x00000040U) /* Timestamp Day bit 6 */ +#define FDCAN_CREL_DAY_7 ((uint32_t)0x00000080U) /* Timestamp Day bit 7 */ + +#define FDCAN_CREL_MON ((uint32_t)0x0000FF00U) /* Timestamp Month bits */ +#define FDCAN_CREL_MON_0 ((uint32_t)0x00000100U) /* Timestamp Month bit 0 */ +#define FDCAN_CREL_MON_1 ((uint32_t)0x00000200U) /* Timestamp Month bit 1 */ +#define FDCAN_CREL_MON_2 ((uint32_t)0x00000400U) /* Timestamp Month bit 2 */ +#define FDCAN_CREL_MON_3 ((uint32_t)0x00000800U) /* Timestamp Month bit 3 */ +#define FDCAN_CREL_MON_4 ((uint32_t)0x00001000U) /* Timestamp Month bit 4 */ +#define FDCAN_CREL_MON_5 ((uint32_t)0x00002000U) /* Timestamp Month bit 5 */ +#define FDCAN_CREL_MON_6 ((uint32_t)0x00004000U) /* Timestamp Month bit 6 */ +#define FDCAN_CREL_MON_7 ((uint32_t)0x00008000U) /* Timestamp Month bit 7 */ + +#define FDCAN_CREL_YEAR ((uint32_t)0x000F0000U) /* Timestamp Year bits */ +#define FDCAN_CREL_YEAR_0 ((uint32_t)0x00010000U) /* Timestamp Year bit 0 */ +#define FDCAN_CREL_YEAR_1 ((uint32_t)0x00020000U) /* Timestamp Year bit 1 */ +#define FDCAN_CREL_YEAR_2 ((uint32_t)0x00040000U) /* Timestamp Year bit 2 */ +#define FDCAN_CREL_YEAR_3 ((uint32_t)0x00080000U) /* Timestamp Year bit 3 */ + +#define FDCAN_CREL_SUBSTEP ((uint32_t)0x00F00000U) /* Sub-step of Core release bits */ +#define FDCAN_CREL_SUBSTEP_0 ((uint32_t)0x00100000U) /* Sub-step of Core release bit 0 */ +#define FDCAN_CREL_SUBSTEP_1 ((uint32_t)0x00200000U) /* Sub-step of Core release bit 1 */ +#define FDCAN_CREL_SUBSTEP_2 ((uint32_t)0x00400000U) /* Sub-step of Core release bit 2 */ +#define FDCAN_CREL_SUBSTEP_3 ((uint32_t)0x00800000U) /* Sub-step of Core release bit 3 */ + +#define FDCAN_CREL_STEP ((uint32_t)0x0F000000U) /* Step of Core release bits */ +#define FDCAN_CREL_STEP_0 ((uint32_t)0x01000000U) /* Step of Core release bit 0 */ +#define FDCAN_CREL_STEP_1 ((uint32_t)0x02000000U) /* Step of Core release bit 1 */ +#define FDCAN_CREL_STEP_2 ((uint32_t)0x04000000U) /* Step of Core release bit 2 */ +#define FDCAN_CREL_STEP_3 ((uint32_t)0x08000000U) /* Step of Core release bit 3 */ + +#define FDCAN_CREL_REL ((uint32_t)0xF0000000U) /* Core release bits */ +#define FDCAN_CREL_REL_0 ((uint32_t)0x10000000U) /* Core release bits 0 */ +#define FDCAN_CREL_REL_1 ((uint32_t)0x20000000U) /* Core release bits 1 */ +#define FDCAN_CREL_REL_2 ((uint32_t)0x40000000U) /* Core release bits 2 */ +#define FDCAN_CREL_REL_3 ((uint32_t)0x80000000U) /* Core release bits 3 */ + +/** Bit definition for FDCAN_ENDN register **/ +#define FDCAN_ENDN_ETV ((uint32_t)0xFFFFFFFFU) /* Endianness Test Value */ + +/** Bit definition for FDCAN_DBTP register **/ +#define FDCAN_DBTP_DSJW ((uint32_t)0x0000000FU) /* Synchronization Jump Width bits */ +#define FDCAN_DBTP_DTSEG2 ((uint32_t)0x000000F0U) /* Data time segment after sample point bits */ +#define FDCAN_DBTP_DTSEG1 ((uint32_t)0x00001F00U) /* Data time segment before sample point bits */ +#define FDCAN_DBTP_DBRP ((uint32_t)0x001F0000U) /* Data BIt Rate Prescaler bits */ + +#define FDCAN_DBTP_TDC ((uint32_t)0x00800000U) /* Transceiver Delay Compensation */ + +/** Bit definition for FDCAN_TEST register **/ +#define FDCAN_TEST_LBCK ((uint32_t)0x00000010U) /* Loop Back Mode */ +#define FDCAN_TEST_TX ((uint32_t)0x00000060U) /* Control bits of Transmit Pin */ +#define FDCAN_TEST_RX ((uint32_t)0x00000080U) /* Receive Pin status */ + +/** Bit definition for FDCAN_RWD register **/ +#define FDCAN_RWD_WDC ((uint32_t)0x000000FFU) /* Watchdog Configuration bits */ +#define FDCAN_RWD_WDC_0 ((uint32_t)0x00000001U) /* Watchdog Configuration bit 0 */ +#define FDCAN_RWD_WDC_1 ((uint32_t)0x00000002U) /* Watchdog Configuration bit 1 */ +#define FDCAN_RWD_WDC_2 ((uint32_t)0x00000004U) /* Watchdog Configuration bit 2 */ +#define FDCAN_RWD_WDC_3 ((uint32_t)0x00000008U) /* Watchdog Configuration bit 3 */ +#define FDCAN_RWD_WDC_4 ((uint32_t)0x00000010U) /* Watchdog Configuration bit 4 */ +#define FDCAN_RWD_WDC_5 ((uint32_t)0x00000020U) /* Watchdog Configuration bit 5 */ +#define FDCAN_RWD_WDC_6 ((uint32_t)0x00000040U) /* Watchdog Configuration bit 6 */ +#define FDCAN_RWD_WDC_7 ((uint32_t)0x00000080U) /* Watchdog Configuration bit 7 */ + +#define FDCAN_RWD_WDV ((uint32_t)0x0000FF00U) /* Watchdog Value bits */ +#define FDCAN_RWD_WDV_0 ((uint32_t)0x00000100U) /* Watchdog Value bit 0 */ +#define FDCAN_RWD_WDV_1 ((uint32_t)0x00000200U) /* Watchdog Value bit 1 */ +#define FDCAN_RWD_WDV_2 ((uint32_t)0x00000400U) /* Watchdog Value bit 2 */ +#define FDCAN_RWD_WDV_3 ((uint32_t)0x00000800U) /* Watchdog Value bit 3 */ +#define FDCAN_RWD_WDV_4 ((uint32_t)0x00001000U) /* Watchdog Value bit 4 */ +#define FDCAN_RWD_WDV_5 ((uint32_t)0x00002000U) /* Watchdog Value bit 5 */ +#define FDCAN_RWD_WDV_6 ((uint32_t)0x00004000U) /* Watchdog Value bit 6 */ +#define FDCAN_RWD_WDV_7 ((uint32_t)0x00008000U) /* Watchdog Value bit 7 */ + +/** Bit definition for FDCAN_CCCR register **/ +#define FDCAN_CCCR_INIT ((uint32_t)0x00000001U) /* Initialization */ +#define FDCAN_CCCR_CCE ((uint32_t)0x00000002U) /* Configuration Change Enable */ +#define FDCAN_CCCR_ASM ((uint32_t)0x00000004U) /* ASM Restricted Operation Mode */ +#define FDCAN_CCCR_CSA ((uint32_t)0x00000008U) /* Clock Stop Acknowledge */ +#define FDCAN_CCCR_CSR ((uint32_t)0x00000010U) /* Clock Stop Request */ +#define FDCAN_CCCR_MON ((uint32_t)0x00000020U) /* Bus Monitoring Mode */ +#define FDCAN_CCCR_DAR ((uint32_t)0x00000040U) /* Disable Automatic Retransmission */ +#define FDCAN_CCCR_TEST ((uint32_t)0x00000080U) /* Test Mode Enable */ +#define FDCAN_CCCR_FDOE ((uint32_t)0x00000100U) /* FD Operation Enable */ +#define FDCAN_CCCR_BRSE ((uint32_t)0x00000200U) /* FDCAN Bit Rate Switch Enable */ +#define FDCAN_CCCR_PXHD ((uint32_t)0x00001000U) /* Protocol Exception Handling Disable */ +#define FDCAN_CCCR_EFBI ((uint32_t)0x00002000U) /* Edge Filtering during Bus Integration */ +#define FDCAN_CCCR_TXP ((uint32_t)0x00004000U) /* Two CAN bit times Transmit Pause */ +#define FDCAN_CCCR_NISO ((uint32_t)0x00008000U) /* Non ISO Operation */ + +/** Bit definition for FDCAN_NBTP register **/ +#define FDCAN_NBTP_NTSEG2 ((uint32_t)0x0000007FU) /* Nominal Time segment after sample point */ +#define FDCAN_NBTP_NTSEG1 ((uint32_t)0x0000FF00U) /* Nominal Time segment before sample point bits bits */ +#define FDCAN_NBTP_NBRP ((uint32_t)0x01FF0000U) /* Bit Rate Prescaler bits */ +#define FDCAN_NBTP_NSJW ((uint32_t)0xFE000000U) /* Nominal (Re)Synchronization Jump Width bits */ + +/** Bit definition for FDCAN_TSCC register **/ +#define FDCAN_TSCC_TSS ((uint32_t)0x00000003U) /* Timestamp Select bits */ +#define FDCAN_TSCC_CONSTANT ((uint32_t)0x00000000U) /* Timestamp counter is always 0x0000 */ +#define FDCAN_TSCC_INC_TCP ((uint32_t)0x00000001U) /* Timestamp counter is increasd according to TCP */ +#define FDCAN_TSCC_USE_EXT ((uint32_t)0x00000002U) /* Use Extern Timestamp counter */ + +#define FDCAN_TSCC_TCP ((uint32_t)0x000F0000U) /* Timestamp Counter Prescaler bits */ +#define FDCAN_TSCC_TCP_DIV1 ((uint32_t)0x00000000U) /* Timestamp counter time unit in equal to CAN bit time */ +#define FDCAN_TSCC_TCP_DIV2 ((uint32_t)0x00010000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TSCC_TCP_DIV3 ((uint32_t)0x00020000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TSCC_TCP_DIV4 ((uint32_t)0x00030000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TSCC_TCP_DIV5 ((uint32_t)0x00040000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TSCC_TCP_DIV6 ((uint32_t)0x00050000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TSCC_TCP_DIV7 ((uint32_t)0x00060000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TSCC_TCP_DIV8 ((uint32_t)0x00070000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TSCC_TCP_DIV9 ((uint32_t)0x00080000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TSCC_TCP_DIV10 ((uint32_t)0x00090000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TSCC_TCP_DIV11 ((uint32_t)0x000A0000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TSCC_TCP_DIV12 ((uint32_t)0x000B0000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TSCC_TCP_DIV13 ((uint32_t)0x000C0000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TSCC_TCP_DIV14 ((uint32_t)0x000D0000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TSCC_TCP_DIV15 ((uint32_t)0x000E0000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TSCC_TCP_DIV16 ((uint32_t)0x000F0000U) /* Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ + +/** Bit definition for FDCAN_TSCV register **/ +#define FDCAN_TSCV_TSC ((uint32_t)0x0000FFFFU) /* Timestamp Counter */ + +/** Bit definition for FDCAN_TOCC register **/ +#define FDCAN_TOCC_ETOC ((uint32_t)0x00000001U) /* Enable Timeout Counter */ + +#define FDCAN_TOCC_TOS ((uint32_t)0x00000006U) /* Timeout Select bits */ +#define FDCAN_TOCC_TOS_CONTINUOUS ((uint32_t)0x00000000U) /* Continuous operation */ +#define FDCAN_TOCC_TOS_TX_EVENT_FIFO ((uint32_t)0x00000002U) /* Controlled by Tx event FIFO */ +#define FDCAN_TOCC_TOS_RX_FIFO0 ((uint32_t)0x00000004U) /* Controlled by Rx FIFO 0 */ +#define FDCAN_TOCC_TOS_RX_FIFO1 ((uint32_t)0x00000006U) /* Controlled by Rx FIFO 1 */ + +#define FDCAN_TOCC_TOP ((uint32_t)0xFFFF0000U) /* Timeout Period */ + +/** Bit definition for FDCAN_TOCV register **/ +#define FDCAN_TOCV_TOC ((uint32_t)0x0000FFFFU) /* Timeout Counter */ + +/** Bit definition for FDCAN_ECR register **/ +#define FDCAN_ECR_TEC ((uint32_t)0x000000FFU) /* Transmit Error Counter */ +#define FDCAN_ECR_REC ((uint32_t)0x00007F00U) /* Receive Error Counter */ +#define FDCAN_ECR_RP ((uint32_t)0x00008000U) /* Receive Error Passive */ +#define FDCAN_ECR_CEL ((uint32_t)0x00FF0000U) /* CAN Error Logging */ + +/** Bit definition for FDCAN_PSR register **/ +#define FDCAN_PSR_LEC ((uint32_t)0x00000007U) /* Last Error Code bits */ +#define FDCAN_PSR_LEC_NONE ((uint32_t)0x00000000U) /* No error occurred */ +#define FDCAN_PSR_LEC_STUFF ((uint32_t)0x00000001U) /* Stuff error */ +#define FDCAN_PSR_LEC_FORM ((uint32_t)0x00000002U) /* Form error */ +#define FDCAN_PSR_LEC_ACK ((uint32_t)0x00000003U) /* Acknowledge error */ +#define FDCAN_PSR_LEC_BIT1 ((uint32_t)0x00000004U) /* Bit 1 (recessive) error */ +#define FDCAN_PSR_LEC_BIT0 ((uint32_t)0x00000005U) /* Bit 0 (dominant) error */ +#define FDCAN_PSR_LEC_CRC ((uint32_t)0x00000006U) /* CRC check sum error */ +#define FDCAN_PSR_LEC_NO_CHANGE ((uint32_t)0x00000007U) /* No change since last read */ + +#define FDCAN_PSR_ACT ((uint32_t)0x00000018U) /* Activity bits */ +#define FDCAN_PSR_ACT_SYNC ((uint32_t)0x00000000U) /* Node is synchronizing on CAN communication */ +#define FDCAN_PSR_ACT_IDLE ((uint32_t)0x00000008U) /* Node is neither receiver nor transmitter */ +#define FDCAN_PSR_ACT_RX ((uint32_t)0x00000010U) /* Node is operating as receiver */ +#define FDCAN_PSR_ACT_TX ((uint32_t)0x00000018U) /* Node is operating as transmitter */ + +#define FDCAN_PSR_EP ((uint32_t)0x00000020U) /* Error Passive bit */ +#define FDCAN_PSR_EW ((uint32_t)0x00000040U) /* Warning Status bit */ +#define FDCAN_PSR_BO ((uint32_t)0x00000080U) /* Bus_Off Status */ + +#define FDCAN_PSR_DLEC ((uint32_t)0x00000700U) /* Data Last Error Code bits */ +#define FDCAN_PSR_DLEC_NONE ((uint32_t)0x00000000U) /* No error occurred */ +#define FDCAN_PSR_DLEC_STUFF ((uint32_t)0x00000100U) /* Stuff error */ +#define FDCAN_PSR_DLEC_FORM ((uint32_t)0x00000200U) /* Form error */ +#define FDCAN_PSR_DLEC_ACK ((uint32_t)0x00000300U) /* Acknowledge error */ +#define FDCAN_PSR_DLEC_BIT1 ((uint32_t)0x00000400U) /* Bit 1 (recessive) error */ +#define FDCAN_PSR_DLEC_BIT0 ((uint32_t)0x00000500U) /* Bit 0 (dominant) error */ +#define FDCAN_PSR_DLEC_CRC ((uint32_t)0x00000600U) /* CRC check sum error */ +#define FDCAN_PSR_DLEC_NO_CHANGE ((uint32_t)0x00000700U) /* No change since last read */ + +#define FDCAN_PSR_RESI ((uint32_t)0x00000800U) /* ESI flag of last received FDCAN Message */ +#define FDCAN_PSR_RBRS ((uint32_t)0x00001000U) /* BRS flag of last received FDCAN Message */ +#define FDCAN_PSR_RFDF ((uint32_t)0x00002000U) /* Received FDCAN Message */ +#define FDCAN_PSR_PXE ((uint32_t)0x00004000U) /* Protocol Exception Event */ + +#define FDCAN_PSR_TDCV ((uint32_t)0x007F0000U) /* Transmitter Delay Compensation Value bits */ + +/** Bit definition for FDCAN_TDCR register **/ +#define FDCAN_TDCR_TDCF ((uint32_t)0x0000007FU) /* Transmitter Delay Compensation Filter bits */ +#define FDCAN_TDCR_TDCF_0 ((uint32_t)0x00000001U) /* Transmitter Delay Compensation Filter bit 0 */ +#define FDCAN_TDCR_TDCF_1 ((uint32_t)0x00000002U) /* Transmitter Delay Compensation Filter bit 1 */ +#define FDCAN_TDCR_TDCF_2 ((uint32_t)0x00000004U) /* Transmitter Delay Compensation Filter bit 2 */ +#define FDCAN_TDCR_TDCF_3 ((uint32_t)0x00000008U) /* Transmitter Delay Compensation Filter bit 3 */ +#define FDCAN_TDCR_TDCF_4 ((uint32_t)0x00000010U) /* Transmitter Delay Compensation Filter bit 4 */ +#define FDCAN_TDCR_TDCF_5 ((uint32_t)0x00000020U) /* Transmitter Delay Compensation Filter bit 5 */ +#define FDCAN_TDCR_TDCF_6 ((uint32_t)0x00000040U) /* Transmitter Delay Compensation Filter bit 6 */ + +#define FDCAN_TDCR_TDCO ((uint32_t)0x00007F00U) /* Transmitter Delay Compensation Offset bits */ +#define FDCAN_TDCR_TDCO_0 ((uint32_t)0x00000100U) /* Transmitter Delay Compensation Offset bit 0 */ +#define FDCAN_TDCR_TDCO_1 ((uint32_t)0x00000200U) /* Transmitter Delay Compensation Offset bit 1 */ +#define FDCAN_TDCR_TDCO_2 ((uint32_t)0x00000400U) /* Transmitter Delay Compensation Offset bit 2 */ +#define FDCAN_TDCR_TDCO_3 ((uint32_t)0x00000800U) /* Transmitter Delay Compensation Offset bit 3 */ +#define FDCAN_TDCR_TDCO_4 ((uint32_t)0x00001000U) /* Transmitter Delay Compensation Offset bit 4 */ +#define FDCAN_TDCR_TDCO_5 ((uint32_t)0x00002000U) /* Transmitter Delay Compensation Offset bit 5 */ +#define FDCAN_TDCR_TDCO_6 ((uint32_t)0x00004000U) /* Transmitter Delay Compensation Offset bit 6 */ + +/** Bit definition for FDCAN_IR register **/ +#define FDCAN_IR_RF0N ((uint32_t)0x00000001U) /* Rx FIFO 0 New Message */ +#define FDCAN_IR_RF0W ((uint32_t)0x00000002U) /* Rx FIFO 0 Watermark Reached */ +#define FDCAN_IR_RF0F ((uint32_t)0x00000004U) /* Rx FIFO 0 Full */ +#define FDCAN_IR_RF0L ((uint32_t)0x00000008U) /* Rx FIFO 0 Message Lost */ +#define FDCAN_IR_RF1N ((uint32_t)0x00000010U) /* Rx FIFO 1 New Message */ +#define FDCAN_IR_RF1W ((uint32_t)0x00000020U) /* Rx FIFO 1 Watermark Reached */ +#define FDCAN_IR_RF1F ((uint32_t)0x00000040U) /* Rx FIFO 1 Full */ +#define FDCAN_IR_RF1L ((uint32_t)0x00000080U) /* Rx FIFO 1 Message Lost */ +#define FDCAN_IR_HPM ((uint32_t)0x00000100U) /* High Priority Message */ +#define FDCAN_IR_TC ((uint32_t)0x00000200U) /* Transmission Completed */ +#define FDCAN_IR_TCF ((uint32_t)0x00000400U) /* Transmission Cancellation Finished */ +#define FDCAN_IR_TFE ((uint32_t)0x00000800U) /* Tx FIFO Empty */ +#define FDCAN_IR_TEFN ((uint32_t)0x00001000U) /* Tx Event FIFO New Entry */ +#define FDCAN_IR_TEFW ((uint32_t)0x00002000U) /* Tx Event FIFO Watermark Reached */ +#define FDCAN_IR_TEFF ((uint32_t)0x00004000U) /* Tx Event FIFO Full */ +#define FDCAN_IR_TEFL ((uint32_t)0x00008000U) /* Tx Event FIFO Element Lost */ +#define FDCAN_IR_TSW ((uint32_t)0x00010000U) /* Timestamp Wraparound */ +#define FDCAN_IR_MRAF ((uint32_t)0x00020000U) /* Message RAM Access Failure */ +#define FDCAN_IR_TOO ((uint32_t)0x00040000U) /* Timeout Occurred */ +#define FDCAN_IR_DRX ((uint32_t)0x00080000U) /* Bit Error Uncorrected */ +#define FDCAN_IR_BEC ((uint32_t)0x00100000U) /* Bit Error Corrected */ +#define FDCAN_IR_BEU ((uint32_t)0x00200000U) /* Bit Error Uncorrected */ +#define FDCAN_IR_ELO ((uint32_t)0x00400000U) /* Error Logging Overflow */ +#define FDCAN_IR_EP ((uint32_t)0x00800000U) /* Error Passive */ +#define FDCAN_IR_EW ((uint32_t)0x01000000U) /* Warning Status */ +#define FDCAN_IR_BO ((uint32_t)0x02000000U) /* Bus_Off Status */ +#define FDCAN_IR_WDI ((uint32_t)0x04000000U) /* Watchdog Interrupt */ +#define FDCAN_IR_PEA ((uint32_t)0x08000000U) /* Protocol Error in Arbitration Phase */ +#define FDCAN_IR_PED ((uint32_t)0x10000000U) /* Protocol Error in Data Phase */ +#define FDCAN_IR_ARA ((uint32_t)0x20000000U) /* Access to Reserved Address */ + +/** Bit definition for FDCAN_IE register **/ +#define FDCAN_IE_RF0NE ((uint32_t)0x00000001U) /* Rx FIFO 0 New Message interrupt enable */ +#define FDCAN_IE_RF0WE ((uint32_t)0x00000002U) /* Rx FIFO 0 Watermark Reached interrupt enable */ +#define FDCAN_IE_RF0FE ((uint32_t)0x00000004U) /* Rx FIFO 0 Full interrupt enable */ +#define FDCAN_IE_RF0LE ((uint32_t)0x00000008U) /* Rx FIFO 0 Message Lost interrupt enable */ +#define FDCAN_IE_RF1NE ((uint32_t)0x00000010U) /* Rx FIFO 1 New Message interrupt enable */ +#define FDCAN_IE_RF1WE ((uint32_t)0x00000020U) /* Rx FIFO 1 Watermark Reached interrupt enable */ +#define FDCAN_IE_RF1FE ((uint32_t)0x00000040U) /* Rx FIFO 1 Full interrupt enable */ +#define FDCAN_IE_RF1LE ((uint32_t)0x00000080U) /* Rx FIFO 1 Message Lost interrupt enable */ +#define FDCAN_IE_HPME ((uint32_t)0x00000100U) /* High Priority Message interrupt enable */ +#define FDCAN_IE_TCE ((uint32_t)0x00000200U) /* Transmission Completed interrupt enable */ +#define FDCAN_IE_TCFE ((uint32_t)0x00000400U) /* Transmission Cancellation Finished interrupt enable */ +#define FDCAN_IE_TFEE ((uint32_t)0x00000800U) /* Tx FIFO Empty interrupt enable */ +#define FDCAN_IE_TEFNE ((uint32_t)0x00001000U) /* Tx Event FIFO New Entry interrupt enable */ +#define FDCAN_IE_TEFWE ((uint32_t)0x00002000U) /* Tx Event FIFO Watermark Reached interrupt enable */ +#define FDCAN_IE_TEFFE ((uint32_t)0x00004000U) /* Tx Event FIFO Full interrupt enable */ +#define FDCAN_IE_TEFLE ((uint32_t)0x00008000U) /* Tx Event FIFO Element Lost interrupt enable */ +#define FDCAN_IE_TSWE ((uint32_t)0x00010000U) /* Timestamp Wraparound interrupt enable */ +#define FDCAN_IE_MRAFE ((uint32_t)0x00020000U) /* Message RAM Access Failure interrupt enable */ +#define FDCAN_IE_TOOE ((uint32_t)0x00040000U) /* Timeout Occurred interrupt enable */ +#define FDCAN_IE_DRXE ((uint32_t)0x00080000U) /* Message stored to Dedicated Rx Buffer interrupt enable */ +#define FDCAN_IE_BECE ((uint32_t)0x00100000U) /* Bit Error Corrected interrupt enable */ +#define FDCAN_IE_BEUE ((uint32_t)0x00200000U) /* Bit Error Uncorrected interrupt enable */ +#define FDCAN_IE_ELOE ((uint32_t)0x00400000U) /* Error Logging Overflow interrupt enable */ +#define FDCAN_IE_EPE ((uint32_t)0x00800000U) /* Error Passive interrupt enable */ +#define FDCAN_IE_EWE ((uint32_t)0x01000000U) /* Warning Status interrupt enable */ +#define FDCAN_IE_BOE ((uint32_t)0x02000000U) /* Bus_Off Status interrupt enable */ +#define FDCAN_IE_WDIE ((uint32_t)0x04000000U) /* Watchdog Interrupt enable */ +#define FDCAN_IE_PEAE ((uint32_t)0x08000000U) /* Protocol Error in Arbitration Phase interrupt enable */ +#define FDCAN_IE_PEDE ((uint32_t)0x10000000U) /* Protocol Error in Data Phase interrupt enable */ +#define FDCAN_IE_ARAE ((uint32_t)0x20000000U) /* AcEcess to Reserved Address interrupt enable */ + +/** Bit definition for FDCAN_ILS register **/ +#define FDCAN_ILS_RF0NL ((uint32_t)0x00000001U) /* Rx FIFO 0 New Message Line */ +#define FDCAN_ILS_RF0WL ((uint32_t)0x00000002U) /* Rx FIFO 0 Watermark Reached Line */ +#define FDCAN_ILS_RF0FL ((uint32_t)0x00000004U) /* Rx FIFO 0 Full Line */ +#define FDCAN_ILS_RF0LL ((uint32_t)0x00000008U) /* Rx FIFO 0 Message Lost Line */ +#define FDCAN_ILS_RF1NL ((uint32_t)0x00000010U) /* Rx FIFO 1 New Message Line */ +#define FDCAN_ILS_RF1WL ((uint32_t)0x00000020U) /* Rx FIFO 1 Watermark Reached Line */ +#define FDCAN_ILS_RF1FL ((uint32_t)0x00000040U) /* Rx FIFO 1 Full Line */ +#define FDCAN_ILS_RF1LL ((uint32_t)0x00000080U) /* Rx FIFO 1 Message Lost Line */ +#define FDCAN_ILS_HPML ((uint32_t)0x00000100U) /* High Priority Message Line */ +#define FDCAN_ILS_TCL ((uint32_t)0x00000200U) /* Transmission Completed Line */ +#define FDCAN_ILS_TCFL ((uint32_t)0x00000400U) /* Transmission Cancellation Finished Line */ +#define FDCAN_ILS_TFEL ((uint32_t)0x00000800U) /* Tx FIFO Empty Line */ +#define FDCAN_ILS_TEFNL ((uint32_t)0x00001000U) /* Tx Event FIFO New Entry Line */ +#define FDCAN_ILS_TEFWL ((uint32_t)0x00002000U) /* Tx Event FIFO Watermark Reached Line */ +#define FDCAN_ILS_TEFFL ((uint32_t)0x00004000U) /* Tx Event FIFO Full Line */ +#define FDCAN_ILS_TEFLL ((uint32_t)0x00008000U) /* Tx Event FIFO Element Lost Line */ +#define FDCAN_ILS_TSWL ((uint32_t)0x00010000U) /* Timestamp Wraparound Line */ +#define FDCAN_ILS_MRAFL ((uint32_t)0x00020000U) /* Message RAM Access Failure Line */ +#define FDCAN_ILS_TOOL ((uint32_t)0x00040000U) /* Timeout Occurred Line */ +#define FDCAN_ILS_DRXL ((uint32_t)0x00080000U) /* Message stored to Dedicated Rx Buffer Line */ +#define FDCAN_ILS_BECL ((uint32_t)0x00100000U) /* Bit Error Corrected interrupt Line */ +#define FDCAN_ILS_BEUL ((uint32_t)0x00200000U) /* Bit Error Uncorrected interrupt Line */ +#define FDCAN_ILS_ELOL ((uint32_t)0x00400000U) /* Error Logging Overflow Line */ +#define FDCAN_ILS_EPL ((uint32_t)0x00800000U) /* Error Passive Line */ +#define FDCAN_ILS_EWL ((uint32_t)0x01000000U) /* Warning Status Line */ +#define FDCAN_ILS_BOL ((uint32_t)0x02000000U) /* Bus_Off Status Line */ +#define FDCAN_ILS_WDIL ((uint32_t)0x04000000U) /* Watchdog Line */ +#define FDCAN_ILS_PEAL ((uint32_t)0x08000000U) /* Protocol Error in Arbitration Phase Line */ +#define FDCAN_ILS_PEDL ((uint32_t)0x10000000U) /* Protocol Error in Data Phase Line */ +#define FDCAN_ILS_ARAL ((uint32_t)0x20000000U) /* Access to Reserved Address Line */ + +/** Bit definition for FDCAN_ILE register **/ +#define FDCAN_ILE_EINT0 ((uint32_t)0x00000001U) /* Enable Interrupt Line 0 */ +#define FDCAN_ILE_EINT1 ((uint32_t)0x00000002U) /* Enable Interrupt Line 1 */ + +/** Bit definition for FDCAN_GFC register **/ +#define FDCAN_GFC_RRFE ((uint32_t)0x00000001U) /* Reject Extended Remote Frames */ +#define FDCAN_GFC_RRFS ((uint32_t)0x00000002U) /* Reject Standard Remote Frames */ + +#define FDCAN_GFC_ANFE ((uint32_t)0x0000000CU) /* Accept Extended Non-matching Frames bits */ +#define FDCAN_GFC_ANFE_0 ((uint32_t)0x00000004U) /* Accept Extended Non-matching Frames bit 0 */ +#define FDCAN_GFC_ANFE_1 ((uint32_t)0x00000008U) /* Accept Extended Non-matching Frames bit 1 */ + +#define FDCAN_GFC_ANFS ((uint32_t)0x00000030U) /* Accept Standard Non-matching Frames bits */ +#define FDCAN_GFC_ANFS_0 ((uint32_t)0x00000010U) /* Accept Standard Non-matching Frames bit 0 */ +#define FDCAN_GFC_ANFS_1 ((uint32_t)0x00000020U) /* Accept Standard Non-matching Frames bit 1 */ + +/** Bit definition for FDCAN_SIDFC register **/ +#define FDCAN_SIDFC_FLSSA ((uint32_t)0x0000FFFCU) /* Filter List Standard Start Address */ +#define FDCAN_SIDFC_LSS ((uint32_t)0x00FF0000U) /* List Size Standard */ + +/** Bit definition for FDCAN_XIDFC register **/ +#define FDCAN_XIDFC_FLESA ((uint32_t)0x0000FFFCU) /* Filter List Extended Start Address */ +#define FDCAN_XIDFC_LSE ((uint32_t)0x007F0000U) /* List Size Extended */ + +/** Bit definition for FDCAN_XIDAM register **/ +#define FDCAN_XIDAM_EIDM ((uint32_t)0x1FFFFFFFU) /* Extended ID Mask */ + +/** Bit definition for FDCAN_HPMS register **/ +#define FDCAN_HPMS_BIDX ((uint32_t)0x0000003FU) /* Buffer Index bits */ + +#define FDCAN_HPMS_MSI ((uint32_t)0x000000C0U) /* Message Storage Indicator bits */ +#define FDCAN_HPMS_MSI_NO_FIFO ((uint32_t)0x00000000U) /* No fifo selected */ +#define FDCAN_HPMS_MSI_MSG_LOST ((uint32_t)0x00000040U) /* Message lost */ +#define FDCAN_HPMS_MSI_FIFO0 ((uint32_t)0x00000080U) /* Message Stored in FIFO 0 */ +#define FDCAN_HPMS_MSI_FIFO1 ((uint32_t)0x000000C0U) /* Message Stored in FIFO 1 */ + +#define FDCAN_HPMS_FIDX ((uint32_t)0x00007F00U) /* Filter Index bits */ + +#define FDCAN_HPMS_FLST ((uint32_t)0x00008000U) /* Filter List */ +#define FDCAN_HPMS_FLST_STD ((uint32_t)0x00000000U) /* Standard Filter List */ +#define FDCAN_HPMS_FLST_EXT ((uint32_t)0x00008000U) /* Extended Filter List */ + +/** Bit definition for FDCAN_NDAT1 register **/ +#define FDCAN_NDAT1_ND0 ((uint32_t)0x00000001U) /* New Data flag of Rx Buffer 0 */ +#define FDCAN_NDAT1_ND1 ((uint32_t)0x00000002U) /* New Data flag of Rx Buffer 1 */ +#define FDCAN_NDAT1_ND2 ((uint32_t)0x00000004U) /* New Data flag of Rx Buffer 2 */ +#define FDCAN_NDAT1_ND3 ((uint32_t)0x00000008U) /* New Data flag of Rx Buffer 3 */ +#define FDCAN_NDAT1_ND4 ((uint32_t)0x00000010U) /* New Data flag of Rx Buffer 4 */ +#define FDCAN_NDAT1_ND5 ((uint32_t)0x00000020U) /* New Data flag of Rx Buffer 5 */ +#define FDCAN_NDAT1_ND6 ((uint32_t)0x00000040U) /* New Data flag of Rx Buffer 6 */ +#define FDCAN_NDAT1_ND7 ((uint32_t)0x00000080U) /* New Data flag of Rx Buffer 7 */ +#define FDCAN_NDAT1_ND8 ((uint32_t)0x00000100U) /* New Data flag of Rx Buffer 8 */ +#define FDCAN_NDAT1_ND9 ((uint32_t)0x00000200U) /* New Data flag of Rx Buffer 9 */ +#define FDCAN_NDAT1_ND10 ((uint32_t)0x00000400U) /* New Data flag of Rx Buffer 10 */ +#define FDCAN_NDAT1_ND11 ((uint32_t)0x00000800U) /* New Data flag of Rx Buffer 11 */ +#define FDCAN_NDAT1_ND12 ((uint32_t)0x00001000U) /* New Data flag of Rx Buffer 12 */ +#define FDCAN_NDAT1_ND13 ((uint32_t)0x00002000U) /* New Data flag of Rx Buffer 13 */ +#define FDCAN_NDAT1_ND14 ((uint32_t)0x00004000U) /* New Data flag of Rx Buffer 14 */ +#define FDCAN_NDAT1_ND15 ((uint32_t)0x00008000U) /* New Data flag of Rx Buffer 15 */ +#define FDCAN_NDAT1_ND16 ((uint32_t)0x00010000U) /* New Data flag of Rx Buffer 16 */ +#define FDCAN_NDAT1_ND17 ((uint32_t)0x00020000U) /* New Data flag of Rx Buffer 17 */ +#define FDCAN_NDAT1_ND18 ((uint32_t)0x00040000U) /* New Data flag of Rx Buffer 18 */ +#define FDCAN_NDAT1_ND19 ((uint32_t)0x00080000U) /* New Data flag of Rx Buffer 19 */ +#define FDCAN_NDAT1_ND20 ((uint32_t)0x00100000U) /* New Data flag of Rx Buffer 20 */ +#define FDCAN_NDAT1_ND21 ((uint32_t)0x00200000U) /* New Data flag of Rx Buffer 21 */ +#define FDCAN_NDAT1_ND22 ((uint32_t)0x00400000U) /* New Data flag of Rx Buffer 22 */ +#define FDCAN_NDAT1_ND23 ((uint32_t)0x00800000U) /* New Data flag of Rx Buffer 23 */ +#define FDCAN_NDAT1_ND24 ((uint32_t)0x01000000U) /* New Data flag of Rx Buffer 24 */ +#define FDCAN_NDAT1_ND25 ((uint32_t)0x02000000U) /* New Data flag of Rx Buffer 25 */ +#define FDCAN_NDAT1_ND26 ((uint32_t)0x04000000U) /* New Data flag of Rx Buffer 26 */ +#define FDCAN_NDAT1_ND27 ((uint32_t)0x08000000U) /* New Data flag of Rx Buffer 27 */ +#define FDCAN_NDAT1_ND28 ((uint32_t)0x10000000U) /* New Data flag of Rx Buffer 28 */ +#define FDCAN_NDAT1_ND29 ((uint32_t)0x20000000U) /* New Data flag of Rx Buffer 29 */ +#define FDCAN_NDAT1_ND30 ((uint32_t)0x40000000U) /* New Data flag of Rx Buffer 30 */ +#define FDCAN_NDAT1_ND31 ((uint32_t)0x80000000U) /* New Data flag of Rx Buffer 31 */ + +/** Bit definition for FDCAN_NDAT2 register **/ +#define FDCAN_NDAT2_ND32 ((uint32_t)0x00000001U) /* New Data flag of Rx Buffer 32 */ +#define FDCAN_NDAT2_ND33 ((uint32_t)0x00000002U) /* New Data flag of Rx Buffer 33 */ +#define FDCAN_NDAT2_ND34 ((uint32_t)0x00000004U) /* New Data flag of Rx Buffer 34 */ +#define FDCAN_NDAT2_ND35 ((uint32_t)0x00000008U) /* New Data flag of Rx Buffer 35 */ +#define FDCAN_NDAT2_ND36 ((uint32_t)0x00000010U) /* New Data flag of Rx Buffer 36 */ +#define FDCAN_NDAT2_ND37 ((uint32_t)0x00000020U) /* New Data flag of Rx Buffer 37 */ +#define FDCAN_NDAT2_ND38 ((uint32_t)0x00000040U) /* New Data flag of Rx Buffer 38 */ +#define FDCAN_NDAT2_ND39 ((uint32_t)0x00000080U) /* New Data flag of Rx Buffer 39 */ +#define FDCAN_NDAT2_ND40 ((uint32_t)0x00000100U) /* New Data flag of Rx Buffer 40 */ +#define FDCAN_NDAT2_ND41 ((uint32_t)0x00000200U) /* New Data flag of Rx Buffer 41 */ +#define FDCAN_NDAT2_ND42 ((uint32_t)0x00000400U) /* New Data flag of Rx Buffer 42 */ +#define FDCAN_NDAT2_ND43 ((uint32_t)0x00000800U) /* New Data flag of Rx Buffer 43 */ +#define FDCAN_NDAT2_ND44 ((uint32_t)0x00001000U) /* New Data flag of Rx Buffer 44 */ +#define FDCAN_NDAT2_ND45 ((uint32_t)0x00002000U) /* New Data flag of Rx Buffer 45 */ +#define FDCAN_NDAT2_ND46 ((uint32_t)0x00004000U) /* New Data flag of Rx Buffer 46 */ +#define FDCAN_NDAT2_ND47 ((uint32_t)0x00008000U) /* New Data flag of Rx Buffer 47 */ +#define FDCAN_NDAT2_ND48 ((uint32_t)0x00010000U) /* New Data flag of Rx Buffer 48 */ +#define FDCAN_NDAT2_ND49 ((uint32_t)0x00020000U) /* New Data flag of Rx Buffer 49 */ +#define FDCAN_NDAT2_ND50 ((uint32_t)0x00040000U) /* New Data flag of Rx Buffer 50 */ +#define FDCAN_NDAT2_ND51 ((uint32_t)0x00080000U) /* New Data flag of Rx Buffer 51 */ +#define FDCAN_NDAT2_ND52 ((uint32_t)0x00100000U) /* New Data flag of Rx Buffer 52 */ +#define FDCAN_NDAT2_ND53 ((uint32_t)0x00200000U) /* New Data flag of Rx Buffer 53 */ +#define FDCAN_NDAT2_ND54 ((uint32_t)0x00400000U) /* New Data flag of Rx Buffer 54 */ +#define FDCAN_NDAT2_ND55 ((uint32_t)0x00800000U) /* New Data flag of Rx Buffer 55 */ +#define FDCAN_NDAT2_ND56 ((uint32_t)0x01000000U) /* New Data flag of Rx Buffer 56 */ +#define FDCAN_NDAT2_ND57 ((uint32_t)0x02000000U) /* New Data flag of Rx Buffer 57 */ +#define FDCAN_NDAT2_ND58 ((uint32_t)0x04000000U) /* New Data flag of Rx Buffer 58 */ +#define FDCAN_NDAT2_ND59 ((uint32_t)0x08000000U) /* New Data flag of Rx Buffer 59 */ +#define FDCAN_NDAT2_ND60 ((uint32_t)0x10000000U) /* New Data flag of Rx Buffer 60 */ +#define FDCAN_NDAT2_ND61 ((uint32_t)0x20000000U) /* New Data flag of Rx Buffer 61 */ +#define FDCAN_NDAT2_ND62 ((uint32_t)0x40000000U) /* New Data flag of Rx Buffer 62 */ +#define FDCAN_NDAT2_ND63 ((uint32_t)0x80000000U) /* New Data flag of Rx Buffer 63 */ + +/** Bit definition for FDCAN_RXF0C register **/ +#define FDCAN_RXF0C_F0SA ((uint32_t)0x0000FFFCU) /* Rx FIFO 0 Start Address */ +#define FDCAN_RXF0C_F0S ((uint32_t)0x007F0000U) /* Rx FIFO 0 Size */ +#define FDCAN_RXF0C_F0WM ((uint32_t)0x7F000000U) /* Rx FIFO 0 Watermark */ +#define FDCAN_RXF0C_F0OM ((uint32_t)0x80000000U) /* Rx FIFO 0 Operation Mode */ + +/** Bit definition for FDCAN_RXF0S register **/ +#define FDCAN_RXF0S_F0FL ((uint32_t)0x0000007FU) /* Rx FIFO 0 Fill Level bits */ +#define FDCAN_RXF0S_F0GI ((uint32_t)0x00003F00U) /* Rx FIFO 0 Get Index bits */ +#define FDCAN_RXF0S_F0PI ((uint32_t)0x003F0000U) /* Rx FIFO 0 Put Index bits */ +#define FDCAN_RXF0S_F0F ((uint32_t)0x01000000U) /* Rx FIFO 0 Full */ +#define FDCAN_RXF0S_RF0L ((uint32_t)0x02000000U) /* Rx FIFO 0 Message Lost */ + +/** Bit definition for FDCAN_RXF0A register **/ +#define FDCAN_RXF0A_F0AI ((uint32_t)0x0000003FU) /* Rx FIFO 0 Acknowledge Index bits */ + +/** Bit definition for FDCAN_RXBC register **/ +#define FDCAN_RXBC_RBSA ((uint32_t)0x0000FFFCU) /* Rx Buffer Start Address */ + +/** Bit definition for FDCAN_RXF1C register **/ +#define FDCAN_RXF1C_F1SA ((uint32_t)0x0000FFFCU) /* Rx FIFO 1 Start Address */ +#define FDCAN_RXF1C_F1S ((uint32_t)0x007F0000U) /* Rx FIFO 1 Size */ +#define FDCAN_RXF1C_F1WM ((uint32_t)0x7F000000U) /* Rx FIFO 1 Watermark */ +#define FDCAN_RXF1C_F1OM ((uint32_t)0x80000000U) /* Rx FIFO 1 Operation Mode */ + +/** Bit definition for FDCAN_RXF1S register **/ +#define FDCAN_RXF1S_F1FL ((uint32_t)0x0000007FU) /* Rx FIFO 1 Fill Level bits */ +#define FDCAN_RXF1S_F1GI ((uint32_t)0x00003F00U) /* Rx FIFO 1 Get Index bits */ +#define FDCAN_RXF1S_F1PI ((uint32_t)0x003F0000U) /* Rx FIFO 1 Put Index bits */ +#define FDCAN_RXF1S_F1F ((uint32_t)0x01000000U) /* Rx FIFO 1 Full */ +#define FDCAN_RXF1S_RF1L ((uint32_t)0x02000000U) /* Rx FIFO 1 Message Lost */ + +#define FDCAN_RXF1S_DMS ((uint32_t)0xC0000000U) /* Debug message status bits */ +#define FDCAN_RXF1S_DMS_0 ((uint32_t)0x40000000U) /* Debug message status bit 0 */ +#define FDCAN_RXF1S_DMS_1 ((uint32_t)0x80000000U) /* Debug message status bit 1 */ + +/** Bit definition for FDCAN_RXF1A register **/ +#define FDCAN_RXF1A_F1AI ((uint32_t)0x0000003FU) /* Rx FIFO 1 Acknowledge Index bits */ + +/** Bit definition for FDCAN_RXESC register **/ +#define FDCAN_RXESC_F0DS ((uint32_t)0x00000007U) /* Rx FIFO 1 Data Field Size bits */ +#define FDCAN_RXESC_F1DS ((uint32_t)0x00000070U) /* Rx FIFO 0 Data Field Size bits */ +#define FDCAN_RXESC_RBDS ((uint32_t)0x00000700U) /* Rx Buffer Data Field Size bits */ + +/** Bit definition for FDCAN_TXBC register **/ +#define FDCAN_TXBC_TBSA ((uint32_t)0x0000FFFCU) /* Tx Buffers Start Address */ +#define FDCAN_TXBC_NDTB ((uint32_t)0x003F0000U) /* Number of Dedicated Transmit Buffers bits */ +#define FDCAN_TXBC_TFQS ((uint32_t)0x3F000000U) /* Transmit FIFO/Queue Size bits */ +#define FDCAN_TXBC_TFQM ((uint32_t)0x40000000U) /* Tx FIFO/Queue Mode */ + +/** Bit definition for FDCAN_TXFQS register **/ +#define FDCAN_TXFQS_TFFL ((uint32_t)0x0000003FU) /* Tx FIFO Free Level bits */ +#define FDCAN_TXFQS_TFGI ((uint32_t)0x00001F00U) /* Tx FIFO Get Index bits */ +#define FDCAN_TXFQS_TFQPI ((uint32_t)0x001F0000U) /* Tx FIFO/Queue Put Index bis */ +#define FDCAN_TXFQS_TFQF ((uint32_t)0x00200000U) /* Tx FIFO/Queue Full */ + +/** Bit definition for FDCAN_TXESC register **/ +#define FDCAN_TXESC_TBDS ((uint32_t)0x00000007U) /* Tx Buffer Data Field Size */ + +#define FDCAN_TXESC_TBDS_8BYTE ((uint32_t)0x00000000U) /* Tx Buffer Data Field Size is 8 Byte */ +#define FDCAN_TXESC_TBDS_12BYTE ((uint32_t)0x00000001U) /* Tx Buffer Data Field Size is 12 Byte */ +#define FDCAN_TXESC_TBDS_16BYTE ((uint32_t)0x00000002U) /* Tx Buffer Data Field Size is 16 Byte */ +#define FDCAN_TXESC_TBDS_20BYTE ((uint32_t)0x00000003U) /* Tx Buffer Data Field Size is 20 Byte */ +#define FDCAN_TXESC_TBDS_24BYTE ((uint32_t)0x00000004U) /* Tx Buffer Data Field Size is 24 Byte */ +#define FDCAN_TXESC_TBDS_32BYTE ((uint32_t)0x00000005U) /* Tx Buffer Data Field Size is 32 Byte */ +#define FDCAN_TXESC_TBDS_48BYTE ((uint32_t)0x00000006U) /* Tx Buffer Data Field Size is 48 Byte */ +#define FDCAN_TXESC_TBDS_64BYTE ((uint32_t)0x00000007U) /* Tx Buffer Data Field Size is 64 Byte */ + +/** Bit definition for FDCAN_TXBRP register **/ +#define FDCAN_TXBRP_TRP0 ((uint32_t)0x00000001U) /* Transmission Request Pending 0 */ +#define FDCAN_TXBRP_TRP1 ((uint32_t)0x00000002U) /* Transmission Request Pending 1 */ +#define FDCAN_TXBRP_TRP2 ((uint32_t)0x00000004U) /* Transmission Request Pending 2 */ +#define FDCAN_TXBRP_TRP3 ((uint32_t)0x00000008U) /* Transmission Request Pending 3 */ +#define FDCAN_TXBRP_TRP4 ((uint32_t)0x00000010U) /* Transmission Request Pending 4 */ +#define FDCAN_TXBRP_TRP5 ((uint32_t)0x00000020U) /* Transmission Request Pending 5 */ +#define FDCAN_TXBRP_TRP6 ((uint32_t)0x00000040U) /* Transmission Request Pending 6 */ +#define FDCAN_TXBRP_TRP7 ((uint32_t)0x00000080U) /* Transmission Request Pending 7 */ +#define FDCAN_TXBRP_TRP8 ((uint32_t)0x00000100U) /* Transmission Request Pending 8 */ +#define FDCAN_TXBRP_TRP9 ((uint32_t)0x00000200U) /* Transmission Request Pending 9 */ +#define FDCAN_TXBRP_TRP10 ((uint32_t)0x00000400U) /* Transmission Request Pending 10 */ +#define FDCAN_TXBRP_TRP11 ((uint32_t)0x00000800U) /* Transmission Request Pending 11 */ +#define FDCAN_TXBRP_TRP12 ((uint32_t)0x00001000U) /* Transmission Request Pending 12 */ +#define FDCAN_TXBRP_TRP13 ((uint32_t)0x00002000U) /* Transmission Request Pending 13 */ +#define FDCAN_TXBRP_TRP14 ((uint32_t)0x00004000U) /* Transmission Request Pending 14 */ +#define FDCAN_TXBRP_TRP15 ((uint32_t)0x00008000U) /* Transmission Request Pending 15 */ +#define FDCAN_TXBRP_TRP16 ((uint32_t)0x00010000U) /* Transmission Request Pending 16 */ +#define FDCAN_TXBRP_TRP17 ((uint32_t)0x00020000U) /* Transmission Request Pending 17 */ +#define FDCAN_TXBRP_TRP18 ((uint32_t)0x00040000U) /* Transmission Request Pending 18 */ +#define FDCAN_TXBRP_TRP19 ((uint32_t)0x00080000U) /* Transmission Request Pending 19 */ +#define FDCAN_TXBRP_TRP20 ((uint32_t)0x00100000U) /* Transmission Request Pending 20 */ +#define FDCAN_TXBRP_TRP21 ((uint32_t)0x00200000U) /* Transmission Request Pending 21 */ +#define FDCAN_TXBRP_TRP22 ((uint32_t)0x00400000U) /* Transmission Request Pending 22 */ +#define FDCAN_TXBRP_TRP23 ((uint32_t)0x00800000U) /* Transmission Request Pending 23 */ +#define FDCAN_TXBRP_TRP24 ((uint32_t)0x01000000U) /* Transmission Request Pending 24 */ +#define FDCAN_TXBRP_TRP25 ((uint32_t)0x02000000U) /* Transmission Request Pending 25 */ +#define FDCAN_TXBRP_TRP26 ((uint32_t)0x04000000U) /* Transmission Request Pending 26 */ +#define FDCAN_TXBRP_TRP27 ((uint32_t)0x08000000U) /* Transmission Request Pending 27 */ +#define FDCAN_TXBRP_TRP28 ((uint32_t)0x10000000U) /* Transmission Request Pending 28 */ +#define FDCAN_TXBRP_TRP29 ((uint32_t)0x20000000U) /* Transmission Request Pending 29 */ +#define FDCAN_TXBRP_TRP30 ((uint32_t)0x40000000U) /* Transmission Request Pending 30 */ +#define FDCAN_TXBRP_TRP31 ((uint32_t)0x80000000U) /* Transmission Request Pending 31 */ + +/** Bit definition for FDCAN_TXBAR register **/ +#define FDCAN_TXBAR_AR0 ((uint32_t)0x00000001U) /* Add Request 0 */ +#define FDCAN_TXBAR_AR1 ((uint32_t)0x00000002U) /* Add Request 1 */ +#define FDCAN_TXBAR_AR2 ((uint32_t)0x00000004U) /* Add Request 2 */ +#define FDCAN_TXBAR_AR3 ((uint32_t)0x00000008U) /* Add Request 3 */ +#define FDCAN_TXBAR_AR4 ((uint32_t)0x00000010U) /* Add Request 4 */ +#define FDCAN_TXBAR_AR5 ((uint32_t)0x00000020U) /* Add Request 5 */ +#define FDCAN_TXBAR_AR6 ((uint32_t)0x00000040U) /* Add Request 6 */ +#define FDCAN_TXBAR_AR7 ((uint32_t)0x00000080U) /* Add Request 7 */ +#define FDCAN_TXBAR_AR8 ((uint32_t)0x00000100U) /* Add Request 8 */ +#define FDCAN_TXBAR_AR9 ((uint32_t)0x00000200U) /* Add Request 9 */ +#define FDCAN_TXBAR_AR10 ((uint32_t)0x00000400U) /* Add Request 10 */ +#define FDCAN_TXBAR_AR11 ((uint32_t)0x00000800U) /* Add Request 11 */ +#define FDCAN_TXBAR_AR12 ((uint32_t)0x00001000U) /* Add Request 12 */ +#define FDCAN_TXBAR_AR13 ((uint32_t)0x00002000U) /* Add Request 13 */ +#define FDCAN_TXBAR_AR14 ((uint32_t)0x00004000U) /* Add Request 14 */ +#define FDCAN_TXBAR_AR15 ((uint32_t)0x00008000U) /* Add Request 15 */ +#define FDCAN_TXBAR_AR16 ((uint32_t)0x00010000U) /* Add Request 16 */ +#define FDCAN_TXBAR_AR17 ((uint32_t)0x00020000U) /* Add Request 17 */ +#define FDCAN_TXBAR_AR18 ((uint32_t)0x00040000U) /* Add Request 18 */ +#define FDCAN_TXBAR_AR19 ((uint32_t)0x00080000U) /* Add Request 19 */ +#define FDCAN_TXBAR_AR20 ((uint32_t)0x00100000U) /* Add Request 20 */ +#define FDCAN_TXBAR_AR21 ((uint32_t)0x00200000U) /* Add Request 21 */ +#define FDCAN_TXBAR_AR22 ((uint32_t)0x00400000U) /* Add Request 22 */ +#define FDCAN_TXBAR_AR23 ((uint32_t)0x00800000U) /* Add Request 23 */ +#define FDCAN_TXBAR_AR24 ((uint32_t)0x01000000U) /* Add Request 24 */ +#define FDCAN_TXBAR_AR25 ((uint32_t)0x02000000U) /* Add Request 25 */ +#define FDCAN_TXBAR_AR26 ((uint32_t)0x04000000U) /* Add Request 26 */ +#define FDCAN_TXBAR_AR27 ((uint32_t)0x08000000U) /* Add Request 27 */ +#define FDCAN_TXBAR_AR28 ((uint32_t)0x10000000U) /* Add Request 28 */ +#define FDCAN_TXBAR_AR29 ((uint32_t)0x20000000U) /* Add Request 29 */ +#define FDCAN_TXBAR_AR30 ((uint32_t)0x40000000U) /* Add Request 30 */ +#define FDCAN_TXBAR_AR31 ((uint32_t)0x80000000U) /* Add Request 31 */ + +/** Bit definition for FDCAN_TXBCR register **/ +#define FDCAN_TXBCR_CR0 ((uint32_t)0x00000001U) /* Cancellation Request 0 */ +#define FDCAN_TXBCR_CR1 ((uint32_t)0x00000002U) /* Cancellation Request 1 */ +#define FDCAN_TXBCR_CR2 ((uint32_t)0x00000004U) /* Cancellation Request 2 */ +#define FDCAN_TXBCR_CR3 ((uint32_t)0x00000008U) /* Cancellation Request 3 */ +#define FDCAN_TXBCR_CR4 ((uint32_t)0x00000010U) /* Cancellation Request 4 */ +#define FDCAN_TXBCR_CR5 ((uint32_t)0x00000020U) /* Cancellation Request 5 */ +#define FDCAN_TXBCR_CR6 ((uint32_t)0x00000040U) /* Cancellation Request 6 */ +#define FDCAN_TXBCR_CR7 ((uint32_t)0x00000080U) /* Cancellation Request 7 */ +#define FDCAN_TXBCR_CR8 ((uint32_t)0x00000100U) /* Cancellation Request 8 */ +#define FDCAN_TXBCR_CR9 ((uint32_t)0x00000200U) /* Cancellation Request 9 */ +#define FDCAN_TXBCR_CR10 ((uint32_t)0x00000400U) /* Cancellation Request 10 */ +#define FDCAN_TXBCR_CR11 ((uint32_t)0x00000800U) /* Cancellation Request 11 */ +#define FDCAN_TXBCR_CR12 ((uint32_t)0x00001000U) /* Cancellation Request 12 */ +#define FDCAN_TXBCR_CR13 ((uint32_t)0x00002000U) /* Cancellation Request 13 */ +#define FDCAN_TXBCR_CR14 ((uint32_t)0x00004000U) /* Cancellation Request 14 */ +#define FDCAN_TXBCR_CR15 ((uint32_t)0x00008000U) /* Cancellation Request 15 */ +#define FDCAN_TXBCR_CR16 ((uint32_t)0x00010000U) /* Cancellation Request 16 */ +#define FDCAN_TXBCR_CR17 ((uint32_t)0x00020000U) /* Cancellation Request 17 */ +#define FDCAN_TXBCR_CR18 ((uint32_t)0x00040000U) /* Cancellation Request 18 */ +#define FDCAN_TXBCR_CR19 ((uint32_t)0x00080000U) /* Cancellation Request 19 */ +#define FDCAN_TXBCR_CR20 ((uint32_t)0x00100000U) /* Cancellation Request 20 */ +#define FDCAN_TXBCR_CR21 ((uint32_t)0x00200000U) /* Cancellation Request 21 */ +#define FDCAN_TXBCR_CR22 ((uint32_t)0x00400000U) /* Cancellation Request 22 */ +#define FDCAN_TXBCR_CR23 ((uint32_t)0x00800000U) /* Cancellation Request 23 */ +#define FDCAN_TXBCR_CR24 ((uint32_t)0x01000000U) /* Cancellation Request 24 */ +#define FDCAN_TXBCR_CR25 ((uint32_t)0x02000000U) /* Cancellation Request 25 */ +#define FDCAN_TXBCR_CR26 ((uint32_t)0x04000000U) /* Cancellation Request 26 */ +#define FDCAN_TXBCR_CR27 ((uint32_t)0x08000000U) /* Cancellation Request 27 */ +#define FDCAN_TXBCR_CR28 ((uint32_t)0x10000000U) /* Cancellation Request 28 */ +#define FDCAN_TXBCR_CR29 ((uint32_t)0x20000000U) /* Cancellation Request 29 */ +#define FDCAN_TXBCR_CR30 ((uint32_t)0x40000000U) /* Cancellation Request 30 */ +#define FDCAN_TXBCR_CR31 ((uint32_t)0x80000000U) /* Cancellation Request 31 */ + +/** Bit definition for FDCAN_TXBTO register **/ +#define FDCAN_TXBTO_TO0 ((uint32_t)0x00000001U) /* Transmission Occurred 0 */ +#define FDCAN_TXBTO_TO1 ((uint32_t)0x00000002U) /* Transmission Occurred 1 */ +#define FDCAN_TXBTO_TO2 ((uint32_t)0x00000004U) /* Transmission Occurred 2 */ +#define FDCAN_TXBTO_TO3 ((uint32_t)0x00000008U) /* Transmission Occurred 3 */ +#define FDCAN_TXBTO_TO4 ((uint32_t)0x00000010U) /* Transmission Occurred 4 */ +#define FDCAN_TXBTO_TO5 ((uint32_t)0x00000020U) /* Transmission Occurred 5 */ +#define FDCAN_TXBTO_TO6 ((uint32_t)0x00000040U) /* Transmission Occurred 6 */ +#define FDCAN_TXBTO_TO7 ((uint32_t)0x00000080U) /* Transmission Occurred 7 */ +#define FDCAN_TXBTO_TO8 ((uint32_t)0x00000100U) /* Transmission Occurred 8 */ +#define FDCAN_TXBTO_TO9 ((uint32_t)0x00000200U) /* Transmission Occurred 9 */ +#define FDCAN_TXBTO_TO10 ((uint32_t)0x00000400U) /* Transmission Occurred 10 */ +#define FDCAN_TXBTO_TO11 ((uint32_t)0x00000800U) /* Transmission Occurred 11 */ +#define FDCAN_TXBTO_TO12 ((uint32_t)0x00001000U) /* Transmission Occurred 12 */ +#define FDCAN_TXBTO_TO13 ((uint32_t)0x00002000U) /* Transmission Occurred 13 */ +#define FDCAN_TXBTO_TO14 ((uint32_t)0x00004000U) /* Transmission Occurred 14 */ +#define FDCAN_TXBTO_TO15 ((uint32_t)0x00008000U) /* Transmission Occurred 15 */ +#define FDCAN_TXBTO_TO16 ((uint32_t)0x00010000U) /* Transmission Occurred 16 */ +#define FDCAN_TXBTO_TO17 ((uint32_t)0x00020000U) /* Transmission Occurred 17 */ +#define FDCAN_TXBTO_TO18 ((uint32_t)0x00040000U) /* Transmission Occurred 18 */ +#define FDCAN_TXBTO_TO19 ((uint32_t)0x00080000U) /* Transmission Occurred 19 */ +#define FDCAN_TXBTO_TO20 ((uint32_t)0x00100000U) /* Transmission Occurred 20 */ +#define FDCAN_TXBTO_TO21 ((uint32_t)0x00200000U) /* Transmission Occurred 21 */ +#define FDCAN_TXBTO_TO22 ((uint32_t)0x00400000U) /* Transmission Occurred 22 */ +#define FDCAN_TXBTO_TO23 ((uint32_t)0x00800000U) /* Transmission Occurred 23 */ +#define FDCAN_TXBTO_TO24 ((uint32_t)0x01000000U) /* Transmission Occurred 24 */ +#define FDCAN_TXBTO_TO25 ((uint32_t)0x02000000U) /* Transmission Occurred 25 */ +#define FDCAN_TXBTO_TO26 ((uint32_t)0x04000000U) /* Transmission Occurred 26 */ +#define FDCAN_TXBTO_TO27 ((uint32_t)0x08000000U) /* Transmission Occurred 27 */ +#define FDCAN_TXBTO_TO28 ((uint32_t)0x10000000U) /* Transmission Occurred 28 */ +#define FDCAN_TXBTO_TO29 ((uint32_t)0x20000000U) /* Transmission Occurred 29 */ +#define FDCAN_TXBTO_TO30 ((uint32_t)0x40000000U) /* Transmission Occurred 30 */ +#define FDCAN_TXBTO_TO31 ((uint32_t)0x80000000U) /* Transmission Occurred 31 */ + +/** Bit definition for FDCAN_TXBCF register **/ +#define FDCAN_TXBCF_CF0 ((uint32_t)0x00000001U) /* Cancellation Finished 0 */ +#define FDCAN_TXBCF_CF1 ((uint32_t)0x00000002U) /* Cancellation Finished 1 */ +#define FDCAN_TXBCF_CF2 ((uint32_t)0x00000004U) /* Cancellation Finished 2 */ +#define FDCAN_TXBCF_CF3 ((uint32_t)0x00000008U) /* Cancellation Finished 3 */ +#define FDCAN_TXBCF_CF4 ((uint32_t)0x00000010U) /* Cancellation Finished 4 */ +#define FDCAN_TXBCF_CF5 ((uint32_t)0x00000020U) /* Cancellation Finished 5 */ +#define FDCAN_TXBCF_CF6 ((uint32_t)0x00000040U) /* Cancellation Finished 6 */ +#define FDCAN_TXBCF_CF7 ((uint32_t)0x00000080U) /* Cancellation Finished 7 */ +#define FDCAN_TXBCF_CF8 ((uint32_t)0x00000100U) /* Cancellation Finished 8 */ +#define FDCAN_TXBCF_CF9 ((uint32_t)0x00000200U) /* Cancellation Finished 9 */ +#define FDCAN_TXBCF_CF10 ((uint32_t)0x00000400U) /* Cancellation Finished 10 */ +#define FDCAN_TXBCF_CF11 ((uint32_t)0x00000800U) /* Cancellation Finished 11 */ +#define FDCAN_TXBCF_CF12 ((uint32_t)0x00001000U) /* Cancellation Finished 12 */ +#define FDCAN_TXBCF_CF13 ((uint32_t)0x00002000U) /* Cancellation Finished 13 */ +#define FDCAN_TXBCF_CF14 ((uint32_t)0x00004000U) /* Cancellation Finished 14 */ +#define FDCAN_TXBCF_CF15 ((uint32_t)0x00008000U) /* Cancellation Finished 15 */ +#define FDCAN_TXBCF_CF16 ((uint32_t)0x00010000U) /* Cancellation Finished 16 */ +#define FDCAN_TXBCF_CF17 ((uint32_t)0x00020000U) /* Cancellation Finished 17 */ +#define FDCAN_TXBCF_CF18 ((uint32_t)0x00040000U) /* Cancellation Finished 18 */ +#define FDCAN_TXBCF_CF19 ((uint32_t)0x00080000U) /* Cancellation Finished 19 */ +#define FDCAN_TXBCF_CF20 ((uint32_t)0x00100000U) /* Cancellation Finished 20 */ +#define FDCAN_TXBCF_CF21 ((uint32_t)0x00200000U) /* Cancellation Finished 21 */ +#define FDCAN_TXBCF_CF22 ((uint32_t)0x00400000U) /* Cancellation Finished 22 */ +#define FDCAN_TXBCF_CF23 ((uint32_t)0x00800000U) /* Cancellation Finished 23 */ +#define FDCAN_TXBCF_CF24 ((uint32_t)0x01000000U) /* Cancellation Finished 24 */ +#define FDCAN_TXBCF_CF25 ((uint32_t)0x02000000U) /* Cancellation Finished 25 */ +#define FDCAN_TXBCF_CF26 ((uint32_t)0x04000000U) /* Cancellation Finished 26 */ +#define FDCAN_TXBCF_CF27 ((uint32_t)0x08000000U) /* Cancellation Finished 27 */ +#define FDCAN_TXBCF_CF28 ((uint32_t)0x10000000U) /* Cancellation Finished 28 */ +#define FDCAN_TXBCF_CF29 ((uint32_t)0x20000000U) /* Cancellation Finished 29 */ +#define FDCAN_TXBCF_CF30 ((uint32_t)0x40000000U) /* Cancellation Finished 30 */ +#define FDCAN_TXBCF_CF31 ((uint32_t)0x80000000U) /* Cancellation Finished 31 */ + +/** Bit definition for FDCAN_TXBTIE register **/ +#define FDCAN_TXBTIE_TIE0 ((uint32_t)0x00000001U) /* Transmission Interrupt Enable 0 */ +#define FDCAN_TXBTIE_TIE1 ((uint32_t)0x00000002U) /* Transmission Interrupt Enable 1 */ +#define FDCAN_TXBTIE_TIE2 ((uint32_t)0x00000004U) /* Transmission Interrupt Enable 2 */ +#define FDCAN_TXBTIE_TIE3 ((uint32_t)0x00000008U) /* Transmission Interrupt Enable 3 */ +#define FDCAN_TXBTIE_TIE4 ((uint32_t)0x00000010U) /* Transmission Interrupt Enable 4 */ +#define FDCAN_TXBTIE_TIE5 ((uint32_t)0x00000020U) /* Transmission Interrupt Enable 5 */ +#define FDCAN_TXBTIE_TIE6 ((uint32_t)0x00000040U) /* Transmission Interrupt Enable 6 */ +#define FDCAN_TXBTIE_TIE7 ((uint32_t)0x00000080U) /* Transmission Interrupt Enable 7 */ +#define FDCAN_TXBTIE_TIE8 ((uint32_t)0x00000100U) /* Transmission Interrupt Enable 8 */ +#define FDCAN_TXBTIE_TIE9 ((uint32_t)0x00000200U) /* Transmission Interrupt Enable 9 */ +#define FDCAN_TXBTIE_TIE10 ((uint32_t)0x00000400U) /* Transmission Interrupt Enable 10 */ +#define FDCAN_TXBTIE_TIE11 ((uint32_t)0x00000800U) /* Transmission Interrupt Enable 11 */ +#define FDCAN_TXBTIE_TIE12 ((uint32_t)0x00001000U) /* Transmission Interrupt Enable 12 */ +#define FDCAN_TXBTIE_TIE13 ((uint32_t)0x00002000U) /* Transmission Interrupt Enable 13 */ +#define FDCAN_TXBTIE_TIE14 ((uint32_t)0x00004000U) /* Transmission Interrupt Enable 14 */ +#define FDCAN_TXBTIE_TIE15 ((uint32_t)0x00008000U) /* Transmission Interrupt Enable 15 */ +#define FDCAN_TXBTIE_TIE16 ((uint32_t)0x00010000U) /* Transmission Interrupt Enable 16 */ +#define FDCAN_TXBTIE_TIE17 ((uint32_t)0x00020000U) /* Transmission Interrupt Enable 17 */ +#define FDCAN_TXBTIE_TIE18 ((uint32_t)0x00040000U) /* Transmission Interrupt Enable 18 */ +#define FDCAN_TXBTIE_TIE19 ((uint32_t)0x00080000U) /* Transmission Interrupt Enable 19 */ +#define FDCAN_TXBTIE_TIE20 ((uint32_t)0x00100000U) /* Transmission Interrupt Enable 20 */ +#define FDCAN_TXBTIE_TIE21 ((uint32_t)0x00200000U) /* Transmission Interrupt Enable 21 */ +#define FDCAN_TXBTIE_TIE22 ((uint32_t)0x00400000U) /* Transmission Interrupt Enable 22 */ +#define FDCAN_TXBTIE_TIE23 ((uint32_t)0x00800000U) /* Transmission Interrupt Enable 23 */ +#define FDCAN_TXBTIE_TIE24 ((uint32_t)0x01000000U) /* Transmission Interrupt Enable 24 */ +#define FDCAN_TXBTIE_TIE25 ((uint32_t)0x02000000U) /* Transmission Interrupt Enable 25 */ +#define FDCAN_TXBTIE_TIE26 ((uint32_t)0x04000000U) /* Transmission Interrupt Enable 26 */ +#define FDCAN_TXBTIE_TIE27 ((uint32_t)0x08000000U) /* Transmission Interrupt Enable 27 */ +#define FDCAN_TXBTIE_TIE28 ((uint32_t)0x10000000U) /* Transmission Interrupt Enable 28 */ +#define FDCAN_TXBTIE_TIE29 ((uint32_t)0x20000000U) /* Transmission Interrupt Enable 29 */ +#define FDCAN_TXBTIE_TIE30 ((uint32_t)0x40000000U) /* Transmission Interrupt Enable 30 */ +#define FDCAN_TXBTIE_TIE31 ((uint32_t)0x80000000U) /* Transmission Interrupt Enable 31 */ + +/** Bit definition for TXBCIE register **/ +#define FDCAN_TXBCIE_CFIE0 ((uint32_t)0x00000001U) /* Cancellation Finished Interrupt Enable 0 */ +#define FDCAN_TXBCIE_CFIE1 ((uint32_t)0x00000002U) /* Cancellation Finished Interrupt Enable 1 */ +#define FDCAN_TXBCIE_CFIE2 ((uint32_t)0x00000004U) /* Cancellation Finished Interrupt Enable 2 */ +#define FDCAN_TXBCIE_CFIE3 ((uint32_t)0x00000008U) /* Cancellation Finished Interrupt Enable 3 */ +#define FDCAN_TXBCIE_CFIE4 ((uint32_t)0x00000010U) /* Cancellation Finished Interrupt Enable 4 */ +#define FDCAN_TXBCIE_CFIE5 ((uint32_t)0x00000020U) /* Cancellation Finished Interrupt Enable 5 */ +#define FDCAN_TXBCIE_CFIE6 ((uint32_t)0x00000040U) /* Cancellation Finished Interrupt Enable 6 */ +#define FDCAN_TXBCIE_CFIE7 ((uint32_t)0x00000080U) /* Cancellation Finished Interrupt Enable 7 */ +#define FDCAN_TXBCIE_CFIE8 ((uint32_t)0x00000100U) /* Cancellation Finished Interrupt Enable 8 */ +#define FDCAN_TXBCIE_CFIE9 ((uint32_t)0x00000200U) /* Cancellation Finished Interrupt Enable 9 */ +#define FDCAN_TXBCIE_CFIE10 ((uint32_t)0x00000400U) /* Cancellation Finished Interrupt Enable 10 */ +#define FDCAN_TXBCIE_CFIE11 ((uint32_t)0x00000800U) /* Cancellation Finished Interrupt Enable 11 */ +#define FDCAN_TXBCIE_CFIE12 ((uint32_t)0x00001000U) /* Cancellation Finished Interrupt Enable 12 */ +#define FDCAN_TXBCIE_CFIE13 ((uint32_t)0x00002000U) /* Cancellation Finished Interrupt Enable 13 */ +#define FDCAN_TXBCIE_CFIE14 ((uint32_t)0x00004000U) /* Cancellation Finished Interrupt Enable 14 */ +#define FDCAN_TXBCIE_CFIE15 ((uint32_t)0x00008000U) /* Cancellation Finished Interrupt Enable 15 */ +#define FDCAN_TXBCIE_CFIE16 ((uint32_t)0x00010000U) /* Cancellation Finished Interrupt Enable 16 */ +#define FDCAN_TXBCIE_CFIE17 ((uint32_t)0x00020000U) /* Cancellation Finished Interrupt Enable 17 */ +#define FDCAN_TXBCIE_CFIE18 ((uint32_t)0x00040000U) /* Cancellation Finished Interrupt Enable 18 */ +#define FDCAN_TXBCIE_CFIE19 ((uint32_t)0x00080000U) /* Cancellation Finished Interrupt Enable 19 */ +#define FDCAN_TXBCIE_CFIE20 ((uint32_t)0x00100000U) /* Cancellation Finished Interrupt Enable 20 */ +#define FDCAN_TXBCIE_CFIE21 ((uint32_t)0x00200000U) /* Cancellation Finished Interrupt Enable 21 */ +#define FDCAN_TXBCIE_CFIE22 ((uint32_t)0x00400000U) /* Cancellation Finished Interrupt Enable 22 */ +#define FDCAN_TXBCIE_CFIE23 ((uint32_t)0x00800000U) /* Cancellation Finished Interrupt Enable 23 */ +#define FDCAN_TXBCIE_CFIE24 ((uint32_t)0x01000000U) /* Cancellation Finished Interrupt Enable 24 */ +#define FDCAN_TXBCIE_CFIE25 ((uint32_t)0x02000000U) /* Cancellation Finished Interrupt Enable 25 */ +#define FDCAN_TXBCIE_CFIE26 ((uint32_t)0x04000000U) /* Cancellation Finished Interrupt Enable 26 */ +#define FDCAN_TXBCIE_CFIE27 ((uint32_t)0x08000000U) /* Cancellation Finished Interrupt Enable 27 */ +#define FDCAN_TXBCIE_CFIE28 ((uint32_t)0x10000000U) /* Cancellation Finished Interrupt Enable 28 */ +#define FDCAN_TXBCIE_CFIE29 ((uint32_t)0x20000000U) /* Cancellation Finished Interrupt Enable 29 */ +#define FDCAN_TXBCIE_CFIE30 ((uint32_t)0x40000000U) /* Cancellation Finished Interrupt Enable 30 */ +#define FDCAN_TXBCIE_CFIE31 ((uint32_t)0x80000000U) /* Cancellation Finished Interrupt Enable 31 */ + +/** Bit definition for FDCAN_TXEFC register **/ +#define FDCAN_TXEFC_EFSA ((uint32_t)0x0000FFFCU) /* Event FIFO Start Address */ +#define FDCAN_TXEFC_EFS ((uint32_t)0x003F0000U) /* Event FIFO Size bits */ +#define FDCAN_TXEFC_EFWM ((uint32_t)0x3F000000U) /* Event FIFO Watermark bits */ + +/** Bit definition for FDCAN_TXEFS register **/ +#define FDCAN_TXEFS_EFFL ((uint32_t)0x0000003FU) /* Event FIFO Fill Level bits */ +#define FDCAN_TXEFS_EFGI ((uint32_t)0x00001F00U) /* Event FIFO Get Index bits */ +#define FDCAN_TXEFS_EFPI ((uint32_t)0x001F0000U) /* Event FIFO Put Index bits */ +#define FDCAN_TXEFS_EFF ((uint32_t)0x01000000U) /* Event FIFO Full */ +#define FDCAN_TXEFS_TEFL ((uint32_t)0x02000000U) /* Tx Event FIFO Element Lost */ + +/** Bit definition for FDCAN_TXEFA register **/ +#define FDCAN_TXEFA_EFAI ((uint32_t)0x0000001FU) /* Event FIFO Acknowledge Index bits */ + +/** Bit definition for FDCAN_TTTMC register **/ +#define FDCAN_TTTMC_TME ((uint32_t)0x007F0000U) /* Trigger memory elements bits */ +#define FDCAN_TTTMC_TME_0 ((uint32_t)0x00010000U) /* Trigger memory elements bits 0 */ +#define FDCAN_TTTMC_TME_1 ((uint32_t)0x00020000U) /* Trigger memory elements bits 1 */ +#define FDCAN_TTTMC_TME_2 ((uint32_t)0x00040000U) /* Trigger memory elements bits 2 */ +#define FDCAN_TTTMC_TME_3 ((uint32_t)0x00080000U) /* Trigger memory elements bits 3 */ +#define FDCAN_TTTMC_TME_4 ((uint32_t)0x00100000U) /* Trigger memory elements bits 4 */ +#define FDCAN_TTTMC_TME_5 ((uint32_t)0x00200000U) /* Trigger memory elements bits 5 */ +#define FDCAN_TTTMC_TME_6 ((uint32_t)0x00400000U) /* Trigger memory elements bits 6 */ + +#define FDCAN_TTTMC_TMSA ((uint32_t)0x0000FFFCU) /* Trigger memory start address bits */ + +/** Bit definition for FDCAN_TTRMC register **/ +#define FDCAN_TTRMC_RMPS ((uint32_t)0x80000000U) /* Reference message Payload select bit */ +#define FDCAN_TTRMC_XTD ((uint32_t)0x40000000U) /* Extended identifier bit */ + +#define FDCAN_TTRMC_RID ((uint32_t)0x1FFFFFFFU) /* Reference identifier Bits */ +#define FDCAN_TTRMC_RID_0 ((uint32_t)0x00000001U) /* Reference identifier Bit0 */ +#define FDCAN_TTRMC_RID_1 ((uint32_t)0x00000002U) /* Reference identifier Bit1 */ +#define FDCAN_TTRMC_RID_2 ((uint32_t)0x00000004U) /* Reference identifier Bit2 */ +#define FDCAN_TTRMC_RID_3 ((uint32_t)0x00000008U) /* Reference identifier Bit3 */ +#define FDCAN_TTRMC_RID_4 ((uint32_t)0x00000010U) /* Reference identifier Bit4 */ +#define FDCAN_TTRMC_RID_5 ((uint32_t)0x00000020U) /* Reference identifier Bit5 */ +#define FDCAN_TTRMC_RID_6 ((uint32_t)0x00000040U) /* Reference identifier Bit6 */ +#define FDCAN_TTRMC_RID_7 ((uint32_t)0x00000080U) /* Reference identifier Bit7 */ +#define FDCAN_TTRMC_RID_8 ((uint32_t)0x00000100U) /* Reference identifier Bit8 */ +#define FDCAN_TTRMC_RID_9 ((uint32_t)0x00000200U) /* Reference identifier Bit9 */ +#define FDCAN_TTRMC_RID_10 ((uint32_t)0x00000400U) /* Reference identifier Bit10 */ +#define FDCAN_TTRMC_RID_11 ((uint32_t)0x00000800U) /* Reference identifier Bit11 */ +#define FDCAN_TTRMC_RID_12 ((uint32_t)0x00001000U) /* Reference identifier Bit12 */ +#define FDCAN_TTRMC_RID_13 ((uint32_t)0x00002000U) /* Reference identifier Bit13 */ +#define FDCAN_TTRMC_RID_14 ((uint32_t)0x00004000U) /* Reference identifier Bit14 */ +#define FDCAN_TTRMC_RID_15 ((uint32_t)0x00008000U) /* Reference identifier Bit15 */ +#define FDCAN_TTRMC_RID_16 ((uint32_t)0x00010000U) /* Reference identifier Bit16 */ +#define FDCAN_TTRMC_RID_17 ((uint32_t)0x00020000U) /* Reference identifier Bit17 */ +#define FDCAN_TTRMC_RID_18 ((uint32_t)0x00040000U) /* Reference identifier Bit18 */ +#define FDCAN_TTRMC_RID_19 ((uint32_t)0x00080000U) /* Reference identifier Bit19 */ +#define FDCAN_TTRMC_RID_20 ((uint32_t)0x00100000U) /* Reference identifier Bit20 */ +#define FDCAN_TTRMC_RID_21 ((uint32_t)0x00200000U) /* Reference identifier Bit21 */ +#define FDCAN_TTRMC_RID_22 ((uint32_t)0x00400000U) /* Reference identifier Bit22 */ +#define FDCAN_TTRMC_RID_23 ((uint32_t)0x00800000U) /* Reference identifier Bit23 */ +#define FDCAN_TTRMC_RID_24 ((uint32_t)0x01000000U) /* Reference identifier Bit24 */ +#define FDCAN_TTRMC_RID_25 ((uint32_t)0x02000000U) /* Reference identifier Bit25 */ +#define FDCAN_TTRMC_RID_26 ((uint32_t)0x04000000U) /* Reference identifier Bit26 */ +#define FDCAN_TTRMC_RID_27 ((uint32_t)0x08000000U) /* Reference identifier Bit27 */ +#define FDCAN_TTRMC_RID_28 ((uint32_t)0x10000000U) /* Reference identifier Bit28 */ + +/** Bit definition for FDCAN_TTOCF register **/ +#define FDCAN_TTOCF_EVTP ((uint32_t)0x04000000U) /* Event trigger polarity bit */ +#define FDCAN_TTOCF_ECC ((uint32_t)0x02000000U) /* Enable clock calibration bit */ +#define FDCAN_TTOCF_EGTF ((uint32_t)0x01000000U) /* Enable global time Filtering bit */ + +#define FDCAN_TTOCF_AWL ((uint32_t)0x00FF0000U) /* Application watchdog limit bits */ +#define FDCAN_TTOCF_AWL_0 ((uint32_t)0x00010000U) /* Application watchdog limit bit 0 */ +#define FDCAN_TTOCF_AWL_1 ((uint32_t)0x00020000U) /* Application watchdog limit bit 1 */ +#define FDCAN_TTOCF_AWL_2 ((uint32_t)0x00040000U) /* Application watchdog limit bit 2 */ +#define FDCAN_TTOCF_AWL_3 ((uint32_t)0x00080000U) /* Application watchdog limit bit 3 */ +#define FDCAN_TTOCF_AWL_4 ((uint32_t)0x00100000U) /* Application watchdog limit bit 4 */ +#define FDCAN_TTOCF_AWL_5 ((uint32_t)0x00200000U) /* Application watchdog limit bit 5 */ +#define FDCAN_TTOCF_AWL_6 ((uint32_t)0x00400000U) /* Application watchdog limit bit 6 */ +#define FDCAN_TTOCF_AWL_7 ((uint32_t)0x00800000U) /* Application watchdog limit bit 7 */ + +#define FDCAN_TTOCF_EECS ((uint32_t)0x00008000U) /* Enable external clock synchronization bit */ + +#define FDCAN_TTOCF_IRTO ((uint32_t)0x00007F00U) /* Initial reference trigger offset bits */ +#define FDCAN_TTOCF_IRTO_0 ((uint32_t)0x00000100U) /* Initial reference trigger offset bit 0 */ +#define FDCAN_TTOCF_IRTO_1 ((uint32_t)0x00000200U) /* Initial reference trigger offset bit 1 */ +#define FDCAN_TTOCF_IRTO_2 ((uint32_t)0x00000400U) /* Initial reference trigger offset bit 2 */ +#define FDCAN_TTOCF_IRTO_3 ((uint32_t)0x00000800U) /* Initial reference trigger offset bit 3 */ +#define FDCAN_TTOCF_IRTO_4 ((uint32_t)0x00001000U) /* Initial reference trigger offset bit 4 */ +#define FDCAN_TTOCF_IRTO_5 ((uint32_t)0x00002000U) /* Initial reference trigger offset bit 5 */ +#define FDCAN_TTOCF_IRTO_6 ((uint32_t)0x00004000U) /* Initial reference trigger offset bit 6 */ + +#define FDCAN_TTOCF_LDSDL ((uint32_t)0x000000E0U) /* LD of synchronization deviation limit bits */ +#define FDCAN_TTOCF_LDSDL_0 ((uint32_t)0x00000020U) /* LD of synchronization deviation limit bit0 */ +#define FDCAN_TTOCF_LDSDL_1 ((uint32_t)0x00000040U) /* LD of synchronization deviation limit bit1 */ +#define FDCAN_TTOCF_LDSDL_2 ((uint32_t)0x00000080U) /* LD of synchronization deviation limit bit2 */ + +#define FDCAN_TTOCF_TM ((uint32_t)0x00000010U) /* Time master bit */ +#define FDCAN_TTOCF_GEN ((uint32_t)0x00000008U) /* Gap enable bit */ + +#define FDCAN_TTOCF_OM ((uint32_t)0x00000003U) /* Operation mode bits */ +#define FDCAN_TTOCF_OM_EVENT ((uint32_t)0x00000000U) /* Event driven CAN communication, default */ +#define FDCAN_TTOCF_OM_LEVEL1 ((uint32_t)0x00000001U) /* TTCAN Level 1 */ +#define FDCAN_TTOCF_OM_LEVEL2 ((uint32_t)0x00000002U) /* TTCAN Level 2 */ +#define FDCAN_TTOCF_OM_LEVEL0 ((uint32_t)0x00000003U) /* TTCAN Level 0 */ + +/** Bit definition for FDCAN_TTMLM register **/ +#define FDCAN_TTMLM_ENTT ((uint32_t)0x0FFF0000U) /* Expected Number of Tx triggers bits */ +#define FDCAN_TTMLM_ENTT_0 ((uint32_t)0x00010000U) /* Expected Number of Tx triggers bit 0 */ +#define FDCAN_TTMLM_ENTT_1 ((uint32_t)0x00020000U) /* Expected Number of Tx triggers bit 1 */ +#define FDCAN_TTMLM_ENTT_2 ((uint32_t)0x00040000U) /* Expected Number of Tx triggers bit 2 */ +#define FDCAN_TTMLM_ENTT_3 ((uint32_t)0x00080000U) /* Expected Number of Tx triggers bit 3 */ +#define FDCAN_TTMLM_ENTT_4 ((uint32_t)0x00100000U) /* Expected Number of Tx triggers bit 4 */ +#define FDCAN_TTMLM_ENTT_5 ((uint32_t)0x00200000U) /* Expected Number of Tx triggers bit 5 */ +#define FDCAN_TTMLM_ENTT_6 ((uint32_t)0x00400000U) /* Expected Number of Tx triggers bit 6 */ +#define FDCAN_TTMLM_ENTT_7 ((uint32_t)0x00800000U) /* Expected Number of Tx triggers bit 7 */ +#define FDCAN_TTMLM_ENTT_8 ((uint32_t)0x01000000U) /* Expected Number of Tx triggers bit 8 */ +#define FDCAN_TTMLM_ENTT_9 ((uint32_t)0x02000000U) /* Expected Number of Tx triggers bit 9 */ +#define FDCAN_TTMLM_ENTT_10 ((uint32_t)0x04000000U) /* Expected Number of Tx triggers bit 10 */ +#define FDCAN_TTMLM_ENTT_11 ((uint32_t)0x08000000U) /* Expected Number of Tx triggers bit 11 */ + +#define FDCAN_TTMLM_TXEW ((uint32_t)0x00000F00U) /* Tx enable Window bits */ +#define FDCAN_TTMLM_TXEW_0 ((uint32_t)0x00000100U) /* Tx enable Window bit 0 */ +#define FDCAN_TTMLM_TXEW_1 ((uint32_t)0x00000200U) /* Tx enable Window bit 1 */ +#define FDCAN_TTMLM_TXEW_2 ((uint32_t)0x00000400U) /* Tx enable Window bit 2 */ +#define FDCAN_TTMLM_TXEW_3 ((uint32_t)0x00000800U) /* Tx enable Window bit 3 */ + +#define FDCAN_TTMLM_CSS ((uint32_t)0x000000C0U) /* Cycle start synchronization bits */ +#define FDCAN_TTMLM_CSS_NONE ((uint32_t)0x00000000U) /* No synchronization pulse */ +#define FDCAN_TTMLM_CSS_BASIC ((uint32_t)0x00000040U) /* Synchronization pulse at the beginning of the basic cycle */ +#define FDCAN_TTMLM_CSS_MATRIX ((uint32_t)0x00000080U) /* Synchronization pulse at the beginning of the matrix cycle */ + +#define FDCAN_TTMLM_CCM ((uint32_t)0x0000003FU) /* Cycle count Max bits */ +#define FDCAN_TTMLM_CCM_NUM1 ((uint32_t)0x00000000U) /* 1 basic cycle per matrix cycle */ +#define FDCAN_TTMLM_CCM_NUM2 ((uint32_t)0x00000001U) /* 2 basic cycle per matrix cycle */ +#define FDCAN_TTMLM_CCM_NUM4 ((uint32_t)0x00000003U) /* 4 basic cycle per matrix cycle */ +#define FDCAN_TTMLM_CCM_NUM8 ((uint32_t)0x00000007U) /* 8 basic cycle per matrix cycle */ +#define FDCAN_TTMLM_CCM_NUM16 ((uint32_t)0x0000000FU) /* 16 basic cycle per matrix cycle */ +#define FDCAN_TTMLM_CCM_NUM32 ((uint32_t)0x0000001FU) /* 32 basic cycle per matrix cycle */ +#define FDCAN_TTMLM_CCM_NUM64 ((uint32_t)0x0000003FU) /* 64 basic cycle per matrix cycle */ + +/** Bit definition for FDCAN_TURCF register **/ +#define FDCAN_TURCF_ELT ((uint32_t)0x80000000U) /* Enable local time bit */ + +#define FDCAN_TURCF_DC ((uint32_t)0x3FFF0000U) /* Denominator configuration bits */ +#define FDCAN_TURCF_DC_0 ((uint32_t)0x00010000U) /* Denominator configuration bit0 */ +#define FDCAN_TURCF_DC_1 ((uint32_t)0x00020000U) /* Denominator configuration bit1 */ +#define FDCAN_TURCF_DC_2 ((uint32_t)0x00040000U) /* Denominator configuration bit2 */ +#define FDCAN_TURCF_DC_3 ((uint32_t)0x00080000U) /* Denominator configuration bit3 */ +#define FDCAN_TURCF_DC_4 ((uint32_t)0x00100000U) /* Denominator configuration bit4 */ +#define FDCAN_TURCF_DC_5 ((uint32_t)0x00200000U) /* Denominator configuration bit5 */ +#define FDCAN_TURCF_DC_6 ((uint32_t)0x00400000U) /* Denominator configuration bit6 */ +#define FDCAN_TURCF_DC_7 ((uint32_t)0x00800000U) /* Denominator configuration bit7 */ +#define FDCAN_TURCF_DC_8 ((uint32_t)0x01000000U) /* Denominator configuration bit8 */ +#define FDCAN_TURCF_DC_9 ((uint32_t)0x02000000U) /* Denominator configuration bit9 */ +#define FDCAN_TURCF_DC_10 ((uint32_t)0x04000000U) /* Denominator configuration bit10 */ +#define FDCAN_TURCF_DC_11 ((uint32_t)0x08000000U) /* Denominator configuration bit11 */ +#define FDCAN_TURCF_DC_12 ((uint32_t)0x10000000U) /* Denominator configuration bit12 */ +#define FDCAN_TURCF_DC_13 ((uint32_t)0x20000000U) /* Denominator configuration bit13 */ + +#define FDCAN_TURCF_NCL ((uint32_t)0x0000FFFFU) /* Numerator configuration low bits */ +#define FDCAN_TURCF_NCL_0 ((uint32_t)0x00000001U) /* Numerator configuration low bit0 */ +#define FDCAN_TURCF_NCL_1 ((uint32_t)0x00000002U) /* Numerator configuration low bit1 */ +#define FDCAN_TURCF_NCL_2 ((uint32_t)0x00000004U) /* Numerator configuration low bit2 */ +#define FDCAN_TURCF_NCL_3 ((uint32_t)0x00000008U) /* Numerator configuration low bit3 */ +#define FDCAN_TURCF_NCL_4 ((uint32_t)0x00000010U) /* Numerator configuration low bit4 */ +#define FDCAN_TURCF_NCL_5 ((uint32_t)0x00000020U) /* Numerator configuration low bit5 */ +#define FDCAN_TURCF_NCL_6 ((uint32_t)0x00000040U) /* Numerator configuration low bit6 */ +#define FDCAN_TURCF_NCL_7 ((uint32_t)0x00000080U) /* Numerator configuration low bit7 */ +#define FDCAN_TURCF_NCL_8 ((uint32_t)0x00000100U) /* Numerator configuration low bit8 */ +#define FDCAN_TURCF_NCL_9 ((uint32_t)0x00000200U) /* Numerator configuration low bit9 */ +#define FDCAN_TURCF_NCL_10 ((uint32_t)0x00000400U) /* Numerator configuration low bit10 */ +#define FDCAN_TURCF_NCL_11 ((uint32_t)0x00000800U) /* Numerator configuration low bit11 */ +#define FDCAN_TURCF_NCL_12 ((uint32_t)0x00001000U) /* Numerator configuration low bit12 */ +#define FDCAN_TURCF_NCL_13 ((uint32_t)0x00002000U) /* Numerator configuration low bit13 */ +#define FDCAN_TURCF_NCL_14 ((uint32_t)0x00004000U) /* Numerator configuration low bit14 */ +#define FDCAN_TURCF_NCL_15 ((uint32_t)0x00008000U) /* Numerator configuration low bit15 */ + +/** Bit definition for FDCAN_TTOCN register **/ +#define FDCAN_TTOCN_LCKC ((uint32_t)0x00008000U) /* TT operation control register Locked bit */ +#define FDCAN_TTOCN_ESCN ((uint32_t)0x00002000U) /* External synchronization control bit */ +#define FDCAN_TTOCN_NIG ((uint32_t)0x00001000U) /* Next is Gap bit */ +#define FDCAN_TTOCN_TMG ((uint32_t)0x00000800U) /* Time mark Gap bit */ +#define FDCAN_TTOCN_FGP ((uint32_t)0x00000400U) /* Finish Gap bit */ +#define FDCAN_TTOCN_GCS ((uint32_t)0x00000200U) /* Gap control select bit */ +#define FDCAN_TTOCN_TTIE ((uint32_t)0x00000100U) /* Trigger time mark interrupt pulse enable bit */ + +#define FDCAN_TTOCN_TMC ((uint32_t)0x000000C0U) /* Register time mark Compare bits */ +#define FDCAN_TTOCN_TMC_NONE ((uint32_t)0x00000000U) /* Register time stamp interrupt not generated */ +#define FDCAN_TTOCN_TMC_BASIC ((uint32_t)0x00000040U) /* If time stamp = cycle time, a register time stamp interrupt is generated */ +#define FDCAN_TTOCN_TMC_LOCAL ((uint32_t)0x00000080U) /* If time stamp = local time, a register time stamp interrupt is generated */ +#define FDCAN_TTOCN_TMC_GLOBAL ((uint32_t)0x000000C0U) /* If time stamp = global time, a register time stamp interrupt is generated */ + +#define FDCAN_TTOCN_RTIE ((uint32_t)0x00000020U) /* Register time mark interrupt pulse enable */ + +#define FDCAN_TTOCN_SWS ((uint32_t)0x00000018U) /* Stop watch source bits */ +#define FDCAN_TTOCN_SWS_STOP ((uint32_t)0x00000000U) /* Stop Monitor Disable */ +#define FDCAN_TTOCN_SWS_CYCLE ((uint32_t)0x00000008U) /* The actual value of the cycle time is copied to FDCAN_TTCPT.SWV */ +#define FDCAN_TTOCN_SWS_LOCAL ((uint32_t)0x00000010U) /* The actual value of the local time is copied to FDCAN_TTCPT.SWV */ +#define FDCAN_TTOCN_SWS_GLOBAL ((uint32_t)0x00000018U) /* The actual value of the global time is copied to FDCAN_TTCPT.SWV */ + +#define FDCAN_TTOCN_SWP ((uint32_t)0x00000004U) /* Stop watch polarity bit */ +#define FDCAN_TTOCN_ECS ((uint32_t)0x00000002U) /* External clock synchronization bit */ +#define FDCAN_TTOCN_SGT ((uint32_t)0x00000001U) /* Set global time bit */ + +/** Bit definition for FDCAN_TTGTP register **/ +#define FDCAN_TTGTP_CTP ((uint32_t)0xFFFF0000U) /* Cycle time target phase bits */ +#define FDCAN_TTGTP_CTP_0 ((uint32_t)0x00010000U) /* Cycle time target phase bit0 */ +#define FDCAN_TTGTP_CTP_1 ((uint32_t)0x00020000U) /* Cycle time target phase bit1 */ +#define FDCAN_TTGTP_CTP_2 ((uint32_t)0x00040000U) /* Cycle time target phase bit2 */ +#define FDCAN_TTGTP_CTP_3 ((uint32_t)0x00080000U) /* Cycle time target phase bit3 */ +#define FDCAN_TTGTP_CTP_4 ((uint32_t)0x00100000U) /* Cycle time target phase bit4 */ +#define FDCAN_TTGTP_CTP_5 ((uint32_t)0x00200000U) /* Cycle time target phase bit5 */ +#define FDCAN_TTGTP_CTP_6 ((uint32_t)0x00400000U) /* Cycle time target phase bit6 */ +#define FDCAN_TTGTP_CTP_7 ((uint32_t)0x00800000U) /* Cycle time target phase bit7 */ +#define FDCAN_TTGTP_CTP_8 ((uint32_t)0x01000000U) /* Cycle time target phase bit8 */ +#define FDCAN_TTGTP_CTP_9 ((uint32_t)0x02000000U) /* Cycle time target phase bit9 */ +#define FDCAN_TTGTP_CTP_10 ((uint32_t)0x04000000U) /* Cycle time target phase bit10 */ +#define FDCAN_TTGTP_CTP_11 ((uint32_t)0x08000000U) /* Cycle time target phase bit11 */ +#define FDCAN_TTGTP_CTP_12 ((uint32_t)0x10000000U) /* Cycle time target phase bit12 */ +#define FDCAN_TTGTP_CTP_13 ((uint32_t)0x20000000U) /* Cycle time target phase bit13 */ +#define FDCAN_TTGTP_CTP_14 ((uint32_t)0x40000000U) /* Cycle time target phase bit14 */ +#define FDCAN_TTGTP_CTP_15 ((uint32_t)0x80000000U) /* Cycle time target phase bit15 */ + +#define FDCAN_TTGTP_TP ((uint32_t)0x0000FFFFU) /* Time Preset bits */ +#define FDCAN_TTGTP_TP_0 ((uint32_t)0x00000001U) /* Time Preset bit0 */ +#define FDCAN_TTGTP_TP_1 ((uint32_t)0x00000002U) /* Time Preset bit1 */ +#define FDCAN_TTGTP_TP_2 ((uint32_t)0x00000004U) /* Time Preset bit2 */ +#define FDCAN_TTGTP_TP_3 ((uint32_t)0x00000008U) /* Time Preset bit3 */ +#define FDCAN_TTGTP_TP_4 ((uint32_t)0x00000010U) /* Time Preset bit4 */ +#define FDCAN_TTGTP_TP_5 ((uint32_t)0x00000020U) /* Time Preset bit5 */ +#define FDCAN_TTGTP_TP_6 ((uint32_t)0x00000040U) /* Time Preset bit6 */ +#define FDCAN_TTGTP_TP_7 ((uint32_t)0x00000080U) /* Time Preset bit7 */ +#define FDCAN_TTGTP_TP_8 ((uint32_t)0x00000100U) /* Time Preset bit8 */ +#define FDCAN_TTGTP_TP_9 ((uint32_t)0x00000200U) /* Time Preset bit9 */ +#define FDCAN_TTGTP_TP_10 ((uint32_t)0x00000400U) /* Time Preset bit10 */ +#define FDCAN_TTGTP_TP_11 ((uint32_t)0x00000800U) /* Time Preset bit11 */ +#define FDCAN_TTGTP_TP_12 ((uint32_t)0x00001000U) /* Time Preset bit12 */ +#define FDCAN_TTGTP_TP_13 ((uint32_t)0x00002000U) /* Time Preset bit13 */ +#define FDCAN_TTGTP_TP_14 ((uint32_t)0x00004000U) /* Time Preset bit14 */ +#define FDCAN_TTGTP_TP_15 ((uint32_t)0x00008000U) /* Time Preset bit15 */ + +/** Bit definition for FDCAN_TTTMK register **/ +#define FDCAN_TTTMK_LCKM ((uint32_t)0x80000000U) /* TT time mark register Locked */ + +#define FDCAN_TTTMK_TICC ((uint32_t)0x007F0000U) /* Time mark cycle code bits */ +#define FDCAN_TTTMK_TICC_0 ((uint32_t)0x00010000U) /* Time mark cycle code bit 0 */ +#define FDCAN_TTTMK_TICC_1 ((uint32_t)0x00020000U) /* Time mark cycle code bit 1 */ +#define FDCAN_TTTMK_TICC_2 ((uint32_t)0x00040000U) /* Time mark cycle code bit 2 */ +#define FDCAN_TTTMK_TICC_3 ((uint32_t)0x00080000U) /* Time mark cycle code bit 3 */ +#define FDCAN_TTTMK_TICC_4 ((uint32_t)0x00100000U) /* Time mark cycle code bit 4 */ +#define FDCAN_TTTMK_TICC_5 ((uint32_t)0x00200000U) /* Time mark cycle code bit 5 */ +#define FDCAN_TTTMK_TICC_6 ((uint32_t)0x00400000U) /* Time mark cycle code bit 6 */ + +#define FDCAN_TTTMK_TM ((uint32_t)0x0000FFFFU) /* Time mark bits */ +#define FDCAN_TTTMK_TM_0 ((uint32_t)0x00000001U) /* Time mark bit0 */ +#define FDCAN_TTTMK_TM_1 ((uint32_t)0x00000002U) /* Time mark bit1 */ +#define FDCAN_TTTMK_TM_2 ((uint32_t)0x00000004U) /* Time mark bit2 */ +#define FDCAN_TTTMK_TM_3 ((uint32_t)0x00000008U) /* Time mark bit3 */ +#define FDCAN_TTTMK_TM_4 ((uint32_t)0x00000010U) /* Time mark bit4 */ +#define FDCAN_TTTMK_TM_5 ((uint32_t)0x00000020U) /* Time mark bit5 */ +#define FDCAN_TTTMK_TM_6 ((uint32_t)0x00000040U) /* Time mark bit6 */ +#define FDCAN_TTTMK_TM_7 ((uint32_t)0x00000080U) /* Time mark bit7 */ +#define FDCAN_TTTMK_TM_8 ((uint32_t)0x00000100U) /* Time mark bit8 */ +#define FDCAN_TTTMK_TM_9 ((uint32_t)0x00000200U) /* Time mark bit9 */ +#define FDCAN_TTTMK_TM_10 ((uint32_t)0x00000400U) /* Time mark bit10 */ +#define FDCAN_TTTMK_TM_11 ((uint32_t)0x00000800U) /* Time mark bit11 */ +#define FDCAN_TTTMK_TM_12 ((uint32_t)0x00001000U) /* Time mark bit12 */ +#define FDCAN_TTTMK_TM_13 ((uint32_t)0x00002000U) /* Time mark bit13 */ +#define FDCAN_TTTMK_TM_14 ((uint32_t)0x00004000U) /* Time mark bit14 */ +#define FDCAN_TTTMK_TM_15 ((uint32_t)0x00008000U) /* Time mark bit15 */ + +/** Bit definition for FDCAN_TTIR register **/ +#define FDCAN_TTIR_CER ((uint32_t)0x00040000U) /* Configuration error bit */ +#define FDCAN_TTIR_AW ((uint32_t)0x00020000U) /* Application watchdog bit */ +#define FDCAN_TTIR_WT ((uint32_t)0x00010000U) /* Watch trigger bit */ +#define FDCAN_TTIR_IWT ((uint32_t)0x00008000U) /* Initialization watch trigger bit */ +#define FDCAN_TTIR_ELC ((uint32_t)0x00004000U) /* Error level Changed bit */ +#define FDCAN_TTIR_SE2 ((uint32_t)0x00002000U) /* Scheduling error 2 bit */ +#define FDCAN_TTIR_SE1 ((uint32_t)0x00001000U) /* Scheduling error 1 bit */ +#define FDCAN_TTIR_TXO ((uint32_t)0x00000800U) /* Tx count overflow bit */ +#define FDCAN_TTIR_TXU ((uint32_t)0x00000400U) /* Tx count underflow bit */ +#define FDCAN_TTIR_GTE ((uint32_t)0x00000200U) /* Global time error bit */ +#define FDCAN_TTIR_GTD ((uint32_t)0x00000100U) /* Global time discontinuity bit */ +#define FDCAN_TTIR_GTW ((uint32_t)0x00000080U) /* Global time wrap bit */ +#define FDCAN_TTIR_SWE ((uint32_t)0x00000040U) /* Stop watch event bit */ +#define FDCAN_TTIR_TTMI ((uint32_t)0x00000020U) /* Trigger time mark event internal bit */ +#define FDCAN_TTIR_RTMI ((uint32_t)0x00000010U) /* Register time mark interrupt bit */ +#define FDCAN_TTIR_SOG ((uint32_t)0x00000008U) /* Start of Gap bit */ +#define FDCAN_TTIR_CSM ((uint32_t)0x00000004U) /* Change of synchronization mode bit */ +#define FDCAN_TTIR_SMC ((uint32_t)0x00000002U) /* Start of matrix cycle bit */ +#define FDCAN_TTIR_SBC ((uint32_t)0x00000001U) /* Start of basic cycle bit */ + +/** Bit definition for FDCAN_TTIE register **/ +#define FDCAN_TTIE_CERE ((uint32_t)0x00040000U) /* Configuration error interrupt enable bit */ +#define FDCAN_TTIE_AWE ((uint32_t)0x00020000U) /* Application watchdog interrupt enable bit */ +#define FDCAN_TTIE_WTE ((uint32_t)0x00010000U) /* Watch trigger interrupt enable bit */ +#define FDCAN_TTIE_IWTE ((uint32_t)0x00008000U) /* Initialization watch trigger interrupt enable bit */ +#define FDCAN_TTIE_ELCE ((uint32_t)0x00004000U) /* Change error level interrupt enable bit */ +#define FDCAN_TTIE_SE2E ((uint32_t)0x00002000U) /* Scheduling error 2 interrupt enable bit */ +#define FDCAN_TTIE_SE1E ((uint32_t)0x00001000U) /* Scheduling error 1 interrupt enable bit */ +#define FDCAN_TTIE_TXOE ((uint32_t)0x00000800U) /* Tx count overflow interrupt enable bit */ +#define FDCAN_TTIE_TXUE ((uint32_t)0x00000400U) /* Tx count underflow interrupt enable bit */ +#define FDCAN_TTIE_GTEE ((uint32_t)0x00000200U) /* Global time error interrupt enable bit */ +#define FDCAN_TTIE_GTDE ((uint32_t)0x00000100U) /* Global time discontinuity interrupt enable bit */ +#define FDCAN_TTIE_GTWE ((uint32_t)0x00000080U) /* Global time wrap interrupt enable bit */ +#define FDCAN_TTIE_SWEE ((uint32_t)0x00000040U) /* Stop watch event interrupt enable bit */ +#define FDCAN_TTIE_TTMIE ((uint32_t)0x00000020U) /* Trigger time mark event internal interrupt enable bit */ +#define FDCAN_TTIE_RTMIE ((uint32_t)0x00000010U) /* Register time mark interrupt enable bit */ +#define FDCAN_TTIE_SOGE ((uint32_t)0x00000008U) /* Start of gap interrupt enable bit */ +#define FDCAN_TTIE_CSME ((uint32_t)0x00000004U) /* Change of synchronization mode interrupt enable bit */ +#define FDCAN_TTIE_SMCE ((uint32_t)0x00000002U) /* Start of matrix cycle interrupt enable bit */ +#define FDCAN_TTIE_SBCE ((uint32_t)0x00000001U) /* Start of basic cycle interrupt enable bit */ + +/** Bit definition for FDCAN_TTILS register **/ +#define FDCAN_TTILS_CERL ((uint32_t)0x00040000U) /* Configuration error interrupt Line bit */ +#define FDCAN_TTILS_AWL ((uint32_t)0x00020000U) /* Application watchdog interrupt Line bit */ +#define FDCAN_TTILS_WTL ((uint32_t)0x00010000U) /* Watch trigger interrupt Line bit */ +#define FDCAN_TTILS_IWTL ((uint32_t)0x00008000U) /* Initialization watch trigger interrupt Line bit */ +#define FDCAN_TTILS_ELCL ((uint32_t)0x00004000U) /* Change error level interrupt Line bit */ +#define FDCAN_TTILS_SE2L ((uint32_t)0x00002000U) /* Scheduling error 2 interrupt Line bit */ +#define FDCAN_TTILS_SE1L ((uint32_t)0x00001000U) /* Scheduling error 1 interrupt Line bit */ +#define FDCAN_TTILS_TXOL ((uint32_t)0x00000800U) /* Tx count overflow interrupt Line bit */ +#define FDCAN_TTILS_TXUL ((uint32_t)0x00000400U) /* Tx count underflow interrupt Line bit */ +#define FDCAN_TTILS_GTEL ((uint32_t)0x00000200U) /* Global time error interrupt Line bit */ +#define FDCAN_TTILS_GTDL ((uint32_t)0x00000100U) /* Global time discontinuity interrupt Line bit */ +#define FDCAN_TTILS_GTWL ((uint32_t)0x00000080U) /* Global time wrap interrupt Line bit */ +#define FDCAN_TTILS_SWEL ((uint32_t)0x00000040U) /* Stop watch event interrupt Line bit */ +#define FDCAN_TTILS_TTMIL ((uint32_t)0x00000020U) /* Trigger time mark event internal interrupt Line bit */ +#define FDCAN_TTILS_RTMIL ((uint32_t)0x00000010U) /* Register time mark interrupt Line bit */ +#define FDCAN_TTILS_SOGL ((uint32_t)0x00000008U) /* Start of gap interrupt Line bit */ +#define FDCAN_TTILS_CSML ((uint32_t)0x00000004U) /* Change of synchronization mode interrupt Line bit */ +#define FDCAN_TTILS_SMCL ((uint32_t)0x00000002U) /* Start of matrix cycle interrupt Line bit */ +#define FDCAN_TTILS_SBCL ((uint32_t)0x00000001U) /* Start of basic cycle interrupt Line bit */ + +/** Bit definition for FDCAN_TTOST register **/ +#define FDCAN_TTOST_SPL ((uint32_t)0x80000000U) /* Schedule phase lock bit */ +#define FDCAN_TTOST_WECS ((uint32_t)0x40000000U) /* Wait for external clock synchronization bit */ +#define FDCAN_TTOST_AWE ((uint32_t)0x20000000U) /* Application watchdog event bit */ +#define FDCAN_TTOST_WFE ((uint32_t)0x10000000U) /* Wait for event bit */ +#define FDCAN_TTOST_GSI ((uint32_t)0x08000000U) /* Gap started Indicator bit */ + +#define FDCAN_TTOST_TMP ((uint32_t)0x07000000U) /* Time master priority bits */ +#define FDCAN_TTOST_TMP_0 ((uint32_t)0x01000000U) /* Time master priority bit0 */ +#define FDCAN_TTOST_TMP_1 ((uint32_t)0x02000000U) /* Time master priority bit1 */ +#define FDCAN_TTOST_TMP_2 ((uint32_t)0x04000000U) /* Time master priority bit2 */ + +#define FDCAN_TTOST_GFI ((uint32_t)0x00800000U) /* Gap finished Indicator bit */ +#define FDCAN_TTOST_WGTD ((uint32_t)0x00400000U) /* Wait for global time discontinuity bits */ + +#define FDCAN_TTOST_RTO ((uint32_t)0x0000FF00U) /* Reference trigger offset bits */ +#define FDCAN_TTOST_RTO_0 ((uint32_t)0x00000100U) /* Reference trigger offset bit0 */ +#define FDCAN_TTOST_RTO_1 ((uint32_t)0x00000200U) /* Reference trigger offset bit1 */ +#define FDCAN_TTOST_RTO_2 ((uint32_t)0x00000400U) /* Reference trigger offset bit2 */ +#define FDCAN_TTOST_RTO_3 ((uint32_t)0x00000800U) /* Reference trigger offset bit3 */ +#define FDCAN_TTOST_RTO_4 ((uint32_t)0x00001000U) /* Reference trigger offset bit4 */ +#define FDCAN_TTOST_RTO_5 ((uint32_t)0x00002000U) /* Reference trigger offset bit5 */ +#define FDCAN_TTOST_RTO_6 ((uint32_t)0x00004000U) /* Reference trigger offset bit6 */ +#define FDCAN_TTOST_RTO_7 ((uint32_t)0x00008000U) /* Reference trigger offset bit7 */ + +#define FDCAN_TTOST_QCS ((uint32_t)0x00000080U) /* Quality of clock Speed bit */ +#define FDCAN_TTOST_QGTP ((uint32_t)0x00000040U) /* Quality of global time phase bit */ + +#define FDCAN_TTOST_SYS ((uint32_t)0x00000030U) /* Synchronization state bits */ +#define FDCAN_TTOST_SYS_NONE ((uint32_t)0x00000000U) /* unsynchronized */ +#define FDCAN_TTOST_SYS_BUS ((uint32_t)0x00000010U) /* Synchronization to FDCAN communications */ +#define FDCAN_TTOST_SYS_GAP ((uint32_t)0x00000020U) /* Scheduling is hung up by gaps (In_Gap) */ +#define FDCAN_TTOST_SYS_SCHEDULE ((uint32_t)0x00000030U) /* Synchronize to Schedule (In_Schedule) */ + +#define FDCAN_TTOST_MS ((uint32_t)0x0000000CU) /* Master state bits */ +#define FDCAN_TTOST_MS_NONE ((uint32_t)0x00000000U) /* No associated master node attributes */ +#define FDCAN_TTOST_MS_SLAVE ((uint32_t)0x00000004U) /* Working as a time-controlled node */ +#define FDCAN_TTOST_MS_BACKUP ((uint32_t)0x00000008U) /* Working as a backup time master node */ +#define FDCAN_TTOST_MS_CURRENT ((uint32_t)0x0000000CU) /* Work as a current time master node */ + +#define FDCAN_TTOST_EL ((uint32_t)0x00000003U) /* Error level bits */ +#define FDCAN_TTOST_EL_S0 ((uint32_t)0x00000000U) /* Severity 0 - no errors */ +#define FDCAN_TTOST_EL_S1 ((uint32_t)0x00000001U) /* Severity 1 - Warning */ +#define FDCAN_TTOST_EL_S2 ((uint32_t)0x00000002U) /* Severity 2 - Error */ +#define FDCAN_TTOST_EL_S3 ((uint32_t)0x00000003U) /* Severity 3 - Serious error */ + +/** Bit definition for FDCAN_TURNA register **/ +#define FDCAN_TURNA_NAV ((uint32_t)0x0003FFFFU) /* Numerator actual value bits */ +#define FDCAN_TURNA_NAV_0 ((uint32_t)0x00000001U) /* Numerator actual value bit0 */ +#define FDCAN_TURNA_NAV_1 ((uint32_t)0x00000002U) /* Numerator actual value bit1 */ +#define FDCAN_TURNA_NAV_2 ((uint32_t)0x00000004U) /* Numerator actual value bit2 */ +#define FDCAN_TURNA_NAV_3 ((uint32_t)0x00000008U) /* Numerator actual value bit3 */ +#define FDCAN_TURNA_NAV_4 ((uint32_t)0x00000010U) /* Numerator actual value bit4 */ +#define FDCAN_TURNA_NAV_5 ((uint32_t)0x00000020U) /* Numerator actual value bit5 */ +#define FDCAN_TURNA_NAV_6 ((uint32_t)0x00000040U) /* Numerator actual value bit6 */ +#define FDCAN_TURNA_NAV_7 ((uint32_t)0x00000080U) /* Numerator actual value bit7 */ +#define FDCAN_TURNA_NAV_8 ((uint32_t)0x00000100U) /* Numerator actual value bit8 */ +#define FDCAN_TURNA_NAV_9 ((uint32_t)0x00000200U) /* Numerator actual value bit9 */ +#define FDCAN_TURNA_NAV_10 ((uint32_t)0x00000400U) /* Numerator actual value bit10 */ +#define FDCAN_TURNA_NAV_11 ((uint32_t)0x00000800U) /* Numerator actual value bit11 */ +#define FDCAN_TURNA_NAV_12 ((uint32_t)0x00001000U) /* Numerator actual value bit12 */ +#define FDCAN_TURNA_NAV_13 ((uint32_t)0x00002000U) /* Numerator actual value bit13 */ +#define FDCAN_TURNA_NAV_14 ((uint32_t)0x00004000U) /* Numerator actual value bit14 */ +#define FDCAN_TURNA_NAV_15 ((uint32_t)0x00008000U) /* Numerator actual value bit15 */ +#define FDCAN_TURNA_NAV_16 ((uint32_t)0x00010000U) /* Numerator actual value bit16 */ +#define FDCAN_TURNA_NAV_17 ((uint32_t)0x00020000U) /* Numerator actual value bit17 */ + +/** Bit definition for FDCAN_TTLGT register **/ +#define FDCAN_TTLGT_GT ((uint32_t)0xFFFF0000U) /* Global time bits */ +#define FDCAN_TTLGT_GT_0 ((uint32_t)0x00010000U) /* Global time bit0 */ +#define FDCAN_TTLGT_GT_1 ((uint32_t)0x00020000U) /* Global time bit1 */ +#define FDCAN_TTLGT_GT_2 ((uint32_t)0x00040000U) /* Global time bit2 */ +#define FDCAN_TTLGT_GT_3 ((uint32_t)0x00080000U) /* Global time bit3 */ +#define FDCAN_TTLGT_GT_4 ((uint32_t)0x00100000U) /* Global time bit4 */ +#define FDCAN_TTLGT_GT_5 ((uint32_t)0x00200000U) /* Global time bit5 */ +#define FDCAN_TTLGT_GT_6 ((uint32_t)0x00400000U) /* Global time bit6 */ +#define FDCAN_TTLGT_GT_7 ((uint32_t)0x00800000U) /* Global time bit7 */ +#define FDCAN_TTLGT_GT_8 ((uint32_t)0x01000000U) /* Global time bit8 */ +#define FDCAN_TTLGT_GT_9 ((uint32_t)0x02000000U) /* Global time bit9 */ +#define FDCAN_TTLGT_GT_10 ((uint32_t)0x04000000U) /* Global time bit10 */ +#define FDCAN_TTLGT_GT_11 ((uint32_t)0x08000000U) /* Global time bit11 */ +#define FDCAN_TTLGT_GT_12 ((uint32_t)0x10000000U) /* Global time bit12 */ +#define FDCAN_TTLGT_GT_13 ((uint32_t)0x20000000U) /* Global time bit13 */ +#define FDCAN_TTLGT_GT_14 ((uint32_t)0x40000000U) /* Global time bit14 */ +#define FDCAN_TTLGT_GT_15 ((uint32_t)0x80000000U) /* Global time bit15 */ + +#define FDCAN_TTLGT_LT ((uint32_t)0x0000FFFFU) /* Local time bits */ +#define FDCAN_TTLGT_LT_0 ((uint32_t)0x00000001U) /* Local time bit0 */ +#define FDCAN_TTLGT_LT_1 ((uint32_t)0x00000002U) /* Local time bit1 */ +#define FDCAN_TTLGT_LT_2 ((uint32_t)0x00000004U) /* Local time bit2 */ +#define FDCAN_TTLGT_LT_3 ((uint32_t)0x00000008U) /* Local time bit3 */ +#define FDCAN_TTLGT_LT_4 ((uint32_t)0x00000010U) /* Local time bit4 */ +#define FDCAN_TTLGT_LT_5 ((uint32_t)0x00000020U) /* Local time bit5 */ +#define FDCAN_TTLGT_LT_6 ((uint32_t)0x00000040U) /* Local time bit6 */ +#define FDCAN_TTLGT_LT_7 ((uint32_t)0x00000080U) /* Local time bit7 */ +#define FDCAN_TTLGT_LT_8 ((uint32_t)0x00000100U) /* Local time bit8 */ +#define FDCAN_TTLGT_LT_9 ((uint32_t)0x00000200U) /* Local time bit9 */ +#define FDCAN_TTLGT_LT_10 ((uint32_t)0x00000400U) /* Local time bit10 */ +#define FDCAN_TTLGT_LT_11 ((uint32_t)0x00000800U) /* Local time bit11 */ +#define FDCAN_TTLGT_LT_12 ((uint32_t)0x00001000U) /* Local time bit12 */ +#define FDCAN_TTLGT_LT_13 ((uint32_t)0x00002000U) /* Local time bit13 */ +#define FDCAN_TTLGT_LT_14 ((uint32_t)0x00004000U) /* Local time bit14 */ +#define FDCAN_TTLGT_LT_15 ((uint32_t)0x00008000U) /* Local time bit15 */ + +/** Bit definition for FDCAN_TTCTC register **/ +#define FDCAN_TTCTC_CC ((uint32_t)0x003F0000U) /* Cycle count bits */ +#define FDCAN_TTCTC_CC_0 ((uint32_t)0x00010000U) /* Cycle count bit0 */ +#define FDCAN_TTCTC_CC_1 ((uint32_t)0x00020000U) /* Cycle count bit1 */ +#define FDCAN_TTCTC_CC_2 ((uint32_t)0x00040000U) /* Cycle count bit2 */ +#define FDCAN_TTCTC_CC_3 ((uint32_t)0x00080000U) /* Cycle count bit3 */ +#define FDCAN_TTCTC_CC_4 ((uint32_t)0x00100000U) /* Cycle count bit4 */ +#define FDCAN_TTCTC_CC_5 ((uint32_t)0x00200000U) /* Cycle count bit5 */ + +#define FDCAN_TTCTC_CT ((uint32_t)0x0000FFFFU) /* Cycle time bits */ +#define FDCAN_TTCTC_CT_0 ((uint32_t)0x00000001U) /* Cycle time bit0 */ +#define FDCAN_TTCTC_CT_1 ((uint32_t)0x00000002U) /* Cycle time bit1 */ +#define FDCAN_TTCTC_CT_2 ((uint32_t)0x00000004U) /* Cycle time bit2 */ +#define FDCAN_TTCTC_CT_3 ((uint32_t)0x00000008U) /* Cycle time bit3 */ +#define FDCAN_TTCTC_CT_4 ((uint32_t)0x00000010U) /* Cycle time bit4 */ +#define FDCAN_TTCTC_CT_5 ((uint32_t)0x00000020U) /* Cycle time bit5 */ +#define FDCAN_TTCTC_CT_6 ((uint32_t)0x00000040U) /* Cycle time bit6 */ +#define FDCAN_TTCTC_CT_7 ((uint32_t)0x00000080U) /* Cycle time bit7 */ +#define FDCAN_TTCTC_CT_8 ((uint32_t)0x00000100U) /* Cycle time bit8 */ +#define FDCAN_TTCTC_CT_9 ((uint32_t)0x00000200U) /* Cycle time bit9 */ +#define FDCAN_TTCTC_CT_10 ((uint32_t)0x00000400U) /* Cycle time bit10 */ +#define FDCAN_TTCTC_CT_11 ((uint32_t)0x00000800U) /* Cycle time bit11 */ +#define FDCAN_TTCTC_CT_12 ((uint32_t)0x00001000U) /* Cycle time bit12 */ +#define FDCAN_TTCTC_CT_13 ((uint32_t)0x00002000U) /* Cycle time bit13 */ +#define FDCAN_TTCTC_CT_14 ((uint32_t)0x00004000U) /* Cycle time bit14 */ +#define FDCAN_TTCTC_CT_15 ((uint32_t)0x00008000U) /* Cycle time bit15 */ + +/** Bit definition for FDCAN_TTCPT register **/ +#define FDCAN_TTCPT_SWV ((uint32_t)0xFFFF0000U) /* Stop watch value bits */ +#define FDCAN_TTCPT_SWV_0 ((uint32_t)0x00010000U) /* Stop watch value bit0 */ +#define FDCAN_TTCPT_SWV_1 ((uint32_t)0x00020000U) /* Stop watch value bit1 */ +#define FDCAN_TTCPT_SWV_2 ((uint32_t)0x00040000U) /* Stop watch value bit2 */ +#define FDCAN_TTCPT_SWV_3 ((uint32_t)0x00080000U) /* Stop watch value bit3 */ +#define FDCAN_TTCPT_SWV_4 ((uint32_t)0x00100000U) /* Stop watch value bit4 */ +#define FDCAN_TTCPT_SWV_5 ((uint32_t)0x00200000U) /* Stop watch value bit5 */ +#define FDCAN_TTCPT_SWV_6 ((uint32_t)0x00400000U) /* Stop watch value bit6 */ +#define FDCAN_TTCPT_SWV_7 ((uint32_t)0x00800000U) /* Stop watch value bit7 */ +#define FDCAN_TTCPT_SWV_8 ((uint32_t)0x01000000U) /* Stop watch value bit8 */ +#define FDCAN_TTCPT_SWV_9 ((uint32_t)0x02000000U) /* Stop watch value bit9 */ +#define FDCAN_TTCPT_SWV_10 ((uint32_t)0x04000000U) /* Stop watch value bit10 */ +#define FDCAN_TTCPT_SWV_11 ((uint32_t)0x08000000U) /* Stop watch value bit11 */ +#define FDCAN_TTCPT_SWV_12 ((uint32_t)0x10000000U) /* Stop watch value bit12 */ +#define FDCAN_TTCPT_SWV_13 ((uint32_t)0x20000000U) /* Stop watch value bit13 */ +#define FDCAN_TTCPT_SWV_14 ((uint32_t)0x40000000U) /* Stop watch value bit14 */ +#define FDCAN_TTCPT_SWV_15 ((uint32_t)0x80000000U) /* Stop watch value bit15 */ + +#define FDCAN_TTCPT_CCV ((uint32_t)0x0000003FU) /* Cycle count value bits */ +#define FDCAN_TTCPT_CCV_0 ((uint32_t)0x00000001U) /* Cycle count value bit0 */ +#define FDCAN_TTCPT_CCV_1 ((uint32_t)0x00000002U) /* Cycle count value bit1 */ +#define FDCAN_TTCPT_CCV_2 ((uint32_t)0x00000004U) /* Cycle count value bit2 */ +#define FDCAN_TTCPT_CCV_3 ((uint32_t)0x00000008U) /* Cycle count value bit3 */ +#define FDCAN_TTCPT_CCV_4 ((uint32_t)0x00000010U) /* Cycle count value bit4 */ +#define FDCAN_TTCPT_CCV_5 ((uint32_t)0x00000020U) /* Cycle count value bit5 */ + +/** Bit definition for FDCAN_TTCSM register **/ +#define FDCAN_TTCSM_CSM ((uint32_t)0x0000FFFFU) /* Cycle sync mark bits */ +#define FDCAN_TTCSM_CSM_0 ((uint32_t)0x00000001U) /* Cycle sync mark bit0 */ +#define FDCAN_TTCSM_CSM_1 ((uint32_t)0x00000002U) /* Cycle sync mark bit1 */ +#define FDCAN_TTCSM_CSM_2 ((uint32_t)0x00000004U) /* Cycle sync mark bit2 */ +#define FDCAN_TTCSM_CSM_3 ((uint32_t)0x00000008U) /* Cycle sync mark bit3 */ +#define FDCAN_TTCSM_CSM_4 ((uint32_t)0x00000010U) /* Cycle sync mark bit4 */ +#define FDCAN_TTCSM_CSM_5 ((uint32_t)0x00000020U) /* Cycle sync mark bit5 */ +#define FDCAN_TTCSM_CSM_6 ((uint32_t)0x00000040U) /* Cycle sync mark bit6 */ +#define FDCAN_TTCSM_CSM_7 ((uint32_t)0x00000080U) /* Cycle sync mark bit7 */ +#define FDCAN_TTCSM_CSM_8 ((uint32_t)0x00000100U) /* Cycle sync mark bit8 */ +#define FDCAN_TTCSM_CSM_9 ((uint32_t)0x00000200U) /* Cycle sync mark bit9 */ +#define FDCAN_TTCSM_CSM_10 ((uint32_t)0x00000400U) /* Cycle sync mark bit10 */ +#define FDCAN_TTCSM_CSM_11 ((uint32_t)0x00000800U) /* Cycle sync mark bit11 */ +#define FDCAN_TTCSM_CSM_12 ((uint32_t)0x00001000U) /* Cycle sync mark bit12 */ +#define FDCAN_TTCSM_CSM_13 ((uint32_t)0x00002000U) /* Cycle sync mark bit13 */ +#define FDCAN_TTCSM_CSM_14 ((uint32_t)0x00004000U) /* Cycle sync mark bit14 */ +#define FDCAN_TTCSM_CSM_15 ((uint32_t)0x00008000U) /* Cycle sync mark bit15 */ + +/** Bit definition for FDCAN_TTTS register **/ +#define FDCAN_TTSS_SSWT ((uint32_t)0x00000003U) /* Select SWT bits */ +#define FDCAN_TTSS_SSWT_0 ((uint32_t)0x00000000U) /* Select SWT0 */ +#define FDCAN_TTSS_SSWT_1 ((uint32_t)0x00000001U) /* Select SWT1 */ +#define FDCAN_TTSS_SSWT_2 ((uint32_t)0x00000002U) /* Select SWT1 */ +#define FDCAN_TTSS_SSWT_3 ((uint32_t)0x00000003U) /* Select SWT2 */ + +#define FDCAN_TTSS_SEVT ((uint32_t)0x0000000CU) /* Select SWT bits */ +#define FDCAN_TTSS_SEVT_0 ((uint32_t)0x00000000U) /* Select SWT0 */ +#define FDCAN_TTSS_SEVT_1 ((uint32_t)0x00000004U) /* Select SWT1 */ +#define FDCAN_TTSS_SEVT_2 ((uint32_t)0x00000008U) /* Select SWT2 */ +#define FDCAN_TTSS_SEVT_3 ((uint32_t)0x0000000CU) /* Select SWT3 */ + +#define FDCAN_TTSS_MRD ((uint32_t)0x00000010U) /* Modify on read */ + +#define FDCAN_TTSS_TS_SEL ((uint32_t)0x000000E0U) /* Select External timestamp clock divided bits */ +#define FDCAN_TTSS_TS_SEL_0 ((uint32_t)0x00000020U) /* Select External timestamp clock divided bit 0 */ +#define FDCAN_TTSS_TS_SEL_1 ((uint32_t)0x00000040U) /* Select External timestamp clock divided bit 1 */ +#define FDCAN_TTSS_TS_SEL_2 ((uint32_t)0x00000080U) /* Select External timestamp clock divided bit 2 */ + +#define FDCAN_TTSS_TS_SEL_DIV4 ((uint32_t)0x00000000U) /* Select External timestamp clock divided is 4 */ +#define FDCAN_TTSS_TS_SEL_DIV8 ((uint32_t)0x00000020U) /* Select External timestamp clock divided is 8 */ +#define FDCAN_TTSS_TS_SEL_DIV16 ((uint32_t)0x00000040U) /* Select External timestamp clock divided is 16 */ +#define FDCAN_TTSS_TS_SEL_DIV32 ((uint32_t)0x00000060U) /* Select External timestamp clock divided is 32 */ +#define FDCAN_TTSS_TS_SEL_DIV64 ((uint32_t)0x00000080U) /* Select External timestamp clock divided is 64 */ +#define FDCAN_TTSS_TS_SEL_DIV128 ((uint32_t)0x000000A0U) /* Select External timestamp clock divided is 128 */ +#define FDCAN_TTSS_TS_SEL_DIV256 ((uint32_t)0x000000C0U) /* Select External timestamp clock divided is 256 */ +#define FDCAN_TTSS_TS_SEL_DIV512 ((uint32_t)0x000000E0U) /* Select External timestamp clock divided is 512 */ + +#define FDCAN_TTSS_TS_EN ((uint32_t)0x00000100U) /* External timestamp vector enable */ + +#define FDCAN_TTSS_RAMSEL ((uint32_t)0x00000200U) /* Message RAM Selection */ + +/*** Secure digital multimedia cards ***/ + +/** Bit definition for SDMMC_CFG1 register **/ +#define SDMMC_CFG1_MBL ((uint32_t)0x00C00000U) /* Maximum Block Length supported by the Core/Device */ +#define SDMMC_CFG1_MBL_0 ((uint32_t)0x00400000U) /* Maximum Block Length supported by the Core/Device bit0 */ +#define SDMMC_CFG1_MBL_1 ((uint32_t)0x00800000U) /* Maximum Block Length supported by the Core/Device bit1 */ +#define SDMMC_CFG1_BCLKF ((uint32_t)0x003FC000U) /* Base Clock Frequency for SD Clock */ +#define SDMMC_CFG1_BCLKF_0 ((uint32_t)0x00004000U) /* Base Clock Frequency for SD Clock bit0 */ +#define SDMMC_CFG1_BCLKF_1 ((uint32_t)0x00008000U) /* Base Clock Frequency for SD Clock bit1 */ +#define SDMMC_CFG1_BCLKF_2 ((uint32_t)0x00010000U) /* Base Clock Frequency for SD Clock bit2 */ +#define SDMMC_CFG1_BCLKF_3 ((uint32_t)0x00020000U) /* Base Clock Frequency for SD Clock bit3 */ +#define SDMMC_CFG1_BCLKF_4 ((uint32_t)0x00040000U) /* Base Clock Frequency for SD Clock bit4 */ +#define SDMMC_CFG1_BCLKF_5 ((uint32_t)0x00080000U) /* Base Clock Frequency for SD Clock bit5 */ +#define SDMMC_CFG1_BCLKF_6 ((uint32_t)0x00100000U) /* Base Clock Frequency for SD Clock bit6 */ +#define SDMMC_CFG1_BCLKF_7 ((uint32_t)0x00200000U) /* Base Clock Frequency for SD Clock bit7 */ +#define SDMMC_CFG1_TCLKU ((uint32_t)0x00002000U) /* Timeout Clock Unit */ +#define SDMMC_CFG1_TCNT ((uint32_t)0x0000007EU) /* Tuning Count */ +#define SDMMC_CFG1_TCNT_0 ((uint32_t)0x00000002U) /* Tuning Count bit0 */ +#define SDMMC_CFG1_TCNT_1 ((uint32_t)0x00000004U) /* Tuning Count bit1 */ +#define SDMMC_CFG1_TCNT_2 ((uint32_t)0x00000008U) /* Tuning Count bit2 */ +#define SDMMC_CFG1_TCNT_3 ((uint32_t)0x00000010U) /* Tuning Count bit3 */ +#define SDMMC_CFG1_TCNT_4 ((uint32_t)0x00000020U) /* Tuning Count bit4 */ +#define SDMMC_CFG1_TCNT_5 ((uint32_t)0x00000040U) /* Tuning Count bit5 */ +#define SDMMC_CFG1_WSGM ((uint32_t)0x00000001U) /* Wakeup Signal Generation Mode */ + +/** Bit definition for SDMMC_CFG2 register **/ +#define SDMMC_CFG2_SPIBMOD ((uint32_t)0x00080000U) /* SPI Block Mode */ +#define SDMMC_CFG2_SPIMOD ((uint32_t)0x00040000U) /* SPI Mode */ +#define SDMMC_CFG2_DDR50 ((uint32_t)0x00004000U) /* DDR50 Support */ +#define SDMMC_CFG2_SDR104 ((uint32_t)0x00002000U) /* SDR104 Support */ +#define SDMMC_CFG2_SDR50 ((uint32_t)0x00001000U) /* SDR50 Support */ +#define SDMMC_CFG2_STYP ((uint32_t)0x00000C00U) /* lot Type */ +#define SDMMC_CFG2_STYP_0 ((uint32_t)0x00000400U) /* lot Type bit0 */ +#define SDMMC_CFG2_STYP_1 ((uint32_t)0x00000800U) /* lot Type bit1 */ +#define SDMMC_CFG2_ASYNCINT ((uint32_t)0x00000200U) /* Asynchronous Interrupt */ +#define SDMMC_CFG2_VS33 ((uint32_t)0x00000020U) /* 3.3V Support */ +#define SDMMC_CFG2_SRS ((uint32_t)0x00000010U) /* Suspend/Resume Support */ +#define SDMMC_CFG2_SDMA ((uint32_t)0x00000008U) /* SDMA Support */ +#define SDMMC_CFG2_HS ((uint32_t)0x00000004U) /* High Speed Support */ +#define SDMMC_CFG2_ADMA2 ((uint32_t)0x00000002U) /* ADMA2 Mode */ +#define SDMMC_CFG2_EMBUS ((uint32_t)0x00000001U) /* 8-bit Support for Embedded Device */ + +/** Bit definition for SDMMC_CFG3 register **/ +#define SDMMC_CFG3_UTFSDR50 ((uint32_t)0x00000010U) /* Use Tuning for SDR50 */ + +/** Bit definition for SDMMC_PV0CTRL register **/ +#define SDMMC_PV0CTRL_CLKFS_DS ((uint32_t)0x007FE000U) /* SDCLK Frequency Select Value for Default Speed */ +#define SDMMC_PV0CTRL_CLKFS_DS_0 ((uint32_t)0x00002000U) /* SDCLK Frequency Select Value for Default Speed bit0 */ +#define SDMMC_PV0CTRL_CLKFS_DS_1 ((uint32_t)0x00004000U) /* SDCLK Frequency Select Value for Default Speed bit1 */ +#define SDMMC_PV0CTRL_CLKFS_DS_2 ((uint32_t)0x00008000U) /* SDCLK Frequency Select Value for Default Speed bit2 */ +#define SDMMC_PV0CTRL_CLKFS_DS_3 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for Default Speed bit3 */ +#define SDMMC_PV0CTRL_CLKFS_DS_4 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for Default Speed bit4 */ +#define SDMMC_PV0CTRL_CLKFS_DS_5 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for Default Speed bit5 */ +#define SDMMC_PV0CTRL_CLKFS_DS_6 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for Default Speed bit6 */ +#define SDMMC_PV0CTRL_CLKFS_DS_7 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for Default Speed bit7 */ +#define SDMMC_PV0CTRL_CLKFS_DS_8 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for Default Speed bit8 */ +#define SDMMC_PV0CTRL_CLKFS_DS_9 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for Default Speed bit9 */ +#define SDMMC_PV0CTRL_CLKFS_INIT ((uint32_t)0x00001FFFU) /* SDCLK Frequency Select Value for Initialization */ +#define SDMMC_PV0CTRL_CLKFS_INIT_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for Initialization Bit0*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for Initialization Bit1*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for Initialization Bit2*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for Initialization Bit3*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for Initialization Bit4*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for Initialization Bit5*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for Initialization Bit6*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for Initialization Bit7*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for Initialization Bit8*/ +#define SDMMC_PV0CTRL_CLKFS_INIT_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for Initialization Bit9*/ + +/** Bit definition for SDMMC_PV1CTRL register **/ +#define SDMMC_PV1CTRL_CLKFS_SDR12 ((uint32_t)0x007FE000U) /* SDCLK Frequency Select Value for SDR12 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_0 ((uint32_t)0x00002000U) /* SDCLK Frequency Select Value for SDR12 bit0 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_1 ((uint32_t)0x00004000U) /* SDCLK Frequency Select Value for SDR12 bit1 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_2 ((uint32_t)0x00008000U) /* SDCLK Frequency Select Value for SDR12 bit2 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_3 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for SDR12 bit3 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_4 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for SDR12 bit4 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_5 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for SDR12 bit5 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_6 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for SDR12 bit6 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_7 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for SDR12 bit7 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_8 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for SDR12 bit8 */ +#define SDMMC_PV1CTRL_CLKFS_SDR12_9 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for SDR12 bit9 */ +#define SDMMC_PV1CTRL_CLKFS_HS ((uint32_t)0x00001FFFU) /* SDCLK Frequency Select Value for High Speed */ +#define SDMMC_PV1CTRL_CLKFS_HS_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for High Speed Bit0 */ +#define SDMMC_PV1CTRL_CLKFS_HS_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for High Speed Bit1 */ +#define SDMMC_PV1CTRL_CLKFS_HS_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for High Speed Bit2 */ +#define SDMMC_PV1CTRL_CLKFS_HS_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for High Speed Bit3 */ +#define SDMMC_PV1CTRL_CLKFS_HS_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for High Speed Bit4 */ +#define SDMMC_PV1CTRL_CLKFS_HS_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for High Speed Bit5 */ +#define SDMMC_PV1CTRL_CLKFS_HS_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for High Speed Bit6 */ +#define SDMMC_PV1CTRL_CLKFS_HS_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for High Speed Bit7 */ +#define SDMMC_PV1CTRL_CLKFS_HS_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for High Speed Bit8 */ +#define SDMMC_PV1CTRL_CLKFS_HS_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for High Speed Bit9 */ + +/** Bit definition for SDMMC_PV2CTRL register **/ +#define SDMMC_PV2CTRL_CLKFS_SDR50 ((uint32_t)0x007FE000U) /* SDCLK Frequency Select Value for SDR50 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_0 ((uint32_t)0x00002000U) /* SDCLK Frequency Select Value for SDR50 Bit0 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_1 ((uint32_t)0x00004000U) /* SDCLK Frequency Select Value for SDR50 Bit1 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_2 ((uint32_t)0x00008000U) /* SDCLK Frequency Select Value for SDR50 Bit2 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_3 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for SDR50 Bit3 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_4 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for SDR50 Bit4 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_5 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for SDR50 Bit5 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_6 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for SDR50 Bit6 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_7 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for SDR50 Bit7 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_8 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for SDR50 Bit8 */ +#define SDMMC_PV2CTRL_CLKFS_SDR50_9 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for SDR50 Bit9 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25 ((uint32_t)0x00001FFFU) /* SDCLK Frequency Select Value for SDR25 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for SDR25 Bit0 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for SDR25 Bit1 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for SDR25 Bit2 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for SDR25 Bit3 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for SDR25 Bit4 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for SDR25 Bit5 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for SDR25 Bit6 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for SDR25 Bit7 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for SDR25 Bit8 */ +#define SDMMC_PV2CTRL_CLKFS_SDR25_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for SDR25 Bit9 */ + +/** Bit definition for SDMMC_PV3CTRL register **/ +#define SDMMC_PV3CTRL_CLKFS_SDR104 ((uint32_t)0x007FE000U) /* SDCLK Frequency Select Value for SDR104 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_0 ((uint32_t)0x00002000U) /* SDCLK Frequency Select Value for SDR104 Bit0 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_1 ((uint32_t)0x00004000U) /* SDCLK Frequency Select Value for SDR104 Bit1 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_2 ((uint32_t)0x00008000U) /* SDCLK Frequency Select Value for SDR104 Bit2 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_3 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for SDR104 Bit3 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_4 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for SDR104 Bit4 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_5 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for SDR104 Bit5 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_6 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for SDR104 Bit6 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_7 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for SDR104 Bit7 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_8 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for SDR104 Bit8 */ +#define SDMMC_PV3CTRL_CLKFS_SDR104_9 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for SDR104 Bit9 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50 ((uint32_t)0x00001FFFU) /* SDCLK Frequency Select Value for DDR50 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for DDR50 Bit0 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for DDR50 Bit1 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for DDR50 Bit2 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for DDR50 Bit3 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for DDR50 Bit4 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for DDR50 Bit5 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for DDR50 Bit6 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for DDR50 Bit7 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for DDR50 Bit8 */ +#define SDMMC_PV3CTRL_CLKFS_DDR50_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for DDR50 Bit9 */ + +/** Bit definition for SDMMC_DLYCTRL register **/ +#define SDMMC_DLYCTRL_OTDE ((uint32_t)0x00000800U) /* Output tap Delay Enable */ +#define SDMMC_DLYCTRL_OTDS ((uint32_t)0x00000780U) /* Output Tap Delay Select */ +#define SDMMC_DLYCTRL_OTDS_0 ((uint32_t)0x00000080U) /* Output Tap Delay Select bit0 */ +#define SDMMC_DLYCTRL_OTDS_1 ((uint32_t)0x00000100U) /* Output Tap Delay Select bit1 */ +#define SDMMC_DLYCTRL_OTDS_2 ((uint32_t)0x00000200U) /* Output Tap Delay Select bit2 */ +#define SDMMC_DLYCTRL_OTDS_3 ((uint32_t)0x00000400U) /* Output Tap Delay Select bit3 */ +#define SDMMC_DLYCTRL_ITCW ((uint32_t)0x00000040U) /* Input Tap Change Window */ +#define SDMMC_DLYCTRL_ITDE ((uint32_t)0x00000020U) /* Input Tap Delay Enable */ +#define SDMMC_DLYCTRL_ITDS ((uint32_t)0x0000001FU) /* Input Tap Delay Select */ +#define SDMMC_DLYCTRL_ITDS_0 ((uint32_t)0x00000001U) /* Input Tap Delay Select Bit0 */ +#define SDMMC_DLYCTRL_ITDS_1 ((uint32_t)0x00000002U) /* Input Tap Delay Select Bit1 */ +#define SDMMC_DLYCTRL_ITDS_2 ((uint32_t)0x00000004U) /* Input Tap Delay Select Bit2 */ +#define SDMMC_DLYCTRL_ITDS_3 ((uint32_t)0x00000008U) /* Input Tap Delay Select Bit3 */ +#define SDMMC_DLYCTRL_ITDS_4 ((uint32_t)0x00000010U) /* Input Tap Delay Select Bit4 */ + +/** Bit definition for SDHOST_DSADD register **/ +#define SDHOST_DSADD_ADD ((uint32_t)0xFFFFFFFFU) /* physical system memory address used for DMA transfers + or the second argument for the Auto CMD23 Bits */ + +/** Bit definition for SDHOST_BLKCFG register **/ +#define SDHOST_BLKCFG_CNT ((uint32_t)0xFFFF0000U) /* Blocks Count for Current Transfer bits */ +#define SDHOST_BLKCFG_CNT_0 ((uint32_t)0x00010000U) /* Blocks Count for Current Transfer bit0 */ +#define SDHOST_BLKCFG_CNT_1 ((uint32_t)0x00020000U) /* Blocks Count for Current Transfer bit1 */ +#define SDHOST_BLKCFG_CNT_2 ((uint32_t)0x00040000U) /* Blocks Count for Current Transfer bit2 */ +#define SDHOST_BLKCFG_CNT_3 ((uint32_t)0x00080000U) /* Blocks Count for Current Transfer bit3 */ +#define SDHOST_BLKCFG_CNT_4 ((uint32_t)0x00100000U) /* Blocks Count for Current Transfer bit4 */ +#define SDHOST_BLKCFG_CNT_5 ((uint32_t)0x00200000U) /* Blocks Count for Current Transfer bit5 */ +#define SDHOST_BLKCFG_CNT_6 ((uint32_t)0x00400000U) /* Blocks Count for Current Transfer bit6 */ +#define SDHOST_BLKCFG_CNT_7 ((uint32_t)0x00800000U) /* Blocks Count for Current Transfer bit7 */ +#define SDHOST_BLKCFG_CNT_8 ((uint32_t)0x01000000U) /* Blocks Count for Current Transfer bit8 */ +#define SDHOST_BLKCFG_CNT_9 ((uint32_t)0x02000000U) /* Blocks Count for Current Transfer bit9 */ +#define SDHOST_BLKCFG_CNT_10 ((uint32_t)0x04000000U) /* Blocks Count for Current Transfer bit10 */ +#define SDHOST_BLKCFG_CNT_11 ((uint32_t)0x08000000U) /* Blocks Count for Current Transfer bit11 */ +#define SDHOST_BLKCFG_CNT_12 ((uint32_t)0x10000000U) /* Blocks Count for Current Transfer bit12 */ +#define SDHOST_BLKCFG_CNT_13 ((uint32_t)0x20000000U) /* Blocks Count for Current Transfer bit13 */ +#define SDHOST_BLKCFG_CNT_14 ((uint32_t)0x40000000U) /* Blocks Count for Current Transfer bit14 */ +#define SDHOST_BLKCFG_CNT_15 ((uint32_t)0x80000000U) /* Blocks Count for Current Transfer bit15 */ +#define SDHOST_BLKCFG_HDBS ((uint32_t)0x00007000U) /* Host SDMA Buffer Size */ +#define SDHOST_BLKCFG_HDBS_0 ((uint32_t)0x00001000U) /* Host SDMA Buffer Size Bit0 */ +#define SDHOST_BLKCFG_HDBS_1 ((uint32_t)0x00002000U) /* Host SDMA Buffer Size Bit1 */ +#define SDHOST_BLKCFG_HDBS_2 ((uint32_t)0x00004000U) /* Host SDMA Buffer Size Bit2 */ +#define SDHOST_BLKCFG_SIZE ((uint32_t)0x00000FFFU) /* Transfer Block Size */ +#define SDHOST_BLKCFG_SIZE_0 ((uint32_t)0x00000001U) /* Transfer Block Size Bit0 */ +#define SDHOST_BLKCFG_SIZE_1 ((uint32_t)0x00000002U) /* Transfer Block Size Bit1 */ +#define SDHOST_BLKCFG_SIZE_2 ((uint32_t)0x00000004U) /* Transfer Block Size Bit2 */ +#define SDHOST_BLKCFG_SIZE_3 ((uint32_t)0x00000008U) /* Transfer Block Size Bit3 */ +#define SDHOST_BLKCFG_SIZE_4 ((uint32_t)0x00000010U) /* Transfer Block Size Bit4 */ +#define SDHOST_BLKCFG_SIZE_5 ((uint32_t)0x00000020U) /* Transfer Block Size Bit5 */ +#define SDHOST_BLKCFG_SIZE_6 ((uint32_t)0x00000040U) /* Transfer Block Size Bit6 */ +#define SDHOST_BLKCFG_SIZE_7 ((uint32_t)0x00000080U) /* Transfer Block Size Bit7 */ +#define SDHOST_BLKCFG_SIZE_8 ((uint32_t)0x00000100U) /* Transfer Block Size Bit8 */ +#define SDHOST_BLKCFG_SIZE_9 ((uint32_t)0x00000200U) /* Transfer Block Size Bit9 */ +#define SDHOST_BLKCFG_SIZE_10 ((uint32_t)0x00000400U) /* Transfer Block Size Bit10 */ +#define SDHOST_BLKCFG_SIZE_11 ((uint32_t)0x00000800U) /* Transfer Block Size Bit11 */ + +/** Bit definition for SDHOST_CMDARG1 register **/ +#define SDHOST_CMDARG1_ARG1 ((uint32_t)0xFFFFFFFFU) /* SD CMD Argument Bit */ +#define SDHOST_CMDARG1_ARG1_0 ((uint32_t)0x00000001U) /* SD CMD Argument Bit0 */ +#define SDHOST_CMDARG1_ARG1_1 ((uint32_t)0x00000002U) /* SD CMD Argument Bit1 */ +#define SDHOST_CMDARG1_ARG1_2 ((uint32_t)0x00000004U) /* SD CMD Argument Bit2 */ +#define SDHOST_CMDARG1_ARG1_3 ((uint32_t)0x00000008U) /* SD CMD Argument Bit3 */ +#define SDHOST_CMDARG1_ARG1_4 ((uint32_t)0x00000010U) /* SD CMD Argument Bit4 */ +#define SDHOST_CMDARG1_ARG1_5 ((uint32_t)0x00000020U) /* SD CMD Argument Bit5 */ +#define SDHOST_CMDARG1_ARG1_6 ((uint32_t)0x00000040U) /* SD CMD Argument Bit6 */ +#define SDHOST_CMDARG1_ARG1_7 ((uint32_t)0x00000080U) /* SD CMD Argument Bit7 */ +#define SDHOST_CMDARG1_ARG1_8 ((uint32_t)0x00000100U) /* SD CMD Argument Bit8 */ +#define SDHOST_CMDARG1_ARG1_9 ((uint32_t)0x00000200U) /* SD CMD Argument Bit9 */ +#define SDHOST_CMDARG1_ARG1_10 ((uint32_t)0x00000400U) /* SD CMD Argument Bit10 */ +#define SDHOST_CMDARG1_ARG1_11 ((uint32_t)0x00000800U) /* SD CMD Argument Bit11 */ +#define SDHOST_CMDARG1_ARG1_12 ((uint32_t)0x00001000U) /* SD CMD Argument Bit12 */ +#define SDHOST_CMDARG1_ARG1_13 ((uint32_t)0x00002000U) /* SD CMD Argument Bit13 */ +#define SDHOST_CMDARG1_ARG1_14 ((uint32_t)0x00004000U) /* SD CMD Argument Bit14 */ +#define SDHOST_CMDARG1_ARG1_15 ((uint32_t)0x00008000U) /* SD CMD Argument Bit15 */ +#define SDHOST_CMDARG1_ARG1_16 ((uint32_t)0x00010000U) /* SD CMD Argument Bit16 */ +#define SDHOST_CMDARG1_ARG1_17 ((uint32_t)0x00020000U) /* SD CMD Argument Bit17 */ +#define SDHOST_CMDARG1_ARG1_18 ((uint32_t)0x00040000U) /* SD CMD Argument Bit18 */ +#define SDHOST_CMDARG1_ARG1_19 ((uint32_t)0x00080000U) /* SD CMD Argument Bit19 */ +#define SDHOST_CMDARG1_ARG1_20 ((uint32_t)0x00100000U) /* SD CMD Argument Bit20 */ +#define SDHOST_CMDARG1_ARG1_21 ((uint32_t)0x00200000U) /* SD CMD Argument Bit21 */ +#define SDHOST_CMDARG1_ARG1_22 ((uint32_t)0x00400000U) /* SD CMD Argument Bit22 */ +#define SDHOST_CMDARG1_ARG1_23 ((uint32_t)0x00800000U) /* SD CMD Argument Bit23 */ +#define SDHOST_CMDARG1_ARG1_24 ((uint32_t)0x01000000U) /* SD CMD Argument Bit24 */ +#define SDHOST_CMDARG1_ARG1_25 ((uint32_t)0x02000000U) /* SD CMD Argument Bit25 */ +#define SDHOST_CMDARG1_ARG1_26 ((uint32_t)0x04000000U) /* SD CMD Argument Bit26 */ +#define SDHOST_CMDARG1_ARG1_27 ((uint32_t)0x08000000U) /* SD CMD Argument Bit27 */ +#define SDHOST_CMDARG1_ARG1_28 ((uint32_t)0x10000000U) /* SD CMD Argument Bit28 */ +#define SDHOST_CMDARG1_ARG1_29 ((uint32_t)0x20000000U) /* SD CMD Argument Bit29 */ +#define SDHOST_CMDARG1_ARG1_30 ((uint32_t)0x40000000U) /* SD CMD Argument Bit30 */ +#define SDHOST_CMDARG1_ARG1_31 ((uint32_t)0x80000000U) /* SD CMD Argument Bit31 */ + +/** Bit definition for SDHOST_TMODE register **/ +#define SDHOST_TMODE_INDEX ((uint32_t)0x3F000000U) /* Command Index */ +#define SDHOST_TMODE_INDEX_0 ((uint32_t)0x01000000U) /* Command Index Bit0 */ +#define SDHOST_TMODE_INDEX_1 ((uint32_t)0x02000000U) /* Command Index Bit1 */ +#define SDHOST_TMODE_INDEX_2 ((uint32_t)0x04000000U) /* Command Index Bit2 */ +#define SDHOST_TMODE_INDEX_3 ((uint32_t)0x08000000U) /* Command Index Bit3 */ +#define SDHOST_TMODE_INDEX_4 ((uint32_t)0x10000000U) /* Command Index Bit4 */ +#define SDHOST_TMODE_INDEX_5 ((uint32_t)0x20000000U) /* Command Index Bit5 */ +#define SDHOST_TMODE_TYPE ((uint32_t)0x00C00000U) /* Command Type */ +#define SDHOST_TMODE_TYPE_0 ((uint32_t)0x00400000U) /* Command Type bit0 */ +#define SDHOST_TMODE_TYPE_1 ((uint32_t)0x00800000U) /* Command Type bit1 */ +#define SDHOST_TMODE_DPRESEL ((uint32_t)0x00200000U) /* Data Present Select */ +#define SDHOST_TMODE_INDEXCK ((uint32_t)0x00100000U) /* Command Index Check Enable */ +#define SDHOST_TMODE_CRCCK ((uint32_t)0x00080000U) /* Command CRC Check Enable */ +#define SDHOST_TMODE_RTYPESEL ((uint32_t)0x00030000U) /* Response Type Select */ +#define SDHOST_TMODE_RTYPESEL_0 ((uint32_t)0x00010000U) /* Response Type Select Bit0 */ +#define SDHOST_TMODE_RTYPESEL_1 ((uint32_t)0x00020000U) /* Response Type Select Bit1 */ +#define SDHOST_TMODE_BLKSEL ((uint32_t)0x00000020U) /* Multi / Single Block Select */ +#define SDHOST_TMODE_DATDIR ((uint32_t)0x00000010U) /* Data Transfer Direction Select */ +#define SDHOST_TMODE_AUTOCMDE ((uint32_t)0x0000000CU) /* Auto CMD Enable */ +#define SDHOST_TMODE_AUTOCMDE_0 ((uint32_t)0x00000004U) /* Auto CMD Enable Bit0 */ +#define SDHOST_TMODE_AUTOCMDE_1 ((uint32_t)0x00000008U) /* Auto CMD Enable Bit1 */ +#define SDHOST_TMODE_BLOCKCNTE ((uint32_t)0x00000002U) /* Block Count Enable */ +#define SDHOST_TMODE_DMAE ((uint32_t)0x00000001U) /* DMA Enable */ + +/** Bit definition for SDHOST_CMDRSP0 register **/ +#define SDHOST_CMDRSP0_RESP0 ((uint32_t)0xFFFFFFFFU) /* CMD response Bit[31:0] */ +/** Bit definition for SDHOST_CMDRSP1 register **/ +#define SDHOST_CMDRSP1_RESP1 ((uint32_t)0xFFFFFFFFU) /* CMD response Bit[63:32] */ +/** Bit definition for SDHOST_CMDRSP2 register **/ +#define SDHOST_CMDRSP2_RESP2 ((uint32_t)0xFFFFFFFFU) /* CMD response Bit[95:64] */ +/** Bit definition for SDHOST_CMDRSP3 register **/ +#define SDHOST_CMDRSP3_RESP3 ((uint32_t)0xFFFFFFFFU) /* CMD response Bit[127:96] */ + +/** Bit definition for SDHOST_BUFDAT register **/ +#define SDHOST_BUFDAT_DAT ((uint32_t)0xFFFFFFFFU) /* Data content Bits */ +#define SDHOST_BUFDAT_DAT_0 ((uint32_t)0x00000001U) /* Data content Bit0 */ +#define SDHOST_BUFDAT_DAT_1 ((uint32_t)0x00000002U) /* Data content Bit1 */ +#define SDHOST_BUFDAT_DAT_2 ((uint32_t)0x00000004U) /* Data content Bit2 */ +#define SDHOST_BUFDAT_DAT_3 ((uint32_t)0x00000008U) /* Data content Bit3 */ +#define SDHOST_BUFDAT_DAT_4 ((uint32_t)0x00000010U) /* Data content Bit4 */ +#define SDHOST_BUFDAT_DAT_5 ((uint32_t)0x00000020U) /* Data content Bit5 */ +#define SDHOST_BUFDAT_DAT_6 ((uint32_t)0x00000040U) /* Data content Bit6 */ +#define SDHOST_BUFDAT_DAT_7 ((uint32_t)0x00000080U) /* Data content Bit7 */ +#define SDHOST_BUFDAT_DAT_8 ((uint32_t)0x00000100U) /* Data content Bit8 */ +#define SDHOST_BUFDAT_DAT_9 ((uint32_t)0x00000200U) /* Data content Bit9 */ +#define SDHOST_BUFDAT_DAT_10 ((uint32_t)0x00000400U) /* Data content Bit10 */ +#define SDHOST_BUFDAT_DAT_11 ((uint32_t)0x00000800U) /* Data content Bit11 */ +#define SDHOST_BUFDAT_DAT_12 ((uint32_t)0x00001000U) /* Data content Bit12 */ +#define SDHOST_BUFDAT_DAT_13 ((uint32_t)0x00002000U) /* Data content Bit13 */ +#define SDHOST_BUFDAT_DAT_14 ((uint32_t)0x00004000U) /* Data content Bit14 */ +#define SDHOST_BUFDAT_DAT_15 ((uint32_t)0x00008000U) /* Data content Bit15 */ +#define SDHOST_BUFDAT_DAT_16 ((uint32_t)0x00010000U) /* Data content Bit16 */ +#define SDHOST_BUFDAT_DAT_17 ((uint32_t)0x00020000U) /* Data content Bit17 */ +#define SDHOST_BUFDAT_DAT_18 ((uint32_t)0x00040000U) /* Data content Bit18 */ +#define SDHOST_BUFDAT_DAT_19 ((uint32_t)0x00080000U) /* Data content Bit19 */ +#define SDHOST_BUFDAT_DAT_20 ((uint32_t)0x00100000U) /* Data content Bit20 */ +#define SDHOST_BUFDAT_DAT_21 ((uint32_t)0x00200000U) /* Data content Bit21 */ +#define SDHOST_BUFDAT_DAT_22 ((uint32_t)0x00400000U) /* Data content Bit22 */ +#define SDHOST_BUFDAT_DAT_23 ((uint32_t)0x00800000U) /* Data content Bit23 */ +#define SDHOST_BUFDAT_DAT_24 ((uint32_t)0x01000000U) /* Data content Bit24 */ +#define SDHOST_BUFDAT_DAT_25 ((uint32_t)0x02000000U) /* Data content Bit25 */ +#define SDHOST_BUFDAT_DAT_26 ((uint32_t)0x04000000U) /* Data content Bit26 */ +#define SDHOST_BUFDAT_DAT_27 ((uint32_t)0x08000000U) /* Data content Bit27 */ +#define SDHOST_BUFDAT_DAT_28 ((uint32_t)0x10000000U) /* Data content Bit28 */ +#define SDHOST_BUFDAT_DAT_29 ((uint32_t)0x20000000U) /* Data content Bit29 */ +#define SDHOST_BUFDAT_DAT_30 ((uint32_t)0x40000000U) /* Data content Bit30 */ +#define SDHOST_BUFDAT_DAT_31 ((uint32_t)0x80000000U) /* Data content Bit31 */ + +/** Bit definition for SDHOST_PRESTS register **/ +#define SDHOST_PRESTS_DATLH ((uint32_t)0x1E000000U) /* DAT[7:4] Line Signal Level */ +#define SDHOST_PRESTS_DATLH_0 ((uint32_t)0x02000000U) /* DAT[4] Line Signal Level */ +#define SDHOST_PRESTS_DATLH_1 ((uint32_t)0x04000000U) /* DAT[5] Line Signal Level */ +#define SDHOST_PRESTS_DATLH_2 ((uint32_t)0x08000000U) /* DAT[6] Line Signal Level */ +#define SDHOST_PRESTS_DATLH_3 ((uint32_t)0x10000000U) /* DAT[7] Line Signal Level */ +#define SDHOST_PRESTS_CMDL ((uint32_t)0x01000000U) /* CMD Line Signal Level */ +#define SDHOST_PRESTS_DATLL ((uint32_t)0x00F00000U) /* DAT[3:0] Line Signal Level */ +#define SDHOST_PRESTS_DATLL_0 ((uint32_t)0x00100000U) /* DAT[0] Line Signal Level */ +#define SDHOST_PRESTS_DATLL_1 ((uint32_t)0x00200000U) /* DAT[1] Line Signal Level */ +#define SDHOST_PRESTS_DATLL_2 ((uint32_t)0x00400000U) /* DAT[2] Line Signal Level */ +#define SDHOST_PRESTS_DATLL_3 ((uint32_t)0x00800000U) /* DAT[3] Line Signal Level */ +#define SDHOST_PRESTS_SDWPL ((uint32_t)0x00080000U) /* Write Protect Switch Pin Level */ +#define SDHOST_PRESTS_SDCDL ((uint32_t)0x00040000U) /* Card Detect Pin Level */ +#define SDHOST_PRESTS_CSTSL ((uint32_t)0x00020000U) /* Card State Stable */ +#define SDHOST_PRESTS_CINS ((uint32_t)0x00010000U) /* Card Inserted */ +#define SDHOST_PRESTS_BUFR ((uint32_t)0x00000800U) /* Buffer Read Enable */ +#define SDHOST_PRESTS_BUFW ((uint32_t)0x00000400U) /* Buffer Write Enable */ +#define SDHOST_PRESTS_RTRANACT ((uint32_t)0x00000200U) /* Read Transfer Active */ +#define SDHOST_PRESTS_WTRANACT ((uint32_t)0x00000100U) /* Write Transfer Active */ +#define SDHOST_PRESTS_RETUNREQ ((uint32_t)0x00000008U) /* Re-Tuning Request */ +#define SDHOST_PRESTS_DLACT ((uint32_t)0x00000004U) /* DAT Line Active */ +#define SDHOST_PRESTS_CMDINHD ((uint32_t)0x00000002U) /* Command Inhibit (DAT) */ +#define SDHOST_PRESTS_CMDINHC ((uint32_t)0x00000001U) /* Command Inhibit (CMD) */ + +/** Bit definition for SDHOST_CTRL1 register **/ +#define SDHOST_CTRL1_RMVWKUP ((uint32_t)0x04000000U) /* Wakeup Event Enable On SD Card Removal */ +#define SDHOST_CTRL1_INSTWKUP ((uint32_t)0x02000000U) /* Wakeup Event Enable On SD Card Insertion */ +#define SDHOST_CTRL1_INTWKUP ((uint32_t)0x01000000U) /* Wakeup Event Enable On Card Interrupt */ +#define SDHOST_CTRL1_BOOTACKC ((uint32_t)0x00800000U) /* Boot Ack Check */ +#define SDHOST_CTRL1_BOOTINALT ((uint32_t)0x00400000U) /* To start boot code access in alternative mode */ +#define SDHOST_CTRL1_BOOTEN ((uint32_t)0x00200000U) /* To start boot code access */ +#define SDHOST_CTRL1_SPIMODE ((uint32_t)0x00100000U) /* SPI mode enable */ +#define SDHOST_CTRL1_INTATBG ((uint32_t)0x00080000U) /* Interrupt At Block Gap */ +#define SDHOST_CTRL1_RWAITCTRL ((uint32_t)0x00040000U) /* Read Wait Control */ +#define SDHOST_CTRL1_CONTREQ ((uint32_t)0x00020000U) /* Continue Request */ +#define SDHOST_CTRL1_SABGREQ ((uint32_t)0x00010000U) /* Stop At Block Gap Request */ +#define SDHOST_CTRL1_HWRST ((uint32_t)0x00001000U) /* Hardware reset */ +#define SDHOST_CTRL1_SDBVSEL ((uint32_t)0x00000E00U) /* SD Bus Voltage Select */ +#define SDHOST_CTRL1_SDPWR ((uint32_t)0x00000100U) /* SD Bus Power */ +#define SDHOST_CTRL1_CDSD ((uint32_t)0x00000080U) /* Card detect signal detection */ +#define SDHOST_CTRL1_CDTL ((uint32_t)0x00000040U) /* Card Detect Test Level */ +#define SDHOST_CTRL1_EDTWIDTH ((uint32_t)0x00000020U) /* Extended Data Transfer Width */ +#define SDHOST_CTRL1_DMASEL ((uint32_t)0x00000018U) /* DMA Select */ +#define SDHOST_CTRL1_DMASEL_0 ((uint32_t)0x00000008U) /* DMA Select Bit0 */ +#define SDHOST_CTRL1_DMASEL_1 ((uint32_t)0x00000010U) /* DMA Select Bit1 */ +#define SDHOST_CTRL1_HSEN ((uint32_t)0x00000004U) /* High Speed Enable */ +#define SDHOST_CTRL1_DTWIDTH ((uint32_t)0x00000002U) /* Data Transfer Width */ +#define SDHOST_CTRL1_LEDCTRL ((uint32_t)0x00000001U) /* LED Control */ + +/** Bit definition for SDHOST_CTRL2 register **/ +#define SDHOST_CTRL2_SWRSTDL ((uint32_t)0x04000000U) /* Software Reset for DAT Line */ +#define SDHOST_CTRL2_SWRSTCL ((uint32_t)0x02000000U) /* Software Reset for CMD Line */ +#define SDHOST_CTRL2_SWRSTALL ((uint32_t)0x01000000U) /* Software Reset for All */ +#define SDHOST_CTRL2_DTCNT ((uint32_t)0x000F0000U) /* Data Timeout Counter Value */ +#define SDHOST_CTRL2_DTCNT_0 ((uint32_t)0x00010000U) /* Data Timeout Counter Value Bit0 */ +#define SDHOST_CTRL2_DTCNT_1 ((uint32_t)0x00020000U) /* Data Timeout Counter Value Bit1 */ +#define SDHOST_CTRL2_DTCNT_2 ((uint32_t)0x00040000U) /* Data Timeout Counter Value Bit2 */ +#define SDHOST_CTRL2_DTCNT_3 ((uint32_t)0x00080000U) /* Data Timeout Counter Value Bit3 */ +#define SDHOST_CTRL2_SDCLKSEL ((uint32_t)0x0000FFC0U) /* SDCLK Frequency Select */ +#define SDHOST_CTRL2_SDCLKSEL_0 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Bit0 */ +#define SDHOST_CTRL2_SDCLKSEL_1 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Bit1 */ +#define SDHOST_CTRL2_SDCLKSEL_2 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Bit2 */ +#define SDHOST_CTRL2_SDCLKSEL_3 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Bit3 */ +#define SDHOST_CTRL2_SDCLKSEL_4 ((uint32_t)0x00000400U) /* SDCLK Frequency Select Bit4 */ +#define SDHOST_CTRL2_SDCLKSEL_5 ((uint32_t)0x00000800U) /* SDCLK Frequency Select Bit5 */ +#define SDHOST_CTRL2_SDCLKSEL_6 ((uint32_t)0x00001000U) /* SDCLK Frequency Select Bit6 */ +#define SDHOST_CTRL2_SDCLKSEL_7 ((uint32_t)0x00002000U) /* SDCLK Frequency Select Bit7 */ +#define SDHOST_CTRL2_SDCLKSEL_8 ((uint32_t)0x00004000U) /* SDCLK Frequency Select Bit8 */ +#define SDHOST_CTRL2_SDCLKSEL_9 ((uint32_t)0x00008000U) /* SDCLK Frequency Select Bit9 */ +#define SDHOST_CTRL2_SDCLKE ((uint32_t)0x00000004U) /* SD Clock Enable */ +#define SDHOST_CTRL2_INCLKSTS ((uint32_t)0x00000002U) /* Internal Clock Stable */ +#define SDHOST_CTRL2_INCLKE ((uint32_t)0x00000001U) /* Internal Clock Enable */ + +/** Bit definition for SDHOST_INTSTS register **/ +#define SDHOST_INTSTS_TRGRERR ((uint32_t)0x10000000U) /* Target Response error */ +#define SDHOST_INTSTS_ADMAERR ((uint32_t)0x02000000U) /* ADMA Error */ +#define SDHOST_INTSTS_ACMDERR ((uint32_t)0x01000000U) /* Auto CMD Error */ +#define SDHOST_INTSTS_DENDERR ((uint32_t)0x00400000U) /* Data End Bit Error */ +#define SDHOST_INTSTS_DCRCERR ((uint32_t)0x00200000U) /* Data CRC Error */ +#define SDHOST_INTSTS_DTERR ((uint32_t)0x00100000U) /* Data Timeout Error */ +#define SDHOST_INTSTS_CINXERR ((uint32_t)0x00080000U) /* Command Index Error */ +#define SDHOST_INTSTS_CENDBERR ((uint32_t)0x00040000U) /* Command End Bit Error */ +#define SDHOST_INTSTS_CCRCERR ((uint32_t)0x00020000U) /* Command CRC Error */ +#define SDHOST_INTSTS_CTERR ((uint32_t)0x00010000U) /* Command Timeout Error */ +#define SDHOST_INTSTS_ALLERR ((uint32_t)0x00008000U) /* Error Interrupt */ +#define SDHOST_INTSTS_BOOTTER ((uint32_t)0x00004000U) /* Boot terminate Interrupt */ +#define SDHOST_INTSTS_BOOTACKR ((uint32_t)0x00002000U) /* Boot ack rcv */ +#define SDHOST_INTSTS_RETUNE ((uint32_t)0x00001000U) /* Re-Tuning Event */ +#define SDHOST_INTSTS_CINT ((uint32_t)0x00000100U) /* Card Interrupt */ +#define SDHOST_INTSTS_CRMV ((uint32_t)0x00000080U) /* Card Removal */ +#define SDHOST_INTSTS_CINS ((uint32_t)0x00000040U) /* Card Insertion */ +#define SDHOST_INTSTS_BUFRRDY ((uint32_t)0x00000020U) /* Buffer Read Ready */ +#define SDHOST_INTSTS_BUFWRDY ((uint32_t)0x00000010U) /* Buffer Write Ready */ +#define SDHOST_INTSTS_DMAINT ((uint32_t)0x00000008U) /* DMA Interrupt */ +#define SDHOST_INTSTS_BLKGAPE ((uint32_t)0x00000004U) /* Block Gap Event */ +#define SDHOST_INTSTS_TC ((uint32_t)0x00000002U) /* Transfer Complete */ +#define SDHOST_INTSTS_CMDC ((uint32_t)0x00000001U) /* Command Complete */ + +/** Bit definition for SDHOST_IE register **/ +#define SDHOST_IE_TRGREE ((uint32_t)0x10000000U) /* Target Response Error /Host Error Status Enable */ +#define SDHOST_IE_ADMAEE ((uint32_t)0x02000000U) /* ADMA Error Status Enable */ +#define SDHOST_IE_ACMDEE ((uint32_t)0x01000000U) /* Auto CMD12 Error Status Enable */ +#define SDHOST_IE_DENDEE ((uint32_t)0x00400000U) /* Data End Bit Error Status Enable */ +#define SDHOST_IE_DCRCEE ((uint32_t)0x00200000U) /* Data CRC Error Status Enable */ +#define SDHOST_IE_DTEE ((uint32_t)0x00100000U) /* Data Timeout Error Status Enable */ +#define SDHOST_IE_CINXEE ((uint32_t)0x00080000U) /* Command Index Error Status Enable */ +#define SDHOST_IE_CENDBEE ((uint32_t)0x00040000U) /* Command End Bit Error Status Enable */ +#define SDHOST_IE_CCRCEE ((uint32_t)0x00020000U) /* Command CRC Error Status Enable */ +#define SDHOST_IE_CTEE ((uint32_t)0x00010000U) /* Command Timeout Error Status Enable */ +#define SDHOST_IE_BOOTTIE ((uint32_t)0x00004000U) /* Boot terminate Interrupt enable */ +#define SDHOST_IE_BOOTACKRE ((uint32_t)0x00002000U) /* Boot ack rcv enable */ +#define SDHOST_IE_RTUNE ((uint32_t)0x00001000U) /* Re-Tuning Event Status Enable */ +#define SDHOST_IE_CINTE ((uint32_t)0x00000100U) /* Card Interrupt Status Enable */ +#define SDHOST_IE_CRMVE ((uint32_t)0x00000080U) /* Card Removal Status Enable */ +#define SDHOST_IE_CINSE ((uint32_t)0x00000040U) /* Card Insertion Status Enable */ +#define SDHOST_IE_BUFRRDYE ((uint32_t)0x00000020U) /* Buffer Read Ready Status Enable */ +#define SDHOST_IE_BUFWRDYE ((uint32_t)0x00000010U) /* Buffer Write Ready Status Enable */ +#define SDHOST_IE_DMAINTE ((uint32_t)0x00000008U) /* DMA Interrupt Status Enable */ +#define SDHOST_IE_BLKGAPEE ((uint32_t)0x00000004U) /* Block Gap Event Status Enable */ +#define SDHOST_IE_TCE ((uint32_t)0x00000002U) /* Transfer Complete Status Enable */ +#define SDHOST_IE_CMDCE ((uint32_t)0x00000001U) /* Command Complete Status Enable */ + +/** Bit definition for SDHOST_ISE register **/ +#define SDHOST_ISE_TRGRESE ((uint32_t)0x10000000U) /* Target Response Error /Host Error Signal Enable */ +#define SDHOST_ISE_ADMAESE ((uint32_t)0x02000000U) /* ADMA Error Signal Enable */ +#define SDHOST_ISE_ACMDESE ((uint32_t)0x01000000U) /* Auto CMD12 Error Signal Enable */ +#define SDHOST_ISE_DENDESE ((uint32_t)0x00400000U) /* Data End Bit Error Signal Enable */ +#define SDHOST_ISE_DCRCESE ((uint32_t)0x00200000U) /* Data CRC Error Signal Enable */ +#define SDHOST_ISE_DTESE ((uint32_t)0x00100000U) /* Data Timeout Error Signal Enable */ +#define SDHOST_ISE_CINXESE ((uint32_t)0x00080000U) /* Command Index Error Signal Enable */ +#define SDHOST_ISE_CENDBESE ((uint32_t)0x00040000U) /* Command End Bit Error Signal Enable */ +#define SDHOST_ISE_CCRCESE ((uint32_t)0x00020000U) /* Command CRC Error Signal Enable */ +#define SDHOST_ISE_CTESE ((uint32_t)0x00010000U) /* Command Timeout Error Signal Enable */ +#define SDHOST_ISE_BOOTTISE ((uint32_t)0x00004000U) /* Boot terminate Interrupt signal enable */ +#define SDHOST_ISE_BOOTACKRSE ((uint32_t)0x00002000U) /* Boot ack rcv signal enable */ +#define SDHOST_ISE_RTUNSE ((uint32_t)0x00001000U) /* Re-Tuning Event signal Enable */ +#define SDHOST_ISE_CINTSE ((uint32_t)0x00000100U) /* Card Interrupt Signal Enable */ +#define SDHOST_ISE_CRMVSE ((uint32_t)0x00000080U) /* Card Removal Signal Enable */ +#define SDHOST_ISE_CINSSE ((uint32_t)0x00000040U) /* Card Insertion Signal Enable */ +#define SDHOST_ISE_BUFRRDYSE ((uint32_t)0x00000020U) /* Buffer Read Ready Signal Enable */ +#define SDHOST_ISE_BUFWRDYSE ((uint32_t)0x00000010U) /* Buffer Write Ready Signal Enable */ +#define SDHOST_ISE_DMAINTSE ((uint32_t)0x00000008U) /* DMA Interrupt Signal Enable */ +#define SDHOST_ISE_BLKGAPESE ((uint32_t)0x00000004U) /* Block Gap Event Signal Enable */ +#define SDHOST_ISE_TCSE ((uint32_t)0x00000002U) /* Transfer Complete Signal Enable */ +#define SDHOST_ISE_CMDCSE ((uint32_t)0x00000001U) /* Command Complete Signal Enable */ + +/** Bit definition for SDHOST_CTRLSTS register **/ +#define SDHOST_CTRLSTS_PREVE ((uint32_t)0x80000000U) /* Preset Value Enable */ +#define SDHOST_CTRLSTS_ASYNCIE ((uint32_t)0x40000000U) /* Asynchronous Interrupt Enable */ +#define SDHOST_CTRLSTS_SCS ((uint32_t)0x00800000U) /* Sampling Clock Select */ +#define SDHOST_CTRLSTS_ETUN ((uint32_t)0x00400000U) /* Execute Tuning */ +#define SDHOST_CTRLSTS_V18SE ((uint32_t)0x00080000U) /* 1.8V Signaling Enable */ +#define SDHOST_CTRLSTS_UHSMOD ((uint32_t)0x00070000U) /* UHS Mode Select */ +#define SDHOST_CTRLSTS_UHSMOD_0 ((uint32_t)0x00010000U) /* UHS Mode Select Bit0 */ +#define SDHOST_CTRLSTS_UHSMOD_1 ((uint32_t)0x00020000U) /* UHS Mode Select Bit1 */ +#define SDHOST_CTRLSTS_UHSMOD_2 ((uint32_t)0x00040000U) /* UHS Mode Select Bit2 */ +#define SDHOST_CTRLSTS_ACMD12E ((uint32_t)0x00000080U) /* Auto CMD12 Enable */ +#define SDHOST_CTRLSTS_ACMDINXE ((uint32_t)0x00000010U) /* Auto CMD Index Error */ +#define SDHOST_CTRLSTS_ACMDEBE ((uint32_t)0x00000008U) /* Auto CMD End Bit Error */ +#define SDHOST_CTRLSTS_ACMDCRCE ((uint32_t)0x00000004U) /* Auto CMD CRC Error */ +#define SDHOST_CTRLSTS_ACMDTE ((uint32_t)0x00000002U) /* Auto CMD Timeout Error */ +#define SDHOST_CTRLSTS_ACMD12NE ((uint32_t)0x00000001U) /* Auto CMD12 not Executed */ + +/** Bit definition for SDHOST_CAP0STS register **/ +#define SDHOST_CAP0STS_STYP ((uint32_t)0xC0000000U) /* Slot Type */ +#define SDHOST_CAP0STS_STYP_0 ((uint32_t)0x40000000U) /* Slot Type bit0 */ +#define SDHOST_CAP0STS_STYP_1 ((uint32_t)0x80000000U) /* Slot Type bit1 */ +#define SDHOST_CAP0STS_ASYNCINT ((uint32_t)0x20000000U) /* Asynchronous Interrupt Support */ +#define SDHOST_CAP0STS_VS33 ((uint32_t)0x01000000U) /* Voltage Support 3.3V */ +#define SDHOST_CAP0STS_SRS ((uint32_t)0x00800000U) /* Suspend / Resume Support */ +#define SDHOST_CAP0STS_SDMA ((uint32_t)0x00400000U) /* SDMA Support */ +#define SDHOST_CAP0STS_HS ((uint32_t)0x00200000U) /* High Speed Support */ +#define SDHOST_CAP0STS_ADMA2 ((uint32_t)0x00080000U) /* ADMA2 */ +#define SDHOST_CAP0STS_EMBUS ((uint32_t)0x00040000U) /* Extended Media Bus Support */ +#define SDHOST_CAP0STS_MBL ((uint32_t)0x00030000U) /* Max Block Length */ +#define SDHOST_CAP0STS_MBL_0 ((uint32_t)0x00010000U) /* Max Block Length Bit0 */ +#define SDHOST_CAP0STS_MBL_1 ((uint32_t)0x00020000U) /* Max Block Length Bit1 */ +#define SDHOST_CAP0STS_BCLKF ((uint32_t)0x0000FF00U) /* Base Clock Frequency for SD Clock */ +#define SDHOST_CAP0STS_BCLKF_0 ((uint32_t)0x00000100U) /* Base Clock Frequency for SD Clock Bit0 */ +#define SDHOST_CAP0STS_BCLKF_1 ((uint32_t)0x00000200U) /* Base Clock Frequency for SD Clock Bit1 */ +#define SDHOST_CAP0STS_BCLKF_2 ((uint32_t)0x00000400U) /* Base Clock Frequency for SD Clock Bit2 */ +#define SDHOST_CAP0STS_BCLKF_3 ((uint32_t)0x00000800U) /* Base Clock Frequency for SD Clock Bit3 */ +#define SDHOST_CAP0STS_BCLKF_4 ((uint32_t)0x00001000U) /* Base Clock Frequency for SD Clock Bit4 */ +#define SDHOST_CAP0STS_BCLKF_5 ((uint32_t)0x00002000U) /* Base Clock Frequency for SD Clock Bit5 */ +#define SDHOST_CAP0STS_BCLKF_6 ((uint32_t)0x00004000U) /* Base Clock Frequency for SD Clock Bit6 */ +#define SDHOST_CAP0STS_BCLKF_7 ((uint32_t)0x00008000U) /* Base Clock Frequency for SD Clock Bit7 */ +#define SDHOST_CAP0STS_TCLKU ((uint32_t)0x00000080U) /* Timeout Clock Unit */ + +/** Bit definition for SDHOST_CAP1STS register **/ +#define SDHOST_CAP1STS_SPIBMOD ((uint32_t)0x02000000U) /* SPI block mode */ +#define SDHOST_CAP1STS_SPIMOD ((uint32_t)0x01000000U) /* SPI mode */ +#define SDHOST_CAP1STS_UTFSDR50 ((uint32_t)0x00002000U) /* Use Tuning for SDR50 */ +#define SDHOST_CAP1STS_RTTIMCNT ((uint32_t)0x00000F00U) /* Timer Count for Re-Tuning */ +#define SDHOST_CAP1STS_RTTIMCNT_0 ((uint32_t)0x00000100U) /* Timer Count for Re-Tuning Bit0 */ +#define SDHOST_CAP1STS_RTTIMCNT_1 ((uint32_t)0x00000200U) /* Timer Count for Re-Tuning Bit1 */ +#define SDHOST_CAP1STS_RTTIMCNT_2 ((uint32_t)0x00000400U) /* Timer Count for Re-Tuning Bit2 */ +#define SDHOST_CAP1STS_RTTIMCNT_3 ((uint32_t)0x00000800U) /* Timer Count for Re-Tuning Bit3 */ +#define SDHOST_CAP1STS_DDR50 ((uint32_t)0x00000004U) /* DDR50 Support */ +#define SDHOST_CAP1STS_SDR104 ((uint32_t)0x00000002U) /* SDR104 Support */ +#define SDHOST_CAP1STS_SDR50 ((uint32_t)0x00000001U) /* SDR50 Support */ + +/** Bit definition for SDHOST_STSFE register **/ +#define SDHOST_STSFE_ADMAE ((uint32_t)0x02000000U) /* Force Event for ADMA Error */ +#define SDHOST_STSFE_ACMDE ((uint32_t)0x01000000U) /* Force Event for Auto CMD Error */ +#define SDHOST_STSFE_DEBE ((uint32_t)0x00400000U) /* Force Event for Data End Bit Error */ +#define SDHOST_STSFE_DCRCE ((uint32_t)0x00200000U) /* Force Event for Data CRC Error */ +#define SDHOST_STSFE_DTE ((uint32_t)0x00100000U) /* Force Event for Data Timeout Error */ +#define SDHOST_STSFE_CINXE ((uint32_t)0x00080000U) /* Force Event for Command Index Error */ +#define SDHOST_STSFE_CEBE ((uint32_t)0x00040000U) /* Force Event for Command End Bit Error */ +#define SDHOST_STSFE_CCRCE ((uint32_t)0x00020000U) /* Force Event for Command CRC Error */ +#define SDHOST_STSFE_CTE ((uint32_t)0x00010000U) /* Force Event for Command Timeout Error */ +#define SDHOST_STSFE_ACMD12E ((uint32_t)0x00000080U) /* Force Event for command not issued by Auto CMD12 Error */ +#define SDHOST_STSFE_ACMDINXE ((uint32_t)0x00000010U) /* Force Event for Auto CMD Index Error */ +#define SDHOST_STSFE_ACMDEBE ((uint32_t)0x00000008U) /* Force Event for Auto CMD End bit Error */ +#define SDHOST_STSFE_ACMDCRCE ((uint32_t)0x00000004U) /* Force Event for Auto CMD CRC Error */ +#define SDHOST_STSFE_ACMDTE ((uint32_t)0x00000002U) /* Force Event for Auto CMD timeout Error */ +#define SDHOST_STSFE_ACMD12NE ((uint32_t)0x00000001U) /* Force Event for Auto CMD12 NOT Executed */ + +/** Bit definition for SDHOST_ADMAESTS register **/ +#define SDHOST_ADMAESTS_ADMALME ((uint32_t)0x00000004U) /* ADMA Length Mismatch Error */ +#define SDHOST_ADMAESTS_ADMAE ((uint32_t)0x00000003U) /* ADMA Error State */ +#define SDHOST_ADMAESTS_ADMAE_0 ((uint32_t)0x00000001U) /* ADMA Error State Bit0 */ +#define SDHOST_ADMAESTS_ADMAE_1 ((uint32_t)0x00000002U) /* ADMA Error State Bit1 */ + +/** Bit definition for SDHOST_ASADD0 register **/ +#define SDHOST_ASADD0_ADD0 ((uint32_t)0xFFFFFFFFU) /* ADMA System Address Bit[31:0] */ +/** Bit definition for SDHOST_ASADD1 register **/ +#define SDHOST_ASADD1_ADD1 ((uint32_t)0xFFFFFFFFU) /* ADMA System Address Bit[63:32] */ + +/** Bit definition for SDHOST_PV0STS register **/ +#define SDHOST_PV0STS_CLKFS_DS ((uint32_t)0x03FF0000U) /* SDCLK Frequency Select Value for Default Speed */ +#define SDHOST_PV0STS_CLKFS_DS_0 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for Default Speed Bit0 */ +#define SDHOST_PV0STS_CLKFS_DS_1 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for Default Speed Bit1 */ +#define SDHOST_PV0STS_CLKFS_DS_2 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for Default Speed Bit2 */ +#define SDHOST_PV0STS_CLKFS_DS_3 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for Default Speed Bit3 */ +#define SDHOST_PV0STS_CLKFS_DS_4 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for Default Speed Bit4 */ +#define SDHOST_PV0STS_CLKFS_DS_5 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for Default Speed Bit5 */ +#define SDHOST_PV0STS_CLKFS_DS_6 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for Default Speed Bit6 */ +#define SDHOST_PV0STS_CLKFS_DS_7 ((uint32_t)0x00800000U) /* SDCLK Frequency Select Value for Default Speed Bit7 */ +#define SDHOST_PV0STS_CLKFS_DS_8 ((uint32_t)0x01000000U) /* SDCLK Frequency Select Value for Default Speed Bit8 */ +#define SDHOST_PV0STS_CLKFS_DS_9 ((uint32_t)0x02000000U) /* SDCLK Frequency Select Value for Default Speed Bit9 */ +#define SDHOST_PV0STS_CLKFS_INIT ((uint32_t)0x000003FFU) /* SDCLK Frequency Select Value for Initialization */ +#define SDHOST_PV0STS_CLKFS_INIT_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for Initialization Bit0 */ +#define SDHOST_PV0STS_CLKFS_INIT_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for Initialization Bit1 */ +#define SDHOST_PV0STS_CLKFS_INIT_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for Initialization Bit2 */ +#define SDHOST_PV0STS_CLKFS_INIT_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for Initialization Bit3 */ +#define SDHOST_PV0STS_CLKFS_INIT_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for Initialization Bit4 */ +#define SDHOST_PV0STS_CLKFS_INIT_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for Initialization Bit5 */ +#define SDHOST_PV0STS_CLKFS_INIT_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for Initialization Bit6 */ +#define SDHOST_PV0STS_CLKFS_INIT_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for Initialization Bit7 */ +#define SDHOST_PV0STS_CLKFS_INIT_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for Initialization Bit8 */ +#define SDHOST_PV0STS_CLKFS_INIT_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for Initialization Bit9 */ + +/** Bit definition for SDHOST_PV1STS register **/ +#define SDHOST_PV1STS_CLKFS_SDR12 ((uint32_t)0x03FF0000U) /* SDCLK Frequency Select Value for SDR12 */ +#define SDHOST_PV1STS_CLKFS_SDR12_0 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for SDR12 Bit0 */ +#define SDHOST_PV1STS_CLKFS_SDR12_1 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for SDR12 Bit1 */ +#define SDHOST_PV1STS_CLKFS_SDR12_2 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for SDR12 Bit2 */ +#define SDHOST_PV1STS_CLKFS_SDR12_3 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for SDR12 Bit3 */ +#define SDHOST_PV1STS_CLKFS_SDR12_4 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for SDR12 Bit4 */ +#define SDHOST_PV1STS_CLKFS_SDR12_5 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for SDR12 Bit5 */ +#define SDHOST_PV1STS_CLKFS_SDR12_6 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for SDR12 Bit6 */ +#define SDHOST_PV1STS_CLKFS_SDR12_7 ((uint32_t)0x00800000U) /* SDCLK Frequency Select Value for SDR12 Bit7 */ +#define SDHOST_PV1STS_CLKFS_SDR12_8 ((uint32_t)0x01000000U) /* SDCLK Frequency Select Value for SDR12 Bit8 */ +#define SDHOST_PV1STS_CLKFS_SDR12_9 ((uint32_t)0x02000000U) /* SDCLK Frequency Select Value for SDR12 Bit9 */ +#define SDHOST_PV1STS_CLKFS_HS ((uint32_t)0x000003FFU) /* SDCLK Frequency Select Value for High Speed */ +#define SDHOST_PV1STS_CLKFS_HS_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for High Speed Bit0 */ +#define SDHOST_PV1STS_CLKFS_HS_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for High Speed Bit1 */ +#define SDHOST_PV1STS_CLKFS_HS_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for High Speed Bit2 */ +#define SDHOST_PV1STS_CLKFS_HS_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for High Speed Bit3 */ +#define SDHOST_PV1STS_CLKFS_HS_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for High Speed Bit4 */ +#define SDHOST_PV1STS_CLKFS_HS_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for High Speed Bit5 */ +#define SDHOST_PV1STS_CLKFS_HS_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for High Speed Bit6 */ +#define SDHOST_PV1STS_CLKFS_HS_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for High Speed Bit7 */ +#define SDHOST_PV1STS_CLKFS_HS_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for High Speed Bit8 */ +#define SDHOST_PV1STS_CLKFS_HS_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for High Speed Bit9 */ + +/** Bit definition for SDHOST_PV2STS register **/ +#define SDHOST_PV2STS_CLKFS_SDR50 ((uint32_t)0x03FF0000U) /* SDCLK Frequency Select Value for SDR50 */ +#define SDHOST_PV2STS_CLKFS_SDR50_0 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for SDR50 Bit0 */ +#define SDHOST_PV2STS_CLKFS_SDR50_1 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for SDR50 Bit1 */ +#define SDHOST_PV2STS_CLKFS_SDR50_2 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for SDR50 Bit2 */ +#define SDHOST_PV2STS_CLKFS_SDR50_3 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for SDR50 Bit3 */ +#define SDHOST_PV2STS_CLKFS_SDR50_4 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for SDR50 Bit4 */ +#define SDHOST_PV2STS_CLKFS_SDR50_5 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for SDR50 Bit5 */ +#define SDHOST_PV2STS_CLKFS_SDR50_6 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for SDR50 Bit6 */ +#define SDHOST_PV2STS_CLKFS_SDR50_7 ((uint32_t)0x00800000U) /* SDCLK Frequency Select Value for SDR50 Bit7 */ +#define SDHOST_PV2STS_CLKFS_SDR50_8 ((uint32_t)0x01000000U) /* SDCLK Frequency Select Value for SDR50 Bit8 */ +#define SDHOST_PV2STS_CLKFS_SDR50_9 ((uint32_t)0x02000000U) /* SDCLK Frequency Select Value for SDR50 Bit9 */ +#define SDHOST_PV2STS_CLKFS_SDR25 ((uint32_t)0x000003FFU) /* SDCLK Frequency Select Value for SDR25 */ +#define SDHOST_PV2STS_CLKFS_SDR25_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for SDR25 Bit0 */ +#define SDHOST_PV2STS_CLKFS_SDR25_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for SDR25 Bit1 */ +#define SDHOST_PV2STS_CLKFS_SDR25_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for SDR25 Bit2 */ +#define SDHOST_PV2STS_CLKFS_SDR25_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for SDR25 Bit3 */ +#define SDHOST_PV2STS_CLKFS_SDR25_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for SDR25 Bit4 */ +#define SDHOST_PV2STS_CLKFS_SDR25_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for SDR25 Bit5 */ +#define SDHOST_PV2STS_CLKFS_SDR25_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for SDR25 Bit6 */ +#define SDHOST_PV2STS_CLKFS_SDR25_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for SDR25 Bit7 */ +#define SDHOST_PV2STS_CLKFS_SDR25_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for SDR25 Bit8 */ +#define SDHOST_PV2STS_CLKFS_SDR25_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for SDR25 Bit9 */ + +/** Bit definition for SDHOST_PV3STS register **/ +#define SDHOST_PV3STS_CLKFS_DDR50 ((uint32_t)0x03FF0000U) /* SDCLK Frequency Select Value for DDR50 */ +#define SDHOST_PV3STS_CLKFS_DDR50_0 ((uint32_t)0x00010000U) /* SDCLK Frequency Select Value for DDR50 Bit0 */ +#define SDHOST_PV3STS_CLKFS_DDR50_1 ((uint32_t)0x00020000U) /* SDCLK Frequency Select Value for DDR50 Bit1 */ +#define SDHOST_PV3STS_CLKFS_DDR50_2 ((uint32_t)0x00040000U) /* SDCLK Frequency Select Value for DDR50 Bit2 */ +#define SDHOST_PV3STS_CLKFS_DDR50_3 ((uint32_t)0x00080000U) /* SDCLK Frequency Select Value for DDR50 Bit3 */ +#define SDHOST_PV3STS_CLKFS_DDR50_4 ((uint32_t)0x00100000U) /* SDCLK Frequency Select Value for DDR50 Bit4 */ +#define SDHOST_PV3STS_CLKFS_DDR50_5 ((uint32_t)0x00200000U) /* SDCLK Frequency Select Value for DDR50 Bit5 */ +#define SDHOST_PV3STS_CLKFS_DDR50_6 ((uint32_t)0x00400000U) /* SDCLK Frequency Select Value for DDR50 Bit6 */ +#define SDHOST_PV3STS_CLKFS_DDR50_7 ((uint32_t)0x00800000U) /* SDCLK Frequency Select Value for DDR50 Bit7 */ +#define SDHOST_PV3STS_CLKFS_DDR50_8 ((uint32_t)0x01000000U) /* SDCLK Frequency Select Value for DDR50 Bit8 */ +#define SDHOST_PV3STS_CLKFS_DDR50_9 ((uint32_t)0x02000000U) /* SDCLK Frequency Select Value for DDR50 Bit9 */ +#define SDHOST_PV3STS_CLKFS_SDR104 ((uint32_t)0x000003FFU) /* SDCLK Frequency Select Value for SDR104 */ +#define SDHOST_PV3STS_CLKFS_SDR104_0 ((uint32_t)0x00000001U) /* SDCLK Frequency Select Value for SDR104 Bit0 */ +#define SDHOST_PV3STS_CLKFS_SDR104_1 ((uint32_t)0x00000002U) /* SDCLK Frequency Select Value for SDR104 Bit1 */ +#define SDHOST_PV3STS_CLKFS_SDR104_2 ((uint32_t)0x00000004U) /* SDCLK Frequency Select Value for SDR104 Bit2 */ +#define SDHOST_PV3STS_CLKFS_SDR104_3 ((uint32_t)0x00000008U) /* SDCLK Frequency Select Value for SDR104 Bit3 */ +#define SDHOST_PV3STS_CLKFS_SDR104_4 ((uint32_t)0x00000010U) /* SDCLK Frequency Select Value for SDR104 Bit4 */ +#define SDHOST_PV3STS_CLKFS_SDR104_5 ((uint32_t)0x00000020U) /* SDCLK Frequency Select Value for SDR104 Bit5 */ +#define SDHOST_PV3STS_CLKFS_SDR104_6 ((uint32_t)0x00000040U) /* SDCLK Frequency Select Value for SDR104 Bit6 */ +#define SDHOST_PV3STS_CLKFS_SDR104_7 ((uint32_t)0x00000080U) /* SDCLK Frequency Select Value for SDR104 Bit7 */ +#define SDHOST_PV3STS_CLKFS_SDR104_8 ((uint32_t)0x00000100U) /* SDCLK Frequency Select Value for SDR104 Bit8 */ +#define SDHOST_PV3STS_CLKFS_SDR104_9 ((uint32_t)0x00000200U) /* SDCLK Frequency Select Value for SDR104 Bit9 */ + +/** Bit definition for SDHOST_BOOTTCTRL register **/ +#define SDHOST_BOOTTCTRL_CNT ((uint32_t)0xFFFFFFFFU) /* Boot Data Timeout Counter Value */ +#define SDHOST_BOOTTCTRL_CNT_0 ((uint32_t)0x00000001U) /* Boot Data Timeout Counter Value Bit0 */ +#define SDHOST_BOOTTCTRL_CNT_1 ((uint32_t)0x00000002U) /* Boot Data Timeout Counter Value Bit1 */ +#define SDHOST_BOOTTCTRL_CNT_2 ((uint32_t)0x00000004U) /* Boot Data Timeout Counter Value Bit2 */ +#define SDHOST_BOOTTCTRL_CNT_3 ((uint32_t)0x00000008U) /* Boot Data Timeout Counter Value Bit3 */ +#define SDHOST_BOOTTCTRL_CNT_4 ((uint32_t)0x00000010U) /* Boot Data Timeout Counter Value Bit4 */ +#define SDHOST_BOOTTCTRL_CNT_5 ((uint32_t)0x00000020U) /* Boot Data Timeout Counter Value Bit5 */ +#define SDHOST_BOOTTCTRL_CNT_6 ((uint32_t)0x00000040U) /* Boot Data Timeout Counter Value Bit6 */ +#define SDHOST_BOOTTCTRL_CNT_7 ((uint32_t)0x00000080U) /* Boot Data Timeout Counter Value Bit7 */ +#define SDHOST_BOOTTCTRL_CNT_8 ((uint32_t)0x00000100U) /* Boot Data Timeout Counter Value Bit8 */ +#define SDHOST_BOOTTCTRL_CNT_9 ((uint32_t)0x00000200U) /* Boot Data Timeout Counter Value Bit9 */ +#define SDHOST_BOOTTCTRL_CNT_10 ((uint32_t)0x00000400U) /* Boot Data Timeout Counter Value Bit10 */ +#define SDHOST_BOOTTCTRL_CNT_11 ((uint32_t)0x00000800U) /* Boot Data Timeout Counter Value Bit11 */ +#define SDHOST_BOOTTCTRL_CNT_12 ((uint32_t)0x00001000U) /* Boot Data Timeout Counter Value Bit12 */ +#define SDHOST_BOOTTCTRL_CNT_13 ((uint32_t)0x00002000U) /* Boot Data Timeout Counter Value Bit13 */ +#define SDHOST_BOOTTCTRL_CNT_14 ((uint32_t)0x00004000U) /* Boot Data Timeout Counter Value Bit14 */ +#define SDHOST_BOOTTCTRL_CNT_15 ((uint32_t)0x00008000U) /* Boot Data Timeout Counter Value Bit15 */ +#define SDHOST_BOOTTCTRL_CNT_16 ((uint32_t)0x00010000U) /* Boot Data Timeout Counter Value Bit16 */ +#define SDHOST_BOOTTCTRL_CNT_17 ((uint32_t)0x00020000U) /* Boot Data Timeout Counter Value Bit17 */ +#define SDHOST_BOOTTCTRL_CNT_18 ((uint32_t)0x00040000U) /* Boot Data Timeout Counter Value Bit18 */ +#define SDHOST_BOOTTCTRL_CNT_19 ((uint32_t)0x00080000U) /* Boot Data Timeout Counter Value Bit19 */ +#define SDHOST_BOOTTCTRL_CNT_20 ((uint32_t)0x00100000U) /* Boot Data Timeout Counter Value Bit20 */ +#define SDHOST_BOOTTCTRL_CNT_21 ((uint32_t)0x00200000U) /* Boot Data Timeout Counter Value Bit21 */ +#define SDHOST_BOOTTCTRL_CNT_22 ((uint32_t)0x00400000U) /* Boot Data Timeout Counter Value Bit22 */ +#define SDHOST_BOOTTCTRL_CNT_23 ((uint32_t)0x00800000U) /* Boot Data Timeout Counter Value Bit23 */ +#define SDHOST_BOOTTCTRL_CNT_24 ((uint32_t)0x01000000U) /* Boot Data Timeout Counter Value Bit24 */ +#define SDHOST_BOOTTCTRL_CNT_25 ((uint32_t)0x02000000U) /* Boot Data Timeout Counter Value Bit25 */ +#define SDHOST_BOOTTCTRL_CNT_26 ((uint32_t)0x04000000U) /* Boot Data Timeout Counter Value Bit26 */ +#define SDHOST_BOOTTCTRL_CNT_27 ((uint32_t)0x08000000U) /* Boot Data Timeout Counter Value Bit27 */ +#define SDHOST_BOOTTCTRL_CNT_28 ((uint32_t)0x10000000U) /* Boot Data Timeout Counter Value Bit28 */ +#define SDHOST_BOOTTCTRL_CNT_29 ((uint32_t)0x20000000U) /* Boot Data Timeout Counter Value Bit29 */ +#define SDHOST_BOOTTCTRL_CNT_30 ((uint32_t)0x40000000U) /* Boot Data Timeout Counter Value Bit30 */ +#define SDHOST_BOOTTCTRL_CNT_31 ((uint32_t)0x80000000U) /* Boot Data Timeout Counter Value Bit31 */ + + + +/******** DBG Module ********/ +/******** Bit definition for DBG_ID register ********/ +#define DBG_ID_IDCODE ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ + +/******** Bit definition for DBG_CTRL register ********/ +#define DBG_CTRL_TRACE_CFG ((uint32_t)0x00000400U) /* Bit[10] */ +#define DBG_CTRL_TRACE_MODE ((uint32_t)0x00000300U) /* Bit[9:8] */ +#define DBG_CTRL_TRACE_MODE_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_CTRL_TRACE_MODE_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_CTRL_TRACE_IOEN ((uint32_t)0x00000080U) /* Bit[7] */ +#define DBG_CTRL_TRGOEN ((uint32_t)0x00000040U) /* Bit[6] */ +#define DBG_CTRL_M7STBY ((uint32_t)0x00000020U) /* Bit[5] */ +#define DBG_CTRL_M7STOP ((uint32_t)0x00000010U) /* Bit[4] */ +#define DBG_CTRL_M7SLEEP ((uint32_t)0x00000008U) /* Bit[3] */ +#define DBG_CTRL_M4STBY ((uint32_t)0x00000004U) /* Bit[2] */ +#define DBG_CTRL_M4STOP ((uint32_t)0x00000002U) /* Bit[1] */ +#define DBG_CTRL_M4SLEEP ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for DBG_M7APB1FZ register ********/ +#define DBG_M7APB1FZ_CANFD5_STOP ((uint32_t)0x00040000U) /* Bit18*/ +#define DBG_M7APB1FZ_CANFD4_STOP ((uint32_t)0x00020000U) /* Bit17*/ +#define DBG_M7APB1FZ_CANFD2_STOP ((uint32_t)0x00010000U) /* Bit16*/ +#define DBG_M7APB1FZ_CANFD1_STOP ((uint32_t)0x00008000U) /* Bit15*/ +#define DBG_M7APB1FZ_WWDG2_STOP ((uint32_t)0x00004000U) /* Bit14 */ +#define DBG_M7APB1FZ_I2C3_STOP ((uint32_t)0x00002000U) /* Bit13*/ +#define DBG_M7APB1FZ_I2C2_STOP ((uint32_t)0x00001000U) /* Bit12*/ +#define DBG_M7APB1FZ_I2C1_STOP ((uint32_t)0x00000800U) /* Bit11*/ +#define DBG_M7APB1FZ_GTIMB3_STOP ((uint32_t)0x00000400U) /* Bit10*/ +#define DBG_M7APB1FZ_GTIMB2_STOP ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_M7APB1FZ_GTIMB1_STOP ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_M7APB1FZ_GTIMA7_STOP ((uint32_t)0x00000080U) /* Bit7*/ +#define DBG_M7APB1FZ_GTIMA6_STOP ((uint32_t)0x00000040U) /* Bit6*/ +#define DBG_M7APB1FZ_GTIMA5_STOP ((uint32_t)0x00000020U) /* Bit5*/ +#define DBG_M7APB1FZ_GTIMA4_STOP ((uint32_t)0x00000010U) /* Bit4*/ +#define DBG_M7APB1FZ_BTIM4_STOP ((uint32_t)0x00000008U) /* Bit3*/ +#define DBG_M7APB1FZ_BTIM3_STOP ((uint32_t)0x00000004U) /* Bit2*/ +#define DBG_M7APB1FZ_BTIM2_STOP ((uint32_t)0x00000002U) /* Bit1*/ +#define DBG_M7APB1FZ_BTIM1_STOP ((uint32_t)0x00000001U) /* Bit0*/ + +/******** Bit definition for DBG_M4APB1FZ register ********/ +#define DBG_M4APB1FZ_CANFD5_STOP ((uint32_t)0x00040000U) /* Bit18*/ +#define DBG_M4APB1FZ_CANFD4_STOP ((uint32_t)0x00020000U) /* Bit17*/ +#define DBG_M4APB1FZ_CANFD2_STOP ((uint32_t)0x00010000U) /* Bit16*/ +#define DBG_M4APB1FZ_CANFD1_STOP ((uint32_t)0x00008000U) /* Bit15*/ +#define DBG_M4APB1FZ_WWDG2_STOP ((uint32_t)0x00004000U) /* Bit14 */ +#define DBG_M4APB1FZ_I2C3_STOP ((uint32_t)0x00002000U) /* Bit13*/ +#define DBG_M4APB1FZ_I2C2_STOP ((uint32_t)0x00001000U) /* Bit12*/ +#define DBG_M4APB1FZ_I2C1_STOP ((uint32_t)0x00000800U) /* Bit11*/ +#define DBG_M4APB1FZ_GTIMB3_STOP ((uint32_t)0x00000400U) /* Bit10*/ +#define DBG_M4APB1FZ_GTIMB2_STOP ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_M4APB1FZ_GTIMB1_STOP ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_M4APB1FZ_GTIMA7_STOP ((uint32_t)0x00000080U) /* Bit7*/ +#define DBG_M4APB1FZ_GTIMA6_STOP ((uint32_t)0x00000040U) /* Bit6*/ +#define DBG_M4APB1FZ_GTIMA5_STOP ((uint32_t)0x00000020U) /* Bit5*/ +#define DBG_M4APB1FZ_GTIMA4_STOP ((uint32_t)0x00000010U) /* Bit4*/ +#define DBG_M4APB1FZ_BTIM4_STOP ((uint32_t)0x00000008U) /* Bit3*/ +#define DBG_M4APB1FZ_BTIM3_STOP ((uint32_t)0x00000004U) /* Bit2*/ +#define DBG_M4APB1FZ_BTIM2_STOP ((uint32_t)0x00000002U) /* Bit1*/ +#define DBG_M4APB1FZ_BTIM1_STOP ((uint32_t)0x00000001U) /* Bit0*/ + +/******** Bit definition for DBG_M7APB2FZ register ********/ +#define DBG_M7APB2FZ_CANFD8_STOP ((uint32_t)0x00002000U) /* Bit13*/ +#define DBG_M7APB2FZ_CANFD7_STOP ((uint32_t)0x00001000U) /* Bit12*/ +#define DBG_M7APB2FZ_CANFD4_STOP ((uint32_t)0x00000800U) /* Bit11*/ +#define DBG_M7APB2FZ_CANFD3_STOP ((uint32_t)0x00000400U) /* Bit10*/ +#define DBG_M7APB2FZ_I2C6_STOP ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_M7APB2FZ_I2C5_STOP ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_M7APB2FZ_I2C4_STOP ((uint32_t)0x00000080U) /* Bit7*/ +#define DBG_M7APB2FZ_ATIM2_STOP ((uint32_t)0x00000040U) /* Bit6*/ +#define DBG_M7APB2FZ_ATIM1_STOP ((uint32_t)0x00000020U) /* Bit5*/ +#define DBG_M7APB2FZ_GTIMA3_STOP ((uint32_t)0x00000010U) /* Bit4*/ +#define DBG_M7APB2FZ_GTIMA2_STOP ((uint32_t)0x00000008U) /* Bit3*/ +#define DBG_M7APB2FZ_GTIMA1_STOP ((uint32_t)0x00000004U) /* Bit2*/ +#define DBG_M7APB2FZ_SHRTIM2_STOP ((uint32_t)0x00000002U) /* Bit1*/ +#define DBG_M7APB2FZ_SHRTIM1_STOP ((uint32_t)0x00000001U) /* Bit0*/ +/******** Bit definition for DBG_M4APB2FZ register ********/ +#define DBG_M4APB2FZ_CANFD8_STOP ((uint32_t)0x00002000U) /* Bit13*/ +#define DBG_M4APB2FZ_CANFD7_STOP ((uint32_t)0x00001000U) /* Bit12*/ +#define DBG_M4APB2FZ_CANFD4_STOP ((uint32_t)0x00000800U) /* Bit11*/ +#define DBG_M4APB2FZ_CANFD3_STOP ((uint32_t)0x00000400U) /* Bit10*/ +#define DBG_M4APB2FZ_I2C6_STOP ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_M4APB2FZ_I2C5_STOP ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_M4APB2FZ_I2C4_STOP ((uint32_t)0x00000080U) /* Bit7*/ +#define DBG_M4APB2FZ_ATIM2_STOP ((uint32_t)0x00000040U) /* Bit6*/ +#define DBG_M4APB2FZ_ATIM1_STOP ((uint32_t)0x00000020U) /* Bit5*/ +#define DBG_M4APB2FZ_GTIMA3_STOP ((uint32_t)0x00000010U) /* Bit4*/ +#define DBG_M4APB2FZ_GTIMA2_STOP ((uint32_t)0x00000008U) /* Bit3*/ +#define DBG_M4APB2FZ_GTIMA1_STOP ((uint32_t)0x00000004U) /* Bit2*/ +#define DBG_M4APB2FZ_SHRTIM2_STOP ((uint32_t)0x00000002U) /* Bit1*/ +#define DBG_M4APB2FZ_SHRTIM1_STOP ((uint32_t)0x00000001U) /* Bit0*/ + +/******** Bit definition for DBG_M7APB5FZ register ********/ +#define DBG_M7APB5FZ_RTC_STOP ((uint32_t)0x00002000U) /* Bit13 */ +#define DBG_M7APB5FZ_LPTIM5_STOP ((uint32_t)0x00001000U) /* Bit12*/ +#define DBG_M7APB5FZ_LPTIM4_STOP ((uint32_t)0x00000800U) /* Bit11*/ +#define DBG_M7APB5FZ_LPTIM3_STOP ((uint32_t)0x00000400U) /* Bit10*/ +#define DBG_M7APB5FZ_LPTIM2_STOP ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_M7APB5FZ_LPTIM1_STOP ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_M7APB5FZ_IWDG2_STOP ((uint32_t)0x00000080U) /* Bit7*/ +#define DBG_M7APB5FZ_IWDG1_STOP ((uint32_t)0x00000040U) /* Bit6*/ +#define DBG_M7APB5FZ_I2C10_STOP ((uint32_t)0x00000020U) /* Bit5*/ +#define DBG_M7APB5FZ_I2C9_STOP ((uint32_t)0x00000010U) /* Bit4*/ +#define DBG_M7APB5FZ_I2C8_STOP ((uint32_t)0x00000008U) /* Bit3*/ +#define DBG_M7APB5FZ_I2C7_STOP ((uint32_t)0x00000004U) /* Bit2*/ +#define DBG_M7APB5FZ_ATIM4_STOP ((uint32_t)0x00000002U) /* Bit1*/ +#define DBG_M7APB5FZ_ATIM3_STOP ((uint32_t)0x00000001U) /* Bit0*/ + +/******** Bit definition for DBG_M4APB5FZ register ********/ +#define DBG_M4APB5FZ_RTC_STOP ((uint32_t)0x00002000U) /* Bit13 */ +#define DBG_M4APB5FZ_LPTIM5_STOP ((uint32_t)0x00001000U) /* Bit12*/ +#define DBG_M4APB5FZ_LPTIM4_STOP ((uint32_t)0x00000800U) /* Bit11*/ +#define DBG_M4APB5FZ_LPTIM3_STOP ((uint32_t)0x00000400U) /* Bit10*/ +#define DBG_M4APB5FZ_LPTIM2_STOP ((uint32_t)0x00000200U) /* Bit9*/ +#define DBG_M4APB5FZ_LPTIM1_STOP ((uint32_t)0x00000100U) /* Bit8*/ +#define DBG_M4APB5FZ_IWDG2_STOP ((uint32_t)0x00000080U) /* Bit7*/ +#define DBG_M4APB5FZ_IWDG1_STOP ((uint32_t)0x00000040U) /* Bit6*/ +#define DBG_M4APB5FZ_I2C10_STOP ((uint32_t)0x00000020U) /* Bit5*/ +#define DBG_M4APB5FZ_I2C9_STOP ((uint32_t)0x00000010U) /* Bit4*/ +#define DBG_M4APB5FZ_I2C8_STOP ((uint32_t)0x00000008U) /* Bit3*/ +#define DBG_M4APB5FZ_I2C7_STOP ((uint32_t)0x00000004U) /* Bit2*/ +#define DBG_M4APB5FZ_ATIM4_STOP ((uint32_t)0x00000002U) /* Bit1*/ +#define DBG_M4APB5FZ_ATIM3_STOP ((uint32_t)0x00000001U) /* Bit0*/ + +/******** Bit definition for DBG_M7APB6FZ register ********/ +#define DBG_M7APB6FZ_WWDG1_STOP ((uint32_t)0x00000001U) /* Bit[0] */ + +/******** Bit definition for DBG_M4APB6FZ register ********/ +#define DBG_M4APB6FZ_WWDG1_STOP ((uint32_t)0x00000001U) /* Bit[0] */ + + +/******** ECCMON Module ********/ +/******** Bit definition for ECCMON_CTRL1 register ********/ +#define ECCMON_CTRL1_E2INTEN6 ((uint32_t)0x20000000) /* Bit[29] */ +#define ECCMON_CTRL1_E2INTEN5 ((uint32_t)0x10000000) /* Bit[28] */ +#define ECCMON_CTRL1_E2INTEN4 ((uint32_t)0x08000000) /* Bit[27] */ +#define ECCMON_CTRL1_E2INTEN3 ((uint32_t)0x04000000) /* Bit[26] */ +#define ECCMON_CTRL1_E2INTEN2 ((uint32_t)0x02000000) /* Bit[25] */ +#define ECCMON_CTRL1_E2INTEN1 ((uint32_t)0x01000000) /* Bit[24] */ +#define ECCMON_CTRL1_E1INTEN6 ((uint32_t)0x00200000) /* Bit[21] */ +#define ECCMON_CTRL1_E1INTEN5 ((uint32_t)0x00100000) /* Bit[20] */ +#define ECCMON_CTRL1_E1INTEN4 ((uint32_t)0x00080000) /* Bit[19] */ +#define ECCMON_CTRL1_E1INTEN3 ((uint32_t)0x00040000) /* Bit[18] */ +#define ECCMON_CTRL1_E1INTEN2 ((uint32_t)0x00020000) /* Bit[17] */ +#define ECCMON_CTRL1_E1INTEN1 ((uint32_t)0x00010000) /* Bit[16] */ +#define ECCMON_CTRL1_TDRBYP6 ((uint32_t)0x00002000) /* Bit[13] */ +#define ECCMON_CTRL1_TDRBYP5 ((uint32_t)0x00001000) /* Bit[12] */ +#define ECCMON_CTRL1_TDRBYP4 ((uint32_t)0x00000800) /* Bit[11] */ +#define ECCMON_CTRL1_TDRBYP3 ((uint32_t)0x00000400) /* Bit[10] */ +#define ECCMON_CTRL1_TDRBYP2 ((uint32_t)0x00000200) /* Bit[9] */ +#define ECCMON_CTRL1_TDRBYP1 ((uint32_t)0x00000100) /* Bit[8] */ +#define ECCMON_CTRL1_ECCEN6 ((uint32_t)0x00000020) /* Bit[5] */ +#define ECCMON_CTRL1_ECCEN5 ((uint32_t)0x00000010) /* Bit[4] */ +#define ECCMON_CTRL1_ECCEN4 ((uint32_t)0x00000008) /* Bit[3] */ +#define ECCMON_CTRL1_ECCEN3 ((uint32_t)0x00000004) /* Bit[2] */ +#define ECCMON_CTRL1_ECCEN2 ((uint32_t)0x00000002) /* Bit[1] */ +#define ECCMON_CTRL1_ECCEN1 ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for ECCMON_CTRL2 register ********/ +#define ECCMON_CTRL2_E2FOEN6 ((uint32_t)0x20000000) /* Bit[29] */ +#define ECCMON_CTRL2_E2FOEN5 ((uint32_t)0x10000000) /* Bit[28] */ +#define ECCMON_CTRL2_E2FOEN4 ((uint32_t)0x08000000) /* Bit[27] */ +#define ECCMON_CTRL2_E2FOEN3 ((uint32_t)0x04000000) /* Bit[26] */ +#define ECCMON_CTRL2_E2FOEN2 ((uint32_t)0x02000000) /* Bit[25] */ +#define ECCMON_CTRL2_E2FOEN1 ((uint32_t)0x01000000) /* Bit[24] */ +#define ECCMON_CTRL2_E1FOEN6 ((uint32_t)0x00200000) /* Bit[21] */ +#define ECCMON_CTRL2_E1FOEN5 ((uint32_t)0x00100000) /* Bit[20] */ +#define ECCMON_CTRL2_E1FOEN4 ((uint32_t)0x00080000) /* Bit[19] */ +#define ECCMON_CTRL2_E1FOEN3 ((uint32_t)0x00040000) /* Bit[18] */ +#define ECCMON_CTRL2_E1FOEN2 ((uint32_t)0x00020000) /* Bit[17] */ +#define ECCMON_CTRL2_E1FOEN1 ((uint32_t)0x00010000) /* Bit[16] */ +#define ECCMON_CTRL2_WROE2EN6 ((uint32_t)0x00000020) /* Bit[5] */ +#define ECCMON_CTRL2_WROE2EN5 ((uint32_t)0x00000010) /* Bit[4] */ +#define ECCMON_CTRL2_WROE2EN4 ((uint32_t)0x00000008) /* Bit[3] */ +#define ECCMON_CTRL2_WROE2EN3 ((uint32_t)0x00000004) /* Bit[2] */ +#define ECCMON_CTRL2_WROE2EN2 ((uint32_t)0x00000002) /* Bit[1] */ +#define ECCMON_CTRL2_WROE2EN1 ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for ECCMON_EINJ register ********/ +#define ECCMON_EINJ_ECSEL6 ((uint32_t)0x0C000000) /* Bit[27:26] */ +#define ECCMON_EINJ_ECSEL6_0 ((uint32_t)0x04000000) /* Bit26*/ +#define ECCMON_EINJ_ECSEL6_1 ((uint32_t)0x08000000) /* Bit27*/ +#define ECCMON_EINJ_ECSEL5 ((uint32_t)0x03000000) /* Bit[25:24] */ +#define ECCMON_EINJ_ECSEL5_0 ((uint32_t)0x01000000) /* Bit24*/ +#define ECCMON_EINJ_ECSEL5_1 ((uint32_t)0x02000000) /* Bit25*/ +#define ECCMON_EINJ_ECSEL4 ((uint32_t)0x00C00000) /* Bit[23:22] */ +#define ECCMON_EINJ_ECSEL4_0 ((uint32_t)0x00400000) /* Bit22*/ +#define ECCMON_EINJ_ECSEL4_1 ((uint32_t)0x00800000) /* Bit23*/ +#define ECCMON_EINJ_ECSEL3 ((uint32_t)0x00300000) /* Bit[21:20] */ +#define ECCMON_EINJ_ECSEL3_0 ((uint32_t)0x00100000) /* Bit20*/ +#define ECCMON_EINJ_ECSEL3_1 ((uint32_t)0x00200000) /* Bit21*/ +#define ECCMON_EINJ_ECSEL2 ((uint32_t)0x000C0000) /* Bit[19:18] */ +#define ECCMON_EINJ_ECSEL2_0 ((uint32_t)0x00040000) /* Bit18*/ +#define ECCMON_EINJ_ECSEL2_1 ((uint32_t)0x00080000) /* Bit19*/ +#define ECCMON_EINJ_ECSEL1 ((uint32_t)0x00030000) /* Bit[17:16] */ +#define ECCMON_EINJ_ECSEL1_0 ((uint32_t)0x00010000) /* Bit16*/ +#define ECCMON_EINJ_ECSEL1_1 ((uint32_t)0x00020000) /* Bit17*/ +#define ECCMON_EINJ_ERICTR6 ((uint32_t)0x00000C00) /* Bit[11:10] */ +#define ECCMON_EINJ_ERICTR6_0 ((uint32_t)0x00000400) /* Bit10*/ +#define ECCMON_EINJ_ERICTR6_1 ((uint32_t)0x00000800) /* Bit11*/ +#define ECCMON_EINJ_ERICTR5 ((uint32_t)0x00000300) /* Bit[9:8] */ +#define ECCMON_EINJ_ERICTR5_0 ((uint32_t)0x00000100) /* Bit8*/ +#define ECCMON_EINJ_ERICTR5_1 ((uint32_t)0x00000200) /* Bit9*/ +#define ECCMON_EINJ_ERICTR4 ((uint32_t)0x000000C0) /* Bit[7:6] */ +#define ECCMON_EINJ_ERICTR4_0 ((uint32_t)0x00000040) /* Bit6*/ +#define ECCMON_EINJ_ERICTR4_1 ((uint32_t)0x00000080) /* Bit7*/ +#define ECCMON_EINJ_ERICTR3 ((uint32_t)0x00000030) /* Bit[5:4] */ +#define ECCMON_EINJ_ERICTR3_0 ((uint32_t)0x00000010) /* Bit4*/ +#define ECCMON_EINJ_ERICTR3_1 ((uint32_t)0x00000020) /* Bit5*/ +#define ECCMON_EINJ_ERICTR2 ((uint32_t)0x0000000C) /* Bit[3:2] */ +#define ECCMON_EINJ_ERICTR2_0 ((uint32_t)0x00000004) /* Bit2*/ +#define ECCMON_EINJ_ERICTR2_1 ((uint32_t)0x00000008) /* Bit3*/ +#define ECCMON_EINJ_ERICTR1 ((uint32_t)0x00000003) /* Bit[1:0] */ +#define ECCMON_EINJ_ERICTR1_0 ((uint32_t)0x00000001) /* Bit0*/ +#define ECCMON_EINJ_ERICTR1_1 ((uint32_t)0x00000002) /* Bit1*/ + +/******** Bit definition for ECCMON_INTFS register ********/ +#define ECCMON_INTFS_E2DCIF6 ((uint32_t)0x00200000) /* Bit[21] */ +#define ECCMON_INTFS_E2DCIF5 ((uint32_t)0x00100000) /* Bit[20] */ +#define ECCMON_INTFS_E2DCIF4 ((uint32_t)0x00080000) /* Bit[19] */ +#define ECCMON_INTFS_E2DCIF3 ((uint32_t)0x00040000) /* Bit[18] */ +#define ECCMON_INTFS_E2DCIF2 ((uint32_t)0x00020000) /* Bit[17] */ +#define ECCMON_INTFS_E2DCIF1 ((uint32_t)0x00010000) /* Bit[16] */ +#define ECCMON_INTFS_E1DCIF6 ((uint32_t)0x00000020) /* Bit[5] */ +#define ECCMON_INTFS_E1DCIF5 ((uint32_t)0x00000010) /* Bit[4] */ +#define ECCMON_INTFS_E1DCIF4 ((uint32_t)0x00000008) /* Bit[3] */ +#define ECCMON_INTFS_E1DCIF3 ((uint32_t)0x00000004) /* Bit[2] */ +#define ECCMON_INTFS_E1DCIF2 ((uint32_t)0x00000002) /* Bit[1] */ +#define ECCMON_INTFS_E1DCIF1 ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for ECCMON_INTF1 register ********/ +#define ECCMON_INTF1_E2DCIFR ((uint32_t)0x00000008) /* Bit[3] */ +#define ECCMON_INTF1_E1DCIFR ((uint32_t)0x00000004) /* Bit[2] */ +#define ECCMON_INTF1_E2DCIFW ((uint32_t)0x00000002) /* Bit[1] */ +#define ECCMON_INTF1_E1DCIFW ((uint32_t)0x00000001) /* Bit[0] */ + +/******** Bit definition for ECCMON_FEADR1 register ********/ +#define ECCMON_FEADR1_E2EAD ((uint32_t)0x80000000) /* Bit[31] */ +#define ECCMON_FEADR1_E1EAD ((uint32_t)0x40000000) /* Bit[30] */ +#define ECCMON_FEADR1_EER ((uint32_t)0x20000000) /* Bit[29] */ +#define ECCMON_FEADR1_EEW ((uint32_t)0x10000000) /* Bit[28] */ +#define ECCMON_FEADR1_EFADR ((uint32_t)0x0FFFFFFF) /* Bit[27:0] */ +#define ECCMON_FEADR1_EFADR_0 ((uint32_t)0x00000001) /* Bit0*/ +#define ECCMON_FEADR1_EFADR_1 ((uint32_t)0x00000002) /* Bit1*/ +#define ECCMON_FEADR1_EFADR_2 ((uint32_t)0x00000004) /* Bit2*/ +#define ECCMON_FEADR1_EFADR_3 ((uint32_t)0x00000008) /* Bit3*/ +#define ECCMON_FEADR1_EFADR_4 ((uint32_t)0x00000010) /* Bit4*/ +#define ECCMON_FEADR1_EFADR_5 ((uint32_t)0x00000020) /* Bit5*/ +#define ECCMON_FEADR1_EFADR_6 ((uint32_t)0x00000040) /* Bit6*/ +#define ECCMON_FEADR1_EFADR_7 ((uint32_t)0x00000080) /* Bit7*/ +#define ECCMON_FEADR1_EFADR_8 ((uint32_t)0x00000100) /* Bit8*/ +#define ECCMON_FEADR1_EFADR_9 ((uint32_t)0x00000200) /* Bit9*/ +#define ECCMON_FEADR1_EFADR_10 ((uint32_t)0x00000400) /* Bit10*/ +#define ECCMON_FEADR1_EFADR_11 ((uint32_t)0x00000800) /* Bit11*/ +#define ECCMON_FEADR1_EFADR_12 ((uint32_t)0x00001000) /* Bit12*/ +#define ECCMON_FEADR1_EFADR_13 ((uint32_t)0x00002000) /* Bit13*/ +#define ECCMON_FEADR1_EFADR_14 ((uint32_t)0x00004000) /* Bit14*/ +#define ECCMON_FEADR1_EFADR_15 ((uint32_t)0x00008000) /* Bit15*/ +#define ECCMON_FEADR1_EFADR_16 ((uint32_t)0x00010000) /* Bit16*/ +#define ECCMON_FEADR1_EFADR_17 ((uint32_t)0x00020000) /* Bit17*/ +#define ECCMON_FEADR1_EFADR_18 ((uint32_t)0x00040000) /* Bit18*/ +#define ECCMON_FEADR1_EFADR_19 ((uint32_t)0x00080000) /* Bit19*/ +#define ECCMON_FEADR1_EFADR_20 ((uint32_t)0x00100000) /* Bit20*/ +#define ECCMON_FEADR1_EFADR_21 ((uint32_t)0x00200000) /* Bit21*/ +#define ECCMON_FEADR1_EFADR_22 ((uint32_t)0x00400000) /* Bit22*/ +#define ECCMON_FEADR1_EFADR_23 ((uint32_t)0x00800000) /* Bit23*/ +#define ECCMON_FEADR1_EFADR_24 ((uint32_t)0x01000000) /* Bit24*/ +#define ECCMON_FEADR1_EFADR_25 ((uint32_t)0x02000000) /* Bit25*/ +#define ECCMON_FEADR1_EFADR_26 ((uint32_t)0x04000000) /* Bit26*/ +#define ECCMON_FEADR1_EFADR_27 ((uint32_t)0x08000000) /* Bit27*/ + +/******** Bit definition for ECCMON_FEDATL1 register ********/ +#define ECCMON_FEDATL1_ERDATL ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define ECCMON_FEDATL1_ERDATL_0 ((uint32_t)0x00000001) /* Bit0*/ +#define ECCMON_FEDATL1_ERDATL_1 ((uint32_t)0x00000002) /* Bit1*/ +#define ECCMON_FEDATL1_ERDATL_2 ((uint32_t)0x00000004) /* Bit2*/ +#define ECCMON_FEDATL1_ERDATL_3 ((uint32_t)0x00000008) /* Bit3*/ +#define ECCMON_FEDATL1_ERDATL_4 ((uint32_t)0x00000010) /* Bit4*/ +#define ECCMON_FEDATL1_ERDATL_5 ((uint32_t)0x00000020) /* Bit5*/ +#define ECCMON_FEDATL1_ERDATL_6 ((uint32_t)0x00000040) /* Bit6*/ +#define ECCMON_FEDATL1_ERDATL_7 ((uint32_t)0x00000080) /* Bit7*/ +#define ECCMON_FEDATL1_ERDATL_8 ((uint32_t)0x00000100) /* Bit8*/ +#define ECCMON_FEDATL1_ERDATL_9 ((uint32_t)0x00000200) /* Bit9*/ +#define ECCMON_FEDATL1_ERDATL_10 ((uint32_t)0x00000400) /* Bit10*/ +#define ECCMON_FEDATL1_ERDATL_11 ((uint32_t)0x00000800) /* Bit11*/ +#define ECCMON_FEDATL1_ERDATL_12 ((uint32_t)0x00001000) /* Bit12*/ +#define ECCMON_FEDATL1_ERDATL_13 ((uint32_t)0x00002000) /* Bit13*/ +#define ECCMON_FEDATL1_ERDATL_14 ((uint32_t)0x00004000) /* Bit14*/ +#define ECCMON_FEDATL1_ERDATL_15 ((uint32_t)0x00008000) /* Bit15*/ +#define ECCMON_FEDATL1_ERDATL_16 ((uint32_t)0x00010000) /* Bit16*/ +#define ECCMON_FEDATL1_ERDATL_17 ((uint32_t)0x00020000) /* Bit17*/ +#define ECCMON_FEDATL1_ERDATL_18 ((uint32_t)0x00040000) /* Bit18*/ +#define ECCMON_FEDATL1_ERDATL_19 ((uint32_t)0x00080000) /* Bit19*/ +#define ECCMON_FEDATL1_ERDATL_20 ((uint32_t)0x00100000) /* Bit20*/ +#define ECCMON_FEDATL1_ERDATL_21 ((uint32_t)0x00200000) /* Bit21*/ +#define ECCMON_FEDATL1_ERDATL_22 ((uint32_t)0x00400000) /* Bit22*/ +#define ECCMON_FEDATL1_ERDATL_23 ((uint32_t)0x00800000) /* Bit23*/ +#define ECCMON_FEDATL1_ERDATL_24 ((uint32_t)0x01000000) /* Bit24*/ +#define ECCMON_FEDATL1_ERDATL_25 ((uint32_t)0x02000000) /* Bit25*/ +#define ECCMON_FEDATL1_ERDATL_26 ((uint32_t)0x04000000) /* Bit26*/ +#define ECCMON_FEDATL1_ERDATL_27 ((uint32_t)0x08000000) /* Bit27*/ +#define ECCMON_FEDATL1_ERDATL_28 ((uint32_t)0x10000000) /* Bit28*/ +#define ECCMON_FEDATL1_ERDATL_29 ((uint32_t)0x20000000) /* Bit29*/ +#define ECCMON_FEDATL1_ERDATL_30 ((uint32_t)0x40000000) /* Bit30*/ +#define ECCMON_FEDATL1_ERDATL_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for ECCMON_FEDATH1 register ********/ +#define ECCMON_FEDATH1_ERDATH ((uint32_t)0xFFFFFFFF) /* Bit[31:0] */ +#define ECCMON_FEDATH1_ERDATH_0 ((uint32_t)0x00000001) /* Bit0*/ +#define ECCMON_FEDATH1_ERDATH_1 ((uint32_t)0x00000002) /* Bit1*/ +#define ECCMON_FEDATH1_ERDATH_2 ((uint32_t)0x00000004) /* Bit2*/ +#define ECCMON_FEDATH1_ERDATH_3 ((uint32_t)0x00000008) /* Bit3*/ +#define ECCMON_FEDATH1_ERDATH_4 ((uint32_t)0x00000010) /* Bit4*/ +#define ECCMON_FEDATH1_ERDATH_5 ((uint32_t)0x00000020) /* Bit5*/ +#define ECCMON_FEDATH1_ERDATH_6 ((uint32_t)0x00000040) /* Bit6*/ +#define ECCMON_FEDATH1_ERDATH_7 ((uint32_t)0x00000080) /* Bit7*/ +#define ECCMON_FEDATH1_ERDATH_8 ((uint32_t)0x00000100) /* Bit8*/ +#define ECCMON_FEDATH1_ERDATH_9 ((uint32_t)0x00000200) /* Bit9*/ +#define ECCMON_FEDATH1_ERDATH_10 ((uint32_t)0x00000400) /* Bit10*/ +#define ECCMON_FEDATH1_ERDATH_11 ((uint32_t)0x00000800) /* Bit11*/ +#define ECCMON_FEDATH1_ERDATH_12 ((uint32_t)0x00001000) /* Bit12*/ +#define ECCMON_FEDATH1_ERDATH_13 ((uint32_t)0x00002000) /* Bit13*/ +#define ECCMON_FEDATH1_ERDATH_14 ((uint32_t)0x00004000) /* Bit14*/ +#define ECCMON_FEDATH1_ERDATH_15 ((uint32_t)0x00008000) /* Bit15*/ +#define ECCMON_FEDATH1_ERDATH_16 ((uint32_t)0x00010000) /* Bit16*/ +#define ECCMON_FEDATH1_ERDATH_17 ((uint32_t)0x00020000) /* Bit17*/ +#define ECCMON_FEDATH1_ERDATH_18 ((uint32_t)0x00040000) /* Bit18*/ +#define ECCMON_FEDATH1_ERDATH_19 ((uint32_t)0x00080000) /* Bit19*/ +#define ECCMON_FEDATH1_ERDATH_20 ((uint32_t)0x00100000) /* Bit20*/ +#define ECCMON_FEDATH1_ERDATH_21 ((uint32_t)0x00200000) /* Bit21*/ +#define ECCMON_FEDATH1_ERDATH_22 ((uint32_t)0x00400000) /* Bit22*/ +#define ECCMON_FEDATH1_ERDATH_23 ((uint32_t)0x00800000) /* Bit23*/ +#define ECCMON_FEDATH1_ERDATH_24 ((uint32_t)0x01000000) /* Bit24*/ +#define ECCMON_FEDATH1_ERDATH_25 ((uint32_t)0x02000000) /* Bit25*/ +#define ECCMON_FEDATH1_ERDATH_26 ((uint32_t)0x04000000) /* Bit26*/ +#define ECCMON_FEDATH1_ERDATH_27 ((uint32_t)0x08000000) /* Bit27*/ +#define ECCMON_FEDATH1_ERDATH_28 ((uint32_t)0x10000000) /* Bit28*/ +#define ECCMON_FEDATH1_ERDATH_29 ((uint32_t)0x20000000) /* Bit29*/ +#define ECCMON_FEDATH1_ERDATH_30 ((uint32_t)0x40000000) /* Bit30*/ +#define ECCMON_FEDATH1_ERDATH_31 ((uint32_t)0x80000000) /* Bit31*/ + +/******** Bit definition for ECCMON_FECOD1 register ********/ +#define ECCMON_FECOD1_ERCOD ((uint32_t)0x0000007F) /* Bit[6:0] */ +#define ECCMON_FECOD1_ERCOD_0 ((uint32_t)0x00000001) /* Bit0*/ +#define ECCMON_FECOD1_ERCOD_1 ((uint32_t)0x00000002) /* Bit1*/ +#define ECCMON_FECOD1_ERCOD_2 ((uint32_t)0x00000004) /* Bit2*/ +#define ECCMON_FECOD1_ERCOD_3 ((uint32_t)0x00000008) /* Bit3*/ +#define ECCMON_FECOD1_ERCOD_4 ((uint32_t)0x00000010) /* Bit4*/ +#define ECCMON_FECOD1_ERCOD_5 ((uint32_t)0x00000020) /* Bit5*/ +#define ECCMON_FECOD1_ERCOD_6 ((uint32_t)0x00000040) /* Bit6*/ + +/*** OPTC register ***/ +/** Bit definition for OTPC_CTRL register **/ +#define OTPC_CTRL_BEEN ((uint32_t)0x00000040U) /* Bit[6] Busy Error Interrupt Control */ +#define OTPC_CTRL_OOREEN ((uint32_t)0x00000020U) /* Bit[5] Operate Over Region Error Interrupt Control */ +#define OTPC_CTRL_RDPEEN ((uint32_t)0x00000010U) /* Bit[4] Read Protected Error Interrupt Control */ +#define OTPC_CTRL_WRPEEN ((uint32_t)0x00000008U) /* Bit[3] Write Protected Error Interrupt Control */ +#define OTPC_CTRL_PGEEN ((uint32_t)0x00000004U) /* Bit[2] Program Error Interrupt Control */ +#define OTPC_CTRL_PRMD ((uint32_t)0x00000002U) /* Bit[1] Read or Write Control */ +#define OTPC_CTRL_LOCK ((uint32_t)0x00000001U) /* Bit[0] Lock Control */ + +/** Bit definition for OTPC_STS register **/ +#define OTPC_STS_BE ((uint32_t)0x00000040U) /* Bit[6] Busy Error Flag */ +#define OTPC_STS_OORE ((uint32_t)0x00000020U) /* Bit[5] Operate Over Region Error Flag */ +#define OTPC_STS_RDPE ((uint32_t)0x00000010U) /* Bit[4] Read Protected Error Flag */ +#define OTPC_STS_WRPE ((uint32_t)0x00000008U) /* Bit[3] Write Protected Error Flag */ +#define OTPC_STS_PGE ((uint32_t)0x00000004U) /* Bit[2] Program Error Flag */ +#define OTPC_STS_KEYE ((uint32_t)0x00000002U) /* Bit[1] Unlock Err Flag */ +#define OTPC_STS_BUSY ((uint32_t)0x00000001U) /* Bit[0] Busy Flag */ + +/** Bit definition for OTPC_KEY register **/ +#define OTPC_KEY_KEY ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Unlock Key */ + +/** Bit definition for OTPC_USC register **/ +#define OTPC_USC_VAL ((uint32_t)0x000001FFU) /* Bit[8:0] 1us Counter */ + + +/** Bit definition for OTPC_ADDR register **/ +#define OTPC_ADDR_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Operate Address of the OTP */ + +/** Bit definition for OTPC_RDATA register **/ +#define OTPC_RDATA_DAT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Read Data */ + +/** Bit definition for OTPC_WDATA register **/ +#define OTPC_WDATA_DAT ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Program Data */ + +/** Bit definition for OTPC_SECJVLD register **/ +#define OTPC_SECJVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] SEC_JTAG Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_SECMDVLD register **/ +#define OTPC_SECMDVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] SEC_MODE Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_RDP2PVLD register **/ +#define OTPC_RDP2PVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] RDP2_PROG Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_BTMVLD register **/ +#define OTPC_BTMVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] BTM Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_BORVLD register **/ +#define OTPC_BORVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] BOR Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_IWDGVLD register **/ +#define OTPC_IWDGVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] IWDG Multi-Copies Valid Tag */ + + +/** Bit definition for OTPC_TCMSZVLD register **/ +#define OTPC_TCMSZVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] TCM SIZE Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_JTAGKVLD register **/ +#define OTPC_JTAGKVLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] JTAG_KEY Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_REKU1VLD register **/ +#define OTPC_REKU1VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] REK_UNIT1 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_REKU2VLD register **/ +#define OTPC_REKU2VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] REK_UNIT2 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_REKU3VLD register **/ +#define OTPC_REKU3VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] REK_UNIT3 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_REKU4V register **/ +#define OTPC_REKU4VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] REK_UNIT4 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_IDKU1VLD register **/ +#define OTPC_IDKU1VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] IDK_UNIT1 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_IDKU2VLD register **/ +#define OTPC_IDKU2VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] IDK_UNIT2 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_IDKU3VLD register **/ +#define OTPC_IDKU3VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] IDK_UNIT3 Multi-Copies Valid Tag */ + +/** Bit definition for OTPC_IDKU4VLD register **/ +#define OTPC_IDKU4VLD_IDX ((uint32_t)0x0000FFFFU) /* Bit[15:0] IDK_UNIT4 Multi-Copies Valid Tag */ + + +/** Bit definition for OTPC_UMUU0 register **/ +#define OTPC_UMUU0_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU1 register **/ +#define OTPC_UMUU1_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU2 register **/ +#define OTPC_UMUU2_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU3 register **/ +#define OTPC_UMUU3_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU4 register **/ +#define OTPC_UMUU4_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU5 register **/ +#define OTPC_UMUU5_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU6 register **/ +#define OTPC_UMUU6_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_UMUU7 register **/ +#define OTPC_UMUU7_UU ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] User Memory Unused Flag */ + +/** Bit definition for OTPC_CRLD1 register **/ +#define OTPC_CRLD1_NRIWDG ((uint32_t)0x3FFF0000U) /* Bit[29:16] SYS_CFG_NRST_IWDG_OTP Payload Data */ +#define OTPC_CRLD1_NRIWDG_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define OTPC_CRLD1_NRIWDG_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define OTPC_CRLD1_NRIWDG_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define OTPC_CRLD1_NRIWDG_3 ((uint32_t)0x00080000U) /* Bit19*/ +#define OTPC_CRLD1_NRIWDG_4 ((uint32_t)0x00100000U) /* Bit20*/ +#define OTPC_CRLD1_NRIWDG_5 ((uint32_t)0x00200000U) /* Bit21*/ +#define OTPC_CRLD1_NRIWDG_6 ((uint32_t)0x00400000U) /* Bit22*/ +#define OTPC_CRLD1_NRIWDG_7 ((uint32_t)0x00800000U) /* Bit23*/ +#define OTPC_CRLD1_NRIWDG_8 ((uint32_t)0x01000000U) /* Bit24*/ +#define OTPC_CRLD1_NRIWDG_9 ((uint32_t)0x02000000U) /* Bit25*/ +#define OTPC_CRLD1_NRIWDG_10 ((uint32_t)0x04000000U) /* Bit26*/ +#define OTPC_CRLD1_NRIWDG_11 ((uint32_t)0x08000000U) /* Bit27*/ +#define OTPC_CRLD1_NRIWDG_12 ((uint32_t)0x10000000U) /* Bit28*/ +#define OTPC_CRLD1_NRIWDG_13 ((uint32_t)0x20000000U) /* Bit29*/ +#define OTPC_CRLD1_BOR ((uint32_t)0x00007000U) /* Bit[14:12] SYS_CFG_BOR_OTP Payload Data*/ +#define OTPC_CRLD1_BOR_0 ((uint32_t)0x00001000U) /* Bit12*/ +#define OTPC_CRLD1_BOR_1 ((uint32_t)0x00002000U) /* Bit13*/ +#define OTPC_CRLD1_BOR_2 ((uint32_t)0x00004000U) /* Bit14*/ +#define OTPC_CRLD1_SJAG ((uint32_t)0x0000000FU) /* Bit[3:0] SEC_JTAG_CFG_OTP Payload Data */ +#define OTPC_CRLD1_SJAG_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define OTPC_CRLD1_SJAG_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define OTPC_CRLD1_SJAG_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define OTPC_CRLD1_SJAG_3 ((uint32_t)0x00000008U) /* Bit3*/ + +/** Bit definition for OTPC_CRLD2 register **/ +#define OTPC_CRLD2_L2MD ((uint32_t)0x00001000U) /* Bit[12] L2_Mode State */ +#define OTPC_CRLD2_L1MD ((uint32_t)0x00000800U) /* Bit[11] L1_Mode State */ +#define OTPC_CRLD2_L0MD ((uint32_t)0x00000400U) /* Bit[10] L0_Mode State */ +#define OTPC_CRLD2_ROOTMD ((uint32_t)0x00000200U) /* Bit[9] ROOT_Mode State */ +#define OTPC_CRLD2_INITMD ((uint32_t)0x00000100U) /* Bit[8] INIT_MOde State */ +#define OTPC_CRLD2_TCMSZ ((uint32_t)0x0000003FU) /* Bit[5:0] TCM_SZ_CFG_OTP Payload Data */ +#define OTPC_CRLD2_TCMSZ_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define OTPC_CRLD2_TCMSZ_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define OTPC_CRLD2_TCMSZ_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define OTPC_CRLD2_TCMSZ_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define OTPC_CRLD2_TCMSZ_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define OTPC_CRLD2_TCMSZ_5 ((uint32_t)0x00000020U) /* Bit5*/ + + + +/*** MMU register ***/ +/** Bit definition for MMU_CTRL register **/ +#define MMU_CTRL_RSTE ((uint32_t)0x00000002U) /* Bit[1] Rest MMU*/ +#define MMU_CTRL_INTE ((uint32_t)0x00000001U) /* Bit[0] MMU Interrupt Enable*/ + +/** Bit definition for MMU_STS register **/ +#define MMU_STS_XSPIL ((uint32_t)0x04000000U) /* Bit[26] XSP1 Configuration Lock Flag*/ +#define MMU_STS_ITRDE ((uint32_t)0x02000000U) /* Bit[25] ITCM Read Error Flag*/ +#define MMU_STS_ITWRE ((uint32_t)0x01000000U) /* Bit[24] ITCM Write Error Flag*/ +#define MMU_STS_BKRDE ((uint32_t)0x00800000U) /* Bit[23] Back Sram Read Error Flag*/ +#define MMU_STS_BKWRE ((uint32_t)0x00400000U) /* Bit[22] Back Sram Write Error Flag*/ +#define MMU_STS_H5RDE ((uint32_t)0x00200000U) /* Bit[21] AHB SRAM5 Read Error Flag*/ +#define MMU_STS_H5WRE ((uint32_t)0x00100000U) /* Bit[20] AHB SRAM5 Write Error Flag*/ +#define MMU_STS_H4RDE ((uint32_t)0x00080000U) /* Bit[19] AHB SRAM4 Read Error Flag*/ +#define MMU_STS_H4WRE ((uint32_t)0x00040000U) /* Bit[18] AHB SRAM4 Write Error Flag*/ +#define MMU_STS_H3RDE ((uint32_t)0x00020000U) /* Bit[17] AHB SRAM3 Read Error Flag*/ +#define MMU_STS_H3WRE ((uint32_t)0x00010000U) /* Bit[16] AHB SRAM3 Write Error Flag*/ +#define MMU_STS_H2RDE ((uint32_t)0x00008000U) /* Bit[15] AHB SRAM2 Read Error Flag*/ +#define MMU_STS_H2WRE ((uint32_t)0x00004000U) /* Bit[14] AHB SRAM2 Write Error Flag*/ +#define MMU_STS_H1RDE ((uint32_t)0x00002000U) /* Bit[13] AHB SRAM1 Read Error Flag*/ +#define MMU_STS_H1WRE ((uint32_t)0x00001000U) /* Bit[12] AHB SRAM1 Write Error Flag*/ +#define MMU_STS_X3RDE ((uint32_t)0x00000800U) /* Bit[11] AXI SRAM3 Read Error Flag*/ +#define MMU_STS_X3WRE ((uint32_t)0x00000400U) /* Bit[10] AXI SRAM3 Write Error Flag*/ +#define MMU_STS_X2RDE ((uint32_t)0x00000200U) /* Bit[9] AXI SRAM2 Read Error Flag*/ +#define MMU_STS_X2WRE ((uint32_t)0x00000100U) /* Bit[8] AXI SRAM2 Write Error Flag*/ +#define MMU_STS_X1RDE ((uint32_t)0x00000080U) /* Bit[7] AXI SRAM1 Read Error Flag*/ +#define MMU_STS_X1WRE ((uint32_t)0x00000040U) /* Bit[6] AXI SRAM1 Write Error Flag*/ +#define MMU_STS_OBL ((uint32_t)0x00000020U) /* Bit[5] OB FLASH Lock*/ +#define MMU_STS_FLASHL ((uint32_t)0x00000010U) /* Bit[4] Flash Lock Flag*/ +#define MMU_STS_XSPIRDE ((uint32_t)0x00000008U) /* Bit[3] XSPI Read Error Flag*/ + +/** Bit definition for MMU_RTADC1~4 register **/ +#define MMU_RTADC_RPROPERTY ((uint32_t)0x000000C0U) /* Region x Property */ +#define MMU_RTADC_RPROPERTY_0 ((uint32_t)0x00000040U) /* Region x Property Bit0 */ +#define MMU_RTADC_RPROPERTY_1 ((uint32_t)0x00000080U) /* Region x Property Bit1 */ + +#define MMU_RTADC_RMOD ((uint32_t)0x00000030U) /* RTAD mode for RTAD Region x */ +#define MMU_RTADC_RMOD_0 ((uint32_t)0x00000010U) /* RTAD mode for RTAD Region x Bit0 */ +#define MMU_RTADC_RMOD_1 ((uint32_t)0x00000020U) /* RTAD mode for RTAD Region x Bit1 */ + +#define MMU_RTADC_RKEYL ((uint32_t)0x00000004U) /* RTAD key lock for RTAD Region x */ +#define MMU_RTADC_RCFGL ((uint32_t)0x00000002U) /* RTAD configuration lock for RTAD Region x */ +#define MMU_RTADC_REN ((uint32_t)0x00000001U) /* RTAD Region x Enable */ + +/** Bit definition for MMU_RTKXPX register **/ +#define MMU_RTKXPX_KEY ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] RegionX PartX Key*/ +#define MMU_RTKXPX_KEY_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_RTKXPX_KEY_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_RTKXPX_KEY_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_RTKXPX_KEY_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_RTKXPX_KEY_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_RTKXPX_KEY_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_RTKXPX_KEY_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_RTKXPX_KEY_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_RTKXPX_KEY_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_RTKXPX_KEY_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_RTKXPX_KEY_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_RTKXPX_KEY_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_RTKXPX_KEY_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_RTKXPX_KEY_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_RTKXPX_KEY_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_RTKXPX_KEY_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_RTKXPX_KEY_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_RTKXPX_KEY_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_RTKXPX_KEY_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_RTKXPX_KEY_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_RTKXPX_KEY_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_RTKXPX_KEY_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_RTKXPX_KEY_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_RTKXPX_KEY_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_RTKXPX_KEY_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_RTKXPX_KEY_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_RTKXPX_KEY_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_RTKXPX_KEY_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_RTKXPX_KEY_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_RTKXPX_KEY_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_RTKXPX_KEY_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_RTKXPX_KEY_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_RTRX register **/ +#define MMU_RTRX_REND ((uint32_t)0x1FFF0000U) /* Bit[28:16] RTAD Region x END for RTAD Region x */ +#define MMU_RTRX_RBEG ((uint32_t)0x00001FFFU) /* Bit[12:0] RTAD Region x BEGIN for RTAD Region x*/ + +/** Bit definition for MMU_RTCRC register **/ +#define MMU_RTCRC_CRC ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] RTAD CRC Poly*/ +#define MMU_RTCRC_CRC_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_RTCRC_CRC_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_RTCRC_CRC_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_RTCRC_CRC_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_RTCRC_CRC_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_RTCRC_CRC_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_RTCRC_CRC_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_RTCRC_CRC_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_RTCRC_CRC_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_RTCRC_CRC_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_RTCRC_CRC_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_RTCRC_CRC_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_RTCRC_CRC_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_RTCRC_CRC_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_RTCRC_CRC_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_RTCRC_CRC_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_RTCRC_CRC_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_RTCRC_CRC_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_RTCRC_CRC_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_RTCRC_CRC_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_RTCRC_CRC_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_RTCRC_CRC_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_RTCRC_CRC_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_RTCRC_CRC_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_RTCRC_CRC_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_RTCRC_CRC_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_RTCRC_CRC_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_RTCRC_CRC_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_RTCRC_CRC_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_RTCRC_CRC_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_RTCRC_CRC_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_RTCRC_CRC_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_ETH1ME register **/ +#define MMU_ETH1ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] ETH1 Master*/ +#define MMU_ETH1ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_ETH1ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_ETH1ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_ETH1ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] ETH1 User ID*/ +#define MMU_ETH1ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_ETH1ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_ETH1ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_ETH1ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_ETH1ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_ETH1ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_ETH1ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_ETH1ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_ETH1ME_EN ((uint32_t)0x00000001U) /* Bit[0] ETH1 Memory Enable*/ + +/** Bit definition for MMU_ETH2ME register **/ +#define MMU_ETH2ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] ETH2 Master*/ +#define MMU_ETH2ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_ETH2ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_ETH2ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_ETH2ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] ETH2 User ID*/ +#define MMU_ETH2ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_ETH2ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_ETH2ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_ETH2ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_ETH2ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_ETH2ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_ETH2ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_ETH2ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_ETH2ME_EN ((uint32_t)0x00000001U) /* Bit[0] ETH2 Memory Enable*/ + +/** Bit definition for MMU_USB1ME register **/ +#define MMU_USB1ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] USB1 Master*/ +#define MMU_USB1ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_USB1ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_USB1ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_USB1ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] USB1 User ID*/ +#define MMU_USB1ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_USB1ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_USB1ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_USB1ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_USB1ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_USB1ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_USB1ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_USB1ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_USB1ME_EN ((uint32_t)0x00000001U) /* Bit[0] USB1 Memory Enable*/ + +/** Bit definition for MMU_USB2ME register **/ +#define MMU_USB2ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] USB2 Master*/ +#define MMU_USB2ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_USB2ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_USB2ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_USB2ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] USB2 User ID*/ +#define MMU_USB2ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_USB2ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_USB2ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_USB2ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_USB2ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_USB2ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_USB2ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_USB2ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_USB2ME_EN ((uint32_t)0x00000001U) /* Bit[0] USB2 Memory Enable*/ + +/** Bit definition for MMU_SD1ME register **/ +#define MMU_SD1ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] SDMMC1 Master*/ +#define MMU_SD1ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_SD1ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_SD1ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_SD1ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] SDMMC User ID*/ +#define MMU_SD1ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_SD1ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_SD1ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_SD1ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_SD1ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_SD1ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_SD1ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_SD1ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_SD1ME_EN ((uint32_t)0x00000001U) /* Bit[0] SDMMC1 Memory Enable*/ + +/** Bit definition for MMU_SD2ME register **/ +#define MMU_SD2ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] SDMMC2 Master*/ +#define MMU_SD2ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_SD2ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_SD2ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_SD2ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] SDMMC2 User ID*/ +#define MMU_SD2ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_SD2ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_SD2ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_SD2ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_SD2ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_SD2ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_SD2ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_SD2ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_SD2ME_EN ((uint32_t)0x00000001U) /* Bit[0] SDMMC2 Memory Enable*/ + +/** Bit definition for MMU_DVP1ME register **/ +#define MMU_DVP1ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] DVP1 Master*/ +#define MMU_DVP1ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_DVP1ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_DVP1ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_DVP1ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] DVP1 User ID*/ +#define MMU_DVP1ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_DVP1ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_DVP1ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_DVP1ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_DVP1ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_DVP1ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_DVP1ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_DVP1ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_DVP1ME_EN ((uint32_t)0x00000001U) /* Bit[0] DVP1 Memory Enable*/ + +/** Bit definition for MMU_DVP2ME register **/ +#define MMU_DVP2ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] DVP2 Master*/ +#define MMU_DVP2ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_DVP2ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_DVP2ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_DVP2ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] DVP2 User ID*/ +#define MMU_DVP2ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_DVP2ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_DVP2ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_DVP2ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_DVP2ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_DVP2ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_DVP2ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_DVP2ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_DVP2ME_EN ((uint32_t)0x00000001U) /* Bit[0] DVP2 Memory Enable*/ + +/** Bit definition for MMU_DMA1ME register **/ +#define MMU_DMA1ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] DMA1 Master*/ +#define MMU_DMA1ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_DMA1ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_DMA1ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_DMA1ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] DMA1 User ID*/ +#define MMU_DMA1ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_DMA1ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_DMA1ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_DMA1ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_DMA1ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_DMA1ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_DMA1ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_DMA1ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_DMA1ME_EN ((uint32_t)0x00000001U) /* Bit[0] DMA1 Memory Enable*/ + +/** Bit definition for MMU_DMA2ME register **/ +#define MMU_DMA2ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] DMA2 Master*/ +#define MMU_DMA2ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_DMA2ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_DMA2ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_DMA2ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] DMA2 User ID*/ +#define MMU_DMA2ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_DMA2ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_DMA2ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_DMA2ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_DMA2ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_DMA2ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_DMA2ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_DMA2ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_DMA2ME_EN ((uint32_t)0x00000001U) /* Bit[0] DMA2 Memory Enable*/ + +/** Bit definition for MMU_DMA3ME register **/ +#define MMU_DMA3ME_MID ((uint32_t)0x00070000U) /* Bit[18:16] DMA3 Master*/ +#define MMU_DMA3ME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_DMA3ME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_DMA3ME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_DMA3ME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] DMA3 User ID*/ +#define MMU_DMA3ME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_DMA3ME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_DMA3ME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_DMA3ME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_DMA3ME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_DMA3ME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_DMA3ME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_DMA3ME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_DMA3ME_EN ((uint32_t)0x00000001U) /* Bit[0] DMA3 Memory Enable*/ + +/** Bit definition for MMU_MDMAME register **/ +#define MMU_MDMAME_MID ((uint32_t)0x00070000U) /* Bit[18:16] MDMA Master*/ +#define MMU_MDMAME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_MDMAME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_MDMAME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_MDMAME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] MDMA User ID*/ +#define MMU_MDMAME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_MDMAME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_MDMAME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_MDMAME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_MDMAME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_MDMAME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_MDMAME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_MDMAME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_MDMAME_EN ((uint32_t)0x00000001U) /* Bit[0] MDMA Memory Enable*/ + +/** Bit definition for MMU_JPEGME register **/ +#define MMU_JPEGME_MID ((uint32_t)0x00070000U) /* Bit[18:16] JPEG Master*/ +#define MMU_JPEGME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_JPEGME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_JPEGME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_JPEGME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] JPEG User ID*/ +#define MMU_JPEGME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_JPEGME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_JPEGME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_JPEGME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_JPEGME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_JPEGME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_JPEGME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_JPEGME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_JPEGME_EN ((uint32_t)0x00000001U) /* Bit[0] JPEG Memory Enable*/ + +/** Bit definition for MMU_LCDME register **/ +#define MMU_LCDME_MID ((uint32_t)0x00070000U) /* Bit[18:16] LCDC Master*/ +#define MMU_LCDME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_LCDME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_LCDME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_LCDME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] LCDC User ID*/ +#define MMU_LCDME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_LCDME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_LCDME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_LCDME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_LCDME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_LCDME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_LCDME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_LCDME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_LCDME_EN ((uint32_t)0x00000001U) /* Bit[0] LCDC Memory Enable*/ + +/** Bit definition for MMU_GPUME register **/ +#define MMU_GPUME_MID ((uint32_t)0x00070000U) /* Bit[18:16] GPU Master*/ +#define MMU_GPUME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_GPUME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_GPUME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_GPUME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] GPU User ID*/ +#define MMU_GPUME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_GPUME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_GPUME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_GPUME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_GPUME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_GPUME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_GPUME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_GPUME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_GPUME_ME ((uint32_t)0x00000001U) /* Bit[0] GPU Memory Enable*/ + +/** Bit definition for MMU_SDPUME register **/ +#define MMU_SDPUME_MID ((uint32_t)0x00070000U) /* Bit[18:16] SDPU Master*/ +#define MMU_SDPUME_MID_0 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_SDPUME_MID_1 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_SDPUME_MID_2 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_SDPUME_UID ((uint32_t)0x0000FF00U) /* Bit[15:8] SDPU User ID*/ +#define MMU_SDPUME_UID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_SDPUME_UID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_SDPUME_UID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_SDPUME_UID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_SDPUME_UID_4 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_SDPUME_UID_5 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_SDPUME_UID_6 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_SDPUME_UID_7 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_SDPUME_EN ((uint32_t)0x00000001U) /* Bit[0] SDPU Memory Enable*/ + +/** Bit definition for MMU_XRD register **/ +#define MMU_XRD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] XSPI Master ID*/ +#define MMU_XRD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_XRD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_XRD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_XRD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_XRD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] XSPI UID*/ +#define MMU_XRD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_XRD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_XRD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_XRD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_XRD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_XRD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_XRD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_XRD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_XRAD register **/ +#define MMU_XRAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] XSPI Read Error Address*/ +#define MMU_XRAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_XRAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_XRAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_XRAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_XRAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_XRAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_XRAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_XRAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_XRAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_XRAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_XRAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_XRAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_XRAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_XRAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_XRAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_XRAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_XRAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_XRAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_XRAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_XRAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_XRAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_XRAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_XRAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_XRAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_XRAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_XRAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_XRAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_XRAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_XRAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_XRAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_XRAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_XRAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_XxWD register **/ +#define MMU_X1WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AXI SRAM1 Master ID*/ +#define MMU_X1WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X1WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X1WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X1WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X1WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AXI SRAM1 UID*/ +#define MMU_X1WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X1WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X1WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X1WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X1WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X1WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X1WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X1WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_X1RD register **/ +#define MMU_X1RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AXI SRAM1 Master ID*/ +#define MMU_X1RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X1RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X1RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X1RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X1RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AXI SRAM1 UID*/ +#define MMU_X1RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X1RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X1RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X1RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X1RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X1RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X1RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X1RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_X1WAD register **/ +#define MMU_X1WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AXI SRAM1 Write Error Address*/ +#define MMU_X1WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X1WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X1WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X1WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X1WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X1WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X1WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X1WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_X1WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X1WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X1WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X1WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X1WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_X1WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_X1WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_X1WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_X1WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_X1WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_X1WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_X1WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_X1WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_X1WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_X1WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_X1WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_X1WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_X1WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_X1WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_X1WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_X1WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_X1WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_X1WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_X1WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_X1RAD register **/ +#define MMU_X1RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AXI SRAM1 Read Error Address*/ +#define MMU_X1RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X1RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X1RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X1RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X1RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X1RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X1RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X1RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_X1RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X1RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X1RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X1RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X1RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_X1RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_X1RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_X1RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_X1RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_X1RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_X1RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_X1RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_X1RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_X1RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_X1RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_X1RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_X1RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_X1RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_X1RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_X1RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_X1RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_X1RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_X1RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_X1RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_X2WD register **/ +#define MMU_X2WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AXI SRAM2 Master ID*/ +#define MMU_X2WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X2WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X2WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X2WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X2WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AXI SRAM2 UID*/ +#define MMU_X2WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X2WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X2WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X2WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X2WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X2WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X2WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X2WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_X2RD register **/ +#define MMU_X2RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AXI SRAM2 Master ID*/ +#define MMU_X2RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X2RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X2RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X2RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X2RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AXI SRAM2 UID*/ +#define MMU_X2RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X2RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X2RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X2RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X2RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X2RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X2RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X2RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_X2WAD register **/ +#define MMU_X2WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AXI SRAM2 Write Error Address*/ +#define MMU_X2WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X2WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X2WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X2WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X2WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X2WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X2WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X2WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_X2WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X2WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X2WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X2WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X2WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_X2WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_X2WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_X2WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_X2WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_X2WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_X2WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_X2WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_X2WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_X2WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_X2WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_X2WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_X2WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_X2WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_X2WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_X2WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_X2WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_X2WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_X2WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_X2WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_X2RAD register **/ +#define MMU_X2RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AXI SRAM2 Read Error Address*/ +#define MMU_X2RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X2RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X2RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X2RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X2RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X2RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X2RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X2RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_X2RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X2RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X2RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X2RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X2RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_X2RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_X2RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_X2RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_X2RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_X2RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_X2RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_X2RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_X2RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_X2RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_X2RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_X2RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_X2RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_X2RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_X2RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_X2RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_X2RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_X2RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_X2RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_X2RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_X3WD register **/ +#define MMU_X3WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AXI SRAM3 Master ID*/ +#define MMU_X3WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X3WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X3WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X3WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X3WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AXI SRAM3 UID*/ +#define MMU_X3WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X3WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X3WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X3WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X3WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X3WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X3WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X3WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_X3RD register **/ +#define MMU_X3RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AXI SRAM3 Master ID*/ +#define MMU_X3RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X3RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X3RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X3RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X3RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AXI SRAM3 UID*/ +#define MMU_X3RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X3RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X3RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X3RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X3RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X3RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X3RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X3RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_X3WAD register **/ +#define MMU_X3WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AXI SRAM3 Write Error Address*/ +#define MMU_X3WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X3WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X3WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X3WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X3WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X3WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X3WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X3WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_X3WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X3WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X3WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X3WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X3WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_X3WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_X3WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_X3WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_X3WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_X3WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_X3WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_X3WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_X3WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_X3WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_X3WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_X3WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_X3WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_X3WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_X3WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_X3WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_X3WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_X3WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_X3WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_X3WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_X3RAD register **/ +#define MMU_X3RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AXI SRAM3 Read Error Address*/ +#define MMU_X3RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_X3RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_X3RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_X3RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_X3RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_X3RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_X3RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_X3RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_X3RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_X3RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_X3RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_X3RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_X3RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_X3RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_X3RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_X3RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_X3RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_X3RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_X3RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_X3RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_X3RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_X3RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_X3RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_X3RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_X3RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_X3RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_X3RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_X3RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_X3RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_X3RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_X3RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_X3RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H1WD register **/ +#define MMU_H1WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM1 Master ID*/ +#define MMU_H1WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H1WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H1WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H1WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H1WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM1 UID*/ +#define MMU_H1WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H1WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H1WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H1WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H1WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H1WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H1WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H1WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H1RD register **/ +#define MMU_H1RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM1 Master ID*/ +#define MMU_H1RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H1RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H1RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H1RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H1RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM1 UID*/ +#define MMU_H1RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H1RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H1RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H1RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H1RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H1RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H1RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H1RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H1WAD register **/ +#define MMU_H1WAD_ADDDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM1 Write Error Address*/ +#define MMU_H1WAD_ADDDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H1WAD_ADDDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H1WAD_ADDDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H1WAD_ADDDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H1WAD_ADDDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H1WAD_ADDDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H1WAD_ADDDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H1WAD_ADDDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H1WAD_ADDDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H1WAD_ADDDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H1WAD_ADDDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H1WAD_ADDDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H1WAD_ADDDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H1WAD_ADDDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H1WAD_ADDDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H1WAD_ADDDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H1WAD_ADDDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H1WAD_ADDDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H1WAD_ADDDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H1WAD_ADDDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H1WAD_ADDDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H1WAD_ADDDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H1WAD_ADDDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H1WAD_ADDDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H1WAD_ADDDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H1WAD_ADDDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H1WAD_ADDDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H1WAD_ADDDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H1WAD_ADDDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H1WAD_ADDDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H1WAD_ADDDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H1WAD_ADDDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H1RAD register **/ +#define MMU_H1RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM1 Read Error Address*/ +#define MMU_H1RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H1RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H1RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H1RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H1RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H1RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H1RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H1RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H1RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H1RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H1RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H1RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H1RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H1RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H1RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H1RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H1RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H1RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H1RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H1RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H1RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H1RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H1RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H1RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H1RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H1RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H1RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H1RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H1RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H1RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H1RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H1RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H2WD register **/ +#define MMU_H2WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM2 Master ID*/ +#define MMU_H2WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H2WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H2WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H2WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H2WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM2 UID*/ +#define MMU_H2WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H2WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H2WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H2WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H2WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H2WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H2WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H2WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H2RD register **/ +#define MMU_H2RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM2 Master ID*/ +#define MMU_H2RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H2RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H2RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H2RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H2RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM2 UID*/ +#define MMU_H2RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H2RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H2RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H2RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H2RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H2RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H2RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H2RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H2WAD register **/ +#define MMU_H2WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM2 Write Error Address*/ +#define MMU_H2WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H2WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H2WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H2WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H2WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H2WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H2WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H2WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H2WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H2WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H2WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H2WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H2WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H2WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H2WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H2WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H2WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H2WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H2WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H2WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H2WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H2WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H2WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H2WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H2WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H2WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H2WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H2WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H2WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H2WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H2WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H2WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H2RAD register **/ +#define MMU_H2RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM2 Read Error Address*/ +#define MMU_H2RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H2RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H2RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H2RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H2RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H2RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H2RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H2RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H2RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H2RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H2RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H2RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H2RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H2RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H2RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H2RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H2RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H2RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H2RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H2RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H2RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H2RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H2RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H2RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H2RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H2RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H2RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H2RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H2RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H2RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H2RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H2RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H3WD register **/ +#define MMU_H3WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM3 Master ID*/ +#define MMU_H3WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H3WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H3WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H3WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H3WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM3 UID*/ +#define MMU_H3WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H3WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H3WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H3WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H3WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H3WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H3WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H3WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H3RD register **/ +#define MMU_H3RD_ID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM3 Master ID*/ +#define MMU_H3RD_ID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H3RD_ID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H3RD_ID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H3RD_ID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H3RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM3 UID*/ +#define MMU_H3RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H3RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H3RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H3RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H3RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H3RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H3RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H3RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H3WAD register **/ +#define MMU_H3WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM3 Write Error Address*/ +#define MMU_H3WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H3WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H3WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H3WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H3WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H3WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H3WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H3WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H3WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H3WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H3WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H3WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H3WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H3WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H3WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H3WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H3WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H3WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H3WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H3WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H3WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H3WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H3WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H3WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H3WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H3WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H3WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H3WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H3WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H3WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H3WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H3WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H3RAD register **/ +#define MMU_H3RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM3 Read Error Address*/ +#define MMU_H3RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H3RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H3RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H3RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H3RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H3RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H3RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H3RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H3RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H3RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H3RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H3RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H3RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H3RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H3RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H3RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H3RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H3RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H3RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H3RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H3RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H3RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H3RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H3RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H3RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H3RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H3RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H3RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H3RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H3RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H3RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H3RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H4WD register **/ +#define MMU_H4WD_ID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM4 Master ID*/ +#define MMU_H4WD_ID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H4WD_ID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H4WD_ID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H4WD_ID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H4WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM4 UID*/ +#define MMU_H4WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H4WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H4WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H4WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H4WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H4WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H4WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H4WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H4RD register **/ +#define MMU_H4RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM4 Master ID*/ +#define MMU_H4RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H4RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H4RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H4RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H4RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM4 UID*/ +#define MMU_H4RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H4RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H4RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H4RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H4RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H4RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H4RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H4RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H4WAD register **/ +#define MMU_H4WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM4 Write Error Address*/ +#define MMU_H4WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H4WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H4WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H4WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H4WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H4WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H4WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H4WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H4WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H4WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H4WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H4WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H4WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H4WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H4WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H4WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H4WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H4WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H4WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H4WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H4WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H4WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H4WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H4WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H4WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H4WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H4WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H4WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H4WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H4WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H4WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H4WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H4RAD register **/ +#define MMU_H4RAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM4 Read Error Address*/ +#define MMU_H4RAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H4RAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H4RAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H4RAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H4RAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H4RAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H4RAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H4RAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H4RAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H4RAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H4RAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H4RAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H4RAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H4RAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H4RAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H4RAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H4RAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H4RAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H4RAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H4RAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H4RAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H4RAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H4RAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H4RAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H4RAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H4RAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H4RAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H4RAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H4RAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H4RAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H4RAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H4RAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_H5WD register **/ +#define MMU_H5WD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM5 Master ID*/ +#define MMU_H5WD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H5WD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H5WD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H5WD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H5WD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM5 UID*/ +#define MMU_H5WD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H5WD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H5WD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H5WD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H5WD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H5WD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H5WD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H5WD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H5RD register **/ +#define MMU_H5RD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] AHB SRAM5 Master ID*/ +#define MMU_H5RD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H5RD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H5RD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H5RD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H5RD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] AHB SRAM5 UID*/ +#define MMU_H5RD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H5RD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H5RD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H5RD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H5RD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H5RD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H5RD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H5RD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_H5WAD register **/ +#define MMU_H5WAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] AHB SRAM5 Read Error Address*/ +#define MMU_H5WAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_H5WAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_H5WAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_H5WAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_H5WAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_H5WAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_H5WAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_H5WAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_H5WAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_H5WAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_H5WAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_H5WAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_H5WAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_H5WAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_H5WAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_H5WAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_H5WAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_H5WAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_H5WAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_H5WAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_H5WAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_H5WAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_H5WAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_H5WAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_H5WAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_H5WAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_H5WAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_H5WAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_H5WAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_H5WAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_H5WAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_H5WAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_BKWD register **/ +#define MMU_BKWD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] Backup SRAM Master ID*/ +#define MMU_BKWD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_BKWD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_BKWD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_BKWD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_BKWD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] Backup SRAM UID*/ +#define MMU_BKWD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_BKWD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_BKWD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_BKWD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_BKWD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_BKWD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_BKWD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_BKWD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_BKRD register **/ +#define MMU_BKRD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] Backup SRAM Master ID*/ +#define MMU_BKRD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_BKRD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_BKRD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_BKRD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_BKRD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] Backup SRAM UID*/ +#define MMU_BKRD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_BKRD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_BKRD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_BKRD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_BKRD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_BKRD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_BKRD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_BKRD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_BKWAD register **/ +#define MMU_BKWAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Backup SRAM Write Error Address*/ +#define MMU_BKWAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_BKWAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_BKWAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_BKWAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_BKWAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_BKWAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_BKWAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_BKWAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_BKWAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_BKWAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_BKWAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_BKWAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_BKWAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_BKWAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_BKWAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_BKWAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_BKWAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_BKWAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_BKWAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_BKWAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_BKWAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_BKWAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_BKWAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_BKWAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_BKWAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_BKWAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_BKWAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_BKWAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_BKWAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_BKWAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_BKWAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_BKWAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_BKRAD register **/ +#define MMU_BKRAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] Backup SRAM Read Error Address*/ +#define MMU_BKRAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_BKRAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_BKRAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_BKRAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_BKRAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_BKRAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_BKRAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_BKRAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_BKRAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_BKRAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_BKRAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_BKRAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_BKRAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_BKRAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_BKRAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_BKRAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_BKRAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_BKRAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_BKRAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_BKRAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_BKRAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_BKRAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_BKRAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_BKRAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_BKRAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_BKRAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_BKRAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_BKRAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_BKRAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_BKRAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_BKRAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_BKRAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_ITWD register **/ +#define MMU_ITWD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] ITCM Master ID*/ +#define MMU_ITWD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_ITWD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_ITWD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_ITWD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_ITWD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] ITCM UID*/ +#define MMU_ITWD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_ITWD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_ITWD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_ITWD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_ITWD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_ITWD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_ITWD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_ITWD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_ITRD register **/ +#define MMU_ITRD_MID ((uint32_t)0x00000F00U) /* Bit[11:8] ITCM Master ID*/ +#define MMU_ITRD_MID_0 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_ITRD_MID_1 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_ITRD_MID_2 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_ITRD_MID_3 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_ITRD_UID ((uint32_t)0x000000FFU) /* Bit[7:0] ITCM UID*/ +#define MMU_ITRD_UID_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_ITRD_UID_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_ITRD_UID_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_ITRD_UID_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_ITRD_UID_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_ITRD_UID_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_ITRD_UID_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_ITRD_UID_7 ((uint32_t)0x00000080U) /* Bit7*/ + +/** Bit definition for MMU_ITWAD register **/ +#define MMU_ITWAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] ITCM Write Error Address*/ +#define MMU_ITWAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_ITWAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_ITWAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_ITWAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_ITWAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_ITWAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_ITWAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_ITWAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_ITWAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_ITWAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_ITWAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_ITWAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_ITWAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_ITWAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_ITWAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_ITWAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_ITWAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_ITWAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_ITWAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_ITWAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_ITWAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_ITWAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_ITWAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_ITWAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_ITWAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_ITWAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_ITWAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_ITWAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_ITWAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_ITWAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_ITWAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_ITWAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + +/** Bit definition for MMU_ITRAD register **/ +#define MMU_ITRAD_ADDR ((uint32_t)0xFFFFFFFFU) /* Bit[31:0] ITCM Read Error Address*/ +#define MMU_ITRAD_ADDR_0 ((uint32_t)0x00000001U) /* Bit0*/ +#define MMU_ITRAD_ADDR_1 ((uint32_t)0x00000002U) /* Bit1*/ +#define MMU_ITRAD_ADDR_2 ((uint32_t)0x00000004U) /* Bit2*/ +#define MMU_ITRAD_ADDR_3 ((uint32_t)0x00000008U) /* Bit3*/ +#define MMU_ITRAD_ADDR_4 ((uint32_t)0x00000010U) /* Bit4*/ +#define MMU_ITRAD_ADDR_5 ((uint32_t)0x00000020U) /* Bit5*/ +#define MMU_ITRAD_ADDR_6 ((uint32_t)0x00000040U) /* Bit6*/ +#define MMU_ITRAD_ADDR_7 ((uint32_t)0x00000080U) /* Bit7*/ +#define MMU_ITRAD_ADDR_8 ((uint32_t)0x00000100U) /* Bit8*/ +#define MMU_ITRAD_ADDR_9 ((uint32_t)0x00000200U) /* Bit9*/ +#define MMU_ITRAD_ADDR_10 ((uint32_t)0x00000400U) /* Bit10*/ +#define MMU_ITRAD_ADDR_11 ((uint32_t)0x00000800U) /* Bit11*/ +#define MMU_ITRAD_ADDR_12 ((uint32_t)0x00001000U) /* Bit12*/ +#define MMU_ITRAD_ADDR_13 ((uint32_t)0x00002000U) /* Bit13*/ +#define MMU_ITRAD_ADDR_14 ((uint32_t)0x00004000U) /* Bit14*/ +#define MMU_ITRAD_ADDR_15 ((uint32_t)0x00008000U) /* Bit15*/ +#define MMU_ITRAD_ADDR_16 ((uint32_t)0x00010000U) /* Bit16*/ +#define MMU_ITRAD_ADDR_17 ((uint32_t)0x00020000U) /* Bit17*/ +#define MMU_ITRAD_ADDR_18 ((uint32_t)0x00040000U) /* Bit18*/ +#define MMU_ITRAD_ADDR_19 ((uint32_t)0x00080000U) /* Bit19*/ +#define MMU_ITRAD_ADDR_20 ((uint32_t)0x00100000U) /* Bit20*/ +#define MMU_ITRAD_ADDR_21 ((uint32_t)0x00200000U) /* Bit21*/ +#define MMU_ITRAD_ADDR_22 ((uint32_t)0x00400000U) /* Bit22*/ +#define MMU_ITRAD_ADDR_23 ((uint32_t)0x00800000U) /* Bit23*/ +#define MMU_ITRAD_ADDR_24 ((uint32_t)0x01000000U) /* Bit24*/ +#define MMU_ITRAD_ADDR_25 ((uint32_t)0x02000000U) /* Bit25*/ +#define MMU_ITRAD_ADDR_26 ((uint32_t)0x04000000U) /* Bit26*/ +#define MMU_ITRAD_ADDR_27 ((uint32_t)0x08000000U) /* Bit27*/ +#define MMU_ITRAD_ADDR_28 ((uint32_t)0x10000000U) /* Bit28*/ +#define MMU_ITRAD_ADDR_29 ((uint32_t)0x20000000U) /* Bit29*/ +#define MMU_ITRAD_ADDR_30 ((uint32_t)0x40000000U) /* Bit30*/ +#define MMU_ITRAD_ADDR_31 ((uint32_t)0x80000000U) /* Bit31*/ + + +/** Bit Offset register **/ +#define REG_BIT0_OFFSET ((uint32_t)0x00000000U) +#define REG_BIT1_OFFSET ((uint32_t)0x00000001U) +#define REG_BIT2_OFFSET ((uint32_t)0x00000002U) +#define REG_BIT3_OFFSET ((uint32_t)0x00000003U) +#define REG_BIT4_OFFSET ((uint32_t)0x00000004U) +#define REG_BIT5_OFFSET ((uint32_t)0x00000005U) +#define REG_BIT6_OFFSET ((uint32_t)0x00000006U) +#define REG_BIT7_OFFSET ((uint32_t)0x00000007U) +#define REG_BIT8_OFFSET ((uint32_t)0x00000008U) +#define REG_BIT9_OFFSET ((uint32_t)0x00000009U) +#define REG_BIT10_OFFSET ((uint32_t)0x0000000AU) +#define REG_BIT11_OFFSET ((uint32_t)0x0000000BU) +#define REG_BIT12_OFFSET ((uint32_t)0x0000000CU) +#define REG_BIT13_OFFSET ((uint32_t)0x0000000DU) +#define REG_BIT14_OFFSET ((uint32_t)0x0000000EU) +#define REG_BIT15_OFFSET ((uint32_t)0x0000000FU) +#define REG_BIT16_OFFSET ((uint32_t)0x00000010U) +#define REG_BIT17_OFFSET ((uint32_t)0x00000011U) +#define REG_BIT18_OFFSET ((uint32_t)0x00000012U) +#define REG_BIT19_OFFSET ((uint32_t)0x00000013U) +#define REG_BIT20_OFFSET ((uint32_t)0x00000014U) +#define REG_BIT21_OFFSET ((uint32_t)0x00000015U) +#define REG_BIT22_OFFSET ((uint32_t)0x00000016U) +#define REG_BIT23_OFFSET ((uint32_t)0x00000017U) +#define REG_BIT24_OFFSET ((uint32_t)0x00000018U) +#define REG_BIT25_OFFSET ((uint32_t)0x00000019U) +#define REG_BIT26_OFFSET ((uint32_t)0x0000001AU) +#define REG_BIT27_OFFSET ((uint32_t)0x0000001BU) +#define REG_BIT28_OFFSET ((uint32_t)0x0000001CU) +#define REG_BIT29_OFFSET ((uint32_t)0x0000001DU) +#define REG_BIT30_OFFSET ((uint32_t)0x0000001EU) +#define REG_BIT31_OFFSET ((uint32_t)0x0000001FU) + + +/*** Exported_macro ***/ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +#define DWT_CR (*(__IO uint32_t *)0xE0001000U) +#define DWT_CYCCNT (*(__IO uint32_t *)0xE0001004U) +#define DEM_CR (*(__IO uint32_t *)0xE000EDFCU) +#define DEM_CR_TRCENA ((uint32_t)0x01000000U) +#define DWT_CR_CYCCNTENA ((uint32_t)0x00000001U) + +#define CPU_DELAY_INTI() do{ \ + /* Enable DWT*/ \ + DEM_CR |= DEM_CR_TRCENA; \ + /* Clear DWT CYCCNT*/ \ + DWT_CYCCNT = 0U; \ + /* Enable DWT CYCCNT*/ \ + DWT_CR |= DWT_CR_CYCCNTENA; \ + }while(0) + +#define CPU_DELAY_DISABLE() do{ \ + /* Disable DWT*/ \ + DEM_CR &= (uint32_t)(~(uint32_t)DEM_CR_TRCENA); \ + }while(0) + + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h76x.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h76x.s new file mode 100644 index 0000000000..1b1e020258 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h76x.s @@ -0,0 +1,892 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + +Stack_Size EQU 0x200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; Reserved + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_IRQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +N32SysTick_Handler PROC + EXPORT N32SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG1_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel0_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA3_Channel0_IRQHandler [WEAK] + EXPORT DMA3_Channel1_IRQHandler [WEAK] + EXPORT DMA3_Channel2_IRQHandler [WEAK] + EXPORT DMA3_Channel3_IRQHandler [WEAK] + EXPORT DMA3_Channel4_IRQHandler [WEAK] + EXPORT DMA3_Channel5_IRQHandler [WEAK] + EXPORT DMA3_Channel6_IRQHandler [WEAK] + EXPORT DMA3_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel0_IRQHandler [WEAK] + EXPORT MDMA_Channel1_IRQHandler [WEAK] + EXPORT MDMA_Channel2_IRQHandler [WEAK] + EXPORT MDMA_Channel3_IRQHandler [WEAK] + EXPORT MDMA_Channel4_IRQHandler [WEAK] + EXPORT MDMA_Channel5_IRQHandler [WEAK] + EXPORT MDMA_Channel6_IRQHandler [WEAK] + EXPORT MDMA_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel8_IRQHandler [WEAK] + EXPORT MDMA_Channel9_IRQHandler [WEAK] + EXPORT MDMA_Channel10_IRQHandler [WEAK] + EXPORT MDMA_Channel11_IRQHandler [WEAK] + EXPORT MDMA_Channel12_IRQHandler [WEAK] + EXPORT MDMA_Channel13_IRQHandler [WEAK] + EXPORT MDMA_Channel14_IRQHandler [WEAK] + EXPORT MDMA_Channel15_IRQHandler [WEAK] + EXPORT SDPU_IRQHandler [WEAK] + EXPORT FPU_CPU1_IRQHandler [WEAK] + EXPORT ECCMON_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT I2C6_EV_IRQHandler [WEAK] + EXPORT I2C6_ER_IRQHandler [WEAK] + EXPORT I2C7_EV_IRQHandler [WEAK] + EXPORT I2C7_ER_IRQHandler [WEAK] + EXPORT I2C8_EV_IRQHandler [WEAK] + EXPORT I2C8_ER_IRQHandler [WEAK] + EXPORT I2C9_EV_IRQHandler [WEAK] + EXPORT I2C9_ER_IRQHandler [WEAK] + EXPORT I2C10_EV_IRQHandler [WEAK] + EXPORT I2C10_ER_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT I2S4_IRQHandler [WEAK] + EXPORT xSPI1_IRQHandler [WEAK] + EXPORT xSPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT LCD_EV_IRQHandler [WEAK] + EXPORT LCD_ER_IRQHandler [WEAK] + EXPORT DVP1_IRQHandler [WEAK] + EXPORT DVP2_IRQHandler [WEAK] + EXPORT DMAMUX2_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB1_HS_WKUP_IRQHandler [WEAK] + EXPORT USB1_HS_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB2_HS_WKUP_IRQHandler [WEAK] + EXPORT USB2_HS_IRQHandler [WEAK] + EXPORT ETH1_IRQHandler [WEAK] + EXPORT ETH1_PMT_LPI_IRQHandler [WEAK] + EXPORT ETH2_IRQHandler [WEAK] + EXPORT ETH2_PMT_LPI_IRQHandler [WEAK] + EXPORT FDCAN1_INT0_IRQHandler [WEAK] + EXPORT FDCAN2_INT0_IRQHandler [WEAK] + EXPORT FDCAN3_INT0_IRQHandler [WEAK] + EXPORT FDCAN4_INT0_IRQHandler [WEAK] + EXPORT FDCAN1_INT1_IRQHandler [WEAK] + EXPORT FDCAN2_INT1_IRQHandler [WEAK] + EXPORT FDCAN3_INT1_IRQHandler [WEAK] + EXPORT FDCAN4_INT1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPUART2_IRQHandler [WEAK] + EXPORT GPU_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT COMP1_2_IRQHandler [WEAK] + EXPORT COMP3_4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT1_IRQHandler [WEAK] + EXPORT SHRTIM1_INT2_IRQHandler [WEAK] + EXPORT SHRTIM1_INT3_IRQHandler [WEAK] + EXPORT SHRTIM1_INT4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT5_IRQHandler [WEAK] + EXPORT SHRTIM1_INT6_IRQHandler [WEAK] + EXPORT SHRTIM1_INT7_IRQHandler [WEAK] + EXPORT SHRTIM1_INT8_IRQHandler [WEAK] + EXPORT SHRTIM2_INT1_IRQHandler [WEAK] + EXPORT SHRTIM2_INT2_IRQHandler [WEAK] + EXPORT SHRTIM2_INT3_IRQHandler [WEAK] + EXPORT SHRTIM2_INT4_IRQHandler [WEAK] + EXPORT SHRTIM2_INT5_IRQHandler [WEAK] + EXPORT SHRTIM2_INT6_IRQHandler [WEAK] + EXPORT SHRTIM2_INT7_IRQHandler [WEAK] + EXPORT SHRTIM2_INT8_IRQHandler [WEAK] + EXPORT FDCAN5_INT0_IRQHandler [WEAK] + EXPORT FDCAN6_INT0_IRQHandler [WEAK] + EXPORT FDCAN7_INT0_IRQHandler [WEAK] + EXPORT FDCAN8_INT0_IRQHandler [WEAK] + EXPORT FDCAN5_INT1_IRQHandler [WEAK] + EXPORT FDCAN6_INT1_IRQHandler [WEAK] + EXPORT FDCAN7_INT1_IRQHandler [WEAK] + EXPORT FDCAN8_INT1_IRQHandler [WEAK] + EXPORT LPTIM5_WKUP_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_H2P_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_P2H_IRQHandler [WEAK] + EXPORT WAKEUP_IO_IRQHandler [WEAK] + EXPORT SEMA4_INT1_IRQHandler [WEAK] + EXPORT WWDG2_RST_IRQHandler [WEAK] + EXPORT OTPC_IRQHandler [WEAK] + EXPORT FEMC_IRQHandler [WEAK] + EXPORT DCMUB_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT MDMA_AHBS_ER_IRQHandler [WEAK] + EXPORT CM7_CATCH_READ_ER_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT DAC4_IRQHandler [WEAK] + EXPORT EMC_IRQHandler [WEAK] + EXPORT DAC5_IRQHandler [WEAK] + EXPORT DAC6_IRQHandler [WEAK] + EXPORT ESC_OPB_IRQHandler [WEAK] + EXPORT ESC_SYNC0_IRQHandler [WEAK] + EXPORT ESC_SYNC1_IRQHandler [WEAK] + EXPORT ESC_WRP_IRQHandler [WEAK] + EXPORT ATIM1_BRK_IRQHandler [WEAK] + EXPORT ATIM1_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM1_CC_IRQHandler [WEAK] + EXPORT ATIM1_UP_IRQHandler [WEAK] + EXPORT ATIM2_BRK_IRQHandler [WEAK] + EXPORT ATIM2_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM2_CC_IRQHandler [WEAK] + EXPORT ATIM2_UP_IRQHandler [WEAK] + EXPORT ATIM3_BRK_IRQHandler [WEAK] + EXPORT ATIM3_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM3_CC_IRQHandler [WEAK] + EXPORT ATIM3_UP_IRQHandler [WEAK] + EXPORT ATIM4_BRK_IRQHandler [WEAK] + EXPORT ATIM4_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM4_CC_IRQHandler [WEAK] + EXPORT ATIM4_UP_IRQHandler [WEAK] + EXPORT GTIMA1_IRQHandler [WEAK] + EXPORT GTIMA2_IRQHandler [WEAK] + EXPORT GTIMA3_IRQHandler [WEAK] + EXPORT GTIMA4_IRQHandler [WEAK] + EXPORT GTIMA5_IRQHandler [WEAK] + EXPORT GTIMA6_IRQHandler [WEAK] + EXPORT GTIMA7_IRQHandler [WEAK] + EXPORT GTIMB1_IRQHandler [WEAK] + EXPORT GTIMB2_IRQHandler [WEAK] + EXPORT GTIMB3_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT BTIM4_IRQHandler [WEAK] + EXPORT LPTIM1_WKUP_IRQHandler [WEAK] + EXPORT LPTIM2_WKUP_IRQHandler [WEAK] + EXPORT LPTIM3_WKUP_IRQHandler [WEAK] + EXPORT LPTIM4_WKUP_IRQHandler [WEAK] + EXPORT DSMU_FLT0_IRQHandler [WEAK] + EXPORT DSMU_FLT1_IRQHandler [WEAK] + EXPORT DSMU_FLT2_IRQHandler [WEAK] + EXPORT DSMU_FLT3_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT DMAMUX1_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT SysTick_Handler [WEAK] + +WWDG1_IRQHandler +PVD_IRQHandler +RTC_TAMPER_IRQHandler +RTC_WKUP_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI9_5_IRQHandler +EXTI15_10_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +DMA2_Channel0_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA3_Channel0_IRQHandler +DMA3_Channel1_IRQHandler +DMA3_Channel2_IRQHandler +DMA3_Channel3_IRQHandler +DMA3_Channel4_IRQHandler +DMA3_Channel5_IRQHandler +DMA3_Channel6_IRQHandler +DMA3_Channel7_IRQHandler +MDMA_Channel0_IRQHandler +MDMA_Channel1_IRQHandler +MDMA_Channel2_IRQHandler +MDMA_Channel3_IRQHandler +MDMA_Channel4_IRQHandler +MDMA_Channel5_IRQHandler +MDMA_Channel6_IRQHandler +MDMA_Channel7_IRQHandler +MDMA_Channel8_IRQHandler +MDMA_Channel9_IRQHandler +MDMA_Channel10_IRQHandler +MDMA_Channel11_IRQHandler +MDMA_Channel12_IRQHandler +MDMA_Channel13_IRQHandler +MDMA_Channel14_IRQHandler +MDMA_Channel15_IRQHandler +SDPU_IRQHandler +FPU_CPU1_IRQHandler +ECCMON_IRQHandler +RTC_ALARM_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +I2C6_EV_IRQHandler +I2C6_ER_IRQHandler +I2C7_EV_IRQHandler +I2C7_ER_IRQHandler +I2C8_EV_IRQHandler +I2C8_ER_IRQHandler +I2C9_EV_IRQHandler +I2C9_ER_IRQHandler +I2C10_EV_IRQHandler +I2C10_ER_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +I2S3_IRQHandler +I2S4_IRQHandler +xSPI1_IRQHandler +xSPI2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SPI7_IRQHandler +LCD_EV_IRQHandler +LCD_ER_IRQHandler +DVP1_IRQHandler +DVP2_IRQHandler +DMAMUX2_IRQHandler +USB1_HS_EPx_OUT_IRQHandler +USB1_HS_EPx_IN_IRQHandler +USB1_HS_WKUP_IRQHandler +USB1_HS_IRQHandler +USB2_HS_EPx_OUT_IRQHandler +USB2_HS_EPx_IN_IRQHandler +USB2_HS_WKUP_IRQHandler +USB2_HS_IRQHandler +ETH1_IRQHandler +ETH1_PMT_LPI_IRQHandler +ETH2_IRQHandler +ETH2_PMT_LPI_IRQHandler +FDCAN1_INT0_IRQHandler +FDCAN2_INT0_IRQHandler +FDCAN3_INT0_IRQHandler +FDCAN4_INT0_IRQHandler +FDCAN1_INT1_IRQHandler +FDCAN2_INT1_IRQHandler +FDCAN3_INT1_IRQHandler +FDCAN4_INT1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +LPUART1_IRQHandler +LPUART2_IRQHandler +GPU_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +ADC3_IRQHandler +COMP1_2_IRQHandler +COMP3_4_IRQHandler +SHRTIM1_INT1_IRQHandler +SHRTIM1_INT2_IRQHandler +SHRTIM1_INT3_IRQHandler +SHRTIM1_INT4_IRQHandler +SHRTIM1_INT5_IRQHandler +SHRTIM1_INT6_IRQHandler +SHRTIM1_INT7_IRQHandler +SHRTIM1_INT8_IRQHandler +SHRTIM2_INT1_IRQHandler +SHRTIM2_INT2_IRQHandler +SHRTIM2_INT3_IRQHandler +SHRTIM2_INT4_IRQHandler +SHRTIM2_INT5_IRQHandler +SHRTIM2_INT6_IRQHandler +SHRTIM2_INT7_IRQHandler +SHRTIM2_INT8_IRQHandler +FDCAN5_INT0_IRQHandler +FDCAN6_INT0_IRQHandler +FDCAN7_INT0_IRQHandler +FDCAN8_INT0_IRQHandler +FDCAN5_INT1_IRQHandler +FDCAN6_INT1_IRQHandler +FDCAN7_INT1_IRQHandler +FDCAN8_INT1_IRQHandler +LPTIM5_WKUP_IRQHandler +JPEG_SGDMA_H2P_IRQHandler +JPEG_SGDMA_P2H_IRQHandler +WAKEUP_IO_IRQHandler +SEMA4_INT1_IRQHandler +WWDG2_RST_IRQHandler +OTPC_IRQHandler +FEMC_IRQHandler +DCMUB_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +MDMA_AHBS_ER_IRQHandler +CM7_CATCH_READ_ER_IRQHandler +DAC3_IRQHandler +DAC4_IRQHandler +EMC_IRQHandler +DAC5_IRQHandler +DAC6_IRQHandler +ESC_OPB_IRQHandler +ESC_SYNC0_IRQHandler +ESC_SYNC1_IRQHandler +ESC_WRP_IRQHandler +ATIM1_BRK_IRQHandler +ATIM1_TRG_COM_IRQHandler +ATIM1_CC_IRQHandler +ATIM1_UP_IRQHandler +ATIM2_BRK_IRQHandler +ATIM2_TRG_COM_IRQHandler +ATIM2_CC_IRQHandler +ATIM2_UP_IRQHandler +ATIM3_BRK_IRQHandler +ATIM3_TRG_COM_IRQHandler +ATIM3_CC_IRQHandler +ATIM3_UP_IRQHandler +ATIM4_BRK_IRQHandler +ATIM4_TRG_COM_IRQHandler +ATIM4_CC_IRQHandler +ATIM4_UP_IRQHandler +GTIMA1_IRQHandler +GTIMA2_IRQHandler +GTIMA3_IRQHandler +GTIMA4_IRQHandler +GTIMA5_IRQHandler +GTIMA6_IRQHandler +GTIMA7_IRQHandler +GTIMB1_IRQHandler +GTIMB2_IRQHandler +GTIMB3_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +BTIM4_IRQHandler +LPTIM1_WKUP_IRQHandler +LPTIM2_WKUP_IRQHandler +LPTIM3_WKUP_IRQHandler +LPTIM4_WKUP_IRQHandler +DSMU_FLT0_IRQHandler +DSMU_FLT1_IRQHandler +DSMU_FLT2_IRQHandler +DSMU_FLT3_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +DMAMUX1_IRQHandler +MMU_IRQHandler +SysTick_Handler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h76x_EWARM.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h76x_EWARM.s new file mode 100644 index 0000000000..3c72ea193e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h76x_EWARM.s @@ -0,0 +1,1529 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + + __iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; Reserved + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_RQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + ;need check to user manual of exti chapter + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK N32SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +N32SysTick_Handler + B N32SysTick_Handler + + PUBWEAK WWDG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG1_IRQHandler + B WWDG1_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_TAMPER_IRQHandler + B RTC_TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK DMA2_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel0_IRQHandler + B DMA2_Channel0_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA3_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel0_IRQHandler + B DMA3_Channel0_IRQHandler + + PUBWEAK DMA3_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel1_IRQHandler + B DMA3_Channel1_IRQHandler + + PUBWEAK DMA3_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel2_IRQHandler + B DMA3_Channel2_IRQHandler + + PUBWEAK DMA3_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel3_IRQHandler + B DMA3_Channel3_IRQHandler + + PUBWEAK DMA3_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel4_IRQHandler + B DMA3_Channel4_IRQHandler + + PUBWEAK DMA3_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel5_IRQHandler + B DMA3_Channel5_IRQHandler + + PUBWEAK DMA3_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel6_IRQHandler + B DMA3_Channel6_IRQHandler + + PUBWEAK DMA3_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel7_IRQHandler + B DMA3_Channel7_IRQHandler + + PUBWEAK MDMA_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel0_IRQHandler + B MDMA_Channel0_IRQHandler + + PUBWEAK MDMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel1_IRQHandler + B MDMA_Channel1_IRQHandler + + PUBWEAK MDMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel2_IRQHandler + B MDMA_Channel2_IRQHandler + + PUBWEAK MDMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel3_IRQHandler + B MDMA_Channel3_IRQHandler + + PUBWEAK MDMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel4_IRQHandler + B MDMA_Channel4_IRQHandler + + PUBWEAK MDMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel5_IRQHandler + B MDMA_Channel5_IRQHandler + + PUBWEAK MDMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel6_IRQHandler + B MDMA_Channel6_IRQHandler + + PUBWEAK MDMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel7_IRQHandler + B MDMA_Channel7_IRQHandler + + PUBWEAK MDMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel8_IRQHandler + B MDMA_Channel8_IRQHandler + + PUBWEAK MDMA_Channel9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel9_IRQHandler + B MDMA_Channel9_IRQHandler + + PUBWEAK MDMA_Channel10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel10_IRQHandler + B MDMA_Channel10_IRQHandler + + PUBWEAK MDMA_Channel11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel11_IRQHandler + B MDMA_Channel11_IRQHandler + + PUBWEAK MDMA_Channel12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel12_IRQHandler + B MDMA_Channel12_IRQHandler + + PUBWEAK MDMA_Channel13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel13_IRQHandler + B MDMA_Channel13_IRQHandler + + PUBWEAK MDMA_Channel14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel14_IRQHandler + B MDMA_Channel14_IRQHandler + + PUBWEAK MDMA_Channel15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel15_IRQHandler + B MDMA_Channel15_IRQHandler + + PUBWEAK SDPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDPU_IRQHandler + B SDPU_IRQHandler + + PUBWEAK FPU_CPU1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_CPU1_IRQHandler + B FPU_CPU1_IRQHandler + + PUBWEAK ECCMON_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECCMON_IRQHandler + B ECCMON_IRQHandler + + PUBWEAK RTC_ALARM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_ALARM_IRQHandler + B RTC_ALARM_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK I2C6_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_EV_IRQHandler + B I2C6_EV_IRQHandler + + PUBWEAK I2C6_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_ER_IRQHandler + B I2C6_ER_IRQHandler + + PUBWEAK I2C7_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_EV_IRQHandler + B I2C7_EV_IRQHandler + + PUBWEAK I2C7_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_ER_IRQHandler + B I2C7_ER_IRQHandler + + PUBWEAK I2C8_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_EV_IRQHandler + B I2C8_EV_IRQHandler + + PUBWEAK I2C8_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_ER_IRQHandler + B I2C8_ER_IRQHandler + + PUBWEAK I2C9_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_EV_IRQHandler + B I2C9_EV_IRQHandler + + PUBWEAK I2C9_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_ER_IRQHandler + B I2C9_ER_IRQHandler + + PUBWEAK I2C10_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_EV_IRQHandler + B I2C10_EV_IRQHandler + + PUBWEAK I2C10_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_ER_IRQHandler + B I2C10_ER_IRQHandler + + PUBWEAK I2S1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S1_IRQHandler + B I2S1_IRQHandler + + PUBWEAK I2S2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S2_IRQHandler + B I2S2_IRQHandler + + PUBWEAK I2S3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S3_IRQHandler + B I2S3_IRQHandler + + PUBWEAK I2S4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S4_IRQHandler + B I2S4_IRQHandler + + PUBWEAK xSPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI1_IRQHandler + B xSPI1_IRQHandler + + PUBWEAK xSPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI2_IRQHandler + B xSPI2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SPI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI7_IRQHandler + B SPI7_IRQHandler + + PUBWEAK LCD_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_EV_IRQHandler + B LCD_EV_IRQHandler + + PUBWEAK LCD_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_ER_IRQHandler + B LCD_ER_IRQHandler + + PUBWEAK DVP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP1_IRQHandler + B DVP1_IRQHandler + + PUBWEAK DVP2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP2_IRQHandler + B DVP2_IRQHandler + + PUBWEAK DMAMUX2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX2_IRQHandler + B DMAMUX2_IRQHandler + + PUBWEAK USB1_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_OUT_IRQHandler + B USB1_HS_EPx_OUT_IRQHandler + + PUBWEAK USB1_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_IN_IRQHandler + B USB1_HS_EPx_IN_IRQHandler + + PUBWEAK USB1_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_WKUP_IRQHandler + B USB1_HS_WKUP_IRQHandler + + PUBWEAK USB1_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_IRQHandler + B USB1_HS_IRQHandler + + PUBWEAK USB2_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_OUT_IRQHandler + B USB2_HS_EPx_OUT_IRQHandler + + PUBWEAK USB2_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_IN_IRQHandler + B USB2_HS_EPx_IN_IRQHandler + + PUBWEAK USB2_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_WKUP_IRQHandler + B USB2_HS_WKUP_IRQHandler + + PUBWEAK USB2_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_IRQHandler + B USB2_HS_IRQHandler + + PUBWEAK ETH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_IRQHandler + B ETH1_IRQHandler + + PUBWEAK ETH1_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_PMT_LPI_IRQHandler + B ETH1_PMT_LPI_IRQHandler + + PUBWEAK ETH2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_IRQHandler + B ETH2_IRQHandler + + PUBWEAK ETH2_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_PMT_LPI_IRQHandler + B ETH2_PMT_LPI_IRQHandler + + PUBWEAK FDCAN1_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT0_IRQHandler + B FDCAN1_INT0_IRQHandler + + PUBWEAK FDCAN2_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT0_IRQHandler + B FDCAN2_INT0_IRQHandler + + PUBWEAK FDCAN3_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT0_IRQHandler + B FDCAN3_INT0_IRQHandler + + PUBWEAK FDCAN4_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT0_IRQHandler + B FDCAN4_INT0_IRQHandler + + PUBWEAK FDCAN1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT1_IRQHandler + B FDCAN1_INT1_IRQHandler + + PUBWEAK FDCAN2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT1_IRQHandler + B FDCAN2_INT1_IRQHandler + + PUBWEAK FDCAN3_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT1_IRQHandler + B FDCAN3_INT1_IRQHandler + + PUBWEAK FDCAN4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT1_IRQHandler + B FDCAN4_INT1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK USART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART7_IRQHandler + B USART7_IRQHandler + + PUBWEAK USART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART8_IRQHandler + B USART8_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK UART11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART11_IRQHandler + B UART11_IRQHandler + + PUBWEAK UART12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART12_IRQHandler + B UART12_IRQHandler + + PUBWEAK UART13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART13_IRQHandler + B UART13_IRQHandler + + PUBWEAK UART14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART14_IRQHandler + B UART14_IRQHandler + + PUBWEAK UART15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART15_IRQHandler + B UART15_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPUART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART2_IRQHandler + B LPUART2_IRQHandler + + PUBWEAK GPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPU_IRQHandler + B GPU_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK COMP1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP1_2_IRQHandler + B COMP1_2_IRQHandler + + PUBWEAK COMP3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP3_4_IRQHandler + B COMP3_4_IRQHandler + + PUBWEAK SHRTIM1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT1_IRQHandler + B SHRTIM1_INT1_IRQHandler + + PUBWEAK SHRTIM1_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT2_IRQHandler + B SHRTIM1_INT2_IRQHandler + + PUBWEAK SHRTIM1_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT3_IRQHandler + B SHRTIM1_INT3_IRQHandler + + PUBWEAK SHRTIM1_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT4_IRQHandler + B SHRTIM1_INT4_IRQHandler + + PUBWEAK SHRTIM1_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT5_IRQHandler + B SHRTIM1_INT5_IRQHandler + + PUBWEAK SHRTIM1_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT6_IRQHandler + B SHRTIM1_INT6_IRQHandler + + PUBWEAK SHRTIM1_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT7_IRQHandler + B SHRTIM1_INT7_IRQHandler + + PUBWEAK SHRTIM1_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT8_IRQHandler + B SHRTIM1_INT8_IRQHandler + + PUBWEAK SHRTIM2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT1_IRQHandler + B SHRTIM2_INT1_IRQHandler + + PUBWEAK SHRTIM2_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT2_IRQHandler + B SHRTIM2_INT2_IRQHandler + + PUBWEAK SHRTIM2_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT3_IRQHandler + B SHRTIM2_INT3_IRQHandler + + PUBWEAK SHRTIM2_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT4_IRQHandler + B SHRTIM2_INT4_IRQHandler + + PUBWEAK SHRTIM2_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT5_IRQHandler + B SHRTIM2_INT5_IRQHandler + + PUBWEAK SHRTIM2_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT6_IRQHandler + B SHRTIM2_INT6_IRQHandler + + PUBWEAK SHRTIM2_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT7_IRQHandler + B SHRTIM2_INT7_IRQHandler + + PUBWEAK SHRTIM2_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT8_IRQHandler + B SHRTIM2_INT8_IRQHandler + + PUBWEAK FDCAN5_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT0_IRQHandler + B FDCAN5_INT0_IRQHandler + + PUBWEAK FDCAN6_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT0_IRQHandler + B FDCAN6_INT0_IRQHandler + + PUBWEAK FDCAN7_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT0_IRQHandler + B FDCAN7_INT0_IRQHandler + + PUBWEAK FDCAN8_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT0_IRQHandler + B FDCAN8_INT0_IRQHandler + + PUBWEAK FDCAN5_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT1_IRQHandler + B FDCAN5_INT1_IRQHandler + + PUBWEAK FDCAN6_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT1_IRQHandler + B FDCAN6_INT1_IRQHandler + + PUBWEAK FDCAN7_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT1_IRQHandler + B FDCAN7_INT1_IRQHandler + + PUBWEAK FDCAN8_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT1_IRQHandler + B FDCAN8_INT1_IRQHandler + + PUBWEAK LPTIM5_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM5_WKUP_IRQHandler + B LPTIM5_WKUP_IRQHandler + + PUBWEAK JPEG_SGDMA_H2P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_H2P_IRQHandler + B JPEG_SGDMA_H2P_IRQHandler + + PUBWEAK JPEG_SGDMA_P2H_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_P2H_IRQHandler + B JPEG_SGDMA_P2H_IRQHandler + + PUBWEAK WAKEUP_IO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WAKEUP_IO_IRQHandler + B WAKEUP_IO_IRQHandler + + PUBWEAK SEMA4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_INT1_IRQHandler + B SEMA4_INT1_IRQHandler + + PUBWEAK WWDG2_RST_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_RST_IRQHandler + B WWDG2_RST_IRQHandler + + PUBWEAK OTPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTPC_IRQHandler + B OTPC_IRQHandler + + PUBWEAK FEMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FEMC_IRQHandler + B FEMC_IRQHandler + + PUBWEAK DCMUB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMUB_IRQHandler + B DCMUB_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK MDMA_AHBS_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_AHBS_ER_IRQHandler + B MDMA_AHBS_ER_IRQHandler + + PUBWEAK CM7_CATCH_READ_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CM7_CATCH_READ_ER_IRQHandler + B CM7_CATCH_READ_ER_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK DAC4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC4_IRQHandler + B DAC4_IRQHandler + + PUBWEAK EMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMC_IRQHandler + B EMC_IRQHandler + + PUBWEAK DAC5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC5_IRQHandler + B DAC5_IRQHandler + + PUBWEAK DAC6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC6_IRQHandler + B DAC6_IRQHandler + + PUBWEAK ESC_OPB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_OPB_IRQHandler + B ESC_OPB_IRQHandler + + PUBWEAK ESC_SYNC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC0_IRQHandler + B ESC_SYNC0_IRQHandler + + PUBWEAK ESC_SYNC1_RQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC1_RQHandler + B ESC_SYNC1_RQHandler + + PUBWEAK ESC_WRP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_WRP_IRQHandler + B ESC_WRP_IRQHandler + + PUBWEAK ATIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_BRK_IRQHandler + B ATIM1_BRK_IRQHandler + + PUBWEAK ATIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_TRG_COM_IRQHandler + B ATIM1_TRG_COM_IRQHandler + + PUBWEAK ATIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_CC_IRQHandler + B ATIM1_CC_IRQHandler + + PUBWEAK ATIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_UP_IRQHandler + B ATIM1_UP_IRQHandler + + PUBWEAK ATIM2_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_BRK_IRQHandler + B ATIM2_BRK_IRQHandler + + PUBWEAK ATIM2_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_TRG_COM_IRQHandler + B ATIM2_TRG_COM_IRQHandler + + PUBWEAK ATIM2_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_CC_IRQHandler + B ATIM2_CC_IRQHandler + + PUBWEAK ATIM2_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_UP_IRQHandler + B ATIM2_UP_IRQHandler + + PUBWEAK ATIM3_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_BRK_IRQHandler + B ATIM3_BRK_IRQHandler + + PUBWEAK ATIM3_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_TRG_COM_IRQHandler + B ATIM3_TRG_COM_IRQHandler + + PUBWEAK ATIM3_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_CC_IRQHandler + B ATIM3_CC_IRQHandler + + PUBWEAK ATIM3_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_UP_IRQHandler + B ATIM3_UP_IRQHandler + + PUBWEAK ATIM4_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_BRK_IRQHandler + B ATIM4_BRK_IRQHandler + + PUBWEAK ATIM4_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_TRG_COM_IRQHandler + B ATIM4_TRG_COM_IRQHandler + + PUBWEAK ATIM4_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_CC_IRQHandler + B ATIM4_CC_IRQHandler + + PUBWEAK ATIM4_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_UP_IRQHandler + B ATIM4_UP_IRQHandler + + PUBWEAK GTIMA1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA1_IRQHandler + B GTIMA1_IRQHandler + + PUBWEAK GTIMA2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA2_IRQHandler + B GTIMA2_IRQHandler + + PUBWEAK GTIMA3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA3_IRQHandler + B GTIMA3_IRQHandler + + PUBWEAK GTIMA4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA4_IRQHandler + B GTIMA4_IRQHandler + + PUBWEAK GTIMA5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA5_IRQHandler + B GTIMA5_IRQHandler + + PUBWEAK GTIMA6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA6_IRQHandler + B GTIMA6_IRQHandler + + PUBWEAK GTIMA7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA7_IRQHandler + B GTIMA7_IRQHandler + + PUBWEAK GTIMB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB1_IRQHandler + B GTIMB1_IRQHandler + + PUBWEAK GTIMB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB2_IRQHandler + B GTIMB2_IRQHandler + + PUBWEAK GTIMB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB3_IRQHandler + B GTIMB3_IRQHandler + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + PUBWEAK BTIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM4_IRQHandler + B BTIM4_IRQHandler + + PUBWEAK LPTIM1_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_WKUP_IRQHandler + B LPTIM1_WKUP_IRQHandler + + PUBWEAK LPTIM2_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM2_WKUP_IRQHandler + B LPTIM2_WKUP_IRQHandler + + PUBWEAK LPTIM3_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM3_WKUP_IRQHandler + B LPTIM3_WKUP_IRQHandler + + PUBWEAK LPTIM4_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM4_WKUP_IRQHandler + B LPTIM4_WKUP_IRQHandler + + PUBWEAK DSMU_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT0_IRQHandler + B DSMU_FLT0_IRQHandler + + PUBWEAK DSMU_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT1_IRQHandler + B DSMU_FLT1_IRQHandler + + PUBWEAK DSMU_FLT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT2_IRQHandler + B DSMU_FLT2_IRQHandler + + PUBWEAK DSMU_FLT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT3_IRQHandler + B DSMU_FLT3_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK DMAMUX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX1_IRQHandler + B DMAMUX1_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm4.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm4.s new file mode 100644 index 0000000000..d651a057ca --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm4.s @@ -0,0 +1,897 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG2_IRQHandler ; Window2 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD AHB_ICACHE_IRQHandler ; CM4 AHB iCache interrupt + DCD AHB_DCACHE_IRQHandler ; CM4 AHB dCache interrupt + DCD FPU_CPU2_IRQHandler ; FPU_CM4 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD AHB_CACHE_PARMON_IRQHandler ; AHB i/dCACHE parity error intertupt + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD 0 ; + DCD SEMA4_INT2_IRQHandler ; SEMA4 interrupt2 + DCD WWDG1_RST_IRQHandler ; WWDG1 reset interrupt through EXTI line 81 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUA_IRQHandler ; DCMUA interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_IRQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG2_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel0_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA3_Channel0_IRQHandler [WEAK] + EXPORT DMA3_Channel1_IRQHandler [WEAK] + EXPORT DMA3_Channel2_IRQHandler [WEAK] + EXPORT DMA3_Channel3_IRQHandler [WEAK] + EXPORT DMA3_Channel4_IRQHandler [WEAK] + EXPORT DMA3_Channel5_IRQHandler [WEAK] + EXPORT DMA3_Channel6_IRQHandler [WEAK] + EXPORT DMA3_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel0_IRQHandler [WEAK] + EXPORT MDMA_Channel1_IRQHandler [WEAK] + EXPORT MDMA_Channel2_IRQHandler [WEAK] + EXPORT MDMA_Channel3_IRQHandler [WEAK] + EXPORT MDMA_Channel4_IRQHandler [WEAK] + EXPORT MDMA_Channel5_IRQHandler [WEAK] + EXPORT MDMA_Channel6_IRQHandler [WEAK] + EXPORT MDMA_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel8_IRQHandler [WEAK] + EXPORT MDMA_Channel9_IRQHandler [WEAK] + EXPORT MDMA_Channel10_IRQHandler [WEAK] + EXPORT MDMA_Channel11_IRQHandler [WEAK] + EXPORT MDMA_Channel12_IRQHandler [WEAK] + EXPORT MDMA_Channel13_IRQHandler [WEAK] + EXPORT MDMA_Channel14_IRQHandler [WEAK] + EXPORT MDMA_Channel15_IRQHandler [WEAK] + EXPORT SDPU_IRQHandler [WEAK] + EXPORT AHB_ICACHE_IRQHandler [WEAK] + EXPORT AHB_DCACHE_IRQHandler [WEAK] + EXPORT FPU_CPU2_IRQHandler [WEAK] + EXPORT ECCMON_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT I2C6_EV_IRQHandler [WEAK] + EXPORT I2C6_ER_IRQHandler [WEAK] + EXPORT I2C7_EV_IRQHandler [WEAK] + EXPORT I2C7_ER_IRQHandler [WEAK] + EXPORT I2C8_EV_IRQHandler [WEAK] + EXPORT I2C8_ER_IRQHandler [WEAK] + EXPORT I2C9_EV_IRQHandler [WEAK] + EXPORT I2C9_ER_IRQHandler [WEAK] + EXPORT I2C10_EV_IRQHandler [WEAK] + EXPORT I2C10_ER_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT I2S4_IRQHandler [WEAK] + EXPORT xSPI1_IRQHandler [WEAK] + EXPORT xSPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT LCD_EV_IRQHandler [WEAK] + EXPORT LCD_ER_IRQHandler [WEAK] + EXPORT DVP1_IRQHandler [WEAK] + EXPORT DVP2_IRQHandler [WEAK] + EXPORT DMAMUX2_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB1_HS_WKUP_IRQHandler [WEAK] + EXPORT USB1_HS_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB2_HS_WKUP_IRQHandler [WEAK] + EXPORT USB2_HS_IRQHandler [WEAK] + EXPORT ETH1_IRQHandler [WEAK] + EXPORT ETH1_PMT_LPI_IRQHandler [WEAK] + EXPORT ETH2_IRQHandler [WEAK] + EXPORT ETH2_PMT_LPI_IRQHandler [WEAK] + EXPORT FDCAN1_INT0_IRQHandler [WEAK] + EXPORT FDCAN2_INT0_IRQHandler [WEAK] + EXPORT FDCAN3_INT0_IRQHandler [WEAK] + EXPORT FDCAN4_INT0_IRQHandler [WEAK] + EXPORT FDCAN1_INT1_IRQHandler [WEAK] + EXPORT FDCAN2_INT1_IRQHandler [WEAK] + EXPORT FDCAN3_INT1_IRQHandler [WEAK] + EXPORT FDCAN4_INT1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPUART2_IRQHandler [WEAK] + EXPORT GPU_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT COMP1_2_IRQHandler [WEAK] + EXPORT COMP3_4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT1_IRQHandler [WEAK] + EXPORT SHRTIM1_INT2_IRQHandler [WEAK] + EXPORT SHRTIM1_INT3_IRQHandler [WEAK] + EXPORT SHRTIM1_INT4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT5_IRQHandler [WEAK] + EXPORT SHRTIM1_INT6_IRQHandler [WEAK] + EXPORT SHRTIM1_INT7_IRQHandler [WEAK] + EXPORT SHRTIM1_INT8_IRQHandler [WEAK] + EXPORT SHRTIM2_INT1_IRQHandler [WEAK] + EXPORT SHRTIM2_INT2_IRQHandler [WEAK] + EXPORT SHRTIM2_INT3_IRQHandler [WEAK] + EXPORT SHRTIM2_INT4_IRQHandler [WEAK] + EXPORT SHRTIM2_INT5_IRQHandler [WEAK] + EXPORT SHRTIM2_INT6_IRQHandler [WEAK] + EXPORT SHRTIM2_INT7_IRQHandler [WEAK] + EXPORT SHRTIM2_INT8_IRQHandler [WEAK] + EXPORT FDCAN5_INT0_IRQHandler [WEAK] + EXPORT FDCAN6_INT0_IRQHandler [WEAK] + EXPORT FDCAN7_INT0_IRQHandler [WEAK] + EXPORT FDCAN8_INT0_IRQHandler [WEAK] + EXPORT FDCAN5_INT1_IRQHandler [WEAK] + EXPORT FDCAN6_INT1_IRQHandler [WEAK] + EXPORT FDCAN7_INT1_IRQHandler [WEAK] + EXPORT FDCAN8_INT1_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT AHB_CACHE_PARMON_IRQHandler [WEAK] + EXPORT LPTIM5_WKUP_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_H2P_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_P2H_IRQHandler [WEAK] + EXPORT WAKEUP_IO_IRQHandler [WEAK] + EXPORT SEMA4_INT2_IRQHandler [WEAK] + EXPORT WWDG1_RST_IRQHandler [WEAK] + EXPORT OTPC_IRQHandler [WEAK] + EXPORT FEMC_IRQHandler [WEAK] + EXPORT DCMUA_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT MDMA_AHBS_ER_IRQHandler [WEAK] + EXPORT CM7_CATCH_READ_ER_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT DAC4_IRQHandler [WEAK] + EXPORT EMC_IRQHandler [WEAK] + EXPORT DAC5_IRQHandler [WEAK] + EXPORT DAC6_IRQHandler [WEAK] + EXPORT ESC_OPB_IRQHandler [WEAK] + EXPORT ESC_SYNC0_IRQHandler [WEAK] + EXPORT ESC_SYNC1_IRQHandler [WEAK] + EXPORT ESC_WRP_IRQHandler [WEAK] + EXPORT ATIM1_BRK_IRQHandler [WEAK] + EXPORT ATIM1_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM1_CC_IRQHandler [WEAK] + EXPORT ATIM1_UP_IRQHandler [WEAK] + EXPORT ATIM2_BRK_IRQHandler [WEAK] + EXPORT ATIM2_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM2_CC_IRQHandler [WEAK] + EXPORT ATIM2_UP_IRQHandler [WEAK] + EXPORT ATIM3_BRK_IRQHandler [WEAK] + EXPORT ATIM3_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM3_CC_IRQHandler [WEAK] + EXPORT ATIM3_UP_IRQHandler [WEAK] + EXPORT ATIM4_BRK_IRQHandler [WEAK] + EXPORT ATIM4_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM4_CC_IRQHandler [WEAK] + EXPORT ATIM4_UP_IRQHandler [WEAK] + EXPORT GTIMA1_IRQHandler [WEAK] + EXPORT GTIMA2_IRQHandler [WEAK] + EXPORT GTIMA3_IRQHandler [WEAK] + EXPORT GTIMA4_IRQHandler [WEAK] + EXPORT GTIMA5_IRQHandler [WEAK] + EXPORT GTIMA6_IRQHandler [WEAK] + EXPORT GTIMA7_IRQHandler [WEAK] + EXPORT GTIMB1_IRQHandler [WEAK] + EXPORT GTIMB2_IRQHandler [WEAK] + EXPORT GTIMB3_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT BTIM4_IRQHandler [WEAK] + EXPORT LPTIM1_WKUP_IRQHandler [WEAK] + EXPORT LPTIM2_WKUP_IRQHandler [WEAK] + EXPORT LPTIM3_WKUP_IRQHandler [WEAK] + EXPORT LPTIM4_WKUP_IRQHandler [WEAK] + EXPORT DSMU_FLT0_IRQHandler [WEAK] + EXPORT DSMU_FLT1_IRQHandler [WEAK] + EXPORT DSMU_FLT2_IRQHandler [WEAK] + EXPORT DSMU_FLT3_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT DMAMUX1_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + + +WWDG2_IRQHandler +PVD_IRQHandler +RTC_TAMPER_IRQHandler +RTC_WKUP_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI9_5_IRQHandler +EXTI15_10_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +DMA2_Channel0_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA3_Channel0_IRQHandler +DMA3_Channel1_IRQHandler +DMA3_Channel2_IRQHandler +DMA3_Channel3_IRQHandler +DMA3_Channel4_IRQHandler +DMA3_Channel5_IRQHandler +DMA3_Channel6_IRQHandler +DMA3_Channel7_IRQHandler +MDMA_Channel0_IRQHandler +MDMA_Channel1_IRQHandler +MDMA_Channel2_IRQHandler +MDMA_Channel3_IRQHandler +MDMA_Channel4_IRQHandler +MDMA_Channel5_IRQHandler +MDMA_Channel6_IRQHandler +MDMA_Channel7_IRQHandler +MDMA_Channel8_IRQHandler +MDMA_Channel9_IRQHandler +MDMA_Channel10_IRQHandler +MDMA_Channel11_IRQHandler +MDMA_Channel12_IRQHandler +MDMA_Channel13_IRQHandler +MDMA_Channel14_IRQHandler +MDMA_Channel15_IRQHandler +SDPU_IRQHandler +AHB_ICACHE_IRQHandler +AHB_DCACHE_IRQHandler +FPU_CPU2_IRQHandler +ECCMON_IRQHandler +RTC_ALARM_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +I2C6_EV_IRQHandler +I2C6_ER_IRQHandler +I2C7_EV_IRQHandler +I2C7_ER_IRQHandler +I2C8_EV_IRQHandler +I2C8_ER_IRQHandler +I2C9_EV_IRQHandler +I2C9_ER_IRQHandler +I2C10_EV_IRQHandler +I2C10_ER_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +I2S3_IRQHandler +I2S4_IRQHandler +xSPI1_IRQHandler +xSPI2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SPI7_IRQHandler +LCD_EV_IRQHandler +LCD_ER_IRQHandler +DVP1_IRQHandler +DVP2_IRQHandler +DMAMUX2_IRQHandler +USB1_HS_EPx_OUT_IRQHandler +USB1_HS_EPx_IN_IRQHandler +USB1_HS_WKUP_IRQHandler +USB1_HS_IRQHandler +USB2_HS_EPx_OUT_IRQHandler +USB2_HS_EPx_IN_IRQHandler +USB2_HS_WKUP_IRQHandler +USB2_HS_IRQHandler +ETH1_IRQHandler +ETH1_PMT_LPI_IRQHandler +ETH2_IRQHandler +ETH2_PMT_LPI_IRQHandler +FDCAN1_INT0_IRQHandler +FDCAN2_INT0_IRQHandler +FDCAN3_INT0_IRQHandler +FDCAN4_INT0_IRQHandler +FDCAN1_INT1_IRQHandler +FDCAN2_INT1_IRQHandler +FDCAN3_INT1_IRQHandler +FDCAN4_INT1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +LPUART1_IRQHandler +LPUART2_IRQHandler +GPU_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +ADC3_IRQHandler +COMP1_2_IRQHandler +COMP3_4_IRQHandler +SHRTIM1_INT1_IRQHandler +SHRTIM1_INT2_IRQHandler +SHRTIM1_INT3_IRQHandler +SHRTIM1_INT4_IRQHandler +SHRTIM1_INT5_IRQHandler +SHRTIM1_INT6_IRQHandler +SHRTIM1_INT7_IRQHandler +SHRTIM1_INT8_IRQHandler +SHRTIM2_INT1_IRQHandler +SHRTIM2_INT2_IRQHandler +SHRTIM2_INT3_IRQHandler +SHRTIM2_INT4_IRQHandler +SHRTIM2_INT5_IRQHandler +SHRTIM2_INT6_IRQHandler +SHRTIM2_INT7_IRQHandler +SHRTIM2_INT8_IRQHandler +FDCAN5_INT0_IRQHandler +FDCAN6_INT0_IRQHandler +FDCAN7_INT0_IRQHandler +FDCAN8_INT0_IRQHandler +FDCAN5_INT1_IRQHandler +FDCAN6_INT1_IRQHandler +FDCAN7_INT1_IRQHandler +FDCAN8_INT1_IRQHandler +DSI_IRQHandler +AHB_CACHE_PARMON_IRQHandler +LPTIM5_WKUP_IRQHandler +JPEG_SGDMA_H2P_IRQHandler +JPEG_SGDMA_P2H_IRQHandler +WAKEUP_IO_IRQHandler +SEMA4_INT2_IRQHandler +WWDG1_RST_IRQHandler +OTPC_IRQHandler +FEMC_IRQHandler +DCMUA_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +MDMA_AHBS_ER_IRQHandler +CM7_CATCH_READ_ER_IRQHandler +DAC3_IRQHandler +DAC4_IRQHandler +EMC_IRQHandler +DAC5_IRQHandler +DAC6_IRQHandler +ESC_OPB_IRQHandler +ESC_SYNC0_IRQHandler +ESC_SYNC1_IRQHandler +ESC_WRP_IRQHandler +ATIM1_BRK_IRQHandler +ATIM1_TRG_COM_IRQHandler +ATIM1_CC_IRQHandler +ATIM1_UP_IRQHandler +ATIM2_BRK_IRQHandler +ATIM2_TRG_COM_IRQHandler +ATIM2_CC_IRQHandler +ATIM2_UP_IRQHandler +ATIM3_BRK_IRQHandler +ATIM3_TRG_COM_IRQHandler +ATIM3_CC_IRQHandler +ATIM3_UP_IRQHandler +ATIM4_BRK_IRQHandler +ATIM4_TRG_COM_IRQHandler +ATIM4_CC_IRQHandler +ATIM4_UP_IRQHandler +GTIMA1_IRQHandler +GTIMA2_IRQHandler +GTIMA3_IRQHandler +GTIMA4_IRQHandler +GTIMA5_IRQHandler +GTIMA6_IRQHandler +GTIMA7_IRQHandler +GTIMB1_IRQHandler +GTIMB2_IRQHandler +GTIMB3_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +BTIM4_IRQHandler +LPTIM1_WKUP_IRQHandler +LPTIM2_WKUP_IRQHandler +LPTIM3_WKUP_IRQHandler +LPTIM4_WKUP_IRQHandler +DSMU_FLT0_IRQHandler +DSMU_FLT1_IRQHandler +DSMU_FLT2_IRQHandler +DSMU_FLT3_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +DMAMUX1_IRQHandler +MMU_IRQHandler + + + + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm4_EWARM.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm4_EWARM.s new file mode 100644 index 0000000000..8cfe4e5359 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm4_EWARM.s @@ -0,0 +1,1543 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + + __iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + + ; External Interrupts + DCD WWDG2_IRQHandler ; Window2 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD AHB_ICACHE_IRQHandler ; CM4 AHB iCache interrupt + DCD AHB_DCACHE_IRQHandler ; CM4 AHB dCache interrupt + DCD FPU_CPU2_IRQHandler ; FPU_CM4 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD CACHE_PARITY_ER_IRQHandler ; AHB i/dCACHE parity error intertupt + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD 0 ; Reserved + DCD SEMA4_INT2_IRQHandler ; SEMA4 interrupt2 + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUA_IRQHandler ; DCMUA interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_RQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + ;need check to user manual of exti chapter + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_IRQHandler + B WWDG2_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_TAMPER_IRQHandler + B RTC_TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK DMA2_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel0_IRQHandler + B DMA2_Channel0_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA3_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel0_IRQHandler + B DMA3_Channel0_IRQHandler + + PUBWEAK DMA3_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel1_IRQHandler + B DMA3_Channel1_IRQHandler + + PUBWEAK DMA3_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel2_IRQHandler + B DMA3_Channel2_IRQHandler + + PUBWEAK DMA3_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel3_IRQHandler + B DMA3_Channel3_IRQHandler + + PUBWEAK DMA3_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel4_IRQHandler + B DMA3_Channel4_IRQHandler + + PUBWEAK DMA3_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel5_IRQHandler + B DMA3_Channel5_IRQHandler + + PUBWEAK DMA3_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel6_IRQHandler + B DMA3_Channel6_IRQHandler + + PUBWEAK DMA3_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel7_IRQHandler + B DMA3_Channel7_IRQHandler + + PUBWEAK MDMA_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel0_IRQHandler + B MDMA_Channel0_IRQHandler + + PUBWEAK MDMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel1_IRQHandler + B MDMA_Channel1_IRQHandler + + PUBWEAK MDMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel2_IRQHandler + B MDMA_Channel2_IRQHandler + + PUBWEAK MDMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel3_IRQHandler + B MDMA_Channel3_IRQHandler + + PUBWEAK MDMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel4_IRQHandler + B MDMA_Channel4_IRQHandler + + PUBWEAK MDMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel5_IRQHandler + B MDMA_Channel5_IRQHandler + + PUBWEAK MDMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel6_IRQHandler + B MDMA_Channel6_IRQHandler + + PUBWEAK MDMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel7_IRQHandler + B MDMA_Channel7_IRQHandler + + PUBWEAK MDMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel8_IRQHandler + B MDMA_Channel8_IRQHandler + + PUBWEAK MDMA_Channel9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel9_IRQHandler + B MDMA_Channel9_IRQHandler + + PUBWEAK MDMA_Channel10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel10_IRQHandler + B MDMA_Channel10_IRQHandler + + PUBWEAK MDMA_Channel11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel11_IRQHandler + B MDMA_Channel11_IRQHandler + + PUBWEAK MDMA_Channel12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel12_IRQHandler + B MDMA_Channel12_IRQHandler + + PUBWEAK MDMA_Channel13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel13_IRQHandler + B MDMA_Channel13_IRQHandler + + PUBWEAK MDMA_Channel14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel14_IRQHandler + B MDMA_Channel14_IRQHandler + + PUBWEAK MDMA_Channel15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel15_IRQHandler + B MDMA_Channel15_IRQHandler + + PUBWEAK SDPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDPU_IRQHandler + B SDPU_IRQHandler + + PUBWEAK AHB_ICACHE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AHB_ICACHE_IRQHandler + B AHB_ICACHE_IRQHandler + + PUBWEAK AHB_DCACHE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AHB_DCACHE_IRQHandler + B AHB_DCACHE_IRQHandler + + PUBWEAK FPU_CPU2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_CPU2_IRQHandler + B FPU_CPU2_IRQHandler + + PUBWEAK ECCMON_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECCMON_IRQHandler + B ECCMON_IRQHandler + + PUBWEAK RTC_ALARM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_ALARM_IRQHandler + B RTC_ALARM_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK I2C6_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_EV_IRQHandler + B I2C6_EV_IRQHandler + + PUBWEAK I2C6_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_ER_IRQHandler + B I2C6_ER_IRQHandler + + PUBWEAK I2C7_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_EV_IRQHandler + B I2C7_EV_IRQHandler + + PUBWEAK I2C7_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_ER_IRQHandler + B I2C7_ER_IRQHandler + + PUBWEAK I2C8_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_EV_IRQHandler + B I2C8_EV_IRQHandler + + PUBWEAK I2C8_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_ER_IRQHandler + B I2C8_ER_IRQHandler + + PUBWEAK I2C9_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_EV_IRQHandler + B I2C9_EV_IRQHandler + + PUBWEAK I2C9_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_ER_IRQHandler + B I2C9_ER_IRQHandler + + PUBWEAK I2C10_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_EV_IRQHandler + B I2C10_EV_IRQHandler + + PUBWEAK I2C10_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_ER_IRQHandler + B I2C10_ER_IRQHandler + + PUBWEAK I2S1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S1_IRQHandler + B I2S1_IRQHandler + + PUBWEAK I2S2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S2_IRQHandler + B I2S2_IRQHandler + + PUBWEAK I2S3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S3_IRQHandler + B I2S3_IRQHandler + + PUBWEAK I2S4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S4_IRQHandler + B I2S4_IRQHandler + + PUBWEAK xSPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI1_IRQHandler + B xSPI1_IRQHandler + + PUBWEAK xSPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI2_IRQHandler + B xSPI2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SPI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI7_IRQHandler + B SPI7_IRQHandler + + PUBWEAK LCD_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_EV_IRQHandler + B LCD_EV_IRQHandler + + PUBWEAK LCD_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_ER_IRQHandler + B LCD_ER_IRQHandler + + PUBWEAK DVP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP1_IRQHandler + B DVP1_IRQHandler + + PUBWEAK DVP2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP2_IRQHandler + B DVP2_IRQHandler + + PUBWEAK DMAMUX2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX2_IRQHandler + B DMAMUX2_IRQHandler + + PUBWEAK USB1_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_OUT_IRQHandler + B USB1_HS_EPx_OUT_IRQHandler + + PUBWEAK USB1_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_IN_IRQHandler + B USB1_HS_EPx_IN_IRQHandler + + PUBWEAK USB1_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_WKUP_IRQHandler + B USB1_HS_WKUP_IRQHandler + + PUBWEAK USB1_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_IRQHandler + B USB1_HS_IRQHandler + + PUBWEAK USB2_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_OUT_IRQHandler + B USB2_HS_EPx_OUT_IRQHandler + + PUBWEAK USB2_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_IN_IRQHandler + B USB2_HS_EPx_IN_IRQHandler + + PUBWEAK USB2_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_WKUP_IRQHandler + B USB2_HS_WKUP_IRQHandler + + PUBWEAK USB2_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_IRQHandler + B USB2_HS_IRQHandler + + PUBWEAK ETH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_IRQHandler + B ETH1_IRQHandler + + PUBWEAK ETH1_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_PMT_LPI_IRQHandler + B ETH1_PMT_LPI_IRQHandler + + PUBWEAK ETH2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_IRQHandler + B ETH2_IRQHandler + + PUBWEAK ETH2_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_PMT_LPI_IRQHandler + B ETH2_PMT_LPI_IRQHandler + + PUBWEAK FDCAN1_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT0_IRQHandler + B FDCAN1_INT0_IRQHandler + + PUBWEAK FDCAN2_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT0_IRQHandler + B FDCAN2_INT0_IRQHandler + + PUBWEAK FDCAN3_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT0_IRQHandler + B FDCAN3_INT0_IRQHandler + + PUBWEAK FDCAN4_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT0_IRQHandler + B FDCAN4_INT0_IRQHandler + + PUBWEAK FDCAN1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT1_IRQHandler + B FDCAN1_INT1_IRQHandler + + PUBWEAK FDCAN2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT1_IRQHandler + B FDCAN2_INT1_IRQHandler + + PUBWEAK FDCAN3_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT1_IRQHandler + B FDCAN3_INT1_IRQHandler + + PUBWEAK FDCAN4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT1_IRQHandler + B FDCAN4_INT1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK USART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART7_IRQHandler + B USART7_IRQHandler + + PUBWEAK USART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART8_IRQHandler + B USART8_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK UART11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART11_IRQHandler + B UART11_IRQHandler + + PUBWEAK UART12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART12_IRQHandler + B UART12_IRQHandler + + PUBWEAK UART13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART13_IRQHandler + B UART13_IRQHandler + + PUBWEAK UART14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART14_IRQHandler + B UART14_IRQHandler + + PUBWEAK UART15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART15_IRQHandler + B UART15_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPUART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART2_IRQHandler + B LPUART2_IRQHandler + + PUBWEAK GPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPU_IRQHandler + B GPU_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK COMP1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP1_2_IRQHandler + B COMP1_2_IRQHandler + + PUBWEAK COMP3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP3_4_IRQHandler + B COMP3_4_IRQHandler + + PUBWEAK SHRTIM1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT1_IRQHandler + B SHRTIM1_INT1_IRQHandler + + PUBWEAK SHRTIM1_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT2_IRQHandler + B SHRTIM1_INT2_IRQHandler + + PUBWEAK SHRTIM1_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT3_IRQHandler + B SHRTIM1_INT3_IRQHandler + + PUBWEAK SHRTIM1_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT4_IRQHandler + B SHRTIM1_INT4_IRQHandler + + PUBWEAK SHRTIM1_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT5_IRQHandler + B SHRTIM1_INT5_IRQHandler + + PUBWEAK SHRTIM1_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT6_IRQHandler + B SHRTIM1_INT6_IRQHandler + + PUBWEAK SHRTIM1_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT7_IRQHandler + B SHRTIM1_INT7_IRQHandler + + PUBWEAK SHRTIM1_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT8_IRQHandler + B SHRTIM1_INT8_IRQHandler + + PUBWEAK SHRTIM2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT1_IRQHandler + B SHRTIM2_INT1_IRQHandler + + PUBWEAK SHRTIM2_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT2_IRQHandler + B SHRTIM2_INT2_IRQHandler + + PUBWEAK SHRTIM2_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT3_IRQHandler + B SHRTIM2_INT3_IRQHandler + + PUBWEAK SHRTIM2_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT4_IRQHandler + B SHRTIM2_INT4_IRQHandler + + PUBWEAK SHRTIM2_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT5_IRQHandler + B SHRTIM2_INT5_IRQHandler + + PUBWEAK SHRTIM2_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT6_IRQHandler + B SHRTIM2_INT6_IRQHandler + + PUBWEAK SHRTIM2_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT7_IRQHandler + B SHRTIM2_INT7_IRQHandler + + PUBWEAK SHRTIM2_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT8_IRQHandler + B SHRTIM2_INT8_IRQHandler + + PUBWEAK FDCAN5_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT0_IRQHandler + B FDCAN5_INT0_IRQHandler + + PUBWEAK FDCAN6_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT0_IRQHandler + B FDCAN6_INT0_IRQHandler + + PUBWEAK FDCAN7_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT0_IRQHandler + B FDCAN7_INT0_IRQHandler + + PUBWEAK FDCAN8_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT0_IRQHandler + B FDCAN8_INT0_IRQHandler + + PUBWEAK FDCAN5_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT1_IRQHandler + B FDCAN5_INT1_IRQHandler + + PUBWEAK FDCAN6_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT1_IRQHandler + B FDCAN6_INT1_IRQHandler + + PUBWEAK FDCAN7_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT1_IRQHandler + B FDCAN7_INT1_IRQHandler + + PUBWEAK FDCAN8_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT1_IRQHandler + B FDCAN8_INT1_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK CACHE_PARITY_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CACHE_PARITY_ER_IRQHandler + B CACHE_PARITY_ER_IRQHandler + + PUBWEAK LPTIM5_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM5_WKUP_IRQHandler + B LPTIM5_WKUP_IRQHandler + + PUBWEAK JPEG_SGDMA_H2P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_H2P_IRQHandler + B JPEG_SGDMA_H2P_IRQHandler + + PUBWEAK JPEG_SGDMA_P2H_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_P2H_IRQHandler + B JPEG_SGDMA_P2H_IRQHandler + + PUBWEAK WAKEUP_IO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WAKEUP_IO_IRQHandler + B WAKEUP_IO_IRQHandler + + PUBWEAK SEMA4_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_INT2_IRQHandler + B SEMA4_INT2_IRQHandler + + PUBWEAK WWDG2_RST_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_RST_IRQHandler + B WWDG2_RST_IRQHandler + + PUBWEAK OTPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTPC_IRQHandler + B OTPC_IRQHandler + + PUBWEAK FEMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FEMC_IRQHandler + B FEMC_IRQHandler + + PUBWEAK DCMUA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMUA_IRQHandler + B DCMUA_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK MDMA_AHBS_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_AHBS_ER_IRQHandler + B MDMA_AHBS_ER_IRQHandler + + PUBWEAK CM7_CATCH_READ_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CM7_CATCH_READ_ER_IRQHandler + B CM7_CATCH_READ_ER_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK DAC4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC4_IRQHandler + B DAC4_IRQHandler + + PUBWEAK EMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMC_IRQHandler + B EMC_IRQHandler + + PUBWEAK DAC5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC5_IRQHandler + B DAC5_IRQHandler + + PUBWEAK DAC6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC6_IRQHandler + B DAC6_IRQHandler + + PUBWEAK ESC_OPB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_OPB_IRQHandler + B ESC_OPB_IRQHandler + + PUBWEAK ESC_SYNC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC0_IRQHandler + B ESC_SYNC0_IRQHandler + + PUBWEAK ESC_SYNC1_RQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC1_RQHandler + B ESC_SYNC1_RQHandler + + PUBWEAK ESC_WRP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_WRP_IRQHandler + B ESC_WRP_IRQHandler + + PUBWEAK ATIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_BRK_IRQHandler + B ATIM1_BRK_IRQHandler + + PUBWEAK ATIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_TRG_COM_IRQHandler + B ATIM1_TRG_COM_IRQHandler + + PUBWEAK ATIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_CC_IRQHandler + B ATIM1_CC_IRQHandler + + PUBWEAK ATIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_UP_IRQHandler + B ATIM1_UP_IRQHandler + + PUBWEAK ATIM2_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_BRK_IRQHandler + B ATIM2_BRK_IRQHandler + + PUBWEAK ATIM2_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_TRG_COM_IRQHandler + B ATIM2_TRG_COM_IRQHandler + + PUBWEAK ATIM2_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_CC_IRQHandler + B ATIM2_CC_IRQHandler + + PUBWEAK ATIM2_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_UP_IRQHandler + B ATIM2_UP_IRQHandler + + PUBWEAK ATIM3_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_BRK_IRQHandler + B ATIM3_BRK_IRQHandler + + PUBWEAK ATIM3_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_TRG_COM_IRQHandler + B ATIM3_TRG_COM_IRQHandler + + PUBWEAK ATIM3_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_CC_IRQHandler + B ATIM3_CC_IRQHandler + + PUBWEAK ATIM3_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_UP_IRQHandler + B ATIM3_UP_IRQHandler + + PUBWEAK ATIM4_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_BRK_IRQHandler + B ATIM4_BRK_IRQHandler + + PUBWEAK ATIM4_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_TRG_COM_IRQHandler + B ATIM4_TRG_COM_IRQHandler + + PUBWEAK ATIM4_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_CC_IRQHandler + B ATIM4_CC_IRQHandler + + PUBWEAK ATIM4_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_UP_IRQHandler + B ATIM4_UP_IRQHandler + + PUBWEAK GTIMA1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA1_IRQHandler + B GTIMA1_IRQHandler + + PUBWEAK GTIMA2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA2_IRQHandler + B GTIMA2_IRQHandler + + PUBWEAK GTIMA3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA3_IRQHandler + B GTIMA3_IRQHandler + + PUBWEAK GTIMA4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA4_IRQHandler + B GTIMA4_IRQHandler + + PUBWEAK GTIMA5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA5_IRQHandler + B GTIMA5_IRQHandler + + PUBWEAK GTIMA6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA6_IRQHandler + B GTIMA6_IRQHandler + + PUBWEAK GTIMA7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA7_IRQHandler + B GTIMA7_IRQHandler + + PUBWEAK GTIMB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB1_IRQHandler + B GTIMB1_IRQHandler + + PUBWEAK GTIMB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB2_IRQHandler + B GTIMB2_IRQHandler + + PUBWEAK GTIMB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB3_IRQHandler + B GTIMB3_IRQHandler + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + PUBWEAK BTIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM4_IRQHandler + B BTIM4_IRQHandler + + PUBWEAK LPTIM1_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_WKUP_IRQHandler + B LPTIM1_WKUP_IRQHandler + + PUBWEAK LPTIM2_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM2_WKUP_IRQHandler + B LPTIM2_WKUP_IRQHandler + + PUBWEAK LPTIM3_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM3_WKUP_IRQHandler + B LPTIM3_WKUP_IRQHandler + + PUBWEAK LPTIM4_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM4_WKUP_IRQHandler + B LPTIM4_WKUP_IRQHandler + + PUBWEAK DSMU_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT0_IRQHandler + B DSMU_FLT0_IRQHandler + + PUBWEAK DSMU_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT1_IRQHandler + B DSMU_FLT1_IRQHandler + + PUBWEAK DSMU_FLT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT2_IRQHandler + B DSMU_FLT2_IRQHandler + + PUBWEAK DSMU_FLT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT3_IRQHandler + B DSMU_FLT3_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK DMAMUX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX1_IRQHandler + B DMAMUX1_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm7.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm7.s new file mode 100644 index 0000000000..fbbb87e838 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm7.s @@ -0,0 +1,892 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD 0 ; + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_IRQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +N32SysTick_Handler PROC + EXPORT N32SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG1_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel0_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA3_Channel0_IRQHandler [WEAK] + EXPORT DMA3_Channel1_IRQHandler [WEAK] + EXPORT DMA3_Channel2_IRQHandler [WEAK] + EXPORT DMA3_Channel3_IRQHandler [WEAK] + EXPORT DMA3_Channel4_IRQHandler [WEAK] + EXPORT DMA3_Channel5_IRQHandler [WEAK] + EXPORT DMA3_Channel6_IRQHandler [WEAK] + EXPORT DMA3_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel0_IRQHandler [WEAK] + EXPORT MDMA_Channel1_IRQHandler [WEAK] + EXPORT MDMA_Channel2_IRQHandler [WEAK] + EXPORT MDMA_Channel3_IRQHandler [WEAK] + EXPORT MDMA_Channel4_IRQHandler [WEAK] + EXPORT MDMA_Channel5_IRQHandler [WEAK] + EXPORT MDMA_Channel6_IRQHandler [WEAK] + EXPORT MDMA_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel8_IRQHandler [WEAK] + EXPORT MDMA_Channel9_IRQHandler [WEAK] + EXPORT MDMA_Channel10_IRQHandler [WEAK] + EXPORT MDMA_Channel11_IRQHandler [WEAK] + EXPORT MDMA_Channel12_IRQHandler [WEAK] + EXPORT MDMA_Channel13_IRQHandler [WEAK] + EXPORT MDMA_Channel14_IRQHandler [WEAK] + EXPORT MDMA_Channel15_IRQHandler [WEAK] + EXPORT SDPU_IRQHandler [WEAK] + EXPORT FPU_CPU1_IRQHandler [WEAK] + EXPORT ECCMON_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT I2C6_EV_IRQHandler [WEAK] + EXPORT I2C6_ER_IRQHandler [WEAK] + EXPORT I2C7_EV_IRQHandler [WEAK] + EXPORT I2C7_ER_IRQHandler [WEAK] + EXPORT I2C8_EV_IRQHandler [WEAK] + EXPORT I2C8_ER_IRQHandler [WEAK] + EXPORT I2C9_EV_IRQHandler [WEAK] + EXPORT I2C9_ER_IRQHandler [WEAK] + EXPORT I2C10_EV_IRQHandler [WEAK] + EXPORT I2C10_ER_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT I2S4_IRQHandler [WEAK] + EXPORT xSPI1_IRQHandler [WEAK] + EXPORT xSPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT LCD_EV_IRQHandler [WEAK] + EXPORT LCD_ER_IRQHandler [WEAK] + EXPORT DVP1_IRQHandler [WEAK] + EXPORT DVP2_IRQHandler [WEAK] + EXPORT DMAMUX2_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB1_HS_WKUP_IRQHandler [WEAK] + EXPORT USB1_HS_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB2_HS_WKUP_IRQHandler [WEAK] + EXPORT USB2_HS_IRQHandler [WEAK] + EXPORT ETH1_IRQHandler [WEAK] + EXPORT ETH1_PMT_LPI_IRQHandler [WEAK] + EXPORT ETH2_IRQHandler [WEAK] + EXPORT ETH2_PMT_LPI_IRQHandler [WEAK] + EXPORT FDCAN1_INT0_IRQHandler [WEAK] + EXPORT FDCAN2_INT0_IRQHandler [WEAK] + EXPORT FDCAN3_INT0_IRQHandler [WEAK] + EXPORT FDCAN4_INT0_IRQHandler [WEAK] + EXPORT FDCAN1_INT1_IRQHandler [WEAK] + EXPORT FDCAN2_INT1_IRQHandler [WEAK] + EXPORT FDCAN3_INT1_IRQHandler [WEAK] + EXPORT FDCAN4_INT1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPUART2_IRQHandler [WEAK] + EXPORT GPU_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT COMP1_2_IRQHandler [WEAK] + EXPORT COMP3_4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT1_IRQHandler [WEAK] + EXPORT SHRTIM1_INT2_IRQHandler [WEAK] + EXPORT SHRTIM1_INT3_IRQHandler [WEAK] + EXPORT SHRTIM1_INT4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT5_IRQHandler [WEAK] + EXPORT SHRTIM1_INT6_IRQHandler [WEAK] + EXPORT SHRTIM1_INT7_IRQHandler [WEAK] + EXPORT SHRTIM1_INT8_IRQHandler [WEAK] + EXPORT SHRTIM2_INT1_IRQHandler [WEAK] + EXPORT SHRTIM2_INT2_IRQHandler [WEAK] + EXPORT SHRTIM2_INT3_IRQHandler [WEAK] + EXPORT SHRTIM2_INT4_IRQHandler [WEAK] + EXPORT SHRTIM2_INT5_IRQHandler [WEAK] + EXPORT SHRTIM2_INT6_IRQHandler [WEAK] + EXPORT SHRTIM2_INT7_IRQHandler [WEAK] + EXPORT SHRTIM2_INT8_IRQHandler [WEAK] + EXPORT FDCAN5_INT0_IRQHandler [WEAK] + EXPORT FDCAN6_INT0_IRQHandler [WEAK] + EXPORT FDCAN7_INT0_IRQHandler [WEAK] + EXPORT FDCAN8_INT0_IRQHandler [WEAK] + EXPORT FDCAN5_INT1_IRQHandler [WEAK] + EXPORT FDCAN6_INT1_IRQHandler [WEAK] + EXPORT FDCAN7_INT1_IRQHandler [WEAK] + EXPORT FDCAN8_INT1_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT LPTIM5_WKUP_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_H2P_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_P2H_IRQHandler [WEAK] + EXPORT WAKEUP_IO_IRQHandler [WEAK] + EXPORT SEMA4_INT1_IRQHandler [WEAK] + EXPORT WWDG2_RST_IRQHandler [WEAK] + EXPORT OTPC_IRQHandler [WEAK] + EXPORT FEMC_IRQHandler [WEAK] + EXPORT DCMUB_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT MDMA_AHBS_ER_IRQHandler [WEAK] + EXPORT CM7_CATCH_READ_ER_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT DAC4_IRQHandler [WEAK] + EXPORT EMC_IRQHandler [WEAK] + EXPORT DAC5_IRQHandler [WEAK] + EXPORT DAC6_IRQHandler [WEAK] + EXPORT ESC_OPB_IRQHandler [WEAK] + EXPORT ESC_SYNC0_IRQHandler [WEAK] + EXPORT ESC_SYNC1_IRQHandler [WEAK] + EXPORT ESC_WRP_IRQHandler [WEAK] + EXPORT ATIM1_BRK_IRQHandler [WEAK] + EXPORT ATIM1_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM1_CC_IRQHandler [WEAK] + EXPORT ATIM1_UP_IRQHandler [WEAK] + EXPORT ATIM2_BRK_IRQHandler [WEAK] + EXPORT ATIM2_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM2_CC_IRQHandler [WEAK] + EXPORT ATIM2_UP_IRQHandler [WEAK] + EXPORT ATIM3_BRK_IRQHandler [WEAK] + EXPORT ATIM3_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM3_CC_IRQHandler [WEAK] + EXPORT ATIM3_UP_IRQHandler [WEAK] + EXPORT ATIM4_BRK_IRQHandler [WEAK] + EXPORT ATIM4_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM4_CC_IRQHandler [WEAK] + EXPORT ATIM4_UP_IRQHandler [WEAK] + EXPORT GTIMA1_IRQHandler [WEAK] + EXPORT GTIMA2_IRQHandler [WEAK] + EXPORT GTIMA3_IRQHandler [WEAK] + EXPORT GTIMA4_IRQHandler [WEAK] + EXPORT GTIMA5_IRQHandler [WEAK] + EXPORT GTIMA6_IRQHandler [WEAK] + EXPORT GTIMA7_IRQHandler [WEAK] + EXPORT GTIMB1_IRQHandler [WEAK] + EXPORT GTIMB2_IRQHandler [WEAK] + EXPORT GTIMB3_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT BTIM4_IRQHandler [WEAK] + EXPORT LPTIM1_WKUP_IRQHandler [WEAK] + EXPORT LPTIM2_WKUP_IRQHandler [WEAK] + EXPORT LPTIM3_WKUP_IRQHandler [WEAK] + EXPORT LPTIM4_WKUP_IRQHandler [WEAK] + EXPORT DSMU_FLT0_IRQHandler [WEAK] + EXPORT DSMU_FLT1_IRQHandler [WEAK] + EXPORT DSMU_FLT2_IRQHandler [WEAK] + EXPORT DSMU_FLT3_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT DMAMUX1_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT SysTick_Handler [WEAK] + +WWDG1_IRQHandler +PVD_IRQHandler +RTC_TAMPER_IRQHandler +RTC_WKUP_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI9_5_IRQHandler +EXTI15_10_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +DMA2_Channel0_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA3_Channel0_IRQHandler +DMA3_Channel1_IRQHandler +DMA3_Channel2_IRQHandler +DMA3_Channel3_IRQHandler +DMA3_Channel4_IRQHandler +DMA3_Channel5_IRQHandler +DMA3_Channel6_IRQHandler +DMA3_Channel7_IRQHandler +MDMA_Channel0_IRQHandler +MDMA_Channel1_IRQHandler +MDMA_Channel2_IRQHandler +MDMA_Channel3_IRQHandler +MDMA_Channel4_IRQHandler +MDMA_Channel5_IRQHandler +MDMA_Channel6_IRQHandler +MDMA_Channel7_IRQHandler +MDMA_Channel8_IRQHandler +MDMA_Channel9_IRQHandler +MDMA_Channel10_IRQHandler +MDMA_Channel11_IRQHandler +MDMA_Channel12_IRQHandler +MDMA_Channel13_IRQHandler +MDMA_Channel14_IRQHandler +MDMA_Channel15_IRQHandler +SDPU_IRQHandler +FPU_CPU1_IRQHandler +ECCMON_IRQHandler +RTC_ALARM_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +I2C6_EV_IRQHandler +I2C6_ER_IRQHandler +I2C7_EV_IRQHandler +I2C7_ER_IRQHandler +I2C8_EV_IRQHandler +I2C8_ER_IRQHandler +I2C9_EV_IRQHandler +I2C9_ER_IRQHandler +I2C10_EV_IRQHandler +I2C10_ER_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +I2S3_IRQHandler +I2S4_IRQHandler +xSPI1_IRQHandler +xSPI2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SPI7_IRQHandler +LCD_EV_IRQHandler +LCD_ER_IRQHandler +DVP1_IRQHandler +DVP2_IRQHandler +DMAMUX2_IRQHandler +USB1_HS_EPx_OUT_IRQHandler +USB1_HS_EPx_IN_IRQHandler +USB1_HS_WKUP_IRQHandler +USB1_HS_IRQHandler +USB2_HS_EPx_OUT_IRQHandler +USB2_HS_EPx_IN_IRQHandler +USB2_HS_WKUP_IRQHandler +USB2_HS_IRQHandler +ETH1_IRQHandler +ETH1_PMT_LPI_IRQHandler +ETH2_IRQHandler +ETH2_PMT_LPI_IRQHandler +FDCAN1_INT0_IRQHandler +FDCAN2_INT0_IRQHandler +FDCAN3_INT0_IRQHandler +FDCAN4_INT0_IRQHandler +FDCAN1_INT1_IRQHandler +FDCAN2_INT1_IRQHandler +FDCAN3_INT1_IRQHandler +FDCAN4_INT1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +LPUART1_IRQHandler +LPUART2_IRQHandler +GPU_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +ADC3_IRQHandler +COMP1_2_IRQHandler +COMP3_4_IRQHandler +SHRTIM1_INT1_IRQHandler +SHRTIM1_INT2_IRQHandler +SHRTIM1_INT3_IRQHandler +SHRTIM1_INT4_IRQHandler +SHRTIM1_INT5_IRQHandler +SHRTIM1_INT6_IRQHandler +SHRTIM1_INT7_IRQHandler +SHRTIM1_INT8_IRQHandler +SHRTIM2_INT1_IRQHandler +SHRTIM2_INT2_IRQHandler +SHRTIM2_INT3_IRQHandler +SHRTIM2_INT4_IRQHandler +SHRTIM2_INT5_IRQHandler +SHRTIM2_INT6_IRQHandler +SHRTIM2_INT7_IRQHandler +SHRTIM2_INT8_IRQHandler +FDCAN5_INT0_IRQHandler +FDCAN6_INT0_IRQHandler +FDCAN7_INT0_IRQHandler +FDCAN8_INT0_IRQHandler +FDCAN5_INT1_IRQHandler +FDCAN6_INT1_IRQHandler +FDCAN7_INT1_IRQHandler +FDCAN8_INT1_IRQHandler +DSI_IRQHandler +LPTIM5_WKUP_IRQHandler +JPEG_SGDMA_H2P_IRQHandler +JPEG_SGDMA_P2H_IRQHandler +WAKEUP_IO_IRQHandler +SEMA4_INT1_IRQHandler +WWDG2_RST_IRQHandler +OTPC_IRQHandler +FEMC_IRQHandler +DCMUB_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +MDMA_AHBS_ER_IRQHandler +CM7_CATCH_READ_ER_IRQHandler +DAC3_IRQHandler +DAC4_IRQHandler +EMC_IRQHandler +DAC5_IRQHandler +DAC6_IRQHandler +ESC_OPB_IRQHandler +ESC_SYNC0_IRQHandler +ESC_SYNC1_IRQHandler +ESC_WRP_IRQHandler +ATIM1_BRK_IRQHandler +ATIM1_TRG_COM_IRQHandler +ATIM1_CC_IRQHandler +ATIM1_UP_IRQHandler +ATIM2_BRK_IRQHandler +ATIM2_TRG_COM_IRQHandler +ATIM2_CC_IRQHandler +ATIM2_UP_IRQHandler +ATIM3_BRK_IRQHandler +ATIM3_TRG_COM_IRQHandler +ATIM3_CC_IRQHandler +ATIM3_UP_IRQHandler +ATIM4_BRK_IRQHandler +ATIM4_TRG_COM_IRQHandler +ATIM4_CC_IRQHandler +ATIM4_UP_IRQHandler +GTIMA1_IRQHandler +GTIMA2_IRQHandler +GTIMA3_IRQHandler +GTIMA4_IRQHandler +GTIMA5_IRQHandler +GTIMA6_IRQHandler +GTIMA7_IRQHandler +GTIMB1_IRQHandler +GTIMB2_IRQHandler +GTIMB3_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +BTIM4_IRQHandler +LPTIM1_WKUP_IRQHandler +LPTIM2_WKUP_IRQHandler +LPTIM3_WKUP_IRQHandler +LPTIM4_WKUP_IRQHandler +DSMU_FLT0_IRQHandler +DSMU_FLT1_IRQHandler +DSMU_FLT2_IRQHandler +DSMU_FLT3_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +DMAMUX1_IRQHandler +MMU_IRQHandler +SysTick_Handler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm7_EWARM.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm7_EWARM.s new file mode 100644 index 0000000000..1b3db8abd6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/startup/startup_n32h78x_cm7_EWARM.s @@ -0,0 +1,1535 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + + __iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD 0 ; Reserved + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; Reserved + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_RQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + ;need check to user manual of exti chapter + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK N32SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +N32SysTick_Handler + B N32SysTick_Handler + + PUBWEAK WWDG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG1_IRQHandler + B WWDG1_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_TAMPER_IRQHandler + B RTC_TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK DMA2_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel0_IRQHandler + B DMA2_Channel0_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA3_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel0_IRQHandler + B DMA3_Channel0_IRQHandler + + PUBWEAK DMA3_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel1_IRQHandler + B DMA3_Channel1_IRQHandler + + PUBWEAK DMA3_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel2_IRQHandler + B DMA3_Channel2_IRQHandler + + PUBWEAK DMA3_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel3_IRQHandler + B DMA3_Channel3_IRQHandler + + PUBWEAK DMA3_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel4_IRQHandler + B DMA3_Channel4_IRQHandler + + PUBWEAK DMA3_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel5_IRQHandler + B DMA3_Channel5_IRQHandler + + PUBWEAK DMA3_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel6_IRQHandler + B DMA3_Channel6_IRQHandler + + PUBWEAK DMA3_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel7_IRQHandler + B DMA3_Channel7_IRQHandler + + PUBWEAK MDMA_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel0_IRQHandler + B MDMA_Channel0_IRQHandler + + PUBWEAK MDMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel1_IRQHandler + B MDMA_Channel1_IRQHandler + + PUBWEAK MDMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel2_IRQHandler + B MDMA_Channel2_IRQHandler + + PUBWEAK MDMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel3_IRQHandler + B MDMA_Channel3_IRQHandler + + PUBWEAK MDMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel4_IRQHandler + B MDMA_Channel4_IRQHandler + + PUBWEAK MDMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel5_IRQHandler + B MDMA_Channel5_IRQHandler + + PUBWEAK MDMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel6_IRQHandler + B MDMA_Channel6_IRQHandler + + PUBWEAK MDMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel7_IRQHandler + B MDMA_Channel7_IRQHandler + + PUBWEAK MDMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel8_IRQHandler + B MDMA_Channel8_IRQHandler + + PUBWEAK MDMA_Channel9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel9_IRQHandler + B MDMA_Channel9_IRQHandler + + PUBWEAK MDMA_Channel10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel10_IRQHandler + B MDMA_Channel10_IRQHandler + + PUBWEAK MDMA_Channel11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel11_IRQHandler + B MDMA_Channel11_IRQHandler + + PUBWEAK MDMA_Channel12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel12_IRQHandler + B MDMA_Channel12_IRQHandler + + PUBWEAK MDMA_Channel13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel13_IRQHandler + B MDMA_Channel13_IRQHandler + + PUBWEAK MDMA_Channel14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel14_IRQHandler + B MDMA_Channel14_IRQHandler + + PUBWEAK MDMA_Channel15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel15_IRQHandler + B MDMA_Channel15_IRQHandler + + PUBWEAK SDPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDPU_IRQHandler + B SDPU_IRQHandler + + PUBWEAK FPU_CPU1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_CPU1_IRQHandler + B FPU_CPU1_IRQHandler + + PUBWEAK ECCMON_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECCMON_IRQHandler + B ECCMON_IRQHandler + + PUBWEAK RTC_ALARM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_ALARM_IRQHandler + B RTC_ALARM_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK I2C6_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_EV_IRQHandler + B I2C6_EV_IRQHandler + + PUBWEAK I2C6_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_ER_IRQHandler + B I2C6_ER_IRQHandler + + PUBWEAK I2C7_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_EV_IRQHandler + B I2C7_EV_IRQHandler + + PUBWEAK I2C7_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_ER_IRQHandler + B I2C7_ER_IRQHandler + + PUBWEAK I2C8_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_EV_IRQHandler + B I2C8_EV_IRQHandler + + PUBWEAK I2C8_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_ER_IRQHandler + B I2C8_ER_IRQHandler + + PUBWEAK I2C9_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_EV_IRQHandler + B I2C9_EV_IRQHandler + + PUBWEAK I2C9_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_ER_IRQHandler + B I2C9_ER_IRQHandler + + PUBWEAK I2C10_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_EV_IRQHandler + B I2C10_EV_IRQHandler + + PUBWEAK I2C10_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_ER_IRQHandler + B I2C10_ER_IRQHandler + + PUBWEAK I2S1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S1_IRQHandler + B I2S1_IRQHandler + + PUBWEAK I2S2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S2_IRQHandler + B I2S2_IRQHandler + + PUBWEAK I2S3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S3_IRQHandler + B I2S3_IRQHandler + + PUBWEAK I2S4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S4_IRQHandler + B I2S4_IRQHandler + + PUBWEAK xSPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI1_IRQHandler + B xSPI1_IRQHandler + + PUBWEAK xSPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI2_IRQHandler + B xSPI2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SPI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI7_IRQHandler + B SPI7_IRQHandler + + PUBWEAK LCD_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_EV_IRQHandler + B LCD_EV_IRQHandler + + PUBWEAK LCD_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_ER_IRQHandler + B LCD_ER_IRQHandler + + PUBWEAK DVP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP1_IRQHandler + B DVP1_IRQHandler + + PUBWEAK DVP2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP2_IRQHandler + B DVP2_IRQHandler + + PUBWEAK DMAMUX2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX2_IRQHandler + B DMAMUX2_IRQHandler + + PUBWEAK USB1_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_OUT_IRQHandler + B USB1_HS_EPx_OUT_IRQHandler + + PUBWEAK USB1_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_IN_IRQHandler + B USB1_HS_EPx_IN_IRQHandler + + PUBWEAK USB1_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_WKUP_IRQHandler + B USB1_HS_WKUP_IRQHandler + + PUBWEAK USB1_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_IRQHandler + B USB1_HS_IRQHandler + + PUBWEAK USB2_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_OUT_IRQHandler + B USB2_HS_EPx_OUT_IRQHandler + + PUBWEAK USB2_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_IN_IRQHandler + B USB2_HS_EPx_IN_IRQHandler + + PUBWEAK USB2_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_WKUP_IRQHandler + B USB2_HS_WKUP_IRQHandler + + PUBWEAK USB2_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_IRQHandler + B USB2_HS_IRQHandler + + PUBWEAK ETH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_IRQHandler + B ETH1_IRQHandler + + PUBWEAK ETH1_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_PMT_LPI_IRQHandler + B ETH1_PMT_LPI_IRQHandler + + PUBWEAK ETH2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_IRQHandler + B ETH2_IRQHandler + + PUBWEAK ETH2_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_PMT_LPI_IRQHandler + B ETH2_PMT_LPI_IRQHandler + + PUBWEAK FDCAN1_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT0_IRQHandler + B FDCAN1_INT0_IRQHandler + + PUBWEAK FDCAN2_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT0_IRQHandler + B FDCAN2_INT0_IRQHandler + + PUBWEAK FDCAN3_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT0_IRQHandler + B FDCAN3_INT0_IRQHandler + + PUBWEAK FDCAN4_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT0_IRQHandler + B FDCAN4_INT0_IRQHandler + + PUBWEAK FDCAN1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT1_IRQHandler + B FDCAN1_INT1_IRQHandler + + PUBWEAK FDCAN2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT1_IRQHandler + B FDCAN2_INT1_IRQHandler + + PUBWEAK FDCAN3_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT1_IRQHandler + B FDCAN3_INT1_IRQHandler + + PUBWEAK FDCAN4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT1_IRQHandler + B FDCAN4_INT1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK USART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART7_IRQHandler + B USART7_IRQHandler + + PUBWEAK USART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART8_IRQHandler + B USART8_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK UART11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART11_IRQHandler + B UART11_IRQHandler + + PUBWEAK UART12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART12_IRQHandler + B UART12_IRQHandler + + PUBWEAK UART13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART13_IRQHandler + B UART13_IRQHandler + + PUBWEAK UART14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART14_IRQHandler + B UART14_IRQHandler + + PUBWEAK UART15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART15_IRQHandler + B UART15_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPUART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART2_IRQHandler + B LPUART2_IRQHandler + + PUBWEAK GPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPU_IRQHandler + B GPU_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK COMP1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP1_2_IRQHandler + B COMP1_2_IRQHandler + + PUBWEAK COMP3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP3_4_IRQHandler + B COMP3_4_IRQHandler + + PUBWEAK SHRTIM1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT1_IRQHandler + B SHRTIM1_INT1_IRQHandler + + PUBWEAK SHRTIM1_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT2_IRQHandler + B SHRTIM1_INT2_IRQHandler + + PUBWEAK SHRTIM1_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT3_IRQHandler + B SHRTIM1_INT3_IRQHandler + + PUBWEAK SHRTIM1_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT4_IRQHandler + B SHRTIM1_INT4_IRQHandler + + PUBWEAK SHRTIM1_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT5_IRQHandler + B SHRTIM1_INT5_IRQHandler + + PUBWEAK SHRTIM1_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT6_IRQHandler + B SHRTIM1_INT6_IRQHandler + + PUBWEAK SHRTIM1_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT7_IRQHandler + B SHRTIM1_INT7_IRQHandler + + PUBWEAK SHRTIM1_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT8_IRQHandler + B SHRTIM1_INT8_IRQHandler + + PUBWEAK SHRTIM2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT1_IRQHandler + B SHRTIM2_INT1_IRQHandler + + PUBWEAK SHRTIM2_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT2_IRQHandler + B SHRTIM2_INT2_IRQHandler + + PUBWEAK SHRTIM2_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT3_IRQHandler + B SHRTIM2_INT3_IRQHandler + + PUBWEAK SHRTIM2_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT4_IRQHandler + B SHRTIM2_INT4_IRQHandler + + PUBWEAK SHRTIM2_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT5_IRQHandler + B SHRTIM2_INT5_IRQHandler + + PUBWEAK SHRTIM2_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT6_IRQHandler + B SHRTIM2_INT6_IRQHandler + + PUBWEAK SHRTIM2_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT7_IRQHandler + B SHRTIM2_INT7_IRQHandler + + PUBWEAK SHRTIM2_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT8_IRQHandler + B SHRTIM2_INT8_IRQHandler + + PUBWEAK FDCAN5_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT0_IRQHandler + B FDCAN5_INT0_IRQHandler + + PUBWEAK FDCAN6_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT0_IRQHandler + B FDCAN6_INT0_IRQHandler + + PUBWEAK FDCAN7_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT0_IRQHandler + B FDCAN7_INT0_IRQHandler + + PUBWEAK FDCAN8_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT0_IRQHandler + B FDCAN8_INT0_IRQHandler + + PUBWEAK FDCAN5_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT1_IRQHandler + B FDCAN5_INT1_IRQHandler + + PUBWEAK FDCAN6_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT1_IRQHandler + B FDCAN6_INT1_IRQHandler + + PUBWEAK FDCAN7_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT1_IRQHandler + B FDCAN7_INT1_IRQHandler + + PUBWEAK FDCAN8_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT1_IRQHandler + B FDCAN8_INT1_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK LPTIM5_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM5_WKUP_IRQHandler + B LPTIM5_WKUP_IRQHandler + + PUBWEAK JPEG_SGDMA_H2P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_H2P_IRQHandler + B JPEG_SGDMA_H2P_IRQHandler + + PUBWEAK JPEG_SGDMA_P2H_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_P2H_IRQHandler + B JPEG_SGDMA_P2H_IRQHandler + + PUBWEAK WAKEUP_IO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WAKEUP_IO_IRQHandler + B WAKEUP_IO_IRQHandler + + PUBWEAK SEMA4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_INT1_IRQHandler + B SEMA4_INT1_IRQHandler + + PUBWEAK WWDG2_RST_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_RST_IRQHandler + B WWDG2_RST_IRQHandler + + PUBWEAK OTPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTPC_IRQHandler + B OTPC_IRQHandler + + PUBWEAK FEMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FEMC_IRQHandler + B FEMC_IRQHandler + + PUBWEAK DCMUB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMUB_IRQHandler + B DCMUB_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK MDMA_AHBS_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_AHBS_ER_IRQHandler + B MDMA_AHBS_ER_IRQHandler + + PUBWEAK CM7_CATCH_READ_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CM7_CATCH_READ_ER_IRQHandler + B CM7_CATCH_READ_ER_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK DAC4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC4_IRQHandler + B DAC4_IRQHandler + + PUBWEAK EMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMC_IRQHandler + B EMC_IRQHandler + + PUBWEAK DAC5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC5_IRQHandler + B DAC5_IRQHandler + + PUBWEAK DAC6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC6_IRQHandler + B DAC6_IRQHandler + + PUBWEAK ESC_OPB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_OPB_IRQHandler + B ESC_OPB_IRQHandler + + PUBWEAK ESC_SYNC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC0_IRQHandler + B ESC_SYNC0_IRQHandler + + PUBWEAK ESC_SYNC1_RQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC1_RQHandler + B ESC_SYNC1_RQHandler + + PUBWEAK ESC_WRP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_WRP_IRQHandler + B ESC_WRP_IRQHandler + + PUBWEAK ATIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_BRK_IRQHandler + B ATIM1_BRK_IRQHandler + + PUBWEAK ATIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_TRG_COM_IRQHandler + B ATIM1_TRG_COM_IRQHandler + + PUBWEAK ATIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_CC_IRQHandler + B ATIM1_CC_IRQHandler + + PUBWEAK ATIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_UP_IRQHandler + B ATIM1_UP_IRQHandler + + PUBWEAK ATIM2_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_BRK_IRQHandler + B ATIM2_BRK_IRQHandler + + PUBWEAK ATIM2_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_TRG_COM_IRQHandler + B ATIM2_TRG_COM_IRQHandler + + PUBWEAK ATIM2_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_CC_IRQHandler + B ATIM2_CC_IRQHandler + + PUBWEAK ATIM2_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_UP_IRQHandler + B ATIM2_UP_IRQHandler + + PUBWEAK ATIM3_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_BRK_IRQHandler + B ATIM3_BRK_IRQHandler + + PUBWEAK ATIM3_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_TRG_COM_IRQHandler + B ATIM3_TRG_COM_IRQHandler + + PUBWEAK ATIM3_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_CC_IRQHandler + B ATIM3_CC_IRQHandler + + PUBWEAK ATIM3_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_UP_IRQHandler + B ATIM3_UP_IRQHandler + + PUBWEAK ATIM4_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_BRK_IRQHandler + B ATIM4_BRK_IRQHandler + + PUBWEAK ATIM4_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_TRG_COM_IRQHandler + B ATIM4_TRG_COM_IRQHandler + + PUBWEAK ATIM4_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_CC_IRQHandler + B ATIM4_CC_IRQHandler + + PUBWEAK ATIM4_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_UP_IRQHandler + B ATIM4_UP_IRQHandler + + PUBWEAK GTIMA1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA1_IRQHandler + B GTIMA1_IRQHandler + + PUBWEAK GTIMA2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA2_IRQHandler + B GTIMA2_IRQHandler + + PUBWEAK GTIMA3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA3_IRQHandler + B GTIMA3_IRQHandler + + PUBWEAK GTIMA4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA4_IRQHandler + B GTIMA4_IRQHandler + + PUBWEAK GTIMA5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA5_IRQHandler + B GTIMA5_IRQHandler + + PUBWEAK GTIMA6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA6_IRQHandler + B GTIMA6_IRQHandler + + PUBWEAK GTIMA7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA7_IRQHandler + B GTIMA7_IRQHandler + + PUBWEAK GTIMB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB1_IRQHandler + B GTIMB1_IRQHandler + + PUBWEAK GTIMB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB2_IRQHandler + B GTIMB2_IRQHandler + + PUBWEAK GTIMB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB3_IRQHandler + B GTIMB3_IRQHandler + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + PUBWEAK BTIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM4_IRQHandler + B BTIM4_IRQHandler + + PUBWEAK LPTIM1_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_WKUP_IRQHandler + B LPTIM1_WKUP_IRQHandler + + PUBWEAK LPTIM2_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM2_WKUP_IRQHandler + B LPTIM2_WKUP_IRQHandler + + PUBWEAK LPTIM3_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM3_WKUP_IRQHandler + B LPTIM3_WKUP_IRQHandler + + PUBWEAK LPTIM4_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM4_WKUP_IRQHandler + B LPTIM4_WKUP_IRQHandler + + PUBWEAK DSMU_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT0_IRQHandler + B DSMU_FLT0_IRQHandler + + PUBWEAK DSMU_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT1_IRQHandler + B DSMU_FLT1_IRQHandler + + PUBWEAK DSMU_FLT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT2_IRQHandler + B DSMU_FLT2_IRQHandler + + PUBWEAK DSMU_FLT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT3_IRQHandler + B DSMU_FLT3_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK DMAMUX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX1_IRQHandler + B DMAMUX1_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/system_n32h76x_78x.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/system_n32h76x_78x.c new file mode 100644 index 0000000000..08b4d5e8dc --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/system_n32h76x_78x.c @@ -0,0 +1,233 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file system_n32h76x_78x.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000UL) /* Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000UL) /* Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000UL) /* Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#define VECT_TAB_OFFSET ((uint32_t)0x00000000UL) /* Vector Table base offset field. */ + +#define FLASH_BANK1_BASE (0x15000000U) + +#define FLASH_BANK2_BASE (0x15080000U) + +uint32_t SystemCoreClock = 600000000; + +#define TCM_SIZE_VALUE (0x20) /*TCM_SIZE=0x20 :256 KB ITCM,256 KB DTCM,512 KB AXI_SRAM*/ + +/** Private_Functions */ + +/* defaule power supply is extern LDO. User can change the way of power supply*/ +//#define PWR_SUPPLY_SELECTION (PWR_LDO_SUPPLY) /* External LDO Supply */ +#define PWR_SUPPLY_SELECTION (PWR_DIRECT_SMPS_SUPPLY) /* DCDC Supply */ +//#define PWR_SUPPLY_SELECTION (PWR_EXTERNAL_SOURCE_SUPPLY) /* VCAP Supply */ + +/** + *\*\name ConfigTcmSize. + *\*\fun Config TCM_SIZE + *\*\param tcmSizeValue : + *\*\ 0x00 :1024KB ITCM,0 KB DTCM,0 KB AXI_SRAM + *\*\ 0x01 :896 KB ITCM,128 KB DTCM,0 KB AXI_SRAM + *\*\ 0x02 :768 KB ITCM,256 KB DTCM,0 KB AXI_SRAM + *\*\ 0x03 :640 KB ITCM,384 KB DTCM,0 KB AXI_SRAM + *\*\ 0x04 :512 KB ITCM,512 KB DTCM,0 KB AXI_SRAM + *\*\ 0x05 :384 KB ITCM,640 KB DTCM,0 KB AXI_SRAM + *\*\ 0x06 :256 KB ITCM,768 KB DTCM,0 KB AXI_SRAM + *\*\ 0x07 :128 KB ITCM,896 KB DTCM,0 KB AXI_SRAM + *\*\ 0x08 :0 KB ITCM,1024KB DTCM,0 KB AXI_SRAM + *\*\ 0x09 :896 KB ITCM,0 KB DTCM,128 KB AXI_SRAM + *\*\ 0x0A :768 KB ITCM,128 KB DTCM,128 KB AXI_SRAM + *\*\ 0x0B :640 KB ITCM,256 KB DTCM,128 KB AXI_SRAM + *\*\ 0x0C :512 KB ITCM,384 KB DTCM,128 KB AXI_SRAM + *\*\ 0x0D :384 KB ITCM,512 KB DTCM,128 KB AXI_SRAM + *\*\ 0x0E :256 KB ITCM,640 KB DTCM,128 KB AXI_SRAM + *\*\ 0x0F :128 KB ITCM,768 KB DTCM,128 KB AXI_SRAM + *\*\ 0x10 :0 KB ITCM,896 KB DTCM,128 KB AXI_SRAM + *\*\ 0x11 :768 KB ITCM,0 KB DTCM,256 KB AXI_SRAM + *\*\ 0x12 :640 KB ITCM,128 KB DTCM,256 KB AXI_SRAM + *\*\ 0x13 :512 KB ITCM,256 KB DTCM,256 KB AXI_SRAM + *\*\ 0x14 :384 KB ITCM,384 KB DTCM,256 KB AXI_SRAM + *\*\ 0x15 :256 KB ITCM,512 KB DTCM,256 KB AXI_SRAM + *\*\ 0x16 :128 KB ITCM,640 KB DTCM,256 KB AXI_SRAM + *\*\ 0x17 :0 KB ITCM,768 KB DTCM,256 KB AXI_SRAM + *\*\ 0x18 :640 KB ITCM,0 KB DTCM,384 KB AXI_SRAM + *\*\ 0x19 :512 KB ITCM,128 KB DTCM,384 KB AXI_SRAM + *\*\ 0x1A :384 KB ITCM,256 KB DTCM,384 KB AXI_SRAM + *\*\ 0x1B :256 KB ITCM,384 KB DTCM,384 KB AXI_SRAM + *\*\ 0x1C :128 KB ITCM,512 KB DTCM,384 KB AXI_SRAM + *\*\ 0x1D :0 KB ITCM,640 KB DTCM,384 KB AXI_SRAM + *\*\ 0x1E :512 KB ITCM,0 KB DTCM,512 KB AXI_SRAM + *\*\ 0x1F :384 KB ITCM,128 KB DTCM,512 KB AXI_SRAM + *\*\ 0x20 :256 KB ITCM,256 KB DTCM,512 KB AXI_SRAM + *\*\ 0x21 :128 KB ITCM,384 KB DTCM,512 KB AXI_SRAM + *\*\ 0x22 :0 KB ITCM,512 KB DTCM,512 KB AXI_SRAM + *\*\ 0x23 :384 KB ITCM,0 KB DTCM,640 KB AXI_SRAM + *\*\ 0x24 :256 KB ITCM,128 KB DTCM,640 KB AXI_SRAM + *\*\ 0x25 :128 KB ITCM,256 KB DTCM,640 KB AXI_SRAM + *\*\ 0x26 :0 KB ITCM,384 KB DTCM,640 KB AXI_SRAM + *\*\ 0x27 :256 KB ITCM,0 KB DTCM,768 KB AXI_SRAM + *\*\ 0x28 :128 KB ITCM,128 KB DTCM,768 KB AXI_SRAM + *\*\ 0x29 :0 KB ITCM,256 KB DTCM,768 KB AXI_SRAM + *\*\ 0x2A :128 KB ITCM,0 KB DTCM,896 KB AXI_SRAM + *\*\ 0x2B :0 KB ITCM,128 KB DTCM,896 KB AXI_SRAM + *\*\ 0x2C~2F :0KB ITCM,0 KB DTCM,1024KB AXI_SRAM + *\*\return none + */ +void ConfigTcmSize(uint32_t tcmSizeValue) +{ + uint32_t currValue = (*(uint32_t(*)(void))0x1ff00f01)(); + if((currValue == 0x2c) && (currValue != tcmSizeValue)) + { + *(uint32_t*)0x51105280 = tcmSizeValue; + NVIC_SystemReset(); + } +} +#ifdef CORE_CM7 +/** +*\*\name PWR_ConfigSupply. +*\*\fun Configure the PWR supply. +*\*\param SupplySource (The input parameters must be the following values): +*\*\ - PWR_LDO_SUPPLY :External LDO SUPPLY +*\*\ - PWR_DIRECT_SMPS_SUPPLY :DCDC SUPPLY +*\*\ - PWR_EXTERNAL_SOURCE_SUPPLY :External VCAP SUPPLY +*\*\return none +**/ +static void PWR_ConfigSupply(uint32_t SupplySource) +{ + __IO uint32_t tempreg; + /* Get the old register value */ + tempreg = PWR->SYSCTRL4; + /* Clear the old value */ + tempreg &= (~PWR_SUPPLY_MODE_MASK); + /* Set the new values */ + tempreg |= SupplySource; + /* Set the power supply configuration */ + PWR->SYSCTRL4 = tempreg; +} +#endif +/** + *\*\name SystemInit. + *\*\fun Setup the microcontroller system.Initialize the FPU setting, vector table location and External memory configuration. + *\*\param none + *\*\return none + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is + detectable by the CPU after a WFI/WFE instruction.*/ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; + +#ifdef CORE_CM7 + +#endif /* CORE_CM7*/ + +#ifdef CORE_CM4 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = 0x30000000; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#ifdef CORE_CM7 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = 0x24000000; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /*defaule TCM_SIZE=0x3f,All TCMSRAM are AXI_SRAM,if you want to use ITCM/DTCM, define INIT_TCM_SIZE*/ +#ifdef USING_TCM + ConfigTcmSize(TCM_SIZE_VALUE); +#endif + /*User can change the way of power supply */ + PWR_ConfigSupply(PWR_SUPPLY_SELECTION); + +#else +#error Please #define CORE_CM4 or CORE_CM7 +#endif +#endif +} + + +/** + *\*\name N32SysTick_Handler. + *\*\fun This function handles N32SysTick Handler. + *\*\param none + *\*\return none + */ +void N32SysTick_Handler(void) +{ + +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/system_n32h76x_78x.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/system_n32h76x_78x.h new file mode 100644 index 0000000000..08f1b3cc79 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/CMSIS/device/system_n32h76x_78x.h @@ -0,0 +1,79 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file system_n32h76x_78x.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __SYSTEM_N32H76X_78X_H__ +#define __SYSTEM_N32H76X_78X_H__ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** N32H76X_78X_System */ + + /** Power supply source configuration **/ +#define PWR_SUPPLY_MODE_MASK (PWR_SYSCTRL4_MLDOEN | PWR_SYSCTRL4_DCDCEN | PWR_SYSCTRL4_VCORESRC | PWR_SYSCTRL4_DCDCFRCEN) +#define PWR_LDO_SUPPLY (PWR_SYSCTRL4_MLDOEN) /* Core domains are supplied from the LDO */ +#define PWR_DIRECT_SMPS_SUPPLY (PWR_SYSCTRL4_DCDCEN) /* Core domains are supplied from the SMPS */ +#define PWR_EXTERNAL_SOURCE_SUPPLY (PWR_SYSCTRL4_VCORESRC) /* The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ + + + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +extern void SystemInit(void); +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_N32H76X_78X_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_Common.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_Common.h new file mode 100644 index 0000000000..b3bb87af01 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_Common.h @@ -0,0 +1,273 @@ +/***************************************************************************** +* NationS Microcontroller Software Support +* ---------------------------------------------------------------------------- +* Copyright (c) 2022, NationS Corporation +* +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* NationS's name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ +/***************************************************************************** +* File Name: Common.h +* Function: Defining Common algorithm library API +* version: V1.0 +* Author: Nations Solution Team +* date: 2022-05-23 +* ****************************************************************************/ +#ifndef _Common_H_ +#define _Common_H_ +#include + +enum{ + Cpy_OK=0x5a5a5a5a,//copy success + SetData_OK = 0x5a5a5a5a,//set zero success + Reverse_OK = 0x5a5a5a5a, //reverse success + IsZero_NOT = 0x5a5a5a5a, //Big number is not zero + IsOne_NOT = 0x5a5a5a5a,//big number is one + IsOne_YES = 0x05a5a5a5,//big number is not one + IsZero_YES = 0x05a5a5a5, //Big number is zero + + Cmp_EQUAL = 0, //Two big number are equal + Cmp_LESS = (int32_t)0xa5a55a5a, //The former big number is less than the latter + Cmp_GREATER = 0x1a5a5a5a,//The former big number is greater than the latter + Cmp_ERROR=0x3a3a3a3a, + RandomSort_OK = 0x5a5a5a5a, //disturb order success + XOR_OK=0x5a5a5a5a, //XOR success + Reverse_ERROR = 0x7A9E0863, //reverse fail due to src and dst are same +}; +typedef struct +{ + uint32_t *data; + uint32_t wordLen; +}N_BIGNUM; +/** + * @brief disturb the sequence order + * @param[in] order pointer to the sequence to be disturbed + * @param[in] rand pointer to random number + * @param[in] the length of order + * @return RandomSort_OK: disturb order success; Others: disturb order fail; + * @note + */ +uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len); + +/** + * @brief Copy data by byte + * @param[in] dst pointer to destination data + * @param[in] src pointer to source data + * @param[in] byte length + * @return Cpy_OK: success; others: fail. + * @note 1. dst and src cannot be same + */ +uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen); + +/** + * @brief Copy data by word + * @param[in] dst pointer to destination data + * @param[in] src pointer to source data + * @param[in] word length + * @return Cpy_OK: success; others: fail. + * @note 1. dst and src must be aligned by word + */ +uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen); + + + /** + * @brief XOR + * @param[in] a pointer to one data to be XORed + * @param[in] b pointer to another data to be XORed + * @param[in] the length of order + * @return XOR_OK: operation success; Others: operation fail; + * @note + */ +uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen); + + /** + * @brief XORed two u32 arrays + * @param[in] a pointer to one data to be XORed + * @param[in] b pointer to another data to be XORed + * @param[in] the length of order + * @return XOR_OK: operation success; Others: operation fail; + * @note + */ +uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen); + +/** + * @brief set data by byte + * @param[in] dst pointer to the address to be set data + * @param[in] data + * @param[in] byte length + * @return SetData_OK: success; others: fail. + * @note + */ +uint32_t SetData_U8(uint8_t *dst,uint8_t data, uint32_t byteLen); + +/** + * @brief set data by word + * @param[in] dst pointer to the address to be set data + * @param[in] data + * @param[in] word length + * @return SetData_OK: success; others: fail. + * @note + */ +uint32_t SetData_U32(uint32_t *dst,uint32_t data, uint32_t wordLen); + +/** + * @brief byte reverse through the whole byte array + * @param[in] dst pointer to the address to be set zero + * @param[in] byte length + * @return Reverse_OK: success; others: fail. + * @note 1.dst and src can be same + 2.first byte and last byte of the array are swapped + */ +uint32_t Reverse_U8(uint8_t *dst, const uint8_t *src, uint32_t byteLen);//�ֽڼ��С��ת�� + +/** + * @brief word reverse((0x00010203,04050607,0x08090A0B)->(0x08090A0B,04050607,0x00010203)) + * @param[out] dst pointer to the destination address + * @param[in] dst pointer to the source address + * @param[in] word length of src + * @return Reverse_OK: success; others: fail. + * @note 1.dst and src can be same + 2.first word and last word of the array are swapped; the words stay the same + */ +uint32_t Reverse_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);//�ּ��С��ת�� + +/** + * @brief reverse byte order of every word, the words stay the same + * @param[in] dst pointer to the destination address + * @param[in] src pointer to the source address + * @param[in] word length + * @return Reverse_OK: success; others: fail. + * @note 1.dst and src can be same + */ +uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);//���ڴ�С��ת�� + +/** + * @brief get bit length of a byte array + * @param[in] n pointer to the array + * @param[in] byteLen + * @return bit length + * @note 1. the byte array is little byte-endian + */ +uint32_t GetBitLen_U8(const uint8_t *n, uint32_t byteLen); + +/** + * @brief get the bit length of big number + * @param[in] n pointer to big number + * @param[in] word length of src + * @return The bit length of n + * @note 1. word little-endian; in a word, it's byte little-endian + */ +uint32_t GetBitLen_U32(const uint32_t *n, uint32_t wordLen); + +/** + * @brief check whether big number is zero or not + * @param[in] n pointer to big number + * @param[in] word length of n + * @return IsZero_YES: zero; IsZero_NOT: not zero. + * @note 1. word little-endian; in a word, it's byte little-endian + */ +uint32_t IsZero_U32(const uint32_t *n, uint32_t wordLen); + +/** + * @brief check whether big number is zero or not + * @param[in] n pointer to big number + * @param[in] byte length of n + * @return IsZero_YES: zero; IsZero_NOT: not zero. + * @note 1. word little-endian; in a word, it's byte little-endian + */ +uint32_t IsZero_U8(const uint8_t *n, uint32_t byteLen); + +/** + * @brief check whether the big number is one or not + * @param[in] n pointer to big number + * @param[in] the word length of n + * @return IsOne_NOT: big number is not one; IsOne_YES: big number is one; + * @note + */ +uint32_t IsOne_U32(const uint32_t *n, uint32_t wordLen); + +/** + * @brief compare two big number + * @param[in] a pointer to one big number + * @param[in] word length of a + * @param[in] b pointer to another big number + * @param[in] word length of b + * @return Cmp_GREATER: a > b; Cmp_LESS: a < b;Cmp_EQUAL: a==b. + * @note 1. word little-endian; in a word, it's byte little-endian + */ +int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen); + +/** + * @brief compare two big number + * @param[in] a pointer to one big number + * @param[in] word length of a + * @param[in] b pointer to another big number + * @param[in] word length of b + * @return Cmp_GREATER: a > b; Cmp_LESS: a < b;Cmp_EQUAL: a==b. + * @note 1. it's byte big-endian + */ +int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen); + +/** + * @brief Load data from buffer to FIFO + * @param[out] dst pointer to destination data + * @param[in] src pointer to source data + * @param[in] word length + * @return Cpy_OK: success; others: fail. + * @note + */ +uint32_t BufToFIFO(volatile uint32_t *dst, const void *src, uint32_t wordLen); + +/** + * @brief Copy data from FIFO to buffer + * @param[out] dst pointer to destination data + * @param[in] src pointer to source data + * @param[in] word length + * @return Cpy_OK: success; others: fail. + * @note + */ +uint32_t FIFOToBuf(void *dst, volatile uint32_t *src, uint32_t wordLen); +/** + * @brief compare two big number(scrambling sequence) + * @param[in] a pointer to one big number + * @param[in] b pointer to another big number + * @param[in] word length of a or b + * @param[in] order pointer to scrambling sequence + * @return Cmp_GREATER: a > b; Cmp_LESS: a < b;Cmp_EQUAL: a==b. + * @note 1. word little-endian; in a word, it's byte little-endian + */ +int32_t Cmp_U32_S(const uint32_t *a, const uint32_t *b, uint32_t wordLen, const uint8_t *order); + + +/** + * @brief compare a and b in byte length + * @param[in] a + * @param[in] b + * @param[in] byteLen + * @param[in] order + * @return Cmp_LESS, a < b Cmp_EQUAL, a = b Cmp_GREATER, a > b Cmp_ERROR, error happens + * @note a[8]={0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x89}, b[8]={0x12,0x22,0x33,0x44,0x55,0x66,0x77,0x88} Cmp_U8_S(a,b) = Cmp_LESS + */ + +int32_t Cmp_U8_S(const uint8_t *a, const uint8_t *b, uint32_t byteLen, const uint8_t *order); +#endif + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_DES.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_DES.h new file mode 100644 index 0000000000..da227a3335 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_DES.h @@ -0,0 +1,131 @@ +/***************************************************************************** +* NationS Microcontroller Software Support +* ---------------------------------------------------------------------------- +* Copyright (c) 2025, NationS Corporation +* +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* NationS's name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ +/*****************************************************************************/ +/***************************************************************************** +* File Name: DES.h +* Function: Defining DES algorithm library API +* version: V1.0 +* Author: nations +* date: 2025-04-15 +* ****************************************************************************/ +#ifndef _DES_H_ +#define _DES_H_ + +#include +#include "n32h76x_78x_Common.h" +#define DES_ECB (0) +#define DES_CBC (1) +#define DES_ENCRYPT 0 +#define DES_DECRYPT 1 + +#define TDES_ECB (0) +#define TDES_CBC (1) +#define TDES_ENCRYPT 0 +#define TDES_DECRYPT 1 + +enum DES +{ + DES_Init_OK = 0x2a2a7a7a, //DES opreation success + DES_Crypto_OK = 0x2a2a7a7a, //DES opreation success + DES_ModeErr = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC) + DES_EnDeErr, //En&De error(Neither encryption nor decryption) + DES_ParaNull, // the part of input(output/iv) Null + DES_KeyLenErr, + DES_LengthErr, + DES_ATTACKED, //DES subjected to attack +}; +typedef struct +{ + uint8_t *in; // the part of input to be encrypted or decrypted + uint8_t *iv; // the part of initial vector + uint8_t *out; // the part of out + uint8_t *key; // the part of key + uint32_t inByteLen; // the length(by byte) of plaintext or cipher + uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt + uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC + uint32_t keyByteLen; //the length(by byte) of key +}DES_PARM; + +typedef DES_PARM TDES_PARM; + + + + +/** + * @brief DES Init + * @param[in] parm pointer to DES context and the detail please refer to struct DES_PARM in DES.h + * @return DES_Init_OK, DES Init success; othets: DES Init fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2. IV can be NULL when ECB mode + * 3. The byte lengrh of message must be as times as 8. + */ +uint32_t DES_Init(DES_PARM *parm); + + + + + +/** + * @brief DES crypto + * @param[in] parm pointer to DES context and the detail please refer to struct DES_PARM in SM1.h + * @return DES_Crypto_OK, DES crypto success; othets: DES crypto fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2. IV can be NULL when ECB mode + * 3. The byte lengrh of message must be as times as 8. + */ + uint32_t DES_Crypto1(DES_PARM *parm); + +/** + * @brief DES close + * @return none + * @note + */ + void DES_Close(void); + + +#define TDES_Init DES_Init +#define TDES_Crypto1 DES_Crypto1 +#define TDES_Close DES_Close + +/** + * @brief Get DES lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get DES lib information + */ + void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + +#define TDES_Version DES_Version +#endif /*_DES_H_*/ + + +/** @} */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_HASH.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_HASH.h new file mode 100644 index 0000000000..ce79776dd4 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_HASH.h @@ -0,0 +1,216 @@ +/***************************************************************************** +* NationS Microcontroller Software Support +* ---------------------------------------------------------------------------- +* Copyright (c) 2025, NationS Corporation +* +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* NationS's name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ +/*****************************************************************************/ +/***************************************************************************** +* File Name:Hash.h +* Function: Defining AES algorithm library API +* version: V1.0 +* Author: nations +* date: 2025-04-15 +* ****************************************************************************/ +#ifndef _HASH_H_ +#define _HASH_H_ +#include "n32h76x_78x_Common.h" +#define ALG_SHA1 (uint16_t)(0x0004) +#define ALG_SHA224 (uint16_t)(0x000A) +#define ALG_SHA256 (uint16_t)(0x000B) +#define ALG_SHA384 (uint16_t)(0x000C) +#define ALG_SHA512 (uint16_t)(0x000D) + +enum +{ + HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV + HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV + HASH_Init_OK = 0x5a5a5a5a,//hash init success + HASH_Start_OK = 0x5a5a5a5a,//hash update success + HASH_Update_OK = 0x5a5a5a5a,//hash update success + HASH_Complete_OK = 0x5a5a5a5a,//hash complete success + HASH_Close_OK = 0x5a5a5a5a,//hash close success + HASH_ByteLenPlus_OK = 0x5a5a5a5a,//byte length plus success + HASH_PadMsg_OK = 0x5a5a5a5a,//message padding success + HASH_ProcMsgBuf_OK = 0x5a5a5a5a, //message processing success + SM3_Hash_OK = 0x5a5a5a5a,//sm3 operation success + SHA256_Hash_OK = 0x5a5a5a5a,//sha256 operation success + SHA1_Hash_OK = 0,//sha1 operation success + SHA224_Hash_OK = 0,//sha224 operation success + SHA384_Hash_OK = 0,//sha384 operation success + SHA512_Hash_OK = 0,//sha512 operation success + HASH_Init_ERROR = 0x01044400,//hash init error + HASH_Start_ERROR, //hash start error + HASH_Update_ERROR, //hash update error + HASH_Complete_ERROR,//hash complete error + HASH_ByteLenPlus_ERROR,//hash byte plus error + HASH_ATTACK, //hash operation subject to attack +}; + + struct _HASH_CTX_; + +typedef struct +{ + const uint16_t HashAlgID;//choice hash algorithm + //const uint32_t * const K, KLen;//K and byte length of K + const uint32_t * const IV, IVLen;//IV and byte length of IV + const uint32_t HASH_ALGCR, HASH_SACCR, HASH_HASHCTRL;//relate registers + const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block + const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest + const uint32_t Cycle; //interation times + uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer + uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer +}HASH_ALG; + + +typedef struct _HASH_CTX_ +{ + const HASH_ALG *hashAlg; //pointer to HASH_ALG + uint32_t sequence; // TRUE if the IV should be saved + uint32_t IV[16]; + uint32_t msgByteLen[4]; + uint8_t msgBuf[132]; + uint32_t msgIdx; +}HASH_CTX; + + +extern const HASH_ALG HASH_ALG_SHA1[1]; +extern const HASH_ALG HASH_ALG_SHA224[1]; +extern const HASH_ALG HASH_ALG_SHA256[1]; +extern const HASH_ALG HASH_ALG_SHA384[1]; +extern const HASH_ALG HASH_ALG_SHA512[1]; + +/** + * @brief Hash init + * @param[in] ctx pointer to HASH_CTX struct + * @return HASH_Init_OK, Hash init success; othets: Hash init fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t HASH_Init(HASH_CTX *ctx); + +/** + * @brief Hash start + * @param[in] ctx pointer to HASH_CTX struct + * @return HASH_Start_OK, Hash start success; othets: Hash start fail + * @note 1.Please refer to the demo in user guidance before using this function + * 2.HASH_Init() should be recalled before use this function + */ +uint32_t HASH_Start(HASH_CTX *ctx); + +/** + * @brief Hash update + * @param[in] ctx pointer to HASH_CTX struct + * @param[in] in pointer to message + * @param[out] out pointer tohash result,digest + * @return HASH_Update_OK, Hash update success; othets: Hash update fail + * @note 1.Please refer to the demo in user guidance before using this function + * 2.HASH_Init() and HASH_Start() should be recalled before use this function + */ +uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen); + +/** + * @brief Hash complete + * @param[in] ctx pointer to HASH_CTX struct + * @param[out] out pointer tohash result,digest + * @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail + * @note 1.Please refer to the demo in user guidance before using this function + * 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function + */ +uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out); + +/** + * @brief Hash close + * @return HASH_Close_OK, Hash close success; othets: Hash close fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +void HASH_Close(void); + + + +/** + * @brief SHA1 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + +/** + * @brief SHA224 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + + +/** + * @brief SHA256 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + +/** + * @brief SHA384 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[in] out pointer tohash result,digest + * @return SHA384_Hash_OK, SHA384 hash success; othets: SHA384 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA384_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + +/** + * @brief SHA512 Hash + * @param[in] in pointer to message + * @param[in] byte length of in + * @param[out] out pointer tohash result,digest + * @return SHA512_Hash_OK, SHA512 hash success; othets: SHA512 hash fail + * @note 1.Please refer to the demo in user guidance before using this function + */ +uint32_t SHA512_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out); + + +/** + * @brief Get HASH lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get HASH lib information + */ +void HASH_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + + +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_RNG.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_RNG.h new file mode 100644 index 0000000000..e84dfaeace --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_RNG.h @@ -0,0 +1,112 @@ +/***************************************************************************** +* NationS Microcontroller Software Support +* ---------------------------------------------------------------------------- +* Copyright (c) 2025, NationS Corporation +* +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* NationS's name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ +/***************************************************************************** +* File Name: RNG.h +* Function: Defining RNG API +* author: nations +* version: V1.0 +* date: 2025-4-15 +* ****************************************************************************/ + + + + + +#include +#ifndef __RNG_H__ +#define __RNG_H__ + + +enum{ + + RNG_OK = 0x5a5a5a5a,//RNG generation process is ok + RNG_LENError = 0x311ECF50, //RNG generation of key length error + RNG_ADDRError = 0x63BB4C39, //This return value is not used + RNG_ADDRNULL = 0x7A9DB86C, // This address is empty + RNG_Attack = 0x4794674F, //The RNG generation process is attacked + RNG_ModeError=0x479467aa, //RNG choose mode is fail + RNG_TESTFAIL=0x479467bb, //RNG test is fail + RNG_SEEDNULL=0x479467cc, //RNG seed is NULL +}; + + +/** + * @brief Get true random number + * @param[out] rand pointer to random number + * @param[out] wordLen pointer to word length of rand + * @return RNG_OK:get random number success; othets: get random number fail + * @note + */ +uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen); + +/** + * @brief Get true random number + * @param[out] rand pointer to random number + * @param[out] wordLen pointer to word length of rand + * @return RNG_OK:get random number success; othets: get random number fail + * @note + */ +uint32_t GetTrueRand_U8(uint8_t *rand, uint32_t bytelen); + +/** + * @brief PseudoRandNumInit + * @param[in] seed of PseudoRandNum + * @return RNG_OK:PseudoRandNumInit success; othets: PseudoRandNumInit fail + * @note + */ +uint32_t PseudoRandNumInit(uint32_t seed[5]); + +/** + * @brief PseudoRandNumReseed + * @param[in] seed of PseudoRandNum + * @return RNG_OK:PseudoRandNumReseed success; othets: PseudoRandNumReseed fail + * @note + */ +uint32_t PseudoRandNumReseed(uint32_t seed[5]); +/** + * @brief Get pseudo random number + * @param[out] rand pointer to random number + * @param[out] rand pointer to random number + * @return RNG_OK:get random number success; othets: get random number fail + */ + +uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen); +/** + * @brief Get RNG lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get DES lib information + */ +void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + +#endif + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_SAC_Common.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_SAC_Common.h new file mode 100644 index 0000000000..567fc09af6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_SAC_Common.h @@ -0,0 +1,122 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_SAC_Common.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SAC_Common_H +#define __SAC_Common_H +#include +//#include "ns3610.h" + +/** + * @file SAC_Common.h + * @brief Declaring registers related to SAC module. + * @author Nations + * @version V0.1 + * @date 7th Dec, 2022 + */ + +#define SDPU_BASE (0x400F2000) +#define SDMA_BASE (SDPU_BASE)//(AHB2PERIPH_BASE + 0x2000):0x400F2000 +#define SAC_BASE (SDPU_BASE + 0x1000) +#define RNG_BASE (SDPU_BASE + 0x1080) +typedef struct +{ + volatile uint32_t SACCR ;//0 + volatile uint32_t SACSR;//4 + volatile uint32_t RESERVED0;//8 + volatile uint32_t SACSFR1;//C +}SAC_TypeDef; + +typedef struct +{ + volatile uint32_t SDMACR;//0 + volatile uint32_t SDMACH0SRCADDR;//4 + volatile uint32_t SDMACH1DSTADDR;//8 + volatile uint32_t RESERVED0;//C + volatile uint32_t RESERVED1;//10 + volatile uint32_t SDMACHCTRL;//14 + volatile uint32_t SDMAINTSTATUS;//18 + volatile uint32_t SDMAINTEN;//1C + volatile uint32_t SDMACRCVALUE0;//20 + volatile uint32_t SDMACRCVALUE1;//24 +}SDMA_TypeDef; + +typedef struct +{ + volatile uint32_t RNGCCTRL;//0 + volatile uint32_t RNGSTATE;//4 + volatile uint32_t RNGDATA1;//8 + volatile uint32_t RNGDRNGSEED;//c + volatile uint32_t RNGDRNGSEED1;//10 + volatile uint32_t RNGINTOUTEN;//14 + +}RNG_TypeDef; + +#define SAC ((SAC_TypeDef * ) SAC_BASE) +#define SDMA ((SDMA_TypeDef * ) SDMA_BASE) +#define RNG ((RNG_TypeDef * ) RNG_BASE) +#define REG32( addr ) (*(volatile uint32_t *)(addr)) +#define SACP1ADR REG32(SDPU_BASE + 0x1040) +#define SACP2ADR REG32(SDPU_BASE + 0x1044) +#define SACP3ADR REG32(SDPU_BASE + 0x1048) +#define SACKADR REG32(SDPU_BASE + 0x104C) +#define SACIADR REG32(SDPU_BASE + 0x1050) +#define SACOADR REG32(SDPU_BASE + 0x1054) +#define SACCNTADR REG32(SDPU_BASE + 0x1058) +#define RNGINTEN REG32((SDPU_BASE + 0x1094)) +#define SDPU_M7_EN REG32 (0x580300B0) +#define RNG_En REG32 (0x58030170) +#define AFEC_RNG REG32 (0x58000434) + + +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_SM4.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_SM4.h new file mode 100644 index 0000000000..e0817d6bd6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_SM4.h @@ -0,0 +1,108 @@ +/***************************************************************************** +* NationS Microcontroller Software Support +* ---------------------------------------------------------------------------- +* Copyright (c) 2025, NationS Corporation +* +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* NationS's name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ +/***************************************************************************** +* File Name: SM4.h +* Function: Defining RNG API +* author: nations +* version: V1.0 +* date: 2025-4-15 +* ****************************************************************************/ + +#ifndef _SM4_H_ +#define _SM4_H_ + +#include "n32h76x_78x_Common.h" + +#define SM4_ECB 0 +#define SM4_CBC 1 +#define SM4_ENCRYPT 0 +#define SM4_DECRYPT 1 + +enum SM4_ENUM +{ + + SM4_Init_OK = 0x5a5a5a5a, //SM4 opreation success + SM4_Crypto_OK=0x5a5a5a5a, //SM4 opreation success + SM4_ParaNull =0x27A90E35, //the address of input is NULL + SM4_ModeErr, //working mode error(Neither ECB nor CBC) + SM4_EnDeErr, // En&De error(Neither encryption nor decryption) + SM4_LengthErr,//the byte length of input error + SM4_ATTACKED, //SM4 subjected to attack +}; +typedef struct{ + uint8_t *in; // the part of input to be encrypted or decrypted + uint8_t *iv; // the part of initial vector + uint8_t *out; // the part of out + uint8_t *key; // the part of key + uint32_t inBytelen; //the word length of input or output + uint32_t En_De; //encrypt/decrypt + uint32_t Mode; // ECB/CBC +}SM4_PARM; +/** + * @brief SM4 Init + * @param[in] parm pointer to SM4 context and the detail please refer to struct SM4_PARM in SM4.h + * @return SM4_Init_OK, SM4 Init success; othets: SM4 Init fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2. IV can be NULL when ECB mode + * 3. The byte lengrh of message must be as times as 16. + */ + +uint32_t SM4_Init(SM4_PARM *parm); + +/** + * @brief SM4 crypto + * @param[in] parm pointer to SM4 context and the detail please refer to struct SM4_PARM in SM4.h + * @return SM4_Crypto_OK, SM4 crypto success; othets: SM4 crypto fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2. IV can be NULL when ECB mode + * 3. The byte lengrh of message must be as times as 16. + */ +uint32_t SM4_Crypto1(SM4_PARM *parm); +/** + * @brief Close SM4 algorithm + * @return none + * @note if you want to close SM4 algorithm, this function can be recalled. + */ +void SM4_Close(void); + + +/** + * @brief Get SM4 lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get SM4 lib information + */ +void SM4_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + + +#endif /*_SM4_H_*/ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_aes.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_aes.h new file mode 100644 index 0000000000..5310261083 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_algo_lib/inc/n32h76x_78x_aes.h @@ -0,0 +1,119 @@ +/***************************************************************************** +* NationS Microcontroller Software Support +* ---------------------------------------------------------------------------- +* Copyright (c) 2025, NationS Corporation +* +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* - Redistributions of source code must retain the above copyright notice, +* this list of conditions and the disclaimer below. +* +* NationS's name may not be used to endorse or promote products derived from +* this software without specific prior written permission. +* +* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* ****************************************************************************/ +/*****************************************************************************/ +/***************************************************************************** +* File Name: AES.h +* Function: Defining AES algorithm library API +* version: V1.0 +* Author: nations +* date: 2025-04-15 +* ****************************************************************************/ +#ifndef __AES_H +#define __AES_H +#include + +#define AES_ECB 0x11111111 +#define AES_CBC 0x22222222 +#define AES_CTR 0x33333333 +#define AES_ENCRYPT 0x44444444 +#define AES_DECRYPT 0x55555555 +#define AES_KEY_128 0x66666666 +#define AES_KEY_192 0x77777777 +#define AES_KEY_256 0x88888888 + + +enum{ + AES_Init_OK = 0x3a3a5a5a, //AES opreation success + AES_Crypto_OK=0x3a3aa5a5, //AES opreation success + AES_ModeErr= 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC,CTR) + AES_EnDeErr, // En&De error(Neither encryption nor decryption) + AES_ParaNull, // the part of input(output/iv) Null + AES_LengthErr,// + AES_KeyLengthError, + AES_ATTACKED, //AES subjected to attack +}; +typedef struct +{ + uint8_t *in; // the part of input to be encrypted or decrypted + uint8_t *iv; // the part of initial vector + uint8_t *out; // the part of out + uint8_t *key; // the part of key + uint32_t keyBytelen; // the length(by byte) of key + uint32_t inBytelen; // the length(by byte) of plaintext or cipher + uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt + uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC,0x33333333-AES_CTR +}AES_PARM; + +/** + * @brief AES Init + * @param[in] parm pointer to AES context and the detail please refer to struct DES_PARM in DES.h + * @return AES_Init_OK, AES Init success; othets: AES Init fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2. IV can be NULL when ECB mode + * 3. The byte lengrh of message must be as times as 16. + */ +uint32_t AES_Init(AES_PARM *parm); + +/** + * @brief AES crypto + * @param[in] parm pointer to DES context and the detail please refer to struct DES_PARM in SM1.h + * @return AES_Crypto_OK, DES crypto success; othets: AES crypto fail(reference to the definition by enum variation) + * @note 1.Please refer to the demo in user guidance before using this function + * 2. IV can be NULL when ECB mode + * 3. The byte lengrh of message must be as times as 16. + */ + +uint32_t AES_Crypto(AES_PARM *parm); + +/** + * @brief AES close + * @return none + * @note + */ +void AES_Close(void); + + + + /** + * @brief Get AES lib version + * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\ + * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version. + * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version... + * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 + * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2. + * @return none + * @1.You can recall this function to get AES lib information + */ +void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version); + + +#endif + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/mmc_host.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/mmc_host.h new file mode 100644 index 0000000000..0f7e076694 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/mmc_host.h @@ -0,0 +1,266 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file mmc_host.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __MMC_HOST_H__ +#define __MMC_HOST_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdmmc_spec.h" +#include "n32h76x_78x_sdmmc.h" + + + + +/* MMC card flags */ +enum +{ + MMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*mmc_card_information Support high speed 26MHZ */ + MMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*mmc_card_information Support high speed 52MHZ */ + MMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*mmc_card_information ddr 52MHZ 1.8V or 3.0V */ + MMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*mmc_card_information DDR 52MHZ 1.2V */ + MMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*mmc_card_information HS200 ,200MHZ,1.8V */ + MMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*mmc_card_information HS200, 200MHZ, 1.2V */ + MMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*mmc_card_information HS400, DDR, 200MHZ,1.8V */ + MMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*mmc_card_information HS400, DDR, 200MHZ,1.2V */ + MMC_SupportHighCapacityFlag = (1U << 8U), /*mmc_card_information Support high capacity */ + MMC_SupportAlternateBootFlag = (1U << 9U), /*mmc_card_information Support alternate boot */ + MMC_SupportDDRBootFlag = (1U << 10U), /*mmc_card_information support DDR boot flag*/ + MMC_SupportHighSpeedBootFlag = (1U << 11U), /*mmc_card_information support high speed boot flag */ + MMC_SupportEnhanceHS400StrobeFlag = (1U << 12U), /*mmc_card_information support enhance HS400 strobe */ +}; + +/* MMC card individual commands */ +typedef enum +{ + MMC_SendOperationCondition = 1U, /* Send Operation Condition */ + MMC_SetRelativeAddress = 3U, /* Set Relative Address */ + MMC_SleepAwake = 5U, /* Sleep Awake */ + MMC_Switch = 6U, /* Switch */ + MMC_SendExtendedCsd = 8U, /* Send EXT_CSD */ + MMC_ReadDataUntilStop = 11U, /* Read Data Until Stop */ + MMC_BusTestRead = 14U, /* Test Read */ + MMC_SendingBusTest = 19U, /* test bus width cmd*/ + MMC_WriteDataUntilStop = 20U, /* Write Data Until Stop */ + MMC_SendTuningBlock = 21U, /* MMC sending tuning block */ + MMC_ProgramCid = 26U, /* Program CID */ + MMC_EraseGroupStart = 35U, /* Erase Group Start */ + MMC_EraseGroupEnd = 36U, /* Erase Group End */ + MMC_FastInputOutput = 39U, /* Fast IO */ + MMC_GoInterruptState = 40U, /* Go interrupt State */ +} mmc_command_t; + +/* mmccard cmd13 retry times */ +#define MMC_CMD13_RETRY_TIMES (10) +/* mmccard access idle timeout value */ +#define MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT (10000U) + +/* Record information of mmccard */ +typedef struct +{ + uint32_t flags; /* mmccard Flags */ + uint32_t busy; /* busy status */ + uint32_t ocr; /* Raw OCR content,, only 24bit avalible for SDIO mmccard */ + mmc_cid cid; /* CID */ + uint32_t rca; /* Relative address of the mmccard */ + mmc_csd_t csd; /* CSD */ + uint32_t userPartitionBlocks; /* Card total block number in user partition */ + uint32_t bootPartitionBlocks; /* Boot partition size united as block size */ + uint32_t eraseGroupBlocks; /* Erase group size united as block size */ + uint32_t blockCount; /* Card total block number */ + uint32_t blockSize; /* mmccard block size */ + mmc_extended_csd_t extendedCsd; /* Extended CSD */ + uint32_t version; /* mmccard version */ +// sd_status_t stat; /* sd 512 bit status */ +}mmc_card_info; + + +/* mmccard bus width */ +typedef enum +{ + MMC_DataBusWidth1bit = 0U, /* MMC data bus width is 1 bit */ + MMC_DataBusWidth4bit = 1U, /* MMC data bus width is 4 bits */ + MMC_DataBusWidth8bit = 2U, /* MMC data bus width is 8 bits */ + MMC_DataBusWidth4bitDDR = 5U, /* MMC data bus width is 4 bits ddr */ + MMC_DataBusWidth8bitDDR = 6U, /* MMC data bus width is 8 bits ddr */ +}mmc_buswidth_t; + + + +/* The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_SHIFT (7U) +/* The bit mask for VOLTAGE WINDOW 1.70V to 1.95V field in OCR */ +#define MMC_OCR_V170TO195_MASK (0x00000080U) +/* The bit shift for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_SHIFT (8U) +/* The bit mask for VOLTAGE WINDOW 2.00V to 2.60V field in OCR */ +#define MMC_OCR_V200TO260_MASK (0x00007F00U) +/* The bit shift for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_SHIFT (15U) +/* The bit mask for VOLTAGE WINDOW 2.70V to 3.60V field in OCR */ +#define MMC_OCR_V270TO360_MASK (0x00FF8000U) +/* The bit shift for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_SHIFT (29U) +/* The bit mask for ACCESS MODE field in OCR */ +#define MMC_OCR_ACCESS_MODE_MASK (0x60000000U) +/* The bit shift for BUSY field in OCR */ +#define MMC_OCR_BUSY_SHIFT (31U) +/* The bit mask for BUSY field in OCR */ +#define MMC_OCR_BUSY_MASK (1U << MMC_OCR_BUSY_SHIFT) + +/* MMC card access mode(Access mode in OCR). */ +typedef enum +{ + MMC_AccessModeByte = 0U, /* The card should be accessed as byte */ + MMC_AccessModeSector = 2U, /* The card should be accessed as sector */ +} mmc_access_mode_t; + +/* mmccard operation voltage */ +typedef enum +{ + MMC_OperationVoltageNone = 0U, /* indicate current voltage setting is not setting by suser*/ + MMC_OperationVoltage120V = 1U, /* mmccard operation voltage is 1.2v */ + MMC_OperationVoltage170to195V = 2U, /* mmccard operation voltage is 1.7v to 1.95v */ + MMC_OperationVoltage270to360V = 0x1FFU, /* mmccard operation voltage is 2.7v to 3.6v */ +}mmc_operation_voltage_t; + +/* CSD structure version(CSD_STRUCTURE in CSD). */ +typedef enum _mmc_csd_structure_version +{ + MMC_CsdStrucureVersion10 = 0U, /* CSD version No. 1.0 */ + MMC_CsdStrucureVersion11 = 1U, /* CSD version No. 1.1 */ + MMC_CsdStrucureVersion12 = 2U, /* CSD version No. 1.2 */ + MMC_CsdStrucureVersionInExtcsd = 3U, /* Version coded in Extended CSD */ +} mmc_csd_structure_version_t; + +/* MMC card specification version(SPEC_VERS in CSD). */ +typedef enum _mmc_specification_version +{ + MMC_SpecificationVersion0 = 0U, /* Allocated by MMCA */ + MMC_SpecificationVersion1 = 1U, /* Allocated by MMCA */ + MMC_SpecificationVersion2 = 2U, /* Allocated by MMCA */ + MMC_SpecificationVersion3 = 3U, /* Allocated by MMCA */ + MMC_SpecificationVersion4 = 4U, /* Version 4.1/4.2/4.3/4.41-4.5-4.51-5.0 */ +} mmc_specification_version_t; + +/* MMC card high-speed timing(HS_TIMING in Extended CSD) */ +typedef enum +{ + MMC_HighSpeedTimingNone = 0U, /* MMC card using none high-speed timing */ + MMC_HighSpeedTiming = 1U, /* MMC card using high-speed timing */ + MMC_HighSpeed200Timing = 2U, /* MMC card high speed 200 timing*/ + MMC_NormalSpeedTiming = 3U, /* MMC card not using high-speed timing */ +} mmc_high_speed_timing_t; + +/* The divide value used to avoid float point calculation when calculate max speed in normal mode. */ +#define DIVIDER_IN_TRANSFER_SPEED (10U) +/* Frequency unit defined in TRANSFER SPEED field in CSD */ +static const uint32_t g_transerSpeedFrequencyUnit[] = {100000U, 1000000U, 10000000U, 100000000U}; +/* The multiplying value defined in TRANSFER SPEED field in CSD */ +static const uint32_t g_transerSpeedMultiplierFactor[] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, + 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; + +/* SD mmccard communication method and speed */ +typedef struct +{ + uint32_t busClock_Hz; /* SD bus clock frequency united in Hz */ + mmc_buswidth_t busWidth; /* set DATA bus width */ + mmc_high_speed_timing_t busTiming; /* work mode */ + sdmmc_dma_t dma; /* dma mode */ + mmc_operation_voltage_t operationVoltageflag; /* mmccard current operation voltage */ +}mmc_card_workmode; + +/* SD mmccard state + * Define the mmccard structure including the necessary fields to identify and describe the mmccard. + */ +typedef struct +{ + SDHOST_Module* SDHOSTx; /* Host device */ + SDMMC_Module* SDMMCx; /* SDMMC */ + SDMMC_CMD command; + mmc_card_info mmc_card_information; + mmc_card_workmode card_workmode; + SDHOST_TMODE_struct TMODE_truct; +} mmc_card_t; + +/* MMC card default relative address */ +#define MMC_DEFAULT_RELATIVE_ADDRESS (2UL) + +Status_card MMC_NormalCMD_Send(mmc_card_t* mmccard, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType); +Status_card MMC_AutoCMD_Send(mmc_card_t* mmccard, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType); + +void MMC_DecodeCid(mmc_card_t* mmccard); +void MMC_DecodeCsd(mmc_card_t* mmccard); +Status_card MMC_PollingCardStatusBusy(mmc_card_t* mmccard,uint32_t timeoutMs); +Status_card MMC_SendExtCsd(mmc_card_t* mmccard); +Status_card MMC_SetMaxEraseUnitSize(mmc_card_t* mmccard); +Status_card MMC_EraseGroups(mmc_card_t* mmccard, uint32_t startGroup, uint32_t endGroup); +Status_card MMC_ReadBlocks(mmc_card_t *mmccard, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount); +Status_card MMC_WriteBlocks(mmc_card_t *mmccard, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount); +Status_card MMC_SwitchVoltage(mmc_card_t *mmccard); +Status_card MMC_SelectBusTiming(mmc_card_t *mmccard); + +/* delay function */ +extern uint32_t MMC_systick_timeoutms; +uint32_t MMC_User_Time_Read(uint32_t time); +void MMC_SysTick_start_time(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MMC_HOST_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/sd_host.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/sd_host.h new file mode 100644 index 0000000000..67e80bf00e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/sd_host.h @@ -0,0 +1,180 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file sd_host.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SD_HOST_H__ +#define __SD_HOST_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdmmc_spec.h" +#include "n32h76x_78x_sdmmc.h" + + + +/* SDSPI individual commands */ +typedef enum +{ + kSDSPI_CommandCrc = 59U, /* Command crc protection on/off */ +} sdspi_command_t; + +/* SD card individual application commands */ +typedef enum +{ + SD_ApplicationSetBusWdith = 6U, /* Set Bus Width */ + SD_ApplicationStatus = 13U, /* Send SD status */ + SD_ApplicationSendNumberWriteBlocks = 22U, /* Send Number Of Written Blocks */ + SD_ApplicationSetWriteBlockEraseCount = 23U, /* Set Write Block Erase Count */ + SD_ApplicationSendOperationCondition = 41U, /* Send Operation Condition */ + SD_ApplicationSetClearCardDetect = 42U, /* Set Connnect/Disconnect pull up on detect pin */ + SD_ApplicationSendScr = 51U, /* Send Scr */ +} sd_application_command_t; + + + +/* card cmd13 retry times */ +#define SD_CMD13_RETRY_TIMES (10) +/* card access idle timeout value */ +#define SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT (600U) /* more then 500ms timeout value */ + + +/* Record information of card */ +typedef struct +{ + uint32_t flags; /* sd card Flags */ + uint32_t busy; /* busy status */ + uint32_t ocr; /* Raw OCR content,, only 24bit avalible for SDIO card */ + sd_cid cid; /* CID */ + uint32_t rca; /* Relative address of the card */ + sd_csd_t csd; /* CSD */ + uint32_t blockCount; /* Card total block number */ + uint32_t blockSize; /* Card block size */ + sd_scr_t scr; /* SCR */ + uint32_t version; /* Card version */ +// sd_status_t stat; /* sd 512 bit status */ +}sd_card_info; + + +/* card bus width */ +typedef enum +{ + SDMMC_BusWdith1Bit = 0U, /* card bus 1 width */ + SDMMC_BusWdith4Bit = 1U, /* card bus 4 width */ + SDMMC_BusWdith8Bit = 2U, /* card bus 8 width */ +}sd_buswidth_t; + + + + +/* card operation voltage */ +typedef enum +{ + SD_OperationVoltageNone = 0U, /* indicate current voltage setting is not setting by suser*/ + SD_OperationVoltage330V = 1U, /* card operation voltage around 3.3v */ + SD_OperationVoltage300V = 2U, /* card operation voltage around 3.0v */ + SD_OperationVoltage180V = 3U, /* card operation voltage around 1.8v */ +}sd_operation_voltage_t; + +/* SD card communication method and speed */ +typedef struct +{ + uint32_t busClock_Hz; /* SD bus clock frequency united in Hz */ + sd_buswidth_t busWidth; /* set DATA bus width */ + SD_ModeConfig mode; /* work mode */ + sdmmc_dma_t dma; /* dma mode */ + sd_operation_voltage_t operationVoltageflag; /* card current operation voltage */ +}sd_card_workmode; + +/* SD card state + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct +{ + SDHOST_Module* SDHOSTx; /* Host device */ + SDMMC_Module* SDMMCx; /* SDMMC */ + SDMMC_CMD command; + sd_card_info sd_card_information; + sd_card_workmode card_workmode; + SDHOST_TMODE_struct TMODE_truct; +} sd_card_t; + + +/* Default block size */ +#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) + +Status_card SD_NormalCMD_Send(sd_card_t* card, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType); +Status_card SD_AutoCMD_Send(sd_card_t* card, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType); + +void SD_DecodeCid(sd_card_t* card); +void SD_DecodeCsd(sd_card_t* card); +Status_card SD_PollingCardStatusBusy(sd_card_t* card,uint32_t timeoutMs); +Status_card SD_SendSCR(sd_card_t* card); +Status_card SD_Erase_Block(sd_card_t* card, uint32_t startBlock, uint32_t blockCount); +Status_card SD_ReadBlocks(sd_card_t *card, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount); +Status_card SD_WriteBlocks(sd_card_t *card, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount); +Status_card SD_SwitchVoltage(sd_card_t *card); +Status_card SD_SelectBusTiming(sd_card_t *card); + +/* delay function */ +extern uint32_t SD_systick_timeoutms; +uint32_t SD_User_Time_Read(uint32_t time); +void SD_SysTick_start_time(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SD_HOST_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/sdmmc_spec.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/sdmmc_spec.h new file mode 100644 index 0000000000..253c747d8a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/inc/sdmmc_spec.h @@ -0,0 +1,548 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file sdmmc_spec.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __SDMMC_SPEC_H__ +#define __SDMMC_SPEC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define swap_uint32( val) (((val << 24) & 0xff000000) | ((val << 8) & 0x00ff0000) | ((val >> 8) & 0x0000ff00) | ((val >> 24) & 0x000000ff)) +/* mask convert */ +#define SDMMC_MASK(bit) (1UL << (bit)) + +/* SD/mmccard status */ +typedef enum +{ + Status_Success = 1, /* Generic status for Success */ + Status_Fail, /* Generic status for Fail */ + Status_PollingCardIdleFailed, /* polling mmccard idle status failed */ + Status_CardStatusIdle, /* mmccard idle */ + Status_CardStatusBusy, /* mmccard busy */ + Status_CardOutOfRange, /* Out of range access. */ + Status_CardNotSupportYet, /* Haven't supported. */ + Status_CardSwitchFailed, /* Switch command failed */ +}Status_card; + +/* Card status bit in R1 */ +enum +{ + SDMMC_R1OutOfRangeFlag = 31, /* Out of range status bit */ + SDMMC_R1AddressErrorFlag = 30, /* Address error status bit */ + SDMMC_R1BlockLengthErrorFlag = 29, /* Block length error status bit */ + SDMMC_R1EraseSequenceErrorFlag = 28, /* Erase sequence error status bit */ + SDMMC_R1EraseParameterErrorFlag = 27, /* Erase parameter error status bit */ + SDMMC_R1WriteProtectViolationFlag = 26, /* Write protection violation status bit */ + SDMMC_R1CardIsLockedFlag = 25, /* Card locked status bit */ + SDMMC_R1LockUnlockFailedFlag = 24, /* lock/unlock error status bit */ + SDMMC_R1CommandCrcErrorFlag = 23, /* CRC error status bit */ + SDMMC_R1IllegalCommandFlag = 22, /* Illegal command status bit */ + SDMMC_R1CardEccFailedFlag = 21, /* Card ecc error status bit */ + SDMMC_R1CardControllerErrorFlag = 20, /* Internal card controller error status bit */ + SDMMC_R1ErrorFlag = 19, /* A general or an unknown error status bit */ + SDMMC_R1CidCsdOverwriteFlag = 16, /* Cid/csd overwrite status bit */ + SDMMC_R1WriteProtectEraseSkipFlag = 15, /* Write protection erase skip status bit */ + SDMMC_R1CardEccDisabledFlag = 14, /* Card ecc disabled status bit */ + SDMMC_R1EraseResetFlag = 13, /* Erase reset status bit */ + SDMMC_R1ReadyForDataFlag = 8, /* Ready for data status bit */ + SDMMC_R1SwitchErrorFlag = 7, /* Switch error status bit */ + SDMMC_R1ApplicationCommandFlag = 5, /* Application command enabled status bit */ + SDMMC_R1AuthenticationSequenceErrorFlag = 3, /* error in the sequence of authentication process */ +}; + +/* R1: current state */ +#define SDMMC_R1_CURRENT_STATE(x) (((x)&0x00001E00U) >> 9U) + +/* CURRENT_STATE filed in R1 */ +typedef enum +{ + SDMMC_R1StateIdle = 0U, /* R1: current state: idle */ + SDMMC_R1StateReady = 1U, /* R1: current state: ready */ + SDMMC_R1StateIdentify = 2U, /* R1: current state: identification */ + SDMMC_R1StateStandby = 3U, /* R1: current state: standby */ + SDMMC_R1StateTransfer = 4U, /* R1: current state: transfer */ + SDMMC_R1StateSendData = 5U, /* R1: current state: sending data */ + SDMMC_R1StateReceiveData = 6U, /* R1: current state: receiving data */ + SDMMC_R1StateProgram = 7U, /* R1: current state: programming */ + SDMMC_R1StateDisconnect = 8U, /* R1: current state: disconnect */ +} sdmmc_r1_current_state_t; + +/* MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ +enum +{ + MMC_ExtendedCsdRevision10 = 0U, /* Revision 1.0 */ + MMC_ExtendedCsdRevision11 = 1U, /* Revision 1.1 */ + MMC_ExtendedCsdRevision12 = 2U, /* Revision 1.2 */ + MMC_ExtendedCsdRevision13 = 3U, /* Revision 1.3 MMC4.3*/ + MMC_ExtendedCsdRevision14 = 4U, /* Revision 1.4 obsolete*/ + MMC_ExtendedCsdRevision15 = 5U, /* Revision 1.5 MMC4.41*/ + MMC_ExtendedCsdRevision16 = 6U, /* Revision 1.6 MMC4.5*/ + MMC_ExtendedCsdRevision17 = 7U, /* Revision 1.7 MMC5.0 */ +}; + +/* SD card product name length united as bytes. */ +#define SD_PRODUCT_NAME_BYTES (5U) +/* SD card CID register */ +typedef struct +{ + uint8_t manufacturerID; /* Manufacturer ID [127:120] */ + uint16_t applicationID; /* OEM/Application ID [119:104] */ + uint8_t productName[SD_PRODUCT_NAME_BYTES]; /* Product name [103:64] */ + uint8_t productVersion; /* Product revision [63:56] */ + uint32_t productSerialNumber; /* Product serial number [55:24] */ + uint16_t manufacturerData; /* Manufacturing date [19:8] */ +} sd_cid; + +/* MMC card product name length united as bytes. */ +#define MMC_PRODUCT_NAME_BYTES (6U) +/* MMC card CID register. */ +typedef struct +{ + uint8_t manufacturerID; /* Manufacturer ID */ + uint16_t applicationID; /* OEM/Application ID */ + uint8_t productName[MMC_PRODUCT_NAME_BYTES]; /* Product name */ + uint8_t productVersion; /* Product revision */ + uint32_t productSerialNumber; /* Product serial number */ + uint8_t manufacturerData; /* Manufacturing date */ +} mmc_cid; + +/* SD card CSD register flags */ +enum +{ + SD_CsdReadBlockPartialFlag = (1U << 0U), /* Partial blocks for read allowed [79:79] */ + SD_CsdWriteBlockMisalignFlag = (1U << 1U), /* Write block misalignment [78:78] */ + SD_CsdReadBlockMisalignFlag = (1U << 2U), /* Read block misalignment [77:77] */ + SD_CsdDsrImplementedFlag = (1U << 3U), /* DSR implemented [76:76] */ + SD_CsdEraseBlockEnabledFlag = (1U << 4U), /* Erase single block enabled [46:46] */ + SD_CsdWriteProtectGroupEnabledFlag = (1U << 5U), /* Write protect group enabled [31:31] */ + SD_CsdWriteBlockPartialFlag = (1U << 6U), /* Partial blocks for write allowed [21:21] */ + SD_CsdFileFormatGroupFlag = (1U << 7U), /* File format group [15:15] */ + SD_CsdCopyFlag = (1U << 8U), /* Copy flag [14:14] */ + SD_CsdPermanentWriteProtectFlag = (1U << 9U), /* Permanent write protection [13:13] */ + SD_CsdTemporaryWriteProtectFlag = (1U << 10U), /* Temporary write protection [12:12] */ +}; + +/* MMC card CSD register flags */ +enum +{ + MMC_CsdReadBlockPartialFlag = (1U << 0U), /* Partial blocks for read allowed */ + MMC_CsdWriteBlockMisalignFlag = (1U << 1U), /* Write block misalignment */ + MMC_CsdReadBlockMisalignFlag = (1U << 2U), /* Read block misalignment */ + MMC_CsdDsrImplementedFlag = (1U << 3U), /* DSR implemented */ + MMC_CsdWriteProtectGroupEnabledFlag = (1U << 4U), /* Write protect group enabled */ + MMC_CsdWriteBlockPartialFlag = (1U << 5U), /* Partial blocks for write allowed */ + MMC_ContentProtectApplicationFlag = (1U << 6U), /* Content protect application */ + MMC_CsdFileFormatGroupFlag = (1U << 7U), /* File format group */ + MMC_CsdCopyFlag = (1U << 8U), /* Copy flag */ + MMC_CsdPermanentWriteProtectFlag = (1U << 9U), /* Permanent write protection */ + MMC_CsdTemporaryWriteProtectFlag = (1U << 10U), /* Temporary write protection */ +}; + +/* SD/MMC mmccard common commands */ +typedef enum +{ + SDMMC_GoIdleState = 0U, /* Go Idle State */ + SDMMC_AllSendCid = 2U, /* All Send CID */ + SDMMC_SetDsr = 4U, /* Set DSR */ + SDMMC_SelectCard = 7U, /* Select mmccard */ + SDMMC_SendCsd = 9U, /* Send CSD */ + SDMMC_SendCid = 10U, /* Send CID */ + SDMMC_StopTransmission = 12U, /* Stop Transmission */ + SDMMC_SendStatus = 13U, /* Send Status */ + SDMMC_GoInactiveState = 15U, /* Go Inactive State */ + SDMMC_SetBlockLength = 16U, /* Set Block Length */ + SDMMC_ReadSingleBlock = 17U, /* Read Single Block */ + SDMMC_ReadMultipleBlock = 18U, /* Read Multiple Block */ + SDMMC_SetBlockCount = 23U, /* Set Block Count */ + SDMMC_WriteSingleBlock = 24U, /* Write Single Block */ + SDMMC_WriteMultipleBlock = 25U, /* Write Multiple Block */ + SDMMC_ProgramCsd = 27U, /* Program CSD */ + SDMMC_SetWriteProtect = 28U, /* Set Write Protect */ + SDMMC_ClearWriteProtect = 29U, /* Clear Write Protect */ + SDMMC_SendWriteProtect = 30U, /* Send Write Protect */ + SDMMC_Erase = 38U, /* Erase */ + SDMMC_LockUnlock = 42U, /* Lock Unlock */ + SDMMC_ApplicationCommand = 55U, /* Send Application Command */ + SDMMC_GeneralCommand = 56U, /* General Purpose Command */ + SDMMC_ReadOcr = 58U, /* Read OCR */ +} sdmmc_command_t; + +/* SD card CSD register */ +typedef struct +{ + uint8_t csdStructure; /* CSD structure [127:126] */ + uint8_t dataReadAccessTime1; /* Data read access-time-1 [119:112] */ + uint8_t dataReadAccessTime2; /* Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /* Maximum data transfer rate [103:96] */ + uint16_t cardCommandClass; /* Card command classes [95:84] */ + uint8_t readBlockLength; /* Maximum read data block length [83:80] */ + uint16_t flags; /* Flags in _sd_csd_flag */ + uint32_t deviceSize; /* Device size [73:62] */ + /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ + uint8_t readCurrentVddMin; /* Maximum read current at VDD min [61:59] */ + uint8_t readCurrentVddMax; /* Maximum read current at VDD max [58:56] */ + uint8_t writeCurrentVddMin; /* Maximum write current at VDD min [55:53] */ + uint8_t writeCurrentVddMax; /* Maximum write current at VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /* Device size multiplier [49:47] */ + + uint8_t eraseSectorSize; /* Erase sector size [45:39] */ + uint8_t writeProtectGroupSize; /* Write protect group size [38:32] */ + uint8_t writeSpeedFactor; /* Write speed factor [28:26] */ + uint8_t writeBlockLength; /* Maximum write data block length [25:22] */ + uint8_t fileFormat; /* File format [11:10] */ +} sd_csd_t; + +/* MMC card CSD register. */ +typedef struct _mmc_csd +{ + uint8_t csdStructureVersion; /* CSD structure [127:126] */ + uint8_t systemSpecificationVersion; /* System specification version [125:122] */ + uint8_t dataReadAccessTime1; /* Data read access-time 1 [119:112] */ + uint8_t dataReadAccessTime2; /* Data read access-time 2 in CLOCK cycles (NSAC*100) [111:104] */ + uint8_t transferSpeed; /* Max. bus clock frequency [103:96] */ + uint16_t cardCommandClass; /* card command classes [95:84] */ + uint8_t readBlockLength; /* Max. read data block length [83:80] */ + uint16_t flags; /* Contain flags in _mmc_csd_flag */ + uint16_t deviceSize; /* Device size [73:62] */ + uint8_t readCurrentVddMin; /* Max. read current @ VDD min [61:59] */ + uint8_t readCurrentVddMax; /* Max. read current @ VDD max [58:56] */ + uint8_t writeCurrentVddMin; /* Max. write current @ VDD min [55:53] */ + uint8_t writeCurrentVddMax; /* Max. write current @ VDD max [52:50] */ + uint8_t deviceSizeMultiplier; /* Device size multiplier [49:47] */ + uint8_t eraseGroupSize; /* Erase group size [46:42] */ + uint8_t eraseGroupSizeMultiplier; /* Erase group size multiplier [41:37] */ + uint8_t writeProtectGroupSize; /* Write protect group size [36:32] */ + uint8_t defaultEcc; /* Manufacturer default ECC [30:29] */ + uint8_t writeSpeedFactor; /* Write speed factor [28:26] */ + uint8_t maxWriteBlockLength; /* Max. write data block length [25:22] */ + uint8_t fileFormat; /* File format [11:10] */ + uint8_t eccCode; /* ECC code [9:8] */ +} mmc_csd_t; + +/* SD card SCR register flags */ +enum +{ + SD_ScrDataStatusAfterErase = (1U << 0U), /* Data status after erases [55:55] */ + SD_ScrSdSpecification3 = (1U << 1U), /* Specification version 3.00 or higher [47:47]*/ +}; + +/* SD card SCR register */ +typedef struct _sd_scr +{ + uint8_t scrStructure; /* SCR Structure [63:60] */ + uint8_t sdSpecification; /* SD memory card specification version [59:56] */ + uint16_t flags; /* SCR flags in _sd_scr_flag */ + uint8_t sdSecurity; /* Security specification supported [54:52] */ + uint8_t sdBusWidths; /* Data bus widths supported [51:48] */ + uint8_t commandSupport; /* Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ + uint32_t reservedForManufacturer; /* reserved for manufacturer usage [31:0] */ +} sd_scr_t; + + +/* MMC card Extended CSD register (unit: byte). */ +typedef struct _mmc_extended_csd +{ + /*uint8_t SecureRemoveType;*/ /* secure removal type[16]*/ + /*uint8_t enProductStateAware;*/ /* product state awareness enablement[17]*/ + /*uint32_t maxPreLoadDataSize;*/ /* max preload data size[21-18]*/ + /*uint32_t preLoadDataSize;*/ /* pre-load data size[25-22]*/ + /*uint8_t ffuStatus;*/ /* FFU status [26]*/ + /*uint8_t modeOperationCode;*/ /* mode operation code[29]*/ + /*uint8_t modeConfig;*/ /* mode config [30]*/ + uint8_t cacheCtrl; /* control to turn on/off cache[33]*/ + /*uint8_t pwroffNotify;*/ /* power off notification[34]*/ + /*uint8_t packedCmdFailIndex;*/ /* packed cmd fail index [35]*/ + /*uint8_t packedCmdStatus;*/ /* packed cmd status[36]*/ + /*uint32_t contextConfig[4U];*/ /* context configuration[51-37]*/ + /*uint16_t extPartitionAttr;*/ /* extended partitions attribut[53-52]*/ + /*uint16_t exceptEventStatus;*/ /* exception events status[55-54]*/ + /*uint16_t exceptEventControl;*/ /* exception events control[57-56]*/ + /*uint8_t toReleaseAddressedGroup;*/ /* number of group to be released[58]*/ + /*uint8_t class6CmdCtrl;*/ /* class 6 command control[59]*/ + /*uint8_t intTimeoutEmu;*/ /* 1st initiallization after disabling sector size emu[60]*/ + /*uint8_t sectorSize;*/ /* sector size[61] */ + /*uint8_t sectorSizeEmu;*/ /* sector size emulation[62]*/ + /*uint8_t nativeSectorSize;*/ /* native sector size[63]*/ + /*uint8_t periodWakeup;*/ /* period wakeup [131]*/ + /*uint8_t tCASESupport;*/ /* package case temperature is controlled[132]*/ + /*uint8_t productionStateAware;*/ /* production state awareness[133]*/ + /*uint32_t enhanceUsrDataStartAddr;*/ /* enhanced user data start addr [139-136]*/ + /*uint32_t enhanceUsrDataSize;*/ /* enhanced user data area size[142-140]*/ + /*uint32_t generalPartitionSize[3];*/ /* general purpose partition size[154-143]*/ + uint8_t partitionAttribute; /* partition attribute [156]*/ + /*uint32_t maxEnhanceAreaSize;*/ /* max enhance area size [159-157]*/ + /*uint8_t hpiManagementEn;*/ /* HPI management [161]*/ + /*uint8_t writeReliabilityParameter;*/ /* write reliability parameter register[166] */ + /*uint8_t writeReliabilitySet;*/ /* write reliability setting register[167] */ + /*uint8_t rpmbSizeMult;*/ /* RPMB size multi [168]*/ + /*uint8_t fwConfig;*/ /* FW configuration[169]*/ + uint8_t userWP; /* user write protect register[171] */ + uint8_t bootPartitionWP; /* boot write protect register[173]*/ + uint8_t bootWPStatus; /* boot write protect status register[174]*/ + uint8_t highDensityEraseGroupDefinition; /* High-density erase group definition [175] */ + uint8_t bootDataBusConditions; /* Boot bus conditions [177] */ + uint8_t bootConfigProtect; /* Boot config protection [178]*/ + uint8_t partitionConfig; /* Boot configuration [179] */ + uint8_t eraseMemoryContent; /* Erased memory content [181] */ + uint8_t dataBusWidth; /* Data bus width mode [183] */ + uint8_t highSpeedTiming; /* High-speed interface timing [185] */ + uint8_t powerClass; /* Power class [187] */ + uint8_t commandSetRevision; /* Command set revision [189] */ + uint8_t commandSet; /* Command set [191] */ + uint8_t extendecCsdVersion; /* Extended CSD revision [192] */ + uint8_t csdStructureVersion; /* CSD structure version [194] */ + uint8_t cardType; /* Card Type [196] */ + uint8_t ioDriverStrength; /* IO driver strength [197] */ + /*uint8_t OutofInterruptBusyTiming;*/ /* out of interrupt busy timing [198] */ + uint8_t partitionSwitchTimeout; /* partition switch timing [199] */ + uint8_t powerClass52MHz195V; /* Power Class for 52MHz @ 1.95V [200] */ + uint8_t powerClass26MHz195V; /* Power Class for 26MHz @ 1.95V [201] */ + uint8_t powerClass52MHz360V; /* Power Class for 52MHz @ 3.6V [202] */ + uint8_t powerClass26MHz360V; /* Power Class for 26MHz @ 3.6V [203] */ + uint8_t minimumReadPerformance4Bit26MHz; /* Minimum Read Performance for 4bit at 26MHz [205] */ + uint8_t minimumWritePerformance4Bit26MHz; /* Minimum Write Performance for 4bit at 26MHz [206] */ + uint8_t minimumReadPerformance8Bit26MHz4Bit52MHz; + /* Minimum read Performance for 8bit at 26MHz/4bit @52MHz [207] */ + uint8_t minimumWritePerformance8Bit26MHz4Bit52MHz; + /* Minimum Write Performance for 8bit at 26MHz/4bit @52MHz [208] */ + uint8_t minimumReadPerformance8Bit52MHz; /* Minimum Read Performance for 8bit at 52MHz [209] */ + uint8_t minimumWritePerformance8Bit52MHz; /* Minimum Write Performance for 8bit at 52MHz [210] */ + uint32_t sectorCount; /* Sector Count [215:212] */ + /*uint8_t sleepNotificationTimeout;*/ /* sleep notification timeout [216]*/ + uint8_t sleepAwakeTimeout; /* Sleep/awake timeout [217] */ + /*uint8_t productionStateAwareTimeout;*/ /* Production state awareness timeout [218]*/ + uint8_t sleepCurrentVCCQ; /* Sleep current (VCCQ) [219] */ + uint8_t sleepCurrentVCC; /* Sleep current (VCC) [220] */ + uint8_t highCapacityWriteProtectGroupSize; /* High-capacity write protect group size [221] */ + uint8_t reliableWriteSectorCount; /* Reliable write sector count [222] */ + uint8_t highCapacityEraseTimeout; /* High-capacity erase timeout [223] */ + uint8_t highCapacityEraseUnitSize; /* High-capacity erase unit size [224] */ + uint8_t accessSize; /* Access size [225] */ + /*uint8_t secureTrimMultiplier;*/ /* secure trim multiplier[229]*/ + /*uint8_t secureEraseMultiplier;*/ /* secure erase multiplier[230]*/ + /*uint8_t secureFeatureSupport;*/ /* secure feature support[231]*/ + /*uint32_t trimMultiplier;*/ /* trim multiplier[232]*/ + uint8_t minReadPerformance8bitAt52MHZDDR; /* Minimum read performance for 8bit at DDR 52MHZ[234]*/ + uint8_t minWritePerformance8bitAt52MHZDDR; /* Minimum write performance for 8bit at DDR 52MHZ[235]*/ + uint8_t powerClass200MHZVCCQ130VVCC360V; /* power class for 200MHZ, at VCCQ= 1.3V,VCC=3.6V[236]*/ + uint8_t powerClass200MHZVCCQ195VVCC360V; /* power class for 200MHZ, at VCCQ= 1.95V,VCC=3.6V[237]*/ + uint8_t powerClass52MHZDDR195V; /* power class for 52MHZ,DDR at Vcc 1.95V[238]*/ + uint8_t powerClass52MHZDDR360V; /* power class for 52MHZ,DDR at Vcc 3.6V[239]*/ + /*uint8_t iniTimeoutAP;*/ /* 1st initialization time after partitioning[241]*/ + /*uint32_t correctPrgSectorNum;*/ /* correct prg sectors number[245-242]*/ + /*uint8_t bkOpsStatus;*/ /* background operations status[246]*/ + /*uint8_t powerOffNotifyTimeout;*/ /* power off notification timeout[247]*/ + uint32_t genericCMD6Timeout; /* generic CMD6 timeout[248]*/ + uint32_t cacheSize; /* cache size[252-249]*/ + uint8_t powerClass200MHZDDR360V; /* power class for 200MHZ, DDR at VCC=2.6V[253]*/ + /*uint32_t fwVer[2U];*/ /* fw VERSION [261-254]*/ + /*uint16_t deviceVer;*/ /* device version[263-262]*/ + /*uint8_t optimalTrimSize;*/ /* optimal trim size[264]*/ + /*uint8_t optimalWriteSize;*/ /* optimal write size[265]*/ + /*uint8_t optimalReadSize;*/ /* optimal read size[266]*/ + /*uint8_t preEolInfo;*/ /* pre EOL information[267]*/ + /*uint8_t deviceLifeTimeEstimationA;*/ /* device life time estimation typeA[268]*/ + /*uint8_t deviceLifeTimeEstimationB;*/ /* device life time estimation typeB[269]*/ + /*uint32_t correctPrgFWSectorNum;*/ /* number of FW sectors correctly programmed[305-302]*/ + /*uint32_t ffuArg;*/ /* FFU argument[490-487]*/ + /*uint8_t operationCodeTimeout;*/ /* operation code timeout[491]*/ + /*uint8_t supportMode;*/ /* support mode [493]*/ + uint8_t extPartitionSupport; /* extended partition attribute support[494]*/ + /*uint8_t largeUnitSize;*/ /* large unit size[495]*/ + /*uint8_t contextManageCap;*/ /* context management capability[496]*/ + /*uint8_t tagResourceSize;*/ /* tag resource size[497]*/ + /*uint8_t tagUnitSize;*/ /* tag unit size[498]*/ + /*uint8_t maxPackedWriteCmd;*/ /* max packed write cmd[500]*/ + /*uint8_t maxPackedReadCmd;*/ /* max packed read cmd[501]*/ + /*uint8_t hpiFeature;*/ /* HPI feature[503]*/ + uint8_t supportedCommandSet; /* Supported Command Sets [504] */ + /*uint8_t extSecurityCmdError;*/ /* extended security commands error[505]*/ +} mmc_extended_csd_t; + + +/* MMC card command set(COMMAND_SET in Extended CSD) */ +typedef enum +{ + MMC_CommandSetStandard = 0U, /*MMC Standard MMC */ + MMC_CommandSet1 = 1U, /*MMC Command set 1 */ + MMC_CommandSet2 = 2U, /*MMC Command set 2 */ + MMC_CommandSet3 = 3U, /*MMC Command set 3 */ + MMC_CommandSet4 = 4U, /*MMC Command set 4 */ +} mmc_command_set_t; + +/* Extended CSD register access mode(Access mode in CMD6). */ +typedef enum +{ + MMC_ExtendedCsdAccessModeCommandSet = 0U, /* MMC Command set related setting */ + MMC_ExtendedCsdAccessModeSetBits = 1U, /* MMC Set bits in specific byte in Extended CSD */ + MMC_ExtendedCsdAccessModeClearBits = 2U, /* MMC Clear bits in specific byte in Extended CSD */ + MMC_ExtendedCsdAccessModeWriteBits = 3U, /* MMC Write a value to specific byte in Extended CSD */ +} mmc_extended_csd_access_mode_t; + +/* EXT CSD byte index */ +typedef enum +{ + MMC_ExtendedCsdIndexFlushCache = 32U, /* flush cache */ + MMC_ExtendedCsdIndexCacheControl = 33U, /* cache control */ + MMC_ExtendedCsdIndexBootPartitionWP = 173U, /* Boot partition write protect */ + MMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /* Erase Group Def */ + MMC_ExtendedCsdIndexBootBusConditions = 177U, /* Boot Bus conditions */ + MMC_ExtendedCsdIndexBootConfigWP = 178U, /* Boot config write protect */ + MMC_ExtendedCsdIndexPartitionConfig = 179U, /* Partition Config, before BOOT_CONFIG */ + MMC_ExtendedCsdIndexBusWidth = 183U, /* Bus Width */ + MMC_ExtendedCsdIndexHighSpeedTiming = 185U, /* High-speed Timing */ + MMC_ExtendedCsdIndexPowerClass = 187U, /* Power Class */ + MMC_ExtendedCsdIndexCommandSet = 191U, /* Command Set */ +} mmc_extended_csd_index_t; + +/* mmc driver strength */ +enum +{ + MMC_DriverStrength0 = 0U, /* Driver type0 ,nominal impedance 50ohm */ + MMC_DriverStrength1 = 1U, /* Driver type1 ,nominal impedance 33ohm */ + MMC_DriverStrength2 = 2U, /* Driver type2 ,nominal impedance 66ohm */ + MMC_DriverStrength3 = 3U, /* Driver type3 ,nominal impedance 100ohm */ + MMC_DriverStrength4 = 4U, /* Driver type4 ,nominal impedance 40ohm */ +}; + +/* The bit shift for COMMAND SET field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_SHIFT (0U) +/* The bit mask for COMMAND set field in SWITCH command. */ +#define MMC_SWITCH_COMMAND_SET_MASK (0x00000007U) +/* The bit shift for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_SHIFT (8U) +/* The bit mask for VALUE field in SWITCH command */ +#define MMC_SWITCH_VALUE_MASK (0x0000FF00U) +/* The bit shift for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_SHIFT (16U) +/* The bit mask for BYTE INDEX field in SWITCH command */ +#define MMC_SWITCH_BYTE_INDEX_MASK (0x00FF0000U) +/* The bit shift for ACCESS MODE field in SWITCH command */ +#define MMC_SWITCH_ACCESS_MODE_SHIFT (24U) +/* The bit mask for ACCESS MODE field in SWITCH command */ +#define MMC_SWTICH_ACCESS_MODE_MASK (0x03000000U) + +/* Default block size */ +#define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) + +/* MMC Extended CSD configuration. */ +typedef struct +{ + mmc_command_set_t commandSet; /* MMC Command set */ + uint8_t ByteValue; /* MMC The value to set */ + uint8_t ByteIndex; /* MMC The byte index in Extended CSD(mmc_extended_csd_index_t) */ + mmc_extended_csd_access_mode_t accessMode; /* MMC Access mode */ +} mmc_extended_csd_config_t; + +/* SD card command class */ +enum +{ + SD_CommandClassBasic = (1U << 0U), /* Card command class 0 */ + SD_CommandClassBlockRead = (1U << 2U), /* Card command class 2 */ + SD_CommandClassBlockWrite = (1U << 4U), /* Card command class 4 */ + SD_CommandClassErase = (1U << 5U), /* Card command class 5 */ + SD_CommandClassWriteProtect = (1U << 6U), /* Card command class 6 */ + SD_CommandClassLockCard = (1U << 7U), /* Card command class 7 */ + SD_CommandClassApplicationSpecific = (1U << 8U), /* Card command class 8 */ + SD_CommandClassInputOutputMode = (1U << 9U), /* Card command class 9 */ + SD_CommandClassSwitch = (1U << 10U), /* Card command class 10 */ +}; + +/* SD card specification version number */ +enum +{ + SD_SpecificationVersion1_0 = (1U << 0U), /* SD card version 1.0-1.01 */ + SD_SpecificationVersion1_1 = (1U << 1U), /* SD card version 1.10 */ + SD_SpecificationVersion2_0 = (1U << 2U), /* SD card version 2.00 */ + SD_SpecificationVersion3_0 = (1U << 3U), /* SD card version 3.0 */ +}; +/* dma mode */ +typedef enum +{ + SDMMC_NODMA = 0U, /* no use dma */ + SDMMC_SDMA = 1U, /* use sdma */ + SDMMC_ADMA = 2U, /* use adma */ +}sdmmc_dma_t; +/* SD card flags */ +enum +{ + SD_SupportHighCapacityFlag = (1U << 1U), /* Support high capacity */ + SD_Support4BitWidthFlag = (1U << 2U), /* Support 4-bit data width */ + SD_SupportSdhcFlag = (1U << 3U), /* Card is SDHC */ + SD_SupportSdxcFlag = (1U << 4U), /* Card is SDXC */ + SD_SupportVoltage180v = (1U << 5U), /* card support 1.8v voltage*/ + SD_SupportSetBlockCountCmd = (1U << 6U), /* card support cmd23 flag*/ + SD_SupportSpeedClassControlCmd = (1U << 7U), /* card support speed class control flag */ +}; +/* SD card individual commands */ +typedef enum +{ + SD_SendRelativeAddress = 3U, /* Send Relative Address */ + SD_Switch = 6U, /* Switch Function */ + SD_SendInterfaceCondition = 8U, /* Send Interface Condition */ + SD_VoltageSwitch = 11U, /* Voltage Switch */ + SD_SpeedClassControl = 20U, /* Speed Class control */ + SD_EraseWriteBlockStart = 32U, /* Write Block Start */ + SD_EraseWriteBlockEnd = 33U, /* Write Block End */ + SD_SendTuningBlock = 19U, /* Send Tuning Block */ +} sd_command_t; +#ifdef __cplusplus +} +#endif + +#endif /* __SDMMC_SPEC_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/src/mmc_host.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/src/mmc_host.c new file mode 100644 index 0000000000..ed49429a04 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/src/mmc_host.c @@ -0,0 +1,1272 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file mmc_host.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "mmc_host.h" + +static Status_card MMC_SendCardStatus(mmc_card_t* mmccard); +static void MMC_configSDMABufferSize(mmc_card_t *mmccard, uint32_t *buffer, uint32_t blockCount); +//static Status_card SD_SwitchFunction(mmc_card_t *mmccard,uint32_t mode); +static Status_card MMC_SetExtendedCsdConfig(mmc_card_t *mmccard, const mmc_extended_csd_config_t *config, uint32_t timeout); + +/* mmccard block erase time, varies according to different cards */ +#define MMC_BLOCKERASE_TIME (250U) + +uint32_t MMC_systick_timeoutms = 0; + +Status_card MMC_NormalCMD_Send(mmc_card_t* mmccard, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType) +{ + Status_card status_temp; + + mmccard->command.index = index; + mmccard->command.argument = argument; + mmccard->command.type = CARD_CommandTypeNormal; + mmccard->command.responseType = responseType; + mmccard->command.flags = 0x00; + mmccard->command.responseErrorFlags = 0x00; + SDMMC_SendCommand(mmccard->SDHOSTx,&mmccard->command,&mmccard->TMODE_truct); + if(SDMMC_WaitCommandDone(mmccard->SDHOSTx,&mmccard->command,ENABLE) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + else + { + status_temp = Status_Success; + } + return status_temp; +} + + +Status_card MMC_AutoCMD_Send(mmc_card_t* mmccard, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType) +{ + Status_card status_temp = Status_Success; + + /* CMD55 */ + mmccard->command.index = SDMMC_ApplicationCommand; + mmccard->command.argument = mmccard->mmc_card_information.rca << 16; + mmccard->command.type = CARD_CommandTypeNormal; + mmccard->command.responseType = CARD_ResponseTypeR1; + mmccard->command.flags = 0x00; + mmccard->command.responseErrorFlags = 0x00; + SDMMC_SendCommand(mmccard->SDHOSTx,&mmccard->command,&mmccard->TMODE_truct); + if(SDMMC_WaitCommandDone(mmccard->SDHOSTx,&mmccard->command,ENABLE) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + mmccard->command.index = index; + mmccard->command.argument = argument; + mmccard->command.type = CARD_CommandTypeNormal; + mmccard->command.responseType = responseType; + mmccard->command.flags = 0x00; + mmccard->command.responseErrorFlags = 0x00; + SDMMC_SendCommand(mmccard->SDHOSTx,&mmccard->command,&mmccard->TMODE_truct); + if(SDMMC_WaitCommandDone(mmccard->SDHOSTx,&mmccard->command,ENABLE) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + return status_temp; +} + + +void MMC_DecodeCid(mmc_card_t* mmccard) +{ + /* get cid */ + mmccard->mmc_card_information.cid.manufacturerID = (uint8_t)((mmccard->command.response[3U] & 0xFF000000U) >> 24U); + mmccard->mmc_card_information.cid.applicationID = (uint16_t)((mmccard->command.response[3U] & 0xFFFF00U) >> 8U); + + mmccard->mmc_card_information.cid.productName[0U] = (uint8_t)((mmccard->command.response[3U] & 0xFFU)); + mmccard->mmc_card_information.cid.productName[1U] = (uint8_t)((mmccard->command.response[2U] & 0xFF000000U) >> 24U); + mmccard->mmc_card_information.cid.productName[2U] = (uint8_t)((mmccard->command.response[2U] & 0xFF0000U) >> 16U); + mmccard->mmc_card_information.cid.productName[3U] = (uint8_t)((mmccard->command.response[2U] & 0xFF00U) >> 8U); + mmccard->mmc_card_information.cid.productName[4U] = (uint8_t)((mmccard->command.response[2U] & 0xFFU)); + mmccard->mmc_card_information.cid.productName[5U] = (uint8_t)((mmccard->command.response[1U] & 0xFF000000U) >> 24U); + + mmccard->mmc_card_information.cid.productVersion = (uint8_t)((mmccard->command.response[1U] & 0xFF000000U) >> 16U); + + mmccard->mmc_card_information.cid.productSerialNumber = (uint32_t)((mmccard->command.response[1U] & 0xFFFFU) << 16U); + mmccard->mmc_card_information.cid.productSerialNumber |= (uint32_t)((mmccard->command.response[0U] & 0xFFFF0000U) >> 16U); + + mmccard->mmc_card_information.cid.manufacturerData = (uint16_t)((mmccard->command.response[0U] & 0xFFF00U) >> 8U); +} + + +void MMC_DecodeCsd(mmc_card_t* mmccard) +{ + uint32_t multiplier; + + mmccard->mmc_card_information.csd.csdStructureVersion = (uint8_t)((mmccard->command.response[3U] & 0xC0000000U) >> 30U); + mmccard->mmc_card_information.csd.systemSpecificationVersion = (uint8_t)((mmccard->command.response[3U] & 0x3C0000000U) >> 26U); + mmccard->mmc_card_information.csd.dataReadAccessTime1 = (uint8_t)((mmccard->command.response[3U] & 0xFF0000U) >> 16U); + mmccard->mmc_card_information.csd.dataReadAccessTime2 = (uint8_t)((mmccard->command.response[3U] & 0xFF00U) >> 8U); + mmccard->mmc_card_information.csd.transferSpeed = (uint8_t)(mmccard->command.response[3U] & 0xFFU); + mmccard->mmc_card_information.csd.cardCommandClass = (uint16_t)((mmccard->command.response[2U] & 0xFFF00000U) >> 20U); + mmccard->mmc_card_information.csd.readBlockLength = (uint8_t)((mmccard->command.response[2U] & 0xF0000U) >> 16U); + if ((mmccard->command.response[2U] & 0x8000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdReadBlockPartialFlag; + } + if ((mmccard->command.response[2U] & 0x4000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdWriteBlockMisalignFlag; + } + if ((mmccard->command.response[2U] & 0x2000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdReadBlockMisalignFlag; + } + if ((mmccard->command.response[2U] & 0x1000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdDsrImplementedFlag; + } + + mmccard->mmc_card_information.csd.deviceSize = (uint16_t)(((mmccard->command.response[2U] & 0x3FFU) << 2U) + ((mmccard->command.response[1U] & 0xC0000000U) >> 30U)); + mmccard->mmc_card_information.csd.readCurrentVddMin = (uint8_t)((mmccard->command.response[1U] & 0x38000000U) >> 27U); + mmccard->mmc_card_information.csd.readCurrentVddMax = (uint8_t)((mmccard->command.response[1U] & 0x07000000U) >> 24U); + mmccard->mmc_card_information.csd.writeCurrentVddMin = (uint8_t)((mmccard->command.response[1U] & 0x00E00000U) >> 21U); + mmccard->mmc_card_information.csd.writeCurrentVddMax = (uint8_t)((mmccard->command.response[1U] & 0x001C0000U) >> 18U); + mmccard->mmc_card_information.csd.deviceSizeMultiplier = (uint8_t)((mmccard->command.response[1U] & 0x00038000U) >> 15U); + mmccard->mmc_card_information.csd.eraseGroupSize = (uint8_t)((mmccard->command.response[1U] & 0x00007C00U) >> 10U); + mmccard->mmc_card_information.csd.eraseGroupSizeMultiplier = (uint8_t)((mmccard->command.response[1U] & 0x000003E0U) >> 5U); + mmccard->mmc_card_information.csd.writeProtectGroupSize = (uint8_t)(mmccard->command.response[1U] & 0x0000001FU); + if ((mmccard->command.response[0U] & 0x80000000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdWriteProtectGroupEnabledFlag; + } + mmccard->mmc_card_information.csd.defaultEcc = (uint8_t)((mmccard->command.response[0U] & 0x60000000U) >> 29U); + mmccard->mmc_card_information.csd.writeSpeedFactor = (uint8_t)((mmccard->command.response[0U] & 0x1C000000U) >> 26U); + mmccard->mmc_card_information.csd.maxWriteBlockLength = (uint8_t)((mmccard->command.response[0U] & 0x03C00000U) >> 22U); + if ((mmccard->command.response[0U] & 0x00200000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdWriteBlockPartialFlag; + } + if ((mmccard->command.response[0U] & 0x00010000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_ContentProtectApplicationFlag; + } + if ((mmccard->command.response[0U] & 0x00008000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdFileFormatGroupFlag; + } + if ((mmccard->command.response[0U] & 0x00004000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdCopyFlag; + } + if ((mmccard->command.response[0U] & 0x00002000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdPermanentWriteProtectFlag; + } + if ((mmccard->command.response[0U] & 0x00001000U) != 0U) + { + mmccard->mmc_card_information.csd.flags |= (uint16_t)MMC_CsdTemporaryWriteProtectFlag; + } + mmccard->mmc_card_information.csd.fileFormat = (uint8_t)((mmccard->command.response[0U] & 0x00000C00U) >> 10U); + mmccard->mmc_card_information.csd.eccCode = (uint8_t)((mmccard->command.response[0U] & 0x00000300U) >> 8U); + + /* Calculate the device total block count. */ + /* For the card capacity of witch higher than 2GB, the maximum possible value should be set to this register + is 0xFFF. */ + if (mmccard->mmc_card_information.csd.deviceSize != 0xFFFU) + { + multiplier = (2UL << (mmccard->mmc_card_information.csd.deviceSizeMultiplier + 2U - 1U)); + mmccard->mmc_card_information.userPartitionBlocks = (((mmccard->mmc_card_information.csd.deviceSize + 1UL) * multiplier) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + + mmccard->mmc_card_information.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; +} + +static Status_card MMC_SendCardStatus(mmc_card_t* mmccard) +{ + Status_card status_temp; + uint32_t retry = MMC_CMD13_RETRY_TIMES; + while(retry != 0U) + { + /* CMD13 */ + if(MMC_NormalCMD_Send(mmccard,SDMMC_SendStatus,mmccard->mmc_card_information.rca << 16,CARD_ResponseTypeR1) != Status_Success) + { + if(SDMMC_GetPresentFlagStatus(mmccard->SDHOSTx,SDHOST_CommandInhibitFlag)) + { + SDMMC_SoftWareReset(mmccard->SDHOSTx,SDHOST_SOFTWARE_CMDLINE); + } + status_temp = Status_Fail; + retry--; + } + else + { + if(((mmccard->command.response[0] & SDMMC_MASK(SDMMC_R1ReadyForDataFlag)) != 0U) && + (SDMMC_R1_CURRENT_STATE(mmccard->command.response[0U]) != (uint32_t)SDMMC_R1StateProgram)) + { + status_temp = Status_CardStatusIdle; + } + else + { + status_temp = Status_CardStatusBusy; + } + break; + } + } + return status_temp; +} + +Status_card MMC_PollingCardStatusBusy(mmc_card_t* mmccard,uint32_t timeoutMs) +{ + uint32_t timeout_temp; + uint32_t timeout_cnt = 0; + bool cardBusy = false; + Status_card status_temp = Status_CardStatusBusy; + + MMC_SysTick_start_time(); + timeout_temp = MMC_systick_timeoutms; + while(timeout_cnt < timeoutMs) + { + if(SDMMC_GetPresentFlagStatus(mmccard->SDHOSTx,SDHOST_Data0LineLevelFlag) == SET) + { + cardBusy = false; + } + else + { + cardBusy = true; + } + + if (cardBusy == false) + { + status_temp = MMC_SendCardStatus(mmccard); + if (status_temp == Status_CardStatusIdle) + { + break; + } + } + + timeout_cnt = MMC_User_Time_Read(timeout_temp); + } + + if(SDMMC_GetFlagStatus(mmccard->SDHOSTx,SDHOST_DataCompleteFlag) == SET) + { + SDMMC_ClrFlag(mmccard->SDHOSTx,SDHOST_DataCompleteFlag); + } + + return status_temp; +} + +static Status_card MMC_SetExtendedCsdConfig(mmc_card_t *mmccard, const mmc_extended_csd_config_t *config, uint32_t timeout) +{ + Status_card status_temp; + uint32_t parameter = 0U; + uint32_t timeoutMS = timeout == 0U ? mmccard->mmc_card_information.extendedCsd.genericCMD6Timeout : timeout; + + parameter |= ((uint32_t)(config->commandSet) << MMC_SWITCH_COMMAND_SET_SHIFT); + parameter |= ((uint32_t)(config->ByteValue) << MMC_SWITCH_VALUE_SHIFT); + parameter |= ((uint32_t)(config->ByteIndex) << MMC_SWITCH_BYTE_INDEX_SHIFT); + parameter |= ((uint32_t)(config->accessMode) << MMC_SWITCH_ACCESS_MODE_SHIFT); + + /* CMD6 */ + if(MMC_NormalCMD_Send(mmccard,MMC_Switch,parameter,CARD_ResponseTypeR1b) != Status_Success) + { + return Status_Fail; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + status_temp = MMC_PollingCardStatusBusy(mmccard, timeoutMS == 0U ? MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT : timeoutMS); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + + return Status_Success; +} + +Status_card MMC_SetMaxEraseUnitSize(mmc_card_t* mmccard) +{ + uint32_t erase_group_size; + uint32_t erase_group_multiplier; + mmc_extended_csd_config_t extendedCsdconfig; + + /* Legacy mmc card , do not support the command */ + if ((mmccard->mmc_card_information.csd.systemSpecificationVersion == (uint32_t)MMC_SpecificationVersion3) && + (mmccard->mmc_card_information.csd.csdStructureVersion == (uint32_t)MMC_CsdStrucureVersion12)) + { + return Status_Success; + } + + if(((mmccard->mmc_card_information.flags & MMC_SupportHighCapacityFlag) == 0U) || + (mmccard->mmc_card_information.extendedCsd.highCapacityEraseUnitSize == 0U) || + (mmccard->mmc_card_information.extendedCsd.highCapacityEraseTimeout == 0U)) + { + erase_group_size = mmccard->mmc_card_information.csd.eraseGroupSize; + erase_group_multiplier = mmccard->mmc_card_information.csd.eraseGroupSizeMultiplier; + mmccard->mmc_card_information.eraseGroupBlocks = ((erase_group_size + 1U) * (erase_group_multiplier + 1U)); + } + else + { + /* Erase Unit Size = 512Kbyte * HC_ERASE_GRP_SIZE. Block size is 512 bytes. */ + mmccard->mmc_card_information.eraseGroupBlocks = (mmccard->mmc_card_information.extendedCsd.highCapacityEraseUnitSize * 1024UL); + + /* Enable high capacity erase unit size. */ + extendedCsdconfig.accessMode = MMC_ExtendedCsdAccessModeSetBits; + extendedCsdconfig.ByteIndex = (uint8_t)MMC_ExtendedCsdIndexEraseGroupDefinition; + extendedCsdconfig.ByteValue = 0x01U; /* The high capacity erase unit size enable bit is bit 0 */ + extendedCsdconfig.commandSet = MMC_CommandSetStandard; + if (Status_Success != MMC_SetExtendedCsdConfig(mmccard, &extendedCsdconfig, 0U)) + { + return Status_Fail; + } + } + + return Status_Success; +} + + + +Status_card MMC_SendExtCsd(mmc_card_t* mmccard) +{ + uint32_t card_ExtCsd[512/4]; + uint8_t* ExtCsd_temp; + SDMMC_Transfer transfer; + Status_card status_temp = Status_Success; + + /* Legacy mmc card , do not support the command */ + if ((mmccard->mmc_card_information.csd.systemSpecificationVersion == (uint32_t)MMC_SpecificationVersion3) && + (mmccard->mmc_card_information.csd.csdStructureVersion == (uint32_t)MMC_CsdStrucureVersion12)) + { + return status_temp; + } + + SDMMC_EnableFlagStatus(mmccard->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,DISABLE); + + transfer.data.AutoCommand12_23 = NoAutoCommand; + transfer.data.enableIgnoreError = ENABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = 1; + transfer.data.blockSize = 512; + transfer.data.rxData = card_ExtCsd; + transfer.data.txData = NULL; + + transfer.command.index = MMC_SendExtendedCsd; + transfer.command.argument = 0x00; + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(mmccard->SDHOSTx,NULL,&transfer,&mmccard->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + if(status_temp == Status_Success) + { + ExtCsd_temp = (uint8_t*)card_ExtCsd; + + /* Extended CSD is transferred as a data block from least byte indexed 0. */ + mmccard->mmc_card_information.extendedCsd.bootPartitionWP = ExtCsd_temp[173U]; + mmccard->mmc_card_information.extendedCsd.bootWPStatus = ExtCsd_temp[174U]; + mmccard->mmc_card_information.extendedCsd.highDensityEraseGroupDefinition = ExtCsd_temp[175U]; + mmccard->mmc_card_information.extendedCsd.bootDataBusConditions = ExtCsd_temp[177U]; + mmccard->mmc_card_information.extendedCsd.bootConfigProtect = ExtCsd_temp[178U]; + mmccard->mmc_card_information.extendedCsd.partitionConfig = ExtCsd_temp[179U]; + mmccard->mmc_card_information.extendedCsd.eraseMemoryContent = ExtCsd_temp[181U]; + mmccard->mmc_card_information.extendedCsd.dataBusWidth = ExtCsd_temp[183U]; + mmccard->mmc_card_information.extendedCsd.highSpeedTiming = ExtCsd_temp[185U]; + mmccard->mmc_card_information.extendedCsd.powerClass = ExtCsd_temp[187U]; + mmccard->mmc_card_information.extendedCsd.commandSetRevision = ExtCsd_temp[189U]; + mmccard->mmc_card_information.extendedCsd.commandSet = ExtCsd_temp[191U]; + mmccard->mmc_card_information.extendedCsd.extendecCsdVersion = ExtCsd_temp[192U]; + mmccard->mmc_card_information.extendedCsd.csdStructureVersion = ExtCsd_temp[194U]; + mmccard->mmc_card_information.extendedCsd.partitionAttribute = ExtCsd_temp[156U]; + mmccard->mmc_card_information.extendedCsd.extPartitionSupport = ExtCsd_temp[494U]; + mmccard->mmc_card_information.extendedCsd.cardType = ExtCsd_temp[196U]; + /* This field define the type of the card. The only currently valid values for this field are 0x01 and 0x03. */ + mmccard->mmc_card_information.flags |= mmccard->mmc_card_information.extendedCsd.cardType; + + mmccard->mmc_card_information.extendedCsd.ioDriverStrength = ExtCsd_temp[197U]; + + mmccard->mmc_card_information.extendedCsd.partitionSwitchTimeout = ExtCsd_temp[199U]; + mmccard->mmc_card_information.extendedCsd.powerClass52MHz195V = ExtCsd_temp[200U]; + mmccard->mmc_card_information.extendedCsd.powerClass26MHz195V = ExtCsd_temp[201U]; + mmccard->mmc_card_information.extendedCsd.powerClass52MHz360V = ExtCsd_temp[202U]; + mmccard->mmc_card_information.extendedCsd.powerClass26MHz360V = ExtCsd_temp[203U]; + mmccard->mmc_card_information.extendedCsd.powerClass200MHZVCCQ130VVCC360V = ExtCsd_temp[236U]; + mmccard->mmc_card_information.extendedCsd.powerClass200MHZVCCQ195VVCC360V = ExtCsd_temp[237U]; + mmccard->mmc_card_information.extendedCsd.powerClass52MHZDDR195V = ExtCsd_temp[238U]; + mmccard->mmc_card_information.extendedCsd.powerClass52MHZDDR360V = ExtCsd_temp[239U]; + mmccard->mmc_card_information.extendedCsd.powerClass200MHZDDR360V = ExtCsd_temp[253U]; + mmccard->mmc_card_information.extendedCsd.minimumReadPerformance4Bit26MHz = ExtCsd_temp[205U]; + mmccard->mmc_card_information.extendedCsd.minimumWritePerformance4Bit26MHz = ExtCsd_temp[206U]; + mmccard->mmc_card_information.extendedCsd.minimumReadPerformance8Bit26MHz4Bit52MHz = ExtCsd_temp[207U]; + mmccard->mmc_card_information.extendedCsd.minimumWritePerformance8Bit26MHz4Bit52MHz = ExtCsd_temp[208U]; + mmccard->mmc_card_information.extendedCsd.minimumReadPerformance8Bit52MHz = ExtCsd_temp[209U]; + mmccard->mmc_card_information.extendedCsd.minimumWritePerformance8Bit52MHz = ExtCsd_temp[210U]; + mmccard->mmc_card_information.extendedCsd.minReadPerformance8bitAt52MHZDDR = ExtCsd_temp[234U]; + mmccard->mmc_card_information.extendedCsd.minWritePerformance8bitAt52MHZDDR = ExtCsd_temp[235U]; + /* Get user partition size. */ + mmccard->mmc_card_information.extendedCsd.sectorCount = ((((uint32_t)ExtCsd_temp[215U]) << 24U) + (((uint32_t)ExtCsd_temp[214U]) << 16U) + + (((uint32_t)ExtCsd_temp[213U]) << 8U) + (uint32_t)ExtCsd_temp[212U]); + if ((mmccard->mmc_card_information.flags & (uint32_t)MMC_SupportHighCapacityFlag) != 0U) + { + mmccard->mmc_card_information.userPartitionBlocks = mmccard->mmc_card_information.extendedCsd.sectorCount; + } + + mmccard->mmc_card_information.extendedCsd.sleepAwakeTimeout = ExtCsd_temp[217U]; + mmccard->mmc_card_information.extendedCsd.sleepCurrentVCCQ = ExtCsd_temp[219U]; + mmccard->mmc_card_information.extendedCsd.sleepCurrentVCC = ExtCsd_temp[220U]; + mmccard->mmc_card_information.extendedCsd.highCapacityWriteProtectGroupSize = ExtCsd_temp[221U]; + mmccard->mmc_card_information.extendedCsd.reliableWriteSectorCount = ExtCsd_temp[222U]; + mmccard->mmc_card_information.extendedCsd.highCapacityEraseTimeout = ExtCsd_temp[223U]; + mmccard->mmc_card_information.extendedCsd.highCapacityEraseUnitSize = ExtCsd_temp[224U]; + mmccard->mmc_card_information.extendedCsd.accessSize = ExtCsd_temp[225U]; + + /* Get boot partition size: 128KB * BOOT_SIZE_MULT*/ + mmccard->mmc_card_information.bootPartitionBlocks = ((128U * 1024U * ExtCsd_temp[226U]) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + /* support HS400 data strobe */ + if (ExtCsd_temp[184] == 1U) + { + mmccard->mmc_card_information.flags |= (uint32_t)MMC_SupportEnhanceHS400StrobeFlag; + } + + /* Check if card support boot mode. */ + if ((ExtCsd_temp[228U] & 0x1U) != 0U) + { + mmccard->mmc_card_information.flags |= (uint32_t)MMC_SupportAlternateBootFlag; + } + else if ((ExtCsd_temp[228U] & 0x2U) != 0U) + { + mmccard->mmc_card_information.flags |= (uint32_t)MMC_SupportDDRBootFlag; + } + else if ((ExtCsd_temp[228U] & 0x4U) != 0U) + { + mmccard->mmc_card_information.flags |= (uint32_t)MMC_SupportHighSpeedBootFlag; + } + else + { + /* empty with intentional */ + } + /* cache size unit 1kb */ + mmccard->mmc_card_information.extendedCsd.cacheSize = (((uint32_t)ExtCsd_temp[252U]) << 24) | (((uint32_t)ExtCsd_temp[251U]) << 16) | + (((uint32_t)ExtCsd_temp[250U]) << 8) | (((uint32_t)ExtCsd_temp[249U])); + + mmccard->mmc_card_information.extendedCsd.genericCMD6Timeout = ExtCsd_temp[248U] * 10UL; + mmccard->mmc_card_information.extendedCsd.supportedCommandSet = ExtCsd_temp[504U]; + + + status_temp = Status_Success; + } + SDMMC_EnableFlagStatus(mmccard->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,ENABLE); + + return status_temp; +} + +static Status_card MMC_CheckEraseGroupRange(mmc_card_t *mmccard, uint32_t startGroup, uint32_t endGroup) +{ + Status_card status_temp = Status_Success; + uint32_t partitionBlocks; + uint32_t eraseGroupBoundary; + + partitionBlocks = mmccard->mmc_card_information.userPartitionBlocks; + + /* Check if current partition's total block count is integer multiples of the erase group size. */ + if ((partitionBlocks % mmccard->mmc_card_information.eraseGroupBlocks) == 0U) + { + eraseGroupBoundary = (partitionBlocks / mmccard->mmc_card_information.eraseGroupBlocks); + } + else + { + /* mmccard will ignore the unavailable blocks within the last erase group automatically. */ + eraseGroupBoundary = (partitionBlocks / mmccard->mmc_card_information.eraseGroupBlocks + 1U); + } + + /* Check if the group range accessed is within current partition's erase group boundary. */ + if ((startGroup > eraseGroupBoundary) || (endGroup > eraseGroupBoundary)) + { + status_temp = Status_CardOutOfRange; + } + + return status_temp; +} + + +Status_card MMC_EraseGroups(mmc_card_t* mmccard, uint32_t startGroup, uint32_t endGroup) +{ + uint32_t startGroupAddress; + uint32_t endGroupAddress; + Status_card status_temp = Status_CardStatusBusy; + uint32_t timeout_value = MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT; + + status_temp = MMC_CheckEraseGroupRange(mmccard, startGroup, endGroup); + if(status_temp != Status_Success) + { + status_temp = Status_CardOutOfRange; + } + else + { + /* polling mmccard status idle */ + status_temp = MMC_PollingCardStatusBusy(mmccard, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + status_temp = Status_PollingCardIdleFailed; + } + } + + if(status_temp == Status_CardStatusIdle) + { + /* Calculate the start group address and end group address */ + startGroupAddress = startGroup; + endGroupAddress = endGroup; + if ((mmccard->mmc_card_information.flags & (uint32_t)MMC_SupportHighCapacityFlag) != 0U) + { + /* The implementation of a higher than 2GB of density of memory will not be backwards compatible with the + lower densities.First of all the address argument for higher than 2GB of density of memory is changed to + be sector address (512B sectors) instead of byte address */ + startGroupAddress = (startGroupAddress * (mmccard->mmc_card_information.eraseGroupBlocks)); + endGroupAddress = (endGroupAddress * (mmccard->mmc_card_information.eraseGroupBlocks)); + } + else + { + /* The address unit is byte when card capacity is lower than 2GB */ + startGroupAddress = (startGroupAddress * (mmccard->mmc_card_information.eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + endGroupAddress = (endGroupAddress * (mmccard->mmc_card_information.eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + + /* CMD35 */ + if(MMC_NormalCMD_Send(mmccard,MMC_EraseGroupStart,startGroupAddress,CARD_ResponseTypeR1) != Status_Success) + { + return Status_Fail; + } + + /* CMD36 */ + if(MMC_NormalCMD_Send(mmccard,MMC_EraseGroupEnd,endGroupAddress,CARD_ResponseTypeR1) != Status_Success) + { + return Status_Fail; + } + + /* CMD38 */ + if(MMC_NormalCMD_Send(mmccard,SDMMC_Erase,0x00,CARD_ResponseTypeR1b) != Status_Success) + { + return Status_Fail; + } + + if ((0U != (mmccard->mmc_card_information.flags & (uint32_t)MMC_SupportHighCapacityFlag)) && + (mmccard->mmc_card_information.extendedCsd.highCapacityEraseTimeout != 0U)) + { + timeout_value = + (uint32_t)mmccard->mmc_card_information.extendedCsd.highCapacityEraseTimeout * 300U * (endGroup - startGroup + 1U); + } + + status_temp = MMC_PollingCardStatusBusy(mmccard, timeout_value); + if (Status_CardStatusIdle != status_temp) + { + status_temp = Status_PollingCardIdleFailed; + } + else + { + status_temp = Status_Success; + } + } + + return status_temp; +} + + +static void MMC_configSDMABufferSize(mmc_card_t *mmccard, uint32_t *buffer, uint32_t blockCount) +{ + SDHOST_SDMA_Buffer_Size Size; + uint32_t address = (uint32_t)buffer; + + if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x1000) <= 0x1000) + { + Size = SDHOST_SDMABUFFERSIZE_4KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x2000) <= 0x2000) + { + Size = SDHOST_SDMABUFFERSIZE_8KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x4000) <= 0x4000) + { + Size = SDHOST_SDMABUFFERSIZE_16KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x8000) <= 0x8000) + { + Size = SDHOST_SDMABUFFERSIZE_32KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x10000) <= 0x10000) + { + Size = SDHOST_SDMABUFFERSIZE_64KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x20000) <= 0x20000) + { + Size = SDHOST_SDMABUFFERSIZE_128KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x40000) <= 0x40000) + { + Size = SDHOST_SDMABUFFERSIZE_256KB; + } + else + { + Size = SDHOST_SDMABUFFERSIZE_512KB; + } + SDMMC_ConfigSDMABufferSize(mmccard->SDHOSTx,Size); +} + +Status_card MMC_ReadBlocks(mmc_card_t *mmccard, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + SDMMC_Transfer transfer; + SDHOST_ADMAconfig dmaConfigtemp; + SDHOST_ADMAconfig *dmaConfig; + Status_card status_temp; + + if(startBlock + blockCount > mmccard->mmc_card_information.userPartitionBlocks) + { + return Status_CardOutOfRange; + } + + /* polling mmccard status idle */ + status_temp = MMC_PollingCardStatusBusy(mmccard, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + + if(mmccard->card_workmode.dma == SDMMC_NODMA) + { + dmaConfig = NULL; + } + else if(mmccard->card_workmode.dma == SDMMC_SDMA) + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeSimple; + dmaConfig->admaTable = NULL; + dmaConfig->admaTableWords = 0; + MMC_configSDMABufferSize(mmccard,buffer,blockCount); + } + else //ADMA + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeAdma2; + dmaConfig->admaTable = buffer; + dmaConfig->admaTableWords = (*buffer & 0xFFFF0000) >> 16; + } + + transfer.data.enableIgnoreError = ENABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = blockCount; + transfer.data.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + transfer.data.rxData = buffer; + transfer.data.txData = NULL; + + if(blockCount <= 1) + { + transfer.command.index = SDMMC_ReadSingleBlock; + transfer.data.AutoCommand12_23 = NoAutoCommand; + } + else + { + transfer.command.index = SDMMC_ReadMultipleBlock; + transfer.data.AutoCommand12_23 = AutoCommand12; + } + transfer.command.argument = startBlock; + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(mmccard->SDHOSTx,dmaConfig,&transfer,&mmccard->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + else + { + status_temp = Status_Success; + } + + return status_temp; +} + + +Status_card MMC_WriteBlocks(mmc_card_t *mmccard, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + SDMMC_Transfer transfer; + SDHOST_ADMAconfig *dmaConfig; + SDHOST_ADMAconfig dmaConfigtemp; + Status_card status_temp; + + if(startBlock + blockCount > mmccard->mmc_card_information.userPartitionBlocks) + { + return Status_CardOutOfRange; + } + + /* polling mmccard status idle */ + status_temp = MMC_PollingCardStatusBusy(mmccard, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + + if(mmccard->card_workmode.dma == SDMMC_NODMA) + { + dmaConfig = NULL; + } + else if(mmccard->card_workmode.dma == SDMMC_SDMA) + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeSimple; + dmaConfig->admaTable = NULL; + dmaConfig->admaTableWords = 0; + MMC_configSDMABufferSize(mmccard,buffer,blockCount); + } + else //ADMA + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeAdma2; + dmaConfig->admaTable = buffer; + dmaConfig->admaTableWords = (*buffer & 0xFFFF0000) >> 16; + } + transfer.data.enableIgnoreError = ENABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = blockCount; + transfer.data.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + transfer.data.rxData = NULL; + transfer.data.txData = buffer; + + if(blockCount <= 1) + { + transfer.command.index = SDMMC_WriteSingleBlock; + transfer.data.AutoCommand12_23 = NoAutoCommand; + } + else + { + transfer.command.index = SDMMC_WriteMultipleBlock; + transfer.data.AutoCommand12_23 = AutoCommand12; + } + transfer.command.argument = startBlock; + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(mmccard->SDHOSTx,dmaConfig,&transfer,&mmccard->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + else + { + status_temp = Status_Success; + } + + return status_temp; +} + + +Status_card MMC_SwitchVoltage(mmc_card_t *mmccard) +{ + Status_card status_temp = Status_Success; + uint32_t Mscnt_value; + uint32_t Mscnt_temp; + if((mmccard->mmc_card_information.flags & SD_SupportVoltage180v) != SD_SupportVoltage180v) + { + status_temp = Status_CardNotSupportYet; + } + + /* CMD11 */ + else if(MMC_NormalCMD_Send(mmccard,SD_VoltageSwitch,0x00,CARD_ResponseTypeR1) != Status_Success) + { + status_temp = Status_Fail; + } + else + { + SDMMC_EnableSDCLK(mmccard->SDHOSTx,DISABLE); + /* delay 5ms */ + Mscnt_value = 0; + MMC_SysTick_start_time(); + Mscnt_temp = MMC_systick_timeoutms; + while(Mscnt_value<1) + { + Mscnt_value = MMC_User_Time_Read(Mscnt_temp); + } + + + if(SDMMC_GetPresentFlagStatus(mmccard->SDHOSTx,(SDHOST_Data0LineLevelFlag | SDHOST_Data1LineLevelFlag | + SDHOST_Data2LineLevelFlag | SDHOST_Data3LineLevelFlag)) == SET) + { + status_temp = Status_Fail; + return status_temp; + } + + SDMMC_EnableVolSwitch(mmccard->SDHOSTx,ENABLE); + /* delay 5ms */ + Mscnt_value = 0; + MMC_SysTick_start_time(); + Mscnt_temp = MMC_systick_timeoutms; + while(Mscnt_value<5) + { + Mscnt_value = MMC_User_Time_Read(Mscnt_temp); + } + + if((mmccard->SDHOSTx->CTRLSTS & SDHOST_CTRLSTS_V18SE) != SDHOST_CTRLSTS_V18SE) + { + status_temp = Status_Fail; + } + else + { + SDMMC_EnableSDCLK(mmccard->SDHOSTx,ENABLE);; + /* Wait until the clock is stable. */ + SDMMC_WaitSDCLKStable(mmccard->SDHOSTx); + + /* delay 1ms */ + Mscnt_value = 0; + MMC_SysTick_start_time(); + Mscnt_temp = MMC_systick_timeoutms; + while(Mscnt_value<1) + { + Mscnt_value = MMC_User_Time_Read(Mscnt_temp); + } + + if(SDMMC_GetPresentFlagStatus(mmccard->SDHOSTx,(SDHOST_Data0LineLevelFlag | SDHOST_Data1LineLevelFlag | + SDHOST_Data2LineLevelFlag | SDHOST_Data3LineLevelFlag)) != SET) + { + status_temp = Status_Fail; + } + } + } + return status_temp; +} + + +//static Status_card SD_SwitchFunction(mmc_card_t *mmccard,uint32_t mode) +//{ +// uint32_t card_scr[16]; +// uint32_t cnt_value; +// SDMMC_Transfer transfer; +// Status_card status_temp = Status_Success; +// +// if(mode > 2) +// { +// mode = mode - 2; +// } + +// SDMMC_EnableFlagStatus(mmccard->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,DISABLE); +// +// transfer.data.AutoCommand12_23 = NoAutoCommand; +// transfer.data.enableIgnoreError = DISABLE; +// transfer.data.dataType = SDHOST_TransferDataNormal; +// transfer.data.blockCount = 1; +// transfer.data.blockSize = 64; +// transfer.data.rxData = card_scr; +// transfer.data.txData = NULL; + +// transfer.command.index = SD_Switch; +// transfer.command.argument = (0x00fffff0U | mode); +// transfer.command.type = CARD_CommandTypeNormal; +// transfer.command.responseType = CARD_ResponseTypeR1; +// transfer.command.flags = 0x00; +// transfer.command.responseErrorFlags = 0x00; +// +// if(SDMMC_TransferBlocking(mmccard->SDHOSTx,NULL,&transfer,&mmccard->TMODE_truct) != SDMMC_SUCCESS) +// { +// status_temp = Status_Fail; +// } +// +// if(status_temp == Status_Success) +// { +// for(cnt_value = 0;cnt_value< 16; cnt_value++) +// { +// card_scr[cnt_value] = swap_uint32(card_scr[cnt_value]); +// } +// +// /* -card_scr[0U]---bit511~bit480; +// -card_scr[1U]---bit479~bit448; +// -card_scr[2U]---bit447~bit416; +// -card_scr[3U]---bit415~bit384; +// -card_scr[4U]---bit383~bit352; +// According to the "switch function status[bits 511~0]" return by switch command in mode "check function": +// -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; +// -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; +// */ +// if((((card_scr[3] >> 16) & (1 << mode)) == 0) || (((card_scr[4] & 0x0F000000) >> 24) != mode)) +// { +// log_info("\r\nError: current mmccard not support function %d\r\n", mode); +// status_temp = Status_CardNotSupportYet; +// } +// } +// +// if(status_temp == Status_Success) +// { +// transfer.command.argument = (0x80fffff0U | mode); +// if(SDMMC_TransferBlocking(mmccard->SDHOSTx,NULL,&transfer,&mmccard->TMODE_truct) != SDMMC_SUCCESS) +// { +// status_temp = Status_Fail; +// } +// +// if(status_temp == Status_Success) +// { +// for(cnt_value = 0;cnt_value< 16; cnt_value++) +// { +// card_scr[cnt_value] = swap_uint32(card_scr[cnt_value]); +// } +// +// /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": +// -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; +// */ +// if(((card_scr[4] & 0x0F000000) >> 24) != mode) +// { +// log_info("\r\nError: switch to function %d failed\r\n", mode); +// status_temp = Status_CardSwitchFailed; +// } +// } +// } +// +// SDMMC_EnableFlagStatus(mmccard->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,ENABLE); +// return status_temp; +//} + + +static Status_card MMC_SetMaxDataBusWidth(mmc_card_t *mmccard) +{ + Status_card status_temp = Status_Success; + mmc_extended_csd_config_t extendedCsdconfig; + + extendedCsdconfig.accessMode = MMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)MMC_ExtendedCsdIndexBusWidth; + extendedCsdconfig.ByteValue = (uint8_t)MMC_DataBusWidth8bitDDR; + extendedCsdconfig.commandSet = MMC_CommandSetStandard; + + if (mmccard->card_workmode.busWidth == MMC_DataBusWidth8bitDDR) + { + if(0U != (mmccard->mmc_card_information.flags & ((uint32_t)MMC_SupportHighSpeedDDR52MHZ180V300VFlag | + (uint32_t)MMC_SupportHighSpeedDDR52MHZ120VFlag))) + { + /* Set data bus width */ + extendedCsdconfig.ByteValue = (uint8_t)MMC_DataBusWidth8bitDDR; + if(MMC_SetExtendedCsdConfig(mmccard,&extendedCsdconfig, 0U) != Status_Success) + { + status_temp = Status_Fail; + } + else + { + SDMMC_ConfigBusWidth(mmccard->SDHOSTx, SDHOST_DataBusWidth8Bit); + status_temp = Status_Success; + mmccard->mmc_card_information.extendedCsd.dataBusWidth = MMC_DataBusWidth8bitDDR; + } + } + else + { + status_temp = Status_CardNotSupportYet; + } + } + + if (mmccard->card_workmode.busWidth == MMC_DataBusWidth4bitDDR) + { + if(0U != (mmccard->mmc_card_information.flags & ((uint32_t)MMC_SupportHighSpeedDDR52MHZ180V300VFlag | + (uint32_t)MMC_SupportHighSpeedDDR52MHZ120VFlag))) + { + /* Set data bus width */ + extendedCsdconfig.ByteValue = (uint8_t)MMC_DataBusWidth4bitDDR; + if(MMC_SetExtendedCsdConfig(mmccard,&extendedCsdconfig, 0U) != Status_Success) + { + status_temp = Status_Fail; + } + else + { + SDMMC_ConfigBusWidth(mmccard->SDHOSTx, SDHOST_DataBusWidth4Bit); + status_temp = Status_Success; + mmccard->mmc_card_information.extendedCsd.dataBusWidth = MMC_DataBusWidth4bitDDR; + } + } + else + { + status_temp = Status_CardNotSupportYet; + } + } + + if (mmccard->card_workmode.busWidth == MMC_DataBusWidth8bit) + { + /* Set data bus width */ + extendedCsdconfig.ByteValue = (uint8_t)MMC_DataBusWidth8bit; + if(MMC_SetExtendedCsdConfig(mmccard,&extendedCsdconfig, 0U) != Status_Success) + { + status_temp = Status_Fail; + } + else + { + SDMMC_ConfigBusWidth(mmccard->SDHOSTx, SDHOST_DataBusWidth8Bit); + status_temp = Status_Success; + mmccard->mmc_card_information.extendedCsd.dataBusWidth = MMC_DataBusWidth8bit; + } + } + + if (mmccard->card_workmode.busWidth == MMC_DataBusWidth4bit) + { + /* Set data bus width */ + extendedCsdconfig.ByteValue = (uint8_t)MMC_DataBusWidth4bit; + if(MMC_SetExtendedCsdConfig(mmccard,&extendedCsdconfig, 0U) != Status_Success) + { + status_temp = Status_Fail; + } + else + { + SDMMC_ConfigBusWidth(mmccard->SDHOSTx, SDHOST_DataBusWidth4Bit); + status_temp = Status_Success; + mmccard->mmc_card_information.extendedCsd.dataBusWidth = MMC_DataBusWidth4bit; + } + } + + return status_temp; +} + + +static Status_card MMC_SwitchHSTiming(mmc_card_t *mmccard, uint8_t timing, uint8_t driverStrength) +{ + uint8_t hsTiming = 0; + + mmc_extended_csd_config_t extendedCsdconfig; + + /* check the target driver strength support or not */ + if (((mmccard->mmc_card_information.extendedCsd.ioDriverStrength & (1U << driverStrength)) == 0U) && + (mmccard->mmc_card_information.extendedCsd.extendecCsdVersion >= (uint8_t)MMC_ExtendedCsdRevision16)) + { + return Status_CardNotSupportYet; + } + /* calucate the register value */ + hsTiming = (timing & 0xFU) | (uint8_t)(driverStrength << 4U); + + /* Switch to high speed timing. */ + extendedCsdconfig.accessMode = MMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)MMC_ExtendedCsdIndexHighSpeedTiming; + extendedCsdconfig.ByteValue = hsTiming; + extendedCsdconfig.commandSet = MMC_CommandSetStandard; + if (Status_Success != MMC_SetExtendedCsdConfig(mmccard, &extendedCsdconfig, 0U)) + { + return Status_Fail; + } + + mmccard->mmc_card_information.extendedCsd.highSpeedTiming = hsTiming; + + return Status_Success; +} + +static Status_card MMC_SwitchToHS200(mmc_card_t *mmccard) +{ + Status_card status_temp = Status_Fail; + + /* select bus width before select bus timing for HS200 mode */ + if (MMC_SetMaxDataBusWidth(mmccard) != Status_Success) + { + return Status_Fail; + } + + /* switch to HS200 mode */ + if (Status_Success != MMC_SwitchHSTiming(mmccard, (uint8_t)MMC_HighSpeed200Timing, MMC_DriverStrength0)) + { + return Status_Fail; + } + + SDMMC_ConfigWorkMode(mmccard->SDHOSTx,SDMMC_SDR104); + + +// card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, freq); +// /* config io speed and strength */ +// if (card->usrParam.ioStrength != NULL) +// { +// card->usrParam.ioStrength(freq); +// } + +// /* excute tuning for HS200 */ +// if (MMC_ExecuteTuning(card) != kStatus_Success) +// { +// return kStatus_SDMMC_TuningFail; +// } + + status_temp = MMC_PollingCardStatusBusy(mmccard, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + return Status_Fail; + } + + return Status_Success; +} + +static Status_card MMC_SwitchToHighSpeed(mmc_card_t *mmccard) +{ +// uint32_t freq = 0U; + + if (Status_Success != MMC_SwitchHSTiming(mmccard, (uint8_t)MMC_HighSpeedTiming, MMC_DriverStrength0)) + { + return Status_Fail; + } + +// if ((mmccard->mmc_card_information.flags & (uint32_t)MMC_SupportHighSpeed52MHZFlag) != 0U) +// { +// freq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, MMC_CLOCK_52MHZ); +// } +// else if ((card->flags & (uint32_t)kMMC_SupportHighSpeed26MHZFlag) != 0U) +// { +// freq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, MMC_CLOCK_26MHZ); +// } +// else +// { +// /* Intentional empty */ +// } + +// card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, freq); +// /* config io speed and strength */ +// if (card->usrParam.ioStrength != NULL) +// { +// card->usrParam.ioStrength(MMC_CLOCK_52MHZ); +// } + + /* Set card data width, it is nessesary to config the the data bus here, to meet emmc5.0 specification, + * when you are working in DDR mode , HS_TIMING must set before set bus width + */ + if (MMC_SetMaxDataBusWidth(mmccard) != Status_Success) + { + return Status_Fail; + } + + if ((mmccard->card_workmode.busWidth == MMC_DataBusWidth4bitDDR) || (mmccard->card_workmode.busWidth == MMC_DataBusWidth8bitDDR)) + { + SDMMC_ConfigWorkMode(mmccard->SDHOSTx,SDMMC_DDR50); + } + else + { + SDMMC_ConfigWorkMode(mmccard->SDHOSTx,SDMMC_SDR50); + } + +// card->busTiming = kMMC_HighSpeedTiming; + + return Status_Success; +} + +Status_card MMC_SelectBusTiming(mmc_card_t *mmccard) +{ + Status_card status_temp = Status_Success; + + /* Legacy mmc card , do not support the command */ + if ((mmccard->mmc_card_information.csd.systemSpecificationVersion == (uint32_t)MMC_SpecificationVersion3) && + (mmccard->mmc_card_information.csd.csdStructureVersion == (uint32_t)MMC_CsdStrucureVersion12)) + { + return Status_Success; + } + + if(mmccard->card_workmode.busTiming == MMC_HighSpeedTimingNone) + { + /* if timing not specified, probe card capability from normal mode */ + mmccard->card_workmode.busTiming = MMC_NormalSpeedTiming; + } + + if(mmccard->card_workmode.busTiming == MMC_HighSpeed200Timing) + { + if(((mmccard->card_workmode.operationVoltageflag == MMC_OperationVoltage170to195V) || \ + (mmccard->card_workmode.operationVoltageflag == MMC_OperationVoltage120V)) && \ + ((mmccard->mmc_card_information.flags & (MMC_SupportHS200200MHZ180VFlag | MMC_SupportHS200200MHZ120VFlag)) != 0U)) + { + if(MMC_SwitchToHS200(mmccard) != Status_Success) + { + return Status_Fail; + } + else + { + status_temp = Status_Success; + } + } + else + { + status_temp = Status_CardNotSupportYet; + } + } + + if(mmccard->card_workmode.busTiming == MMC_HighSpeedTiming) + { + if(MMC_SwitchToHighSpeed(mmccard) != Status_Success) + { + return Status_Fail; + } + else + { + status_temp = Status_Success; + } + } + + if(mmccard->card_workmode.busTiming == MMC_NormalSpeedTiming) + { + /* select bus width */ + if (MMC_SetMaxDataBusWidth(mmccard) != Status_Success) + { + return Status_Fail; + } + else + { + status_temp = Status_Success; + } + } + + return status_temp; +} + +/** Read User Time Since Last Set + * param last time. + */ +uint32_t MMC_User_Time_Read(uint32_t time) +{ + if(MMC_systick_timeoutms>=time) + { + return MMC_systick_timeoutms-time; + } + return(0xFFFFFFFF-time+MMC_systick_timeoutms); +} + +/** MMC_SysTick_start_time. **/ +void MMC_SysTick_start_time(void) +{ + MMC_systick_timeoutms = 0; + +} + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/src/sd_host.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/src/sd_host.c new file mode 100644 index 0000000000..b07fdb68dd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_periph_app/src/sd_host.c @@ -0,0 +1,873 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file sd_host.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "sd_host.h" + +static Status_card SD_SendCardStatus(sd_card_t* card); +static void SD_configSDMABufferSize(sd_card_t *card, uint32_t *buffer, uint32_t blockCount); +static Status_card SD_SwitchFunction(sd_card_t *card,uint32_t mode);; + + + +/* SD card block erase time, varies according to different SD cards */ +#define SD_BLOCKERASE_TIME (250U) + +uint32_t SD_systick_timeoutms = 0; + +Status_card SD_NormalCMD_Send(sd_card_t* card, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType) +{ + Status_card status_temp; + + card->command.index = index; + card->command.argument = argument; + card->command.type = CARD_CommandTypeNormal; + card->command.responseType = responseType; + card->command.flags = 0x00; + card->command.responseErrorFlags = 0x00; + SDMMC_SendCommand(card->SDHOSTx,&card->command,&card->TMODE_truct); + if(SDMMC_WaitCommandDone(card->SDHOSTx,&card->command,ENABLE) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + else + { + status_temp = Status_Success; + } + return status_temp; +} + + +Status_card SD_AutoCMD_Send(sd_card_t* card, uint32_t index,uint32_t argument,SDMMC_CardRspType responseType) +{ + Status_card status_temp = Status_Success; + + /* CMD55 */ + card->command.index = SDMMC_ApplicationCommand; + card->command.argument = card->sd_card_information.rca << 16; + card->command.type = CARD_CommandTypeNormal; + card->command.responseType = CARD_ResponseTypeR1; + card->command.flags = 0x00; + card->command.responseErrorFlags = 0x00; + SDMMC_SendCommand(card->SDHOSTx,&card->command,&card->TMODE_truct); + if(SDMMC_WaitCommandDone(card->SDHOSTx,&card->command,ENABLE) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + card->command.index = index; + card->command.argument = argument; + card->command.type = CARD_CommandTypeNormal; + card->command.responseType = responseType; + card->command.flags = 0x00; + card->command.responseErrorFlags = 0x00; + SDMMC_SendCommand(card->SDHOSTx,&card->command,&card->TMODE_truct); + if(SDMMC_WaitCommandDone(card->SDHOSTx,&card->command,ENABLE) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + return status_temp; +} + + +void SD_DecodeCid(sd_card_t* card) +{ + /* get cid */ + card->sd_card_information.cid.manufacturerID = (uint8_t)((card->command.response[3U] & 0xFF000000U) >> 24U); + card->sd_card_information.cid.applicationID = (uint16_t)((card->command.response[3U] & 0xFFFF00U) >> 8U); + + card->sd_card_information.cid.productName[0U] = (uint8_t)((card->command.response[3U] & 0xFFU)); + card->sd_card_information.cid.productName[1U] = (uint8_t)((card->command.response[2U] & 0xFF000000U) >> 24U); + card->sd_card_information.cid.productName[2U] = (uint8_t)((card->command.response[2U] & 0xFF0000U) >> 16U); + card->sd_card_information.cid.productName[3U] = (uint8_t)((card->command.response[2U] & 0xFF00U) >> 8U); + card->sd_card_information.cid.productName[4U] = (uint8_t)((card->command.response[2U] & 0xFFU)); + + card->sd_card_information.cid.productVersion = (uint8_t)((card->command.response[1U] & 0xFF000000U) >> 24U); + + card->sd_card_information.cid.productSerialNumber = (uint32_t)((card->command.response[1U] & 0xFFFFFFU) << 8U); + card->sd_card_information.cid.productSerialNumber |= (uint32_t)((card->command.response[0U] & 0xFF000000U) >> 24U); + + card->sd_card_information.cid.manufacturerData = (uint16_t)((card->command.response[0U] & 0xFFF00U) >> 8U); +} + + +void SD_DecodeCsd(sd_card_t* card) +{ + card->sd_card_information.csd.csdStructure = (uint8_t)((card->command.response[3U] & 0xC0000000U) >> 30U); + card->sd_card_information.csd.dataReadAccessTime1 = (uint8_t)((card->command.response[3U] & 0xFF0000U) >> 16U); + card->sd_card_information.csd.dataReadAccessTime2 = (uint8_t)((card->command.response[3U] & 0xFF00U) >> 8U); + card->sd_card_information.csd.transferSpeed = (uint8_t)(card->command.response[3U] & 0xFFU); + card->sd_card_information.csd.cardCommandClass = (uint16_t)((card->command.response[2U] & 0xFFF00000U) >> 20U); + card->sd_card_information.csd.readBlockLength = (uint8_t)((card->command.response[2U] & 0xF0000U) >> 16U); + if ((card->command.response[2U] & 0x8000U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdReadBlockPartialFlag; + } + if ((card->command.response[2U] & 0x4000U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdWriteBlockMisalignFlag; + } + if ((card->command.response[2U] & 0x2000U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdReadBlockMisalignFlag; + } + if ((card->command.response[2U] & 0x1000U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdDsrImplementedFlag; + } + if (card->sd_card_information.csd.csdStructure == 0U) + { + card->sd_card_information.csd.deviceSize = (uint32_t)((card->command.response[2U] & 0x3FFU) << 2U); + card->sd_card_information.csd.deviceSize |= (uint32_t)((card->command.response[1U] & 0xC0000000U) >> 30U); + card->sd_card_information.csd.readCurrentVddMin = (uint8_t)((card->command.response[1U] & 0x38000000U) >> 27U); + card->sd_card_information.csd.readCurrentVddMax = (uint8_t)((card->command.response[1U] & 0x7000000U) >> 24U); + card->sd_card_information.csd.writeCurrentVddMin = (uint8_t)((card->command.response[1U] & 0xE00000U) >> 20U); + card->sd_card_information.csd.writeCurrentVddMax = (uint8_t)((card->command.response[1U] & 0x1C0000U) >> 18U); + card->sd_card_information.csd.deviceSizeMultiplier = (uint8_t)((card->command.response[1U] & 0x38000U) >> 15U); + + /* Get card total block count and block size. */ + card->sd_card_information.blockCount = ((card->sd_card_information.csd.deviceSize + 1U) << (card->sd_card_information.csd.deviceSizeMultiplier + 2U)); + card->sd_card_information.blockSize = (1UL << (card->sd_card_information.csd.readBlockLength)); + if (card->sd_card_information.blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) + { + card->sd_card_information.blockCount = (card->sd_card_information.blockCount * card->sd_card_information.blockSize); + card->sd_card_information.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + card->sd_card_information.blockCount = (card->sd_card_information.blockCount / card->sd_card_information.blockSize); + } + } + else if (card->sd_card_information.csd.csdStructure == 1U) + { + card->sd_card_information.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + + card->sd_card_information.csd.deviceSize = (uint32_t)((card->command.response[2U] & 0x3FU) << 16U); + card->sd_card_information.csd.deviceSize |= (uint32_t)((card->command.response[1U] & 0xFFFF0000U) >> 16U); + if (card->sd_card_information.csd.deviceSize >= 0xFFFFU) + { + card->sd_card_information.flags |= (uint32_t)SD_SupportSdxcFlag; + } + + card->sd_card_information.blockCount = ((card->sd_card_information.csd.deviceSize + 1U) * 1024U); + } + else + { + /* not support csd version */ + } + + if ((uint8_t)((card->command.response[1U] & 0x4000U) >> 14U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdEraseBlockEnabledFlag; + } + card->sd_card_information.csd.eraseSectorSize = (uint8_t)((card->command.response[1U] & 0x3F80U) >> 7U); + card->sd_card_information.csd.writeProtectGroupSize = (uint8_t)(card->command.response[1U] & 0x7FU); + if ((uint8_t)(card->command.response[0U] & 0x80000000U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdWriteProtectGroupEnabledFlag; + } + card->sd_card_information.csd.writeSpeedFactor = (uint8_t)((card->command.response[0U] & 0x1C000000U) >> 26U); + card->sd_card_information.csd.writeBlockLength = (uint8_t)((card->command.response[0U] & 0x3C00000U) >> 22U); + if ((uint8_t)((card->command.response[0U] & 0x200000U) >> 21U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdWriteBlockPartialFlag; + } + if ((uint8_t)((card->command.response[0U] & 0x8000U) >> 15U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdFileFormatGroupFlag; + } + if ((uint8_t)((card->command.response[0U] & 0x4000U) >> 14U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdCopyFlag; + } + if ((uint8_t)((card->command.response[0U] & 0x2000U) >> 13U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdPermanentWriteProtectFlag; + } + if ((uint8_t)((card->command.response[0U] & 0x1000U) >> 12U) != 0U) + { + card->sd_card_information.csd.flags |= (uint16_t)SD_CsdTemporaryWriteProtectFlag; + } + card->sd_card_information.csd.fileFormat = (uint8_t)((card->command.response[0U] & 0xC00U) >> 10U); +} + +static Status_card SD_SendCardStatus(sd_card_t* card) +{ + Status_card status_temp; + uint32_t retry = SD_CMD13_RETRY_TIMES; + while(retry != 0U) + { + /* CMD13 */ + if(SD_NormalCMD_Send(card,SDMMC_SendStatus,card->sd_card_information.rca << 16,CARD_ResponseTypeR1) != Status_Success) + { + if(SDMMC_GetPresentFlagStatus(card->SDHOSTx,SDHOST_CommandInhibitFlag)) + { + SDMMC_SoftWareReset(card->SDHOSTx,SDHOST_SOFTWARE_CMDLINE); + } + status_temp = Status_Fail; + retry--; + } + else + { + if(((card->command.response[0] & SDMMC_MASK(SDMMC_R1ReadyForDataFlag)) != 0U) && + (SDMMC_R1_CURRENT_STATE(card->command.response[0U]) != (uint32_t)SDMMC_R1StateProgram)) + { + status_temp = Status_CardStatusIdle; + } + else + { + status_temp = Status_CardStatusBusy; + } + break; + } + } + return status_temp; +} + +Status_card SD_PollingCardStatusBusy(sd_card_t* card,uint32_t timeoutMs) +{ + uint32_t timeout_temp; + uint32_t timeout_cnt = 0; + bool cardBusy = false; + Status_card status_temp = Status_CardStatusBusy; + + SD_SysTick_start_time(); + timeout_temp = SD_systick_timeoutms; + while(timeout_cnt < timeoutMs) + { + if(SDMMC_GetPresentFlagStatus(card->SDHOSTx,SDHOST_Data0LineLevelFlag) == SET) + { + cardBusy = false; + } + else + { + cardBusy = true; + } + + if (cardBusy == false) + { + status_temp = SD_SendCardStatus(card); + if (status_temp == Status_CardStatusIdle) + { + break; + } + } + + timeout_cnt = SD_User_Time_Read(timeout_temp); + } + + if(SDMMC_GetFlagStatus(card->SDHOSTx,SDHOST_DataCompleteFlag) == SET) + { + SDMMC_ClrFlag(card->SDHOSTx,SDHOST_DataCompleteFlag); + } + + return status_temp; +} + +Status_card SD_SendSCR(sd_card_t* card) +{ + uint32_t card_scr[2]; + SDMMC_Transfer transfer; + Status_card status_temp = Status_Success; + + SDMMC_EnableFlagStatus(card->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,DISABLE); + + /* CMD55 */ + if(SD_NormalCMD_Send(card,SDMMC_ApplicationCommand,card->sd_card_information.rca << 16,CARD_ResponseTypeR1) != Status_Success) + { + status_temp = Status_Fail; + } + + + transfer.data.AutoCommand12_23 = NoAutoCommand; + transfer.data.enableIgnoreError = DISABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = 1; + transfer.data.blockSize = 8; + transfer.data.rxData = card_scr; + transfer.data.txData = NULL; + + transfer.command.index = SD_ApplicationSendScr; + transfer.command.argument = 0x00; + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(card->SDHOSTx,NULL,&transfer,&card->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + if(status_temp == Status_Success) + { + card->sd_card_information.scr.scrStructure = (uint8_t)((card_scr[0] & 0x000000F0U) >> 4); + card->sd_card_information.scr.sdSpecification = (uint8_t)(card_scr[0] & 0x0000000FU); + + if((card_scr[0] & 0x00008000) != 0) + { + card->sd_card_information.scr.flags |= (uint8_t)SD_ScrDataStatusAfterErase; + } + card->sd_card_information.scr.sdSecurity = (uint8_t)((card_scr[0] & 0x00007000U) >> 12); + card->sd_card_information.scr.sdBusWidths = (uint8_t)((card_scr[0] & 0x00000F00U) >> 8); + if((card_scr[0] & 0x00800000) != 0) + { + card->sd_card_information.scr.flags |= (uint8_t)SD_ScrSdSpecification3; + } + card->sd_card_information.scr.commandSupport = (uint8_t)((card_scr[0] & 0x03000000U) >> 24); + card->sd_card_information.scr.reservedForManufacturer = (((card_scr[1] << 24) & 0xff000000) | ((card_scr[1] << 8) & 0x00ff0000) + | ((card_scr[1] >> 8) & 0x0000ff00) | ((card_scr[1] >> 24) & 0x000000ff)); + + if(card->sd_card_information.scr.sdSpecification == 0U) + { + card->sd_card_information.version = SD_SpecificationVersion1_0; + } + else if(card->sd_card_information.scr.sdSpecification == 1U) + { + card->sd_card_information.version = SD_SpecificationVersion1_1; + } + else if(card->sd_card_information.scr.sdSpecification == 2U) + { + card->sd_card_information.version = SD_SpecificationVersion2_0; + if((card->sd_card_information.flags & SD_ScrSdSpecification3) != 0) + { + card->sd_card_information.version = SD_SpecificationVersion3_0; + } + } + else + { + /* reserved */ + } + + if((card->sd_card_information.scr.sdBusWidths & 0x04U) != 0) + { + card->sd_card_information.flags |= (uint32_t)SD_Support4BitWidthFlag; + } + + if((card->sd_card_information.scr.commandSupport & 0x01U) != 0) + { + card->sd_card_information.flags |= (uint32_t)SD_SupportSpeedClassControlCmd; + } + + if((card->sd_card_information.scr.commandSupport & 0x02U) != 0) + { + card->sd_card_information.flags |= (uint32_t)SD_SupportSetBlockCountCmd; + } + + status_temp = Status_Success; + } + SDMMC_EnableFlagStatus(card->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,ENABLE); + + return status_temp; +} + + +Status_card SD_Erase_Block(sd_card_t* card, uint32_t startBlock, uint32_t blockCount) +{ + uint32_t eraseBlockStart; + uint32_t eraseBlockEnd; + Status_card status_temp = Status_CardStatusBusy; + uint32_t timeout_block = SD_BLOCKERASE_TIME; /* 250ms erase timeout by default */ + + if(startBlock + blockCount > card->sd_card_information.blockCount) + { + return Status_CardOutOfRange; + } + + /* polling card status idle */ + status_temp = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + + eraseBlockStart = startBlock; + eraseBlockEnd = eraseBlockStart + blockCount - 1U; + + /* SDSC card */ + if (0U == (card->sd_card_information.flags & (uint32_t)SD_SupportHighCapacityFlag)) + { + eraseBlockStart = startBlock * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + + /* CMD32 */ + if(SD_NormalCMD_Send(card,SD_EraseWriteBlockStart,eraseBlockStart,CARD_ResponseTypeR1) != Status_Success) + { + return Status_Fail; + } + + /* CMD33 */ + if(SD_NormalCMD_Send(card,SD_EraseWriteBlockEnd,eraseBlockEnd,CARD_ResponseTypeR1) != Status_Success) + { + return Status_Fail; + } + + /* CMD38 */ + if(SD_NormalCMD_Send(card,SDMMC_Erase,0x00,CARD_ResponseTypeR1b) != Status_Success) + { + return Status_Fail; + } + + status_temp = SD_PollingCardStatusBusy(card, timeout_block*blockCount); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + return status_temp; +} + + +static void SD_configSDMABufferSize(sd_card_t *card, uint32_t *buffer, uint32_t blockCount) +{ + SDHOST_SDMA_Buffer_Size Size; + uint32_t address = (uint32_t)buffer; + + if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x1000) <= 0x1000) + { + Size = SDHOST_SDMABUFFERSIZE_4KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x2000) <= 0x2000) + { + Size = SDHOST_SDMABUFFERSIZE_8KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x4000) <= 0x4000) + { + Size = SDHOST_SDMABUFFERSIZE_16KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x8000) <= 0x8000) + { + Size = SDHOST_SDMABUFFERSIZE_32KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x10000) <= 0x10000) + { + Size = SDHOST_SDMABUFFERSIZE_64KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x20000) <= 0x20000) + { + Size = SDHOST_SDMABUFFERSIZE_128KB; + } + else if(blockCount * FSL_SDMMC_DEFAULT_BLOCK_SIZE + (address%0x40000) <= 0x40000) + { + Size = SDHOST_SDMABUFFERSIZE_256KB; + } + else + { + Size = SDHOST_SDMABUFFERSIZE_512KB; + } + SDMMC_ConfigSDMABufferSize(card->SDHOSTx,Size); +} + +Status_card SD_ReadBlocks(sd_card_t *card, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + SDMMC_Transfer transfer; + SDHOST_ADMAconfig dmaConfigtemp; + SDHOST_ADMAconfig *dmaConfig; + Status_card status_temp; + + if(startBlock + blockCount > card->sd_card_information.blockCount) + { + return Status_CardOutOfRange; + } + + /* polling card status idle */ + status_temp = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + + if(card->card_workmode.dma == SDMMC_NODMA) + { + dmaConfig = NULL; + } + else if(card->card_workmode.dma == SDMMC_SDMA) + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeSimple; + dmaConfig->admaTable = NULL; + dmaConfig->admaTableWords = 0; + SD_configSDMABufferSize(card,buffer,blockCount); + } + else //ADMA + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeAdma2; + dmaConfig->admaTable = buffer; + dmaConfig->admaTableWords = (*buffer & 0xFFFF0000) >> 16; + } + + transfer.data.enableIgnoreError = DISABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = blockCount; + transfer.data.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + transfer.data.rxData = buffer; + transfer.data.txData = NULL; + + if(blockCount <= 1) + { + transfer.command.index = SDMMC_ReadSingleBlock; + transfer.data.AutoCommand12_23 = NoAutoCommand; + } + else + { + transfer.command.index = SDMMC_ReadMultipleBlock; + transfer.data.AutoCommand12_23 = AutoCommand12; + } + transfer.command.argument = startBlock; + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(card->SDHOSTx,dmaConfig,&transfer,&card->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + else + { + status_temp = Status_Success; + } + + return status_temp; +} + + +Status_card SD_WriteBlocks(sd_card_t *card, uint32_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + SDMMC_Transfer transfer; + SDHOST_ADMAconfig *dmaConfig; + SDHOST_ADMAconfig dmaConfigtemp; + Status_card status_temp; + + if(startBlock + blockCount > card->sd_card_information.blockCount) + { + return Status_CardOutOfRange; + } + + /* polling card status idle */ + status_temp = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (Status_CardStatusIdle != status_temp) + { + return Status_PollingCardIdleFailed; + } + + if(card->card_workmode.dma == SDMMC_NODMA) + { + dmaConfig = NULL; + } + else if(card->card_workmode.dma == SDMMC_SDMA) + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeSimple; + dmaConfig->admaTable = NULL; + dmaConfig->admaTableWords = 0; + SD_configSDMABufferSize(card,buffer,blockCount); + } + else //ADMA + { + dmaConfig = &dmaConfigtemp; + dmaConfig->dmaMode = DmaModeAdma2; + dmaConfig->admaTable = buffer; + dmaConfig->admaTableWords = (*buffer & 0xFFFF0000) >> 16; + } + transfer.data.enableIgnoreError = DISABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = blockCount; + transfer.data.blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + transfer.data.rxData = NULL; + transfer.data.txData = buffer; + + if(blockCount <= 1) + { + transfer.command.index = SDMMC_WriteSingleBlock; + transfer.data.AutoCommand12_23 = NoAutoCommand; + } + else + { + transfer.command.index = SDMMC_WriteMultipleBlock; + transfer.data.AutoCommand12_23 = AutoCommand12; + } + transfer.command.argument = startBlock; + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(card->SDHOSTx,dmaConfig,&transfer,&card->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + else + { + status_temp = Status_Success; + } + + return status_temp; +} + + +Status_card SD_SwitchVoltage(sd_card_t *card) +{ + Status_card status_temp = Status_Success; + uint32_t Mscnt_value; + uint32_t Mscnt_temp; + if((card->sd_card_information.flags & SD_SupportVoltage180v) != SD_SupportVoltage180v) + { + status_temp = Status_CardNotSupportYet; + } + + /* CMD11 */ + else if(SD_NormalCMD_Send(card,SD_VoltageSwitch,0x00,CARD_ResponseTypeR1) != Status_Success) + { + status_temp = Status_Fail; + } + else + { + SDMMC_EnableSDCLK(card->SDHOSTx,DISABLE); + /* delay 5ms */ + Mscnt_value = 0; + SD_SysTick_start_time(); + Mscnt_temp = SD_systick_timeoutms; + while(Mscnt_value<1) + { + Mscnt_value = SD_User_Time_Read(Mscnt_temp); + } + + if(SDMMC_GetPresentFlagStatus(card->SDHOSTx,(SDHOST_Data0LineLevelFlag | SDHOST_Data1LineLevelFlag | + SDHOST_Data2LineLevelFlag | SDHOST_Data3LineLevelFlag)) == SET) + { + status_temp = Status_Fail; + return status_temp; + } + + SDMMC_EnableVolSwitch(card->SDHOSTx,ENABLE); + /* delay 5ms */ + Mscnt_value = 0; + SD_SysTick_start_time(); + Mscnt_temp = SD_systick_timeoutms; + while(Mscnt_value<5) + { + Mscnt_value = SD_User_Time_Read(Mscnt_temp); + } + + if((card->SDHOSTx->CTRLSTS & SDHOST_CTRLSTS_V18SE) != SDHOST_CTRLSTS_V18SE) + { + status_temp = Status_Fail; + } + else + { + SDMMC_EnableSDCLK(card->SDHOSTx,ENABLE);; + /* Wait until the SD clock is stable. */ + SDMMC_WaitSDCLKStable(card->SDHOSTx); + + /* delay 1ms */ + Mscnt_value = 0; + SD_SysTick_start_time(); + Mscnt_temp = SD_systick_timeoutms; + while(Mscnt_value<1) + { + Mscnt_value = SD_User_Time_Read(Mscnt_temp); + } + + if(SDMMC_GetPresentFlagStatus(card->SDHOSTx,(SDHOST_Data0LineLevelFlag | SDHOST_Data1LineLevelFlag | + SDHOST_Data2LineLevelFlag | SDHOST_Data3LineLevelFlag)) != SET) + { + status_temp = Status_Fail; + } + } + } + return status_temp; +} + + +void sd_delay(uint32_t cnt) +{ + while(cnt--); +} + +static Status_card SD_SwitchFunction(sd_card_t *card,uint32_t mode) +{ + uint32_t card_scr[16]; + uint32_t cnt_value; + SDMMC_Transfer transfer; + Status_card status_temp = Status_Success; + + if(mode > 2) + { + mode = mode - 2; + } + + SDMMC_EnableFlagStatus(card->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,DISABLE); + + transfer.data.AutoCommand12_23 = NoAutoCommand; + transfer.data.enableIgnoreError = DISABLE; + transfer.data.dataType = SDHOST_TransferDataNormal; + transfer.data.blockCount = 1; + transfer.data.blockSize = 64; + transfer.data.rxData = card_scr; + transfer.data.txData = NULL; + + transfer.command.index = SD_Switch; + transfer.command.argument = (0x00fffff0U | mode); + transfer.command.type = CARD_CommandTypeNormal; + transfer.command.responseType = CARD_ResponseTypeR1; + transfer.command.flags = 0x00; + transfer.command.responseErrorFlags = 0x00; + + if(SDMMC_TransferBlocking(card->SDHOSTx,NULL,&transfer,&card->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + if(status_temp == Status_Success) + { + for(cnt_value = 0;cnt_value< 16; cnt_value++) + { + card_scr[cnt_value] = swap_uint32(card_scr[cnt_value]); + } + + /* -card_scr[0U]---bit511~bit480; + -card_scr[1U]---bit479~bit448; + -card_scr[2U]---bit447~bit416; + -card_scr[3U]---bit415~bit384; + -card_scr[4U]---bit383~bit352; + According to the "switch function status[bits 511~0]" return by switch command in mode "check function": + -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; + -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; + */ + if((((card_scr[3] >> 16) & (1 << mode)) == 0) || (((card_scr[4] & 0x0F000000) >> 24) != mode)) + { + status_temp = Status_CardNotSupportYet; + } + } + + if(status_temp == Status_Success) + { + transfer.command.argument = (0x80fffff0U | mode); + if(SDMMC_TransferBlocking(card->SDHOSTx,NULL,&transfer,&card->TMODE_truct) != SDMMC_SUCCESS) + { + status_temp = Status_Fail; + } + + if(status_temp == Status_Success) + { + for(cnt_value = 0;cnt_value< 16; cnt_value++) + { + card_scr[cnt_value] = swap_uint32(card_scr[cnt_value]); + } + + /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": + -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; + */ + if(((card_scr[4] & 0x0F000000) >> 24) != mode) + { + status_temp = Status_CardSwitchFailed; + } + } + } + + SDMMC_EnableFlagStatus(card->SDHOSTx,SDHOST_DataErrorFlag | SDHOST_CommandErrorFlag,ENABLE); + return status_temp; +} + + +Status_card SD_SelectBusTiming(sd_card_t *card) +{ + Status_card status_temp; + if((card->sd_card_information.version <= SD_SpecificationVersion1_0) || ((card->sd_card_information.csd.cardCommandClass & SD_CommandClassSwitch) != SD_CommandClassSwitch)) + { + status_temp = Status_CardNotSupportYet; + } + else + { + if((card->card_workmode.mode == SDMMC_DS) || (card->card_workmode.mode == SDMMC_HS)) + { + status_temp = SD_SwitchFunction(card,card->card_workmode.mode); + } + else + { + if((card->sd_card_information.flags & SD_SupportVoltage180v) != SD_SupportVoltage180v) + { + status_temp = Status_CardNotSupportYet; + } + else + { + status_temp = SD_SwitchFunction(card,card->card_workmode.mode); + } + } + } + return status_temp; +} + +/** Read User Time Since Last Set + * param last time. + */ +uint32_t SD_User_Time_Read(uint32_t time) +{ + if(SD_systick_timeoutms>=time) + { + return SD_systick_timeoutms-time; + } + return(0xFFFFFFFF-time+SD_systick_timeoutms); +} + +/** SD_SysTick_start_time. **/ +void SD_SysTick_start_time(void) +{ + SD_systick_timeoutms = 0; + +} + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/misc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/misc.h new file mode 100644 index 0000000000..f8a0da2208 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/misc.h @@ -0,0 +1,292 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file misc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __MISC_H__ +#define __MISC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** MISC Driving Functions Declaration **/ + +/** NVIC Init Structure definition **/ +typedef struct +{ + uint8_t NVIC_IRQChannel; /* Specifies the IRQ channel to be enabled or disabled. */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /* Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. */ + + uint8_t NVIC_IRQChannelSubPriority; /* Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. */ + + FunctionalState NVIC_IRQChannelCmd; /* Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. */ +} NVIC_InitType; + +#if (__MPU_PRESENT == 1) + +/** MPU Region initialization structure **/ +typedef struct +{ + uint8_t Enable; /* Specifies the status of the region. */ + uint8_t Number; /* Specifies the number of the region to protect. */ + uint32_t BaseAddress; /* Specifies the base address of the region to protect. */ + uint8_t Size; /* Specifies the size of the region to protect. */ + uint8_t SubRegionDisable; /* Specifies the number of the subregion protection to disable. */ + uint8_t TypeExtField; /* Specifies the TEX field level. */ + uint8_t AccessPermission; /* Specifies the region access permission type. */ + uint8_t DisableExec; /* Specifies the instruction access status. */ + uint8_t IsShareable; /* Specifies the shareability status of the protected region. */ + uint8_t IsCacheable; /* Specifies the cacheable status of the region protected. */ + uint8_t IsBufferable; /* Specifies the bufferable status of the protected region. */ +}MPU_Region_InitType; + + +/** CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000UL) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002UL) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004UL) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006UL) + + +/** CORTEX_MPU_Region_Enable CORTEX MPU Region Enable */ +#define MPU_REGION_ENABLE ((uint8_t)0x01u) +#define MPU_REGION_DISABLE ((uint8_t)0x00u) + +/** CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00u) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01u) + + +/** CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01u) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00u) + +/** CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01u) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00u) + + +/** CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01u) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00u) + +/** CORTEX_MPU_TEX_Levels MPU TEX Levels */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00u) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01u) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02u) + +/** CORTEX_MPU_Region_Size CORTEX MPU Region Size */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04u) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05u) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06u) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07u) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08u) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09u) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0Au) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0Bu) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0Cu) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0Du) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0Eu) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0Fu) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10u) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11u) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12u) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13u) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14u) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15u) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16u) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17u) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18u) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19u) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1Au) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1Bu) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1Cu) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1Du) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1Eu) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1Fu) + + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00u) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01u) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02u) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03u) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05u) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06u) + + +/**CORTEX_MPU_Region_Number CORTEX MPU Region Number */ + +#define MPU_REGION_NUMBER0 ((uint8_t)0x00u) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01u) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02u) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03u) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04u) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05u) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06u) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07u) +#if !defined(CORE_CM4) +#define MPU_REGION_NUMBER8 ((uint8_t)0x08u) +#define MPU_REGION_NUMBER9 ((uint8_t)0x09u) +#define MPU_REGION_NUMBER10 ((uint8_t)0x0Au) +#define MPU_REGION_NUMBER11 ((uint8_t)0x0Bu) +#define MPU_REGION_NUMBER12 ((uint8_t)0x0Cu) +#define MPU_REGION_NUMBER13 ((uint8_t)0x0Du) +#define MPU_REGION_NUMBER14 ((uint8_t)0x0Eu) +#define MPU_REGION_NUMBER15 ((uint8_t)0x0Fu) +#endif /* !defined(CORE_CM4) */ + + +#endif /* __MPU_PRESENT */ + + + +/** MISC driver modules **/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U) /* access key */ + +/** Vector_Table_Base **/ +#define NVIC_VectTab_RAM ((uint32_t)0x20000000U) /* RAM start address*/ +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000U) /* FLASH start address*/ + +/** LowPowerMode **/ +#define NVIC_LP_SEVONPEND (SCB_SCR_SEVONPEND) +#define NVIC_LP_SLEEPDEEP (SCB_SCR_SLEEPDEEP) +#define NVIC_LP_SLEEPONEXIT (SCB_SCR_SLEEPONEXIT) + +/** Preemption_Sub_Priority_Group **/ +#define NVIC_PriorityGroup_0 (SCB_AIRCR_PRIGROUP7) /* 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 (SCB_AIRCR_PRIGROUP6) /* 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 (SCB_AIRCR_PRIGROUP5) /* 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 (SCB_AIRCR_PRIGROUP4) /* 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 (SCB_AIRCR_PRIGROUP3) /* 4 bits for pre-emption priority 0 bits for subpriority */ + +/** Preemption_Priority_Group **/ +#define NVIC_PRE_PRIORITY_0 ((uint8_t)0x00U) +#define NVIC_PRE_PRIORITY_1 ((uint8_t)0x01U) +#define NVIC_PRE_PRIORITY_2 ((uint8_t)0x02U) +#define NVIC_PRE_PRIORITY_3 ((uint8_t)0x03U) +#define NVIC_PRE_PRIORITY_4 ((uint8_t)0x04U) +#define NVIC_PRE_PRIORITY_5 ((uint8_t)0x05U) +#define NVIC_PRE_PRIORITY_6 ((uint8_t)0x06U) +#define NVIC_PRE_PRIORITY_7 ((uint8_t)0x07U) +#define NVIC_PRE_PRIORITY_8 ((uint8_t)0x08U) +#define NVIC_PRE_PRIORITY_9 ((uint8_t)0x09U) +#define NVIC_PRE_PRIORITY_10 ((uint8_t)0x0AU) +#define NVIC_PRE_PRIORITY_11 ((uint8_t)0x0BU) +#define NVIC_PRE_PRIORITY_12 ((uint8_t)0x0CU) +#define NVIC_PRE_PRIORITY_13 ((uint8_t)0x0DU) +#define NVIC_PRE_PRIORITY_14 ((uint8_t)0x0EU) +#define NVIC_PRE_PRIORITY_15 ((uint8_t)0x0FU) + +/** Sub_Priority_Group **/ +#define NVIC_SUB_PRIORITY_0 ((uint8_t)0x00U) +#define NVIC_SUB_PRIORITY_1 ((uint8_t)0x01U) +#define NVIC_SUB_PRIORITY_2 ((uint8_t)0x02U) +#define NVIC_SUB_PRIORITY_3 ((uint8_t)0x03U) +#define NVIC_SUB_PRIORITY_4 ((uint8_t)0x04U) +#define NVIC_SUB_PRIORITY_5 ((uint8_t)0x05U) +#define NVIC_SUB_PRIORITY_6 ((uint8_t)0x06U) +#define NVIC_SUB_PRIORITY_7 ((uint8_t)0x07U) +#define NVIC_SUB_PRIORITY_8 ((uint8_t)0x08U) +#define NVIC_SUB_PRIORITY_9 ((uint8_t)0x09U) +#define NVIC_SUB_PRIORITY_10 ((uint8_t)0x0AU) +#define NVIC_SUB_PRIORITY_11 ((uint8_t)0x0BU) +#define NVIC_SUB_PRIORITY_12 ((uint8_t)0x0CU) +#define NVIC_SUB_PRIORITY_13 ((uint8_t)0x0DU) +#define NVIC_SUB_PRIORITY_14 ((uint8_t)0x0EU) +#define NVIC_SUB_PRIORITY_15 ((uint8_t)0x0FU) + +#define CM7_CPU ((uint32_t)0x00000002) + +#define VECT_SIZE ((uint32_t)0x400U) + +#if defined(DUAL_CORE) +#define CM4_CPU ((uint32_t)0x00000001) +#endif /*DUAL_CORE*/ + +/** SysTick_CLKSource **/ +#define SysTick_CLKSource_HCLK_Div8 (~SysTick_CTRL_CLKSOURCE) +#define SysTick_CLKSource_HCLK (SysTick_CTRL_CLKSOURCE) + + +#if (__MPU_PRESENT == 1) + +void MPU_Disable(void); +void MPU_Enable(uint32_t MPU_Control); +void MPU_ConfigRegion(MPU_Region_InitType *MPU_Init); + +#endif /*__MPU_PRESENT == 1*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitType* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +void CopyVectTable(uint32_t SrcAddr, uint32_t DesAddr, uint32_t size); +uint32_t Get_CurrentCPU(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_adc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_adc.h new file mode 100644 index 0000000000..a52fb404ef --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_adc.h @@ -0,0 +1,733 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_adc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_ADC_H__ +#define __N32H76X_78X_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" +#include + + + +/** ADC_Exported_Types **/ + + +/** ADC Init structure definition **/ +typedef struct +{ + uint32_t WorkMode; /* Configures the ADC to operate in independent or dual mode.*/ + + FunctionalState MultiChEn; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. */ + + FunctionalState ContinueConvEn; /* Specifies whether the conversion is performed in + Continuous or Single mode. */ + uint32_t ExtTrigSelect; /*Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral */ + + uint32_t DataTransferMode; /*Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA or DFSDM.*/ + + uint32_t DatAlign; /* Set ADC conversion data alignment.*/ + + uint8_t ChsNumber; /* Set ADC group regular sequencer length*/ + + uint32_t Resolution; /* Set ADC resolution*/ + +} ADC_InitType; + +/** ADC offset structure definition **/ +typedef struct +{ + FunctionalState OffsetEn; /* Set Offset enable or disable*/ + FunctionalState OffsetSatenEn; /* Set Offset satera*/ + FunctionalState OffsetDirPositiveEn; + uint8_t OffsetChannel; + uint16_t OffsetData; +} ADC_OffsetType; + + +typedef enum +{ + ADC_CTRL3_CKMOD_AHB = 0, + ADC_CTRL3_CKMOD_PLL = 1, +} ADC_CTRL3_CKMOD; + +typedef enum +{ + ADC_AWDG1 = 0, + ADC_AWDG2 = 1, + ADC_AWDG3 = 2, +} ADC_AWDG; + + /** Multimode - Delay between two sampling phases **/ +#define ADC_ADC_MULTI_TWOSMP_DELAY_MASK (ADC_DLYSMP_INTLEADVAL) +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_1 ((uint32_t)0x00000000U << 28U) /**1 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_2 ((uint32_t)0x00000001U << 28U) /**2 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_3 ((uint32_t)0x00000002U << 28U) /**3 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_4 ((uint32_t)0x00000003U << 28U) /**4 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_5 ((uint32_t)0x00000004U << 28U) /**5 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_6 ((uint32_t)0x00000005U << 28U) /**6 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_7 ((uint32_t)0x00000006U << 28U) /**7 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_8 ((uint32_t)0x00000007U << 28U) /**8 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_9 ((uint32_t)0x00000008U << 28U) /**9 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_10 ((uint32_t)0x00000009U << 28U) /**0 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_11 ((uint32_t)0x0000000AU << 28U) /**11 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_12 ((uint32_t)0x0000000BU << 28U) /**12 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_13 ((uint32_t)0x0000000CU << 28U) /**13 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_14 ((uint32_t)0x0000000DU << 28U) /**14 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_15 ((uint32_t)0x0000000EU << 28U) /**15 ADC clock cycle */ +#define ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_16 ((uint32_t)0x0000000FU << 28U) /**16 ADC clock cycle */ + + + /** Indenpent mode - Delay between two sampling phases **/ +#define ADC_INDENPENT_TWOSMP_DELAY_EN_MASK (ADC_DLYSMP_DLYSAMPEN) + +#define ADC_INDENPENT_TWOSMP_DELAY_MASK (ADC_DLYSMP_DLYVAL | ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_1 (((uint32_t)0x00000000U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**1 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_2 (((uint32_t)0x00000001U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**2 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_3 (((uint32_t)0x00000002U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**3 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_4 (((uint32_t)0x00000003U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**4 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_5 (((uint32_t)0x00000004U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**5 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_6 (((uint32_t)0x00000005U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**6 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_7 (((uint32_t)0x00000006U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**7 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_8 (((uint32_t)0x00000007U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**8 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_9 (((uint32_t)0x00000008U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**9 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_10 (((uint32_t)0x00000009U << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**10 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_11 (((uint32_t)0x0000000AU << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**11 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_12 (((uint32_t)0x0000000BU << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**12 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_13 (((uint32_t)0x0000000CU << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**13 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_14 (((uint32_t)0x0000000DU << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**14 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_15 (((uint32_t)0x0000000EU << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**15 ADC clock cycle */ +#define ADC_INDENPENT_TWOSMP_DELAY_CYCLE_16 (((uint32_t)0x0000000FU << 24U)|ADC_INDENPENT_TWOSMP_DELAY_EN_MASK) /**16 ADC clock cycle */ + +/** ADC_muli_mode ,including dual-ADC mode and tripple-ADC mode **/ +#define ADC_WORKMODE_MULT_MASK (ADC_CTRL1_MULTMODE) +#define ADC_WORKMODE_INDEPENDENT ((uint32_t)0x00000000U << 11U) +/** Dual-ADC mode **/ +#define ADC_WORKMODE_DUAL_REG_INJECT_SIMULT ((uint32_t)0x00000001U << 11U) +#define ADC_WORKMODE_DUAL_REG_SIMULT_ALTER_TRIG ((uint32_t)0x00000002U << 11U) +#define ADC_WORKMODE_DUAL_INJ_SIMULT_INTERL ((uint32_t)0x00000003U << 11U) +#define ADC_WORKMODE_DUAL_INJ_SIMULT ((uint32_t)0x00000005U << 11U) +#define ADC_WORKMODE_DUAL_REG_SIMULT ((uint32_t)0x00000006U << 11U) +#define ADC_WORKMODE_DUAL_INTERL ((uint32_t)0x00000007U << 11U) +#define ADC_WORKMODE_DUAL_ALTER_TRIG ((uint32_t)0x00000009U << 11U) +/** Tripple-ADC mode **/ +#define ADC_WORKMODE_TRIPPLE_REG_INJECT_SIMULT ((uint32_t)0x00000011U << 11U) +#define ADC_WORKMODE_TRIPPLE_REG_SIMULT_ALTER_TRIG ((uint32_t)0x00000012U << 11U) +#define ADC_WORKMODE_TRIPPLE_INJ_SIMULT_INTERL ((uint32_t)0x00000013U << 11U) +#define ADC_WORKMODE_TRIPPLE_INJ_SIMULT ((uint32_t)0x00000015U << 11U) +#define ADC_WORKMODE_TRIPPLE_REG_SIMULT ((uint32_t)0x00000016U << 11U) +#define ADC_WORKMODE_TRIPPLE_INTERL ((uint32_t)0x00000017U << 11U) +#define ADC_WORKMODE_TRIPPLE_ALTER_TRIG ((uint32_t)0x00000019U << 11U) + + +/** ADC CTRL1 MASK **/ +#define ADC_SCANMD_EN_MASK (ADC_CTRL1_SCANMD) /* Muti-channels enable mask */ +#define ADC_JAUTO_EN_MASK (ADC_CTRL1_AUTOJC) /* Automatic injected group conversion enable mask */ + +#define ADC_DISC_REG_EN_MASK (ADC_CTRL1_DREGCH) /* ADC Discontinous mode enable on regluar channels mask */ +#define ADC_DISC_INJ_EN_MASK (ADC_CTRL1_DJCH) /* ADC Discontinous mode enable on injected channels mask */ + +#define ADC_DISC_NUM_MASK (ADC_CTRL1_DCTU) /* ADC Discontinuous mode channel count */ +/** ADC_channels_definition **/ +#define ADC_CH_MASK (ADC_CTRL1_AWD1CH) +#define ADC_CH_0 ((uint8_t)0x00U) +#define ADC_CH_1 ((uint8_t)0x01U) +#define ADC_CH_2 ((uint8_t)0x02U) +#define ADC_CH_3 ((uint8_t)0x03U) +#define ADC_CH_4 ((uint8_t)0x04U) +#define ADC_CH_5 ((uint8_t)0x05U) +#define ADC_CH_6 ((uint8_t)0x06U) +#define ADC_CH_7 ((uint8_t)0x07U) +#define ADC_CH_8 ((uint8_t)0x08U) +#define ADC_CH_9 ((uint8_t)0x09U) +#define ADC_CH_10 ((uint8_t)0x0AU) +#define ADC_CH_11 ((uint8_t)0x0BU) +#define ADC_CH_12 ((uint8_t)0x0CU) +#define ADC_CH_13 ((uint8_t)0x0DU) +#define ADC_CH_14 ((uint8_t)0x0EU) +#define ADC_CH_15 ((uint8_t)0x0FU) +#define ADC_CH_16 ((uint8_t)0x10U) +#define ADC_CH_17 ((uint8_t)0x11U) +#define ADC_CH_18 ((uint8_t)0x12U) +#define ADC_CH_19 ((uint8_t)0x13U) + +/** ADC_analog_watchdog_channels_Mask_definition **/ +#define ADC_AWD1CH_MASK (ADC_CTRL1_AWD1CH) + +/** ADC_analog_watchdog_selection **/ +#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE (ADC_CTRL1_AWD1SGLEN | ADC_CTRL1_AWD1ERCH) +#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE (ADC_CTRL1_AWD1SGLEN | ADC_CTRL1_AWD1EJCH) +#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE (ADC_CTRL1_AWD1SGLEN | ADC_CTRL1_AWD1ERCH | ADC_CTRL1_AWD1EJCH) +#define ADC_ANALOG_WTDG_ALLREG_ENABLE (ADC_CTRL1_AWD1ERCH) +#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE (ADC_CTRL1_AWD1EJCH) +#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE (ADC_CTRL1_AWD1ERCH | ADC_CTRL1_AWD1EJCH) +#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000U) + +/** ADC CTRL2 MASK **/ +#define ADC_ON_EN_MASK (ADC_CTRL2_ON) /* ADC enable mask */ +#define ADC_CONT_EN_MASK (ADC_CTRL2_CTU) /* ADC continuous conversion mask */ +#define ADC_CALI_EN_MASK (ADC_CTRL2_ENCAL) /* A/D start calibration mask */ +#define ADC_MUTI_ADC_DSMU_MASK (ADC_CTRL2_MDSMU) /* Multi-adc DSMU mode mask */ + +/** ADC_Regular_Group_Trigger_Edge_Configuration **/ +#define ADC_REG_TRIG_EXT_MASK (ADC_CTRL2_EXTPRSEL) +#define ADC_REG_TRIG_EXT_SOFTWARE ((uint32_t)0x00000000U) +#define ADC_REG_TRIG_EXT_RISING (ADC_CTRL2_EXTPRSEL_0) /* rising edge */ +#define ADC_REG_TRIG_EXT_FALLING (ADC_CTRL2_EXTPRSEL_1) /* falling edge */ +#define ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CTRL2_EXTPRSEL_1 | ADC_CTRL2_EXTPRSEL_0) /* rising and falling edges */ + +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_REG_TRIG_EXT_RISING) /* default trigger rising edge */ +/** ADC_Injected_Group_Trigger_Edge_Configuration **/ +#define ADC_INJ_TRIG_EXT_MASK (ADC_CTRL2_EXTPJSEL) +#define ADC_INJ_TRIG_EXT_SOFTWARE ((uint32_t)0x00000000U) +#define ADC_INJ_TRIG_EXT_RISING (ADC_CTRL2_EXTPJSEL_0) /* rising edge */ +#define ADC_INJ_TRIG_EXT_FALLING (ADC_CTRL2_EXTPJSEL_1) /* falling edge */ +#define ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CTRL2_EXTPJSEL_1 | ADC_CTRL2_EXTPJSEL_0) /* rising and falling edges */ + +#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_INJ_TRIG_EXT_RISING) /* default trigger rising edge */ + +/** ADC_external_trigger_sources_for_injected_channels_conversion **/ +#define ADC_EXT_TRIG_INJ_CONV_MASK (ADC_CTRL2_EXTJSEL | ADC_INJ_TRIG_EXT_MASK) +#define ADC_EXT_TRIG_INJ_CONV_ATIM1_CC1 (((uint32_t)0x00000000U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM1_CC2 (((uint32_t)0x00000001U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM1_CC3 (((uint32_t)0x00000002U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM1_CC4 (((uint32_t)0x00000003U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM1_TRGO (((uint32_t)0x00000004U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM2_CC1 (((uint32_t)0x00000005U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM2_CC2 (((uint32_t)0x00000006U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM2_CC3 (((uint32_t)0x00000007U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM1_TRGO2 (((uint32_t)0x00000008U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM2_TRGO (((uint32_t)0x00000009U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM3_CC1 (((uint32_t)0x0000000AU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM3_CC2 (((uint32_t)0x0000000BU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM3_CC3 (((uint32_t)0x0000000CU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM3_CC4 (((uint32_t)0x0000000DU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM2_TRGO2 (((uint32_t)0x0000000EU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM3_TRGO (((uint32_t)0x0000000FU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM4_TRGO2 (((uint32_t)0x00000010U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM3_TRGO2 (((uint32_t)0x00000011U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_ATIM4_TRGO (((uint32_t)0x00000012U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMB1_TRGO (((uint32_t)0x00000013U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMB2_TRGO (((uint32_t)0x00000014U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMB3_TRGO (((uint32_t)0x00000015U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMA1_TRGO (((uint32_t)0x00000016U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMB1_CC1 (((uint32_t)0x00000017U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMB2_CC4 (((uint32_t)0x00000018U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMB3_CC1 (((uint32_t)0x00000019U << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_GTIMA1_CC3 (((uint32_t)0x0000001AU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_SHRTIM1_TRGO2 (((uint32_t)0x0000001BU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_SHRTIM1_TRGO4 (((uint32_t)0x0000001CU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_SHRTIM2_TRGO2 (((uint32_t)0x0000001DU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_SHRTIM2_TRGO4 (((uint32_t)0x0000001EU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_EXT_INT0_15 (((uint32_t)0x0000001FU << 13U) | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_INJ_CONV_SOFTWARE (((uint32_t)0x00000000U << 13U)) + +/** ADC_external_trigger_sources_for_regular_channels_conversion **/ +#define ADC_EXT_TRIG_REG_CONV_MASK (ADC_CTRL2_EXTRSEL | ADC_REG_TRIG_EXT_MASK) +#define ADC_EXT_TRIG_REG_CONV_ATIM1_CC1 (((uint32_t)0x00000000U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM1_CC2 (((uint32_t)0x00000001U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM1_CC3 (((uint32_t)0x00000002U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM1_CC4 (((uint32_t)0x00000003U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM1_TRGO (((uint32_t)0x00000004U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM2_CC1 (((uint32_t)0x00000005U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM2_CC2 (((uint32_t)0x00000006U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM2_CC3 (((uint32_t)0x00000007U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM1_TRGO2 (((uint32_t)0x00000008U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM2_TRGO (((uint32_t)0x00000009U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM3_CC1 (((uint32_t)0x0000000AU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM3_CC2 (((uint32_t)0x0000000BU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM3_CC3 (((uint32_t)0x0000000CU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM3_CC4 (((uint32_t)0x0000000DU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM2_TRGO2 (((uint32_t)0x0000000EU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM3_TRGO (((uint32_t)0x0000000FU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM4_TRGO2 (((uint32_t)0x00000010U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM3_TRGO2 (((uint32_t)0x00000011U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_ATIM4_TRGO (((uint32_t)0x00000012U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMB1_TRGO (((uint32_t)0x00000013U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMB2_TRGO (((uint32_t)0x00000014U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMB3_TRGO (((uint32_t)0x00000015U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMA1_TRGO (((uint32_t)0x00000016U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMB1_CC2 (((uint32_t)0x00000017U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMB2_CC4 (((uint32_t)0x00000018U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMB3_CC2 (((uint32_t)0x00000019U << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_GTIMA1_CC4 (((uint32_t)0x0000001AU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_SHRTIM1_TRGO1 (((uint32_t)0x0000001BU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_SHRTIM1_TRGO3 (((uint32_t)0x0000001CU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_SHRTIM2_TRGO1 (((uint32_t)0x0000001DU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_SHRTIM2_TRGO3 (((uint32_t)0x0000001EU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_EXT_INT0_15 (((uint32_t)0x0000001FU << 24U) | ADC_REG_TRIG_EXT_EDGE_DEFAULT) +#define ADC_EXT_TRIG_REG_CONV_SOFTWARE (((uint32_t)0x00000000U << 24U)) + +/** ADC DMA Mode **/ +#define ADC_MULTI_REG_DMA_MODE_MASK (ADC_CTRL2_DMAMD) +#define ADC_MULTI_REG_DMA_DISABLE (0x00000000UL) +#define ADC_MULTI_REG_DMA_EACH_ADC (ADC_CTRL2_DMAMD_0) /* each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CTRL2_DMAMD_1) /* one DMA channel for muti ADC (DMA of ADC master). Setting for ADC resolution of 12 and 10 bits */ + +/** ADC_data_align **/ +#define ADC_DAT_ALIGN_MASK (ADC_CTRL2_ALIG) +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000U) +#define ADC_DAT_ALIGN_L (ADC_CTRL2_ALIG) + +#define ADC_TS_EN_MASK (ADC_CTRL2_TEMPEN) /** ADC temper sensor enable **/ +#define ADC_VREFINT_EN_MASK (ADC_CTRL3_VREFINTEN) /** ADC vreint enable **/ +#define ADC_INJ_SWSTART_MASK (ADC_CTRL2_SWSTRJCH)/** Start conversion of injected channels **/ +#define ADC_REG_SWSTART_MASK (ADC_CTRL2_SWSTRRCH)/** Start conversion of regular channels **/ + +/** DataTransferMode **/ +#define ADC_DATA_TRANS_Mode_MASK (ADC_CTRL2_DMNGT | ADC_CTRL2_MDSMU ) +#define ADC_REG_DR_TRANSFER (0x00000000U ) /** ADC conversions are transferred to DR rigister **/ +#define ADC_REG_DSMU_TRANSFER (ADC_CTRL2_DMNGT_1) /** ADC conversion data are transferred to DSMU ,using for single-ADC**/ +#define ADC_REG_MUTI_DSMU_TRANSFER (ADC_CTRL2_DMNGT_1 | ADC_CTRL2_MDSMU) /** ADC conversion data are transferred to DSMU ,using for muti-ADC**/ +#define ADC_REG_DMA_TRANSFER (ADC_CTRL2_DMNGT_1 | ADC_CTRL2_DMNGT_0)/** ADC conversion data are transferred by DMA **/ + +/** ADC CTRL3 MASK **/ +#define ADC_DATA_RES_MASK (ADC_CTRL3_RES) +#define ADC_DATA_RES_10BIT (~ADC_DATA_RES_MASK) +#define ADC_DATA_RES_12BIT (ADC_DATA_RES_MASK) + +#define ADC_CAL_DIFF_MODE_MASK (ADC_CTRL3_CALDIF) /** ADC differential mode bit mask **/ +#define ADC_CAL_AUTO_LOAD_MASK (ADC_CTRL3_CALALD) /** ADC auto calibration bit mask **/ +#define ADC_CLOCK_MODE_MASK (ADC_CTRL3_CLOCKMOD) /** ADC clock mode bit mask **/ +#define ADC_BYPASS_CAL_MASK (ADC_CTRL3_BPCAL) /** ADC bypass calibration mode bit mask **/ +#define ADC_VOLT_MONITOR_EN_MASK (ADC_CTRL3_VBATMEN)/** ADCVbat monitor enable bit mask **/ + +#define ADC_GAIN_COMPENSATION_MODE_MASK (ADC_CTRL3_GCOMPEN | ADC_CTRL3_GCOMP_SATEN) +#define ADC_GAIN_COMPENSATION_MODE0 (ADC_CTRL3_GCOMPEN) /** ADC gain compensation enable and the Saturation range is max 0x0-0xFFFU **/ +#define ADC_GAIN_COMPENSATION_MODE1 (ADC_CTRL3_GCOMPEN | ADC_CTRL3_GCOMP_SATEN) /** ADC gain compensation enable and the Saturation range is max 0x0-0x3FFFU **/ + +#define ADC_GAIN_COMPENSATION_VALUE_MASK (ADC_GCOMP_GCOMPDAT) + +#define ADC_INJ_SWSTOP_MASK (ADC_CTRL3_SWJSTOP) /** Stop conversion of injected channels **/ +#define ADC_REG_SWSTOP_MASK (ADC_CTRL3_SWRSTOP) /** Stop conversion of regular channels **/ +#define ADC_INJ_START_MASK (ADC_CTRL3_JSTART ) /** Start conversion of injected channels **/ +#define ADC_REG_START_MASK (ADC_CTRL3_RSTART ) /** Start conversion of regular channels **/ + +#define ADC_CLOCK_MODE_PLL (ADC_CLOCK_MODE_MASK) +#define ADC_CLOCK_MODE_AHB (~ADC_CLOCK_MODE_MASK) + +#define ADC_OVERSAMPE_RATE_TIMES_MASK (ADC_OSCFG_OSR) /**ADC oversampling ratio times bit mask **/ +#define ADC_OVERSAMPE_RATE_TIMES_1 (((uint32_t)0x00000000U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_2 (((uint32_t)0x00000001U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_4 (((uint32_t)0x00000002U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_8 (((uint32_t)0x00000003U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_16 (((uint32_t)0x00000004U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_32 (((uint32_t)0x00000005U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_64 (((uint32_t)0x00000006U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_128 (((uint32_t)0x00000007U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_256 (((uint32_t)0x00000008U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_512 (((uint32_t)0x00000009U) << 14) +#define ADC_OVERSAMPE_RATE_TIMES_1024 (((uint32_t)0x0000000AU) << 14) + +#define ADC_OVERSAMPE_DATA_SHIFT_MASK (ADC_OSCFG_OSS) /**ADC oversampling data right shift bit mask **/ +#define ADC_OVERSAMPE_DATA_SHIFT_0 (((uint32_t)0x00000000U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_1 (((uint32_t)0x00000001U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_2 (((uint32_t)0x00000002U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_3 (((uint32_t)0x00000003U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_4 (((uint32_t)0x00000004U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_5 (((uint32_t)0x00000005U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_6 (((uint32_t)0x00000006U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_7 (((uint32_t)0x00000007U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_8 (((uint32_t)0x00000008U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_9 (((uint32_t)0x00000009U) << 18) +#define ADC_OVERSAMPE_DATA_SHIFT_10 (((uint32_t)0x0000000AU) << 18) + +#define ADC_OVERSAMPE_REG_EN_MASK (ADC_OSCFG_OSRE) /**ADC oversampling on regular channels **/ +#define ADC_OVERSAMPE_INJ_EN_MASK (ADC_OSCFG_OSJE) /**ADC oversampling on injected channels **/ +#define ADC_OVERSAMPE_TRIG_REG_MASK (ADC_OSCFG_OSRTRIG) /**ADC oversampling trigger mode on regular channels **/ +#define ADC_OVERSAMPE_MODE_MASK (ADC_OSCFG_OSRMD) /**ADC oversampling mode on regular channels **/ +/**Oversample scope **/ +#define ADC_OVERSAMPE_DISABLE ((uint32_t)0x00000000U) +#define ADC_OVERSAMPE_REGULAR_CONTINUED (ADC_OVERSAMPE_REG_EN_MASK) +#define ADC_OVERSAMPE_REGULAR_RESUMED (ADC_OVERSAMPE_MODE_MASK | ADC_OVERSAMPE_REG_EN_MASK) +#define ADC_OVERSAMPE_INJECTED (ADC_OVERSAMPE_INJ_EN_MASK) +#define ADC_OVERSAMPE_REGULAR_INJECTED (ADC_OVERSAMPE_REG_EN_MASK | ADC_OVERSAMPE_INJ_EN_MASK) + +/** ADC_sampling_time **/ +#define ADC_SAMP_TIME_CYCLES_MASK (ADC_SAMPT1_SAMP0) +#define ADC_SAMP_TIME_CYCLES_1 ((uint8_t)0x00U) +#define ADC_SAMP_TIME_CYCLES_2 ((uint8_t)0x01U) +#define ADC_SAMP_TIME_CYCLES_3 ((uint8_t)0x02U) +#define ADC_SAMP_TIME_CYCLES_4 ((uint8_t)0x03U) +#define ADC_SAMP_TIME_CYCLES_5 ((uint8_t)0x04U) +#define ADC_SAMP_TIME_CYCLES_6 ((uint8_t)0x05U) +#define ADC_SAMP_TIME_CYCLES_7 ((uint8_t)0x06U) +#define ADC_SAMP_TIME_CYCLES_10 ((uint8_t)0x07U) +#define ADC_SAMP_TIME_CYCLES_13 ((uint8_t)0x08U) +#define ADC_SAMP_TIME_CYCLES_17 ((uint8_t)0x09U) +#define ADC_SAMP_TIME_CYCLES_24 ((uint8_t)0x0AU) +#define ADC_SAMP_TIME_CYCLES_32 ((uint8_t)0x0BU) +#define ADC_SAMP_TIME_CYCLES_83 ((uint8_t)0x0CU) +#define ADC_SAMP_TIME_CYCLES_93 ((uint8_t)0x0DU) +#define ADC_SAMP_TIME_CYCLES_215 ((uint8_t)0x0EU) +#define ADC_SAMP_TIME_CYCLES_397 ((uint8_t)0x0FU) + + +/** ADC_offset_channel_offset **/ +#define ADC_REGESTER_OFFSET_1 ((uint8_t)0x24U) +#define ADC_REGESTER_OFFSET_2 ((uint8_t)0x28U) +#define ADC_REGESTER_OFFSET_3 ((uint8_t)0x2CU) +#define ADC_REGESTER_OFFSET_4 ((uint8_t)0x30U) + +#define ADC_OFFSET_EN_MASK (ADC_OFFSET1_OFFSCH1EN) +#define ADC_OFFSET_CH_MASK (ADC_OFFSET1_OFFSCH1CH) +#define ADC_OFFSET_SATEN_EN_MASK (ADC_OFFSET1_OFFSCH1SATEN) +#define ADC_OFFSET_DIR_MASK (ADC_OFFSET1_OFFSCH1DIR) +#define ADC_OFFSET_DATA_MASK (ADC_OFFSET1_OFFSCH1DAT) + +/** AWDG 1 Filtering Definition **/ +#define ADC_AWDG1_FILTERING_MASK (ADC_AWD1LOW_AWDFIL) +#define ADC_AWDG1_FILTERING_NONE (0x00000000U) +#define ADC_AWDG1_FILTERING_2SAMPLES (ADC_AWD1LOW_AWDFIL_0) +#define ADC_AWDG1_FILTERING_3SAMPLES (ADC_AWD1LOW_AWDFIL_1) +#define ADC_AWDG1_FILTERING_4SAMPLES (ADC_AWD1LOW_AWDFIL_1 | ADC_AWD1LOW_AWDFIL_0) +#define ADC_AWDG1_FILTERING_5SAMPLES (ADC_AWD1LOW_AWDFIL_2) +#define ADC_AWDG1_FILTERING_6SAMPLES (ADC_AWD1LOW_AWDFIL_2 | ADC_AWD1LOW_AWDFIL_0) +#define ADC_AWDG1_FILTERING_7SAMPLES (ADC_AWD1LOW_AWDFIL_2 | ADC_AWD1LOW_AWDFIL_1) +#define ADC_AWDG1_FILTERING_8SAMPLES (ADC_AWD1LOW_AWDFIL_2 | ADC_AWD1LOW_AWDFIL_1 | ADC_AWD1LOW_AWDFIL_0) + +/** AWDG 2/3 Enable Definition **/ +#define ADC_AWDG2_EN_OFFSET ((uint8_t)0x4CU) +#define ADC_AWDG3_EN_OFFSET ((uint8_t)0x50U) +#define ADC_AWDG23_EN_MASK (ADC_AWD2EN_AWD2EN) +/** AWDG 2/3 Interrupt Enable Definition **/ +#define ADC_AWDG2_INTEN_OFFSET ((uint8_t)0x54U) +#define ADC_AWDG3_INTEN_OFFSET ((uint8_t)0x58U) +#define ADC_AWDG23_INTEN_MASK (ADC_AWD2INTEN) +/** AWDG 2/3 Status Definition **/ +#define ADC_AWDG2_STS_OFFSET ((uint8_t)0x5CU) +#define ADC_AWDG3_STS_OFFSET ((uint8_t)0x60U) +#define ADC_AWDG23_STATUS_MASK (ADC_AWD2STS) + +/** ADC regular sequence **/ +#define ADC_RESQ_SEQ_MASK (ADC_RSEQ4_SEQ1) + + +/** ADC inject sequence **/ +#define ADC_JESQ_LEN_MASK (ADC_JSEQ_JLEN) +#define ADC_JESQ_SEQ_MASK (ADC_JSEQ_JSEQ1) + + +#define ADC_INJECT_DATA_OFFSET_1 ((uint8_t)0x78U) +#define ADC_INJECT_DATA_OFFSET_2 ((uint8_t)0x7CU) +#define ADC_INJECT_DATA_OFFSET_3 ((uint8_t)0x80U) +#define ADC_INJECT_DATA_OFFSET_4 ((uint8_t)0x84U) + + + +/** ADC_flags_definition **/ +#define ADC_FLAG_ALL_MASK (ADC_STS_ALL) +#define ADC_FLAG_ENDC (ADC_STS_ENDC) +#define ADC_FLAG_EOC_ANY (ADC_STS_ENDCA) +#define ADC_FLAG_JSTR (ADC_STS_JSTR) +#define ADC_FLAG_JENDC (ADC_STS_JENDC) +#define ADC_FLAG_JEOC_ANY (ADC_STS_JENDCA) +#define ADC_FLAG_STR (ADC_STS_STR) +#define ADC_FLAG_AWDG1 (ADC_STS_AWDG1) +#define ADC_FLAG_RDY (ADC_STS_RDY) +#define ADC_FLAG_PDRDY (ADC_STS_PDRDY) +#define ADC_FLAG_EOSAMP (ADC_STS_EOSAMP) +#define ADC_FLAG_ROSOVF (ADC_STS_ROSOVF) +#define ADC_FLAG_JOSOVF (ADC_STS_JOSOVF) +#define ADC_FLAG_ROSOVFDSMU (ADC_STS_ROSOVFDSMU) +#define ADC_FLAG_REFLAG (ADC_STS_REFLAG) +#define ADC_FLAG_WEFLAG (ADC_STS_WEFLAG) + + +/** ADC_FIFO_flags_definition **/ +#define ADC_FIFO_FLAG_FULL ((uint16_t)ADC_FIFOSTS_FFLAG) +#define ADC_FIFO_FLAG_EMPTY ((uint16_t)ADC_FIFOSTS_EFLAG) +#define ADC_FIFO_FLAG_HALF_FULL ((uint16_t)ADC_FIFOSTS_HFFLAG) +#define ADC_FIFO_FLAG_NOT_EMPTY ((uint16_t)ADC_FIFOSTS_NEFLAG) + +/** ADC_FIFO_Invailed_Data_definition **/ +#define ADC_FIFO_INVALIED_DATA_COUNT_MASK (ADC_FIFOSTS_DATCNT) + +/** ADC_FIFO_CFG_definition **/ +#define ADC_FIFO_EN_MASK (ADC_FIFOCFG_EN) +#define ADC_FIFO_CLR_MASK (ADC_FIFOCFG_CLR) +#define ADC_FIFO_WATER_LEVEL_MASK (ADC_FIFOCFG_WL) + +/** ADC_FIFO_INTEN_definition **/ +#define ADC_FIFO_INT_FULL ((uint16_t)ADC_FIFOCFG_FINTEN) +#define ADC_FIFO_INT_EMPTY ((uint16_t)ADC_FIFOCFG_EINTEN) +#define ADC_FIFO_INT_HALF_FULL ((uint16_t)ADC_FIFOCFG_HFINTEN) +#define ADC_FIFO_INT_NOT_EMPTY ((uint16_t)ADC_FIFOCFG_NEINTEN) + + +/** ADC_interrupts_definition **/ +#define ADC_INT_CONTROL_MASK (0x7C00003FU) /*bit8 - bit25 insert ADC_STS Flag*/ +#define ADC_INT_WRITEERR (ADC_CTRL1_WEIEN | ((uint32_t)ADC_FLAG_WEFLAG <<8U) ) +#define ADC_INT_READERR (ADC_CTRL1_REIEN | ((uint32_t)ADC_FLAG_REFLAG <<8U) ) +#define ADC_INT_EOSAMP (ADC_CTRL1_EOSMPIEN | ((uint32_t)ADC_FLAG_EOSAMP <<8U) ) +#define ADC_INT_PDRDY (ADC_CTRL1_PDRDYIEN | ((uint32_t)ADC_FLAG_PDRDY <<8U) ) +#define ADC_INT_RDY (ADC_CTRL1_RDYIEN | ((uint32_t)ADC_FLAG_RDY <<8U) ) +#define ADC_INT_AWD1 (ADC_CTRL1_AWD1IEN | ((uint32_t)ADC_FLAG_AWDG1 <<8U) ) +#define ADC_INT_JENDC (ADC_CTRL1_JENDCIEN | ((uint32_t)ADC_FLAG_JENDC <<8U) ) +#define ADC_INT_JENDCA (ADC_CTRL1_JENDCAIEN | ((uint32_t)ADC_FLAG_JEOC_ANY <<8U) ) +#define ADC_INT_ENDC (ADC_CTRL1_ENDCIEN | ((uint32_t)ADC_FLAG_ENDC <<8U) ) +#define ADC_INT_ENDCA (ADC_CTRL1_ENDCAIEN | ((uint32_t)ADC_FLAG_EOC_ANY <<8U) ) + +// /** ADC1_channels_definition **/ +#define ADC1_Channel_00_PA0_C (ADC_CH_0) +#define ADC1_Channel_01_PA1_C (ADC_CH_1) +#define ADC1_Channel_02_PF11 (ADC_CH_2) +#define ADC1_Channel_03_PA6 (ADC_CH_3) +#define ADC1_Channel_04_PC4 (ADC_CH_4) +#define ADC1_Channel_05_PB1 (ADC_CH_5) +#define ADC1_Channel_06_PF12 (ADC_CH_6) +#define ADC1_Channel_07_PA7 (ADC_CH_7) +#define ADC1_Channel_08_PC5 (ADC_CH_8) +#define ADC1_Channel_09_PB0 (ADC_CH_9) +#define ADC1_Channel_10_PC0 (ADC_CH_10) +#define ADC1_Channel_11_PC1 (ADC_CH_11) +#define ADC1_Channel_12_PC2 (ADC_CH_12) +#define ADC1_Channel_13_PC3 (ADC_CH_13) +#define ADC1_Channel_14_PA2 (ADC_CH_14) +#define ADC1_Channel_15_PA3 (ADC_CH_15) +#define ADC1_Channel_16_PA0 (ADC_CH_16) +#define ADC1_Channel_17_PA1 (ADC_CH_17) +#define ADC1_Channel_18_PA4 (ADC_CH_18) +#define ADC1_Channel_19_PA5 (ADC_CH_19) + +// /** ADC2_channels_definition **/ +#define ADC2_Channel_00_PA0_C_PC2_C (ADC_CH_0) //this channel can be optionally conected to PA0_C or PC2_C; +#define ADC2_Channel_01_PA1_C_PC3_C (ADC_CH_1) //this channel can be optionally conected to PA1_C or PC3_C; +#define ADC2_Channel_02_PF13 (ADC_CH_2) +#define ADC2_Channel_03_PA6 (ADC_CH_3) +#define ADC2_Channel_04_PC4 (ADC_CH_4) +#define ADC2_Channel_05_PB1 (ADC_CH_5) +#define ADC2_Channel_06_PF14 (ADC_CH_6) +#define ADC2_Channel_07_PA7 (ADC_CH_7) +#define ADC2_Channel_08_PC5 (ADC_CH_8) +#define ADC2_Channel_09_PB0 (ADC_CH_9) +#define ADC2_Channel_10_PC0 (ADC_CH_10) +#define ADC2_Channel_11_PC1 (ADC_CH_11) +#define ADC2_Channel_12_PC2 (ADC_CH_12) +#define ADC2_Channel_13_PC3 (ADC_CH_13) +#define ADC2_Channel_14_PA2 (ADC_CH_14) +#define ADC2_Channel_15_PA3 (ADC_CH_15) +#define ADC2_Channel_16_DAC135 (ADC_CH_16) +#define ADC2_Channel_17_DAC246 (ADC_CH_17) +#define ADC2_Channel_18_PA4 (ADC_CH_18) +#define ADC2_Channel_19_PA5 (ADC_CH_19) + +// /** ADC3_channels_definition **/ +#define ADC3_Channel_00_PC2_C (ADC_CH_0) +#define ADC3_Channel_01_PC3_C (ADC_CH_1) +#define ADC3_Channel_02_PF9 (ADC_CH_2) +#define ADC3_Channel_03_PF7 (ADC_CH_3) +#define ADC3_Channel_04_PF5 (ADC_CH_4) +#define ADC3_Channel_05_PF3 (ADC_CH_5) +#define ADC3_Channel_06_PF10 (ADC_CH_6) +#define ADC3_Channel_07_PF8 (ADC_CH_7) +#define ADC3_Channel_08_PF6 (ADC_CH_8) +#define ADC3_Channel_09_PF4 (ADC_CH_9) +#define ADC3_Channel_10_PC0 (ADC_CH_10) +#define ADC3_Channel_11_PC1 (ADC_CH_11) +#define ADC3_Channel_12_PC2 (ADC_CH_12) +#define ADC3_Channel_13_PH2 (ADC_CH_13) +#define ADC3_Channel_14_PH3 (ADC_CH_14) +#define ADC3_Channel_15_PH4 (ADC_CH_15) +#define ADC3_Channel_16_PH5 (ADC_CH_16) +#define ADC3_Channel_17_Battery_DIV4 (ADC_CH_17) +#define ADC3_Channel_18_Temperture_Sensor (ADC_CH_18) +#define ADC3_Channel_19_VREFINT (ADC_CH_19) + +/** ADC_differential_selection_channnels_definition **/ +#define ADC_DIFSEL_CHS_MASK (ADC_DIFSEL_DIFSEL) +#define ADC_DIFSEL_CHS_1 (ADC_DIFSEL_DIFSEL_CH1) +#define ADC_DIFSEL_CHS_2 (ADC_DIFSEL_DIFSEL_CH2) +#define ADC_DIFSEL_CHS_3 (ADC_DIFSEL_DIFSEL_CH3) +#define ADC_DIFSEL_CHS_4 (ADC_DIFSEL_DIFSEL_CH4) +#define ADC_DIFSEL_CHS_5 (ADC_DIFSEL_DIFSEL_CH5) +#define ADC_DIFSEL_CHS_6 (ADC_DIFSEL_DIFSEL_CH6) +#define ADC_DIFSEL_CHS_7 (ADC_DIFSEL_DIFSEL_CH7) +#define ADC_DIFSEL_CHS_8 (ADC_DIFSEL_DIFSEL_CH8) +#define ADC_DIFSEL_CHS_9 (ADC_DIFSEL_DIFSEL_CH9) +#define ADC_DIFSEL_CHS_10 (ADC_DIFSEL_DIFSEL_CH10) +#define ADC_DIFSEL_CHS_11 (ADC_DIFSEL_DIFSEL_CH11) +#define ADC_DIFSEL_CHS_12 (ADC_DIFSEL_DIFSEL_CH12) +#define ADC_DIFSEL_CHS_13 (ADC_DIFSEL_DIFSEL_CH13) +#define ADC_DIFSEL_CHS_14 (ADC_DIFSEL_DIFSEL_CH14) +#define ADC_DIFSEL_CHS_15 (ADC_DIFSEL_DIFSEL_CH15) +#define ADC_DIFSEL_CHS_16 (ADC_DIFSEL_DIFSEL_CH16) +#define ADC_DIFSEL_CHS_17 (ADC_DIFSEL_DIFSEL_CH17) +#define ADC_DIFSEL_CHS_18 (ADC_DIFSEL_DIFSEL_CH18) +#define ADC_DIFSEL_CHS_19 (ADC_DIFSEL_DIFSEL_CH19) + + +/** ADC_channel_mode_definition **/ +#define ADC_SINGLE_ENDED ((uint32_t)0x00LU) /** signal-ended mode **/ +#define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x01LU) /** differential mode **/ + +/** ADC_Write/Read_Internal_Register_definition **/ + +#define ADC_WRITE_READ_TIMEOUT_CYCLE ((uint32_t)0xFFLU) + +#define ADC_WRITE_REG_MASK (ADC_INTLRCFG_WEN | ADC_INTLRCFG_ADDR | ADC_INTLRCFG_WDATA | ADC_INTLRCFG_RWSTART) +#define ADC_WRITE_READ_START (ADC_INTLRCFG_RWSTART) +#define ADC_WRITE_READ_RDY (ADC_INTLRCFG_DONE) +#define ADC_READ_REG_MASK (ADC_INTLRCFG_WEN | ADC_INTLRCFG_ADDR | ADC_INTLRCFG_RWSTART) +#define ADC_RDATA_MASK (ADC_INTLRCFG_RDATA) + +#define ADC_CALIBRATION_ADDR ((uint8_t)0x05U) +#define ADC_CALIBRATION_RDY ((uint8_t)0x40U) +#define ADC_CALIBRATION_RDY ((uint8_t)0x40U) +/** ADC_Gain_Compensation_definition **/ +#define ADC_GAIN_COMPENSATION_EN_MASK (ADC_GCOMP_GCOMPDAT) + + + +/** ADC_Exported_Functions **/ + +void ADC_DeInit(ADC_Module* ADCx); +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); +void ADC_InitStruct(ADC_InitType* ADC_InitStruct); +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_SetDMATransferMode(ADC_Module *ADCx, uint32_t DMAMode); +void ADC_CalibrationOperation(ADC_Module* ADCx); +void ADC_CalibrationReset(ADC_Module* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); + +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); +FlagStatus ADC_GetGainCompensationCmdStatus(ADC_Module* ADCx); +void ADC_EnableTempSensor(FunctionalState Cmd); +void ADC_EnableVrefint(FunctionalState Cmd); +void ADC_StopRegularConv(ADC_Module* ADCx); +void ADC_StopInjectedConv(ADC_Module* ADCx); +void ADC_StartInjectedConv(ADC_Module *ADCx); +void ADC_StartRegularConv(ADC_Module *ADCx); +void ADC_SetRegularDataTransferMode(ADC_Module *ADCx, uint32_t DataTransferMode); +void ADC_EnableMutiAdcDSMU(ADC_Module *ADCx, FunctionalState Cmd); + +void ADC_SetRegularTriggerEdge(ADC_Module* ADCx, uint32_t ExternalRegularTriggerEdge); +void ADC_SetInjectTriggerEdge(ADC_Module* ADCx, uint32_t ExternalInjectTriggerEdge); + +void ADC_SetIndenpentSamplingDelay(ADC_Module* ADCx, uint32_t IndenpentSamplingDelay); +void ADC_SetMultiTwoSamplingDelay(ADC_Module* ADCx, uint32_t MultiTwoSamplingDelay); + +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +uint16_t ADC_GetDat(ADC_Module* ADCx); +uint32_t ADC_GetMutiModeConversionDat(ADC_Module* ADCx); +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ConfigExternalTrigRegularConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigRegularConv); + +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); +void ADC_ConfigAnalogWatchdog1WorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_SetAWDG1FilteringConfig(ADC_Module *ADCx, uint32_t FilteringCount); +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, ADC_AWDG Awdg, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_ConfigAnalogWatchdog1SingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); +void ADC_SetAnalogWatchdog23MonitChannels(ADC_Module* ADCx, uint8_t AWDG_RegEnOffset, uint32_t AWDG_ChannelGroup); +uint32_t ADC_GetAnalogWatchdog23MonitChannels(ADC_Module* ADCx, uint8_t AWDG_RegEnOffset); +void ADC_SetAnalogWatchdog23IntConfig(ADC_Module* ADCx, uint8_t AWDG_RegIntEnOffset, uint32_t AWDG_ChannelEn); +uint32_t ADC_GetAnalogWatchdog23IntConfig(ADC_Module* ADCx, uint8_t AWDG_RegEnOffset); +uint32_t ADC_GetAnalogWatchdog23StatusFlag(ADC_Module* ADCx, uint8_t AWDG_RegSTSOffset); +void ADC_ClearAnalogWatchdog23StatusFlag(ADC_Module* ADCx, uint8_t AWDG_RegSTSOffset, uint32_t AWDG_ChannelFlag); +void ADC_EnableAnalogWatchdogEventToTIM(ADC_Module* ADCx, ADC_AWDG Awdg, FunctionalState Cmd); + +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint32_t ADC_FLAG); +void ADC_ClearFlag(ADC_Module* ADCx, uint32_t ADC_FLAG); +void ADC_ConfigInt(ADC_Module* ADCx, uint32_t ADC_IT, FunctionalState Cmd); +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint32_t ADC_IT); +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint32_t ADC_IT); + +void ADC_SetChannelSingleDiff(ADC_Module* ADCx, uint32_t Channel, uint32_t SingleDiff); + +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); +void ADC_SelectClockMode(ADC_Module* ADCx, uint32_t ClockMode); +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState Cmd); +void ADC_EnableBatteryVoltageMonitor(FunctionalState Cmd); + +/*functions related to oversampling */ +void ADC_ConfigOverSamplingRatioAndShift(ADC_Module *ADCx, uint32_t Ratio, uint32_t Shift); +void ADC_SetOverSamplingScope(ADC_Module *ADCx, uint32_t OversampleScope); +void ADC_EnableOverSamplingDiscont(ADC_Module *ADCx, FunctionalState Cmd); +void ADC_SetOffsetConfig(ADC_Module* ADCx, uint8_t ADC_Offset, ADC_OffsetType* ADC_OffsetStruct); +void ADC_GetOffsetConfig(ADC_Module* ADCx, uint8_t ADC_Offset, ADC_OffsetType* ADC_OffsetStruct); +void ADC_SetGainCompensation(ADC_Module *ADCx, uint32_t GainCompensationMode, uint32_t GainCompensationValue); + +/*functions related to FIFO operations*/ +void ADC_ClearFIFO(ADC_Module* ADCx); +void ADC_EnableFIFO(ADC_Module* ADCx, FunctionalState Cmd); +uint8_t ADC_GetFIFOInvalidedDataCount(ADC_Module* ADCx); +FlagStatus ADC_GetFIFOFlagStatus(ADC_Module* ADCx, uint16_t ADC_FIFOFLAG); +void ADC_ClearFIFOFlag(ADC_Module* ADCx, uint16_t ADC_FIFO_FLAG); +void ADC_ConfigFIFOWaterLevel(ADC_Module* ADCx, uint32_t FIFO_Level); +void ADC_ConfigFIFOInt(ADC_Module* ADCx, uint16_t ADC_FIFO_IT, FunctionalState Cmd); +void ADC_ClearFIFOIntPendingBit(ADC_Module* ADCx, uint16_t ADC_FIFO_IT); + +//ErrorStatus ADC_ReadDataFromInternalReg(ADC_Module* ADCx, uint8_t Addr, uint16_t *ReadOutData); +//ErrorStatus ADC_WriteDataIntoInternalReg(ADC_Module* ADCx, uint8_t Addr, uint8_t Data); + +void ADC_ConfigClk(ADC_Module* ADCx, ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t Pll_CLK_source, uint32_t RCC_ADCPrescaler); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_ADC_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_comp.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_comp.h new file mode 100644 index 0000000000..37c5959dba --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_comp.h @@ -0,0 +1,330 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_comp.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_COMP_H__ +#define __N32H76X_78X_COMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" +#include + + +/** COMP_Exported_Types **/ + +typedef enum +{ + COMP1 = 0, + COMP2 = 1, + COMP3 = 2, + COMP4 = 3 +} COMPX; + + +typedef enum { + COMPX_CTRL_INMSEL_RES = (0x7U << 1), + /*comp1 inm sel*/ + COMP1_CTRL_INMSEL_PB1 = (0x0U << 1), + COMP1_CTRL_INMSEL_PC4 = (0x1U << 1), + COMP1_CTRL_INMSEL_DAC1_IOUT = (0x2U << 1), + COMP1_CTRL_INMSEL_DAC2_IOUT = (0x3U << 1), + COMP1_CTRL_INMSEL_DAC3_IOUT = (0x4U << 1), + COMP1_CTRL_INMSEL_DAC4_IOUT = (0x5U << 1), + COMP1_CTRL_INMSEL_DAC5_IOUT = (0x6U << 1), + COMP1_CTRL_INMSEL_DAC6_IOUT = (0x7U << 1), + COMP1_CTRL_INMSEL_VREF1 = (0x8U << 1), + COMP1_CTRL_INMSEL_PF3 = (0x9U << 1), + /*comp2 inm sel*/ + COMP2_CTRL_INMSEL_PE7 = (0x0U << 1), + COMP2_CTRL_INMSEL_PE10 = (0x1U << 1), + COMP2_CTRL_INMSEL_DAC1_IOUT = (0x2U << 1), + COMP2_CTRL_INMSEL_DAC2_IOUT = (0x3U << 1), + COMP2_CTRL_INMSEL_DAC3_IOUT = (0x4U << 1), + COMP2_CTRL_INMSEL_DAC4_IOUT = (0x5U << 1), + COMP2_CTRL_INMSEL_DAC5_IOUT = (0x6U << 1), + COMP2_CTRL_INMSEL_DAC6_IOUT = (0x7U << 1), + COMP2_CTRL_INMSEL_VREF2 = (0x8U << 1), + COMP2_CTRL_INMSEL_PF6 = (0x9U << 1), + /*comp3 inm sel*/ + COMP3_CTRL_INMSEL_PF1 = (0x0U << 1), + COMP3_CTRL_INMSEL_PF14 = (0x1U << 1), + COMP3_CTRL_INMSEL_DAC1_IOUT = (0x2U << 1), + COMP3_CTRL_INMSEL_DAC2_IOUT = (0x3U << 1), + COMP3_CTRL_INMSEL_DAC3_IOUT = (0x4U << 1), + COMP3_CTRL_INMSEL_DAC4_IOUT = (0x5U << 1), + COMP3_CTRL_INMSEL_DAC5_IOUT = (0x6U << 1), + COMP3_CTRL_INMSEL_DAC6_IOUT = (0x7U << 1), + + /*comp4 inm sel*/ + COMP4_CTRL_INMSEL_PH9 = (0x0U << 1), + COMP4_CTRL_INMSEL_PH6 = (0x1U << 1), + COMP4_CTRL_INMSEL_DAC1_IOUT = (0x2U << 1), + COMP4_CTRL_INMSEL_DAC2_IOUT = (0x3U << 1), + COMP4_CTRL_INMSEL_DAC3_IOUT = (0x4U << 1), + COMP4_CTRL_INMSEL_DAC4_IOUT = (0x5U << 1), + COMP4_CTRL_INMSEL_DAC5_IOUT = (0x6U << 1), + COMP4_CTRL_INMSEL_DAC6_IOUT = (0x7U << 1), + COMP4_CTRL_INMSEL_PH8 = (0x8U << 1) +}COMP_CTRL_INMSEL; + +typedef enum { + COMPX_CTRL_INPSEL_RES = (0xFU << 5), + /*comp1 inp sel*/ + COMP1_CTRL_INPSEL_PB0 = (0x0U << 5), + COMP1_CTRL_INPSEL_PB2 = (0x1U << 5), + COMP1_CTRL_INPSEL_DAC1_IOUT = (0x2U << 5), + COMP1_CTRL_INPSEL_DAC2_IOUT = (0x3U << 5), + COMP1_CTRL_INPSEL_DAC3_IOUT = (0x4U << 5), + COMP1_CTRL_INPSEL_DAC4_IOUT = (0x5U << 5), + COMP1_CTRL_INPSEL_DAC5_IOUT = (0x6U << 5), + COMP1_CTRL_INPSEL_DAC6_IOUT = (0x7U << 5), + COMP1_CTRL_INPSEL_VREF1 = (0x8U << 5), + COMP1_CTRL_INPSEL_PF5 = (0x9U << 5), + /*comp2 inp sel*/ + COMP2_CTRL_INPSEL_PE9 = (0x0U << 5), + COMP2_CTRL_INPSEL_PE11 = (0x1U << 5), + COMP2_CTRL_INPSEL_DAC1_IOUT = (0x2U << 5), + COMP2_CTRL_INPSEL_DAC2_IOUT = (0x3U << 5), + COMP2_CTRL_INPSEL_DAC3_IOUT = (0x4U << 5), + COMP2_CTRL_INPSEL_DAC4_IOUT = (0x5U << 5), + COMP2_CTRL_INPSEL_DAC5_IOUT = (0x6U << 5), + COMP2_CTRL_INPSEL_DAC6_IOUT = (0x7U << 5), + COMP2_CTRL_INPSEL_VREF2 = (0x8U << 5), + COMP2_CTRL_INPSEL_PB2 = (0x9U << 5), + COMP2_CTRL_INPSEL_PF7 = (0xAU << 5), + /*comp3 inp sel*/ + COMP3_CTRL_INPSEL_PF2 = (0x0U << 5), + COMP3_CTRL_INPSEL_PF15 = (0x1U << 5), + COMP3_CTRL_INPSEL_DAC1_IOUT = (0x2U << 5), + COMP3_CTRL_INPSEL_DAC2_IOUT = (0x3U << 5), + COMP3_CTRL_INPSEL_DAC3_IOUT = (0x4U << 5), + COMP3_CTRL_INPSEL_DAC4_IOUT = (0x5U << 5), + COMP3_CTRL_INPSEL_DAC5_IOUT = (0x6U << 5), + COMP3_CTRL_INPSEL_DAC6_IOUT = (0x7U << 5), + + /*comp4 inp sel*/ + COMP4_CTRL_INPSEL_PH10 = (0x0U << 5), + COMP4_CTRL_INPSEL_PH7 = (0x1U << 5), + COMP4_CTRL_INPSEL_DAC1_IOUT = (0x2U << 5), + COMP4_CTRL_INPSEL_DAC2_IOUT = (0x3U << 5), + COMP4_CTRL_INPSEL_DAC3_IOUT = (0x4U << 5), + COMP4_CTRL_INPSEL_DAC4_IOUT = (0x5U << 5), + COMP4_CTRL_INPSEL_DAC5_IOUT = (0x6U << 5), + COMP4_CTRL_INPSEL_DAC6_IOUT = (0x7U << 5), + COMP4_CTRL_INPSEL_PF15 = (0x8U << 5), + COMP4_CTRL_INPSEL_PF10 = (0x9U << 5) +}COMP_CTRL_INPSEL; + +/*comp hysteresis level select*/ +typedef enum +{ + COMP_CTRL_HYST_NO = (0x0U << 14), + COMP_CTRL_HYST_LOW = (0x1U << 14), + COMP_CTRL_HYST_MID = (0x2U << 14), + COMP_CTRL_HYST_HIGH = (0x3U << 14) +} COMP_CTRL_HYST; + +/*comp Blking source select*/ +typedef enum +{ + COMP_CTRL_BLKING_NO = (0x0U << 16 ), + COMP_CTRL_BLKING_ATIM1_OC5 = (0x0U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMB1_OC5 = (0x1U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMB2_OC5 = (0x2U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_ATIM2_OC5 = (0x3U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_ATIM3_OC5 = (0x4U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_ATIM4_OC1 = (0x5U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMB3_OC5 = (0x6U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA4_OC5 = (0x7U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA2_OC3 = (0x8U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA1_OC3 = (0x9U << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA3_OC3 = (0xAU << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA5_OC3 = (0xBU << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA6_OC3 = (0xCU << 16 | COMP1_CTRL_BLKINGEN), + COMP_CTRL_BLKING_GTIMA7_OC3 = (0xDU << 16 | COMP1_CTRL_BLKINGEN) +} COMP_CTRL_BLKING; + +/** COMP_Exported_Constants **/ + +/** COMPx_CTRL **/ +#define COMP_CTRL_OUT_MASK (COMP1_CTRL_OUT) + +#define COMP_CTRL_BLKING_MASK (COMP1_CTRL_BLKING | COMP1_CTRL_BLKINGEN) + +#define COMP_CTRL_HYST_MASK (COMP1_CTRL_HYST) + +#define COMP_POL_MASK (COMP1_CTRL_POL) +#define COMP_OUTPOL_FLIP (COMP1_CTRL_POL) +#define COMP_OUTPOL_NFLIP (0x00000000U) + +#define COMP_CTRL_INPSEL_MASK (COMP1_CTRL_INPSEL) /*MAX INPSEL BIT.*/ + +#define COMP_CTRL_INMSEL_MASK (COMP1_CTRL_INMSEL) /*MAX INMSEL BIT.*/ + +#define COMP_CTRL_EN_MASK (COMP1_CTRL_EN) + +/** COMPx_FILC **/ + +#define COMP_VFLAG_P (COMP1_FILC_VP_FLAG) /*using DAC stable value as Comparator's positive input.*/ +#define COMP_VFLAG_N (COMP1_FILC_VN_FLAG) /*using DAC stable value as Comparator's negetive input.*/ +#define COMP_FILC_SAMPW_MASK (COMP1_FILC_SAMPW) /*Low filter sample window size. Number of samples to monitor is SAMPWIN+1.*/ +#define COMP_FILC_THRESH_MASK (COMP1_FILC_THRESH)/*For proper operation, the value of THRESH must be greater than SAMPWIN / 2.*/ +#define COMP_FILC_FILEN_MASK (COMP1_FILC_FILEN) /*Filter enable.*/ + +/** COMPx_FILP **/ +#define COMP_FILCLKCR_CLKPSC_MASK (COMP1_FILP_CLKPSC)/*Low filter sample clock prescale. Number of system clocks between samples = CLK_PRE_CYCLE + 1, e.g.*/ + + +/** COMP_LPMODE **/ +#define COMP_LPMODE_LP_EN_MASK (COMP_LPR_CLKSEL) + +/** COMP_WINMODE **/ +#define COMP_WINMODE_CMPMD_MSK (COMP_WINMODE_COMP12MD|COMP_WINMODE_COMP34MD) +#define COMP_WINMODE_CMP34MD (COMP_WINMODE_COMP34MD)/* Comparators 3 and 4 can be used in window mode.*/ +#define COMP_WINMODE_CMP12MD (COMP_WINMODE_COMP12MD)/* Comparators 1 and 2 can be used in window mode.*/ + +/** COMP_LOCK **/ +#define COMP_LOCK_MSK (COMP_LOCK) +#define COMP1_LOCK (COMP_LOCK_CMP1LK) +#define COMP2_LOCK (COMP_LOCK_CMP2LK) +#define COMP3_LOCK (COMP_LOCK_CMP3LK) +#define COMP4_LOCK (COMP_LOCK_CMP4LK) + +/** COMP_INTEN **/ +#define COMP_INTIEN_MSK (COMP_INTEN) +#define COMP1_INTEN (COMP_INTEN_CMP1IEN) +#define COMP2_INTEN (COMP_INTEN_CMP2IEN) +#define COMP3_INTEN (COMP_INTEN_CMP3IEN) +#define COMP4_INTEN (COMP_INTEN_CMP4IEN) + +/** COMP_INTSTS **/ +#define COMP_INTSTS_MSK (COMP_INTSTS) +#define COMP1_INTSTS (COMP_INTSTS_COMP1IS) +#define COMP2_INTSTS (COMP_INTSTS_COMP2IS) +#define COMP3_INTSTS (COMP_INTSTS_COMP3IS) +#define COMP4_INTSTS (COMP_INTSTS_COMP4IS) + +/** COMP_VREFSCL **/ +#define COMP_VREFSCL_VVEN_MSK (COMP1_CTRL_VV1EN) +#define COMP_VREFSCL_VVTRM_MSK (COMP1_CTRL_VV1TRM) /** Vref Voltage scaler triming value. **/ + +/** COMP_OTIMEN **/ +#define COMP_TIM_EN_MSK (COMP_OTIMEN_MASK) +#define COMP1_TIM_EN (COMP_OTIMEN_CMP1OEN) +#define COMP2_TIM_EN (COMP_OTIMEN_CMP2OEN) +#define COMP3_TIM_EN (COMP_OTIMEN_CMP3OEN) +#define COMP4_TIM_EN (COMP_OTIMEN_CMP4OEN) + +/** COMP Init structure definition **/ +typedef struct +{ + COMP_CTRL_BLKING Blking; + + COMP_CTRL_HYST Hyst; + + FunctionalState PolRev; /* out polarity reverse */ + + COMP_CTRL_INPSEL InpSel; + COMP_CTRL_INMSEL InmSel; + + FunctionalState En; /* COMP enable */ + + /* filter config */ + uint8_t SampWindow; /* 5bit */ + uint8_t Threshold; /* 5bit need > SampWindow/2 */ + FunctionalState FilterEn; + + /* filter psc config */ + uint16_t ClkPsc; +} COMP_InitType; + + +/** COMP_Exported_Functions **/ +void COMP_DeInit(void); +void COMP_StructInit(COMP_InitType* COMP_InitStruct); +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct); + +void COMP_Enable(COMPX COMPx, FunctionalState Cmd); +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel); +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel); +void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST); +void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK); + +void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal); +void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW); +void COMP_EnableVflag(COMPX COMPx, uint32_t InputMode, FunctionalState Cmd); + +FlagStatus COMP_GetOutStatus(COMPX COMPx); +FlagStatus COMP_GetFilterOutStatus(COMPX COMPx); + +void COMP_SetLowPowerMode(FunctionalState Cmd); +void COMP_WindowModeEnable(uint32_t WinModeEn, FunctionalState Cmd); +void COMP_SetLock(uint32_t Lock); +void COMP_SetIntEn(uint32_t IntEn, FunctionalState Cmd); + +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx); +void COMP_ClearIntStsOneComp(COMPX COMPx); + +void COMP_SetRefScl( uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); +void COMP_OutToTimEnable(uint32_t TimEn, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_COMP_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_cordic.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_cordic.h new file mode 100644 index 0000000000..eda862761e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_cordic.h @@ -0,0 +1,236 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_cordic.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_CORDIC_H__ +#define __N32H76X_78X_CORDIC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + + +/*** CORDIC Structure Definition Start ***/ + +/** CORDIC initialize configuration structure definition **/ +typedef struct +{ + uint32_t Function; /* Select function */ + uint32_t Precision; /* Set the number of iterations */ + uint32_t Scale; /* Select Scaling Factor */ + uint32_t NbWrite; /* Select the number of CORDIC_WDAT register to write */ + uint32_t NbRead; /* Select the number of CORDIC_RDAT register to read */ + uint32_t InSize; /* Select input data width */ + uint32_t OutSize; /* Select output data width */ + uint32_t InSelect; /* Select floating-point input or fixed-point input */ + uint32_t OutSelect; /* Select floating-point output or fixed-point output */ + uint32_t CodinLimit; /* Enables or disables Coordinate Limit */ + uint32_t PhaseLimit; /* Enables or disables Phase Limit */ +} CORDIC_InitType; + +/*** CORDIC Structure Definition End ***/ + + +/*** CORDIC Macro Definition Start ***/ + +/** CORDIC Coordinate Limit definition **/ +#define CORDIC_CODIN_LIMIT_ENABLE (CORDIC_CTRLSTS_CODINLIMIT) /* Coordinate Output Limit enable */ +#define CORDIC_CODIN_LIMIT_DISABLE ((uint32_t)0x00000000U) /* Coordinate Output Limit disable */ + +/** CORDIC Phase Limit definition **/ +#define CORDIC_PHASE_LIMIT_ENABLE (CORDIC_CTRLSTS_PHASELIMIT) /* Phase Output Limit enable */ +#define CORDIC_PHASE_LIMIT_DISABLE ((uint32_t)0x00000000U) /* Phase Output Limit disable */ + +/** CORDIC Output Select definition **/ +#define CORDIC_OUTPUT_FLOAT (CORDIC_CTRLSTS_FLOATOUT) /* Floating-point Output */ +#define CORDIC_OUTPUT_FIX ((uint32_t)0x00000000U) /* Fixed-point Output */ + +/** CORDIC Input Select definition **/ +#define CORDIC_INPUT_FLOAT (CORDIC_CTRLSTS_FLOATIN) /* Floating-point Input */ +#define CORDIC_INPUT_FIX ((uint32_t)0x00000000U) /* Fixed-point Input */ + +/** CORDIC Output width definition **/ +#define CORDIC_OUTSIZE_16BITS (CORDIC_CTRLSTS_OUTSIZE) /* 16 bits output data size (e.g:Q1.15 format) */ +#define CORDIC_OUTSIZE_32BITS ((uint32_t)0x00000000U) /* 32 bits output data size (e.g:Q1.31 format) */ + +/** CORDIC Input width definition **/ +#define CORDIC_INSIZE_16BITS (CORDIC_CTRLSTS_INSIZE) /* 16 bits input data size (e.g:Q1.15 format) */ +#define CORDIC_INSIZE_32BITS ((uint32_t)0x00000000U) /* 32 bits input data size (e.g:Q1.31 format) */ + +/** CORDIC Read register Number definition **/ +#define CORDIC_NBREAD_2 (CORDIC_CTRLSTS_NUMREAD) /* Two 32-bit Data containing two 32-bits + data output (e.g:Q1.31 format) */ +#define CORDIC_NBREAD_1 ((uint32_t)0x00000000U) /* One 32-bits read containing either only one \ + 32-bit data output (e.g:Q1.31 format), or two \ + 16-bit data output (e.g:Q1.15 format) packed \ + in one 32 bits Data */ + +/** CORDIC Write register Number definition **/ +#define CORDIC_NBWRITE_2 (CORDIC_CTRLSTS_NUMWRITE) /* Two 32-bit write containing two 32-bits \ + data input (e.g:Q1.31 format) */ +#define CORDIC_NBWRITE_1 ((uint32_t)0x00000000U) /* One 32-bits write containing either only one \ + 32-bit data input (e.g:Q1.31 format), or two \ + 16-bit data input (e.g:Q1.15 format) packed \ + in one 32 bits Data */ + +/** CORDIC Scaling Factor definition **/ +#define CORDIC_SCALE_0 ( (uint32_t)0x00000000U) /* Scaling Factor is 2^0 */ +#define CORDIC_SCALE_1 ( CORDIC_CTRLSTS_SCALE_0 ) /* Scaling Factor is 2^1 */ +#define CORDIC_SCALE_2 ( CORDIC_CTRLSTS_SCALE_1 ) /* Scaling Factor is 2^2 */ +#define CORDIC_SCALE_3 ( CORDIC_CTRLSTS_SCALE_1 \ + | CORDIC_CTRLSTS_SCALE_0 ) /* Scaling Factor is 2^3 */ +#define CORDIC_SCALE_4 ( CORDIC_CTRLSTS_SCALE_2 ) /* Scaling Factor is 2^4 */ +#define CORDIC_SCALE_5 ( CORDIC_CTRLSTS_SCALE_2 \ + | CORDIC_CTRLSTS_SCALE_0 ) /* Scaling Factor is 2^5 */ +#define CORDIC_SCALE_6 ( CORDIC_CTRLSTS_SCALE_2 \ + | CORDIC_CTRLSTS_SCALE_1 ) /* Scaling Factor is 2^6 */ +#define CORDIC_SCALE_7 ( CORDIC_CTRLSTS_SCALE_2 \ + | CORDIC_CTRLSTS_SCALE_1 \ + | CORDIC_CTRLSTS_SCALE_0 ) /* Scaling Factor is 2^7 */ + +/** CORDIC Precision(Number of iterations) definition **/ +#define CORDIC_PRECISION_1CYCLE ( CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 1*4*/ +#define CORDIC_PRECISION_2CYCLES ( CORDIC_CTRLSTS_PRECISION_1 ) /* Iteration Count is 2*4*/ +#define CORDIC_PRECISION_3CYCLES ( CORDIC_CTRLSTS_PRECISION_1 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 3*4*/ +#define CORDIC_PRECISION_4CYCLES ( CORDIC_CTRLSTS_PRECISION_2 ) /* Iteration Count is 4*4*/ +#define CORDIC_PRECISION_5CYCLES ( CORDIC_CTRLSTS_PRECISION_2 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 5*4*/ +#define CORDIC_PRECISION_6CYCLES ( CORDIC_CTRLSTS_PRECISION_2 \ + | CORDIC_CTRLSTS_PRECISION_1 ) /* Iteration Count is 6*4*/ +#define CORDIC_PRECISION_7CYCLES ( CORDIC_CTRLSTS_PRECISION_2 \ + | CORDIC_CTRLSTS_PRECISION_1 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 7*4*/ +#define CORDIC_PRECISION_8CYCLES ( CORDIC_CTRLSTS_PRECISION_3 ) /* Iteration Count is 8*4*/ +#define CORDIC_PRECISION_9CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 9*4*/ +#define CORDIC_PRECISION_10CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_1 ) /* Iteration Count is 10*4*/ +#define CORDIC_PRECISION_11CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_1 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 11*4*/ +#define CORDIC_PRECISION_12CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_2 ) /* Iteration Count is 12*4*/ +#define CORDIC_PRECISION_13CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_2 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 13*4*/ +#define CORDIC_PRECISION_14CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_2 \ + | CORDIC_CTRLSTS_PRECISION_1 ) /* Iteration Count is 14*4*/ +#define CORDIC_PRECISION_15CYCLES ( CORDIC_CTRLSTS_PRECISION_3 \ + | CORDIC_CTRLSTS_PRECISION_2 \ + | CORDIC_CTRLSTS_PRECISION_1 \ + | CORDIC_CTRLSTS_PRECISION_0 ) /* Iteration Count is 15*4*/ + +/** CORDIC Function definition **/ +#define CORDIC_FUNCTION_COSINE ((uint32_t)0x00000000U) /* Cosine */ +#define CORDIC_FUNCTION_SINE ( CORDIC_CTRLSTS_FUNC_0 ) /* Sine */ +#define CORDIC_FUNCTION_PHASE ( CORDIC_CTRLSTS_FUNC_1 ) /* Phase */ +#define CORDIC_FUNCTION_MODULUS ( CORDIC_CTRLSTS_FUNC_1 \ + | CORDIC_CTRLSTS_FUNC_0 ) /* Modulus */ +#define CORDIC_FUNCTION_ARCTANGENT ( CORDIC_CTRLSTS_FUNC_2 ) /* Arctangent */ +#define CORDIC_FUNCTION_HCOSINE ( CORDIC_CTRLSTS_FUNC_2 \ + | CORDIC_CTRLSTS_FUNC_0 ) /* Hyperbolic Cosine */ +#define CORDIC_FUNCTION_HSINE ( CORDIC_CTRLSTS_FUNC_2 \ + | CORDIC_CTRLSTS_FUNC_1 ) /* Hyperbolic Sine */ +#define CORDIC_FUNCTION_HARCTANGENT ( CORDIC_CTRLSTS_FUNC_2 \ + | CORDIC_CTRLSTS_FUNC_1 \ + | CORDIC_CTRLSTS_FUNC_0 ) /* Hyperbolic Arctangent */ +#define CORDIC_FUNCTION_NATURALLOG ( CORDIC_CTRLSTS_FUNC_3 ) /* Natural Logarithm */ +#define CORDIC_FUNCTION_SQUAREROOT ( CORDIC_CTRLSTS_FUNC_3 \ + | CORDIC_CTRLSTS_FUNC_0 ) /* Square Root */ + +/** CORDIC Interrupt definition **/ +#define CORDIC_INT (CORDIC_CTRLSTS_INTEN) /* Result Ready Interrupt Enable */ +#define CORDIC_INT_INOVERFLOW (CORDIC_CTRLSTS_INOVINTEN) /* Input overflow Interrupt Enable */ + +/** CORDIC on DMA transfer direction definition **/ +#define CORDIC_AS_DMA_DSTADDR ((uint32_t)0x00000001U) /* CORDIC register address as Destination address for DMA */ +#define CORDIC_AS_DMA_SRCADDR ((uint32_t)0x00000000U) /* CORDIC register address as Source address for DMA */ + +/** CORDIC flag definition **/ +#define CORDIC_FLAG_RRF (CORDIC_CTRLSTS_RRF) /* Result ready flag */ +#define CORDIC_FLAG_INOVF (CORDIC_CTRLSTS_INOVF) /* Input parameter overflow flag */ +#define CORDIC_FLAG_DMAWENF (CORDIC_CTRLSTS_DMAWEN) /* DMA Write Request Enable Flag */ +#define CORDIC_FLAG_DMARENF (CORDIC_CTRLSTS_DMAREN) /* DMA Read Request Enable Flag */ +#define CORDIC_FLAG_INTENF (CORDIC_CTRLSTS_INTEN) /* CORDIC Interrupt Enable Flag */ +#define CORDIC_FLAG_INOVINTENF (CORDIC_CTRLSTS_INOVINTEN) /* CORDIC Overflow Interrupt Enable Flag */ + +/*** CORDIC Macro Definition End ***/ + +/*** CORDIC Driving Functions Declaration ***/ +void CORDIC_DeInit(void); +void CORDIC_Init(CORDIC_InitType* CORDIC_InitParam); +void CORDIC_StructInit(CORDIC_InitType* CORDIC_InitParam); +void CORDIC_InterruptCmd(uint32_t Interrupt, FunctionalStatus Cmd); +void CORDIC_DMAReadRequestCmd(FunctionalStatus Cmd); +void CORDIC_DMAWriteRequestCmd(FunctionalStatus Cmd); +uint32_t CORDIC_GetRegisterAddr(uint32_t Direction); +void CORDIC_WriteData(uint32_t *pInData); +void CORDIC_ReadData(uint32_t *pOutData); +FlagStatus CORDIC_GetFlagStatus(uint32_t Flag); +void CORDIC_ClearStatusFlag(uint32_t Flag); + +/*** CORDIC Driving Functions Declaration End ***/ + + + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_CORDIC_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_crc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_crc.h new file mode 100644 index 0000000000..7c9f827f11 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_crc.h @@ -0,0 +1,160 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_crc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_CRC_H__ +#define __N32H76x_78x_CRC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32h76x_78x.h" + +typedef struct +{ + uint32_t GeneratingPolynomial; /* Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. */ + uint32_t CRCLength; /* This parameter is a value of ref CRC_Polynomial_Sizes and indicates CRC length. + Value can be either one of + arg ref CRC_POLYLENGTH_32B (32-bit CRC), + arg ref CRC_POLYLENGTH_16B (16-bit CRC), + arg ref CRC_POLYLENGTH_8B (8-bit CRC), + arg ref CRC_POLYLENGTH_7B (7-bit CRC). */ + uint32_t InitValue; /* Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + uint32_t InputDataByteInversionMode; /* This parameter is a value of ref CRC Input Data Byte Reverse and specifies input data byte inversion mode. + Can be either one of the following values + arg ref CRC_INDATA_BYTE_REVERSE_NONE no input data inversion + arg ref CRC_INDATA_BYTE_REVERSE_HALFWORD halfword-wise inversion,0x1A2B3C4D becomes 0x2B1A4D3C + arg ref CRC_INDATA_BYTE_REVERSE_WORD word-wise inversion, 0x1A2B3C4D becomes 0x4D3C2B1A */ + uint32_t InputDataBitInversionMode; /* This parameter is a value of ref CRC Input Data Bit Reverse and specifies input data inversion mode. + Can be either one of the following values + arg ref CRC_INDATA_BIT_REVERSE_NONE no input data inversion + arg ref CRC_INDATA_BIT_REVERSE_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 + arg ref CRC_INDATA_BIT_REVERSE_HALFWORD halfword-wise inversion,0x1A2B3C4D becomes 0xD458B23C + arg ref CRC_INDATA_BIT_REVERSE_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + uint32_t OutputDataInversionMode; /* This parameter is a value of ref CRC Output Data Reverse and specifies output data (i.e. CRC) inversion mode. + Can be either + arg ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + arg ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ + uint32_t InputDataXor; /* This parameter is used to set CRC_DR XOR calculation value before CRC calculation. */ + + uint32_t OutputDataXor; /* This parameter is used to set CRC_DR XOR calculation value after CRC calculation. */ +} CRC_InitType; + +/** CRC_Default_Polynomial_Value Default CRC generating polynomial **/ +#define DEFAULT_CRC32_POLY ((uint32_t)0x04C11DB7U) /* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ + +/** CRC_Default_InitValue Default CRC computation initialization value */ +#define DEFAULT_CRC_INITVALUE ((uint32_t)0xFFFFFFFFU) /* Initial CRC default value */ + +/** CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral */ +#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U) /* Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B (CRC_CTRL_POLYSIZE_0) /* Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B (CRC_CTRL_POLYSIZE_1) /* Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B (CRC_CTRL_POLYSIZE) /* Resort to a 7-bit long generating polynomial */ + +/** CRC Input Data Byte Reverse */ +#define CRC_INDATA_BYTE_REVERSE_NONE ((uint32_t)0x00000000U) /* Input Data Byte order not affected */ +#define CRC_INDATA_BYTE_REVERSE_HALFWORD (CRC_CTRL_BYTEENDIAN_1) /* Input Data Byte reversal done by half-word */ +#define CRC_INDATA_BYTE_REVERSE_WORD (CRC_CTRL_BYTEENDIAN) /* Input Data Byte reversal done by word */ + +/** CRC Input Data Bit Reverse */ +#define CRC_INDATA_BIT_REVERSE_NONE ((uint32_t)0x00000000U) /* Input Data bit order not affected */ +#define CRC_INDATA_BIT_REVERSE_BYTE (CRC_CTRL_REVIN_0) /* Input Data bit reversal done by byte */ +#define CRC_INDATA_BIT_REVERSE_HALFWORD (CRC_CTRL_REVIN_1) /* Input Data bit reversal done by half-word */ +#define CRC_INDATA_BIT_REVERSE_WORD (CRC_CTRL_REVIN_1 \ + |CRC_CTRL_REVIN_0) /* Input Data bit reversal done by word */ + +/** CRC Output Data Reverse */ +#define CRC_OUTDATA_REVERSE_NONE ((uint32_t)0x00000000U) /* Output Data bit order not affected */ +#define CRC_OUTDATA_REVERSE_BIT (CRC_CTRL_REVOUT) /* Output Data bit reversal done by bit */ + +/** CRC_Input_Buffer_Format Input Buffer Format */ +#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U) /* Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U) /* Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U) /* Input data in word format */ + + +void CRC_ResetCalculation(void); +void CRC_DeInit(void); +void CRC_SetInputByteOrder(uint32_t ReverseMode); +void CRC_SetInputBitOrder(uint32_t ReverseMode); +void CRC_SetOutputBitOrder(uint32_t ReverseMode); +void CRC_SetInputDataXor(uint32_t xor_value); +void CRC_SetOutputDataXor(uint32_t xor_value); +void CRC_SetInitialData(uint32_t InitCrc); +void CRC_SetPolynomialCoef(uint32_t PolynomCoef); +void CRC_SetPolynomialSize(uint32_t PolySize); + +void CRC_StructInit(CRC_InitType *CRC_InitStruct); +void CRC_Init(CRC_InitType *CRC_InitStruct); +uint32_t CRC_Calculate(uint32_t InputDataFormat, void *pBuffer, uint32_t BufferLength); +uint32_t CRC_Accumulate(uint32_t InputDataFormat, void *pBuffer, uint32_t BufferLength); +uint32_t CRC_GetLRC(void); +uint32_t CRC_GetIDAT(void); +void CRC_WriteIDAT(uint32_t Idat); + + +#ifdef __cplusplus +} +#endif + +#endif /* __n32h76x_78x_CRC_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dac.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dac.h new file mode 100644 index 0000000000..a1a4e4dee3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dac.h @@ -0,0 +1,346 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dac.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_DAC_H__ +#define __N32H76X_78X_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** DAC_Exported_Types **/ + +typedef enum +{ + DAC1 = 0, + DAC2 = 1, + DAC3 = 2, + DAC4 = 3, + DAC5 = 4, + DAC6 = 5 +} DACX; + +typedef struct +{ + uint32_t DAC_Trigger; + + uint32_t DAC_Trigger2; + + uint32_t DAC_WaveGeneration; + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; + + FunctionalState DAC_OutputBuffer; /* Enable or disable the DAC output buffer */ + + FunctionalState DAC_TriggerEnable; /* Enable or disable the DAC external trigger ,when it is disable, it means Conversion is automatic once the DACx(y)_Dxxx register \ + has been loaded, and not by external trigger */ + + FunctionalState DAC_ConnectOnChipPeripheral ; /* Secifies whether the DAC output is connected or not to on chip peripheral */ + + FunctionalState DAC_ConnectExternalPin ; /* Secifies whether the DAC output is connected or not to external pin */ + + FunctionalState DAC_DMADoubleDataMode; /* Enable or disable DMA double data mode */ + + FunctionalState DAC_SignedFormat; /* Enable or disable signed format mode */ + +}DAC_InitType; + + +/** DAC_Exported_Constants **/ + +/** DAC_trigger **/ +#define DAC_Trigger_Software ((uint32_t)0x00000000U << 11) +#define DAC_Trigger_ATIM1_TRGO ((uint32_t)0x00000001U << 11) +#define DAC_Trigger_ATIM2_TRGO ((uint32_t)0x00000002U << 11) +#define DAC_Trigger_ATIM3_TRGO ((uint32_t)0x00000003U << 11) +#define DAC_Trigger_ATIM4_TRGO ((uint32_t)0x00000004U << 11) +#define DAC_Trigger_GTIMA1_TRGO ((uint32_t)0x00000005U << 11) +#define DAC_Trigger_GTIMA2_TRGO ((uint32_t)0x00000006U << 11) +#define DAC_Trigger_GTIMA3_TRGO ((uint32_t)0x00000007U << 11) +#define DAC_Trigger_GTIMA4_TRGO ((uint32_t)0x00000008U << 11) +#define DAC_Trigger_GTIMA5_TRGO ((uint32_t)0x00000009U << 11) +#define DAC_Trigger_GTIMA6_TRGO ((uint32_t)0x0000000AU << 11) +#define DAC_Trigger_GTIMA7_TRGO ((uint32_t)0x0000000BU << 11) +#define DAC_Trigger_GTIMB1_TRGO ((uint32_t)0x0000000CU << 11) +#define DAC_Trigger_GTIMB2_TRGO ((uint32_t)0x0000000DU << 11) +#define DAC_Trigger_GTIMB3_TRGO ((uint32_t)0x0000000EU << 11) +#define DAC_Trigger_EXTI5 ((uint32_t)0x0000000FU << 11) +#define DAC_Trigger_EXTI7 ((uint32_t)0x00000010U << 11) +#define DAC_Trigger_EXTI9 ((uint32_t)0x00000011U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRG1 ((uint32_t)0x00000012U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRG2 ((uint32_t)0x00000013U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRG3 ((uint32_t)0x00000014U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRG4 ((uint32_t)0x00000015U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRG5 ((uint32_t)0x00000016U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRG6 ((uint32_t)0x00000017U << 11) +#define DAC_Trigger_SHRTIM1_RST_TRGO123 ((uint32_t)0x00000018U << 11) +#define DAC_Trigger_SHRTIM2_RST_TRG1 ((uint32_t)0x00000019U << 11) +#define DAC_Trigger_SHRTIM2_RST_TRG2 ((uint32_t)0x0000001AU << 11) +#define DAC_Trigger_SHRTIM2_RST_TRG3 ((uint32_t)0x0000001BU << 11) +#define DAC_Trigger_SHRTIM2_RST_TRG4 ((uint32_t)0x0000001CU << 11) +#define DAC_Trigger_SHRTIM2_RST_TRG5 ((uint32_t)0x0000001DU << 11) +#define DAC_Trigger_SHRTIM2_RST_TRG6 ((uint32_t)0x0000001EU << 11) +#define DAC_Trigger_SHRTIM2_RST_TRGO123 ((uint32_t)0x0000001FU << 11) + +/** DAC_step_trigger **/ +#define DAC_Trigger2_Software ((uint32_t)0x00000000U << 1) +#define DAC_Trigger2_ATIM1_TRGO ((uint32_t)0x00000001U << 1) +#define DAC_Trigger2_ATIM2_TRGO ((uint32_t)0x00000002U << 1) +#define DAC_Trigger2_ATIM3_TRGO ((uint32_t)0x00000003U << 1) +#define DAC_Trigger2_ATIM4_TRGO ((uint32_t)0x00000004U << 1) +#define DAC_Trigger2_GTIMA1_TRGO ((uint32_t)0x00000005U << 1) +#define DAC_Trigger2_GTIMA2_TRGO ((uint32_t)0x00000006U << 1) +#define DAC_Trigger2_GTIMA3_TRGO ((uint32_t)0x00000007U << 1) +#define DAC_Trigger2_GTIMA4_TRGO ((uint32_t)0x00000008U << 1) +#define DAC_Trigger2_GTIMA5_TRGO ((uint32_t)0x00000009U << 1) +#define DAC_Trigger2_GTIMA6_TRGO ((uint32_t)0x0000000AU << 1) +#define DAC_Trigger2_GTIMA7_TRGO ((uint32_t)0x0000000BU << 1) +#define DAC_Trigger2_GTIMB1_TRGO ((uint32_t)0x0000000CU << 1) +#define DAC_Trigger2_GTIMB2_TRGO ((uint32_t)0x0000000DU << 1) +#define DAC_Trigger2_GTIMB3_TRGO ((uint32_t)0x0000000EU << 1) +#define DAC_Trigger2_EXTI6 ((uint32_t)0x0000000FU << 1) +#define DAC_Trigger2_EXTI8 ((uint32_t)0x00000010U << 1) +#define DAC_Trigger2_EXTI10 ((uint32_t)0x00000011U << 1) +#define DAC_Trigger2_SHRTIM1_STEP_TRG1 ((uint32_t)0x00000012U << 1) +#define DAC_Trigger2_SHRTIM1_STEP_TRG2 ((uint32_t)0x00000013U << 1) +#define DAC_Trigger2_SHRTIM1_STEP_TRG3 ((uint32_t)0x00000014U << 1) +#define DAC_Trigger2_SHRTIM1_STEP_TRG4 ((uint32_t)0x00000015U << 1) +#define DAC_Trigger2_SHRTIM1_STEP_TRG5 ((uint32_t)0x00000016U << 1) +#define DAC_Trigger2_SHRTIM1_STEP_TRG6 ((uint32_t)0x00000017U << 1) +#define DAC_Trigger2_SHRTIM2_STEP_TRG1 ((uint32_t)0x00000019U << 1) +#define DAC_Trigger2_SHRTIM2_STEP_TRG2 ((uint32_t)0x0000001AU << 1) +#define DAC_Trigger2_SHRTIM2_STEP_TRG3 ((uint32_t)0x0000001BU << 1) +#define DAC_Trigger2_SHRTIM2_STEP_TRG4 ((uint32_t)0x0000001CU << 1) +#define DAC_Trigger2_SHRTIM2_STEP_TRG5 ((uint32_t)0x0000001DU << 1) +#define DAC_Trigger2_SHRTIM2_STEP_TRG6 ((uint32_t)0x0000001EU << 1) + + +/** DAC_wave_generation **/ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000U) +#define DAC_WaveGeneration_Noise ((uint32_t)DAC_CTRL_WxEN_0) +#define DAC_WaveGeneration_Triangle ((uint32_t)DAC_CTRL_WxEN_1) +#define DAC_WaveGeneration_SAWTOOTH_INC ((uint32_t)DAC_CTRL_WxEN_2) +#define DAC_WaveGeneration_SAWTOOTH_DEC ((uint32_t)DAC_CTRL_WxEN_2 | DAC_CTRL_WxEN_1) + +/** DAC_lfsrunmask_triangleamplitude **/ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000U << 6) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000001U << 6) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000002U << 6) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000003U << 6) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000004U << 6) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000005U << 6) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000006U << 6) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000007U << 6) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000008U << 6) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000009U << 6) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x0000000AU << 6) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x0000000BU << 6) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000U << 6) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000001U << 6) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000002U << 6) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000003U << 6) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000004U << 6) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000005U << 6) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000006U << 6) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000007U << 6) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000008U << 6) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000009U << 6) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x0000000AU << 6) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x0000000BU << 6) /* Select max triangle amplitude of 4095 */ + + +/** DAC_CTRL **/ +#define DACy_CTRL_TRIG_OVERLOCKIEN_EN_MASK ((uint32_t)DAC_CTRL_TROVCyIEN) +#define DACy_CTRL_OUTPUT_TO_EXTPIN_EN_MASK ((uint32_t)DAC_CTRL_EXOUTy) +#define DACy_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK ((uint32_t)DAC_CTRL_INOUTy) +#define DACy_CTRL_CALIBATE_EN_MASK ((uint32_t)DAC_CTRL_CALyEN) +#define DACy_CTRL_WAVE_TYPE_MASK ((uint32_t)DAC_CTRL_WyEN) +#define DACy_CTRL_SINGFORMAT_EN_MASK ((uint32_t)DAC_CTRL_SINFORMATyEN) +#define DACy_CTRL_DMADOUBLEMODE_EN_MASK ((uint32_t)DAC_CTRL_DMADOUBLEyEN) +#define DACy_CTRL_HIGH_DRIVER_EN_MASK ((uint32_t)DAC_CTRL_HDByEN) +#define DACy_CTRL_DMA_UDRIEN_EN_MASK ((uint32_t)DAC_CTRL_DMAUDRyIEn) +#define DACy_CTRL_TRIGGER_EN_MASK ((uint32_t)DAC_CTRL_TyEN) +#define DACy_CTRL_BUFF_EN_MASK ((uint32_t)DAC_CTRL_ByEN) +#define DACy_CTRL_DMA_EN_MASK ((uint32_t)DAC_CTRL_DMAyEN) +#define DACy_CTRL_EN_MASK ((uint32_t)DAC_CTRL_DACyEN) + +#define DACx_CTRL_TRIG_OVERLOCKIEN_EN_MASK ((uint32_t)DAC_CTRL_TROVCxIEN) +#define DACx_CTRL_OUTPUT_TO_EXTPIN_EN_MASK ((uint32_t)DAC_CTRL_EXOUTx) +#define DACx_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK ((uint32_t)DAC_CTRL_INOUTx) +#define DACx_CTRL_CALIBATE_EN_MASK ((uint32_t)DAC_CTRL_CALxEN) +#define DACx_CTRL_WAVE_TYPE_MASK ((uint32_t)DAC_CTRL_WxEN) +#define DACx_CTRL_SINGFORMAT_EN_MASK ((uint32_t)DAC_CTRL_SINFORMATxEN) +#define DACx_CTRL_DMADOUBLEMODE_EN_MASK ((uint32_t)DAC_CTRL_DMADOUBLExEN) +#define DACx_CTRL_HIGH_DRIVER_EN_MASK ((uint32_t)DAC_CTRL_HDBxEN) +#define DACx_CTRL_DMA_UDRIEN_EN_MASK ((uint32_t)DAC_CTRL_DMAUDRxIEn) +#define DACx_CTRL_TRIGGER_EN_MASK ((uint32_t)DAC_CTRL_TxEN) +#define DACx_CTRL_BUFF_EN_MASK ((uint32_t)DAC_CTRL_BxEN) +#define DACx_CTRL_DMA_EN_MASK ((uint32_t)DAC_CTRL_DMAxEN) +#define DACx_CTRL_EN_MASK ((uint32_t)DAC_CTRL_DACxEN) + +/** DAC_SOTT **/ +#define DACx_CTRL_TRIGxEN_MASK (DAC_SOTTR_TRxEN) +#define DACy_CTRL_TRIGyEN_MASK (DAC_SOTTR_TRyEN) +#define DACx_CTRL_TRIGxSTEPEN_MASK (DAC_SOTTR_TRBxEN) +#define DACy_CTRL_TRIGySTEPEN_MASK (DAC_SOTTR_TRByEN) + +#define DACx_CTRL_TRIGALLEN_MASK (DAC_SOTTR_TRxEN | DAC_SOTTR_TRyEN) +#define DACy_CTRL_TRIGALLSTEPEN_MASK (DAC_SOTTR_TRBxEN | DAC_SOTTR_TRByEN) + +/** DAC_SELCTRL **/ +#define DACx_SELCTRL_SINCSEL_MASK (DAC_SETCTRL_SINCSELx) +#define DACx_SELCTRL_MAxSEL_MASK (DAC_SETCTRL_MAxSEL) +#define DACx_SELCTRL_TxSEL_MASK (DAC_SETCTRL_TxSEL) + +#define DACy_SELCTRL_SINCSEL_MASK (DAC_SETCTRL_SINCSELy) +#define DACy_SELCTRL_MAySEL_MASK (DAC_SETCTRL_MAySEL) +#define DACy_SELCTRL_TySEL_MASK (DAC_SETCTRL_TySEL) + +/** DAC_GCTRL **/ +#define DAC_GCTRL_SYNSEL_MASK (DAC_GCTRL_SYNSEL) + +#define DAC12_GCTRL_PCS_MASK (DAC12_GCTRL_PCS) +#define DAC3456_GCTRL_PCS_MASK (DAC3456_GCTRL_PCS) + +#define DAC_GCTRL_FREQ_MODE_MASK (DAC12_GCTRL_HFSEL) +#define DAC_HIGH_FREQ_MODE_DISABLE ((~DAC12_GCTRL_HFSEL)) +#define DAC_HIGH_FREQ_MODE_BELOW_80M (DAC12_GCTRL_HFSEL_0) +#define DAC_HIGH_FREQ_MODE_BELOW_160M (DAC12_GCTRL_HFSEL_1) +#define DAC_HIGH_FREQ_MODE_ABOVE_160M (DAC12_GCTRL_HFSEL_0|DAC12_GCTRL_HFSEL_1) + +/** DAC_CALC **/ +#define DAC_CALC_OTRIMxVALUE_MASK (DAC_CALC_OTRIMx) +#define DAC_CALC_OTRIMyVALUE_MASK (DAC_CALC_OTRIMy) + +/** DAC_STINC **/ +#define DAC_STINC_STINCDATAx_MASK (DAC_STINC_STINCDATAx) +#define DAC_STINC_STINCDATAy_MASK (DAC_STINC_STINCDATAy) +/** DAC_STRST **/ +#define DAC_STRST_STRSTDATAx_MASK (DAC_STRST_STRSTDATAx) +#define DAC_STRST_STRSTDATAy_MASK (DAC_STRST_STRSTDATAy) + +#define IS_DAC12(x) ((uint8_t)(x) < 2) +#define IS_DAC34(x) (((uint8_t)(x) == 2) || ((uint8_t)(x) == 3)) +#define IS_DAC56(x) (((uint8_t)(x) == 4) || ((uint8_t)(x) == 5)) + +#define IS_DAC13(x) ((((uint8_t)(x) == 0) || ((uint8_t)(x) == 2))) + +#define IS_DAC135(x) (((uint8_t)(x) % 2) == 0) +#define IS_DAC246(x) (((uint8_t)(x) % 2) != 0) + +/** DAC_data_alignment **/ +#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000000U) +#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004U) +#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000008U) + +/**DAC interrupts_definition **/ +#define DAC_INT_DMAUDRIEN (DAC_CTRL_DMAUDRxIEn) +#define DAC_INT_TROVIEN (DAC_CTRL_TROVCxIEN) + +/** DAC_STS Flag **/ +#define DAC_FLAG_DMAUDR (DAC_STS_DMAUDRx) +#define DAC_FLAG_CALCOMPLETE (DAC_STS_CALFLAGx) +#define DAC_FLAG_DORSTAT (DAC_STS_DORSTATx) +#define DAC_FLAG_TROVC (DAC_STS_TROVCFLAGx) +#define DAC_FLAG_VFLAGCOMP (DAC_STS_VFLAGxCOMP) + +/** DAC_STS INT Flag **/ +#define DAC_INTFLAG_DMAUDR (DAC_STS_DMAUDRx) +#define DAC_INTFLAG_TROVC (DAC_STS_TROVCFLAGx) + + +/** DAC_Exported_Functions **/ +void DAC_DeInit(DACX DACx); +void DAC_StructInit(DAC_InitType* DAC_InitStruct); +void DAC_Init(DACX DACx, DAC_InitType* DAC_InitStruct); + +void DAC_Enable(DACX DACx, FunctionalState Cmd); +void DAC_DmaEnable(DACX DACx, FunctionalState Cmd); +void DAC_CaliEnable(DACX DACx, FunctionalState Cmd); +void DAC_ConnetToExternalPinEnable(DACX DACx, FunctionalState Cmd); +void DAC_ConnetToOnChipEnable(DACX DACx, FunctionalState Cmd); +void DAC_HighDriveAbilityEnable(DACX DACx, FunctionalState Cmd); +void DAC_SignFormatModeEnable(DACX DACx, FunctionalState Cmd); +void DAC_DMADoubleDataModeEnable(DACX DACx, FunctionalState Cmd); + +void DAC_SoftTrgEnable(DACX DACx, FunctionalState Cmd); +void DAC_SoftTrgSawStepEnable(DACX DACx, FunctionalState Cmd); +void DAC_DualSoftwareTrgEnable(DAC_Module *Dual_DACx, FunctionalState Cmd); +void DAC_DualSoftwareTrgSawStepEnable(DAC_Module *Dual_DACx, FunctionalState Cmd); + +void DAC_WaveGenerationConfig(DACX DACx, uint32_t DAC_Wave); +void DAC_SetSawtoothResetValue(DACX DACx, uint16_t ResetValue); +void DAC_SetSawtoothStepValue(DACX DACx, uint16_t StepData); +void DAC_SetData(DACX DACx, uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChData(DAC_Module *Dual_DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetOutputDataVal(DACX DACx); + +FlagStatus DAC_GetFlagSts(DACX DACx, uint32_t DAC_FLAG); +void DAC_ClearFlag(DACX DACx, uint32_t DAC_FLAG); + +void DAC_ConfigInt(DACX DACx, uint32_t DAC_IT, FunctionalState Cmd); +FlagStatus DAC_GetIntSts(DACX DACx, uint32_t DAC_IT); +void DAC_ClearITPendingBit(DACX DACx, uint32_t DAC_IT); + +void DAC_ConfigClkPrescaler(DAC_Module* DACx, uint8_t Prescaler); +void DAC_SetHighFrequencyMode(DAC_Module* DACx, uint32_t mode); +void DAC_SetUserTrimming(DACX DACx, uint8_t TrimmingValue); +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_DAC_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dbg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dbg.h new file mode 100644 index 0000000000..0be5790509 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dbg.h @@ -0,0 +1,161 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dbg.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_DBG_H__ +#define __N32H76x_78x_DBG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32h76x_78x.h" + + +#define DBG_FLASH_SIZE_MASK ((uint32_t)0x000000C0U) +#define DBG_REV_NUM_MASK ((uint32_t)0xFF000000U) +#define DBG_DEV_NUM_MASK ((uint32_t)0x00FFF000U) + +#define REGISTER_OFFSET_POS ((uint8_t)0x18U) +#define REGISTER_OFFSET_MASK ((uint32_t)0xFF000000U) +#define REGISTER_DBG_CTRL_OFFSET ((uint32_t)0x04000000U) +#define REGISTER_M7_APB1_OFFSET ((uint32_t)0x08000000U) +#define REGISTER_M7_APB2_OFFSET ((uint32_t)0x10000000U) +#define REGISTER_M7_APB5_OFFSET ((uint32_t)0x18000000U) +#define REGISTER_M7_APB6_OFFSET ((uint32_t)0x20000000U) + + + +#define DBG_TRGIO_INPUT_DIRECTION ((uint32_t)0x00000000U) +#define DBG_TRGIO_OUTPUT_DIRECTION (DBG_CTRL_TRACE_IOEN) + +#define DBG_M7SLEEP (DBG_CTRL_M7SLEEP | REGISTER_DBG_CTRL_OFFSET) +#define DBG_M7STOP (DBG_CTRL_M7STOP | REGISTER_DBG_CTRL_OFFSET) +#define DBG_M7STANDBY (DBG_CTRL_M7STBY | REGISTER_DBG_CTRL_OFFSET) +#define DBG_M4SLEEP (DBG_CTRL_M4SLEEP | REGISTER_DBG_CTRL_OFFSET) +#define DBG_M4STOP (DBG_CTRL_M4STOP | REGISTER_DBG_CTRL_OFFSET) +#define DBG_M4STANDBY (DBG_CTRL_M4STBY | REGISTER_DBG_CTRL_OFFSET) + +#define DBG_WWDG1_STOP (DBG_M7APB6FZ_WWDG1_STOP | REGISTER_M7_APB6_OFFSET ) + +#define DBG_ATIM3_STOP (DBG_M7APB5FZ_ATIM3_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_ATIM4_STOP (DBG_M7APB5FZ_ATIM4_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_I2C7SMBUS_TIMEOUT (DBG_M7APB5FZ_I2C7_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_I2C8SMBUS_TIMEOUT (DBG_M7APB5FZ_I2C8_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_I2C9SMBUS_TIMEOUT (DBG_M7APB5FZ_I2C9_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_I2C10SMBUS_TIMEOUT (DBG_M7APB5FZ_I2C10_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_IWDG1_STOP (DBG_M7APB5FZ_IWDG1_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_IWDG2_STOP (DBG_M7APB5FZ_IWDG2_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_LPTIM1_STOP (DBG_M7APB5FZ_LPTIM1_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_LPTIM2_STOP (DBG_M7APB5FZ_LPTIM2_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_LPTIM3_STOP (DBG_M7APB5FZ_LPTIM3_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_LPTIM4_STOP (DBG_M7APB5FZ_LPTIM4_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_LPTIM5_STOP (DBG_M7APB5FZ_LPTIM5_STOP | REGISTER_M7_APB5_OFFSET) +#define DBG_RTC_STOP (DBG_M7APB5FZ_RTC_STOP | REGISTER_M7_APB5_OFFSET) + +#define DBG_CANFD3_STOP (DBG_M7APB2FZ_CANFD3_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_CANFD4_STOP (DBG_M7APB2FZ_CANFD4_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_CANFD7_STOP (DBG_M7APB2FZ_CANFD7_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_CANFD8_STOP (DBG_M7APB2FZ_CANFD8_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_I2C4SMBUS_TIMEOUT (DBG_M7APB2FZ_I2C4_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_I2C5SMBUS_TIMEOUT (DBG_M7APB2FZ_I2C5_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_I2C6SMBUS_TIMEOUT (DBG_M7APB2FZ_I2C6_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_ATIM1_STOP (DBG_M7APB2FZ_ATIM1_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_ATIM2_STOP (DBG_M7APB2FZ_ATIM2_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_GTIMA1_STOP (DBG_M7APB2FZ_GTIMA1_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_GTIMA2_STOP (DBG_M7APB2FZ_GTIMA2_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_GTIMA3_STOP (DBG_M7APB2FZ_GTIMA3_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_SHRTIM1_STOP (DBG_M7APB2FZ_SHRTIM1_STOP | REGISTER_M7_APB2_OFFSET) +#define DBG_SHRTIM2_STOP (DBG_M7APB2FZ_SHRTIM2_STOP | REGISTER_M7_APB2_OFFSET) + +#define DBG_BTIM1_STOP (DBG_M7APB1FZ_BTIM1_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_BTIM2_STOP (DBG_M7APB1FZ_BTIM2_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_BTIM3_STOP (DBG_M7APB1FZ_BTIM3_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_BTIM4_STOP (DBG_M7APB1FZ_BTIM4_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMA4_STOP (DBG_M7APB1FZ_GTIMA4_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMA5_STOP (DBG_M7APB1FZ_GTIMA5_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMA6_STOP (DBG_M7APB1FZ_GTIMA6_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMA7_STOP (DBG_M7APB1FZ_GTIMA7_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMB1_STOP (DBG_M7APB1FZ_GTIMB1_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMB2_STOP (DBG_M7APB1FZ_GTIMB2_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_GTIMB3_STOP (DBG_M7APB1FZ_GTIMB3_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_I2C1SMBUS_TIMEOUT (DBG_M7APB1FZ_I2C1_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_I2C2SMBUS_TIMEOUT (DBG_M7APB1FZ_I2C2_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_I2C3SMBUS_TIMEOUT (DBG_M7APB1FZ_I2C3_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_WWDG2_STOP (DBG_M7APB1FZ_WWDG2_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_CANFD1_STOP (DBG_M7APB1FZ_CANFD1_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_CANFD2_STOP (DBG_M7APB1FZ_CANFD2_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_CANFD5_STOP (DBG_M7APB1FZ_CANFD5_STOP | REGISTER_M7_APB1_OFFSET) +#define DBG_CANFD6_STOP (DBG_M7APB1FZ_CANFD6_STOP | REGISTER_M7_APB1_OFFSET) + + + +uint32_t DBG_GetRevNum(void); +uint32_t DBG_GetDevNum(void); + +void DBG_SetExternalTriggerPinDirection(uint32_t PinDirection); +void DBG_M7ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd); +void DBG_M4ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd); + +uint32_t DBG_GetFlashSize(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76x_78x_DBG_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dcmu.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dcmu.h new file mode 100644 index 0000000000..7eef8b6d4f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dcmu.h @@ -0,0 +1,197 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dcmu.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_DCMU_H__ +#define __N32H76X_78X_DCMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** n32h76x_78x_StdPeriph_Driver **/ + +/** DCMU_Exported_Constants **/ + +/** DCMU Min and Max Define **/ +#define DCMU_TXMSGID_MIN (0U) /* DCMU Transmit Messaging Register ID Min */ +#define DCMU_TXMSGID_MAX (3U) /* DCMU Transmit Messaging Register ID Max */ +#define DCMU_RXMSGID_MIN (0U) /* DCMU Receive Messaging Register ID Min */ +#define DCMU_RXMSGID_MAX (3U) /* DCMU Receive Messaging Register ID Max */ +#define DCMU_GPIRID_MIN (0U) /* DCMU General Purpose Interrupt Request ID Min */ +#define DCMU_GPIRID_MAX (3U) /* DCMU General Purpose Interrupt Request ID Max */ +#define DCMU_FLAGID_MIN (0U) /* DCMU Flag ID Min */ +#define DCMU_FLAGID_MAX (2U) /* DCMU Flag ID Max */ + +#define DCMU_CTRL_GPIE0_MASK (DCMU_CTRL_GPIE0) +#define DCMU_CTRL_GPIE1_MASK (DCMU_CTRL_GPIE1) +#define DCMU_CTRL_GPIE2_MASK (DCMU_CTRL_GPIE2) +#define DCMU_CTRL_GPIE3_MASK (DCMU_CTRL_GPIE3) +#define DCMU_CTRL_TEIE0_MASK (DCMU_CTRL_TEIE0) +#define DCMU_CTRL_TEIE1_MASK (DCMU_CTRL_TEIE1) +#define DCMU_CTRL_TEIE2_MASK (DCMU_CTRL_TEIE2) +#define DCMU_CTRL_TEIE3_MASK (DCMU_CTRL_TEIE3) + +#define DCMU_CTRL_RFIE0_MASK (DCMU_CTRL_RFIE0) +#define DCMU_CTRL_RFIE1_MASK (DCMU_CTRL_RFIE1) +#define DCMU_CTRL_RFIE2_MASK (DCMU_CTRL_RFIE2) +#define DCMU_CTRL_RFIE3_MASK (DCMU_CTRL_RFIE3) + +#define DCMU_CTRL_GPIE_ALL_MASK (DCMU_CTRL_GPIE0 | DCMU_CTRL_GPIE1 | DCMU_CTRL_GPIE2 | DCMU_CTRL_GPIE3) +#define DCMU_CTRL_TEIE_ALL_MASK (DCMU_CTRL_TEIE0 | DCMU_CTRL_TEIE1 | DCMU_CTRL_TEIE2 | DCMU_CTRL_TEIE3) +#define DCMU_CTRL_RFIE_ALL_MASK (DCMU_CTRL_RFIE0 | DCMU_CTRL_RFIE1 | DCMU_CTRL_RFIE2 | DCMU_CTRL_RFIE3) +#define DCMU_CTRL_ALL_IE_MASK (DCMU_CTRL_GPIE_ALL_MASK|DCMU_CTRL_TEIE_ALL_MASK|DCMU_CTRL_RFIE_ALL_MASK) + +#define DCMU_CTRL_GPIR0_MASK (DCMU_CTRL_GPIR0) +#define DCMU_CTRL_GPIR1_MASK (DCMU_CTRL_GPIR1) +#define DCMU_CTRL_GPIR2_MASK (DCMU_CTRL_GPIR2) +#define DCMU_CTRL_GPIR3_MASK (DCMU_CTRL_GPIR3) +#define DCMU_CTRL_GPIR_ALL_MASK (DCMU_CTRL_GPIR0_MASK | DCMU_CTRL_GPIR1_MASK | DCMU_CTRL_GPIR2_MASK | DCMU_CTRL_GPIR3_MASK) + +#define DCMU_CTRL_RST_MASK (DCMU_CTRL_RST) + +#define DCMU_CTRL_TXFN0_MASK (DCMU_CTRL_TXFN0) +#define DCMU_CTRL_TXFN1_MASK (DCMU_CTRL_TXFN1) +#define DCMU_CTRL_TXFN2_MASK (DCMU_CTRL_TXFN2) +#define DCMU_CTRL_TXFN_ALL_MASK (DCMU_CTRL_TXFN0_MASK | DCMU_CTRL_TXFN1_MASK | DCMU_CTRL_TXFN2_MASK) + +#define DCMU_STS_GPIF0_MASK (DCMU_STS_GPIF0) +#define DCMU_STS_GPIF1_MASK (DCMU_STS_GPIF1) +#define DCMU_STS_GPIF2_MASK (DCMU_STS_GPIF2) +#define DCMU_STS_GPIF3_MASK (DCMU_STS_GPIF3) +#define DCMU_STS_TEF0_MASK (DCMU_STS_TEF0) +#define DCMU_STS_TEF1_MASK (DCMU_STS_TEF1) +#define DCMU_STS_TEF2_MASK (DCMU_STS_TEF2) +#define DCMU_STS_TEF3_MASK (DCMU_STS_TEF3) +#define DCMU_STS_RFF0_MASK (DCMU_STS_RFF0) +#define DCMU_STS_RFF1_MASK (DCMU_STS_RFF1) +#define DCMU_STS_RFF2_MASK (DCMU_STS_RFF2) +#define DCMU_STS_RFF3_MASK (DCMU_STS_RFF3) + +#define DCMU_STS_GPIF_ALL_MASK (DCMU_STS_GPIF0_MASK|DCMU_STS_GPIF1_MASK|DCMU_STS_GPIF2_MASK|DCMU_STS_GPIF3_MASK) +#define DCMU_STS_TEF_ALL_MASK (DCMU_STS_TEF0_MASK|DCMU_STS_TEF1_MASK|DCMU_STS_TEF2_MASK|DCMU_STS_TEF3_MASK) +#define DCMU_STS_RFF_ALL_MASK (DCMU_STS_RFF0_MASK|DCMU_STS_RFF1_MASK|DCMU_STS_RFF2_MASK|DCMU_STS_RFF3_MASK) + +#define DCMU_STS_EPF_MASK (DCMU_STS_EPF) +#define DCMU_STS_FUPF_MASK (DCMU_STS_FUPF) +#define DCMU_STS_RSTF_MASK (DCMU_STS_RSTF) + +#define DCMU_STS_RCVFN0_MASK (DCMU_STS_RCVFN0) +#define DCMU_STS_RCVFN1_MASK (DCMU_STS_RCVFN1) +#define DCMU_STS_RCVFN2_MASK (DCMU_STS_RCVFN2) +#define DCMU_STS_RCVFN_ALL_MASK (DCMU_STS_RCVFN0_MASK|DCMU_STS_RCVFN1_MASK|DCMU_STS_RCVFN2_MASK) + + +/** DCMU_Exported_Typedef_t **/ +typedef enum dcmu_wait_mode +{ + NON_BLOCKING =0, + BLOCKING + +}dcmu_wait_mode_t; + +typedef enum dcmu_txmsg_idx +{ + TXMSG_IDX0 = 0, + TXMSG_IDX1 , + TXMSG_IDX2 , + TXMSG_IDX3 + +}dcmu_txmsg_idx_t; + +typedef enum dcmu_rcvmsg_idx +{ + RCVMSG_IDX0 = 0, + RCVMSG_IDX1 , + RCVMSG_IDX2 , + RCVMSG_IDX3 + +}dcmu_rcvmsg_idx_t; + +typedef enum dcmu_gpi_idx +{ + GPI_IDX0 = 0, + GPI_IDX1 , + GPI_IDX2 , + GPI_IDX3 + +}dcmu_gpi_idx_t; + + + + +/** DCMU_Exported_Functions **/ + +void DCMU_DeInit( void ); + +#if defined(CORE_CM7) +void DCMU_SelfReset( void ); +#endif + +void DCMU_TransmitMsg( uint8_t TxIdx, uint32_t TxMsgData, dcmu_wait_mode_t Mode); +uint32_t DCMU_ReceiveMsg( uint8_t RcvIdx, dcmu_wait_mode_t Mode); +void DCMU_Set3BitFlagNumbers( uint8_t FlagData, dcmu_wait_mode_t Mode); +uint8_t DCMU_Get3BitFlagNumbers( void ); +uint32_t DCMU_GetStatusFlags( uint32_t StatusMask); +uint32_t DCMU_GetIntPendingFlags( uint32_t IntPendingMask); +void DCMU_ClearIntPendingFlags( uint32_t GPIntPendingMask); +void DCMU_ConfigInt( uint32_t IntMask, FunctionalState Cmd); +void DCMU_RequestGPInt( uint32_t ReqGPIntMask); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_DCMU_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dma.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dma.h new file mode 100644 index 0000000000..e18255f88e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dma.h @@ -0,0 +1,448 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dma.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_DMA_H__ +#define __N32H76x_78x_DMA_H__ + + +#include +#include "n32h76x_78x.h" + + +#if defined(DMA1) || defined(DMA2) || defined(DMA3) + + + +/** DMA Channel Numbers per DMA Controller definition **/ +#define DMA_NUM_CHANNELS 8 + +/** DMA Channel Enable/Disable definition **/ +#define DMA_CH_ENABLE ((uint32_t)(DMA_CHEN_CH0WEN | DMA_CHEN_CH0)) +#define DMA_CH_DISABLE ((uint32_t)(DMA_CHEN_CH0WEN & (~DMA_CHEN_CH0))) + +/** DMA Interrupt Mask/Unmask definition **/ +#define DMA_INT_UNMASK ((uint32_t)(DMA_TCINTMSK_CH0WEN | DMA_TCINTMSK_CH0)) +#define DMA_INT_MASK ((uint32_t)(DMA_TCINTMSK_CH0WEN & (~DMA_TCINTMSK_CH0))) + +/** DMA Source Single Transaction Request Enable/Disable definition **/ +#define DMA_SSTR_ENABLE ((uint32_t)(DMA_SRCSGTREQ_CH0WEN | DMA_SRCSGTREQ_CH0)) +#define DMA_SSTR_DISABLE ((uint32_t)(DMA_SRCSGTREQ_CH0WEN & (~DMA_SRCSGTREQ_CH0))) + +/** DMA Source Last Transaction Request Enable/Disable definition **/ +#define DMA_SLTR_ENABLE ((uint32_t)(DMA_SRCLTREQ_CH0WEN | DMA_SRCLTREQ_CH0)) +#define DMA_SLTR_DISABLE ((uint32_t)(DMA_SRCLTREQ_CH0WEN & (~DMA_SRCLTREQ_CH0))) + +/** DMA Source Transaction Request Enable/Disable definition **/ +#define DMA_STR_ENABLE ((uint32_t)(DMA_SRCSWTREQ_CH0WEN | DMA_SRCSWTREQ_CH0)) +#define DMA_STR_DISABLE ((uint32_t)(DMA_SRCSWTREQ_CH0WEN & (~DMA_SRCSWTREQ_CH0))) + +/** DMA Destination Single Transaction Request Enable/Disable definition **/ +#define DMA_DSTR_ENABLE ((uint32_t)(DMA_DSTSGTREQ_CH0WEN | DMA_DSTSGTREQ_CH0)) +#define DMA_DSTR_DISABLE ((uint32_t)(DMA_DSTSGTREQ_CH0WEN & (~DMA_DSTSGTREQ_CH0))) + +/** DMA Destination Last Transaction Request Enable/Disable definition **/ +#define DMA_DLTR_ENABLE ((uint32_t)(DMA_DSTLTREQ_CH0WEN | DMA_DSTLTREQ_CH0)) +#define DMA_DLTR_DISABLE ((uint32_t)(DMA_DSTLTREQ_CH0WEN & (~DMA_DSTLTREQ_CH0))) + +/** DMA Destination Transaction Request Enable/Disable definition **/ +#define DMA_DTR_ENABLE ((uint32_t)(DMA_DSTSWTREQ_CH0WEN | DMA_DSTSWTREQ_CH0)) +#define DMA_DTR_DISABLE ((uint32_t)(DMA_DSTSWTREQ_CH0WEN & (~DMA_DSTSWTREQ_CH0))) + +/** DMA Channel Bus Lock Level definition **/ +#define DMA_CH_BUS_LOCK_LEVEL_OCDMATFR ((uint64_t)(DMA_CHNCFG_LOCKBL_0 \ + & DMA_CHNCFG_LOCKBL_1)) /* Over complete DMA transfer */ +#define DMA_CH_BUS_LOCK_LEVEL_OCDMABLKTFR ((uint64_t)(DMA_CHNCFG_LOCKBL_0)) /* Over complete DMA block transfer */ +#define DMA_CH_BUS_LOCK_LEVEL_OCDMATRAN ((uint64_t)(DMA_CHNCFG_LOCKBL_1)) /* Over complete DMA transfer */ + +/** DMA Channel Lock Level definition **/ +#define DMA_CH_LOCK_LEVEL_OCDMATFR ((uint64_t)(DMA_CHNCFG_LOCKCHL_0 \ + & DMA_CHNCFG_LOCKCHL_1)) /* Over complete DMA transfer */ +#define DMA_CH_LOCK_LEVEL_OCDMABLKTFR ((uint64_t)(DMA_CHNCFG_LOCKCHL_0)) /* Over complete DMA block transfer */ +#define DMA_CH_LOCK_LEVEL_OCDMATRAN ((uint64_t)(DMA_CHNCFG_LOCKCHL_1)) /* Over complete DMA transfer */ + +/** DMA Channel interrupt event definition **/ +#define DMA_EVENT_TRANSFER_COMPLETE ((uint32_t)DMA_TCINTSTS_CH0) /* IntTfr: Transfer complete interrupt event */ +#define DMA_EVENT_BLOCK_TRANSFER_COMPLETE ((uint32_t)DMA_BTCINTSTS_CH0) /* IntBlock: Block transfer complete interrupt event */ +#define DMA_EVENT_SRC_TRANSACTION_COMPLETE ((uint32_t)DMA_STCINTSTS_CH0) /* IntSrcTran: Source transaction complete interrupt event */ +#define DMA_EVENT_DST_TRANSACTION_COMPLETE ((uint32_t)DMA_DTCINTSTS_CH0) /* IntDstTran: Destination transaction complete interrupt event */ +#define DMA_EVENT_ERROR ((uint32_t)DMA_ERRINTSTS_CH0) /* IntErr: Error interrupt event */ + + +/** DMA Channel Number typedef **/ +typedef enum +{ + DMA_CHANNEL_0 = 0x0UL, + DMA_CHANNEL_1 = 0x1UL, + DMA_CHANNEL_2 = 0x2UL, + DMA_CHANNEL_3 = 0x3UL, + DMA_CHANNEL_4 = 0x4UL, + DMA_CHANNEL_5 = 0x5UL, + DMA_CHANNEL_6 = 0x6UL, + DMA_CHANNEL_7 = 0x7UL +} DMA_ChNumType; + +/** DMA Channel Status typedef **/ +typedef enum +{ + DMA_CH_STS_OK = 0, /* DMA status OK */ + DMA_CH_STS_ERROR, /* DMA status Error */ + DMA_CH_STS_BUSY /* DMA status Busy */ +} DMA_ChStatusType; + +/** DMA channel transfer types typedef **/ +typedef enum +{ + DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK, /* Single block */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD, /* Multi-block: src address contiguous, dst address reload */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS, /* Multi-block: src address reload, dst address contiguous */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD, /* Multi-block: src address reload, dst address reload */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED, /* Multi-block: src address contiguous, dst address linked */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED, /* Multi-block: src address reload, dst address linked */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS, /* Multi-block: src address linked, dst address contiguous */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD, /* Multi-block: src address linked, dst address reload */ + DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED /* Multi-block: src address linked, dst address linked */ +} DMA_ChTfrType; + +/** DMA channel transfer flow modes typedef **/ +typedef enum +{ + DMA_CH_TRANSFER_FLOW_M2M_DMA = 0x0UL, /* Memory to memory (DMA flow controller) */ + DMA_CH_TRANSFER_FLOW_M2P_DMA = 0x1UL, /* Memory to peripheral (DMA flow controller) */ + DMA_CH_TRANSFER_FLOW_P2M_DMA = 0x2UL, /* Peripheral to memory (DMA flow controller) */ + DMA_CH_TRANSFER_FLOW_P2P_DMA = 0x3UL, /* Peripheral to peripheral (DMA flow controller) */ + DMA_CH_TRANSFER_FLOW_P2M_PER = 0x4UL, /* Peripheral to memory (Peripheral flow controller) */ + DMA_CH_TRANSFER_FLOW_P2P_SRCPER = 0x5UL, /* Peripheral to peripheral (Source peripheral flow controller) */ + DMA_CH_TRANSFER_FLOW_M2P_PER = 0x6UL, /* Memory to peripheral (Peripheral flow controller) */ + DMA_CH_TRANSFER_FLOW_P2P_DSTPER = 0x7UL /* Peripheral to peripheral (Destination peripheral flow controller) */ +} DMA_ChTfrFlowType; + +/** DMA channel master interface layer select typedef **/ +typedef enum +{ + DMA_CH_AHB_MASTER_1 = 0x0UL, /* AHB master 1 */ + DMA_CH_AHB_MASTER_2 = 0x1UL /* AHB master 2 */ +} DMA_ChMstSelType; + +/** DMA channel valid burst length value typedef **/ +typedef enum +{ + DMA_CH_BURST_LENGTH_1 = 0x0UL, /* Burst length: 1 data item */ + DMA_CH_BURST_LENGTH_4 = 0x1UL, /* Burst length: 4 data items */ + DMA_CH_BURST_LENGTH_8 = 0x2UL, /* Burst length: 8 data items */ + DMA_CH_BURST_LENGTH_16 = 0x3UL, /* Burst length: 16 data items */ + DMA_CH_BURST_LENGTH_32 = 0x4UL, /* Burst length: 32 data items */ + DMA_CH_BURST_LENGTH_64 = 0x5UL, /* Burst length: 64 data items */ + DMA_CH_BURST_LENGTH_128 = 0x6UL, /* Burst length: 128 data items */ + DMA_CH_BURST_LENGTH_256 = 0x7UL /* Burst length: 256 data items */ +} DMA_ChBurstLenType; + +/** DMA channel valid transfer width values typedef **/ +typedef enum +{ + DMA_CH_TRANSFER_WIDTH_8 = 0x0UL, /* 8-bit transfer width */ + DMA_CH_TRANSFER_WIDTH_16 = 0x1UL, /* 16-bit transfer width */ + DMA_CH_TRANSFER_WIDTH_32 = 0x2UL, /* 32-bit transfer width */ +} DMA_ChTfrWidthType; + +/** DMA channel address count mode typedef **/ +typedef enum +{ + DMA_CH_ADDRESS_COUNT_MODE_INCREMENT = 0x0UL, /* Address count mode: increment */ + DMA_CH_ADDRESS_COUNT_MODE_DECREMENT = 0x1UL, /* Address count mode: decrement */ + DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE = 0x2UL /* Address count mode: no change */ +} DMA_ChAddrCountType; + +/** DMA channel priorities typedef **/ +typedef enum +{ + DMA_CH_PRIORITY_0 = 0x0UL, /* DMA channel priority 0 (low) */ + DMA_CH_PRIORITY_1 = 0x1UL, /* DMA channel priority 1 */ + DMA_CH_PRIORITY_2 = 0x2UL, /* DMA channel priority 2 */ + DMA_CH_PRIORITY_3 = 0x3UL, /* DMA channel priority 3 */ + DMA_CH_PRIORITY_4 = 0x4UL, /* DMA channel priority 4 */ + DMA_CH_PRIORITY_5 = 0x5UL, /* DMA channel priority 5 */ + DMA_CH_PRIORITY_6 = 0x6UL, /* DMA channel priority 6 */ + DMA_CH_PRIORITY_7 = 0x7UL /* DMA channel priority 7 (high) */ +} DMA_ChPriorType; + +/** DMA channel Source handshake interface typedef **/ +typedef enum +{ + DMA_CH_SRC_HANDSHAKING_HARDWARE = 0x0UL, /* Source: hardware handshake */ + DMA_CH_SRC_HANDSHAKING_SOFTWARE = 0x1UL /* Source: software handshake */ +} DMA_ChSrcHsType; + +/** DMA channel Destination handshake interface typedef **/ +typedef enum +{ + DMA_CH_DST_HANDSHAKING_HARDWARE = 0x0UL, /* Destination: hardware handshake */ + DMA_CH_DST_HANDSHAKING_SOFTWARE = 0x1UL /* Destination: software handshake */ +} DMA_ChDstHsType; + +/** DMA channel hardware handshaking interface, available when DMA is flow controller typedef **/ +typedef enum +{ + DMA_CH_HARDWARE_HANDSHAKING_IF_0 = 0x0UL, /* Hardware handshaking interface 0 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_1 = 0x1UL, /* Hardware handshaking interface 1 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_2 = 0x2UL, /* Hardware handshaking interface 2 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_3 = 0x3UL, /* Hardware handshaking interface 3 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_4 = 0x4UL, /* Hardware handshaking interface 4 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_5 = 0x5UL, /* Hardware handshaking interface 5 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_6 = 0x6UL, /* Hardware handshaking interface 6 */ + DMA_CH_HARDWARE_HANDSHAKING_IF_7 = 0x7UL, /* Hardware handshaking interface 7 */ +} DMA_ChHwHsIfType; + +/* DMA channel handshaking interface polarity typedef */ +typedef enum +{ + DMA_CH_HANDSHAKING_IF_POL_H = 0x0UL, /* Active HIGH */ + DMA_CH_HANDSHAKING_IF_POL_L = 0x1UL, /* Active LOW */ +} DMA_ChHsIfPolType; + +/** DMA Channel events typedef **/ +typedef enum +{ + DMA_CH_EVENT_TRANSFER_COMPLETE = 0x1UL, /* Transfer complete event */ + DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE = 0x2UL, /* Block transfer complete event */ + DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE = 0x4UL, /* Source transaction complete event */ + DMA_CH_EVENT_DST_TRANSACTION_COMPLETE = 0x8UL, /* Destination transaction complete event */ + DMA_CH_EVENT_ERROR = 0x10UL /* DMA error event */ +} DMA_ChEventType; + +/** DMA Channel Transaction types typedef **/ +typedef enum +{ + DMA_CH_TRANSACTION_TYPE_SINGLE, /* Single DMA transaction */ + DMA_CH_TRANSACTION_TYPE_BURST /* Burst transaction */ +} DMA_ChTransacType; + + + +/** Start of section using anonymous unions **/ +#if defined (__CC_ARM) + /* Save the current compiler state (Keil only) */ + #pragma push + /* Enable anonymous unions */ + #pragma anon_unions +#elif defined(__ICCARM__) + /* Enable anonymous consortia */ + #pragma language=extended +#elif defined(__GNUC__) + /* GCC supports anonymous unions by default */ +#else + #warning "Anonymous unions may not be supported by this compiler. Check compiler documentation." +#endif + +/** DMA channel linked list item structure, 32-bits alignment **/ +typedef struct __DMA_LinkListItemType +{ + uint32_t SrcAddr; /* Source address */ + uint32_t DstAddr; /* Destination address */ + struct __DMA_LinkListItemType *pNext; /* The next linked list item pointer */ + + union + { + uint32_t ChCtrlL32; + struct + { + uint32_t IntEn: 1; /* Enable interrupts? */ + uint32_t DstTfrWidth: 3; /* Destination transfer width */ + uint32_t SrcTfrWidth: 3; /* Source transfer width */ + uint32_t DstAddrCountMode: 2; /* Destination address count mode */ + uint32_t SrcAddrCountMode: 2; /* Source address count mode */ + uint32_t DstBurstLen: 3; /* Destination burst length */ + uint32_t SrcBurstLen: 3; /* Source burst length */ + uint32_t SrcGatherEn: 1; /* Enable source gather? */ + uint32_t DstScatterEn: 1; /* Enable destination scatter? */ + uint32_t : 1; + uint32_t TfrTypeFlowCtrl: 3; /* Transfer Type and Flow Control */ + uint32_t : 4; + uint32_t DstLinkedListEn: 1; /* Enable destination linked list? */ + uint32_t SrcLinkedListEn: 1; /* Enable source linked list? */ + uint32_t : 3; + }; + }; + + union + { + uint32_t ChCtrlH32; + struct + { + uint32_t BlkTfrSize: 12; /* DMA block size for DMA controlled transfers [max. 4095]*/ + uint32_t DoneFlag: 1; /* Block transfer complete flag */ + uint32_t : 19; + }; + }; + +} DMA_LinkListItemType; + +/** DMA Channel Initialize configuration structure **/ +typedef struct +{ + union + { + uint64_t ChCtrl; + struct + { + uint64_t IntEn: 1; /* Enable interrupts? */ + uint64_t DstTfrWidth: 3; /* Destination transfer width */ + uint64_t SrcTfrWidth: 3; /* Source transfer width */ + uint64_t DstAddrCountMode: 2; /* Destination address count mode */ + uint64_t SrcAddrCountMode: 2; /* Source address count mode */ + uint64_t DstBurstLen: 3; /* Destination burst length */ + uint64_t SrcBurstLen: 3; /* Source burst length */ + uint64_t SrcGatherEn: 1; /* Enable source gather? */ + uint64_t DstScatterEn: 1; /* Enable destination scatter? */ + uint64_t : 1; + uint64_t TfrTypeFlowCtrl: 3; /* Transfer Type and Flow Control */ + uint64_t DstMasterSelect: 2; /* Destination Master Interface layer */ + uint64_t SrcMasterSelect: 2; /* Source Master Interface layer */ + uint64_t : 5; + uint64_t BlkTfrSize: 12; /* DMA block size for DMA controlled transfers [max. 4095]*/ + uint64_t : 20; + }; + }; + + uint32_t SrcAddr; /* Source address */ + uint32_t DstAddr; /* Destination address */ + DMA_LinkListItemType* pLinkListItem; /* Linked list item pointer */ + + union + { + uint32_t SrcGatherCtrl; + struct + { + uint32_t SrcGatherInterval: 20; /* Source gather interval */ + uint32_t SrcGatherCount: 12; /* Source gather count */ + }; + }; + + union + { + uint32_t DstScatterCtrl; + struct + { + uint32_t DstScatterInterval: 20; /* Destination scatter interval */ + uint32_t DstScatterCount: 12; /* Destination scatter count */ + }; + }; + + DMA_ChTfrType TfrType; /* DMA transfer type */ + DMA_ChPriorType ChannelPriority; /* DMA channel priority */ + DMA_ChSrcHsType SrcHandshaking; /* DMA source handshaking interface */ + DMA_ChHwHsIfType SrcHsInterface; /* DMA source assigned handshaking interface */ + DMA_ChHsIfPolType SrcHsInterfacePol; /* DMA source handshaking interface polarity */ + DMA_ChDstHsType DstHandshaking; /* DMA destination handshaking interface */ + DMA_ChHwHsIfType DstHsInterface; /* DMA destination assigned handshaking interface */ + DMA_ChHsIfPolType DstHsInterfacePol; /* DMA destination handshaking interface polarity */ + +} DMA_ChInitType; + + +/** End of section using anonymous unions (Keil only) **/ +#if defined (__CC_ARM) + /* Restore compiler settings */ + #pragma pop +#endif + + +void DMA_ControllerCmd(DMA_Module *const DMAy, FunctionalStatus Cmd); +bool DMA_ControllerIsEnabled(DMA_Module *const DMAy); +void DMA_ChannelCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); +bool DMA_ChannelIsEnabled(DMA_Module *const DMAy, DMA_ChNumType ChNum); +DMA_ChStatusType DMA_ChannelInit(DMA_Module *const DMAy, DMA_ChInitType *const DMA_ChInitParam, DMA_ChNumType ChNum); +void DMA_ChannelStructInit(DMA_ChInitType *const DMA_ChInitParam); +void DMA_ChannelSuspend(DMA_Module *const DMAy, DMA_ChNumType ChNum); +bool DMA_ChannelIsSuspended(DMA_Module *const DMAy, DMA_ChNumType ChNum); +void DMA_ChannelResume(DMA_Module *const DMAy, DMA_ChNumType ChNum); + +void DMA_ChannelEventCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Event, FunctionalStatus Cmd); +void DMA_ClearChannelEventStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Event); +uint8_t DMA_GetCombinedStatus(DMA_Module *const DMAy); +INTStatus DMA_GetChannelIntTfrStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum); +INTStatus DMA_GetChannelIntBlockStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum); +INTStatus DMA_GetChannelIntSrcTranStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum); +INTStatus DMA_GetChannelIntDstTranStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum); +INTStatus DMA_GetChannelIntErrStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum); + +void DMA_ChannelSourceGatherCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); +void DMA_SetChannelSourceGather(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Interval, uint16_t Count); +void DMA_ChannelDestinationScatterCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); +void DMA_SetChannelDestinationScatter(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Interval, uint16_t Count); + +void DMA_SetChannelSourceAddress(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t *pAddr); +void DMA_SetChannelDestinationAddress(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t *pAddr); +void DMA_SetChannelBlockSize(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Size); +uint16_t DMA_GetTransferredNumber(DMA_Module *const DMAy, DMA_ChNumType ChNum); +void DMA_SetChannelLinkedListPointer(DMA_Module *const DMAy, DMA_ChNumType ChNum, DMA_LinkListItemType* pStr); +void DMA_TriggerSourceRequest(DMA_Module *const DMAy, DMA_ChNumType ChNum, DMA_ChTransacType Type, bool isLast); +void DMA_TriggerDestinationRequest(DMA_Module *const DMAy, DMA_ChNumType ChNum, DMA_ChTransacType Type, bool isLast); +void DMA_ChannelSourceAddressReloadCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); +void DMA_ChannelDestinationAddressReloadCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); + +void DMA_ChannelBusLockCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); +void DMA_ChannelLockCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd); +void DMA_SetChannelBusLockLevel(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint64_t Level); +void DMA_SetChannelLockLevel(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint64_t Level); + + + +#ifdef __cplusplus +} +#endif + + +#endif /* ( defined(DMA1) || defined(DMA2) || defined(DMA3) ) */ +#endif /* __N32H76x_H78x_DMA_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dmamux.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dmamux.h new file mode 100644 index 0000000000..8117877bba --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dmamux.h @@ -0,0 +1,534 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dmamux.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef N32H76x_78x_DMAMUX_H +#define N32H76x_78x_DMAMUX_H + +#include "n32h76x_78x.h" + + +typedef enum +{ + DMAMUX1_ID =0, + DMAMUX2_ID =1 +}DMAMUX_ID; + + +/* Define used to get DMAMUX CHxCTRL register size */ +#define DMAMUX_CHCTRL_SIZE (0x00000004U) + +/* Define used to get DMAMUX status register offset */ +#define DMAMUX_CH_STATUS_OFFSET (0x80U) +/* Define used to get DMAMUX RequestGenerator offset */ +#define DMAMUX_REQ_GEN_OFFSET (0x100U) +/* Define used to get DMAMUX Request Generator status register offset */ +#define DMAMUX_REQ_GEN_STATUS_OFFSET (0x180U) + + +/** DMAMUX1_Request_selection DMAMUX1 Request selection */ +#define DMAMUX_REQUEST_ID_MASK (DMAMUX_CHxCTRL_REQID_MASK) +/* DMAMUX1 requests */ +#define DMAMUX1_REQUEST_GENERATOR0 ((uint16_t)0x01U-1U) /* DMAMUX1 request generator 0 */ +#define DMAMUX1_REQUEST_GENERATOR1 ((uint16_t)0x02U-1U) /* DMAMUX1 request generator 1 */ +#define DMAMUX1_REQUEST_GENERATOR2 ((uint16_t)0x03U-1U) /* DMAMUX1 request generator 2 */ +#define DMAMUX1_REQUEST_GENERATOR3 ((uint16_t)0x04U-1U) /* DMAMUX1 request generator 3 */ +#define DMAMUX1_REQUEST_GENERATOR4 ((uint16_t)0x05U-1U) /* DMAMUX1 request generator 4 */ +#define DMAMUX1_REQUEST_GENERATOR5 ((uint16_t)0x06U-1U) /* DMAMUX1 request generator 5 */ +#define DMAMUX1_REQUEST_GENERATOR6 ((uint16_t)0x07U-1U) /* DMAMUX1 request generator 6 */ +#define DMAMUX1_REQUEST_GENERATOR7 ((uint16_t)0x08U-1U) /* DMAMUX1 request generator 7 */ +#define DMAMUX1_REQUEST_ADC1 ((uint16_t)0x09U-1U) /* DMAMUX1 ADC1 request */ +#define DMAMUX1_REQUEST_ADC2 ((uint16_t)0x0AU-1U) /* DMAMUX1 ADC2 request */ +#define DMAMUX1_REQUEST_ADC3 ((uint16_t)0x0BU-1U) /* DMAMUX1 ADC3 request */ +//SHRTIM_DMA0-6 SHRTIM1-2 12-25 +#define DMAMUX1_REQUEST_SHRTIM1_DMA0 ((uint16_t)0x0CU-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM1_DMA1 ((uint16_t)0x0DU-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM1_DMA2 ((uint16_t)0x0EU-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM1_DMA3 ((uint16_t)0x0FU-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM1_DMA4 ((uint16_t)0x10U-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM1_DMA5 ((uint16_t)0x11U-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM1_DMA6 ((uint16_t)0x12U-1U) /* DMAMUX1 SHRTIM1 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA0 ((uint16_t)0x13U-1U) /* DMAMUX1 SHRTIM2 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA1 ((uint16_t)0x14U-1U) /* DMAMUX1 SHRTIM2 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA2 ((uint16_t)0x15U-1U) /* DMAMUX1 SHRTIM2 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA3 ((uint16_t)0x16U-1U) /* DMAMUX1 SHRTIM2 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA4 ((uint16_t)0x17U-1U) /* DMAMUX1 SHRTIM2 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA5 ((uint16_t)0x18U-1U) /* DMAMUX1 SHRTIM2 request */ +#define DMAMUX1_REQUEST_SHRTIM2_DMA6 ((uint16_t)0x19U-1U) /* DMAMUX1 SHRTIM2 request */ +//ATIM 26-53 +#define DMAMUX1_REQUEST_ATIM1_UP ((uint16_t)0x1AU-1U) /* DMAMUX1 ATIM1 UP request */ +#define DMAMUX1_REQUEST_ATIM1_CH1 ((uint16_t)0x1BU-1U) /* DMAMUX1 ATIM1 CH1 request */ +#define DMAMUX1_REQUEST_ATIM1_CH2 ((uint16_t)0x1CU-1U) /* DMAMUX1 ATIM1 CH2 request */ +#define DMAMUX1_REQUEST_ATIM1_CH3 ((uint16_t)0x1DU-1U) /* DMAMUX1 ATIM1 CH3 request */ +#define DMAMUX1_REQUEST_ATIM1_CH4 ((uint16_t)0x1EU-1U) /* DMAMUX1 ATIM1 CH4 request */ +#define DMAMUX1_REQUEST_ATIM1_TRIG ((uint16_t)0x1FU-1U) /* DMAMUX1 ATIM1 TRIG request */ +#define DMAMUX1_REQUEST_ATIM1_COM ((uint16_t)0x20U-1U) /* DMAMUX1 ATIM1 COM request */ +#define DMAMUX1_REQUEST_ATIM2_UP ((uint16_t)0x21U-1U) /* DMAMUX1 ATIM2 UP request */ +#define DMAMUX1_REQUEST_ATIM2_CH1 ((uint16_t)0x22U-1U) /* DMAMUX1 ATIM2 CH1 request */ +#define DMAMUX1_REQUEST_ATIM2_CH2 ((uint16_t)0x23U-1U) /* DMAMUX1 ATIM2 CH2 request */ +#define DMAMUX1_REQUEST_ATIM2_CH3 ((uint16_t)0x24U-1U) /* DMAMUX1 ATIM2 CH3 request */ +#define DMAMUX1_REQUEST_ATIM2_CH4 ((uint16_t)0x25U-1U) /* DMAMUX1 ATIM2 CH4 request */ +#define DMAMUX1_REQUEST_ATIM2_TRIG ((uint16_t)0x26U-1U) /* DMAMUX1 ATIM2 TRIG request */ +#define DMAMUX1_REQUEST_ATIM2_COM ((uint16_t)0x27U-1U) /* DMAMUX1 ATIM2 COM request */ +#define DMAMUX1_REQUEST_ATIM3_UP ((uint16_t)0x28U-1U) /* DMAMUX1 ATIM3 UP request */ +#define DMAMUX1_REQUEST_ATIM3_CH1 ((uint16_t)0x29U-1U) /* DMAMUX1 ATIM3 CH1 request */ +#define DMAMUX1_REQUEST_ATIM3_CH2 ((uint16_t)0x2AU-1U) /* DMAMUX1 ATIM3 CH2 request */ +#define DMAMUX1_REQUEST_ATIM3_CH3 ((uint16_t)0x2BU-1U) /* DMAMUX1 ATIM3 CH3 request */ +#define DMAMUX1_REQUEST_ATIM3_CH4 ((uint16_t)0x2CU-1U) /* DMAMUX1 ATIM3 CH4 request */ +#define DMAMUX1_REQUEST_ATIM3_TRIG ((uint16_t)0x2DU-1U) /* DMAMUX1 ATIM3 TRIG request */ +#define DMAMUX1_REQUEST_ATIM3_COM ((uint16_t)0x2EU-1U) /* DMAMUX1 ATIM1 COM request */ +#define DMAMUX1_REQUEST_ATIM4_UP ((uint16_t)0x2FU-1U) /* DMAMUX1 ATIM4 UP request */ +#define DMAMUX1_REQUEST_ATIM4_CH1 ((uint16_t)0x30U-1U) /* DMAMUX1 ATIM4 CH1 request */ +#define DMAMUX1_REQUEST_ATIM4_CH2 ((uint16_t)0x31U-1U) /* DMAMUX1 ATIM4 CH2 request */ +#define DMAMUX1_REQUEST_ATIM4_CH3 ((uint16_t)0x32U-1U) /* DMAMUX1 ATIM4 CH3 request */ +#define DMAMUX1_REQUEST_ATIM4_CH4 ((uint16_t)0x33U-1U) /* DMAMUX1 ATIM4 CH4 request */ +#define DMAMUX1_REQUEST_ATIM4_TRIG ((uint16_t)0x34U-1U) /* DMAMUX1 ATIM4 TRIG request */ +#define DMAMUX1_REQUEST_ATIM4_COM ((uint16_t)0x35U-1U) /* DMAMUX1 ATIM1 COM request */ +//GTIM 54-113 +#define DMAMUX1_REQUEST_GTIMA1_CH1 ((uint16_t)0x36U-1U) /* DMAMUX1 GTIMA1 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA1_CH2 ((uint16_t)0x37U-1U) /* DMAMUX1 GTIMA1 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA1_CH3 ((uint16_t)0x38U-1U) /* DMAMUX1 GTIMA1 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA1_CH4 ((uint16_t)0x39U-1U) /* DMAMUX1 GTIMA1 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA1_TRIG ((uint16_t)0x3AU-1U) /* DMAMUX1 GTIMA1 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA1_UP ((uint16_t)0x3BU-1U) /* DMAMUX1 GTIMA1 UP request */ +#define DMAMUX1_REQUEST_GTIMA2_CH1 ((uint16_t)0x3CU-1U) /* DMAMUX1 GTIMA2 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA2_CH2 ((uint16_t)0x3DU-1U) /* DMAMUX1 GTIMA2 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA2_CH3 ((uint16_t)0x3EU-1U) /* DMAMUX1 GTIMA2 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA2_CH4 ((uint16_t)0x3FU-1U) /* DMAMUX1 GTIMA2 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA2_TRIG ((uint16_t)0x40U-1U) /* DMAMUX1 GTIMA2 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA2_UP ((uint16_t)0x41U-1U) /* DMAMUX1 GTIMA2 UP request */ +#define DMAMUX1_REQUEST_GTIMA3_CH1 ((uint16_t)0x42U-1U) /* DMAMUX1 GTIMA3 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA3_CH2 ((uint16_t)0x43U-1U) /* DMAMUX1 GTIMA3 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA3_CH3 ((uint16_t)0x44U-1U) /* DMAMUX1 GTIMA3 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA3_CH4 ((uint16_t)0x45U-1U) /* DMAMUX1 GTIMA3 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA3_TRIG ((uint16_t)0x46U-1U) /* DMAMUX1 GTIMA3 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA3_UP ((uint16_t)0x47U-1U) /* DMAMUX1 GTIMA3 UP request */ +#define DMAMUX1_REQUEST_GTIMA4_CH1 ((uint16_t)0x48U-1U) /* DMAMUX1 GTIMA4 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA4_CH2 ((uint16_t)0x49U-1U) /* DMAMUX1 GTIMA4 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA4_CH3 ((uint16_t)0x4AU-1U) /* DMAMUX1 GTIMA4 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA4_CH4 ((uint16_t)0x4BU-1U) /* DMAMUX1 GTIMA4 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA4_TRIG ((uint16_t)0x4CU-1U) /* DMAMUX1 GTIMA4 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA4_UP ((uint16_t)0x4DU-1U) /* DMAMUX1 GTIMA4 UP request */ +#define DMAMUX1_REQUEST_GTIMA5_CH1 ((uint16_t)0x4EU-1U) /* DMAMUX1 GTIMA5 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA5_CH2 ((uint16_t)0x4FU-1U) /* DMAMUX1 GTIMA5 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA5_CH3 ((uint16_t)0x50U-1U) /* DMAMUX1 GTIMA5 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA5_CH4 ((uint16_t)0x51U-1U) /* DMAMUX1 GTIMA5 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA5_TRIG ((uint16_t)0x52U-1U) /* DMAMUX1 GTIMA5 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA5_UP ((uint16_t)0x53U-1U) /* DMAMUX1 GTIMA5 UP request */ +#define DMAMUX1_REQUEST_GTIMA6_CH1 ((uint16_t)0x54U-1U) /* DMAMUX1 GTIMA6 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA6_CH2 ((uint16_t)0x55U-1U) /* DMAMUX1 GTIMA6 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA6_CH3 ((uint16_t)0x56U-1U) /* DMAMUX1 GTIMA6 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA6_CH4 ((uint16_t)0x57U-1U) /* DMAMUX1 GTIMA6 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA6_TRIG ((uint16_t)0x58U-1U) /* DMAMUX1 GTIMA6 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA6_UP ((uint16_t)0x59U-1U) /* DMAMUX1 GTIMA6 UP request */ +#define DMAMUX1_REQUEST_GTIMA7_CH1 ((uint16_t)0x5AU-1U) /* DMAMUX1 GTIMA7 CH1 request */ +#define DMAMUX1_REQUEST_GTIMA7_CH2 ((uint16_t)0x5BU-1U) /* DMAMUX1 GTIMA7 CH2 request */ +#define DMAMUX1_REQUEST_GTIMA7_CH3 ((uint16_t)0x5CU-1U) /* DMAMUX1 GTIMA7 CH3 request */ +#define DMAMUX1_REQUEST_GTIMA7_CH4 ((uint16_t)0x5DU-1U) /* DMAMUX1 GTIMA7 CH4 request */ +#define DMAMUX1_REQUEST_GTIMA7_TRIG ((uint16_t)0x5EU-1U) /* DMAMUX1 GTIMA7 TRIG request */ +#define DMAMUX1_REQUEST_GTIMA7_UP ((uint16_t)0x5FU-1U) /* DMAMUX1 GTIMA7 UP request */ +#define DMAMUX1_REQUEST_GTIMB1_CH1 ((uint16_t)0x60U-1U) /* DMAMUX1 GTIMB1 CH1 request */ +#define DMAMUX1_REQUEST_GTIMB1_CH2 ((uint16_t)0x61U-1U) /* DMAMUX1 GTIMB1 CH2 request */ +#define DMAMUX1_REQUEST_GTIMB1_CH3 ((uint16_t)0x62U-1U) /* DMAMUX1 GTIMB1 CH3 request */ +#define DMAMUX1_REQUEST_GTIMB1_CH4 ((uint16_t)0x63U-1U) /* DMAMUX1 GTIMB1 CH4 request */ +#define DMAMUX1_REQUEST_GTIMB1_TRIG ((uint16_t)0x64U-1U) /* DMAMUX1 GTIMB1 TRIG request */ +#define DMAMUX1_REQUEST_GTIMB1_UP ((uint16_t)0x65U-1U) /* DMAMUX1 GTIMB1 UP request */ +#define DMAMUX1_REQUEST_GTIMB2_CH1 ((uint16_t)0x66U-1U) /* DMAMUX1 GTIMB2 CH1 request */ +#define DMAMUX1_REQUEST_GTIMB2_CH2 ((uint16_t)0x67U-1U) /* DMAMUX1 GTIMB2 CH2 request */ +#define DMAMUX1_REQUEST_GTIMB2_CH3 ((uint16_t)0x68U-1U) /* DMAMUX1 GTIMB2 CH3 request */ +#define DMAMUX1_REQUEST_GTIMB2_CH4 ((uint16_t)0x69U-1U) /* DMAMUX1 GTIMB2 CH4 request */ +#define DMAMUX1_REQUEST_GTIMB2_TRIG ((uint16_t)0x6AU-1U) /* DMAMUX1 GTIMB2 TRIG request */ +#define DMAMUX1_REQUEST_GTIMB2_UP ((uint16_t)0x6BU-1U) /* DMAMUX1 GTIMB2 UP request */ +#define DMAMUX1_REQUEST_GTIMB3_CH1 ((uint16_t)0x6CU-1U) /* DMAMUX1 GTIMB3 CH1 request */ +#define DMAMUX1_REQUEST_GTIMB3_CH2 ((uint16_t)0x6DU-1U) /* DMAMUX1 GTIMB3 CH2 request */ +#define DMAMUX1_REQUEST_GTIMB3_CH3 ((uint16_t)0x6EU-1U) /* DMAMUX1 GTIMB3 CH3 request */ +#define DMAMUX1_REQUEST_GTIMB3_CH4 ((uint16_t)0x6FU-1U) /* DMAMUX1 GTIMB3 CH4 request */ +#define DMAMUX1_REQUEST_GTIMB3_TRIG ((uint16_t)0x70U-1U) /* DMAMUX1 GTIMB3 TRIG request */ +#define DMAMUX1_REQUEST_GTIMB3_UP ((uint16_t)0x71U-1U) /* DMAMUX1 GTIMB3 UP request */ +//I2C 114-133 +#define DMAMUX1_REQUEST_I2C1_RX ((uint16_t)0x72U-1U) /* DMAMUX1 I2C1 RX request */ +#define DMAMUX1_REQUEST_I2C1_TX ((uint16_t)0x73U-1U) /* DMAMUX1 I2C1 TX request */ +#define DMAMUX1_REQUEST_I2C2_RX ((uint16_t)0x74U-1U) /* DMAMUX1 I2C2 RX request */ +#define DMAMUX1_REQUEST_I2C2_TX ((uint16_t)0x75U-1U) /* DMAMUX1 I2C2 TX request */ +#define DMAMUX1_REQUEST_I2C3_RX ((uint16_t)0x76U-1U) /* DMAMUX1 I2C3 RX request */ +#define DMAMUX1_REQUEST_I2C3_TX ((uint16_t)0x77U-1U) /* DMAMUX1 I2C3 TX request */ +#define DMAMUX1_REQUEST_I2C4_RX ((uint16_t)0x78U-1U) /* DMAMUX1 I2C4 RX request */ +#define DMAMUX1_REQUEST_I2C4_TX ((uint16_t)0x79U-1U) /* DMAMUX1 I2C4 TX request */ +#define DMAMUX1_REQUEST_I2C5_RX ((uint16_t)0x7AU-1U) /* DMAMUX1 I2C5 RX request */ +#define DMAMUX1_REQUEST_I2C5_TX ((uint16_t)0x7BU-1U) /* DMAMUX1 I2C5 TX request */ +#define DMAMUX1_REQUEST_I2C6_RX ((uint16_t)0x7CU-1U) /* DMAMUX1 I2C6 RX request */ +#define DMAMUX1_REQUEST_I2C6_TX ((uint16_t)0x7DU-1U) /* DMAMUX1 I2C6 TX request */ +#define DMAMUX1_REQUEST_I2C7_RX ((uint16_t)0x7EU-1U) /* DMAMUX1 I2C7 RX request */ +#define DMAMUX1_REQUEST_I2C7_TX ((uint16_t)0x7FU-1U) /* DMAMUX1 I2C7 TX request */ +#define DMAMUX1_REQUEST_I2C8_RX ((uint16_t)0x80U-1U) /* DMAMUX1 I2C8 RX request */ +#define DMAMUX1_REQUEST_I2C8_TX ((uint16_t)0x81U-1U) /* DMAMUX1 I2C8 TX request */ +#define DMAMUX1_REQUEST_I2C9_RX ((uint16_t)0x82U-1U) /* DMAMUX1 I2C9 RX request */ +#define DMAMUX1_REQUEST_I2C9_TX ((uint16_t)0x83U-1U) /* DMAMUX1 I2C9 TX request */ +#define DMAMUX1_REQUEST_I2C10_RX ((uint16_t)0x84U-1U) /* DMAMUX1 I2C10 RX request */ +#define DMAMUX1_REQUEST_I2C10_TX ((uint16_t)0x85U-1U) /* DMAMUX1 I2C10 TX request */ +//USART 134-149 +#define DMAMUX1_REQUEST_USART1_RX ((uint16_t)0x86U-1U) /* DMAMUX1 USART1 RX request */ +#define DMAMUX1_REQUEST_USART1_TX ((uint16_t)0x87U-1U) /* DMAMUX1 USART1 TX request */ +#define DMAMUX1_REQUEST_USART2_RX ((uint16_t)0x88U-1U) /* DMAMUX1 USART2 RX request */ +#define DMAMUX1_REQUEST_USART2_TX ((uint16_t)0x89U-1U) /* DMAMUX1 USART2 TX request */ +#define DMAMUX1_REQUEST_USART3_RX ((uint16_t)0x8AU-1U) /* DMAMUX1 USART3 RX request */ +#define DMAMUX1_REQUEST_USART3_TX ((uint16_t)0x8BU-1U) /* DMAMUX1 USART3 TX request */ +#define DMAMUX1_REQUEST_USART4_RX ((uint16_t)0x8CU-1U) /* DMAMUX1 USART4 RX request */ +#define DMAMUX1_REQUEST_USART4_TX ((uint16_t)0x8DU-1U) /* DMAMUX1 USART4 TX request */ +#define DMAMUX1_REQUEST_USART5_RX ((uint16_t)0x8EU-1U) /* DMAMUX1 USART5 RX request */ +#define DMAMUX1_REQUEST_USART5_TX ((uint16_t)0x8FU-1U) /* DMAMUX1 USART5 TX request */ +#define DMAMUX1_REQUEST_USART6_RX ((uint16_t)0x90U-1U) /* DMAMUX1 USART6 RX request */ +#define DMAMUX1_REQUEST_USART6_TX ((uint16_t)0x91U-1U) /* DMAMUX1 USART6 TX request */ +#define DMAMUX1_REQUEST_USART7_RX ((uint16_t)0x92U-1U) /* DMAMUX1 USART7 RX request */ +#define DMAMUX1_REQUEST_USART7_TX ((uint16_t)0x93U-1U) /* DMAMUX1 USART7 TX request */ +#define DMAMUX1_REQUEST_USART8_RX ((uint16_t)0x94U-1U) /* DMAMUX1 USART8 RX request */ +#define DMAMUX1_REQUEST_USART8_TX ((uint16_t)0x95U-1U) /* DMAMUX1 USART8 TX request */ +//UART9-15 150-163 +#define DMAMUX1_REQUEST_UART9_RX ((uint16_t)0x96U-1U) /* DMAMUX1 UART9 RX request */ +#define DMAMUX1_REQUEST_UART9_TX ((uint16_t)0x97U-1U) /* DMAMUX1 UART9 TX request */ +#define DMAMUX1_REQUEST_UART10_RX ((uint16_t)0x98U-1U) /* DMAMUX1 UART10 RX request */ +#define DMAMUX1_REQUEST_UART10_TX ((uint16_t)0x99U-1U) /* DMAMUX1 UART10 TX request */ +#define DMAMUX1_REQUEST_UART11_RX ((uint16_t)0x9AU-1U) /* DMAMUX1 UART11 RX request */ +#define DMAMUX1_REQUEST_UART11_TX ((uint16_t)0x9BU-1U) /* DMAMUX1 UART11 TX request */ +#define DMAMUX1_REQUEST_UART12_RX ((uint16_t)0x9CU-1U) /* DMAMUX1 UART12 RX request */ +#define DMAMUX1_REQUEST_UART12_TX ((uint16_t)0x9DU-1U) /* DMAMUX1 UART12 TX request */ +#define DMAMUX1_REQUEST_UART13_RX ((uint16_t)0x9EU-1U) /* DMAMUX1 UART13 RX request */ +#define DMAMUX1_REQUEST_UART13_TX ((uint16_t)0x9FU-1U) /* DMAMUX1 UART13 TX request */ +#define DMAMUX1_REQUEST_UART14_RX ((uint16_t)0xA0U-1U) /* DMAMUX1 UART14 RX request */ +#define DMAMUX1_REQUEST_UART14_TX ((uint16_t)0xA1U-1U) /* DMAMUX1 UART14 TX request */ +#define DMAMUX1_REQUEST_UART15_RX ((uint16_t)0xA2U-1U) /* DMAMUX1 UART15 RX request */ +#define DMAMUX1_REQUEST_UART15_TX ((uint16_t)0xA3U-1U) /* DMAMUX1 UART15 TX request */ +//SPI1-7 164-185 +#define DMAMUX1_REQUEST_SPI1_RX ((uint16_t)0xA4U-1U) /* DMAMUX1 SPI1 RX request */ +#define DMAMUX1_REQUEST_I2S1_TX ((uint16_t)0xA5U-1U) /* DMAMUX1 I2S1 TX request */ +#define DMAMUX1_REQUEST_SPI2_RX ((uint16_t)0xA6U-1U) /* DMAMUX1 SPI2 RX request */ +#define DMAMUX1_REQUEST_I2S2_TX ((uint16_t)0xA7U-1U) /* DMAMUX1 I2S2 TX request */ +#define DMAMUX1_REQUEST_SPI3_RX ((uint16_t)0xA8U-1U) /* DMAMUX1 SPI3 RX request */ +#define DMAMUX1_REQUEST_I2S3_TX ((uint16_t)0xA9U-1U) /* DMAMUX1 I2S3 TX request */ +#define DMAMUX1_REQUEST_SPI4_RX ((uint16_t)0xAAU-1U) /* DMAMUX1 SPI4 RX request */ +#define DMAMUX1_REQUEST_I2S4_TX ((uint16_t)0xABU-1U) /* DMAMUX1 I2S4 TX request */ +#define DMAMUX1_REQUEST_SPI5_RX ((uint16_t)0xACU-1U) /* DMAMUX1 SPI5 RX request */ +#define DMAMUX1_REQUEST_SPI1_TX ((uint16_t)0xADU-1U) /* DMAMUX1 SPI1 TX request */ +#define DMAMUX1_REQUEST_SPI6_RX ((uint16_t)0xAEU-1U) /* DMAMUX1 SPI6 RX request */ +#define DMAMUX1_REQUEST_SPI2_TX ((uint16_t)0xAFU-1U) /* DMAMUX1 SPI2 TX request */ +#define DMAMUX1_REQUEST_SPI7_RX ((uint16_t)0xB0U-1U) /* DMAMUX1 SPI7 RX request */ +#define DMAMUX1_REQUEST_SPI3_TX ((uint16_t)0xB1U-1U) /* DMAMUX1 SPI3 TX request */ +#define DMAMUX1_REQUEST_I2S1_RX ((uint16_t)0xB2U-1U) /* DMAMUX1 I2S1 RX request */ +#define DMAMUX1_REQUEST_SPI4_TX ((uint16_t)0xB3U-1U) /* DMAMUX1 SPI4 TX request */ +#define DMAMUX1_REQUEST_I2S2_RX ((uint16_t)0xB4U-1U) /* DMAMUX1 I2S2 RX request */ +#define DMAMUX1_REQUEST_SPI5_TX ((uint16_t)0xB5U-1U) /* DMAMUX1 SPI5 TX request */ +#define DMAMUX1_REQUEST_I2S3_RX ((uint16_t)0xB6U-1U) /* DMAMUX1 I2S3 RX request */ +#define DMAMUX1_REQUEST_SPI6_TX ((uint16_t)0xB7U-1U) /* DMAMUX1 SPI6 TX request */ +#define DMAMUX1_REQUEST_I2S4_RX ((uint16_t)0xB8U-1U) /* DMAMUX1 I2S4 RX request */ +#define DMAMUX1_REQUEST_SPI7_TX ((uint16_t)0xB9U-1U) /* DMAMUX1 SPI7 TX request */ +//LPUART 1-2 +#define DMAMUX1_REQUEST_LPUART1_RX ((uint16_t)0xBAU-1U) /* DMAMUX1 LPUART1 RX request */ +#define DMAMUX1_REQUEST_LPUART1_TX ((uint16_t)0xBBU-1U) /* DMAMUX1 LPUART1 RX request */ +#define DMAMUX1_REQUEST_LPUART2_RX ((uint16_t)0xBCU-1U) /* DMAMUX1 LPUART2 RX request */ +#define DMAMUX1_REQUEST_LPUART2_TX ((uint16_t)0xBDU-1U) /* DMAMUX1 LPUART2 RX request */ +//DAC1-2 190-191 +#define DMAMUX1_REQUEST_DAC1 ((uint16_t)0xBEU-1U) /* DMAMUX1 DAC1 request */ +#define DMAMUX1_REQUEST_DAC2 ((uint16_t)0xBFU-1U) /* DMAMUX1 DAC2 request */ +//DSMU 192-195 +#define DMAMUX1_REQUEST_DSMU_CH1 ((uint16_t)0xC0U-1U) /* DMAMUX1 DSMU1 request */ +#define DMAMUX1_REQUEST_DSMU_CH2 ((uint16_t)0xC1U-1U) /* DMAMUX1 DSMU2 request */ +#define DMAMUX1_REQUEST_DSMU_CH3 ((uint16_t)0xC2U-1U) /* DMAMUX1 DSMU3 request */ +#define DMAMUX1_REQUEST_DSMU_CH4 ((uint16_t)0xC3U-1U) /* DMAMUX1 DSMU4 request */ +//CANFD 1-2 196-203 +#define DMAMUX1_REQUEST_CANFD1 ((uint16_t)0xC4U-1U) /* DMAMUX1 CANFD1 request */ +#define DMAMUX1_REQUEST_CANFD2 ((uint16_t)0xC5U-1U) /* DMAMUX1 CANFD2 request */ +#define DMAMUX1_REQUEST_CANFD3 ((uint16_t)0xC6U-1U) /* DMAMUX1 CANFD3 request */ +#define DMAMUX1_REQUEST_CANFD4 ((uint16_t)0xC7U-1U) /* DMAMUX1 CANFD4 request */ +#define DMAMUX1_REQUEST_CANFD5 ((uint16_t)0xC8U-1U) /* DMAMUX1 CANFD5 request */ +#define DMAMUX1_REQUEST_CANFD6 ((uint16_t)0xC9U-1U) /* DMAMUX1 CANFD6 request */ +#define DMAMUX1_REQUEST_CANFD7 ((uint16_t)0xCAU-1U) /* DMAMUX1 CANFD7 request */ +#define DMAMUX1_REQUEST_CANFD8 ((uint16_t)0xCBU-1U) /* DMAMUX1 CANFD8 request */ +//CORDIC 204-205 +#define DMAMUX1_REQUEST_CORDIC_READ ((uint16_t)0xCCU-1U) /* DMAMUX1 CORDIC Read request */ +#define DMAMUX1_REQUEST_CORDIC_WRITE ((uint16_t)0xCDU-1U) /* DMAMUX1 CORDIC Write request */ +//CORDIC 206-207 +#define DMAMUX1_REQUEST_FMAC_READ ((uint16_t)0xCEU-1U) /* DMAMUX1 FMAC Read request */ +#define DMAMUX1_REQUEST_FMAC_WRITE ((uint16_t)0xCFU-1U) /* DMAMUX1 FMAC Write request */ +//BTIM1-4 208-211UEST +#define DMAMUX1_REQUEST_BTIM1 ((uint16_t)0xD0U-1U) /* DMAMUX1 BTIM1 request */ +#define DMAMUX1_REQUEST_BTIM2 ((uint16_t)0xD1U-1U) /* DMAMUX1 BTIM2 request */ +#define DMAMUX1_REQUEST_BTIM3 ((uint16_t)0xD2U-1U) /* DMAMUX1 BTIM3 request */ +#define DMAMUX1_REQUEST_BTIM4 ((uint16_t)0xD3U-1U) /* DMAMUX1 BTIM4 request */ +//GTIMB1-3 212-214UEST +#define DMAMUX1_REQUEST_GTIMB1_COM ((uint16_t)0xD4U-1U) /* DMAMUX1 GTIMB1 COM request */ +#define DMAMUX1_REQUEST_GTIMB2_COM ((uint16_t)0xD5U-1U) /* DMAMUX1 GTIMB2 COM request */ +#define DMAMUX1_REQUEST_GTIMB3_COM ((uint16_t)0xD6U-1U) /* DMAMUX1 GTIMB3 COM request */ +//DAC3-6 215-218 +#define DMAMUX1_REQUEST_DAC3 ((uint16_t)0xB7U-1U) /* DMAMUX1 DAC3 request */ +#define DMAMUX1_REQUEST_DAC4 ((uint16_t)0xB8U-1U) /* DMAMUX1 DAC4 request */ +#define DMAMUX1_REQUEST_DAC5 ((uint16_t)0xB9U-1U) /* DMAMUX1 DAC5 request */ +#define DMAMUX1_REQUEST_DAC6 ((uint16_t)0xBAU-1U) /* DMAMUX1 DAC6 request */ + + +/* DMAMUX_2 requests */ +#define DMAMUX2_REQUEST_GENERATOR0 ((uint16_t)0x01U-1U) /* DMAMUX2 request generator 0 */ +#define DMAMUX2_REQUEST_GENERATOR1 ((uint16_t)0x02U-1U) /* DMAMUX2 request generator 1 */ +#define DMAMUX2_REQUEST_GENERATOR2 ((uint16_t)0x03U-1U) /* DMAMUX2 request generator 2 */ +#define DMAMUX2_REQUEST_GENERATOR3 ((uint16_t)0x04U-1U) /* DMAMUX2 request generator 3 */ +#define DMAMUX2_REQUEST_GENERATOR4 ((uint16_t)0x05U-1U) /* DMAMUX2 request generator 4 */ +#define DMAMUX2_REQUEST_GENERATOR5 ((uint16_t)0x06U-1U) /* DMAMUX2 request generator 5 */ +#define DMAMUX2_REQUEST_GENERATOR6 ((uint16_t)0x07U-1U) /* DMAMUX2 request generator 6 */ +#define DMAMUX2_REQUEST_GENERATOR7 ((uint16_t)0x08U-1U) /* DMAMUX2 request generator 7 */ +#define DMAMUX2_REQUEST_GENERATOR8 ((uint16_t)0x09U-1U) /* DMAMUX2 request generator 8 */ +#define DMAMUX2_REQUEST_GENERATOR9 ((uint16_t)0x0AU-1U) /* DMAMUX2 request generator 9 */ +#define DMAMUX2_REQUEST_GENERATOR10 ((uint16_t)0x0BU-1U) /* DMAMUX2 request generator 10 */ +#define DMAMUX2_REQUEST_GENERATOR11 ((uint16_t)0x0CU-1U) /* DMAMUX2 request generator 11 */ +#define DMAMUX2_REQUEST_GENERATOR12 ((uint16_t)0x0DU-1U) /* DMAMUX2 request generator 12 */ +#define DMAMUX2_REQUEST_GENERATOR13 ((uint16_t)0x0EU-1U) /* DMAMUX2 request generator 13 */ +#define DMAMUX2_REQUEST_GENERATOR14 ((uint16_t)0x0FU-1U) /* DMAMUX2 request generator 14 */ +#define DMAMUX2_REQUEST_GENERATOR15 ((uint16_t)0x10U-1U) /* DMAMUX2 request generator 15 */ +//xSPI1-2 1-4 +#define DMAMUX2_REQUEST_REQ_XSPI1_RX ((uint16_t)0x19U-1U) /* DMAMUX2 XSPI1 RX request */ +#define DMAMUX2_REQUEST_REQ_XSPI1_TX ((uint16_t)0x1AU-1U) /* DMAMUX2 XSPI1 TX request */ +#define DMAMUX2_REQUEST_REQ_XSPI2_RX ((uint16_t)0x1BU-1U) /* DMAMUX2 XSPI2 RX request */ +#define DMAMUX2_REQUEST_REQ_XSPI2_TX ((uint16_t)0x1CU-1U) /* DMAMUX2 XSPI2 TX request */ + +#define DMAMUX_SYNC_ID_MASK (DMAMUX_CHxCTRL_SYID_MASK) +/** DMAMUX_SYNC_EVT Synchronization Signal Event */ +#define DMAMUX1_SYNC_DMAMUX1_EVT0_7 ((uint32_t)0x00000000U) /* DMAMUX1 synchronization Signal is DMAMUX1 Channel0~7 Event */ +#define DMAMUX1_SYNC_DMAMUX1_EVT8_15 ((uint32_t)0x01000000U) /* DMAMUX1 synchronization Signal is DMAMUX1 Channel8~15 Event */ +#define DMAMUX1_SYNC_DMAMUX1_EVT16_23 ((uint32_t)0x02000000U) /* DMAMUX1 synchronization Signal is DMAMUX1 Channel16~23 Event */ +#define DMAMUX1_SYNC_LPTIM5_OUT ((uint32_t)0x03000000U) /* DMAMUX1 synchronization Signal is LPTIM5 OUT */ +#define DMAMUX1_SYNC_LPTIM4_OUT ((uint32_t)0x04000000U) /* DMAMUX1 synchronization Signal is LPTIM4 OUT */ +#define DMAMUX1_SYNC_LPTIM3_OUT ((uint32_t)0x05000000U) /* DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define DMAMUX1_SYNC_LPTIM2_OUT ((uint32_t)0x06000000U) /* DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define DMAMUX1_SYNC_LPTIM1_OUT ((uint32_t)0x07000000U) /* DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define DMAMUX1_SYNC_EXTI0 ((uint32_t)0x08000000U) /* DMAMUX1 synchronization Signal is EXTI0 IT */ +#define DMAMUX2_SYNC_INTERNAL_USED ((uint32_t)0x00000000U) /* DMAMUX2 synchronization Signal is Internal used or unused */ + + +#define DMAMUX_REQ_NUMBER_MASK (DMAMUX_CHxCTRL_NUMREQ_MASK) +#define DMAMUX_REQ_NUMBER_Pos (19U) + +/** DMAMUX Synchronization Signal Polarity*/ +#define DMAMUX_SYNC_POL_MASK (DMAMUX_CHxCTRL_SYPOL_MASK) +#define DMAMUX_SYNC_NO_EVENT (0x00000000U) /* All requests are blocked */ +#define DMAMUX_SYNC_POL_RISING (DMAMUX_CHxCTRL_SYPOL_0) /* Synchronization on event on rising edge */ +#define DMAMUX_SYNC_POL_FALLING (DMAMUX_CHxCTRL_SYPOL_1) /* Synchronization on event on falling edge */ +#define DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CHxCTRL_SYPOL_0 | DMAMUX_CHxCTRL_SYPOL_1) /* Synchronization on event on rising and falling edge */ + +#define DMAMUX_EVENT_GEN_MASK (DMAMUX_CHxCTRL_EVEGEN) +#define DMAMUX_SYN_ENABLE_MASK (DMAMUX_CHxCTRL_SYEN) +#define DMAMUX_SYNOVERRUN_INTEN_MASK (DMAMUX_CHxCTRL_SOIEN) + +#define DMAMUX_GEN_ENABLE_MASK (DMAMUX_CHxCFG_GEN) + +/** DMAMUX_REQUEST_GENERATOR Request Generator Channel */ +#define DMAMUX_REQ_GEN_0 (0x00000000U) +#define DMAMUX_REQ_GEN_1 (0x00000001U) +#define DMAMUX_REQ_GEN_2 (0x00000002U) +#define DMAMUX_REQ_GEN_3 (0x00000003U) +#define DMAMUX_REQ_GEN_4 (0x00000004U) +#define DMAMUX_REQ_GEN_5 (0x00000005U) +#define DMAMUX_REQ_GEN_6 (0x00000006U) +#define DMAMUX_REQ_GEN_7 (0x00000007U) +#define DMAMUX_REQ_GEN_8 (0x00000008U) +#define DMAMUX_REQ_GEN_9 (0x00000009U) +#define DMAMUX_REQ_GEN_10 (0x0000000AU) +#define DMAMUX_REQ_GEN_11 (0x0000000BU) +#define DMAMUX_REQ_GEN_12 (0x0000000CU) +#define DMAMUX_REQ_GEN_13 (0x0000000DU) +#define DMAMUX_REQ_GEN_14 (0x0000000EU) +#define DMAMUX_REQ_GEN_15 (0x0000000FU) + +/** DMAMUX_REQUEST_GEN_POLARITY External Request Signal Generation Polarity */ +#define DMAMUX_REQ_GEN_POL_MASK (DMAMUX_CHxCFG_GPOL_MASK) +#define DMAMUX_REQ_GEN_NO_EVENT (0x00000000U) /* No external DMA request generation */ +#define DMAMUX_REQ_GEN_POL_RISING (DMAMUX_CHxCFG_GPOL_0) /* External DMA request generation on event on rising edge */ +#define DMAMUX_REQ_GEN_POL_FALLING (DMAMUX_CHxCFG_GPOL_1) /* External DMA request generation on event on falling edge */ +#define DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_CHxCFG_GPOL_0 | DMAMUX_CHxCFG_GPOL_1) /* External DMA request generation on rising and falling edge */ + +#define DMAMUX_REQ_GEN_NUMBER_MASK (DMAMUX_CHxCFG_GNUMREQ_MASK) +#define DMAMUX_REQ_GEN_NUMBER_Pos (19U) + +#define DMAMUX_TRIGOVERRUN_INTEN_MASK (DMAMUX_CHxCFG_TOVIEN) + +#define DMAMUX_REQ_GEN_SIG_ID_MASK (DMAMUX_CHxCFG_SYID_MASK) + +/** DMAMUX1 External Request Signal Generation */ +#define DMAMUX1_REQ_GEN_DMAMUX1_EVT0_EVT7 ((uint32_t)0x00000001U-1U) /* DMAMUX1 Request generator Signal is DMAMUX1 Channel0-7 Event */ +#define DMAMUX1_REQ_GEN_DMAMUX1_EVT8_EVT5 ((uint32_t)0x00000002U-1U) /* DMAMUX1 Request generator Signal is DMAMUX1 Channel8_15 Event */ +#define DMAMUX1_REQ_GEN_DMAMUX1_EVT16_EVT23 ((uint32_t)0x00000003U-1U) /* DMAMUX1 Request generator Signal is DMAMUX1 Channel16_23 Event */ +#define DMAMUX1_REQ_GEN_LPTIM4_OUT ((uint32_t)0x00000004U-1U) /* DMAMUX1 Request generator Signal is LPTIM4 OUT */ +#define DMAMUX1_REQ_GEN_LPTIM3_OUT ((uint32_t)0x00000005U-1U) /* DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define DMAMUX1_REQ_GEN_LPTIM2_OUT ((uint32_t)0x00000006U-1U) /* DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define DMAMUX1_REQ_GEN_LPTIM1_OUT ((uint32_t)0x00000007U-1U) /* DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define DMAMUX1_REQ_GEN_EXTI0 ((uint32_t)0x00000008U-1U) /* DMAMUX1 Request generator Signal is EXTI0 IT */ +#define DMAMUX1_REQ_GEN_CANFD1_INT0 ((uint32_t)0x00000009U-1U) /* DMAMUX1 Request generator Signal is CANFD1 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD2_INT0 ((uint32_t)0x0000000AU-1U) /* DMAMUX1 Request generator Signal is CANFD2 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD3_INT0 ((uint32_t)0x0000000BU-1U) /* DMAMUX1 Request generator Signal is CANFD3 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD4_INT0 ((uint32_t)0x0000000CU-1U) /* DMAMUX1 Request generator Signal is CANFD4 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD5_INT0 ((uint32_t)0x0000000DU-1U) /* DMAMUX1 Request generator Signal is CANFD5 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD6_INT0 ((uint32_t)0x0000000EU-1U) /* DMAMUX1 Request generator Signal is CANFD6 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD7_INT0 ((uint32_t)0x0000000FU-1U) /* DMAMUX1 Request generator Signal is CANFD7 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_CANFD8_INT0 ((uint32_t)0x00000010U-1U) /* DMAMUX1 Request generator Signal is CANFD8 golgal interrupt 0 */ +#define DMAMUX1_REQ_GEN_LPTIM5_OUT ((uint32_t)0x00000011U-1U) /* DMAMUX1 Request generator Signal is LPTIM4 OUT */ +#define DMAMUX1_REQ_GEN_ESC_INT ((uint32_t)0x00000012U-1U) /* DMAMUX1 Request generator Signal is ESC golgal interrupt */ +#define DMAMUX1_REQ_GEN_CANFD1_INT1 ((uint32_t)0x00000013U-1U) /* DMAMUX1 Request generator Signal is CANFD1 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD2_INT1 ((uint32_t)0x00000014U-1U) /* DMAMUX1 Request generator Signal is CANFD2 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD3_INT1 ((uint32_t)0x00000015U-1U) /* DMAMUX1 Request generator Signal is CANFD3 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD4_INT1 ((uint32_t)0x00000016U-1U) /* DMAMUX1 Request generator Signal is CANFD4 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD5_INT1 ((uint32_t)0x00000017U-1U) /* DMAMUX1 Request generator Signal is CANFD5 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD6_INT1 ((uint32_t)0x00000018U-1U) /* DMAMUX1 Request generator Signal is CANFD6 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD7_INT1 ((uint32_t)0x00000019U-1U) /* DMAMUX1 Request generator Signal is CANFD7 golgal interrupt 1 */ +#define DMAMUX1_REQ_GEN_CANFD8_INT1 ((uint32_t)0x0000001AU-1U) /* DMAMUX1 Request generator Signal is CANFD8 golgal interrupt 1 */ +/** DMAMUX2 External Request Signal Generation */ +#define DMAMUX2_DMA1_CH0_TC_INT ((uint32_t)0x00000001U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel0 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH1_TC_INT ((uint32_t)0x00000002U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel1 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH2_TC_INT ((uint32_t)0x00000003U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel2 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH3_TC_INT ((uint32_t)0x00000004U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel3 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH4_TC_INT ((uint32_t)0x00000005U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel4 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH5_TC_INT ((uint32_t)0x00000006U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel5 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH6_TC_INT ((uint32_t)0x00000007U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel6 Transfer complete inttrupt */ +#define DMAMUX2_DMA1_CH7_TC_INT ((uint32_t)0x00000008U-1U) /* DMAMUX2 Request generator Signal is DMA1 Channel7 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH0_TC_INT ((uint32_t)0x00000009U-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel0 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH1_TC_INT ((uint32_t)0x0000000AU-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel1 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH2_TC_INT ((uint32_t)0x0000000BU-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel2 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH3_TC_INT ((uint32_t)0x0000000CU-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel3 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH4_TC_INT ((uint32_t)0x0000000DU-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel4 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH5_TC_INT ((uint32_t)0x0000000EU-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel5 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH6_TC_INT ((uint32_t)0x0000000FU-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel6 Transfer complete inttrupt */ +#define DMAMUX2_DMA2_CH7_TC_INT ((uint32_t)0x00000010U-1U) /* DMAMUX2 Request generator Signal is DMA2 Channel7 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH0_TC_INT ((uint32_t)0x00000011U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel0 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH1_TC_INT ((uint32_t)0x00000012U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel1 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH2_TC_INT ((uint32_t)0x00000013U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel2 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH3_TC_INT ((uint32_t)0x00000014U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel3 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH4_TC_INT ((uint32_t)0x00000015U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel4 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH5_TC_INT ((uint32_t)0x00000016U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel5 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH6_TC_INT ((uint32_t)0x00000017U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel6 Transfer complete inttrupt */ +#define DMAMUX2_DMA3_CH7_TC_INT ((uint32_t)0x00000018U-1U) /* DMAMUX2 Request generator Signal is DMA3 Channel7 Transfer complete inttrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_LCDC_INT ((uint32_t)0x00000019U-1U) /* DMAMUX2 Request generator Signal is LCD interrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_GPU_INT ((uint32_t)0x0000001AU-1U) /* DMAMUX2 Request generator Signal is GPU interrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_JEPG_SGDMA_H2P_INT ((uint32_t)0x0000001BU-1U) /* DMAMUX2 Request generator Signal is JEPG_SGDMA_H2P interrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_JEPG_SGDMA_P2H_INT ((uint32_t)0x0000001CU-1U) /* DMAMUX2 Request generator Signal is JEPG_SGDMA_P2H interrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_MIPI_INT ((uint32_t)0x0000001DU-1U) /* DMAMUX2 Request generator Signal is MIPI interrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_USB1_INT ((uint32_t)0x0000001EU-1U) /* DMAMUX2 Request generator Signal is USB1 interrupt */ +#define DMAMUX2_REQ_GEN_DMAMUX2_USB2_INT ((uint32_t)0x0000001FU-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_SDMMC1_INT ((uint32_t)0x00000020U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_SDMMC2_INT ((uint32_t)0x00000021U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_DVP1_INT ((uint32_t)0x00000022U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_DVP2_INT ((uint32_t)0x00000023U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_EHT1_INT ((uint32_t)0x00000024U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_EHT2_INT ((uint32_t)0x00000025U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ +#define DMAMUX2_REQ_GEN_SDPU_INT ((uint32_t)0x00000026U-1U) /* DMAMUX2 Request generator Signal is USB2 interrupt */ + + +/* DMAMUX_CHANNEL DMAMUX Channel */ +#define DMAMUX_CHANNEL_0 ((uint32_t)0x00000000U) /* DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX_MDMA Channel 0 connected to MDMA Channel 0 */ +#define DMAMUX_CHANNEL_1 ((uint32_t)0x00000001U) /* DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX_MDMA Channel 1 connected to MDMA Channel 1 */ +#define DMAMUX_CHANNEL_2 ((uint32_t)0x00000002U) /* DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX_MDMA Channel 2 connected to MDMA Channel 2 */ +#define DMAMUX_CHANNEL_3 ((uint32_t)0x00000003U) /* DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX_MDMA Channel 3 connected to MDMA Channel 3 */ +#define DMAMUX_CHANNEL_4 ((uint32_t)0x00000004U) /* DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX_MDMA Channel 4 connected to MDMA Channel 4 */ +#define DMAMUX_CHANNEL_5 ((uint32_t)0x00000005U) /* DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX_MDMA Channel 5 connected to MDMA Channel 5 */ +#define DMAMUX_CHANNEL_6 ((uint32_t)0x00000006U) /* DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX_MDMA Channel 6 connected to MDMA Channel 6 */ +#define DMAMUX_CHANNEL_7 ((uint32_t)0x00000007U) /* DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX_MDMA Channel 7 connected to MDMA Channel 7 */ +#define DMAMUX_CHANNEL_8 ((uint32_t)0x00000008U) /* DMAMUX1 Channel 8 connected to DMA2 Channel 0 , DMAMUX_MDMA Channel 8 connected to MDMA Channel 8 */ +#define DMAMUX_CHANNEL_9 ((uint32_t)0x00000009U) /* DMAMUX1 Channel 9 connected to DMA2 Channel 1 , DMAMUX_MDMA Channel 9 connected to MDMA Channel 9 */ +#define DMAMUX_CHANNEL_10 ((uint32_t)0x0000000AU) /* DMAMUX1 Channel 10 connected to DMA2 Channel 2 , DMAMUX_MDMA Channel 10 connected to MDMA Channel 10 */ +#define DMAMUX_CHANNEL_11 ((uint32_t)0x0000000BU) /* DMAMUX1 Channel 11 connected to DMA2 Channel 3 , DMAMUX_MDMA Channel 11 connected to MDMA Channel 11 */ +#define DMAMUX_CHANNEL_12 ((uint32_t)0x0000000CU) /* DMAMUX1 Channel 12 connected to DMA2 Channel 4 , DMAMUX_MDMA Channel 12 connected to MDMA Channel 12 */ +#define DMAMUX_CHANNEL_13 ((uint32_t)0x0000000DU) /* DMAMUX1 Channel 13 connected to DMA2 Channel 5 , DMAMUX_MDMA Channel 13 connected to MDMA Channel 13 */ +#define DMAMUX_CHANNEL_14 ((uint32_t)0x0000000EU) /* DMAMUX1 Channel 14 connected to DMA2 Channel 6 , DMAMUX_MDMA Channel 14 connected to MDMA Channel 14 */ +#define DMAMUX_CHANNEL_15 ((uint32_t)0x0000000FU) /* DMAMUX1 Channel 15 connected to DMA2 Channel 7 , DMAMUX_MDMA Channel 15 connected to MDMA Channel 15 */ +#define DMAMUX_CHANNEL_16 ((uint32_t)0x00000010U) /* DMAMUX1 Channel 16 connected to DMA3 Channel 0 , invailed for MDMA*/ +#define DMAMUX_CHANNEL_17 ((uint32_t)0x00000011U) /* DMAMUX1 Channel 17 connected to DMA3 Channel 1 , invailed for MDMA */ +#define DMAMUX_CHANNEL_18 ((uint32_t)0x00000012U) /* DMAMUX1 Channel 18 connected to DMA3 Channel 2 , invailed for MDMA */ +#define DMAMUX_CHANNEL_19 ((uint32_t)0x00000013U) /* DMAMUX1 Channel 19 connected to DMA3 Channel 3 , invailed for MDMA */ +#define DMAMUX_CHANNEL_20 ((uint32_t)0x00000014U) /* DMAMUX1 Channel 20 connected to DMA3 Channel 4 , invailed for MDMA */ +#define DMAMUX_CHANNEL_21 ((uint32_t)0x00000015U) /* DMAMUX1 Channel 21 connected to DMA3 Channel 5 , invailed for MDMA */ +#define DMAMUX_CHANNEL_22 ((uint32_t)0x00000016U) /* DMAMUX1 Channel 22 connected to DMA3 Channel 6 , invailed for MDMA */ +#define DMAMUX_CHANNEL_23 ((uint32_t)0x00000017U) /* DMAMUX1 Channel 23 connected to DMA3 Channel 7 , invailed for MDMA */ + + +void DMAMUX_DeInit(DMAMUX_ID DMAMUXx); + +void DMAMUX_SetRequestID(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t Request); +uint32_t DMAMUX_GetRequestID(DMAMUX_ID DMAMUXx, uint32_t Channel); +void DMAMUX_SetSyncID(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t SyncID); +uint32_t DMAMUX_GetSyncID(DMAMUX_ID DMAMUXx, uint32_t Channel); +void DMAMUX_SetSyncRequestNumber(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t RequestNumber); +uint32_t DMAMUX_GetSyncRequestNumber(DMAMUX_ID DMAMUXx, uint32_t Channel); +void DMAMUX_SetSyncPolarity(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t Polarity); +uint32_t DMAMUX_GetSyncPolarity(DMAMUX_ID DMAMUXx, uint32_t Channel); +void DMAMUX_EnableEventGeneration(DMAMUX_ID DMAMUXx, uint32_t Channel, FunctionalState Cmd); +void DMAMUX_EnableSync(DMAMUX_ID DMAMUXx, uint32_t Channel, FunctionalState Cmd); +void DMAMUX_EnableRequestGen(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, FunctionalState Cmd); +void DMAMUX_SetRequestGenPolarity(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity); +uint32_t DMAMUX_GetRequestGenPolarity(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel); +void DMAMUX_SetGenRequestNumber(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNumber); +uint32_t DMAMUX_GetGenRequestNumber(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel); +void DMAMUX_SetRequestSignalID(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID); +uint32_t DMAMUX_GetRequestSignalID(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel); + +void DMAMUX_EnableSynEventOverrunInt(DMAMUX_ID DMAMUXx, uint32_t Channel, FunctionalState Cmd); +void DMAMUX_EnableTrigOverrunInt(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, FunctionalState Cmd); + +FlagStatus DMAMUX_GetSynOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t Channel); +FlagStatus DMAMUX_GetTrigOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel); +void DMAMUX_ClearSynOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t Channel); +void DMAMUX_ClearTrigOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel); + + +#ifdef __cplusplus +} +#endif + + + +#endif /*N32H76x_H78x_DMAMUX_H */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsi.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsi.h new file mode 100644 index 0000000000..8f26c72a76 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsi.h @@ -0,0 +1,623 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dsi.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_DSI_H__ +#define __N32H76X_78X_DSI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Includes */ +#include "n32h76x_78x.h" + +#define DSI_TIME_OUT_VALUE ((uint32_t)0x00001000U) + +#define DSI_REGISTER_MASK ((uint32_t)0x00000000U) + +#define DSI_NO_ERRORS ((uint32_t)0x00000000U) + +#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037U) /* Maximum return packet configuration */ + +/** DSI_Video_Mode_Type DSI Video Mode Type **/ +#define DSI_VID_MODE_NB_PULSES DSI_REGISTER_MASK +#define DSI_VID_MODE_NB_EVENTS VID_VIDEOMOD_VIDEOMOD_0 +#define DSI_VID_MODE_BURST VID_VIDEOMOD_VIDEOMOD_1 + +/** DSI_Video_Pixel_Format **/ +#define DSI_RGB_565_16BIT ((uint32_t)0x0EU) +#define DSI_RGB_666_18BIT ((uint32_t)0x1EU) +#define DSI_RGB_666_18BIT_LP ((uint32_t)0x2EU) +#define DSI_RGB_888_24BIT ((uint32_t)0x3EU) + +/** DSI ACTIVE LANES **/ +#define DSI_ACTIVE_DATALANE0 ((uint32_t)0U) +#define DSI_ACTIVE_DATALANE1 ((uint32_t)1U) +#define DSI_ACTIVE_DATALANE2 ((uint32_t)2U) +#define DSI_ACTIVE_DATALANE3 ((uint32_t)3U) + +/** DSI_Number_Of_Lanes **/ +#define DSI_ONE_DATA_LANE (1) +#define DSI_TWO_DATA_LANES (2) +#define DSI_THREE_DATA_LANES (3) +#define DSI_FOUR_DATA_LANES (4) + +#define DSI_DATALANE0 (DSI_REGISTER_MASK) +#define DSI_DATALANE1 (VID_VC_VC_0) +#define DSI_DATALANE2 (VID_VC_VC_1) +#define DSI_DATALANE3 (VID_VC_VC_0 | VID_VC_VC_1) + +#define DSI_ULPS_ONE_DATA_LANE (DSI_WRPCTRL_ULPSDLEN_0) +#define DSI_ULPS_TWO_DATA_LANE (DSI_WRPCTRL_ULPSDLEN_0 | DSI_WRPCTRL_ULPSDLEN_1) +#define DSI_ULPS_THREE_DATA_LANE (DSI_WRPCTRL_ULPSDLEN_0 | DSI_WRPCTRL_ULPSDLEN_1 | DSI_WRPCTRL_ULPSDLEN_2) +#define DSI_ULPS_FOUR_DATA_LANE (DSI_WRPCTRL_ULPSDLEN_0 | DSI_WRPCTRL_ULPSDLEN_1 | DSI_WRPCTRL_ULPSDLEN_2 | DSI_WRPCTRL_ULPSDLEN_3) + +/** DSI Multiple packets per video line **/ +#define DSI_1_PACKETS_PER_LINE (VID_PKTPERLINE_PKTPERLINE_0) +#define DSI_2_PACKETS_PER_LINE (VID_PKTPERLINE_PKTPERLINE_1) +#define DSI_4_PACKETS_PER_LINE (VID_PKTPERLINE_PKTPERLINE_2) + +/** DSI_HOST: CONTROLLER OFF/ON **/ +#define DSI_TURN_OFF (DSI_REGISTER_MASK) +#define DSI_TURN_ON (DSI_NUMLANES_NUMLANES) + +/** DSI_HOST NON-CONTINUOUS HS CLOCK/CONTINUOUS HS CLOCK **/ +#define DSI_NON_CONTINUOUS_HS_CLOCK (DSI_REGISTER_MASK) +#define DSI_CONTINUOUS_HS_CLOCK (DSI_CONTHSCLK_CONTHSCLK) + +/** DSI_HOST ENABLE INSERT AN EOTP **/ +#define DSI_INSERT_EOTP_DISABLE (DSI_REGISTER_MASK) +#define DSI_INSERT_EOTP_ENABLE (DSI_AUTOINSERT_EOTP_AUTOINSEOTP) + +/** DSI_HOST ENABLE CHECK CRC **/ +#define DSI_CHECK_CRC_ENABLE (DSI_REGISTER_MASK) +#define DSI_CHECK_CRC_DISABLE (DSI_DISRXCRCCHK_DISRXCRCCHK) + +/** DSI_HOST DISABLE BURST **/ +#define DSI_BURST_ENABLE (DSI_REGISTER_MASK) +#define DSI_BURST_DISABLE (DSI_DISBST_DISBST) + +/** DSI_HOST ENABLE CLK SIGNALS **/ +#define DSI_CLKLANE_DISABLE (DSI_REGISTER_MASK) +#define DSI_CLKLANE_ENABLE (DSI_CLKLANEN_CLKLANEN) + +/** DSI_HOST ENABLE DATA LANE SIGNALS **/ +#define DSI_DATALANEALL_DISABLE (DSI_REGISTER_MASK) +#define DSI_ONE_DATALANE_ENABLE (DSI_DATLANEN_DATLANEN_0) +#define DSI_TWO_DATALANES_ENABLE (DSI_DATLANEN_DATLANEN_1 | DSI_DATLANEN_DATLANEN_0) +#define DSI_THREE_DATALANES_ENABLE (DSI_DATLANEN_DATLANEN_2 | DSI_DATLANEN_DATLANEN_1 | DSI_DATLANEN_DATLANEN_0) +#define DSI_FOUR_DATALANES_ENABLE (DSI_DATLANEN_DATLANEN_3 | DSI_DATLANEN_DATLANEN_2 | DSI_DATLANEN_DATLANEN_1 | DSI_DATLANEN_DATLANEN_0) + +/** DSI_HOST VID SKEW CAL ENABLE **/ +#define DSI_SKEWCALLINE_DISABLE (DSI_REGISTER_MASK) +#define DSI_SKEWCALLINE_ENABLE (DSI_SKEWCALINE_SKEWCALINE) + +/** DSI_HOST VID ENABLE **/ +#define DSI_VID_DISABLE (DSI_REGISTER_MASK) +#define DSI_VID_ENABLE (VID_EN_EN) + +/** DSI_HOST VID THE ALIGNMENT OF PIXELS **/ +#define DSI_LSB_ALIGNMENT (DSI_REGISTER_MASK) +#define DSI_MSB_ALIGNMENT (VID_PIXALIGN_PIXALIGN) + +/** DSI_HOST VID Polarity of VSYNC **/ +#define DSI_VSYNC_ACTIVE_LOW (DSI_REGISTER_MASK) +#define DSI_VSYNC_ACTIVE_HIGH (VID_VSYNCPOL_VSYNCPOL) + +/** DSI_HOST VID Polarity of HSYNC **/ +#define DSI_HSYNC_ACTIVE_LOW (DSI_REGISTER_MASK) +#define DSI_HSYNC_ACTIVE_HIGH (VID_HSYNCPOL_HSYNCPOL) + +/** DSI_HOST VID OVERRIDE MODE **/ +#define DSI_OVERRIDE_MODE_DISABLE (DSI_REGISTER_MASK) +#define DSI_OVERRIDE_MODE_ENABLE (VID_OVERIDE_OVERIDE) + +/** DSI_HOST VID BLLP MODE **/ +#define DSI_BLANKING_PACKETS_INBLLP (DSI_REGISTER_MASK) +#define DSI_LP_MODE_INBLLP (VID_BLLPMOD_BLLPMOD) + +/** DSI_HOST VID NULL PACKET IN BLLP MODE **/ +#define DSI_NULL_PACKET_INBLLP_DISABLE (DSI_REGISTER_MASK) +#define DSI_NULL_PACKET_INBLLP_ENABLE (VID_NULLPKTBLLP_NULLPKTBLLP) + +/** DSI_HOST VID EXTERNAL VIDEO INTERFACE PACKET REQUESTS ARE ALLOWED **/ +#define DSI_EXT_PACKETS_DISABLE (DSI_REGISTER_MASK) +#define DSI_EXT_PACKETS_VSYNC_ENABLE (VID_EXTPKTEN_EXTPKTEN_0) +#define DSI_EXT_PACKETS_VBP_ENABLE (VID_EXTPKTEN_EXTPKTEN_1) +#define DSI_EXT_PACKETS_AVL_ENABLE (VID_EXTPKTEN_EXTPKTEN_2) +#define DSI_EXT_PACKETS_VFP_ENABLE (VID_EXTPKTEN_EXTPKTEN_3) + +/** DSI Packets Data type **/ +#define DSI_SHORT_VSYNC_START (0x01U) +#define DSI_SHORT_VSYNC_END (0x11U) +#define DSI_SHORT_HSYNC_START (0x21U) +#define DSI_SHORT_HSYNC_END (0x31U) +#define DSI_SHORT_EOTP (0x08U) +#define DSI_SHORT_CMOFF (0x02U) +#define DSI_SHORT_CMON (0x12U) +#define DSI_SHORT_SHUTDOWN_PH (0x22U) +#define DSI_SHORT_TURNON_PH (0x3FU) +#define DSI_SHORT_GWRITE_NOPARA (0x03U) +#define DSI_SHORT_GWRITE_1PARA (0x13U) +#define DSI_SHORT_GWRITE_2PARA (0x23U) +#define DSI_SHORT_GREAD_NOPARA (0x04U) +#define DSI_SHORT_GREAD_1PARA (0x14U) +#define DSI_SHORT_GREAD_2PARA (0x24U) +#define DSI_SHORT_DCSWRITE_NOPARA (0x05U) +#define DSI_SHORT_DCSWRITE_1PARA (0x15U) +#define DSI_SHORT_DCSREAD_NOPARA (0x06U) +#define DSI_SHORT_MAX_PKTSIZE (0x37U) +#define DSI_LONG_NULL_PKT (0x09U) +#define DSI_LONG_BLANK_PKT (0x19U) +#define DSI_LONG_GWRITE (0x29U) +#define DSI_LONG_DCSWRITE (0x39U) +#define DSI_LONG_YUV422_20BIT (0x0CU) +#define DSI_LONG_YUV422_24BIT (0x1CU) +#define DSI_LONG_YUV422_16BIT (0x2CU) +#define DSI_LONG_RGB101010_30BIT (0x0DU) +#define DSI_LONG_RGB121212_36BIT (0x1DU) +#define DSI_LONG_YUV420_12BIT (0x3DU) +#define DSI_LONG_RGB565 (0x0EU) +#define DSI_LONG_RGB666 (0x1EU) +#define DSI_LONG_RGB666_LP (0x2EU) +#define DSI_LONG_RGB888 (0x3EU) + +/** DSI_DCS_Command DSI DCS Command **/ +#define DSI_ENTER_IDLE_MODE (0x39U) +#define DSI_ENTER_INVERT_MODE (0x21U) +#define DSI_ENTER_NORMAL_MODE (0x13U) +#define DSI_ENTER_PARTIAL_MODE (0x12U) +#define DSI_ENTER_SLEEP_MODE (0x10U) +#define DSI_EXIT_IDLE_MODE (0x38U) +#define DSI_EXIT_INVERT_MODE (0x20U) +#define DSI_EXIT_SLEEP_MODE (0x11U) +#define DSI_GET_3D_CONTROL (0x3FU) +#define DSI_GET_ADDRESS_MODE (0x0BU) +#define DSI_GET_BLUE_CHANNEL (0x08U) +#define DSI_GET_DIAGNOSTIC_RESULT (0x0FU) +#define DSI_GET_DISPLAY_MODE (0x0DU) +#define DSI_GET_GREEN_CHANNEL (0x07U) +#define DSI_GET_PIXEL_FORMAT (0x0CU) +#define DSI_GET_POWER_MODE (0x0AU) +#define DSI_GET_RED_CHANNEL (0x06U) +#define DSI_GET_SCANLINE (0x45U) +#define DSI_GET_SIGNAL_MODE (0x0EU) +#define DSI_NOP (0x00U) +#define DSI_READ_DDB_CONTINUE (0xA8U) +#define DSI_READ_DDB_START (0xA1U) +#define DSI_READ_MEMORY_CONTINUE (0x3EU) +#define DSI_READ_MEMORY_START (0x2EU) +#define DSI_SET_3D_CONTROL (0x3DU) +#define DSI_SET_ADDRESS_MODE (0x36U) +#define DSI_SET_COLUMN_ADDRESS (0x2AU) +#define DSI_SET_DISPLAY_OFF (0x28U) +#define DSI_SET_DISPLAY_ON (0x29U) +#define DSI_SET_GAMMA_CURVE (0x26U) +#define DSI_SET_PAGE_ADDRESS (0x2BU) +#define DSI_SET_PARTIAL_COLUMNS (0x31U) +#define DSI_SET_PARTIAL_ROWS (0x30U) +#define DSI_SET_PIXEL_FORMAT (0x3AU) +#define DSI_SET_SCROLL_AREA (0x33U) +#define DSI_SET_SCROLL_START (0x37U) +#define DSI_SET_TEAR_OFF (0x34U) +#define DSI_SET_TEAR_ON (0x35U) +#define DSI_SET_TEAR_SCANLINE (0x44U) +#define DSI_SET_VSYNC_TIMING (0x40U) +#define DSI_SOFT_RESET (0x01U) +#define DSI_WRITE_LUT (0x2DU) +#define DSI_WRITE_MEMORY_CONTINUE (0x3CU) +#define DSI_WRITE_MEMORY_START (0x2CU) + +/** DSI_Color_Coding DSI Color Coding **/ +#define DSI_RGB565 ((uint32_t)0x00000000U) /* The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 ((uint32_t)0x00000003U) /* The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 ((uint32_t)0x00000005U) + +/** DSI PHY Flags DSI Flags **/ +#define DSI_PHY_FLAG_PLL_UNLOCK (DSIPHY_PLLSTS_PLLUNLOCK) +#define DSI_PHY_FLAG_PLL_FM_CPLT (DSIPHY_PLLSTS_PLLFMCPLT) +#define DSI_PHY_FLAG_PLL_FM_UNDER (DSIPHY_PLLSTS_PLLFMUNDER) +#define DSI_PHY_FLAG_PLL_FM_OVER (DSIPHY_PLLSTS_PLLFMOVER) +#define DSI_PHY_FLAG_PLL_DIGCLK_MISS (DSIPHY_PLLSTS_PLLDIGCKMISS) +#define DSI_PHY_FLAG_PLL_FBCLK_MISS (DSIPHY_PLLSTS_PLLFBKCKMISS) +#define DSI_PHY_FLAG_PLL_REFCLK_MISS (DSIPHY_PLLSTS_PLLREFCKMISS) +#define DSI_PHY_FLAG_PHY_READY (DSIPHY_PLLSTS_PHYREADY) + +/** DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type **/ +#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /* DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /* DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /* Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /* Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /* Generic short write, two parameters */ + +/** DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type **/ +#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /* DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /* Generic long write */ + +/** DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type **/ +#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006U) /* DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /* Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /* Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /* Generic short read, two parameters */ + +#define DSI_EOTP ((uint32_t)0x00000008U) + +/** DSI_Lane_Group DSI Lane Group **/ +#define DSI_CLOCK_LANE ((uint32_t)0x00000000U) +#define DSI_DATA_LANES ((uint32_t)0x00000001U) + +/** DSI_Communication_Delay DSI Communication Delay **/ +#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U) +#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U) +#define DSI_HS_DELAY ((uint32_t)0x00000002U) + +/** DSI_CustomLane DSI CustomLane **/ +#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000U) +#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U) + +/** DSI_Lane_Select DSI Lane Select **/ +#define DSI_CLK_LANE ((uint32_t)0x00000000U) +#define DSI_DATA_LANE0 ((uint32_t)0x00000001U) +#define DSI_DATA_LANE1 ((uint32_t)0x00000002U) + +#define DSI_MODE_LPDT (DSI_REGISTER_MASK) +#define DSI_MODE_HSDT (DSI_PKTCTRL_MOD) + +/** DSI Host periph status flag **/ +#define DSI_FLAG_SOT_ERROR (DSI_STS_SOTERR) +#define DSI_FLAG_SOTSYNC_ERROR (DSI_STS_SOTSYNCERR) +#define DSI_FLAG_EOTSYNC_ERROR (DSI_STS_EOTSYNCERR) +#define DSI_FLAG_ESCMOD_ERROR (DSI_STS_ESCMODERR) +#define DSI_FLAG_LPTXSYNC_ERROR (DSI_STS_LPTXSYNCERR) +#define DSI_FLAG_TO_ERROR (DSI_STS_TOERR) +#define DSI_FLAG_FCTRL_ERROR (DSI_STS_FCTRLERR) +#define DSI_FLAG_COTDET_ERROR (DSI_STS_COTDET) +#define DSI_FLAG_ECCSB_ERROR (DSI_STS_ECCSERR) +#define DSI_FLAG_ECCML_ERROR (DSI_STS_ECCMERR) +#define DSI_FLAG_CRC_ERROR (DSI_STS_CRCERR) +#define DSI_FLAG_DATATYPE_ERROR (DSI_STS_DATYPERR) +#define DSI_FLAG_VCIDINVLID_ERROR (DSI_STS_VCIDINVLD) +#define DSI_FLAG_INVLID_TXLEN_ERROR (DSI_STS_INVLDTXL) +#define DSI_FLAG_PROVILT_ERROR (DSI_STS_PROVILT) +#define DSI_FLAG_BIT0_ERROR (DSI_STS_BIT0) +#define DSI_FLAG_BIT1_ERROR (DSI_STS_BIT1) +#define DSI_FLAG_BIT2_ERROR (DSI_STS_BIT2) +#define DSI_FLAG_BIT3_ERROR (DSI_STS_BIT3) + +/** DSI Host RX error status flag **/ +#define DSI_ERROR_FLAG_ECCSB (DSI_ERRSTS_ECCSERR) +#define DSI_ERROR_FLAG_ECCML (DSI_ERRSTS_ECCMERR) +#define DSI_ERROR_FLAG_CRC (DSI_ERRSTS_CRCERR) +#define DSI_ERROR_FLAG_HTXTO (DSI_ERRSTS_HTXTOERR) +#define DSI_ERROR_FLAG_LRXTO (DSI_ERRSTS_LRXTOERR) +#define DSI_ERROR_FLAG_BATTO (DSI_ERRSTS_BATTOERR) + +/** DSI Host packet status flag **/ +#define DSI_PKT_FLAG_NIDLE (DSI_PKTSTS_NIDLE) +#define DSI_PKT_FLAG_TXD (DSI_PKTSTS_TXD) +#define DSI_PKT_FLAG_DPHYDIR (DSI_PKTSTS_DPHYDIR) +#define DSI_PKT_FLAG_TXFOVER (DSI_PKTSTS_TXFOVER) +#define DSI_PKT_FLAG_TXFUNDER (DSI_PKTSTS_TXFUNDER) +#define DSI_PKT_FLAG_RXFOVER (DSI_PKTSTS_RXFOVER) +#define DSI_PKT_FLAG_RXFUNDER (DSI_PKTSTS_RXFUNDER) +#define DSI_PKT_FLAG_RXPKTD (DSI_PKTSTS_RXPKTD) +#define DSI_PKT_FLAG_ALLRXPKTD (DSI_PKTSTS_ALLRXPKTD) + +/** DSI Wrapper interrupt sources **/ +#define DSI_WRAPPER_INT_BLKERRIEN (DSI_WRPCTRL_BLKEERIEN) +#define DSI_WRAPPER_INT_SPERRIEN (DSI_WRPCTRL_SPERRIEN) +#define DSI_WRAPPER_INT_OVERRIEN (DSI_WRPCTRL_OVERRIEN) +#define DSI_WRAPPER_INT_UNDERRIEN (DSI_WRPCTRL_UNDERRIEN) + +/** DSI Wrapper Flag **/ +#define DSI_WRAPPER_FLAG_ISKEWCALDN (DSI_WRPSTS_ISKEWCALDN) +#define DSI_WRAPPER_FLAG_PSKEWCALDN (DSI_WRPSTS_PSKEWCALDN) +#define DSI_WRAPPER_FLAG_TRIGACK (DSI_WRPSTS_TRIGACK) +#define DSI_WRAPPER_FLAG_BLKERRIEN (DSI_WRPSTS_BLKERRF) +#define DSI_WRAPPER_FLAG_SPERRIEN (DSI_WRPSTS_SPERRIEN) +#define DSI_WRAPPER_FLAG_OVERRIEN (DSI_WRPSTS_OVERRIEN) +#define DSI_WRAPPER_FLAG_UNDERRIEN (DSI_WRPSTS_UNDERRIEN) + + +/** DSI Lock structures definition **/ +typedef enum +{ + DSI_UNLOCKED = 0x00, + DSI_LOCKED = 0x01 +} DSI_LockTypeDef; + +/** DSI Status structures definition **/ +typedef enum +{ + DSI_OK = 0x00, + DSI_RESET = 0x01, + DSI_READY = 0x02, + DSI_ERROR = 0x03, + DSI_BUSY = 0x04, + DSI_TIMEOUT = 0x05 +} DSI_StateTypeDef; + +/** DSI Host Init Structure definition **/ +typedef struct +{ + uint32_t NumOfLanes; /* Number of lanes */ + uint32_t BurstSel; /* Select combined burst or not */ + uint32_t AutoInsertEOTP; /* Select auto insert EOTP or not */ + uint32_t DisRXCRC; /* Select check CRC or not */ +} DSI_HostInitTypeDef; + +/** DSI Clock structure definition **/ +typedef struct +{ + uint32_t ClockBeforeHS; /* Set the number of byte clock periods before HS */ + uint32_t ClockHS2LP; /* Set the number of byte clock periods before clock lane into LP after detected in stop state */ + uint32_t ClockLP2HS; /* Set the number of byte clock periods LP mode to HS mode */ + uint32_t ClockExitULPS; /* Set the number of byte clock periods in MARK_1 state after exiting ULPS */ + uint32_t ContinuousHSCLK; /* Select the continuous HS clock or non-continuous HS clock */ +} DSI_ClockInitTypeDef; + +/** DSI Skew Calibration Clock structure definition **/ +typedef struct +{ + uint32_t ClockInitialSkewcal; /* Set the number of byte clock consumed by an initial skewcal */ + uint32_t ClockPeriodicSkewcal; /* Set the number of byte clock consumed by a periodic skewcal */ + uint32_t ClockAlternateCal; /* Set the number of byte clock consumed by an alternate calibration */ + uint32_t LinePeriodicSkewcal; /* Set the lane to issue periodic */ +} DSI_SkewcalInitTypeDef; + + +/** DSI PHY Clock structure definition **/ +typedef struct +{ + uint32_t RefCLK_In_Sel; + uint32_t PLL_PRE_DIV; + uint32_t PLL_FBK_INT; + uint32_t EXTD_CYCLE_SEL; + uint32_t PLL_FBK_FRA23_16; + uint32_t PLL_FBK_FRA15_8; + uint32_t PLL_FBK_FRA7_0; + uint32_t PLL_SSC_PRD9_8; + uint32_t PLL_SSC_PRD7_0; + uint32_t PLL_SSC_DELTA_INIT17_16; + uint32_t PLL_SSC_DELTA_INIT15_8; + uint32_t PLL_SSC_DELTA_INIT7_0; + uint32_t PLL_SSC_DELTA17_16; + uint32_t PLL_SSC_DELTA15_8; + uint32_t PLL_SSC_DELTA7_0; + uint32_t DLANE_HS_PER_TIME; + uint32_t DLANE_HS_ZERO_TIME; + uint32_t DLANE_HS_TRAIL_TIME; + uint32_t CLANE_HS_PER_TIME; + uint32_t CLANE_HS_ZERO_TIME; + uint32_t CLANE_HS_TRAIL_TIME; + uint32_t CLANE_HS_CLK_PRE_TIME; + uint32_t CLANE_HS_CLK_POST_TIME; + uint32_t L0_Swap_Sel_Value; // data/clock lane value config to PAD_CDTX_L0X + uint32_t L1_Swap_Sel_Value; // data/clock lane value config to PAD_CDTX_L1X + uint32_t L2_Swap_Sel_Value; // data/clock lane value config to PAD_CDTX_L2X + uint32_t L3_Swap_Sel_Value; // data/clock lane value config to PAD_CDTX_L3X + uint32_t L4_Swap_Sel_Value; // data/clock lane value config to PAD_CDTX_L4X +} DSI_PHY_InitTypeDef; + + +/** DSI Video mode configuration **/ +typedef struct +{ + uint32_t PixelsPerPacket; /* Number of pixels to be sent on a video line */ + uint32_t PixelPayloadSize; /* Maximum number of pixels that should be sent as one DSI packet */ + uint32_t PixelAlignment; /* Set the alignment of pixels smaller than the maximum pixel size */ + uint32_t PixelFormat; /* Set the pixel format */ + uint32_t VSPolarity; /* VSYNC pin polarity */ + uint32_t HSPolarity; /* HSYNC pin polarity */ + uint32_t Mode; /* Video mode type */ + uint32_t Override; /* Select CFG_VID parameters or first video frame is used to calibrate */ + uint32_t DelayFromStart; /* Set the number of cycles to delay the start of line */ + uint32_t HorizontalFrontPorch; /* Horizontal front-porch duration, Only Override = 1 need to program */ + uint32_t HorizontalBackPorch; /* Horizontal back-porch duration (in lane byte clock cycles), Only Override = 1 need to program */ + uint32_t HorizontalSyncActive; /* Horizontal synchronism active duration (in lane byte clock cycles), Only Override = 1 need to program */ + uint32_t PacketsPerLine; /* Multiple packets per video line */ + uint32_t VerticalBackPorch; /* Vertical back-porch duration, Only Override = 1 need to program */ + uint32_t VerticalFrontPorch; /* Vertical front-porch duration, Only Override = 1 need to program */ + uint32_t BLLPMode; /* Select blanking packets or LP mode in BLLP */ + uint32_t NULLPacketInBLLP; /* Select blanking packet or NULL packet in BLLP */ + uint32_t VerticalActive; /* Vertical active duration, Only Override = 1 need to program */ + uint32_t VirtualChannel; /* Virtual channel ID */ + uint32_t ExternalPacket; /* Select external to the video interface packet requests are allowed */ + uint32_t VerticalSyncStartPayload; /* Set the payload value for vertical sync start */ + uint32_t PayloadPerPacket; /* Set the payload in a multipacket per video line */ +} DSI_VidCfgTypeDef; + +/** DSI HOST Timeouts definition **/ +typedef struct +{ + uint32_t HighSpeedTXTimeout; /* High-speed tx time-out */ + uint32_t LowPowerRxTimeout; /* Low-power rx time-out */ + uint32_t BTATimeout; /* Bus turn around BTA time-out */ +} DSI_TimeoutCfgTypeDef; + +/** DSI Adapted command mode configuration **/ +typedef struct +{ + uint32_t VirtualChannelID; /* Virtual channel ID */ + uint32_t ColorCoding; /* Color coding for LCDC interface */ + uint32_t CommandSize; /* Maximum allowed size for an LCDC write memory command, measured in pixels.*/ + uint32_t TearingEffectSource; /* Tearing effect source */ + uint32_t TearingEffectPolarity; /* Tearing effect pin polarity */ + uint32_t HSPolarity; /* HSYNC pin polarity */ + uint32_t VSPolarity; /* VSYNC pin polarity */ + uint32_t DEPolarity; /* Data Enable pin polarity */ + uint32_t VSyncPol; /* VSync edge on which the LCDC is halted */ + uint32_t AutomaticRefresh; /* Automatic refresh mode */ + uint32_t TEAcknowledgeRequest; /* Tearing Effect Acknowledge Request Enable */ +} DSI_CmdCfgTypeDef; + +/** DSI lowpower command transmission mode configuration **/ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /* Generic Short Write Zero parameters Transmission */ + uint32_t LPGenShortWriteOneP; /* Generic Short Write One parameter Transmission */ + uint32_t LPGenShortWriteTwoP; /* Generic Short Write Two parameters Transmission */ + uint32_t LPGenShortReadNoP; /* Generic Short Read Zero parameters Transmission */ + uint32_t LPGenShortReadOneP; /* Generic Short Read One parameter Transmission */ + uint32_t LPGenShortReadTwoP; /* Generic Short Read Two parameters Transmission */ + uint32_t LPGenLongWrite; /* Generic Long Write Transmission */ + uint32_t LPDcsShortWriteNoP; /* DCS Short Write Zero parameters Transmission */ + uint32_t LPDcsShortWriteOneP; /* DCS Short Write One parameter Transmission */ + uint32_t LPDcsShortReadNoP; /* DCS Short Read Zero parameters Transmission */ + uint32_t LPDcsLongWrite; /* DCS Long Write Transmission */ + uint32_t LPMaxReadPacket; /* Maximum Read Packet Size Transmission */ + uint32_t AcknowledgeRequest; /* Acknowledge Request Enable */ +} DSI_LPCmdTypeDef; + +/** DSI PHY Timings definition **/ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /* The maximum time that the D-PHY clock lane takes to go from high-speed to low-power transmission */ + uint32_t ClockLaneLP2HSTime; /* The maximum time that the D-PHY clock lane takes to go from low-power to high-speed transmission */ + uint32_t DataLaneHS2LPTime; /* The maximum time that the D-PHY data lanes takes to go from high-speed to low-power transmission */ + uint32_t DataLaneLP2HSTime; /* The maximum time that the D-PHY data lanes takes to go from low-power to high-speed transmission */ + uint32_t DataLaneMaxReadTime; /* The maximum time required to perform a read command */ + uint32_t StopWaitTime; /* The minimum wait period to request a High-Speed transmission after the Stop state */ +} DSI_PHY_TimerTypeDef; + +/** DSI Packet header type define **/ +typedef struct +{ + uint32_t WordCount; /* DSI packet word count */ + uint32_t ChannelID; /* DSI packet virtual channel */ + uint32_t DataType; /* DSI Error monitoring mask */ +} DSI_PKTHeaderTypeDef; + +/** DSI Packet Control type define **/ +typedef struct +{ + DSI_PKTHeaderTypeDef Header; + uint32_t CmdType; + uint32_t IsBTAEnable; + uint32_t IsBTAOnly; +} DSI_PKTCtrlTypeDef; + + +/** DSI handle Structure definition **/ +typedef struct +{ + DSI_Module *Instance; /* DSI Register base address */ + DSI_Wrapper_Module *InstanceWrap; /* DSI Wrapper Register base address */ + DSI_HostInitTypeDef HostInit; /* DSI required parameters */ + DSI_ClockInitTypeDef ClockInit; /* DSI required parameters */ + DSI_SkewcalInitTypeDef SkewcalInit; /* DSI optional required parameters */ + DSI_LockTypeDef Lock; /* DSI peripheral status */ + __IO DSI_StateTypeDef State; /* DSI communication state */ + __IO uint32_t ErrorCode; /* DSI Error code */ + uint32_t ErrorMsk; /* DSI Error monitoring mask */ +} DSI_HandleTypeDef; + + + +DSI_StateTypeDef DSI_EnableResetTrigger(DSI_HandleTypeDef *hdsi); + +void DSI_EnableWrapper(DSI_HandleTypeDef *hdsi, FunctionalState Cmd); +void DSI_Disable(DSI_HandleTypeDef *hdsi); + +void DSI_EnableClockLane(DSI_HandleTypeDef *hdsi, FunctionalState Cmd); +void DSI_ConfigDataLaneNum(DSI_HandleTypeDef *hdsi, uint32_t datalinenum); + +void DSI_CofigWrapULPSDL(DSI_HandleTypeDef *hdsi, uint32_t datalinenum, FunctionalState Cmd); +void DSI_EnableWrapULPSCL(DSI_HandleTypeDef *hdsi, FunctionalState Cmd); +DSI_StateTypeDef DSI_EnterULPSData(DSI_HandleTypeDef *hdsi, FunctionalState Cmd); +DSI_StateTypeDef DSI_EnterULPSClock(DSI_HandleTypeDef *hdsi); +DSI_StateTypeDef DSI_ExitULPSClock(DSI_HandleTypeDef *hdsi); +DSI_StateTypeDef DSI_EnterULPS(DSI_HandleTypeDef *hdsi); +DSI_StateTypeDef DSI_ExitULPS(DSI_HandleTypeDef *hdsi); + +void DSI_DisableSkewCal(DSI_HandleTypeDef *hdsi); +void DSI_EnableWrapperISkewCal(DSI_HandleTypeDef *hdsi, FunctionalState Cmd); +void DSI_EnableWrapperPSkewCal(DSI_HandleTypeDef *hdsi, FunctionalState Cmd); +DSI_StateTypeDef DSI_EnableInitialSkewCalib(DSI_HandleTypeDef *hdsi); +DSI_StateTypeDef DSI_EnablePeriodSkewCali(DSI_HandleTypeDef *hdsi); + +void DSI_SetVCID(DSI_HandleTypeDef *hdsi, uint32_t channel); +DSI_StateTypeDef DSI_ConfigTimeout(DSI_HandleTypeDef *hdsi, uint32_t hstxcnt, uint32_t lprxcnt, uint32_t btacnt); +DSI_StateTypeDef DSI_Start(DSI_HandleTypeDef *hdsi); + + +DSI_StateTypeDef DSI_APBPKT_ShortWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t Speed, uint32_t Param1, uint32_t Param2); +DSI_StateTypeDef DSI_APBPKT_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t Speed, uint8_t *ParametersTable, uint32_t NbParams); +DSI_StateTypeDef DSI_LongWrite(DSI_HandleTypeDef *hdsi, DSI_PKTCtrlTypeDef PacketCtrl, uint8_t *ParametersTable); +DSI_StateTypeDef DSI_APBPKT_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, uint8_t *ParametersTable); +DSI_StateTypeDef DSI_APBPKT_Read_BTA(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, uint32_t Size, uint32_t Mode); +DSI_StateTypeDef DSI_Read(DSI_HandleTypeDef *hdsi, uint8_t *RxArray, uint32_t RxSize); + +void DSI_Wrapper_ConfigInt(DSI_HandleTypeDef *hdsi, uint32_t DSI_IT, FunctionalState Cmd); +FlagStatus DSI_Wrapper_GetFlagStatus(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG); +void DSI_Wrapper_ClearFlag(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG); +INTStatus DSI_Wrapper_GetIntStatus(DSI_HandleTypeDef *hdsi, uint32_t DSI_IT); + +FlagStatus DSI_GetPHYStatus(DSI_HandleTypeDef *hdsi); +FlagStatus DSI_GetSTS(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG); +FlagStatus DSI_GetERRSTS(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG); +FlagStatus DSI_GetPKTSTS(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG); + +DSI_StateTypeDef DSI_DeInit(DSI_HandleTypeDef *hdsi); +void DSI_InitHostWrap(DSI_HandleTypeDef *hdsi); +void DSI_InitPHY(DSI_HandleTypeDef *hdsi, DSI_PHY_InitTypeDef *PHY_InitParams); +DSI_StateTypeDef DSI_Init(DSI_HandleTypeDef *hdsi); +DSI_StateTypeDef DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_DSI_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsmu.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsmu.h new file mode 100644 index 0000000000..0b35e3d49c --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dsmu.h @@ -0,0 +1,446 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dsmu.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76x_78x_DSMU_H__ +#define __N32H76x_78x_DSMU_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** DSMU channel output clock structure definition **/ +typedef struct +{ + FunctionalState Activation; /* Output clock enable/disable */ + uint32_t Selection; /* Output clock is system clock or audio clock. + This parameter can be a value of @ref DSMU_Channel_OuputClock */ + uint32_t Divider; /* Output clock divider. + This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ +}DSMU_Channel_OutputClockType; + +/** DSMU channel input structure definition **/ +typedef struct +{ + uint32_t Multiplexer; /* Input is external serial inputs, internal register or ADC output. + This parameter can be a value of @ref DSMU_Channel_InputMultiplexer */ + uint32_t DataPacking; /* Standard, interleaved or dual mode for internal register. + This parameter can be a value of @ref DSMU_Channel_DataPacking */ + uint32_t Pins; /* Input pins are taken from same or following channel. + This parameter can be a value of @ref DSMU_Channel_InputPins */ +}DSMU_Channel_InputType; + +/** DSMU channel serial interface structure definition **/ +typedef struct +{ + uint32_t Type; /* SPI or Manchester modes. + This parameter can be a value of @ref DSMU_Channel_SerialInterfaceType */ + uint32_t SpiClock; /* SPI clock select (external or internal with different sampling point). + This parameter can be a value of @ref DSMU_Channel_SpiClock */ +} DSMU_Channel_SerialInterfaceType; + +/** DSMU channel analog watchdog structure definition **/ +typedef struct +{ + uint32_t FilterOrder; /* Analog watchdog Sinc filter order. + This parameter can be a value of @ref DSMU_Channel_AwdFilterOrder */ + uint32_t Oversampling; /* Analog watchdog filter oversampling ratio. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ +} DSMU_Channel_AwdType; + +/** DSMU channel init structure definition **/ +typedef struct +{ + DSMU_Channel_OutputClockType OutputClock; /* DSMU channel output clock parameters */ + DSMU_Channel_InputType Input; /* DSMU channel input parameters */ + DSMU_Channel_SerialInterfaceType SerialInterface; /* DSMU channel serial interface parameters */ + DSMU_Channel_AwdType Awd; /* DSMU channel analog watchdog parameters */ + int32_t Offset; /* DSMU channel offset. + This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ + uint32_t RightBitShift; /* DSMU channel right bit shift. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ +} DSMU_Channel_InitType; + +/** DSMU filter regular conversion parameters structure definition **/ +typedef struct +{ + uint32_t Trigger; /* Trigger used to start regular conversion: software or synchronous. + This parameter can be a value of @ref DSMU_Filter_Trigger */ + FunctionalState FastMode; /* Enable/disable fast mode for regular conversion */ + FunctionalState DmaMode; /* Enable/disable DMA for regular conversion */ +} DSMU_Filter_RegularParamType; + +/** DSMU filter injected conversion parameters structure definition **/ +typedef struct +{ + uint32_t Trigger; /* Trigger used to start injected conversion: software, external or synchronous. + This parameter can be a value of @ref DSMU_Filter_Trigger */ + FunctionalState ScanMode; /* Enable/disable scanning mode for injected conversion */ + FunctionalState DmaMode; /* Enable/disable DMA for injected conversion */ + uint32_t ExtTrigger; /* External trigger. + This parameter can be a value of @ref DSMU_Filter_ExtTrigger */ +} DSMU_Filter_InjectedParamType; + +/** DSMU filter parameters structure definition **/ +typedef struct +{ + uint32_t SincOrder; /* Sinc filter order. + This parameter can be a value of @ref DSMU_Filter_SincOrder */ + uint32_t Oversampling; /* Filter oversampling ratio. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t IntOversampling; /* Integrator oversampling ratio. + This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ +} DSMU_Filter_FilterParamType; + +/** DSMU filter init structure definition **/ +typedef struct +{ + DSMU_Filter_RegularParamType RegularParam; /* DSMU regular conversion parameters */ + DSMU_Filter_InjectedParamType InjectedParam; /* DSMU injected conversion parameters */ + DSMU_Filter_FilterParamType FilterParam; /* DSMU filter parameters */ +} DSMU_Filter_InitType; + + +/** DSMU filter analog watchdog parameters structure definition **/ +typedef struct +{ + uint32_t DataSource; /* Values from digital filter or from channel watchdog filter. + This parameter can be a value of @ref DSMU_Filter_AwdDataSource */ + uint32_t ChannelSelect; /* Analog watchdog channel selection. + This parameter can be a values combination of @ref DSMU_Channel_Selection */ + int32_t HighThreshold; /* High threshold for the analog watchdog. + This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ + int32_t LowThreshold; /* Low threshold for the analog watchdog. + This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ + uint32_t HighBreakSignal; /* Break signal assigned to analog watchdog high threshold event. + This parameter can be a values combination of @ref DSMU_BreakSignals */ + uint32_t LowBreakSignal; /* Break signal assigned to analog watchdog low threshold event. + This parameter can be a values combination of @ref DSMU_BreakSignals */ +} DSMU_Filter_AwdParamType; + +/** DSMU_Channel_OuputClock DSMU channel output clock selection **/ +#define DSMU_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /* Source for output clock is system clock */ +#define DSMU_CHANNEL_OUTPUT_CLOCK_AUDIO (DSMU_CHYCFG1_CLKOUTSRC) /* Source for output clock is audio clock */ + +/** DSMU_Channel_InputMultiplexer DSMU channel input multiplexer **/ +#define DSMU_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /* Data are taken from external inputs */ +#define DSMU_CHANNEL_ADC_OUTPUT (DSMU_CHYCFG1_DATMUX_0) /* Data are taken from ADC output */ +#define DSMU_CHANNEL_INTERNAL_REGISTER (DSMU_CHYCFG1_DATMUX_1) /* Data are taken from internal register */ + +/** DSMU_Channel_DataPacking DSMU channel input data packing **/ +#define DSMU_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /* Standard data packing mode */ +#define DSMU_CHANNEL_INTERLEAVED_MODE (DSMU_CHYCFG1_DATPACK_0) /* Interleaved data packing mode */ +#define DSMU_CHANNEL_DUAL_MODE (DSMU_CHYCFG1_DATPACK_1) /* Dual data packing mode */ + +/** DSMU_Channel_InputPins DSMU channel input pins **/ +#define DSMU_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /* Input from pins on same channel */ +#define DSMU_CHANNEL_FOLLOWING_CHANNEL_PINS (DSMU_CHYCFG1_CHINSEL) /* Input from pins on following channel */ + +/** DSMU_Channel_SerialInterfaceType DSMU channel serial interface type **/ +#define DSMU_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /* SPI with rising edge */ +#define DSMU_CHANNEL_SPI_FALLING (DSMU_CHYCFG1_SITP_0) /* SPI with falling edge */ +#define DSMU_CHANNEL_MANCHESTER_RISING (DSMU_CHYCFG1_SITP_1) /* Manchester with rising edge */ +#define DSMU_CHANNEL_MANCHESTER_FALLING (DSMU_CHYCFG1_SITP) /* Manchester with falling edge */ + +/** DSMU_Channel_SpiClock DSMU channel SPI clock selection **/ +#define DSMU_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /* External SPI clock */ +#define DSMU_CHANNEL_SPI_CLOCK_INTERNAL (DSMU_CHYCFG1_SPICLKSEL_0) /* Internal SPI clock */ +#define DSMU_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING (DSMU_CHYCFG1_SPICLKSEL_1) /* Internal SPI clock divided by 2, falling edge */ +#define DSMU_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING (DSMU_CHYCFG1_SPICLKSEL) /* Internal SPI clock divided by 2, rising edge */ + +/** DSMU_Channel_AwdFilterOrder DSMU channel analog watchdog filter order **/ +#define DSMU_AWD_FASTSINC_ORDER ((uint32_t)0x00000000U) /* FastSinc filter type */ +#define DSMU_AWD_SINC1_ORDER (DSMU_CHYAWDSCDET_AWDFORD_0) /* Sinc 1 filter type */ +#define DSMU_AWD_SINC2_ORDER (DSMU_CHYAWDSCDET_AWDFORD_1) /* Sinc 2 filter type */ +#define DSMU_AWD_SINC3_ORDER (DSMU_CHYAWDSCDET_AWDFORD) /* Sinc 3 filter type */ + +/** DSMU_Filter_Trigger DSMU filter conversion trigger **/ +#define DSMU_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /* Software trigger */ +#define DSMU_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /* Synchronous with DSMU_FLT0 */ +#define DSMU_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /* External trigger (only for injected conversion) */ + +/** DSMU_Channel_Selection DSMU filter channel select **/ +/* bit[31:24] used for FLTxCTRL1.RCH[2:0]*/ +/* bit[23:16] used for FLTxCTRL2.AWDCH[7:0]*/ +/* bit[15:8] used for FLTxCTRL2.EXDETCH[7:0]*/ +/* bit[7:0] used for FLTxJCHG.JCHG[7:0]*/ +#define DSMU_CHANNEL_SELECT_0 ((uint32_t)0x00010101U) /* Select Channel 0 */ +#define DSMU_CHANNEL_SELECT_1 ((uint32_t)0x01020202U) /* Select Channel 1 */ +#define DSMU_CHANNEL_SELECT_2 ((uint32_t)0x02040404U) /* Select Channel 2 */ +#define DSMU_CHANNEL_SELECT_3 ((uint32_t)0x03080808U) /* Select Channel 3 */ +#define DSMU_CHANNEL_SELECT_4 ((uint32_t)0x04101010U) /* Select Channel 4 */ +#define DSMU_CHANNEL_SELECT_5 ((uint32_t)0x05202020U) /* Select Channel 5 */ +#define DSMU_CHANNEL_SELECT_6 ((uint32_t)0x06404040U) /* Select Channel 6 */ +#define DSMU_CHANNEL_SELECT_7 ((uint32_t)0x07808080U) /* Select Channel 7 */ + +/** DSMU_Filter_ExtTrigger DSMU filter external trigger **/ +#define DSMU_FILTER_EXT_TRIG_ATIM1_TRGO ((uint32_t)0x00000000U) /* Select ATIM1_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_ATIM2_TRGO ((uint32_t)0x00000100U) /* Select ATIM2_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_ATIM3_TRGO ((uint32_t)0x00000200U) /* Select ATIM3_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_ATIM4_TRGO ((uint32_t)0x00000300U) /* Select ATIM4_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMB1_TRGO ((uint32_t)0x00000400U) /* Select GTIMB1_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMB2_TRGO ((uint32_t)0x00000500U) /* Select GTIMB2_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMB3_TRGO ((uint32_t)0x00000600U) /* Select GTIMB3_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMA1_TRGO ((uint32_t)0x00000700U) /* Select GTIMA1_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMA2_TRGO ((uint32_t)0x00000800U) /* Select GTIMA2_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMA3_TRGO ((uint32_t)0x00000900U) /* Select GTIMA3_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMA4_TRGO ((uint32_t)0x00000A00U) /* Select GTIMA4_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_GTIMA5_TRGO ((uint32_t)0x00000B00U) /* Select GTIMA5_TRGO as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_ATIM1_TRGO2 ((uint32_t)0x00000C00U) /* Select ATIM1_TRGO2 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_ATIM3_TRGO2 ((uint32_t)0x00000D00U) /* Select ATIM3_TRGO2 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG1 ((uint32_t)0x00000E00U) /* Select SHRTIM1_ADC_TRG1 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG2 ((uint32_t)0x00000F00U) /* Select SHRTIM1_ADC_TRG2 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG3 ((uint32_t)0x00001000U) /* Select SHRTIM1_ADC_TRG3 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG4 ((uint32_t)0x00001100U) /* Select SHRTIM1_ADC_TRG4 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG1 ((uint32_t)0x00001200U) /* Select SHRTIM2_ADC_TRG1 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG2 ((uint32_t)0x00001300U) /* Select SHRTIM2_ADC_TRG2 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG3 ((uint32_t)0x00001400U) /* Select SHRTIM2_ADC_TRG3 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG4 ((uint32_t)0x00001500U) /* Select SHRTIM2_ADC_TRG4 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI6 ((uint32_t)0x00001600U) /* Select EXTI6 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI7 ((uint32_t)0x00001700U) /* Select EXTI7 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI8 ((uint32_t)0x00001800U) /* Select EXTI8 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI9 ((uint32_t)0x00001900U) /* Select EXTI9 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI10 ((uint32_t)0x00001A00U) /* Select EXTI10 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI11 ((uint32_t)0x00001B00U) /* Select EXTI11 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI12 ((uint32_t)0x00001C00U) /* Select EXTI12 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI13 ((uint32_t)0x00001D00U) /* Select EXTI13 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI14 ((uint32_t)0x00001E00U) /* Select EXTI14 as trigger signal for injected conversion */ +#define DSMU_FILTER_EXT_TRIG_EXTI15 ((uint32_t)0x00001F00U) /* Select EXTI15 as trigger signal for injected conversion */ + +/** DSMU_Filter_ExtTriggerEdge DSMU filter external trigger edge **/ +#define DSMU_FILTER_EXT_TRIG_DISABLE ((uint32_t)0x00000000U) /* External trigger disable */ +#define DSMU_FILTER_EXT_TRIG_RISING_EDGE (DSMU_FLTXCTRL1_JEXTEN_0) /* External rising edge */ +#define DSMU_FILTER_EXT_TRIG_FALLING_EDGE (DSMU_FLTXCTRL1_JEXTEN_1) /* External falling edge */ +#define DSMU_FILTER_EXT_TRIG_BOTH_EDGES (DSMU_FLTXCTRL1_JEXTEN) /* External rising and falling edges */ + +/** DSMU_Filter_SincOrder DSMU filter sinc order **/ +#define DSMU_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /* FastSinc filter type */ +#define DSMU_FILTER_SINC1_ORDER ( DSMU_FLTXFCTRL_FORD_0) /* Sinc 1 filter type */ +#define DSMU_FILTER_SINC2_ORDER ( DSMU_FLTXFCTRL_FORD_1) /* Sinc 2 filter type */ +#define DSMU_FILTER_SINC3_ORDER ( DSMU_FLTXFCTRL_FORD_0 \ + | DSMU_FLTXFCTRL_FORD_1) /* Sinc 3 filter type */ +#define DSMU_FILTER_SINC4_ORDER ( DSMU_FLTXFCTRL_FORD_2) /* Sinc 4 filter type */ +#define DSMU_FILTER_SINC5_ORDER ( DSMU_FLTXFCTRL_FORD_0 \ + | DSMU_FLTXFCTRL_FORD_2) /* Sinc 5 filter type */ + +/** DSMU_Filter_AwdDataSource DSMU filter analog watchdog data source **/ +#define DSMU_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /* From digital filter */ +#define DSMU_FILTER_AWD_CHANNEL_DATA (DSMU_FLTXCTRL1_AWDFSEL) /* From analog watchdog channel */ + +/** DSMU_BreakSignals DSMU break signals **/ +#define DSMU_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /* No break signal */ +#define DSMU_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /* Break signal 0 */ +#define DSMU_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /* Break signal 1 */ +#define DSMU_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /* Break signal 2 */ +#define DSMU_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /* Break signal 3 */ + +/** DSMU_ContinuousMode DSMU Continuous Mode **/ +#define DSMU_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /* Conversion are not continuous */ +#define DSMU_CONTINUOUS_CONV_ON (DSMU_FLTXCTRL1_RCONT) /* Conversion are continuous */ + +/** DSMU_AwdThreshold DSMU analog watchdog threshold **/ +#define DSMU_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /* Analog watchdog high threshold */ +#define DSMU_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /* Analog watchdog low threshold */ + +/** DSMU interrupt enable bit **/ +#define DSMU_INT_CLOCK_ABSENCE (DSMU_FLTXCTRL2_CLKABIEN) /* Clock absence interrupt enable */ +#define DSMU_INT_SHORT_CIRCUIT (DSMU_FLTXCTRL2_SCDETIEN) /* Short circuit interrupt enable */ +#define DSMU_INT_ANALOG_WATCHDOG (DSMU_FLTXCTRL2_AWDIEN) /* Analog watchdog interrupt enable */ +#define DSMU_INT_REGULAR_OVERRUN (DSMU_FLTXCTRL2_ROVRIEN) /* Regular conversion overrun interrupt enable */ +#define DSMU_INT_INJECT_OVERRUN (DSMU_FLTXCTRL2_JOVRIEN) /* Injected conversion overrun interrupt enable */ +#define DSMU_INT_REGULAR_END (DSMU_FLTXCTRL2_REOCIEN) /* Regular conversion end interrupt enable */ +#define DSMU_INT_INJECT_END (DSMU_FLTXCTRL2_JEOCIEN) /* Injected conversion end interrupt enable */ + +/** DSMU interrupt flag bit **/ +#define DSMU_FLAG_SHORT_CIRCUIT_CH0 (DSMU_FLTXSTS_SCDETF_0) /* Short circuit event flag for channel0 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH1 (DSMU_FLTXSTS_SCDETF_1) /* Short circuit event flag for channel1 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH2 (DSMU_FLTXSTS_SCDETF_2) /* Short circuit event flag for channel2 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH3 (DSMU_FLTXSTS_SCDETF_3) /* Short circuit event flag for channel3 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH4 (DSMU_FLTXSTS_SCDETF_4) /* Short circuit event flag for channel4 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH5 (DSMU_FLTXSTS_SCDETF_5) /* Short circuit event flag for channel5 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH6 (DSMU_FLTXSTS_SCDETF_6) /* Short circuit event flag for channel6 */ +#define DSMU_FLAG_SHORT_CIRCUIT_CH7 (DSMU_FLTXSTS_SCDETF_7) /* Short circuit event flag for channel7 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH0 (DSMU_FLTXSTS_CLKABF_0) /* Clock absence event flag for channel0 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH1 (DSMU_FLTXSTS_CLKABF_1) /* Clock absence event flag for channel1 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH2 (DSMU_FLTXSTS_CLKABF_2) /* Clock absence event flag for channel2 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH3 (DSMU_FLTXSTS_CLKABF_3) /* Clock absence event flag for channel3 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH4 (DSMU_FLTXSTS_CLKABF_4) /* Clock absence event flag for channel4 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH5 (DSMU_FLTXSTS_CLKABF_5) /* Clock absence event flag for channel5 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH6 (DSMU_FLTXSTS_CLKABF_6) /* Clock absence event flag for channel6 */ +#define DSMU_FLAG_CLOCK_ABSENCE_CH7 (DSMU_FLTXSTS_CLKABF_7) /* Clock absence event flag for channel7 */ +#define DSMU_FLAG_REGULAR_ACTIVE (DSMU_FLTXSTS_RCIP) /* Rugular conversion active flag */ +#define DSMU_FLAG_INJECT_ACTIVE (DSMU_FLTXSTS_JCIP) /* Injected conversion active flag */ +#define DSMU_FLAG_ANALOG_WATCHDOG (DSMU_FLTXSTS_AWDF) /* Analog watchdog event flag */ +#define DSMU_FLAG_REGULAR_OVERRUN (DSMU_FLTXSTS_ROVRF) /* Regular conversion overrun flag */ +#define DSMU_FLAG_INJECT_OVERRUN (DSMU_FLTXSTS_JOVRF) /* Injected conversion overrun flag */ +#define DSMU_FLAG_REGULAR_END (DSMU_FLTXSTS_REOCF) /* Regular conversion end flag */ +#define DSMU_FLAG_INJECT_END (DSMU_FLTXSTS_JEOCF) /* Injected conversion end flag */ + +/** DSMU interrupt flag clear bit **/ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH0 (DSMU_FLTXINTCLR_CLRSCDETF_0) /* Clear Short circuit event flag for channel0 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH1 (DSMU_FLTXINTCLR_CLRSCDETF_1) /* Clear Short circuit event flag for channel1 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH2 (DSMU_FLTXINTCLR_CLRSCDETF_2) /* Clear Short circuit event flag for channel2 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH3 (DSMU_FLTXINTCLR_CLRSCDETF_3) /* Clear Short circuit event flag for channel3 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH4 (DSMU_FLTXINTCLR_CLRSCDETF_4) /* Clear Short circuit event flag for channel4 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH5 (DSMU_FLTXINTCLR_CLRSCDETF_5) /* Clear Short circuit event flag for channel5 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH6 (DSMU_FLTXINTCLR_CLRSCDETF_6) /* Clear Short circuit event flag for channel6 */ +#define DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH7 (DSMU_FLTXINTCLR_CLRSCDETF_7) /* Clear Short circuit event flag for channel7 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH0 (DSMU_FLTXINTCLR_CLRCLKABF_0) /* Clear Clock absence event flag for channel0 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH1 (DSMU_FLTXINTCLR_CLRCLKABF_1) /* Clear Clock absence event flag for channel1 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH2 (DSMU_FLTXINTCLR_CLRCLKABF_2) /* Clear Clock absence event flag for channel2 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH3 (DSMU_FLTXINTCLR_CLRCLKABF_3) /* Clear Clock absence event flag for channel3 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH4 (DSMU_FLTXINTCLR_CLRCLKABF_4) /* Clear Clock absence event flag for channel4 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH5 (DSMU_FLTXINTCLR_CLRCLKABF_5) /* Clear Clock absence event flag for channel5 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH6 (DSMU_FLTXINTCLR_CLRCLKABF_6) /* Clear Clock absence event flag for channel6 */ +#define DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH7 (DSMU_FLTXINTCLR_CLRCLKABF_7) /* Clear Clock absence event flag for channel7 */ +#define DSMU_CLEAR_FLAG_REGULAR_OVERRUN (DSMU_FLTXINTCLR_CLRROVRF) /* Clear Regular conversion overrun flag */ +#define DSMU_CLEAR_FLAG_INJECT_OVERRUN (DSMU_FLTXINTCLR_CLRJOVRF) /* Clear Injected conversion overrun flag */ +#define DSMU_CLEAR_FLAG_ALL ( DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH0 | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH1 \ + | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH2 | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH3 \ + | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH4 | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH5 \ + | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH6 | DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH7 \ + | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH0 | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH1 \ + | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH2 | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH3 \ + | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH4 | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH5 \ + | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH6 | DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH7 \ + | DSMU_CLEAR_FLAG_REGULAR_OVERRUN | DSMU_CLEAR_FLAG_INJECT_OVERRUN ) + +/** DSMU analog watchdog flag bit **/ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH0 (DSMU_FLTXAWDSTS_AWDHTF_0) /* Analog wathcdog high threshold error flag for channel0 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH1 (DSMU_FLTXAWDSTS_AWDHTF_1) /* Analog wathcdog high threshold error flag for channel1 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH2 (DSMU_FLTXAWDSTS_AWDHTF_2) /* Analog wathcdog high threshold error flag for channel2 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH3 (DSMU_FLTXAWDSTS_AWDHTF_3) /* Analog wathcdog high threshold error flag for channel3 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH4 (DSMU_FLTXAWDSTS_AWDHTF_4) /* Analog wathcdog high threshold error flag for channel4 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH5 (DSMU_FLTXAWDSTS_AWDHTF_5) /* Analog wathcdog high threshold error flag for channel5 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH6 (DSMU_FLTXAWDSTS_AWDHTF_6) /* Analog wathcdog high threshold error flag for channel6 */ +#define DSMU_AWD_FLAG_HIGH_THRESHOLD_CH7 (DSMU_FLTXAWDSTS_AWDHTF_7) /* Analog wathcdog high threshold error flag for channel7 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH0 (DSMU_FLTXAWDSTS_AWDLTF_0) /* Analog wathcdog low threshold error flag for channel0 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH1 (DSMU_FLTXAWDSTS_AWDLTF_1) /* Analog wathcdog low threshold error flag for channel1 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH2 (DSMU_FLTXAWDSTS_AWDLTF_2) /* Analog wathcdog low threshold error flag for channel2 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH3 (DSMU_FLTXAWDSTS_AWDLTF_3) /* Analog wathcdog low threshold error flag for channel3 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH4 (DSMU_FLTXAWDSTS_AWDLTF_4) /* Analog wathcdog low threshold error flag for channel4 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH5 (DSMU_FLTXAWDSTS_AWDLTF_5) /* Analog wathcdog low threshold error flag for channel5 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH6 (DSMU_FLTXAWDSTS_AWDLTF_6) /* Analog wathcdog low threshold error flag for channel6 */ +#define DSMU_AWD_FLAG_LOW_THRESHOLD_CH7 (DSMU_FLTXAWDSTS_AWDLTF_7) /* Analog wathcdog low threshold error flag for channel7 */ + +/** DSMU analog watchdog flag clear bit **/ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH0 (DSMU_FLTXAWDCLR_CLRAWDHTF_0) /* Clear Analog wathcdog high threshold error flag for channel0 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH1 (DSMU_FLTXAWDCLR_CLRAWDHTF_1) /* Clear Analog wathcdog high threshold error flag for channel1 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH2 (DSMU_FLTXAWDCLR_CLRAWDHTF_2) /* Clear Analog wathcdog high threshold error flag for channel2 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH3 (DSMU_FLTXAWDCLR_CLRAWDHTF_3) /* Clear Analog wathcdog high threshold error flag for channel3 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH4 (DSMU_FLTXAWDCLR_CLRAWDHTF_4) /* Clear Analog wathcdog high threshold error flag for channel4 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH5 (DSMU_FLTXAWDCLR_CLRAWDHTF_5) /* Clear Analog wathcdog high threshold error flag for channel5 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH6 (DSMU_FLTXAWDCLR_CLRAWDHTF_6) /* Clear Analog wathcdog high threshold error flag for channel6 */ +#define DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH7 (DSMU_FLTXAWDCLR_CLRAWDHTF_7) /* Clear Analog wathcdog high threshold error flag for channel7 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH0 (DSMU_FLTXAWDCLR_CLRAWDLTF_0) /* Clear Analog wathcdog low threshold error flag for channel0 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH1 (DSMU_FLTXAWDCLR_CLRAWDLTF_1) /* Clear Analog wathcdog low threshold error flag for channel1 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH2 (DSMU_FLTXAWDCLR_CLRAWDLTF_2) /* Clear Analog wathcdog low threshold error flag for channel2 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH3 (DSMU_FLTXAWDCLR_CLRAWDLTF_3) /* Clear Analog wathcdog low threshold error flag for channel3 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH4 (DSMU_FLTXAWDCLR_CLRAWDLTF_4) /* Clear Analog wathcdog low threshold error flag for channel4 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH5 (DSMU_FLTXAWDCLR_CLRAWDLTF_5) /* Clear Analog wathcdog low threshold error flag for channel5 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH6 (DSMU_FLTXAWDCLR_CLRAWDLTF_6) /* Clear Analog wathcdog low threshold error flag for channel6 */ +#define DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH7 (DSMU_FLTXAWDCLR_CLRAWDLTF_7) /* Clear Analog wathcdog low threshold error flag for channel7 */ +#define DSMU_CLEAR_AWD_FLAG_ALL ( DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH0 | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH1 \ + | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH2 | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH3 \ + | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH4 | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH5 \ + | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH6 | DSMU_CLEAR_AWD_FLAG_HIGH_THRESHOLD_CH7 \ + | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH0 | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH1 \ + | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH2 | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH3 \ + | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH4 | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH5 \ + | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH6 | DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH7) + + +void DSMU_DeInit(void); +void DSMU_InitChannelStruct(DSMU_Channel_InitType* DSMU_ChannelInitStruct); +void DSMU_InitFilterStruct(DSMU_Filter_InitType* DSMU_FilterInitStruct); +ErrorStatus DSMU_ChannelInit(DSMU_Channel_Submodule* DSMU_Channely, DSMU_Channel_InitType* DSMU_ChannelInitStruct); +void DSMU_ChannelDeInit(DSMU_Channel_Submodule* DSMU_Channely); +void DSMU_ChannelCkAbEnable(DSMU_Channel_Submodule* DSMU_Channely); +void DSMU_ChannelCkAbDisable(DSMU_Channel_Submodule* DSMU_Channely); +void DSMU_ChannelScdStart(DSMU_Channel_Submodule* DSMU_Channely,uint32_t Threshold, uint32_t BreakSignal); +void DSMU_ChannelScdStop(DSMU_Channel_Submodule* DSMU_Channely); +int16_t DSMU_ChannelGetAwdValue(const DSMU_Channel_Submodule* DSMU_Channely); +void DSMU_ChannelModifyOffset(DSMU_Channel_Submodule* DSMU_Channely, int32_t Offset); +void DSMU_ChannelWriteData(DSMU_Channel_Submodule* DSMU_Channely,uint32_t data); +ErrorStatus DSMU_FilterInit(DSMU_Filter_Submodule* DSMU_Filterx, DSMU_Filter_InitType* DSMU_FilterInitStruct); +void DSMU_FilterEnable(DSMU_Filter_Submodule* DSMU_Filterx, FunctionalState Cmd); +void DSMU_FilterConfigRegChannel(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t ChannelSelect,uint32_t ContinuousMode); +void DSMU_FilterConfigInjChannel(DSMU_Filter_Submodule* DSMU_Filterx,uint32_t ChannelSelect); +int32_t DSMU_FilterGetRegularValue(const DSMU_Filter_Submodule* DSMU_Filterx, uint32_t* Channel); +int32_t DSMU_FilterGetInjectedValue(const DSMU_Filter_Submodule* DSMU_Filterx,uint32_t* Channel); +void DSMU_FilterAwdStart(DSMU_Filter_Submodule* DSMU_Filterx, DSMU_Filter_AwdParamType* awdParam); +void DSMU_FilterAwdStop(DSMU_Filter_Submodule* DSMU_Filterx); +void DSMU_FilterExdStart(DSMU_Filter_Submodule* DSMU_Filterx,uint32_t ChannelSelect); +void DSMU_FilterExdStop(DSMU_Filter_Submodule* DSMU_Filterx); +int32_t DSMU_FilterGetExdMaxValue(const DSMU_Filter_Submodule* DSMU_Filterx,uint32_t* Channel); +int32_t DSMU_FilterGetExdMinValue(const DSMU_Filter_Submodule* DSMU_Filterx,uint32_t* Channel); +uint32_t DSMU_FilterGetConvTimeValue(const DSMU_Filter_Submodule* DSMU_Filterx); +void DSMU_RegConvStart(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger); +void DSMU_RegConvStop(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger); +void DSMU_InjConvStart(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger, uint32_t TiggerEdge); +void DSMU_InjConvStop(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger); +FlagStatus DSMU_GetFlagStatus(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_IntFlag); +void DSMU_ClearFlag(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_IntFlagClear); +FlagStatus DSMU_GetAwdFlagStatus(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_AwdFlag); +void DSMU_ClearAwdFlag(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_AwdFlagClear); +void DSMU_ConfigInt(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_Int, FunctionalState Cmd); +void DSMU_ConfigRegChDMA(DSMU_Filter_Submodule* DSMU_Filterx, FunctionalState Cmd); +void DSMU_ConfigInjChDMA(DSMU_Filter_Submodule* DSMU_Filterx, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* N32H76x_78x_DSMU_H */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dvp.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dvp.h new file mode 100644 index 0000000000..0016d66e0d --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_dvp.h @@ -0,0 +1,433 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dvp.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_DVP_H +#define __N32H76x_78x_DVP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/*** DVP Structure Definition Start ***/ + +/** DVP Init structure definition **/ +typedef struct +{ + + uint32_t CaptureMode; /* Specifies the capture mode. */ + + uint32_t CropMode; /* Specifies the crop mode. */ + + uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.*/ + + uint16_t CropStartX; /* Specifies the start point x. */ + + uint16_t CropStartY; /* Specifies the start point y. */ + + uint16_t CropEndX; /* Specifies the end point x. */ + + uint16_t CropEndY; /* Specifies the end point y. */ + + uint8_t VBFilter; /* Specifies the VSYNC blanking glitch filtering. */ + + uint32_t PixelClkPolarity; /* Specifies the pixel clock polarity */ + + uint32_t HsyncPolarity; /* Specifies the Horizontal synchronization polarity */ + + uint32_t VsyncPolarity; /* Specifies the vertical synchronization polarity */ + + uint32_t DataInvert; /* Specifies the data invert. */ + + uint32_t DataReverse; /* Specifies the data reverse. */ + + uint32_t DataMode; /* Specifies the data port mode. */ + + uint32_t PixelByte; /* Specifies pixel byte. */ + +}DVP_InitType; + + +/** DVP DMA init structure definition **/ +typedef struct +{ + + uint8_t FrameBufferNum; /* Specifies Frame Buffer number. */ + + uint32_t FrameBufferAddress1; /* Specifies Frame Buffer 1 Address. */ + + uint32_t FrameBufferAddress2; /* Specifies Frame Buffer 2 Address. */ + + uint32_t DisplayStatus; /* Specifies Display buffer status. */ + + uint32_t FifoThreshold; /* Specifies FIFO transmit threshold. */ + + uint32_t BurstSize; /* Specifies Frame Buffer size. */ + + uint32_t FrameBufferSize; /* Specifies Frame Buffer size. */ + +}DVP_DMAInitType; + +/*** DVP Structure Definition End ***/ + +/*** DVP Macro Definition Start ***/ +/** DVP register bit field mask definition **/ +#define DVP_REG_BIT_FIELD_MASK ((uint32_t)0x00000000U) + +/** DVP enable definition**/ +#define DVP_ENABLE (DVP_CTRL_DVPEN) +#define DVP_DISABLE (DVP_INTSTS_DVPDIS) + +/** DVP Capture Mode definition**/ +#define DVP_CAPTURE_MODE_MASK (~DVP_CTRL_CM) +#define DVP_CAPTURE_MODE_CONTINUE (DVP_REG_BIT_FIELD_MASK) +#define DVP_CAPTURE_MODE_SINGLE (DVP_CTRL_CM) + +/** DVP Cropping Feature definition**/ +#define DVP_CROP_MODE_MASK (~DVP_CTRL_CROPEN) +#define DVP_NORMAL_MODE (DVP_REG_BIT_FIELD_MASK) +#define DVP_CROP_MODE (DVP_CTRL_CROPEN) + +/** DVP VSYNC blanking glitch filtering control definition**/ +#define DVP_VBFLT_MASK (~((uint32_t)DVP_CTRL_VBFLT)) + +/** DVP interrupts definition **/ +#define DVP_INT_M1S (DVP_INTEN_M1SIE ) +#define DVP_INT_M2S (DVP_INTEN_M2SIE ) +#define DVP_INT_M1TC (DVP_INTEN_M1TCIE ) +#define DVP_INT_M2TC (DVP_INTEN_M2TCIE ) +#define DVP_INT_FO (DVP_INTEN_FOIE ) +#define DVP_INT_AHBERR (DVP_INTEN_AHBERR ) +#define DVP_INT_MO (DVP_INTEN_MOIE ) +#define DVP_INT_SKIP (DVP_INTEN_SKIPIE ) +#define DVP_INT_CERR (DVP_INTEN_CERRIE ) +#define DVP_INT_SERR (DVP_INTEN_SERRIE ) +#define DVP_INT_FMS (DVP_INTEN_FMSIE ) + +/** DVP flags definition **/ +#define DVP_FLAG_M1S (DVP_INTSTS_M1SF ) +#define DVP_FLAG_M2S (DVP_INTSTS_M2SF ) +#define DVP_FLAG_M1TC (DVP_INTSTS_M1TCF ) +#define DVP_FLAG_M2TC (DVP_INTSTS_M2TCF ) +#define DVP_FLAG_M1FO (DVP_INTSTS_M1FOF ) +#define DVP_FLAG_M2FO (DVP_INTSTS_M2FOF ) +#define DVP_FLAG_AHBERR1 (DVP_INTSTS_AHBERR1F ) +#define DVP_FLAG_AHBERR2 (DVP_INTSTS_AHBERR2F ) +#define DVP_FLAG_M1O (DVP_INTSTS_M1OF ) +#define DVP_FLAG_M2O (DVP_INTSTS_M2OF ) +#define DVP_FLAG_SKIP (DVP_INTSTS_SKIPF ) +#define DVP_FLAG_CERR (DVP_INTSTS_CERRF ) +#define DVP_FLAG_SERR (DVP_INTSTS_SERRF ) +#define DVP_FLAG_FMS (DVP_INTSTS_FMSF ) + +/** DVP pixel clock polarity definition **/ +#define DVP_PIXEL_POLARITY_MASK (~DVP_PORTCFG_PCLKPOL) +#define DVP_PIXEL_POLARITY_RISING (DVP_REG_BIT_FIELD_MASK) /* if the data from the sensor is expected to be latched at the rising edge of the pixel clock. */ +#define DVP_PIXEL_POLARITY_FALLING (DVP_PORTCFG_PCLKPOL) /* if the data from the sensor is expected to be latched at the falling edge of the pixel clock. */ + +/** DVP horizontal polarity definition **/ +#define DVP_HSYNC_POLARITY_MASK (~DVP_PORTCFG_HSPOL) +#define DVP_HSYNC_POLARITY_HIGH (DVP_REG_BIT_FIELD_MASK) /* when HSYNC=0 is high active. */ +#define DVP_HSYNC_POLARITY_LOW (DVP_PORTCFG_HSPOL) /* when HSYNC=1 is low active. */ + +/** DVP vertical polarity definition **/ +#define DVP_VSYNC_POLARITY_MASK (~DVP_PORTCFG_VSPOL) +#define DVP_VSYNC_POLARITY_HIGH (DVP_PORTCFG_VSPOL) /* when VSYNC=1 is high active. */ +#define DVP_VSYNC_POLARITY_LOW (DVP_REG_BIT_FIELD_MASK) /* when VSYNC=0 islow active. */ + +/** DVP Data bit inversion definition **/ +#define DVP_DATA_INVERT_MASK (~DVP_PORTCFG_DATINV) +#define DVP_DATA_INVERT (DVP_PORTCFG_DATINV) /* enable data bit inversion on the DVP port data. */ +#define DVP_DATA_NOTINVERT (DVP_REG_BIT_FIELD_MASK) /* data bit inversion is not enabled. */ + +/** DVP Data bit reverse definition **/ +#define DVP_DATA_REVERSE_MASK (~DVP_PORTCFG_DATRVS) +#define DVP_DATA_REVERSE (DVP_PORTCFG_DATRVS) /* enable to reverse data bit order on the DVP port data. */ +#define DVP_DATA_NOTREVERSE (DVP_REG_BIT_FIELD_MASK) /* remain original data bit order. */ + + +/** DVP Embedded Synchronization Code Position definition **/ +#define DVP_EMBSYNC_POS_MASK (~DVP_PORTCFG_SLC) +#define DVP_EMBSYNC_LSB (DVP_PORTCFG_SLC) /* the sync code is aligned to the least significant bit of the data lines. */ +#define DVP_EMBSYNC_MSB (DVP_REG_BIT_FIELD_MASK) /* the sync code is aligned to the most significant bit of the data lines. */ + +/** DVP Embedded Synchronization Code mode definition **/ +#define DVP_EMBSYNC_MASK (~DVP_PORTCFG_EMBSEN) +#define DVP_SYNC_MODE_SOFTWARE (DVP_PORTCFG_EMBSEN) /* embedded synchronization mode. */ +#define DVP_SYNC_MODE_HARDWARE (DVP_REG_BIT_FIELD_MASK) /* use VSYNC and HSYNC to do synchronization. */ + +/** DVP data port mode definition **/ +#define DVP_DATA_MODE_MASK (~DVP_PORTCFG_DBIT) +#define DVP_DATA_MODE1 (DVP_REG_BIT_FIELD_MASK) /* 8-bit physical data port, and data is captured on all data lines. */ +#define DVP_DATA_MODE2 (DVP_PORTCFG_DBIT0) /* 10-bit physical data port, and data is captured on all data lines. */ +#define DVP_DATA_MODE3 (DVP_PORTCFG_DBIT1) /* 12-bit physical data port, and data is captured on all data lines. */ +#define DVP_DATA_MODE4 (DVP_PORTCFG_DBIT0 | DVP_PORTCFG_DBIT1) /* 14-bit physical data port, and data is captured on all data lines. */ +#define DVP_DATA_MODE5 (DVP_PORTCFG_DBIT2) /* 16-bit physical data port, and data is captured on all data lines. */ +#define DVP_DATA_MODE6 (DVP_PORTCFG_DBIT0 | DVP_PORTCFG_DBIT2) /* 10-bit physical data port, and data is captured on 8 data lines [9:2] only. */ +#define DVP_DATA_MODE7 (DVP_PORTCFG_DBIT1 | DVP_PORTCFG_DBIT2) /* 12-bit physical data port, and data is captured on 10 data lines [11:2] only. */ +#define DVP_DATA_MODE8 (DVP_PORTCFG_DBIT) /* 12-bit physical data port, and data is captured on 8 data lines [11:4] only. */ + +/** DVP pixel bytes definition **/ +#define DVP_PIXEL_BYTE_MASK (~DVP_PORTCFG_PIXELDB) +#define DVP_PIXEL_BYTE1 (DVP_REG_BIT_FIELD_MASK) /* one byte per pixel */ +#define DVP_PIXEL_BYTE2 (DVP_PORTCFG_PIXELDB) /* two byte per pixel */ + +/** DVP bytes mapping definition **/ +#define DVP_BYTE_ORDER_MASK (~DVP_PORTCFG_BMAP) + +#define DVP_BYTE0_ORDER1 (DVP_REG_BIT_FIELD_MASK) +#define DVP_BYTE0_ORDER2 (DVP_PORTCFG_BMAP0) +#define DVP_BYTE0_ORDER3 (DVP_PORTCFG_BMAP1) +#define DVP_BYTE0_ORDER4 (DVP_PORTCFG_BMAP0 | DVP_PORTCFG_BMAP1) + +#define DVP_BYTE1_ORDER1 (DVP_REG_BIT_FIELD_MASK) +#define DVP_BYTE1_ORDER2 (DVP_PORTCFG_BMAP2) +#define DVP_BYTE1_ORDER3 (DVP_PORTCFG_BMAP3) +#define DVP_BYTE1_ORDER4 (DVP_PORTCFG_BMAP2 | DVP_PORTCFG_BMAP3) + +#define DVP_BYTE2_ORDER1 (DVP_REG_BIT_FIELD_MASK) +#define DVP_BYTE2_ORDER2 (DVP_PORTCFG_BMAP4) +#define DVP_BYTE2_ORDER3 (DVP_PORTCFG_BMAP5) +#define DVP_BYTE2_ORDER4 (DVP_PORTCFG_BMAP4 | DVP_PORTCFG_BMAP5) + +#define DVP_BYTE3_ORDER1 (DVP_REG_BIT_FIELD_MASK) +#define DVP_BYTE3_ORDER2 (DVP_PORTCFG_BMAP6) +#define DVP_BYTE3_ORDER3 (DVP_PORTCFG_BMAP7) +#define DVP_BYTE3_ORDER4 (DVP_PORTCFG_BMAP6 | DVP_PORTCFG_BMAP7) + +/** DVP Frame Line Skip definition **/ +#define DVP_SKIP_LINE1 ((uint32_t)0x00000001U) +#define DVP_SKIP_LINE2 ((uint32_t)0x00000002U) +#define DVP_SKIP_LINE3 ((uint32_t)0x00000003U) +#define DVP_SKIP_LINE4 ((uint32_t)0x00000004U) +#define DVP_SKIP_LINE5 ((uint32_t)0x00000005U) +#define DVP_SKIP_LINE6 ((uint32_t)0x00000006U) +#define DVP_SKIP_LINE7 ((uint32_t)0x00000007U) +#define DVP_SKIP_LINE8 ((uint32_t)0x00000008U) +#define DVP_SKIP_LINE9 ((uint32_t)0x00000009U) +#define DVP_SKIP_LINE10 ((uint32_t)0x0000000AU) +#define DVP_SKIP_LINE11 ((uint32_t)0x0000000BU) +#define DVP_SKIP_LINE12 ((uint32_t)0x0000000CU) +#define DVP_SKIP_LINE13 ((uint32_t)0x0000000DU) +#define DVP_SKIP_LINE14 ((uint32_t)0x0000000EU) +#define DVP_SKIP_LINE15 ((uint32_t)0x0000000FU) + +/** DVP Initial Frame Line Skip definition **/ +#define DVP_ISKIP_MASK (~DVP_PORTCFG_HISKIP) + +/** DVP Repeat Frame Line Skip definition **/ +#define DVP_RSKIP_MASK (~DVP_PORTCFG_HRSKIP) +#define DVP_ODD_LINE ((uint32_t)0x0000000EU) +#define DVP_EVEN_LINE ((uint32_t)0x0000000FU) + +/** DVP Frame Buffer 1 enable control definition **/ +#define DVP_BUFFER1_MASK ((uint32_t)~DVP_FIFOCFG_M1ADDREN) +#define DVP_BUFFER1 ((uint32_t)DVP_FIFOCFG_M1ADDREN) + +/** DVP Frame Buffer 2 enable control definition **/ +#define DVP_BUFFER2_MASK (~DVP_FIFOCFG_M2ADDREN) +#define DVP_BUFFER2 (DVP_FIFOCFG_M2ADDREN) + +/** DVP bursting across 1K boundary control definition **/ +#define DVP_1K_BOUNDARY_MASK (~DVP_FIFOCFG_EN1KBD) +#define DVP_1K_BOUNDARY_ENABLE (DVP_FIFOCFG_EN1KBD) +#define DVP_1K_BOUNDARY_DISABLE (DVP_REG_BIT_FIELD_MASK) + +/** DVP show current frame buffer status definition **/ +#define DVP_DISPLAY_STATUS_MASK (~DVP_FIFOCFG_DISPMODE) +#define DVP_DISPLAY_ADDRESS (DVP_FIFOCFG_DISPMODE) +#define DVP_DISPLAY_NUMBER (DVP_REG_BIT_FIELD_MASK) + +/** DVP transmit threshold definition **/ +#define DVP_FIFO_THRSEHOLD_MASK (~DVP_FIFOCFG_TXFTH) +#define DVP_FIFO_THRSEHOLD_BYTE_8 (DVP_REG_BIT_FIELD_MASK) +#define DVP_FIFO_THRSEHOLD_BYTE_16 (DVP_FIFOCFG_TXFTH0) +#define DVP_FIFO_THRSEHOLD_BYTE_32 (DVP_FIFOCFG_TXFTH1) +#define DVP_FIFO_THRSEHOLD_BYTE_64 (DVP_FIFOCFG_TXFTH0 | DVP_FIFOCFG_TXFTH1) +#define DVP_FIFO_THRSEHOLD_BYTE_128 (DVP_FIFOCFG_TXFTH2) +#define DVP_FIFO_THRSEHOLD_BYTE_256 (DVP_FIFOCFG_TXFTH2 | DVP_FIFOCFG_TXFTH0) +#define DVP_FIFO_THRSEHOLD_BYTE_512 (DVP_FIFOCFG_TXFTH2 | DVP_FIFOCFG_TXFTH1) +#define DVP_FIFO_THRSEHOLD_BYTE_1024 (DVP_FIFOCFG_TXFTH2 | DVP_FIFOCFG_TXFTH1 | DVP_FIFOCFG_TXFTH0) + +/** DVP data burst definition **/ +#define DVP_BURST_SIZE_MASK (~DVP_FIFOCFG_TXBURSZ) +#define DVP_BURST_SIZE_BYTE_8 (DVP_REG_BIT_FIELD_MASK) +#define DVP_BURST_SIZE_BYTE_16 (DVP_FIFOCFG_TXBURSZ0) +#define DVP_BURST_SIZE_BYTE_24 (DVP_FIFOCFG_TXBURSZ1) +#define DVP_BURST_SIZE_BYTE_32 (DVP_FIFOCFG_TXBURSZ0 | DVP_FIFOCFG_TXBURSZ1) +#define DVP_BURST_SIZE_BYTE_40 (DVP_FIFOCFG_TXBURSZ2) +#define DVP_BURST_SIZE_BYTE_48 (DVP_FIFOCFG_TXBURSZ2 | DVP_FIFOCFG_TXBURSZ0) +#define DVP_BURST_SIZE_BYTE_56 (DVP_FIFOCFG_TXBURSZ2 | DVP_FIFOCFG_TXBURSZ1) +#define DVP_BURST_SIZE_BYTE_64 (DVP_FIFOCFG_TXBURSZ) +/*** DVP Private Definition End ***/ + +/*** DVP Driving Functions Declaration ***/ +void DVP_DeInit(DVP_Module *DVPx); +void DVP_Init(DVP_Module *DVPx, DVP_InitType* DVP_InitParam); +void DVP_StructInit(DVP_InitType* DVP_InitParam); +void DVP_ConfigDma(DVP_Module *DVPx, DVP_DMAInitType* DVP_DMAInitParam); +void DVP_DMAStructInit(DVP_DMAInitType* DVP_DMAInitParam); +void DVP_EnablePort(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_EnableCrop(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_ConfigVBlankFilter(DVP_Module *DVPx, uint8_t Filt); +void DVP_ConfigInt(DVP_Module *DVPx, uint32_t DVPInt, FunctionalState Cmd); +FlagStatus DVP_GetFlagStatus(DVP_Module *DVPx, uint32_t DVP_Flag); +void DVP_ClearFlag(DVP_Module *DVPx, uint32_t DVP_Flag); +INTStatus DVP_GetIntStatus(DVP_Module *DVPx, uint32_t DVP_Int); +void DVP_ClrIntPendingBit(DVP_Module *DVPx, uint32_t DVP_Int); +void DVP_ConfigPixelClockPolarity(DVP_Module *DVPx, uint32_t PLCK_POL); +void DVP_ConfigHSyncPolarity(DVP_Module *DVPx, uint32_t HSYNC_POL); +void DVP_ConfigVSyncPolarity(DVP_Module *DVPx, uint32_t VSYNC_POL); +void DVP_EnableDataInvert(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_EnableDataReverse(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_ConfigEmbSyncPos(DVP_Module *DVPx, uint32_t SYNC_Pos); +void DVP_ConfigEmbSyncData(DVP_Module *DVPx, uint8_t FrameStartValue, uint8_t FrameEndValue, uint8_t LineStartValue, uint8_t LineEndValue); +void DVP_ConfigEmbSyncDataMask(DVP_Module *DVPx, uint8_t FrameStartMask, uint8_t FrameEndMask, uint8_t LineStartMask, uint8_t LineEndMask); +void DVP_EnableEmbSyncMode(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_ConfigDataMode(DVP_Module *DVPx, uint32_t Mode); +void DVP_ConfigPixelByte(DVP_Module *DVPx, uint32_t Pixel_Byte); +void DVP_ConfigDATAByteOrder(DVP_Module *DVPx, uint32_t Byte0, uint32_t Byte1, uint32_t Byte2, uint32_t Byte3); +void DVP_ConfigInitSKIP(DVP_Module *DVPx, uint32_t Line); +void DVP_EnableBuffer1(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_SetBuffer1Address(DVP_Module *DVPx, uint32_t Addres); +void DVP_EnableBuffer2(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_SetBuffer2Address(DVP_Module *DVPx, uint32_t Addres); +void DVP_SetBufferSize(DVP_Module *DVPx, uint32_t Size); +void DVP_SetDisplayBufferStatus(DVP_Module *DVPx, uint32_t State_Mode); +uint32_t DVP_GetDisplayBufferStatus1(DVP_Module *DVPx); +uint32_t DVP_GetDisplayBufferStatus2(DVP_Module *DVPx); +void DVP_EnableAcross1KBoundary(DVP_Module *DVPx, FunctionalState Cmd); +void DVP_ConfigCROPStart(DVP_Module *DVPx, uint16_t X,uint16_t Y); +void DVP_ConfigCROPEnd(DVP_Module *DVPx, uint16_t X,uint16_t Y); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76x_78x_DVP_H */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eccmon.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eccmon.h new file mode 100644 index 0000000000..84afa1d35f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eccmon.h @@ -0,0 +1,170 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_eccmon.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_ECCMON_H__ +#define __N32H76x_78x_ECCMON_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32h76x_78x.h" +#include "n32h76x_78x_rcc.h" + + +/** ECCMON Init Structure definition **/ +typedef struct +{ + uint32_t MemType; /*Specifies ECCMON monit memory ,can |(or) operation */ + uint32_t CaptureSelect;/*Specifies ECC error event capture selection*/ + uint32_t ErrFlagOut;/*Specifies which error flag out to FLAG_En_OT port,as system fault events*/ +} ECCMON_InitType; + +typedef struct +{ + ECCMON_TypeDef * MonitorUnit;/*ECCMON1P1,ECCMON1P2.......ECCMON3*/ + uint32_t MonitorIndex;/*min:0,max:5*/ +}ECCMON_MonitorType; +#define ECCMON_GROUP_REG_ADDR_GAP (0x05UL) //5 registers +#define AXI_SRAM1_BASE_ADDR ((uint32_t)0x24000000) +#define AXI_SRAM2_BASE_ADDR ((uint32_t)0x24020000) +#define AXI_SRAM3_BASE_ADDR ((uint32_t)0x240A0000) +#define AHB_SRAM1_BASE_ADDR ((uint32_t)0x30000000) +#define AHB_SRAM2_BASE_ADDR ((uint32_t)0x30020000) +#define AHB_SRAM3_BASE_ADDR ((uint32_t)0x30040000) +#define AHB_SRAM4_BASE_ADDR ((uint32_t)0x30048000) +#define AHB_SRAM5_BANK1_BASE_ADDR ((uint32_t)0x30050000) +#define AHB_SRAM5_BANK2_BASE_ADDR ((uint32_t)0x30054000) +#define ITCM_BASE_ADDR ((uint32_t)0x00000000) +#define DTCM_BASE_ADDR ((uint32_t)0x20000000) +#define BACKUP_SRAM_BASE_ADDR ((uint32_t)0x38000000) +/** ECCMON Memory Type definition **/ +#define ECCMON_NONE_SRAM ((uint32_t)0x0000) +#define ECCMON_AXI_SRAM1 ((uint32_t)0x0001) //corresponding ECCMON1P1,n=1 +#define ECCMON_AXI_SRAM2 ((uint32_t)0x0002) //corresponding ECCMON1P2,n=0 +#define ECCMON_AXI_SRAM3 ((uint32_t)0x0004) //corresponding ECCMON1P2,n=1 +#define ECCMON_ITCM ((uint32_t)0x0008) //corresponding ECCMON1P3,n=0 +#define ECCMON_D0TCM ((uint32_t)0x0010) //corresponding ECCMON1P4,n=0 +#define ECCMON_D1TCM ((uint32_t)0x0020) //corresponding ECCMON1P4,n=1 +#define ECCMON_AHB_SRAM1 ((uint32_t)0x0040) //corresponding ECCMON2,n=0 +#define ECCMON_AHB_SRAM2 ((uint32_t)0x0080) //corresponding ECCMON2,n=1 +#define ECCMON_AHB_SRAM3 ((uint32_t)0x0100) //corresponding ECCMON2,n=2 +#define ECCMON_AHB_SRAM4 ((uint32_t)0x0200) //corresponding ECCMON2,n=3 +#define ECCMON_AHB_SRAM5_BANK1 ((uint32_t)0x0400) //corresponding ECCMON2,n=4 +#define ECCMON_AHB_SRAM5_BANK2 ((uint32_t)0x0800) //corresponding ECCMON2,n=5 +#define ECCMON_BACKUP_SRAM ((uint32_t)0x1000) //corresponding ECCMON3,n=0 +/**ECCMON Error Flag Out Type definiton**/ +#define ECCMON_NO_ERROR_FLAG_OUT ((uint32_t)0x00u) +#define ECCMON_1BIT_ERROR_FLAG_OUT ((uint32_t)0x01u) +#define ECCMON_2BIT_ERROR_FLAG_OUT ((uint32_t)0x02u) +#define ECCMON_1_2BIT_ERROR_FLAG_OUT ((uint32_t)0x03u) +/**ECCMON Capture Selection**/ +#define ECCMON_CAPTURE_1_2BIT_ERROR ((uint32_t)0x00u) +#define ECCMON_CAPTURE_1BIT_ERROR ((uint32_t)ECCMON_EINJ_ECSEL1_0) +#define ECCMON_CAPTURE_2BIT_ERROR ((uint32_t)ECCMON_EINJ_ECSEL1_1) +#define ECCMON_CAPTURE_NONE_ERROR ((uint32_t)ECCMON_EINJ_ECSEL1_0|ECCMON_EINJ_ECSEL1_1) + + +/**ECCMON interrupt Type definiton**/ +#define ECCMON_1BIT_ERROR_INT ((uint32_t)0x01u) +#define ECCMON_2BIT_ERROR_INT ((uint32_t)0x02u) +#define ECCMON_1_2BIT_ERROR_INT ((uint32_t)0x03u) + +/**ECCMON Interrupt definiton**/ +#define ECCMON_FLAG_E1DCIFW (ECCMON_INTF1_E1DCIFW) +#define ECCMON_FLAG_E2DCIFW (ECCMON_INTF1_E2DCIFW) +#define ECCMON_FLAG_E1DCIFR (ECCMON_INTF1_E1DCIFR) +#define ECCMON_FLAG_E2DCIFR (ECCMON_INTF1_E2DCIFR) + +#define ECCMON_INT_E1DCIFW (ECCMON_INTF1_E1DCIFW) +#define ECCMON_INT_E2DCIFW (ECCMON_INTF1_E2DCIFW) +#define ECCMON_INT_E1DCIFR (ECCMON_INTF1_E1DCIFR) +#define ECCMON_INT_E2DCIFR (ECCMON_INTF1_E2DCIFR) +/**ECCMON error context flag define */ +#define ECCMON_ERR_CONTEXT_FLAG_E2EAD (ECCMON_FEADR1_E2EAD) +#define ECCMON_ERR_CONTEXT_FLAG_E1EAD (ECCMON_FEADR1_E1EAD) + +/**ECCMON Inject type**/ +#define ECCMON_NO_INJECT ((uint32_t)0x00u) +#define ECCMON_INJECT_1BIT (ECCMON_EINJ_ERICTR1_0) +#define ECCMON_INJECT_2BIT (ECCMON_EINJ_ERICTR1_0|ECCMON_EINJ_ERICTR1_1) +#define ECCMON_INJECT_MASK (ECCMON_EINJ_ERICTR1_0|ECCMON_EINJ_ERICTR1_1) + +void ECCMON_StructInit(ECCMON_InitType *ECCMON_InitStruct); +void ECCMON_Init(ECCMON_InitType *ECCMON_InitStruct); +void ECCMON_ConfigInt(uint32_t ECCMON_MemType, uint32_t ECCMON_IntType); +void ECCMON_InjectError(uint32_t ECCMON_MemType, uint32_t ECCMON_InjectType); +void ECCMON_SetBypassTempRegister(uint32_t ECCMON_MemType, FunctionalState Cmd); +void ECCMON_SetWriteOn2Bit(uint32_t ECCMON_MemType, FunctionalState Cmd); +void ECCMON_Enable(uint32_t ECCMON_MemType,FunctionalState Cmd); +void ECCMON_EnableClk(void); +uint32_t ECCMON_GetFailAddress(uint32_t ECCMON_MemType); +uint32_t ECCMON_GetFailDataLow(uint32_t ECCMON_MemType); +uint32_t ECCMON_GetFailDataHigh(uint32_t ECCMON_MemType); +uint32_t ECCMON_GetFailErrorCode(uint32_t ECCMON_MemType); +FlagStatus ECCMON_GetErrorContextFlagStatus(uint32_t ECCMON_MemType, uint32_t ECCMON_ERR_CONTEXT_FLAG); +void ECCMON_ClrErrorContextFlag(uint32_t ECCMON_MemType, uint32_t ECCMON_ERR_CONTEXT_FLAG); + +FlagStatus ECCMON_GetFlagStatus(uint32_t ECCMON_MemType, uint32_t ECCMON_FLAG); +void ECCMON_ClrFlag(uint32_t ECCMON_MemType, uint32_t ECCMON_FLAG); +INTStatus ECCMON_GetIntStatus(uint32_t ECCMON_MemType, uint32_t ECCMON_INT); +#ifdef __cplusplus +} +#endif + +#endif /* __n32h76x_78x_CRC_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eth.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eth.h new file mode 100644 index 0000000000..81b840cbe8 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_eth.h @@ -0,0 +1,1490 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_eth.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_ETH_H__ +#define __N32H76X_78X_ETH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include "n32h76x_78x.h" +#include "n32h76x_78x_rcc.h" +#include "n32h76x_78x_gpio.h" + + +#define ETH_TX_DESC_NUMBER ((uint32_t)0x00000004U) /* Tx Descriptor Length: Minimum is 4, maximum is 1024 */ +#define ETH_RX_DESC_NUMBER ((uint32_t)0x00000004U) /* Rx Descriptor Length: Minimum is 4, maximum is 1024 */ + + +/*** ETH Structure Definition Start ***/ + +typedef enum +{ + ETH_MII_MODE = ((uint32_t)0x00000000U), + ETH_RMII_MODE = ((uint32_t)0x00000001U), + ETH_GMII_MODE = ((uint32_t)0x00000002U) +} EthMediaInterfaceType; + +typedef enum +{ + ETH_MDCCLK_NORMAL = ((uint32_t)0x00000000U), /* Frequency range: 1.0MHz ≤ MDC clock ≤ 2.5MHz */ + ETH_MDCCLK_FAST = ((uint32_t)0x00000001U) /* Frequency range: MDC clock > 2.5MHz */ +} EthMdcClkType; + +typedef enum +{ + ETH_SUCCESS = ((uint32_t)0x00000000U), /* No error */ + ETH_ERROR_BUSY = ((uint32_t)0x00000001U), /* Busy error */ + ETH_ERROR_PARAM = ((uint32_t)0x00000002U), /* Parameter error */ + ETH_ERROR_TIMEOUT = ((uint32_t)0x00000004U), /* Timeout error */ + ETH_ERROR_DMA = ((uint32_t)0x00000008U), /* DMA transfer error */ + ETH_ERROR_MAC = ((uint32_t)0x00000010U), /* MAC transfer error */ + ETH_ERROR_RPHY = ((uint32_t)0x00000020U), /* Read PHY register error */ + ETH_ERROR_WPHY = ((uint32_t)0x00000040U), /* Write PHY register error */ + DESC_OWNED_BY_DMA = ((uint32_t)0x00000080U), /* Descriptor is owned by the DMA */ + NO_DESC_TO_BUILD = ((uint32_t)0x00000100U), /* No descriptors to build */ + NO_DATA_TRANSFER = ((uint32_t)0x00000200U), /* No data transfer */ + FATAL_BUS_ERROR = ((uint32_t)0x00000400U), /* Fatal Bus Error */ + ETH_ERROR_MIF = ((uint32_t)0x00000800U) /* Media interface selection error */ +} EthFuncStatusType; + +typedef enum +{ + ETH_MAC_ADDR0_OFFSET = ((uint32_t)0x00000000U), /* MAC Address0 Offset */ + ETH_MAC_ADDR1_OFFSET = ((uint32_t)0x00000008U), /* MAC Address1 Offset */ + ETH_MAC_ADDR2_OFFSET = ((uint32_t)0x00000010U), /* MAC Address2 Offset */ + ETH_MAC_ADDR3_OFFSET = ((uint32_t)0x00000018U) /* MAC Address3 Offset */ +} EthMacAddr0123Type; + +typedef enum +{ + ETH_MACADDR1_OFFSET = ((uint32_t)0x00000008U), /* MAC Address1 Offset */ + ETH_MACADDR2_OFFSET = ((uint32_t)0x00000010U), /* MAC Address2 Offset */ + ETH_MACADDR3_OFFSET = ((uint32_t)0x00000018U) /* MAC Address3 Offset */ +} EthMacAddr123Type; + +typedef enum +{ + ETH_MMC_SCGP_OFFSET = ((uint32_t)0x0000004CU), /* TX Single Collision Good Packets Counter register address Offset */ + ETH_MMC_MCGP_OFFSET = ((uint32_t)0x00000050U), /* TX Multiple Collision Good Packets Counter register address Offset */ + ETH_MMC_PCG_OFFSET = ((uint32_t)0x00000068U), /* TX Good Packets Counter register address Offset */ + ETH_MMC_BPG_OFFSET = ((uint32_t)0x0000008CU), /* RX Good Broadcast Packets Counter register address Offset */ + ETH_MMC_MPG_OFFSET = ((uint32_t)0x00000090U), /* RX Good Multicast Packets Counter register address Offset */ + ETH_MMC_CRCEP_OFFSET = ((uint32_t)0x00000094U), /* RX CRC Error Packets Counter register address Offset */ + ETH_MMC_AEP_OFFSET = ((uint32_t)0x00000098U), /* RX Alignment Error Packets Counter register address Offset */ + ETH_MMC_UPG_OFFSET = ((uint32_t)0x000000C4U) /* RX Good Unicast Packets Counter register address Offset */ +} EthMmcAddrType; + +typedef enum +{ + ETH_MACTS_SSIR_OFFSET = ((uint32_t)0x00000004U), /* Sub Second Increment register address Offset */ + ETH_MACTS_STSR_OFFSET = ((uint32_t)0x00000008U), /* System Time Seconds register address Offset */ + ETH_MACTS_STNSR_OFFSET = ((uint32_t)0x0000000CU), /* System Time Nanoseconds register address Offset */ + ETH_MACTS_STSUR_OFFSET = ((uint32_t)0x00000010U), /* System Time Seconds Update register address Offset */ + ETH_MACTS_STNSUR_OFFSET = ((uint32_t)0x00000014U), /* System Time Nanoseconds Update register address Offset */ + ETH_MACTS_TAR_OFFSET = ((uint32_t)0x00000018U), /* Timestamp Addend register address Offset */ + ETH_MACTS_TTSNSR_OFFSET = ((uint32_t)0x00000030U), /* Tx Timestamp Status Nanoseconds register address Offset */ + ETH_MACTS_TTSSR_OFFSET = ((uint32_t)0x00000034U), /* Tx Timestamp Status Seconds register address Offset */ + ETH_MACTS_TICNSR_OFFSET = ((uint32_t)0x00000058U), /* Timestamp Ingress Correction Nanosecond register address Offset */ + ETH_MACTS_TECNSR_OFFSET = ((uint32_t)0x0000005CU), /* Timestamp Egress Correction Nanosecond register address Offset */ + ETH_MACTS_TILR_OFFSET = ((uint32_t)0x00000068U), /* Timestamp Ingress Latency register address Offset */ + ETH_MACTS_TELR_OFFSET = ((uint32_t)0x0000006CU), /* Timestamp Egress Latency register address Offset */ + ETH_MACTS_PTTSR_OFFSET = ((uint32_t)0x00000080U), /* PPS Target Time Seconds register address Offset */ + ETH_MACTS_PTTNSR_OFFSET = ((uint32_t)0x00000084U) /* PPS Target Time Nanosecond register address Offset */ +} EthTsAddrType; + +typedef enum +{ + ETH_TX_PACKETS_FEATURES_CSUM = ((uint32_t)0x00000001U), /* Checksum Control */ + ETH_TX_PACKETS_FEATURES_SAIC = ((uint32_t)0x00000002U), /* Source Address Insertion Control */ + ETH_TX_PACKETS_FEATURES_VLANTAG = ((uint32_t)0x00000004U), /* VLAN Tag */ + ETH_TX_PACKETS_FEATURES_INNERVLANTAG = ((uint32_t)0x00000008U), /* Inner VLAN Tag */ + ETH_TX_PACKETS_FEATURES_TSO = ((uint32_t)0x00000010U), /* TCP Segementation */ + ETH_TX_PACKETS_FEATURES_CRCPAD = ((uint32_t)0x00000020U), /* CRC Pad Control */ + ETH_TX_PACKETS_FEATURES_OSTC = ((uint32_t)0x00000040U) /* One-Step Timestamp Correction */ +} EthTxPackAttrType; + +typedef enum +{ + ETH_MACADDR_FILTER_SA = ((uint32_t)0x00000000U), + ETH_MACADDR_FILTER_DA = ((uint32_t)0x00000008U) +} EthMacAddrFilterType; + +typedef enum +{ + ETH_PREAMBLE_LEN_7BYTES = ((uint32_t)0x00000000U), + ETH_PREAMBLE_LEN_5BYTES = ((uint32_t)0x00000004U), + ETH_PREAMBLE_LEN_3BYTES = ((uint32_t)0x00000008U) +} EthTxPreLenType; + +typedef enum +{ + ETH_BACK_OFF_LIMIT_10 = ((uint32_t)0x00000000U), + ETH_BACK_OFF_LIMIT_8 = ((uint32_t)0x00000020U), + ETH_BACK_OFF_LIMIT_4 = ((uint32_t)0x00000040U), + ETH_BACK_OFF_LIMIT_1 = ((uint32_t)0x00000060U) +} EthBacOffLimType; + +typedef enum +{ + ETH_HALF_DUPLEX_MODE = ((uint32_t)0x00000000U), + ETH_FULL_DUPLEX_MODE = ((uint32_t)0x00002000U) +} EthDuplexType; + +typedef enum +{ + ETH_SPEED_1000M = ((uint32_t)0x00000000U), + ETH_SPEED_10M = ((uint32_t)0x00008000U), + ETH_SPEED_100M = ((uint32_t)0x0000C000U) +} EthSpeedType; + +typedef enum +{ + ETH_INTER_PACKET_GAP_96BIT = ((uint32_t)0x00000000U), + ETH_INTER_PACKET_GAP_88BIT = ((uint32_t)0x01000000U), + ETH_INTER_PACKET_GAP_80BIT = ((uint32_t)0x02000000U), + ETH_INTER_PACKET_GAP_72BIT = ((uint32_t)0x03000000U), + ETH_INTER_PACKET_GAP_64BIT = ((uint32_t)0x04000000U), + ETH_INTER_PACKET_GAP_56BIT = ((uint32_t)0x05000000U), + ETH_INTER_PACKET_GAP_48BIT = ((uint32_t)0x06000000U), + ETH_INTER_PACKET_GAP_40BIT = ((uint32_t)0x07000000U) +} EthIntPktGapType; + +typedef enum +{ + ETH_SRC_ADDR_CTRL_INTERNAL_SIGNALS = ((uint32_t)0x00000000U), /* The generation of the source address field is controlled by internal signals */ + ETH_SRC_ADDR_CTRL_INSERT_MACAR0 = ((uint32_t)0x20000000U), /* The Source Address field is inserted by the contents of the MAC Address 0 register */ + ETH_SRC_ADDR_CTRL_REPLACE_MACAR0 = ((uint32_t)0x30000000U), /* The Source Address field is replaced by the contents of the MAC Address 0 register */ + ETH_SRC_ADDR_CTRL_INSERT_MACAR1 = ((uint32_t)0x60000000U), /* The Source Address field is inserted by the contents of the MAC Address 1 register */ + ETH_SRC_ADDR_CTRL_REPLACE_MACAR1 = ((uint32_t)0x70000000U), /* The Source Address field is replaced by the contents of the MAC Address 1 register */ +} EthSrcAddrCtrlType; + +typedef enum +{ + ETH_CTRL_PACKETS_FLTR_ALL = ((uint32_t)0x00000000U), /* MAC filters all control packets from reaching the application */ + ETH_CTRL_PACKETS_FW_XCPT_PAU = ((uint32_t)0x00000040U), /* MAC forwards all control packets except Pause packets to the \ + application even if they fail the Address filter */ + ETH_CTRL_PACKETS_FW_ALL = ((uint32_t)0x00000080U), /* MAC forwards all control packets to the application even if \ + they fail the Address filter */ + ETH_CTRL_PACKETS_FW_PASS = ((uint32_t)0x000000C0U) /* MAC forwards the control packets that pass the Address filter */ +} EthCtrlPktType; + +typedef enum +{ + ETH_WDG_TIMEOUT_2KBYTES = ((uint32_t)0x00000000U), + ETH_WDG_TIMEOUT_3KBYTES = ((uint32_t)0x00000001U), + ETH_WDG_TIMEOUT_4KBYTES = ((uint32_t)0x00000002U), + ETH_WDG_TIMEOUT_5KBYTES = ((uint32_t)0x00000003U), + ETH_WDG_TIMEOUT_6KBYTES = ((uint32_t)0x00000004U), + ETH_WDG_TIMEOUT_7KBYTES = ((uint32_t)0x00000005U), + ETH_WDG_TIMEOUT_8KBYTES = ((uint32_t)0x00000006U), + ETH_WDG_TIMEOUT_9KBYTES = ((uint32_t)0x00000007U), + ETH_WDG_TIMEOUT_10KBYTES = ((uint32_t)0x00000008U), + ETH_WDG_TIMEOUT_11KBYTES = ((uint32_t)0x00000009U), + ETH_WDG_TIMEOUT_12KBYTES = ((uint32_t)0x0000000AU), + ETH_WDG_TIMEOUT_13KBYTES = ((uint32_t)0x0000000BU), + ETH_WDG_TIMEOUT_14KBYTES = ((uint32_t)0x0000000CU), + ETH_WDG_TIMEOUT_15KBYTES = ((uint32_t)0x0000000DU), + ETH_WDG_TIMEOUT_16KBYTES = ((uint32_t)0x0000000EU) +} EthWdgTimOutType; + +typedef enum +{ + ETH_PAUSE_LOW_THRESHOLD_PT4 = ((uint32_t)0x00000000U), /* Pause Time minus 4 Slot Times */ + ETH_PAUSE_LOW_THRESHOLD_PT28 = ((uint32_t)0x00000010U), /* Pause Time minus 28 Slot Times */ + ETH_PAUSE_LOW_THRESHOLD_PT36 = ((uint32_t)0x00000020U), /* Pause Time minus 36 Slot Times */ + ETH_PAUSE_LOW_THRESHOLD_PT144 = ((uint32_t)0x00000030U), /* Pause Time minus 144 Slot Times */ + ETH_PAUSE_LOW_THRESHOLD_PT256 = ((uint32_t)0x00000040U), /* Pause Time minus 256 Slot Times */ + ETH_PAUSE_LOW_THRESHOLD_PT512 = ((uint32_t)0x00000050U) /* Pause Time minus 512 Slot Times */ +} EthPauLowThdType; + +typedef enum +{ + ETH_TXQUEUE_OPERATE_THRESHOLD_32 = ((uint32_t)0x00000000U), /* Threshold Mode, level: 32Bytes */ + ETH_TXQUEUE_OPERATE_STOREFORWARD = ((uint32_t)0x00000002U), /* Store and Forward Mode */ + ETH_TXQUEUE_OPERATE_THRESHOLD_64 = ((uint32_t)0x00000010U), /* Threshold Mode, level: 64Bytes */ + ETH_TXQUEUE_OPERATE_THRESHOLD_96 = ((uint32_t)0x00000020U), /* Threshold Mode, level: 96Bytes */ + ETH_TXQUEUE_OPERATE_THRESHOLD_128 = ((uint32_t)0x00000030U), /* Threshold Mode, level: 128Bytes */ + ETH_TXQUEUE_OPERATE_THRESHOLD_192 = ((uint32_t)0x00000040U), /* Threshold Mode, level: 192Bytes */ + ETH_TXQUEUE_OPERATE_THRESHOLD_256 = ((uint32_t)0x00000050U), /* Threshold Mode, level: 256Bytes */ + ETH_TXQUEUE_OPERATE_THRESHOLD_384 = ((uint32_t)0x00000060U), /* Threshold Mode, level: 384Bytes */ + ETH_TXQUEUE_OPERATE_THRESHOLD_512 = ((uint32_t)0x00000070U) /* Threshold Mode, level: 512Bytes */ +} EthTxQOpeType; + +typedef enum +{ + ETH_RXQUEUE_OPERATE_THRESHOLD_64 = ((uint32_t)0x00000000U), /* Threshold Mode, level: 64Bytes */ + ETH_RXQUEUE_OPERATE_THRESHOLD_32 = ((uint32_t)0x00000001U), /* Threshold Mode, level: 32Bytes */ + ETH_RXQUEUE_OPERATE_THRESHOLD_96 = ((uint32_t)0x00000002U), /* Threshold Mode, level: 96Bytes */ + ETH_RXQUEUE_OPERATE_THRESHOLD_128 = ((uint32_t)0x00000003U), /* Threshold Mode, level: 128Bytes */ + ETH_RXQUEUE_OPERATE_STOREFORWARD = ((uint32_t)0x00000020U) /* Store and Forward Mode */ +} EthRxQOpeType; + +typedef enum +{ + ETH_DMA_ARBITRA_WRR_RX1_TX1 = ((uint32_t)0x00000000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 1:1 */ + ETH_DMA_ARBITRA_FP_RX = ((uint32_t)0x00000002U), /* Fixed Priority, Rx path has priority over Tx path */ + ETH_DMA_ARBITRA_WRR_TX1_RX1 = ((uint32_t)0x00000800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 1:1 */ + ETH_DMA_ARBITRA_FP_TX = ((uint32_t)0x00000802U), /* Fixed Priority, Tx path has priority over Rx path */ + ETH_DMA_ARBITRA_WRR_RX2_TX1 = ((uint32_t)0x00001000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 2:1 */ + ETH_DMA_ARBITRA_WRR_TX2_RX1 = ((uint32_t)0x00001800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 2:1 */ + ETH_DMA_ARBITRA_WRR_RX3_TX1 = ((uint32_t)0x00002000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 3:1 */ + ETH_DMA_ARBITRA_WRR_TX3_RX1 = ((uint32_t)0x00002800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 3:1 */ + ETH_DMA_ARBITRA_WRR_RX4_TX1 = ((uint32_t)0x00003000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 4:1 */ + ETH_DMA_ARBITRA_WRR_TX4_RX1 = ((uint32_t)0x00003800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 4:1 */ + ETH_DMA_ARBITRA_WRR_RX5_TX1 = ((uint32_t)0x00004000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 5:1 */ + ETH_DMA_ARBITRA_WRR_TX5_RX1 = ((uint32_t)0x00004800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 5:1 */ + ETH_DMA_ARBITRA_WRR_RX6_TX1 = ((uint32_t)0x00005000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 6:1 */ + ETH_DMA_ARBITRA_WRR_TX6_RX1 = ((uint32_t)0x00005800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 6:1 */ + ETH_DMA_ARBITRA_WRR_RX7_TX1 = ((uint32_t)0x00006000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 7:1 */ + ETH_DMA_ARBITRA_WRR_TX7_RX1 = ((uint32_t)0x00006800U), /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 7:1 */ + ETH_DMA_ARBITRA_WRR_RX8_TX1 = ((uint32_t)0x00007000U), /* Weighted Round-Robin with Rx:Tx, Rx:Tx = 8:1 */ + ETH_DMA_ARBITRA_WRR_TX8_RX1 = ((uint32_t)0x00007800U) /* Weighted Round-Robin with Tx:Rx, Tx:Rx = 8:1 */ +} EthTxRxArbType; + +typedef enum +{ + ETH_BURST_MODE_UNFIXED = ((uint32_t)0x00000000U), /* Unspecified length (INCR) or SINGLE transfers */ + ETH_BURST_MODE_FIXED = ((uint32_t)0x00000001U), /* Specified length (INCRx or SINGLE) */ + ETH_BURST_MODE_MIXED = ((uint32_t)0x00004000U) /* Mixed Burst */ +} EthBurstType; + +typedef enum +{ + ETH_DESC_SKIP_LEN_0BIT = ((uint32_t)0x00000000U), + ETH_DESC_SKIP_LEN_32BIT = ((uint32_t)0x00040000U), + ETH_DESC_SKIP_LEN_64BIT = ((uint32_t)0x00080000U), + ETH_DESC_SKIP_LEN_96BIT = ((uint32_t)0x000C0000U), + ETH_DESC_SKIP_LEN_128BIT = ((uint32_t)0x00100000U), + ETH_DESC_SKIP_LEN_160BIT = ((uint32_t)0x00140000U), + ETH_DESC_SKIP_LEN_192BIT = ((uint32_t)0x00180000U), + ETH_DESC_SKIP_LEN_224BIT = ((uint32_t)0x001C0000U) +} EthDesSkiLenType; + +typedef enum +{ + ETH_TX_PROGRAM_BURST_LEN_1 = ((uint32_t)0x00010000U), + ETH_TX_PROGRAM_BURST_LEN_2 = ((uint32_t)0x00020000U), + ETH_TX_PROGRAM_BURST_LEN_4 = ((uint32_t)0x00040000U), + ETH_TX_PROGRAM_BURST_LEN_8 = ((uint32_t)0x00080000U), + ETH_TX_PROGRAM_BURST_LEN_16 = ((uint32_t)0x00100000U), + ETH_TX_PROGRAM_BURST_LEN_32 = ((uint32_t)0x00200000U) +} EthTxBurLenType; + +typedef enum +{ + ETH_RX_PROGRAM_BURST_LEN_1 = ((uint32_t)0x00010000U), + ETH_RX_PROGRAM_BURST_LEN_2 = ((uint32_t)0x00020000U), + ETH_RX_PROGRAM_BURST_LEN_4 = ((uint32_t)0x00040000U), + ETH_RX_PROGRAM_BURST_LEN_8 = ((uint32_t)0x00080000U), + ETH_RX_PROGRAM_BURST_LEN_16 = ((uint32_t)0x00100000U), + ETH_RX_PROGRAM_BURST_LEN_32 = ((uint32_t)0x00200000U) +} EthRxBurLenType; + +typedef enum +{ + ETH_VLANTAGRXSTRIPPING_NONE = ((uint32_t)0x00000000U), + ETH_VLANTAGRXSTRIPPING_IFPASS = ((uint32_t)0x00200000U), + ETH_VLANTAGRXSTRIPPING_IFFAILS = ((uint32_t)0x00400000U), + ETH_VLANTAGRXSTRIPPING_ALWAYS = ((uint32_t)0x00600000U) +} EthRxVlanStripType; + +typedef enum +{ + ETH_VLANTYPECHECK_CVLAN = ((uint32_t)0x00000000U), + ETH_VLANTYPECHECK_SVLAN = ((uint32_t)0x000C0000U), + ETH_VLANTYPECHECK_DISABLE = ((uint32_t)0x00100000U) +} EthVlanCheckType; + + + + +/** ETH initialize configuration structure definition **/ +typedef struct +{ + /******************* MAC Basic Configuration *******************/ + EthTxPreLenType TxPreambleLen; /* Configs the Preamble Length for Transmit packets */ + + uint32_t DeferralCheck; /* Enables or Disable Deferral check function in the half-duplex mode */ + + EthBacOffLimType BackOffLimit; /* Selects the Back-Off limit value in the half-duplex mode */ + + uint32_t DisTxRetry; /* Enables or Disable MAC retry transmission, when a collision occurs in Half Duplex mode */ + + uint32_t DisCSDuringTransmit; /* Enables or Disable Carrier Sense During Transmission in the half-duplex mode */ + + uint32_t DisRxOwn; /* Enables or Disable Receive Own in Half Duplex mode */ + + uint32_t CSBeforeTransmit; /* Enables or Disable Carrier Sense Before Transmission in the full-duplex mode */ + + uint32_t Loopback; /* Enables or Disable Loopback Mode */ + + EthDuplexType Duplex; /* Selects the Half-duplex or Full-duplex mode */ + + EthSpeedType SpeedSelect; /* Selects the speed mode: 10Mbps or 100Mbps or 1000Mbps, note ETH2 only 10Mbps or 100Mbps */ + + uint32_t JumboPacket; /* Enables or Disable Jumbo Packet */ + + uint32_t DisTxJabber; /* Enables or Disable Jabber timer on Tx path */ + + uint32_t PacketBurst; /* Enables or Disable Packet Burst in GMII half-duplex mode, ETH2 is not supported */ + + uint32_t DisRxWatchdog; /* Enables or Disable Watchdog timer on Rx path */ + + uint32_t AutoPadCRCStrip; /* Enables or Disable Automatic Pad or CRC Stripping function */ + + uint32_t CRCStripTypePacket; /* Enables or Disable CRC stripping for Type packets function */ + + uint32_t Support2KPacket; /* Enables or Disable IEEE 802.3as Support for 2K Packets function */ + + uint32_t GiantPacketSizeLimitCtrl; /* Enables or Disable Giant Packet Size Limit Control */ + + EthIntPktGapType InterPacketGapVal; /* Configs the minimum Inter-Packet Gap between packets during transmission */ + + uint32_t ChecksumOffload; /* Enables or Disable Checksum Offload function */ + + EthSrcAddrCtrlType SrcAddrCtrl; /* Selects the Source Address Insertion or Replacement Control */ + + uint32_t ARPOffload; /* Enables or Disable ARP Offload function */ + + /****************** MAC Extended Configuration ******************/ + uint32_t GiantPacketSizeLimit; /* Configs Giant Packet Size Limit value, If the received packet size is greater than the \ + value programmed in this field in units of bytes, the MAC declares the received packet \ + as Giant packet. This value must be ≥ 1518 bytes */ + + uint32_t DisRxPacketCRCCheck; /* Enables or Disable CRC Checking for Rx Packets */ + + uint32_t SPDetect; /* Enables or Disable Slow Protocol Detection */ + + uint32_t USPPacketDetect; /* Enables or Disable Unicast Slow Protocol Packet Detect */ + + uint32_t ExtInterPacketGap; /* Enables or Disable Extended Inter-Packet Gap */ + + uint32_t ExtInterPacketGapVal; /* Configs the minimum Inter-Packet Gap between packets during transmission */ + + uint32_t DropARPPacket; /* Enables or Disable ARP Packet Drop function if IP Address Mismatch */ + + /**************** MAC Packet Filter Configuration ***************/ + uint32_t Promiscuous; /* Enables or Disable Promiscuous Mode */ + + uint32_t HashUnicast; /* Enables or Disable Hash Unicast Filtering Mode */ + + uint32_t HashMulticast; /* Enables or Disable Hash Multicast Filtering Mode */ + + uint32_t DAInverseFiltering; /* Enables or Disable DA Inverse Filtering Mode */ + + uint32_t PassAllMulticast; /* Enables or Disable Pass All Multicast Mode */ + + uint32_t DisBroadcastPackets; /* Enables or Disable Broadcast Packets */ + + EthCtrlPktType PassControlPackets; /* Configs the forwarding of all control packets */ + + uint32_t SAInverseFiltering; /* Enables or Disable SA Inverse Filtering Mode */ + + uint32_t SAFilter; /* Enables or Disable SA Filter */ + + uint32_t HashOrPerfectFilter; /* Enables or Disable Hash or Perfect Filter */ + + uint32_t VLANTagFilter; /* Enables or Disable VLAN Tag Filter */ + + uint32_t Layer3Layer4Filter; /* Enables or Disable Layer 3 and Layer 4 Filter */ + + uint32_t DropNonTcpUdpPackets; /* Enables or Disable Drop Non-TCP/UDP over IP Packets */ + + uint32_t ReceiveAll; /* Enables or Disable Receive All mode */ + + /************** MAC Watchdog Timeout Configuration **************/ + EthWdgTimOutType WatchdogTimeout; /* Configs watchdog timeout for a received packet, if the length of a received packet \ + exceeds the value of this field, such packet is terminated and declared as an error \ + packet */ + + uint32_t ProgramWatchdog; /* Enables or Disable Programmable Watchdog function */ + + /**************** MAC Flow Control Configuration ****************/ + uint32_t TxFlowControl; /* Enables or Disable Transmit Flow Control function */ + + EthPauLowThdType PauseLowThreshold; /* Configs the threshold of the Pause timer */ + + uint32_t DisZeroQuantaPause; /* Enables or Disable Zero-Quanta Pause function */ + + uint32_t PauseTime; /* Configs the value to be used in the Pause Time field in the Tx control packet */ + + uint32_t RxFlowControl; /* Enables or Disable Receive Flow Control function */ + + uint32_t UPPacketDetect; /* Enables or Disable Unicast Pause Packet Detect */ + + /*********** MAC Transaction Layer (MTL) Configuration **********/ + EthTxQOpeType TxQueueOperateMode; /* Config Tx Store and Forward Mode or Threshold Mode and threshold level */ + + EthRxQOpeType RxQueueOperateMode; /* Configs Rx Store and Forward Mode or Threshold Mode and threshold level */ + + uint32_t ForwardUSGoodPacket; /* Enables or Disable Forward Undersized Good Packets function */ + + uint32_t ForwardErrorPacket; /* Enables or Disable Forward Error Packets function */ + + uint32_t DisDropTCPIPCSErrorPacket; /* Enables or Disable Dropping of TCP/IP Checksum Error Packets */ + + /****************** DMA Bus Mode Configuration ******************/ + EthTxRxArbType TxRxArbitration; /* Configs the arbitration scheme between the Tx and Rx paths of DMA */ + + uint32_t DescriptorCache; /* Enables or Disable Descriptor Cache function */ + + /*************** DMA System Bus Mode Configuration **************/ + EthBurstType BurstMode; /* Configs the AHB Master interface burst transfers */ + + uint32_t AddrAlignedBeats; /* Enables or Disable AHB Master interface address-aligned burst transfers on Read \ + and Write channels */ + + uint32_t RebuildINCRxBurst; /* Enables or Disable AHB Master to rebuild the pending beats of any initiated burst \ + transfer with INCRx and SINGLE transfers */ + + /******************* DMA Channel Configuration ******************/ + uint32_t MaxSegmentSize; /* Configs the maximum segment size that should be used while segmenting the packet \ + This parameter can be a value from 0x40 to 0x3FFF */ + + uint32_t PBLx8mode; /* Enables or Disable PBL multiplication by eight */ + + EthDesSkiLenType DescriptorSkipLen; /* Configs the Word number to skip between two unchained descriptors */ + + /************** DMA Channel Transmit Configuration **************/ + uint32_t OperateSecondPacket; /* Enables or Disable Operate on Second Packet mode, it instructs the DMA to process \ + the second packet of the Transmit data even before the status for the first packet \ + is obtained */ + + uint32_t TCPSegment; /* Enables or Disable TCP Segmentation function */ + + EthTxBurLenType TxBurstLength; /* Configs the maximum number of beats to be transferred in one DMA block data transfer */ + + uint32_t EarlyTxInterruptCtrl; /* Enables or Disable Early Transmit Interrupt function */ + + /*************** DMA Channel Receive Configuration ***************/ + EthRxBurLenType RxBurstLength; /* Configs the maximum number of beats to be transferred in one DMA block data transfer */ + + uint32_t EarlyRxInterruptCtrl; /* Enables or Disable Early Receive Interrupt function */ + + uint32_t RxPacketFlush; /* Enables or Disable Rx Packet Flush function */ + +} ETH_InitType; + +/** ETH Rx VLAN tag initialize configuration structure definition **/ +typedef struct +{ + uint32_t VLANTagHashTableMatch; /* Enables or Disables VLAN Tag Hash Table Match */ + + uint32_t VLANTagInStatus; /* Enables or Disables VLAN Tag in Rx status */ + + EthRxVlanStripType StripVLANTag; /* Sets the VLAN Tag Stripping on Receive */ + + EthVlanCheckType VLANTypeCheck; /* Enables or Disables VLAN Type Check */ + + uint32_t VLANTagInverceMatch; /* Enables or disables VLAN Tag Inverse Match */ + + uint32_t VLANTagComparison12Bit; /* Enables or disables 12-Bit VLAN Tag Comparison */ + +} ETH_RxVLANTagInitType; + +/** ETH DMA Descriptor structure definition **/ +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + __IO uint32_t Buf1Addr; /* Used to backup rx buffer 1 address */ + __IO uint32_t Buf2Addr; /* Used to backup rx buffer 2 address */ +} ETH_DMADescType; + +/** ETH DMA Tx Descriptor List structure definition **/ +typedef struct +{ + uint32_t TxDesc[ETH_TX_DESC_NUMBER]; /* Tx DMA descriptors addresses */ + + uint32_t CurTxDesc; /* Current Tx descriptor index for packet transmission */ +} ETH_TxDescListType; + +/** ETH DMA Rx Descriptor List structure definition **/ +typedef struct +{ + uint32_t RxDesc[ETH_RX_DESC_NUMBER]; /* Rx DMA descriptors addresses */ + + uint32_t CurRxDesc; /* Current Rx descriptor, ready for next reception */ + + uint32_t FirstAppDesc; /* First descriptor of last received packet */ + + uint32_t AppDescNbr; /* Number of descriptors of last received packet */ + + uint32_t AppContextDesc; /* If 1 a context descriptor is present in last received packet + If 0 no context descriptor is present in last received packet */ + + uint32_t ItMode; /* If 1, DMA will generate the Rx complete interrupt + If 0, DMA will not generate the Rx complete interrupt */ +} ETH_RxDescListType; + +/** ETH Buffers List structure definition **/ +typedef struct __ETH_BufferType +{ + uint8_t* pBuf; /* buffer address */ + + uint32_t Len; /* buffer length */ + + struct __ETH_BufferType* pNext; /* Pointer to the next buffer in the list */ +} ETH_BufferType; + +/** ETH Transmit Packet structure definition **/ +typedef struct +{ + uint32_t Attributes; /* Tx packet HW features capabilities + This parameter can be a combination of EthTxPackAttrType */ + + ETH_BufferType* pTxBuffer; /* Tx buffers pointers */ + + uint32_t Length; /* Total packet length */ + + uint32_t SAInsertCtrl; /* Source address insertion control */ + + uint32_t CRCPadCtrl; /* Specifies the CRC and Pad insertion and replacement control */ + + uint32_t ChecksumCtrl; /* Specifies the checksum insertion control */ + + uint32_t VlanTag; /* Sets VLAN Tag only when VLAN is enabled */ +} ETH_TxPacketType; + +/** ETH Received Packet structure definition **/ +typedef struct +{ + uint32_t DescriptorCnt; /* Number of Rx Descriptors */ + + uint32_t VlanTag; /* Vlan Tag value */ + + uint32_t Checksum; /* Rx Checksum status */ + + uint32_t HeaderType; /* IP header type */ + + uint32_t PayloadType; /* Payload type */ + + uint32_t MACFilterStatus; /* MAC filter status */ + + uint32_t ErrorCode; /* Rx error code */ +} ETH_RxPacketType; + +/** Function prototype for phy get link status functions. +*\*\param addr PHY port address +*\*\param reg PHY register address +*\*\return Acquired PHY link state value containing speed core duplex mode +**/ +typedef uint16_t (*phyGetLinkStatus_fn)(uint16_t addr, uint16_t reg); + +/** ETH External PHY information definition **/ +typedef struct +{ + uint16_t phyAddr; /* PHY address, value 0~31 */ + + uint16_t bcRegAddr; /* PHY Basic Control Register */ + + uint16_t bsRegAddr; /* PHY Basic Status Register */ + + uint16_t sdRegAddr; /* Address of the status register indicating speed and duplex mode in auto-negotiation mode */ + + uint16_t phyReset; /* PHY Reset */ + + // uint16_t phyLoopback; /* Select PHY's loop-back mode */ + + uint16_t phyMode; /* Set PHY's duplex and speed mode */ + + uint16_t phyAutoNeg; /* Enable PHY's auto-negotiation function */ + + uint16_t phyAutoNegOK; /* Auto-negotiation completed */ + + uint16_t phyLinkOK; /* Valid link established */ + + uint16_t phyDuplexMask; /* PHY Duplex mask */ + + uint16_t phySpeedMask; /* PHY Speed mask */ + + phyGetLinkStatus_fn phyGetLinkStatus; +} ETH_PHYInfoType; + +/** ETH module information definition **/ +typedef struct +{ + EthMediaInterfaceType MediaInterface; /* Selects the interface where the MAC is connected to the PHY */ + + FunctionalStatus AutoNegCmd; /* Enables or Disables the AutoNegotiation mode for the external PHY */ + + FunctionalStatus PPSOutCmd; /* Enables or Disables the PPS out operations */ + + FunctionalStatus PMTCmd; /* Enables or Disables the PMT (MAC Magic Packet/Remote Wake-Up Packet) */ + + FunctionalStatus LPICmd; /* Enables or Disables the LPI (Low-power interface, EEE mode) */ + + EthMdcClkType MDCClockMode; /* Selects the MDC clock range from 1.0M to 2.5M or greater than 2.5M */ + + uint32_t CSRClkDiv; /* Provides the CSR clock division factor used to calculate the MDC clock. + Available only when the MDC clock range is greater than 2.5M */ + + uint8_t* pMACAddr; /* MAC Address of used Hardware: must be pointer on an array of 6 bytes */ + + ETH_DMADescType* pTxDesc; /* Provides the address of the first DMA Tx descriptor in the list */ + + ETH_DMADescType* pRxDesc; /* Provides the address of the first DMA Rx descriptor in the list */ + + uint32_t RxBuffLen; /* Provides the length of Rx buffers size */ + + ETH_TxDescListType TxDescList; /* Holds all Tx descriptors list addresses and current descriptor index */ + + ETH_RxDescListType RxDescList; /* Holds all Rx descriptors list addresses and current descriptor index */ + + ETH_PHYInfoType PHYInfo; /* Provides information related to PHY initialization and some status information */ + +} ETH_InfoType; + + +/*** ETH Structure Definition End ***/ + + +/*** ETH Macro Definition Start ***/ + +/** ETH register bit field mask definition **/ +#define ETH_REG_BIT_FIELD_MASK ((uint32_t)0x00000000U) + +/** ETH Link speed duplex definition **/ +#define ETH_LINK_10FULL ((uint32_t)0x00000001U) +#define ETH_LINK_10HALF ((uint32_t)0x00000002U) +#define ETH_LINK_100FULL ((uint32_t)0x00000004U) +#define ETH_LINK_100HALF ((uint32_t)0x00000008U) +#define ETH_LINK_1000FULL ((uint32_t)0x00000010U) +#define ETH_LINK_1000HALF ((uint32_t)0x00000020U) + +/** ETH MAC Interrupt flag definition **/ +#define ETH_MAC_INT_FLAG_PHY ((uint32_t)(ETH_MACINTSTS_PHYIS)) +#define ETH_MAC_INT_FLAG_PMT ((uint32_t)(ETH_MACINTSTS_PMTIS)) +#define ETH_MAC_INT_FLAG_MMCRX ((uint32_t)(ETH_MACINTSTS_MMCIS \ + | ETH_MACINTSTS_MMCRXIS)) +#define ETH_MAC_INT_FLAG_MMCTX ((uint32_t)(ETH_MACINTSTS_MMCIS \ + | ETH_MACINTSTS_MMCTXIS)) +#define ETH_MAC_INT_FLAG_TS ((uint32_t)(ETH_MACINTSTS_TSIS)) +#define ETH_MAC_INT_FLAG_TX ((uint32_t)(ETH_MACINTSTS_TXSTSIS)) +#define ETH_MAC_INT_FLAG_RX ((uint32_t)(ETH_MACINTSTS_RXSTSIS)) +#define ETH_MAC_INT_FLAG_MDIO ((uint32_t)(ETH_MACINTSTS_MDIOIS)) + +/** ETH MAC Interrupt definition **/ +#define ETH_MAC_INT_PHY ((uint32_t)ETH_MACINTEN_PHYIE) +#define ETH_MAC_INT_PMT ((uint32_t)ETH_MACINTEN_PMTIE) +#define ETH_MAC_INT_TS ((uint32_t)ETH_MACINTEN_TSIE) +#define ETH_MAC_INT_TX ((uint32_t)ETH_MACINTEN_TXSTSIE) +#define ETH_MAC_INT_RX ((uint32_t)ETH_MACINTEN_RXSTSIE) +#define ETH_MAC_INT_MDIO ((uint32_t)ETH_MACINTEN_MDIOIE) + +/** ETH MAC TX-RX flag definition **/ +#define ETH_MACTX_FLAG_TJT ((uint32_t)ETH_MACRXTXSTS_TJT) +#define ETH_MACTX_FLAG_NCARR ((uint32_t)ETH_MACRXTXSTS_NCARR) +#define ETH_MACTX_FLAG_LCARR ((uint32_t)ETH_MACRXTXSTS_LCARR) +#define ETH_MACTX_FLAG_EXDEF ((uint32_t)ETH_MACRXTXSTS_EXDEF) +#define ETH_MACTX_FLAG_LCOL ((uint32_t)ETH_MACRXTXSTS_LCOL) +#define ETH_MACTX_FLAG_EXCOL ((uint32_t)ETH_MACRXTXSTS_EXCOL) +#define ETH_MACRX_FLAG_RWT ((uint32_t)ETH_MACRXTXSTS_RWT) + +/** ETH PMT flag definition **/ +#define ETH_PMT_FLAG_WUPFRPR ((uint32_t)ETH_MACPMTCTRLSTS_RWKFILTRST) /* Remote Wake-Up Packet Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUPR ((uint32_t)ETH_MACPMTCTRLSTS_RWKPRCVD) /* Remote Wake-Up Packet Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)ETH_MACPMTCTRLSTS_MGKPRCVD) /* Magic Packet Received */ + +/** ETH MDC clock frequency definition **/ +#define ETH_MACMDIOADDR_CR_MASK ((uint32_t)(ETH_MACMDIOADDR_CR)) +#define ETH_MDCNCLK_CRSCLK_DIV42 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + & ETH_MACMDIOADDR_CR_1 \ + & ETH_MACMDIOADDR_CR_2 \ + & ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCNCLK_CRSCLK_DIV62 ((uint32_t)(ETH_MACMDIOADDR_CR_0)) +#define ETH_MDCNCLK_CRSCLK_DIV16 ((uint32_t)(ETH_MACMDIOADDR_CR_1)) +#define ETH_MDCNCLK_CRSCLK_DIV26 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_1)) +#define ETH_MDCNCLK_CRSCLK_DIV102 ((uint32_t)(ETH_MACMDIOADDR_CR_2)) +#define ETH_MDCNCLK_CRSCLK_DIV124 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_2)) +#define ETH_MDCNCLK_CRSCLK_DIV204 ((uint32_t)(ETH_MACMDIOADDR_CR_1 \ + | ETH_MACMDIOADDR_CR_2)) +#define ETH_MDCNCLK_CRSCLK_DIV324 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_1 \ + | ETH_MACMDIOADDR_CR_2)) + +#define ETH_MDCFCLK_CRSCLK_DIV4 ((uint32_t)(ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV6 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV8 ((uint32_t)(ETH_MACMDIOADDR_CR_1 \ + | ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV10 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_1 \ + | ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV12 ((uint32_t)(ETH_MACMDIOADDR_CR_2 \ + | ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV14 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_2 \ + | ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV16 ((uint32_t)(ETH_MACMDIOADDR_CR_1 \ + | ETH_MACMDIOADDR_CR_2 \ + | ETH_MACMDIOADDR_CR_3)) +#define ETH_MDCFCLK_CRSCLK_DIV18 ((uint32_t)(ETH_MACMDIOADDR_CR_0 \ + | ETH_MACMDIOADDR_CR_1 \ + | ETH_MACMDIOADDR_CR_2 \ + | ETH_MACMDIOADDR_CR_3)) + +/** ETH MAC Address Filter Mask Bytes definition **/ +#define ETH_MACADDR_MASK_MBC ((uint32_t)ETH_MACADDR1H_MBC) +#define ETH_MACADDR_MASK_BYTE1 ((uint32_t)ETH_MACADDR1H_MBC_0) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACADDR_MASK_BYTE2 ((uint32_t)ETH_MACADDR1H_MBC_1) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACADDR_MASK_BYTE3 ((uint32_t)ETH_MACADDR1H_MBC_2) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACADDR_MASK_BYTE4 ((uint32_t)ETH_MACADDR1H_MBC_3) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACADDR_MASK_BYTE5 ((uint32_t)ETH_MACADDR1H_MBC_4) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACADDR_MASK_BYTE6 ((uint32_t)ETH_MACADDR1H_MBC_5) /* Mask MAC Address high reg bits [15:8] */ + +/** ETH MAC Timestamp update method definition **/ +#define ETH_MACTS_FINE_UPDATE ((uint32_t)ETH_MACTSCTRL_TSCFUPDT) /* Fine Update method */ +#define ETH_MACTS_COARSE_UPDATE ((uint32_t)ETH_REG_BIT_FIELD_MASK) /* Coarse Update method */ + +/** ETH MAC PTP Packet Type definition **/ +#define ETH_MACPTP_TYPE_VERSION2 ((uint32_t)ETH_MACTSCTRL_TSVER2ENA) +#define ETH_MACPTP_TYPE_ETHERNET ((uint32_t)ETH_MACTSCTRL_TSIPENA) +#define ETH_MACPTP_TYPE_IPV6UDP ((uint32_t)ETH_MACTSCTRL_TSIPV6ENA) +#define ETH_MACPTP_TYPE_IPV4UDP ((uint32_t)ETH_MACTSCTRL_TSIPV4ENA) + +/** ETH MAC TimeStamp update calculation mode definition **/ +#define ETH_MACTS_CALMODE_SUB ((uint32_t)ETH_MACSYSTNSUP_ADDSUB) /* Subtract Time */ +#define ETH_MACTS_CALMODE_ADD ((uint32_t)ETH_REG_BIT_FIELD_MASK) /* Add Time */ + +/** ETH MAC PPS Frequency Control definition **/ +#define ETH_MACPPS_FREQCTRL_B2D1 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0)) /* Binary rollover is 2 Hz, Digital rollover is 1 Hz */ +#define ETH_MACPPS_FREQCTRL_B4D2 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_1)) /* Binary rollover is 4 Hz, Digital rollover is 2 Hz */ +#define ETH_MACPPS_FREQCTRL_B8D4 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_1)) /* Binary rollover is 8 Hz, Digital rollover is 4 Hz */ +#define ETH_MACPPS_FREQCTRL_B16D8 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_2)) /* Binary rollover is 16 Hz, Digital rollover is 8 Hz */ +#define ETH_MACPPS_FREQCTRL_B32D16 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_2)) /* Binary rollover is 32 Hz, Digital rollover is 16 Hz */ +#define ETH_MACPPS_FREQCTRL_B64D32 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_1 \ + | ETH_MACPPSCTRL_PPSCTRL_2)) /* Binary rollover is 64 Hz, Digital rollover is 32 Hz */ +#define ETH_MACPPS_FREQCTRL_B128D64 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_1 \ + | ETH_MACPPSCTRL_PPSCTRL_2)) /* Binary rollover is 128 Hz, Digital rollover is 64 Hz */ +#define ETH_MACPPS_FREQCTRL_B256D128 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 256 Hz, Digital rollover is 128 Hz */ +#define ETH_MACPPS_FREQCTRL_B512D256 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 512 Hz, Digital rollover is 256 Hz */ +#define ETH_MACPPS_FREQCTRL_B1024D512 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_1 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 1024 Hz, Digital rollover is 512 Hz */ +#define ETH_MACPPS_FREQCTRL_B2048D1024 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_1 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 2048 Hz, Digital rollover is 1024 Hz */ +#define ETH_MACPPS_FREQCTRL_B4096D2048 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_2 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 4096 Hz, Digital rollover is 2048 Hz */ +#define ETH_MACPPS_FREQCTRL_B8192D4096 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_2 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 8192 Hz, Digital rollover is 4096 Hz */ +#define ETH_MACPPS_FREQCTRL_B16384D8192 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_1 \ + | ETH_MACPPSCTRL_PPSCTRL_2 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 16384 Hz, Digital rollover is 8192 Hz */ +#define ETH_MACPPS_FREQCTRL_B32768D16384 ((uint32_t)(ETH_MACPPSCTRL_PPSCTRL_0 \ + | ETH_MACPPSCTRL_PPSCTRL_1 \ + | ETH_MACPPSCTRL_PPSCTRL_2 \ + | ETH_MACPPSCTRL_PPSCTRL_3)) /* Binary rollover is 32768 Hz, Digital rollover is 16384 Hz */ + + +/** ETH MMC RX Interrupt flag definition **/ +#define ETH_MMCRX_INT_FLAG_BCGPIS ((uint32_t)ETH_MMCRXINT_RXBCGPIS) +#define ETH_MMCRX_INT_FLAG_MCGPIS ((uint32_t)ETH_MMCRXINT_RXMCGPIS) +#define ETH_MMCRX_INT_FLAG_CRCERPIS ((uint32_t)ETH_MMCRXINT_RXCRCERPIS) +#define ETH_MMCRX_INT_FLAG_ALGNERPIS ((uint32_t)ETH_MMCRXINT_RXALGNERPIS) +#define ETH_MMCRX_INT_FLAG_UCGPIS ((uint32_t)ETH_MMCRXINT_RXUCGPIS) + +/** ETH MMC TX Interrupt flag definition **/ +#define ETH_MMCTX_INT_FLAG_SCOLGPIS ((uint32_t)ETH_MMCTXINT_TXSCOLGPIS) +#define ETH_MMCTX_INT_FLAG_MCOLGPIS ((uint32_t)ETH_MMCTXINT_TXMCOLGPIS) +#define ETH_MMCTX_INT_FLAG_GPKTIS ((uint32_t)ETH_MMCTXINT_TXGPKTIS) + +/** ETH MMC RX Interrupt definition **/ +#define ETH_MMCRX_INT_BCGPIM ((uint32_t)ETH_MMCRXINTMSK_RXBCGPIM) +#define ETH_MMCRX_INT_MCGPIM ((uint32_t)ETH_MMCRXINTMSK_RXMCGPIM) +#define ETH_MMCRX_INT_CRCERPIM ((uint32_t)ETH_MMCRXINTMSK_RXCRCERPIM) +#define ETH_MMCRX_INT_ALGNERPIM ((uint32_t)ETH_MMCRXINTMSK_RXALGNERPIM) +#define ETH_MMCRX_INT_UCGPIM ((uint32_t)ETH_MMCRXINTMSK_RXUCGPIM) + +/** ETH MMC TX Interrupt definition **/ +#define ETH_MMCTX_INT_SCOLGPIM ((uint32_t)ETH_MMCTXINTMSK_TXSCOLGPIM) +#define ETH_MMCTX_INT_MCOLGPIM ((uint32_t)ETH_MMCTXINTMSK_TXMCOLGPIM) +#define ETH_MMCTX_INT_GPKTIM ((uint32_t)ETH_MMCTXINTMSK_TXGPKTIM) + +/** ETH MAC TimeStamp flag definition **/ +#define ETH_MACTS_FLAG_SOVF ((uint32_t)ETH_MACTSSTS_TSSOVF) /* Seconds Overflow flag */ +#define ETH_MACTS_FLAG_TARGT0 ((uint32_t)ETH_MACTSSTS_TSTARGT0) /* Target Time Reached flag */ +#define ETH_MACTS_FLAG_TRGTERR0 ((uint32_t)ETH_MACTSSTS_TSTRGTERR0) /* Target Time Error flag */ +#define ETH_MACTS_FLAG_TXTSSIS ((uint32_t)ETH_MACTSSTS_TXTSSIS) /* Tx Timestamp Status Interrupt Status flag */ + + + +/** ETH MTL Interrupt flag definition **/ +#define ETH_MTL_INT_FLAG_Q0IS ((uint32_t)ETH_MTLINTSTS_Q0IS) + +/** ETH MTL Queue Interrupt definition **/ +#define ETH_MTLTXQUEUE_INT_UIE ((uint32_t)ETH_MTLQINTCTRLSTS_TXUIE) /* Transmit Queue Underflow Interrupt */ +#define ETH_MTLRXQUEUE_INT_OIE ((uint32_t)ETH_MTLQINTCTRLSTS_RXOIE) /* Receive Queue Overflow Interrupt */ + +/** ETH MTL Queue Interrupt flag definition **/ +#define ETH_MTLTXQUEUE_INT_FLAG_UNFIS ((uint32_t)ETH_MTLQINTCTRLSTS_TXUNFIS) /* Transmit Queue Underflow Interrupt Flag */ +#define ETH_MTLRXQUEUE_INT_FLAG_OVFIS ((uint32_t)ETH_MTLQINTCTRLSTS_RXOVFIS) /* Receive Queue Overflow Interrupt Flag */ + +/** ETH MTL Counter flag definition **/ +#define ETH_MTLCOUNTER_FLAG_UFCNTOVF ((uint32_t)ETH_MTLTXQUDF_UFCNTOVF) /* Underflow Packet Counter Overflow Flag */ +#define ETH_MTLCOUNTER_FLAG_OVFCNTOVF ((uint32_t)ETH_MTLRXQMPOFCNT_OVFCNTOVF) /* Overflow Packet Counter Overflow Flag */ +#define ETH_MTLCOUNTER_FLAG_MISCNTOVF ((uint32_t)ETH_MTLRXQMPOFCNT_MISCNTOVF) /* Missed Packet Counter Overflow Flag */ + +/** ETH MTL Queue Status definition **/ +#define ETH_TRCSTS_MASK ((uint32_t)(ETH_MTLTXQDBG_TRCSTS)) +#define ETH_MTLTXQSTS_IDLE ((uint32_t)(ETH_MTLTXQDBG_TRCSTS_0 \ + & ETH_MTLTXQDBG_TRCSTS_1)) +#define ETH_MTLTXQSTS_READ ((uint32_t)(ETH_MTLTXQDBG_TRCSTS_0)) +#define ETH_MTLTXQSTS_WAIT ((uint32_t)(ETH_MTLTXQDBG_TRCSTS_1)) +#define ETH_MTLTXQSTS_FLUSH ((uint32_t)(ETH_MTLTXQDBG_TRCSTS_0 \ + | ETH_MTLTXQDBG_TRCSTS_1)) +#define ETH_MTLTXQSTS_NOT_EMPTY ((uint32_t)(ETH_MTLTXQDBG_TXQSTS)) + +#define ETH_RRCSTS_MASK ((uint32_t)(ETH_MTLRXQDBG_RRCSTS)) +#define ETH_MTLRXQSTS_IDLE ((uint32_t)(ETH_MTLRXQDBG_RRCSTS_0 \ + & ETH_MTLRXQDBG_RRCSTS_1)) +#define ETH_MTLRXQSTS_READ_DATA ((uint32_t)(ETH_MTLRXQDBG_RRCSTS_0)) /* Reading packet data */ +#define ETH_MTLRXQSTS_READ_STS ((uint32_t)(ETH_MTLRXQDBG_RRCSTS_1)) /* Reading packet status (or timestamp) */ +#define ETH_MTLRXQSTS_FLUSH ((uint32_t)(ETH_MTLRXQDBG_RRCSTS_0 \ + | ETH_MTLRXQDBG_RRCSTS_1)) /* Flushing the packet data and status */ + +#define ETH_RXQSTS_MASK ((uint32_t)(ETH_MTLRXQDBG_RXQSTS)) +#define ETH_MTLRXQSTS_EMPTY ((uint32_t)(ETH_MTLRXQDBG_RXQSTS_0 \ + & ETH_MTLRXQDBG_RXQSTS_1)) /* Rx Queue empty */ +#define ETH_MTLRXQSTS_BLW_THR ((uint32_t)(ETH_MTLRXQDBG_RXQSTS_0)) /* Rx Queue fill-level below flow-control deactivate threshold */ +#define ETH_MTLRXQSTS_ABV_THR ((uint32_t)(ETH_MTLRXQDBG_RXQSTS_1)) /* Rx Queue fill-level above flow-control activate threshold */ +#define ETH_MTLRXQSTS_FULL ((uint32_t)(ETH_MTLRXQDBG_RXQSTS_0 \ + | ETH_MTLRXQDBG_RXQSTS_1)) /* Rx Queue full */ + +#define ETH_MTLRXQSTS_PACK_NBR ((uint32_t)(ETH_MTLRXQDBG_PRXQ)) + +/** ETH DMA Interrupt flag definition **/ +#define ETH_DMA_INT_FLAG_DMACH0 ((uint32_t)ETH_DMAINTSTS_DC0IS) +#define ETH_DMA_INT_FLAG_MTL ((uint32_t)ETH_DMAINTSTS_MTLIS) +#define ETH_DMA_INT_FLAG_MAC ((uint32_t)ETH_DMAINTSTS_MACIS) + +/** ETH DMA channel 0 transmit process flag definition **/ +#define ETH_DMACH0_TXPRO_FLAG_STOP ((uint32_t)(ETH_DMADBGSTS_TPS0_0 \ + & ETH_DMADBGSTS_TPS0_1 \ + & ETH_DMADBGSTS_TPS0_2 \ + & ETH_DMADBGSTS_TPS0_3)) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMACH0_TXPRO_FLAG_RUN_FTTD ((uint32_t)(ETH_DMADBGSTS_TPS0_0)) /* Running (Fetching Tx Transfer Descriptor) */ +#define ETH_DMACH0_TXPRO_FLAG_RUN_WS ((uint32_t)(ETH_DMADBGSTS_TPS0_1)) /* Running (Waiting for status) */ +#define ETH_DMACH0_TXPRO_FLAG_RUN_RDS ((uint32_t)(ETH_DMADBGSTS_TPS0_0 \ + | ETH_DMADBGSTS_TPS0_1)) /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */ +#define ETH_DMACH0_TXPRO_FLAG_TSTMP_WS ((uint32_t)(ETH_DMADBGSTS_TPS0_2)) /* Timestamp write status */ +#define ETH_DMACH0_TXPRO_FLAG_SUSPND ((uint32_t)(ETH_DMADBGSTS_TPS0_1 \ + | ETH_DMADBGSTS_TPS0_2)) /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */ +#define ETH_DMACH0_TXPRO_FLAG_RUN_CTD ((uint32_t)(ETH_DMADBGSTS_TPS0_0 \ + | ETH_DMADBGSTS_TPS0_1 \ + | ETH_DMADBGSTS_TPS0_2)) /* Running (Closing Tx Descriptor) */ + +/** ETH DMA channel 0 receive process flag definition **/ +#define ETH_DMACH0_RXPRO_FLAG_STOP ((uint32_t)(ETH_DMADBGSTS_RPS0_0 \ + & ETH_DMADBGSTS_RPS0_1 \ + & ETH_DMADBGSTS_RPS0_2 \ + & ETH_DMADBGSTS_RPS0_3)) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMACH0_RXPRO_FLAG_RUN_FTTD ((uint32_t)(ETH_DMADBGSTS_RPS0_0)) /* Running (Fetching Rx Transfer Descriptor) */ +#define ETH_DMACH0_RXPRO_FLAG_RUN_WRP ((uint32_t)(ETH_DMADBGSTS_RPS0_0 \ + | ETH_DMADBGSTS_RPS0_1)) /* Running (Waiting for Rx packet) */ +#define ETH_DMACH0_RXPRO_FLAG_SUSPND ((uint32_t)(ETH_DMADBGSTS_RPS0_2)) /* Suspended (Rx Descriptor Unavailable) */ +#define ETH_DMACH0_RXPRO_FLAG_RUN_CRD ((uint32_t)(ETH_DMADBGSTS_RPS0_0 \ + | ETH_DMADBGSTS_RPS0_2)) /* Running (Closing the Rx Descriptor) */ +#define ETH_DMACH0_RXPRO_FLAG_TSTMP ((uint32_t)(ETH_DMADBGSTS_RPS0_1 \ + | ETH_DMADBGSTS_RPS0_2)) /* Timestamp write status */ +#define ETH_DMACH0_RXPRO_FLAG_RUN_TRP ((uint32_t)(ETH_DMADBGSTS_RPS0_0 \ + | ETH_DMADBGSTS_RPS0_1 \ + | ETH_DMADBGSTS_RPS0_2)) /* Running (Transferring the received packet data from the Rx buffer to the system memory) */ + +/** ETH DMA channel 0 Interrupt definition **/ +#define ETH_DMACH0_INT_TI ((uint32_t)ETH_DMACH0INTEN_TIE) +#define ETH_DMACH0_INT_TPS ((uint32_t)ETH_DMACH0INTEN_TXSE) +#define ETH_DMACH0_INT_TBU ((uint32_t)ETH_DMACH0INTEN_TBUE) +#define ETH_DMACH0_INT_RI ((uint32_t)ETH_DMACH0INTEN_RIE) +#define ETH_DMACH0_INT_RBU ((uint32_t)ETH_DMACH0INTEN_RBUE) +#define ETH_DMACH0_INT_RPS ((uint32_t)ETH_DMACH0INTEN_RSE) +#define ETH_DMACH0_INT_RWT ((uint32_t)ETH_DMACH0INTEN_RWTE) +#define ETH_DMACH0_INT_ETI ((uint32_t)ETH_DMACH0INTEN_ETIE) +#define ETH_DMACH0_INT_ERI ((uint32_t)ETH_DMACH0INTEN_ERIE) +#define ETH_DMACH0_INT_FBE ((uint32_t)ETH_DMACH0INTEN_FBEE) +#define ETH_DMACH0_INT_CDE ((uint32_t)ETH_DMACH0INTEN_CDEE) +#define ETH_DMACH0_INT_AIS ((uint32_t)ETH_DMACH0INTEN_AIE) +#define ETH_DMACH0_INT_NIS ((uint32_t)ETH_DMACH0INTEN_NIE) + +/** ETH DMA channel 0 flag definition **/ +#define ETH_DMACH0_FLAG_TI ((uint32_t)ETH_DMACH0STS_TI) +#define ETH_DMACH0_FLAG_TPS ((uint32_t)ETH_DMACH0STS_TPS) +#define ETH_DMACH0_FLAG_TBU ((uint32_t)ETH_DMACH0STS_TBU) +#define ETH_DMACH0_FLAG_RI ((uint32_t)ETH_DMACH0STS_RI) +#define ETH_DMACH0_FLAG_RBU ((uint32_t)ETH_DMACH0STS_RBU) +#define ETH_DMACH0_FLAG_RPS ((uint32_t)ETH_DMACH0STS_RPS) +#define ETH_DMACH0_FLAG_RWT ((uint32_t)ETH_DMACH0STS_RWT) +#define ETH_DMACH0_FLAG_ETI ((uint32_t)ETH_DMACH0STS_ETI) +#define ETH_DMACH0_FLAG_ERI ((uint32_t)ETH_DMACH0STS_ERI) +#define ETH_DMACH0_FLAG_FBE ((uint32_t)ETH_DMACH0STS_FBE) +#define ETH_DMACH0_FLAG_CDE ((uint32_t)ETH_DMACH0STS_CDE) +#define ETH_DMACH0_FLAG_AIS ((uint32_t)ETH_DMACH0STS_AIS) +#define ETH_DMACH0_FLAG_NIS ((uint32_t)ETH_DMACH0STS_NIS) + +/** ETH DMA channel 0 Interrupt flag definition **/ +#define ETH_DMACH0_INT_FLAG_TI ((uint32_t)ETH_DMACH0STS_TI) +#define ETH_DMACH0_INT_FLAG_TPS ((uint32_t)ETH_DMACH0STS_TPS) +#define ETH_DMACH0_INT_FLAG_TBU ((uint32_t)ETH_DMACH0STS_TBU) +#define ETH_DMACH0_INT_FLAG_RI ((uint32_t)ETH_DMACH0STS_RI) +#define ETH_DMACH0_INT_FLAG_RBU ((uint32_t)ETH_DMACH0STS_RBU) +#define ETH_DMACH0_INT_FLAG_RPS ((uint32_t)ETH_DMACH0STS_RPS) +#define ETH_DMACH0_INT_FLAG_RWT ((uint32_t)ETH_DMACH0STS_RWT) +#define ETH_DMACH0_INT_FLAG_ETI ((uint32_t)ETH_DMACH0STS_ETI) +#define ETH_DMACH0_INT_FLAG_ERI ((uint32_t)ETH_DMACH0STS_ERI) +#define ETH_DMACH0_INT_FLAG_FBE ((uint32_t)ETH_DMACH0STS_FBE) +#define ETH_DMACH0_INT_FLAG_CDE ((uint32_t)ETH_DMACH0STS_CDE) +#define ETH_DMACH0_INT_FLAG_AIS ((uint32_t)ETH_DMACH0STS_AIS) +#define ETH_DMACH0_INT_FLAG_NIS ((uint32_t)ETH_DMACH0STS_NIS) + +/** ETH DMA Receive Interrupt Watchdog Timer Count Unit definition **/ +#define ETH_DMARXINT_WDGTIM_CNTUNIT_256 ((uint32_t)(ETH_DMACH0RXINTWT_RWTU_0 \ + & ETH_DMACH0RXINTWT_RWTU_1)) +#define ETH_DMARXINT_WDGTIM_CNTUNIT_512 ((uint32_t)(ETH_DMACH0RXINTWT_RWTU_0)) +#define ETH_DMARXINT_WDGTIM_CNTUNIT_1024 ((uint32_t)(ETH_DMACH0RXINTWT_RWTU_1)) +#define ETH_DMARXINT_WDGTIM_CNTUNIT_2048 ((uint32_t)(ETH_DMACH0RXINTWT_RWTU_0 \ + | ETH_DMACH0RXINTWT_RWTU_1)) + + + +/*** ETH Macro Definition End ***/ + + +/*** ETH DMA Transmit Normal Descriptor (Read Format) Start ***/ + +/** Bit definition for ETH_DMATXND0RF register (TDES0) **/ +#define ETH_DMATXND0RF_BUF1AP ((uint32_t)0xFFFFFFFF) /* Buffer 1 Address Pointer */ +#define ETH_DMATXND0RF_TSOHAP ((uint32_t)0xFFFFFFFF) /* TSO Header Address Pointer */ + +/** Bit definition for ETH_DMATXND1RF register (TDES1) **/ +#define ETH_DMATXND1RF_BUF2AP ((uint32_t)0xFFFFFFFF) /* Buffer 2 Address Pointer */ + +/** Bit definition for ETH_DMATXND2RF register (TDES2) **/ +#define ETH_DMATXND2RF_B1L ((uint32_t)0x00003FFF) /* Buffer 1 Length */ +#define ETH_DMATXND2RF_HL ((uint32_t)0x00003FFF) /* Header length when TCP segmentation is enabled */ +#define ETH_DMATXND2RF_VTIR ((uint32_t)0x0000C000) /* VTIR[1:0]: VLAN Tag Insertion or Replacement */ +#define ETH_DMATXND2RF_VTIR_0 ((uint32_t)0x00004000) /* VTIR bit 0 */ +#define ETH_DMATXND2RF_VTIR_1 ((uint32_t)0x00008000) /* VTIR bit 1 */ +#define ETH_DMATXND2RF_B2L ((uint32_t)0x3FFF0000) /* Buffer 2 Length */ +#define ETH_DMATXND2RF_TTSE ((uint32_t)0x40000000) /* Transmit Timestamp Enable */ +#define ETH_DMATXND2RF_IOC ((uint32_t)0x80000000) /* Interrupt on Completion */ + +/** Bit definition for ETH_DMATXND3RF register (TDES3) **/ +#define ETH_DMATXND3RF_FL ((uint32_t)0x00007FFF) /* Frame Length */ +#define ETH_DMATXND3RF_TPL ((uint32_t)0x0003FFFF) /* TCP Payload Length */ +#define ETH_DMATXND3RF_CIC ((uint32_t)0x00030000) /* CIC[1:0]: Checksum Insertion Control */ +#define ETH_DMATXND3RF_CIC_0 ((uint32_t)0x00010000) /* CIC bit 0 */ +#define ETH_DMATXND3RF_CIC_1 ((uint32_t)0x00020000) /* CIC bit 1 */ +#define ETH_DMATXND3RF_TSE ((uint32_t)0x00040000) /* TCP Segmentation Enable */ +#define ETH_DMATXND3RF_THL ((uint32_t)0x00780000) /* TCP/UDP Header Length */ +#define ETH_DMATXND3RF_SAIC ((uint32_t)0x00380000) /* SAIC[2:0]: SA Insertion Control */ +#define ETH_DMATXND3RF_SAIC_0 ((uint32_t)0x00080000) /* SAIC bit 0 */ +#define ETH_DMATXND3RF_SAIC_1 ((uint32_t)0x00100000) /* SAIC bit 1 */ +#define ETH_DMATXND3RF_SAIC_2 ((uint32_t)0x00200000) /* SAIC bit 2 */ +#define ETH_DMATXND3RF_CPC ((uint32_t)0x0C000000) /* CPC[1:0]: CRC Pad Control */ +#define ETH_DMATXND3RF_CPC_0 ((uint32_t)0x04000000) /* CPC bit 0 */ +#define ETH_DMATXND3RF_CPC_1 ((uint32_t)0x08000000) /* CPC bit 1 */ +#define ETH_DMATXND3RF_LD ((uint32_t)0x10000000) /* Last Descriptor */ +#define ETH_DMATXND3RF_FD ((uint32_t)0x20000000) /* First Descriptor */ +#define ETH_DMATXND3RF_CTXT ((uint32_t)0x40000000) /* Context Type */ +#define ETH_DMATXND3RF_OWN ((uint32_t)0x80000000) /* Own Bit */ + +#define ETH_CHECKSUM_INSERT_DISABIE ((uint32_t)(ETH_DMATXND3RF_CIC_0 \ + & ETH_DMATXND3RF_CIC_1)) +#define ETH_CHECKSUM_INSERT_ONLY_IPHDR ((uint32_t)(ETH_DMATXND3RF_CIC_0)) +#define ETH_CHECKSUM_INSERT_IPHDR_PAYLOAD ((uint32_t)(ETH_DMATXND3RF_CIC_1)) +#define ETH_CHECKSUM_INSERT_IPHDR_PAYLOAD_PHDR_CALC ((uint32_t)(ETH_DMATXND3RF_CIC_0 \ + | ETH_DMATXND3RF_CIC_1)) + +#define ETH_CRC_PAD_INSERT ((uint32_t)(ETH_DMATXND3RF_CPC_0 \ + & ETH_DMATXND3RF_CPC_1)) +#define ETH_CRC_INSERT ((uint32_t)(ETH_DMATXND3RF_CPC_0)) +#define ETH_CRC_INSERT_DISABIE ((uint32_t)(ETH_DMATXND3RF_CPC_1)) +#define ETH_CRC_REPLACEMENT ((uint32_t)(ETH_DMATXND3RF_CPC_0 \ + | ETH_DMATXND3RF_CPC_1)) + +/*** ETH DMA Transmit Normal Descriptor (Read Format) End ***/ + + +/*** ETH DMA Transmit Normal Descriptor (Write-Back Format) Start ***/ + +/** Bit definition for ETH_DMATXND0WBF register (TDES0) **/ +#define ETH_DMATXND0WBF_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Packet Timestamp Low */ + +/** Bit definition for ETH_DMATXND1WBF register (TDES1) **/ +#define ETH_DMATXND1WBF_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Packet Timestamp High */ + +/** Bit definition for ETH_DMATXND3WBF register (TDES3) **/ +#define ETH_DMATXND3WBF_IHE ((uint32_t)0x00000001) /* IP Header Error */ +#define ETH_DMATXND3WBF_DB ((uint32_t)0x00000002) /* Deferred Bit */ +#define ETH_DMATXND3WBF_UF ((uint32_t)0x00000004) /* Underflow Error */ +#define ETH_DMATXND3WBF_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATXND3WBF_CC ((uint32_t)0x000000F0) /* Collision Count */ +#define ETH_DMATXND3WBF_EC ((uint32_t)0x00000100) /* Excessive Collision */ +#define ETH_DMATXND3WBF_LC ((uint32_t)0x00000200) /* Late Collision */ +#define ETH_DMATXND3WBF_NC ((uint32_t)0x00000400) /* No Carrier */ +#define ETH_DMATXND3WBF_LOC ((uint32_t)0x00000800) /* Loss of Carrier */ +#define ETH_DMATXND3WBF_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATXND3WBF_PF ((uint32_t)0x00002000) /* Packet Flushed */ +#define ETH_DMATXND3WBF_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATXND3WBF_ES ((uint32_t)0x00008000) /* Error Summary */ +#define ETH_DMATXND3WBF_EUE ((uint32_t)0x00010000) /* ECC Uncorrectable Error Status in TSO memory */ +#define ETH_DMATXND3WBF_TTSS ((uint32_t)0x00020000) /* Tx Timestamp Status */ +#define ETH_DMATXND3WBF_DE ((uint32_t)0x00800000) /* Descriptor Error */ +#define ETH_DMATXND3WBF_LD ((uint32_t)0x10000000) /* Last Descriptor */ +#define ETH_DMATXND3WBF_FD ((uint32_t)0x20000000) /* First Descriptor */ +#define ETH_DMATXND3WBF_CTXT ((uint32_t)0x40000000) /* Context Type */ +#define ETH_DMATXND3WBF_OWN ((uint32_t)0x80000000) /* Own Bit */ + +/** ETH DMA Tx Descriptor flag definition **/ +#define ETH_DMATXDESC_FLAG_IHE ((uint32_t)ETH_DMATXND3WBF_IHE) +#define ETH_DMATXDESC_FLAG_DB ((uint32_t)ETH_DMATXND3WBF_DB) +#define ETH_DMATXDESC_FLAG_UF ((uint32_t)ETH_DMATXND3WBF_UF) +#define ETH_DMATXDESC_FLAG_ED ((uint32_t)ETH_DMATXND3WBF_ED) +#define ETH_DMATXDESC_FLAG_CC ((uint32_t)ETH_DMATXND3WBF_CC) +#define ETH_DMATXDESC_FLAG_EC ((uint32_t)ETH_DMATXND3WBF_EC) +#define ETH_DMATXDESC_FLAG_LC ((uint32_t)ETH_DMATXND3WBF_LC) +#define ETH_DMATXDESC_FLAG_NC ((uint32_t)ETH_DMATXND3WBF_NC) +#define ETH_DMATXDESC_FLAG_LOC ((uint32_t)ETH_DMATXND3WBF_LOC) +#define ETH_DMATXDESC_FLAG_PCE ((uint32_t)ETH_DMATXND3WBF_PCE) +#define ETH_DMATXDESC_FLAG_PF ((uint32_t)ETH_DMATXND3WBF_PF) +#define ETH_DMATXDESC_FLAG_JT ((uint32_t)ETH_DMATXND3WBF_JT) +#define ETH_DMATXDESC_FLAG_ES ((uint32_t)ETH_DMATXND3WBF_ES) +#define ETH_DMATXDESC_FLAG_TTSS ((uint32_t)ETH_DMATXND3WBF_TTSS) +#define ETH_DMATXDESC_FLAG_DE ((uint32_t)ETH_DMATXND3WBF_DE) +#define ETH_DMATXDESC_FLAG_LD ((uint32_t)ETH_DMATXND3WBF_LD) +#define ETH_DMATXDESC_FLAG_FD ((uint32_t)ETH_DMATXND3WBF_FD) + +/*** ETH DMA Transmit Normal Descriptor (Write-Back Format) End ***/ + + +/*** ETH DMA Transmit Context Descriptor Start ***/ + +/** Bit definition for ETH_DMATXCD0 register (TDES0) **/ +#define ETH_DMATXCD0_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Packet Timestamp Low */ + +/** Bit definition for ETH_DMATXCD1 register (TDES1) **/ +#define ETH_DMATXCD1_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Packet Timestamp High */ + +/** Bit definition for ETH_DMATXCD2 register (TDES2) **/ +#define ETH_DMATXCD2_MSS ((uint32_t)0x00003FFF) /* Maximum Segment Size */ +#define ETH_DMATXCD2_IVT ((uint32_t)0xFFFF0000) /* Inner VLAN Tag */ + +/** Bit definition for ETH_DMATXCD3 register (TDES3) **/ +#define ETH_DMATXCD3_VT ((uint32_t)0x0000FFFF) /* VLAN Tag */ +#define ETH_DMATXCD3_VLTV ((uint32_t)0x00010000) /* VLAN Tag Valid */ +#define ETH_DMATXCD3_IVLTV ((uint32_t)0x00020000) /* VLAN Tag Valid */ +#define ETH_DMATXCD3_IVTIR ((uint32_t)0x000C0000) /* IVTIR[1:0]: Inner VLAN Tag Insert or Replace */ +#define ETH_DMATXCD3_IVTIR_0 ((uint32_t)0x00040000) /* IVTIR bit 0 */ +#define ETH_DMATXCD3_IVTIR_1 ((uint32_t)0x00080000) /* IVTIR bit 1 */ +#define ETH_DMATXCD3_CDE ((uint32_t)0x00800000) /* Context Descriptor Error */ +#define ETH_DMATXCD3_TCMSSV ((uint32_t)0x04000000) /* One-Step Timestamp Correction Input */ +#define ETH_DMATXCD3_OSTC ((uint32_t)0x08000000) /* One-Step Timestamp Correction Enable */ +#define ETH_DMATXCD3_CTXT ((uint32_t)0x40000000) /* Context Type */ +#define ETH_DMATXCD3_OWN ((uint32_t)0x80000000) /* Own Bit */ + + +/*** ETH DMA Transmit Context Descriptor End ***/ + + +/*** ETH DMA Receive Normal Descriptor (Read Format) Start ***/ + +/** Bit definition for ETH_DMARXND0RF register (RDES0) **/ +#define ETH_DMARXND0RF_BUF1AP ((uint32_t)0xFFFFFFFF) /* Buffer 1 Address Pointer */ + +/** Bit definition for ETH_DMARXND2RF register (RDES2) **/ +#define ETH_DMARXND2RF_BUF2AP ((uint32_t)0xFFFFFFFF) /* Buffer 2 Address Pointer */ + +/** Bit definition for ETH_DMARXND3RF register (RDES3) **/ +#define ETH_DMARXND3RF_BUF1V ((uint32_t)0x01000000) /* Buffer 1 Address Valid */ +#define ETH_DMARXND3RF_BUF2V ((uint32_t)0x02000000) /* Buffer 2 Address Valid */ +#define ETH_DMARXND3RF_IOC ((uint32_t)0x40000000) /* Interrupt Enabled on Completion */ +#define ETH_DMARXND3RF_OWN ((uint32_t)0x80000000) /* Own Bit */ + +/*** ETH DMA Receive Normal Descriptor (Read Format) End ***/ + + +/*** ETH DMA Receive Normal Descriptor (Write-Back Format) Start ***/ + +/** Bit definition for ETH_DMARXND0WBF register (RDES0) **/ +#define ETH_DMARXND0WBF_OVT ((uint32_t)0x0000FFFF) /* Outer VLAN Tag */ +#define ETH_DMARXND0WBF_IVT ((uint32_t)0xFFFF0000) /* Inner VLAN Tag */ + +/** Bit definition for ETH_DMARXND1WBF register (RDES1) **/ +#define ETH_DMARXND1WBF_PT ((uint32_t)0x00000007) /* PT[2:0]: Payload Type */ +#define ETH_DMARXND1WBF_PT_0 ((uint32_t)0x00000001) /* PT bit 0 */ +#define ETH_DMARXND1WBF_PT_1 ((uint32_t)0x00000002) /* PT bit 1 */ +#define ETH_DMARXND1WBF_PT_2 ((uint32_t)0x00000004) /* PT bit 2 */ +#define ETH_DMARXND1WBF_IPHE ((uint32_t)0x00000008) /* IP Header Error */ +#define ETH_DMARXND1WBF_IPV4 ((uint32_t)0x00000010) /* IPV4 Header Present */ +#define ETH_DMARXND1WBF_IPV6 ((uint32_t)0x00000020) /* IPV6 Header Present */ +#define ETH_DMARXND1WBF_IPCB ((uint32_t)0x00000040) /* IP Checksum Bypassed */ +#define ETH_DMARXND1WBF_IPCE ((uint32_t)0x00000080) /* IP Payload Error */ +#define ETH_DMARXND1WBF_PMT ((uint32_t)0x00000F00) /* PMT[3:0]: PTP Message Type */ +#define ETH_DMARXND1WBF_PMT_0 ((uint32_t)0x00000100) /* PMT bit 0 */ +#define ETH_DMARXND1WBF_PMT_1 ((uint32_t)0x00000200) /* PMT bit 1 */ +#define ETH_DMARXND1WBF_PMT_2 ((uint32_t)0x00000400) /* PMT bit 2 */ +#define ETH_DMARXND1WBF_PMT_3 ((uint32_t)0x00000800) /* PMT bit 3 */ +#define ETH_DMARXND1WBF_PFT ((uint32_t)0x00001000) /* PTP Packet Type */ +#define ETH_DMARXND1WBF_PV ((uint32_t)0x00002000) /* PTP Version */ +#define ETH_DMARXND1WBF_TSA ((uint32_t)0x00004000) /* Timestamp Available */ +#define ETH_DMARXND1WBF_TD ((uint32_t)0x00008000) /* Timestamp Dropped */ +#define ETH_DMARXND1WBF_OPC ((uint32_t)0xFFFF0000) /* OAM Sub-Type Code, or MAC Control Packet opcode */ + +/** ETH DMA Rx Descriptor Extended flag definition **/ +#define ETH_DMARXDESC_EXTFLAG_PT_NONE ((uint32_t)(ETH_DMARXND1WBF_PT_0 \ + & ETH_DMARXND1WBF_PT_1 \ + & ETH_DMARXND1WBF_PT_2)) /* Payload Type: Unknown */ +#define ETH_DMARXDESC_EXTFLAG_PT_NUDP ((uint32_t)(ETH_DMARXND1WBF_PT_0)) /* Payload Type: UDP */ +#define ETH_DMARXDESC_EXTFLAG_PT_TCP ((uint32_t)(ETH_DMARXND1WBF_PT_1)) /* Payload Type: TCP */ +#define ETH_DMARXDESC_EXTFLAG_PT_ICNP ((uint32_t)(ETH_DMARXND1WBF_PT_0 \ + | ETH_DMARXND1WBF_PT_1)) /* Payload Type: ICMP */ +#define ETH_DMARXDESC_EXTFLAG_IPHE ((uint32_t)(ETH_DMARXND1WBF_IPHE)) +#define ETH_DMARXDESC_EXTFLAG_IPV4 ((uint32_t)(ETH_DMARXND1WBF_IPV4)) +#define ETH_DMARXDESC_EXTFLAG_IPV6 ((uint32_t)(ETH_DMARXND1WBF_IPV6)) +#define ETH_DMARXDESC_EXTFLAG_IPCB ((uint32_t)(ETH_DMARXND1WBF_IPCB)) +#define ETH_DMARXDESC_EXTFLAG_IPCE ((uint32_t)(ETH_DMARXND1WBF_IPCE)) +#define ETH_DMARXDESC_EXTFLAG_PMT_NONE ((uint32_t)(ETH_DMARXND1WBF_PMT_0 \ + & ETH_DMARXND1WBF_PMT_1 \ + & ETH_DMARXND1WBF_PMT_2 \ + & ETH_DMARXND1WBF_PMT_3)) /* No PTP message received */ +#define ETH_DMARXDESC_EXTFLAG_PMT_SYNC ((uint32_t)(ETH_DMARXND1WBF_PMT_0)) /* PTP Message Type: SYNC */ +#define ETH_DMARXDESC_EXTFLAG_PMT_FU ((uint32_t)(ETH_DMARXND1WBF_PMT_1)) /* PTP Message Type: Follow_Up */ +#define ETH_DMARXDESC_EXTFLAG_PMT_DREQ ((uint32_t)(ETH_DMARXND1WBF_PMT_0 \ + | ETH_DMARXND1WBF_PMT_1)) /* PTP Message Type: Delay_Req */ +#define ETH_DMARXDESC_EXTFLAG_PMT_DRESP ((uint32_t)(ETH_DMARXND1WBF_PMT_2)) /* PTP Message Type: Delay_Resp */ +#define ETH_DMARXDESC_EXTFLAG_PMT_PDREQ ((uint32_t)(ETH_DMARXND1WBF_PMT_0 \ + | ETH_DMARXND1WBF_PMT_2)) /* PTP Message Type: Pdelay_Req */ +#define ETH_DMARXDESC_EXTFLAG_PMT_PDRESP ((uint32_t)(ETH_DMARXND1WBF_PMT_1 \ + | ETH_DMARXND1WBF_PMT_2)) /* PTP Message Type: Pdelay_Resp */ +#define ETH_DMARXDESC_EXTFLAG_PMT_PRFU ((uint32_t)(ETH_DMARXND1WBF_PMT_0 \ + | ETH_DMARXND1WBF_PMT_1 \ + | ETH_DMARXND1WBF_PMT_2)) /* PTP Message Type: Pdelay_Resp_Follow_Up */ +#define ETH_DMARXDESC_EXTFLAG_PMT_ANN ((uint32_t)(ETH_DMARXND1WBF_PMT_3)) /* PTP Message Type: Announce */ +#define ETH_DMARXDESC_EXTFLAG_PMT_MAN ((uint32_t)(ETH_DMARXND1WBF_PMT_0 \ + | ETH_DMARXND1WBF_PMT_3)) /* PTP Message Type: Management */ +#define ETH_DMARXDESC_EXTFLAG_PMT_SIG ((uint32_t)(ETH_DMARXND1WBF_PMT_1 \ + | ETH_DMARXND1WBF_PMT_3)) /* PTP Message Type: Signaling */ +#define ETH_DMARXDESC_EXTFLAG_PMT_PRT ((uint32_t)(ETH_DMARXND1WBF_PMT_0 \ + | ETH_DMARXND1WBF_PMT_1 \ + | ETH_DMARXND1WBF_PMT_2 \ + | ETH_DMARXND1WBF_PMT_3)) /* PTP packet with Reserved message Type */ +#define ETH_DMARXDESC_EXTFLAG_PFT ((uint32_t)(ETH_DMARXND1WBF_PFT)) +#define ETH_DMARXDESC_EXTFLAG_PV ((uint32_t)(ETH_DMARXND1WBF_PV)) +#define ETH_DMARXDESC_EXTFLAG_TSA ((uint32_t)(ETH_DMARXND1WBF_TSA)) +#define ETH_DMARXDESC_EXTFLAG_TD ((uint32_t)(ETH_DMARXND1WBF_TD)) + + +/** Bit definition for ETH_DMARXND2WBF register (RDES2) **/ +#define ETH_DMARXND2WBF_ARPNR ((uint32_t)0x00000400) /* ARP Reply Not Generated */ +#define ETH_DMARXND2WBF_VFS ((uint32_t)0x00008000) /* VLAN Filter Status */ +#define ETH_DMARXND2WBF_SAF ((uint32_t)0x00010000) /* SA Address Filter Fail */ +#define ETH_DMARXND2WBF_DAF ((uint32_t)0x00020000) /* DA Address Filter Fail */ +#define ETH_DMARXND2WBF_HF ((uint32_t)0x00040000) /* Hash Filter Status */ +#define ETH_DMARXND2WBF_MADRM ((uint32_t)0x07F80000) /* MAC Address Match */ +#define ETH_DMARXND2WBF_HV ((uint32_t)0x07F80000) /* Hash Value */ +#define ETH_DMARXND2WBF_L3FM ((uint32_t)0x08000000) /* Layer 3 Filter Match */ +#define ETH_DMARXND2WBF_L4FM ((uint32_t)0x10000000) /* Layer 4 Filter Match */ +#define ETH_DMARXND2WBF_L3L4FM ((uint32_t)0xE0000000) /* L3L4FM[2:0]: Layer 3 and Layer 4 Filter Number Matched */ +#define ETH_DMARXND2WBF_L3L4FM_0 ((uint32_t)0x20000000) /* L3L4FM bit 0 */ +#define ETH_DMARXND2WBF_L3L4FM_1 ((uint32_t)0x40000000) /* L3L4FM bit 1 */ +#define ETH_DMARXND2WBF_L3L4FM_2 ((uint32_t)0x80000000) /* L3L4FM bit 2 */ + +/** ETH DMA Rx Descriptor Filter flag definition **/ +#define ETH_DMARXDESC_FLTFLAG_VFS ((uint32_t)(ETH_DMARXND2WBF_VFS)) +#define ETH_DMARXDESC_FLTFLAG_SAF ((uint32_t)(ETH_DMARXND2WBF_SAF)) +#define ETH_DMARXDESC_FLTFLAG_DAF ((uint32_t)(ETH_DMARXND2WBF_DAF)) +#define ETH_DMARXDESC_FLTFLAG_HF ((uint32_t)(ETH_DMARXND2WBF_HF)) + + +/** Bit definition for ETH_DMARXND3WBF register (RDES3) **/ +#define ETH_DMARXND3WBF_PL ((uint32_t)0x00007FFF) /* Packet Length */ +#define ETH_DMARXND3WBF_ES ((uint32_t)0x00008000) /* Error Summary */ +#define ETH_DMARXND3WBF_LT ((uint32_t)0x00070000) /* LT[2:0]: Length/Type Field */ +#define ETH_DMARXND3WBF_LT_0 ((uint32_t)0x00010000) /* LT bit 0 */ +#define ETH_DMARXND3WBF_LT_1 ((uint32_t)0x00020000) /* LT bit 1 */ +#define ETH_DMARXND3WBF_LT_2 ((uint32_t)0x00040000) /* LT bit 2 */ +#define ETH_DMARXND3WBF_DE ((uint32_t)0x00080000) /* Dribble Bit Error */ +#define ETH_DMARXND3WBF_RE ((uint32_t)0x00100000) /* Receive Error */ +#define ETH_DMARXND3WBF_OE ((uint32_t)0x00200000) /* Overflow Error */ +#define ETH_DMARXND3WBF_RWT ((uint32_t)0x00400000) /* Receive Watchdog Timeout */ +#define ETH_DMARXND3WBF_GP ((uint32_t)0x00800000) /* Giant Packet */ +#define ETH_DMARXND3WBF_CE ((uint32_t)0x01000000) /* CRC Error */ +#define ETH_DMARXND3WBF_RS0V ((uint32_t)0x02000000) /* Receive Status RDES0 Valid */ +#define ETH_DMARXND3WBF_RS1V ((uint32_t)0x04000000) /* Receive Status RDES1 Valid */ +#define ETH_DMARXND3WBF_RS2V ((uint32_t)0x08000000) /* Receive Status RDES2 Valid */ +#define ETH_DMARXND3WBF_LD ((uint32_t)0x10000000) /* Last Descriptor */ +#define ETH_DMARXND3WBF_FD ((uint32_t)0x20000000) /* First Descriptor */ +#define ETH_DMARXND3WBF_CTXT ((uint32_t)0x40000000) /* Receive Context Descriptor */ +#define ETH_DMARXND3WBF_OWN ((uint32_t)0x80000000) /* Own Bit */ + +#define ETH_DMARXND3WBF_LT_LP ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + & ETH_DMARXND3WBF_LT_1 \ + & ETH_DMARXND3WBF_LT_2)) /* length packet */ +#define ETH_DMARXND3WBF_LT_TP ((uint32_t)(ETH_DMARXND3WBF_LT_0)) /* type packet */ +#define ETH_DMARXND3WBF_LT_ARP ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + | ETH_DMARXND3WBF_LT_1)) /* ARP Request packet type */ +#define ETH_DMARXND3WBF_LT_VLAN ((uint32_t)(ETH_DMARXND3WBF_LT_2)) /* Type packet with VLAN Tag */ +#define ETH_DMARXND3WBF_LT_DVLAN ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + | ETH_DMARXND3WBF_LT_2)) /* Type packet with Double VLAN Tag */ +#define ETH_DMARXND3WBF_LT_MAC ((uint32_t)(ETH_DMARXND3WBF_LT_1 \ + | ETH_DMARXND3WBF_LT_2)) /* MAC Control packet type */ +#define ETH_DMARXND3WBF_LT_OAM ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + | ETH_DMARXND3WBF_LT_1 \ + | ETH_DMARXND3WBF_LT_2)) /* OAM packet type */ + +/** ETH DMA Rx Descriptor flag definition **/ +#define ETH_DMARXDESC_FLAG_ES ((uint32_t)(ETH_DMATXND3WBF_IHE)) +#define ETH_DMARXDESC_FLAG_LT_LP ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + & ETH_DMARXND3WBF_LT_1 \ + & ETH_DMARXND3WBF_LT_2)) /* length packet */ +#define ETH_DMARXDESC_FLAG_LT_TP ((uint32_t)(ETH_DMARXND3WBF_LT_0)) /* type packet */ +#define ETH_DMARXDESC_FLAG_LT_ARP ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + | ETH_DMARXND3WBF_LT_1)) /* ARP Request packet type */ +#define ETH_DMARXDESC_FLAG_LT_VLAN ((uint32_t)(ETH_DMARXND3WBF_LT_2)) /* Type packet with VLAN Tag */ +#define ETH_DMARXDESC_FLAG_LT_DVLAN ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + | ETH_DMARXND3WBF_LT_2)) /* Type packet with Double VLAN Tag */ +#define ETH_DMARXDESC_FLAG_LT_MAC ((uint32_t)(ETH_DMARXND3WBF_LT_1 \ + | ETH_DMARXND3WBF_LT_2)) /* MAC Control packet type */ +#define ETH_DMARXDESC_FLAG_LT_OAM ((uint32_t)(ETH_DMARXND3WBF_LT_0 \ + | ETH_DMARXND3WBF_LT_1 \ + | ETH_DMARXND3WBF_LT_2)) /* OAM packet type */ +#define ETH_DMARXDESC_FLAG_DE ((uint32_t)(ETH_DMARXND3WBF_DE)) +#define ETH_DMARXDESC_FLAG_RE ((uint32_t)(ETH_DMARXND3WBF_RE)) +#define ETH_DMARXDESC_FLAG_OE ((uint32_t)(ETH_DMARXND3WBF_OE)) +#define ETH_DMARXDESC_FLAG_RWT ((uint32_t)(ETH_DMARXND3WBF_RWT)) +#define ETH_DMARXDESC_FLAG_GP ((uint32_t)(ETH_DMARXND3WBF_GP)) +#define ETH_DMARXDESC_FLAG_CE ((uint32_t)(ETH_DMARXND3WBF_CE)) +#define ETH_DMARXDESC_FLAG_RS0V ((uint32_t)(ETH_DMARXND3WBF_RS0V)) +#define ETH_DMARXDESC_FLAG_RS1V ((uint32_t)(ETH_DMARXND3WBF_RS1V)) +#define ETH_DMARXDESC_FLAG_RS2V ((uint32_t)(ETH_DMARXND3WBF_RS2V)) +#define ETH_DMARXDESC_FLAG_LD ((uint32_t)(ETH_DMARXND3WBF_LD)) +#define ETH_DMARXDESC_FLAG_FD ((uint32_t)(ETH_DMARXND3WBF_FD)) + + +/*** ETH DMA Receive Normal Descriptor (Write-Back Format) End ***/ + + +/*** ETH DMA Receive Context Descriptor Start ***/ + +/** Bit definition for ETH_DMARXCD0 register (RDES0) **/ +#define ETH_DMARXCD0_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Packet Timestamp Low */ + +/** Bit definition for ETH_DMARXCD1 register (RDES1) **/ +#define ETH_DMARXCD1_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Packet Timestamp High */ + +/** Bit definition for ETH_DMARXCD3 register (RDES3) **/ +#define ETH_DMARXCD3_DE ((uint32_t)0x20000000) /* Descriptor Error */ +#define ETH_DMARXCD3_CTXT ((uint32_t)0x40000000) /* Receive Context Descriptor */ +#define ETH_DMARXCD3_OWN ((uint32_t)0x80000000) /* Own Bit */ + +/*** ETH DMA Receive Context Descriptor End ***/ + + +/*** ETH Driving Functions Declaration ***/ +void ETH_DeInit(ETH_Module* ETHx); +void ETH_StructInit(ETH_Module* ETHx, ETH_InitType* ETH_InitParam); +void ETH_DMATxDescListInit(ETH_Module* ETHx, ETH_InfoType* pInfo); +void ETH_DMARxDescListInit(ETH_Module* ETHx, ETH_InfoType* pInfo); +void ETH_ConfigMDCNormalClock(ETH_Module* ETHx, RCC_ClocksTypeDef* pClk); +void ETH_ConfigMDCFastClock(ETH_Module* ETHx, uint32_t DivValue); +uint32_t ETH_ReadPHYRegister(ETH_Module* ETHx, uint32_t PHYAddr, uint32_t PHYReg, uint32_t* pRegValue); +uint32_t ETH_WritePHYRegister(ETH_Module* ETHx, uint32_t PHYAddr, uint32_t PHYReg, uint32_t PHYRegValue); +EthFuncStatusType ETH_ExternalPHYInit(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_InitType* ETH_InitParam); +EthFuncStatusType ETH_Init(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_InitType* ETH_InitParam); +void ETH_TxMACCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_RxMACCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_SetHashTable(ETH_Module* ETHx, uint32_t *pHashTable); +void ETH_RxVLANTagStructInit(ETH_RxVLANTagInitType* ETH_RxVTInitParam); +void ETH_RxVLANTagInit(ETH_Module* ETHx, ETH_RxVLANTagInitType* ETH_RxVTInitParam); +void ETH_SetVLANHashTable(ETH_Module* ETHx, uint16_t HashTable); +void ETH_SetRxVLANIdentifier(ETH_Module* ETHx, uint32_t VLANIdentifier); +void ETH_InitiatePauseControlPacket(ETH_Module* ETHx); +void ETH_ActivateBackpressure(ETH_Module* ETHx); +void ETH_PowerDownCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MagicPacketDetectionCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_WakeUpPacketDetectionCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_GlobalUnicastWakeUpCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_ResetWakeUpPacketFilterRegPointer(ETH_Module* ETHx); +void ETH_SetWakeUpPacketFilterRegister(ETH_Module* ETHx, uint32_t *pBuffer); +void ETH_CSRRegisterWrite1ClearCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_SetMACAddress(ETH_Module* ETHx, EthMacAddr0123Type Offset, uint8_t* pAddr); +void ETH_GetMACAddress(ETH_Module* ETHx, EthMacAddr0123Type Offset, uint8_t* pAddr); +void ETH_MACAddressPerfectFilterCmd(ETH_Module* ETHx, EthMacAddr123Type Offset, FunctionalStatus Cmd); +void ETH_SetMACAddressFilter(ETH_Module* ETHx, EthMacAddr123Type Offset, EthMacAddrFilterType Filter); +void ETH_SetMACAddressFilterMaskBytes(ETH_Module* ETHx, EthMacAddr123Type Offset, uint32_t MaskByte); +void ETH_MMCCountersReset(ETH_Module* ETHx); +void ETH_MMCCounterStopRolloverCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MMCResetOnReadCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MMCCounterFreezeCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MMCCounterHalfPreset(ETH_Module* ETHx); +void ETH_MMCCounterFullPreset(ETH_Module* ETHx); +void ETH_MMCCounterUpdateForDropBCPacketCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +uint32_t ETH_GetMMCCounterValue(ETH_Module* ETHx, EthMmcAddrType Offset); +void ETH_MACTimeStampCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_SetTimeStampUpdateMethod(ETH_Module* ETHx, uint32_t Method); +void ETH_MACTimeStampInit(ETH_Module* ETHx); +void ETH_MACTimeStampUpdate(ETH_Module* ETHx); +// void ETH_EnableTimeStampIntTrigger(ETH_Module* ETHx); +void ETH_MACTimeStampAddendRegUpdate(ETH_Module* ETHx); +void ETH_MACTimeStampAllPacketsCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MACTimeStampDigBinRolloverCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_PTPTypePacketProcesCmd(ETH_Module* ETHx, uint32_t PacketType, FunctionalStatus Cmd); +void ETH_MACAddrPTPPacketFilterCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MACTxTimeStampStatusModeCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_SetSubSecondIncrementValue(ETH_Module* ETHx, uint8_t IncValue); +void ETH_SetTimeStampUpdateValue(ETH_Module* ETHx, uint32_t CalMode, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetTimeStampAddendValue(ETH_Module* ETHx, uint32_t AddValue); +uint32_t ETH_GetTimeStampRegValue(ETH_Module* ETHx, EthTsAddrType Offset); +void ETH_ConfigPPSOutput(ETH_Module* ETHx, uint32_t OutputFreq); +void ETH_SetPPSTargetTimeValue(ETH_Module* ETHx, uint32_t SecondValue, uint32_t SubSecondValue); + +void ETH_MTLDropTxStatusCmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_MTLCounterPreset(ETH_Module* ETHx); +void ETH_MTLCounterReset(ETH_Module* ETHx); +void ETH_FlushTransmitQueue(ETH_Module* ETHx); +uint16_t ETH_GetMTLUnderflowPacketCounter(ETH_Module* ETHx); +uint16_t ETH_GetMTLOverflowPacketCounter(ETH_Module* ETHx); +uint16_t ETH_GetMTLMissedPacketCounter(ETH_Module* ETHx); + +void ETH_SoftwareReset(ETH_Module* ETHx); +void ETH_TxDMACmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_RxDMACmd(ETH_Module* ETHx, FunctionalStatus Cmd); +void ETH_ResumeDMATransmission(ETH_Module* ETHx); +void ETH_ResumeDMAReception(ETH_Module* ETHx); +void ETH_SetRxInterruptWatchdogTimer(ETH_Module* ETHx, uint32_t CntUnit, uint32_t CntValue); +uint32_t ETH_GetCurrentTxDescriptorAddress(ETH_Module* ETHx); +uint32_t ETH_GetCurrentRxDescriptorAddress(ETH_Module* ETHx); +uint32_t ETH_GetCurrentTxBufferAddress(ETH_Module* ETHx); +uint32_t ETH_GetCurrentRxBufferAddress(ETH_Module* ETHx); +uint8_t ETH_GetTxDMAErrorType(ETH_Module* ETHx); +uint8_t ETH_GetRxDMAErrorType(ETH_Module* ETHx); +uint16_t ETH_GetDMACh0DroppedPacketCounter(ETH_Module* ETHx); +uint16_t ETH_GetDMACh0ERICounter(ETH_Module* ETHx); + +EthFuncStatusType ETH_RxDescAssignMemory(ETH_InfoType* pInfo, uint32_t Index, uint8_t* pBuffer1, uint8_t* pBuffer2); +EthFuncStatusType ETH_BuildRxDescriptors(ETH_Module* ETHx, ETH_InfoType* pInfo); +EthFuncStatusType ETH_PrepareTxDescriptors(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_TxPacketType* pTxPacket, uint32_t ItMode); +EthFuncStatusType ETH_Transmit(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_TxPacketType* pTxPacket, uint32_t Timeout); +EthFuncStatusType ETH_TransmitIT(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_TxPacketType* pTxPacket); +uint8_t ETH_IsRxDataAvailable(ETH_InfoType* pInfo); +EthFuncStatusType ETH_GetRxDataBuffer(ETH_InfoType* pInfo, ETH_BufferType* pRxBuffer); +uint32_t ETH_GetRxDataLength(ETH_InfoType* pInfo); +EthFuncStatusType ETH_GetRxPacketInfo(ETH_InfoType* pInfo, ETH_RxPacketType* pRxPacket); +void ETH_Start(ETH_Module* ETHx); +void ETH_StartIT(ETH_Module* ETHx, ETH_InfoType* pInfo); +void ETH_Stop(ETH_Module* ETHx); +void ETH_StopIT(ETH_Module* ETHx, ETH_InfoType* pInfo); + +FlagStatus ETH_GetTxDescFlagStatus(ETH_DMADescType* pTxDescriptor, uint32_t Flag); +FlagStatus ETH_GetRxDescExtendedFlagStatus(ETH_DMADescType* pRxDescriptor, uint32_t Flag); +FlagStatus ETH_GetRxDescFilterFlagStatus(ETH_DMADescType* pRxDescriptor, uint32_t Flag); +FlagStatus ETH_GetRxDescFlagStatus(ETH_DMADescType* pRxDescriptor, uint32_t Flag); +FlagStatus ETH_GetFlowControlBusyStatus(ETH_Module* ETHx); +INTStatus ETH_GetMACInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); +FlagStatus ETH_GetMACTxRxFlagStatus(ETH_Module* ETHx, uint32_t Flag); +FlagStatus ETH_GetPMTFlagStatus(ETH_Module* ETHx, uint32_t Flag); +INTStatus ETH_GetMMCRxInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); +INTStatus ETH_GetMMCTxInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); +FlagStatus ETH_GetMACTimeStampFlagStatus(ETH_Module* ETHx, uint32_t Flag); +FlagStatus ETH_GetFlushTransmitQueueStatus(ETH_Module* ETHx); +INTStatus ETH_GetMTLInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); +INTStatus ETH_GetMTLQueueInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); +FlagStatus ETH_GetMTLCounterFlagStatus(ETH_Module* ETHx, uint32_t Flag); +FlagStatus ETH_GetSoftwareResetStatus(ETH_Module* ETHx); +INTStatus ETH_GetDMAInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); +uint32_t ETH_GetDMACh0TxProcessStatus(ETH_Module* ETHx); +uint32_t ETH_GetDMACh0RxProcessStatus(ETH_Module* ETHx); +FlagStatus ETH_GetDMACh0FlagStatus(ETH_Module* ETHx, uint32_t Flag); +INTStatus ETH_GetDMACh0InterruptStatus(ETH_Module* ETHx, uint32_t IntFlag); + +void ETH_ClearMACPHYInterruptFlag(ETH_Module* ETHx); +void ETH_ClearPMTFlag(ETH_Module* ETHx, uint32_t Flag); +void ETH_ClearMMCRxInterruptFlag(ETH_Module* ETHx, uint32_t IntFlag); +void ETH_ClearMMCTxInterruptFlag(ETH_Module* ETHx, uint32_t IntFlag); +void ETH_ClearMACTimeStampFlag(ETH_Module* ETHx, uint32_t Flag); +void ETH_ClearMACTxRxFlag(ETH_Module* ETHx, uint32_t Flag); +void ETH_ClearMACMDIOInterruptFlag(ETH_Module* ETHx); +void ETH_ClearMTLQueueInterruptFlag(ETH_Module* ETHx, uint32_t IntFlag); +void ETH_ClearDMACh0Flag(ETH_Module* ETHx, uint32_t Flag); +void ETH_ClearDMACh0InterruptFlag(ETH_Module* ETHx, uint32_t IntFlag); + +void ETH_ConfigMACInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd); +void ETH_ConfigMMCRxInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd); +void ETH_ConfigMMCTxInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd); +void ETH_ConfigMTLQueueInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd); +void ETH_ConfigDMACh0Interrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd); + +/*** ETH Driving Functions Declaration End ***/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __N32H76X_78X_ETH_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_exti.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_exti.h new file mode 100644 index 0000000000..34cef24979 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_exti.h @@ -0,0 +1,200 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_exti.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_EXTI_H__ +#define __N32H76X_78X_EXTI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32h76x_78x.h" + +/*** EXTI Structure Definition Start ***/ + + + +/** EXTI mode enumeration **/ +typedef enum +{ + EXTI_Mode_Interrupt = 0x60, + EXTI_Mode_Event = 0xA0, +}EXTIMode_TypeDef; + +/** EXTI Trigger enumeration **/ +typedef enum +{ + EXTI_Trigger_Rising = 0x00, + EXTI_Trigger_Falling = 0x20, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +/** EXTI Init Structure definition **/ +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.*/ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. */ +} EXTI_InitType; + +/*** EXTI Structure Definition End ***/ + + +/*** EXTI Macro Definition Start ***/ +/** EXTI_Lines **/ +#define EXTI_LINE0 ((uint32_t)0) /* External interrupt line 0 */ +#define EXTI_LINE1 ((uint32_t)1) /* External interrupt line 1 */ +#define EXTI_LINE2 ((uint32_t)2) /* External interrupt line 2 */ +#define EXTI_LINE3 ((uint32_t)3) /* External interrupt line 3 */ +#define EXTI_LINE4 ((uint32_t)4) /* External interrupt line 4 */ +#define EXTI_LINE5 ((uint32_t)5) /* External interrupt line 5 */ +#define EXTI_LINE6 ((uint32_t)6) /* External interrupt line 6 */ +#define EXTI_LINE7 ((uint32_t)7) /* External interrupt line 7 */ +#define EXTI_LINE8 ((uint32_t)8) /* External interrupt line 8 */ +#define EXTI_LINE9 ((uint32_t)9) /* External interrupt line 9 */ +#define EXTI_LINE10 ((uint32_t)10) /* External interrupt line 10 */ +#define EXTI_LINE11 ((uint32_t)11) /* External interrupt line 11 */ +#define EXTI_LINE12 ((uint32_t)12) /* External interrupt line 12 */ +#define EXTI_LINE13 ((uint32_t)13) /* External interrupt line 13 */ +#define EXTI_LINE14 ((uint32_t)14) /* External interrupt line 14 */ +#define EXTI_LINE15 ((uint32_t)15) /* External interrupt line 15 */ +#define EXTI_LINE16 ((uint32_t)16) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE17 ((uint32_t)17) /* External interrupt line 17 Connected to the RTC_ALARM */ +#define EXTI_LINE18 ((uint32_t)18) /* External interrupt line 18 Connected to the RTC tamper or timestamp*/ +#define EXTI_LINE19 ((uint32_t)19) /* External interrupt line 19 Connected to the RTC wakeup timer */ +#define EXTI_LINE20 ((uint32_t)20) /* External interrupt line 20 Connected to the COMP1 output */ +#define EXTI_LINE21 ((uint32_t)21) /* External interrupt line 21 Connected to the COMP2 output */ +#define EXTI_LINE22 ((uint32_t)22) /* External interrupt line 22 Connected to the COMP3 output */ +#define EXTI_LINE23 ((uint32_t)23) /* External interrupt line 23 Connected to the COMP4 output */ +#define EXTI_LINE24 ((uint32_t)100) /* External interrupt line 24 Connected to the SDMMC1_wkup */ +#define EXTI_LINE25 ((uint32_t)101) /* External interrupt line 25 Connected to the SDMMC2_wkup*/ +#define EXTI_LINE49 ((uint32_t)42) /* External interrupt line 49 Connected to the LPUART1 wakeup */ +#define EXTI_LINE51 ((uint32_t)127) /* External interrupt line 51 Connected to the DCMUA Interrupt */ +#define EXTI_LINE52 ((uint32_t)43) /* External interrupt line 52 Connected to the LPUART2 wakeup */ +#define EXTI_LINE54 ((uint32_t)130) /* External interrupt line 54 Connected to the DCMUB Interruptt */ +#define EXTI_LINE55 ((uint32_t)139) /* External interrupt line 55 Connected to the CM7 AHBS_ABORT */ +#define EXTI_LINE56 ((uint32_t)138) /* External interrupt line 56 Connected to the CM7_AHBSRDY_ERROR */ +#define EXTI_LINE62 ((uint32_t)48) /* External interrupt line 62 Connected to the USB1 wakeup */ +#define EXTI_LINE63 ((uint32_t)49) /* External interrupt line 63 Connected to the USB2 wakeup */ +#define EXTI_LINE64 ((uint32_t)44) /* External interrupt line 64 Connected to the CM7 Correctable Error on Cache Read */ +#define EXTI_LINE65 ((uint32_t)45) /* External interrupt line 65 Connected to the CM7 Fatal Error on Cache Read */ +#define EXTI_LINE66 ((uint32_t)37) /* External interrupt line 66 Connected to the LPTIM1 wakeup */ +#define EXTI_LINE67 ((uint32_t)38) /* External interrupt line 67 Connected to the LPTIM2 wakeup */ +#define EXTI_LINE68 ((uint32_t)39) /* External interrupt line 68 Connected to the LPTIM3 wakeup */ +#define EXTI_LINE69 ((uint32_t)40) /* External interrupt line 69 Connected to the LPTIM4 wakeup */ +#define EXTI_LINE70 ((uint32_t)31) /* External interrupt line 70 Connected to the wakeup1 */ +#define EXTI_LINE71 ((uint32_t)32) /* External interrupt line 71 Connected to the wakeup2 */ +#define EXTI_LINE72 ((uint32_t)33) /* External interrupt line 72 Connected to the wakeup3 */ +#define EXTI_LINE73 ((uint32_t)34) /* External interrupt line 73 Connected to the wakeup4 */ +#define EXTI_LINE74 ((uint32_t)35) /* External interrupt line 74 Connected to the wakeup5 */ +#define EXTI_LINE75 ((uint32_t)36) /* External interrupt line 75 Connected to the wakeup6 */ +#define EXTI_LINE76 ((uint32_t)152) /* External interrupt line 76 Connected to the RCC interrupt */ +#define EXTI_LINE77 ((uint32_t)153) /* External interrupt line 77 Connected to the SEMA1 interrupt */ +#define EXTI_LINE78 ((uint32_t)154) /* External interrupt line 78 Connected to the SEMA2 interrupt */ +#define EXTI_LINE79 ((uint32_t)155) /* External interrupt line 79 Connected to the CortexM4 SEV interrupt */ +#define EXTI_LINE80 ((uint32_t)156) /* External interrupt line 80 Connected to the CortexM7 SEV interrupt */ +#define EXTI_LINE81 ((uint32_t)24) /* External interrupt line 81 Connected to the WWDG1 reset */ +#define EXTI_LINE82 ((uint32_t)25) /* External interrupt line 82 Connected to the WWDG2 reset */ +#define EXTI_LINE83 ((uint32_t)102) /* External interrupt line 83 Connected to the ETH1 Wkup */ +#define EXTI_LINE84 ((uint32_t)103) /* External interrupt line 84 Connected to the ETH2 Wkup */ +#define EXTI_LINE85 ((uint32_t)157) /* External interrupt line 85 Connected to the HSECSS interrupt */ +#define EXTI_LINE86 ((uint32_t)41) /* External interrupt line 86 Connected to the LPTIM5 wakeup */ +#define EXTI_LINE87 ((uint32_t)28) /* External interrupt line 87 Connected to the DSI Error Event */ +#define EXTI_LINE88 ((uint32_t)51) /* External interrupt line 88 Connected to the BKP EMC */ +#define EXTI_LINE89 ((uint32_t)50) /* External interrupt line 89 Connected to the VDDD EMC */ + +/** EXTI_TSSEL_Line **/ +#define EXTI_TSSEL_LINE_MASK (EXTI_TS_SEL_TSSEL) /** External interrupt line all **/ +#define EXTI_TSSEL_LINE0 (EXTI_TS_SEL_EXTI0) /** External interrupt line 0 **/ +#define EXTI_TSSEL_LINE1 (EXTI_TS_SEL_EXTI1) /** External interrupt line 1 **/ +#define EXTI_TSSEL_LINE2 (EXTI_TS_SEL_EXTI2) /** External interrupt line 2 **/ +#define EXTI_TSSEL_LINE3 (EXTI_TS_SEL_EXTI3) /** External interrupt line 3 **/ +#define EXTI_TSSEL_LINE4 (EXTI_TS_SEL_EXTI4) /** External interrupt line 4 **/ +#define EXTI_TSSEL_LINE5 (EXTI_TS_SEL_EXTI5) /** External interrupt line 5 **/ +#define EXTI_TSSEL_LINE6 (EXTI_TS_SEL_EXTI6) /** External interrupt line 6 **/ +#define EXTI_TSSEL_LINE7 (EXTI_TS_SEL_EXTI7) /** External interrupt line 7 **/ +#define EXTI_TSSEL_LINE8 (EXTI_TS_SEL_EXTI8) /** External interrupt line 8 **/ +#define EXTI_TSSEL_LINE9 (EXTI_TS_SEL_EXTI9) /** External interrupt line 9 **/ +#define EXTI_TSSEL_LINE10 (EXTI_TS_SEL_EXTI10) /** External interrupt line 10 **/ +#define EXTI_TSSEL_LINE11 (EXTI_TS_SEL_EXTI11) /** External interrupt line 11 **/ +#define EXTI_TSSEL_LINE12 (EXTI_TS_SEL_EXTI12) /** External interrupt line 12 **/ +#define EXTI_TSSEL_LINE13 (EXTI_TS_SEL_EXTI13) /** External interrupt line 13 **/ +#define EXTI_TSSEL_LINE14 (EXTI_TS_SEL_EXTI14) /** External interrupt line 14 **/ +#define EXTI_TSSEL_LINE15 (EXTI_TS_SEL_EXTI15) /** External interrupt line 15 **/ + +/*** EXTI Macro Definition End ***/ + +/** EXTI Driving Functions Declaration **/ +void EXTI_DeInit(void); + +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct ); +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct ); +void EXTI_TriggerSWInt(uint32_t EXTI_Line ); +FlagStatus EXTI_GetStatusFlag( uint32_t EXTI_Line); +void EXTI_ClrStatusFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClrITPendBit(uint32_t EXTI_Line); +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line); + +#ifdef __cplusplus +} + +#endif + +#endif /* __N32H76X_78X_EXTI_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fdcan.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fdcan.h new file mode 100644 index 0000000000..5836d5093c --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fdcan.h @@ -0,0 +1,1718 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_fdcan.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_FDCAN_H__ +#define __N32H76X_78X_FDCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** FDCAN Message RAM blocks **/ +typedef struct +{ + uint32_t StdFilterStrAddr; /* Specifies the Standard Filter List Start Address. + This parameter must be 32-bit alignment */ + uint32_t ExtFilterStrAddr; /* Specifies the Extended Filter List Start Address. + This parameter must be a 32-bit alignment */ + uint32_t RxFIFO0StrAddr; /* Specifies the Rx FIFO 0 Start Address. + This parameter must be a 32-bit alignment */ + uint32_t RxFIFO1StrAddr; /* Specifies the Rx FIFO 1 Start Address. + This parameter must be a 32-bit alignment */ + uint32_t RxBufferStrAddr; /* Specifies the Rx Buffer Start Address. + This parameter must be a 32-bit alignment */ + uint32_t TxEventFIFOStrAddr; /* Specifies the Tx Event FIFO Start Address. + This parameter must be a 32-bit alignment */ + uint32_t TxBufferStrAddr; /* Specifies the Tx Buffers Start Address. + This parameter must be a 32-bit alignment */ + uint32_t TxFIFOQueueStrAddr; /* Specifies the Tx FIFO/Queue Start Address. + This parameter must be a 32-bit alignment */ + uint32_t TTMemoryStrAddr; /* Specifies the Trigger Memory Start Address. + This parameter must be a 32-bit alignment */ + uint32_t EndAddress; /* Specifies the End Address of the allocated RAM. + This parameter must be a 32-bit alignment */ + uint32_t LastTxFifoQReqBuf; /* FDCAN Tx buffer index of latest Tx FIFO/Queue request */ + uint32_t RxFifo0Size; /* Specifies the number of Rx FIFO0 Elements. + This parameter must be a value between 0 and 64. */ + uint32_t RxFifo1Size; /* Specifies the number of Rx FIFO1 Elements. + This parameter must be a value between 0 and 64. */ + uint32_t RxBufferSize; /* Specifies the number of Dedicated Rx Buffer elements. + This parameter must be a value between 0 and 64. */ + uint32_t TxBufferSize; /* Specifies the number of Dedicated Tx Buffers. + This parameter must be a value between 0 and 32. */ + uint32_t RxFifo0DataSize; /* Specifies the Data Field Size in an Rx FIFO 0 element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + uint32_t RxFifo1DataSize; /* Specifies the Data Field Size in an Rx FIFO 1 element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + uint32_t RxBufferDataSize; /* Specifies the Data Field Size in an Rx Buffer element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + uint32_t TxBufferDataSize; /* Specifies the Data Field Size in a Dedicated Tx Buffer element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ +} FDCAN_MsgRamType; + +/** FDCAN Init Structure Definition **/ +typedef struct +{ + uint32_t FrameFormat; /* FDCAN frame format. This parameter must be one of the following values: + - FDCAN_FRAME_CLASSIC + - FDCAN_FRAME_FD_NO_BRS + - FDCAN_FRAME_FD_BRS */ + uint32_t Mode; /* FDCAN operation mode. This parameter must be one of the following values: + - FDCAN_MODE_NORMAL + - FDCAN_MODE_RESTRICTED_OPERATION + - FDCAN_MODE_BUS_MONITORING + - FDCAN_MODE_INTERNAL_LOOPBACK + - FDCAN_MODE_EXTERNAL_LOOPBACK */ + uint32_t Prescaler; /* Specifies the Nominal Bit Rate Prescaler. + This parameter must be a value between 1 and 512. */ + uint32_t SyncJumpWidth; /* Specifies the Nominal (Re)Synchronization Jump Width. + This parameter must be a value between 1 and 128. */ + uint32_t TimeSeg1; /* Specifies the Nominal time segment before sample point. + This parameter must be a value between 2 and 256. */ + uint32_t TimeSeg2; /* Specifies the Nominal time segment after sample point. + This parameter must be a value between 2 and 128. */ + + uint32_t DataPrescaler; /* Specifies the Data Bit Rate Prescaler. + This parameter must be a value between 1 and 32. */ + uint32_t DataSyncJumpWidth; /* Specifies the Data (Re)Synchronization Jump Width. + This parameter must be a value between 1 and 16. */ + uint32_t DataTimeSeg1; /* Specifies the Data time segment before sample point. + This parameter must be a value between 1 and 32. */ + uint32_t DataTimeSeg2; /* Specifies the Data time segment after sample point. + This parameter must be a value between 1 and 16. */ + + uint32_t MsgRamStrAddr; /* Specifies the Message RAM start address. + This parameter must be one of the following values: + - FDCAN_START_ADDRESS_SRAM5BANK1 , 0x30050000 as FDCAN base address. + - FDCAN_START_ADDRESS_SRAM5BANK2 , 0x30054000 as FDCAN base address.*/ + uint32_t MsgRamOffset; /* Specifies the valid Message RAM word address offset, Overall offset of FDCAN nodes. + This parameter must be a value between 0 and 0x4000 */ + uint32_t StdFilterSize; /* Specifies the number of standard Message ID filters. + This parameter must be a value between 0 and 128. */ + uint32_t ExtFilterSize; /* pecifies the number of extended Message ID filters. + This parameter must be a value between 0 and 64. */ + uint32_t RxFifo0Size; /* Specifies the number of Rx FIFO0 Elements. + This parameter must be a value between 0 and 64. */ + uint32_t RxFifo1Size; /* Specifies the number of Rx FIFO1 Elements. + This parameter must be a value between 0 and 64. */ + uint32_t RxBufferSize; /* Specifies the number of Dedicated Rx Buffer elements. + This parameter must be a value between 0 and 64. */ + uint32_t TxEventSize; /* Specifies the number of Tx Event FIFO elements. + This parameter must be a value between 0 and 32. */ + uint32_t TxBufferSize; /* Specifies the number of Dedicated Tx Buffers. + This parameter must be a value between 0 and 32. */ + uint32_t RxFifo0DataSize; /* Specifies the Data Field Size in an Rx FIFO 0 element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + uint32_t RxFifo1DataSize; /* Specifies the Data Field Size in an Rx FIFO 1 element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + uint32_t RxBufferDataSize; /* Specifies the Data Field Size in an Rx Buffer element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + uint32_t TxBufferDataSize; /* Specifies the Data Field Size in a Dedicated Tx Buffer element,counted in words. + This parameter must be one of the following values: + - FDCAN_DATA_BYTES_8 + - FDCAN_DATA_BYTES_12 + - FDCAN_DATA_BYTES_16 + - FDCAN_DATA_BYTES_20 + - FDCAN_DATA_BYTES_24 + - FDCAN_DATA_BYTES_32 + - FDCAN_DATA_BYTES_48 + - FDCAN_DATA_BYTES_64 */ + + uint32_t TxFifoQueueMode; /* Tx FIFO/Queue Mode selection. + This parameter must be one of the following values: + - FDCAN_TX_FIFO_MODE + - FDCAN_TX_QUEUE_MODE */ + uint32_t TxFifoQueueSize; /* Specifies the number of Tx Buffers used for Tx FIFO/Queue. + This parameter must be a value between 0 and 32. */ + FDCAN_MsgRamType *pMsgInfo; /* Pointer to the message info block used for current FDCANx . */ + FunctionalState AutoRetransmission; /* Enable or disable the automatic retransmission mode. + This parameter must be set to ENABLE or DISABLE. */ + FunctionalState TransmitPause; /* Enable or disable the Transmit Pause feature. + This parameter must be set to ENABLE or DISABLE. */ + FunctionalState ProtocolException; /* Enable or disable the Protocol Exception Handling. + This parameter must be set to ENABLE or DISABLE. */ +} FDCAN_InitType; + +/** FDCAN filter structure definition **/ +typedef struct +{ + uint32_t IdType; /* Specifies the identifier type. + This parameter must be one of the following values: + - FDCAN_STANDARD_ID + - FDCAN_EXTENDED_ID */ + uint32_t FilterIndex; /* Specifies the filter which will be initialized. + This parameter must be a value between: + - 0 and 127, if IdType is FDCAN_STANDARD_ID + - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ + uint32_t FilterType; /* Specifies the filter type. + This parameter must be one of the following values: + - FDCAN_FILTER_RANGE + - FDCAN_FILTER_DUAL + - FDCAN_FILTER_MASK + - FDCAN_FILTER_RANGE_NO_EIDM */ + uint32_t FilterConfig; /* Specifies the filter configuration. + This parameter must be one of the following values: + -FDCAN_FILTER_DISABLE + -FDCAN_FILTER_TO_RXFIFO0 + -FDCAN_FILTER_TO_RXFIFO1 + -FDCAN_FILTER_REJECT + -FDCAN_FILTER_HP + -FDCAN_FILTER_TO_RXFIFO0_HP + -FDCAN_FILTER_TO_RXFIFO1_HP + -FDCAN_FILTER_TO_RXBUFFER */ + uint32_t FilterID1; /* Specifies the filter identification 1. + This parameter must be a value between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + uint32_t FilterID2; /* Specifies the filter identification 2. + This parameter must be a value between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER. */ + uint32_t RxBufferIndex; /* Specifies the index of Rx buffer in which the matching message will be stored. + This parameter must be a value between 0 and 63. + And it is ignored if FilterConfig is not FDCAN_FILTER_TO_RXBUFFER */ +} FDCAN_FilterType; + + +/** FDCAN Tx buffer header structure definition **/ +typedef struct +{ + uint32_t IdType; /* Specifies the identifier type for the message that will be transmitted. + This parameter must be one of the following values: + - FDCAN_STANDARD_ID + - FDCAN_EXTENDED_ID */ + uint32_t ID; /* Specifies the identifier. + This parameter must be a value between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + uint32_t TxFrameType; /* Specifies the frame type of the message that will be transmitted. + This parameter must be one of the following values: + - FDCAN_DATA_FRAME + - FDCAN_REMOTE_FRAME */ + uint32_t DataLength; /* Specifies the length of the data frame that will be transmitted. + This parameter must be one of the following values: + - FDCAN_DLC_BYTES_0 + - FDCAN_DLC_BYTES_1 + - FDCAN_DLC_BYTES_2 + - FDCAN_DLC_BYTES_3 + - FDCAN_DLC_BYTES_4 + - FDCAN_DLC_BYTES_5 + - FDCAN_DLC_BYTES_6 + - FDCAN_DLC_BYTES_7 + - FDCAN_DLC_BYTES_8 + - FDCAN_DLC_BYTES_12 + - FDCAN_DLC_BYTES_16 + - FDCAN_DLC_BYTES_20 + - FDCAN_DLC_BYTES_24 + - FDCAN_DLC_BYTES_32 + - FDCAN_DLC_BYTES_48 + - FDCAN_DLC_BYTES_64 */ + uint32_t ErrorState; /* Specifies the error state indicator. + This parameter must be one of the following values: + - FDCAN_ESI_ACTIVE + - FDCAN_ESI_PASSIVE */ + uint32_t BitRateSwitch; /* Specifies whether the data frame transmitted with or without bit rate switching. + This parameter must be one of the following values: + - FDCAN_BRS_OFF + - FDCAN_BRS_ON */ + uint32_t FDFormat; /* Specifies whether the Tx frame transmitted in classic or FD format. + This parameter must be one of the following values: + - FDCAN_CLASSIC_CAN + - FDCAN_FD_CAN */ + uint32_t TxEventFifo; /* Specifies the event FIFO control. + This parameter must be one of the following values: + - FDCAN_NO_TX_EVENTS + - FDCAN_STORE_TX_EVENTS */ + uint32_t MsgMarker; /* Specifies the message marker copied into Tx Event FIFO element. + This parameter must be a value between 0 and 0xFF */ +} FDCAN_TxHeaderType; + +/** FDCAN Rx header structure definition **/ +typedef struct +{ + uint32_t IdType; /* Specifies the identifier type of the received message. + This parameter must be one of the following values: + - FDCAN_STANDARD_ID + - FDCAN_EXTENDED_ID */ + uint32_t ID; /* Specifies the identifier type for the message that will be transmitted. + This parameter must be a value between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + uint32_t RxFrameType; /* Specifies the the received message frame type. + This parameter must be one of the following values: + - FDCAN_DATA_FRAME + - FDCAN_REMOTE_FRAME */ + uint32_t DataLength; /* Specifies the received frame length. + This parameter must be one of the following values: + - FDCAN_DLC_BYTES_0 + - FDCAN_DLC_BYTES_1 + - FDCAN_DLC_BYTES_2 + - FDCAN_DLC_BYTES_3 + - FDCAN_DLC_BYTES_4 + - FDCAN_DLC_BYTES_5 + - FDCAN_DLC_BYTES_6 + - FDCAN_DLC_BYTES_7 + - FDCAN_DLC_BYTES_8 + - FDCAN_DLC_BYTES_12 + - FDCAN_DLC_BYTES_16 + - FDCAN_DLC_BYTES_20 + - FDCAN_DLC_BYTES_24 + - FDCAN_DLC_BYTES_32 + - FDCAN_DLC_BYTES_48 + - FDCAN_DLC_BYTES_64 */ + uint32_t ErrorState; /* Specifies the error state indicator. + This parameter must be one of the following values: + - FDCAN_ESI_ACTIVE + - FDCAN_ESI_PASSIVE */ + uint32_t BitRateSwitch; /* Specifies whether the Rx frame is received with or without bit + This parameter must be one of the following values: + - FDCAN_BRS_OFF + - FDCAN_BRS_ON */ + uint32_t FDFormat; /* Specifies whether the Rx frame is received in classic or FD + This parameter must be one of the following values: + - FDCAN_CLASSIC_CAN + - FDCAN_FD_CAN */ + uint32_t RxTimestamp; /* Specifies the timestamp counter value captured on start of frame reception. + This parameter must be a value between 0 and 0xFFFF */ + uint32_t FilterIndex; /* Specifies the index of matching Rx acceptance filter element. + This parameter must be a value between: + - 0 and 127, if IdType is FDCAN_STANDARD_ID + - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ + uint32_t Matching; /* Specifies whether the accepted frame did not match any Rx filter. + This parameter must be one of the following values: + - FDCAN_ACCEPT_MACHING_FIDX + - FDCAN_ACCEPT_NON_MATCHING */ + +} FDCAN_RxHeaderType; + +/** FDCAN Tx event FIFO structure definition **/ +typedef struct +{ + uint32_t IdType; /* Specifies the identifier type for the message that will be transmitted. + This parameter must be one of the following values: + - FDCAN_STANDARD_ID + - FDCAN_EXTENDED_ID */ + uint32_t ID; /* Specifies the identifier. + This parameter must be a value between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + uint32_t TxFrameType; /* Specifies the frame type of the message that will be transmitted. + This parameter must be one of the following values: + - FDCAN_DATA_FRAME + - FDCAN_REMOTE_FRAME */ + uint32_t DataLength; /* Specifies the length of the data frame that will be transmitted. + This parameter must be one of the following values: + - FDCAN_DLC_BYTES_0 + - FDCAN_DLC_BYTES_1 + - FDCAN_DLC_BYTES_2 + - FDCAN_DLC_BYTES_3 + - FDCAN_DLC_BYTES_4 + - FDCAN_DLC_BYTES_5 + - FDCAN_DLC_BYTES_6 + - FDCAN_DLC_BYTES_7 + - FDCAN_DLC_BYTES_8 + - FDCAN_DLC_BYTES_12 + - FDCAN_DLC_BYTES_16 + - FDCAN_DLC_BYTES_20 + - FDCAN_DLC_BYTES_24 + - FDCAN_DLC_BYTES_32 + - FDCAN_DLC_BYTES_48 + - FDCAN_DLC_BYTES_64 */ + uint32_t ErrorState; /* Specifies the error state indicator. + This parameter must be one of the following values: + - FDCAN_ESI_ACTIVE + - FDCAN_ESI_PASSIVE */ + uint32_t BitRateSwitch; /* Specifies whether the data frame transmitted with or without bit rate switching. + This parameter must be one of the following values: + - FDCAN_BRS_OFF + - FDCAN_BRS_ON */ + uint32_t FDFormat; /* Specifies whether the Tx frame transmitted in classic or FD format. + This parameter must be one of the following values: + - FDCAN_CLASSIC_CAN + - FDCAN_FD_CAN */ + uint32_t TxTimestamp; /* Specifies the timestamp counter value captured on start of frame transmission. + This parameter must be a value between 0 and 0xFFFF */ + uint32_t MsgMarker; /* Specifies the message marker copied from Tx buffer. + This parameter must be a value between 0 and 0xFF */ + uint32_t EventType; /* Specifies the event type. + This parameter must be one of the following values: + - FDCAN_TX_EVENT + - FDCAN_TX_IN_SPITE_OF_ABORT */ +} FDCAN_TxEventFifoType; + +/** FDCAN High Priority Message Status structure definition **/ +typedef struct +{ + uint32_t FilterList; /* Specifies the filter list of the matching filter element. + This parameter can be one of the following values: + - FDCAN_HP_STANDARD_FILTER_LIST + - FDCAN_HP_EXTENDED_FILTER_LIST */ + uint32_t FilterIndex; /* Specifies the index of matching filter element. + This parameter can be a value between: + - 0 and 127, if FilterList is FDCAN_HP_STANDARD_FILTER_LIST + - 0 and 63, if FilterList is FDCAN_HP_EXTENDED_FILTER_LIST */ + uint32_t MsgStore; /* Specifies the HP Message Storage. + This parameter can be one of the following values: + - FDCAN_HP_STORAGE_NO_FIFO + - FDCAN_HP_STORAGE_MSG_LOST + - FDCAN_HP_STORAGE_RXFIFO0 + - FDCAN_HP_STORAGE_RXFIFO1 */ + uint32_t MsgIndex; /* Specifies the Index of Rx FIFO element to which the message was stored. + This parameter is valid only when MessageStorage is one of the following values + - FDCAN_HP_STORAGE_RXFIFO0 + - FDCAN_HP_STORAGE_RXFIFO1 */ +} FDCAN_HpMsgStatus; + +/** FDCAN Protocol Status structure definition **/ +typedef struct +{ + uint32_t LastError; /* Specifies the type of the last error that occurred on the FDCAN bus. + This parameter can be one of the following values: + - FDCAN_LAST_ERROR_NONE + - FDCAN_LAST_ERROR_STUFF + - FDCAN_LAST_ERROR_FORM + - FDCAN_LAST_ERROR_ACK + - FDCAN_LAST_ERROR_BIT1 + - FDCAN_LAST_ERROR_BIT0 + - FDCAN_LAST_ERROR_CRC + - FDCAN_LAST_ERROR_NO_CHANGE */ + uint32_t LastDataError; /* Specifies the type of the last error that occurred in the data phase of a CAN FD frame. + This parameter can be one of the following values: + - FDCAN_LAST_DATA_ERROR_NONE + - FDCAN_LAST_DATA_ERROR_STUFF + - FDCAN_LAST_DATA_ERROR_FORM + - FDCAN_LAST_DATA_ERROR_ACK + - FDCAN_LAST_DATA_ERROR_BIT1 + - FDCAN_LAST_DATA_ERROR_BIT0 + - FDCAN_LAST_DATA_ERROR_CRC + - FDCAN_LAST_DATA_ERROR_NO_CHANGE */ + uint32_t Activity; /* Specifies the FDCAN module communication state. + This parameter can be one of the following values: + - FDCAN_COM_STATE_SYNC + - FDCAN_COM_STATE_IDLE + - FDCAN_COM_STATE_RX + - FDCAN_COM_STATE_TX */ + uint32_t Error; /* Specifies the FDCAN module error status. + This parameter can be one of the following values: + - FDCAN_ERROR_ACTIVE + - FDCAN_ERROR_PASSIVE */ + uint32_t Warning; /* Specifies the FDCAN module warning status. + This parameter can be one of the following values: + - FDCAN_WARNING_BELOW_96 + - FDCAN_WARNING_REACH_96 */ + uint32_t BusOff; /* Specifies the FDCAN module Bus_Off status. + This parameter can be one of the following values: + - FDCAN_BUS_ON + - FDCAN_BUS_OFF */ + uint32_t RxESIflag; /* Specifies ESI flag of last received CAN FD message. + This parameter can be one of the following values: + - FDCAN_ESI_NOT_SET + - FDCAN_ESI_SET */ + uint32_t RxBRSflag; /* Specifies BRS flag of last received CAN FD message. + This parameter can be one of the following values: + - FDCAN_BRS_NOT_SET + - FDCAN_BRS_SET */ + uint32_t RxFDFflag; /* Specifies if CAN FD message (FDF flag set) has been received since last protocol status. + This parameter can be one of the following values: + - FDCAN_FDMSG_NOT_RECEIVED + - FDCAN_FDMSG_RECEIVED */ + uint32_t Exception; /* Specifies the FDCAN module Protocol Exception status. + This parameter can be one of the following values: + - FDCAN_NO_EXCEPTION + - FDCAN_HAVE_EXCEPTION */ + uint32_t TDCvalue; /* Specifies the Transmitter Delay Compensation Value. + This parameter can be a value between 0 and 127 */ + +} FDCAN_ProtocolStatus; + +/**FDCAN Error Counters structure definition **/ +typedef struct +{ + uint32_t TxErrorCnt; /* Specifies the Transmit Error Counter Value. + This parameter can be a value between 0 and 255 */ + uint32_t RxErrorCnt; /* Specifies the Receive Error Counter Value. + This parameter can be a value between 0 and 127 */ + uint32_t RxErrorPassive; /* Specifies the Receive Error Passive status. + This parameter can be one of the following values: + - FDCAN_RX_ERROR_BELOW_128 + - FDCAN_RX_ERROR_REACH_128 */ + uint32_t ErrorLogging; /* Specifies the Transmit/Receive error logging counter value. + This parameter can be a value between 0 and 255. */ +} FDCAN_ErrorCounters; + +/** FDCAN TT Init structure definition **/ +typedef struct +{ + uint32_t OperationMode; /* Specifies the FDCAN Operation Mode. + This parameter must be one of the following values: + - FDCAN_TT_COMMUNICATION_LEVEL1 + - FDCAN_TT_COMMUNICATION_LEVEL2 + - FDCAN_TT_COMMUNICATION_LEVEL0 */ + uint32_t GapEnable; /* Specifies the FDCAN TT Operation. + This parameter must be one of the following values: + - FDCAN_STRICTLY_TT_OPERATION + - FDCAN_EXT_EVT_SYNC_TT_OPERATION */ + uint32_t TimeMaster; /* Specifies whether the instance is a slave or a potential master. + This parameter must be one of the following values: + - FDCAN_TT_SLAVE + - FDCAN_TT_POTENTIAL_MASTER */ + uint32_t SyncDevLimit; /* Specifies the Synchronization Deviation Limit SDL of the TUR + numerator : TUR = (Numerator +/- SDL) / Denominator. + With : SDL = 2^(SyncDevLimit+5). + This parameter must be a value between 0 and 7 */ + uint32_t InitRefTrigOffset; /* Specifies the Initial Reference Trigger Offset. + This parameter must be a value between 0 and 127 */ + uint32_t ExternalClkSync; /* Enable or disable External Clock Synchronization. + This parameter must be one of the following values: + - FDCAN_TT_EXT_CLK_SYNC_DISABLE + - FDCAN_TT_EXT_CLK_SYNC_ENABLE + This parameter is ignored if OperationMode is FDCAN_TT_COMMUNICATION_LEVEL1 */ + uint32_t AppWdgLimit; /* Specifies the Application Watchdog Limit . + This parameter must be a value between 0 and 255. + This parameter is ignored if OperationMode is FDCAN_TT_COMMUNICATION_LEVEL0 */ + uint32_t GlobalTimeFilter; /* Enable or disable Global Time Filtering. + This parameter must be one of the following values: + - FDCAN_TT_GLOB_TIME_FILT_DISABLE + - FDCAN_TT_GLOB_TIME_FILT_ENABLE + This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1 */ + uint32_t ClockCalibration; /* Enable or disable Automatic Clock Calibration. + This parameter must be one of the following values: + - FDCAN_TT_AUTO_CLK_CALIB_DISABLE + - FDCAN_TT_AUTO_CLK_CALIB_ENABLE + This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1 */ + uint32_t EvtTrigPolarity; /* Specifies the Event Trigger Polarity. + This parameter must be one of the following values: + - FDCAN_TT_EVT_TRIG_POL_RISING + - FDCAN_TT_EVT_TRIG_POL_FALLING + This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0 */ + uint32_t BasicCycles; /* Specifies the number of basic cycles in the system matrix. + This parameter must be one of the following values: + - FDCAN_TT_CYCLES_PER_MATRIX_1 + - FDCAN_TT_CYCLES_PER_MATRIX_2 + - FDCAN_TT_CYCLES_PER_MATRIX_4 + - FDCAN_TT_CYCLES_PER_MATRIX_8 + - FDCAN_TT_CYCLES_PER_MATRIX_16 + - FDCAN_TT_CYCLES_PER_MATRIX_32 + - FDCAN_TT_CYCLES_PER_MATRIX_64 */ + uint32_t CycleStartSync; /* Enable or disable synchronization pulse output at pin fdcan1_soc. + This parameter must be one of the following values: + - FDCAN_TT_NO_SYNC_PULSE + - FDCAN_TT_SYNC_BASIC_CYCLE_START + - FDCAN_TT_SYNC_MATRIX_START */ + uint32_t TxEnableWindow; /* Specifies the length of Tx enable window in NTUs. + This parameter must be a value between 1 and 16 */ + uint32_t ExpTxTrigSize; /* Specifies the number of expected Tx_Triggers in the system matrix. + This is the sum of Tx_Triggers for exclusive, single arbitrating and + merged arbitrating windows. + This parameter must be a value between 0 and 4095 */ + uint32_t TURNumerator; /* Specifies the TUR (Time Unit Ratio) numerator. + It is advised to set this parameter to the largest applicable value. + This parameter must be a value between 0x10000 and 0x1FFFF */ + uint32_t TURDenominator; /* Specifies the TUR (Time Unit Ratio) denominator. + This parameter must be a value between 0x0001 and 0x3FFF */ + uint32_t TrigMemorySize; /* Specifies the number of trigger memory elements. + This parameter must be a value between 0 and 64 */ + uint32_t StopWatchTrigSel; /* Specifies the input to be used as stop watch trigger. + This parameter must be one of the following values: + - FDCAN_TT_STOP_WATCH_TRIGGER_0 + - FDCAN_TT_STOP_WATCH_TRIGGER_1 + - FDCAN_TT_STOP_WATCH_TRIGGER_2 + - FDCAN_TT_STOP_WATCH_TRIGGER_3 */ + uint32_t EventTrigSel; /* Specifies the input to be used as event trigger. + This parameter must be one of the following values: + - FDCAN_TT_EVENT_TRIGGER_0 + - FDCAN_TT_EVENT_TRIGGER_1 + - FDCAN_TT_EVENT_TRIGGER_2 + - FDCAN_TT_EVENT_TRIGGER_3 */ + +} FDCAN_TT_InitType; + +/** FDCAN Trigger structure definition **/ +typedef struct +{ + uint32_t TriggerIndex; /* Specifies the trigger which will be configured. + This parameter must be a number between 0 and 63 */ + uint32_t TimeMark; /* Specifies the cycle time for which the trigger becomes active. + This parameter must be a number between 0 and 0xFFFF */ + uint32_t RepeatFactor; /* Specifies the trigger repeat factor. + This parameter must be one of the following values: + - FDCAN_TT_REPEAT_EVERY_CYCLE + - FDCAN_TT_REPEAT_EVERY_2ND_CYCLE + - FDCAN_TT_REPEAT_EVERY_4TH_CYCLE + - FDCAN_TT_REPEAT_EVERY_8TH_CYCLE + - FDCAN_TT_REPEAT_EVERY_16TH_CYCLE + - FDCAN_TT_REPEAT_EVERY_32ND_CYCLE + - FDCAN_TT_REPEAT_EVERY_64TH_CYCLE */ + uint32_t StartCycle; /* Specifies the index of the first cycle in which the trigger becomes active. + This parameter must be a value between 0 and RepeatFactor. + This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. */ + uint32_t TmEventInt; /* Enable or disable the internal time mark event. + This parameter must be one of the following values: + - FDCAN_TT_TM_NO_INTERNAL_EVENT + - FDCAN_TT_TM_GEN_INTERNAL_EVENT */ + uint32_t TmEventExt; /* Enable or disable the external time mark event. + This parameter must be one of the following values: + - FDCAN_TT_TM_NO_EXTERNAL_EVENT + - FDCAN_TT_TM_GEN_EXTERNAL_EVENT */ + uint32_t TriggerType; /* Specifies the trigger type. + This parameter must be one of the following values: + - FDCAN_TT_TX_REF_TRIGGER + - FDCAN_TT_TX_REF_TRIGGER_GAP + - FDCAN_TT_TX_TRIGGER_SINGLE + - FDCAN_TT_TX_TRIGGER_CONTINUOUS + - FDCAN_TT_TX_TRIGGER_ARBITRATION + - FDCAN_TT_TX_TRIGGER_MERGED + - FDCAN_TT_WATCH_TRIGGER + - FDCAN_TT_WATCH_TRIGGER_GAP + - FDCAN_TT_RX_TRIGGER + - FDCAN_TT_TIME_BASE_TRIGGER + - FDCAN_TT_END_OF_LIST */ + uint32_t FilterType; /* Specifies the filter identifier type. + This parameter must be one of the following values: + - FDCAN_STANDARD_ID + - FDCAN_EXTENDED_ID */ + uint32_t TxBufferIndex; /* Specifies the index of the Tx buffer for which the trigger is valid. + This parameter must be one of the following values: + - FDCAN_TX_BUFFER0 + - FDCAN_TX_BUFFER1 + - FDCAN_TX_BUFFER2 + - FDCAN_TX_BUFFER3 + - FDCAN_TX_BUFFER4 + - FDCAN_TX_BUFFER5 + - FDCAN_TX_BUFFER6 + - FDCAN_TX_BUFFER7 + - FDCAN_TX_BUFFER8 + - FDCAN_TX_BUFFER9 + - FDCAN_TX_BUFFER10 + - FDCAN_TX_BUFFER11 + - FDCAN_TX_BUFFER12 + - FDCAN_TX_BUFFER13 + - FDCAN_TX_BUFFER14 + - FDCAN_TX_BUFFER15 + - FDCAN_TX_BUFFER16 + - FDCAN_TX_BUFFER17 + - FDCAN_TX_BUFFER18 + - FDCAN_TX_BUFFER19 + - FDCAN_TX_BUFFER20 + - FDCAN_TX_BUFFER21 + - FDCAN_TX_BUFFER22 + - FDCAN_TX_BUFFER23 + - FDCAN_TX_BUFFER24 + - FDCAN_TX_BUFFER25 + - FDCAN_TX_BUFFER26 + - FDCAN_TX_BUFFER27 + - FDCAN_TX_BUFFER28 + - FDCAN_TX_BUFFER29 + - FDCAN_TX_BUFFER30 + - FDCAN_TX_BUFFER31 */ + uint32_t FilterIndex; /* Specifies the filter for which the trigger is valid. + This parameter must be a number between: + - 0 and 127, if FilterType is FDCAN_STANDARD_ID + - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ +} FDCAN_TriggerType; + +/** FDCAN TT Operation Status structure definition **/ +typedef struct +{ + uint32_t ErrorLevel; /* Specifies the type of the TT operation error level. + This parameter can be one of the following values: + - FDCAN_TT_NO_ERROR + - FDCAN_TT_WARNING + - FDCAN_TT_ERROR + - FDCAN_TT_SEVERE_ERROR */ + uint32_t MasterState; /* Specifies the type of the TT master state. + This parameter can be one of the following values: + - FDCAN_TT_MASTER_OFF + - FDCAN_TT_TIME_SLAVE + - FDCAN_TT_BACKUP_TIME_MASTER + - FDCAN_TT_CURRENT_TIME_MASTER */ + uint32_t SyncState; /* Specifies the type of the TT synchronization state. + This parameter can be one of the following values: + - FDCAN_TT_OUT_OF_SYNC + - FDCAN_TT_SYNCHRONIZING + - FDCAN_TT_IN_GAP + - FDCAN_TT_IN_SCHEDULE */ + uint32_t GTimeQuality; /* Specifies the Quality of Global Time Phase. + This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. + This parameter can be: + - FDCAN_TT_GTIME_NOT_VALID + - FDCAN_TT_GTIME_IN_MASTER_PHASE */ + uint32_t ClockQuality; /* Specifies the Quality of Clock Speed. + This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. + This parameter can be: + - FDCAN_TT_LOCAL_CLOCK_NOT_SYNC + - FDCAN_TT_SYNC_DEV_LESS_THAN_SDL */ + uint32_t RefTrigOffset; /* Specifies the Actual Reference Trigger Offset Value. + This parameter can be a number between 0 and 0xFF */ + uint32_t GTimeDiscPending; /* Specifies the Global Time Discontinuity State. + This parameter can be: + - FDCAN_TT_NO_GTIME_PENDING + - FDCAN_TT_WATI_GTIMESYNC_PRESENT */ + uint32_t GapFinished; /* Specifies whether a Gap is finished. + This parameter can be: + - FDCAN_TT_GAP_RESET + - FDCAN_TT_GAP_FINISHED */ + uint32_t MasterPriority; /* Specifies the Priority of actual Time Master. + This parameter can be a number between 0 and 0x7 */ + uint32_t GapStarted; /* Specifies whether a Gap is started. + This parameter can be: + - FDCAN_TT_NO_GAP + - FDCAN_TT_GAP_STARTED */ + uint32_t WaitForEvt; /* Specifies whether a Gap is announced. + This parameter can be: + - FDCAN_TT_GAP_NOT_ANNOUNCED + - FDCAN_TT_REF_MSG_RECEIVED */ + uint32_t AppWdgEvt; /* Specifies the Application Watchdog State. + This parameter can be: + - FDCAN_TT_WATCHDOG_VALID + - FDCAN_TT_WATCHDOG_INVALID */ + uint32_t ECSPending; /* Specifies the External Clock Synchronization State. + This parameter can be: + - FDCAN_TT_NO_EXT_CLOCK_SYNC + - FDCAN_TT_WAIT_EXT_CLOCK_SYNC */ + uint32_t PhaseLock; /* Specifies the Phase Lock State. + This parameter can be: + - FDCAN_TT_PHASE_OUT_OF_RANGE + - FDCAN_TT_PHASE_IN_RANGE */ +} FDCAN_TT_Status; + + +/** FDCAN timeout constant define **/ +#define FDCAN_TIMEOUT_VALUE (600000U) /*10ms*/ +#define FDCAN_TIMEOUT_COUNT (50U) + +/*** FDCAN message ram define ***/ + +/*** FDCAN Message ram size define ***/ +#define FDCAN_MESSAGE_RAM_SIZE (0x1000UL*4UL) /* max 0x1000 words */ + +/*** FDCAN Message element size define, conuted in word(32bit) ***/ +#define FDCAN_STD_FILTER_WORDS (1U) +#define FDCAN_EXT_FILTER_WORDS (2U) +#define FDCAN_TX_EVENT_FIFO_WORDS (2U) +#define FDCAN_TT_MEMORY_WORDS (2U) + +/*** FD CAN message element bit define for Rx FIFO0/1, Rx buffer, Tx buffer, and Tx evnet fifo ***/ +/** Element 1st byte define, used for both Rx FIFO0/1, Rx buffer, Tx buffer, and Tx evnet fifo **/ +#define FDCAN_ELEMENT_ESI ((uint32_t)0x80000000U) /* Error State Indicator */ +#define FDCAN_ELEMENT_XTD ((uint32_t)0x40000000U) /* Extended Identifier */ +#define FDCAN_ELEMENT_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */ +#define FDCAN_ELEMENT_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */ +#define FDCAN_ELEMENT_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */ + +/** Part of element 2nd byte define, used for both Rx FIFO0/1, Rx buffer, Tx buffer, and Tx evnet fifo **/ +#define FDCAN_ELEMENT_FDF ((uint32_t)0x00200000U) /* FD Format */ +#define FDCAN_ELEMENT_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */ +#define FDCAN_ELEMENT_DLC ((uint32_t)0x000F0000U) /* Data Length Code */ + +/** Part of element 2nd byte define, used for both Rx FIFO0/1, Rx buffer **/ +#define FDCAN_ELEMENT_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */ +#define FDCAN_ELEMENT_FIDX ((uint32_t)0x7F000000U) /* Filter Index */ + +/** Part of element 2nd byte define, used for both Rx FIFO0/1, Rx buffer, and Tx evnet fifo **/ +#define FDCAN_ELEMENT_TS ((uint32_t)0x0000FFFFU) /* Timestamp */ + +/** Part of element 2nd byte define, used for Tx buffer and Tx evnet fifo **/ +#define FDCAN_ELEMENT_MM ((uint32_t)0xFF000000U) /* Message Marker */ + +/** Part of element 2nd byte define, just used for Tx buffer **/ +#define FDCAN_ELEMENT_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */ + +/** Part of element 2nd byte define, just used for Tx evnet fifo **/ +#define FDCAN_ELEMENT_ET ((uint32_t)0x00C00000U) /* Event type */ + +/** Bit offset define **/ +#define FDCAN_ELEMENT_STDID_OFFSET (REG_BIT18_OFFSET) +#define FDCAN_ELEMENT_FIDX_OFFSET (REG_BIT24_OFFSET) +#define FDCAN_ELEMENT_DLC_OFFSET (REG_BIT16_OFFSET) +#define FDCAN_ELEMENT_MM_OFFSET (REG_BIT24_OFFSET) + +/** FDCAN Error State Indicator, used for elememnt FDCAN_ELEMENT_ESI **/ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /* Transmitting node is error active */ +#define FDCAN_ESI_PASSIVE (FDCAN_ELEMENT_ESI) /* Transmitting node is error passive */ + +/** ID type define, used for elememnt FDCAN_ELEMENT_XTD and register TTRMC **/ +#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /* Standard ID element */ +#define FDCAN_EXTENDED_ID (FDCAN_ELEMENT_XTD) /* Extended ID element */ + +/** Standard frame type define, used for elememnt FDCAN_ELEMENT_RTR **/ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /* Data frame */ +#define FDCAN_REMOTE_FRAME (FDCAN_ELEMENT_RTR) /* Remote frame */ + +/** FDCAN format define, used for elememnt FDCAN_ELEMENT_FDF **/ +#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /* Frame transmitted/received in Classic CAN format */ +#define FDCAN_FD_CAN (FDCAN_ELEMENT_FDF) /* Frame transmitted/received in FDCAN format */ + +/** FDCAN Bit Rate Switching define, used for elememnt FDCAN_ELEMENT_BRS **/ +#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /* FDCAN frames transmitted/received without bit rate switching */ +#define FDCAN_BRS_ON (FDCAN_ELEMENT_BRS) /* FDCAN frames transmitted/received with bit rate switching */ + +/** FDCAN Data Length Code define, used for element FDCAN_ELEMENT_DLC **/ +#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /* 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /* 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /* 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /* 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /* 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /* 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /* 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /* 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /* 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /* 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /* 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /* 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /* 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /* 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /* 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 (FDCAN_ELEMENT_DLC) /* 64 bytes data field */ + +/** FDCAN accept non-natching frame define, used for element FDCAN_ELEMENT_ANMF **/ +#define FDCAN_ACCEPT_MACHING_FIDX ((uint32_t)0x00000000U) /* Accepted frame matches the ID indecated by FIDX */ +#define FDCAN_ACCEPT_NON_MATCHING (FDCAN_ELEMENT_ANMF) /* Accepted frame does't match and ID */ + +/** FDCAN Event FIFO control define, used for element **/ +#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /* Do not store Tx events */ +#define FDCAN_STORE_TX_EVENTS (FDCAN_ELEMENT_EFC) /* Store Tx events */ + +/** FDCAN Event Type, used for element FDCAN_ELEMENT_ET **/ +#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /* Tx event */ +#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /* Transmission in spite of cancellation */ + +/*** FD CAN message element bit define for Standard and Extended message ID filter ***/ +/** FDCAN Filter element define, used for Standard filter **/ +#define FDCAN_ELEMENT_SFT ((uint32_t)0xC0000000U) /* Standard Filter Type */ +#define FDCAN_ELEMENT_SFEC ((uint32_t)0x38000000U) /* Standard Filter Element Configuration */ +#define FDCAN_ELEMENT_SFID1 ((uint32_t)0x07FF0000U) /* Standard Filter ID 1 */ +#define FDCAN_ELEMENT_SFID2 ((uint32_t)0x000007FFU) /* Standard Filter ID 2 */ + +/** FDCAN Filter element define, used for Externded filter **/ +/* Byte 0 */ +#define FDCAN_ELEMENT_EFEC ((uint32_t)0xE0000000U) /* Externded Filter Element Configuration */ +#define FDCAN_ELEMENT_EFID1 ((uint32_t)0x1FFFFFFFU) /* Externded Filter ID 1 */ + +/* Byte 1 */ +#define FDCAN_ELEMENT_EFT ((uint32_t)0xC0000000U) /* Externded Filter Type */ +#define FDCAN_ELEMENT_EFID2 ((uint32_t)0x1FFFFFFFU) /* Externded Filter ID 1 */ + +/** FDCAN Filter Type, used for both FDCAN_ELEMENT_EFT and FDCAN_ELEMENT_SFT **/ +#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /* Range filter from FilterID1 to FilterID2 */ +#define FDCAN_FILTER_DUAL ((uint32_t)0x40000000U) /* Dual ID filter for FilterID1 or FilterID2 */ +#define FDCAN_FILTER_MASK ((uint32_t)0x80000000U) /* Classic filter: FilterID1 = filter, FilterID2 = mask */ +#define FDCAN_FILTER_RANGE_NO_EIDM (FDCAN_ELEMENT_EFT) /* Range filter from FilterID1 to FilterID2, EIDM mask not applied */ + +/** FDCAN Filter Configuration, usd for FDCAN_ELEMENT_EFEC and FDCAN_ELEMENT_SFEC, it must be used with bit offset **/ +#define FDCAN_FILTER_DISABLE ((uint32_t)0x0000000U) /* Disable filter element */ +#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x0000001U) /* Store in Rx FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x0000002U) /* Store in Rx FIFO 1 if filter matches */ +#define FDCAN_FILTER_REJECT ((uint32_t)0x0000003U) /* Reject ID if filter matches */ +#define FDCAN_FILTER_HP ((uint32_t)0x0000004U) /* Set high priority if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x0000005U) /* Set high priority and store in FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x0000006U) /* Set high priority and store in FIFO 1 if filter matches */ +#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x0000007U) /* Store into Rx Buffer, configuration of FilterType ignored */ + +/** Bit offset define **/ +#define FDCAN_ELEMENT_SFEC_OFFSET (REG_BIT27_OFFSET) +#define FDCAN_ELEMENT_ID1_OFFSET (REG_BIT16_OFFSET) +#define FDCAN_ELEMENT_EFEC_OFFSET (REG_BIT29_OFFSET) + +/*** FD CAN message element bit define for Trigger Memory ***/ +/* Byte 0 */ +#define FDCAN_ELEMENT_TM ((uint32_t)0xFFFF0000U) /* Time Mark */ +#define FDCAN_ELEMENT_CC ((uint32_t)0x00007F00U) /* Cycle Code */ +#define FDCAN_ELEMENT_TMIN ((uint32_t)0x00000020U) /* Internal Time Mark Event */ +#define FDCAN_ELEMENT_TMEX ((uint32_t)0x00000010U) /* External Time Mark Event */ +#define FDCAN_ELEMENT_TYPE ((uint32_t)0x0000000FU) /* Trigger Type */ + +/* Byte 1 */ +#define FDCAN_ELEMENT_FTYPE ((uint32_t)0x00800000U) /* Filter Type */ +#define FDCAN_ELEMENT_MNR ((uint32_t)0x007F0000U) /* Message Number */ +#define FDCAN_ELEMENT_MSC ((uint32_t)0x00000007U) /* Message Status Count */ + +/** Bit offset define **/ +#define FDCAN_ELEMENT_TM_OFFSET (REG_BIT16_OFFSET) +#define FDCAN_ELEMENT_CC_OFFSET (REG_BIT8_OFFSET) +#define FDCAN_ELEMENT_MNR_OFFSET (REG_BIT16_OFFSET) + +/** FDCAN TT trigger valid cycle code, used for both FDCAN_ELEMENT_CC and register TTTMK **/ +#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /* Trigger valid for all cycles */ +#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /* Trigger valid every 2nd cycle */ +#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /* Trigger valid every 4th cycle */ +#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /* Trigger valid every 8th cycle */ +#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /* Trigger valid every 16th cycle */ +#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /* Trigger valid every 32nd cycle */ +#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /* Trigger valid every 64th cycle */ + +/** FDCAN TT time mark event internal, used for FDCAN_ELEMENT_TMIN **/ +#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /* No action */ +#define FDCAN_TT_TM_GEN_INTERNAL_EVENT (FDCAN_ELEMENT_TMIN) /* Internal event is generated when trigger becomes active */ + +/** FDCAN TT time mark event external, used for FDCAN_ELEMENT_TMEX **/ +#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /* No action */ +#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT (FDCAN_ELEMENT_TMEX) /* External event (pulse) is generated when trigger becomes active */ + +/** FDCAN TT trigger type,used for FDCAN_ELEMENT_TYPE **/ +#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /* Transmit reference message in strictly time-triggered operation */ +#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /* Transmit reference message in external event-synchronized time-triggered operation */ +#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /* Start a single transmission in an exclusive time window */ +#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /* Start a continuous transmission in an exclusive time window */ +#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /* Start a transmission in an arbitration time window */ +#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /* Start a merged arbitration window */ +#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /* Check for missing reference messages in strictly time-triggered operation */ +#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /* Check for missing reference messages in external event-synchronized time-triggered operation */ +#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /* Check for the reception of periodic messages in exclusive time windows */ +#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /* Generate internal/external events depending on TmEventInt/TmEventExt configuration */ +#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /* Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ + +/** FDCAN TT trigger type,used for FDCAN_ELEMENT_FTYPE **/ +#define FDCAN_FILTER_STANDARD_ID ((uint32_t)0x00000000U) /* Standard ID element */ +#define FDCAN_FILTER_EXTENDED_ID (FDCAN_ELEMENT_FTYPE) /* Extended ID element */ + +/*** FDCAN register define ***/ + +/** FDCAN frame format define **/ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /* Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS (FDCAN_CCCR_FDOE) /* FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS (FDCAN_CCCR_FDOE|FDCAN_CCCR_BRSE) /* FD mode with BitRate Switching */ + +/** FDCAN operatioin mode define **/ +#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /* Normal mode */ +#define FDCAN_MODE_RESTRICTED_OPERATION (FDCAN_CCCR_ASM) /* Restricted Operation mode */ +#define FDCAN_MODE_BUS_MONITORING (FDCAN_CCCR_MON) /* Bus Monitoring mode */ +#define FDCAN_MODE_INTERNAL_LOOPBACK (FDCAN_CCCR_TEST|FDCAN_CCCR_MON) /* Internal LoopBack mode */ +#define FDCAN_MODE_EXTERNAL_LOOPBACK (FDCAN_CCCR_TEST) /* External LoopBack mode */ + +/** FDCAN Tx FIFO and Tx Queue operation modes define **/ +#define FDCAN_TX_FIFO_MODE ((uint32_t)0x00000000U) /* FIFO mode */ +#define FDCAN_TX_QUEUE_MODE ((uint32_t)FDCAN_TXBC_TFQM) /* Queue mode */ + +/** FDCAN data field size define, conuted in words, used for both Rx FIFO0/1, Rx buffer, Tx buffer **/ +#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /* 8 bytes data field */ +#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /* 12 bytes data field */ +#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /* 16 bytes data field */ +#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /* 20 bytes data field */ +#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /* 24 bytes data field */ +#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /* 32 bytes data field */ +#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /* 48 bytes data field */ +#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /* 64 bytes data field */ + +/** FDCAN FDCAN Tx Location bit define, used for TXBRP, TXBAR, TXBCR, TXBTO, TXBCF, TXBTIE, TXBCIE registers **/ +#define FDCAN_TX_BUFFER0 (FDCAN_TXBRP_TRP0 ) /* Tx Buffer 0 bit */ +#define FDCAN_TX_BUFFER1 (FDCAN_TXBRP_TRP1 ) /* Tx Buffer 1 bit */ +#define FDCAN_TX_BUFFER2 (FDCAN_TXBRP_TRP2 ) /* Tx Buffer 2 bit */ +#define FDCAN_TX_BUFFER3 (FDCAN_TXBRP_TRP3 ) /* Tx Buffer 3 bit */ +#define FDCAN_TX_BUFFER4 (FDCAN_TXBRP_TRP4 ) /* Tx Buffer 4 bit */ +#define FDCAN_TX_BUFFER5 (FDCAN_TXBRP_TRP5 ) /* Tx Buffer 5 bit */ +#define FDCAN_TX_BUFFER6 (FDCAN_TXBRP_TRP6 ) /* Tx Buffer 6 bit */ +#define FDCAN_TX_BUFFER7 (FDCAN_TXBRP_TRP7 ) /* Tx Buffer 7 bit */ +#define FDCAN_TX_BUFFER8 (FDCAN_TXBRP_TRP8 ) /* Tx Buffer 8 bit */ +#define FDCAN_TX_BUFFER9 (FDCAN_TXBRP_TRP9 ) /* Tx Buffer 9 bit */ +#define FDCAN_TX_BUFFER10 (FDCAN_TXBRP_TRP10) /* Tx Buffer 10 bit */ +#define FDCAN_TX_BUFFER11 (FDCAN_TXBRP_TRP11) /* Tx Buffer 11 bit */ +#define FDCAN_TX_BUFFER12 (FDCAN_TXBRP_TRP12) /* Tx Buffer 12 bit */ +#define FDCAN_TX_BUFFER13 (FDCAN_TXBRP_TRP13) /* Tx Buffer 13 bit */ +#define FDCAN_TX_BUFFER14 (FDCAN_TXBRP_TRP14) /* Tx Buffer 14 bit */ +#define FDCAN_TX_BUFFER15 (FDCAN_TXBRP_TRP15) /* Tx Buffer 15 bit */ +#define FDCAN_TX_BUFFER16 (FDCAN_TXBRP_TRP16) /* Tx Buffer 16 bit */ +#define FDCAN_TX_BUFFER17 (FDCAN_TXBRP_TRP17) /* Tx Buffer 17 bit */ +#define FDCAN_TX_BUFFER18 (FDCAN_TXBRP_TRP18) /* Tx Buffer 18 bit */ +#define FDCAN_TX_BUFFER19 (FDCAN_TXBRP_TRP19) /* Tx Buffer 19 bit */ +#define FDCAN_TX_BUFFER20 (FDCAN_TXBRP_TRP20) /* Tx Buffer 20 bit */ +#define FDCAN_TX_BUFFER21 (FDCAN_TXBRP_TRP21) /* Tx Buffer 21 bit */ +#define FDCAN_TX_BUFFER22 (FDCAN_TXBRP_TRP22) /* Tx Buffer 22 bit */ +#define FDCAN_TX_BUFFER23 (FDCAN_TXBRP_TRP23) /* Tx Buffer 23 bit */ +#define FDCAN_TX_BUFFER24 (FDCAN_TXBRP_TRP24) /* Tx Buffer 24 bit */ +#define FDCAN_TX_BUFFER25 (FDCAN_TXBRP_TRP25) /* Tx Buffer 25 bit */ +#define FDCAN_TX_BUFFER26 (FDCAN_TXBRP_TRP26) /* Tx Buffer 26 bit */ +#define FDCAN_TX_BUFFER27 (FDCAN_TXBRP_TRP27) /* Tx Buffer 27 bit */ +#define FDCAN_TX_BUFFER28 (FDCAN_TXBRP_TRP28) /* Tx Buffer 28 bit */ +#define FDCAN_TX_BUFFER29 (FDCAN_TXBRP_TRP29) /* Tx Buffer 29 bit */ +#define FDCAN_TX_BUFFER30 (FDCAN_TXBRP_TRP30) /* Tx Buffer 30 bit */ +#define FDCAN_TX_BUFFER31 (FDCAN_TXBRP_TRP31) /* Tx Buffer 31 bit */ + +/** FDCAN Rx buffer index define **/ +#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /* Rx Buffer 0 */ +#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /* Rx Buffer 1 */ +#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /* Rx Buffer 2 */ +#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /* Rx Buffer 3 */ +#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /* Rx Buffer 4 */ +#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /* Rx Buffer 5 */ +#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /* Rx Buffer 6 */ +#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /* Rx Buffer 7 */ +#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /* Rx Buffer 8 */ +#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /* Rx Buffer 9 */ +#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /* Rx Buffer 10 */ +#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /* Rx Buffer 11 */ +#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /* Rx Buffer 12 */ +#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /* Rx Buffer 13 */ +#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /* Rx Buffer 14 */ +#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /* Rx Buffer 15 */ +#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /* Rx Buffer 16 */ +#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /* Rx Buffer 17 */ +#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /* Rx Buffer 18 */ +#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /* Rx Buffer 19 */ +#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /* Rx Buffer 20 */ +#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /* Rx Buffer 21 */ +#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /* Rx Buffer 22 */ +#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /* Rx Buffer 23 */ +#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /* Rx Buffer 24 */ +#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /* Rx Buffer 25 */ +#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /* Rx Buffer 26 */ +#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /* Rx Buffer 27 */ +#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /* Rx Buffer 28 */ +#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /* Rx Buffer 29 */ +#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /* Rx Buffer 30 */ +#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /* Rx Buffer 31 */ +#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /* Rx Buffer 32 */ +#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /* Rx Buffer 33 */ +#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /* Rx Buffer 34 */ +#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /* Rx Buffer 35 */ +#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /* Rx Buffer 36 */ +#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /* Rx Buffer 37 */ +#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /* Rx Buffer 38 */ +#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /* Rx Buffer 39 */ +#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /* Rx Buffer 40 */ +#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /* Rx Buffer 41 */ +#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /* Rx Buffer 42 */ +#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /* Rx Buffer 43 */ +#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /* Rx Buffer 44 */ +#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /* Rx Buffer 45 */ +#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /* Rx Buffer 46 */ +#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /* Rx Buffer 47 */ +#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /* Rx Buffer 48 */ +#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /* Rx Buffer 49 */ +#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /* Rx Buffer 50 */ +#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /* Rx Buffer 51 */ +#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /* Rx Buffer 52 */ +#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /* Rx Buffer 53 */ +#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /* Rx Buffer 54 */ +#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /* Rx Buffer 55 */ +#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /* Rx Buffer 56 */ +#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /* Rx Buffer 57 */ +#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /* Rx Buffer 58 */ +#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /* Rx Buffer 59 */ +#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /* Rx Buffer 60 */ +#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /* Rx Buffer 61 */ +#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /* Rx Buffer 62 */ +#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /* Rx Buffer 63 */ + +/** FDCAN virtual index define for Rx FIFO and Tx envent FIFO **/ +#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /* Rx FIFO 0 */ +#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /* Rx FIFO 1 */ +#define FDCAN_TX_EVENT_FIFO ((uint32_t)0x00000042U) /* Tx event FIFO */ + +/** FDCAN High Priority Message Storage **/ +#define FDCAN_HP_STANDARD_FILTER_LIST (FDCAN_HPMS_FLST_STD) /* Standard filter list */ +#define FDCAN_HP_EXTENDED_FILTER_LIST (FDCAN_HPMS_FLST_EXT) /* Extended filter list */ + +/** FDCAN High Priority Message Storage **/ +#define FDCAN_HP_STORAGE_NO_FIFO (FDCAN_HPMS_MSI_NO_FIFO ) /* No FIFO selected */ +#define FDCAN_HP_STORAGE_MSG_LOST (FDCAN_HPMS_MSI_MSG_LOST) /* FIFO message lost */ +#define FDCAN_HP_STORAGE_RXFIFO0 (FDCAN_HPMS_MSI_FIFO0 ) /* Message stored in FIFO 0 */ +#define FDCAN_HP_STORAGE_RXFIFO1 (FDCAN_HPMS_MSI_FIFO0 ) /* Message stored in FIFO 1 */ + +/** FDCAN receive error passive **/ +#define FDCAN_RX_ERROR_BELOW_128 ((uint32_t)0x00000000U) /* The receive error counter is below the error passive level of 128 */ +#define FDCAN_RX_ERROR_REACH_128 (FDCAN_ECR_RP) /* The receive error counter has reached the error passive level of 128 */ + +/** FDCAN protocol error code **/ +#define FDCAN_LAST_ERROR_NONE (FDCAN_PSR_LEC_NONE ) /* No error occurred */ +#define FDCAN_LAST_ERROR_STUFF (FDCAN_PSR_LEC_STUFF ) /* Stuff error */ +#define FDCAN_LAST_ERROR_FORM (FDCAN_PSR_LEC_FORM ) /* Form error */ +#define FDCAN_LAST_ERROR_ACK (FDCAN_PSR_LEC_ACK ) /* Acknowledge error */ +#define FDCAN_LAST_ERROR_BIT1 (FDCAN_PSR_LEC_BIT1 ) /* Bit 1 (recessive) error */ +#define FDCAN_LAST_ERROR_BIT0 (FDCAN_PSR_LEC_BIT0 ) /* Bit 0 (dominant) error */ +#define FDCAN_LAST_ERROR_CRC (FDCAN_PSR_LEC_CRC ) /* CRC check sum error */ +#define FDCAN_LAST_ERROR_NO_CHANGE (FDCAN_PSR_LEC_NO_CHANGE) /* No change since last read */ + +#define FDCAN_LAST_DATA_ERROR_NONE (FDCAN_PSR_DLEC_NONE ) /* No error occurred */ +#define FDCAN_LAST_DATA_ERROR_STUFF (FDCAN_PSR_DLEC_STUFF ) /* Stuff error */ +#define FDCAN_LAST_DATA_ERROR_FORM (FDCAN_PSR_DLEC_FORM ) /* Form error */ +#define FDCAN_LAST_DATA_ERROR_ACK (FDCAN_PSR_DLEC_ACK ) /* Acknowledge error */ +#define FDCAN_LAST_DATA_ERROR_BIT1 (FDCAN_PSR_DLEC_BIT1 ) /* Bit 1 (recessive) error */ +#define FDCAN_LAST_DATA_ERROR_BIT0 (FDCAN_PSR_DLEC_BIT0 ) /* Bit 0 (dominant) error */ +#define FDCAN_LAST_DATA_ERROR_CRC (FDCAN_PSR_DLEC_CRC ) /* CRC check sum error */ +#define FDCAN_LAST_DATA_ERROR_NO_CHANGE (FDCAN_PSR_DLEC_NO_CHANGE) /* No change since last read */ + +/** FDCAN protocol communication state **/ +#define FDCAN_COM_STATE_SYNC (FDCAN_PSR_ACT_SYNC) /* Node is synchronizing on CAN communication */ +#define FDCAN_COM_STATE_IDLE (FDCAN_PSR_ACT_IDLE) /* Node is neither receiver nor transmitter */ +#define FDCAN_COM_STATE_RX (FDCAN_PSR_ACT_RX ) /* Node is operating as receiver */ +#define FDCAN_COM_STATE_TX (FDCAN_PSR_ACT_TX ) /* Node is operating as transmitter */ + +/** FDCAN protocol error passive **/ +#define FDCAN_ERROR_ACTIVE ((uint32_t)0x00000000U) /* Node is active error state */ +#define FDCAN_ERROR_PASSIVE (FDCAN_PSR_EP) /* Node is passive error state */ + +/** FDCAN protocol warning status **/ +#define FDCAN_WARNING_BELOW_96 ((uint32_t)0x00000000U) /* RxErrorCnt and TxErrorCnt are below the Error_Warning limit of 96 */ +#define FDCAN_WARNING_REACH_96 (FDCAN_PSR_EW) /* At least one of error counters has reached the Error_Warning limit of 96 */ + +/** FDCAN protocol bus off status **/ +#define FDCAN_BUS_ON ((uint32_t)0x00000000U) /* Node is not bus off state */ +#define FDCAN_BUS_OFF (FDCAN_PSR_BO) /* Node is bus off state */ + +/** FDCAN protocol ESI flag of last received FDCAN message **/ +#define FDCAN_ESI_NOT_SET ((uint32_t)0x00000000U) /* ESI flag of last received FDCAN message is not set */ +#define FDCAN_ESI_SET (FDCAN_PSR_RESI) /* ESI flag of last received FDCAN message is set */ + +/** FDCAN protocol BRS flag of last received FDCAN message **/ +#define FDCAN_BRS_NOT_SET ((uint32_t)0x00000000U) /* BSR flag of last received FDCAN message is not set */ +#define FDCAN_BRS_SET (FDCAN_PSR_RBRS) /* BSR flag of last received FDCAN message is set */ + +/** FDCAN protocol received a FDCAN message **/ +#define FDCAN_FDMSG_NOT_RECEIVED ((uint32_t)0x00000000U) /* Have not received any FDCAN message after CPU reset */ +#define FDCAN_FDMSG_RECEIVED (FDCAN_PSR_RFDF) /* Have received FDCAN message after CPU reset */ + +/** FDCAN protocol exception event **/ +#define FDCAN_NO_EXCEPTION ((uint32_t)0x00000000U) /* No protocol exception event occurred since last read access */ +#define FDCAN_HAVE_EXCEPTION (FDCAN_PSR_PXE) /* Protocol exception event occurred */ + +/** FDCAN FIFO operation mode, used for both Rx FIFO 0 and FIFO 1 **/ +#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /* Rx FIFO blocking mode */ +#define FDCAN_RX_FIFO_OVERWRITE (FDCAN_RXF0C_F0OM) /* Rx FIFO overwrite mode */ + +/** FDCAN non-matching frames **/ +#define FDCAN_ACCEPT_STD_IN_RX_FIFO0 ((uint32_t)0x00000000U) /* Accept Standard Frame in Rx FIFO 0 */ +#define FDCAN_ACCEPT_STD_IN_RX_FIFO1 (FDCAN_GFC_ANFS_0) /* Accept Standard Frame in Rx FIFO 1 */ +#define FDCAN_REJECT_STD (FDCAN_GFC_ANFS_1) /* Reject Standard Frame */ + +#define FDCAN_ACCEPT_EXT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /* Accept Extended Frame in Rx FIFO 0 */ +#define FDCAN_ACCEPT_EXT_IN_RX_FIFO1 (FDCAN_GFC_ANFE_0) /* Accept Extended Frame in Rx FIFO 1 */ +#define FDCAN_REJECT_EXT (FDCAN_GFC_ANFE_1) /* Reject Extended Frame */ + +/** FDCAN reject remote frames **/ +#define FDCAN_FILTER_STD_REMOTE ((uint32_t)0x00000000U) /* Filter Standard remote frames */ +#define FDCAN_REJECT_STD_REMOTE (FDCAN_GFC_RRFS) /* Reject all Standard remote frames */ +#define FDCAN_FILTER_EXT_REMOTE ((uint32_t)0x00000000U) /* Filter Extended remote frames */ +#define FDCAN_REJECT_EXT_REMOTE (FDCAN_GFC_RRFE) /* Reject all Extended remote frames */ + +/** FDCAN interrupt line **/ +#define FDCAN_INTERRUPT_LINE0 (FDCAN_ILE_EINT0) /* Interrupt Line 0 */ +#define FDCAN_INTERRUPT_LINE1 (FDCAN_ILE_EINT1) /* Interrupt Line 1 */ + +/** FDCAN timestamp select define **/ +#define FDCAN_TIMESTAMP_DISABLE (FDCAN_TSCC_CONSTANT) /* Timestamp counter value is always 0x0000 */ +#define FDCAN_TIMESTAMP_INTERNAL (FDCAN_TSCC_INC_TCP) /* Timestamp counter value incremented according to TCP */ +#define FDCAN_TIMESTAMP_EXTERNAL (FDCAN_TSCC_USE_EXT) /* External timestamp counter value used */ + +/** FDCAN internal timestamp prescaler define **/ +#define FDCAN_TIMESTAMP_PRESC_1 (FDCAN_TSCC_TCP_DIV1 ) /* Timestamp counter time unit in equal to CAN bit time */ +#define FDCAN_TIMESTAMP_PRESC_2 (FDCAN_TSCC_TCP_DIV2 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 (FDCAN_TSCC_TCP_DIV3 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 (FDCAN_TSCC_TCP_DIV4 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 (FDCAN_TSCC_TCP_DIV5 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 (FDCAN_TSCC_TCP_DIV6 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 (FDCAN_TSCC_TCP_DIV7 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 (FDCAN_TSCC_TCP_DIV8 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 (FDCAN_TSCC_TCP_DIV9 ) /* Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 (FDCAN_TSCC_TCP_DIV10) /* Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 (FDCAN_TSCC_TCP_DIV11) /* Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 (FDCAN_TSCC_TCP_DIV12) /* Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 (FDCAN_TSCC_TCP_DIV13) /* Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 (FDCAN_TSCC_TCP_DIV14) /* Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 (FDCAN_TSCC_TCP_DIV15) /* Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 (FDCAN_TSCC_TCP_DIV16) /* Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ + +/** FDCAN external timestamp clock divider define **/ +#define FDCAN_EXT_TIMESTAMP_DISABLE ((uint32_t)0x00000000U) /* Extenal timestamp clock disable */ +#define FDCAN_EXT_TIMESTAMP_ENABLE (FDCAN_TTSS_TS_EN) /* Extenal timestamp clock enable */ + +/** FDCAN external timestamp clock divider define **/ +#define FDCAN_EXT_TIMESTAMP_DIV_4 (FDCAN_TTSS_TS_SEL_DIV4 ) /* Extenal timestamp clock is PCLK divided by 4 */ +#define FDCAN_EXT_TIMESTAMP_DIV_8 (FDCAN_TTSS_TS_SEL_DIV8 ) /* Extenal timestamp clock is PCLK divided by 8 */ +#define FDCAN_EXT_TIMESTAMP_DIV_16 (FDCAN_TTSS_TS_SEL_DIV16 ) /* Extenal timestamp clock is PCLK divided by 16 */ +#define FDCAN_EXT_TIMESTAMP_DIV_32 (FDCAN_TTSS_TS_SEL_DIV32 ) /* Extenal timestamp clock is PCLK divided by 32 */ +#define FDCAN_EXT_TIMESTAMP_DIV_64 (FDCAN_TTSS_TS_SEL_DIV64 ) /* Extenal timestamp clock is PCLK divided by 64 */ +#define FDCAN_EXT_TIMESTAMP_DIV_128 (FDCAN_TTSS_TS_SEL_DIV128) /* Extenal timestamp clock is PCLK divided by 128 */ +#define FDCAN_EXT_TIMESTAMP_DIV_256 (FDCAN_TTSS_TS_SEL_DIV256) /* Extenal timestamp clock is PCLK divided by 256 */ +#define FDCAN_EXT_TIMESTAMP_DIV_512 (FDCAN_TTSS_TS_SEL_DIV512) /* Extenal timestamp clock is PCLK divided by 512 */ + +/** FDCAN timeout operation define **/ +#define FDCAN_TIMEOUT_CONTINUOUS (FDCAN_TOCC_TOS_CONTINUOUS ) /* Timeout continuous operation */ +#define FDCAN_TIMEOUT_TX_EVENT_FIFO (FDCAN_TOCC_TOS_TX_EVENT_FIFO) /* Timeout controlled by Tx Event FIFO */ +#define FDCAN_TIMEOUT_RX_FIFO0 (FDCAN_TOCC_TOS_RX_FIFO0 ) /* Timeout controlled by Rx FIFO 0 */ +#define FDCAN_TIMEOUT_RX_FIFO1 (FDCAN_TOCC_TOS_RX_FIFO1 ) /* Timeout controlled by Rx FIFO 1 */ + +/* FDCAN modify on read function define */ +#define FDCAN_ENABLE_MODIFY_ON_READ ((uint32_t)0x00000000U) /* Modify on read enable */ +#define FDCAN_DISABLE_MODIFY_ON_READ (FDCAN_TTSS_MRD) /* Modify on read disable */ + +/*** TT-CAN register define ***/ + +/** FDCAN TT reference message payload **/ +#define FDCAN_TT_REF_MSG_NO_PAYLOAD ((uint32_t)0x00000000U) /* Reference message has no additional payload */ +#define FDCAN_TT_REF_MSG_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /* Additional payload is taken from Tx Buffer 0 */ + +/** FDCAN Operation Mode **/ +#define FDCAN_TT_COMMUNICATION_LEVEL1 (FDCAN_TTOCF_OM_LEVEL1) /* Time triggered communication, level 1 */ +#define FDCAN_TT_COMMUNICATION_LEVEL2 (FDCAN_TTOCF_OM_LEVEL2) /* Time triggered communication, level 2 */ +#define FDCAN_TT_COMMUNICATION_LEVEL0 (FDCAN_TTOCF_OM_LEVEL0) /* Time triggered communication, level 0 */ + +/** FDCAN TT Operation **/ +#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /* Strictly time-triggered operation */ +#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /* External event-synchronized time-triggered operation */ + +/** FDCAN TT Time Master **/ +#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /* Time slave */ +#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /* Potential time master */ + +/** FDCAN TT External Clock Synchronization **/ +#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /* External clock synchronization in Level 0,2 disabled */ +#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /* External clock synchronization in Level 0,2 enabled */ + +/** FDCAN TT Global Time Filtering **/ +#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /* Global time filtering in Level 0,2 disabled */ +#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /* Global time filtering in Level 0,2 enabled */ + +/** FDCAN TT Automatic Clock Calibration **/ +#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /* Automatic clock calibration in Level 0,2 disabled */ +#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /* Automatic clock calibration in Level 0,2 enabled */ + +/**FDCAN TT Event Trigger Polarity **/ +#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /* Rising edge trigger */ +#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /* Falling edge trigger */ + +/** FDCAN TT Basic Cycle Number **/ +#define FDCAN_TT_CYCLES_PER_MATRIX_1 (FDCAN_TTMLM_CCM_NUM1 ) /* 1 Basic Cycle per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_2 (FDCAN_TTMLM_CCM_NUM2 ) /* 2 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_4 (FDCAN_TTMLM_CCM_NUM4 ) /* 4 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_8 (FDCAN_TTMLM_CCM_NUM8 ) /* 8 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_16 (FDCAN_TTMLM_CCM_NUM16) /* 16 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_32 (FDCAN_TTMLM_CCM_NUM32) /* 32 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_64 (FDCAN_TTMLM_CCM_NUM64) /* 64 Basic Cycles per Matrix */ + +/** FDCAN TT Cycle Start Sync **/ +#define FDCAN_TT_NO_SYNC_PULSE (FDCAN_TTMLM_CSS_NONE) /* No sync pulse */ +#define FDCAN_TT_SYNC_BASIC_CYCLE_START (FDCAN_TTMLM_CSS_BASIC ) /* Sync pulse at start of basic cycle */ +#define FDCAN_TT_SYNC_MATRIX_START (FDCAN_TTMLM_CSS_MATRIX) /* Sync pulse at start of matrix */ + +/** FDCAN TT Stop Watch Trigger Selection **/ +#define FDCAN_TT_STOP_WATCH_TRIGGER_0 (FDCAN_TTSS_SSWT_0) /* GTIMx selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_1 (FDCAN_TTSS_SSWT_1) /* GTIMx selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_2 (FDCAN_TTSS_SSWT_2) /* ETHx selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_3 (FDCAN_TTSS_SSWT_3) /* SHRTIMx selected as stop watch trigger */ + +/**FDCAN TT Event Trigger Selection **/ +#define FDCAN_TT_EVENT_TRIGGER_0 (FDCAN_TTSS_SEVT_0) /* GTIMx selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_1 (FDCAN_TTSS_SEVT_1) /* GTIMx selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_2 (FDCAN_TTSS_SEVT_2) /* ETHx selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_3 (FDCAN_TTSS_SEVT_3) /* SHRTIMx selected as event trigger */ + +/** FDCAN TT Stop Watch Source **/ +#define FDCAN_TT_STOP_WATCH_DISABLED (FDCAN_TTOCN_SWS_STOP) /* Stop Watch disabled */ +#define FDCAN_TT_STOP_WATCH_CYCLE_TIME (FDCAN_TTOCN_SWS_CYCLE ) /* Cycle time is copied to Capture Time register */ +#define FDCAN_TT_STOP_WATCH_LOCAL_TIME (FDCAN_TTOCN_SWS_LOCAL ) /* Local time is copied to Capture Time register */ +#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME (FDCAN_TTOCN_SWS_GLOBAL ) /* Global time is copied to Capture Time register */ + +/** FDCAN TT Stop Watch Polarity **/ +#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U)/* Stop watch source is captured at rising edge of fdcan1_swt */ +#define FDCAN_TT_STOP_WATCH_FALLING (FDCAN_TTOCN_SWP) /* Stop watch source is captured at falling edge of fdcan1_swt */ + +/** FDCAN TT Time Mark Source **/ +#define FDCAN_TT_REG_TIMEMARK_DIABLED (FDCAN_TTOCN_TMC_NONE) /* No Register Time Mark Interrupt generated */ +#define FDCAN_TT_REG_TIMEMARK_CYCLE_TIME (FDCAN_TTOCN_TMC_BASIC ) /* Register Time Mark Interrupt if Time Mark = cycle time */ +#define FDCAN_TT_REG_TIMEMARK_LOCAL_TIME (FDCAN_TTOCN_TMC_LOCAL ) /* Register Time Mark Interrupt if Time Mark = local time */ +#define FDCAN_TT_REG_TIMEMARK_GLOBAL_TIME (FDCAN_TTOCN_TMC_GLOBAL ) /* Register Time Mark Interrupt if Time Mark = global time */ + +/** FDCAN TT Error Level **/ +#define FDCAN_TT_NO_ERROR (FDCAN_TTOST_EL_S0) /* Severity 0 - No Error */ +#define FDCAN_TT_WARNING (FDCAN_TTOST_EL_S1) /* Severity 1 - Warning */ +#define FDCAN_TT_ERROR (FDCAN_TTOST_EL_S2) /* Severity 2 - Error */ +#define FDCAN_TT_SEVERE_ERROR (FDCAN_TTOST_EL_S3) /* Severity 3 - Severe Error */ + +/** FDCAN TT Master State **/ +#define FDCAN_TT_MASTER_OFF (FDCAN_TTOST_MS_NONE ) /* Master_Off, no master properties relevant */ +#define FDCAN_TT_TIME_SLAVE (FDCAN_TTOST_MS_SLAVE ) /* Operating as Time Slave */ +#define FDCAN_TT_BACKUP_TIME_MASTER (FDCAN_TTOST_MS_BACKUP ) /* Operating as Backup Time Master */ +#define FDCAN_TT_CURRENT_TIME_MASTER (FDCAN_TTOST_MS_CURRENT) /* Operating as current Time Master */ + +/** FDCAN TT Synchronization State **/ +#define FDCAN_TT_OUT_OF_SYNC (FDCAN_TTOST_SYS_NONE ) /* Out of Synchronization */ +#define FDCAN_TT_SYNCHRONIZING (FDCAN_TTOST_SYS_SYNC ) /* Synchronizing to communication */ +#define FDCAN_TT_IN_GAP (FDCAN_TTOST_SYS_IN_GAP ) /* Schedule suspended by Gap */ +#define FDCAN_TT_IN_SCHEDULE (FDCAN_TTOST_SYS_IN_SCHEDULE) /* Synchronized to schedule */ + +/** FDCAN TT Quality of global time phase. **/ +#define FDCAN_TT_GTIME_NOT_VALID ((uint32_t)0x00000000U) /* Global time not valid */ +#define FDCAN_TT_GTIME_IN_MASTER_PHASE (FDCAN_TTOST_QGTP ) /* Global time in phase with Time Master */ + +/** FDCAN TT Quality of clock Speed **/ +#define FDCAN_TT_LOCAL_CLOCK_NOT_SYNC ((uint32_t)0x00000000U) /* Local clock speed not synchronized to Time Master clock speed */ +#define FDCAN_TT_SYNC_DEV_LESS_THAN_SDL (FDCAN_TTOST_QCS ) /* Synchronization Deviation <= SDL */ + +/** FDCAN TT Wait for global time discontinuity **/ +#define FDCAN_TT_NO_GTIME_PENDING ((uint32_t)0x00000000U) /* No global time preset pending */ +#define FDCAN_TT_WATI_GTIMESYNC_PRESENT (FDCAN_TTOST_WGTD ) /* Node waits for the global time preset to take effect */ + +/** FDCAN TT Gap finished Indicator **/ +#define FDCAN_TT_GAP_RESET ((uint32_t)0x00000000U) /* Reset at the end of each reference message */ +#define FDCAN_TT_GAP_FINISHED (FDCAN_TTOST_GFI ) /* Gap finished by FDCAN */ + +/** FDCAN TT Gap started Indicator **/ +#define FDCAN_TT_NO_GAP ((uint32_t)0x00000000U) /* No Gap in schedule */ +#define FDCAN_TT_GAP_STARTED (FDCAN_TTOST_GSI ) /* Gap time after basic cycle has started */ + +/** FDCAN TT Wait for event **/ +#define FDCAN_TT_GAP_NOT_ANNOUNCED ((uint32_t)0x00000000U) /* No Gap announced */ +#define FDCAN_TT_REF_MSG_RECEIVED (FDCAN_TTOST_WFE ) /* Reference message with Next_is_Gap = 1 received */ + +/** FDCAN TT Application watchdog event. **/ +#define FDCAN_TT_WATCHDOG_VALID ((uint32_t)0x00000000U) /* Application watchdog served in time */ +#define FDCAN_TT_WATCHDOG_INVALID (FDCAN_TTOST_AWE ) /* Failed to serve application watchdog in time */ + +/** FDCAN TT Wait for external clock synchronization **/ +#define FDCAN_TT_NO_EXT_CLOCK_SYNC ((uint32_t)0x00000000U) /* No external clock synchronization pending. */ +#define FDCAN_TT_WAIT_EXT_CLOCK_SYNC (FDCAN_TTOST_WECS ) /* Node waits for external clock synchronization to take effect. */ + +/** FDCAN TT Schedule phase lock. **/ +#define FDCAN_TT_PHASE_OUT_OF_RANGE ((uint32_t)0x00000000U) /* Phase outside range. */ +#define FDCAN_TT_PHASE_IN_RANGE (FDCAN_TTOST_SPL ) /* Phase inside range. */ + +/** FDCAN Interrupt masks **/ +#define FDCAN_INT_MASK ((uint32_t)0x3FFFFFFFU)/* FDCAN interrupts mask */ + +/** FDCAN Flags **/ +#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS (FDCAN_IR_ARA ) /* Access to reserved address occurred */ +#define FDCAN_FLAG_DATA_PROTOCOL_ERROR (FDCAN_IR_PED ) /* Protocol error in data phase detected */ +#define FDCAN_FLAG_ARB_PROTOCOL_ERROR (FDCAN_IR_PEA ) /* Protocol error in arbitration phase detected */ +#define FDCAN_FLAG_RAM_WATCHDOG (FDCAN_IR_WDI ) /* Message RAM Watchdog event due to missing READY */ +#define FDCAN_FLAG_BUS_OFF (FDCAN_IR_BO ) /* Bus_Off status changed */ +#define FDCAN_FLAG_ERROR_WARNING (FDCAN_IR_EW ) /* Error_Warning status changed */ +#define FDCAN_FLAG_ERROR_PASSIVE (FDCAN_IR_EP ) /* Error_Passive status changed */ +#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW (FDCAN_IR_ELO ) /* Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_FLAG_BITERROR_CORRECTED (FDCAN_IR_BEC ) /* Bit Error Corrected */ +#define FDCAN_FLAG_BITERROR_UNCORRECTED (FDCAN_IR_BEU ) /* Bit Error Uncorrected */ +#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE (FDCAN_IR_DRX ) /* At least one received message stored into a Rx Buffer */ +#define FDCAN_FLAG_TIMEOUT_OCCURRED (FDCAN_IR_TOO ) /* Timeout reached */ +#define FDCAN_FLAG_RAM_ACCESS_FAILURE (FDCAN_IR_MRAF) /* Message RAM access failure occurred */ +#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND (FDCAN_IR_TSW ) /* Timestamp counter wrapped around */ +#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST (FDCAN_IR_TEFL) /* Tx Event FIFO element lost */ +#define FDCAN_FLAG_TX_EVT_FIFO_FULL (FDCAN_IR_TEFF) /* Tx Event FIFO full */ +#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK (FDCAN_IR_TEFW) /* Tx Event FIFO fill level reached watermark */ +#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA (FDCAN_IR_TEFN) /* Tx Handler wrote Tx Event FIFO element */ +#define FDCAN_FLAG_TX_FIFO_EMPTY (FDCAN_IR_TFE ) /* Tx FIFO Empty */ +#define FDCAN_FLAG_TX_ABORT_COMPLETE (FDCAN_IR_TCF ) /* Transmission Cancellation Finished */ +#define FDCAN_FLAG_TX_COMPLETE (FDCAN_IR_TC ) /* Transmission Completed */ +#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG (FDCAN_IR_HPM ) /* High priority message received */ +#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST (FDCAN_IR_RF1L) /* Rx FIFO 1 message lost */ +#define FDCAN_FLAG_RX_FIFO1_FULL (FDCAN_IR_RF1F) /* Rx FIFO 1 full */ +#define FDCAN_FLAG_RX_FIFO1_WATERMARK (FDCAN_IR_RF1W) /* Rx FIFO 1 fill level reached watermark */ +#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE (FDCAN_IR_RF1N) /* New message written to Rx FIFO 1 */ +#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST (FDCAN_IR_RF0L) /* Rx FIFO 0 message lost */ +#define FDCAN_FLAG_RX_FIFO0_FULL (FDCAN_IR_RF0F) /* Rx FIFO 0 full */ +#define FDCAN_FLAG_RX_FIFO0_WATERMARK (FDCAN_IR_RF0W) /* Rx FIFO 0 fill level reached watermark */ +#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE (FDCAN_IR_RF0N) /* New message written to Rx FIFO 0 */ + +/** FDCAN Tx Interrupts **/ +#define FDCAN_INT_TX_COMPLETE (FDCAN_IE_TCE ) /* Transmission Completed */ +#define FDCAN_INT_TX_ABORT_COMPLETE (FDCAN_IE_TCFE) /* Transmission Cancellation Finished */ +#define FDCAN_INT_TX_FIFO_EMPTY (FDCAN_IE_TFEE) /* Tx FIFO Empty */ + +/**FDCAN Rx Interrupts **/ +#define FDCAN_INT_RX_HIGH_PRIORITY_MSG (FDCAN_IE_HPME) /* High priority message received */ +#define FDCAN_INT_RX_BUFFER_NEW_MESSAGE (FDCAN_IE_DRXE) /* At least one received message stored into a Rx Buffer */ + +/** FDCAN Counter Interrupts **/ +#define FDCAN_INT_TIMESTAMP_WRAPAROUND (FDCAN_IE_TSWE) /* Timestamp counter wrapped around */ +#define FDCAN_INT_TIMEOUT_OCCURRED (FDCAN_IE_TOOE) /* Timeout reached */ + +/** FDCAN Tx Event FIFO Interrupts **/ +#define FDCAN_INT_TX_EVT_FIFO_ELT_LOST (FDCAN_IE_TEFLE) /* Tx Event FIFO element lost */ +#define FDCAN_INT_TX_EVT_FIFO_FULL (FDCAN_IE_TEFFE) /* Tx Event FIFO full */ +#define FDCAN_INT_TX_EVT_FIFO_WATERMARK (FDCAN_IE_TEFWE) /* Tx Event FIFO fill level reached watermark */ +#define FDCAN_INT_TX_EVT_FIFO_NEW_DATA (FDCAN_IE_TEFNE) /* Tx Handler wrote Tx Event FIFO element */ + +/** FDCAN Rx FIFO 0 Interrupts **/ +#define FDCAN_INT_RX_FIFO0_MESSAGE_LOST (FDCAN_IE_RF0LE) /* Rx FIFO 0 message lost */ +#define FDCAN_INT_RX_FIFO0_FULL (FDCAN_IE_RF0FE) /* Rx FIFO 0 full */ +#define FDCAN_INT_RX_FIFO0_WATERMARK (FDCAN_IE_RF0WE) /* Rx FIFO 0 fill level reached watermark */ +#define FDCAN_INT_RX_FIFO0_NEW_MESSAGE (FDCAN_IE_RF0NE) /* New message written to Rx FIFO 0 */ + +/** FDCAN Rx FIFO 1 Interrupts **/ +#define FDCAN_INT_RX_FIFO1_MESSAGE_LOST (FDCAN_IE_RF1LE) /* Rx FIFO 1 message lost */ +#define FDCAN_INT_RX_FIFO1_FULL (FDCAN_IE_RF1FE) /* Rx FIFO 1 full */ +#define FDCAN_INT_RX_FIFO1_WATERMARK (FDCAN_IE_RF1WE) /* Rx FIFO 1 fill level reached watermark */ +#define FDCAN_INT_RX_FIFO1_NEW_MESSAGE (FDCAN_IE_RF1NE) /* New message written to Rx FIFO 1 */ + +/** FDCAN Error Interrupts **/ +#define FDCAN_INT_RAM_ACCESS_FAILURE (FDCAN_IE_MRAFE) /* Message RAM access failure occurred */ +#define FDCAN_INT_ERROR_LOGGING_OVERFLOW (FDCAN_IE_ELOE ) /* Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_INT_RAM_WATCHDOG (FDCAN_IE_WDIE ) /* Message RAM Watchdog event due to missing READY */ +#define FDCAN_INT_ARB_PROTOCOL_ERROR (FDCAN_IE_PEAE ) /* Protocol error in arbitration phase detected */ +#define FDCAN_INT_DATA_PROTOCOL_ERROR (FDCAN_IE_PEDE ) /* Protocol error in data phase detected */ +#define FDCAN_INT_RESERVED_ADDRESS_ACCESS (FDCAN_IE_ARAE ) /* Access to reserved address occurred */ + +/** FDCAN Error Status Interrupts **/ +#define FDCAN_INT_ERROR_PASSIVE (FDCAN_IE_EPE) /* Error_Passive status changed */ +#define FDCAN_INT_ERROR_WARNING (FDCAN_IE_EWE) /* Error_Warning status changed */ +#define FDCAN_INT_BUS_OFF (FDCAN_IE_BOE) /* Bus_Off status changed */ + +/** SRAM Bit Error Status Interrupts **/ +#define FDCAN_INT_BITERROR_CORRECTED (FDCAN_IE_BECE) /* Bit Error Corrected */ +#define FDCAN_INT_BITERROR_UNCORRECTED (FDCAN_IE_BEUE) /* Bit Error Uncorrected */ + +/** FDCAN TT Interrupt masks **/ +#define FDCAN_TT_INT_MASK ((uint32_t)0x0007FFFFU) /* FDCAN TT interrupts mask */ + +/** FDCAN TT Flags **/ +#define FDCAN_TT_FLAG_BASIC_CYCLE_START (FDCAN_TTIR_SBC ) /* Start of Basic Cycle */ +#define FDCAN_TT_FLAG_MATRIX_CYCLE_START (FDCAN_TTIR_SMC ) /* Start of Matrix Cycle */ +#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE (FDCAN_TTIR_CSM ) /* Change of Synchronization Mode */ +#define FDCAN_TT_FLAG_START_OF_GAP (FDCAN_TTIR_SOG ) /* Start of Gap */ +#define FDCAN_TT_FLAG_REG_TIME_MARK (FDCAN_TTIR_RTMI) /* Register Time Mark Interrupt */ +#define FDCAN_TT_FLAG_TRIG_TIME_MARK (FDCAN_TTIR_TTMI) /* Trigger Time Mark Event Internal */ +#define FDCAN_TT_FLAG_STOP_WATCH (FDCAN_TTIR_SWE ) /* Stop Watch Event */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP (FDCAN_TTIR_GTW ) /* Global Time Wrap */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC (FDCAN_TTIR_GTD ) /* Global Time Discontinuity */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR (FDCAN_TTIR_GTE ) /* Global Time Error */ +#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW (FDCAN_TTIR_TXU ) /* Tx Count Underflow */ +#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW (FDCAN_TTIR_TXO ) /* Tx Count Overflow */ +#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 (FDCAN_TTIR_SE1 ) /* Scheduling Error 1 */ +#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 (FDCAN_TTIR_SE2 ) /* Scheduling Error 2 */ +#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE (FDCAN_TTIR_ELC ) /* Error Level Changed */ +#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER (FDCAN_TTIR_IWT ) /* Initialization Watch Trigger */ +#define FDCAN_TT_FLAG_WATCH_TRIGGER (FDCAN_TTIR_WT ) /* Watch Trigger */ +#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG (FDCAN_TTIR_AW ) /* Application Watchdog */ +#define FDCAN_TT_FLAG_CONFIG_ERROR (FDCAN_TTIR_CER ) /* Configuration Error */ + +/** FDCAN TT Schedule Synchronization Interrupts **/ +#define FDCAN_TT_INT_BASIC_CYCLE_START (FDCAN_TTIE_SBCE) /* Start of Basic Cycle */ +#define FDCAN_TT_INT_MATRIX_CYCLE_START (FDCAN_TTIE_SMCE) /* Start of Matrix Cycle */ +#define FDCAN_TT_INT_SYNC_MODE_CHANGE (FDCAN_TTIE_CSME) /* Change of Synchronization Mode */ +#define FDCAN_TT_INT_START_OF_GAP (FDCAN_TTIE_SOGE) /* Start of Gap */ + +/** FDCAN TT Time Mark Interrupts **/ +#define FDCAN_TT_INT_REG_TIME_MARK (FDCAN_TTIE_RTMIE) /* Register Time Mark Interrupt */ +#define FDCAN_TT_INT_TRIG_TIME_MARK (FDCAN_TTIE_TTMIE) /* Trigger Time Mark Event Internal */ + +/** FDCAN TT Stop Watch Interrupt **/ +#define FDCAN_TT_INT_STOP_WATCH (FDCAN_TTIE_SWEE) /* Stop Watch Event */ + +/** FDCAN TT Global Time Interrupts **/ +#define FDCAN_TT_INT_GLOBAL_TIME_WRAP (FDCAN_TTIE_GTWE) /* Global Time Wrap */ +#define FDCAN_TT_INT_GLOBAL_TIME_DISC (FDCAN_TTIE_GTDE) /* Global Time Discontinuity */ + +/** FDCAN TT Disturbing Error Interrupts **/ +#define FDCAN_TT_INT_GLOBAL_TIME_ERROR (FDCAN_TTIE_GTEE) /* Global Time Error */ +#define FDCAN_TT_INT_TX_COUNT_UNDERFLOW (FDCAN_TTIE_TXUE) /* Tx Count Underflow */ +#define FDCAN_TT_INT_TX_COUNT_OVERFLOW (FDCAN_TTIE_TXOE) /* Tx Count Overflow */ +#define FDCAN_TT_INT_SCHEDULING_ERROR_1 (FDCAN_TTIE_SE1E) /* Scheduling Error 1 */ +#define FDCAN_TT_INT_SCHEDULING_ERROR_2 (FDCAN_TTIE_SE2E) /* Scheduling Error 2 */ +#define FDCAN_TT_INT_ERROR_LEVEL_CHANGE (FDCAN_TTIE_ELCE) /* Error Level Changed */ + +/** FDCAN TT Fatal Error Interrupts **/ +#define FDCAN_TT_INT_INIT_WATCH_TRIGGER (FDCAN_TTIE_IWTE) /* Initialization Watch Trigger */ +#define FDCAN_TT_INT_WATCH_TRIGGER (FDCAN_TTIE_WTE ) /* Watch Trigger */ +#define FDCAN_TT_INT_APPLICATION_WATCHDOG (FDCAN_TTIE_AWE ) /* Application Watchdog */ +#define FDCAN_TT_INT_CONFIG_ERROR (FDCAN_TTIE_CERE) /* Configuration Error */ + +/*** Registers bit offset define ***/ + +/** FDCAN DBTP register bit offset define **/ +#define FDCAN_DBTP_DTSEG2_OFFSET (REG_BIT4_OFFSET) /* Date time segment after sample point */ +#define FDCAN_DBTP_DTSEG1_OFFSET (REG_BIT8_OFFSET) /* Date time segment before sample point */ +#define FDCAN_DBTP_DBRP_OFFSET (REG_BIT16_OFFSET) /* Date Bit Rate Prescaler */ +#define FDCAN_DBTP_DSJW_OFFSET (REG_BIT0_OFFSET) /* Date (Re)Synchronization Jump Width */ + +/** FDCAN NBTP register bit offset define **/ +#define FDCAN_NBTP_NTSEG2_OFFSET (REG_BIT0_OFFSET) /* Nominal time segment after sample point */ +#define FDCAN_NBTP_NTSEG1_OFFSET (REG_BIT8_OFFSET) /* Nominal time segment before sample point */ +#define FDCAN_NBTP_NBRP_OFFSET (REG_BIT16_OFFSET) /* Nominal Bit Rate Prescaler */ +#define FDCAN_NBTP_NSJW_OFFSET (REG_BIT25_OFFSET) /* Nominal (Re)Synchronization Jump Width */ + +/** FDCAN TOCC register bit offset define **/ +#define FDCAN_TOCC_TOP_OFFSET (REG_BIT16_OFFSET) /* Timeout Period */ + +/** FDCAN ECR register bit offset define **/ +#define FDCAN_ECR_REC_OFFSET (REG_BIT8_OFFSET) /* Receive Error Counter */ +#define FDCAN_ECR_CEL_OFFSET (REG_BIT16_OFFSET) /* FDCAN Error Logging*/ + +/** FDCAN PSR register bit offset define **/ +#define FDCAN_PSR_TDCV_OFFSET (REG_BIT16_OFFSET) /* FDCAN Transmitter Delay Compensation Value */ + +/** FDCAN TDCR register bit offset define **/ +#define FDCAN_TDCR_TDCO_OFFSET (REG_BIT8_OFFSET) /* ransmitter Delay Compensation SSP Offset */ + +/** FDCAN HPMS register bit offset define **/ +#define FDCAN_HPMS_FIDX_OFFSET (REG_BIT8_OFFSET) /* Filter Index */ + +/** FDCAN RXESC register bit offset define **/ +#define FDCAN_RXESC_F0DS_OFFSET (REG_BIT0_OFFSET ) /* FDCAN Rx FIFO 0 element size */ +#define FDCAN_RXESC_F1DS_OFFSET (REG_BIT4_OFFSET ) /* FDCAN Rx FIFO 1 element size */ +#define FDCAN_RXESC_RBDS_OFFSET (REG_BIT8_OFFSET ) /* FDCAN Rx Buffer element size */ + +/** FDCAN RXF0C/RXF1C register bit offset define **/ +#define FDCAN_RXFXC_FXWM_OFFSET (REG_BIT24_OFFSET ) /* FDCAN Rx FIFO 0/1 watermark */ + +/** FDCAN RXF0C/RXF1C register bit offset define **/ +#define FDCAN_RXFXS_FXGI_OFFSET (REG_BIT8_OFFSET ) /* FDCAN Rx FIFO 0/1 Get Index */ + +/** FDCAN start address and size bit offset define, used for: + - Standard filter list + - Extended filter list + - Rx FIFO0 + - Rx FIFO1 + - Rx buffer + - Tx event FIFO + - Tx buffer + - Trigger Memory + **/ +#define FDCAN_START_ADDRESS_OFFSET (REG_BIT2_OFFSET) /* Start address */ +#define FDCAN_SIZE_NUMBER_OFFSET (REG_BIT16_OFFSET) /* Number of elements */ + +/** FDCAN TXBC register bit offset define **/ +#define FDCAN_TXBC_TFQS_OFFSET (REG_BIT24_OFFSET) /* Tx FIFO/queue elements number */ +#define FDCAN_TXBC_NDTB_OFFSET (REG_BIT16_OFFSET) /* Number of Dedicated Transmit Buffers */ + +/** FDCAN TXFQS register bit offset define **/ +#define FDCAN_TXFQS_TFQPI_OFFSET (REG_BIT16_OFFSET) /* Tx FIFO/Queue Put Index */ + +/** FDCAN TXEFS register bit offset define **/ +#define FDCAN_TXEFS_EFGI_OFFSET (REG_BIT8_OFFSET) /** FDCAN Tx event fifo get index */ + +/* FDCAN start address SRAM5 BANK select */ +#define FDCAN_START_ADDRESS_SRAM5BANK1 ((uint32_t)0x30050000U) /* Select SRAM5 BANK1: 0x30050000 as FDCAN base address. */ +#define FDCAN_START_ADDRESS_SRAM5BANK2 ((uint32_t)0x30054000U) /* Select SRAM5 BANK2: 0x30054000 as FDCAN base address. */ +#define FDCAN_START_ADDRESS_RAMSEL (FDCAN_TTSS_RAMSEL) /* Message RAM select. */ +/** FDCAN TTRMC register bit offset define **/ +#define FDCAN_TTRMC_STD_ID_OFFSET (REG_BIT18_OFFSET) /* TT Standard Reference Identifier */ + +/** FDCAN TTOCF register bit offset define **/ +#define FDCAN_TTOCF_LDSDL_OFFSET (REG_BIT5_OFFSET) /* TT LD of Synchronization Deviation Limit */ +#define FDCAN_TTOCF_IRTO_OFFSET (REG_BIT8_OFFSET) /* TT Initial Reference Trigger Offset*/ +#define FDCAN_TTOCF_AWL_OFFSET (REG_BIT16_OFFSET) /* TT Application Watchdog Limit */ + +/** FDCAN TTMLM register bit offset define **/ +#define FDCAN_TTMLM_TXEW_OFFSET (REG_BIT8_OFFSET) /* TT Tx Enable Window */ +#define FDCAN_TTMLM_ENIT_OFFSET (REG_BIT16_OFFSET) /* TT Expected Number of Tx Triggers */ + +/** FDCAN TURCF register bit offset define **/ +#define FDCAN_TURCF_DC_OFFSET (REG_BIT16_OFFSET) /* TT Time Unit Ratio */ + +/** FDCAN TTGTP register bit offset define **/ +#define FDCAN_TTGTP_CTP_OFFSET (REG_BIT16_OFFSET) /* TT Cycle Time Target Phase */ + +/** FDCAN TTTMK register bit offset define **/ +#define FDCAN_TTTMK_TICC_OFFSET (REG_BIT16_OFFSET) /* TT Time Mark Cycle Code */ + +/** FDCAN TTOST register bit offset define **/ +#define FDCAN_TTOST_RTO_OFFSET (REG_BIT8_OFFSET) /* TT Reference trigger offset */ +#define FDCAN_TTOST_TMP_OFFSET (REG_BIT24_OFFSET) /* TT Time master priority */ +/** Variable declaration **/ +extern FDCAN_MsgRamType FDCAN_MsgRam; + +/** Function declaration **/ +void FDCAN_DeInit(FDCAN_Module* FDCANx); +ErrorStatus FDCAN_Init(FDCAN_Module* FDCANx, FDCAN_InitType *FDCAN_InitParam); +ErrorStatus FDCAN_EnterSleep(FDCAN_Module *FDCANx); +ErrorStatus FDCAN_ExitSleep(FDCAN_Module *FDCANx); +void FDCAN_EnableISOMode(FDCAN_Module *FDCANx); +void FDCAN_DisableISOMode(FDCAN_Module *FDCANx); +void FDCAN_EnableEdgeFilter(FDCAN_Module *FDCANx); +void FDCAN_DisableEdgeFilter(FDCAN_Module *FDCANx); +void FDCAN_Start(FDCAN_Module *FDCANx); +ErrorStatus FDCAN_Stop(FDCAN_Module *FDCANx); +void FDCAN_GetProtocolStatus(FDCAN_Module *FDCANx, FDCAN_ProtocolStatus *ProtocolStatus); +void FDCAN_GetErrorCounters(FDCAN_Module *FDCANx, FDCAN_ErrorCounters *ErrorCounters); +void FDCAN_ConfigRamWatchdog(FDCAN_Module *FDCANx, uint32_t Value); +uint32_t FDCAN_CheckRestrictedMode(FDCAN_Module *FDCANx); +void FDCAN_ExitRestrictedMode(FDCAN_Module *FDCANx); + +void FDCAN_ConfigFilter(FDCAN_Module *FDCANx, FDCAN_FilterType *sFilterConfig); +void FDCAN_ConfigGlobalFilter(FDCAN_Module *FDCANx, + uint32_t NonMatchingStd, + uint32_t NonMatchingExt, + uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt); +void FDCAN_ConfigExtIdMask(FDCAN_Module *FDCANx, uint32_t Mask); + + +void FDCAN_ConfigRxFifoMode(FDCAN_Module *FDCANx, uint32_t RxFifo, uint32_t Mode); +void FDCAN_ConfigFifoWatermark(FDCAN_Module *FDCANx, uint32_t FIFO, uint32_t Watermark); +uint32_t FDCAN_GetRxFifoFillLevel(FDCAN_Module *FDCANx, uint32_t RxFifo); + +ErrorStatus FDCAN_GetRxMsg(FDCAN_Module *FDCANx, uint32_t RxLocation, FDCAN_RxHeaderType *pRxHeader, uint8_t *pRxData); +void FDCAN_GetHpMsgStatus(FDCAN_Module *FDCANx, FDCAN_HpMsgStatus *HpMsgStatus); +ErrorStatus FDCAN_CheckNewRxBufMsg(FDCAN_Module *FDCANx, uint32_t Index); + +void FDCAN_ConfigTSPrescaler(FDCAN_Module *FDCANx, uint32_t Prescaler); +void FDCAN_Config_TS(FDCAN_Module *FDCANx, uint32_t Select); +uint16_t FDCAN_Get_TS(FDCAN_Module *FDCANx); +void FDCAN_Reset_TS(FDCAN_Module *FDCANx); +void FDCAN_ConfigExtTSDivider(FDCAN_Module *FDCANx, uint32_t Div); +void FDCAN_EnableExtTS(FDCAN_Module *FDCANx, FunctionalState Cmd); +void FDCAN_ConfigTimeoutCounter(FDCAN_Module *FDCANx, uint32_t TimeoutSelect, uint32_t TimeoutPeriod); +void FDCAN_EnableTimeoutCounter(FDCAN_Module *FDCANx); +void FDCAN_DisableTimeoutCounter(FDCAN_Module *FDCANx); +uint16_t FDCAN_GetTimeoutCounter(FDCAN_Module *FDCANx); +void FDCAN_ResetTimeoutCounter(FDCAN_Module *FDCANx); + +void FDCAN_ConfigTxDelayCompensation(FDCAN_Module *FDCANx, uint32_t Offset, uint32_t Filter); +void FDCAN_EnableTxDelayCompensation(FDCAN_Module *FDCANx); +void FDCAN_DisableTxDelayCompensation(FDCAN_Module *FDCANx); + +ErrorStatus FDCAN_AddMsgToTxFifoQ(FDCAN_Module *FDCANx, FDCAN_TxHeaderType *pTxHeader, uint8_t *pTxData); +ErrorStatus FDCAN_AddMsgToTxBuffer(FDCAN_Module *FDCANx, FDCAN_TxHeaderType *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); +void FDCAN_EnableTxBufferRequest(FDCAN_Module *FDCANx, uint32_t BufferIndex); +uint32_t FDCAN_GetLastTxFifoQReqBuf(FDCAN_Module *FDCANx); +void FDCAN_AbortTxRequest(FDCAN_Module *FDCANx, uint32_t BufferIndex); +ErrorStatus FDCAN_GetTxEvent(FDCAN_Module *FDCANx, FDCAN_TxEventFifoType *pTxEvent); +FlagStatus FDCAN_CheckTxBufRequest(FDCAN_Module *FDCANx, uint32_t IndexBit); +FlagStatus FDCAN_CheckBufTxResult(FDCAN_Module *FDCANx, uint32_t IndexBit); +FlagStatus FDCAN_CheckBufTxCancel(FDCAN_Module *FDCANx, uint32_t IndexBit); +uint32_t FDCAN_GetTxFifoFreeLevel(FDCAN_Module *FDCANx); + +ErrorStatus FDCAN_TT_Init(FDCAN_Module *FDCANx, FDCAN_TT_InitType *pTTParams); +void FDCAN_TT_ConfigRefMsg(FDCAN_Module *FDCANx, uint32_t IdType, uint32_t ID, uint32_t Payload); +void FDCAN_TT_ConfigTrigger(FDCAN_Module *FDCANx, FDCAN_TriggerType *sTriggerConfig); +ErrorStatus FDCAN_TT_SetGlobalTime(FDCAN_Module *FDCANx, uint32_t TimePreset); +ErrorStatus FDCAN_TT_SetClockSync(FDCAN_Module *FDCANx, uint32_t NewTURNumerator); +ErrorStatus FDCAN_TT_ConfigStopWatch(FDCAN_Module *FDCANx, uint32_t Source, uint32_t Polarity); +ErrorStatus FDCAN_TT_ConfigRegTimeMark(FDCAN_Module *FDCANx, + uint32_t TimeMarkSource, uint32_t TimeMarkValue, + uint32_t RepeatFactor, uint32_t StartCycle); +ErrorStatus FDCAN_TT_EnableRegTMPulse(FDCAN_Module *FDCANx, FunctionalState Cmd); +ErrorStatus FDCAN_TT_EnableTrigTMPulse(FDCAN_Module *FDCANx, FunctionalState Cmd); +ErrorStatus FDCAN_TT_EnableGapPinCtrl(FDCAN_Module *FDCANx, FunctionalState Cmd); +ErrorStatus FDCAN_TT_EnableTMGapCtrl(FDCAN_Module *FDCANx, FunctionalState Cmd); +ErrorStatus FDCAN_TT_SetNextIsGap(FDCAN_Module *FDCANx); +ErrorStatus FDCAN_TT_SetEndOfGap(FDCAN_Module *FDCANx); +ErrorStatus FDCAN_TT_ConfigExtSyncPhase(FDCAN_Module *FDCANx, uint32_t TargetPhase); +ErrorStatus FDCAN_TT_EnableExtSync(FDCAN_Module *FDCANx, FunctionalState Cmd); +void FDCAN_TT_GetStatus(FDCAN_Module *FDCANx, FDCAN_TT_Status *TTStatus); + +FlagStatus FDCAN_GetFlag(FDCAN_Module *FDCANx, uint32_t Flag); +void FDCAN_ClearFlag(FDCAN_Module *FDCANx, uint32_t Flag); +void FDCAN_ConfigIntLine(FDCAN_Module *FDCANx, uint32_t Int, uint32_t IntLine); +void FDCAN_EnableInt(FDCAN_Module *FDCANx, uint32_t Int); +void FDCAN_DisableInt(FDCAN_Module *FDCANx, uint32_t Int); +FlagStatus FDCAN_GetIntFlag(FDCAN_Module *FDCANx, uint32_t Flag); +ErrorStatus FDCAN_ActivateInt(FDCAN_Module *FDCANx, uint32_t Int, uint32_t BufferIndexes); +void FDCAN_DeactivateInt(FDCAN_Module *FDCANx, uint32_t Int); + +FlagStatus FDCAN_TT_GetIntFlag(FDCAN_Module *FDCANx, uint32_t TT_Flag); +FlagStatus FDCAN_TT_GetFlag(FDCAN_Module *FDCANx, uint32_t TT_Flag); +void FDCAN_TT_ClearFlag(FDCAN_Module *FDCANx, uint32_t TT_Flag); +void FDCAN_TT_ConfigIntLine(FDCAN_Module *FDCANx, uint32_t TT_Int, uint32_t IntLine); +void FDCAN_TT_EnableInt(FDCAN_Module *FDCANx, uint32_t TT_Int, FunctionalState Cmd); +void FDCAN_TT_DisableInt(FDCAN_Module *FDCANx, uint32_t TT_Int); +FlagStatus FDCAN_TT_GetInt(FDCAN_Module *FDCANx, uint32_t TT_Flag); +ErrorStatus FDCAN_TT_ActivateInt(FDCAN_Module *FDCANx, uint32_t TT_Int); +void FDCAN_TT_DeactivateInt(FDCAN_Module *FDCANx, uint32_t TT_Int); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_FDCAN_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_femc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_femc.h new file mode 100644 index 0000000000..cb23e4896e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_femc.h @@ -0,0 +1,372 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_femc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_FEMC_H__ +#define __N32H76X_78X_FEMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + + +/** Timing parameters **/ +typedef struct +{ + uint32_t Trc; /* Defines the RC in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + + uint32_t Twc; /* Defines the WC in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + + uint32_t Tcere; /* Defines the CEOE or REA in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t Twp; /* Defines the WP in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t Tpcclr; /* Defines the PC OR CLR in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t Ttrar; /* Defines the TR or AR in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t Twerr; /* Defines the WE or RR in memory clock cycles. This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + +} FEMC_TimingInitType; + +/** FEMC Chip Init structure definition **/ +typedef struct +{ + uint32_t ReadSyncMode; /* Defines the read sync enable. This parameter can be a value of @ref FEMC_Memory_Read_Mode */ + + uint32_t WriteSyncMode; /* Defines the write sync enable. This parameter can be a value of @ref FEMC_Memory_Write_Mode */ + + uint32_t ReadBurstLen; /* Defines the number of read data access. This parameter can be a value of @ref FEMC_Memory_Read_Burst_Length. */ + + uint32_t WriteBurstLen; /* Defines the number of write data access. This parameter can be a value of @ref FEMC_Memory_Write_Burst_Length. */ + + uint32_t MemWidth; /* Defines the memory width. This parameter can be a value of @ref FEMC_Memory_Width. */ + + uint32_t BAA; /* Defines the BAA signal enable. This parameter can be a value of @ref FEMC_BAA_Port_Selection. */ + + uint32_t ADV; /* Defines the ADVS signal enable. This parameter can be a value of @ref FEMC_ADV_Port_Selection. */ + + uint32_t BLSS; /* Defines the BLS signal selection. This parameter can be a value of @ref FEMC_BLS_Synchronization_Selection. */ + + uint32_t BurstAlign; /* Defines whether memory bursts are split on memory burst boundaries, when you configure the FEMC to perform synchronous transfers + This parameter can be a value of @ref FEMC_Burst_align_Selection. */ + +} FEMC_ChipInitType; + +/** FEMC Init structure definition **/ +typedef struct +{ + FEMC_ChipInitType ChipCfg; + FEMC_TimingInitType TimingCfg; + +}FEMC_InitType; + +/** FEMC ECC Configuration Structure definition **/ +typedef struct +{ + uint32_t BLKNum; /* Defines the number of 512 byte blocks in a nand flash page. */ + + uint32_t Mode; /* Defines the mode of the ECC block. This parameter can be a value of @ref FEMC_ECC_Mode */ + + uint32_t ReadMode; /* Defines when ECC values are read from memory. This parameter can be a value of @ref FEMC_ECC_Read_Time */ + + uint32_t JUMP; /* Defines whether the memory supports column change address commands or not. This parameter can be a value of @ref FEMC_ECC_Jump_Mode */ + + uint32_t A8OUTMSK; /* Defines if A8 is output with the address. This parameter can be a value of @ref FEMC_ECC_A8_Output */ + + uint32_t ReadINT; /* Defines the ECC pass interrupt state when the ECC data is read from memory. This parameter can be a value of @ref FEMC_ECC_Pass_Interrupt */ + + uint32_t ABTINT; /* Defines the ECC error interrupt state when an error occurs. This parameter can be a value of @ref FEMC_ECC_Abort_Interrupt */ + + uint32_t EXTBLKEN; /* Defines whether enables a small block for extra information after the last 512 bytes block in the page or not. + This parameter can be a value of @ref FEMC_ECC_Extra_Block_State */ + + uint32_t EXTBLKSize; /* Defines the size of the extra block in memory after the last 512-byte block. This parameter can be a value of @ref FEMC_ECC_Extra_Block_Size */ + + uint32_t CMD0; /* Defines the commands that the ECC block uses to detect the start of an ECC operation for nand flash memory interface*/ + + uint32_t CMD1; /* Defines the commands that the ECC block uses to access different parts of a NAND page for nand flash memory interface*/ + +}FEMC_ECCInitType; + +/** Last Ecc Operation Status **/ +typedef enum +{ + COMPLETE = 0U, + UNALIGNADDR = 1U, + DATASTOP = 2U, + DATASTOP_NOREAD = 3U, +} ECC_Last_Stats; + + +#define SRAM_NOR_CHIP_1 (0x00) /* SRAM Nor Flash Chip 0 */ +#define SRAM_NOR_CHIP_2 (0x01) /* SRAM Nor Flash Chip 1 */ +#define SRAM_NOR_CHIP_3 (0x02) /* SRAM Nor Flash Chip 2 */ +#define SRAM_NOR_CHIP_4 (0x03) /* SRAM Nor Flash Chip 3 */ + +#define NAND_CHIP_1 (0x04) /* NAND Chip 1 */ +#define NAND_CHIP_2 (0x05) /* NAND Chip 2 */ + + +/** FEMC Memory Read Mode **/ +#define FEMC_MEM_READ_ASYNC ((uint32_t)0x00000000) +#define FEMC_MEM_READ_SYNC (FEMC_OMCFG_RDSYN) +/** FEMC Memory Write Mode **/ +#define FEMC_MEM_WRITE_ASYNC ((uint32_t)0x00000000) +#define FEMC_MEM_WRITE_SYNC (FEMC_OMCFG_WRSYN) + +/** FEMC Memory Read Burst Length **/ +#define FEMC_MEM_READ_BURST_1 ((uint32_t)0x00000000) /* 1 beat */ +#define FEMC_MEM_READ_BURST_4 (FEMC_OMCFG_RDBL_0) /* 4 beats */ +#define FEMC_MEM_READ_BURST_8 (FEMC_OMCFG_RDBL_1) /* 8 beats */ +#define FEMC_MEM_READ_BURST_16 (FEMC_OMCFG_RDBL_1 | FEMC_OMCFG_RDBL_0) /* 16 beats */ +#define FEMC_MEM_READ_BURST_32 (FEMC_OMCFG_RDBL_2) /* 32 beats */ +#define FEMC_MEM_READ_BURST_CONTINUOUS (FEMC_OMCFG_RDBL_2 | FEMC_OMCFG_RDBL_0) /* continuous */ + +/** FEMC Memory Write Burst Length **/ +#define FEMC_MEM_WRITE_BURST_1 (0UL) /* 1 beat */ +#define FEMC_MEM_WRITE_BURST_4 (FEMC_OMCFG_WRBL_0) /* 4 beats */ +#define FEMC_MEM_WRITE_BURST_8 (FEMC_OMCFG_WRBL_1) /* 8 beats */ +#define FEMC_MEM_WRITE_BURST_16 (FEMC_OMCFG_WRBL_1 | FEMC_OMCFG_WRBL_0) /* 16 beats */ +#define FEMC_MEM_WRITE_BURST_32 (FEMC_OMCFG_WRBL_2) /* 32 beats */ +#define FEMC_MEM_WRITE_BURST_CONTINUOUS (FEMC_OMCFG_WRBL_2 | FEMC_OMCFG_WRBL_0) /* continuous */ + +/** FEMC Memory Width **/ +#define FEMC_MEMORY_WIDTH_8BIT ((uint32_t)0x00000000) +#define FEMC_MEMORY_WIDTH_16BIT (FEMC_OMCFG_MDBW_0) +#define FEMC_MEMORY_WIDTH_32BIT (FEMC_OMCFG_MDBW_1) + +/** FEMC BAA Port Selection **/ +#define FEMC_BAA_PORT_DISABLE ((uint32_t)0x00000000) +#define FEMC_BAA_PORT_ENABLE (FEMC_OMCFG_BAA) + +/** FEMC ADV Port Selection **/ +#define FEMC_ADV_PORT_DISABLE ((uint32_t)0x00000000) +#define FEMC_ADV_PORT_ENABLE (FEMC_OMCFG_ADV) + +/** FEMC_BLS_Synchronization_Selection **/ +#define FEMC_BLS_SYNC_CS ((uint32_t)0x00000000) +#define FEMC_BLS_SYNC_WE (FEMC_OMCFG_BLSS) + +/** FEMC_Burst_align_Selection **/ +#define FEMC_BURST_NO_SPLIT ((uint32_t)0x00000000) +#define FEMC_BURST_SPLIT_ON_32 (FEMC_OMCFG_BSTAGN_0) +#define FEMC_BURST_SPLIT_ON_64 (FEMC_OMCFG_BSTAGN_1) +#define FEMC_BURST_SPLIT_ON_128 (FEMC_OMCFG_BSTAGN_1 | FEMC_OMCFG_BSTAGN_0) +#define FEMC_BURST_SPLIT_ON_256 (FEMC_OMCFG_BSTAGN_2) + +/** FEMC Command **/ +#define FEMC_CMD_UPDATEREGS_AND_AXI ((uint32_t)0x00000000) +#define FEMC_CMD_MDREGCONFIG (FEMC_CTRL_CMDTYPE_0) +#define FEMC_CMD_UPDATEREGS (FEMC_CTRL_CMDTYPE_1) +#define FEMC_CMD_MDREGCONFIG_AND_UPDATEREGS (FEMC_CTRL_CMDTYPE_1 | FEMC_CTRL_CMDTYPE_0) + +/** FEMC CRE Polarity **/ +#define FEMC_CRE_POLARITY_LOW ((uint32_t)0x00000000) /* CRE is LOW */ +#define FEMC_CRE_POLARITY_HIGH (FEMC_CTRL_CREPOL) /* CRE is HIGH when ModeReg write occurs */ + +/** FEMC Flag definition **/ +#define FEMC_SRAM_FLAG (FEMC_STS_RINT0F) +#define FEMC_NAND_FLAG (FEMC_STS_RINT1F) +#define FEMC_ECC_FLAG (FEMC_STS_RECCINTF) +#define FEMC_SRAM_EN_FLAG (FEMC_STS_INT0ENF) +#define FEMC_NAND_EN_FLAG (FEMC_STS_INT1ENF) +#define FEMC_ECC_EN_FLAG (FEMC_STS_ECCINTENF) + +/** FEMC Flag clear */ +#define FEMC_SRAM_FLAG_CLEAR (FEMC_CCFG_INT0CLR) +#define FEMC_NAND_FLAG_CLEAR (FEMC_CCFG_INT1CLR) + +/** FEMC interrupts definition **/ +#define FEMC_IT_SRAM_EN (FEMC_CFG_INT0EN) +#define FEMC_IT_NAND_EN (FEMC_CFG_INT1EN) +#define FEMC_IT_ECC_EN (FEMC_CFG_ECCINTEN) + +/** FEMC interrupts clear */ +#define FEMC_IT_SRAM_FLAG_CLEAR (FEMC_CCFG_INT0CLR) +#define FEMC_IT_NAND_FLAG_CLEAR (FEMC_CCFG_INT1CLR) + +/** FEMC interrupts disable **/ +#define FEMC_IT_SRAM_DIS (FEMC_CCFG_INT0DIS) +#define FEMC_IT_NAND_DIS (FEMC_CCFG_INT1DIS) +#define FEMC_IT_ECC_DIS (FEMC_CCFG_ECCINTDIS) + +/** FEMC interrupts status **/ +#define FEMC_IT_SRAM_FLAG (FEMC_STS_INT0F) +#define FEMC_IT_NAND_FLAG (FEMC_STS_INT1F) +#define FEMC_IT_ECC_FLAG (FEMC_STS_ECCINTF) + +/** FEMC SRAM interface type **/ +#define FEMC_SRAM_MULT (FEMC_STS1_M0TYPE_0 | FEMC_STS1_M0TYPE_1) +#define FEMC_SRAM_NON_MULT (FEMC_STS1_M0TYPE_0) + +/** FEMC ECC Page block number **/ +#define FEMC_ECC_NO_512_BYTES ((uint32_t)0x00000000) +#define FEMC_ECC_ONE_512_BYTES (FEMC_ECCCFG_BLKNUM_0) +#define FEMC_ECC_TWO_512_BYTES (FEMC_ECCCFG_BLKNUM_1) +#define FEMC_ECC_FOUR_512_BYTES (FEMC_ECCCFG_BLKNUM_1 | FEMC_ECCCFG_BLKNUM_0) + +/** FEMC ECC Mode **/ +#define FEMC_ECC_BYPASSED ((uint32_t)0x00000000) +#define FEMC_ECC_FOR_APB (FEMC_ECCCFG_MOD_0) +#define FEMC_ECC_AUTO_WR (FEMC_ECCCFG_MOD_1) + +/** FEMC ECC Read Mode **/ +#define FEMC_ECC_READ_BLOCK_END ((uint32_t)0x00000000) +#define FEMC_ECC_READ_PAGE_END (FEMC_ECCCFG_RMOD) + +/** FEMC ECC Jump Mode **/ +#define FEMC_ECC_NO_JUMP ((uint32_t)0x00000000) +#define FEMC_ECC_COLUMN_JUMP (FEMC_ECCCFG_JUMP_0) +#define FEMC_ECC_FULL_JUMP (FEMC_ECCCFG_JUMP_1) + +/** FEMC ECC A8 Output **/ +#define FEMC_A8_OUTPUT_DISABLE (FEMC_ECCCFG_A8OUTMSK) +#define FEMC_A8_OUTPUT_ENABLE ((uint32_t)0x00000000) + +/** FEMC ECC Pass Interrupt **/ +#define FEMC_ECC_PASS_INTERRUPT_DISABLE ((uint32_t)0x00000000) +#define FEMC_ECC_PASS_INTERRUPT_ENABLE (FEMC_ECCCFG_RDCINT) + +/** FEMC ECC Abort Interrupt **/ +#define FEMC_ECC_ABORT_INTERRUPT_DISABLE ((uint32_t)0x00000000) +#define FEMC_ECC_ABORT_INTERRUPT_ENABLE (FEMC_ECCCFG_ABTINT) + +/** FEMC ECC Extra Block Size **/ +#define FEMC_ECC_EXTRA_BLOCK_4_BYTES ((uint32_t)0x00000000) +#define FEMC_ECC_EXTRA_BLOCK_8_BYTES (FEMC_ECCCFG_EBLKSIZ_0) +#define FEMC_ECC_EXTRA_BLOCK_16_BYTES (FEMC_ECCCFG_EBLKSIZ_1) +#define FEMC_ECC_EXTRA_BLOCK_32_BYTES (FEMC_ECCCFG_EBLKSIZ_1 | FEMC_ECCCFG_EBLKSIZ_0) + +/** FEMC ECC Extra Block State **/ +#define FEMC_ECC_EXTRA_BLOCK_DISABLE ((uint32_t)0x00000000) +#define FEMC_ECC_EXTRA_BLOCK_ENABLE (FEMC_ECCCFG_EBLKEN) + +/** FEMC ECC Page block Index **/ +#define FEMC_ECC_PAGE_BLOCK_INDEX0 ((uint32_t)0x00000000) +#define FEMC_ECC_PAGE_BLOCK_INDEX1 ((uint32_t)0x00000001) +#define FEMC_ECC_PAGE_BLOCK_INDEX2 ((uint32_t)0x00000002) +#define FEMC_ECC_PAGE_BLOCK_INDEX3 ((uint32_t)0x00000003) +#define FEMC_ECC_PAGE_BLOCK_EXTRA ((uint32_t)0x00000004) + +/** FEMC Flag Index **/ +#define FEMC_ECC_FLAG_VALUE_VALID (FEMC_ECCSTS_VLDF_0) +#define FEMC_ECC_FLAG_FAIL (FEMC_ECCSTS_FAILF_0) +#define FEMC_ECC_FLAG_CAN_CORRECT (FEMC_ECCSTS_CORCTF_0) +#define FEMC_ECC_FLAG_READ (FEMC_ECCSTS_RDF_0) + +/** FEMC ECC Page Block Interrupt Index **/ +#define FEMC_ECC_INT_FLAG_PAGE_BLOCK0 (FEMC_ECCSTS_INTF_0) +#define FEMC_ECC_INT_FLAG_PAGE_BLOCK1 (FEMC_ECCSTS_INTF_1) +#define FEMC_ECC_INT_FLAG_PAGE_BLOCK2 (FEMC_ECCSTS_INTF_2) +#define FEMC_ECC_INT_FLAG_PAGE_BLOCK3 (FEMC_ECCSTS_INTF_3) +#define FEMC_ECC_INT_FLAG_PAGE_EXTRA (FEMC_ECCSTS_INTF_4) +#define FEMC_ECC_INT_FLAG_ABORT (FEMC_ECCSTS_INTF_5) + +/** FEMC ECC Block Flag Index **/ +#define FEMC_ECC_BLOCK_FLAG_CAN_CORRECT ((uint32_t)0x0000001) +#define FEMC_ECC_BLOCK_FLAG_FAIL ((uint32_t)0x0000002) +#define FEMC_ECC_BLOCK_FLAG_READ ((uint32_t)0x0000004) +#define FEMC_ECC_BLOCK_FLAG_VALUE_VALID ((uint32_t)0x0000008) +#define FEMC_ECC_BLOCK_FLAG_INTERRUPT ((uint32_t)0x0000010) + +/** FEMC Last status **/ +#define FEMC_ECC_LAST_STATUS_COMPLETE ((uint32_t)0x0000000) +#define FEMC_ECC_LAST_STATUS_UNALIGNADDR (FEMC_ECCSTS_LASTS_0) +#define FEMC_ECC_LAST_STATUS_DATASTOP (FEMC_ECCSTS_LASTS_1) +#define FEMC_ECC_LAST_STATUS_DATASTOP_NOREAD (FEMC_ECCSTS_LASTS_0 | FEMC_ECCSTS_LASTS_1) + +/** FEMC_Exported_Functions **/ +void FEMC_Init(FEMC_InitType *FEMC_InitStruct); +void FEMC_InitStruct(FEMC_InitType* FEMC_InitStruct); +void FEMC_SetCommand(uint32_t Chip, uint32_t Cmd, uint32_t CrePolarity, uint32_t Address); +ErrorStatus FEMC_CheckChipStatus(uint32_t Chip, FEMC_ChipInitType *ChipCfg); +ErrorStatus FEMC_CheckTimingStatus(uint32_t Chip, FEMC_TimingInitType *TimingCfg); +void FEMC_SetRefreshPeriod(uint32_t PeriodVal); +uint32_t FEMC_GetRefreshPeriod(void); +void FEMC_SetAddressmatch(uint32_t Chip, uint32_t Address_Match_Value); +void FEMC_SRAMMuxModeEnable(FunctionalState NewState); +void FEMC_SRAMAGTMEnable(FunctionalState NewState); +void FEMC_SRAMSYNCEnable(FunctionalState NewState); +void FEMC_NANDCSLEnable(FunctionalState NewState); +void FEMC_NANDAGTMEnable(FunctionalState NewState); +void FEMC_NANDSYNCEnable(FunctionalState NewState); +void FEMC_RemapEnable(FunctionalState NewState); +void FEMC_AsyncADVConfig(FunctionalState NewState); +uint32_t FEMC_GetSRAMType(void); + +void FEMC_ClrFlag(uint32_t FEMC_FLAG); +FlagStatus FEMC_GetFlag(uint32_t FEMC_FLAG); +void FEMC_ITConfig(uint32_t FEMC_IT, FunctionalState NewState); +void FEMC_ClrITFlag(uint32_t FEMC_FLAG); +ITStatus FEMC_GetITFlag(uint32_t FEMC_IT_FLAG); + +void FEMC_ECC_Init(const FEMC_ECCInitType *ECCInitType); +void FEMC_SetECCAddr(uint32_t address0, uint32_t address1); +FlagStatus FEMC_GetECCFlag(uint32_t FEMC_ECC_Flag_Index, uint32_t ECC_Block_Index); +FlagStatus FEMC_GetECCITFlag(uint32_t ECC_Block_Index); +void FEMC_ECCClrFlag(uint32_t ECC_Block_Index); +FlagStatus FEMC_GetECCBusyFlag(void); +ECC_Last_Stats FEMC_GetECCLastSTS(void); +FlagStatus FEMC_GetECCRWFlag(void); +FlagStatus FEMC_GetECCBlockSTS(uint32_t ECC_Block_Index, uint32_t FEMC_Block_Flag_Index); +void FEMC_ClrECCBlockSTS(uint32_t ECC_Block_Index, uint32_t FEMC_Block_Flag_Index); +uint32_t FEMC_GetECCvalue(uint32_t ECC_Block_Index); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_FEMC_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fmac.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fmac.h new file mode 100644 index 0000000000..c7127943bc --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_fmac.h @@ -0,0 +1,189 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_fmac.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_FMAC_H +#define __N32H76X_78X_FMAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** FMAC Init structure definition **/ + +typedef struct +{ + uint8_t InputBufBaseAddress; /* Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF) */ + + uint8_t InputBufSize; /* Number of 16-bit words allocated to the input buffer (including the optional "headroom")*/ + + uint8_t CoeffBufBaseAddress; /* Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF)*/ + + uint8_t CoeffBufSize; /* Number of 16-bit words allocated to the coefficient buffer */ + + uint8_t OutBufBaseAddress; /* Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). */ + + uint8_t OutBufSize; /* Number of 16-bit words allocated to the output buffer (including the optional "headroom") */ + + uint8_t P; /* Parameter P (vector length, number of filter taps, etc.) */ + + uint8_t Q; /* Parameter Q (vector length, etc.). Ignored if not needed */ + + uint8_t R; /* Parameter R (gain, etc.). Ignored if not needed. */ + + uint32_t InputBufThreshold; /* Input threshold: the buffer full flag will be set if the number of free spaces in the buffer is lower than this threshold*/ + + uint32_t OutBufThreshold; /* Output threshold: the buffer empty flag will be set if the number of unread values */ + + uint32_t Limit; /* Enable or disable the limit feature */ + + uint32_t Func; /* Filter type */ +} FMAC_InitType; + +/** FMAC preload buffer parameters structure definition **/ +typedef struct +{ + int16_t *pInputData; /* content of the input data */ + uint8_t InputDataSize; /* Size of the input data */ + + int16_t *pCoeffA; /* [IIR only] Initialization of the coefficient vector A. If not needed, it should be set to NULL. */ + uint8_t CoeffASize; /* Size of the coefficient vector A. */ + int16_t *pCoeffB; /* Initialization of the coefficient vector B. If not needed (re-use of a previously loaded buffer), it should be set to NULL. */ + uint8_t CoeffBSize; /* Size of the coefficient vector B. */ + int16_t *pOutputData; /* content of the output data */ + uint8_t OutputDataSize; /* size of the output data */ +} FMAC_PreLoadType; + +/* Function define */ +#define FMAC_FUNC_LOADX1 ((uint32_t)0x01000000U) /* Load X1 buffer */ +#define FMAC_FUNC_LOADX2 ((uint32_t)0x02000000U) /* Load X2 buffer */ +#define FMAC_FUNC_LOADY ((uint32_t)0x03000000U) /* Load Y buffer */ +#define FMAC_FUNC_CONVO_FIR ((uint32_t)0x08000000U) /* Convolution (FIR filter) */ +#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)0x09000000U) /* IIR filter (direct form 1) */ + +/* Buffer threshold define, used for X1 buffer and Y buffer */ +#define FMAC_THRESHOLD1 ((uint32_t)0x00000000U) /* Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. + Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */ +#define FMAC_THRESHOLD2 ((uint32_t)0x01000000U) /* Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. + Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */ +#define FMAC_THRESHOLD4 ((uint32_t)0x02000000U) /* Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. + Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */ +#define FMAC_THRESHOLD8 ((uint32_t)0x03000000U) /* Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. + Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */ + +/* Data limit define */ +#define FMAC_LIMIT_DISABLE ((uint32_t)0x00000000U) /* Limit disabled */ +#define FMAC_LIMIT_ENABLE FMAC_CTRL_LIMITEN /* Limit enabled */ + +/* FMAC flag definitions */ +#define FMAC_FLAG_YBUFEF FMAC_STS_YBUFEF /* Y buffer empty flag */ +#define FMAC_FLAG_X1BUFFF FMAC_STS_X1BUFFF /* X1 buffer full flag */ +#define FMAC_FLAG_OVF FMAC_STS_OVF /* Overflow error flag */ +#define FMAC_FLAG_UNF FMAC_STS_UNF /* Underflow error flag */ +#define FMAC_FLAG_SATF FMAC_STS_SATF /* Saturation error flag */ + +/* FMAC interrupt definitions */ +#define FMAC_INT_READ FMAC_CTRL_RINTEN /* Enable read interrupt */ +#define FMAC_INT_WRITE FMAC_CTRL_WIINEN /* Enable write interrupt */ +#define FMAC_INT_OV FMAC_CTRL_OVINTEN /* Enable overflow error interrupts */ +#define FMAC_INT_UN FMAC_CTRL_UNINTEN /* Enable underflow error interrupts */ +#define FMAC_INT_SAT FMAC_CTRL_SATINTEN /* Enable saturation error interrupts */ + +/* FMAC DMA mdoe definitions */ +#define FMAC_DMA_READ FMAC_CTRL_DMAREN /* Enable DMA read channel requests */ +#define FMAC_DMA_WRITE FMAC_CTRL_DMAWEN /* Enable DMA write channel requests */ + +/* FMAC interrupt flag definitions */ +#define FMAC_INT_FLAG_YBUFEF ((FMAC_INT_READ << 16U) | FMAC_FLAG_YBUFEF) /* Y buffer empty interrupt flag */ +#define FMAC_INT_FLAG_X1BUFFF ((FMAC_INT_WRITE << 16U) | FMAC_FLAG_X1BUFFF) /* X1 buffer full interrupt flag */ +#define FMAC_INT_FLAG_OVF ((FMAC_INT_OV << 16U) | FMAC_FLAG_OVF) /* Overflow error interrupt flag */ +#define FMAC_INT_FLAG_UNF ((FMAC_INT_UN << 16U) | FMAC_FLAG_UNF) /* underflow error interrupt flag */ +#define FMAC_INT_FLAG_SATF ((FMAC_INT_SAT << 16U) | FMAC_FLAG_SATF) /* saturation error interrupt flag */ +#define FMAC_INT_FLAG_MASK ((uint32_t)0x0000FFFF) + +/* FMAC polling-based communications time-out value */ +#define FMAC_TIMEOUT (400000000U) +/* FMAC reset time-out value */ +#define FMAC_RESET_TIMEOUT_VALUE (200000000U) + +void FMAC_DeInit(void); +void FMAC_StructInit(FMAC_InitType * FMAC_InitStruct); +void FMAC_PreLoadStructInit(FMAC_PreLoadType * FMAC_PreloadStruct); +void FMAC_Init(FMAC_InitType * FMAC_InitStruct); +void FMAC_PreLoadData(uint32_t size, int16_t array[]); +ErrorStatus FMAC_PreloadBufferData(FMAC_PreLoadType * FMAC_PreloadStruct); +void FMAC_ConfigParam(FMAC_InitType* FMAC_ParamStruct); +void FMAC_FilterStart(FMAC_InitType* FMAC_ParamStruct); +ErrorStatus FMAC_Reset(void); +void FMAC_Enable(FunctionalState Cmd); +void FMAC_ConfigX1(uint8_t Baseaddr, uint8_t Bufsize, uint32_t Threshold); +void FMAC_ConfigX2(uint8_t Baseaddr, uint8_t Bufsize); +void FMAC_ConfigY(uint8_t Baseaddr, uint8_t Bufsize, uint32_t Threshold); +void FMAC_WriteData(int16_t data); +int16_t FMAC_ReadData(void); +void FMAC_EnableLimit(FunctionalState Cmd); +void FMAC_EnableDMA(uint32_t dma_req, FunctionalState Cmd); +ErrorStatus FMAC_FinishCalculate(void); +void FMAC_ConfigInt(uint32_t interrupt, FunctionalState Cmd); +FlagStatus FMAC_GetIntStatus(uint32_t FMAC_INT); +FlagStatus FMAC_GetFlagStatus(uint32_t FMAC_FLAG); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_FMAC_H */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_gpio.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_gpio.h new file mode 100644 index 0000000000..db2b79deef --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_gpio.h @@ -0,0 +1,912 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_gpio.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ + +#ifndef __N32H76X_78X_GPIO_H__ +#define __N32H76X_78X_GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32h76x_78x.h" + + + /*** GPIO Structure Definition Start ***/ + + + /***GPIO Init structure definition***/ +typedef struct +{ + uint32_t Pin; /* Specifies the GPIO pins to be configured. */ + uint32_t GPIO_Mode; /* Specifies the operating mode for the selected pins. */ + uint32_t GPIO_Pull; /* Specifies the Pull-up or Pull-Down activation for the selected pins. */ + uint32_t GPIO_Slew_Rate; /* Specify the reverse speed for the selected pins. */ + uint32_t GPIO_Current; /* Driving capability of the select pins. */ + uint32_t GPIO_Alternate; /* Peripheral to be connected to the selected pins. */ +}GPIO_InitType; + +/** Bit_SET and Bit_RESET enumeration **/ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}Bit_OperateType; + +/*** GPIO Structure Definition End ***/ + +/*** GPIO Macro Definition Start ***/ +#define GPIO_GET_INDEX(GPIOX_BASE) (((GPIOX_BASE) - GPIOA_BASE)/0x400UL) + +#define GPIO_GET_PERIPH(INDEX) ((GPIO_Module*)(GPIOA_BASE + (INDEX) * 0x400UL)) + +/** Bit mask define **/ +#define GPIO_PMODE_BIT_MASK (GPIO_PMODE_PMODE0) +#define GPIO_PUPD_BIT_MASK (GPIO_PUPD_PUPD0) +#define GPIO_AFSEL_BIT_MASK (GPIO_AFSEL0_AFSEL0) +#define GPIO_DS_BIT_MASK (GPIO_DS_DS0) +#define GPIO_SR_BIT_MASK (GPIO_SR_SR0) +#define AFIO_EXTI_BIT_MASK (AFIO_EXTI_CFG1_EXTI0) + +/** SIP SDRAM priority select in AFIO **/ +#define AFIO_SIP_SDRAM_PRIORITY_HIGH (AFIO_RMP_CFG_SIP_SDRAM_SEL) +#define AFIO_SIP_SDRAM_PRIORITY_LOW ((uint32_t)0x00000000U) + +/** SPI mode definition in AFIO **/ +#define AFIO_SPI1_NSS (AFIO_RMP_CFG_SPI1_NSS) +#define AFIO_SPI2_NSS (AFIO_RMP_CFG_SPI2_NSS) +#define AFIO_SPI3_NSS (AFIO_RMP_CFG_SPI3_NSS) +#define AFIO_SPI4_NSS (AFIO_RMP_CFG_SPI4_NSS) +#define AFIO_SPI5_NSS (AFIO_RMP_CFG_SPI5_NSS) +#define AFIO_SPI6_NSS (AFIO_RMP_CFG_SPI6_NSS) +#define AFIO_SPI7_NSS (AFIO_RMP_CFG_SPI7_NSS) +#define AFIO_SPI_NSS_HIGH_IMPEDANCE ((uint32_t)0x00000000U) +#define AFIO_SPI_NSS_HIGH_LEVEL (AFIO_RMP_CFG_SPI1_NSS) + +/** SIP FLASH MODE SEL in AFIO **/ +#define AFIO_FLASH0 ((uint32_t)0x00000000U) // IS25WJ032F +#define AFIO_FLASH1 AFIO_RMP_CFG_SIP_FLASHSEL_0 // IS25LP016D +#define AFIO_FLASH2 AFIO_RMP_CFG_SIP_FLASHSEL_1 // XM25LU32CK +#define AFIO_FLASH3 AFIO_RMP_CFG_SIP_FLASHSEL_1 | AFIO_RMP_CFG_SIP_FLASHSEL_0 // GT25Q16A +#define AFIO_FLASH4 AFIO_RMP_CFG_SIP_FLASHSEL_2 // GT25Q32A +#define AFIO_DISFLASH AFIO_RMP_CFG_SIP_FLASHSEL_2 | AFIO_RMP_CFG_SIP_FLASHSEL_1 | AFIO_RMP_CFG_SIP_FLASHSEL_0 // Disable SIP segment (switch to Main IOM) Default + +/** EXTI Analog Filter definition in AFIO **/ +#define AFIO_EXTI_FILTER_ENABLE ((uint32_t)0x00000000U) +#define AFIO_EXTI_FILTER_DISABLE (AFIO_RMP_CFG_EXTI_AFLTBYPS) + +/** DBG enable definition in AFIO **/ +#define AFIO_SELECT_SPI1 (AFIO_RMP_CFG_SPI1_SEL) +#define AFIO_SELECT_SPI2 (AFIO_RMP_CFG_SPI2_SEL) +#define AFIO_SELECT_SPI3 (AFIO_RMP_CFG_SPI3_SEL) +#define AFIO_SELECT_SPI4 (AFIO_RMP_CFG_SPI4_SEL) +#define I2S_MODE ((uint32_t)0x00000000U) +#define SPI_MODE (AFIO_RMP_CFG_SPI1_SEL) + +/** SDMMC clk select in AFIO **/ +#define SDMMC1_CLKFB (AFIO_RMP_CFG_SDMMC1_CLKFB) +#define SDMMC2_CLKFB (AFIO_RMP_CFG_SDMMC2_CLKFB) + +#define I2S1_FULLDUPLEX ((uint32_t)0x00000000) +#define I2S2_FULLDUPLEX (AFIO_RMP_CFG_I2S_FDUP_0) +#define I2S3_FULLDUPLEX (AFIO_RMP_CFG_I2S_FDUP_1) +#define I2S4_FULLDUPLEX (AFIO_RMP_CFG_I2S_FDUP_0 | AFIO_RMP_CFG_I2S_FDUP_1) + +#define SIP_Mode_FAST (GPIO_SR_FAST_SLEW) +#define SIP_Mode_SLOW (GPIO_SR_SLOW_SLEW) + +/** XSPI BigEndian select in AFIO **/ +#define XSPI1_ENDIAN (AFIO_RMP_CFG_XSPI1_EDN) +#define XSPI2_ENDIAN (AFIO_RMP_CFG_XSPI2_EDN) +#define XSPI_LITTLE_ENDIAN ((uint32_t)0x00000000U) +#define XSPI_BIG_ENDIAN (AFIO_RMP_CFG_XSPI1_EDN) + +/** FEMC NAND SRAM select in AFIO **/ +#define FEMC_NAND_SEL (AFIO_RMP_CFG_FEMCSEL) +#define FEMC_SRAM_SEL ((uint32_t)0x00000000U) + +/** FEMC NO_BYTE STROBE select in AFIO **/ +#define NO_BYTE_STROBE (AFIO_RMP_CFG_FEMC_NOBYTE) +#define BYTE_STROBE ((uint32_t)0x00000000U) + +/** ETH2 PHY select in AFIO **/ +#define ETH2_RMII_SEL (AFIO_RMP_CFG_ETH2_PHY) +#define ETH2_MII_SEL ((uint32_t)0x00000000U) + +/** ETH1 PHY select in AFIO **/ +#define ETH1_GMII_SEL ((uint32_t)0x00000000U) +#define ETH1_RGMII_SEL (AFIO_RMP_CFG_ETH1_PHY_0) +#define ETH1_RMII_SEL (AFIO_RMP_CFG_ETH1_PHY_1) +#define ETH1_MII_SEL (AFIO_RMP_CFG_ETH1_PHY_0 | AFIO_RMP_CFG_ETH1_PHY_1) + +/** Bit mask define **/ +#define GPIO_PUPD_BIT_MASK (GPIO_PUPD_PUPD0) +#define GPIO_DS_BIT_MASK (GPIO_DS_DS0) +#define GPIO_SR_BIT_MASK (GPIO_SR_SR0) + +/** GPIO_mode_define **/ +#define GPIO_MODE_OD_MARK (GPIO_POTYPE_OPEN_DRAIN << 4) + +#define GPIO_MODE_INPUT (GPIO_PMODE_INPUT) /* Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (GPIO_PMODE_OUTPUT) /* Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (GPIO_PMODE_OUTPUT | GPIO_MODE_OD_MARK) /* Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (GPIO_PMODE_AF_OUTPUT) /* Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (GPIO_PMODE_AF_OUTPUT | GPIO_MODE_OD_MARK) /* Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (GPIO_PMODE_ANALOG) /* Analog Mode */ + +/** GPIO pins define **/ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFFU) /* All pins selected */ +#define GPIO_PIN_NONE ((uint16_t)0x0000U) /* None pin selected */ + +/** GPIO Pull-Up or Pull-Down Activation **/ +#define GPIO_NO_PULL (GPIO_PUPD_NO_PULL) /* No Pull-up or Pull-down activation */ +#define GPIO_PULL_UP (GPIO_PUPD_PULL_UP) /* Pull-up activation */ +#define GPIO_PULL_DOWN (GPIO_PUPD_PULL_DOWN) /* Pull-down activation */ + +/** GPIO Drive strength config **/ +#define GPIO_DC_2mA (GPIO_DS_2mA) +#define GPIO_DC_4mA (GPIO_DS_4mA) +#define GPIO_DC_8mA (GPIO_DS_8mA) +#define GPIO_DC_12mA (GPIO_DS_12mA) + +#define GPIO_5VTOL_DC_1mA (GPIO_DS_2mA) +#define GPIO_5VTOL_DC_2mA (GPIO_DS_4mA) +#define GPIO_5VTOL_DC_4mA (GPIO_DS_8mA) +#define GPIO_5VTOL_DC_6mA (GPIO_DS_12mA) + +#define GPIO_SDRAM_DC_1mA (GPIO_DS_2mA) +#define GPIO_SDRAM_DC_2mA (GPIO_DS_2mA) +#define GPIO_SDRAM_DC_4mA (GPIO_DS_4mA) +#define GPIO_SDRAM_DC_5mA (GPIO_DS_4mA) +#define GPIO_SDRAM_DC_8mA (GPIO_DS_8mA) +#define GPIO_SDRAM_DC_12mA (GPIO_DS_12mA) + +/** slew rate config **/ +#define GPIO_SLEW_RATE_FAST (GPIO_SR_FAST_SLEW) +#define GPIO_SLEW_RATE_SLOW (GPIO_SR_SLOW_SLEW) + +/** GPIO port sources **/ +#define GPIOA_PORT_SOURCE ((uint8_t)0x00U) +#define GPIOB_PORT_SOURCE ((uint8_t)0x01U) +#define GPIOC_PORT_SOURCE ((uint8_t)0x02U) +#define GPIOD_PORT_SOURCE ((uint8_t)0x03U) +#define GPIOE_PORT_SOURCE ((uint8_t)0x04U) +#define GPIOF_PORT_SOURCE ((uint8_t)0x05U) +#define GPIOG_PORT_SOURCE ((uint8_t)0x06U) +#define GPIOH_PORT_SOURCE ((uint8_t)0x07U) +#define GPIOI_PORT_SOURCE ((uint8_t)0x08U) +#define GPIOJ_PORT_SOURCE ((uint8_t)0x09U) +#define GPIOK_PORT_SOURCE ((uint8_t)0x0AU) + +/** GPIO pin sources **/ +#define GPIO_PIN_SOURCE0 ((uint8_t)0x00U) /* Pin 0 selected */ +#define GPIO_PIN_SOURCE1 ((uint8_t)0x01U) /* Pin 1 selected */ +#define GPIO_PIN_SOURCE2 ((uint8_t)0x02U) /* Pin 2 selected */ +#define GPIO_PIN_SOURCE3 ((uint8_t)0x03U) /* Pin 3 selected */ +#define GPIO_PIN_SOURCE4 ((uint8_t)0x04U) /* Pin 4 selected */ +#define GPIO_PIN_SOURCE5 ((uint8_t)0x05U) /* Pin 5 selected */ +#define GPIO_PIN_SOURCE6 ((uint8_t)0x06U) /* Pin 6 selected */ +#define GPIO_PIN_SOURCE7 ((uint8_t)0x07U) /* Pin 7 selected */ +#define GPIO_PIN_SOURCE8 ((uint8_t)0x08U) /* Pin 8 selected */ +#define GPIO_PIN_SOURCE9 ((uint8_t)0x09U) /* Pin 9 selected */ +#define GPIO_PIN_SOURCE10 ((uint8_t)0x0AU) /* Pin 10 selected */ +#define GPIO_PIN_SOURCE11 ((uint8_t)0x0BU) /* Pin 11 selected */ +#define GPIO_PIN_SOURCE12 ((uint8_t)0x0CU) /* Pin 12 selected */ +#define GPIO_PIN_SOURCE13 ((uint8_t)0x0DU) /* Pin 13 selected */ +#define GPIO_PIN_SOURCE14 ((uint8_t)0x0EU) /* Pin 14 selected */ +#define GPIO_PIN_SOURCE15 ((uint8_t)0x0FU) /* Pin 15 selected */ + +/** GPIOx_Alternate_function_selection Alternate function selection **/ +#define GPIO_AF0 (GPIO_AFSEL_AF0 ) +#define GPIO_AF1 (GPIO_AFSEL_AF1 ) +#define GPIO_AF2 (GPIO_AFSEL_AF2 ) +#define GPIO_AF3 (GPIO_AFSEL_AF3 ) +#define GPIO_AF4 (GPIO_AFSEL_AF4 ) +#define GPIO_AF5 (GPIO_AFSEL_AF5 ) +#define GPIO_AF6 (GPIO_AFSEL_AF6 ) +#define GPIO_AF7 (GPIO_AFSEL_AF7 ) +#define GPIO_AF8 (GPIO_AFSEL_AF8 ) +#define GPIO_AF9 (GPIO_AFSEL_AF9 ) +#define GPIO_AF10 (GPIO_AFSEL_AF10) +#define GPIO_AF11 (GPIO_AFSEL_AF11) +#define GPIO_AF12 (GPIO_AFSEL_AF12) +#define GPIO_AF13 (GPIO_AFSEL_AF13) +#define GPIO_AF14 (GPIO_AFSEL_AF14) +#define GPIO_AF15 (GPIO_AFSEL_AF15) +#define GPIO_NO_AF (GPIO_AFSEL_AF15) +#define GPIO_NO_AF1 (GPIO_AFSEL_AF13) //user can change no alternate function according different GPIOs + +#define EXTI_GPIOA_Pin_0 ((uint8_t)0x00) +#define EXTI_GPIOB_Pin_0 ((uint8_t)0x01) +#define EXTI_GPIOC_Pin_0 ((uint8_t)0x02) +#define EXTI_GPIOD_Pin_0 ((uint8_t)0x03) +#define EXTI_GPIOE_Pin_0 ((uint8_t)0x04) +#define EXTI_GPIOF_Pin_0 ((uint8_t)0x05) +#define EXTI_GPIOG_Pin_0 ((uint8_t)0x06) +#define EXTI_GPIOH_Pin_0 ((uint8_t)0x07) +#define EXTI_GPIOI_Pin_0 ((uint8_t)0x08) +#define EXTI_GPIOJ_Pin_0 ((uint8_t)0x09) +#define EXTI_GPIOK_Pin_0 ((uint8_t)0x0A) + +#define EXTI_GPIOA_Pin_1 ((uint8_t)0x0B) +#define EXTI_GPIOB_Pin_1 ((uint8_t)0x0C) +#define EXTI_GPIOC_Pin_1 ((uint8_t)0x0D) +#define EXTI_GPIOD_Pin_1 ((uint8_t)0x0E) +#define EXTI_GPIOE_Pin_1 ((uint8_t)0x0F) +#define EXTI_GPIOF_Pin_1 ((uint8_t)0x10) +#define EXTI_GPIOG_Pin_1 ((uint8_t)0x11) +#define EXTI_GPIOH_Pin_1 ((uint8_t)0x12) +#define EXTI_GPIOI_Pin_1 ((uint8_t)0x13) +#define EXTI_GPIOJ_Pin_1 ((uint8_t)0x14) +#define EXTI_GPIOK_Pin_1 ((uint8_t)0x15) + +#define EXTI_GPIOA_Pin_2 ((uint8_t)0x16) +#define EXTI_GPIOB_Pin_2 ((uint8_t)0x17) +#define EXTI_GPIOC_Pin_2 ((uint8_t)0x18) +#define EXTI_GPIOD_Pin_2 ((uint8_t)0x19) +#define EXTI_GPIOE_Pin_2 ((uint8_t)0x1A) +#define EXTI_GPIOF_Pin_2 ((uint8_t)0x1B) +#define EXTI_GPIOG_Pin_2 ((uint8_t)0x1C) +#define EXTI_GPIOH_Pin_2 ((uint8_t)0x1D) +#define EXTI_GPIOI_Pin_2 ((uint8_t)0x1E) +#define EXTI_GPIOJ_Pin_2 ((uint8_t)0x1F) +#define EXTI_GPIOK_Pin_2 ((uint8_t)0x20) + +#define EXTI_GPIOA_Pin_3 ((uint8_t)0x21) +#define EXTI_GPIOB_Pin_3 ((uint8_t)0x22) +#define EXTI_GPIOC_Pin_3 ((uint8_t)0x23) +#define EXTI_GPIOD_Pin_3 ((uint8_t)0x24) +#define EXTI_GPIOE_Pin_3 ((uint8_t)0x25) +#define EXTI_GPIOF_Pin_3 ((uint8_t)0x26) +#define EXTI_GPIOG_Pin_3 ((uint8_t)0x27) +#define EXTI_GPIOH_Pin_3 ((uint8_t)0x28) +#define EXTI_GPIOI_Pin_3 ((uint8_t)0x29) +#define EXTI_GPIOJ_Pin_3 ((uint8_t)0x2A) +#define EXTI_GPIOK_Pin_3 ((uint8_t)0x2B) + +#define EXTI_GPIOA_Pin_4 ((uint8_t)0x2C) +#define EXTI_GPIOB_Pin_4 ((uint8_t)0x2D) +#define EXTI_GPIOC_Pin_4 ((uint8_t)0x2E) +#define EXTI_GPIOD_Pin_4 ((uint8_t)0x2F) +#define EXTI_GPIOE_Pin_4 ((uint8_t)0x30) +#define EXTI_GPIOF_Pin_4 ((uint8_t)0x31) +#define EXTI_GPIOG_Pin_4 ((uint8_t)0x32) +#define EXTI_GPIOH_Pin_4 ((uint8_t)0x33) +#define EXTI_GPIOI_Pin_4 ((uint8_t)0x34) +#define EXTI_GPIOJ_Pin_4 ((uint8_t)0x35) +#define EXTI_GPIOK_Pin_4 ((uint8_t)0x36) + +#define EXTI_GPIOA_Pin_5 ((uint8_t)0x37) +#define EXTI_GPIOB_Pin_5 ((uint8_t)0x38) +#define EXTI_GPIOC_Pin_5 ((uint8_t)0x39) +#define EXTI_GPIOD_Pin_5 ((uint8_t)0x3A) +#define EXTI_GPIOE_Pin_5 ((uint8_t)0x3B) +#define EXTI_GPIOF_Pin_5 ((uint8_t)0x3C) +#define EXTI_GPIOG_Pin_5 ((uint8_t)0x3D) +#define EXTI_GPIOH_Pin_5 ((uint8_t)0x3E) +#define EXTI_GPIOI_Pin_5 ((uint8_t)0x3F) +#define EXTI_GPIOJ_Pin_5 ((uint8_t)0x40) +#define EXTI_GPIOK_Pin_5 ((uint8_t)0x41) + +#define EXTI_GPIOA_Pin_6 ((uint8_t)0x42) +#define EXTI_GPIOB_Pin_6 ((uint8_t)0x43) +#define EXTI_GPIOC_Pin_6 ((uint8_t)0x44) +#define EXTI_GPIOD_Pin_6 ((uint8_t)0x45) +#define EXTI_GPIOE_Pin_6 ((uint8_t)0x46) +#define EXTI_GPIOF_Pin_6 ((uint8_t)0x47) +#define EXTI_GPIOG_Pin_6 ((uint8_t)0x48) +#define EXTI_GPIOH_Pin_6 ((uint8_t)0x49) +#define EXTI_GPIOI_Pin_6 ((uint8_t)0x4A) +#define EXTI_GPIOJ_Pin_6 ((uint8_t)0x4B) +#define EXTI_GPIOK_Pin_6 ((uint8_t)0x4C) + +#define EXTI_GPIOA_Pin_7 ((uint8_t)0x4D) +#define EXTI_GPIOB_Pin_7 ((uint8_t)0x4E) +#define EXTI_GPIOC_Pin_7 ((uint8_t)0x4F) +#define EXTI_GPIOD_Pin_7 ((uint8_t)0x50) +#define EXTI_GPIOE_Pin_7 ((uint8_t)0x51) +#define EXTI_GPIOF_Pin_7 ((uint8_t)0x52) +#define EXTI_GPIOG_Pin_7 ((uint8_t)0x53) +#define EXTI_GPIOH_Pin_7 ((uint8_t)0x54) +#define EXTI_GPIOI_Pin_7 ((uint8_t)0x55) +#define EXTI_GPIOJ_Pin_7 ((uint8_t)0x56) +#define EXTI_GPIOK_Pin_7 ((uint8_t)0x57) + +#define EXTI_GPIOA_Pin_8 ((uint8_t)0x58) +#define EXTI_GPIOB_Pin_8 ((uint8_t)0x59) +#define EXTI_GPIOC_Pin_8 ((uint8_t)0x5A) +#define EXTI_GPIOD_Pin_8 ((uint8_t)0x5B) +#define EXTI_GPIOE_Pin_8 ((uint8_t)0x5C) +#define EXTI_GPIOF_Pin_8 ((uint8_t)0x5D) +#define EXTI_GPIOG_Pin_8 ((uint8_t)0x5E) +#define EXTI_GPIOH_Pin_8 ((uint8_t)0x5F) +#define EXTI_GPIOI_Pin_8 ((uint8_t)0x60) +#define EXTI_GPIOJ_Pin_8 ((uint8_t)0x61) + +#define EXTI_GPIOA_Pin_9 ((uint8_t)0x63) +#define EXTI_GPIOB_Pin_9 ((uint8_t)0x64) +#define EXTI_GPIOC_Pin_9 ((uint8_t)0x65) +#define EXTI_GPIOD_Pin_9 ((uint8_t)0x66) +#define EXTI_GPIOE_Pin_9 ((uint8_t)0x67) +#define EXTI_GPIOF_Pin_9 ((uint8_t)0x68) +#define EXTI_GPIOG_Pin_9 ((uint8_t)0x69) +#define EXTI_GPIOH_Pin_9 ((uint8_t)0x6A) +#define EXTI_GPIOI_Pin_9 ((uint8_t)0x6B) +#define EXTI_GPIOJ_Pin_9 ((uint8_t)0x6C) + +#define EXTI_GPIOA_Pin_10 ((uint8_t)0x6E) +#define EXTI_GPIOB_Pin_10 ((uint8_t)0x6F) +#define EXTI_GPIOC_Pin_10 ((uint8_t)0x70) +#define EXTI_GPIOD_Pin_10 ((uint8_t)0x71) +#define EXTI_GPIOE_Pin_10 ((uint8_t)0x72) +#define EXTI_GPIOF_Pin_10 ((uint8_t)0x73) +#define EXTI_GPIOG_Pin_10 ((uint8_t)0x74) +#define EXTI_GPIOH_Pin_10 ((uint8_t)0x75) +#define EXTI_GPIOI_Pin_10 ((uint8_t)0x76) +#define EXTI_GPIOJ_Pin_10 ((uint8_t)0x77) + +#define EXTI_GPIOA_Pin_11 ((uint8_t)0x79) +#define EXTI_GPIOB_Pin_11 ((uint8_t)0x7A) +#define EXTI_GPIOC_Pin_11 ((uint8_t)0x7B) +#define EXTI_GPIOD_Pin_11 ((uint8_t)0x7C) +#define EXTI_GPIOE_Pin_11 ((uint8_t)0x7D) +#define EXTI_GPIOF_Pin_11 ((uint8_t)0x7E) +#define EXTI_GPIOG_Pin_11 ((uint8_t)0x7F) +#define EXTI_GPIOH_Pin_11 ((uint8_t)0x80) +#define EXTI_GPIOI_Pin_11 ((uint8_t)0x81) +#define EXTI_GPIOJ_Pin_11 ((uint8_t)0x82) + +#define EXTI_GPIOA_Pin_12 ((uint8_t)0x84) +#define EXTI_GPIOB_Pin_12 ((uint8_t)0x85) +#define EXTI_GPIOC_Pin_12 ((uint8_t)0x86) +#define EXTI_GPIOD_Pin_12 ((uint8_t)0x87) +#define EXTI_GPIOE_Pin_12 ((uint8_t)0x88) +#define EXTI_GPIOF_Pin_12 ((uint8_t)0x89) +#define EXTI_GPIOG_Pin_12 ((uint8_t)0x8A) +#define EXTI_GPIOH_Pin_12 ((uint8_t)0x8B) +#define EXTI_GPIOI_Pin_12 ((uint8_t)0x8C) +#define EXTI_GPIOJ_Pin_12 ((uint8_t)0x8D) + +#define EXTI_GPIOA_Pin_13 ((uint8_t)0x8F) +#define EXTI_GPIOB_Pin_13 ((uint8_t)0x90) +#define EXTI_GPIOC_Pin_13 ((uint8_t)0x91) +#define EXTI_GPIOD_Pin_13 ((uint8_t)0x92) +#define EXTI_GPIOE_Pin_13 ((uint8_t)0x93) +#define EXTI_GPIOF_Pin_13 ((uint8_t)0x94) +#define EXTI_GPIOG_Pin_13 ((uint8_t)0x95) +#define EXTI_GPIOH_Pin_13 ((uint8_t)0x96) +#define EXTI_GPIOI_Pin_13 ((uint8_t)0x97) +#define EXTI_GPIOJ_Pin_13 ((uint8_t)0x98) + +#define EXTI_GPIOA_Pin_14 ((uint8_t)0x9A) +#define EXTI_GPIOB_Pin_14 ((uint8_t)0x9B) +#define EXTI_GPIOC_Pin_14 ((uint8_t)0x9C) +#define EXTI_GPIOD_Pin_14 ((uint8_t)0x9D) +#define EXTI_GPIOE_Pin_14 ((uint8_t)0x9E) +#define EXTI_GPIOF_Pin_14 ((uint8_t)0x9F) +#define EXTI_GPIOG_Pin_14 ((uint8_t)0xA0) +#define EXTI_GPIOH_Pin_14 ((uint8_t)0xA1) +#define EXTI_GPIOI_Pin_14 ((uint8_t)0xA2) +#define EXTI_GPIOJ_Pin_14 ((uint8_t)0xA3) + +#define EXTI_GPIOA_Pin_15 ((uint8_t)0xA5) +#define EXTI_GPIOB_Pin_15 ((uint8_t)0xA6) +#define EXTI_GPIOC_Pin_15 ((uint8_t)0xA7) +#define EXTI_GPIOD_Pin_15 ((uint8_t)0xA8) +#define EXTI_GPIOE_Pin_15 ((uint8_t)0xA9) +#define EXTI_GPIOF_Pin_15 ((uint8_t)0xAA) +#define EXTI_GPIOG_Pin_15 ((uint8_t)0xAB) +#define EXTI_GPIOH_Pin_15 ((uint8_t)0xAC) +#define EXTI_GPIOI_Pin_15 ((uint8_t)0xAD) +#define EXTI_GPIOJ_Pin_15 ((uint8_t)0xAE) + +#define AFIO_TOL5V_PA0 (AFIO_TOL5V_CFG1_PA0TOLENN) +#define AFIO_TOL5V_PA0_C (AFIO_TOL5V_CFG1_PA0_C_TOLENN) +#define AFIO_TOL5V_PA1 (AFIO_TOL5V_CFG1_PA1TOLENN) +#define AFIO_TOL5V_PA1_C (AFIO_TOL5V_CFG1_PA1_C_TOLENN) +#define AFIO_TOL5V_PA2 (AFIO_TOL5V_CFG1_PA2TOLENN) +#define AFIO_TOL5V_PA3 (AFIO_TOL5V_CFG1_PA3TOLENN) +#define AFIO_TOL5V_PA4 (AFIO_TOL5V_CFG1_PA4TOLENN) +#define AFIO_TOL5V_PA5 (AFIO_TOL5V_CFG1_PA5TOLENN) +#define AFIO_TOL5V_PA6 (AFIO_TOL5V_CFG1_PA6TOLENN) +#define AFIO_TOL5V_PA7 (AFIO_TOL5V_CFG1_PA7TOLENN) + +#define AFIO_TOL5V_PB0 (AFIO_TOL5V_CFG2_PB0TOLENN) +#define AFIO_TOL5V_PB1 (AFIO_TOL5V_CFG2_PB1TOLENN) + +#define AFIO_TOL5V_PC0 (AFIO_TOL5V_CFG3_PC0TOLENN) +#define AFIO_TOL5V_PC1 (AFIO_TOL5V_CFG3_PC1TOLENN) +#define AFIO_TOL5V_PC2 (AFIO_TOL5V_CFG3_PC2TOLENN) +#define AFIO_TOL5V_PC2_C (AFIO_TOL5V_CFG3_PC2_C_TOLENN) +#define AFIO_TOL5V_PC3 (AFIO_TOL5V_CFG3_PC3TOLENN) +#define AFIO_TOL5V_PC3_C (AFIO_TOL5V_CFG3_PC3_C_TOLENN) +#define AFIO_TOL5V_PC4 (AFIO_TOL5V_CFG3_PC4TOLENN) +#define AFIO_TOL5V_PC5 (AFIO_TOL5V_CFG3_PC5TOLENN) +#define AFIO_TOL5V_PC6 (AFIO_TOL5V_CFG3_PC6TOLENN) +#define AFIO_TOL5V_PC8 (AFIO_TOL5V_CFG3_PC8TOLENN) +#define AFIO_TOL5V_PC13 (AFIO_TOL5V_CFG3_PC13TOLENN) + +#define AFIO_TOL5V_PF3 (AFIO_TOL5V_CFG4_PF3TOLENN) +#define AFIO_TOL5V_PF4 (AFIO_TOL5V_CFG4_PF4TOLENN) +#define AFIO_TOL5V_PF5 (AFIO_TOL5V_CFG4_PF5TOLENN) +#define AFIO_TOL5V_PF6 (AFIO_TOL5V_CFG4_PF6TOLENN) +#define AFIO_TOL5V_PF7 (AFIO_TOL5V_CFG4_PF7TOLENN) +#define AFIO_TOL5V_PF8 (AFIO_TOL5V_CFG4_PF8TOLENN) +#define AFIO_TOL5V_PF9 (AFIO_TOL5V_CFG4_PF9TOLENN) +#define AFIO_TOL5V_PF10 (AFIO_TOL5V_CFG4_PF10TOLENN) +#define AFIO_TOL5V_PF11 (AFIO_TOL5V_CFG4_PF11TOLENN) +#define AFIO_TOL5V_PF12 (AFIO_TOL5V_CFG4_PF12TOLENN) +#define AFIO_TOL5V_PF13 (AFIO_TOL5V_CFG4_PF13TOLENN) +#define AFIO_TOL5V_PF14 (AFIO_TOL5V_CFG4_PF14TOLENN) + +#define AFIO_TOL5V_PH2 (AFIO_TOL5V_CFG5_PH2TOLENN) +#define AFIO_TOL5V_PH3 (AFIO_TOL5V_CFG5_PH3TOLENN) +#define AFIO_TOL5V_PH4 (AFIO_TOL5V_CFG5_PH4TOLENN) +#define AFIO_TOL5V_PH5 (AFIO_TOL5V_CFG5_PH5TOLENN) + +#define AFIO_TOL5V_PI8 (AFIO_TOL5V_CFG6_PI8TOLENN) +#define AFIO_TOL5V_PI15 (AFIO_TOL5V_CFG6_PI15TOLENN) + +#define AFIO_TOL5V_PJ0 (AFIO_TOL5V_CFG7_PJ0TOLENN) +#define AFIO_TOL5V_PJ3 (AFIO_TOL5V_CFG7_PJ3TOLENN) +#define AFIO_TOL5V_PJ4 (AFIO_TOL5V_CFG7_PJ4TOLENN) +#define AFIO_TOL5V_PJ5 (AFIO_TOL5V_CFG7_PJ5TOLENN) +#define AFIO_TOL5V_PJ6 (AFIO_TOL5V_CFG7_PJ6TOLENN) +#define AFIO_TOL5V_PJ7 (AFIO_TOL5V_CFG7_PJ7TOLENN) + + +typedef enum +{ + SHRT_FAULT_CHANNEL_1 = 0, + SHRT_FAULT_CHANNEL_2, + SHRT_FAULT_CHANNEL_3, + SHRT_FAULT_CHANNEL_4, + SHRT_FAULT_CHANNEL_5, + SHRT_FAULT_CHANNEL_6, +}SHRT_FAULT_CHANNEL_NUM; + +/*FAULT*/ +typedef enum +{ + SHRT1_FAULT_CHANNEL_PA15 = 1, + SHRT1_FAULT_CHANNEL_PB3, + SHRT1_FAULT_CHANNEL_PC11, + SHRT1_FAULT_CHANNEL_PD4, + SHRT1_FAULT_CHANNEL_PE4, + SHRT1_FAULT_CHANNEL_PG9, + SHRT1_FAULT_CHANNEL_PG10, + SHRT1_FAULT_CHANNEL_PI6, + SHRT1_FAULT_CHANNEL_PI15, + SHRT1_FAULT_CHANNEL_PK2, +}SHRT1_FAULT_CHANNEL; + +typedef enum +{ + SHRT2_FAULT_CHANNEL_PC5 = 1, + SHRT2_FAULT_CHANNEL_PD1, + SHRT2_FAULT_CHANNEL_PD15, + SHRT2_FAULT_CHANNEL_PF9, + SHRT2_FAULT_CHANNEL_PF13, + SHRT2_FAULT_CHANNEL_PG1, + SHRT2_FAULT_CHANNEL_PI0, + SHRT2_FAULT_CHANNEL_PI9, + SHRT2_FAULT_CHANNEL_PI13, + SHRT2_FAULT_CHANNEL_PJ0, + SHRT2_FAULT_CHANNEL_PK1, + SHRT2_FAULT_CHANNEL_PK6, +}SHRT2_FAULT_CHANNEL; + +typedef enum +{ + SHRT_EXEV_CHANNEL_1 = 0, + SHRT_EXEV_CHANNEL_2, + SHRT_EXEV_CHANNEL_3, + SHRT_EXEV_CHANNEL_4, + SHRT_EXEV_CHANNEL_5, + SHRT_EXEV_CHANNEL_6, + SHRT_EXEV_CHANNEL_7, + SHRT_EXEV_CHANNEL_8, + SHRT_EXEV_CHANNEL_9, + SHRT_EXEV_CHANNEL_10, +}SHRT_EXEV_CHANNEL_NUM; + +/*External Event*/ +typedef enum +{ + SHRT1_EXEV_CHANNEL_PB4 = 1, + SHRT1_EXEV_CHANNEL_PB5, + SHRT1_EXEV_CHANNEL_PB6, + SHRT1_EXEV_CHANNEL_PB7, + SHRT1_EXEV_CHANNEL_PC10, + SHRT1_EXEV_CHANNEL_PC12, + SHRT1_EXEV_CHANNEL_PD5, + SHRT1_EXEV_CHANNEL_PD8, + SHRT1_EXEV_CHANNEL_PD9, + SHRT1_EXEV_CHANNEL_PE6, + SHRT1_EXEV_CHANNEL_PG0, + SHRT1_EXEV_CHANNEL_PG11, + SHRT1_EXEV_CHANNEL_PG12, + SHRT1_EXEV_CHANNEL_PG13, + SHRT1_EXEV_CHANNEL_PI14, + SHRT1_EXEV_CHANNEL_PJ5, + SHRT1_EXEV_CHANNEL_PK3, + SHRT1_EXEV_CHANNEL_PK4, +}SHRT1_EXEV_CHANNEL; + +typedef enum +{ + SHRT2_EXEV_CHANNEL_PA2 = 1, + SHRT2_EXEV_CHANNEL_PC4, + SHRT2_EXEV_CHANNEL_PD0, + SHRT2_EXEV_CHANNEL_PD11, + SHRT2_EXEV_CHANNEL_PE3, + SHRT2_EXEV_CHANNEL_PE14, + SHRT2_EXEV_CHANNEL_PF10, + SHRT2_EXEV_CHANNEL_PG8, + SHRT2_EXEV_CHANNEL_PG15, + SHRT2_EXEV_CHANNEL_PH7, + SHRT2_EXEV_CHANNEL_PH8, + SHRT2_EXEV_CHANNEL_PH10, + SHRT2_EXEV_CHANNEL_PH11, + SHRT2_EXEV_CHANNEL_PH12, + SHRT2_EXEV_CHANNEL_PI11, + SHRT2_EXEV_CHANNEL_PJ2, + SHRT2_EXEV_CHANNEL_PJ14, + SHRT2_EXEV_CHANNEL_PK0, +}SHRT2_EXEV_CHANNEL; + +#define AFIO_SIP_DAT0 (0x00) +#define AFIO_SIP_DAT1 (0x01) +#define AFIO_SIP_DAT2 (0x02) +#define AFIO_SIP_DAT3 (0x03) +#define AFIO_SIP_DAT4 (0x04) +#define AFIO_SIP_DAT5 (0x05) +#define AFIO_SIP_DAT6 (0x06) +#define AFIO_SIP_DAT7 (0x07) +#define AFIO_SIP_MASK ((uint32_t)0x00000003U) +#define AFIO_SIP_Mode_NO_PULL (GPIO_PUPD_NO_PULL) /* No Pull-up or Pull-down activation */ +#define AFIO_SIP_Mode_PULL_UP (GPIO_PUPD_PULL_UP) /* Pull-up activation */ +#define AFIO_SIP_Mode_PULL_DOWN (GPIO_PUPD_PULL_DOWN) /* Pull-down activation */ + +/** AFIO SIP Drive strength config **/ +#define SIP_DC_2mA (GPIO_DS_2mA) +#define SIP_DC_4mA (GPIO_DS_4mA) +#define SIP_DC_8mA (GPIO_DS_8mA) +#define SIP_DC_12mA (GPIO_DS_12mA) + +/** AFIO SIP Slew_Rate **/ +#define SIP_Mode_FAST (GPIO_SR_FAST_SLEW) +#define SIP_Mode_SLOW (GPIO_SR_SLOW_SLEW) + +/** ADC switch config **/ +#define ADC_SW_PA0_C_MSK (AFIO_ADCSW_CFG_SWPA0_C) +#define ADC_SW_PA0_C_ADC2_INP0 (AFIO_ADCSW_CFG_SWPA0_C_0) +#define ADC_SW_PA0_C_ADC2_INP1 (AFIO_ADCSW_CFG_SWPA0_C_1) +#define ADC_SW_PA0_C_ADC1_INP0 (AFIO_ADCSW_CFG_SWPA0_C_2) +#define ADC_SW_PA0_C_ADC1_INP1 (AFIO_ADCSW_CFG_SWPA0_C_3) +#define ADC_SW_PA0_C_CLOSE ((uint32_t)0x00000000U) + +#define ADC_SW_PC2_C_MSK (AFIO_ADCSW_CFG_SWPC2_C) +#define ADC_SW_PC2_C_ADC2_INP0 (AFIO_ADCSW_CFG_SWPC2_C_0) +#define ADC_SW_PC2_C_ADC2_INP1 (AFIO_ADCSW_CFG_SWPC2_C_1) +#define ADC_SW_PC2_C_ADC3_INP0 (AFIO_ADCSW_CFG_SWPC2_C_2) +#define ADC_SW_PC2_C_ADC3_INP1 (AFIO_ADCSW_CFG_SWPC2_C_3) +#define ADC_SW_PC2_C_CLOSE ((uint32_t)0x00000000U) + +#define ADC_SW_PC3_C_MSK (AFIO_ADCSW_CFG_SWPC3_C) +#define ADC_SW_PC3_C_ADC2_INP1 (AFIO_ADCSW_CFG_SWPC3_C_0) +#define ADC_SW_PC3_C_ADC3_INP2 (AFIO_ADCSW_CFG_SWPC3_C_1) +#define ADC_SW_PC3_C_CLOSE ((uint32_t)0x00000000U) + +#define ADC_SW_PA1_C_MSK (AFIO_ADCSW_CFG_SWPA1_C) +#define ADC_SW_PA1_C_ADC2_INP1 (AFIO_ADCSW_CFG_SWPA1_C_0) +#define ADC_SW_PA1_C_ADC1_INP1 (AFIO_ADCSW_CFG_SWPA1_C_1) +#define ADC_SW_PA1_C_CLOSE ((uint32_t)0x00000000U) + +#define ADC_SW_PI15_MSK (AFIO_ADCSW_CFG_SWPI15) +#define ADC_SW_PI15_ADC2_INP17 (AFIO_ADCSW_CFG_SWPI15_0) +#define ADC_SW_PI15_ADC3_INP17 (AFIO_ADCSW_CFG_SWPI15_1) +#define ADC_SW_PI15_CLOSE ((uint32_t)0x00000000U) + +#define ADC_SW_VBAT_MSK (0x00000000) +#define ADC_SW_VBAT_ADC3_INP17 (AFIO_ADCSW_CFG_VBAT) + +#define ADC_SW_PJ0_MSK (0x00000000) +#define ADC_SW_PJ0_ADC2_INP16 (AFIO_ADCSW_CFG_SW_PJ0) + +#define ADC_SW_PJ3_MSK (0x00000000) +#define ADC_SW_PJ3_ADC3_INP18 (AFIO_ADCSW_CFG_SW_PJ3) + +#define ADC_SW_TEMP_MSK (0x00000000) +#define ADC_SW_TEMP_ADC3_INP18 (AFIO_ADCSW_CFG_SW_TEMP) + +#define ADC_SW_PJ4_MSK (0x00000000) +#define ADC_SW_PJ4_ADC3_INP19 (AFIO_ADCSW_CFG_SW_PJ4) + +#define ADC_SW_PJ5_MSK (0x00000000) +#define ADC_SW_PJ5_ADC2_INP16 (AFIO_ADCSW_CFG_SW_PJ5) + +#define ADC_SW_PJ6_MSK (0x00000000) +#define ADC_SW_PJ6_ADC3_INP18 (AFIO_ADCSW_CFG_SW_PJ6) + +#define ADC_SW_PJ7_MSK (0x00000000) +#define ADC_SW_PJ7_ADC3_INP19 (AFIO_ADCSW_CFG_SW_PJ7) + +#define ADC_SW_VREF_MSK (0x00000000) +#define ADC_SW_VREF_ADC3_INP19 (AFIO_ADCSW_CFG_VREF) + +#define ADC_SW_DAC246_OUT_MSK (AFIO_ADCSW_CFG_SW_DAC246_OUT) +#define ADC_SW_DAC2_OUT_ADC2_INP17 (AFIO_ADCSW_CFG_SW_DAC2_OUT) +#define ADC_SW_DAC4_OUT_ADC2_INP17 (AFIO_ADCSW_CFG_SW_DAC4_OUT) +#define ADC_SW_DAC6_OUT_ADC2_INP17 (AFIO_ADCSW_CFG_SW_DAC6_OUT) +#define ADC_SW_DAC246_OUT_ADC2_DISABLE ((uint32_t)0x00000000U) + +#define ADC_SW_DAC135_OUT_MSK (AFIO_ADCSW_CFG_SW_DAC135_OUT) +#define ADC_SW_DAC1_OUT_ADC2_INP16 (AFIO_ADCSW_CFG_SW_DAC1_OUT) +#define ADC_SW_DAC3_OUT_ADC2_INP16 (AFIO_ADCSW_CFG_SW_DAC3_OUT) +#define ADC_SW_DAC5_OUT_ADC2_INP16 (AFIO_ADCSW_CFG_SW_DAC5_OUT) +#define ADC_SW_DAC135_OUT_ADC2_DISABLE ((uint32_t)0x00000000U) + +typedef enum +{ + AFIO_ADC_1 = 2U, + AFIO_ADC_2 = 1U, + AFIO_ADC_3 = 0U +}AFIO_ADC_NUM; + +typedef enum +{ + AFIO_ADC_ETRR = 0U, + AFIO_ADC_ETRI = 1U +}AFIO_ADC_ETRType; + +typedef enum +{ + AFIO_ADC_TRIG_EXTI_0 = 0x00U, + AFIO_ADC_TRIG_EXTI_1 = 0x01U, + AFIO_ADC_TRIG_EXTI_2, + AFIO_ADC_TRIG_EXTI_3, + AFIO_ADC_TRIG_EXTI_4, + AFIO_ADC_TRIG_EXTI_5, + AFIO_ADC_TRIG_EXTI_6, + AFIO_ADC_TRIG_EXTI_7, + AFIO_ADC_TRIG_EXTI_8, + AFIO_ADC_TRIG_EXTI_9, + AFIO_ADC_TRIG_EXTI_10, + AFIO_ADC_TRIG_EXTI_11, + AFIO_ADC_TRIG_EXTI_12, + AFIO_ADC_TRIG_EXTI_13, + AFIO_ADC_TRIG_EXTI_14, + AFIO_ADC_TRIG_EXTI_15, +}AFIO_ADC_Trig_RemapType; + +typedef enum +{ + AFIO_SDRAM_PIN_PA4 = 0, + AFIO_SDRAM_PIN_PA5 = 1, + AFIO_SDRAM_PIN_PA7, + AFIO_SDRAM_PIN_PB5, + AFIO_SDRAM_PIN_PB6, + AFIO_SDRAM_PIN_PB14, + AFIO_SDRAM_PIN_PB15, + AFIO_SDRAM_PIN_PC0, + AFIO_SDRAM_PIN_PC2, + AFIO_SDRAM_PIN_PC3, + AFIO_SDRAM_PIN_PC4, + AFIO_SDRAM_PIN_PC5, + AFIO_SDRAM_PIN_PC12, + AFIO_SDRAM_PIN_PD0, + AFIO_SDRAM_PIN_PD1, + AFIO_SDRAM_PIN_PD2, + AFIO_SDRAM_PIN_PD8, + AFIO_SDRAM_PIN_PD9, + AFIO_SDRAM_PIN_PD10, + AFIO_SDRAM_PIN_PD14, + AFIO_SDRAM_PIN_PD15, + AFIO_SDRAM_PIN_PE0, + AFIO_SDRAM_PIN_PE1, + AFIO_SDRAM_PIN_PE7, + AFIO_SDRAM_PIN_PE8, + AFIO_SDRAM_PIN_PE9, + AFIO_SDRAM_PIN_PE10, + AFIO_SDRAM_PIN_PE11, + AFIO_SDRAM_PIN_PE12, + AFIO_SDRAM_PIN_PE13, + AFIO_SDRAM_PIN_PE14, + AFIO_SDRAM_PIN_PE15, + + AFIO_SDRAM_PIN_PF0, + AFIO_SDRAM_PIN_PF1, + AFIO_SDRAM_PIN_PF2, + AFIO_SDRAM_PIN_PF3, + AFIO_SDRAM_PIN_PF4, + AFIO_SDRAM_PIN_PF5, + AFIO_SDRAM_PIN_PF11, + AFIO_SDRAM_PIN_PF12, + AFIO_SDRAM_PIN_PF13, + AFIO_SDRAM_PIN_PF14, + AFIO_SDRAM_PIN_PF15, + AFIO_SDRAM_PIN_PG0, + AFIO_SDRAM_PIN_PG1, + AFIO_SDRAM_PIN_PG2, + AFIO_SDRAM_PIN_PG4, + AFIO_SDRAM_PIN_PG5, + AFIO_SDRAM_PIN_PG8, + AFIO_SDRAM_PIN_PG15, + AFIO_SDRAM_PIN_PH2, + AFIO_SDRAM_PIN_PH3, + AFIO_SDRAM_PIN_PH5, + AFIO_SDRAM_PIN_PH6, + AFIO_SDRAM_PIN_PH7, + AFIO_SDRAM_PIN_PH8, + AFIO_SDRAM_PIN_PH9, + AFIO_SDRAM_PIN_PH10, + AFIO_SDRAM_PIN_PH11, + AFIO_SDRAM_PIN_PH12, + AFIO_SDRAM_PIN_PH13, + AFIO_SDRAM_PIN_PH14, + AFIO_SDRAM_PIN_PH15, + AFIO_SDRAM_PIN_PI0, + + AFIO_SDRAM_PIN_PI1, + AFIO_SDRAM_PIN_PI2, + AFIO_SDRAM_PIN_PI3, + AFIO_SDRAM_PIN_PI4, + AFIO_SDRAM_PIN_PI5, + AFIO_SDRAM_PIN_PI6, + AFIO_SDRAM_PIN_PI7, + AFIO_SDRAM_PIN_PI9, + AFIO_SDRAM_PIN_PI10 +} AFIO_SDRAM_PIN; + + +/** GPIO_Exported_Functions **/ +void GPIO_DeInit( GPIO_Module *GPIOx); +void GPIO_AFIODeInit( void ); +void GPIO_InitStruct(GPIO_InitType* InitStruct); +void GPIO_InitPeripheral( GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit( GPIO_Module* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData( GPIO_Module* GPIOx ); +uint8_t GPIO_ReadOutputDataBit( GPIO_Module* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData( GPIO_Module* GPIOx ); +void GPIO_SetBits( GPIO_Module* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits( GPIO_Module* GPIOx, uint16_t GPIO_Pin ); +void GPIO_WriteBit( GPIO_Module* GPIOx, uint16_t GPIO_Pin, Bit_OperateType BitVal); +void GPIO_Write( GPIO_Module* GPIOx, uint16_t data_value ); +void GPIO_TogglePin(GPIO_Module *GPIOx, uint16_t Pin); +void GPIO_ConfigPinLock( GPIO_Module* GPIOx, uint16_t GPIO_Pin); + +void GPIO_ConfigEXTILine(uint8_t EXTI_Line, uint8_t GPIO_PinSource); +void AFIO_ConfigEXTIFilter(uint32_t EXTI_Filter); + +void AFIO_ConfigADCExtLineTrigSource(AFIO_ADC_NUM ADC_num, AFIO_ADC_ETRType ADCETRType, AFIO_ADC_Trig_RemapType ADCTrigRemap); + +void GPIO_AFIOInitDefault(void); +void AFIO_ConfigSHRT1EXEVPin(SHRT1_EXEV_CHANNEL channel_pin, SHRT_EXEV_CHANNEL_NUM channel_num); +void AFIO_ConfigSHRT1FALTPin(SHRT1_FAULT_CHANNEL channel_pin, SHRT_FAULT_CHANNEL_NUM channel_num); +void AFIO_ConfigSHRT2EXEVPin(SHRT2_EXEV_CHANNEL channel_pin, SHRT_EXEV_CHANNEL_NUM channel_num); +void AFIO_ConfigSHRT2FALTPin(SHRT2_FAULT_CHANNEL channel_pin, SHRT_FAULT_CHANNEL_NUM channel_num); +void AFIO_ConfigSIPFLASHSEL(uint32_t AFIO_FLASH); +void AFIO_ConfigSIPSDRAMPrior(uint32_t priority); +void AFIO_ConfigSPII2SMode(uint32_t AFIO_SPIx_I2Sx, uint32_t PADS_Mode); +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS, uint32_t NSS_Mode); +void AFIO_ConfigXSPIBigEndian(uint32_t xspi_endian, uint32_t Endian); +void AFIO_ConfigIOFilter(uint8_t Filter_Cycle); +void AFIO_ConfigPinAnFilter(GPIO_Module* GPIOx, uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinFilter(GPIO_Module* GPIOx, uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigHSMODE(GPIO_Module* GPIOx, uint32_t Pin, FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOA(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOB(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOC(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOF(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOH(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOI(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigPinTol5VGPIOJ(uint32_t Pin,FunctionalState cmd); +void AFIO_ConfigSDRAMDSNRemap(AFIO_SDRAM_PIN pin, FunctionalState cmd); +void AFIO_ConfigSDRAMDSPRemap(AFIO_SDRAM_PIN pin, FunctionalState cmd); +void AFIO_ConfigSDRAMVREFRemap(AFIO_SDRAM_PIN pin, FunctionalState cmd); +void AFIO_ConfigSDRAMVREFData(uint8_t reg_index, uint32_t data); +void AFIO_ConfigSDRAMDSNData(uint8_t reg_index, uint32_t data); +void AFIO_ConfigSDRAMDSPData(uint8_t reg_index, uint32_t data); +void AFIO_ConfigETH1Mode(uint32_t ETH1_PHY_sel); +void AFIO_ConfigETH2Mode(uint32_t ETH2_PHY_sel); +void AFIO_ConfigFEMCNANDSRAM(uint32_t Nand_Sram_sel); +void AFIO_FEMCNOByteStrobe(uint32_t Byte_Strobes_sel); +void AFIO_I2SFullpuplexSel(uint32_t AFIO_clk_sel); +void AFIO_SDMMCClkSel(uint32_t AFIO_clk_sel, FunctionalState cmd); +void AFIO_ConfigXSPIDecNonce(uint8_t nonce_num, u32 data); +void AFIO_SIPInitPeripheral(uint8_t sip_index, uint32_t pupd, uint32_t slew_rate, uint32_t driver_stength); + +void AFIO_ADCSWPJ0Enable(FunctionalState Cmd); +void AFIO_ADCSWPJ3Enable(FunctionalState Cmd); +void AFIO_ADCSWPJ4Enable(FunctionalState Cmd); +void AFIO_ADCSWPJ5Enable(FunctionalState Cmd); +void AFIO_ADCSWPJ6Enable(FunctionalState Cmd); +void AFIO_ADCSWPJ7Enable(FunctionalState Cmd); +void AFIO_ADCSWTEMPEnable(FunctionalState Cmd); +void AFIO_ADCSWVBATEnable(FunctionalState Cmd); +void AFIO_ADCSWVREFEnable(FunctionalState Cmd); + +void AFIO_ConfigADCSWDAC246OUT(uint32_t ADCsw); +void AFIO_ConfigADCSWDAC135OUT(uint32_t ADCsw); +void AFIO_ConfigADCSWPA0_C(uint32_t ADCsw); +void AFIO_ConfigADCSWPA1_C(uint32_t ADCsw); +void AFIO_ConfigADCSWPC2_C(uint32_t ADCsw); +void AFIO_ConfigADCSWPC3_C(uint32_t ADCsw); +void AFIO_ConfigADCSWPI15(uint32_t ADCsw); + + +#ifdef __cplusplus +} + +#endif + +#endif /* __N32H76X_78X_GPIO_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2c.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2c.h new file mode 100644 index 0000000000..d3998e7a0e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2c.h @@ -0,0 +1,430 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_i2c.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_I2C_H__ +#define __N32H76X_78X_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** n32h76x_78x_StdPeriph_Driver **/ + +/** I2C Init structure definition **/ + +typedef struct +{ + uint32_t Timing; /* Specifies the I2C_BUSTIM_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t HSTiming; /* Specifies the I2C_HSBUSTIM_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /* Specifies if 7-bit or 10-bit addressing mode is selected. */ + + uint32_t DualAddressMode; /* Specifies if dual addressing mode is selected. */ + + uint32_t OwnAddress2; /* Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /* Specifies the acknowledge mask address second device own address if dual addressing mode is selected */ + + uint32_t GeneralCallMode; /* Specifies if general call mode is selected. */ + + uint32_t NoStretchMode; /* Specifies if nostretch mode is selected. */ + +} I2C_InitType; + + + +#define I2C_REG_BIT_MASK ((uint32_t)0x00000000U) +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) +#define CTRL1_CLEAR_MASK (~(I2C_CTRL1_GENC|I2C_CTRL1_NOSTRCH)) +#define CTRL2_CLEAR_MASK (~(I2C_CTRL2_ADR10|I2C_CTRL2_AUTOSTOP|I2C_CTRL2_NAK)) + +/** High speed setting with sys_clk = 30Mhz **/ +#define I2C_H_SPEED_2_7_4_MHZ 0x00010204 +#define I2C_H_SPEED_3_MHZ 0x00010104 +#define I2C_H_SPEED_3_3_4_MHZ 0x00010103 +#define I2C_H_SPEED_3_7_7_MHZ 0x00010102 +#define I2C_TIMING 0x50210607 //48Mhz Sys_Clk :400Khz + +/** I2C_ADDRESSING_MODE I2C Addressing Mode **/ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) + +/** I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode **/ +#define I2C_DUALADDRESS_DISABLE (I2C_REG_BIT_MASK) +#define I2C_DUALADDRESS_ENABLE I2C_ADR2_AD2EN + +/** I2C AD2MASK mask **/ +#define I2C_ADDRESS2MASK_NONE (I2C_REG_BIT_MASK) +#define I2C_ADDRESS2MASK_1 (I2C_ADR2_AD2MSK_0) +#define I2C_ADDRESS2MASK_2_1 (I2C_ADR2_AD2MSK_1) +#define I2C_ADDRESS2MASK_3_1 (I2C_ADR2_AD2MSK_0|I2C_ADR2_AD2MSK_1) +#define I2C_ADDRESS2MASK_4_1 (I2C_ADR2_AD2MSK_2) +#define I2C_ADDRESS2MASK_5_1 (I2C_ADR2_AD2MSK_0|I2C_ADR2_AD2MSK_2) +#define I2C_ADDRESS2MASK_6_1 (I2C_ADR2_AD2MSK_1|I2C_ADR2_AD2MSK_2) +#define I2C_ADDRESS2MASK_7_1 (I2C_ADR2_AD2MSK) + +/** I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode **/ +#define I2C_GENERALCALL_DISABLE (I2C_REG_BIT_MASK) +#define I2C_GENERALCALL_ENABLE I2C_CTRL1_GENC + +/** I2C_NOSTRCH_MODE I2C No-Stretch Mode **/ +#define I2C_NOSTRCH_DISABLE (I2C_REG_BIT_MASK) +#define I2C_NOSTRCH_ENABLE I2C_CTRL1_NOSTRCH + + +/** I2C Private Defines **/ + +/** I2C SPE mask **/ +#define CTRL1_SPEN_SET I2C_CTRL1_I2CEN +#define CTRL1_SPEN_RESET (~I2C_CTRL1_I2CEN) + +/** I2C DF mask **/ +#define CTRL1_DF_SET I2C_CTRL1_DF +/** I2C DFX filter mask **/ +#define CTRL1_DFX_SET I2C_CTRL1_DFX + +#define CTRL1_DF10_RESET (~(I2C_CTRL1_DFX | I2C_CTRL1_DF)) + +/** I2C AF mask **/ +#define CTRL1_AF_SET I2C_CTRL1_AFOFF +#define CTRL1_AF_RESET (~I2C_CTRL1_AFOFF) + +/** I2C DMA TRANSMISSION mask **/ +#define CTRL1_DMAWREN_TRANSMISSION_SET I2C_CTRL1_DMAWREN +#define CTRL1_DMAWREN_TRANSMISSION_RESET (~I2C_CTRL1_DMAWREN) + +/** I2C DMA RECEPTION mask **/ +#define CTRL1_DMARDEN_RECEPTION_SET I2C_CTRL1_DMARDEN +#define CTRL1_DMARDEN_RECEPTION_RESET (~I2C_CTRL1_DMARDEN) + +/** I2C (SBCTL)SLAVE BYTE CONTROL mask **/ +#define CTRL1_SBCTL_SET I2C_CTRL1_SBCTL +#define CTRL1_SBCTL_RESET (~I2C_CTRL1_SBCTL) + +/** I2C NOSTRETCH mask **/ +#define CTRL1_NOSTRETCH_SET I2C_CTRL1_NOSTRCH +#define CTRL1_NOSTRETCH_RESET (~I2C_CTRL1_NOSTRCH) + +/** I2C GENC mask **/ +#define CTRL1_GENC_SET I2C_CTRL1_GENC +#define CTRL1_GENC_RESET (~I2C_CTRL1_GENC) + +/** I2C SMBH mask **/ +#define CTRL1_SMBH_SET I2C_CTRL1_SMBH +#define CTRL1_SMBH_RESET (~I2C_CTRL1_SMBH) + +/** I2C SMBD mask **/ +#define CTRL1_SMBD_SET I2C_CTRL1_SMBD +#define CTRL1_SMBD_RESET (~I2C_CTRL1_SMBD) + +/** I2C ALRTEN mask **/ +#define CTRL1_ALRTEN_SET I2C_CTRL1_ALRTEN +#define CTRL1_ALRTEN_RESET (~I2C_CTRL1_ALRTEN) + +/** I2C CRC mask **/ +#define CTRL1_CRCEN_SET I2C_CTRL1_CRCEN +#define CTRL1_CRCEN_RESET (~I2C_CTRL1_CRCEN) + +/** I2C RX FIFO INTERRUPT mask **/ +#define CTRL1_FRXIE_SET I2C_CTRL1_FRXIE +#define CTRL1_FRXIE_RESET (~I2C_CTRL1_FRXIE) + +/** I2C TX FIFO INTERRUPT mask **/ +#define CTRL1_FTXIE_SET I2C_CTRL1_FTXIE +#define CTRL1_FTXIE_RESET (~I2C_CTRL1_FTXIE) + +/** I2C NAK mask **/ +#define STSINT_ADRRCV_MASK I2C_STSINT_ADRRCV + +/** I2C MASTER TRANSFER DIRECTION **/ +#define CTRL2_MASTER_WRITE (~I2C_CTRL2_RD_RWNN) +#define CTRL2_MASTER_READ I2C_CTRL2_RD_RWNN + +/** I2C 10/7 addressing mode **/ +#define CTRL2_ADR10 I2C_CTRL2_ADR10 +#define CTRL2_ADR7 (~I2C_CTRL2_ADR10) + +/** I2C HDR10 mask **/ +#define CTRL2_HDR10_ENABLE I2C_CTRL2_HDR10 +#define CTRL2_HDR10_DISABLE (~I2C_CTRL2_HDR10) + +/** I2C START mask **/ +#define CTRL2_START_ENABLE I2C_CTRL2_START +#define CTRL2_START_DISABLE (~I2C_CTRL2_START) + +/** I2C STOP mask **/ +#define CTRL2_STOP_ENABLE I2C_CTRL2_STOP +#define CTRL2_STOP_DISABLE (~I2C_CTRL2_STOP) + +/** I2C NAK mask **/ +#define CTRL2_NACK I2C_CTRL2_NAK +#define CTRL2_ACK (~I2C_CTRL2_NAK) + +/** I2C REFILL **/ +#define CTRL2_REFILL_ENABLE I2C_CTRL2_REFILL +#define CTRL2_REFILL_DISABLE (~I2C_CTRL2_REFILL) + +/** I2C AUTOSTOP **/ +#define CTRL2_AUTO_STOP I2C_CTRL2_AUTOSTOP +#define CTRL2_SOFTWARE_STOP (~I2C_CTRL2_AUTOSTOP) + +/** I2C CRCBYTE mask **/ +#define CTRL2_CRCBYTE_ENABLE I2C_CTRL2_CRCBYTE +#define CTRL2_CRCBYTE_DISABLE (~I2C_CTRL2_CRCBYTE) + +/** I2C own ADR1 mask **/ +#define ADR1_OWN_ADR1_ENABLE I2C_ADR1_AD1EN +#define ADR1_OWN_ADR1_DISABLE (~I2C_ADR1_AD1EN) + +/** I2C AD1MODE mask **/ +#define ADR1MODE_10_BIT_ADDR I2C_ADR1_AD1MODE +#define ADR1MODE_7_BIT_ADDR (~I2C_ADR1_AD1MODE) + +/** I2C AD2 mask **/ +#define ADR2_ENABLE I2C_ADR2_AD2EN +#define ADR2_DISABLE (~I2C_ADR2_AD2EN) + +/** I2C ADD2 mask **/ +#define ADR2_AD2_RESET (~I2C_ADR2_AD2) +#define ADR2_AD2_SET I2C_ADR2_AD2 + +/** I2C TMOUTA idle clok timeout detection **/ +#define TMOUTA_SCL_LOW_TMOUT (~I2C_TMOUTR_TMIDLE) +#define TMOUTA_SCL_SDA_LOW_TMOUT I2C_TMOUTR_TMIDLE + +/** I2C TMOUTEN mask **/ +#define TMOUTEN_ENABLE I2C_TMOUTR_TMOUTEN +#define TMOUTEN_DISABLE (~I2C_TMOUTR_TMOUTEN) + +/** I2C TMEXTEN mask **/ +#define TMEXTEN_ENABLE I2C_TMOUTR_TMEXTEN +#define TMEXTEN_DISABLE (~I2C_TMOUTR_TMEXTEN) + +/** I2C TX FIFO active **/ +#define TFE_ENABLE I2C_FIFOCSR_TFE +#define TFE_DISABLE (~I2C_FIFOCSR_TFE) + +/** I2C RX FIFO active **/ +#define RFE_ENABLE I2C_FIFOCSR_RFE +#define RFE_DISABLE (~I2C_FIFOCSR_RFE) + +/** I2C TX_ILEVEL **/ +#define TX_ILEVEL_1 I2C_FIFOCSR_TX_ILEVEL01 +#define TX_ILEVEL_2 I2C_FIFOCSR_TX_ILEVEL02 +#define TX_ILEVEL_3 I2C_FIFOCSR_TX_ILEVEL03 +#define TX_ILEVEL_4 I2C_FIFOCSR_TX_ILEVEL04 +#define TX_ILEVEL_5 I2C_FIFOCSR_TX_ILEVEL05 +#define TX_ILEVEL_6 I2C_FIFOCSR_TX_ILEVEL06 +#define TX_ILEVEL_7 I2C_FIFOCSR_TX_ILEVEL07 +#define TX_ILEVEL_8 I2C_FIFOCSR_TX_ILEVEL08 + +/** I2C RX_ILEVEL **/ +#define RX_ILEVEL_1 I2C_FIFOCSR_RX_ILEVEL01 +#define RX_ILEVEL_2 I2C_FIFOCSR_RX_ILEVEL02 +#define RX_ILEVEL_3 I2C_FIFOCSR_RX_ILEVEL03 +#define RX_ILEVEL_4 I2C_FIFOCSR_RX_ILEVEL04 +#define RX_ILEVEL_5 I2C_FIFOCSR_RX_ILEVEL05 +#define RX_ILEVEL_6 I2C_FIFOCSR_RX_ILEVEL06 +#define RX_ILEVEL_7 I2C_FIFOCSR_RX_ILEVEL07 +#define RX_ILEVEL_8 I2C_FIFOCSR_RX_ILEVEL08 + +/** I2C QUICK COMMAND **/ +#define QCMD_ENABLE I2C_QCMD_QCMDEN +#define QCMD_DISABLE (~I2C_QCMD_QCMDEN) + +#define QCMDAD_MASK (~I2C_QCMD_QCMDAD) + +/** I2C SCL ANALOG FILTER mask **/ +#define SCLAFENN_ENABLE I2C_GFLTRCTRL_SCLAFENN +#define SCLAFENN_DISABLE (~I2C_GFLTRCTRL_SCLAFENN) + +/** I2C bus timeout **/ +#define I2C_TMOUTA_MASK (~I2C_TMOUTR_TMOUTA) +#define I2C_TMOUTB_MASK (~I2C_TMOUTR_TMOUTB) + +#define I2C_TMOUTA_DETECT_SCL_LOW (I2C_REG_BIT_MASK) +#define I2C_TMOUTA_DETECT_BUS_IDLE (I2C_TMOUTR_TMIDLE) + +/** I2C Analogue Filter Width **/ +/* I2C GFLTRCTRL mask */ +#define I2C_SDAAFW_MASK (~I2C_GFLTRCTRL_SDAAFW) +#define I2C_SCLAFW_MASK (~I2C_GFLTRCTRL_SCLAFW) + +#define I2C_ANALOG_FILTER_WIDTH_5NS (I2C_REG_BIT_MASK) +#define I2C_ANALOG_FILTER_WIDTH_15NS (I2C_GFLTRCTRL_SDAAFW_0) +#define I2C_ANALOG_FILTER_WIDTH_25NS (I2C_GFLTRCTRL_SDAAFW_1) +#define I2C_ANALOG_FILTER_WIDTH_35NS (I2C_GFLTRCTRL_SDAAFW) + +/** I2C SDA ANALOG FILTER mask **/ +#define SDAAFENN_ENABLE I2C_GFLTRCTRL_SDAAFENN +#define SDAAFENN_DISABLE (~I2C_GFLTRCTRL_SDAAFENN) + +#define I2C_SADR_RWN_MASK (~(I2C_CTRL2_RWN|I2C_CTRL2_SADR)) +#define I2C_SADR_MASK (I2C_CTRL2_SADR) +#define I2C_DIRECTION_SEND (I2C_REG_BIT_MASK) +#define I2C_DIRECTION_RECV (I2C_CTRL2_RWN) + +/** I2C Flag definition **/ +#define I2C_FLAG_WRE I2C_STSINT_WRE +#define I2C_FLAG_WRAVL I2C_STSINT_WRAVL +#define I2C_FLAG_RDAVL I2C_STSINT_RDAVL +#define I2C_FLAG_ADR I2C_STSINT_ADR +#define I2C_FLAG_NAKF I2C_STSINT_NAKF +#define I2C_FLAG_STOPF I2C_STSINT_STOPF +#define I2C_FLAG_TFC I2C_STSINT_TFC +#define I2C_FLAG_TFCR I2C_STSINT_TFCR +#define I2C_FLAG_BSER I2C_STSINT_BSER +#define I2C_FLAG_ABLO I2C_STSINT_ABLO +#define I2C_FLAG_OVF I2C_STSINT_OVF +#define I2C_FLAG_CRCERR I2C_STSINT_CRCERR +#define I2C_FLAG_TMOUT I2C_STSINT_TMOUT +#define I2C_FLAG_ALRT I2C_STSINT_ALRT +#define I2C_FLAG_QADR I2C_STSINT_QADR +#define I2C_FLAG_BUSY I2C_STSINT_BUSY +#define I2C_FLAG_DIR I2C_STSINT_DIR +#define I2C_FLAG_FRXNE I2C_STSINT_FRXNE +#define I2C_FLAG_FTXIS I2C_STSINT_FTXIS + +/** I2C_interrupts_definition **/ +#define I2C_INT_WDR I2C_CTRL1_WDRIE /* TX interrupt enable */ +#define I2C_INT_RDR I2C_CTRL1_RDRIE /* RX interrupt enable */ +#define I2C_INT_ADR I2C_CTRL1_ADRIE +#define I2C_INT_NACK I2C_CTRL1_NAKIE /* Address match interrupt enable */ +#define I2C_INT_STOP I2C_CTRL1_STOPIE /* Stop detection interrupt enable */ +#define I2C_INT_TFC I2C_CTRL1_TFCIE /* Transfer complete interrupt enable */ +#define I2C_INT_ERR I2C_CTRL1_ERRIE /* Error interrupt enable */ +#define I2C_INT_RXFIFO I2C_CTRL1_FRXIE /* FIFO RX interrupt enable */ +#define I2C_INT_TXFIFO I2C_CTRL1_FTXIE /* FIFO TX interrupt enable */ + +/* I2C BYTENUM byte number mask */ +#define BYTENUM_Mask (~I2C_CTRL2_BYTECNT) +/* I2C FIFO_TX_ILEVEL mask */ +#define FIFO_TX_ILEVEL_Mask (~I2C_FIFOCSR_TXILEVEL) +/* I2C FIFO_RX_ILEVEL mask */ +#define FIFO_RX_ILEVEL_Mask (~I2C_FIFOCSR_RXILEVEL) +/* I2C FIFO_TX_ILEVEL mask */ +#define FIFO_TX_FLEVEL_Mask (I2C_FIFOCSR_TXFLEVEL) +/* I2C FIFO_RX_ILEVEL mask */ +#define FIFO_RX_FLEVEL_Mask (I2C_FIFOCSR_RXFLEVEL) + +/** I2C_Exported_Macros **/ + +/** I2C_Exported_Functions **/ +void I2C_DeInit(I2C_Module* I2Cx); +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct); +void I2C_InitStruct(I2C_InitType* I2C_StructInit); +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigSendAddress(I2C_Module* I2Cx, uint32_t address, uint32_t direction); +void I2C_Enable10bitAddressHeader(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableAutomaticEnd(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableReload(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address); +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableSlaveByteControl(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableSMBusAlert(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableSMBusDefaultAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableSMBusHostAddr(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data); +uint8_t I2C_RecvData(I2C_Module* I2Cx); +void I2C_SendCRC(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableCRC(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableQuickCommand(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_ConfigQuickCommandAddr(I2C_Module* I2Cx, uint8_t Address); +void I2C_EnableTXFIFO(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableRXFIFO(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableTXDMA(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableRXDMA(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_SetTransferByteNumber(I2C_Module* I2Cx, uint8_t Number_Of_bytes); +void I2C_SetTXFIFO_ILEVEL(I2C_Module* I2Cx, uint8_t TX_ILEVEL); +void I2C_SetRXFIFO_ILEVEL(I2C_Module* I2Cx, uint8_t RX_ILEVEL); +void I2C_EnableSCLTimeoutDetection(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableExtenClkTimeout(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_SetBusTimeoutA(I2C_Module* I2Cx, uint32_t bus_timeout); +void I2C_SetBusTimeoutB(I2C_Module* I2Cx, uint32_t bus_timeout); +void I2C_ConfigIdleClockTimeout(I2C_Module* I2Cx, uint32_t bus_timeout); +void I2C_EnableAnalogFilter(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableSDAAnalogFilter(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_EnableSCLAnalogFilter(I2C_Module* I2Cx, FunctionalState Cmd); +void I2C_SetSCLAnalogFilterWidth(I2C_Module* I2Cx, uint32_t width); +void I2C_SetSDAAnalogFilterWidth(I2C_Module* I2Cx, uint32_t width); +void I2C_SetDigitalFilterWidth(I2C_Module* I2Cx, uint32_t width); +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); +void I2C_ConfigInt(I2C_Module* I2Cx, uint32_t I2C_IT, FunctionalState Cmd); + +uint8_t I2C_GetTXFIFO_FLEVEL(I2C_Module* I2Cx); +uint8_t I2C_GetRXFIFO_FLEVEL(I2C_Module* I2Cx); +uint8_t I2C_GetCRC(I2C_Module* I2Cx); +uint8_t I2C_GetReceiveAddress(I2C_Module* I2Cx); +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_I2C_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2s.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2s.h new file mode 100644 index 0000000000..19e3495aa0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_i2s.h @@ -0,0 +1,272 @@ +/** ---------------------------------------------------------------------------- + * Nationz Technology Software Support - NATIONZ - + * ----------------------------------------------------------------------------- + * Copyright (c) 2019, Nationz Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Nationz's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ----------------------------------------------------------------------------- + */ +/** **************************************************************************** + * @copyright Nationz Co.,Ltd + * Copyright (c) 2019 All Rights Reserved + ******************************************************************************* + * @file ns3610cm4_spi.h + * @author + * @date + * @version v1.0.0 + * @brief + ******************************************************************************/ +#ifndef __NS3610CM4_I2S_H +#define __NS3610CM4_I2S_H + +/* Includes ------------------------------------------------------------------*/ +#include "n32h76x_78x.h" +#include "n32h76x_78x_rcc.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** Bit definition for I2S_RX_FIFO register **/ +#define I2S_RX_FIFO ((uint16_t)0xFFFF) + +/** Bit definition for I2S_FIFO_BURST_NUM register **/ +#define I2S_FIFO_BURST_NUM_TX ((uint16_t)0x0007) /* I2S TX FIFO Half Empty Threshold Value Configure */ +#define I2S_FIFO_BURST_NUM_RX ((uint16_t)0x0070) /* I2S RX FIFO Half Full Threshold Value Configure */ + +/** Bit definition for I2S_FIFO_NUM register **/ +#define I2S_FIFO_NUM_TX_CNT ((uint16_t)0x000F) /* I2S TX FIFO Valid Data Number */ +#define I2S_FIFO_NUM_RX_CNT ((uint16_t)0x00F0) /* I2S RX FIFO Valid Data Number */ + +/** Bit definition for I2S_TRANS_NUM register **/ +#define I2S_TRANS_NUM ((uint16_t)0xFFFF) + +/** Bit definition for I2S_I2SCFG register **/ +#define I2SCFG_I2SEN ((uint16_t)0x0001) /* I2S Enable */ +#define SPI_I2SCFG_MOD ((uint16_t)0x0002) /* I2S Mode */ + +#define I2SCFG_STD ((uint16_t)0x000C) /* STD[3:2] bits (I2S standard selection) */ +#define I2SCFG_STDSEL1 ((uint16_t)0x0008) /* Bit 1 */ +#define I2SCFG_STDSEL0 ((uint16_t)0x0004) /* Bit 0 */ + +#define I2SCFG_TDATLEN ((uint16_t)0x00C0) /* TDATLEN[1:0] bits (Data length to be transferred) */ +#define I2SCFG_TDATLEN1 ((uint16_t)0x0080) /* Bit 1 */ +#define I2SCFG_TDATLEN0 ((uint16_t)0x0040) /* Bit 0 */ + +#define I2SCFG_CHLEN ((uint16_t)0x0100) /* Channel Length */ +#define I2SCFG_PCMFSYNC ((uint16_t)0x0200) /* PCM frame synchronization */ +#define I2SCFG_CLKPOL ((uint16_t)0x0400) /* steady state clock polarity */ +#define I2SCFG_ERR_BYPASS ((uint16_t)0x0800) /* PCM Long for 13bit is No bypass */ + +/** Bit definition for SPI_I2SPR register **/ +#define I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define I2SPR_MCKOEN ((uint16_t)0x0800) /* Master Clock Output Enable */ + +/* -------------------------- Up is the Bit Define -------------------------------- */ + +/** I2s Mode select**/ +#define I2S_MODE_SEL_MASK (~SPI_I2SCFG_MOD) /* selet spi/I2S mode bit */ +#define SEL_SPI_MODE ((uint16_t)0x0000) +#define SEL_I2S_MODE (SPI_I2SCFG_MOD) + + +#define I2SCFG_CFG ((uint16_t)0x0030) /* I2S Mode Configure */ +#define I2SCFG_CFG1 ((uint16_t)0x0020) /* I2S Mode Configure Bit */ +#define I2SCFG_CFG0 ((uint16_t)0x0010) /* I2S Mode Configure Bit */ +/** I2sMode **/ +#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000U) +#define I2S_MODE_SlAVE_RX (I2SCFG_CFG0) +#define I2S_MODE_MASTER_TX (I2SCFG_CFG1) +#define I2S_MODE_MASTER_RX (I2SCFG_CFG0 | I2SCFG_CFG1) +#define I2S_MODE_MASK (I2SCFG_CFG) /* MODCFG bit Mask */ + + + +/** I2S_EXT_DMA_transfer_requests **/ +#define I2S_EXT_DMA_TX ((uint16_t)0x0004U) +#define I2S_EXT_DMA_RX ((uint16_t)0x0002U) +/** I2S_EXT_interrupts_definition **/ +#define I2S_EXT_INT_TEINTEN ((uint16_t)0x0010U) +#define I2S_EXT_INT_RNEINTEN ((uint16_t)0x0020U) +#define I2S_EXT_INT_ERRINTEN ((uint16_t)0x0040U) + +/** I2S_EXT_flags_definition **/ +#define I2S_EXT_TE_FLAG ((uint16_t)0x0001U) +#define I2S_EXT_RNE_FLAG ((uint16_t)0x0002U) +#define I2S_EXT_BUSY_FLAG ((uint16_t)0x0004U) +#define I2S_EXT_OVER_FLAG ((uint16_t)0x0020U) +#define I2S_EXT_UNDER_FLAG ((uint16_t)0x0040U) +#define I2S_EXT_CHSIDE_FLAG ((uint16_t)0x0080U) + +/** I2S_interrupts_definition **/ +#define I2S_INT_TE ((uint8_t)0x40) +#define I2S_INT_RNE ((uint8_t)0x51) +#define I2S_INT_ERR ((uint8_t)0x60) +#define I2S_INT_RXONLYC ((uint8_t)0xEC) +#define I2S_INT_RXFIFOF ((uint8_t)0xCB) +#define I2S_INT_RXFIFOHF ((uint8_t)0xB9) +#define I2S_INT_TXFIFOHE ((uint8_t)0xA8) +#define I2S_INT_MODERR ((uint8_t)0x64) +#define I2S_INT_CRCERR ((uint8_t)0x63) +#define I2S_INT_OVERERR ((uint8_t)0x65) +#define I2S_INT_UNDER ((uint8_t)0x66) + + +/** I2S_flags_definition **/ +#define I2S_TE_FLAG ((uint16_t)0x0001U) +#define I2S_RNE_FLAG ((uint16_t)0x0002U) +#define I2S_BUSY_FLAG ((uint16_t)0x0004U) +#define I2S_CRCERR_FLAG ((uint16_t)0x0008U) +#define I2S_MODERR_FLAG ((uint16_t)0x0010U) +#define I2S_OVER_FLAG ((uint16_t)0x0020U) +#define I2S_UNDER_FLAG ((uint16_t)0x0040U) +#define I2S_CHSIDE_FLAG ((uint16_t)0x0080U) +#define I2S_TXFIFOHE_FLAG ((uint16_t)0x0100U) +#define I2S_RXFIFOHF_FLAG ((uint16_t)0x0200U) +#define I2S_TXFIFOE_FLAG ((uint16_t)0x0400U) +#define I2S_RXFIFOF_FLAG ((uint16_t)0x0800U) +#define I2S_RXONLYC_FLAG ((uint16_t)0x1000U) + +/** I2S_DMA_transfer_requests **/ + +#define I2S_DMA_TX ((uint16_t)0x0004U) +#define I2S_DMA_RX ((uint16_t)0x0002U) + +/** I2S Init structure definition **/ + +typedef struct +{ + uint16_t I2sMode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2sMode */ + + uint16_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref Standard */ + + uint16_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ + uint32_t ClkSrcFrequency; /*!< Specifies the I2S clock source frequency in Hz.*/ +} I2S_InitType; + + +/** Standard **/ +#define I2S_STD_PHILLIPS ((uint16_t)0x0000U) +#define I2S_STD_MSB_ALIGN (I2SCFG_STDSEL0) +#define I2S_STD_LSB_ALIGN (I2SCFG_STDSEL1) +#define I2S_STD_PCM_SHORTFRAME (I2SCFG_STDSEL0 | I2SCFG_STDSEL1) +#define I2S_STD_PCM_LONGFRAME (I2SCFG_STDSEL0 | I2SCFG_STDSEL1 | I2SCFG_PCMFSYNC) +#define I2S_STANDARD_MASK (I2SCFG_STD) /* STDSEL and PCMFSYNC bit Mask */ + + +/** I2S_Data_Format **/ +#define I2S_DATA_FORMAT_MASK (~(I2SCFG_CHLEN | I2SCFG_TDATLEN)) /* CHBITS and TDATLEN bit Mask */ +#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000U) +#define I2S_DATA_FMT_16BITS_EXTENDED (I2SCFG_CHLEN) +#define I2S_DATA_FMT_24BITS (I2SCFG_CHLEN | I2SCFG_TDATLEN0) +#define I2S_DATA_FMT_32BITS (I2SCFG_CHLEN | I2SCFG_TDATLEN1) + +/** I2S_MCLK_Output **/ + +#define I2S_MCLK_ENABLE ((uint16_t)0x0800U) +#define I2S_MCLK_DISABLE ((uint16_t)0x0000U) + + +/** I2S_Audio_Frequency **/ + +#define I2S_AUDIO_FREQ_192K ((uint32_t)192000U) +#define I2S_AUDIO_FREQ_96K ((uint32_t)96000U) +#define I2S_AUDIO_FREQ_48K ((uint32_t)48000U) +#define I2S_AUDIO_FREQ_44K ((uint32_t)44100U) +#define I2S_AUDIO_FREQ_32K ((uint32_t)32000U) +#define I2S_AUDIO_FREQ_22K ((uint32_t)22050U) +#define I2S_AUDIO_FREQ_16K ((uint32_t)16000U) +#define I2S_AUDIO_FREQ_11K ((uint32_t)11025U) +#define I2S_AUDIO_FREQ_8K ((uint32_t)8000U) +#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2U) + +/** I2S_Clock_Polarity **/ +#define I2S_CLKPOL_LOW ((uint16_t)0x0000U) +#define I2S_CLKPOL_HIGH (SPI_I2SCFG_CLKPOL) +#define I2S_CLKPOL_MASK (~SPI_I2SCFG_CLKPOL) /* MCLKOEN bit Mask */ + +/** I2S Converter **/ +#define I2S_TURN_ON (I2SCFG_I2SEN | SPI_I2SCFG_MOD) /* I2SEN and MODSEL bit */ +#define I2S_TURN_OFF (~(I2SCFG_I2SEN | SPI_I2SCFG_MOD)) /* I2SEN bit Mask */ + +///** I2S_EXT_DMA_transfer_requests **/ + +#define I2S_EXT_DMA_TX ((uint16_t)0x0004U) +#define I2S_EXT_DMA_RX ((uint16_t)0x0002U) + +void I2S_Reset(I2S_Module* I2Sx); +void I2S_EnableInt(I2S_Module* I2Sx, uint8_t I2S_IT, FunctionalState Cmd); +FlagStatus I2S_GetStatus(I2S_Module* I2Sx, uint8_t i2s_flag); +INTStatus I2S_GetIntStatus(const I2S_Module* I2sx, uint8_t I2S_IT); +void I2S_ClrITPendingBit(I2S_Module* I2Sx, uint8_t I2S_IT); +void I2S_TransmitData(I2S_Module* I2Sx, uint16_t Data); +uint16_t I2S_ReceiveData(I2S_Module* I2Sx); +void I2S_EnableDma(I2S_Module* I2Sx, uint16_t I2S_DMAReq, FunctionalState Cmd); +void I2S_Init(I2S_Module* I2Sx,const I2S_InitType* I2S_InitStruct); +void I2S_Enable(I2S_Module* I2Sx, FunctionalState Cmd); +void I2S_InitStruct(I2S_InitType* I2S_InitStruct); +void I2S_MclkEnable(I2S_Module* I2Sx, FunctionalState Cmd); +void I2S_StandardConfig(I2S_Module* I2Sx, uint16_t Standard); +void I2S_ModeConfig(I2S_Module* I2Sx, uint16_t I2sMode); +void I2S_DataFormatConfig(I2S_Module* I2Sx, uint16_t DataFormat); +void I2S_ClkPolConfig(I2S_Module* I2Sx, uint16_t CLKPOL); +void I2S_AudioFrequencyConfig(I2S_Module* I2Sx, uint32_t AudioFrequency); +void I2S_EXTInit(I2S_EXT_Module* I2Sx_EXT,const I2S_InitType* I2S_EXT_InitStruct); +void I2S_EXTInitStruct(I2S_InitType* I2S_EXT_InitStruct); +void I2S_EXTEnable(I2S_EXT_Module* I2Sx_EXT, FunctionalState Cmd); +void I2S_EXTTransmitData(I2S_EXT_Module* I2Sx, uint16_t Data); +uint16_t I2S_EXTReceiveData(const I2S_EXT_Module* I2Sx); +FlagStatus I2S_EXTGetStatus(const I2S_EXT_Module* I2Sx, uint16_t I2S_EXT_FLAG); +void I2S_EXTEnableDma(I2S_EXT_Module* I2Sx, uint16_t I2S_EXT_DMAReq, FunctionalState Cmd); +void I2S_EXTEnableInt(I2S_EXT_Module* I2Sx, uint8_t I2S_EXT_IT, FunctionalState Cmd); +void I2S_SPIModeSelect(I2S_Module* I2Sx, uint16_t Mode); +INTStatus I2S_EXTGetIntStatus(const I2S_EXT_Module* I2Sx, uint8_t I2S_EXT_IT); +void I2S_DataFifoTransmit(I2S_Module* I2Sx, uint16_t Data); +uint16_t I2S_DataFifoGet(I2S_Module* I2Sx); +void I2S_EXTClrITPendingBit(I2S_EXT_Module* I2Sx, uint8_t I2S_EXT_IT); + +#ifdef __cplusplus +} + +#endif +#endif /*__NS3610CM4_I2S_H */ + + +/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_iwdg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_iwdg.h new file mode 100644 index 0000000000..3ac450a26f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_iwdg.h @@ -0,0 +1,108 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_iwdg.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_IWDG_H__ +#define __N32H76X_78X_IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +typedef enum +{ + IWDG_PVU_FLAG = IWDG_STS_PVU, + IWDG_CRVU_FLAG = IWDG_STS_CRVU, + IWDG_FRZF_FLAG = IWDG_STS_FRZF, +}IWDG_STATUS_FLAG; + +/** KEY register bit mask **/ +#define KEY_ReloadKey ((uint16_t)0xAAAA) +#define KEY_EnableKey ((uint16_t)0xCCCC) +#define IWDG_FREEZE ((uint16_t)0x4567) +#define IWDG_UNFREEZE ((uint16_t)0x89AB) + +/** PREDIV and RELV register write permission **/ +typedef enum +{ + IWDG_WRITE_ENABLE = 0x5555, + IWDG_WRITE_DISABLE = 0x0000 +}IWDOG_WRITE_CONFIG; + +#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00) +#define IWDG_PRESCALER_DIV8 (IWDG_PREDIV_PD0) +#define IWDG_PRESCALER_DIV16 (IWDG_PREDIV_PD1) +#define IWDG_PRESCALER_DIV32 (IWDG_PREDIV_PD1 | IWDG_PREDIV_PD0) +#define IWDG_PRESCALER_DIV64 (IWDG_PREDIV_PD2) +#define IWDG_PRESCALER_DIV128 (IWDG_PREDIV_PD2 | IWDG_PREDIV_PD0) +#define IWDG_PRESCALER_DIV256 (IWDG_PREDIV_PD2 | IWDG_PREDIV_PD1 | IWDG_PREDIV_PD0) + + +void IWDG_WriteConfig(IWDG_Module* IWDGx,IWDOG_WRITE_CONFIG IWDG_WriteAccess); +void IWDG_SetPrescalerDiv(IWDG_Module* IWDGx,uint8_t IWDG_Prescaler); +void IWDG_CntReload(IWDG_Module* IWDGx,uint16_t Reload); +void IWDG_ReloadKey(IWDG_Module* IWDGx); +void IWDG_Enable(IWDG_Module* IWDGx); +void IWDG_Freeze_Enable(IWDG_Module* IWDGx,FunctionalState Cmd); +FlagStatus IWDG_GetStatus(IWDG_Module* IWDGx,IWDG_STATUS_FLAG IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_IWDG_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_jpeg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_jpeg.h new file mode 100644 index 0000000000..7c64df8d03 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_jpeg.h @@ -0,0 +1,383 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_jpeg.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_JPEG_H__ +#define __N32H76x_78x_JPEG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32h76x_78x.h" + +typedef enum +{ + BITEQ0 = 0U, + BITEQ1 = 1U +} BitValue; + +/***** JPEG CTRL module ****/ +#define JPEG_DECODE ((uint32_t)0x00000000U) /* JPEG operation Decode */ +#define JPEG_ENCODE JPEG_CTRL_TYPE /* JPEG operation Encode */ + +#define JPEG_NOSWAP ((uint32_t)0x00000000U) /* No Swap Data for YCbCr 4:2:2 Format in BRC */ +#define JPEG_SWAP JPEG_CTRL_SWAP /* Swap Data for YCbCr 4:2:2 Format in BRC */ + + +/* JPEG SGDMA Module */ + +/* Descriptor flag */ +#define SGDMA_DESCF_LINKDISABLE ((uint32_t)0x00000000U) /* Link Disable */ +#define SGDMA_DESCF_LINKENABLE JPEGDMA_DESCF_LINKE /* Link Enable */ + +#define SGDMA_DESCF_STARTDISABLE ((uint32_t)0x00000000U) /* Non Start of Frame */ +#define SGDMA_DESCF_STARTENABLE JPEGDMA_DESCF_LINKE /* Start of Frame */ + +#define SGDMA_DESCF_ENDDISABLE ((uint32_t)0x00000000U) /* Non End of Frame */ +#define SGDMA_DESCF_ENDENABLE JPEGDMA_DESCF_LINKE /* End of Frame */ + +#define SGDMA_DESCF_DESCCONDISABLE ((uint32_t)0x00000000U) /* The descriptor is not consumed */ +#define SGDMA_DESCF_DESCCONENABLE JPEGDMA_DESCF_LINKE /* Descriptor Consumed */ + +/** Scatter-Gather Descriptor **/ +typedef struct{ + uint32_t linkenable : 1; // bit 0 - Link Enable. + uint32_t startframe : 1; // bit 1 - Start of Frame. + uint32_t endframe : 1; // bit 2 - End of Frame. + uint32_t desccons : 1; // bit 3 - Descriptor Consumed. + uint32_t reserved : 28; // bit 31:4 - Reserved. +} SGx_desc_flags_bits; + +typedef union{ + uint32_t value; + SGx_desc_flags_bits bits; +}SGx_desc_flags; + +/** Scatter-Gather Descriptor type - 32-bit **/ +typedef struct +{ + SGx_desc_flags desc_flags; //Descriptor flag bits: 0: Link Enable, 1: Start of Frame, 2: End of Frame, 3: Descriptor Consumed. 4-31: Reserved + uint32_t blk_size; //[15:0] Block_Size [31:16] Block_Used + uint32_t blk_addr; // The starting address of the data block + uint32_t link_addr; // Link to the next descriptor. Used when Link Enable = 1. +} SGx_DESC32; + +/** Scatter-Gather Descriptor type - 64-bit **/ +typedef struct +{ + SGx_desc_flags desc_flags; // Descriptor flag bits: 0: Link Enable, 1: Start of Frame, 2: End of Frame, 3: Descriptor Consumed. 4-31: Reserved + uint32_t blk_size; // Block_Size + uint32_t blk_used; // Block_Used + uint32_t blk_addr_low; // The starting address of the data block [31:0] + uint32_t blk_addr_high; // The starting address of the data block [63:32] + uint32_t reserved; // Reserved field; not used in current implementation + uint32_t link_addr_low; // Link to the next descriptor. Used when Link Enable = 1. + uint32_t link_addr_high; // Link to the next descriptor. Used when Link Enable = 1. +} SGx_DESC64; + + +/** SGDMA Descriptor Memory Mode **/ +#define SGDMA_DESCLIST_LIST ((uint32_t)0x00000000U) /* The descriptor list structure is a simple List */ +#define SGDMA_DESCLIST_RING JPEGDMA_CTRL_MMODE_1 /* The descriptor list structure is a Ring Buffer */ + +#define SGDMA_DESC_MEMORY ((uint32_t)0x00000000U) /* Descriptors stored in memory */ +#define SGDMA_DESC_CSR JPEGDMA_CTRL_MMODE_0 /* Descriptors programmed through CSR */ + +/** SGDMA Operation Mode **/ +#define SGDMA_EOF_PAUSEDMA ((uint32_t)0x00000000U) /* Pause DMA operation on EOF and wait for driver action */ +#define SGDMA_EOF_RESUMEDMA JPEGDMA_CTRL_OPMODE_0 /* Resume operation of the DMA normally after the EOF */ + +#define SGDMA_BURST_FIXED ((uint32_t)0x00000000U) /* AXI4 MM FIXED burst (aligned addresses only) */ +#define SGDMA_BURST_INCR JPEGDMA_CTRL_OPMODE_1 /* AXI4 MM INCR burst */ + +/** SGDMA H2P Init Structure definition **/ +typedef struct +{ + SGx_DESC64 h2p_desc; /* 64bit Descriptor */ + uint32_t max_burstsize; /* Maximum allowed size for an AXI4 MM burst */ + uint32_t SGlist_size; /* Scatter-Gather List Size */ + uint32_t SGlist_Head; /* Scatter-Gather List Head index pointer */ + uint32_t SGlist_Tail; /* Scatter-Gather List Tail index pointer */ + uint32_t SGlist_Threshold; /* Almost Out Of Descriptors Threshold */ + uint32_t desclist_type; /* The descriptor list structure type */ + uint32_t descstored_type; /* The descriptor storage location */ + uint32_t DMA_EOF_type; /* DMA operation mode on EOF */ + uint32_t DMA_burst_type; /* DMA burst type */ +} SGDMA_H2P_InitType; + +/** SGDMA P2H Init Structure definition **/ +typedef struct +{ + SGx_DESC64 p2h_desc; /* 64bit Descriptor */ + uint32_t max_burstsize; /* Maximum allowed size for an AXI4 MM burst */ + uint32_t SGlist_size; /* Scatter-Gather List Size */ + uint32_t SGlist_Head; /* Scatter-Gather List Head index pointer */ + uint32_t SGlist_Tail; /* Scatter-Gather List Tail index pointer */ + uint32_t SGlist_Threshold; /* Almost Out Of Descriptors Threshold */ + uint32_t desclist_type; /* The descriptor list structure type */ + uint32_t descstored_type; /* The descriptor storage location */ + uint32_t DMA_EOF_type; /* DMA operation mode on EOF */ + uint32_t DMA_burst_type; /* DMA burst type */ +} SGDMA_P2H_InitType; + +/* SGDMA interrupt */ +#define SGDMA_INTSTS_WDATAERREN JPEGDMA_INTSTS_WDATAERR /* AXI MM Write Error when writing data */ +#define SGDMA_INTSTS_RDATAERR JPEGDMA_INTSTS_RDATAERR /* AXI MM Read Error when reading data */ +#define SGDMA_INTSTS_WDESCERR JPEGDMA_INTSTS_WDESCERR /* AXI MM Write Error when writing a descriptor */ +#define SGDMA_INTSTS_RDESCERR JPEGDMA_INTSTS_RDESCERR /* AXI MM Read Error when reading a descriptor */ +#define SGDMA_INTSTS_EOD JPEGDMA_INTSTS_EOD /* End-Of-Descriptor */ +#define SGDMA_INTSTS_AOOD JPEGDMA_INTSTS_AOOD /* Channel is Almost Out of Descriptors */ +#define SGDMA_INTSTS_OOD JPEGDMA_INTSTS_OOD /* Out Of Descriptors */ +#define SGDMA_INTSTS_EOFIN JPEGDMA_INTSTS_EOFIN /* End-Of-Frame sampled at the input of the channel */ +#define SGDMA_INTSTS_EOFOUT JPEGDMA_INTSTS_EOFOUT /* End-Of-Frame sampled at the output of the channel */ +#define SGDMA_INTSTS_GINT JPEGDMA_INTSTS_GINT /* Global interrupt status bit for the Channel */ +#define SGDMA_INTSTS_BUSY JPEGDMA_STS_BUSY /* H2P/P2H is processing a transfer */ + +/* JPEG BRC Module */ + +/** JPEG BRC Init Structure definition **/ +typedef struct +{ + uint32_t buffer_addr; /* buffer memory address */ + uint32_t buffer_size; /* buffer memory size, in byte */ + uint32_t upsample_mode; /* Up sampling mode */ +} JPEGBRC_InitType; + +/* JPEG RBC Module */ + +/** JPEG BRC Init Structure definition **/ +typedef struct +{ + uint32_t pixel_format; /* Pixel format */ + uint32_t sample_order; /* Switch input sample order */ + uint32_t frame_width; /* Frame width */ + uint32_t frame_height; /* Frame height */ + uint32_t component0names; /* Component 0 names */ + uint32_t component1names; /* Component 1 names */ + uint32_t component2names; /* Component 2 names */ + uint32_t C0startaddress; /* Component 0 Start Address */ + uint32_t C0buffersize; /* Size of buffer in the AXI memory */ +} JPEGRBC_InitType; + +/* Pixel format */ +#define JPEGRBC_4_4_4_NONINTERLEAVED ((uint32_t)0x00000000U) /* 4:4:4 non-interleaved format */ +#define JPEGRBC_4_2_2_NONINTERLEAVED ((uint32_t)0x00000001U) /* 4:2:2 non-interleaved format */ +#define JPEGRBC_4_2_0_NONINTERLEAVED ((uint32_t)0x00000002U) /* 4:2:0 non-interleaved format */ +#define JPEGRBC_MONOCHROME ((uint32_t)0x00000003U) /* monochrome format */ +#define JPEGRBC_4_4_4_INTERLEAVED ((uint32_t)0x00000004U) /* 4:4:4 interleaved format */ +#define JPEGRBC_4_2_2_INTERLEAVED ((uint32_t)0x00000005U) /* 4:2:2 interleaved format */ +#define JPEGRBC_4_2_0_INTERLEAVED ((uint32_t)0x00000006U) /* 4:2:0 interleaved format */ + +/* sample_order */ +#define JPEGRBC_MSBSAMPLE ((uint32_t)0x00000000U) /* Switch input sample order MSB */ +#define JPEGRBC_LSBSAMPLE (JPEGRBC_SWITCH_SWITCH) /* Switch input sample order LSB */ + + +/* JPEG DEC Module */ + +/** JPEG DEC Init Structure definition **/ +typedef struct +{ + uint32_t buffer_addr; /* buffer memory address */ + uint32_t buffer_size; /* buffer memory size, in byte */ + uint32_t upsample_mode; /* Up sampling mode */ +} JPEGDEC_InitType; + +#define JPEGDEC_EOB0_ADDRESS ((uint32_t)0x20U) /* JPEGDEC_HUFTAB0_EOB offset address */ +#define JPEGDEC_EOB1_ADDRESS ((uint32_t)0x24U) /* JPEGDEC_HUFTAB1_EOB offset address */ +#define JPEGDEC_EOB2_ADDRESS ((uint32_t)0x28U) /* JPEGDEC_HUFTAB2_EOB offset address */ +#define JPEGDEC_EOB3_ADDRESS ((uint32_t)0x2CU) /* JPEGDEC_HUFTAB3_EOB offset address */ + +#define JPEGDEC_HUFFTABLE ((uint32_t)0x00000000U) /* Huffman decoder table */ +#define JPEGDEC_DVECTORTABLE (JPEGDEC_HUF_ADDR_TABLE_0) /* D vector table */ +#define JPEGDEC_IVECTORTABLE (JPEGDEC_HUF_ADDR_TABLE_1) /* I vector table */ +#define JPEGDEC_HUFFACCTABLE (JPEGDEC_HUF_ADDR_TABLE) /* Huffman decoder accelerator tables */ + +#define JPEGDEC_DCTABLE ((uint32_t)0x00000000U) /* DC table */ +#define JPEGDEC_ACTABLE (JPEGDEC_HUF_ADDR_ACDC) /* AC table */ + +#define JPEGDEC_HUFFTABLE_0 ((uint32_t)0x00000000U) /* table 0 */ +#define JPEGDEC_HUFFTABLE_1 (JPEGDEC_HUF_ADDR_HNUM_0) /* table 1 */ +#define JPEGDEC_HUFFTABLE_2 (JPEGDEC_HUF_ADDR_HNUM_1) /* table 2 */ +#define JPEGDEC_HUFFTABLE_3 (JPEGDEC_HUF_ADDR_HNUM) /* table 3 */ + +#define JPEGDEC_QT0_ADDRESS ((uint32_t)0x400U) /* QT0 offset address */ +#define JPEGDEC_QT1_ADDRESS ((uint32_t)0x500U) /* QT1 offset address */ +#define JPEGDEC_QT2_ADDRESS ((uint32_t)0x600U) /* QT2 offset address */ +#define JPEGDEC_QT3_ADDRESS ((uint32_t)0x700U) /* QT3 offset address */ + +/* JPEG ENC Module */ + +/* output_select */ +#define JPEGENC_OUTPUT_NOTHING ((uint32_t)0x00000000U)/* No data Ouptut in output stream */ +#define JPEGENC_OUTPUT_QT0 (JPEGENC_HSEL_QT0) /* Ouptut quantisation table 0 in output stream */ +#define JPEGENC_OUTPUT_QT1 (JPEGENC_HSEL_QT1) /* Ouptut quantisation table 1 in output stream */ +#define JPEGENC_OUTPUT_QT2 (JPEGENC_HSEL_QT2) /* Ouptut quantisation table 2 in output stream */ +#define JPEGENC_OUTPUT_QT3 (JPEGENC_HSEL_QT3) /* Ouptut quantisation table 3 in output stream */ +#define JPEGENC_OUTPUT_HT0 (JPEGENC_HSEL_HT0) /* Ouptut Huffman table 0 in output stream */ +#define JPEGENC_OUTPUT_HT1 (JPEGENC_HSEL_HT1) /* Ouptut Huffman table 1 in output stream */ +#define JPEGENC_OUTPUT_HT2 (JPEGENC_HSEL_HT2) /* Ouptut Huffman table 2 in output stream */ +#define JPEGENC_OUTPUT_HT3 (JPEGENC_HSEL_HT3) /* Ouptut Huffman table 3 in output stream */ +#define JPEGENC_OUTPUT_ONLY (JPEGENC_HSEL_NFD) /* Output tables in only one frames */ +#define JPEGENC_OUTPUT_NOECS (JPEGENC_HSEL_ATF) /* No ouptut ECS data in only one frames in output stream */ + +/* output_select */ +#define JPEGENC_RESSART_DISABLE ((uint32_t)0x00000000U) /* Disable restart marker generation */ +#define JPEGENC_RESSART_ENABLE (JPEGENC_RICTRL_RIEN) /* Enable restart marker generation */ + +/* Corereset */ +#define JPEGENC_CORERST_ENABLE ((uint32_t)0x00000000U) /* no reset the core if any error occurred */ +#define JPEGENC_CORERST_DISABLE (JPEGENC_CTRL_ERST) /* reset the core if any error occurred */ + + +/*** Huffman tables ***/ +typedef struct +{ + uint16_t* DCcode_offset; + uint16_t* ACcode_offset; + uint16_t* DCcode_start; + uint16_t* ACcode_start; + uint32_t EOBS; + uint32_t ZRLS; +} Huffmantables_InitType; + +/** JPEG ENC Init Structure definition **/ +typedef struct +{ + Huffmantables_InitType HuffmanTable0; /* Huffman table0 */ + Huffmantables_InitType HuffmanTable1; /* Huffman table0 */ + Huffmantables_InitType HuffmanTable2; /* Huffman table0 */ + Huffmantables_InitType HuffmanTable3; /* Huffman table0 */ + uint8_t* header_address; /* File frame header storage address */ + uint32_t header_size; /* File frame header size */ + uint8_t* hufftab0_header_address; /* Huffman table0 frame header storage address */ + uint32_t hufftab0_header_size; /* Huffman table0 frame header size */ + uint8_t* hufftab1_header_address; /* Huffman table1 frame header storage address */ + uint32_t hufftab1_header_size; /* Huffman table1 frame header size */ + uint8_t* hufftab2_header_address; /* Huffman table2 frame header storage address */ + uint32_t hufftab2_header_size; /* Huffman table2 frame header size */ + uint8_t* hufftab3_header_address; /* Huffman table3 frame header storage address */ + uint32_t hufftab3_header_size; /* Huffman table3 frame header size */ + uint8_t* footer_address; /* File frame footer storage address */ + uint32_t footer_size; /* File frame footer size */ + uint32_t output_select; /* Header parts out select */ + uint8_t* QT0_address; /* Quantisation table 0 storage address */ + uint8_t* QT1_address; /* Quantisation table 1 storage address */ + uint8_t* QT2_address; /* Quantisation table 2 storage address */ + uint8_t* QT3_address; /* Quantisation table 3 storage address */ + uint32_t restart_interval; /* restart interval enable*/ + uint32_t interval_num; /* Number of blocks per restart interval */ + uint32_t C0QT_select; /* Quantisation table selector for component 0 */ + uint32_t C1QT_select; /* Quantisation table selector for component 1 */ + uint32_t C2QT_select; /* Quantisation table selector for component 2 */ + uint32_t C3QT_select; /* Quantisation table selector for component 3 */ + uint32_t C0HT_select; /* Huffman table selector for component 0 */ + uint32_t C1HT_select; /* Huffman table selector for component 1 */ + uint32_t C2HT_select; /* Huffman table selector for component 2 */ + uint32_t C3HT_select; /* Huffman table selector for component 3 */ + uint32_t Corereset; /* reset the core if any error occurred */ +} JPEGENC_InitType; + + +/***** JPEG CTRL module ****/ +void JPEG_ConfigType(uint32_t Type); +void JPEG_ConfigSwap(uint32_t Type); + +/***** JPEG SGDMA module ****/ +void SGDMA_H2P_Init(SGDMA_H2P_InitType* SGDMA_H2P_InitStruct); +void SGDMA_P2H_Init(SGDMA_P2H_InitType* SGDMA_P2H_InitStruct); +void SGDMA_Reset(JPEG_SGDMA_Module *SGDMAx); +void SGDMA_Start(JPEG_SGDMA_Module *SGDMAx); +void SGDMA_ConfigInt(JPEG_SGDMA_Module* SGDMAx, uint32_t SGDMA_INT, FunctionalState Cmd); +FlagStatus SGDMAx_GetFlagStatus(JPEG_SGDMA_Module* SGDMAx, uint32_t Flag); +FlagStatus SGDMAx_GetIntStatus(JPEG_SGDMA_Module* SGDMAx, uint32_t Flag); +void SGDMAx_ClrFlag(JPEG_SGDMA_Module* SGDMAx, uint32_t Flag); + +/***** JPEG BRC module ****/ +ErrorStatus JPEGBRC_Init(JPEGBRC_InitType* JPEGBRC_InitStruct); +void JPEGBRC_Enable(FunctionalState Cmd); + +/***** JPEG RBC module ****/ +ErrorStatus JPEGRBC_Init(JPEGRBC_InitType* JPEGRBC_InitStruct); +void JPEGRBC_Enable(FunctionalState Cmd); + +/***** JPEG DEC module ****/ +void JPEGDEC_Enable(FunctionalState Cmd); +FlagStatus JPEGDEC_GetFlagStatus(uint32_t Flag); +uint32_t JPEGDEC_GetUNKErrorAddress(void); +uint32_t JPEGDEC_GetUNEXPErrorAddress(void); +uint16_t JPEGDEC_GetHESYMErrorAddress(void); +uint32_t JPEGDEC_GetHESYMECSErrorAddress(void); +uint32_t JPEGDEC_GetHUFSErrorAddress(void); +ErrorStatus JPEGDEC_TableAccessRequest(FunctionalState Cmd); +void JPEGDEC_SetHUFTable_EOB(uint32_t TableAddress,uint32_t EOBSymbol,uint32_t EOBSymbolMask); +ErrorStatus JPEGDEC_SetHuffTable(uint32_t TableType,uint32_t Tableselector,uint32_t TableNum,uint32_t* Value,uint32_t Count); +void JPEGDEC_SetQuantiTable(uint32_t TableAddress,uint8_t* Value,uint32_t Count); + +/***** JPEG ENC module ****/ +ErrorStatus JPEGENC_Init(JPEGENC_InitType* JPEGENC_InitStruct); +void JPEGENC_OutputEnable(uint32_t outputsel,FunctionalState Cmd); +void JPEGENC_Enable(FunctionalState Cmd); +void JPEGENC_DynamicAdjustEnable(FunctionalState Cmd); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76x_78x_JPEG_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lcdc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lcdc.h new file mode 100644 index 0000000000..1d54171f2c --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lcdc.h @@ -0,0 +1,335 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_lcdc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_LCDC_H +#define __N32H76x_78x_LCDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/*** LCDC Structure Definition Start ***/ + +/** LCDC Init structure definition is used with LCDC. **/ +typedef struct +{ + uint32_t LCDC_HSPolarity; /* configures the horizontal synchronization polarity. */ + + uint32_t LCDC_VSPolarity; /* configures the vertical synchronization polarity. */ + + uint32_t LCDC_DEPolarity; /* configures the data enable polarity. */ + + uint32_t LCDC_PCPolarity; /* configures the pixel clock polarity. */ + + uint32_t LCDC_HorizontalSync; /* configures the number of Horizontal synchronization width. */ + + uint32_t LCDC_VerticalSync; /* configures the number of Vertical synchronization height. */ + + uint32_t LCDC_AccumulatedHBP; /* configures the accumulated horizontal back porch width. */ + + uint32_t LCDC_AccumulatedVBP; /* configures the accumulated vertical back porch height. */ + + uint32_t LCDC_AccumulatedActiveW; /* configures the accumulated active width. */ + + uint32_t LCDC_AccumulatedActiveH; /* configures the accumulated active height. */ + + uint32_t LCDC_TotalWidth; /* configures the total width. */ + + uint32_t LCDC_TotalHeight; /* configures the total height. */ + + uint32_t LCDC_BackgroundRedValue; /* configures the background red value. */ + + uint32_t LCDC_BackgroundGreenValue; /* configures the background green value. */ + + uint32_t LCDC_BackgroundBlueValue; /* configures the background blue value. */ +} LCDC_InitType; + +typedef struct +{ + uint32_t LCDC_HorizontalStart; /* Configures the window horizontal start Position. */ + + uint32_t LCDC_HorizontalStop; /* Configures the window horizontal stop Position. */ + + uint32_t LCDC_HorizontalScalerStop; /* Configures the scaler window horizontal stop Position. */ + + uint32_t LCDC_VerticalStart; /* Configures the window vertical start Position. */ + + uint32_t LCDC_VerticalStop; /* Configures the window vertical stop Position. */ + + uint32_t LCDC_VerticalScalerStop; /* Configures the scaler window vertical stop Position. */ + + uint32_t LCDC_PixelFormat; /* Specifies the pixel format. */ + + uint32_t LCDC_ConstantAlpha; /* Specifies the constant alpha used for blending. */ + + uint32_t LCDC_DefaultAlpha; /* Configures the default alpha value. */ + + uint32_t LCDC_BlendingFactor1; /* Select the blending factor 1. */ + + uint32_t LCDC_BlendingFactor2; /* Select the blending factor 2. */ + + uint32_t LCDC_CFBStartAdress; /* Configures the color frame buffer address. */ + + uint32_t LCDC_AFB0StartAdress; /* Configures the Auxiliary frame buffer 0 address. */ + + uint32_t LCDC_AFB1StartAdress; /* Configures the Auxiliary frame buffer 1 address. */ + + uint32_t LCDC_CFBLineLength; /* Configures the color frame buffer line length. */ + + uint32_t LCDC_CFBLineNumber; /* Configures the number of line in frame buffer. */ + + uint32_t LCDC_CFBPitch; /* Configures the color frame buffer pitch in bytes. */ + + uint32_t LCDC_DefaultColorBlue; /* Configures the default blue value. */ + + uint32_t LCDC_DefaultColorGreen; /* Configures the default green value. */ + + uint32_t LCDC_DefaultColorRed; /* Configures the default red value. */ +} LCDC_Layer_InitType; + +typedef struct +{ + uint32_t LCDC_Blue; /* Blue width */ + + uint32_t LCDC_Green; /* Green width */ + + uint32_t LCDC_Red; /* Red width */ +}LCDC_RGBType; + +typedef struct +{ + uint32_t LCDC_POSX; /* Current X Position */ + uint32_t LCDC_POSY; /* Current Y Position */ +} LCDC_PosType; + +typedef struct +{ + uint32_t LCDC_ColorKeyBlue; /* Configures the color key blue value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LCDC_ColorKeyGreen; /* Configures the color key green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LCDC_ColorKeyRed; /* Configures the color key red value. + This parameter must range from 0x00 to 0xFF. */ +} LCDC_ColorKeying_InitType; + + +typedef struct +{ + uint32_t LCDC_CLUTAdress; /* Configures the CLUT address. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LCDC_RedValue; /* Configures the red value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LCDC_GreenValue; /* Configures the green value. + This parameter must range from 0x00 to 0xFF. */ + + uint32_t LCDC_BlueValue; /* Configures the blue value. + This parameter must range from 0x00 to 0xFF. */ +} LCDC_CLUT_InitType; + +/*** LCDC Structure Definition End ***/ + +/*** LCDC Macro Definition Start ***/ + +/** LCDC register bit mask definition **/ +#define LCDC_REG_BIT_MASK ((uint32_t)0x00000000) + +/** Horizontal Synchronization Polarity **/ +#define LCDC_HSPolarity_LOW (LCDC_REG_BIT_MASK) +#define LCDC_HSPolarity_HIGH (LCDC_GCTRL_HSPOL) + +/** Vertical Synchronization Polarity **/ +#define LCDC_VSPolarity_LOW (LCDC_REG_BIT_MASK) +#define LCDC_VSPolarity_HIGH (LCDC_GCTRL_VSPOL) + +/** Data enable Polarity **/ +#define LCDC_DEPolarity_LOW (LCDC_GCTRL_DEPOL) +#define LCDC_DEPolarity_HIGH (LCDC_REG_BIT_MASK) + +/** Pixel clock Polarity **/ +#define LCDC_PCPolarity_IPC (LCDC_REG_BIT_MASK) +#define LCDC_PCPolarity_IIPC (LCDC_GCTRL_PCLKPOL) + +/** LCDC reload **/ +#define LCDC_IMReload (LCDC_SRCTRL_IMR) +#define LCDC_VBReload (LCDC_SRCTRL_VBR) + +/** LCDC reload **/ +#define LCDC_LayerIMReload (LCDC_LSRCTRL_IMR) +#define LCDC_LayerVBReload (LCDC_LSRCTRL_VBR) +#define LCDC_LayerMGReload (LCDC_LSRCTRL_MGR) + +/** LCDC Pixel format **/ +#define LCDC_Pixel_Format_ARGB8888 (LCDC_REG_BIT_MASK) +#define LCDC_Pixel_Format_ABGR8888 (LCDC_PFCTRL_PF_0) +#define LCDC_Pixel_Format_RGBA8888 (LCDC_PFCTRL_PF_1) +#define LCDC_Pixel_Format_BGRA8888 (LCDC_PFCTRL_PF_0 | LCDC_PFCTRL_PF_1) +#define LCDC_Pixel_Format_RGB565 (LCDC_PFCTRL_PF_2) +#define LCDC_Pixel_Format_BGR565 (LCDC_PFCTRL_PF_0 | LCDC_PFCTRL_PF_2) +#define LCDC_Pixel_Format_RGB888 (LCDC_PFCTRL_PF_1 | LCDC_PFCTRL_PF_2) +#define LCDC_Pixel_Format_Custom (LCDC_PFCTRL_PF_0 | LCDC_PFCTRL_PF_1 | LCDC_PFCTRL_PF_2) + +/** LCDC blending factor1 **/ +#define LCDC_BlendingFactor1_CA (LCDC_BFCTRL_BF1_2) +#define LCDC_BlendingFactor1_PAxCA (LCDC_BFCTRL_BF1_1 | LCDC_BFCTRL_BF1_2) + +/** LCDC blending factor2 **/ +#define LCDC_BlendingFactor2_CA (LCDC_BFCTRL_BF2_0 | LCDC_BFCTRL_BF2_2) +#define LCDC_BlendingFactor2_PAxCA (LCDC_BFCTRL_BF2_0 | LCDC_BFCTRL_BF2_1 | LCDC_BFCTRL_BF2_2) + +/** LCDC interrupt sources **/ +#define LCDC_INT_LIEN (LCDC_INTEN_LIEN) +#define LCDC_INT_FUIEN (LCDC_INTEN_FUIEN) +#define LCDC_INT_BEIEN (LCDC_INTEN_BEIEN) +#define LCDC_INT_RRIEN (LCDC_INTEN_RRIEN) +#define LCDC_INT_STNSIGIEN (LCDC_INTEN_STNSIGIEN) +#define LCDC_INT_STNSYNCIEN (LCDC_INTEN_STNSYNCIEN) +#define LCDC_INT_FUKIEN (LCDC_INTEN_FUKIEN) +#define LCDC_INT_CRCIEN (LCDC_INTEN_CRCIEN) +#define LCDC_INT_RFEIEN (LCDC_INTEN_RFEIEN) + +/** LCDC Flags **/ +#define LCDC_FLAG_L (LCDC_INTEN_LIEN) +#define LCDC_FLAG_FU (LCDC_INTEN_FUIEN) +#define LCDC_FLAG_BE (LCDC_INTEN_BEIEN) +#define LCDC_FLAG_RR (LCDC_INTEN_RRIEN) +#define LCDC_FLAG_STNSIG (LCDC_INTEN_STNSIGIEN) +#define LCDC_FLAG_STNSYNC (LCDC_INTEN_STNSYNCIEN) +#define LCDC_FLAG_FUK (LCDC_INTEN_FUKIEN) +#define LCDC_FLAG_CRC (LCDC_INTEN_CRCIEN) +#define LCDC_FLAG_RFE (LCDC_INTEN_RFEIEN) + + +void LCDC_DeInit(void); +void LCDC_Init(LCDC_InitType* LCDC_InitStruct); +void LCDC_StructInit(LCDC_InitType* LCDC_InitStruct); +void LCDC_StructInit(LCDC_InitType* LCDC_InitStruct); +void LCDC_Enable(FunctionalState Cmd); +void LCDC_DitherEnable(FunctionalState Cmd); +LCDC_RGBType LCDC_GetDitherWidth(void); +void LCDC_DitherStructInit(LCDC_RGBType* LCDC_RGB_DitherStruct); +void LCDC_LINTPConfig(uint32_t LCDC_LINTPosition); +void LCDC_LayerInit(LCDC_Layer_Module* LCDC_Layerx , LCDC_Layer_InitType* LCDC_Layer_InitStruct); +void LCDC_LayerStructInit(LCDC_Layer_InitType* LCDC_Layer_InitStruct); +void LCDC_LayerEnable(LCDC_Layer_Module* LCDC_Layerx , FunctionalState Cmd); +LCDC_PosType LCDC_GetPosStatus(void); +void LCDC_PosStructInit(LCDC_PosType* LCDC_Pos_InitStruct); +FlagStatus LCDC_GetCDStatus(uint32_t LCDC_CD); +void LCDC_ReloadConfig(uint32_t LCDC_Reload); +void LCDC_LayerReloadConfig(LCDC_Layer_Module* LCDC_Layerx , uint32_t LCDC_LayerReload); +void LCDC_ColorKeyingConfig(LCDC_Layer_Module* LCDC_Layerx, LCDC_ColorKeying_InitType* LCDC_ColorKeying_InitStruct, FunctionalState Cmd); +void LCDC_ColorKeyingStructInit(LCDC_ColorKeying_InitType* LCDC_ColorKeying_InitStruct); +void LCDC_CLUTEnable(LCDC_Layer_Module* LCDC_Layerx, FunctionalState Cmd); +void LCDC_CLUTInit(LCDC_Layer_Module* LCDC_Layerx, LCDC_CLUT_InitType* LCDC_CLUT_InitStruct); +void LCDC_CLUTStructInit(LCDC_CLUT_InitType* LCDC_CLUT_InitStruct); +void LCDC_LayerPosition(LCDC_Layer_Module* LCDC_Layerx, uint16_t OffsetX, uint16_t OffsetY); +void LCDC_LayerAlpha(LCDC_Layer_Module* LCDC_Layerx, uint8_t ConstantAlpha); +void LCDC_LayerAddress(LCDC_Layer_Module* LCDC_Layerx, uint32_t Address); +void LCDC_LayerSize(LCDC_Layer_Module* LCDC_Layerx, uint32_t Width, uint32_t Height); +void LCDC_LayerPixelFormat(LCDC_Layer_Module* LCDC_Layerx, uint32_t PixelFormat); +void LCDC_ConfigInt(uint32_t LCDC_IT, FunctionalState Cmd); +FlagStatus LCDC_GetFlagStatus(uint32_t LCDC_FLAG); +FlagStatus LCDC_GetFlagStatus(uint32_t LCDC_FLAG); +void LCDC_ClearFlag(uint32_t LCDC_FLAG); +INTStatus LCDC_GetIntStatus(uint32_t LCDC_IT); +void LCDC_ClrIntPendingBit(uint32_t LCDC_IT); + + + + +/** LCDC_Exported_Functions End **/ + +#ifdef __cplusplus +} + +#endif + +#endif /*__N32H76x_78x_LCDC_H */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lptim.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lptim.h new file mode 100644 index 0000000000..c4ab1dd621 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lptim.h @@ -0,0 +1,284 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_lptim.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_LPTIM_H__ +#define __N32H76X_78X_LPTIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" +#include "n32h76x_78x_rcc.h" + +/*** LPTIM Structure Definition Start ***/ + + +/** LPTIM initialize configuration structure definition **/ +typedef struct +{ + uint32_t ClockSource; /* Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of LPTIM Clock Source definition. + This feature can be modified afterwards using unitary function LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /* Specifies the prescaler division ratio. + This parameter can be a value of LPTIM Prescaler Value definition. + This feature can be modified afterwards using using unitary function LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /* Specifies the waveform shape. + This parameter can be a value of LPTIM Output Waveform Type definition. + This feature can be modified afterwards using unitary function LPTIM_ConfigOutput().*/ + + uint32_t Polarity; /* Specifies waveform polarity. + This parameter can be a value of LPTIM Output Polarity definition. + This feature can be modified afterwards using unitary function LPTIM_ConfigOutput().*/ +} LPTIM_InitType; + +/*** LPTIM Structure Definition End ***/ + + +/*** LPTIM Macro Definition Start ***/ + +/** LPTIM status definition **/ +#define LPTIM_COMP_MATCH_STATUS ((uint32_t)LPTIM_INTSTS_CMPM) /* Compare match */ +#define LPTIM_AUTO_RELOAD_STATUS ((uint32_t)LPTIM_INTSTS_ARRM) /* Autoreload match */ +#define LPTIM_EXT_TRIG_EDGE_EVENT_STATUS ((uint32_t)LPTIM_INTSTS_EXTRIG) /* External trigger edge event */ +#define LPTIM_COMP_UPDATE_STATUS ((uint32_t)LPTIM_INTSTS_CMPUPD) /* Compare register update OK */ +#define LPTIM_AUTO_RELOAD_UPDATE_STATUS ((uint32_t)LPTIM_INTSTS_ARRUPD) /* Autoreload register update OK */ +#define LPTIM_COUNTER_DIR_UP_STATUS ((uint32_t)LPTIM_INTSTS_UP) /* Counter direction change down to up */ +#define LPTIM_COUNTER_DIR_DOWN_STATUS ((uint32_t)LPTIM_INTSTS_DOWN) /* Counter direction change up to down */ + +/** LPTIM flag definition **/ +#define LPTIM_COMP_MATCH_FLAG ((uint32_t)LPTIM_INTCLR_CMPMCF) /* Compare match Clear Flag */ +#define LPTIM_AUTO_RELOAD_FLAG ((uint32_t)LPTIM_INTCLR_ARRMCF) /* Autoreload match Clear Flag */ +#define LPTIM_EXT_TRIG_EDGE_EVENT_FLAG ((uint32_t)LPTIM_INTCLR_EXTRIGCF) /* External trigger edge event Clear Flag */ +#define LPTIM_COMP_UPDATE_FLAG ((uint32_t)LPTIM_INTCLR_CMPUPDCF) /* Compare register update OK Clear Flag */ +#define LPTIM_AUTO_RELOAD_UPDATE_FLAG ((uint32_t)LPTIM_INTCLR_ARRUPDCF) /* Autoreload register update OK Clear Flag */ +#define LPTIM_COUNTER_DIR_UP_FLAG ((uint32_t)LPTIM_INTCLR_UPCF) /* Counter direction change down to up Clear Flag */ +#define LPTIM_COUNTER_DIR_DOWN_FLAG ((uint32_t)LPTIM_INTCLR_DOWNCF) /* Counter direction change up to down Clear Flag */ + +/** LPTIM interrupt definition **/ +#define LPTIM_COMP_MATCH_INT ((uint32_t)LPTIM_INTEN_CMPMIE) /* Compare match Interrupt */ +#define LPTIM_AUTO_RELOAD_INT ((uint32_t)LPTIM_INTEN_ARRMIE) /* Autoreload match Interrupt */ +#define LPTIM_EXT_TRIG_EDGE_EVENT_INT ((uint32_t)LPTIM_INTEN_EXTRIGIE) /* External trigger edge event Interrupt */ +#define LPTIM_COMP_UPDATE_INT ((uint32_t)LPTIM_INTEN_CMPUPDIE) /* Compare register update OK Interrupt */ +#define LPTIM_AUTO_RELOAD_UPDATE_INT ((uint32_t)LPTIM_INTEN_ARRUPDIE) /* Autoreload register update OK Interrupt */ +#define LPTIM_COUNTER_DIR_UP_INT ((uint32_t)LPTIM_INTEN_UPIE) /* Counter direction change down to up Interrupt */ +#define LPTIM_COUNTER_DIR_DOWN_INT ((uint32_t)LPTIM_INTEN_DOWNIE) /* Counter direction change up to down Interrupt */ + +/** LPTIM Operating Mode definition **/ +#define LPTIM_OPERATING_MODE_CONTINUOUS ((uint32_t)LPTIM_CTRL_TSTCM) /* LP Timer starts in continuous mode */ +#define LPTIM_OPERATING_MODE_ONESHOT ((uint32_t)LPTIM_CTRL_SNGMST) /* LP Tilmer starts in single mode */ + +/** LPTIM Update Mode definition **/ +#define LPTIM_UPDATE_MODE_IMMEDIATE ((uint32_t)0x00000000U) /* Preload is disabled: registers are updated after each APB bus write access */ +#define LPTIM_UPDATE_MODE_ENDOFPERIOD ((uint32_t)LPTIM_CFG_RELOAD) /* preload is enabled: registers are updated at the end of the current LPTIM period */ + +/** LPTIM Counter Mode definition **/ +#define LPTIM_COUNTER_MODE_INTERNAL ((uint32_t)0x00000000U) /* The counter is incremented following each internal clock pulse */ +#define LPTIM_COUNTER_MODE_EXTERNAL ((uint32_t)LPTIM_CFG_CNTMEN) /* The counter is incremented following each valid clock pulse on the LPTIM external Input1 */ + +/** LPTIM Output Waveform Type definition **/ +#define LPTIM_OUTPUT_WAVEFORM_PWM ((uint32_t)0x00000000U) /* LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE */ +#define LPTIM_OUTPUT_WAVEFORM_SETONCE ((uint32_t)LPTIM_CFG_WAVE) /* LPTIM generates a Set Once waveform */ + +/** LPTIM Output Polarity definition **/ +#define LPTIM_OUTPUT_POLARITY_REGULAR ((uint32_t)0x00000000U) /* The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers */ +#define LPTIM_OUTPUT_POLARITY_INVERSE ((uint32_t)LPTIM_CFG_WAVEPOL) /* The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers */ + +/** LPTIM Prescaler Value definition **/ +#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x00000000U) /* Prescaler division factor is set to 1 */ +#define LPTIM_PRESCALER_DIV2 ((uint32_t)LPTIM_CFG_CLKPRE_0) /* Prescaler division factor is set to 2 */ +#define LPTIM_PRESCALER_DIV4 ((uint32_t)LPTIM_CFG_CLKPRE_1) /* Prescaler division factor is set to 4 */ +#define LPTIM_PRESCALER_DIV8 ((uint32_t)LPTIM_CFG_CLKPRE_1 \ + | LPTIM_CFG_CLKPRE_0) /* Prescaler division factor is set to 8 */ +#define LPTIM_PRESCALER_DIV16 ((uint32_t)LPTIM_CFG_CLKPRE_2) /* Prescaler division factor is set to 16 */ +#define LPTIM_PRESCALER_DIV32 ((uint32_t)LPTIM_CFG_CLKPRE_2 \ + | LPTIM_CFG_CLKPRE_0) /* Prescaler division factor is set to 32 */ +#define LPTIM_PRESCALER_DIV64 ((uint32_t)LPTIM_CFG_CLKPRE_2 \ + | LPTIM_CFG_CLKPRE_1) /* Prescaler division factor is set to 64 */ +#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFG_CLKPRE) /* Prescaler division factor is set to 128 */ + +/** LPTIM Trigger Source definition **/ +#define LPTIM_TRIG_SOURCE_GPIO ((uint32_t)0x00000000U) /* External input trigger is connected to TIMx_ETR input */ +#define LPTIM_TRIG_SOURCE_RTCALARMA ((uint32_t)LPTIM_CFG_TRGSEL_0) /* External input trigger is connected to RTC Alarm A */ +#define LPTIM_TRIG_SOURCE_RTCALARMB ((uint32_t)LPTIM_CFG_TRGSEL_1) /* External input trigger is connected to RTC Alarm B */ +#define LPTIM_TRIG_SOURCE_RTCTAMP1 ((uint32_t)LPTIM_CFG_TRGSEL_1 \ + | LPTIM_CFG_TRGSEL_0) /* External input trigger is connected to RTC Tamper 1 */ +#define LPTIM_TRIG_SOURCE_RTCTAMP2 ((uint32_t)LPTIM_CFG_TRGSEL_2) /* External input trigger is connected to RTC Tamper 2 */ +#define LPTIM_TRIG_SOURCE_RTCTAMP3 ((uint32_t)LPTIM_CFG_TRGSEL_2 \ + | LPTIM_CFG_TRGSEL_0) /* External input trigger is connected to RTC Tamper 3 */ +#define LPTIM_TRIG_SOURCE_COMP1 ((uint32_t)LPTIM_CFG_TRGSEL_2 \ + | LPTIM_CFG_TRGSEL_1) /* External input trigger is connected to COMP1 output */ +#define LPTIM_TRIG_SOURCE_COMP2 ((uint32_t)LPTIM_CFG_TRGSEL_2 \ + | LPTIM_CFG_TRGSEL_1 \ + | LPTIM_CFG_TRGSEL_0) /* External input trigger is connected to COMP2 output */ +#define LPTIM_TRIG_SOURCE_COMP3 ((uint32_t)LPTIM_CFG_TRGSEL_3) /* External input trigger is connected to COMP3 output */ +#define LPTIM_TRIG_SOURCE_COMP4 ((uint32_t)LPTIM_CFG_TRGSEL_3 \ + | LPTIM_CFG_TRGSEL_0) /* External input trigger is connected to COMP4 output */ + +/** LPTIM Trigger Filter definition **/ +#define LPTIM_TRIG_FILTER_NONE ((uint32_t)0x00000000U) /* Any trigger active level change is considered as a valid trigger */ +#define LPTIM_TRIG_FILTER_2 ((uint32_t)LPTIM_CFG_TRIGFLT_0) /* Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger */ +#define LPTIM_TRIG_FILTER_4 ((uint32_t)LPTIM_CFG_TRIGFLT_1) /* Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger */ +#define LPTIM_TRIG_FILTER_8 ((uint32_t)LPTIM_CFG_TRIGFLT) /* Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger */ + +/** LPTIM Trigger Polarity definition **/ +#define LPTIM_TRIG_POLARITY_RISING ((uint32_t)LPTIM_CFG_TRGEN_0) /* LPTIM counter starts when a rising edge is detected */ +#define LPTIM_TRIG_POLARITY_FALLING ((uint32_t)LPTIM_CFG_TRGEN_1) /* LPTIM counter starts when a falling edge is detected */ +#define LPTIM_TRIG_POLARITY_RISING_FALLING ((uint32_t)LPTIM_CFG_TRGEN) /* LPTIM counter starts when a rising or a falling edge is detected */ + +/** LPTIM Clock Source definition **/ +#define LPTIM_CLK_SOURCE_INTERNAL ((uint32_t)0x00000000U) /* LPTIM is clocked by internal clock source ((uint32_t)APB clock or any of the embedded oscillators) */ +#define LPTIM_CLK_SOURCE_EXTERNAL ((uint32_t)LPTIM_CFG_CLKSEL) /* LPTIM is clocked by an external clock source through the LPTIM external Input1 */ + +/** LPTIM Clock Filter definition **/ +#define LPTIM_CLK_FILTER_NONE ((uint32_t)0x00000000U) /* Any external clock signal level change is considered as a valid transition */ +#define LPTIM_CLK_FILTER_2 ((uint32_t)LPTIM_CFG_CLKFLT_0) /* External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition */ +#define LPTIM_CLK_FILTER_4 ((uint32_t)LPTIM_CFG_CLKFLT_1) /* External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition */ +#define LPTIM_CLK_FILTER_8 ((uint32_t)LPTIM_CFG_CLKFLT) /* External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition */ + +/** LPTIM Clock Polarity definition **/ +#define LPTIM_CLK_POLARITY_RISING ((uint32_t)0x00000000U) /* The rising edge is the active edge used for counting */ +#define LPTIM_CLK_POLARITY_FALLING ((uint32_t)LPTIM_CFG_CLKPOL_0) /* The falling edge is the active edge used for counting */ +#define LPTIM_CLK_POLARITY_RISING_FALLING ((uint32_t)LPTIM_CFG_CLKPOL_1) /* Both edges are active edges */ +#define LPTIM_CLK_POLARITY_RISING_FALLING_NO ((uint32_t)LPTIM_CFG_CLKPOL_0 \ + | LPTIM_CFG_CLKPOL_1) /* Both edges are not active edges */ + +/** LPTIM Encoder Mode definition **/ +#define LPTIM_ENCODER_MODE_RISING ((uint32_t)0x00000000U) /* The rising edge is the active edge used for counting */ +#define LPTIM_ENCODER_MODE_FALLING ((uint32_t)LPTIM_CFG_CLKPOL_0) /* The falling edge is the active edge used for counting */ +#define LPTIM_ENCODER_MODE_RISING_FALLING ((uint32_t)LPTIM_CFG_CLKPOL_1) /* Both edges are active edges */ + +/** LPTIM Input1 connected option definition **/ +#define LPTIM_INPUT1_CONNECT_GPIO ((uint32_t)0x00000000U) /* Input1 connected to GPIO */ +#define LPTIM_INPUT1_CONNECT_COMP1 ((uint32_t)LPTIM_OPT_OPT1_2) /* Input1 connected to COMP1_OUT */ +#define LPTIM_INPUT1_CONNECT_COMP2 ((uint32_t)LPTIM_OPT_OPT1_2 \ + | LPTIM_OPT_OPT1_0) /* Input1 connected to COMP2_OUT */ +#define LPTIM_INPUT1_CONNECT_COMP3 ((uint32_t)LPTIM_OPT_OPT1_2 \ + | LPTIM_OPT_OPT1_1) /* Input1 connected to COMP3_OUT */ +#define LPTIM_INPUT1_CONNECT_COMP4 ((uint32_t)LPTIM_OPT_OPT1_2 \ + | LPTIM_OPT_OPT1_1 \ + | LPTIM_OPT_OPT1_0) /* Input1 connected to COMP4_OUT */ + + +/** LPTIM Input2 connected option definition **/ +#define LPTIM_INPUT2_CONNECT_GPIO ((uint32_t)0x00000000U) /* Input2 connected to GPIO */ +#define LPTIM_INPUT2_CONNECT_COMP1 ((uint32_t)LPTIM_OPT_OPT2_2) /* Input2 connected to COMP1_OUT */ +#define LPTIM_INPUT2_CONNECT_COMP2 ((uint32_t)LPTIM_OPT_OPT2_2 \ + | LPTIM_OPT_OPT2_0) /* Input2 connected to COMP2_OUT */ +#define LPTIM_INPUT2_CONNECT_COMP3 ((uint32_t)LPTIM_OPT_OPT2_2 \ + | LPTIM_OPT_OPT2_1) /* Input2 connected to COMP3_OUT */ +#define LPTIM_INPUT2_CONNECT_COMP4 ((uint32_t)LPTIM_OPT_OPT2_2 \ + | LPTIM_OPT_OPT2_1 \ + | LPTIM_OPT_OPT2_0) /* Input2 connected to COMP4_OUT */ + +/*** LPTIM Driving Functions Declaration ***/ +void LPTIM_DeInit(LPTIM_Module* LPTIMx); +void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct); +ErrorStatus LPTIM_Init(LPTIM_Module* LPTIMx, LPTIM_InitType* LPTIM_InitStruct); +void LPTIM_Cmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd); +uint32_t LPTIM_IsEnabled(LPTIM_Module* LPTIMx); +void LPTIM_StartCounter(LPTIM_Module* LPTIMx, uint32_t OperatingMode); +void LPTIM_SetUpdateMode(LPTIM_Module* LPTIMx, uint32_t UpdateMode); +uint32_t LPTIM_GetUpdateMode(LPTIM_Module* LPTIMx); +void LPTIM_SetAutoReloadValue(LPTIM_Module* LPTIMx, uint32_t AutoReload); +uint32_t LPTIM_GetAutoReloadValue(LPTIM_Module* LPTIMx); +void LPTIM_SetCompareValue(LPTIM_Module* LPTIMx, uint32_t CompareValue); +uint32_t LPTIM_GetCompareValue(LPTIM_Module* LPTIMx); +uint32_t LPTIM_GetCounterValue(LPTIM_Module* LPTIMx); +void LPTIM_SetCounterMode(LPTIM_Module* LPTIMx, uint32_t CounterMode); +uint32_t LPTIM_GetCounterMode(LPTIM_Module* LPTIMx); +void LPTIM_ConfigOutput(LPTIM_Module* LPTIMx, uint32_t Waveform, uint32_t Polarity); +void LPTIM_SetWaveform(LPTIM_Module* LPTIMx, uint32_t Waveform); +uint32_t LPTIM_GetWaveform(LPTIM_Module* LPTIMx); +void LPTIM_SetPolarity(LPTIM_Module* LPTIMx, uint32_t Polarity); +uint32_t LPTIM_GetPolarity(LPTIM_Module* LPTIMx); +void LPTIM_SetPrescaler(LPTIM_Module* LPTIMx, uint32_t Prescaler); +uint32_t LPTIM_GetPrescaler(LPTIM_Module* LPTIMx); +void LPTIM_TimeoutCmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd); +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module* LPTIMx); +void LPTIM_SoftwareTrigger(LPTIM_Module* LPTIMx); +void LPTIM_ConfigTrigger(LPTIM_Module* LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity); +uint32_t LPTIM_GetTriggerSource(LPTIM_Module* LPTIMx); +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module* LPTIMx); +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module* LPTIMx); +void LPTIM_SetClockSource(LPTIM_Module* LPTIMx, uint32_t ClockSource); +uint32_t LPTIM_GetClockSource(LPTIM_Module* LPTIMx); +void LPTIM_ConfigClock(LPTIM_Module* LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity); +uint32_t LPTIM_GetClockPolarity(LPTIM_Module* LPTIMx); +uint32_t LPTIM_GetClockFilter(LPTIM_Module* LPTIMx); +void LPTIM_SetEncoderModeClockPolarity(LPTIM_Module* LPTIMx, uint32_t ClockPolarity); +uint32_t LPTIM_GetEncoderModeClockPolarity(LPTIM_Module* LPTIMx); +void LPTIM_EncoderModeCmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd); +void LPTIM_NoEncoderModeCmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd); +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module* LPTIMx); +uint32_t LPTIM_IsEnabledNoEncoderMode(LPTIM_Module* LPTIMx); +void LPTIM_ClearIntFlag(LPTIM_Module* LPTIMx, uint32_t IntFlag); +uint32_t LPTIM_IsActiveIntStatus(LPTIM_Module* LPTIMx, uint32_t IntSts); +void LPTIM_ConfigInt(LPTIM_Module* LPTIMx, uint32_t Interrupt, FunctionalStatus Cmd); +uint32_t LPTIM_IsEnabledInt(LPTIM_Module* LPTIMx, uint32_t Interrupt); +void LPTIM_ConfigInput1(LPTIM_Module* LPTIMx, uint32_t ConnectSelect); +void LPTIM_ConfigInput2(LPTIM_Module* LPTIMx, uint32_t ConnectSelect); + + +/*** LPTIM Driving Functions Declaration End ***/ + + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_LPTIM_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lpuart.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lpuart.h new file mode 100644 index 0000000000..241d553892 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_lpuart.h @@ -0,0 +1,319 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_lpuart.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_LPUART_H__ +#define __N32H76X_LPUART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + + +/** @addtogroup LPUART + * @{ + */ + +/** @addtogroup LPUART_Exported_Types + * @{ + */ + +/** + * @brief LPUART Init Structure definition + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate))) + - FractionalDivider */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (only support + 8 data bits). */ + + uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref Mode */ + + uint32_t RtsThreshold; /* Specifies RTS Threshold. + This parameter can be a value of @ref RtsThreshold */ + + uint32_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref LPUART_Hardware_Flow_Control */ +} LPUART_InitType; + +#define LPUART_REG_BIT_MASK (uint32_t)0x00000000U + +#define CTRL_CLR_MASK ((uint32_t)(~(LPUART_CTRL_RXEN \ + |LPUART_CTRL_TXEN \ + |LPUART_CTRL_PC \ + |LPUART_CTRL_PEN \ + |LPUART_CTRL_RTST_0 \ + |LPUART_CTRL_RTST_1\ + |LPUART_CTRL_CTSEN \ + |LPUART_CTRL_RTSEN))) /*!< LPUART CTRL Mask */ + + + + +/** LPUART parity selection **/ + +#define LPUART_PE_NO ((uint32_t)LPUART_CTRL_PC) /* LPUART parity disable */ +#define LPUART_PE_EVEN ((uint32_t)LPUART_REG_BIT_MASK)/* Even parity */ +#define LPUART_PE_ODD ((uint32_t)LPUART_CTRL_PEN) /* Odd parity */ +#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD)) + + +/** LPUART is configured as RX or TX **/ +#define LPUART_MODE_RX ((uint32_t)LPUART_CTRL_RXEN) /* Transmitter enable */ +#define LPUART_MODE_TX ((uint32_t)LPUART_CTRL_TXEN) /* Receiver enable */ +#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX)) + + +/** LPUART RtsThreshold **/ +#define LPUART_RTSTH_FIFOHF ((uint32_t)LPUART_REG_BIT_MASK) +#define LPUART_RTSTH_FIFO3QF ((uint32_t)LPUART_CTRL_RTST_0) +#define LPUART_RTSTH_FIFOFU ((uint32_t)LPUART_CTRL_RTST_1) +#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \ + (((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU)) + + + /** LPUART Hardware Flow Control **/ +#define CTRL_HFCTRL_MASK ((uint32_t)(~LPUART_HFCTRL_RTS_CTS)) /* LPUART HFCTRL Bit Mask */ +#define LPUART_HFCTRL_NONE ((uint32_t)LPUART_REG_BIT_MASK) +#define LPUART_HFCTRL_CTS ((uint32_t)LPUART_CTRL_CTSEN) +#define LPUART_HFCTRL_RTS ((uint32_t)LPUART_CTRL_RTSEN) +#define LPUART_HFCTRL_RTS_CTS ((uint32_t)(LPUART_CTRL_CTSEN | LPUART_CTRL_RTSEN)) +#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \ + (((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \ + || ((CONTROL) == LPUART_HFCTRL_RTS_CTS)) + +/** LPUART_Interrupt_definition **/ +#define LPUART_INT_MASK ((uint32_t)0x00007FFFU) /* LPUART Interrupt Mask */ +#define LPUART_INT_PE ((uint32_t)LPUART_INTEN_PCEIEN) +#define LPUART_INT_TXC ((uint32_t)LPUART_INTEN_TXCIEN) +#define LPUART_INT_RXFIFO_OV ((uint32_t)LPUART_INTEN_RXFOIEN) +#define LPUART_INT_RXFIFO_FU ((uint32_t)LPUART_INTEN_RXFFIEN) +#define LPUART_INT_RXFIFO_HF ((uint32_t)LPUART_INTEN_RXFHFIEN) +#define LPUART_INT_RXFIFO_NE ((uint32_t)LPUART_INTEN_RXFNEIEN) +#define LPUART_INT_WUF ((uint32_t)LPUART_INTEN_WUIEN) +#define LPUART_INT_TXFIFO_OV ((uint32_t)LPUART_INTEN_TXFOIEN) +#define LPUART_INT_TXFIFO_FU ((uint32_t)LPUART_INTEN_TXFFIEN) +#define LPUART_INT_TXFIFO_QF ((uint32_t)LPUART_INTEN_TXFQFIEN) +#define LPUART_INT_TXFIFO_HF ((uint32_t)LPUART_INTEN_TXFHFIEN) +#define LPUART_INT_TXFIFO_NE ((uint32_t)LPUART_INTEN_TXFNEIEN) + +#define LPUART_INT_IDLEF ((uint32_t)LPUART_INTEN_IDLEFIEN) +#define LPUART_INT_FE ((uint32_t)LPUART_INTEN_FEIEN) +#define LPUART_INT_TXFIFO_EM ((uint32_t)LPUART_INTEN_TXFEIEN) + + +#define IS_LPUART_CFG_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_RXFIFO_OV) || ((IT) == LPUART_INT_RXFIFO_FU) \ + || ((IT) == LPUART_INT_RXFIFO_HF) || ((IT) == LPUART_INT_RXFIFO_NE) || ((IT) == LPUART_INT_WUF)||((IT) == LPUART_INT_TXFIFO_OV) \ + || ((IT) == LPUART_INT_TXFIFO_FU) || ((IT) == LPUART_INT_TXFIFO_QF) || ((IT) == LPUART_INT_TXFIFO_HF)||((IT) == LPUART_INT_TXFIFO_NE) \ + || ((IT) == LPUART_INT_IDLEF) || ((IT) == LPUART_INT_FE) || ((IT) == LPUART_INT_TXFIFO_EM)) + +#define IS_LPUART_GET_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_RXFIFO_OV) || ((IT) == LPUART_INT_RXFIFO_FU) \ + || ((IT) == LPUART_INT_RXFIFO_HF) || ((IT) == LPUART_INT_RXFIFO_NE) || ((IT) == LPUART_INT_WUF)||((IT) == LPUART_INT_TXFIFO_OV) \ + || ((IT) == LPUART_INT_TXFIFO_FU) || ((IT) == LPUART_INT_TXFIFO_QF) || ((IT) == LPUART_INT_TXFIFO_HF)||((IT) == LPUART_INT_TXFIFO_NE) \ + || ((IT) == LPUART_INT_IDLEF) || ((IT) == LPUART_INT_FE) || ((IT) == LPUART_INT_TXFIFO_EM)) +#define IS_LPUART_CLR_INT(IT) \ + (((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_RXFIFO_OV) || ((IT) == LPUART_INT_RXFIFO_FU) \ + || ((IT) == LPUART_INT_RXFIFO_HF) || ((IT) == LPUART_INT_RXFIFO_NE) || ((IT) == LPUART_INT_WUF)||((IT) == LPUART_INT_TXFIFO_OV) \ + || ((IT) == LPUART_INT_TXFIFO_FU) || ((IT) == LPUART_INT_TXFIFO_QF) || ((IT) == LPUART_INT_TXFIFO_HF)||((IT) == LPUART_INT_TXFIFO_NE) \ + || ((IT) == LPUART_INT_IDLEF) || ((IT) == LPUART_INT_FE) || ((IT) == LPUART_INT_TXFIFO_EM)) + +/** LPUART_DMA_Requests **/ +#define LPUART_DMAREQ_TX ((uint32_t)LPUART_CTRL_DMATXEN) +#define LPUART_DMAREQ_RX ((uint32_t)LPUART_CTRL_DMARXEN) + +#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF9F) == (uint32_t)0x00) && ((DMAREQ) != (uint32_t)0x00)) + + +/** LPUART_WakeUp_methods **/ +#define LPUART_WUSTP_ON ((uint32_t)LPUART_CTRL_WUSTPEN) +#define LPUART_WUSTP_STARTBIT ((uint32_t)(LPUART_CTRL_WUS_0|LPUART_CTRL_WUS_1|LPUART_CTRL_WUS_3)) +#define LPUART_WUSTP_RXNE ((uint32_t)LPUART_CTRL_WUS_0) +#define LPUART_WUSTP_BYTE ((uint32_t)LPUART_CTRL_WUS_1) +#define LPUART_WUSTP_FRAME_2 ((uint32_t)(LPUART_CTRL_WUS_1|LPUART_CTRL_WUS_0)) +#define LPUART_WUSTP_FRAME_3 ((uint32_t)(LPUART_CTRL_WUS_2) +#define LPUART_WUSTP_FRAME_4 ((uint32_t)(LPUART_CTRL_WUS_2|LPUART_CTRL_WUS_0)) +#define LPUART_WUSTP_FRAME_5 ((uint32_t)(LPUART_CTRL_WUS_2|LPUART_CTRL_WUS_1)) +#define LPUART_WUSTP_FRAME_6 ((uint32_t)(LPUART_CTRL_WUS_2|LPUART_CTRL_WUS_1|LPUART_CTRL_WUS_0)) +#define LPUART_WUSTP_FRAME_7 ((uint32_t)LPUART_CTRL_WUS_3) +#define LPUART_WUSTP_FRAME_8 ((uint32_t)(LPUART_CTRL_WUS_3|LPUART_CTRL_WUS_0)) +#define LPUART_WUSTP_FRAME_MANY ((uint32_t)(LPUART_CTRL_WUS_3|LPUART_CTRL_WUS_1)) +#define CTRL_WUSTP_MASK ((uint32_t)(~(LPUART_CTRL_WUS_0|LPUART_CTRL_WUS_1|LPUART_CTRL_WUS_2|LPUART_CTRL_WUS_3))) /*!< LPUART WakeUp Method Mask */ + +#define IS_LPUART_WAKEUP(WAKEUP) \ + (((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME_2) \ + ((WAKEUP) == LPUART_WUSTP_FRAME_3) || ((WAKEUP) == LPUART_WUSTP_FRAME_4) || ((WAKEUP) == LPUART_WUSTP_FRAME_5) || ((WAKEUP) == LPUART_WUSTP_FRAME_6) \ + ((WAKEUP) == LPUART_WUSTP_FRAME_7) || ((WAKEUP) == LPUART_WUSTP_FRAME_8) || ((WAKEUP) == LPUART_WUSTP_FRAME_MANY)) + +/** LPUART_Sampling_methods **/ +#define LPUART_SMPCNT_3B ((uint32_t)LPUART_REG_BIT_MASK) +#define LPUART_SMPCNT_1B ((uint32_t)LPUART_CTRL_SSM) +#define CTRL_SMPCNT_MASK ((uint32_t)(~LPUART_CTRL_SSM)) /*!< LPUART Sampling Method Mask */ + +/** LPUART_Flush_TXFIFO **/ +#define LPUART_FLUSHTXF_ENABLE ((uint32_t)LPUART_CTRL_FTXF) +#define LPUART_FLUSHTXF_DISABLE ((uint32_t)(~LPUART_CTRL_FTXF)) + + +/** LPUART_Flush_RXFIFO **/ +#define LPUART_FLUSHRXF_ENABLE ((uint32_t)LPUART_CTRL_FRXF) +#define LPUART_FLUSHRXF_DISABLE ((uint32_t)(~LPUART_CTRL_FRXF)) + + +/** LPUART_IDLEFRAME_DETECT **/ +#define LPUART_IDLEF_ENABLE ((uint32_t)LPUART_CTRL_IDLEFEN) /* LPUART Idle frame Enable */ +#define LPUART_IDLEF_DISABLE ((uint32_t)(~LPUART_CTRL_IDLEFEN)) /* LPUART Idle frame Disable */ + +/** LPUART_LoopBack_Self-Test **/ +#define LPUART_LOOPBACK_ENABLE ((uint32_t)LPUART_CTRL_LB) +#define LPUART_LOOPBACK_DISABLE ((uint32_t)(~LPUART_CTRL_LB)) + + +/** LPUART_Flags **/ + +#define LPUART_FLAG_PE ((uint32_t)LPUART_INTEN_PCEIEN) +#define LPUART_FLAG_TXC ((uint32_t)LPUART_STS_TXCF) +#define LPUART_FLAG_RXFIFO_OV ((uint32_t)LPUART_STS_RXFOF) +#define LPUART_FLAG_RXFIFO_FU ((uint32_t)LPUART_STS_RXFFF) +#define LPUART_FLAG_RXFIFO_HF ((uint32_t)LPUART_STS_RXFHFF) +#define LPUART_FLAG_RXFIFO_NE ((uint32_t)LPUART_STS_RXFNEF) +#define LPUART_FLAG_CTS ((uint32_t)LPUART_STS_CTSF) +#define LPUART_FLAG_WUF ((uint32_t)LPUART_STS_WUF) +#define LPUART_FLAG_NEF ((uint32_t)LPUART_STS_NEF) +#define LPUART_FLAG_TXFIFO_OV ((uint32_t)LPUART_STS_TXFOF) +#define LPUART_FLAG_TXFIFO_FU ((uint32_t)LPUART_STS_TXFFF) +#define LPUART_FLAG_TXFIFO_QF ((uint32_t)LPUART_STS_TXFQFF) +#define LPUART_FLAG_TXFIFO_HF ((uint32_t)LPUART_STS_TXFHFF) +#define LPUART_FLAG_TXFIFO_NE ((uint32_t)LPUART_STS_TXFNEF) +#define LPUART_FLAG_IDLEF ((uint32_t)LPUART_STS_IDLEF) +#define LPUART_FLAG_FRAME_ER ((uint32_t)LPUART_STS_FE) +#define LPUART_FLAG_TXFIFO_EM ((uint32_t)LPUART_STS_TXFEF) + + +#define IS_LPUART_FLAG(FLAG) \ + (((FLAG) == LPUART_FLAG_PE) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_RXFIFO_OV) \ + || ((FLAG) == LPUART_FLAG_RXFIFO_FU) || ((FLAG) == LPUART_FLAG_RXFIFO_HF) || ((FLAG) == LPUART_FLAG_RXFIFO_NE) \ + || ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NEF) \ + || ((FLAG) == LPUART_FLAG_TXFIFO_OV) || ((FLAG) == LPUART_FLAG_TXFIFO_FU) || ((FLAG) == LPUART_FLAG_TXFIFO_QF) \ + || ((FLAG) == LPUART_FLAG_TXFIFO_HF) || ((FLAG) == LPUART_FLAG_TXFIFO_NE) || ((FLAG) == LPUART_FLAG_IDLEF) \ + || ((FLAG) == LPUART_FLAG_FRAME_ER) || ((FLAG) == LPUART_FLAG_TXFIFO_EM) ) + +//#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000)) + +#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF) + + + + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup LPUART_Exported_Functions + * @{ + */ + + + + + +void LPUART_DeInit(LPUART_Module* LPUARTx); +void LPUART_Init(LPUART_Module* LPUARTx, LPUART_InitType* LPUART_InitStruct); +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct); +void LPUART_FlushRxFifo(LPUART_Module* LPUARTx); +void LPUART_FlushTxFifo(LPUART_Module* LPUARTx); +void LPUART_ConfigInt(LPUART_Module* LPUARTx,uint32_t LPUART_INT, FunctionalState Cmd); +void LPUART_EnableDMA(LPUART_Module* LPUARTx,uint32_t LPUART_DMAReq, FunctionalState Cmd); +void LPUART_ConfigWakeUpMethod(LPUART_Module* LPUARTx,uint32_t LPUART_WakeUpMethod); +void LPUART_EnableWakeUpStop(LPUART_Module* LPUARTx,FunctionalState Cmd); +void LPUART_ConfigSamplingMethod(LPUART_Module* LPUARTx,uint32_t LPUART_SamplingMethod); +void LPUART_EnableLoopBack(LPUART_Module* LPUARTx,FunctionalState Cmd); +void LPUART_SendData(LPUART_Module* LPUARTx,uint8_t Data); +uint8_t LPUART_ReceiveData(LPUART_Module* LPUARTx); +void LPUART_ConfigWakeUpData(LPUART_Module* LPUARTx,uint32_t LPUART_WakeUpData1,uint32_t LPUART_WakeUpData2); +FlagStatus LPUART_GetFlagStatus(LPUART_Module* LPUARTx,uint32_t LPUART_FLAG); +void LPUART_ClrFlag(LPUART_Module* LPUARTx,uint32_t LPUART_FLAG); +INTStatus LPUART_GetIntStatus(LPUART_Module* LPUARTx,uint32_t LPUART_INT); +void LPUART_ClrIntPendingBit(LPUART_Module* LPUARTx,uint32_t LPART_INT); +void LPUART_IdleFrameSet(LPUART_Module* LPUARTx,FunctionalState Cmd); +void LPUART_ConfigRXByte(LPUART_Module* LPUARTx,uint8_t LPUART_RXNUMWU); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_LPUART_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mdma.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mdma.h new file mode 100644 index 0000000000..1d1524f145 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mdma.h @@ -0,0 +1,540 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_mdma.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_MDMA_H__ +#define __N32H76x_78x_MDMA_H__ + + +#include +#include "n32h76x_78x.h" + + +#if defined (MDMA) + + +/** MDMA Channel Numbers per MDMA Controller definition **/ +#define MDMA_NUM_CHANNELS (16U) + +/** MDMA Channel Enable/Disable definition **/ +#define MDMA_CH_ENABLE ((uint32_t)(MDMA_CHEN_CH0WEN | MDMA_CHEN_CH0)) +#define MDMA_CH_DISABLE ((uint32_t)(MDMA_CHEN_CH0WEN & (~MDMA_CHEN_CH0))) + +/** MDMA Channel Suspend/Resume definition **/ +#define MDMA_CH_SUSPEND ((uint32_t)(MDMA_CHSUSP_CH0WEN | MDMA_CHSUSP_CH0)) +#define MDMA_CH_RESUME ((uint32_t)(MDMA_CHSUSP_CH0WEN & (~MDMA_CHSUSP_CH0))) + +/** MDMA Common Register Interrupt definition **/ +#define MDMA_COMMON_INT_SIURDEI ((uint32_t)MDMA_CRINTSTSEN_SIURDEIS) /* Slave Interface Undefined Register Decode Error Interrupt */ +#define MDMA_COMMON_INT_SICRWOHEI ((uint32_t)MDMA_CRINTSTSEN_SICRWOHEIS) /* Slave Interface Common Register Write On Hold Error Interrupt */ +#define MDMA_COMMON_INT_SICRR2WOEI ((uint32_t)MDMA_CRINTSTSEN_SICRR2WOEIS) /* Slave Interface Common Register Read to Write Only Error Interrupt */ +#define MDMA_COMMON_INT_SICRW2ROEI ((uint32_t)MDMA_CRINTSTSEN_SICRW2ROEIS) /* Slave Interface Common Register Write to Read Only Error Interrupt */ +#define MDMA_COMMON_INT_SICRDEI ((uint32_t)MDMA_CRINTSTSEN_SICRDEIS) /* Slave Interface Common Register Decode Error Interrupt */ + +/** MDMA Clear Common Register Interrupt definition **/ +#define MDMA_COMMON_INT_CLEAR ((uint32_t)(MDMA_CRINTCLR_SIURDEIC | \ + MDMA_CRINTCLR_SICRWOHEIC | \ + MDMA_CRINTCLR_SICRR2WOEIC | \ + MDMA_CRINTCLR_SICRW2ROEIC | \ + MDMA_CRINTCLR_SICRDEIC)) + +/** MDMA Common Register Interrupt Status Enable register mask definition **/ +#define MDMA_COMMON_INT_STS_MASK ((uint32_t)(MDMA_CRINTSTSEN_SIURDEIS | \ + MDMA_CRINTSTSEN_SICRWOHEIS | \ + MDMA_CRINTSTSEN_SICRR2WOEIS | \ + MDMA_CRINTSTSEN_SICRW2ROEIS | \ + MDMA_CRINTSTSEN_SICRDEIS)) + +/** MDMA Common Register Interrupt Signal Enable register mask definition **/ +#define MDMA_COMMON_INT_SGL_MASK ((uint32_t)(MDMA_CRINTSGLEN_SIURDEIS | \ + MDMA_CRINTSGLEN_SICRWOHEIS | \ + MDMA_CRINTSGLEN_SICRR2WOEIS | \ + MDMA_CRINTSGLEN_SICRW2ROEIS | \ + MDMA_CRINTSGLEN_SICRDEIS)) + +/** MDMA Channel Interrupt definition **/ +#define MDMA_CH_INT_CH_ABORTED ((uint32_t)MDMA_CHNINTSTSEN_CHA) +#define MDMA_CH_INT_CH_DISABLED ((uint32_t)MDMA_CHNINTSTSEN_CHD) +#define MDMA_CH_INT_CH_SUSPENDED ((uint32_t)MDMA_CHNINTSTSEN_CHS) +#define MDMA_CH_INT_CH_SRC_SUSPENDED ((uint32_t)MDMA_CHNINTSTSEN_CHSS) +#define MDMA_CH_INT_CH_LOCK_CLEARED ((uint32_t)MDMA_CHNINTSTSEN_CHLC) +#define MDMA_CH_INT_SLV_IF_W_ON_HOLD_ERR ((uint32_t)MDMA_CHNINTSTSEN_SIWOHE) +#define MDMA_CH_INT_SLV_IF_W_ON_CH_EN_ERR ((uint32_t)MDMA_CHNINTSTSEN_SIWOCEE) +#define MDMA_CH_INT_SLV_IF_R2WO_ERR ((uint32_t)MDMA_CHNINTSTSEN_SIRTWOE) +#define MDMA_CH_INT_SLV_IF_W2RO_ERR ((uint32_t)MDMA_CHNINTSTSEN_SIWTROE) +#define MDMA_CH_INT_SLV_IF_DEC_ERR ((uint32_t)MDMA_CHNINTSTSEN_SIDE) +#define MDMA_CH_INT_SLV_IF_MULTI_BLK_TYPE_ERR ((uint32_t)MDMA_CHNINTSTSEN_SIMBTE) +#define MDMA_CH_INT_SDW_REG_LLI_INVALID_ERR ((uint32_t)MDMA_CHNINTSTSEN_SLIE) +#define MDMA_CH_INT_LLI_W_SLV_ERR ((uint32_t)MDMA_CHNINTSTSEN_LWSE) +#define MDMA_CH_INT_LLI_R_SLV_ERR ((uint32_t)MDMA_CHNINTSTSEN_LRSE) +#define MDMA_CH_INT_LLI_W_DEC_ERR ((uint32_t)MDMA_CHNINTSTSEN_LWDE) +#define MDMA_CH_INT_LLI_R_DEC_ERR ((uint32_t)MDMA_CHNINTSTSEN_LRDE) +#define MDMA_CH_INT_DST_SLV_ERR ((uint32_t)MDMA_CHNINTSTSEN_DSTSE) +#define MDMA_CH_INT_SRC_SLV_ERR ((uint32_t)MDMA_CHNINTSTSEN_SRCSE) +#define MDMA_CH_INT_DST_DEC_ERR ((uint32_t)MDMA_CHNINTSTSEN_DSTDE) +#define MDMA_CH_INT_SRC_DEC_ERR ((uint32_t)MDMA_CHNINTSTSEN_SRCDE) +#define MDMA_CH_INT_DST_TRAN_COMPLE ((uint32_t)MDMA_CHNINTSTSEN_DSTTC) +#define MDMA_CH_INT_SRC_TRAN_COMPLE ((uint32_t)MDMA_CHNINTSTSEN_SRCTC) +#define MDMA_CH_INT_DMA_TRF_DONE ((uint32_t)MDMA_CHNINTSTSEN_DMATD) +#define MDMA_CH_INT_BLK_TRF_DONE ((uint32_t)MDMA_CHNINTSTSEN_BLKTD) + +/** MDMA Clear Channel Interrupt definition **/ +#define MDMA_CH_INT_CLEAR ((uint32_t)(MDMA_CHNINTCLR_CHA | \ + MDMA_CHNINTCLR_CHD | \ + MDMA_CHNINTCLR_CHS | \ + MDMA_CHNINTCLR_CHSS | \ + MDMA_CHNINTCLR_CHLC | \ + MDMA_CHNINTCLR_SIWOHE | \ + MDMA_CHNINTCLR_SIWOCEE | \ + MDMA_CHNINTCLR_SIRTWOE | \ + MDMA_CHNINTCLR_SIWTROE | \ + MDMA_CHNINTCLR_SIDE | \ + MDMA_CHNINTCLR_SIMBTE | \ + MDMA_CHNINTCLR_SLIE | \ + MDMA_CHNINTCLR_LWSE | \ + MDMA_CHNINTCLR_LRSE | \ + MDMA_CHNINTCLR_LWDE | \ + MDMA_CHNINTCLR_LRDE | \ + MDMA_CHNINTCLR_DSTSE | \ + MDMA_CHNINTCLR_SRCSE | \ + MDMA_CHNINTCLR_DSTDE | \ + MDMA_CHNINTCLR_SRCDE | \ + MDMA_CHNINTCLR_DSTTC | \ + MDMA_CHNINTCLR_SRCTC | \ + MDMA_CHNINTCLR_DMATD | \ + MDMA_CHNINTCLR_BLKTD)) + +/** MDMA Channel Interrupt Status Enable register mask definition **/ +#define MDMA_CH_INT_STS_MASK ((uint32_t)(MDMA_CHNINTSTSEN_CHA | \ + MDMA_CHNINTSTSEN_CHD | \ + MDMA_CHNINTSTSEN_CHS | \ + MDMA_CHNINTSTSEN_CHSS | \ + MDMA_CHNINTSTSEN_CHLC | \ + MDMA_CHNINTSTSEN_SIWOHE | \ + MDMA_CHNINTSTSEN_SIWOCEE | \ + MDMA_CHNINTSTSEN_SIRTWOE | \ + MDMA_CHNINTSTSEN_SIWTROE | \ + MDMA_CHNINTSTSEN_SIDE | \ + MDMA_CHNINTSTSEN_SIMBTE | \ + MDMA_CHNINTSTSEN_SLIE | \ + MDMA_CHNINTSTSEN_LWSE | \ + MDMA_CHNINTSTSEN_LRSE | \ + MDMA_CHNINTSTSEN_LWDE | \ + MDMA_CHNINTSTSEN_LRDE | \ + MDMA_CHNINTSTSEN_DSTSE | \ + MDMA_CHNINTSTSEN_SRCSE | \ + MDMA_CHNINTSTSEN_DSTDE | \ + MDMA_CHNINTSTSEN_SRCDE | \ + MDMA_CHNINTSTSEN_DSTTC | \ + MDMA_CHNINTSTSEN_SRCTC | \ + MDMA_CHNINTSTSEN_DMATD | \ + MDMA_CHNINTSTSEN_BLKTD)) + +/** MDMA Channel Interrupt Signal Enable register mask definition **/ +#define MDMA_CH_INT_SGL_MASK ((uint32_t)(MDMA_CHNINTSGLEN_CHA | \ + MDMA_CHNINTSGLEN_CHD | \ + MDMA_CHNINTSGLEN_CHS | \ + MDMA_CHNINTSGLEN_CHSS | \ + MDMA_CHNINTSGLEN_CHLC | \ + MDMA_CHNINTSGLEN_SIWOHE | \ + MDMA_CHNINTSGLEN_SIWOCEE | \ + MDMA_CHNINTSGLEN_SIRTWOE | \ + MDMA_CHNINTSGLEN_SIWTROE | \ + MDMA_CHNINTSGLEN_SIDE | \ + MDMA_CHNINTSGLEN_SIMBTE | \ + MDMA_CHNINTSGLEN_SLIE | \ + MDMA_CHNINTSGLEN_LWSE | \ + MDMA_CHNINTSGLEN_LRSE | \ + MDMA_CHNINTSGLEN_LWDE | \ + MDMA_CHNINTSGLEN_LRDE | \ + MDMA_CHNINTSGLEN_DSTSE | \ + MDMA_CHNINTSGLEN_SRCSE | \ + MDMA_CHNINTSGLEN_DSTDE | \ + MDMA_CHNINTSGLEN_SRCDE | \ + MDMA_CHNINTSGLEN_DSTTC | \ + MDMA_CHNINTSGLEN_SRCTC | \ + MDMA_CHNINTSGLEN_DMATD | \ + MDMA_CHNINTSGLEN_BLKTD)) + + + +/** MDMA Channel Number typedef **/ +typedef enum +{ + MDMA_CHANNEL_0 = 0x0UL, + MDMA_CHANNEL_1 = 0x1UL, + MDMA_CHANNEL_2 = 0x2UL, + MDMA_CHANNEL_3 = 0x3UL, + MDMA_CHANNEL_4 = 0x4UL, + MDMA_CHANNEL_5 = 0x5UL, + MDMA_CHANNEL_6 = 0x6UL, + MDMA_CHANNEL_7 = 0x7UL, + MDMA_CHANNEL_8 = 0x8UL, + MDMA_CHANNEL_9 = 0x9UL, + MDMA_CHANNEL_10 = 0xAUL, + MDMA_CHANNEL_11 = 0xBUL, + MDMA_CHANNEL_12 = 0xCUL, + MDMA_CHANNEL_13 = 0xDUL, + MDMA_CHANNEL_14 = 0xEUL, + MDMA_CHANNEL_15 = 0xFUL +} MDMA_ChNumType; + +/** MDMA Channel Status typedef **/ +typedef enum +{ + MDMA_CH_STS_OK = 0, /* MDMA status OK */ + MDMA_CH_STS_ERROR, /* MDMA status Error */ + MDMA_CH_STS_BUSY /* MDMA status Busy */ +} MDMA_ChStatusType; + +/** MDMA Channel Master Select typedef **/ +typedef enum +{ + MDMA_CH_MASTER_1 = 0, /* AXI master 1 */ + MDMA_CH_MASTER_2 /* AXI master 2 */ +} MDMA_ChMasterSelType; + +/** MDMA channel multi block transfer type typedef **/ +typedef enum +{ + MDMA_CH_MULTI_BLOCK_CONTIGUOUS = 0x0UL, /* Contiguous Multiblock Type */ + MDMA_CH_MULTI_BLOCK_RELOAD = 0x1UL, /* Reload Multiblock Type */ + MDMA_CH_MULTI_BLOCK_LINKED_LIST = 0x3UL /* Linked List based Multiblock Type */ +} MDMA_ChMultBlkTfrType; + +/** MDMA channel transfer type and flow control typedef **/ +typedef enum +{ + MDMA_CH_TRANSFER_FLOW_M2M_MDMA = 0x0UL, /* Memory to memory (MDMA flow controller) */ + MDMA_CH_TRANSFER_FLOW_M2P_MDMA = 0x1UL, /* Memory to peripheral (MDMA flow controller) */ + MDMA_CH_TRANSFER_FLOW_P2M_MDMA = 0x2UL, /* Peripheral to memory (MDMA flow controller) */ + MDMA_CH_TRANSFER_FLOW_P2P_MDMA = 0x3UL, /* Peripheral to peripheral (MDMA flow controller) */ + MDMA_CH_TRANSFER_FLOW_P2M_SRCPER = 0x4UL, /* Peripheral to memory (Source Peripheral flow controller) */ + MDMA_CH_TRANSFER_FLOW_P2P_SRCPER = 0x5UL, /* Peripheral to peripheral (Source peripheral flow controller) */ + MDMA_CH_TRANSFER_FLOW_M2P_DSTPER = 0x6UL, /* Memory to peripheral (Destination Peripheral flow controller) */ + MDMA_CH_TRANSFER_FLOW_P2P_DSTPER = 0x7UL /* Peripheral to peripheral (Destination peripheral flow controller) */ +} MDMA_ChTfrFlowType; + +/** MDMA channel transfer width typedef **/ +typedef enum +{ + MDMA_CH_TRANSFER_WIDTH_8 = 0x0UL, /* 8-bit transfer width */ + MDMA_CH_TRANSFER_WIDTH_16 = 0x1UL, /* 16-bit transfer width */ + MDMA_CH_TRANSFER_WIDTH_32 = 0x2UL, /* 32-bit transfer width */ + MDMA_CH_TRANSFER_WIDTH_64 = 0x3UL /* 64-bit transfer width */ +} MDMA_ChTfrWidthType; + +/** MDMA channel burst transaction length typedef **/ +typedef enum +{ + MDMA_CH_BURST_TRAN_LEN_1 = 0x0UL, /* 1 Data Item read from Source in the burst transaction */ + MDMA_CH_BURST_TRAN_LEN_4 = 0x1UL, /* 4 Data Item read from Source in the burst transaction */ + MDMA_CH_BURST_TRAN_LEN_8 = 0x2UL, /* 8 Data Item read from Source in the burst transaction */ + MDMA_CH_BURST_TRAN_LEN_16 = 0x3UL, /* 16 Data Item read from Source in the burst transaction */ + MDMA_CH_BURST_TRAN_LEN_32 = 0x4UL, /* 32 Data Item read from Source in the burst transaction */ + MDMA_CH_BURST_TRAN_LEN_64 = 0x5UL, /* 64 Data Item read from Source in the burst transaction */ + MDMA_CH_BURST_TRAN_LEN_128 = 0x6UL, /* 128 Data Item read from Source in the burst transaction */ +} MDMA_ChBurstTranLenType; + +/** MDMA channel address count mode typedef **/ +typedef enum +{ + MDMA_CH_ADDRESS_COUNT_MODE_INCREMENT = 0x0UL, /* Address count mode: increment */ + MDMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE = 0x1UL /* Address count mode: no change */ +} MDMA_ChAddrCountType; + +/** MDMA channel priorities typedef **/ +typedef enum +{ + MDMA_CH_PRIORITY_0 = 0x0UL, /* MDMA channel priority 0 (low) */ + MDMA_CH_PRIORITY_1 = 0x1UL, /* MDMA channel priority 1 */ + MDMA_CH_PRIORITY_2 = 0x2UL, /* MDMA channel priority 2 */ + MDMA_CH_PRIORITY_3 = 0x3UL, /* MDMA channel priority 3 */ + MDMA_CH_PRIORITY_4 = 0x4UL, /* MDMA channel priority 4 */ + MDMA_CH_PRIORITY_5 = 0x5UL, /* MDMA channel priority 5 */ + MDMA_CH_PRIORITY_6 = 0x6UL, /* MDMA channel priority 6 */ + MDMA_CH_PRIORITY_7 = 0x7UL, /* MDMA channel priority 7 */ + MDMA_CH_PRIORITY_8 = 0x8UL, /* MDMA channel priority 8 */ + MDMA_CH_PRIORITY_9 = 0x9UL, /* MDMA channel priority 9 */ + MDMA_CH_PRIORITY_10 = 0xAUL, /* MDMA channel priority 10 */ + MDMA_CH_PRIORITY_11 = 0xBUL, /* MDMA channel priority 11 */ + MDMA_CH_PRIORITY_12 = 0xCUL, /* MDMA channel priority 12 */ + MDMA_CH_PRIORITY_13 = 0xDUL, /* MDMA channel priority 13 */ + MDMA_CH_PRIORITY_14 = 0xEUL, /* MDMA channel priority 14 */ + MDMA_CH_PRIORITY_15 = 0xFUL /* MDMA channel priority 15 (high) */ +} MDMA_ChPriorType; + +/** MDMA channel Source handshake interface typedef **/ +typedef enum +{ + MDMA_CH_SRC_HANDSHAKING_HARDWARE = 0x0UL, /* Source: hardware handshake */ + MDMA_CH_SRC_HANDSHAKING_SOFTWARE = 0x1UL /* Source: software handshake */ +} MDMA_ChSrcHsType; + +/** MDMA channel Destination handshake interface typedef **/ +typedef enum +{ + MDMA_CH_DST_HANDSHAKING_HARDWARE = 0x0UL, /* Destination: hardware handshake */ + MDMA_CH_DST_HANDSHAKING_SOFTWARE = 0x1UL /* Destination: software handshake */ +} MDMA_ChDstHsType; + +/** MDMA channel hardware handshaking interface typedef, available when MDMA is flow controller **/ +typedef enum +{ + MDMA_CH_HARDWARE_HANDSHAKING_IF_0 = 0x0UL, /* Hardware handshaking interface 0 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_1 = 0x1UL, /* Hardware handshaking interface 1 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_2 = 0x2UL, /* Hardware handshaking interface 2 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_3 = 0x3UL, /* Hardware handshaking interface 3 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_4 = 0x4UL, /* Hardware handshaking interface 4 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_5 = 0x5UL, /* Hardware handshaking interface 5 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_6 = 0x6UL, /* Hardware handshaking interface 6 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_7 = 0x7UL, /* Hardware handshaking interface 7 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_8 = 0x8UL, /* Hardware handshaking interface 8 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_9 = 0x9UL, /* Hardware handshaking interface 9 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_10 = 0xAUL, /* Hardware handshaking interface 10 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_11 = 0xBUL, /* Hardware handshaking interface 11 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_12 = 0xCUL, /* Hardware handshaking interface 12 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_13 = 0xDUL, /* Hardware handshaking interface 13 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_14 = 0xEUL, /* Hardware handshaking interface 14 */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_15 = 0xFUL /* Hardware handshaking interface 15 */ +} MDMA_ChHwHsIfType; + +/** MDMA channel hardware handshaking interface polarity typedef **/ +typedef enum +{ + MDMA_CH_HARDWARE_HANDSHAKING_IF_POL_H = 0x0UL, /* Active HIGH */ + MDMA_CH_HARDWARE_HANDSHAKING_IF_POL_L = 0x1UL /* Active LOW */ +} MDMA_ChHwHsIfPolType; + +/** MDMA Channel Software Handshake transfer types typedef **/ +typedef enum +{ + MDMA_CH_SOFTWARE_HANDSHAKING_TFR_SINGLE, /* Single DMA transfer */ + MDMA_CH_SOFTWARE_HANDSHAKING_TFR_BURST /* Burst transfer */ +} MDMA_ChSwHsTfrType; + + +/** Start of section using anonymous unions **/ +#if defined (__CC_ARM) + /* Save the current compiler state (Keil only) */ + #pragma push + /* Enable anonymous unions */ + #pragma anon_unions +#elif defined(__ICCARM__) + /* Enable anonymous consortia */ + #pragma language=extended +#elif defined(__GNUC__) + /* GCC supports anonymous unions by default */ +#else + #warning "Anonymous unions may not be supported by this compiler. Check compiler documentation." +#endif + +/** MDMA channel linked list item structure, 64-bits alignment **/ +typedef struct __MDMA_LinkListItemType +{ + uint64_t SrcAddr; /* Source address */ + + uint64_t DstAddr; /* Destination address */ + + uint32_t BlkSize; /* MDMA block size for MDMA controlled transfers [max. 8191] */ + + uint32_t RESERVED0; /* Reserved */ + + struct __MDMA_LinkListItemType *pNext; /* The next linked list item pointer */ + + union + { + uint64_t ChCtrl; + struct + { + uint64_t SrcMasterSel: 1; /* Source Master Select "0: AXI master 1, 1: AXI Master 2" */ + uint64_t : 1; + uint64_t DstMasterSel: 1; /* Destination Master Select "0: AXI master 1, 1: AXI Master 2" */ + uint64_t : 1; + uint64_t SrcAddrInc: 1; /* Source Address Increment */ + uint64_t : 1; + uint64_t DstAddrInc: 1; /* Destination Address Increment */ + uint64_t : 1; + uint64_t SrcTfrWidth: 3; /* Source Transfer width */ + uint64_t DstTfrWidth: 3; /* Destination Transfer width */ + uint64_t SrcBurstTranLen: 4; /* Source Burst Transaction Length */ + uint64_t DstBurstTranLen: 4; /* Destination Burst Transaction Length */ + uint64_t : 8; + uint64_t NonPosLastWriteEn: 1; /* Non Posted Last Write Enable */ + uint64_t : 1; + + uint64_t : 6; + uint64_t SrcBurstLenEn: 1; /* Source Burst Length Enable */ + uint64_t SrcBurstLen: 8; /* Source Burst Length */ + uint64_t DstBurstLenEn: 1; /* Destination Burst Length Enable */ + uint64_t DstBurstLen: 8; /* Destination Burst Length */ + uint64_t : 2; + uint64_t IocBlkTfr: 1; /* Interrupt On completion of Block Transfer */ + uint64_t : 3; + uint64_t SdwLlILast: 1; /* Last Linked List Item */ + uint64_t SdwLlIValid: 1; /* Linked List Item (LLI) valid */ + }; + }; + +} MDMA_LinkListItemType; + +/** MDMA Channel Initialize configuration structure **/ +typedef struct +{ + union + { + uint64_t ChCtrl; + struct + { + uint64_t SrcMasterSel: 1; /* Source Master Select "0: AXI master 1, 1: AXI Master 2" */ + uint64_t : 1; + uint64_t DstMasterSel: 1; /* Destination Master Select "0: AXI master 1, 1: AXI Master 2" */ + uint64_t : 1; + uint64_t SrcAddrInc: 1; /* Source Address Increment */ + uint64_t : 1; + uint64_t DstAddrInc: 1; /* Destination Address Increment */ + uint64_t : 1; + uint64_t SrcTfrWidth: 3; /* Source Transfer width */ + uint64_t DstTfrWidth: 3; /* Destination Transfer width */ + uint64_t SrcBurstTranLen: 4; /* Source Burst Transaction Length */ + uint64_t DstBurstTranLen: 4; /* Destination Burst Transaction Length */ + uint64_t : 8; + uint64_t NonPosLastWriteEn: 1; /* Non Posted Last Write Enable */ + uint64_t : 1; + + uint64_t : 6; + uint64_t SrcBurstLenEn: 1; /* Source Burst Length Enable */ + uint64_t SrcBurstLen: 8; /* Source Burst Length */ + uint64_t DstBurstLenEn: 1; /* Destination Burst Length Enable */ + uint64_t DstBurstLen: 8; /* Destination Burst Length */ + uint64_t : 2; + uint64_t IocBlkTfr: 1; /* Interrupt On completion of Block Transfer */ + uint64_t : 3; + uint64_t SdwLlILast: 1; /* Last Linked List Item */ + uint64_t SdwLlIValid: 1; /* Linked List Item (LLI) valid */ + }; + }; + + uint64_t SrcAddr; /* Source address */ + uint64_t DstAddr; /* Destination address */ + MDMA_LinkListItemType *pLinkListItem; /* Linked list item pointer */ + + uint32_t BlkSize; /* MDMA block size for MDMA controlled transfers [max. 8191] */ + MDMA_ChPriorType ChannelPriority; /* MDMA channel priority */ + + MDMA_ChSrcHsType SrcHandshaking; /* MDMA source handshaking interface */ + MDMA_ChHwHsIfType SrcHsInterface; /* MDMA source assigned handshaking interface */ + MDMA_ChHwHsIfPolType SrcHsInterfacePol; /* MDMA source hardware handshaking interface polarity */ + MDMA_ChDstHsType DstHandshaking; /* MDMA destination handshaking interface */ + MDMA_ChHwHsIfType DstHsInterface; /* MDMA destination assigned handshaking interface */ + MDMA_ChHwHsIfPolType DstHsInterfacePol; /* MDMA destination hardware handshaking interface polarity */ + + MDMA_ChTfrFlowType TfrTypeFlowCtrl; /* MDMA transfer type and flow control */ + MDMA_ChMultBlkTfrType SrcMultBlkTfrType; /* Source Multi Block Transfer Type */ + MDMA_ChMultBlkTfrType DstMultBlkTfrType; /* Destination Multi Block Transfer Type */ + +} MDMA_ChInitType; + +/** End of section using anonymous unions (Keil only) **/ +#if defined (__CC_ARM) + /* Restore compiler settings */ + #pragma pop +#endif + + +void MDMA_ControllerCmd(MDMA_Module *const MDMAy, FunctionalStatus Cmd); +bool MDMA_ControllerIsEnabled(MDMA_Module *const MDMAy); +void MDMA_ControllerSoftReset(MDMA_Module *const MDMAy); +void MDMA_ChannelCmd(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, FunctionalStatus Cmd); +bool MDMA_ChannelIsEnabled(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); +MDMA_ChStatusType MDMA_ChannelInit(MDMA_Module *const MDMAy, MDMA_ChInitType *const MDMA_ChInitParam, MDMA_ChNumType ChNum); +void MDMA_ChannelStructInit(MDMA_ChInitType *const MDMA_ChInitParam); +void MDMA_ChannelSuspend(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); +bool MDMA_ChannelIsSuspended(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); +void MDMA_ChannelResume(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); + +void MDMA_GlobalInterruptCmd(MDMA_Module *const MDMAy, FunctionalStatus Cmd); +void MDMA_CommonInterruptStatusCmd(MDMA_Module *const MDMAy, uint32_t Interrupt, FunctionalStatus Cmd); +void MDMA_CommonInterruptSignalCmd(MDMA_Module *const MDMAy, uint32_t Interrupt, FunctionalStatus Cmd); +void MDMA_ClearCommonInterruptStatus(MDMA_Module *const MDMAy, uint32_t Interrupt); +uint64_t MDMA_GetCombinedStatus(MDMA_Module *const MDMAy); +INTStatus MDMA_GetCommonInterruptStatus(MDMA_Module *const MDMAy, uint32_t Interrupt); +void MDMA_ChannelInterruptStatusCmd(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt, FunctionalStatus Cmd); +void MDMA_ChannelInterruptSignalCmd(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt, FunctionalStatus Cmd); +void MDMA_ClearChannelInterruptStatus(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt); +INTStatus MDMA_GetChannelInterruptStatus(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt); + +void MDMA_SetChannelSourceAddress(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint64_t Addr); +void MDMA_SetChannelDestinationAddress(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint64_t Addr); +void MDMA_SetChannelBlockSize(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Size); +uint32_t MDMA_GetTransferredNumber(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); +void MDMA_SetChannelLinkedListPointer(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint64_t StrAddr); +void MDMA_SetChannelSrcMultiBlockType(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChMultBlkTfrType Type); +void MDMA_SetChannelDstMultiBlockType(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChMultBlkTfrType Type); +void MDMA_TriggerSourceRequest(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChSwHsTfrType Type, bool isLast); +void MDMA_TriggerDestinationRequest(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChSwHsTfrType Type, bool isLast); +void MDMA_BlockTransferResumeRequest(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); + +void MDMA_SetChannelLinkedListItemValid(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); +bool MDMA_ChannelLinkedListItemIsValid(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); +void MDMA_SetChannelLastLinkedListItem(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum); + + + +#ifdef __cplusplus +} +#endif + +#endif /* defined (MDMA) */ +#endif /* __N32H76x_78x_MDMA_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mmu.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mmu.h new file mode 100644 index 0000000000..38795d2381 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_mmu.h @@ -0,0 +1,256 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_mmu.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_MMU_H__ +#define __N32H76X_78X_MMU_H__ + +#include "n32h76x_78x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** MMU Flash Key **/ +#define MMU_FLASH_KEY0 ((uint32_t) 0x89ABCDEFU) +#define MMU_FLASH_KEY1 ((uint32_t) 0x01234567U) + +/** MMU Control **/ +#define MMU_RESET (MMU_CTRL_RSTE) +#define MMU_INT_EN (MMU_CTRL_INTE) + +/** MMU status register **/ +#define MMU_XSPI_LOCK_FLAG (MMU_STS_XSPIL) +#define MMU_ITCM_RERR_FLAG (MMU_STS_ITRDE) +#define MMU_ITCM_WERR_FLAG (MMU_STS_ITWRE) +#define MMU_BKSRAM_RERR_FLAG (MMU_STS_BKRDE) +#define MMU_BKSRAM_WERR_FLAG (MMU_STS_BKWRE) +#define MMU_AHBSRAM5_RERR_FLAG (MMU_STS_H5RDE) +#define MMU_AHBSRAM5_WERR_FLAG (MMU_STS_H5WRE) +#define MMU_AHBSRAM4_RERR_FLAG (MMU_STS_H4RDE) +#define MMU_AHBSRAM4_WERR_FLAG (MMU_STS_H4WRE) +#define MMU_AHBSRAM3_RERR_FLAG (MMU_STS_H3RDE) +#define MMU_AHBSRAM3_WERR_FLAG (MMU_STS_H3WRE) +#define MMU_AHBSRAM2_RERR_FLAG (MMU_STS_H2RDE) +#define MMU_AHBSRAM2_WERR_FLAG (MMU_STS_H2WRE) +#define MMU_AHBSRAM1_RERR_FLAG (MMU_STS_H1RDE) +#define MMU_AHBSRAM1_WERR_FLAG (MMU_STS_H1WRE) +#define MMU_AXISRAM3_RERR_FLAG (MMU_STS_X3RDE) +#define MMU_AXISRAM3_WERR_FLAG (MMU_STS_X3WRE) +#define MMU_AXISRAM2_RERR_FLAG (MMU_STS_X2RDE) +#define MMU_AXISRAM2_WERR_FLAG (MMU_STS_X2WRE) +#define MMU_AXISRAM1_RERR_FLAG (MMU_STS_X1RDE) +#define MMU_AXISRAM1_WERR_FLAG (MMU_STS_X1WRE) +#define MMU_OB_LOCK_FLAG (MMU_STS_OBL) +#define MMU_FLASH_LOCK_FLAG (MMU_STS_FLASHL) +#define MMU_XSPI_RERR_FLAG (MMU_STS_XSPIRDE) + +/** MMU RTAD **/ +#define MMU_RTAD_ADDRESS_OFFSET ((uint32_t)0x00000034U) +#define MMU_RTAD1 ((uint32_t)0x00000001U) +#define MMU_RTAD2 ((uint32_t)0x00000002U) +#define MMU_RTAD3 ((uint32_t)0x00000003U) +#define MMU_RTAD4 ((uint32_t)0x00000004U) + +#define MMU_RTR_ADDRESS_OFFSET ((uint32_t)0x00000084U) +#define MMU_RTR_ENDADDR_OFFSET ((uint32_t)0x00000010U) +#define MMU_RTAD_REGION1 ((uint32_t)0x00000001U) +#define MMU_RTAD_REGION2 ((uint32_t)0x00000002U) +#define MMU_RTAD_REGION3 ((uint32_t)0x00000003U) +#define MMU_RTAD_REGION4 ((uint32_t)0x00000004U) + +#define MMU_RTAD_ENABLE (MMU_RTADC_REN) +#define MMU_RTAD_CFG_LOCK (MMU_RTADC_RCFGL) +#define MMU_RTAD_KEY_LOCK (MMU_RTADC_RKEYL) + +#define MMU_RTAD_MODE_DEC_INST ((uint32_t) 0x00000000U) +#define MMU_RTAD_MODE_DEC_DATA (MMU_RTADC_RMOD_0) +#define MMU_RTAD_MODE_DEC_ALL (MMU_RTADC_RMOD_1) +#define MMU_RTAD_MODE_MASK (MMU_RTADC_RMOD) + +#define MMU_RTAD_PROPERTY_INST ((uint32_t) 0x00000000U) +#define MMU_RTAD_PROPERTY_DATA (MMU_RTADC_RPROPERTY_0) +#define MMU_RTAD_PROPERTY_ALL (MMU_RTADC_RPROPERTY_1) +#define MMU_RTAD_PROPERTY_MASK (MMU_RTADC_RPROPERTY) + +#define MMU_RTAD_REGION1_PART0_KEY ((uint32_t) 0x00000044U) +#define MMU_RTAD_REGION1_PART1_KEY ((uint32_t) 0x00000048U) +#define MMU_RTAD_REGION1_PART2_KEY ((uint32_t) 0x0000004CU) +#define MMU_RTAD_REGION1_PART3_KEY ((uint32_t) 0x00000050U) + +#define MMU_RTAD_REGION2_PART0_KEY ((uint32_t) 0x00000054U) +#define MMU_RTAD_REGION2_PART1_KEY ((uint32_t) 0x00000058U) +#define MMU_RTAD_REGION2_PART2_KEY ((uint32_t) 0x0000005CU) +#define MMU_RTAD_REGION2_PART3_KEY ((uint32_t) 0x00000060U) + +#define MMU_RTAD_REGION3_PART0_KEY ((uint32_t) 0x00000064U) +#define MMU_RTAD_REGION3_PART1_KEY ((uint32_t) 0x00000068U) +#define MMU_RTAD_REGION3_PART2_KEY ((uint32_t) 0x0000006CU) +#define MMU_RTAD_REGION3_PART3_KEY ((uint32_t) 0x00000070U) + +#define MMU_RTAD_REGION4_PART0_KEY ((uint32_t) 0x00000074U) +#define MMU_RTAD_REGION4_PART1_KEY ((uint32_t) 0x00000078U) +#define MMU_RTAD_REGION4_PART2_KEY ((uint32_t) 0x0000007CU) +#define MMU_RTAD_REGION4_PART3_KEY ((uint32_t) 0x00000080U) + + +/** MMU Module Memory **/ +#define MMU_MEMORY_ADDRESS_OFFSET ((uint32_t)0x0000012CU) +#define MMU_MEMORY_EN (MMU_ETH1ME_EN) +#define MMU_MEMORY_ETH1 ((uint32_t) 0x00000001U) +#define MMU_MEMORY_ETH2 ((uint32_t) 0x00000002U) +#define MMU_MEMORY_USB1 ((uint32_t) 0x00000003U) +#define MMU_MEMORY_USB2 ((uint32_t) 0x00000004U) +#define MMU_MEMORY_SDMMC1 ((uint32_t) 0x00000005U) +#define MMU_MEMORY_SDMMC2 ((uint32_t) 0x00000006U) +#define MMU_MEMORY_DVP1 ((uint32_t) 0x00000007U) +#define MMU_MEMORY_DVP2 ((uint32_t) 0x00000008U) +#define MMU_MEMORY_DMA1 ((uint32_t) 0x00000009U) +#define MMU_MEMORY_DMA2 ((uint32_t) 0x0000000AU) +#define MMU_MEMORY_DMA3 ((uint32_t) 0x0000000BU) +#define MMU_MEMORY_MDMA ((uint32_t) 0x0000000CU) +#define MMU_MEMORY_JPEG ((uint32_t) 0x0000000DU) +#define MMU_MEMORY_LCDC ((uint32_t) 0x0000000EU) +#define MMU_MEMORY_GPU ((uint32_t) 0x0000000FU) +#define MMU_MEMORY_SDPU ((uint32_t) 0x00000010U) +#define MMU_MEMORY_UID_OFFSET (REG_BIT8_OFFSET) +#define MMU_MEMORY_MID_OFFSET (REG_BIT16_OFFSET) + +/** MMU Read Error Address Register **/ +#define MMU_XRAD_ADDR_OFFSET ((uint32_t) 0x00000178U) +#define MMU_X1RAD_ADDR_OFFSET ((uint32_t) 0x00000188U) +#define MMU_X2RAD_ADDR_OFFSET ((uint32_t) 0x00000198U) +#define MMU_X3RAD_ADDR_OFFSET ((uint32_t) 0x000001A8U) + +#define MMU_H1RAD_ADDR_OFFSET ((uint32_t) 0x0000021CU) +#define MMU_H2RAD_ADDR_OFFSET ((uint32_t) 0x0000022CU) +#define MMU_H3RAD_ADDR_OFFSET ((uint32_t) 0x0000023CU) +#define MMU_H4RAD_ADDR_OFFSET ((uint32_t) 0x0000024CU) +#define MMU_H5RAD_ADDR_OFFSET ((uint32_t) 0x0000025CU) + +#define MMU_BKRAD_ADDR_OFFSET ((uint32_t) 0x0000026CU) +#define MMU_ITRAD_ADDR_OFFSET ((uint32_t) 0x0000027CU) + +/** MMU Write Error Address Register **/ +#define MMU_X1WAD_ADDR_OFFSET ((uint32_t) 0x00000184U) +#define MMU_X2WAD_ADDR_OFFSET ((uint32_t) 0x00000194U) +#define MMU_X3WAD_ADDR_OFFSET ((uint32_t) 0x000001A4U) + +#define MMU_H1WAD_ADDR_OFFSET ((uint32_t) 0x00000218U) +#define MMU_H2WAD_ADDR_OFFSET ((uint32_t) 0x00000228U) +#define MMU_H3WAD_ADDR_OFFSET ((uint32_t) 0x00000238U) +#define MMU_H4WAD_ADDR_OFFSET ((uint32_t) 0x00000248U) +#define MMU_H5WAD_ADDR_OFFSET ((uint32_t) 0x00000258U) + +#define MMU_BKWAD_ADDR_OFFSET ((uint32_t) 0x00000268U) +#define MMU_ITWAD_ADDR_OFFSET ((uint32_t) 0x00000278U) + +/** MMU Read Error Debug Register **/ +#define MMU_XRD_ADDR_OFFSET ((uint32_t) 0x00000170U) +#define MMU_X1RD_ADDR_OFFSET ((uint32_t) 0x00000180U) +#define MMU_X2RD_ADDR_OFFSET ((uint32_t) 0x00000190U) +#define MMU_X3RD_ADDR_OFFSET ((uint32_t) 0x000001A0U) + +#define MMU_H1RD_ADDR_OFFSET ((uint32_t) 0x00000214U) +#define MMU_H2RD_ADDR_OFFSET ((uint32_t) 0x00000224U) +#define MMU_H3RD_ADDR_OFFSET ((uint32_t) 0x00000234U) +#define MMU_H4RD_ADDR_OFFSET ((uint32_t) 0x00000244U) +#define MMU_H5RD_ADDR_OFFSET ((uint32_t) 0x00000254U) + +#define MMU_BKRD_ADDR_OFFSET ((uint32_t) 0x00000264U) +#define MMU_ITRD_ADDR_OFFSET ((uint32_t) 0x00000274U) +#define MMU_RERRDEBUG_MID_OFFSET (REG_BIT8_OFFSET) + +/** MMU Write Error Debug Register **/ +#define MMU_X1WD_ADDR_OFFSET ((uint32_t) 0x0000017CU) +#define MMU_X2WD_ADDR_OFFSET ((uint32_t) 0x0000018CU) +#define MMU_X3WD_ADDR_OFFSET ((uint32_t) 0x0000019CU) + +#define MMU_H1WD_ADDR_OFFSET ((uint32_t) 0x00000210U) +#define MMU_H2WD_ADDR_OFFSET ((uint32_t) 0x00000220U) +#define MMU_H3WD_ADDR_OFFSET ((uint32_t) 0x00000230U) +#define MMU_H4WD_ADDR_OFFSET ((uint32_t) 0x00000240U) +#define MMU_H5WD_ADDR_OFFSET ((uint32_t) 0x00000250U) + +#define MMU_BKWD_ADDR_OFFSET ((uint32_t) 0x00000260U) +#define MMU_ITWD_ADDR_OFFSET ((uint32_t) 0x00000270U) +#define MMU_WERRDEBUG_MID_OFFSET (REG_BIT8_OFFSET) + +/** MMU Function **/ +void MMU_ConfigReset(FunctionalState Cmd); +void MMU_ConfigInt(FunctionalState Cmd); +FlagStatus MMU_GetFlagStatus(uint32_t MMU_FLAG); +void MMU_ClrFlag(uint32_t MMU_FLAG); +void MMU_EnableRTAD(uint32_t RTADx, FunctionalState Cmd); +uint32_t MMU_GetRTADRegionKey(uint32_t region); +void MMU_ConfigRTADCFGLock(uint32_t RTADx, FunctionalState Cmd); +void MMU_ConfigRTADKeyLock(uint32_t RTADx, FunctionalState Cmd); +void MMU_ConfigRTADMode(uint32_t RTADx, uint32_t mode); +void MMU_ConfigRTADProperty(uint32_t RTADx, uint32_t property); +void MMU_ConfigRTADRegionAddress(uint32_t region, uint32_t begin_addr, uint32_t end_addr); +uint32_t MMU_GetRTADCRC(void); +void MMU_EnableModuleMemory(uint32_t module, FunctionalState Cmd); +uint8_t MMU_GetModuleUserID(uint32_t module); +uint8_t MMU_GetModuleMasterID(uint32_t module); +uint32_t MMU_GetReadErrorAddress(uint32_t readerroraddr); +uint32_t MMU_GetWriteErrorAddress(uint32_t writeerroraddr); +uint32_t MMU_GetWriteErrorMasterID(uint32_t writeerrordebug); +uint32_t MMU_GetWriteErrorUserID(uint32_t writeerrordebug); +uint32_t MMU_GetReadErrorMasterID(uint32_t readerrordebug); +uint32_t MMU_GetReadErrorUserID(uint32_t readerrordebug); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_MMU_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_otpc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_otpc.h new file mode 100644 index 0000000000..bdcea155bd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_otpc.h @@ -0,0 +1,171 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_otpc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_OTPC_H__ +#define __N32H76X_78X_OTPC_H__ + +#include "n32h76x_78x.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** OTPC status**/ +typedef enum +{ + OTPC_UNCOMPLETE = 1, + OTPC_ERR_TIMEOUT, + OTPC_COMPLETE, +}OTPC_STS; + +/** OTPC reload data structure definition **/ +typedef struct +{ + uint32_t NRST_IWDG_OTPValue; /* Corresponding to the value of SYS_CFG_CRST_SWDG_OTP in OTP */ + uint32_t BOR_OTPValue; /* Corresponding to the value of BOR in OTP */ + uint32_t SEC_JTAG_OTPValue; /* Corresponding to the value of SEC_JTAG in OTP */ + FlagStatus L2MODE; /* Chip L2 mode*/ + FlagStatus L1MODE; /* Chip L2 mode*/ + FlagStatus L0MODE; /* Chip L2 mode*/ + FlagStatus ROOTMODE; /* Chip ROOT mode*/ + FlagStatus INITMODE; /* Chip INIT mode*/ + uint32_t TCM_SIZE_OTPValue; /* Corresponding to the value of TCM_SIZE in OTP */ +} OTPC_DBGReloadValue; + + +/** OTPC Keys **/ +#define OTPC_KEY1 ((uint32_t)0x45670123U) +#define OTPC_KEY2 ((uint32_t)0xCDEF89ABU) + +/** OTPC Operation **/ +#define OTPC_CMD_WRITE (OTPC_CTRL_PRMD) +#define OTPC_CMD_READ (~OTPC_CTRL_PRMD) +#define OTPC_CMD_LOCK (OTPC_CTRL_LOCK) + +/** OTPC us Counter Mask**/ +#define OTPC_USC_MASK (OTPC_USC_VAL) + +/** OTPC Flags **/ +#define OTPC_FLAG_BE ((uint32_t)OTPC_STS_BE ) /* Bit[6] */ +#define OTPC_FLAG_OORE ((uint32_t)OTPC_STS_OORE) /* Bit[5] */ +#define OTPC_FLAG_RDPE ((uint32_t)OTPC_STS_RDPE) /* Bit[4] */ +#define OTPC_FLAG_WRPE ((uint32_t)OTPC_STS_WRPE) /* Bit[3] */ +#define OTPC_FLAG_PGE ((uint32_t)OTPC_STS_PGE ) /* Bit[2] */ +#define OTPC_FLAG_KEYE ((uint32_t)OTPC_STS_KEYE) /* Bit[1] */ +#define OTPC_FLAG_BUSY ((uint32_t)OTPC_STS_BUSY) /* Bit[0] */ +#define OTPC_ERROR_STS (OTPC_FLAG_BE | OTPC_FLAG_OORE | OTPC_FLAG_RDPE | OTPC_FLAG_WRPE | OTPC_FLAG_PGE) +#define OTPC_ALLERROR_STS (OTPC_FLAG_BE | OTPC_FLAG_OORE | OTPC_FLAG_RDPE | OTPC_FLAG_WRPE | OTPC_FLAG_PGE | OTPC_FLAG_KEYE) + +/** OTPC Interrupt **/ +#define OTPC_INT_BE ((uint32_t)OTPC_CTRL_BEEN) /* Bit[6] */ +#define OTPC_INT_OORE ((uint32_t)OTPC_CTRL_OOREEN) /* Bit[5] */ +#define OTPC_INT_RDPE ((uint32_t)OTPC_CTRL_RDPEEN) /* Bit[4] */ +#define OTPC_INT_WRPE ((uint32_t)OTPC_CTRL_WRPEEN) /* Bit[3] */ +#define OTPC_INT_PGE ((uint32_t)OTPC_CTRL_PGEEN) /* Bit[2] */ + +/** User config register Offset Address **/ +#define OTPC_VARIOUS_REG_MASK ((uint32_t)0x0000FFFFU) +#define OTPC_SEC_JTAG_REG ((uint32_t)0x00000020U) +#define OTPC_SEC_MODE_REG ((uint32_t)0x00000028U) +#define OTPC_RDP2_REG ((uint32_t)0x00000030U) +#define OTPC_BTM_REG ((uint32_t)0x00000038U) +#define OTPC_BOR_REG ((uint32_t)0x0000003CU) +#define OTPC_IWDG_REG ((uint32_t)0x00000040U) +#define OTPC_TCM_SIZE_REG ((uint32_t)0x00000044U) +#define OTPC_JTAG_KEY_REG ((uint32_t)0x00000050U) +#define OTPC_REK_UNIT1_REG ((uint32_t)0x00000054U) +#define OTPC_REK_UNIT2_REG ((uint32_t)0x00000058U) +#define OTPC_REK_UNIT3_REG ((uint32_t)0x0000005CU) +#define OTPC_REK_UNIT4_REG ((uint32_t)0x00000060U) +#define OTPC_IDK_UNIT1_REG ((uint32_t)0x00000064U) +#define OTPC_IDK_UNIT2_REG ((uint32_t)0x00000068U) +#define OTPC_IDK_UNIT3_REG ((uint32_t)0x0000006CU) +#define OTPC_IDK_UNIT4_REG ((uint32_t)0x00000070U) +#define OTPC_UMUU_BASE_REG ((uint32_t)0x00000074U) + +/** OTPC CRLD1 register bit offset define **/ +#define OTPC_CRLD1_NRIWDG_OFFSET (REG_BIT16_OFFSET) /* NRST IWDG OTP Value */ +#define OTPC_CRLD1_BOR_OFFSET (REG_BIT12_OFFSET) /* BOR OTP Value */ + +#define OTPC_TIME_OUT ((uint32_t)0xffffffffU) /* timeout */ + +/* OTPC User unuse memory */ +#define OTPC_UNUSE_STARTADDRESS ((uint32_t)0x00000500U) /* OTPC User unuse memory start address */ +#define OTPC_UNUSE_PAGESIZE ((uint32_t)0x00000020U) /* OTPC User unuse memory page size */ + +/** OTPC Function **/ +void OTPC_Unlock(void); +void OTPC_Lock(void); +FlagStatus OTPC_GetLockStatus(void); +void OTPC_SetUsCount(uint32_t us_count); +FlagStatus OTPC_GetFlagStatus(uint32_t optc_flag); +void OTPC_ClearFlag(uint32_t optc_flag); +FlagStatus OTPC_CheckError(void); +OTPC_STS OTPC_WaitForLastOperation(void); +void OTPC_ConfigInterrupt(uint32_t otpc_int, FunctionalState cmd); +void OTPC_WriteEnable(void); +void OTPC_ReadEnable(void); +void OTPC_SetAddr(uint32_t addr); +void OTPC_SetWriteData(uint32_t data); +OTPC_STS OTPC_ProgramWord(uint32_t addr, uint32_t data); +OTPC_STS OTPC_ReadWord(uint32_t addr, uint32_t *data); +uint32_t OTPC_GetUserCfgVaildNum(uint32_t ConfigUser); +FlagStatus OTPC_CheckUserMemoryUnused(uint32_t addr); +void OTPC_GetReload(OTPC_DBGReloadValue* DBGReloadValue); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_OTPC_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_pwr.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_pwr.h new file mode 100644 index 0000000000..c661c7c7f5 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_pwr.h @@ -0,0 +1,425 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_pwr.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_PWR_H__ +#define __N32H76X_78X_PWR_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "n32h76x_78x.h" + + +/** PWR sleep status enmu definition **/ +typedef enum +{ + PWR_SLEEP_NOW = 0x0, + PWR_SLEEP_ON_EXIT = 0x1, +} PWR_SLEEPONEXIT_STATUS; + +/** PWR registers bit mask **/ +/** PWR system status enmu definition **/ +typedef enum +{ + PWR_SYSTEM_RUN = 0x0, + PWR_SYSTEM_STOP0 = 0x1, + PWR_SYSTEM_STOP2 = 0x2, +} SYSTEM_OPTC_STATUS; +/** PWR system memory enmu definition **/ +typedef enum +{ + SYSTEM_MEMORY_AXISRAM = 0x0, + SYSTEM_MEMORY_AHBSRAM1 = 0x1, + SYSTEM_MEMORY_AHBSRAM2 = 0x2, + SYSTEM_MEMORY_AHBSRAM3 = 0x3, + SYSTEM_MEMORY_AHBSRAM4 = 0x4, + SYSTEM_MEMORY_AHBSRAM5S1 = 0x5, + SYSTEM_MEMORY_AHBSRAM5S2 = 0x6, +} SYSTEM_MEMORY_TYPE; +/** PWR VDDD POR/PDR mode enmu definition **/ +typedef enum +{ + SYSTEM_RUN_MODE = 0x0, + SYSTEM_LOW_POWER_MODE = 0x1, +} SYSTEM_POWER_TYPE; + +/** register bit mask **/ +#define PWR_REG_BIT_MASK ((uint32_t)0x00000000U) + +/** POR BOR DCDC VSEL Control Register **/ +#define PVD_ContrlBaseAddress (AFEC_BASE + 0x2CU) +#define AVD_ContrlBaseAddress (AFEC_BASE + 0x00U) +#define DCDC_ContrlBaseAddress (AFEC_BASE + 0x30U) +/** POR BOR DCDC VSEL bit mask **/ +#define BOR_VSEL_BIT_MASK ((uint32_t)0x03E00000U) +#define POR_VSEL_BIT_MASK ((uint32_t)0x001F0000U) + +#define DCDC_VSEL_MASK ((uint32_t)0x00001F00U) +#define DCDC_VSEL_POR_MASK ((uint32_t)0x001F0000U) +#define DCDC_VSEL_BOR_MASK ((uint32_t)0x03E00000U) + + +/** CM7/CM4 low power config **/ +#define PWR_PDSLPS_MASK (~(PWR_CTRL_LPS | PWR_CTRL_PDS)) +#define PWR_PDS_SET (PWR_CTRL_PDS) +#define PWR_REGULATOR_NORMAL (PWR_REG_BIT_MASK) +#define PWR_REGULATOR_LOWPOWER (PWR_CTRL_LPS) + +/** PWR_ENABLE **/ +#define PWR_STBRET_ENABLE (PWR_M7CTRL2_BSRSTBRET) +#define PWR_VBATRET_ENABLE (PWR_M7CTRL2_BSRVBRET) + +/** PVD level config **/ +#define PWR_PVD_LEVEL_MASK ((uint32_t)0x001E0000U) +#define PWR_PVD_LEVEL_2V28 ((uint32_t)0x000A0000U) +#define PWR_PVD_LEVEL_2V38 ((uint32_t)0x000C0000U) +#define PWR_PVD_LEVEL_2V48 ((uint32_t)0x000E0000U) +#define PWR_PVD_LEVEL_2V58 ((uint32_t)0x00100000U) +#define PWR_PVD_LEVEL_2V68 ((uint32_t)0x00120000U) +#define PWR_PVD_LEVEL_2V78 ((uint32_t)0x00140000U) +#define PWR_PVD_LEVEL_2V88 ((uint32_t)0x00160000U) +#define PWR_PVD_LEVEL_3V28 ((uint32_t)0x00180000U) +#define PWR_PVD_LEVEL_3V38 ((uint32_t)0x001A0000U) +#define PWR_PVD_LEVEL_3V48 ((uint32_t)0x001C0000U) +#define PWR_PVD_LEVEL_3V58 ((uint32_t)0x001E0000U) +/** AVD level config **/ +#define PWR_AVD_LEVEL_MASK ((uint32_t)0x0000F000U) +#define PWR_AVD_LEVEL_2V28 ((uint32_t)0x00005000U) +#define PWR_AVD_LEVEL_2V38 ((uint32_t)0x00006000U) +#define PWR_AVD_LEVEL_2V48 ((uint32_t)0x00007000U) +#define PWR_AVD_LEVEL_2V58 ((uint32_t)0x00008000U) +#define PWR_AVD_LEVEL_2V68 ((uint32_t)0x00009000U) +#define PWR_AVD_LEVEL_2V78 ((uint32_t)0x0000A000U) +#define PWR_AVD_LEVEL_2V88 ((uint32_t)0x0000B000U) +#define PWR_AVD_LEVEL_3V28 ((uint32_t)0x0000C000U) +#define PWR_AVD_LEVEL_3V38 ((uint32_t)0x0000D000U) +#define PWR_AVD_LEVEL_3V48 ((uint32_t)0x0000E000U) +#define PWR_AVD_LEVEL_3V58 ((uint32_t)0x0000F000U) + +/**VDDD POR PDR level config **/ +#define PWR_VDDD_POR_Level_MASK ((uint32_t)0x00000003U) +#define PWR_VDDD_POR_Level_0V70 ((uint32_t)0x00000000U) +#define PWR_VDDD_POR_Level_0V75 ((uint32_t)0x00000002U) +#define PWR_VDDD_POR_Level_0V80 ((uint32_t)0x00000003U) +/**VDDD POR PDR bit offset **/ +#define PWR_VDDD_POR_LEVEL_OFFSET ((uint32_t)0x0000000CU) +#define PWR_VDDD_LPPOR_LEVEL_OFFSET ((uint32_t)0x00000016U) + +/** DCDC POR PDR level config **/ +#define PWR_DCDC_POR_Level_MASK ((uint32_t)0x0000001FU) +#define PWR_DCDC_POR_Level_0V80 ((uint32_t)0x00000005U) +#define PWR_DCDC_POR_Level_0V85 ((uint32_t)0x00000006U) +#define PWR_DCDC_POR_Level_0V90 ((uint32_t)0x00000007U) +/**DCDC POR PDR bit offset **/ +#define PWR_DCDC_POR_LEVEL_OFFSET ((uint32_t)0x00000010U) +#define PWR_DCDC_LPPOR_LEVEL_OFFSET ((uint32_t)0x00000011U) + +/** Main LDO Output Voltage config **/ +#define PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_MASK ((uint32_t)0x00000003U) +#define PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_0V80 ((uint32_t)0x00000000U) +#define PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_0V85 ((uint32_t)0x00000001U) +#define PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_0V90 ((uint32_t)0x00000002U) +/**Main LDO Output Voltage bit offset **/ +#define PWR_MLDO_VOLT_OUTPUT_LEVEL_OFFSET ((uint32_t)0x00000008U) +#define PWR_MLDO_LP_VOLT_OUTPUT_LEVEL_OFFSET ((uint32_t)0x0000000AU) + +/** DCDC Output Voltage config **/ +#define PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_MASK ((uint32_t)0x0000000FU) +#define PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_0V80 ((uint32_t)0x00000005U) +#define PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_0V85 ((uint32_t)0x00000006U) +#define PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_0V90 ((uint32_t)0x00000007U) +/**DCDC Output Voltage bit offset **/ +#define PWR_DCDC_VOLT_OUTPUT_LEVEL_OFFSET ((uint32_t)0x00000008U) +#define PWR_DCDC_LP_VOLT_OUTPUT_LEVEL_OFFSET ((uint32_t)0x00000018U) + +/** BKPLDO Output Voltage config **/ +#define PWR_BKPLDO_VOLTAGE_OUTPUT_LEVEL_MASK ((uint32_t)0x00000001U) +#define PWR_BKPLDO_VOLTAGE_OUTPUT_LEVEL_0V80 ((uint32_t)0x00000001U) +#define PWR_BKPLDO_VOLTAGE_OUTPUT_LEVEL_0V90 ((uint32_t)0x00000000U) +/**BKPLDO Output Voltage bit offset **/ +#define PWR_BKPLDO_VOLT_OUTPUT_LEVEL_OFFSET ((uint32_t)0x0000000FU) +#define PWR_BKPLDO_LP_VOLT_OUTPUT_LEVEL_OFFSET ((uint32_t)0x00000010U) + +/**MR Output Voltage Enable bit **/ +#define PWR_MR_LPVSELEN (PWR_SYSCTRL4_MR_LPVSELEN) + +/** Sleep_mode_entry **/ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) + +/** STOP_mode_entry **/ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) + +/** STANDBY_mode_entry **/ +#define PWR_STANDBYEntry_WFI ((uint8_t)0x01U) +#define PWR_STANDBYEntry_WFE ((uint8_t)0x02U) + + +/** Stop2 enable **/ +#define PWR_STOP2EN (PWR_M7CTRL2_STOP2EN) +#define PWR_PDSEN (PWR_M7CTRL1_PDS) + +/** wakeup pin enable **/ +#define WAKEUP_PIN0EN (PWR_M7CTRLSTS_WKUP0EN) +#define WAKEUP_PIN1EN (PWR_M7CTRLSTS_WKUP1EN) +#define WAKEUP_PIN2EN (PWR_M7CTRLSTS_WKUP2EN) +#define WAKEUP_PIN3EN (PWR_M7CTRLSTS_WKUP3EN) +#define WAKEUP_PIN4EN (PWR_M7CTRLSTS_WKUP4EN) +#define WAKEUP_PIN5EN (PWR_M7CTRLSTS_WKUP5EN) + +#define WAKEUP_RTCEN (PWR_M7CTRL2_RTC_ALMWUPEN) +#define WAKEUP_NRSTEN (PWR_M7CTRL2_NRST_WUPEN) + +/** wakeup pin polarity config **/ +#define WAKEUP_PIN0POL (PWR_M7CTRLSTS_WKUP0POL) +#define WAKEUP_PIN1POL (PWR_M7CTRLSTS_WKUP1POL) +#define WAKEUP_PIN2POL (PWR_M7CTRLSTS_WKUP2POL) +#define WAKEUP_PIN3POL (PWR_M7CTRLSTS_WKUP3POL) +#define WAKEUP_PIN4POL (PWR_M7CTRLSTS_WKUP4POL) +#define WAKEUP_PIN5POL (PWR_M7CTRLSTS_WKUP5POL) + +/** PWR_Flag **/ +#define PWR_FLAG_WKUP0 (PWR_M7CTRLSTS_WKUP0F) +#define PWR_FLAG_WKUP1 (PWR_M7CTRLSTS_WKUP1F) +#define PWR_FLAG_WKUP2 (PWR_M7CTRLSTS_WKUP2F) +#define PWR_FLAG_WKUP3 (PWR_M7CTRLSTS_WKUP3F) +#define PWR_FLAG_WKUP4 (PWR_M7CTRLSTS_WKUP4F) +#define PWR_FLAG_WKUP5 (PWR_M7CTRLSTS_WKUP5F) +#define PWR_FLAG_WKUPP (PWR_M7CTRLSTS_WKUP6F) +#define PWR_FLAG_STANDBY (PWR_M7CTRLSTS_SBF) +#define PWR_FLAG_VBAT (PWR_M7CTRLSTS_VBATF) + +/** PWR_Flag clear **/ +#define PWR_CLR_WKUPx (PWR_M7CTRL1_CWKUPF) +#define PWR_CLR_STANDBY (PWR_M7CTRL1_CSBF) +#define PWR_CLR_VBAT (PWR_M7CTRL1_CVBATF) + + +/** PWR_system control 1 **/ +#define PWR_PVDEN (PWR_SYSCTRL1_PVDEN) +#define PWR_AVDEN (PWR_SYSCTRL1_AVDEN) +#define PWR_DBKPEN (PWR_SYSCTRL1_DBKP) +#define PWR_BKPLDOEN (PWR_SYSCTRL1_BKPLDOEN) + +/** NRST_Digital Filtering **/ +#define PWR_NRST_DGF_CNT_MASK (PWR_SYSCTRL1_NRST_DGFCNT) +#define PWR_NRST_DGF_BP (PWR_SYSCTRL1_NRST_DGFBP) + +#define PWR_NRST_DGF_CNT_BIT_OFFSET (16U) +/** PWR_SystemFlag **/ +#define PWR_SYSFLAG_PVDO (PWR_SYSCTRLSTS_PVDO) +#define PWR_SYSFLAG_AVDO (PWR_SYSCTRLSTS_AVDO) +#define PWR_SYSFLAG_OTPRDY (PWR_SYSCTRLSTS_OTP_PWRRDY) +#define PWR_FLAG_DCDCBP (PWR_SYSCTRLSTS_DCDC_BPF) + +/** PWR_system control 2 **/ +#define PWR_MROFF_IN_STANDBY (PWR_SYSCTRL2_MR_STBOFFEN) + +/** Module PWR Enable **/ +#define GRAPHIC_GPU_PWRCTRL (PWR_IPMEMCTRL_GPU_PWREN) +#define GRAPHIC_LCDC_PWRCTRL (PWR_IPMEMCTRL_LCDC_PWREN) +#define GRAPHIC_JPEG_PWRCTRL (PWR_IPMEMCTRL_JPEG_PWREN) +#define GRAPHIC_DSI_PWRCTRL (PWR_IPMEMCTRL_DSI_PWREN) +#define GRAPHIC_DVP_PWRCTRL (PWR_IPMEMCTRL_DVP_PWREN) +#define HSC2_ETH2_PWRCTRL (PWR_IPMEMCTRL_ETH2_PWREN) +#define HSC2_USB2_PWRCTRL (PWR_IPMEMCTRL_USB2_PWREN) +#define HSC2_SDMMC2_PWRCTRL (PWR_IPMEMCTRL_SDMMC2_PWREN) +#define HSC1_ETH1_PWRCTRL (PWR_IPMEMCTRL_ETH1_PWREN) +#define HSC1_USB1_PWRCTRL (PWR_IPMEMCTRL_USB1_PWREN) +#define HSC1_SDMMC1_PWRCTRL (PWR_IPMEMCTRL_SDMMC1_PWREN) +#define FMAC_PWRCTRL (PWR_IPMEMCTRL_FMAC_PWREN) +#define ESC_PWRCTRL (PWR_IPMEMCTRL_ESC_PWREN) + +/** PWR Ready flag **/ +#define FMAC_PWRRDY_FLAG (PWR_IPMEMCTRLSTS_FMAC_PWRRDY) +#define ESC_PWRRDY_FLAG (PWR_IPMEMCTRLSTS_ESC_PWRRDY) + +/** MDMA PWR control **/ +#define MDMA_POWER_ENABLE (PWR_MDMACTRL_MDMA_PWREN) +#define MDMA_FUNCTION_ENABLE (PWR_MDMACTRL_MDMA_FUCEN) +#define MDMA_ISOLATION_ENABLE (PWR_MDMACTRL_MDMA_ISNEN) +#define MDMA_POWER_RDY (PWR_MDMACTRL_MDMA_PRDY) +#define MDMA_PSWACK1 (PWR_MDMACTRL_MDMA_PSWACK1) + +/** ESC PWR control **/ +#define ESC_POWER_ENABLE (PWR_ESCCTRL_ESC_PWREN) +#define ESC_FUNCTION_ENABLE (PWR_ESCCTRL_ESC_FUCEN) +#define ESC_ISOLATION_ENABLE (PWR_ESCCTRL_ESC_ISNEN) +#define ESC_POWER_RDY (PWR_ESCCTRL_ESC_PRDY) +#define ESC_PSWACK1 (PWR_ESCCTRL_ESC_PSWACK1) + +/** SHRTIM PWR control **/ +#define SHRTIM1_POWER_ENABLE (PWR_SHRTIMCTRL_SHR1_PWREN) +#define SHRTIM1_FUNCTION_ENABLE (PWR_SHRTIMCTRL_SHR1_FUCEN) +#define SHRTIM1_ISOLATION_ENABLE (PWR_SHRTIMCTRL_SHR1_ISNEN) +#define SHRTIM1_POWER_RDY (PWR_SHRTIMCTRL_SHR1_PRDY) +#define SHRTIM1_PSWACK1 (PWR_SHRTIMCTRL_SHR1_PSWACK1) + +#define SHRTIM2_POWER_ENABLE (PWR_SHRTIMCTRL_SHR2_PWREN) +#define SHRTIM2_FUNCTION_ENABLE (PWR_SHRTIMCTRL_SHR2_FUCEN) +#define SHRTIM2_ISOLATION_ENABLE (PWR_SHRTIMCTRL_SHR2_ISNEN) +#define SHRTIM2_POWER_RDY (PWR_SHRTIMCTRL_SHR2_PRDY) +#define SHRTIM2_PSWACK1 (PWR_SHRTIMCTRL_SHR2_PSWACK1) + +#define SHRTIMA_POWER_ENABLE (PWR_SHRTIMCTRL_SHRA_PWREN) +#define SHRTIMA_FUNCTION_ENABLE (PWR_SHRTIMCTRL_SHRA_FUCEN) +#define SHRTIMA_ISOLATION_ENABLE (PWR_SHRTIMCTRL_SHRA_ISNEN) +#define SHRTIMA_POWER_RDY (PWR_SHRTIMCTRL_SHRA_PRDY) +#define SHRTIMA_PSWACK1 (PWR_SHRTIMCTRL_SHRA_PSWACK1) + +/** OPTC_POWER control **/ +#define OPTC_POWER_ENTER_MODE_MASK (0x000000003U) +#define OPTC_POWER_ENTER_RUN_MODE (0x000000000U) +#define OPTC_POWER_ENTER_DEEPSTANDBY_MODE (0x000000001U) +#define OPTC_POWER_ENTER_STANDBY_MODE (0x000000002U) + + + +/** SYSTEM MEMORY Low Power mode in Stop2 mode **/ +#define SYSTEM_MEMORY_STATUS_MASK (0x000000003U) +#define SYSTEM_MEMORY_STATUS_PD (0x000000000U) +#define SYSTEM_MEMORY_STATUS_RETENTION_1 (0x000000001U) +#define SYSTEM_MEMORY_STATUS_RETENTION_2 (0x000000002U) + +#define SYSTEM_MEMORY_AXISRAM_BITOFFSET (0x00000000DU) + +/** ALL SYSTEM MEMORY Low Power mode in Stop0 mode **/ +#define ALL_SYSTEM_MEMORY_STATUS_MASK (PWR_SYSMEMLPCTRL_MEM_PGSTP0EN | PWR_SYSMEMLPCTRL_MEM_RETSTP0EN) +#define ALL_SYSTEM_MEMORY_STATUS_CHIP_DISABLE (0x000000000U) +#define ALL_SYSTEM_MEMORY_STATUS_PRECHARGE (PWR_SYSMEMLPCTRL_MEM_RETSTP0EN) +#define ALL_SYSTEM_MEMORY_STATUS_RETENTION_1 (PWR_SYSMEMLPCTRL_MEM_PGSTP0EN | PWR_SYSMEMLPCTRL_MEM_RETSTP0EN) + + + +typedef enum{ + GRAPHIC_Domain = 0, + HSC1_Domain = 1, + HSC2_Domain = 2 +}DOMAIN_Type; + +typedef enum{ + Power_SHRTIM1 = 0, + Power_SHRTIM2 = 1, +}SHRTIM_PowerType; + +/** PWR wakeup PIN polarity enmu definition **/ +typedef enum +{ + POL_HIGH = 0x0, + POL_LOW = 0x1, +} WAKEUP_PIN_POL; + + + +/** PWR_Exported_Functions **/ + +void PWR_DeInit_Sys(void); +void PWR_DeInit_CM7(void); +void PWR_DeInit_CM4(void); + +void PWR_BackupAccessEnable(FunctionalState Cmd); +void PWR_AvdEnable(FunctionalState Cmd); +void PWR_PvdEnable(FunctionalState Cmd); +void PWR_BorEnable(FunctionalState Cmd); +void PWR_PVDLevelConfig(uint32_t level); +void PWR_AVDLevelConfig(uint32_t level); +void PWR_EnableMRInStandby(FunctionalState Cmd); +void PWR_EnableBKPLDO(FunctionalState Cmd); + +void PWR_ConfigDigitalFilterOnNRST(uint32_t cycle_cnt, FunctionalState Cmd); + +void PWR_EnableLPMRVoltageOutput(FunctionalState Cmd); +void PWR_VDDDPORLevelConfig(SYSTEM_POWER_TYPE mode, uint32_t level); +void PWR_DCDCPORLevelConfig(SYSTEM_POWER_TYPE mode, uint32_t level); + +void PWR_MLDOOutputVoltageConfig(SYSTEM_POWER_TYPE mode, uint32_t level); +void PWR_DCDCOutputVoltageConfig(SYSTEM_POWER_TYPE mode, uint32_t level); +void PWR_BKPLDOOutputVoltageConfig(SYSTEM_POWER_TYPE mode, uint32_t level); + +void PWR_MDMA_DomainEnable(FunctionalState Cmd); +void PWR_SHRTIM_DomainEnable(SHRTIM_PowerType shrtimx, FunctionalState Cmd); +void PWR_MoudlePowerEnable(uint32_t module, FunctionalState Cmd); + +void PWR_EnableBKPSRAMRetainInStandbyMode(FunctionalState Cmd); +void PWR_EnableBKPSRAMRetainInVbatMode(FunctionalState Cmd); +void PWR_WakeUpPinEnable(uint32_t pin, FunctionalState Cmd); +void PWR_WakeUpPinPolarity(uint32_t pin, WAKEUP_PIN_POL polarity); +void PWR_WakeUpRTCEnable(FunctionalState Cmd); +void PWR_WakeUpNRSTEnable(FunctionalState Cmd); + +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +FlagStatus PWR_GetSystemFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry); +void PWR_EnterSTOP0Mode(uint8_t PWR_STOPEntry); +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); + +void PWR_EnableOPTC_LPMode(SYSTEM_OPTC_STATUS ChipStatus, uint32_t OPTC_Mode, FunctionalState Cmd); +void PWR_EnableTCMPiece(uint32_t PieceIndex, FunctionalState Cmd); +void PWR_TCMModeSelInSTOP2(uint32_t PieceIndex, uint32_t Mode); + +void PWR_SystemMemoryModeSelInSTOP2(SYSTEM_MEMORY_TYPE SysMemoryType, uint32_t Mode); +void PWR_SystemMemoryModeSelInSTOP0(uint32_t Mode); +void PWR_EnableSystemMemory(SYSTEM_MEMORY_TYPE SysMemoryType, FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif //__N32H76X_78X_PWR_H__ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rcc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rcc.h new file mode 100644 index 0000000000..fc0e93a579 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rcc.h @@ -0,0 +1,2542 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_rcc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_RCC_H +#define __N32H76X_78X_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes */ +#include "n32h76x_78x.h" + +/** RCC_Exported_Types **/ +typedef struct +{ + uint32_t PLL1AClkFreq; /* returns PLL1A clock frequency expressed in Hz */ + uint32_t PLL1BClkFreq; /* returns PLL1B clock frequency expressed in Hz */ + uint32_t PLL1CClkFreq; /* returns PLL1C clock frequency expressed in Hz */ + uint32_t PLL2AClkFreq; /* returns PLL2A clock frequency expressed in Hz */ + uint32_t PLL2BClkFreq; /* returns PLL2B clock frequency expressed in Hz */ + uint32_t PLL2CClkFreq; /* returns PLL2C clock frequency expressed in Hz */ + uint32_t PLL3AClkFreq; /* returns PLL3A clock frequency expressed in Hz */ + uint32_t PLL3BClkFreq; /* returns PLL3B clock frequency expressed in Hz */ + uint32_t PLL3CClkFreq; /* returns PLL3C clock frequency expressed in Hz */ + uint32_t SysClkFreq; /* returns SysClk clock frequency expressed in Hz */ + uint32_t SysBusDivClkFreq; /* returns SysBusDivClk clock frequency expressed in Hz */ + uint32_t M4ClkFreq; /* returns M4 clock frequency expressed in Hz */ + uint32_t M7ClkFreq; /* returns M7 clock frequency expressed in Hz */ + uint32_t AXIClkFreq; /* returns AXI clock frequency expressed in Hz */ + uint32_t AHB1ClkFreq; /* returns AHB1 clock frequency expressed in Hz */ + uint32_t AHB2ClkFreq; /* returns AHB2 clock frequency expressed in Hz */ + uint32_t AHB5ClkFreq; /* returns AHB5 clock frequency expressed in Hz */ + uint32_t AHB6ClkFreq; /* returns AHB6 clock frequency expressed in Hz */ + uint32_t AHB9ClkFreq; /* returns AHB9 clock frequency expressed in Hz */ + uint32_t APB1ClkFreq; /* returns APB1 clock frequency expressed in Hz */ + uint32_t APB2ClkFreq; /* returns APB2 clock frequency expressed in Hz */ + uint32_t APB5ClkFreq; /* returns APB5 clock frequency expressed in Hz */ + uint32_t APB6ClkFreq; /* returns APB6 clock frequency expressed in Hz */ + uint32_t PeriphClkFreq; /* returns Periph clock frequency expressed in Hz */ + +}RCC_ClocksTypeDef; + +#define VCO_MIN 300000000 //300M +#define VCO_MAX 1250000000//1.25G +#define REF_MIN 1000000 //1M +#define REF_MAX 64000000 //64M +#define NR_MIN 1 +#define NR_MAX 64 +#define NF_MIN 2 +#define NF_MAX 4095 + +/** RCC R_BIT_MASK **/ +#define RCC_REG_BIT_MASK ((uint32_t)0x00000000) + +/** RCC_Flag **/ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define RCC_FLAG_OFFSET ((uint8_t)0x05) +//SRCCTRL1=1 +#define RCC_FLAG_HSIRD ((uint8_t)0x21) +#define RCC_FLAG_HSERD ((uint8_t)0x23) +#define RCC_FLAG_MSIRD ((uint8_t)0x27) +#define RCC_FLAG_AFEHSIRD ((uint8_t)0x3E) +#define RCC_FLAG_AFEMSIRD ((uint8_t)0x3F) +//SRCCTRL2=2 +#define RCC_FLAG_MSICALE ((uint8_t)0x5C) +#define RCC_FLAG_HSICALE ((uint8_t)0x5D) +#define RCC_FLAG_BOR ((uint8_t)0x5E) +//BDCTRL=3 +#define RCC_FLAG_LSIRD ((uint8_t)0x61) +#define RCC_FLAG_LSERD ((uint8_t)0x65) +#define RCC_FLAG_LSECSS ((uint8_t)0x69) +#define RCC_FLAG_LSISECRD ((uint8_t)0x73) +#define RCC_FLAG_RTCHSFSW ((uint8_t)0x74) +#define RCC_FLAG_RTCLSFSW ((uint8_t)0x75) +#define RCC_FLAG_LSIPF ((uint8_t)0x79) +#define RCC_FLAG_AFELSIRD ((uint8_t)0x7E) +#define RCC_FLAG_AFELSERD ((uint8_t)0x7F) +//CTRLSTS=4 +#define RCC_FLAG_PINRST ((uint8_t)0x80) +#define RCC_FLAG_PORRST ((uint8_t)0x81) +#define RCC_FLAG_CM7SFTRST ((uint8_t)0x82) +#define RCC_FLAG_CM4SFTRST ((uint8_t)0x83) +#define RCC_FLAG_IWDG2RST ((uint8_t)0x84) +#define RCC_FLAG_IWDG1RST ((uint8_t)0x85) +#define RCC_FLAG_WWDG2RST ((uint8_t)0x86) +#define RCC_FLAG_WWDG1RST ((uint8_t)0x87) +#define RCC_FLAG_MMURST ((uint8_t)0x89) +#define RCC_FLAG_BORRST ((uint8_t)0x8B) +#define RCC_FLAG_BKPEMCRST ((uint8_t)0x8C) +#define RCC_FLAG_RETEMCRST ((uint8_t)0x8D) +#define RCC_FLAG_C2LPRST ((uint8_t)0x8E) +#define RCC_FLAG_C1LPRST ((uint8_t)0x8F) +//PLLFD=5 +#define RCC_FLAG_SHRPLLG ((uint8_t)0xAB) +#define RCC_FLAG_PLL3G ((uint8_t)0xAA) +#define RCC_FLAG_PLL2G ((uint8_t)0xA9) +#define RCC_FLAG_PLL1G ((uint8_t)0xA8) +#define RCC_FLAG_SHRPLLF ((uint8_t)0xA7) +#define RCC_FLAG_PLL3F ((uint8_t)0xA6) +#define RCC_FLAG_PLL2F ((uint8_t)0xA5) +#define RCC_FLAG_PLL1F ((uint8_t)0xA4) + + +#define RCC_REMOVE_RESET_FLAG (RCC_CTRLSTS_RMRSTF) +#define RCC_RSTEN_M4REL (RCC_M4RSTREL_EN) + +/** AHB1 peripherals reset **/ +#define RCC_AHB1_PERIPHRST_SDMMC2 (RCC_AHB1RST1_SDMMC2RST) +#define RCC_AHB1_PERIPHRST_SDHOST2 (RCC_AHB1RST1_SDHOST2RST ) +#define RCC_AHB1_PERIPHRST_USB2WRAP (RCC_AHB1RST1_USB2WRAPRST ) +#define RCC_AHB1_PERIPHRST_USB2POR (RCC_AHB1RST1_USB2PORRST ) +#define RCC_AHB1_PERIPHRST_USB2 (RCC_AHB1RST1_USB2RST ) +#define RCC_AHB1_PERIPHRST_DMAMUX1 (RCC_AHB1RST1_DMAMUX1RST ) +#define RCC_AHB1_PERIPHRST_ADC1 (RCC_AHB1RST1_ADC1RST ) + +#define RCC_AHB1_PERIPHRST_ETH2 (RCC_AHB1RST2_ETH2RST) + +#define RCC_AHB1_PERIPHRST_ECCMAC (RCC_AHB1RST3_ECCMACRST) +#define RCC_AHB1_PERIPHRST_DMA1 (RCC_AHB1RST3_DMA1RST ) +#define RCC_AHB1_PERIPHRST_DMA2 (RCC_AHB1RST3_DMA2RST ) +#define RCC_AHB1_PERIPHRST_DMA3 (RCC_AHB1RST3_DMA3RST ) + +#define RCC_AHB1_PERIPHRST_ADC2 (RCC_AHB1RST4_ADC2RST) +#define RCC_AHB1_PERIPHRST_ADC3 (RCC_AHB1RST4_ADC3RST) +/** APB1 peripherals reset **/ +#define RCC_APB1_PERIPHRST_BTIM1 (RCC_APB1RST1_BTIM1RST ) +#define RCC_APB1_PERIPHRST_BTIM2 (RCC_APB1RST1_BTIM2RST ) +#define RCC_APB1_PERIPHRST_BTIM3 (RCC_APB1RST1_BTIM3RST ) +#define RCC_APB1_PERIPHRST_BTIM4 (RCC_APB1RST1_BTIM4RST ) +#define RCC_APB1_PERIPHRST_GTIMB1 (RCC_APB1RST1_GTIMB1RST) +#define RCC_APB1_PERIPHRST_GTIMB2 (RCC_APB1RST1_GTIMB2RST) +#define RCC_APB1_PERIPHRST_GTIMB3 (RCC_APB1RST1_GTIMB3RST) +#define RCC_APB1_PERIPHRST_GTIMA4 (RCC_APB1RST1_GTIMA4RST) + +#define RCC_APB1_PERIPHRST_GTIMA5 (RCC_APB1RST2_GTIMA5RST) +#define RCC_APB1_PERIPHRST_GTIMA6 (RCC_APB1RST2_GTIMA6RST) +#define RCC_APB1_PERIPHRST_GTIMA7 (RCC_APB1RST2_GTIMA7RST) +#define RCC_APB1_PERIPHRST_SPI3 (RCC_APB1RST2_SPI3RST ) +#define RCC_APB1_PERIPHRST_DAC12 (RCC_APB1RST2_DAC12RST ) +#define RCC_APB1_PERIPHRST_WWDG2 (RCC_APB1RST2_WWDG2RST ) + +#define RCC_APB1_PERIPHRST_USART1 (RCC_APB1RST3_USART1RST) +#define RCC_APB1_PERIPHRST_USART2 (RCC_APB1RST3_USART2RST) +#define RCC_APB1_PERIPHRST_USART3 (RCC_APB1RST3_USART3RST) +#define RCC_APB1_PERIPHRST_USART4 (RCC_APB1RST3_USART4RST) +#define RCC_APB1_PERIPHRST_UART9 (RCC_APB1RST3_UART9RST ) +#define RCC_APB1_PERIPHRST_UART10 (RCC_APB1RST3_UART10RST ) +#define RCC_APB1_PERIPHRST_UART11 (RCC_APB1RST3_UART11RST ) +#define RCC_APB1_PERIPHRST_UART12 (RCC_APB1RST3_UART12RST ) + +#define RCC_APB1_PERIPHRST_I2S3 (RCC_APB1RST4_I2S3RST ) +#define RCC_APB1_PERIPHRST_I2S4 (RCC_APB1RST4_I2S4RST ) +#define RCC_APB1_PERIPHRST_I2C1 (RCC_APB1RST4_I2C1RST ) +#define RCC_APB1_PERIPHRST_I2C2 (RCC_APB1RST4_I2C2RST ) +#define RCC_APB1_PERIPHRST_I2C3 (RCC_APB1RST4_I2C3RST ) + +#define RCC_APB1_PERIPHRST_FDCAN1 (RCC_APB1RST5_FDCAN1RST) +#define RCC_APB1_PERIPHRST_FDCAN2 (RCC_APB1RST5_FDCAN2RST) +#define RCC_APB1_PERIPHRST_FDCAN5 (RCC_APB1RST5_FDCAN5RST) +#define RCC_APB1_PERIPHRST_FDCAN6 (RCC_APB1RST5_FDCAN6RST) +#define RCC_APB1_PERIPHRST_CAHI (RCC_APB1RST5_CAHIRST ) +#define RCC_APB1_PERIPHRST_CAHD (RCC_APB1RST5_CAHDRST ) +/** AHB2 peripherals reset **/ +#define RCC_AHB2_PERIPHRST_DAC56 (RCC_AHB2RST1_DAC56RST ) +#define RCC_AHB2_PERIPHRST_DAC34 (RCC_AHB2RST1_DAC34RST ) +#define RCC_AHB2_PERIPHRST_USB1WRAP (RCC_AHB2RST1_USB1WRAPRST) +#define RCC_AHB2_PERIPHRST_USB1POR (RCC_AHB2RST1_USB1PORRST ) +#define RCC_AHB2_PERIPHRST_USB1 (RCC_AHB2RST1_USB1RST ) +#define RCC_AHB2_PERIPHRST_ETH1 (RCC_AHB2RST1_ETH1RST ) +#define RCC_AHB2_PERIPHRST_ECCM2 (RCC_AHB2RST1_ECCM2RST ) +#define RCC_AHB2_PERIPHRST_CORDIC (RCC_AHB2RST1_CORDICRST ) +#define RCC_AHB2_PERIPHRST_SDPU (RCC_AHB2RST1_SDPURST ) +#define RCC_AHB2_PERIPHRST_FMAC (RCC_AHB2RST1_FMACRST ) +/** APB2 peripherals reset **/ +#define RCC_APB2_PERIPHRST_ATIM1 (RCC_APB2RST1_ATIM1RST ) +#define RCC_APB2_PERIPHRST_ATIM2 (RCC_APB2RST1_ATIM2RST ) +#define RCC_APB2_PERIPHRST_GTIMA1 (RCC_APB2RST1_GTIMA1RST ) +#define RCC_APB2_PERIPHRST_GTIMA2 (RCC_APB2RST1_GTIMA2RST ) +#define RCC_APB2_PERIPHRST_GTIMA3 (RCC_APB2RST1_GTIMA3RST ) +#define RCC_APB2_PERIPHRST_SHRTIM1 (RCC_APB2RST1_SHRTIM1RST) +#define RCC_APB2_PERIPHRST_SHRTIM2 (RCC_APB2RST1_SHRTIM2RST) + +#define RCC_APB2_PERIPHRST_I2S1 (RCC_APB2RST2_I2S1RST ) +#define RCC_APB2_PERIPHRST_I2S2 (RCC_APB2RST2_I2S2RST ) +#define RCC_APB2_PERIPHRST_SPI1 (RCC_APB2RST2_SPI1RST ) +#define RCC_APB2_PERIPHRST_SPI2 (RCC_APB2RST2_SPI2RST ) +#define RCC_APB2_PERIPHRST_DSMU (RCC_APB2RST2_DSMURST ) +#define RCC_APB2_PERIPHRST_I2C4 (RCC_APB2RST2_I2C4RST ) +#define RCC_APB2_PERIPHRST_I2C5 (RCC_APB2RST2_I2C5RST ) +#define RCC_APB2_PERIPHRST_I2C6 (RCC_APB2RST2_I2C6RST ) + +#define RCC_APB2_PERIPHRST_USART5 (RCC_APB2RST3_USART5RST ) +#define RCC_APB2_PERIPHRST_USART6 (RCC_APB2RST3_USART6RST ) +#define RCC_APB2_PERIPHRST_USART7 (RCC_APB2RST3_USART7RST ) +#define RCC_APB2_PERIPHRST_USART8 (RCC_APB2RST3_USART8RST ) +#define RCC_APB2_PERIPHRST_UART13 (RCC_APB2RST3_UART13RST ) +#define RCC_APB2_PERIPHRST_UART14 (RCC_APB2RST3_UART14RST ) +#define RCC_APB2_PERIPHRST_UART15 (RCC_APB2RST3_UART15RST ) + +#define RCC_APB2_PERIPHRST_FDCAN3 (RCC_APB2RST4_FDCAN3RST ) +#define RCC_APB2_PERIPHRST_FDCAN4 (RCC_APB2RST4_FDCAN4RST ) +#define RCC_APB2_PERIPHRST_FDCAN7 (RCC_APB2RST4_FDCAN7RST ) +#define RCC_APB2_PERIPHRST_FDCAN8 (RCC_APB2RST4_FDCAN8RST ) +/** AHB5 peripherals reset **/ +#define RCC_AHB5_PERIPHRST_GPIOA (RCC_AHB5RST1_GPIOARST) +#define RCC_AHB5_PERIPHRST_GPIOB (RCC_AHB5RST1_GPIOBRST) +#define RCC_AHB5_PERIPHRST_GPIOC (RCC_AHB5RST1_GPIOCRST) +#define RCC_AHB5_PERIPHRST_GPIOD (RCC_AHB5RST1_GPIODRST) +#define RCC_AHB5_PERIPHRST_GPIOE (RCC_AHB5RST1_GPIOERST) +#define RCC_AHB5_PERIPHRST_GPIOF (RCC_AHB5RST1_GPIOFRST) +#define RCC_AHB5_PERIPHRST_GPIOG (RCC_AHB5RST1_GPIOGRST) +#define RCC_AHB5_PERIPHRST_GPIOH (RCC_AHB5RST1_GPIOHRST) + +#define RCC_AHB5_PERIPHRST_GPIOI (RCC_AHB5RST2_GPIOIRST) +#define RCC_AHB5_PERIPHRST_GPIOJ (RCC_AHB5RST2_GPIOJRST) +#define RCC_AHB5_PERIPHRST_GPIOK (RCC_AHB5RST2_GPIOKRST) +#define RCC_AHB5_PERIPHRST_ECCM3 (RCC_AHB5RST2_ECCM3RST) +#define RCC_AHB5_PERIPHRST_PWR (RCC_AHB5RST2_PWRRST ) +#define RCC_AHB5_PERIPHRST_CRC (RCC_AHB5RST2_CRCRST ) +#define RCC_AHB5_PERIPHRST_SEMA4 (RCC_AHB5RST2_SEMA4RST) +#define RCC_AHB5_PERIPHRST_AFIO (RCC_AHB5RST2_AFIORST ) +/** APB5 peripherals reset **/ +#define RCC_APB5_PERIPHRST_ATIM3 (RCC_APB5RST1_ATIM3RST) +#define RCC_APB5_PERIPHRST_ATIM4 (RCC_APB5RST1_ATIM4RST) +#define RCC_APB5_PERIPHRST_SPI4 (RCC_APB5RST1_SPI4RST ) +#define RCC_APB5_PERIPHRST_SPI5 (RCC_APB5RST1_SPI5RST ) +#define RCC_APB5_PERIPHRST_SPI6 (RCC_APB5RST1_SPI6RST ) +#define RCC_APB5_PERIPHRST_SPI7 (RCC_APB5RST1_SPI7RST ) + +#define RCC_APB5_PERIPHRST_I2C7 (RCC_APB5RST2_I2C7RST ) +#define RCC_APB5_PERIPHRST_I2C8 (RCC_APB5RST2_I2C8RST ) +#define RCC_APB5_PERIPHRST_I2C9 (RCC_APB5RST2_I2C9RST ) +#define RCC_APB5_PERIPHRST_I2C10 (RCC_APB5RST2_I2C10RST) +/** AXI/AHB6/APB6 peripherals reset **/ +#define RCC_AXI_PERIPHRST_JPEGD (RCC_AXIRST1_JPEGDRST ) +#define RCC_AXI_PERIPHRST_JPEGE (RCC_AXIRST1_JPEGERST ) +#define RCC_AXI_PERIPHRST_DMAMUX2 (RCC_AXIRST1_DMAMUX2RST ) +#define RCC_AXI_PERIPHRST_MDMA (RCC_AXIRST1_MDMARST ) +#define RCC_AXI_PERIPHRST_SDMMC1 (RCC_AXIRST1_SDMMC1RST) +#define RCC_AXI_PERIPHRST_SDHOST1 (RCC_AXIRST1_SDHOST1RST ) +#define RCC_AXI_PERIPHRST_ECCM1 (RCC_AXIRST1_ECCM1RST ) +#define RCC_AXI_PERIPHRST_OTPC (RCC_AXIRST1_OTPCRST ) + +#define RCC_AXI_PERIPHRST_DSICFG (RCC_AXIRST2_DSICFGRST ) +#define RCC_AXI_PERIPHRST_DSI (RCC_AXIRST2_DSIRST ) +#define RCC_AXI_PERIPHRST_LCDC (RCC_AXIRST2_LCDCRST ) +#define RCC_AXI_PERIPHRST_DVP1 (RCC_AXIRST2_DVP1RST ) +#define RCC_AXI_PERIPHRST_DVP2 (RCC_AXIRST2_DVP2RST ) +#define RCC_AXI_PERIPHRST_WWDG1 (RCC_AXIRST2_WWDG1RST ) + +#define RCC_AXI_PERIPHRST_GPU (RCC_AXIRST3_GPURST ) + +#define RCC_AXI_PERIPHRST_XSPI1 (RCC_AXIRST4_XSPI1RST ) +#define RCC_AXI_PERIPHRST_XSPI2 (RCC_AXIRST4_XSPI2RST ) +#define RCC_AXI_PERIPHRST_FEMCCFG (RCC_AXIRST4_FEMCCFGRST ) +#define RCC_AXI_PERIPHRST_FEMC (RCC_AXIRST4_FEMCRST ) +#define RCC_AXI_PERIPHRST_SDRAM (RCC_AXIRST4_SDRAMRST ) +/** AHB9 peripherals reset **/ +#define RCC_AHB9_PERIPHRST_ESC (RCC_AHB9RST1_ESCRST) +/** Retention domain peripherals reset **/ +#define RCC_RD_PERIPHRST_LPTIM1 (RCC_RDRST1_LPTIM1RST ) +#define RCC_RD_PERIPHRST_LPTIM2 (RCC_RDRST1_LPTIM2RST ) +#define RCC_RD_PERIPHRST_LPTIM3 (RCC_RDRST1_LPTIM3RST ) +#define RCC_RD_PERIPHRST_LPTIM4 (RCC_RDRST1_LPTIM4RST ) +#define RCC_RD_PERIPHRST_LPTIM5 (RCC_RDRST1_LPTIM5RST ) +#define RCC_RD_PERIPHRST_LPUART1 (RCC_RDRST1_LPUART1RST) +#define RCC_RD_PERIPHRST_LPUART2 (RCC_RDRST1_LPUART2RST) + +#define RCC_RD_PERIPHRST_COMP (RCC_RDRST2_COMPRST) + + +/** AHB1 peripherals enable **/ +#define RCC_AHB1_PERIPHEN_M7_SDMMC2 (RCC_AHB1EN1_M7SDMMC2EN ) +#define RCC_AHB1_PERIPHEN_M4_SDMMC2 (RCC_AHB1EN1_M4SDMMC2EN ) +#define RCC_AHB1_PERIPHEN_M7_SDMMC2LP (RCC_AHB1EN1_M7SDMMC2LPEN ) +#define RCC_AHB1_PERIPHEN_M4_SDMMC2LP (RCC_AHB1EN1_M4SDMMC2LPEN ) +#define RCC_AHB1_PERIPHEN_M7_USB2 (RCC_AHB1EN1_M7USB2EN ) +#define RCC_AHB1_PERIPHEN_M4_USB2 (RCC_AHB1EN1_M4USB2EN ) +#define RCC_AHB1_PERIPHEN_M7_USB2LP (RCC_AHB1EN1_M7USB2LPEN ) +#define RCC_AHB1_PERIPHEN_M4_USB2LP (RCC_AHB1EN1_M4USB2LPEN ) +#define RCC_AHB1_PERIPHEN_M7_DMAMUX1 (RCC_AHB1EN1_M7DMAMUX1EN ) +#define RCC_AHB1_PERIPHEN_M4_DMAMUX1 (RCC_AHB1EN1_M4DMAMUX1EN ) +#define RCC_AHB1_PERIPHEN_M7_DMAMUX1LP (RCC_AHB1EN1_M7DMAMUX1LPEN ) +#define RCC_AHB1_PERIPHEN_M4_DMAMUX1LP (RCC_AHB1EN1_M4DMAMUX1LPEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC1PLL (RCC_AHB1EN1_M7ADC1PLLEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC1PLL (RCC_AHB1EN1_M4ADC1PLLEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC1PLLLP (RCC_AHB1EN1_M7ADC1PLLLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC1PLLLP (RCC_AHB1EN1_M4ADC1PLLLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC1SYS (RCC_AHB1EN1_M7ADC1SYSEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC1SYS (RCC_AHB1EN1_M4ADC1SYSEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC1SYSLP (RCC_AHB1EN1_M7ADC1SYSLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC1SYSLP (RCC_AHB1EN1_M4ADC1SYSLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC1BUS (RCC_AHB1EN1_M7ADC1BUSEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC1BUS (RCC_AHB1EN1_M4ADC1BUSEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC1BUSLP (RCC_AHB1EN1_M7ADC1BUSLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC1BUSLP (RCC_AHB1EN1_M4ADC1BUSLPEN) + +#define RCC_AHB1_PERIPHEN_M7_ETH2TX (RCC_AHB1EN2_M7ETH2TXEN ) +#define RCC_AHB1_PERIPHEN_M4_ETH2TX (RCC_AHB1EN2_M4ETH2TXEN ) +#define RCC_AHB1_PERIPHEN_M7_ETH2TXLP (RCC_AHB1EN2_M7ETH2TXLPEN ) +#define RCC_AHB1_PERIPHEN_M4_ETH2TXLP (RCC_AHB1EN2_M4ETH2TXLPEN ) +#define RCC_AHB1_PERIPHEN_M7_ETH2RX (RCC_AHB1EN2_M7ETH2RXEN ) +#define RCC_AHB1_PERIPHEN_M4_ETH2RX (RCC_AHB1EN2_M4ETH2RXEN ) +#define RCC_AHB1_PERIPHEN_M7_ETH2RXLP (RCC_AHB1EN2_M7ETH2RXLPEN ) +#define RCC_AHB1_PERIPHEN_M4_ETH2RXLP (RCC_AHB1EN2_M4ETH2RXLPEN ) +#define RCC_AHB1_PERIPHEN_M7_ETH2MAC (RCC_AHB1EN2_M7ETH2MACEN ) +#define RCC_AHB1_PERIPHEN_M4_ETH2MAC (RCC_AHB1EN2_M4ETH2MACEN ) +#define RCC_AHB1_PERIPHEN_M7_ETH2MACLP (RCC_AHB1EN2_M7ETH2MACLPEN) +#define RCC_AHB1_PERIPHEN_M4_ETH2MACLP (RCC_AHB1EN2_M4ETH2MACLPEN) + +#define RCC_AHB1_PERIPHEN_M7_ECCMAC (RCC_AHB1EN3_M7ECCMACEN ) +#define RCC_AHB1_PERIPHEN_M4_ECCMAC (RCC_AHB1EN3_M4ECCMACEN ) +#define RCC_AHB1_PERIPHEN_M7_ECCMACLP (RCC_AHB1EN3_M7ECCMACLPEN ) +#define RCC_AHB1_PERIPHEN_M4_ECCMACLP (RCC_AHB1EN3_M4ECCMACLPEN ) +#define RCC_AHB1_PERIPHEN_M7_DMA1 (RCC_AHB1EN3_M7DMA1EN ) +#define RCC_AHB1_PERIPHEN_M4_DMA1 (RCC_AHB1EN3_M4DMA1EN ) +#define RCC_AHB1_PERIPHEN_M7_DMA1LP (RCC_AHB1EN3_M7DMA1LPEN ) +#define RCC_AHB1_PERIPHEN_M4_DMA1LP (RCC_AHB1EN3_M4DMA1LPEN ) +#define RCC_AHB1_PERIPHEN_M7_DMA2 (RCC_AHB1EN3_M7DMA2EN ) +#define RCC_AHB1_PERIPHEN_M4_DMA2 (RCC_AHB1EN3_M4DMA2EN ) +#define RCC_AHB1_PERIPHEN_M7_DMA2LP (RCC_AHB1EN3_M7DMA2LPEN ) +#define RCC_AHB1_PERIPHEN_M4_DMA2LP (RCC_AHB1EN3_M4DMA2LPEN ) +#define RCC_AHB1_PERIPHEN_M7_DMA3 (RCC_AHB1EN3_M7DMA3EN ) +#define RCC_AHB1_PERIPHEN_M4_DMA3 (RCC_AHB1EN3_M4DMA3EN ) +#define RCC_AHB1_PERIPHEN_M7_DMA3LP (RCC_AHB1EN3_M7DMA3LPEN ) +#define RCC_AHB1_PERIPHEN_M4_DMA3LP (RCC_AHB1EN3_M4DMA3LPEN ) + +#define RCC_AHB1_PERIPHEN_M7_ADC2PLL (RCC_AHB1EN4_M7ADC2PLLEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC2PLL (RCC_AHB1EN4_M4ADC2PLLEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC2PLLLP (RCC_AHB1EN4_M7ADC2PLLLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC2PLLLP (RCC_AHB1EN4_M4ADC2PLLLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC2SYS (RCC_AHB1EN4_M7ADC2SYSEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC2SYS (RCC_AHB1EN4_M4ADC2SYSEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC2SYSLP (RCC_AHB1EN4_M7ADC2SYSLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC2SYSLP (RCC_AHB1EN4_M4ADC2SYSLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC2BUS (RCC_AHB1EN4_M7ADC2BUSEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC2BUS (RCC_AHB1EN4_M4ADC2BUSEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC2BUSLP (RCC_AHB1EN4_M7ADC2BUSLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC2BUSLP (RCC_AHB1EN4_M4ADC2BUSLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC3PLL (RCC_AHB1EN4_M7ADC3PLLEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC3PLL (RCC_AHB1EN4_M4ADC3PLLEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC3PLLLP (RCC_AHB1EN4_M7ADC3PLLLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC3PLLLP (RCC_AHB1EN4_M4ADC3PLLLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC3SYS (RCC_AHB1EN4_M7ADC3SYSEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC3SYS (RCC_AHB1EN4_M4ADC3SYSEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC3SYSLP (RCC_AHB1EN4_M7ADC3SYSLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC3SYSLP (RCC_AHB1EN4_M4ADC3SYSLPEN) +#define RCC_AHB1_PERIPHEN_M7_ADC3BUS (RCC_AHB1EN4_M7ADC3BUSEN ) +#define RCC_AHB1_PERIPHEN_M4_ADC3BUS (RCC_AHB1EN4_M4ADC3BUSEN ) +#define RCC_AHB1_PERIPHEN_M7_ADC3BUSLP (RCC_AHB1EN4_M7ADC3BUSLPEN) +#define RCC_AHB1_PERIPHEN_M4_ADC3BUSLP (RCC_AHB1EN4_M4ADC3BUSLPEN) +/** APB1 peripherals enable **/ +#define RCC_APB1_PERIPHEN_M7_BTIM1 (RCC_APB1EN1_M7BTIM1EN ) +#define RCC_APB1_PERIPHEN_M4_BTIM1 (RCC_APB1EN1_M4BTIM1EN ) +#define RCC_APB1_PERIPHEN_M7_BTIM1LP (RCC_APB1EN1_M7BTIM1LPEN ) +#define RCC_APB1_PERIPHEN_M4_BTIM1LP (RCC_APB1EN1_M4BTIM1LPEN ) +#define RCC_APB1_PERIPHEN_M7_BTIM2 (RCC_APB1EN1_M7BTIM2EN ) +#define RCC_APB1_PERIPHEN_M4_BTIM2 (RCC_APB1EN1_M4BTIM2EN ) +#define RCC_APB1_PERIPHEN_M7_BTIM2LP (RCC_APB1EN1_M7BTIM2LPEN ) +#define RCC_APB1_PERIPHEN_M4_BTIM2LP (RCC_APB1EN1_M4BTIM2LPEN ) +#define RCC_APB1_PERIPHEN_M7_BTIM3 (RCC_APB1EN1_M7BTIM3EN ) +#define RCC_APB1_PERIPHEN_M4_BTIM3 (RCC_APB1EN1_M4BTIM3EN ) +#define RCC_APB1_PERIPHEN_M7_BTIM3LP (RCC_APB1EN1_M7BTIM3LPEN ) +#define RCC_APB1_PERIPHEN_M4_BTIM3LP (RCC_APB1EN1_M4BTIM3LPEN ) +#define RCC_APB1_PERIPHEN_M7_BTIM4 (RCC_APB1EN1_M7BTIM4EN ) +#define RCC_APB1_PERIPHEN_M4_BTIM4 (RCC_APB1EN1_M4BTIM4EN ) +#define RCC_APB1_PERIPHEN_M7_BTIM4LP (RCC_APB1EN1_M7BTIM4LPEN ) +#define RCC_APB1_PERIPHEN_M4_BTIM4LP (RCC_APB1EN1_M4BTIM4LPEN ) +#define RCC_APB1_PERIPHEN_M7_GTIMB1 (RCC_APB1EN1_M7GTIMB1EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMB1 (RCC_APB1EN1_M4GTIMB1EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMB1LP (RCC_APB1EN1_M7GTIMB1LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMB1LP (RCC_APB1EN1_M4GTIMB1LPEN) +#define RCC_APB1_PERIPHEN_M7_GTIMB2 (RCC_APB1EN1_M7GTIMB2EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMB2 (RCC_APB1EN1_M4GTIMB2EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMB2LP (RCC_APB1EN1_M7GTIMB2LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMB2LP (RCC_APB1EN1_M4GTIMB2LPEN) +#define RCC_APB1_PERIPHEN_M7_GTIMB3 (RCC_APB1EN1_M7GTIMB3EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMB3 (RCC_APB1EN1_M4GTIMB3EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMB3LP (RCC_APB1EN1_M7GTIMB3LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMB3LP (RCC_APB1EN1_M4GTIMB3LPEN) +#define RCC_APB1_PERIPHEN_M7_GTIMA4 (RCC_APB1EN1_M7GTIMA4EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMA4 (RCC_APB1EN1_M4GTIMA4EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMA4LP (RCC_APB1EN1_M7GTIMA4LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMA4LP (RCC_APB1EN1_M4GTIMA4LPEN) + +#define RCC_APB1_PERIPHEN_M7_GTIMA5 (RCC_APB1EN2_M7GTIMA5EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMA5 (RCC_APB1EN2_M4GTIMA5EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMA5LP (RCC_APB1EN2_M7GTIMA5LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMA5LP (RCC_APB1EN2_M4GTIMA5LPEN) +#define RCC_APB1_PERIPHEN_M7_GTIMA6 (RCC_APB1EN2_M7GTIMA6EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMA6 (RCC_APB1EN2_M4GTIMA6EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMA6LP (RCC_APB1EN2_M7GTIMA6LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMA6LP (RCC_APB1EN2_M4GTIMA6LPEN) +#define RCC_APB1_PERIPHEN_M7_GTIMA7 (RCC_APB1EN2_M7GTIMA7EN ) +#define RCC_APB1_PERIPHEN_M4_GTIMA7 (RCC_APB1EN2_M4GTIMA7EN ) +#define RCC_APB1_PERIPHEN_M7_GTIMA7LP (RCC_APB1EN2_M7GTIMA7LPEN) +#define RCC_APB1_PERIPHEN_M4_GTIMA7LP (RCC_APB1EN2_M4GTIMA7LPEN) +#define RCC_APB1_PERIPHEN_M7_SPI3 (RCC_APB1EN2_M7SPI3EN ) +#define RCC_APB1_PERIPHEN_M4_SPI3 (RCC_APB1EN2_M4SPI3EN ) +#define RCC_APB1_PERIPHEN_M7_SPI3LP (RCC_APB1EN2_M7SPI3LPEN ) +#define RCC_APB1_PERIPHEN_M4_SPI3LP (RCC_APB1EN2_M4SPI3LPEN ) +#define RCC_APB1_PERIPHEN_M7_DAC12 (RCC_APB1EN2_M7DAC12EN ) +#define RCC_APB1_PERIPHEN_M4_DAC12 (RCC_APB1EN2_M4DAC12EN ) +#define RCC_APB1_PERIPHEN_M7_DAC12LP (RCC_APB1EN2_M7DAC12LPEN ) +#define RCC_APB1_PERIPHEN_M4_DAC12LP (RCC_APB1EN2_M4DAC12LPEN ) +#define RCC_APB1_PERIPHEN_M7_WWDG2 (RCC_APB1EN2_M7WWDG2EN ) +#define RCC_APB1_PERIPHEN_M4_WWDG2 (RCC_APB1EN2_M4WWDG2EN ) +#define RCC_APB1_PERIPHEN_M7_WWDG2LP (RCC_APB1EN2_M7WWDG2LPEN ) +#define RCC_APB1_PERIPHEN_M4_WWDG2LP (RCC_APB1EN2_M4WWDG2LPEN ) + + +#define RCC_APB1_PERIPHEN_M7_USART1 (RCC_APB1EN3_M7USART1EN ) +#define RCC_APB1_PERIPHEN_M4_USART1 (RCC_APB1EN3_M4USART1EN ) +#define RCC_APB1_PERIPHEN_M7_USART1LP (RCC_APB1EN3_M7USART1LPEN) +#define RCC_APB1_PERIPHEN_M4_USART1LP (RCC_APB1EN3_M4USART1LPEN) +#define RCC_APB1_PERIPHEN_M7_USART2 (RCC_APB1EN3_M7USART2EN ) +#define RCC_APB1_PERIPHEN_M4_USART2 (RCC_APB1EN3_M4USART2EN ) +#define RCC_APB1_PERIPHEN_M7_USART2LP (RCC_APB1EN3_M7USART2LPEN) +#define RCC_APB1_PERIPHEN_M4_USART2LP (RCC_APB1EN3_M4USART2LPEN) +#define RCC_APB1_PERIPHEN_M7_USART3 (RCC_APB1EN3_M7USART3EN ) +#define RCC_APB1_PERIPHEN_M4_USART3 (RCC_APB1EN3_M4USART3EN ) +#define RCC_APB1_PERIPHEN_M7_USART3LP (RCC_APB1EN3_M7USART3LPEN) +#define RCC_APB1_PERIPHEN_M4_USART3LP (RCC_APB1EN3_M4USART3LPEN) +#define RCC_APB1_PERIPHEN_M7_USART4 (RCC_APB1EN3_M7USART4EN ) +#define RCC_APB1_PERIPHEN_M4_USART4 (RCC_APB1EN3_M4USART4EN ) +#define RCC_APB1_PERIPHEN_M7_USART4LP (RCC_APB1EN3_M7USART4LPEN) +#define RCC_APB1_PERIPHEN_M4_USART4LP (RCC_APB1EN3_M4USART4LPEN) +#define RCC_APB1_PERIPHEN_M7_UART9 (RCC_APB1EN3_M7UART9EN ) +#define RCC_APB1_PERIPHEN_M4_UART9 (RCC_APB1EN3_M4UART9EN ) +#define RCC_APB1_PERIPHEN_M7_UART9LP (RCC_APB1EN3_M7UART9LPEN ) +#define RCC_APB1_PERIPHEN_M4_UART9LP (RCC_APB1EN3_M4UART9LPEN ) +#define RCC_APB1_PERIPHEN_M7_UART10 (RCC_APB1EN3_M7UART10EN ) +#define RCC_APB1_PERIPHEN_M4_UART10 (RCC_APB1EN3_M4UART10EN ) +#define RCC_APB1_PERIPHEN_M7_UART10LP (RCC_APB1EN3_M7UART10LPEN ) +#define RCC_APB1_PERIPHEN_M4_UART10LP (RCC_APB1EN3_M4UART10LPEN ) +#define RCC_APB1_PERIPHEN_M7_UART11 (RCC_APB1EN3_M7UART11EN ) +#define RCC_APB1_PERIPHEN_M4_UART11 (RCC_APB1EN3_M4UART11EN ) +#define RCC_APB1_PERIPHEN_M7_UART11LP (RCC_APB1EN3_M7UART11LPEN ) +#define RCC_APB1_PERIPHEN_M4_UART11LP (RCC_APB1EN3_M4UART11LPEN ) +#define RCC_APB1_PERIPHEN_M7_UART12 (RCC_APB1EN3_M7UART12EN ) +#define RCC_APB1_PERIPHEN_M4_UART12 (RCC_APB1EN3_M4UART12EN ) +#define RCC_APB1_PERIPHEN_M7_UART12LP (RCC_APB1EN3_M7UART12LPEN ) +#define RCC_APB1_PERIPHEN_M4_UART12LP (RCC_APB1EN3_M4UART12LPEN ) + +#define RCC_APB1_PERIPHEN_M7_I2S3 (RCC_APB1EN4_M7I2S3EN ) +#define RCC_APB1_PERIPHEN_M4_I2S3 (RCC_APB1EN4_M4I2S3EN ) +#define RCC_APB1_PERIPHEN_M7_I2S3LP (RCC_APB1EN4_M7I2S3LPEN ) +#define RCC_APB1_PERIPHEN_M4_I2S3LP (RCC_APB1EN4_M4I2S3LPEN ) +#define RCC_APB1_PERIPHEN_M7_I2S4 (RCC_APB1EN4_M7I2S4EN ) +#define RCC_APB1_PERIPHEN_M4_I2S4 (RCC_APB1EN4_M4I2S4EN ) +#define RCC_APB1_PERIPHEN_M7_I2S4LP (RCC_APB1EN4_M7I2S4LPEN ) +#define RCC_APB1_PERIPHEN_M4_I2S4LP (RCC_APB1EN4_M4I2S4LPEN ) +#define RCC_APB1_PERIPHEN_M7_I2C1 (RCC_APB1EN4_M7I2C1EN ) +#define RCC_APB1_PERIPHEN_M4_I2C1 (RCC_APB1EN4_M4I2C1EN ) +#define RCC_APB1_PERIPHEN_M7_I2C1LP (RCC_APB1EN4_M7I2C1LPEN ) +#define RCC_APB1_PERIPHEN_M4_I2C1LP (RCC_APB1EN4_M4I2C1LPEN ) +#define RCC_APB1_PERIPHEN_M7_I2C2 (RCC_APB1EN4_M7I2C2EN ) +#define RCC_APB1_PERIPHEN_M4_I2C2 (RCC_APB1EN4_M4I2C2EN ) +#define RCC_APB1_PERIPHEN_M7_I2C2LP (RCC_APB1EN4_M7I2C2LPEN ) +#define RCC_APB1_PERIPHEN_M4_I2C2LP (RCC_APB1EN4_M4I2C2LPEN ) +#define RCC_APB1_PERIPHEN_M7_I2C3 (RCC_APB1EN4_M7I2C3EN ) +#define RCC_APB1_PERIPHEN_M4_I2C3 (RCC_APB1EN4_M4I2C3EN ) +#define RCC_APB1_PERIPHEN_M7_I2C3LP (RCC_APB1EN4_M7I2C3LPEN ) +#define RCC_APB1_PERIPHEN_M4_I2C3LP (RCC_APB1EN4_M4I2C3LPEN ) + +#define RCC_APB1_PERIPHEN_M7_FDCAN1 (RCC_APB1EN5_M7FDCAN1EN ) +#define RCC_APB1_PERIPHEN_M4_FDCAN1 (RCC_APB1EN5_M4FDCAN1EN ) +#define RCC_APB1_PERIPHEN_M7_FDCAN1LP (RCC_APB1EN5_M7FDCAN1LPEN) +#define RCC_APB1_PERIPHEN_M4_FDCAN1LP (RCC_APB1EN5_M4FDCAN1LPEN) +#define RCC_APB1_PERIPHEN_M7_FDCAN2 (RCC_APB1EN5_M7FDCAN2EN ) +#define RCC_APB1_PERIPHEN_M4_FDCAN2 (RCC_APB1EN5_M4FDCAN2EN ) +#define RCC_APB1_PERIPHEN_M7_FDCAN2LP (RCC_APB1EN5_M7FDCAN2LPEN) +#define RCC_APB1_PERIPHEN_M4_FDCAN2LP (RCC_APB1EN5_M4FDCAN2LPEN) +#define RCC_APB1_PERIPHEN_M7_FDCAN5 (RCC_APB1EN5_M7FDCAN5EN ) +#define RCC_APB1_PERIPHEN_M4_FDCAN5 (RCC_APB1EN5_M4FDCAN5EN ) +#define RCC_APB1_PERIPHEN_M7_FDCAN5LP (RCC_APB1EN5_M7FDCAN5LPEN) +#define RCC_APB1_PERIPHEN_M4_FDCAN5LP (RCC_APB1EN5_M4FDCAN5LPEN) +#define RCC_APB1_PERIPHEN_M7_FDCAN6 (RCC_APB1EN5_M7FDCAN6EN ) +#define RCC_APB1_PERIPHEN_M4_FDCAN6 (RCC_APB1EN5_M4FDCAN6EN ) +#define RCC_APB1_PERIPHEN_M7_FDCAN6LP (RCC_APB1EN5_M7FDCAN6LPEN) +#define RCC_APB1_PERIPHEN_M4_FDCAN6LP (RCC_APB1EN5_M4FDCAN6LPEN) +/** AHB2 peripherals enable **/ +#define RCC_AHB2_PERIPHEN_M7_USB1 (RCC_AHB2EN1_M7USB1EN ) +#define RCC_AHB2_PERIPHEN_M4_USB1 (RCC_AHB2EN1_M4USB1EN ) +#define RCC_AHB2_PERIPHEN_M7_USB1LP (RCC_AHB2EN1_M7USB1LPEN ) +#define RCC_AHB2_PERIPHEN_M4_USB1LP (RCC_AHB2EN1_M4USB1LPEN ) +#define RCC_AHB2_PERIPHEN_M7_ECCM2 (RCC_AHB2EN1_M7ECCM2EN ) +#define RCC_AHB2_PERIPHEN_M4_ECCM2 (RCC_AHB2EN1_M4ECCM2EN ) +#define RCC_AHB2_PERIPHEN_M7_ECCM2LP (RCC_AHB2EN1_M7ECCM2LPEN ) +#define RCC_AHB2_PERIPHEN_M4_ECCM2LP (RCC_AHB2EN1_M4ECCM2LPEN ) +#define RCC_AHB2_PERIPHEN_M7_CORDIC (RCC_AHB2EN1_M7CORDICEN ) +#define RCC_AHB2_PERIPHEN_M4_CORDIC (RCC_AHB2EN1_M4CORDICEN ) +#define RCC_AHB2_PERIPHEN_M7_CORDICLP (RCC_AHB2EN1_M7CORDICLPEN ) +#define RCC_AHB2_PERIPHEN_M4_CORDICLP (RCC_AHB2EN1_M4CORDICLPEN ) +#define RCC_AHB2_PERIPHEN_M7_SDPU (RCC_AHB2EN1_M7SDPUEN ) +#define RCC_AHB2_PERIPHEN_M4_SDPU (RCC_AHB2EN1_M4SDPUEN ) +#define RCC_AHB2_PERIPHEN_M7_SDPULP (RCC_AHB2EN1_M7SDPULPEN ) +#define RCC_AHB2_PERIPHEN_M4_SDPULP (RCC_AHB2EN1_M4SDPULPEN ) +#define RCC_AHB2_PERIPHEN_M7_FMAC (RCC_AHB2EN1_M7FMACEN ) +#define RCC_AHB2_PERIPHEN_M4_FMAC (RCC_AHB2EN1_M4FMACEN ) +#define RCC_AHB2_PERIPHEN_M7_FMACLP (RCC_AHB2EN1_M7FMACLPEN ) +#define RCC_AHB2_PERIPHEN_M4_FMACLP (RCC_AHB2EN1_M4FMACLPEN ) + +#define RCC_AHB2_PERIPHEN_M7_DAC56 (RCC_AHB2EN2_M7DAC56EN ) +#define RCC_AHB2_PERIPHEN_M4_DAC56 (RCC_AHB2EN2_M4DAC56EN ) +#define RCC_AHB2_PERIPHEN_M7_DAC56LP (RCC_AHB2EN2_M7DAC56LPEN ) +#define RCC_AHB2_PERIPHEN_M4_DAC56LP (RCC_AHB2EN2_M4DAC56LPEN ) +#define RCC_AHB2_PERIPHEN_M7_DAC34 (RCC_AHB2EN2_M7DAC34EN ) +#define RCC_AHB2_PERIPHEN_M4_DAC34 (RCC_AHB2EN2_M4DAC34EN ) +#define RCC_AHB2_PERIPHEN_M7_DAC34LP (RCC_AHB2EN2_M7DAC34LPEN ) +#define RCC_AHB2_PERIPHEN_M4_DAC34LP (RCC_AHB2EN2_M4DAC34LPEN ) +#define RCC_AHB2_PERIPHEN_M7_ETH1TX (RCC_AHB2EN2_M7ETH1TXEN ) +#define RCC_AHB2_PERIPHEN_M4_ETH1TX (RCC_AHB2EN2_M4ETH1TXEN ) +#define RCC_AHB2_PERIPHEN_M7_ETH1TXLP (RCC_AHB2EN2_M7ETH1TXLPEN ) +#define RCC_AHB2_PERIPHEN_M4_ETH1TXLP (RCC_AHB2EN2_M4ETH1TXLPEN ) +#define RCC_AHB2_PERIPHEN_M7_ETH1RX (RCC_AHB2EN2_M7ETH1RXEN ) +#define RCC_AHB2_PERIPHEN_M4_ETH1RX (RCC_AHB2EN2_M4ETH1RXEN ) +#define RCC_AHB2_PERIPHEN_M7_ETH1RXLP (RCC_AHB2EN2_M7ETH1RXLPEN ) +#define RCC_AHB2_PERIPHEN_M4_ETH1RXLP (RCC_AHB2EN2_M4ETH1RXLPEN ) +#define RCC_AHB2_PERIPHEN_M7_ETH1MAC (RCC_AHB2EN2_M7ETH1MACEN ) +#define RCC_AHB2_PERIPHEN_M4_ETH1MAC (RCC_AHB2EN2_M4ETH1MACEN ) +#define RCC_AHB2_PERIPHEN_M7_ETH1MACLP (RCC_AHB2EN2_M7ETH1MACLPEN) +#define RCC_AHB2_PERIPHEN_M4_ETH1MACLP (RCC_AHB2EN2_M4ETH1MACLPEN) +/** APB2 peripherals enable **/ +#define RCC_APB2_PERIPHEN_M7_ATIM1 (RCC_APB2EN1_M7ATIM1EN ) +#define RCC_APB2_PERIPHEN_M4_ATIM1 (RCC_APB2EN1_M4ATIM1EN ) +#define RCC_APB2_PERIPHEN_M7_ATIM1LP (RCC_APB2EN1_M7ATIM1LPEN ) +#define RCC_APB2_PERIPHEN_M4_ATIM1LP (RCC_APB2EN1_M4ATIM1LPEN ) +#define RCC_APB2_PERIPHEN_M7_ATIM2 (RCC_APB2EN1_M7ATIM2EN ) +#define RCC_APB2_PERIPHEN_M4_ATIM2 (RCC_APB2EN1_M4ATIM2EN ) +#define RCC_APB2_PERIPHEN_M7_ATIM2LP (RCC_APB2EN1_M7ATIM2LPEN ) +#define RCC_APB2_PERIPHEN_M4_ATIM2LP (RCC_APB2EN1_M4ATIM2LPEN ) +#define RCC_APB2_PERIPHEN_M7_GTIMA1 (RCC_APB2EN1_M7GTIMA1EN ) +#define RCC_APB2_PERIPHEN_M4_GTIMA1 (RCC_APB2EN1_M4GTIMA1EN ) +#define RCC_APB2_PERIPHEN_M7_GTIMA1LP (RCC_APB2EN1_M7GTIMA1LPEN ) +#define RCC_APB2_PERIPHEN_M4_GTIMA1LP (RCC_APB2EN1_M4GTIMA1LPEN ) +#define RCC_APB2_PERIPHEN_M7_GTIMA2 (RCC_APB2EN1_M7GTIMA2EN ) +#define RCC_APB2_PERIPHEN_M4_GTIMA2 (RCC_APB2EN1_M4GTIMA2EN ) +#define RCC_APB2_PERIPHEN_M7_GTIMA2LP (RCC_APB2EN1_M7GTIMA2LPEN ) +#define RCC_APB2_PERIPHEN_M4_GTIMA2LP (RCC_APB2EN1_M4GTIMA2LPEN ) +#define RCC_APB2_PERIPHEN_M7_GTIMA3 (RCC_APB2EN1_M7GTIMA3EN ) +#define RCC_APB2_PERIPHEN_M4_GTIMA3 (RCC_APB2EN1_M4GTIMA3EN ) +#define RCC_APB2_PERIPHEN_M7_GTIMA3LP (RCC_APB2EN1_M7GTIMA3LPEN ) +#define RCC_APB2_PERIPHEN_M4_GTIMA3LP (RCC_APB2EN1_M4GTIMA3LPEN ) +#define RCC_APB2_PERIPHEN_M7_SHRTIM1 (RCC_APB2EN1_M7SHRTIM1EN ) +#define RCC_APB2_PERIPHEN_M4_SHRTIM1 (RCC_APB2EN1_M4SHRTIM1EN ) +#define RCC_APB2_PERIPHEN_M7_SHRTIM1LP (RCC_APB2EN1_M7SHRTIM1LPEN) +#define RCC_APB2_PERIPHEN_M4_SHRTIM1LP (RCC_APB2EN1_M4SHRTIM1LPEN) +#define RCC_APB2_PERIPHEN_M7_SHRTIM2 (RCC_APB2EN1_M7SHRTIM2EN ) +#define RCC_APB2_PERIPHEN_M4_SHRTIM2 (RCC_APB2EN1_M4SHRTIM2EN ) +#define RCC_APB2_PERIPHEN_M7_SHRTIM2LP (RCC_APB2EN1_M7SHRTIM2LPEN) +#define RCC_APB2_PERIPHEN_M4_SHRTIM2LP (RCC_APB2EN1_M4SHRTIM2LPEN) + +#define RCC_APB2_PERIPHEN_M7_I2S1 (RCC_APB2EN2_M7I2S1EN ) +#define RCC_APB2_PERIPHEN_M4_I2S1 (RCC_APB2EN2_M4I2S1EN ) +#define RCC_APB2_PERIPHEN_M7_I2S1LP (RCC_APB2EN2_M7I2S1LPEN ) +#define RCC_APB2_PERIPHEN_M4_I2S1LP (RCC_APB2EN2_M4I2S1LPEN ) +#define RCC_APB2_PERIPHEN_M7_I2S2 (RCC_APB2EN2_M7I2S2EN ) +#define RCC_APB2_PERIPHEN_M4_I2S2 (RCC_APB2EN2_M4I2S2EN ) +#define RCC_APB2_PERIPHEN_M7_I2S2LP (RCC_APB2EN2_M7I2S2LPEN ) +#define RCC_APB2_PERIPHEN_M4_I2S2LP (RCC_APB2EN2_M4I2S2LPEN ) +#define RCC_APB2_PERIPHEN_M7_SPI1 (RCC_APB2EN2_M7SPI1EN ) +#define RCC_APB2_PERIPHEN_M4_SPI1 (RCC_APB2EN2_M4SPI1EN ) +#define RCC_APB2_PERIPHEN_M7_SPI1LP (RCC_APB2EN2_M7SPI1LPEN ) +#define RCC_APB2_PERIPHEN_M4_SPI1LP (RCC_APB2EN2_M4SPI1LPEN ) +#define RCC_APB2_PERIPHEN_M7_SPI2 (RCC_APB2EN2_M7SPI2EN ) +#define RCC_APB2_PERIPHEN_M4_SPI2 (RCC_APB2EN2_M4SPI2EN ) +#define RCC_APB2_PERIPHEN_M7_SPI2LP (RCC_APB2EN2_M7SPI2LPEN ) +#define RCC_APB2_PERIPHEN_M4_SPI2LP (RCC_APB2EN2_M4SPI2LPEN ) +#define RCC_APB2_PERIPHEN_M7_DSMU (RCC_APB2EN2_M7DSMUEN ) +#define RCC_APB2_PERIPHEN_M4_DSMU (RCC_APB2EN2_M4DSMUEN ) +#define RCC_APB2_PERIPHEN_M7_DSMULP (RCC_APB2EN2_M7DSMULPEN ) +#define RCC_APB2_PERIPHEN_M4_DSMULP (RCC_APB2EN2_M4DSMULPEN ) +#define RCC_APB2_PERIPHEN_M7_I2C4 (RCC_APB2EN2_M7I2C4EN ) +#define RCC_APB2_PERIPHEN_M4_I2C4 (RCC_APB2EN2_M4I2C4EN ) +#define RCC_APB2_PERIPHEN_M7_I2C4LP (RCC_APB2EN2_M7I2C4LPEN ) +#define RCC_APB2_PERIPHEN_M4_I2C4LP (RCC_APB2EN2_M4I2C4LPEN ) +#define RCC_APB2_PERIPHEN_M7_I2C5 (RCC_APB2EN2_M7I2C5EN ) +#define RCC_APB2_PERIPHEN_M4_I2C5 (RCC_APB2EN2_M4I2C5EN ) +#define RCC_APB2_PERIPHEN_M7_I2C5LP (RCC_APB2EN2_M7I2C5LPEN ) +#define RCC_APB2_PERIPHEN_M4_I2C5LP (RCC_APB2EN2_M4I2C5LPEN ) +#define RCC_APB2_PERIPHEN_M7_I2C6 (RCC_APB2EN2_M7I2C6EN ) +#define RCC_APB2_PERIPHEN_M4_I2C6 (RCC_APB2EN2_M4I2C6EN ) +#define RCC_APB2_PERIPHEN_M7_I2C6LP (RCC_APB2EN2_M7I2C6LPEN ) +#define RCC_APB2_PERIPHEN_M4_I2C6LP (RCC_APB2EN2_M4I2C6LPEN ) + +#define RCC_APB2_PERIPHEN_M7_USART5 (RCC_APB2EN3_M7USART5EN ) +#define RCC_APB2_PERIPHEN_M4_USART5 (RCC_APB2EN3_M4USART5EN ) +#define RCC_APB2_PERIPHEN_M7_USART5LP (RCC_APB2EN3_M7USART5LPEN ) +#define RCC_APB2_PERIPHEN_M4_USART5LP (RCC_APB2EN3_M4USART5LPEN ) +#define RCC_APB2_PERIPHEN_M7_USART6 (RCC_APB2EN3_M7USART6EN ) +#define RCC_APB2_PERIPHEN_M4_USART6 (RCC_APB2EN3_M4USART6EN ) +#define RCC_APB2_PERIPHEN_M7_USART6LP (RCC_APB2EN3_M7USART6LPEN ) +#define RCC_APB2_PERIPHEN_M4_USART6LP (RCC_APB2EN3_M4USART6LPEN ) +#define RCC_APB2_PERIPHEN_M7_USART7 (RCC_APB2EN3_M7USART7EN ) +#define RCC_APB2_PERIPHEN_M4_USART7 (RCC_APB2EN3_M4USART7EN ) +#define RCC_APB2_PERIPHEN_M7_USART7LP (RCC_APB2EN3_M7USART7LPEN ) +#define RCC_APB2_PERIPHEN_M4_USART7LP (RCC_APB2EN3_M4USART7LPEN ) +#define RCC_APB2_PERIPHEN_M7_USART8 (RCC_APB2EN3_M7USART8EN ) +#define RCC_APB2_PERIPHEN_M4_USART8 (RCC_APB2EN3_M4USART8EN ) +#define RCC_APB2_PERIPHEN_M7_USART8LP (RCC_APB2EN3_M7USART8LPEN ) +#define RCC_APB2_PERIPHEN_M4_USART8LP (RCC_APB2EN3_M4USART8LPEN ) +#define RCC_APB2_PERIPHEN_M7_UART13 (RCC_APB2EN3_M7UART13EN ) +#define RCC_APB2_PERIPHEN_M4_UART13 (RCC_APB2EN3_M4UART13EN ) +#define RCC_APB2_PERIPHEN_M7_UART13LP (RCC_APB2EN3_M7UART13LPEN ) +#define RCC_APB2_PERIPHEN_M4_UART13LP (RCC_APB2EN3_M4UART13LPEN ) +#define RCC_APB2_PERIPHEN_M7_UART14 (RCC_APB2EN3_M7UART14EN ) +#define RCC_APB2_PERIPHEN_M4_UART14 (RCC_APB2EN3_M4UART14EN ) +#define RCC_APB2_PERIPHEN_M7_UART14LP (RCC_APB2EN3_M7UART14LPEN ) +#define RCC_APB2_PERIPHEN_M4_UART14LP (RCC_APB2EN3_M4UART14LPEN ) +#define RCC_APB2_PERIPHEN_M7_UART15 (RCC_APB2EN3_M7UART15EN ) +#define RCC_APB2_PERIPHEN_M4_UART15 (RCC_APB2EN3_M4UART15EN ) +#define RCC_APB2_PERIPHEN_M7_UART15LP (RCC_APB2EN3_M7UART15LPEN ) +#define RCC_APB2_PERIPHEN_M4_UART15LP (RCC_APB2EN3_M4UART15LPEN ) + +#define RCC_APB2_PERIPHEN_M7_FDCAN3 (RCC_APB2EN4_M7FDCAN3EN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN3 (RCC_APB2EN4_M4FDCAN3EN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN3LP (RCC_APB2EN4_M7FDCAN3LPEN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN3LP (RCC_APB2EN4_M4FDCAN3LPEN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN4 (RCC_APB2EN4_M7FDCAN4EN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN4 (RCC_APB2EN4_M4FDCAN4EN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN4LP (RCC_APB2EN4_M7FDCAN4LPEN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN4LP (RCC_APB2EN4_M4FDCAN4LPEN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN7 (RCC_APB2EN4_M7FDCAN7EN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN7 (RCC_APB2EN4_M4FDCAN7EN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN7LP (RCC_APB2EN4_M7FDCAN7LPEN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN7LP (RCC_APB2EN4_M4FDCAN7LPEN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN8 (RCC_APB2EN4_M7FDCAN8EN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN8 (RCC_APB2EN4_M4FDCAN8EN ) +#define RCC_APB2_PERIPHEN_M7_FDCAN8LP (RCC_APB2EN4_M7FDCAN8LPEN ) +#define RCC_APB2_PERIPHEN_M4_FDCAN8LP (RCC_APB2EN4_M4FDCAN8LPEN ) +/** AHB5 peripherals enable **/ +#define RCC_AHB5_PERIPHEN_M7_GPIOA (RCC_AHB5EN1_M7GPIOAEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOA (RCC_AHB5EN1_M4GPIOAEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOALP (RCC_AHB5EN1_M7GPIOALPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOALP (RCC_AHB5EN1_M4GPIOALPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOB (RCC_AHB5EN1_M7GPIOBEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOB (RCC_AHB5EN1_M4GPIOBEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOBLP (RCC_AHB5EN1_M7GPIOBLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOBLP (RCC_AHB5EN1_M4GPIOBLPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOC (RCC_AHB5EN1_M7GPIOCEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOC (RCC_AHB5EN1_M4GPIOCEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOCLP (RCC_AHB5EN1_M7GPIOCLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOCLP (RCC_AHB5EN1_M4GPIOCLPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOD (RCC_AHB5EN1_M7GPIODEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOD (RCC_AHB5EN1_M4GPIODEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIODLP (RCC_AHB5EN1_M7GPIODLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIODLP (RCC_AHB5EN1_M4GPIODLPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOE (RCC_AHB5EN1_M7GPIOEEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOE (RCC_AHB5EN1_M4GPIOEEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOELP (RCC_AHB5EN1_M7GPIOELPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOELP (RCC_AHB5EN1_M4GPIOELPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOF (RCC_AHB5EN1_M7GPIOFEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOF (RCC_AHB5EN1_M4GPIOFEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOFLP (RCC_AHB5EN1_M7GPIOFLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOFLP (RCC_AHB5EN1_M4GPIOFLPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOG (RCC_AHB5EN1_M7GPIOGEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOG (RCC_AHB5EN1_M4GPIOGEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOGLP (RCC_AHB5EN1_M7GPIOGLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOGLP (RCC_AHB5EN1_M4GPIOGLPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOH (RCC_AHB5EN1_M7GPIOHEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOH (RCC_AHB5EN1_M4GPIOHEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOHLP (RCC_AHB5EN1_M7GPIOHLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOHLP (RCC_AHB5EN1_M4GPIOHLPEN) + +#define RCC_AHB5_PERIPHEN_M7_GPIOI (RCC_AHB5EN2_M7GPIOIEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOI (RCC_AHB5EN2_M4GPIOIEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOILP (RCC_AHB5EN2_M7GPIOILPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOILP (RCC_AHB5EN2_M4GPIOILPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOJ (RCC_AHB5EN2_M7GPIOJEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOJ (RCC_AHB5EN2_M4GPIOJEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOJLP (RCC_AHB5EN2_M7GPIOJLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOJLP (RCC_AHB5EN2_M4GPIOJLPEN) +#define RCC_AHB5_PERIPHEN_M7_GPIOK (RCC_AHB5EN2_M7GPIOKEN ) +#define RCC_AHB5_PERIPHEN_M4_GPIOK (RCC_AHB5EN2_M4GPIOKEN ) +#define RCC_AHB5_PERIPHEN_M7_GPIOKLP (RCC_AHB5EN2_M7GPIOKLPEN) +#define RCC_AHB5_PERIPHEN_M4_GPIOKLP (RCC_AHB5EN2_M4GPIOKLPEN) +#define RCC_AHB5_PERIPHEN_M7_ECCM3 (RCC_AHB5EN2_M7ECCM3EN ) +#define RCC_AHB5_PERIPHEN_M4_ECCM3 (RCC_AHB5EN2_M4ECCM3EN ) +#define RCC_AHB5_PERIPHEN_M7_ECCM3LP (RCC_AHB5EN2_M7ECCM3LPEN) +#define RCC_AHB5_PERIPHEN_M4_ECCM3LP (RCC_AHB5EN2_M4ECCM3LPEN) +#define RCC_AHB5_PERIPHEN_PWR (RCC_AHB5EN2_PWREN ) +#define RCC_AHB5_PERIPHEN_PWRLP (RCC_AHB5EN2_PWRLPEN ) +#define RCC_AHB5_PERIPHEN_M7_CRC (RCC_AHB5EN2_M7CRCEN ) +#define RCC_AHB5_PERIPHEN_M4_CRC (RCC_AHB5EN2_M4CRCEN ) +#define RCC_AHB5_PERIPHEN_M7_CRCLP (RCC_AHB5EN2_M7CRCLPEN ) +#define RCC_AHB5_PERIPHEN_M4_CRCLP (RCC_AHB5EN2_M4CRCLPEN ) +#define RCC_AHB5_PERIPHEN_M7_SEMA4 (RCC_AHB5EN2_M7SEMA4EN ) +#define RCC_AHB5_PERIPHEN_M4_SEMA4 (RCC_AHB5EN2_M4SEMA4EN ) +#define RCC_AHB5_PERIPHEN_M7_SEMA4LP (RCC_AHB5EN2_M7SEMA4LPEN) +#define RCC_AHB5_PERIPHEN_M4_SEMA4LP (RCC_AHB5EN2_M4SEMA4LPEN) +#define RCC_AHB5_PERIPHEN_M7_AFIO (RCC_AHB5EN2_M7AFIOEN ) +#define RCC_AHB5_PERIPHEN_M4_AFIO (RCC_AHB5EN2_M4AFIOEN ) +#define RCC_AHB5_PERIPHEN_M7_AFIOLP (RCC_AHB5EN2_M7AFIOLPEN ) +#define RCC_AHB5_PERIPHEN_M4_AFIOLP (RCC_AHB5EN2_M4AFIOLPEN ) +/** APB5 peripherals enable **/ +#define RCC_APB5_PERIPHEN_M7_ATIM3 (RCC_APB5EN1_M7ATIM3EN ) +#define RCC_APB5_PERIPHEN_M4_ATIM3 (RCC_APB5EN1_M4ATIM3EN ) +#define RCC_APB5_PERIPHEN_M7_ATIM3LP (RCC_APB5EN1_M7ATIM3LPEN ) +#define RCC_APB5_PERIPHEN_M4_ATIM3LP (RCC_APB5EN1_M4ATIM3LPEN ) +#define RCC_APB5_PERIPHEN_M7_ATIM4 (RCC_APB5EN1_M7ATIM4EN ) +#define RCC_APB5_PERIPHEN_M4_ATIM4 (RCC_APB5EN1_M4ATIM4EN ) +#define RCC_APB5_PERIPHEN_M7_ATIM4LP (RCC_APB5EN1_M7ATIM4LPEN ) +#define RCC_APB5_PERIPHEN_M4_ATIM4LP (RCC_APB5EN1_M4ATIM4LPEN ) +#define RCC_APB5_PERIPHEN_M7_AFEC (RCC_APB5EN1_M7AFECEN ) +#define RCC_APB5_PERIPHEN_M4_AFEC (RCC_APB5EN1_M4AFECEN ) +#define RCC_APB5_PERIPHEN_M7_AFECLP (RCC_APB5EN1_M7AFECLPEN ) +#define RCC_APB5_PERIPHEN_M4_AFECLP (RCC_APB5EN1_M4AFECLPEN ) +#define RCC_APB5_PERIPHEN_M7_SPI4 (RCC_APB5EN1_M7SPI4EN ) +#define RCC_APB5_PERIPHEN_M4_SPI4 (RCC_APB5EN1_M4SPI4EN ) +#define RCC_APB5_PERIPHEN_M7_SPI4LP (RCC_APB5EN1_M7SPI4LPEN ) +#define RCC_APB5_PERIPHEN_M4_SPI4LP (RCC_APB5EN1_M4SPI4LPEN ) +#define RCC_APB5_PERIPHEN_M7_SPI5 (RCC_APB5EN1_M7SPI5EN ) +#define RCC_APB5_PERIPHEN_M4_SPI5 (RCC_APB5EN1_M4SPI5EN ) +#define RCC_APB5_PERIPHEN_M7_SPI5LP (RCC_APB5EN1_M7SPI5LPEN ) +#define RCC_APB5_PERIPHEN_M4_SPI5LP (RCC_APB5EN1_M4SPI5LPEN ) +#define RCC_APB5_PERIPHEN_M7_SPI6 (RCC_APB5EN1_M7SPI6EN ) +#define RCC_APB5_PERIPHEN_M4_SPI6 (RCC_APB5EN1_M4SPI6EN ) +#define RCC_APB5_PERIPHEN_M7_SPI6LP (RCC_APB5EN1_M7SPI6LPEN ) +#define RCC_APB5_PERIPHEN_M4_SPI6LP (RCC_APB5EN1_M4SPI6LPEN ) +#define RCC_APB5_PERIPHEN_M7_SPI7 (RCC_APB5EN1_M7SPI7EN ) +#define RCC_APB5_PERIPHEN_M4_SPI7 (RCC_APB5EN1_M4SPI7EN ) +#define RCC_APB5_PERIPHEN_M7_SPI7LP (RCC_APB5EN1_M7SPI7LPEN ) +#define RCC_APB5_PERIPHEN_M4_SPI7LP (RCC_APB5EN1_M4SPI7LPEN ) + +#define RCC_APB5_PERIPHEN_M7_I2C7 (RCC_APB5EN2_M7I2C7EN ) +#define RCC_APB5_PERIPHEN_M4_I2C7 (RCC_APB5EN2_M4I2C7EN ) +#define RCC_APB5_PERIPHEN_M7_I2C7LP (RCC_APB5EN2_M7I2C7LPEN ) +#define RCC_APB5_PERIPHEN_M4_I2C7LP (RCC_APB5EN2_M4I2C7LPEN ) +#define RCC_APB5_PERIPHEN_M7_I2C8 (RCC_APB5EN2_M7I2C8EN ) +#define RCC_APB5_PERIPHEN_M4_I2C8 (RCC_APB5EN2_M4I2C8EN ) +#define RCC_APB5_PERIPHEN_M7_I2C8LP (RCC_APB5EN2_M7I2C8LPEN ) +#define RCC_APB5_PERIPHEN_M4_I2C8LP (RCC_APB5EN2_M4I2C8LPEN ) +#define RCC_APB5_PERIPHEN_M7_I2C9 (RCC_APB5EN2_M7I2C9EN ) +#define RCC_APB5_PERIPHEN_M4_I2C9 (RCC_APB5EN2_M4I2C9EN ) +#define RCC_APB5_PERIPHEN_M7_I2C9LP (RCC_APB5EN2_M7I2C9LPEN ) +#define RCC_APB5_PERIPHEN_M4_I2C9LP (RCC_APB5EN2_M4I2C9LPEN ) +#define RCC_APB5_PERIPHEN_M7_I2C10 (RCC_APB5EN2_M7I2C10EN ) +#define RCC_APB5_PERIPHEN_M4_I2C10 (RCC_APB5EN2_M4I2C10EN ) +#define RCC_APB5_PERIPHEN_M7_I2C10LP (RCC_APB5EN2_M7I2C10LPEN ) +#define RCC_APB5_PERIPHEN_M4_I2C10LP (RCC_APB5EN2_M4I2C10LPEN ) +#define RCC_APB5_PERIPHEN_EXTI (RCC_APB5EN2_EXTIEN ) +#define RCC_APB5_PERIPHEN_EXTILP (RCC_APB5EN2_EXTILPEN ) +#define RCC_APB5_PERIPHEN_M7_RTCPCLK (RCC_APB5EN2_M7RTCPCLKEN ) +#define RCC_APB5_PERIPHEN_M4_RTCPCLK (RCC_APB5EN2_M4RTCPCLKEN ) +#define RCC_APB5_PERIPHEN_M7_RTCPCLKLP (RCC_APB5EN2_M7RTCPCLKLPEN) +#define RCC_APB5_PERIPHEN_M4_RTCPCLKLP (RCC_APB5EN2_M4RTCPCLKLPEN) +#define RCC_APB5_PERIPHEN_IWDG1PCLK (RCC_APB5EN2_IWDG1PCLKEN ) +#define RCC_APB5_PERIPHEN_IWDG1PCLKLP (RCC_APB5EN2_IWDG1PCLKLPEN) +#define RCC_APB5_PERIPHEN_IWDG2PCLK (RCC_APB5EN2_IWDG2PCLKEN ) +#define RCC_APB5_PERIPHEN_IWDG2PCLKLP (RCC_APB5EN2_IWDG2PCLKLPEN) +/** APB9 peripherals enable **/ +#define RCC_AHB9_PERIPHEN_M7_ESC (RCC_AHB9EN1_M7ESCEN ) +#define RCC_AHB9_PERIPHEN_M4_ESC (RCC_AHB9EN1_M4ESCEN ) +#define RCC_AHB9_PERIPHEN_M7_ESCLP (RCC_AHB9EN1_M7ESCLPEN) +#define RCC_AHB9_PERIPHEN_M4_ESCLP (RCC_AHB9EN1_M4ESCLPEN) +/** Retention domain peripherals enable **/ +#define RCC_RD_PERIPHEN_M7_LPTIM1 (RCC_RDEN1_M7LPTIM1EN ) +#define RCC_RD_PERIPHEN_M4_LPTIM1 (RCC_RDEN1_M4LPTIM1EN ) +#define RCC_RD_PERIPHEN_M7_LPTIM1LP (RCC_RDEN1_M7LPTIM1LPEN ) +#define RCC_RD_PERIPHEN_M4_LPTIM1LP (RCC_RDEN1_M4LPTIM1LPEN ) +#define RCC_RD_PERIPHEN_M7_LPTIM2 (RCC_RDEN1_M7LPTIM2EN ) +#define RCC_RD_PERIPHEN_M4_LPTIM2 (RCC_RDEN1_M4LPTIM2EN ) +#define RCC_RD_PERIPHEN_M7_LPTIM2LP (RCC_RDEN1_M7LPTIM2LPEN ) +#define RCC_RD_PERIPHEN_M4_LPTIM2LP (RCC_RDEN1_M4LPTIM2LPEN ) +#define RCC_RD_PERIPHEN_M7_LPTIM3 (RCC_RDEN1_M7LPTIM3EN ) +#define RCC_RD_PERIPHEN_M4_LPTIM3 (RCC_RDEN1_M4LPTIM3EN ) +#define RCC_RD_PERIPHEN_M7_LPTIM3LP (RCC_RDEN1_M7LPTIM3LPEN ) +#define RCC_RD_PERIPHEN_M4_LPTIM3LP (RCC_RDEN1_M4LPTIM3LPEN ) +#define RCC_RD_PERIPHEN_M7_LPTIM4 (RCC_RDEN1_M7LPTIM4EN ) +#define RCC_RD_PERIPHEN_M4_LPTIM4 (RCC_RDEN1_M4LPTIM4EN ) +#define RCC_RD_PERIPHEN_M7_LPTIM4LP (RCC_RDEN1_M7LPTIM4LPEN ) +#define RCC_RD_PERIPHEN_M4_LPTIM4LP (RCC_RDEN1_M4LPTIM4LPEN ) +#define RCC_RD_PERIPHEN_M7_LPTIM5 (RCC_RDEN1_M7LPTIM5EN ) +#define RCC_RD_PERIPHEN_M4_LPTIM5 (RCC_RDEN1_M4LPTIM5EN ) +#define RCC_RD_PERIPHEN_M7_LPTIM5LP (RCC_RDEN1_M7LPTIM5LPEN ) +#define RCC_RD_PERIPHEN_M4_LPTIM5LP (RCC_RDEN1_M4LPTIM5LPEN ) +#define RCC_RD_PERIPHEN_M7_LPUART1 (RCC_RDEN1_M7LPUART1EN ) +#define RCC_RD_PERIPHEN_M4_LPUART1 (RCC_RDEN1_M4LPUART1EN ) +#define RCC_RD_PERIPHEN_M7_LPUART1LP (RCC_RDEN1_M7LPUART1LPEN) +#define RCC_RD_PERIPHEN_M4_LPUART1LP (RCC_RDEN1_M4LPUART1LPEN) +#define RCC_RD_PERIPHEN_M7_LPUART2 (RCC_RDEN1_M7LPUART2EN ) +#define RCC_RD_PERIPHEN_M4_LPUART2 (RCC_RDEN1_M4LPUART2EN ) +#define RCC_RD_PERIPHEN_M7_LPUART2LP (RCC_RDEN1_M7LPUART2LPEN) +#define RCC_RD_PERIPHEN_M4_LPUART2LP (RCC_RDEN1_M4LPUART2LPEN) + +#define RCC_RD_PERIPHEN_M7_COMP (RCC_RDEN2_M7COMPEN ) +#define RCC_RD_PERIPHEN_M4_COMP (RCC_RDEN2_M4COMPEN ) +#define RCC_RD_PERIPHEN_M7_COMPLP (RCC_RDEN2_M7COMPLPEN ) +#define RCC_RD_PERIPHEN_M4_COMPLP (RCC_RDEN2_M4COMPLPEN ) +/** AXI peripherals enable **/ +#define RCC_AXI_PERIPHEN_M7_JPEGD (RCC_AXIEN1_M7JPEGDEN ) +#define RCC_AXI_PERIPHEN_M4_JPEGD (RCC_AXIEN1_M4JPEGDEN ) +#define RCC_AXI_PERIPHEN_M7_JPEGDLP (RCC_AXIEN1_M7JPEGDLPEN ) +#define RCC_AXI_PERIPHEN_M4_JPEGDLP (RCC_AXIEN1_M4JPEGDLPEN ) +#define RCC_AXI_PERIPHEN_M7_JPEGE (RCC_AXIEN1_M7JPEGEEN ) +#define RCC_AXI_PERIPHEN_M4_JPEGE (RCC_AXIEN1_M4JPEGEEN ) +#define RCC_AXI_PERIPHEN_M7_JPEGELP (RCC_AXIEN1_M7JPEGELPEN ) +#define RCC_AXI_PERIPHEN_M4_JPEGELP (RCC_AXIEN1_M4JPEGELPEN ) +#define RCC_AXI_PERIPHEN_M7_DMAMUX2 (RCC_AXIEN1_M7DMAMUX2EN ) +#define RCC_AXI_PERIPHEN_M4_DMAMUX2 (RCC_AXIEN1_M4DMAMUX2EN ) +#define RCC_AXI_PERIPHEN_M7_DMAMUX2LP (RCC_AXIEN1_M7DMAMUX2LPEN) +#define RCC_AXI_PERIPHEN_M4_DMAMUX2LP (RCC_AXIEN1_M4DMAMUX2LPEN) +#define RCC_AXI_PERIPHEN_M7_MDMA (RCC_AXIEN1_M7MDMAEN ) +#define RCC_AXI_PERIPHEN_M4_MDMA (RCC_AXIEN1_M4MDMAEN ) +#define RCC_AXI_PERIPHEN_M7_MDMALP (RCC_AXIEN1_M7MDMALPEN ) +#define RCC_AXI_PERIPHEN_M4_MDMALP (RCC_AXIEN1_M4MDMALPEN ) +#define RCC_AXI_PERIPHEN_M7_SDMMC1 (RCC_AXIEN1_M7SDMMC1EN ) +#define RCC_AXI_PERIPHEN_M4_SDMMC1 (RCC_AXIEN1_M4SDMMC1EN ) +#define RCC_AXI_PERIPHEN_M7_SDMMC1LP (RCC_AXIEN1_M7SDMMC1LPEN ) +#define RCC_AXI_PERIPHEN_M4_SDMMC1LP (RCC_AXIEN1_M4SDMMC1LPEN ) +#define RCC_AXI_PERIPHEN_M7_ECCM1 (RCC_AXIEN1_M7ECCM1EN ) +#define RCC_AXI_PERIPHEN_M4_ECCM1 (RCC_AXIEN1_M4ECCM1EN ) +#define RCC_AXI_PERIPHEN_M7_ECCM1LP (RCC_AXIEN1_M7ECCM1LPEN ) +#define RCC_AXI_PERIPHEN_M4_ECCM1LP (RCC_AXIEN1_M4ECCM1LPEN ) +#define RCC_AXI_PERIPHEN_M7_OTPC (RCC_AXIEN1_M7OTPCEN ) +#define RCC_AXI_PERIPHEN_M4_OTPC (RCC_AXIEN1_M4OTPCEN ) +#define RCC_AXI_PERIPHEN_M7_OTPCLP (RCC_AXIEN1_M7OTPCLPEN ) +#define RCC_AXI_PERIPHEN_M4_OTPCLP (RCC_AXIEN1_M4OTPCLPEN ) + +#define RCC_AXI_PERIPHEN_M7_DSI (RCC_AXIEN2_M7DSIEN ) +#define RCC_AXI_PERIPHEN_M4_DSI (RCC_AXIEN2_M4DSIEN ) +#define RCC_AXI_PERIPHEN_M7_DSILP (RCC_AXIEN2_M7DSILPEN ) +#define RCC_AXI_PERIPHEN_M4_DSILP (RCC_AXIEN2_M4DSILPEN ) +#define RCC_AXI_PERIPHEN_M7_LCDC (RCC_AXIEN2_M7LCDCEN ) +#define RCC_AXI_PERIPHEN_M4_LCDC (RCC_AXIEN2_M4LCDCEN ) +#define RCC_AXI_PERIPHEN_M7_LCDCLP (RCC_AXIEN2_M7LCDCLPEN ) +#define RCC_AXI_PERIPHEN_M4_LCDCLP (RCC_AXIEN2_M4LCDCLPEN ) +#define RCC_AXI_PERIPHEN_M7_LCDCAPB (RCC_AXIEN2_M7LCDCAPBEN ) +#define RCC_AXI_PERIPHEN_M4_LCDCAPB (RCC_AXIEN2_M4LCDCAPBEN ) +#define RCC_AXI_PERIPHEN_M7_LCDCAPBLP (RCC_AXIEN2_M7LCDCAPBLPEN ) +#define RCC_AXI_PERIPHEN_M4_LCDCAPBLP (RCC_AXIEN2_M4LCDCAPBLPEN ) +#define RCC_AXI_PERIPHEN_M7_DVP1 (RCC_AXIEN2_M7DVP1EN ) +#define RCC_AXI_PERIPHEN_M4_DVP1 (RCC_AXIEN2_M4DVP1EN ) +#define RCC_AXI_PERIPHEN_M7_DVP1LP (RCC_AXIEN2_M7DVP1LPEN ) +#define RCC_AXI_PERIPHEN_M4_DVP1LP (RCC_AXIEN2_M4DVP1LPEN ) +#define RCC_AXI_PERIPHEN_M7_DVP1APB (RCC_AXIEN2_M7DVP1APBEN ) +#define RCC_AXI_PERIPHEN_M4_DVP1APB (RCC_AXIEN2_M4DVP1APBEN ) +#define RCC_AXI_PERIPHEN_M7_DVP1APBLP (RCC_AXIEN2_M7DVP1APBLPEN) +#define RCC_AXI_PERIPHEN_M4_DVP1APBLP (RCC_AXIEN2_M4DVP1APBLPEN) +#define RCC_AXI_PERIPHEN_M7_DVP2 (RCC_AXIEN2_M7DVP2EN ) +#define RCC_AXI_PERIPHEN_M4_DVP2 (RCC_AXIEN2_M4DVP2EN ) +#define RCC_AXI_PERIPHEN_M7_DVP2LP (RCC_AXIEN2_M7DVP2LPEN ) +#define RCC_AXI_PERIPHEN_M4_DVP2LP (RCC_AXIEN2_M4DVP2LPEN ) +#define RCC_AXI_PERIPHEN_M7_DVP2APB (RCC_AXIEN2_M7DVP2APBEN ) +#define RCC_AXI_PERIPHEN_M4_DVP2APB (RCC_AXIEN2_M4DVP2APBEN ) +#define RCC_AXI_PERIPHEN_M7_DVP2APBLP (RCC_AXIEN2_M7DVP2APBLPEN) +#define RCC_AXI_PERIPHEN_M4_DVP2APBLP (RCC_AXIEN2_M4DVP2APBLPEN) +#define RCC_AXI_PERIPHEN_M7_WWDG1 (RCC_AXIEN2_M7WWDG1EN ) +#define RCC_AXI_PERIPHEN_M4_WWDG1 (RCC_AXIEN2_M4WWDG1EN ) +#define RCC_AXI_PERIPHEN_M7_WWDG1LP (RCC_AXIEN2_M7WWDG1LPEN ) +#define RCC_AXI_PERIPHEN_M4_WWDG1LP (RCC_AXIEN2_M4WWDG1LPEN ) + +#define RCC_AXI_PERIPHEN_M7_TASRAM2 (RCC_AXIEN3_M7TASRAM2EN ) +#define RCC_AXI_PERIPHEN_M4_TASRAM2 (RCC_AXIEN3_M4TASRAM2EN ) +#define RCC_AXI_PERIPHEN_M7_TASRAM2LP (RCC_AXIEN3_M7TASRAM2LPEN) +#define RCC_AXI_PERIPHEN_M4_TASRAM2LP (RCC_AXIEN3_M4TASRAM2LPEN) +#define RCC_AXI_PERIPHEN_M7_TASRAM3 (RCC_AXIEN3_M7TASRAM3EN ) +#define RCC_AXI_PERIPHEN_M4_TASRAM3 (RCC_AXIEN3_M4TASRAM3EN ) +#define RCC_AXI_PERIPHEN_M7_TASRAM3LP (RCC_AXIEN3_M7TASRAM3LPEN) +#define RCC_AXI_PERIPHEN_M4_TASRAM3LP (RCC_AXIEN3_M4TASRAM3LPEN) +#define RCC_AXI_PERIPHEN_M7_TCM (RCC_AXIEN3_M7TCMEN ) +#define RCC_AXI_PERIPHEN_M4_TCM (RCC_AXIEN3_M4TCMEN ) +#define RCC_AXI_PERIPHEN_M7_TCMLP (RCC_AXIEN3_M7TCMLPEN ) +#define RCC_AXI_PERIPHEN_M4_TCMLP (RCC_AXIEN3_M4TCMLPEN ) +#define RCC_AXI_PERIPHEN_M7_TCMAXI (RCC_AXIEN3_M7TCMAXIEN ) +#define RCC_AXI_PERIPHEN_M4_TCMAXI (RCC_AXIEN3_M4TCMAXIEN ) +#define RCC_AXI_PERIPHEN_M7_TCMAXILP (RCC_AXIEN3_M7TCMAXILPEN ) +#define RCC_AXI_PERIPHEN_M4_TCMAXILP (RCC_AXIEN3_M4TCMAXILPEN ) +#define RCC_AXI_PERIPHEN_M7_TCMAPB (RCC_AXIEN3_M7TCMAPBEN ) +#define RCC_AXI_PERIPHEN_M4_TCMAPB (RCC_AXIEN3_M4TCMAPBEN ) +#define RCC_AXI_PERIPHEN_M7_TCMAPBLP (RCC_AXIEN3_M7TCMAPBLPEN ) +#define RCC_AXI_PERIPHEN_M4_TCMAPBLP (RCC_AXIEN3_M4TCMAPBLPEN ) +#define RCC_AXI_PERIPHEN_M7_ASRAM1 (RCC_AXIEN3_M7ASRAM1EN ) +#define RCC_AXI_PERIPHEN_M4_ASRAM1 (RCC_AXIEN3_M4ASRAM1EN ) +#define RCC_AXI_PERIPHEN_M7_ASRAM1LP (RCC_AXIEN3_M7ASRAM1LPEN ) +#define RCC_AXI_PERIPHEN_M4_ASRAM1LP (RCC_AXIEN3_M4ASRAM1LPEN ) +#define RCC_AXI_PERIPHEN_M7_AXIROM (RCC_AXIEN3_M7AXIROMEN ) +#define RCC_AXI_PERIPHEN_M4_AXIROM (RCC_AXIEN3_M4AXIROMEN ) +#define RCC_AXI_PERIPHEN_M7_AXIROMLP (RCC_AXIEN3_M7AXIROMLPEN ) +#define RCC_AXI_PERIPHEN_M4_AXIROMLP (RCC_AXIEN3_M4AXIROMLPEN ) +#define RCC_AXI_PERIPHEN_M7_GPU (RCC_AXIEN3_M7GPUEN ) +#define RCC_AXI_PERIPHEN_M4_GPU (RCC_AXIEN3_M4GPUEN ) +#define RCC_AXI_PERIPHEN_M7_GPULP (RCC_AXIEN3_M7GPULPEN ) +#define RCC_AXI_PERIPHEN_M4_GPULP (RCC_AXIEN3_M4GPULPEN ) + +#define RCC_AXI_PERIPHEN_M7_XSPI1 (RCC_AXIEN4_M7XSPI1EN ) +#define RCC_AXI_PERIPHEN_M4_XSPI1 (RCC_AXIEN4_M4XSPI1EN ) +#define RCC_AXI_PERIPHEN_M7_XSPI1LP (RCC_AXIEN4_M7XSPI1LPEN ) +#define RCC_AXI_PERIPHEN_M4_XSPI1LP (RCC_AXIEN4_M4XSPI1LPEN ) +#define RCC_AXI_PERIPHEN_M7_XSPI2 (RCC_AXIEN4_M7XSPI2EN ) +#define RCC_AXI_PERIPHEN_M4_XSPI2 (RCC_AXIEN4_M4XSPI2EN ) +#define RCC_AXI_PERIPHEN_M7_XSPI2LP (RCC_AXIEN4_M7XSPI2LPEN ) +#define RCC_AXI_PERIPHEN_M4_XSPI2LP (RCC_AXIEN4_M4XSPI2LPEN ) +#define RCC_AXI_PERIPHEN_M7_FEMC (RCC_AXIEN4_M7FEMCEN ) +#define RCC_AXI_PERIPHEN_M4_FEMC (RCC_AXIEN4_M4FEMCEN ) +#define RCC_AXI_PERIPHEN_M7_FEMCLP (RCC_AXIEN4_M7FEMCLPEN ) +#define RCC_AXI_PERIPHEN_M4_FEMCLP (RCC_AXIEN4_M4FEMCLPEN ) +#define RCC_AXI_PERIPHEN_M7_SDRAM (RCC_AXIEN4_M7SDRAMEN ) +#define RCC_AXI_PERIPHEN_M4_SDRAM (RCC_AXIEN4_M4SDRAMEN ) +#define RCC_AXI_PERIPHEN_M7_SDRAMLP (RCC_AXIEN4_M7SDRAMLPEN ) +#define RCC_AXI_PERIPHEN_M4_SDRAMLP (RCC_AXIEN4_M4SDRAMLPEN ) +#define RCC_AXI_PERIPHEN_M7_DSIULPS (RCC_AXIEN4_M7DSIULPSEN ) +#define RCC_AXI_PERIPHEN_M4_DSIULPS (RCC_AXIEN4_M4DSIULPSEN ) +#define RCC_AXI_PERIPHEN_M7_DSIULPSLP (RCC_AXIEN4_M7DSIULPSLPEN) +#define RCC_AXI_PERIPHEN_M4_DSIULPSLP (RCC_AXIEN4_M4DSIULPSLPEN) + +/** CFG2 register peripherals enable **/ +#define RCC_CFG2_PERIPHEN_M4_CAHI (RCC_CFG2_M4CAHIEN ) +#define RCC_CFG2_PERIPHEN_M4_CAHIPCLK (RCC_CFG2_M4CAHIPCLKEN ) +#define RCC_CFG2_PERIPHEN_M4_CAHD (RCC_CFG2_M4CAHDEN ) +#define RCC_CFG2_PERIPHEN_M4_CAHDPCLK (RCC_CFG2_M4CAHDPCLKEN ) +#define RCC_CFG2_PERIPHEN_M7_MMU (RCC_CFG2_M7MMUEN ) +#define RCC_CFG2_PERIPHEN_M7_MMULP (RCC_CFG2_M7MMULPEN ) +#define RCC_CFG2_PERIPHEN_M4_MMU (RCC_CFG2_M4MMUEN ) +#define RCC_CFG2_PERIPHEN_M4_MMULP (RCC_CFG2_M4MMULPEN ) +#define RCC_CFG2_PERIPHEN_M7_SRAMBKP (RCC_CFG2_M7SRAMBKPEN ) +#define RCC_CFG2_PERIPHEN_M4_SRAMBKP (RCC_CFG2_M4SRAMBKPEN ) +#define RCC_CFG2_PERIPHEN_M7_SRAMBKPLP (RCC_CFG2_M7SRAMBKPLPEN) +#define RCC_CFG2_PERIPHEN_M4_SRAMBKPLP (RCC_CFG2_M4SRAMBKPLPEN) +#define RCC_CFG2_PERIPHEN_M7_SRAM1 (RCC_CFG2_M7SRAM1EN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM1 (RCC_CFG2_M4SRAM1EN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM1LP (RCC_CFG2_M7SRAM1LPEN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM1LP (RCC_CFG2_M4SRAM1LPEN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM2 (RCC_CFG2_M7SRAM2EN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM2 (RCC_CFG2_M4SRAM2EN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM2LP (RCC_CFG2_M7SRAM2LPEN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM2LP (RCC_CFG2_M4SRAM2LPEN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM3 (RCC_CFG2_M7SRAM3EN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM3 (RCC_CFG2_M4SRAM3EN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM3LP (RCC_CFG2_M7SRAM3LPEN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM3LP (RCC_CFG2_M4SRAM3LPEN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM4 (RCC_CFG2_M7SRAM4EN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM4 (RCC_CFG2_M4SRAM4EN ) +#define RCC_CFG2_PERIPHEN_M7_SRAM4LP (RCC_CFG2_M7SRAM4LPEN ) +#define RCC_CFG2_PERIPHEN_M4_SRAM4LP (RCC_CFG2_M4SRAM4LPEN ) + +/** CFG4 register peripherals enable **/ +#define RCC_CFG4_PERIPHEN_AHB1BUS (RCC_CFG4_AHB1CLKEN ) +#define RCC_CFG4_PERIPHEN_AHB2BUS (RCC_CFG4_AHB2CLKEN ) +#define RCC_CFG4_PERIPHEN_AHB5BUS (RCC_CFG4_AHB5CLKEN ) +#define RCC_CFG4_PERIPHEN_AHB6BUS (RCC_CFG4_AHB6CLKEN ) +#define RCC_CFG4_PERIPHEN_AXIBUS (RCC_CFG4_AXICLKEN ) +#define RCC_CFG4_PERIPHEN_APB1BUS (RCC_CFG4_APB1CLKEN ) +#define RCC_CFG4_PERIPHEN_APB2BUS (RCC_CFG4_APB2CLKEN ) +#define RCC_CFG4_PERIPHEN_APB5BUS (RCC_CFG4_APB5CLKEN ) +#define RCC_CFG4_PERIPHEN_APB6BUS (RCC_CFG4_APB6CLKEN ) +#define RCC_CFG4_PERIPHEN_AHB9BUS (RCC_CFG4_AHB9CLKEN ) +#define RCC_CFG4_PERIPHEN_M7AXIMATRIX_GPV (RCC_CFG4_AXIMM7GCLKEN) +#define RCC_CFG4_PERIPHEN_M4AXIMATRIX_GPV (RCC_CFG4_AXIMM4GCLKEN) +#define RCC_CFG4_PERIPHEN_HSICG (RCC_CFG4_HSICGEN ) +#define RCC_CFG4_PERIPHEN_HSIKERCG (RCC_CFG4_HSIKERCGEN ) +#define RCC_CFG4_PERIPHEN_HSECG (RCC_CFG4_HSECGEN ) +#define RCC_CFG4_PERIPHEN_HSEKERCG (RCC_CFG4_HSEKERCGEN ) +#define RCC_CFG4_PERIPHEN_MSICG (RCC_CFG4_MSICGEN ) +#define RCC_CFG4_PERIPHEN_MSIKERCG (RCC_CFG4_MSIKERCGEN ) +#define RCC_CFG4_PERIPHEN_M7AXIMATRIX (RCC_CFG4_AXIMM7CLKEN ) +#define RCC_CFG4_PERIPHEN_AXIGGPV (RCC_CFG4_AXIGCLKEN ) +#define RCC_CFG4_PERIPHEN_M4AXIMATRIX (RCC_CFG4_AXIMM4CLKEN ) +#define RCC_CFG4_PERIPHEN_M7DCMUCLK (RCC_CFG4_DCMUM7CLKEN ) +#define RCC_CFG4_PERIPHEN_M4DCMUCLK (RCC_CFG4_DCMUM4CLKEN ) +#define RCC_CFG4_PERIPHEN_AHBMATRIX1 (RCC_CFG4_AHBM1CLKEN ) +#define RCC_CFG4_PERIPHEN_AHBMATRIX2 (RCC_CFG4_AHBM2CLKEN ) +#define RCC_CFG4_PERIPHEN_AHBMATRIX3 (RCC_CFG4_AHBM3CLKEN ) + +/** CFG5 register peripherals enable **/ +#define RCC_CFG5_PERIPHEN_M7_SRAM5 (RCC_CFG5_M7SRAM5EN ) +#define RCC_CFG5_PERIPHEN_M4_SRAM5 (RCC_CFG5_M4SRAM5EN ) +#define RCC_CFG5_PERIPHEN_M7_SRAM5LP (RCC_CFG5_M7SRAM5LPEN ) +#define RCC_CFG5_PERIPHEN_M4_SRAM5LP (RCC_CFG5_M4SRAM5LPEN ) + + +/** HSE_configuration **/ +#define RCC_HSE_DISABLE (RCC_REG_BIT_MASK) +#define RCC_HSE_ENABLE (RCC_SRCCTRL1_HSEEN) +#define RCC_HSE_BYPASS (RCC_SRCCTRL1_HSEBP) +#define RCC_HSE_RDCNTEN (RCC_SRCCTRL1_HSERDCNTEN) +#define RCC_HSE_STABLE_FLAG (RCC_SRCCTRL1_HSERDF) + +/** LSI_configuration **/ +#define RCC_LSI_ENABLE (RCC_BDCTRL_LSIEN) +#define RCC_LSIRDY_ENABLE (RCC_BDCTRL_LSIRDEN) +#define RCC_LSI_STABLE_FLAG (RCC_BDCTRL_LSIRDF|RCC_BDCTRL_AFELSIRDF) + +#define RCC_SECLSI_ENABLE (RCC_BDCTRL_LSISECEN) +#define RCC_SECLSI_STABLE_FLAG (RCC_BDCTRL_LSISECRDF) + +/** HSI_configuration **/ +#define RCC_HSI_ENABLE (RCC_SRCCTRL1_HSIEN) +#define RCC_HSI_STABLE_FLAG (RCC_SRCCTRL1_HSIRDF|RCC_SRCCTRL1_AFEHSIRDF) + +/** MSI_configuration **/ +#define RCC_MSI_ENABLE (RCC_SRCCTRL1_MSIEN) +#define RCC_MSI_STABLE_FLAG (RCC_SRCCTRL1_MSIRDF|RCC_SRCCTRL1_AFEMSIRDF) + +/** System_clock_status mask **/ +#define RCC_SYSCLK_STS_MASK (RCC_SRCCTRL1_SCLKSTS) +#define RCC_SYSCLK_STS_HSI (RCC_SRCCTRL1_SCLKSTS_HSI ) +#define RCC_SYSCLK_STS_MSI (RCC_SRCCTRL1_SCLKSTS_MSI ) +#define RCC_SYSCLK_STS_HSE (RCC_SRCCTRL1_SCLKSTS_HSE ) +#define RCC_SYSCLK_STS_PLL1A (RCC_SRCCTRL1_SCLKSTS_PLL1) + +#define RCC_SYSCLK_SRC_MASK (~RCC_SRCCTRL1_SCLKSW ) +#define RCC_SYSCLK_SRC_HSI (RCC_SRCCTRL1_SCLKSW_HSI ) +#define RCC_SYSCLK_SRC_MSI (RCC_SRCCTRL1_SCLKSW_MSI ) +#define RCC_SYSCLK_SRC_HSE (RCC_SRCCTRL1_SCLKSW_HSE ) +#define RCC_SYSCLK_SRC_PLL1A (RCC_SRCCTRL1_SCLKSW_PLL1) + + +/** LSE_configuration **/ +#define RCC_LSE_DISABLE (RCC_REG_BIT_MASK) +#define RCC_LSE_ENABLE (RCC_BDCTRL_LSEEN) +#define RCC_LSE_BYPASS (RCC_BDCTRL_LSEBP) +#define RCC_LSE_LSELDO (RCC_BDCTRL_LSELDOEN) +#define RCC_LSERDY_ENABLE (RCC_BDCTRL_LSERDEN) +#define RCC_LSE_RDCNTEN (RCC_BDCTRL_LSERDCNTEN) +#define RCC_LSE_STABLE_FLAG (RCC_BDCTRL_LSERDF|RCC_BDCTRL_AFELSERDF) +/** PLL_clock **/ +#define RCC_PLL_BWAJ_MASK (~RCC_PLL1CTRL1_PLL1BWAJ) +#define RCC_PLL_CLKR_CLKF_MASK (RCC_REG_BIT_MASK) +#define RCC_PLL_SRC_MASK (~RCC_PLL1CTRL1_PLL1SRC) +#define RCC_PLL_LOCK_FLAG (RCC_PLL1CTRL1_PLL1PHLK) +#define RCC_PLL_LDO_ENABLE (RCC_PLL1CTRL1_PLL1LDOEN) +#define RCC_PLL_ENABLE (RCC_PLL1CTRL1_PLL1EN ) +#define RCC_PLL_RESET_ENABLE (RCC_PLL1CTRL1_PLL1RST ) +#define RCC_PLL_POWER_DOWN (RCC_PLL1CTRL1_PLL1PD ) + +#define RCC_PLL_SRC_HSI (RCC_REG_BIT_MASK ) +#define RCC_PLL_SRC_MSI (RCC_PLL1CTRL1_PLL1SRC_1 ) +#define RCC_PLL_SRC_HSE (RCC_PLL1CTRL1_PLL1SRC_0|RCC_PLL1CTRL1_PLL1SRC_1 ) + +/** cortex Selection **/ +#define RCC_M7HYPERCLK_SRC_MASK (~RCC_SRCCTRL2_M7HYPSEL ) +#define RCC_M7HYPERCLK_SRC_PLL1A (RCC_REG_BIT_MASK ) +#define RCC_M7HYPERCLK_SRC_PLL2A (RCC_SRCCTRL2_M7HYPSEL ) + +#define RCC_AXIHYPERCLK_SRC_MASK (~RCC_SRCCTRL2_AXIHYPSEL ) +#define RCC_AXIHYPERCLK_SRC_PLL1A (RCC_REG_BIT_MASK ) +#define RCC_AXIHYPERCLK_SRC_PLL2A (RCC_SRCCTRL2_AXIHYPSEL ) + +/** PLL1C,PLL2C,PLL3C DIV values **/ +#define RCC_PLLC_DIV_MASK (~RCC_PLL1DIV_PLL1CDIV ) +#define RCC_PLLC_DIV1 (RCC_PLL1DIV_PLL1CDIV_DIV1 ) +#define RCC_PLLC_DIV2 (RCC_PLL1DIV_PLL1CDIV_DIV2 ) +#define RCC_PLLC_DIV3 (RCC_PLL1DIV_PLL1CDIV_DIV3 ) +#define RCC_PLLC_DIV4 (RCC_PLL1DIV_PLL1CDIV_DIV4 ) +#define RCC_PLLC_DIV5 (RCC_PLL1DIV_PLL1CDIV_DIV5 ) +#define RCC_PLLC_DIV6 (RCC_PLL1DIV_PLL1CDIV_DIV6 ) +#define RCC_PLLC_DIV7 (RCC_PLL1DIV_PLL1CDIV_DIV7 ) +#define RCC_PLLC_DIV8 (RCC_PLL1DIV_PLL1CDIV_DIV8 ) +#define RCC_PLLC_DIV9 (RCC_PLL1DIV_PLL1CDIV_DIV9 ) +#define RCC_PLLC_DIV10 (RCC_PLL1DIV_PLL1CDIV_DIV10) +#define RCC_PLLC_DIV11 (RCC_PLL1DIV_PLL1CDIV_DIV11) +#define RCC_PLLC_DIV12 (RCC_PLL1DIV_PLL1CDIV_DIV12) +#define RCC_PLLC_DIV13 (RCC_PLL1DIV_PLL1CDIV_DIV13) +#define RCC_PLLC_DIV14 (RCC_PLL1DIV_PLL1CDIV_DIV14) +#define RCC_PLLC_DIV15 (RCC_PLL1DIV_PLL1CDIV_DIV15) +#define RCC_PLLC_DIV16 (RCC_PLL1DIV_PLL1CDIV_DIV16) +#define RCC_PLLC_DIV17 (RCC_PLL1DIV_PLL1CDIV_DIV17) +#define RCC_PLLC_DIV18 (RCC_PLL1DIV_PLL1CDIV_DIV18) +#define RCC_PLLC_DIV19 (RCC_PLL1DIV_PLL1CDIV_DIV19) +#define RCC_PLLC_DIV20 (RCC_PLL1DIV_PLL1CDIV_DIV20) +#define RCC_PLLC_DIV21 (RCC_PLL1DIV_PLL1CDIV_DIV21) +#define RCC_PLLC_DIV22 (RCC_PLL1DIV_PLL1CDIV_DIV22) +#define RCC_PLLC_DIV23 (RCC_PLL1DIV_PLL1CDIV_DIV23) +#define RCC_PLLC_DIV24 (RCC_PLL1DIV_PLL1CDIV_DIV24) +#define RCC_PLLC_DIV25 (RCC_PLL1DIV_PLL1CDIV_DIV25) +#define RCC_PLLC_DIV26 (RCC_PLL1DIV_PLL1CDIV_DIV26) +#define RCC_PLLC_DIV27 (RCC_PLL1DIV_PLL1CDIV_DIV27) +#define RCC_PLLC_DIV28 (RCC_PLL1DIV_PLL1CDIV_DIV28) +#define RCC_PLLC_DIV29 (RCC_PLL1DIV_PLL1CDIV_DIV29) +#define RCC_PLLC_DIV30 (RCC_PLL1DIV_PLL1CDIV_DIV30) +#define RCC_PLLC_DIV31 (RCC_PLL1DIV_PLL1CDIV_DIV31) +#define RCC_PLLC_DIV32 (RCC_PLL1DIV_PLL1CDIV_DIV32) +#define RCC_PLLC_DIV33 (RCC_PLL1DIV_PLL1CDIV_DIV33) +#define RCC_PLLC_DIV34 (RCC_PLL1DIV_PLL1CDIV_DIV34) +#define RCC_PLLC_DIV35 (RCC_PLL1DIV_PLL1CDIV_DIV35) +#define RCC_PLLC_DIV36 (RCC_PLL1DIV_PLL1CDIV_DIV36) +#define RCC_PLLC_DIV37 (RCC_PLL1DIV_PLL1CDIV_DIV37) +#define RCC_PLLC_DIV38 (RCC_PLL1DIV_PLL1CDIV_DIV38) +#define RCC_PLLC_DIV39 (RCC_PLL1DIV_PLL1CDIV_DIV39) +#define RCC_PLLC_DIV40 (RCC_PLL1DIV_PLL1CDIV_DIV40) +#define RCC_PLLC_DIV41 (RCC_PLL1DIV_PLL1CDIV_DIV41) +#define RCC_PLLC_DIV42 (RCC_PLL1DIV_PLL1CDIV_DIV42) +#define RCC_PLLC_DIV43 (RCC_PLL1DIV_PLL1CDIV_DIV43) +#define RCC_PLLC_DIV44 (RCC_PLL1DIV_PLL1CDIV_DIV44) +#define RCC_PLLC_DIV45 (RCC_PLL1DIV_PLL1CDIV_DIV45) +#define RCC_PLLC_DIV46 (RCC_PLL1DIV_PLL1CDIV_DIV46) +#define RCC_PLLC_DIV47 (RCC_PLL1DIV_PLL1CDIV_DIV47) +#define RCC_PLLC_DIV48 (RCC_PLL1DIV_PLL1CDIV_DIV48) +#define RCC_PLLC_DIV49 (RCC_PLL1DIV_PLL1CDIV_DIV49) +#define RCC_PLLC_DIV50 (RCC_PLL1DIV_PLL1CDIV_DIV50) +#define RCC_PLLC_DIV51 (RCC_PLL1DIV_PLL1CDIV_DIV51) +#define RCC_PLLC_DIV52 (RCC_PLL1DIV_PLL1CDIV_DIV52) +#define RCC_PLLC_DIV53 (RCC_PLL1DIV_PLL1CDIV_DIV53) +#define RCC_PLLC_DIV54 (RCC_PLL1DIV_PLL1CDIV_DIV54) +#define RCC_PLLC_DIV55 (RCC_PLL1DIV_PLL1CDIV_DIV55) +#define RCC_PLLC_DIV56 (RCC_PLL1DIV_PLL1CDIV_DIV56) +#define RCC_PLLC_DIV57 (RCC_PLL1DIV_PLL1CDIV_DIV57) +#define RCC_PLLC_DIV58 (RCC_PLL1DIV_PLL1CDIV_DIV58) +#define RCC_PLLC_DIV59 (RCC_PLL1DIV_PLL1CDIV_DIV59) +#define RCC_PLLC_DIV60 (RCC_PLL1DIV_PLL1CDIV_DIV60) +#define RCC_PLLC_DIV61 (RCC_PLL1DIV_PLL1CDIV_DIV61) +#define RCC_PLLC_DIV62 (RCC_PLL1DIV_PLL1CDIV_DIV62) +#define RCC_PLLC_DIV63 (RCC_PLL1DIV_PLL1CDIV_DIV63) + +/** PLL1B,PLL2B,PLL3B DIV values **/ +#define RCC_PLLB_DIV_MASK (~RCC_PLL1DIV_PLL1BDIV ) +#define RCC_PLLB_DIV1 (RCC_PLL1DIV_PLL1BDIV_DIV1 ) +#define RCC_PLLB_DIV2 (RCC_PLL1DIV_PLL1BDIV_DIV2 ) +#define RCC_PLLB_DIV3 (RCC_PLL1DIV_PLL1BDIV_DIV3 ) +#define RCC_PLLB_DIV4 (RCC_PLL1DIV_PLL1BDIV_DIV4 ) +#define RCC_PLLB_DIV5 (RCC_PLL1DIV_PLL1BDIV_DIV5 ) +#define RCC_PLLB_DIV6 (RCC_PLL1DIV_PLL1BDIV_DIV6 ) +#define RCC_PLLB_DIV7 (RCC_PLL1DIV_PLL1BDIV_DIV7 ) +#define RCC_PLLB_DIV8 (RCC_PLL1DIV_PLL1BDIV_DIV8 ) +#define RCC_PLLB_DIV9 (RCC_PLL1DIV_PLL1BDIV_DIV9 ) +#define RCC_PLLB_DIV10 (RCC_PLL1DIV_PLL1BDIV_DIV10) +#define RCC_PLLB_DIV11 (RCC_PLL1DIV_PLL1BDIV_DIV11) +#define RCC_PLLB_DIV12 (RCC_PLL1DIV_PLL1BDIV_DIV12) +#define RCC_PLLB_DIV13 (RCC_PLL1DIV_PLL1BDIV_DIV13) +#define RCC_PLLB_DIV14 (RCC_PLL1DIV_PLL1BDIV_DIV14) +#define RCC_PLLB_DIV15 (RCC_PLL1DIV_PLL1BDIV_DIV15) +#define RCC_PLLB_DIV16 (RCC_PLL1DIV_PLL1BDIV_DIV16) +#define RCC_PLLB_DIV17 (RCC_PLL1DIV_PLL1BDIV_DIV17) +#define RCC_PLLB_DIV18 (RCC_PLL1DIV_PLL1BDIV_DIV18) +#define RCC_PLLB_DIV19 (RCC_PLL1DIV_PLL1BDIV_DIV19) +#define RCC_PLLB_DIV20 (RCC_PLL1DIV_PLL1BDIV_DIV20) +#define RCC_PLLB_DIV21 (RCC_PLL1DIV_PLL1BDIV_DIV21) +#define RCC_PLLB_DIV22 (RCC_PLL1DIV_PLL1BDIV_DIV22) +#define RCC_PLLB_DIV23 (RCC_PLL1DIV_PLL1BDIV_DIV23) +#define RCC_PLLB_DIV24 (RCC_PLL1DIV_PLL1BDIV_DIV24) +#define RCC_PLLB_DIV25 (RCC_PLL1DIV_PLL1BDIV_DIV25) +#define RCC_PLLB_DIV26 (RCC_PLL1DIV_PLL1BDIV_DIV26) +#define RCC_PLLB_DIV27 (RCC_PLL1DIV_PLL1BDIV_DIV27) +#define RCC_PLLB_DIV28 (RCC_PLL1DIV_PLL1BDIV_DIV28) +#define RCC_PLLB_DIV29 (RCC_PLL1DIV_PLL1BDIV_DIV29) +#define RCC_PLLB_DIV30 (RCC_PLL1DIV_PLL1BDIV_DIV30) +#define RCC_PLLB_DIV31 (RCC_PLL1DIV_PLL1BDIV_DIV31) +#define RCC_PLLB_DIV32 (RCC_PLL1DIV_PLL1BDIV_DIV32) +#define RCC_PLLB_DIV33 (RCC_PLL1DIV_PLL1BDIV_DIV33) +#define RCC_PLLB_DIV34 (RCC_PLL1DIV_PLL1BDIV_DIV34) +#define RCC_PLLB_DIV35 (RCC_PLL1DIV_PLL1BDIV_DIV35) +#define RCC_PLLB_DIV36 (RCC_PLL1DIV_PLL1BDIV_DIV36) +#define RCC_PLLB_DIV37 (RCC_PLL1DIV_PLL1BDIV_DIV37) +#define RCC_PLLB_DIV38 (RCC_PLL1DIV_PLL1BDIV_DIV38) +#define RCC_PLLB_DIV39 (RCC_PLL1DIV_PLL1BDIV_DIV39) +#define RCC_PLLB_DIV40 (RCC_PLL1DIV_PLL1BDIV_DIV40) +#define RCC_PLLB_DIV41 (RCC_PLL1DIV_PLL1BDIV_DIV41) +#define RCC_PLLB_DIV42 (RCC_PLL1DIV_PLL1BDIV_DIV42) +#define RCC_PLLB_DIV43 (RCC_PLL1DIV_PLL1BDIV_DIV43) +#define RCC_PLLB_DIV44 (RCC_PLL1DIV_PLL1BDIV_DIV44) +#define RCC_PLLB_DIV45 (RCC_PLL1DIV_PLL1BDIV_DIV45) +#define RCC_PLLB_DIV46 (RCC_PLL1DIV_PLL1BDIV_DIV46) +#define RCC_PLLB_DIV47 (RCC_PLL1DIV_PLL1BDIV_DIV47) +#define RCC_PLLB_DIV48 (RCC_PLL1DIV_PLL1BDIV_DIV48) +#define RCC_PLLB_DIV49 (RCC_PLL1DIV_PLL1BDIV_DIV49) +#define RCC_PLLB_DIV50 (RCC_PLL1DIV_PLL1BDIV_DIV50) +#define RCC_PLLB_DIV51 (RCC_PLL1DIV_PLL1BDIV_DIV51) +#define RCC_PLLB_DIV52 (RCC_PLL1DIV_PLL1BDIV_DIV52) +#define RCC_PLLB_DIV53 (RCC_PLL1DIV_PLL1BDIV_DIV53) +#define RCC_PLLB_DIV54 (RCC_PLL1DIV_PLL1BDIV_DIV54) +#define RCC_PLLB_DIV55 (RCC_PLL1DIV_PLL1BDIV_DIV55) +#define RCC_PLLB_DIV56 (RCC_PLL1DIV_PLL1BDIV_DIV56) +#define RCC_PLLB_DIV57 (RCC_PLL1DIV_PLL1BDIV_DIV57) +#define RCC_PLLB_DIV58 (RCC_PLL1DIV_PLL1BDIV_DIV58) +#define RCC_PLLB_DIV59 (RCC_PLL1DIV_PLL1BDIV_DIV59) +#define RCC_PLLB_DIV60 (RCC_PLL1DIV_PLL1BDIV_DIV60) +#define RCC_PLLB_DIV61 (RCC_PLL1DIV_PLL1BDIV_DIV61) +#define RCC_PLLB_DIV62 (RCC_PLL1DIV_PLL1BDIV_DIV62) +#define RCC_PLLB_DIV63 (RCC_PLL1DIV_PLL1BDIV_DIV63) + +/** PLL1A,PLL2A,PLL3A DIV values **/ +#define RCC_PLLA_DIV_MASK (~RCC_PLL1DIV_PLL1ADIV ) +#define RCC_PLLA_DIV1 (RCC_PLL1DIV_PLL1ADIV_DIV1 ) +#define RCC_PLLA_DIV2 (RCC_PLL1DIV_PLL1ADIV_DIV2 ) +#define RCC_PLLA_DIV3 (RCC_PLL1DIV_PLL1ADIV_DIV3 ) +#define RCC_PLLA_DIV4 (RCC_PLL1DIV_PLL1ADIV_DIV4 ) +#define RCC_PLLA_DIV5 (RCC_PLL1DIV_PLL1ADIV_DIV5 ) +#define RCC_PLLA_DIV6 (RCC_PLL1DIV_PLL1ADIV_DIV6 ) +#define RCC_PLLA_DIV7 (RCC_PLL1DIV_PLL1ADIV_DIV7 ) +#define RCC_PLLA_DIV8 (RCC_PLL1DIV_PLL1ADIV_DIV8 ) +#define RCC_PLLA_DIV9 (RCC_PLL1DIV_PLL1ADIV_DIV9 ) +#define RCC_PLLA_DIV10 (RCC_PLL1DIV_PLL1ADIV_DIV10) +#define RCC_PLLA_DIV11 (RCC_PLL1DIV_PLL1ADIV_DIV11) +#define RCC_PLLA_DIV12 (RCC_PLL1DIV_PLL1ADIV_DIV12) +#define RCC_PLLA_DIV13 (RCC_PLL1DIV_PLL1ADIV_DIV13) +#define RCC_PLLA_DIV14 (RCC_PLL1DIV_PLL1ADIV_DIV14) +#define RCC_PLLA_DIV15 (RCC_PLL1DIV_PLL1ADIV_DIV15) +#define RCC_PLLA_DIV16 (RCC_PLL1DIV_PLL1ADIV_DIV16) +#define RCC_PLLA_DIV17 (RCC_PLL1DIV_PLL1ADIV_DIV17) +#define RCC_PLLA_DIV18 (RCC_PLL1DIV_PLL1ADIV_DIV18) +#define RCC_PLLA_DIV19 (RCC_PLL1DIV_PLL1ADIV_DIV19) +#define RCC_PLLA_DIV20 (RCC_PLL1DIV_PLL1ADIV_DIV20) +#define RCC_PLLA_DIV21 (RCC_PLL1DIV_PLL1ADIV_DIV21) +#define RCC_PLLA_DIV22 (RCC_PLL1DIV_PLL1ADIV_DIV22) +#define RCC_PLLA_DIV23 (RCC_PLL1DIV_PLL1ADIV_DIV23) +#define RCC_PLLA_DIV24 (RCC_PLL1DIV_PLL1ADIV_DIV24) +#define RCC_PLLA_DIV25 (RCC_PLL1DIV_PLL1ADIV_DIV25) +#define RCC_PLLA_DIV26 (RCC_PLL1DIV_PLL1ADIV_DIV26) +#define RCC_PLLA_DIV27 (RCC_PLL1DIV_PLL1ADIV_DIV27) +#define RCC_PLLA_DIV28 (RCC_PLL1DIV_PLL1ADIV_DIV28) +#define RCC_PLLA_DIV29 (RCC_PLL1DIV_PLL1ADIV_DIV29) +#define RCC_PLLA_DIV30 (RCC_PLL1DIV_PLL1ADIV_DIV30) +#define RCC_PLLA_DIV31 (RCC_PLL1DIV_PLL1ADIV_DIV31) +#define RCC_PLLA_DIV32 (RCC_PLL1DIV_PLL1ADIV_DIV32) +#define RCC_PLLA_DIV33 (RCC_PLL1DIV_PLL1ADIV_DIV33) +#define RCC_PLLA_DIV34 (RCC_PLL1DIV_PLL1ADIV_DIV34) +#define RCC_PLLA_DIV35 (RCC_PLL1DIV_PLL1ADIV_DIV35) +#define RCC_PLLA_DIV36 (RCC_PLL1DIV_PLL1ADIV_DIV36) +#define RCC_PLLA_DIV37 (RCC_PLL1DIV_PLL1ADIV_DIV37) +#define RCC_PLLA_DIV38 (RCC_PLL1DIV_PLL1ADIV_DIV38) +#define RCC_PLLA_DIV39 (RCC_PLL1DIV_PLL1ADIV_DIV39) +#define RCC_PLLA_DIV40 (RCC_PLL1DIV_PLL1ADIV_DIV40) +#define RCC_PLLA_DIV41 (RCC_PLL1DIV_PLL1ADIV_DIV41) +#define RCC_PLLA_DIV42 (RCC_PLL1DIV_PLL1ADIV_DIV42) +#define RCC_PLLA_DIV43 (RCC_PLL1DIV_PLL1ADIV_DIV43) +#define RCC_PLLA_DIV44 (RCC_PLL1DIV_PLL1ADIV_DIV44) +#define RCC_PLLA_DIV45 (RCC_PLL1DIV_PLL1ADIV_DIV45) +#define RCC_PLLA_DIV46 (RCC_PLL1DIV_PLL1ADIV_DIV46) +#define RCC_PLLA_DIV47 (RCC_PLL1DIV_PLL1ADIV_DIV47) +#define RCC_PLLA_DIV48 (RCC_PLL1DIV_PLL1ADIV_DIV48) +#define RCC_PLLA_DIV49 (RCC_PLL1DIV_PLL1ADIV_DIV49) +#define RCC_PLLA_DIV50 (RCC_PLL1DIV_PLL1ADIV_DIV50) +#define RCC_PLLA_DIV51 (RCC_PLL1DIV_PLL1ADIV_DIV51) +#define RCC_PLLA_DIV52 (RCC_PLL1DIV_PLL1ADIV_DIV52) +#define RCC_PLLA_DIV53 (RCC_PLL1DIV_PLL1ADIV_DIV53) +#define RCC_PLLA_DIV54 (RCC_PLL1DIV_PLL1ADIV_DIV54) +#define RCC_PLLA_DIV55 (RCC_PLL1DIV_PLL1ADIV_DIV55) +#define RCC_PLLA_DIV56 (RCC_PLL1DIV_PLL1ADIV_DIV56) +#define RCC_PLLA_DIV57 (RCC_PLL1DIV_PLL1ADIV_DIV57) +#define RCC_PLLA_DIV58 (RCC_PLL1DIV_PLL1ADIV_DIV58) +#define RCC_PLLA_DIV59 (RCC_PLL1DIV_PLL1ADIV_DIV59) +#define RCC_PLLA_DIV60 (RCC_PLL1DIV_PLL1ADIV_DIV60) +#define RCC_PLLA_DIV61 (RCC_PLL1DIV_PLL1ADIV_DIV61) +#define RCC_PLLA_DIV62 (RCC_PLL1DIV_PLL1ADIV_DIV62) +#define RCC_PLLA_DIV63 (RCC_PLL1DIV_PLL1ADIV_DIV63) + +/** HSI DIV values **/ +#define RCC_HSICLK_DIV_MASK (~RCC_SYSBUSDIV1_HSIDIV ) +#define RCC_HSICLK_DIV1 (RCC_SYSBUSDIV1_HSIDIV_DIV1 ) +#define RCC_HSICLK_DIV2 (RCC_SYSBUSDIV1_HSIDIV_DIV2 ) +#define RCC_HSICLK_DIV4 (RCC_SYSBUSDIV1_HSIDIV_DIV4 ) +#define RCC_HSICLK_DIV8 (RCC_SYSBUSDIV1_HSIDIV_DIV8 ) +#define RCC_HSICLK_DIV16 (RCC_SYSBUSDIV1_HSIDIV_DIV16 ) +#define RCC_HSICLK_DIV32 (RCC_SYSBUSDIV1_HSIDIV_DIV32 ) +#define RCC_HSICLK_DIV64 (RCC_SYSBUSDIV1_HSIDIV_DIV64 ) +#define RCC_HSICLK_DIV128 (RCC_SYSBUSDIV1_HSIDIV_DIV128) +#define RCC_HSICLK_DIV256 (RCC_SYSBUSDIV1_HSIDIV_DIV256) +#define RCC_HSICLK_DIV512 (RCC_SYSBUSDIV1_HSIDIV_DIV512) + +/** MSI DIV values **/ +#define RCC_MSICLK_DIV_MASK (~RCC_SYSBUSDIV1_MSIDIV ) +#define RCC_MSICLK_DIV1 (RCC_SYSBUSDIV1_MSIDIV_DIV1 ) +#define RCC_MSICLK_DIV2 (RCC_SYSBUSDIV1_MSIDIV_DIV2 ) +#define RCC_MSICLK_DIV4 (RCC_SYSBUSDIV1_MSIDIV_DIV4 ) +#define RCC_MSICLK_DIV8 (RCC_SYSBUSDIV1_MSIDIV_DIV8 ) +#define RCC_MSICLK_DIV16 (RCC_SYSBUSDIV1_MSIDIV_DIV16 ) +#define RCC_MSICLK_DIV32 (RCC_SYSBUSDIV1_MSIDIV_DIV32 ) +#define RCC_MSICLK_DIV64 (RCC_SYSBUSDIV1_MSIDIV_DIV64 ) +#define RCC_MSICLK_DIV128 (RCC_SYSBUSDIV1_MSIDIV_DIV128) +#define RCC_MSICLK_DIV256 (RCC_SYSBUSDIV1_MSIDIV_DIV256) +#define RCC_MSICLK_DIV512 (RCC_SYSBUSDIV1_MSIDIV_DIV512) + +/** AXI Clock Hyper Mode DIV values **/ +#define RCC_AXICLK_HYP_DIV_MASK (~RCC_SYSBUSDIV1_AXIHYPDIV ) +#define RCC_AXICLK_HYP_DIV1 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV1 ) +#define RCC_AXICLK_HYP_DIV2 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV2 ) +#define RCC_AXICLK_HYP_DIV4 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV4 ) +#define RCC_AXICLK_HYP_DIV8 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV8 ) +#define RCC_AXICLK_HYP_DIV16 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV16 ) +#define RCC_AXICLK_HYP_DIV32 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV32 ) +#define RCC_AXICLK_HYP_DIV64 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV64 ) +#define RCC_AXICLK_HYP_DIV128 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV128) +#define RCC_AXICLK_HYP_DIV256 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV256) +#define RCC_AXICLK_HYP_DIV512 (RCC_SYSBUSDIV1_AXIHYPDIV_DIV512) + +/** M7 Clock Hyper Mode DIV values **/ +#define RCC_M7CLK_HYP_DIV_MASK (~RCC_SYSBUSDIV1_M7HYPDIV ) +#define RCC_M7CLK_HYP_DIV1 (RCC_SYSBUSDIV1_M7HYPDIV_DIV1 ) +#define RCC_M7CLK_HYP_DIV2 (RCC_SYSBUSDIV1_M7HYPDIV_DIV2 ) +#define RCC_M7CLK_HYP_DIV4 (RCC_SYSBUSDIV1_M7HYPDIV_DIV4 ) +#define RCC_M7CLK_HYP_DIV8 (RCC_SYSBUSDIV1_M7HYPDIV_DIV8 ) +#define RCC_M7CLK_HYP_DIV16 (RCC_SYSBUSDIV1_M7HYPDIV_DIV16 ) +#define RCC_M7CLK_HYP_DIV32 (RCC_SYSBUSDIV1_M7HYPDIV_DIV32 ) +#define RCC_M7CLK_HYP_DIV64 (RCC_SYSBUSDIV1_M7HYPDIV_DIV64 ) +#define RCC_M7CLK_HYP_DIV128 (RCC_SYSBUSDIV1_M7HYPDIV_DIV128) +#define RCC_M7CLK_HYP_DIV256 (RCC_SYSBUSDIV1_M7HYPDIV_DIV256) +#define RCC_M7CLK_HYP_DIV512 (RCC_SYSBUSDIV1_M7HYPDIV_DIV512) + +/** AXI Clock DIV values **/ +#define RCC_AXICLK_DIV_MASK (~RCC_SYSBUSDIV1_AXIDIV ) +#define RCC_AXICLK_DIV1 (RCC_SYSBUSDIV1_AXIDIV_DIV1 ) +#define RCC_AXICLK_DIV2 (RCC_SYSBUSDIV1_AXIDIV_DIV2 ) +#define RCC_AXICLK_DIV4 (RCC_SYSBUSDIV1_AXIDIV_DIV4 ) +#define RCC_AXICLK_DIV8 (RCC_SYSBUSDIV1_AXIDIV_DIV8 ) +#define RCC_AXICLK_DIV16 (RCC_SYSBUSDIV1_AXIDIV_DIV16 ) +#define RCC_AXICLK_DIV32 (RCC_SYSBUSDIV1_AXIDIV_DIV32 ) +#define RCC_AXICLK_DIV64 (RCC_SYSBUSDIV1_AXIDIV_DIV64 ) +#define RCC_AXICLK_DIV128 (RCC_SYSBUSDIV1_AXIDIV_DIV128) +#define RCC_AXICLK_DIV256 (RCC_SYSBUSDIV1_AXIDIV_DIV256) +#define RCC_AXICLK_DIV512 (RCC_SYSBUSDIV1_AXIDIV_DIV512) + +/** System bus clock DIV values **/ +#define RCC_BUSCLK_DIV_MASK (~RCC_SYSBUSDIV1_BUSDIV ) +#define RCC_BUSCLK_DIV1 (RCC_SYSBUSDIV1_BUSDIV_DIV1 ) +#define RCC_BUSCLK_DIV2 (RCC_SYSBUSDIV1_BUSDIV_DIV2 ) +#define RCC_BUSCLK_DIV4 (RCC_SYSBUSDIV1_BUSDIV_DIV4 ) +#define RCC_BUSCLK_DIV8 (RCC_SYSBUSDIV1_BUSDIV_DIV8 ) +#define RCC_BUSCLK_DIV16 (RCC_SYSBUSDIV1_BUSDIV_DIV16 ) +#define RCC_BUSCLK_DIV32 (RCC_SYSBUSDIV1_BUSDIV_DIV32 ) +#define RCC_BUSCLK_DIV64 (RCC_SYSBUSDIV1_BUSDIV_DIV64 ) +#define RCC_BUSCLK_DIV128 (RCC_SYSBUSDIV1_BUSDIV_DIV128) +#define RCC_BUSCLK_DIV256 (RCC_SYSBUSDIV1_BUSDIV_DIV256) +#define RCC_BUSCLK_DIV512 (RCC_SYSBUSDIV1_BUSDIV_DIV512) + +/** System clock DIV values **/ +#define RCC_SYSCLK_DIV_MASK (~RCC_SYSBUSDIV1_SCLKDIV ) +#define RCC_SYSCLK_DIV1 (RCC_SYSBUSDIV1_SCLKDIV_DIV1 ) +#define RCC_SYSCLK_DIV2 (RCC_SYSBUSDIV1_SCLKDIV_DIV2 ) +#define RCC_SYSCLK_DIV4 (RCC_SYSBUSDIV1_SCLKDIV_DIV4 ) +#define RCC_SYSCLK_DIV8 (RCC_SYSBUSDIV1_SCLKDIV_DIV8 ) +#define RCC_SYSCLK_DIV16 (RCC_SYSBUSDIV1_SCLKDIV_DIV16 ) +#define RCC_SYSCLK_DIV32 (RCC_SYSBUSDIV1_SCLKDIV_DIV32 ) +#define RCC_SYSCLK_DIV64 (RCC_SYSBUSDIV1_SCLKDIV_DIV64 ) +#define RCC_SYSCLK_DIV128 (RCC_SYSBUSDIV1_SCLKDIV_DIV128) +#define RCC_SYSCLK_DIV256 (RCC_SYSBUSDIV1_SCLKDIV_DIV256) +#define RCC_SYSCLK_DIV512 (RCC_SYSBUSDIV1_SCLKDIV_DIV512) + + +#define RCC_APBCLK_DIV_MASK (~(RCC_SYSBUSDIV2_APB1DIV|RCC_SYSBUSDIV2_APB2DIV|RCC_SYSBUSDIV2_APB5DIV|RCC_SYSBUSDIV2_APB6DIV)) +/** APB6 clock DIV values **/ +#define RCC_APB6CLK_DIV1 (RCC_SYSBUSDIV2_APB6DIV_DIV1 ) +#define RCC_APB6CLK_DIV2 (RCC_SYSBUSDIV2_APB6DIV_DIV2 ) +#define RCC_APB6CLK_DIV4 (RCC_SYSBUSDIV2_APB6DIV_DIV4 ) +#define RCC_APB6CLK_DIV8 (RCC_SYSBUSDIV2_APB6DIV_DIV8 ) +#define RCC_APB6CLK_DIV16 (RCC_SYSBUSDIV2_APB6DIV_DIV16) +/** APB5 clock DIV values **/ +#define RCC_APB5CLK_DIV1 (RCC_SYSBUSDIV2_APB5DIV_DIV1 ) +#define RCC_APB5CLK_DIV2 (RCC_SYSBUSDIV2_APB5DIV_DIV2 ) +#define RCC_APB5CLK_DIV4 (RCC_SYSBUSDIV2_APB5DIV_DIV4 ) +#define RCC_APB5CLK_DIV8 (RCC_SYSBUSDIV2_APB5DIV_DIV8 ) +#define RCC_APB5CLK_DIV16 (RCC_SYSBUSDIV2_APB5DIV_DIV16) +/** APB2 clock DIV values **/ +#define RCC_APB2CLK_DIV1 (RCC_SYSBUSDIV2_APB2DIV_DIV1 ) +#define RCC_APB2CLK_DIV2 (RCC_SYSBUSDIV2_APB2DIV_DIV2 ) +#define RCC_APB2CLK_DIV4 (RCC_SYSBUSDIV2_APB2DIV_DIV4 ) +#define RCC_APB2CLK_DIV8 (RCC_SYSBUSDIV2_APB2DIV_DIV8 ) +#define RCC_APB2CLK_DIV16 (RCC_SYSBUSDIV2_APB2DIV_DIV16) +/** APB1 clock DIV values **/ +#define RCC_APB1CLK_DIV1 (RCC_SYSBUSDIV2_APB1DIV_DIV1 ) +#define RCC_APB1CLK_DIV2 (RCC_SYSBUSDIV2_APB1DIV_DIV2 ) +#define RCC_APB1CLK_DIV4 (RCC_SYSBUSDIV2_APB1DIV_DIV4 ) +#define RCC_APB1CLK_DIV8 (RCC_SYSBUSDIV2_APB1DIV_DIV8 ) +#define RCC_APB1CLK_DIV16 (RCC_SYSBUSDIV2_APB1DIV_DIV16) + +/** Ethernet system clock DIV values **/ +#define RCC_ETHPTPCLK_SRC_MASK (~RCC_AHB2SEL1_ETH1PTPSEL) +#define RCC_ETHPTPCLK_SRC_SYSBUSDIV (RCC_AHB2SEL1_ETH1PTPSEL_SYSBUSDIV) +#define RCC_ETHPTPCLK_SRC_PERIPH (RCC_AHB2SEL1_ETH1PTPSEL_PERIPH) +#define RCC_ETHPTPCLK_SRC_PLL2C (RCC_AHB2SEL1_ETH1PTPSEL_PLL2C ) +#define RCC_ETHPTPCLK_SRC_PLL3A (RCC_AHB2SEL1_ETH1PTPSEL_PLL3A ) + +#define RCC_ETHPTPCLK_SYSBUSDIV_MASK (~RCC_AHB2DIV1_ETH1SYSDIV ) +#define RCC_ETHPTPCLK_SYSBUSDIV1 (RCC_AHB2DIV1_ETH1SYSDIV_DIV1 ) +#define RCC_ETHPTPCLK_SYSBUSDIV2 (RCC_AHB2DIV1_ETH1SYSDIV_DIV2 ) +#define RCC_ETHPTPCLK_SYSBUSDIV4 (RCC_AHB2DIV1_ETH1SYSDIV_DIV4 ) +#define RCC_ETHPTPCLK_SYSBUSDIV8 (RCC_AHB2DIV1_ETH1SYSDIV_DIV8 ) +#define RCC_ETHPTPCLK_SYSBUSDIV16 (RCC_AHB2DIV1_ETH1SYSDIV_DIV16 ) +#define RCC_ETHPTPCLK_SYSBUSDIV32 (RCC_AHB2DIV1_ETH1SYSDIV_DIV32 ) +#define RCC_ETHPTPCLK_SYSBUSDIV64 (RCC_AHB2DIV1_ETH1SYSDIV_DIV64 ) +#define RCC_ETHPTPCLK_SYSBUSDIV128 (RCC_AHB2DIV1_ETH1SYSDIV_DIV128) +#define RCC_ETHPTPCLK_SYSBUSDIV256 (RCC_AHB2DIV1_ETH1SYSDIV_DIV256) +#define RCC_ETHPTPCLK_SYSBUSDIV512 (RCC_AHB2DIV1_ETH1SYSDIV_DIV512) + +#define RCC_ETH1GMIITXCLK_SRC_MASK (~RCC_AHB2SEL1_ETH1GMIITXSEL) +#define RCC_ETH1GMIITXCLK_SRC_PLL3A (RCC_AHB2SEL1_ETH1GMIITXSEL_PLL3A) +#define RCC_ETH1GMIITXCLK_SRC_PLL2B (RCC_AHB2SEL1_ETH1GMIITXSEL_PLL2B) +#define RCC_ETH1GMIITXCLK_SRC_IOM (RCC_AHB2SEL1_ETH1GMIITXSEL_IOM ) +#define RCC_ETH1GMIITXCLK_SRC_PLL1C (RCC_AHB2SEL1_ETH1GMIITXSEL_PLL1C) +/** SDMMC2 clock values **/ +#define RCC_SDMMC2KERCLK_SRC_MASK (~RCC_AHB1SEL1_SDMMC2KERSEL) +#define RCC_SDMMC2KERCLK_SRC_SYSBUSDIV (RCC_AHB1SEL1_SDMMC2KERSEL_SYSBUSDIV) +#define RCC_SDMMC2KERCLK_SRC_PERIPH (RCC_AHB1SEL1_SDMMC2KERSEL_PERIPH) +#define RCC_SDMMC2KERCLK_SRC_PLL2A (RCC_AHB1SEL1_SDMMC2KERSEL_PLL2A ) +#define RCC_SDMMC2KERCLK_SRC_PLL3A (RCC_AHB1SEL1_SDMMC2KERSEL_PLL3A ) +#define RCC_SDMMC2KERCLK_SRC_PLL1B (RCC_AHB1SEL1_SDMMC2KERSEL_PLL1B ) + +#define RCC_SDMMC2KERCLK_SYSBUSDIV_MASK (~RCC_AHB1DIV1_SDMMC2SYSDIV ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV1 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV1 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV2 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV2 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV4 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV4 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV8 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV8 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV16 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV16 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV32 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV32 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV64 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV64 ) +#define RCC_SDMMC2KERCLK_SYSBUSDIV128 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV128) +#define RCC_SDMMC2KERCLK_SYSBUSDIV256 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV256) +#define RCC_SDMMC2KERCLK_SYSBUSDIV512 (RCC_AHB1DIV1_SDMMC2SYSDIV_DIV512) + + +#define RCC_SDMMC1KERCLK_SRC_MASK (~RCC_AXISEL1_SDMMC1KERSEL) +#define RCC_SDMMC1KERCLK_SRC_AXIDIV (RCC_AXISEL1_SDMMC1KERSEL_AXIDIV) +#define RCC_SDMMC1KERCLK_SRC_PERIPH (RCC_AXISEL1_SDMMC1KERSEL_PERIPH) +#define RCC_SDMMC1KERCLK_SRC_PLL2A (RCC_AXISEL1_SDMMC1KERSEL_PLL2A ) +#define RCC_SDMMC1KERCLK_SRC_PLL3A (RCC_AXISEL1_SDMMC1KERSEL_PLL3A ) +#define RCC_SDMMC1KERCLK_SRC_PLL1B (RCC_AXISEL1_SDMMC1KERSEL_PLL1B ) + +#define RCC_SDMMC1KERCLK_AXIDIV_MASK (~RCC_AXIDIV1_SDMMC1AXIDIV ) +#define RCC_SDMMC1KERCLK_AXIDIV1 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV1 ) +#define RCC_SDMMC1KERCLK_AXIDIV2 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV2 ) +#define RCC_SDMMC1KERCLK_AXIDIV4 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV4 ) +#define RCC_SDMMC1KERCLK_AXIDIV8 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV8 ) +#define RCC_SDMMC1KERCLK_AXIDIV16 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV16 ) +#define RCC_SDMMC1KERCLK_AXIDIV32 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV32 ) +#define RCC_SDMMC1KERCLK_AXIDIV64 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV64 ) +#define RCC_SDMMC1KERCLK_AXIDIV128 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV128) +#define RCC_SDMMC1KERCLK_AXIDIV256 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV256) +#define RCC_SDMMC1KERCLK_AXIDIV512 (RCC_AXIDIV1_SDMMC1AXIDIV_DIV512) + + +/** DSMU system bus clock prescalar values **/ +#define RCC_DSMUKERCLK_SRC_MASK (~RCC_APB2SEL1_DSMUKERSEL ) +#define RCC_DSMUKERCLK_SRC_APB2 (RCC_APB2SEL1_DSMUKERSEL_APB2 ) +#define RCC_DSMUKERCLK_SRC_SYSBUSDIV (RCC_APB2SEL1_DSMUKERSEL_SYSBUSDIV) + +#define RCC_DSMUKERCLK_SYSBUSDIV_MASK (~RCC_APB2DIV1_APB2DSMUDIV ) +#define RCC_DSMUKERCLK_SYSBUSDIV1 (RCC_APB2DIV1_APB2DSMUDIV_DIV1 ) +#define RCC_DSMUKERCLK_SYSBUSDIV2 (RCC_APB2DIV1_APB2DSMUDIV_DIV2 ) +#define RCC_DSMUKERCLK_SYSBUSDIV4 (RCC_APB2DIV1_APB2DSMUDIV_DIV4 ) +#define RCC_DSMUKERCLK_SYSBUSDIV8 (RCC_APB2DIV1_APB2DSMUDIV_DIV8 ) +#define RCC_DSMUKERCLK_SYSBUSDIV16 (RCC_APB2DIV1_APB2DSMUDIV_DIV16) + + + +/** DSMU Kernel A clock selection register + */ + +#define RCC_DSMUKERACLK_SRC_MASK (~RCC_APB2SEL1_DSMUKERASEL ) +#define RCC_DSMUKERACLK_SRC_APB2 (RCC_APB2SEL1_DSMUKERASEL_APB2 ) +#define RCC_DSMUKERACLK_SRC_PLL1B (RCC_APB2SEL1_DSMUKERASEL_PLL1B ) +#define RCC_DSMUKERACLK_SRC_PLL2B (RCC_APB2SEL1_DSMUKERASEL_PLL2B ) +#define RCC_DSMUKERACLK_SRC_PLL3A (RCC_APB2SEL1_DSMUKERASEL_PLL3A ) +#define RCC_DSMUKERACLK_SRC_CKIN (RCC_APB2SEL1_DSMUKERASEL_CKIN ) +#define RCC_DSMUKERACLK_SRC_PERIPH (RCC_APB2SEL1_DSMUKERASEL_PERIPH) + +#define RCC_DSMUKERACLK_CKIN_MASK (~RCC_CFG3_I2SSEL) +#define RCC_DSMUKERACLK_CKIN_I2S1 (RCC_CFG3_I2SSEL_I2S1) +#define RCC_DSMUKERACLK_CKIN_I2S2 (RCC_CFG3_I2SSEL_I2S2) +#define RCC_DSMUKERACLK_CKIN_I2S3 (RCC_CFG3_I2SSEL_I2S3) +#define RCC_DSMUKERACLK_CKIN_I2S4 (RCC_CFG3_I2SSEL_I2S4) + +/** Periph clock selection register + */ +#define RCC_PERIPHCLK_SRC_MASK (~RCC_CFG3_PERSW) +#define RCC_PERIPHCLK_SRC_HSI (RCC_REG_BIT_MASK) +#define RCC_PERIPHCLK_SRC_MSI (RCC_CFG3_PERSW_1) +#define RCC_PERIPHCLK_SRC_HSE (RCC_CFG3_PERSW_0|RCC_CFG3_PERSW_1) + +/** USB1/2 reference clock selection register + */ +#define RCC_USBREFCLK_HSE_DIV_MASK (~RCC_AHB2DIV1_USBHSEDIV) +#define RCC_USBREFCLK_HSE_DIV1 (RCC_AHB2DIV1_USBHSEDIV_DIV1) +#define RCC_USBREFCLK_HSE_DIV2 (RCC_AHB2DIV1_USBHSEDIV_DIV2) + +#define RCC_ADC1PLLCLK_SRC_MASK (~RCC_AHB1SEL1_ADC1PLLSEL) +#define RCC_ADC2PLLCLK_SRC_MASK (~RCC_AHB1SEL1_ADC2PLLSEL) +#define RCC_ADC3PLLCLK_SRC_MASK (~RCC_AHB1SEL1_ADC3PLLSEL) +#define RCC_ADCPLLCLK_SRC_PLL2B (RCC_AHB1SEL1_ADC1PLLSEL_PLL2B) +#define RCC_ADCPLLCLK_SRC_PLL1B (RCC_AHB1SEL1_ADC1PLLSEL_PLL1B) +#define RCC_ADCPLLCLK_SRC_PLL3B (RCC_AHB1SEL1_ADC1PLLSEL_PLL3B) +#define RCC_ADCPLLCLK_SRC_PLL3C (RCC_AHB1SEL1_ADC1PLLSEL_PLL3C) + + +#define RCC_ADC1SYSCLK_DIV_MASK (~RCC_AHB1DIV2_ADC1SYSDIV) +#define RCC_ADC2SYSCLK_DIV_MASK (~RCC_AHB1DIV2_ADC2SYSDIV) +#define RCC_ADC3SYSCLK_DIV_MASK (~RCC_AHB1DIV2_ADC3SYSDIV) +#define RCC_ADCSYSCLK_DIV1 (RCC_AHB1DIV2_ADC1SYSDIV_DIV1 ) +#define RCC_ADCSYSCLK_DIV2 (RCC_AHB1DIV2_ADC1SYSDIV_DIV2 ) +#define RCC_ADCSYSCLK_DIV3 (RCC_AHB1DIV2_ADC1SYSDIV_DIV3 ) +#define RCC_ADCSYSCLK_DIV4 (RCC_AHB1DIV2_ADC1SYSDIV_DIV4 ) +#define RCC_ADCSYSCLK_DIV5 (RCC_AHB1DIV2_ADC1SYSDIV_DIV5 ) +#define RCC_ADCSYSCLK_DIV6 (RCC_AHB1DIV2_ADC1SYSDIV_DIV6 ) +#define RCC_ADCSYSCLK_DIV7 (RCC_AHB1DIV2_ADC1SYSDIV_DIV7 ) +#define RCC_ADCSYSCLK_DIV8 (RCC_AHB1DIV2_ADC1SYSDIV_DIV8 ) +#define RCC_ADCSYSCLK_DIV9 (RCC_AHB1DIV2_ADC1SYSDIV_DIV9 ) +#define RCC_ADCSYSCLK_DIV10 (RCC_AHB1DIV2_ADC1SYSDIV_DIV10) +#define RCC_ADCSYSCLK_DIV11 (RCC_AHB1DIV2_ADC1SYSDIV_DIV11) +#define RCC_ADCSYSCLK_DIV12 (RCC_AHB1DIV2_ADC1SYSDIV_DIV12) +#define RCC_ADCSYSCLK_DIV13 (RCC_AHB1DIV2_ADC1SYSDIV_DIV13) +#define RCC_ADCSYSCLK_DIV14 (RCC_AHB1DIV2_ADC1SYSDIV_DIV14) +#define RCC_ADCSYSCLK_DIV15 (RCC_AHB1DIV2_ADC1SYSDIV_DIV15) +#define RCC_ADCSYSCLK_DIV16 (RCC_AHB1DIV2_ADC1SYSDIV_DIV16) +#define RCC_ADCSYSCLK_DIV17 (RCC_AHB1DIV2_ADC1SYSDIV_DIV17) +#define RCC_ADCSYSCLK_DIV18 (RCC_AHB1DIV2_ADC1SYSDIV_DIV18) +#define RCC_ADCSYSCLK_DIV19 (RCC_AHB1DIV2_ADC1SYSDIV_DIV19) +#define RCC_ADCSYSCLK_DIV20 (RCC_AHB1DIV2_ADC1SYSDIV_DIV20) +#define RCC_ADCSYSCLK_DIV21 (RCC_AHB1DIV2_ADC1SYSDIV_DIV21) +#define RCC_ADCSYSCLK_DIV22 (RCC_AHB1DIV2_ADC1SYSDIV_DIV22) +#define RCC_ADCSYSCLK_DIV23 (RCC_AHB1DIV2_ADC1SYSDIV_DIV23) +#define RCC_ADCSYSCLK_DIV24 (RCC_AHB1DIV2_ADC1SYSDIV_DIV24) +#define RCC_ADCSYSCLK_DIV25 (RCC_AHB1DIV2_ADC1SYSDIV_DIV25) +#define RCC_ADCSYSCLK_DIV26 (RCC_AHB1DIV2_ADC1SYSDIV_DIV26) +#define RCC_ADCSYSCLK_DIV27 (RCC_AHB1DIV2_ADC1SYSDIV_DIV27) +#define RCC_ADCSYSCLK_DIV28 (RCC_AHB1DIV2_ADC1SYSDIV_DIV28) +#define RCC_ADCSYSCLK_DIV29 (RCC_AHB1DIV2_ADC1SYSDIV_DIV29) +#define RCC_ADCSYSCLK_DIV30 (RCC_AHB1DIV2_ADC1SYSDIV_DIV30) +#define RCC_ADCSYSCLK_DIV31 (RCC_AHB1DIV2_ADC1SYSDIV_DIV31) +#define RCC_ADCSYSCLK_DIV32 (RCC_AHB1DIV2_ADC1SYSDIV_DIV32) +#define RCC_ADCSYSCLK_DIV33 (RCC_AHB1DIV2_ADC1SYSDIV_DIV33) +#define RCC_ADCSYSCLK_DIV34 (RCC_AHB1DIV2_ADC1SYSDIV_DIV34) +#define RCC_ADCSYSCLK_DIV35 (RCC_AHB1DIV2_ADC1SYSDIV_DIV35) +#define RCC_ADCSYSCLK_DIV36 (RCC_AHB1DIV2_ADC1SYSDIV_DIV36) +#define RCC_ADCSYSCLK_DIV37 (RCC_AHB1DIV2_ADC1SYSDIV_DIV37) +#define RCC_ADCSYSCLK_DIV38 (RCC_AHB1DIV2_ADC1SYSDIV_DIV38) +#define RCC_ADCSYSCLK_DIV39 (RCC_AHB1DIV2_ADC1SYSDIV_DIV39) +#define RCC_ADCSYSCLK_DIV40 (RCC_AHB1DIV2_ADC1SYSDIV_DIV40) +#define RCC_ADCSYSCLK_DIV41 (RCC_AHB1DIV2_ADC1SYSDIV_DIV41) +#define RCC_ADCSYSCLK_DIV42 (RCC_AHB1DIV2_ADC1SYSDIV_DIV42) +#define RCC_ADCSYSCLK_DIV43 (RCC_AHB1DIV2_ADC1SYSDIV_DIV43) +#define RCC_ADCSYSCLK_DIV44 (RCC_AHB1DIV2_ADC1SYSDIV_DIV44) +#define RCC_ADCSYSCLK_DIV45 (RCC_AHB1DIV2_ADC1SYSDIV_DIV45) +#define RCC_ADCSYSCLK_DIV46 (RCC_AHB1DIV2_ADC1SYSDIV_DIV46) +#define RCC_ADCSYSCLK_DIV47 (RCC_AHB1DIV2_ADC1SYSDIV_DIV47) +#define RCC_ADCSYSCLK_DIV48 (RCC_AHB1DIV2_ADC1SYSDIV_DIV48) +#define RCC_ADCSYSCLK_DIV49 (RCC_AHB1DIV2_ADC1SYSDIV_DIV49) +#define RCC_ADCSYSCLK_DIV50 (RCC_AHB1DIV2_ADC1SYSDIV_DIV50) +#define RCC_ADCSYSCLK_DIV51 (RCC_AHB1DIV2_ADC1SYSDIV_DIV51) +#define RCC_ADCSYSCLK_DIV52 (RCC_AHB1DIV2_ADC1SYSDIV_DIV52) +#define RCC_ADCSYSCLK_DIV53 (RCC_AHB1DIV2_ADC1SYSDIV_DIV53) +#define RCC_ADCSYSCLK_DIV54 (RCC_AHB1DIV2_ADC1SYSDIV_DIV54) +#define RCC_ADCSYSCLK_DIV55 (RCC_AHB1DIV2_ADC1SYSDIV_DIV55) +#define RCC_ADCSYSCLK_DIV56 (RCC_AHB1DIV2_ADC1SYSDIV_DIV56) +#define RCC_ADCSYSCLK_DIV57 (RCC_AHB1DIV2_ADC1SYSDIV_DIV57) +#define RCC_ADCSYSCLK_DIV58 (RCC_AHB1DIV2_ADC1SYSDIV_DIV58) +#define RCC_ADCSYSCLK_DIV59 (RCC_AHB1DIV2_ADC1SYSDIV_DIV59) +#define RCC_ADCSYSCLK_DIV60 (RCC_AHB1DIV2_ADC1SYSDIV_DIV60) +#define RCC_ADCSYSCLK_DIV61 (RCC_AHB1DIV2_ADC1SYSDIV_DIV61) +#define RCC_ADCSYSCLK_DIV62 (RCC_AHB1DIV2_ADC1SYSDIV_DIV62) +#define RCC_ADCSYSCLK_DIV63 (RCC_AHB1DIV2_ADC1SYSDIV_DIV63) + + +/** APB1 "btimer(n)_gated_ker_clk" DIV values **/ +#define RCC_BTIMKERCLK_AHB1_DIV_MASK (~RCC_APB1DIV1_APB1BTIMDIV ) +#define RCC_BTIMKERCLK_AHB1_DIV1 (RCC_APB1DIV1_APB1BTIMDIV_DIV1 ) +#define RCC_BTIMKERCLK_AHB1_DIV2 (RCC_APB1DIV1_APB1BTIMDIV_DIV2 ) +#define RCC_BTIMKERCLK_AHB1_DIV4 (RCC_APB1DIV1_APB1BTIMDIV_DIV4 ) +#define RCC_BTIMKERCLK_AHB1_DIV8 (RCC_APB1DIV1_APB1BTIMDIV_DIV8 ) +#define RCC_BTIMKERCLK_AHB1_DIV16 (RCC_APB1DIV1_APB1BTIMDIV_DIV16) + +/** APB1 "gtimer(n)_gated_ker_clk" DIV values **/ +#define RCC_GTIMKERCLK_AHB1_DIV_MASK (~RCC_APB1DIV1_APB1GTIMDIV ) +#define RCC_GTIMKERCLK_AHB1_DIV1 (RCC_APB1DIV1_APB1GTIMDIV_DIV1 ) +#define RCC_GTIMKERCLK_AHB1_DIV2 (RCC_APB1DIV1_APB1GTIMDIV_DIV2 ) +#define RCC_GTIMKERCLK_AHB1_DIV4 (RCC_APB1DIV1_APB1GTIMDIV_DIV4 ) +#define RCC_GTIMKERCLK_AHB1_DIV8 (RCC_APB1DIV1_APB1GTIMDIV_DIV8 ) +#define RCC_GTIMKERCLK_AHB1_DIV16 (RCC_APB1DIV1_APB1GTIMDIV_DIV16) + +/** APB2 "atimer(n)_gated_ker_clk" prescalar values **/ +#define RCC_ATIMKERCLK_AHB2_DIV_MASK (~RCC_APB2DIV1_APB2ATIMDIV ) +#define RCC_ATIMKERCLK_AHB2_DIV1 (RCC_APB2DIV1_APB2ATIMDIV_DIV1 ) +#define RCC_ATIMKERCLK_AHB2_DIV2 (RCC_APB2DIV1_APB2ATIMDIV_DIV2 ) +#define RCC_ATIMKERCLK_AHB2_DIV4 (RCC_APB2DIV1_APB2ATIMDIV_DIV4 ) +#define RCC_ATIMKERCLK_AHB2_DIV8 (RCC_APB2DIV1_APB2ATIMDIV_DIV8 ) +#define RCC_ATIMKERCLK_AHB2_DIV16 (RCC_APB2DIV1_APB2ATIMDIV_DIV16) + +/** APB2 "gtimer(n)_gated_ker_clk" prescalar values **/ +#define RCC_GTIMKERCLK_AHB2_DIV_MASK (~RCC_APB2DIV1_APB2GTIMDIV ) +#define RCC_GTIMKERCLK_AHB2_DIV1 (RCC_APB2DIV1_APB2GTIMDIV_DIV1 ) +#define RCC_GTIMKERCLK_AHB2_DIV2 (RCC_APB2DIV1_APB2GTIMDIV_DIV2 ) +#define RCC_GTIMKERCLK_AHB2_DIV4 (RCC_APB2DIV1_APB2GTIMDIV_DIV4 ) +#define RCC_GTIMKERCLK_AHB2_DIV8 (RCC_APB2DIV1_APB2GTIMDIV_DIV8 ) +#define RCC_GTIMKERCLK_AHB2_DIV16 (RCC_APB2DIV1_APB2GTIMDIV_DIV16) + +/** APB5 "atimer(n)_gated_ker_clk" prescalar values **/ +#define RCC_ATIMKERCLK_AHB5_DIV_MASK (~RCC_APB5DIV1_APB5ATIMDIV ) +#define RCC_ATIMKERCLK_AHB5_DIV1 (RCC_APB5DIV1_APB5ATIMDIV_DIV1 ) +#define RCC_ATIMKERCLK_AHB5_DIV2 (RCC_APB5DIV1_APB5ATIMDIV_DIV2 ) +#define RCC_ATIMKERCLK_AHB5_DIV4 (RCC_APB5DIV1_APB5ATIMDIV_DIV4 ) +#define RCC_ATIMKERCLK_AHB5_DIV8 (RCC_APB5DIV1_APB5ATIMDIV_DIV8 ) +#define RCC_ATIMKERCLK_AHB5_DIV16 (RCC_APB5DIV1_APB5ATIMDIV_DIV16) + + +/** APB1 USART prescalar values **/ +#define RCC_USARTPCLK_AHB1_DIV_MASK (~RCC_APB1DIV1_APB1USARTDIV ) +#define RCC_USARTPCLK_AHB1_DIV1 (RCC_APB1DIV1_APB1USARTDIV_DIV1 ) +#define RCC_USARTPCLK_AHB1_DIV2 (RCC_APB1DIV1_APB1USARTDIV_DIV2 ) +#define RCC_USARTPCLK_AHB1_DIV4 (RCC_APB1DIV1_APB1USARTDIV_DIV4 ) +#define RCC_USARTPCLK_AHB1_DIV8 (RCC_APB1DIV1_APB1USARTDIV_DIV8 ) +#define RCC_USARTPCLK_AHB1_DIV16 (RCC_APB1DIV1_APB1USARTDIV_DIV16) + +/** APB1 "i2s(n)_ker_gated_clk" DIV values **/ +#define RCC_I2S1_2_KERCLK_SYSBUSDIV_MASK (~RCC_APB2DIV1_APB2I2SDIV ) +#define RCC_I2S3_4_KERCLK_SYSBUSDIV_MASK (~RCC_APB1DIV1_APB1I2SDIV ) +#define RCC_I2SKERCLK_SYSBUSDIV1 (RCC_APB1DIV1_APB1I2SDIV_DIV1 ) +#define RCC_I2SKERCLK_SYSBUSDIV2 (RCC_APB1DIV1_APB1I2SDIV_DIV2 ) +#define RCC_I2SKERCLK_SYSBUSDIV4 (RCC_APB1DIV1_APB1I2SDIV_DIV4 ) +#define RCC_I2SKERCLK_SYSBUSDIV8 (RCC_APB1DIV1_APB1I2SDIV_DIV8 ) +#define RCC_I2SKERCLK_SYSBUSDIV16 (RCC_APB1DIV1_APB1I2SDIV_DIV16) + + +#define RCC_I2S1KERCLK_SRC_MASK (~RCC_APB2SEL1_I2S1KERSEL ) +#define RCC_I2S2KERCLK_SRC_MASK (~RCC_APB2SEL1_I2S2KERSEL ) +#define RCC_I2S3KERCLK_SRC_MASK (~RCC_APB1SEL1_I2S3KERSEL ) +#define RCC_I2S4KERCLK_SRC_MASK (~RCC_APB1SEL1_I2S4KERSEL ) +#define RCC_I2SKERCLK_SRC_SYSBUSDIV (RCC_APB2SEL1_I2S1KERSEL_SYSBUSDIV) +#define RCC_I2SKERCLK_SRC_PLL3B (RCC_APB2SEL1_I2S1KERSEL_PLL3B ) +#define RCC_I2SKERCLK_SRC_HSI (RCC_APB2SEL1_I2S1KERSEL_HSI ) +#define RCC_I2SKERCLK_SRC_CLKIN (RCC_APB2SEL1_I2S1KERSEL_CLKIN ) + +/** "i2c(n)_ker_gated_clk" prescalar values when "I2C(n)_KER_CLK_SEL" is selected as 3'b100 **/ + +#define RCC_I2C1_3_KERCLK_SYSBUSDIV_MASK (~RCC_APB1DIV1_APB1I2CDIV ) +#define RCC_I2C4_6_KERCLK_SYSBUSDIV_MASK (~RCC_APB2DIV1_APB2I2CDIV ) +#define RCC_I2C7_10_KERCLK_SYSBUSDIV_MASK (~RCC_APB5DIV1_APB5I2CDIV ) + +#define RCC_I2CKERCLK_SYSBUSDIV1 (RCC_APB1DIV1_APB1I2CDIV_DIV1 ) +#define RCC_I2CKERCLK_SYSBUSDIV2 (RCC_APB1DIV1_APB1I2CDIV_DIV2 ) +#define RCC_I2CKERCLK_SYSBUSDIV4 (RCC_APB1DIV1_APB1I2CDIV_DIV4 ) +#define RCC_I2CKERCLK_SYSBUSDIV8 (RCC_APB1DIV1_APB1I2CDIV_DIV8 ) +#define RCC_I2CKERCLK_SYSBUSDIV16 (RCC_APB1DIV1_APB1I2CDIV_DIV16) + +#define RCC_I2C1KERCLK_SRC_MASK (~RCC_APB1SEL1_I2C1KERSEL ) +#define RCC_I2C2KERCLK_SRC_MASK (~RCC_APB1SEL1_I2C2KERSEL ) +#define RCC_I2C3KERCLK_SRC_MASK (~RCC_APB1SEL1_I2C3KERSEL ) +#define RCC_I2C4KERCLK_SRC_MASK (~RCC_APB2SEL1_I2C4KERSEL ) +#define RCC_I2C5KERCLK_SRC_MASK (~RCC_APB2SEL1_I2C5KERSEL ) +#define RCC_I2C6KERCLK_SRC_MASK (~RCC_APB2SEL1_I2C6KERSEL ) +#define RCC_I2C7KERCLK_SRC_MASK (~RCC_APB5SEL1_I2C7KERSEL ) +#define RCC_I2C8KERCLK_SRC_MASK (~RCC_APB5SEL1_I2C8KERSEL ) +#define RCC_I2C9KERCLK_SRC_MASK (~RCC_APB5SEL1_I2C9KERSEL ) +#define RCC_I2C10KERCLK_SRC_MASK (~RCC_APB5SEL1_I2C10KERSEL ) + +#define RCC_I2CKERCLK_SRC_SYSBUSDIV (RCC_APB1SEL1_I2C3KERSEL_SYSBUSDIV) +#define RCC_I2CKERCLK_SRC_PLL3C (RCC_APB1SEL1_I2C3KERSEL_PLL3C ) +#define RCC_I2CKERCLK_SRC_HSI (RCC_APB1SEL1_I2C3KERSEL_HSI ) +#define RCC_I2CKERCLK_SRC_MSI (RCC_APB1SEL1_I2C3KERSEL_MSI ) + + +/** CAN FD Kernel clock selection register **/ +#define RCC_FDCAN1_2_5_6_KERCLK_SYSBUSDIV_MASK (~RCC_APB1DIV1_APB1FDCANDIV ) +#define RCC_FDCAN3_4_7_8_KERCLK_SYSBUSDIV_MASK (~RCC_APB2DIV1_APB2FDCANDIV ) + +#define RCC_FDCANKERCLK_SYSBUSDIV1 (RCC_APB1DIV1_APB1FDCANDIV_DIV1 ) +#define RCC_FDCANKERCLK_SYSBUSDIV2 (RCC_APB1DIV1_APB1FDCANDIV_DIV2 ) +#define RCC_FDCANKERCLK_SYSBUSDIV4 (RCC_APB1DIV1_APB1FDCANDIV_DIV4 ) +#define RCC_FDCANKERCLK_SYSBUSDIV8 (RCC_APB1DIV1_APB1FDCANDIV_DIV8 ) +#define RCC_FDCANKERCLK_SYSBUSDIV16 (RCC_APB1DIV1_APB1FDCANDIV_DIV16) + +#define RCC_FDCAN1KERCLK_SRC_MASK (~RCC_APB1SEL1_FDCAN1KERSEL) +#define RCC_FDCAN2KERCLK_SRC_MASK (~RCC_APB1SEL1_FDCAN2KERSEL) +#define RCC_FDCAN5KERCLK_SRC_MASK (~RCC_APB1SEL2_FDCAN5KERSEL) +#define RCC_FDCAN6KERCLK_SRC_MASK (~RCC_APB1SEL2_FDCAN6KERSEL) +#define RCC_FDCAN3KERCLK_SRC_MASK (~RCC_APB2SEL2_FDCAN3KERSEL) +#define RCC_FDCAN4KERCLK_SRC_MASK (~RCC_APB2SEL2_FDCAN4KERSEL) +#define RCC_FDCAN7KERCLK_SRC_MASK (~RCC_APB2SEL2_FDCAN7KERSEL) +#define RCC_FDCAN8KERCLK_SRC_MASK (~RCC_APB2SEL2_FDCAN8KERSEL) + +#define RCC_FDCANKERCLK_SRC_SYSBUSDIV (RCC_APB1SEL1_FDCAN2KERSEL_SYSBUSDIV) +#define RCC_FDCANKERCLK_SRC_PLL1C (RCC_APB1SEL1_FDCAN2KERSEL_PLL1C ) +#define RCC_FDCANKERCLK_SRC_PLL2C (RCC_APB1SEL1_FDCAN2KERSEL_PLL2C ) +#define RCC_FDCANKERCLK_SRC_PLL3B (RCC_APB1SEL1_FDCAN2KERSEL_PLL3B ) +#define RCC_FDCANKERCLK_SRC_PERIPH (RCC_APB1SEL1_FDCAN2KERSEL_PERIPH) + + +/** EXTI clock source selection. **/ + +#define RCC_EXTI_SYSBUSDIV_MASK (~RCC_APB5DIV1_APB5EXTIDIV ) +#define RCC_EXTICLK_SYSBUSDIV1 (RCC_APB5DIV1_APB5EXTIDIV_DIV1 ) +#define RCC_EXTICLK_SYSBUSDIV2 (RCC_APB5DIV1_APB5EXTIDIV_DIV2 ) +#define RCC_EXTICLK_SYSBUSDIV4 (RCC_APB5DIV1_APB5EXTIDIV_DIV4 ) +#define RCC_EXTICLK_SYSBUSDIV8 (RCC_APB5DIV1_APB5EXTIDIV_DIV8 ) +#define RCC_EXTICLK_SYSBUSDIV16 (RCC_APB5DIV1_APB5EXTIDIV_DIV16) + +/** RTC Kernel clock source selection. The BDRST bit can be used to reset this field **/ +#define RCC_RTC_ENABLE (RCC_BDCTRL_RTCEN) + +#define RCC_RTCCLK_SRC_MASK (~RCC_BDCTRL_RTCSEL) +#define RCC_RTCCLK_SRC_LSE (RCC_BDCTRL_RTCSEL_LSE) +#define RCC_RTCCLK_SRC_LSI (RCC_BDCTRL_RTCSEL_LSI) +#define RCC_RTCCLK_SRC_HSEDIV (RCC_BDCTRL_RTCSEL_HSEDIV) + +#define RCC_RTCCLK_HSEDIV_MASK (~RCC_CFG5_RTCHSEDIV ) +#define RCC_RTCCLK_HSEDIV1 (RCC_CFG5_RTCHSEDIV_DIV1 ) +#define RCC_RTCCLK_HSEDIV2 (RCC_CFG5_RTCHSEDIV_DIV2 ) +#define RCC_RTCCLK_HSEDIV3 (RCC_CFG5_RTCHSEDIV_DIV3 ) +#define RCC_RTCCLK_HSEDIV4 (RCC_CFG5_RTCHSEDIV_DIV4 ) +#define RCC_RTCCLK_HSEDIV5 (RCC_CFG5_RTCHSEDIV_DIV5 ) +#define RCC_RTCCLK_HSEDIV6 (RCC_CFG5_RTCHSEDIV_DIV6 ) +#define RCC_RTCCLK_HSEDIV7 (RCC_CFG5_RTCHSEDIV_DIV7 ) +#define RCC_RTCCLK_HSEDIV8 (RCC_CFG5_RTCHSEDIV_DIV8 ) +#define RCC_RTCCLK_HSEDIV9 (RCC_CFG5_RTCHSEDIV_DIV9 ) +#define RCC_RTCCLK_HSEDIV10 (RCC_CFG5_RTCHSEDIV_DIV10 ) +#define RCC_RTCCLK_HSEDIV11 (RCC_CFG5_RTCHSEDIV_DIV11 ) +#define RCC_RTCCLK_HSEDIV12 (RCC_CFG5_RTCHSEDIV_DIV12 ) +#define RCC_RTCCLK_HSEDIV13 (RCC_CFG5_RTCHSEDIV_DIV13 ) +#define RCC_RTCCLK_HSEDIV14 (RCC_CFG5_RTCHSEDIV_DIV14 ) +#define RCC_RTCCLK_HSEDIV15 (RCC_CFG5_RTCHSEDIV_DIV15 ) +#define RCC_RTCCLK_HSEDIV16 (RCC_CFG5_RTCHSEDIV_DIV16 ) +#define RCC_RTCCLK_HSEDIV17 (RCC_CFG5_RTCHSEDIV_DIV17 ) +#define RCC_RTCCLK_HSEDIV18 (RCC_CFG5_RTCHSEDIV_DIV18 ) +#define RCC_RTCCLK_HSEDIV19 (RCC_CFG5_RTCHSEDIV_DIV19 ) +#define RCC_RTCCLK_HSEDIV20 (RCC_CFG5_RTCHSEDIV_DIV20 ) +#define RCC_RTCCLK_HSEDIV21 (RCC_CFG5_RTCHSEDIV_DIV21 ) +#define RCC_RTCCLK_HSEDIV22 (RCC_CFG5_RTCHSEDIV_DIV22 ) +#define RCC_RTCCLK_HSEDIV23 (RCC_CFG5_RTCHSEDIV_DIV23 ) +#define RCC_RTCCLK_HSEDIV24 (RCC_CFG5_RTCHSEDIV_DIV24 ) +#define RCC_RTCCLK_HSEDIV25 (RCC_CFG5_RTCHSEDIV_DIV25 ) +#define RCC_RTCCLK_HSEDIV26 (RCC_CFG5_RTCHSEDIV_DIV26 ) +#define RCC_RTCCLK_HSEDIV27 (RCC_CFG5_RTCHSEDIV_DIV27 ) +#define RCC_RTCCLK_HSEDIV28 (RCC_CFG5_RTCHSEDIV_DIV28 ) +#define RCC_RTCCLK_HSEDIV29 (RCC_CFG5_RTCHSEDIV_DIV29 ) +#define RCC_RTCCLK_HSEDIV30 (RCC_CFG5_RTCHSEDIV_DIV30 ) +#define RCC_RTCCLK_HSEDIV31 (RCC_CFG5_RTCHSEDIV_DIV31 ) +#define RCC_RTCCLK_HSEDIV32 (RCC_CFG5_RTCHSEDIV_DIV32 ) +#define RCC_RTCCLK_HSEDIV33 (RCC_CFG5_RTCHSEDIV_DIV33 ) +#define RCC_RTCCLK_HSEDIV34 (RCC_CFG5_RTCHSEDIV_DIV34 ) +#define RCC_RTCCLK_HSEDIV35 (RCC_CFG5_RTCHSEDIV_DIV35 ) +#define RCC_RTCCLK_HSEDIV36 (RCC_CFG5_RTCHSEDIV_DIV36 ) +#define RCC_RTCCLK_HSEDIV37 (RCC_CFG5_RTCHSEDIV_DIV37 ) +#define RCC_RTCCLK_HSEDIV38 (RCC_CFG5_RTCHSEDIV_DIV38 ) +#define RCC_RTCCLK_HSEDIV39 (RCC_CFG5_RTCHSEDIV_DIV39 ) +#define RCC_RTCCLK_HSEDIV40 (RCC_CFG5_RTCHSEDIV_DIV40 ) +#define RCC_RTCCLK_HSEDIV41 (RCC_CFG5_RTCHSEDIV_DIV41 ) +#define RCC_RTCCLK_HSEDIV42 (RCC_CFG5_RTCHSEDIV_DIV42 ) +#define RCC_RTCCLK_HSEDIV43 (RCC_CFG5_RTCHSEDIV_DIV43 ) +#define RCC_RTCCLK_HSEDIV44 (RCC_CFG5_RTCHSEDIV_DIV44 ) +#define RCC_RTCCLK_HSEDIV45 (RCC_CFG5_RTCHSEDIV_DIV45 ) +#define RCC_RTCCLK_HSEDIV46 (RCC_CFG5_RTCHSEDIV_DIV46 ) +#define RCC_RTCCLK_HSEDIV47 (RCC_CFG5_RTCHSEDIV_DIV47 ) +#define RCC_RTCCLK_HSEDIV48 (RCC_CFG5_RTCHSEDIV_DIV48 ) +#define RCC_RTCCLK_HSEDIV49 (RCC_CFG5_RTCHSEDIV_DIV49 ) +#define RCC_RTCCLK_HSEDIV50 (RCC_CFG5_RTCHSEDIV_DIV50 ) +#define RCC_RTCCLK_HSEDIV51 (RCC_CFG5_RTCHSEDIV_DIV51 ) +#define RCC_RTCCLK_HSEDIV52 (RCC_CFG5_RTCHSEDIV_DIV52 ) +#define RCC_RTCCLK_HSEDIV53 (RCC_CFG5_RTCHSEDIV_DIV53 ) +#define RCC_RTCCLK_HSEDIV54 (RCC_CFG5_RTCHSEDIV_DIV54 ) +#define RCC_RTCCLK_HSEDIV55 (RCC_CFG5_RTCHSEDIV_DIV55 ) +#define RCC_RTCCLK_HSEDIV56 (RCC_CFG5_RTCHSEDIV_DIV56 ) +#define RCC_RTCCLK_HSEDIV57 (RCC_CFG5_RTCHSEDIV_DIV57 ) +#define RCC_RTCCLK_HSEDIV58 (RCC_CFG5_RTCHSEDIV_DIV58 ) +#define RCC_RTCCLK_HSEDIV59 (RCC_CFG5_RTCHSEDIV_DIV59 ) +#define RCC_RTCCLK_HSEDIV60 (RCC_CFG5_RTCHSEDIV_DIV60 ) +#define RCC_RTCCLK_HSEDIV61 (RCC_CFG5_RTCHSEDIV_DIV61 ) +#define RCC_RTCCLK_HSEDIV62 (RCC_CFG5_RTCHSEDIV_DIV62 ) +#define RCC_RTCCLK_HSEDIV63 (RCC_CFG5_RTCHSEDIV_DIV63 ) + +#define RCC_BKUP_RESET (RCC_BDCTRL_BDRST) +#define RCC_DCMU_RESET (RCC_CFG4_DCMURST) +/** LPTIMER1 Kernel clock selection register **/ +#define RCC_LPTIM1CLK_SRC_MASK (~RCC_RDSEL1_LPTIM1SEL ) +#define RCC_LPTIM2CLK_SRC_MASK (~RCC_RDSEL1_LPTIM2SEL ) +#define RCC_LPTIM3CLK_SRC_MASK (~RCC_RDSEL1_LPTIM3SEL ) +#define RCC_LPTIM4CLK_SRC_MASK (~RCC_RDSEL1_LPTIM4SEL ) +#define RCC_LPTIM5CLK_SRC_MASK (~RCC_RDSEL1_LPTIM5SEL ) + +#define RCC_LPTIMCLK_SRC_APB5 (RCC_RDSEL1_LPTIM1SEL_APB5 ) +#define RCC_LPTIMCLK_SRC_LSI (RCC_RDSEL1_LPTIM1SEL_LSI ) +#define RCC_LPTIMCLK_SRC_LSE (RCC_RDSEL1_LPTIM1SEL_LSE ) +#define RCC_LPTIMCLK_SRC_HSE (RCC_RDSEL1_LPTIM1SEL_HSE ) +#define RCC_LPTIMCLK_SRC_HSI (RCC_RDSEL1_LPTIM1SEL_HSI ) +#define RCC_LPTIMCLK_SRC_MSI (RCC_RDSEL1_LPTIM1SEL_MSI ) +#define RCC_LPTIMCLK_SRC_COMP1 (RCC_RDSEL1_LPTIM1SEL_COMP1) +#define RCC_LPTIMCLK_SRC_COMP2 (RCC_RDSEL1_LPTIM1SEL_COMP2) +#define RCC_LPTIMCLK_SRC_COMP3 (RCC_RDSEL1_LPTIM1SEL_COMP3) +#define RCC_LPTIMCLK_SRC_COMP4 (RCC_RDSEL1_LPTIM1SEL_COMP4) + +#define RCC_GATEEN_LPTIM1_COMP1 (RCC_RDCTRL1_LPTIM1COMP1EN) +#define RCC_GATEEN_LPTIM1_COMP2 (RCC_RDCTRL1_LPTIM1COMP2EN) +#define RCC_GATEEN_LPTIM1_COMP3 (RCC_RDCTRL1_LPTIM1COMP3EN) +#define RCC_GATEEN_LPTIM1_COMP4 (RCC_RDCTRL1_LPTIM1COMP4EN) + +#define RCC_GATEEN_LPTIM2_COMP1 (RCC_RDCTRL1_LPTIM2COMP1EN) +#define RCC_GATEEN_LPTIM2_COMP2 (RCC_RDCTRL1_LPTIM2COMP2EN) +#define RCC_GATEEN_LPTIM2_COMP3 (RCC_RDCTRL1_LPTIM2COMP3EN) +#define RCC_GATEEN_LPTIM2_COMP4 (RCC_RDCTRL1_LPTIM2COMP4EN) + +#define RCC_GATEEN_LPTIM3_COMP1 (RCC_RDCTRL2_LPTIM3COMP1EN) +#define RCC_GATEEN_LPTIM3_COMP2 (RCC_RDCTRL2_LPTIM3COMP2EN) +#define RCC_GATEEN_LPTIM3_COMP3 (RCC_RDCTRL2_LPTIM3COMP3EN) +#define RCC_GATEEN_LPTIM3_COMP4 (RCC_RDCTRL2_LPTIM3COMP4EN) + +#define RCC_GATEEN_LPTIM4_COMP1 (RCC_RDCTRL2_LPTIM4COMP1EN) +#define RCC_GATEEN_LPTIM4_COMP2 (RCC_RDCTRL2_LPTIM4COMP2EN) +#define RCC_GATEEN_LPTIM4_COMP3 (RCC_RDCTRL2_LPTIM4COMP3EN) +#define RCC_GATEEN_LPTIM4_COMP4 (RCC_RDCTRL2_LPTIM4COMP4EN) + +#define RCC_GATEEN_LPTIM5_COMP1 (RCC_RDCTRL3_LPTIM5COMP1EN) +#define RCC_GATEEN_LPTIM5_COMP2 (RCC_RDCTRL3_LPTIM5COMP2EN) +#define RCC_GATEEN_LPTIM5_COMP3 (RCC_RDCTRL3_LPTIM5COMP3EN) +#define RCC_GATEEN_LPTIM5_COMP4 (RCC_RDCTRL3_LPTIM5COMP4EN) + +/** LPUART1 Kernel clock selection register **/ +#define RCC_LPUART1CLK_SRC_MASK (~RCC_RDSEL1_LPUART1SEL ) +#define RCC_LPUART2CLK_SRC_MASK (~RCC_RDSEL1_LPUART2SEL ) + +#define RCC_LPUARTCLK_SRC_SYSBUSDIV (RCC_RDSEL1_LPUART1SEL_SYSBUSDIV ) +#define RCC_LPUARTCLK_SRC_HSI (RCC_RDSEL1_LPUART1SEL_HSI ) +#define RCC_LPUARTCLK_SRC_LSE (RCC_RDSEL1_LPUART1SEL_LSE ) +#define RCC_LPUARTCLK_SRC_HSE (RCC_RDSEL1_LPUART1SEL_HSE ) +#define RCC_LPUARTCLK_SRC_MSI (RCC_RDSEL1_LPUART1SEL_MSI ) + +#define RCC_LPUARTCLK_SYSBUSDIV_MASK (~RCC_RDDIV1_LPUARTDIV ) +#define RCC_LPUARTCLK_SYSBUSDIV1 (RCC_RDDIV1_LPUARTDIV_DIV1 ) +#define RCC_LPUARTCLK_SYSBUSDIV2 (RCC_RDDIV1_LPUARTDIV_DIV2 ) +#define RCC_LPUARTCLK_SYSBUSDIV4 (RCC_RDDIV1_LPUARTDIV_DIV4 ) +#define RCC_LPUARTCLK_SYSBUSDIV8 (RCC_RDDIV1_LPUARTDIV_DIV8 ) +#define RCC_LPUARTCLK_SYSBUSDIV16 (RCC_RDDIV1_LPUARTDIV_DIV16) + +/** Comparator Controller Clock Switch Selection **/ + +#define RCC_COMPLSXCLK_SRC_MASK (~RCC_RDSEL1_COMPSEL ) +#define RCC_COMPLSXCLK_SRC_LSI (RCC_REG_BIT_MASK ) +#define RCC_COMPLSXCLK_SRC_LSE (RCC_RDSEL1_COMPSEL ) + +#define RCC_COMPKERCLK_SYSBUSDIV_MASK (~RCC_RDDIV1_COMPDIV ) +#define RCC_COMPKERCLK_SYSBUSDIV1 (RCC_RDDIV1_COMPDIV_DIV1 ) +#define RCC_COMPKERCLK_SYSBUSDIV2 (RCC_RDDIV1_COMPDIV_DIV2 ) +#define RCC_COMPKERCLK_SYSBUSDIV4 (RCC_RDDIV1_COMPDIV_DIV4 ) +#define RCC_COMPKERCLK_SYSBUSDIV8 (RCC_RDDIV1_COMPDIV_DIV8 ) +#define RCC_COMPKERCLK_SYSBUSDIV16 (RCC_RDDIV1_COMPDIV_DIV16) + +/** FEMC clock values **/ +#define RCC_FEMCM0CLK_SRC_MASK (~RCC_AXISEL2_FEMCM0SEL) +#define RCC_FEMCM1CLK_SRC_MASK (~RCC_AXISEL2_FEMCM1SEL) +#define RCC_FEMCCLK_SRC_AXIDIV (RCC_AXISEL2_FEMCM0SEL_AXIDIV) +#define RCC_FEMCCLK_SRC_PERIPH (RCC_AXISEL2_FEMCM0SEL_PERIPH) +#define RCC_FEMCCLK_SRC_PLL2C (RCC_AXISEL2_FEMCM0SEL_PLL2C ) +#define RCC_FEMCCLK_SRC_PLL3B (RCC_AXISEL2_FEMCM0SEL_PLL3B ) +#define RCC_FEMCCLK_SRC_PLL1B (RCC_AXISEL2_FEMCM0SEL_PLL1B ) + +#define RCC_FEMCM0CLK_AXIDIV_MASK (~RCC_AXIDIV2_FEMCM0AXIDIV ) +#define RCC_FEMCM1CLK_AXIDIV_MASK (~RCC_AXIDIV2_FEMCM1AXIDIV ) +#define RCC_FEMCCLK_AXIDIV1 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV1 ) +#define RCC_FEMCCLK_AXIDIV2 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV2 ) +#define RCC_FEMCCLK_AXIDIV3 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV3 ) +#define RCC_FEMCCLK_AXIDIV4 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV4 ) +#define RCC_FEMCCLK_AXIDIV5 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV5 ) +#define RCC_FEMCCLK_AXIDIV6 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV6 ) +#define RCC_FEMCCLK_AXIDIV7 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV7 ) +#define RCC_FEMCCLK_AXIDIV8 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV8 ) +#define RCC_FEMCCLK_AXIDIV9 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV9 ) +#define RCC_FEMCCLK_AXIDIV10 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV10) +#define RCC_FEMCCLK_AXIDIV11 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV11) +#define RCC_FEMCCLK_AXIDIV12 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV12) +#define RCC_FEMCCLK_AXIDIV13 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV13) +#define RCC_FEMCCLK_AXIDIV14 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV14) +#define RCC_FEMCCLK_AXIDIV15 (RCC_AXIDIV2_FEMCM0AXIDIV_DIV15) + +/** DSI clock values **/ +#define RCC_DSIREFCLK_HSE_DIV_MASK (~RCC_CFG5_DSIHSEDIV ) +#define RCC_DSIREFCLK_HSE_DIV1 (RCC_REG_BIT_MASK ) +#define RCC_DSIREFCLK_HSE_DIV2 (RCC_CFG5_DSIHSEDIV_0 ) + +#define RCC_DSIKERCLK_SRC_MASK (~RCC_AXISEL1_DSIKERSEL ) +#define RCC_DSIKERCLK_SRC_REF (RCC_REG_BIT_MASK ) +#define RCC_DSIKERCLK_SRC_PLL3C (RCC_AXISEL1_DSIKERSEL_0 ) + +#define RCC_DSIPPICLK_SRC_MASK (~RCC_AXISEL1_DSIPPITXSEL) +#define RCC_DSIPPICLK_SRC_REFDIV (RCC_AXISEL1_DSIPPITXSEL_REFDIV) +#define RCC_DSIPPICLK_SRC_PLL2B (RCC_AXISEL1_DSIPPITXSEL_PLL2B ) +#define RCC_DSIPPICLK_SRC_PERIPH (RCC_AXISEL1_DSIPPITXSEL_PERIPH) +#define RCC_DSIPPICLK_SRC_AXIDIV (RCC_AXISEL1_DSIPPITXSEL_AXIDIV) + +#define RCC_DSIPPICLK_REFDIV_MASK (~RCC_AXIDIV1_DSIREFDIV ) +#define RCC_DSIPPICLK_AXIDIV_MASK (~RCC_AXIDIV2_DSIAXIPPIDIV ) +#define RCC_DSIPPICLK_DIV1 (RCC_AXIDIV1_DSIREFDIV_DIV1 ) +#define RCC_DSIPPICLK_DIV2 (RCC_AXIDIV1_DSIREFDIV_DIV2 ) +#define RCC_DSIPPICLK_DIV4 (RCC_AXIDIV1_DSIREFDIV_DIV4 ) +#define RCC_DSIPPICLK_DIV8 (RCC_AXIDIV1_DSIREFDIV_DIV8 ) +#define RCC_DSIPPICLK_DIV16 (RCC_AXIDIV1_DSIREFDIV_DIV16 ) +#define RCC_DSIPPICLK_DIV32 (RCC_AXIDIV1_DSIREFDIV_DIV32 ) +#define RCC_DSIPPICLK_DIV64 (RCC_AXIDIV1_DSIREFDIV_DIV64 ) +#define RCC_DSIPPICLK_DIV128 (RCC_AXIDIV1_DSIREFDIV_DIV128) +#define RCC_DSIPPICLK_DIV256 (RCC_AXIDIV1_DSIREFDIV_DIV256) +#define RCC_DSIPPICLK_DIV512 (RCC_AXIDIV1_DSIREFDIV_DIV512) + +#define RCC_DSIULPSCLK_SRC_MASK (~RCC_AXISEL1_DSIULPSSEL ) +#define RCC_DSIULPSCLK_SRC_REFDIV (RCC_REG_BIT_MASK ) +#define RCC_DSIULPSCLK_SRC_PLL3C (RCC_AXISEL1_DSIULPSSEL_0 ) + +#define RCC_DSIULPSCLK_REFDIV_MASK (~RCC_AXIDIV2_DSIREFULPSDIV ) +#define RCC_DSIULPSCLK_REFDIV1 (RCC_AXIDIV2_DSIREFULPSDIV_DIV1 ) +#define RCC_DSIULPSCLK_REFDIV2 (RCC_AXIDIV2_DSIREFULPSDIV_DIV2 ) +#define RCC_DSIULPSCLK_REFDIV4 (RCC_AXIDIV2_DSIREFULPSDIV_DIV4 ) +#define RCC_DSIULPSCLK_REFDIV8 (RCC_AXIDIV2_DSIREFULPSDIV_DIV8 ) +#define RCC_DSIULPSCLK_REFDIV16 (RCC_AXIDIV2_DSIREFULPSDIV_DIV16 ) +#define RCC_DSIULPSCLK_REFDIV32 (RCC_AXIDIV2_DSIREFULPSDIV_DIV32 ) +#define RCC_DSIULPSCLK_REFDIV64 (RCC_AXIDIV2_DSIREFULPSDIV_DIV64 ) +#define RCC_DSIULPSCLK_REFDIV128 (RCC_AXIDIV2_DSIREFULPSDIV_DIV128) +#define RCC_DSIULPSCLK_REFDIV256 (RCC_AXIDIV2_DSIREFULPSDIV_DIV256) +#define RCC_DSIULPSCLK_REFDIV512 (RCC_AXIDIV2_DSIREFULPSDIV_DIV512) + +/** "axi_gated_bus_div_lcdc_clk" prescalar values **/ +#define RCC_LCDCPIXELCLK_SRC_MASK (~RCC_AXISEL1_LCDCKERSEL) +#define RCC_LCDCPIXELCLK_SRC_AXIDIV (RCC_AXISEL1_LCDCKERSEL_AXIDIV) +#define RCC_LCDCPIXELCLK_SRC_PERIPH (RCC_AXISEL1_LCDCKERSEL_PERIPH) +#define RCC_LCDCPIXELCLK_SRC_PLL2C (RCC_AXISEL1_LCDCKERSEL_PLL2C ) +#define RCC_LCDCPIXELCLK_SRC_PLL3B (RCC_AXISEL1_LCDCKERSEL_PLL3B ) + +#define RCC_LCDCPIXELCLK_AXIDIV_MASK (~RCC_AXIDIV1_LCDCAXIDIV ) +#define RCC_LCDCPIXELCLK_AXIDIV1 (RCC_AXIDIV1_LCDCAXIDIV_DIV1 ) +#define RCC_LCDCPIXELCLK_AXIDIV2 (RCC_AXIDIV1_LCDCAXIDIV_DIV2 ) +#define RCC_LCDCPIXELCLK_AXIDIV4 (RCC_AXIDIV1_LCDCAXIDIV_DIV4 ) +#define RCC_LCDCPIXELCLK_AXIDIV8 (RCC_AXIDIV1_LCDCAXIDIV_DIV8 ) +#define RCC_LCDCPIXELCLK_AXIDIV16 (RCC_AXIDIV1_LCDCAXIDIV_DIV16 ) +#define RCC_LCDCPIXELCLK_AXIDIV32 (RCC_AXIDIV1_LCDCAXIDIV_DIV32 ) +#define RCC_LCDCPIXELCLK_AXIDIV64 (RCC_AXIDIV1_LCDCAXIDIV_DIV64 ) +#define RCC_LCDCPIXELCLK_AXIDIV128 (RCC_AXIDIV1_LCDCAXIDIV_DIV128) +#define RCC_LCDCPIXELCLK_AXIDIV256 (RCC_AXIDIV1_LCDCAXIDIV_DIV256) +#define RCC_LCDCPIXELCLK_AXIDIV512 (RCC_AXIDIV1_LCDCAXIDIV_DIV512) + +/** DVP values **/ +#define RCC_DVP1MCLK_SRC_MASK (~RCC_AXISEL1_DVP1MSEL) +#define RCC_DVP2MCLK_SRC_MASK (~RCC_AXISEL1_DVP2MSEL) +#define RCC_DVPMCLK_SRC_AXIDIV (RCC_AXISEL1_DVP1MSEL_AXIDIV) +#define RCC_DVPMCLK_SRC_PERIPH (RCC_AXISEL1_DVP1MSEL_PERIPH) +#define RCC_DVPMCLK_SRC_PLL2C (RCC_AXISEL1_DVP1MSEL_PLL2C ) +#define RCC_DVPMCLK_SRC_PLL3A (RCC_AXISEL1_DVP1MSEL_PLL3A ) + +#define RCC_DVPMCLK_AXIDIV_MASK (~RCC_AXIDIV1_DVPMAXIDIV ) +#define RCC_DVPMCLK_AXIDIV1 (RCC_AXIDIV1_DVPMAXIDIV_DIV1 ) +#define RCC_DVPMCLK_AXIDIV2 (RCC_AXIDIV1_DVPMAXIDIV_DIV2 ) +#define RCC_DVPMCLK_AXIDIV4 (RCC_AXIDIV1_DVPMAXIDIV_DIV4 ) +#define RCC_DVPMCLK_AXIDIV8 (RCC_AXIDIV1_DVPMAXIDIV_DIV8 ) +#define RCC_DVPMCLK_AXIDIV16 (RCC_AXIDIV1_DVPMAXIDIV_DIV16 ) +#define RCC_DVPMCLK_AXIDIV32 (RCC_AXIDIV1_DVPMAXIDIV_DIV32 ) +#define RCC_DVPMCLK_AXIDIV64 (RCC_AXIDIV1_DVPMAXIDIV_DIV64 ) +#define RCC_DVPMCLK_AXIDIV128 (RCC_AXIDIV1_DVPMAXIDIV_DIV128) +#define RCC_DVPMCLK_AXIDIV256 (RCC_AXIDIV1_DVPMAXIDIV_DIV256) +#define RCC_DVPMCLK_AXIDIV512 (RCC_AXIDIV1_DVPMAXIDIV_DIV512) +/** XSPI values **/ +#define RCC_XSPI1SSICLK_SRC_MASK (~RCC_AXISEL1_XSPI1SSISEL ) +#define RCC_XSPI2SSICLK_SRC_MASK (~RCC_AXISEL1_XSPI2SSISEL ) +#define RCC_XSPISSICLK_SRC_AXI (RCC_AXISEL1_XSPI1SSISEL_AXI ) +#define RCC_XSPISSICLK_SRC_PLL3C (RCC_AXISEL1_XSPI1SSISEL_PLL3C) +#define RCC_XSPISSICLK_SRC_PLL1B (RCC_AXISEL1_XSPI1SSISEL_PLL1B) +#define RCC_XSPISSICLK_SRC_PLL2A (RCC_AXISEL1_XSPI1SSISEL_PLL2A) +#define RCC_XSPISSICLK_SRC_PLL2C (RCC_AXISEL1_XSPI1SSISEL_PLL2C) + +/** SDRAM values **/ +#define RCC_SDRAMMEMCLK_SRC_MASK (~RCC_AXISEL2_SDRAMMEMSEL) +#define RCC_SDRAMMEMCLK_SRC_AXIDIV (RCC_AXISEL2_SDRAMMEMSEL_AXIDIV) +#define RCC_SDRAMMEMCLK_SRC_PERIPH (RCC_AXISEL2_SDRAMMEMSEL_PERIPH) +#define RCC_SDRAMMEMCLK_SRC_PLL2A (RCC_AXISEL2_SDRAMMEMSEL_PLL2A ) +#define RCC_SDRAMMEMCLK_SRC_PLL3A (RCC_AXISEL2_SDRAMMEMSEL_PLL3A ) +#define RCC_SDRAMMEMCLK_SRC_PLL1B (RCC_AXISEL2_SDRAMMEMSEL_PLL1B ) + +#define RCC_SDRAMMEMCLK_AXIDIV_MASK (~RCC_AXIDIV2_SDRAMMEMDIV ) +#define RCC_SDRAMMEMCLK_AXIDIV1 (RCC_AXIDIV2_SDRAMMEMDIV_DIV1 ) +#define RCC_SDRAMMEMCLK_AXIDIV2 (RCC_AXIDIV2_SDRAMMEMDIV_DIV2 ) +#define RCC_SDRAMMEMCLK_AXIDIV4 (RCC_AXIDIV2_SDRAMMEMDIV_DIV4 ) +#define RCC_SDRAMMEMCLK_AXIDIV8 (RCC_AXIDIV2_SDRAMMEMDIV_DIV8 ) +#define RCC_SDRAMMEMCLK_AXIDIV16 (RCC_AXIDIV2_SDRAMMEMDIV_DIV16 ) +#define RCC_SDRAMMEMCLK_AXIDIV32 (RCC_AXIDIV2_SDRAMMEMDIV_DIV32 ) +#define RCC_SDRAMMEMCLK_AXIDIV64 (RCC_AXIDIV2_SDRAMMEMDIV_DIV64 ) +#define RCC_SDRAMMEMCLK_AXIDIV128 (RCC_AXIDIV2_SDRAMMEMDIV_DIV128) +#define RCC_SDRAMMEMCLK_AXIDIV256 (RCC_AXIDIV2_SDRAMMEMDIV_DIV256) +#define RCC_SDRAMMEMCLK_AXIDIV512 (RCC_AXIDIV2_SDRAMMEMDIV_DIV512) + +/** ETHERCAT values **/ +#define RCC_ESCKERCLK_SRC_MASK (~RCC_AHB9SEL1_ESCKERSEL) +#define RCC_ESCKERCLK_SRC_SYSBUSDIV (RCC_AHB9SEL1_ESCKERSEL_SYSBUSDIV) +#define RCC_ESCKERCLK_SRC_PLL2B (RCC_AHB9SEL1_ESCKERSEL_PLL2B ) +#define RCC_ESCKERCLK_SRC_PLL3A (RCC_AHB9SEL1_ESCKERSEL_PLL3A ) +#define RCC_ESCKERCLK_SRC_PLL3C (RCC_AHB9SEL1_ESCKERSEL_PLL3C ) +#define RCC_ESCKERCLK_SRC_PLL1B (RCC_AHB9SEL1_ESCKERSEL_PLL1B ) + +#define RCC_ESCKERCLK_SYSBUSDIV_MASK (~RCC_AHB9DIV1_ESCSYSDIV ) +#define RCC_ESCKERCLK_SYSBUSDIV1 (RCC_AHB9DIV1_ESCSYSDIV_DIV1 ) +#define RCC_ESCKERCLK_SYSBUSDIV2 (RCC_AHB9DIV1_ESCSYSDIV_DIV2 ) +#define RCC_ESCKERCLK_SYSBUSDIV4 (RCC_AHB9DIV1_ESCSYSDIV_DIV4 ) +#define RCC_ESCKERCLK_SYSBUSDIV8 (RCC_AHB9DIV1_ESCSYSDIV_DIV8 ) +#define RCC_ESCKERCLK_SYSBUSDIV16 (RCC_AHB9DIV1_ESCSYSDIV_DIV16 ) +#define RCC_ESCKERCLK_SYSBUSDIV32 (RCC_AHB9DIV1_ESCSYSDIV_DIV32 ) +#define RCC_ESCKERCLK_SYSBUSDIV64 (RCC_AHB9DIV1_ESCSYSDIV_DIV64 ) +#define RCC_ESCKERCLK_SYSBUSDIV128 (RCC_AHB9DIV1_ESCSYSDIV_DIV128) +#define RCC_ESCKERCLK_SYSBUSDIV256 (RCC_AHB9DIV1_ESCSYSDIV_DIV256) +#define RCC_ESCKERCLK_SYSBUSDIV512 (RCC_AHB9DIV1_ESCSYSDIV_DIV512) +/** SDPU system clock DIV values **/ +#define RCC_TRNG_ENABLE (RCC_CFG5_TRNGEN ) + +#define RCC_TRNGCLK_SRC_MASK (~RCC_CFG5_TRNGSEL ) +#define RCC_TRNGCLK_SRC_SYSBUSDIV (RCC_REG_BIT_MASK ) +#define RCC_TRNGCLK_SRC_HSI (RCC_CFG5_TRNGSEL ) + +#define RCC_TRNGCLK_SYSBUSDIV_MASK (~RCC_CFG5_TRNGDIV ) +#define RCC_TRNGCLK_SYSBUSDIV1 (RCC_CFG5_TRNGDIV_DIV1 ) +#define RCC_TRNGCLK_SYSBUSDIV2 (RCC_CFG5_TRNGDIV_DIV2 ) +#define RCC_TRNGCLK_SYSBUSDIV4 (RCC_CFG5_TRNGDIV_DIV4 ) +#define RCC_TRNGCLK_SYSBUSDIV8 (RCC_CFG5_TRNGDIV_DIV8 ) +#define RCC_TRNGCLK_SYSBUSDIV16 (RCC_CFG5_TRNGDIV_DIV16 ) +#define RCC_TRNGCLK_SYSBUSDIV32 (RCC_CFG5_TRNGDIV_DIV32 ) +#define RCC_TRNGCLK_SYSBUSDIV64 (RCC_CFG5_TRNGDIV_DIV64 ) +#define RCC_TRNGCLK_SYSBUSDIV128 (RCC_CFG5_TRNGDIV_DIV128) +#define RCC_TRNGCLK_SYSBUSDIV256 (RCC_CFG5_TRNGDIV_DIV256) +#define RCC_TRNGCLK_SYSBUSDIV512 (RCC_CFG5_TRNGDIV_DIV512) + + +/** MCO1 clock selection register **/ +#define RCC_MCO1_SRC_MASK (~RCC_CFG3_MCO1SEL ) +#define RCC_MCO1_SRC_LSI (RCC_CFG3_MCO1SEL_LSI ) +#define RCC_MCO1_SRC_HSI (RCC_CFG3_MCO1SEL_HSI ) +#define RCC_MCO1_SRC_MSI (RCC_CFG3_MCO1SEL_MSI ) +#define RCC_MCO1_SRC_LSE (RCC_CFG3_MCO1SEL_LSE ) +#define RCC_MCO1_SRC_HSE (RCC_CFG3_MCO1SEL_HSE ) +#define RCC_MCO1_SRC_PLL3B (RCC_CFG3_MCO1SEL_PLL3B) + +/** MCO1 clock prescalar values **/ +#define RCC_MCO1_DIV_MASK (~RCC_CFG3_MCO1DIV ) +#define RCC_MCO1_DIV1 (RCC_CFG3_MCO1DIV_DIV1 ) +#define RCC_MCO1_DIV2 (RCC_CFG3_MCO1DIV_DIV2 ) +#define RCC_MCO1_DIV4 (RCC_CFG3_MCO1DIV_DIV4 ) +#define RCC_MCO1_DIV8 (RCC_CFG3_MCO1DIV_DIV8 ) +#define RCC_MCO1_DIV16 (RCC_CFG3_MCO1DIV_DIV16 ) +#define RCC_MCO1_DIV32 (RCC_CFG3_MCO1DIV_DIV32 ) +#define RCC_MCO1_DIV64 (RCC_CFG3_MCO1DIV_DIV64 ) +#define RCC_MCO1_DIV128 (RCC_CFG3_MCO1DIV_DIV128) + +/** MCO2 clock selection register **/ +#define RCC_MCO2_SRC_MASK (~RCC_CFG3_MCO2SEL ) +#define RCC_MCO2_SRC_SYSCLK (RCC_CFG3_MCO2SEL_SYSCLK) +#define RCC_MCO2_SRC_PLL1A (RCC_CFG3_MCO2SEL_PLL1A) +#define RCC_MCO2_SRC_PLL2A (RCC_CFG3_MCO2SEL_PLL2A) +#define RCC_MCO2_SRC_PLL3A (RCC_CFG3_MCO2SEL_PLL3A) +#define RCC_MCO2_SRC_SHRPLL (RCC_CFG3_MCO2SEL_SHRPLL) +#define RCC_MCO2_SRC_LSE (RCC_CFG3_MCO2SEL_LSE) + + +/** MCO2 clock prescalar values **/ +#define RCC_MCO2_DIV_MASK (~RCC_CFG3_MCO2DIV ) +#define RCC_MCO2_DIV1 (RCC_CFG3_MCO2DIV_DIV1 ) +#define RCC_MCO2_DIV2 (RCC_CFG3_MCO2DIV_DIV2 ) +#define RCC_MCO2_DIV4 (RCC_CFG3_MCO2DIV_DIV4 ) +#define RCC_MCO2_DIV8 (RCC_CFG3_MCO2DIV_DIV8 ) +#define RCC_MCO2_DIV16 (RCC_CFG3_MCO2DIV_DIV16 ) +#define RCC_MCO2_DIV32 (RCC_CFG3_MCO2DIV_DIV32 ) +#define RCC_MCO2_DIV64 (RCC_CFG3_MCO2DIV_DIV64 ) +#define RCC_MCO2_DIV128 (RCC_CFG3_MCO2DIV_DIV128) + +#define RCC_STOPEN_FDCAN1 (RCC_APB1EN5_FDCAN1STPREQ) +#define RCC_STOPEN_FDCAN2 (RCC_APB1EN5_FDCAN2STPREQ) +#define RCC_STOPEN_FDCAN5 (RCC_APB1EN5_FDCAN5STPREQ) +#define RCC_STOPEN_FDCAN6 (RCC_APB1EN5_FDCAN6STPREQ) +#define RCC_STOPEN_FDCAN3 (RCC_APB2EN4_FDCAN3STPREQ) +#define RCC_STOPEN_FDCAN4 (RCC_APB2EN4_FDCAN4STPREQ) +#define RCC_STOPEN_FDCAN7 (RCC_APB2EN4_FDCAN7STPREQ) +#define RCC_STOPEN_FDCAN8 (RCC_APB2EN4_FDCAN8STPREQ) + +#define RCC_FLAG_STOPACK_FDCAN1 (RCC_APB1EN5_FDCAN1STPACK) +#define RCC_FLAG_STOPACK_FDCAN2 (RCC_APB1EN5_FDCAN2STPACK) +#define RCC_FLAG_STOPACK_FDCAN5 (RCC_APB1EN5_FDCAN5STPACK) +#define RCC_FLAG_STOPACK_FDCAN6 (RCC_APB1EN5_FDCAN6STPACK) +#define RCC_FLAG_STOPACK_FDCAN3 (RCC_APB2EN4_FDCAN3STPACK) +#define RCC_FLAG_STOPACK_FDCAN4 (RCC_APB2EN4_FDCAN4STPACK) +#define RCC_FLAG_STOPACK_FDCAN7 (RCC_APB2EN4_FDCAN7STPACK) +#define RCC_FLAG_STOPACK_FDCAN8 (RCC_APB2EN4_FDCAN8STPACK) + +#define RCC_INT_LSECSS (RCC_CLKINT1_LSECSSIF) +#define RCC_INT_HSECSS (RCC_CLKINT1_HSECSSIF) +#define RCC_INT_BOR (RCC_CLKINT1_BORIF) +#define RCC_INT_PLL1RD (RCC_CLKINT1_PLL1RDIF) +#define RCC_INT_PLL2RD (RCC_CLKINT1_PLL2RDIF) +#define RCC_INT_PLL3RD (RCC_CLKINT1_PLL3RDIF) +#define RCC_INT_SHRPLLRD (RCC_CLKINT1_SHRPLLRDIF) + +#define RCC_INT_HSERD (RCC_CLKINT2_HSERDIF) +#define RCC_INT_HSIRD (RCC_CLKINT2_HSIRDIF) +#define RCC_INT_MSIRD (RCC_CLKINT2_MSIRDIF) +#define RCC_INT_LSERD (RCC_CLKINT2_LSERDIF) +#define RCC_INT_LSIRD (RCC_CLKINT2_LSIRDIF) +#define RCC_INT_HSICALE (RCC_CLKINT2_HSICALEIF) +#define RCC_INT_MSICALE (RCC_CLKINT2_MSICALEIF) + +#define RCC_INT_PLL1LKF (RCC_CLKINT3_PLL1LKFIF) +#define RCC_INT_PLL2LKF (RCC_CLKINT3_PLL2LKFIF) +#define RCC_INT_PLL3LKF (RCC_CLKINT3_PLL3LKFIF) +#define RCC_INT_SHRPLLLKF (RCC_CLKINT3_SHRPLLLKFIF) +#define RCC_INT_LSIF (RCC_CLKINT3_LSIFIF) + +#define RCC_RSTEN_WWDG1 (RCC_CFG1_WWDG1RSTEN ) +#define RCC_RSTEN_WWDG2 (RCC_CFG1_WWDG2RSTEN ) +#define RCC_RSTEN_BOR (RCC_BDCTRL_BORRSTEN ) +#define RCC_RSTEN_C1LP (RCC_BDCTRL_C1LPRSTEN ) +#define RCC_RSTEN_C2LP (RCC_BDCTRL_C2LPRSTEN ) +#define RCC_RSTEN_BKPEMC (RCC_BDCTRL_BKPEMCRSTEN) +#define RCC_RSTEN_RETEMC (RCC_BDCTRL_RETEMCRSTEN) + +/** source values **/ +#define RCC_HSITRIM_MASK (~RCC_SRCCTRL3_HSITRIM) +#define RCC_MSITRIM_MASK (~RCC_SRCCTRL2_MSITRIM) +#define RCC_HSECSS_ENABLE (RCC_SRCCTRL1_HSECSSEN) + +#define RCC_LSI_SRCCTRL_BY_SOFTWARE (RCC_BDCTRL_LSIOVREN) +#define RCC_LSI_SRCCTRL_BY_HARDWARE (~RCC_BDCTRL_LSIOVREN) +#define RCC_LSICSS_ENABLE (RCC_BDCTRL_LSICSSEN) +#define RCC_LSI_FAILACK_ENABLE (RCC_BDCTRL_LSIPFACK) + +#define RCC_LSE_CALCNT_ENABLE (RCC_LSEOS_LSECALCNTEN) +#define RCC_LSE_CALCNT_MASK (RCC_LSEOS_LSECALCNT) + +#define RCC_FLAG_LSECSS_CALCNTRD (RCC_LSEOS_LSECALCNTF) +#define RCC_FLAG_LSECSS_OFFSET (RCC_LSEOS_LSEOSF) + +#define RCC_LSE_OFFSET_ENABLE (RCC_LSEOS_LSEOSEN) +#define RCC_LSEOSTHR_MASK (~RCC_LSEOS_LSEOSTHR) + +#define RCC_HSE_CALCNT_ENABLE (RCC_HSECAL_HSECALCNTEN) +#define RCC_HSE_CALCNT_MASK (RCC_HSECAL_HSECALCNT) + +#define RCC_FLAG_HSECSS_CALCNTRD (RCC_HSECAL_HSECALCNTF) +#define RCC_FLAG_HSECSS_OFFSET (RCC_HSEOS_HSEOSF) +#define RCC_FLAG_HSECSS_MAXPD (RCC_HSEOS_HSEMAXPDF) +#define RCC_FLAG_HSECSS_MINND (RCC_HSEOS_HSEMINNDF) + +#define RCC_HSECSS_OFFSET (RCC_HSEOS_HSEOSEN) +#define RCC_HSECSS_MAXPD (RCC_HSEOS_HSEMAXPDEN) +#define RCC_HSECSS_MINND (RCC_HSEOS_HSEMINNDEN) + +#define RCC_HSEOSTHR_MASK (~RCC_HSEOS_HSEOSTHR) +#define RCC_HSEMAXPDTHR_MASK (~RCC_HSEOS_HSEMAXPDTHR) +#define RCC_HSEMINNDTHR_MASK (~RCC_HSEOS_HSEMINNDTHR) + +#define RCC_FAIL_DETECT_EN_SHRPLL (RCC_PLLFD_SHRPLLFEN) +#define RCC_FAIL_DETECT_EN_PLL3 (RCC_PLLFD_PLL3FEN) +#define RCC_FAIL_DETECT_EN_PLL2 (RCC_PLLFD_PLL2FEN) +#define RCC_FAIL_DETECT_EN_PLL1 (RCC_PLLFD_PLL1FEN) + +/** LPTIM filter values **/ +#define RCC_LPTIM1FILT_ENABLE (RCC_RDCTRL1_LPTIM1FLTEN) +#define RCC_LPTIM1_FILTCLK_SRC_MSI (RCC_RDCTRL1_LPTIM1FLTSEL) +#define RCC_LPTIM1_FILTCLK_SRC_APB5 (~RCC_RDCTRL1_LPTIM1FLTSEL) +#define I2C_LPTIM1FLTDFC_MASK (~RCC_RDCTRL1_LPTIM1FLTDFC) + +#define RCC_LPTIM2FILT_ENABLE (RCC_RDCTRL1_LPTIM2FLTEN) +#define RCC_LPTIM2_FILTCLK_SRC_MSI (RCC_RDCTRL1_LPTIM2FLTSEL) +#define RCC_LPTIM2_FILTCLK_SRC_APB5 (~RCC_RDCTRL1_LPTIM2FLTSEL) +#define I2C_LPTIM2FLTDFC_MASK (~RCC_RDCTRL1_LPTIM2FLTDFC) + +#define RCC_LPTIM3FILT_ENABLE (RCC_RDCTRL2_LPTIM3FLTEN) +#define RCC_LPTIM3_FILTCLK_SRC_MSI (RCC_RDCTRL2_LPTIM3FLTSEL) +#define RCC_LPTIM3_FILTCLK_SRC_APB5 (~RCC_RDCTRL2_LPTIM3FLTSEL) +#define I2C_LPTIM3FLTDFC_MASK (~RCC_RDCTRL2_LPTIM3FLTDFC) + +#define RCC_LPTIM4FILT_ENABLE (RCC_RDCTRL2_LPTIM4FLTEN) +#define RCC_LPTIM4_FILTCLK_SRC_MSI (RCC_RDCTRL2_LPTIM4FLTSEL) +#define RCC_LPTIM4_FILTCLK_SRC_APB5 (~RCC_RDCTRL2_LPTIM4FLTSEL) +#define I2C_LPTIM4FLTDFC_MASK (~RCC_RDCTRL2_LPTIM4FLTDFC) + +#define RCC_LPTIM5FILT_ENABLE (RCC_RDCTRL3_LPTIM5FLTEN) +#define RCC_LPTIM5_FILTCLK_SRC_MSI (RCC_RDCTRL3_LPTIM5FLTSEL) +#define RCC_LPTIM5_FILTCLK_SRC_APB5 (~RCC_RDCTRL3_LPTIM5FLTSEL) +#define I2C_LPTIM5FLTDFC_MASK (~RCC_RDCTRL3_LPTIM5FLTDFC) + +#define RCC_WWDG1RSTDLCNT_MASK (~RCC_CFG1_WWDG1RSTDLCNT) +#define RCC_WWDG2RSTDLCNT_MASK (~RCC_CFG1_WWDG2RSTDLCNT) + +#define RCC_M7TRACECLK_DIV_MASK (~RCC_CFG1_M7TRACEDIV) +#define RCC_M4TRACECLK_DIV_MASK (~RCC_CFG1_M4TRACEDIV) +#define RCC_TRACECLK_DIV1 (RCC_CFG1_M7TRACEDIV_DIV1 ) +#define RCC_TRACECLK_DIV2 (RCC_CFG1_M7TRACEDIV_DIV2 ) +#define RCC_TRACECLK_DIV4 (RCC_CFG1_M7TRACEDIV_DIV4 ) +#define RCC_TRACECLK_DIV8 (RCC_CFG1_M7TRACEDIV_DIV8 ) +#define RCC_TRACECLK_DIV16 (RCC_CFG1_M7TRACEDIV_DIV16 ) +#define RCC_TRACECLK_DIV32 (RCC_CFG1_M7TRACEDIV_DIV32 ) +#define RCC_TRACECLK_DIV64 (RCC_CFG1_M7TRACEDIV_DIV64 ) +#define RCC_TRACECLK_DIV128 (RCC_CFG1_M7TRACEDIV_DIV128) +#define RCC_TRACECLK_DIV256 (RCC_CFG1_M7TRACEDIV_DIV256) +#define RCC_TRACECLK_DIV512 (RCC_CFG1_M7TRACEDIV_DIV512) + +#define RCC_M7STCLK_DIV_MASK (~RCC_CFG3_M7STCLKDIV) +#define RCC_M4STCLK_DIV_MASK (~RCC_CFG3_M4STCLKDIV) +#define RCC_STCLK_DIV1 (RCC_CFG3_M7STCLKDIV_DIV1 ) +#define RCC_STCLK_DIV2 (RCC_CFG3_M7STCLKDIV_DIV2 ) +#define RCC_STCLK_DIV4 (RCC_CFG3_M7STCLKDIV_DIV4 ) +#define RCC_STCLK_DIV8 (RCC_CFG3_M7STCLKDIV_DIV8 ) +#define RCC_STCLK_DIV16 (RCC_CFG3_M7STCLKDIV_DIV16 ) +#define RCC_STCLK_DIV32 (RCC_CFG3_M7STCLKDIV_DIV32 ) +#define RCC_STCLK_DIV64 (RCC_CFG3_M7STCLKDIV_DIV64 ) +#define RCC_STCLK_DIV128 (RCC_CFG3_M7STCLKDIV_DIV128) +#define RCC_STCLK_DIV256 (RCC_CFG3_M7STCLKDIV_DIV256) +#define RCC_STCLK_DIV512 (RCC_CFG3_M7STCLKDIV_DIV512) + +#define RCC_DUALCORE_DBG_ENABLE (RCC_CFG5_DCDCLKEN) + +#define RCC_RTCCLK_HSIDIV_MASK (~RCC_CFG5_RTCHSIDIV) +#define RCC_RTCCLK_HSIDIV1 (RCC_CFG5_RTCHSIDIV_DIV1 ) +#define RCC_RTCCLK_HSIDIV2 (RCC_CFG5_RTCHSIDIV_DIV2 ) +#define RCC_RTCCLK_HSIDIV4 (RCC_CFG5_RTCHSIDIV_DIV4 ) +#define RCC_RTCCLK_HSIDIV8 (RCC_CFG5_RTCHSIDIV_DIV8 ) +#define RCC_RTCCLK_HSIDIV16 (RCC_CFG5_RTCHSIDIV_DIV16 ) +#define RCC_RTCCLK_HSIDIV32 (RCC_CFG5_RTCHSIDIV_DIV32 ) +#define RCC_RTCCLK_HSIDIV64 (RCC_CFG5_RTCHSIDIV_DIV64 ) +#define RCC_RTCCLK_HSIDIV128 (RCC_CFG5_RTCHSIDIV_DIV128) +#define RCC_RTCCLK_HSIDIV256 (RCC_CFG5_RTCHSIDIV_DIV256) +#define RCC_RTCCLK_HSIDIV512 (RCC_CFG5_RTCHSIDIV_DIV512) + +#define RCC_SOFTLOCK_EN_SHRPLL (RCC_PLLSFTLK_SHRPLLSFTLK) +#define RCC_SOFTLOCK_EN_PLL3 (RCC_PLLSFTLK_PLL3SFTLK ) +#define RCC_SOFTLOCK_EN_PLL2 (RCC_PLLSFTLK_PLL2SFTLK ) +#define RCC_SOFTLOCK_EN_PLL1 (RCC_PLLSFTLK_PLL1SFTLK ) + +#define RCC_SHRTIMAFE_RESET_ENABLE (RCC_PLLSFTLK_SHRTIMAFERST ) +#define RCC_SDRAM_DELAY_ENABLE (RCC_PLLSFTLK_SDRAMDLEN ) + +#define RCC_SDRAM_DELAY_MASK (~RCC_PLLSFTLK_SDRAMDLSEL ) +#define RCC_SDRAM_DELAY_0_2NS (RCC_PLLSFTLK_SDRAMDLSEL_0_2NS) +#define RCC_SDRAM_DELAY_0_4NS (RCC_PLLSFTLK_SDRAMDLSEL_0_4NS) +#define RCC_SDRAM_DELAY_0_6NS (RCC_PLLSFTLK_SDRAMDLSEL_0_6NS) +#define RCC_SDRAM_DELAY_0_8NS (RCC_PLLSFTLK_SDRAMDLSEL_0_8NS) +#define RCC_SDRAM_DELAY_1_0NS (RCC_PLLSFTLK_SDRAMDLSEL_1_0NS) +#define RCC_SDRAM_DELAY_1_2NS (RCC_PLLSFTLK_SDRAMDLSEL_1_2NS) +#define RCC_SDRAM_DELAY_1_4NS (RCC_PLLSFTLK_SDRAMDLSEL_1_4NS) +#define RCC_SDRAM_DELAY_1_6NS (RCC_PLLSFTLK_SDRAMDLSEL_1_6NS) +#define RCC_SDRAM_DELAY_1_8NS (RCC_PLLSFTLK_SDRAMDLSEL_1_8NS) +#define RCC_SDRAM_DELAY_2_0NS (RCC_PLLSFTLK_SDRAMDLSEL_2_0NS) +#define RCC_SDRAM_DELAY_2_2NS (RCC_PLLSFTLK_SDRAMDLSEL_2_2NS) +#define RCC_SDRAM_DELAY_2_4NS (RCC_PLLSFTLK_SDRAMDLSEL_2_4NS) +#define RCC_SDRAM_DELAY_2_6NS (RCC_PLLSFTLK_SDRAMDLSEL_2_6NS) +#define RCC_SDRAM_DELAY_2_8NS (RCC_PLLSFTLK_SDRAMDLSEL_2_8NS) +#define RCC_SDRAM_DELAY_3_0NS (RCC_PLLSFTLK_SDRAMDLSEL_3_0NS) +#define RCC_SDRAM_DELAY_3_2NS (RCC_PLLSFTLK_SDRAMDLSEL_3_2NS) + +void RCC_DeInit(void); +void RCC_ConfigHse(uint32_t RCC_HSE); +void RCC_EnableHsi(FunctionalState Cmd); +void RCC_EnableMsi(FunctionalState Cmd); +void RCC_ConfigLse(uint32_t RCC_LSE); +void RCC_EnableLsi(FunctionalState Cmd); +void RCC_EnableSecondaryLsi(FunctionalState Cmd); +void RCC_ConfigSysclk(uint32_t sysclk_source); +uint32_t RCC_GetSysclkSrc(void); +void RCC_ConfigHSIclkDivider(uint32_t CLK_divider); +void RCC_ConfigMSIclkDivider(uint32_t CLK_divider); +void RCC_ConfigM7Clk(uint32_t CLK_source); +void RCC_ConfigAXIClk(uint32_t CLK_source); +void RCC_ConfigPLL1CDivider(uint32_t CLK_divider); +void RCC_ConfigPLL1BDivider(uint32_t CLK_divider); +void RCC_ConfigPLL1ADivider(uint32_t CLK_divider); +void RCC_ConfigPLL2CDivider(uint32_t CLK_divider); +void RCC_ConfigPLL2BDivider(uint32_t CLK_divider); +void RCC_ConfigPLL2ADivider(uint32_t CLK_divider); +void RCC_ConfigPLL3CDivider(uint32_t CLK_divider); +void RCC_ConfigPLL3BDivider(uint32_t CLK_divider); +void RCC_ConfigPLL3ADivider(uint32_t CLK_divider); +void RCC_ConfigAXIHyperDivider(uint32_t CLK_divider); +void RCC_ConfigM7HyperDivider(uint32_t CLK_divider); +void RCC_ConfigAXIclkDivider(uint32_t CLK_divider); +void RCC_ConfigSysbusDivider(uint32_t CLK_divider); +void RCC_ConfigSysclkDivider(uint32_t CLK_divider); +void RCC_ConfigAPBclkDivider(uint32_t APB1_divider, uint32_t APB2_divider, uint32_t APB5_divider, uint32_t APB6_divider); +void RCC_EnableAHB1PeriphReset1(uint32_t AHB_periph); +void RCC_EnableAHB1PeriphReset2(uint32_t AHB_periph); +void RCC_EnableAHB1PeriphReset3(uint32_t AHB_periph); +void RCC_EnableAHB1PeriphReset4(uint32_t AHB_periph); +void RCC_EnableAPB1PeriphReset1(uint32_t APB_periph); +void RCC_EnableAPB1PeriphReset2(uint32_t APB_periph); +void RCC_EnableAPB1PeriphReset3(uint32_t APB_periph); +void RCC_EnableAPB1PeriphReset4(uint32_t APB_periph); +void RCC_EnableAPB1PeriphReset5(uint32_t APB_periph); +void RCC_EnableAHB2PeriphReset1(uint32_t AHB_periph); +void RCC_EnableAPB2PeriphReset1(uint32_t APB_periph); +void RCC_EnableAPB2PeriphReset2(uint32_t APB_periph); +void RCC_EnableAPB2PeriphReset3(uint32_t APB_periph); +void RCC_EnableAPB2PeriphReset4(uint32_t APB_periph); +void RCC_EnableAHB5PeriphReset1(uint32_t AHB_periph); +void RCC_EnableAHB5PeriphReset2(uint32_t AHB_periph); +void RCC_EnableAPB5PeriphReset1(uint32_t APB_periph); +void RCC_EnableAPB5PeriphReset2(uint32_t APB_periph); +void RCC_EnableAXIPeriphReset1(uint32_t AXI_periph); +void RCC_EnableAXIPeriphReset2(uint32_t AXI_periph); +void RCC_EnableAXIPeriphReset3(uint32_t AXI_periph); +void RCC_EnableAXIPeriphReset4(uint32_t AXI_periph); +void RCC_EnableAHB9PeriphReset1(uint32_t AHB_periph); +void RCC_EnableRDPeriphReset1(uint32_t RD_periph); +void RCC_EnableRDPeriphReset2(uint32_t RD_periph); +void RCC_EnableAHB1PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAHB1PeriphClk2(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAHB1PeriphClk3(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAHB1PeriphClk4(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk1(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk2(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk3(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk4(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB1PeriphClk5(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAHB2PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAHB2PeriphClk2(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk1(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk2(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk3(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB2PeriphClk4(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAHB5PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAHB5PeriphClk2(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableAPB5PeriphClk1(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAPB5PeriphClk2(uint32_t APB_periph, FunctionalState Cmd); +void RCC_EnableAHB9PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd); +void RCC_EnableRDPeriphClk1(uint32_t RD_periph, FunctionalState Cmd); +void RCC_EnableRDPeriphClk2(uint32_t RD_periph, FunctionalState Cmd); +void RCC_EnableAXIPeriphClk1(uint32_t AXI_periph, FunctionalState Cmd); +void RCC_EnableAXIPeriphClk2(uint32_t AXI_periph, FunctionalState Cmd); +void RCC_EnableAXIPeriphClk3(uint32_t AXI_periph, FunctionalState Cmd); +void RCC_EnableAXIPeriphClk4(uint32_t AXI_periph, FunctionalState Cmd); +void RCC_ConfigETH2PtpClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigETH1PtpClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigETH1GMIITXClk(uint32_t CLK_source); +void RCC_ConfigSDMMC2KerClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigSDMMC1KerClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigDSMUKerClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigDSMUKerAClk(uint32_t CLK_source, uint32_t CLK_pinsel); +void RCC_ConfigUSBRefClk(uint32_t CLK_divider); +void RCC_ConfigAdc1PllClk(uint32_t CLK_source); +void RCC_ConfigAdc1SysClk(uint32_t CLK_divider); +void RCC_ConfigAdc2PllClk(uint32_t CLK_source); +void RCC_ConfigAdc2SysClk(uint32_t CLK_divider); +void RCC_ConfigAdc3PllClk(uint32_t CLK_source); +void RCC_ConfigAdc3SysClk(uint32_t CLK_divider); +void RCC_ConfigBTIMKerClk(uint32_t CLK_divider); +void RCC_ConfigGTIMA1_3_KerClk(uint32_t CLK_divider); +void RCC_ConfigGTIMA4_7_KerClk(uint32_t CLK_divider); +void RCC_ConfigGTIMB1_3_KerClk(uint32_t CLK_divider); +void RCC_ConfigATIM1_2_KerClk(uint32_t CLK_divider); +void RCC_ConfigATIM3_4_KerClk(uint32_t CLK_divider); +void RCC_ConfigUSARTPClk(uint32_t CLK_divider); +void RCC_ConfigI2S1KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2S2KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2S1_2_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigI2S3KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2S4KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2S3_4_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigI2C1KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C2KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C3KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C1_3_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigI2C4KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C5KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C6KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C4_6_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigI2C7KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C8KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C9KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C10KerClkSource(uint32_t CLK_source); +void RCC_ConfigI2C7_10_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigFDCAN1KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN2KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN5KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN6KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN1_2_5_6_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigFDCAN3KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN4KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN7KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN8KerClkSource(uint32_t CLK_source); +void RCC_ConfigFDCAN3_4_7_8_KerSysDivider(uint32_t CLK_divider); +void RCC_ConfigEXTISysDivider(uint32_t CLK_divider); +void RCC_ConfigRtcClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_EnableRtcClk(FunctionalState Cmd); +void RCC_EnableBackupReset(void); +void RCC_EnableDCMUReset(void); +void RCC_ConfigLPTIM1Clk(uint32_t CLK_source); +void RCC_EnableLPTIM1CompGate(uint32_t COMP_sel, FunctionalState Cmd); +void RCC_ConfigLPTIM2Clk(uint32_t CLK_source); +void RCC_EnableLPTIM2CompGate(uint32_t COMP_sel, FunctionalState Cmd); +void RCC_ConfigLPTIM3Clk(uint32_t CLK_source); +void RCC_EnableLPTIM3CompGate(uint32_t COMP_sel, FunctionalState Cmd); +void RCC_ConfigLPTIM4Clk(uint32_t CLK_source); +void RCC_EnableLPTIM4CompGate(uint32_t COMP_sel, FunctionalState Cmd); +void RCC_ConfigLPTIM5Clk(uint32_t CLK_source); +void RCC_EnableLPTIM5CompGate(uint32_t COMP_sel, FunctionalState Cmd); +void RCC_ConfigLPUART1ClkSource(uint32_t CLK_source); +void RCC_ConfigLPUART2ClkSource(uint32_t CLK_source); +void RCC_ConfigLPUART1_2_ClkDivider(uint32_t CLK_divider); +void RCC_ConfigCOMPLsxClk(uint32_t CLK_source); +void RCC_ConfigCOMPKerClk(uint32_t CLK_divider); +void RCC_ConfigFEMCM0Clk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigFEMCM1Clk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigDSIRefClk(uint32_t CLK_divider); +void RCC_ConfigDSIKerClk(uint32_t CLK_source); +void RCC_ConfigDSIPpitxClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigDSIUlpsClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigLCDCPixelClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigDVP1MClkSource(uint32_t CLK_source); +void RCC_ConfigDVP2MClkSource(uint32_t CLK_source); +void RCC_ConfigDVP1_2_MClkDivider(uint32_t CLK_divider); +void RCC_ConfigXSPI1SSIClk(uint32_t CLK_source); +void RCC_ConfigXSPI2SSIClk(uint32_t CLK_source); +void RCC_ConfigSDRAMMemClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigETHERCATKerClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigTRNGClk(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_EnableTRNGClk(FunctionalState Cmd); +void RCC_EnableCFG2PeriphClk1(uint32_t CFG2_periph, FunctionalState Cmd); +void RCC_EnableCFG4PeriphClk1(uint32_t CFG4_periph, FunctionalState Cmd); +void RCC_EnableCFG5PeriphClk1(uint32_t CFG5_periph, FunctionalState Cmd); +void RCC_ConfigMco1(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_ConfigMco2(uint32_t CLK_source, uint32_t CLK_divider); +void RCC_EnableFDCANStopRequest1(uint32_t FDCAN_sel, FunctionalState Cmd); +void RCC_EnableFDCANStopRequest2(uint32_t FDCAN_sel, FunctionalState Cmd); +void RCC_ConfigPeriphClk(uint32_t CLK_source); +void RCC_EnableModuleResetRequest(uint32_t Module_sel, FunctionalState Cmd); +void RCC_ConfigInt1(uint32_t Interrupt, FunctionalState Cmd); +void RCC_ConfigInt2(uint32_t Interrupt, FunctionalState Cmd); +void RCC_ConfigInt3(uint32_t Interrupt, FunctionalState Cmd); +void RCC_ClrIntPendingBit1(uint32_t interrupt_clear); +void RCC_ClrIntPendingBit2(uint32_t interrupt_clear); +void RCC_ClrIntPendingBit3(uint32_t interrupt_clear); +void RCC_ClearResetFlag(void); +void RCC_EnableCM4(uint32_t CM4_BaseAddr); +void RCC_GetClocksFreqValue(RCC_ClocksTypeDef* RCC_Clocks); +ErrorStatus RCC_WaitHseStable(void); +ErrorStatus RCC_WaitHsiStable(void); +ErrorStatus RCC_WaitMsiStable(void); +ErrorStatus RCC_WaitLseStable(void); +ErrorStatus RCC_WaitLsiStable(void); +ErrorStatus RCC_WaitSecondaryLsiStable(void); +ErrorStatus RCC_CalculatePLLParam(uint64_t fin, uint64_t fout, uint32_t* nr, uint32_t* nf, uint32_t* wb); +ErrorStatus RCC_ConfigSHRPll(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd); +ErrorStatus RCC_ConfigPll1(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd); +ErrorStatus RCC_ConfigPll2(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd); +ErrorStatus RCC_ConfigPll3(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd); +ErrorStatus RCC_ConfigSHRPll_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd); +ErrorStatus RCC_ConfigPll1_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd); +ErrorStatus RCC_ConfigPll2_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd); +ErrorStatus RCC_ConfigPll3_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd); +FlagStatus RCC_GetFDCANStopAckFlag1(uint32_t RCC_flag); +FlagStatus RCC_GetFDCANStopAckFlag2(uint32_t RCC_flag); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_flag); +INTStatus RCC_GetIntStatus1(uint32_t interrupt_flag); +INTStatus RCC_GetIntStatus2(uint32_t interrupt_flag); +INTStatus RCC_GetIntStatus3(uint32_t interrupt_flag); +void RCC_SetSysClkToMode0(void); +void RCC_SetSysClkToMode1(void); +void RCC_SetSysClkToMode2(void); +void RCC_SetHsiCalibValue(uint16_t calibration_value); +void RCC_SetMsiCalibValue(uint16_t calibration_value); +void RCC_EnableHSEClockSecuritySystem(FunctionalState Cmd); +void RCC_SelectLSISourceControl(uint32_t CLK_source); +void RCC_EnableLSIClockSecuritySystem(FunctionalState Cmd); +void RCC_EnableLSIFailAcknowledge(FunctionalState Cmd); +void RCC_EnableLSECalibrationCount(FunctionalState Cmd); +void RCC_EnableLSEOffsetDetection(FunctionalState Cmd); +void RCC_SetLSEOffsetThreshold(uint8_t threshold_value); +void RCC_EnableHSECalibrationCount(FunctionalState Cmd); +void RCC_EnableHSECSSCheck(uint32_t Chk_type, FunctionalState Cmd); +void RCC_SetHSEOffsetThreshold(uint8_t threshold_value); +void RCC_SetHSEPositiveDeviationMAXThreshold(uint8_t threshold_value); +void RCC_SetHSENegativeDeviationMINThreshold(uint8_t threshold_value); +void RCC_SetLSICSSDelayValue(uint32_t delay_value); +void RCC_SetLSEReadyDelayValue(uint32_t delay_value); +void RCC_SetMSIReadyDelayValue(uint32_t delay_value); +void RCC_SetHSEReadyDelayValue(uint32_t delay_value); +void RCC_EnablePLLFailDetection(uint32_t Chk_type, FunctionalState Cmd); +void RCC_EnableLPTIM1Filter(FunctionalState Cmd); +void RCC_SelectLPTIM1FilterSource(uint32_t CLK_source); +void RCC_ConfigLPTIM1FilterWidth(uint8_t width_value); +void RCC_EnableLPTIM2Filter(FunctionalState Cmd); +void RCC_SelectLPTIM2FilterSource(uint32_t CLK_source); +void RCC_ConfigLPTIM2FilterWidth(uint8_t width_value); +void RCC_EnableLPTIM3Filter(FunctionalState Cmd); +void RCC_SelectLPTIM3FilterSource(uint32_t CLK_source); +void RCC_ConfigLPTIM3FilterWidth(uint8_t width_value); +void RCC_EnableLPTIM4Filter(FunctionalState Cmd); +void RCC_SelectLPTIM4FilterSource(uint32_t CLK_source); +void RCC_ConfigLPTIM4FilterWidth(uint8_t width_value); +void RCC_EnableLPTIM5Filter(FunctionalState Cmd); +void RCC_SelectLPTIM5FilterSource(uint32_t CLK_source); +void RCC_ConfigLPTIM5FilterWidth(uint8_t width_value); +void RCC_SetWWDG1ResetDelayValue(uint8_t delay_value); +void RCC_SetWWDG2ResetDelayValue(uint8_t delay_value); +void RCC_ConfigM7TraceClkDivider(uint32_t CLK_divider); +void RCC_ConfigM4TraceClkDivider(uint32_t CLK_divider); +void RCC_ConfigM7SystickClkDivider(uint32_t CLK_divider); +void RCC_ConfigM4SystickClkDivider(uint32_t CLK_divider); +void RCC_EnableDualCoreDebugClk(FunctionalState Cmd); +void RCC_ConfigRTCHSIClkDivider(uint32_t CLK_divider); +void RCC_EnablePLLSoftwareLock(uint32_t lock_type, FunctionalState Cmd); +void RCC_EnableSHRTIMAFEReset(FunctionalState Cmd); +void RCC_EnableSDRAMDelayChain(FunctionalState Cmd); +void RCC_ConfigSDRAMDelay(uint32_t CLK_delay); +void RCC_ConfigHSEDriveStrength(uint32_t CLK_driver); +uint8_t RCC_GetLSECalibrationCount(void); +FlagStatus RCC_GetLSECSSFlag(uint32_t RCC_flag); +uint16_t RCC_GetHSECalibrationCount(void); +FlagStatus RCC_GetHSECSSFlag(uint32_t RCC_flag); + + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_RCC_H */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rtc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rtc.h new file mode 100644 index 0000000000..b392e4dc3e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_rtc.h @@ -0,0 +1,455 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_rtc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_RTC_H__ +#define __N32H76X_78X_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** RTC Init structure definition **/ +typedef struct +{ + uint32_t RTC_HourFormat; /* Specifies the RTC Hour Format. */ + + uint32_t RTC_AsynchPrediv; /* Specifies the RTC Asynchronous Predivider value */ + + uint32_t RTC_SynchPrediv; /* Specifies the RTC Synchronous Predivider value */ +} RTC_InitType; + + +/** RTC Time structure definition **/ +typedef struct +{ + uint8_t Hours; /* Specifies the RTC Time Hour */ + + uint8_t Minutes; /* Specifies the RTC Time Minutes */ + + uint8_t Seconds; /* Specifies the RTC Time Seconds */ + + uint8_t H12; /* Specifies the RTC AM/PM Time */ +} RTC_TimeType; + +/** RTC Date structure definition **/ +typedef struct +{ + uint8_t WeekDay; /* Specifies the RTC Date WeekDay */ + + uint8_t Month; /* Specifies the RTC Date Month (in BCD format) */ + + uint8_t Date; /* Specifies the RTC Date */ + + uint8_t Year; /* Specifies the RTC Date Year */ +} RTC_DateType; + +/** RTC Alarm structure definition **/ +typedef struct +{ + RTC_TimeType AlarmTime; /* Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /* Specifies the RTC Alarm Masks */ + + uint32_t DateWeekMode; /* Specifies the RTC Alarm is on Date or WeekDay */ + + uint8_t DateWeekValue; /* Specifies the RTC Alarm Date/WeekDay */ +} RTC_AlarmType; + + +#define RTC_REG_BIT_MASK ((uint32_t)0x00000000) + +/** RTC_Hour_Formats **/ +#define RTC_24HOUR_FORMAT (RTC_REG_BIT_MASK) +#define RTC_12HOUR_FORMAT (RTC_CTRL_HFMT) + +/** Masks Definition **/ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU) +#define RTC_DATE_RESERVED_MASK ((uint32_t)0x00FFFF3FU) + +#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDFU) +#define RTC_FLAGS_MASK ((uint32_t)(0x1FFFF7F)) + +/** RTC_TIMEOUT_Definitions**/ +#define INITMODE_TIMEOUT ((uint32_t)0x00020000) +#define SYNCHRO_TIMEOUT ((uint32_t)0x00080000) +#define RECALPF_TIMEOUT ((uint32_t)0x00010000) +#define SHPF_TIMEOUT ((uint32_t)0x00020000) + +/** RTC_AM_PM_Definitions **/ +#define RTC_AM_H12 ((uint8_t)0x00) +#define RTC_PM_H12 (RTC_CTRL_HFMT) + +/** Coded in BCD format **/ +#define RTC_MONTH_JANUARY ((uint8_t)0x01) +#define RTC_MONTH_FEBRURY ((uint8_t)0x02) +#define RTC_MONTH_MARCH ((uint8_t)0x03) +#define RTC_MONTH_APRIL ((uint8_t)0x04) +#define RTC_MONTH_MAY ((uint8_t)0x05) +#define RTC_MONTH_JUNE ((uint8_t)0x06) +#define RTC_MONTH_JULY ((uint8_t)0x07) +#define RTC_MONTH_AUGUST ((uint8_t)0x08) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12) + +/** RTC_WeekDay_Definitions **/ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) + +/** RTC_AlarmDateWeekDay_Definitions **/ +#define RTC_ALARM_SEL_WEEKDAY_DATE (RTC_REG_BIT_MASK) +#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY (RTC_ALARMA_WKDSEL) + +/** RTC_AlarmMask_Definitions **/ +#define RTC_ALARMMASK_NONE (RTC_REG_BIT_MASK) +#define RTC_ALARMMASK_WEEKDAY (RTC_ALARMA_MASK4) +#define RTC_ALARMMASK_HOURS (RTC_ALARMA_MASK3) +#define RTC_ALARMMASK_MINUTES (RTC_ALARMA_MASK2) +#define RTC_ALARMMASK_SECONDS (RTC_ALARMA_MASK1) +#define RTC_ALARMMASK_ALL (RTC_ALARMA_MASK4 | RTC_ALARMA_MASK3 | RTC_ALARMA_MASK2 | RTC_ALARMA_MASK1) + +/** RTC_Alarms_Definitions **/ +#define RTC_A_ALARM (RTC_CTRL_ALAEN) +#define RTC_B_ALARM (RTC_CTRL_ALBEN) + +/** RTC_Bypass_Definitions **/ +#define RTC_BYPASS_UPDATE (RTC_CTRL_BYPS) + +/* RTC_Alarm_Sub_Seconds_Masks_Definitions */ +#define RTC_SUBS_MASK_ALL (RTC_REG_BIT_MASK) /* All Alarm SS fields are masked There is no comparison on sub seconds for Alarm */ +#define RTC_SUBS_MASK_SS14_1 (RTC_ALRMASS_MASKSSB_0) /* SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared */ +#define RTC_SUBS_MASK_SS14_2 (RTC_ALRMASS_MASKSSB_1) /* SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ +#define RTC_SUBS_MASK_SS14_3 (RTC_ALRMASS_MASKSSB_0 | RTC_ALRMASS_MASKSSB_1) /* SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ +#define RTC_SUBS_MASK_SS14_4 (RTC_ALRMASS_MASKSSB_2) /* SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ +#define RTC_SUBS_MASK_SS14_5 (RTC_ALRMASS_MASKSSB_2 | RTC_ALRMASS_MASKSSB_0) /* SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ +#define RTC_SUBS_MASK_SS14_6 (RTC_ALRMASS_MASKSSB_2 | RTC_ALRMASS_MASKSSB_1) /* SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ +#define RTC_SUBS_MASK_SS14_7 (RTC_ALRMASS_MASKSSB_2 | RTC_ALRMASS_MASKSSB_1 | RTC_ALRMASS_MASKSSB_0) /* SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ +#define RTC_SUBS_MASK_SS14_8 (RTC_ALRMASS_MASKSSB_3) /* SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ +#define RTC_SUBS_MASK_SS14_9 (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_0) /* SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ +#define RTC_SUBS_MASK_SS14_10 (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_1) /* SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ +#define RTC_SUBS_MASK_SS14_11 (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_1 | RTC_ALRMASS_MASKSSB_0) /* SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ +#define RTC_SUBS_MASK_SS14_12 (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_2) /* SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ +#define RTC_SUBS_MASK_SS14_13 (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_2 | RTC_ALRMASS_MASKSSB_0) /* SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ +#define RTC_SUBS_MASK_SS14_14 (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_2 | RTC_ALRMASS_MASKSSB_1) /* SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ +#define RTC_SUBS_MASK_NONE (RTC_ALRMASS_MASKSSB_3 | RTC_ALRMASS_MASKSSB_2 | RTC_ALRMASS_MASKSSB_1 | RTC_ALRMASS_MASKSSB_0) /* SS[14:0] are compared and must match to activate alarm */ + + +typedef enum +{ + RTC_WKUPCLK_RTCCLK_DIV16 = (RTC_REG_BIT_MASK), + RTC_WKUPCLK_RTCCLK_DIV8 = (RTC_CTRL_WKUPSEL_0), + RTC_WKUPCLK_RTCCLK_DIV4 = (RTC_CTRL_WKUPSEL_1), + RTC_WKUPCLK_RTCCLK_DIV2 = (RTC_CTRL_WKUPSEL_0 | RTC_CTRL_WKUPSEL_1), + RTC_WKUPCLK_CK_SPRE_16BITS = (RTC_CTRL_WKUPSEL_2), + RTC_WKUPCLK_CK_SPRE_17BITS = (RTC_CTRL_WKUPSEL_1 | RTC_CTRL_WKUPSEL_2), +}RTC_WAKE_UP_CLOCK; + + +/** RTC_Time_Stamp_Edges_definitions **/ +#define RTC_TIMESTAMP_EDGE_RISING (RTC_REG_BIT_MASK) +#define RTC_TIMESTAMP_EDGE_FALLING (RTC_CTRL_TEDGE) + +/** RTC_Reference_Detection_definitions **/ +#define RTC_REFERENCE_DETECT_DISABLE (RTC_REG_BIT_MASK) +#define RTC_REFERENCE_DETECT_ENABLE (RTC_CTRL_REFCLKEN) + +/** RTC_Output_selection_Definitions **/ +#define RTC_OUTPUT_DIS (RTC_REG_BIT_MASK) +#define RTC_OUTPUT_ALA (RTC_CTRL_OUTSEL_0) +#define RTC_OUTPUT_ALB (RTC_CTRL_OUTSEL_1) +#define RTC_OUTPUT_WKUP (RTC_CTRL_OUTSEL_0 | RTC_CTRL_OUTSEL_1) + +#define RTC_OUTPUT_TAMP (RTC_CTRL_TAMPOE) +#define RTC_OUTPUT2_EN (RTC_CTRL_OUT2EN) + +/** RTC_Output_Polarity_Definitions **/ +#define RTC_OUTPOL_HIGH (RTC_REG_BIT_MASK) +#define RTC_OUTPOL_LOW (RTC_CTRL_OPOL) + +/** RTC_Calib_Output_selection_Definitions **/ +#define RTC_CALIB_OUTPUT_256HZ (RTC_REG_BIT_MASK) +#define RTC_CALIB_OUTPUT_1HZ (RTC_CTRL_CALOSEL) + +/** if RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds **/ +#define SMOOTH_CALIB_32SEC (RTC_REG_BIT_MASK) + +/** if RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds **/ +#define SMOOTH_CALIB_16SEC (RTC_CALIB_CW16) + +/** if RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds **/ +#define SMOOTH_CALIB_8SEC (RTC_CALIB_CW8) + +/** The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 **/ +#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET (RTC_CALIB_CP) + +/** The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] **/ +#define RTC_SMOOTH_CALIB_PLUS_PULSES_RESET (RTC_REG_BIT_MASK) + +/** RTC_DayLightSaving_Definitions **/ +#define RTC_DAYLIGHT_SAVING_SUB1H (RTC_CTRL_SU1H) +#define RTC_DAYLIGHT_SAVING_ADD1H (RTC_CTRL_AD1H) + +#define RTC_STORE_OPERATION_RESET (RTC_REG_BIT_MASK) +#define RTC_STORE_OPERATION_SET (RTC_CTRL_BAKP) + +/** RTC_Output_Type_ALARM_OUT **/ +#define RTC_OUTPUT_PUSHPULL (RTC_REG_BIT_MASK) +#define RTC_OUTPUT_OPENDRAIN (RTC_OPT_TYPE) + +/** RTC_PWR_SIGNAL_TYPE **/ +#define RTC_PWR_SIGNAL_PULSE (RTC_REG_BIT_MASK) +#define RTC_PWR_SIGNAL_LEVEL (RTC_OPT_PWREST) + +/** RTC_Output_Duty_Cycle **/ +#define RTC_Output_Duty_50 (RTC_REG_BIT_MASK) +#define RTC_Output_Duty_DIV (RTC_OPT_OPDC) + +/** RTC_Add_Fraction_Of_Second_Value **/ +#define RTC_SHIFT_SUB1S_DISABLE (RTC_REG_BIT_MASK) +#define RTC_SHIFT_SUB1S_ENABLE (RTC_SCTRL_AD1S) + +/** RTC_Input_parameter_format_definitions **/ +#define RTC_FORMAT_BIN (RTC_REG_BIT_MASK) //BIN format +#define RTC_FORMAT_BCD (0x00000001) //register format + +/** RTC_Flags_Definitions **/ +#define RTC_INT_FLAG_RESERVED_MASK ((uint32_t)0x01FFFFFF) + +#define RTC_FLAG_BPRAM_ERF (RTC_INITSTS_BKSRAMREF) +#define RTC_FLAG_ITISF (RTC_INITSTS_IETSF) +#define RTC_FLAG_CALOVF (RTC_INITSTS_CAOVF) +#define RTC_FLAG_TAMP8F (RTC_INITSTS_TAM8F) +#define RTC_FLAG_TAMP7F (RTC_INITSTS_TAM7F) +#define RTC_FLAG_TAMP6F (RTC_INITSTS_TAM6F) +#define RTC_FLAG_TAMP5F (RTC_INITSTS_TAM5F) +#define RTC_FLAG_TAMP4F (RTC_INITSTS_TAM4F) +#define RTC_FLAG_RECPF (RTC_INITSTS_RECPF) +#define RTC_FLAG_TAMP3F (RTC_INITSTS_TAM3F) +#define RTC_FLAG_TAMP2F (RTC_INITSTS_TAM2F) +#define RTC_FLAG_TAMP1F (RTC_INITSTS_TAM1F) +#define RTC_FLAG_TISOVF (RTC_INITSTS_TISOVF) +#define RTC_FLAG_TISF (RTC_INITSTS_TISF) +#define RTC_FLAG_WTF (RTC_INITSTS_WTF) +#define RTC_FLAG_ALBF (RTC_INITSTS_ALBF) +#define RTC_FLAG_ALAF (RTC_INITSTS_ALAF) +#define RTC_FLAG_INITM (RTC_INITSTS_INITM) +#define RTC_FLAG_INITF (RTC_INITSTS_INITF) +#define RTC_FLAG_RSYF (RTC_INITSTS_RSYF) +#define RTC_FLAG_INITSF (RTC_INITSTS_INITSF) +#define RTC_FLAG_SHOPF (RTC_INITSTS_SHOPF) +#define RTC_FLAG_WTWF (RTC_INITSTS_WTWF) +#define RTC_FLAG_ALBWF (RTC_INITSTS_ALBWF) +#define RTC_FLAG_ALAWF (RTC_INITSTS_ALAWF) + +/** RTC_Interrupts_Definitions **/ +#define RTC_INT_CAOV (RTC_CTRL_CAOVIEN) +#define RTC_INT_TAMP8 ((uint32_t)0x02000000) +#define RTC_INT_TAMP7 ((uint32_t)0x01000000) +#define RTC_INT_TAMP6 ((uint32_t)0x00800000) +#define RTC_INT_TAMP5 ((uint32_t)0x00400000) +#define RTC_INT_TAMP4 ((uint32_t)0x00200000) +#define RTC_INT_TAMP3 ((uint32_t)0x00080000) +#define RTC_INT_TAMP2 ((uint32_t)0x00040000) +#define RTC_INT_TAMP1 ((uint32_t)0x00020000) +#define RTC_INT_TS (RTC_CTRL_TSIEN) +#define RTC_INT_WUT (RTC_CTRL_WTIEN) +#define RTC_INT_ALRB (RTC_CTRL_ALBIEN) +#define RTC_INT_ALRA (RTC_CTRL_ALAIEN) + + +/** RTC_Tamper_Trigger_Definitions **/ +#define RTC_TamperTrigger_RisingEdge (RTC_REG_BIT_MASK) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002) +#define RTC_TamperTrigger_HighLevel (RTC_REG_BIT_MASK) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000002) + +/** RTC_Tamper_Filter_Definitions **/ +#define RTC_TamperFilter_Disable (RTC_REG_BIT_MASK) /* Tamper filter is disabled */ +#define RTC_TamperFilter_2Sample (RTC_TMPCFG_TPFLT_0) /* Tamper is activated after 2 consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample (RTC_TMPCFG_TPFLT_1) /* Tamper is activated after 4 consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample (RTC_TMPCFG_TPFLT_0 | RTC_TMPCFG_TPFLT_1) /* Tamper is activated after 8 consecutive samples at the active leve */ + +/** RTC_Tamper_Sampling_Frequencies_Definitions **/ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 (RTC_REG_BIT_MASK) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 (RTC_TMPCFG_TPFREQ_0) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 (RTC_TMPCFG_TPFREQ_1) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 (RTC_TMPCFG_TPFREQ_0 | RTC_TMPCFG_TPFREQ_1) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 (RTC_TMPCFG_TPFREQ_2) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 (RTC_TMPCFG_TPFREQ_0 | RTC_TMPCFG_TPFREQ_2) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 (RTC_TMPCFG_TPFREQ_1 | RTC_TMPCFG_TPFREQ_2) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 (RTC_TMPCFG_TPFREQ_0 | RTC_TMPCFG_TPFREQ_1 | RTC_TMPCFG_TPFREQ_2) /* Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +#define RTC_TAMPCR_TAMPFREQ (RTC_TMPCFG_TPFREQ_0 | RTC_TMPCFG_TPFREQ_1 | RTC_TMPCFG_TPFREQ_2) /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + +/** RTC_Tamper_Pin_Precharge_Duration_Definitions **/ +#define RTC_TamperPrechargeDuration_1RTCCLK (RTC_REG_BIT_MASK) /* Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define RTC_TamperPrechargeDuration_2RTCCLK (RTC_TMPCFG_TPPRCH_0) /* Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_4RTCCLK (RTC_TMPCFG_TPPRCH_1) /* Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define RTC_TamperPrechargeDuration_8RTCCLK (RTC_TMPCFG_TPPRCH_0 | RTC_TMPCFG_TPPRCH_1) /* Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ + +/** @defgroup RTC_Tamper_Pins_Definitions **/ +/** @defgroup RTC Tamper Source Definitions **/ +#define RTC_TAMPER_1 (0) /* Tamper 1 */ +#define RTC_TAMPER_2 (1) /* Tamper 2 */ +#define RTC_TAMPER_3 (2) /* Tamper 3 */ +#define RTC_TAMPER_4 (3) /* Tamper 4 */ +#define RTC_TAMPER_5 (4) /* Tamper 5 */ +#define RTC_TAMPER_6 (5) /* Tamper 6 */ +#define RTC_TAMPER_7 (6) /* Tamper 7 */ +#define RTC_TAMPER_8 (7) /* Tamper 8 */ + +/** Function used to set the RTC configuration to the default reset state **/ +ErrorStatus RTC_DeInit(void); + +/** Initialization and Configuration functions **/ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct); +void RTC_StructInit(RTC_InitType* RTC_InitStruct); +void RTC_EnableWriteProtection(FunctionalState Cmd); +ErrorStatus RTC_EnterInitMode(void); +void RTC_ExitInitMode(void); +ErrorStatus RTC_WaitForSynchro(void); +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd); +void RTC_EnableBypassShadow(FunctionalState Cmd); + +/** Time and Date configuration functions **/ +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct); +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct); +uint32_t RTC_GetSubSecond(void); +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct); +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct); + +/** RTC output configuration **/ +void RTC_EnableOutput2(FunctionalState Cmd); +void RTC_ConfigOutputType(uint32_t RTC_OutputType); +void RTC_ConfigOutputDuty(uint32_t duty_cycle); +void RTC_ConfigOutputPullUp(FunctionalState Cmd); + +void RTC_ConfigPWREvtSig(uint32_t signal_type); + +/** Alarms (Alarm A and Alarm B) configuration functions **/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct); +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct); +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd); +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/** WakeUp Timer configuration functions **/ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock); +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); +uint32_t RTC_GetWakeUpCounter(void); +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd); + +/** Daylight Saving configuration functions **/ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void); + +/** Output pin Configuration function **/ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); +void RTC_EnableTampOutput(FunctionalState Cmd); + +/** Coarse and Smooth Calibration configuration functions **/ +void RTC_EnableCalibOutput(FunctionalState Cmd); +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput); +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/** TimeStamp configuration functions **/ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd); +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct); +uint32_t RTC_GetTimeStampSubSecond(void); + +void RTC_EnableInterEventTimeStamp(FunctionalState Cmd); + +/** RTC_Shift_control_synchonisation_functions **/ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/** Interrupts and flags management functions **/ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd); +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +void RTC_ClrFlag(uint32_t RTC_FLAG); +INTStatus RTC_GetITStatus(uint32_t RTC_INT); +void RTC_ClrIntPendingBit(uint32_t RTC_INT); + +/** Tamper configuration functions **/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +void RTC_TamperPullUpCmd(FunctionalState NewState); +void RTC_TamperMskCmd(uint32_t TAMPxMSK, FunctionalState NewState); +void RTC_TamperIECmd(uint32_t TAMPxIE, FunctionalState NewState); +void RTC_EnableTampErase(uint32_t RTC_Tamper_Erase, FunctionalState NewState); + +void RTC_BKUPRgWrite(uint8_t register_num, uint32_t Data); +uint32_t RTC_BKUPRgRead(uint8_t register_num); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_RTC_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdmmc.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdmmc.h new file mode 100644 index 0000000000..7a86e20325 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdmmc.h @@ -0,0 +1,851 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_sdmmc.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_SDMMC_H__ +#define __N32H76X_78X_SDMMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + + +/** Function declaration **/ + +/** SDMMC Init Structure Definition **/ +typedef struct +{ + uint32_t MaxBlockLen; /* Maximum Block Length supported by the Core/Device */ + uint32_t SDBaseCLKFreq; /* xin_clk, Base Clock Frequency for SD Clock */ + uint32_t TimeOutUnit; /* the unit of base clock frequency used to detect Data Timeout Error */ + uint32_t TuningCNT; /* the number of delay taps that are supported for tuning the rxclk_in */ + uint32_t WKUPSignalMode; /* Wakeup Signal Generation Mode */ + uint32_t SPIBlockMode; /* SPI Block Mode */ + uint32_t SPIMode; /* SPI Mode Support */ + uint32_t DDR50; /* DDR50 Support */ + uint32_t SDR104; /* SDR104 Support */ + uint32_t SDR50; /* SDR50 Support */ + uint32_t SlotType; /* Slot Type */ + uint32_t AsyncInt; /* Asynchronous Interrupt Support */ + uint32_t Suspend_Resume; /* Suspend/Resume Support */ + uint32_t SDMA; /* SDMA Support */ + uint32_t HS; /* High Speed Support */ + uint32_t ADMA2; /* ADMA2 Support */ + uint32_t Embedded_8bit; /* 8-bit Support for Embedded Device */ + uint32_t UseTuningSDR50; /* Use Tuning for SDR50 */ + uint32_t DSSDCLKFreq; /* SDCLK Frequency Select Value for Default Speed */ + uint32_t INITSDCLKFreq; /* SDCLK Frequency Select Value for Initialization */ + uint32_t SDR12SDCLKFreq; /* SDCLK Frequency Select Value for SDR12 */ + uint32_t HSSDCLKFreq; /* SDCLK Frequency Select Value for High Speed */ + uint32_t SDR50SDCLKFreq; /* SDCLK Frequency Select Value for SDR50 */ + uint32_t SDR25SDCLKFreq; /* SDCLK Frequency Select Value for SDR25 */ + uint32_t SDR104SDCLKFreq; /* SDCLK Frequency Select Value for SDR104 */ + uint32_t DDR50SDCLKFreq; /* SDCLK Frequency Select Value for DDR50 */ +} SDMMC_WrapperType; + +/** SDHSOT capability Structure Definition **/ +typedef struct +{ + uint32_t MaxBlockLen; /* Maximum Block Length supported by the Core/Device */ + uint32_t SDBaseCLKFreq; /* xin_clk, Base Clock Frequency for SD Clock */ + uint32_t TimeOutUnit; /* the unit of base clock frequency used to detect Data Timeout Error */ + uint32_t SPIBlockMode; /* SPI Block Mode */ + uint32_t SPIMode; /* SPI Mode Support */ + uint32_t DDR50; /* DDR50 Support */ + uint32_t SDR104; /* SDR104 Support */ + uint32_t SDR50; /* SDR50 Support */ + uint32_t SlotType; /* Slot Type */ + uint32_t AsyncInt; /* Asynchronous Interrupt Support */ + uint32_t Suspend_Resume; /* Suspend/Resume Support */ + uint32_t SDMA; /* SDMA Support */ + uint32_t HS; /* High Speed Support */ + uint32_t ADMA2; /* ADMA2 Support */ + uint32_t Embedded_8bit; /* 8-bit Support for Embedded Device */ + uint32_t UseTuningSDR50; /* Use Tuning for SDR50 */ +} SDHOST_capability; + +/** SDHSOT preset value Structure Definition **/ +typedef struct +{ + uint32_t DSSDCLKFreq; /* SDCLK Frequency Select Value for Default Speed */ + uint32_t INITSDCLKFreq; /* SDCLK Frequency Select Value for Initialization */ + uint32_t SDR12SDCLKFreq; /* SDCLK Frequency Select Value for SDR12 */ + uint32_t HSSDCLKFreq; /* SDCLK Frequency Select Value for High Speed */ + uint32_t SDR50SDCLKFreq; /* SDCLK Frequency Select Value for SDR50 */ + uint32_t SDR25SDCLKFreq; /* SDCLK Frequency Select Value for SDR25 */ + uint32_t SDR104SDCLKFreq; /* SDCLK Frequency Select Value for SDR104 */ + uint32_t DDR50SDCLKFreq; /* SDCLK Frequency Select Value for DDR50 */ +} SDHOST_presetvalue; + + +/** SDMMC Status **/ +typedef enum +{ + SDMMC_BusyTransferring = 1, /* Transfer is on-going. */ + SDMMC_PrepareAdmaDescriptorFailed, /* Set DMA descriptor failed. */ + SDMMC_SendCommandFailed, /* Send command failed. */ + SDMMC_TransferDataFailed, /* Transfer data failed. */ + SDMMC_DMADataAddrNotAlign, /* Data address not aligned. */ + SDMMC_ReTuningRequest, /* Re-tuning request. */ + SDMMC_TuningError, /* Tuning error. */ + SDMMC_NotSupport, /* Not support. */ + SDMMC_TransferDataComplete, /* Transfer data complete. */ + SDMMC_SendCommandSuccess, /* Transfer command complete. */ + SDMMC_TransferDMAComplete, /* Transfer DMA complete. */ + SDMMC_SUCCESS, /* The code execution flow is normal. */ + SDMMC_ERROR, /* Code execution flow exception. */ + SDMMC_OutOfRange /* Out of range access. */ +} SDMMC_STS; + +/* SDMMC transfer flags */ +typedef enum +{ + SDMMC_CommandOnly = 1U, /* transfer command only */ + SDMMC_CommandAndTxData = 2U, /* transfer command and transmit data */ + SDMMC_CommandAndRxData = 4U, /* transfer command and receive data */ + SDMMC_DataWithAutoCmd12 = 8U, /* transfer data with auto cmd12 enabled */ + SDMMC_DataWithAutoCmd23 = 16U, /* transfer data with auto cmd23 enabled */ + SDMMC_BootData = 32U, /* transfer boot data */ + SDMMC_BootDataContinuous = 64U, /* transfer boot data continuous */ +} SDMMC_TRANSFlAG; + +/* Data transfer direction. */ +typedef enum +{ + SDMMC_TransferDirSend = 0U, /* transfer direction send. */ + SDMMC_TransferDirReceive = SDHOST_TMODE_DATDIR, /* transfer direction receive. */ +} SDMMC_TRANSDIR; + + +/* The command type */ +typedef enum +{ + CARD_CommandTypeNormal = 0U, /* Normal command */ + CARD_CommandTypeSuspend = 1U, /* Suspend command */ + CARD_CommandTypeResume = 2U, /* Resume command */ + CARD_CommandTypeAbort = 3U, /* Abort command */ + CARD_CommandTypeEmpty = 4U, /* Empty command */ +} SDMMC_CardCMDType; + +/* The command response type. + * Defines the command response type from card to host controller. + */ +typedef enum +{ + CARD_ResponseTypeNone = 0U, /* Response type: none */ + CARD_ResponseTypeR1 = 1U, /* Response type: R1 */ + CARD_ResponseTypeR1b = 2U, /* Response type: R1b */ + CARD_ResponseTypeR2 = 3U, /* Response type: R2 */ + CARD_ResponseTypeR3 = 4U, /* Response type: R3 */ + CARD_ResponseTypeR4 = 5U, /* Response type: R4 */ + CARD_ResponseTypeR5 = 6U, /* Response type: R5 */ + CARD_ResponseTypeR5b = 7U, /* Response type: R5b */ + CARD_ResponseTypeR6 = 8U, /* Response type: R6 */ + CARD_ResponseTypeR7 = 9U, /* Response type: R7 */ +} SDMMC_CardRspType; + + +/* Since every write operation to the TMODE register triggers the issuance of a CMD, + this struct is used to store some of the status bits of the TMODE register, + which are then written to the TMODE register collectively when issuing a CMD. */ +typedef struct +{ + uint32_t DMAE; /* DMA Enable. */ + uint32_t BCNTE; /* Block Count Enable. */ + uint32_t ACMDE; /* Auto CMD Enable. */ + uint32_t DATDIR; /* Data Transfer Direction Select. */ + uint32_t BLKSEL; /* Multi / Single Block Select. */ +} SDHOST_TMODE_struct; + +/* Card command descriptor. Defines card command-related attribute. */ +typedef struct +{ + uint32_t index; /* Command index. */ + uint32_t argument; /* Command argument. */ + SDMMC_CardCMDType type; /* Command type. */ + SDMMC_CardRspType responseType; /* Command response type. */ + uint32_t response[4U]; /* Response for this command. */ + uint32_t responseErrorFlags; /* Response error flag, which need to check the command reponse. */ + uint32_t flags; /* Cmd flags. */ +} SDMMC_CMD; + +/* Card data descriptor. + * + * Defines a structure to contain data-related attribute. The 'enableIgnoreError' is used when upper card + * driver wants to ignore the error event to read/write all the data and not to stop read/write immediately when an + * error event happens. For example, bus testing procedure for MMC card. + */ +typedef struct +{ + uint32_t AutoCommand12_23; /* Enable auto CMD12/CMD23. */ + FunctionalState enableIgnoreError; /* Enable to ignore error event to read/write all the data. */ + uint8_t dataType; /* this is used to distinguish the normal/tuning/boot data. */ + uint32_t blockSize; /* Block size. */ + uint32_t blockCount; /* Block count. */ + uint32_t *rxData; /* Buffer to save data read. */ + const uint32_t *txData; /* Data buffer to write. */ +} SDMMC_DATA; + +/* Transfer state. */ +typedef struct +{ + SDMMC_DATA data; /* Data to transfer. */ + SDMMC_CMD command; /* Command to send. */ +} SDMMC_Transfer; + +/* Data structure to configure the MMC boot feature. */ +typedef struct +{ + uint32_t ackTimeoutCount; /* Timeout value for the boot ACK. */ + uint32_t bootMode; /* Boot mode selection. */ + uint32_t blockCount; /* Block count */ + uint32_t blockSize; /* Block size. */ + uint32_t BootAck; /* Enable or disable boot ACK. */ +} SDHOST_boot_config; + +/* DMA mode */ +typedef enum +{ + DmaModeSimple = 0UL, /* SDMA is selected. */ + DmaModeAdma2 = SDHOST_CTRL1_DMASEL_1, /* ADMA2 is selected. */ +} SDHOST_DMAMODE; + +/* ADMA configuration. */ +typedef struct +{ + SDHOST_DMAMODE dmaMode; /* DMA mode. */ + uint32_t *admaTable; /* ADMA table address, can't be null if transfer way is ADMA2. */ + uint32_t admaTableWords; /* ADMA table length united as words, can't be 0 if transfer way is ADMA2. */ +} SDHOST_ADMAconfig; + + +/* Defines the ADMA2 descriptor structure. */ +typedef struct +{ + uint32_t attribute; /* The control and status field. */ + const uint32_t *address; /* The address field. */ +} SDHOST_ADMA2_descriptor; + +/* SDHOST Present status flag. */ +enum +{ + SDHOST_CommandInhibitFlag = SDHOST_PRESTS_CMDINHC, /* Command inhibit. */ + SDHOST_DataInhibitFlag = SDHOST_PRESTS_CMDINHD, /* Data inhibit. */ + SDHOST_DataLineActiveFlag = SDHOST_PRESTS_DLACT, /* Data line active. */ + SDHOST_ReTuningRequestFlag = SDHOST_PRESTS_RETUNREQ, /* Re-tuning request flag */ + SDHOST_WriteTransferActiveFlag = SDHOST_PRESTS_WTRANACT, /* Write transfer active. */ + SDHOST_ReadTransferActiveFlag = SDHOST_PRESTS_RTRANACT, /* Read transfer active. */ + SDHOST_BufferWriteEnableFlag = SDHOST_PRESTS_BUFW, /* Buffer write enable. */ + SDHOST_BufferReadEnableFlag = SDHOST_PRESTS_BUFR, /* Buffer read enable. */ + SDHOST_CardInsertedFlag = SDHOST_PRESTS_CINS, /* Card inserted. */ + SDHOST_CardStateStableFlag = SDHOST_PRESTS_CSTSL, /* Card State Stable. */ + SDHOST_CardDetectPinFlag = SDHOST_PRESTS_SDCDL, /* Card Detect Pin Level. */ + SDHOST_CardWPSwitchPinFlag = SDHOST_PRESTS_SDCDL, /* Write Protect Switch Pin Level. */ + + SDHOST_CommandLineLevelFlag = SDHOST_PRESTS_CMDL, /* Command line signal level. */ + SDHOST_Data0LineLevelFlag = SDHOST_PRESTS_DATLL_0, /* Data0 line signal level. */ + SDHOST_Data1LineLevelFlag = SDHOST_PRESTS_DATLL_1, /* Data1 line signal level. */ + SDHOST_Data2LineLevelFlag = SDHOST_PRESTS_DATLL_2, /* Data2 line signal level. */ + SDHOST_Data3LineLevelFlag = SDHOST_PRESTS_DATLL_3, /* Data3 line signal level. */ + SDHOST_Data4LineLevelFlag = SDHOST_PRESTS_DATLH_0, /* Data4 line signal level. */ + SDHOST_Data5LineLevelFlag = SDHOST_PRESTS_DATLH_1, /* Data5 line signal level. */ + SDHOST_Data6LineLevelFlag = SDHOST_PRESTS_DATLH_2, /* Data6 line signal level. */ + SDHOST_Data7LineLevelFlag = SDHOST_PRESTS_DATLH_3, /* Data7 line signal level. */ +}; + + +/* SDHOST interrupt status flag */ +enum +{ + SDHOST_CommandCompleteFlag = SDHOST_INTSTS_CMDC, /* Command complete. */ + SDHOST_DataCompleteFlag = SDHOST_INTSTS_TC, /* Data complete. */ + SDHOST_BlockGapEventFlag = SDHOST_INTSTS_BLKGAPE, /* Block gap event. */ + SDHOST_DmaCompleteFlag = SDHOST_INTSTS_DMAINT, /* DMA interrupt. */ + SDHOST_BufferWriteReadyFlag = SDHOST_INTSTS_BUFWRDY, /* Buffer write ready. */ + SDHOST_BufferReadReadyFlag = SDHOST_INTSTS_BUFRRDY, /* Buffer read ready. */ + SDHOST_CardInsertionFlag = SDHOST_INTSTS_CINS, /* Card inserted. */ + SDHOST_CardRemovalFlag = SDHOST_INTSTS_CRMV, /* Card removed. */ + SDHOST_CardInterruptFlag = SDHOST_INTSTS_CINT, /* Card interrupt. */ + SDHOST_ReTuningEventFlag = SDHOST_INTSTS_RETUNE, /* Re-Tuning event */ + SDHOST_BootACKRcvFlag = SDHOST_INTSTS_BOOTACKR, /* BOOT ACK receive */ + SDHOST_BootTerminateFlag = SDHOST_INTSTS_BOOTTER, /* Boot terminate */ + SDHOST_AllErrorFlag = SDHOST_INTSTS_ALLERR, /* Sum of all error flags below */ + SDHOST_CommandTimeoutFlag = SDHOST_INTSTS_CTERR, /* Command timeout error. */ + SDHOST_CommandCrcErrorFlag = SDHOST_INTSTS_CCRCERR, /* Command CRC error. */ + SDHOST_CommandEndBitErrorFlag = SDHOST_INTSTS_CENDBERR, /* Command end bit error. */ + SDHOST_CommandIndexErrorFlag = SDHOST_INTSTS_CINXERR, /* Command index error. */ + SDHOST_DataTimeoutFlag = SDHOST_INTSTS_DTERR, /* Data timeout error. */ + SDHOST_DataCrcErrorFlag = SDHOST_INTSTS_DCRCERR, /* Data CRC error. */ + SDHOST_DataEndBitErrorFlag = SDHOST_INTSTS_DENDERR, /* Data end bit error. */ + SDHOST_AutoCommand12ErrorFlag = SDHOST_INTSTS_ACMDERR, /* Auto CMD12 error. */ + SDHOST_DmaErrorFlag = SDHOST_INTSTS_ADMAERR, /* ADMA error. */ + SDHOST_TargetResErrorFlag = SDHOST_INTSTS_TRGRERR, /* Target Response error. */ + + SDHOST_CommandErrorFlag = (SDHOST_CommandTimeoutFlag | SDHOST_CommandCrcErrorFlag | SDHOST_CommandEndBitErrorFlag | + SDHOST_CommandIndexErrorFlag), /* Command error */ + SDHOST_DataErrorFlag = (SDHOST_DataTimeoutFlag | SDHOST_DataCrcErrorFlag | SDHOST_DataEndBitErrorFlag | + SDHOST_AutoCommand12ErrorFlag), /* Data error */ + SDHOST_ErrorFlag = (SDHOST_CommandErrorFlag | SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag | + SDHOST_TargetResErrorFlag), /* All other error */ + + SDHOST_DataFlag = (SDHOST_DataCompleteFlag | SDHOST_BufferWriteReadyFlag | SDHOST_BufferReadReadyFlag | + SDHOST_DataErrorFlag), /* Data interrupts */ + + SDHOST_DataDMAFlag = (SDHOST_DataCompleteFlag | SDHOST_DataErrorFlag | SDHOST_DmaErrorFlag), /* Data interrupts */ + + SDHOST_CommandFlag = (SDHOST_CommandErrorFlag | SDHOST_CommandCompleteFlag), /* Command interrupts */ + SDHOST_CardDetectFlag = (SDHOST_CardInsertionFlag | SDHOST_CardRemovalFlag), /* Card detection interrupts */ + SDHOST_AllInterruptFlags = + (SDHOST_BlockGapEventFlag | SDHOST_CardInterruptFlag | SDHOST_CommandFlag | SDHOST_DataFlag | SDHOST_ErrorFlag | + SDHOST_ReTuningEventFlag | SDHOST_DmaCompleteFlag | SDHOST_BootTerminateFlag | SDHOST_BootACKRcvFlag | SDHOST_CardDetectFlag), /* All flags mask */ +}; + +/* Auto CMD12 error status flag. */ +enum +{ + SDHOST_AutoCommand12NotExecutedFlag = SDHOST_CTRLSTS_ACMD12NE, /* Not executed error. */ + SDHOST_AutoCommand12TimeoutFlag = SDHOST_CTRLSTS_ACMDTE, /* Timeout error. */ + SDHOST_AutoCommand12EndBitErrorFlag = SDHOST_CTRLSTS_ACMDEBE, /* End bit error. */ + SDHOST_AutoCommand12CrcErrorFlag = SDHOST_CTRLSTS_ACMDCRCE, /* CRC error. */ + SDHOST_AutoCommand12IndexErrorFlag = SDHOST_CTRLSTS_ACMDINXE, /* Index error. */ + SDHOST_AutoCommand12NotIssuedFlag = SDHOST_CTRLSTS_ACMD12E, /* Not issued error. */ +}; + +/* ADMA error status flag. */ +enum +{ + SDHOST_AdmaLenghMismatchFlag = SDHOST_ADMAESTS_ADMALME, /* ADMA Length Mismatch Error. */ +}; + + +/* AutoCommand12_23 type. */ +enum +{ + NoAutoCommand = 0U, /* No Auto command. */ + AutoCommand23 = 1U, /* AutoCommand23 enable. */ + AutoCommand12 = 2U, /* AutoCommand12 enable. */ +}; + +/* Tansfer data type definition. */ +enum +{ + SDHOST_TransferDataNormal = 0U, /* Transfer normal read/write data. */ + SDHOST_TransferDataTuning = 1U, /* Transfer tuning data. */ + SDHOST_TransferDataBoot = 2U, /* Transfer boot data. */ + SDHOST_TransferDataBootcontinous = 3U, /* Transfer boot data continuously. */ +}; + +/** SDMMC timeout constant define **/ +#define SDMMC_TIMEOUT_VALUE (600000U) /*10ms*/ + +/* Software Reset for DAT/CMD/ALL Line */ +#define SDHOST_SOFTWARE_DATALINE (SDHOST_CTRL2_SWRSTDL) /* Software Reset for DAT Line */ +#define SDHOST_SOFTWARE_CMDLINE (SDHOST_CTRL2_SWRSTCL) /* Software Reset for CMD Line */ +#define SDHOST_SOFTWARE_ALLLINE (SDHOST_CTRL2_SWRSTALL) /* Software Reset for ALL Line */ + +/* Maximum Block Length supported by the Core/Device */ +#define SDMMC_MAXBLOCKLEN_512B ((uint32_t)0x00000000U) /* 512 Bytes */ +#define SDMMC_MAXBLOCKLEN_1024B (SDMMC_CFG1_MBL_0) /* 1024 Bytes */ +#define SDMMC_MAXBLOCKLEN_2048B (SDMMC_CFG1_MBL_1) /* 2048 Bytes */ + +/* the unit of base clock frequency used to detect Data Timeout Error */ +#define SDMMC_TIMEOUTCLKUNIT_KHZ ((uint32_t)0x00000000U) /* KHz */ +#define SDMMC_TIMEOUTCLKUNIT_MHZ (SDMMC_CFG1_TCLKU) /* MHz */ + +/* Wakeup Signal Generation Mode */ +#define SDMMC_SYNCWKUP ((uint32_t)0x00000000U) /* wakeup event are syncrhonized with controller clock (xin_clk). */ +#define SDMMC_ASYNCWKUP (SDMMC_CFG1_WSGM) /* wakeup event are async with xin_clk */ + +/* SPI Block Mode */ +#define SDMMC_TIMEOUTCLKUNIT_KHZ ((uint32_t)0x00000000U) /* KHz */ +#define SDMMC_TIMEOUTCLKUNIT_MHZ (SDMMC_CFG1_TCLKU) /* MHz */ + +/* SPI Block Mode Support */ +#define SDMMC_SPIBLOCKMODESUPPORT (SDMMC_CFG2_SPIBMOD) /* SPI Block Mode support */ +#define SDMMC_SPIBLOCKMODEUNSUPPORT ((uint32_t)0x00000000U) /* SPI Block Mode not support */ + +/* SPI Mode Support */ +#define SDMMC_SPIMODESUPPORT (SDMMC_CFG2_SPIMOD) /* SPI Mode support */ +#define SDMMC_SPIMODEUNSUPPORT ((uint32_t)0x00000000U) /* SPI Mode not support */ + +/* DDR50 Mode Support */ +#define SDMMC_DDR50SUPPORT (SDMMC_CFG2_DDR50) /* DDR50 support */ +#define SDMMC_DDR50UNSUPPORT ((uint32_t)0x00000000U) /* DDR50 not support */ + +/* SDR104 Mode Support */ +#define SDMMC_SDR104SUPPORT (SDMMC_CFG2_SDR104) /* SDR104 support */ +#define SDMMC_SDR104UNSUPPORT ((uint32_t)0x00000000U) /* SDR104 not support */ + +/* SDR50 Mode Support */ +#define SDMMC_SDR50SUPPORT (SDMMC_CFG2_SDR50) /* SDR50 support */ +#define SDMMC_SDR50UNSUPPORT ((uint32_t)0x00000000U) /* SDR50 not support */ + +/* Slot Type */ +#define SDMMC_SDTYPE ((uint32_t)0x00000000U) /* SD/SDIO Device */ +#define SDMMC_EMMCTYPE (SDMMC_CFG2_STYP_0) /* emmc Device */ + +/* Asynchronous Interrupt Support */ +#define SDMMC_ASYNCINTSUPPORT (SDMMC_CFG2_ASYNCINT) /* Asynchronous Interrupt Support */ +#define SDMMC_ASYNCINTUNSUPPORT ((uint32_t)0x00000000U) /* Asynchronous Interrupt not Support */ + +/* Suspend/Resume Support */ +#define SDMMC_SUSRESSUPPORT (SDMMC_CFG2_SRS) /* Suspend/Resume Support */ +#define SDMMC_SUSRESUNSUPPORT ((uint32_t)0x00000000U) /* Suspend/Resume not Support */ + +/* SDMA Support */ +#define SDMMC_SDMASUPPORT (SDMMC_CFG2_SDMA) /* SDMA Support */ +#define SDMMC_SDMAUNSUPPORT ((uint32_t)0x00000000U) /* SDMA not Support */ + +/* High Speed Support */ +#define SDMMC_HSSUPPORT (SDMMC_CFG2_HS) /* High Speed Support */ +#define SDMMC_HSUNSUPPORT ((uint32_t)0x00000000U) /* High Speed not Support */ + +/* ADMA2 Support */ +#define SDMMC_ADMA2SUPPORT (SDMMC_CFG2_ADMA2) /* ADMA2 Support */ +#define SDMMC_ADMA2UNSUPPORT ((uint32_t)0x00000000U) /* ADMA2 not Support */ + +/* 8-bit Support for Embedded Device */ +#define SDMMC_EMBEDDEDSUPPORT (SDMMC_CFG2_EMBUS) /* 8-bit Support for Embedded Device */ +#define SDMMC_EMBEDDEDUNSUPPORT ((uint32_t)0x00000000U) /* 8-bit not Support for Embedded Device */ + +/* Use Tuning for SDR50 */ +#define SDMMC_SDR50TUNING (SDMMC_CFG3_UTFSDR50) /* Use Tuning for SDR50 */ +#define SDMMC_SDR50UNTUNING ((uint32_t)0x00000000U) /* Not use Tuning for SDR50 */ + +/* Manual tuning sdclk output */ +#define SDMMC_MANUALTUNOUT_EN (SDMMC_DLYCTRL_OTDE) /* Output tap Delay Enable */ +#define SDMMC_MANUALTUNOUT_DELAYMASK (SDMMC_DLYCTRL_OTDS) /* Output Tap Delay Select */ + +/* Manual tuning rclk input */ +#define SDMMC_MANUALTUNGATE_EN (SDMMC_DLYCTRL_ITCW) /* Input Tap Change Window */ +#define SDMMC_MANUALTUNIN_EN (SDMMC_DLYCTRL_ITDE) /* Input tap Delay Enable */ +#define SDMMC_MANUALTUNIN_DELAYMASK (SDMMC_DLYCTRL_ITDS) /* Input Tap Delay Select */ + +/* Sampling Clock Select */ +#define SDHOST_SAMPCLKSEL (SDHOST_CTRLSTS_SCS) /* Sampling Clock Select */ +#define SDHOST_AUTOTUNE (SDHOST_CTRLSTS_ETUN) /* Execute Tuning */ + + +/** SDMMC CFG1 register bit offset define **/ +#define SDMMC_CFG1_BCLKF_OFFSET (REG_BIT14_OFFSET ) /* Base Clock Frequency for SD Clock */ +#define SDMMC_CFG1_TCNT_OFFSET (REG_BIT1_OFFSET ) /* Tuning Count */ + +/** SDMMC PVxCTRL register bit offset define **/ +#define SDMMC_PV0CTRL_CLKFS_OFFSET (REG_BIT13_OFFSET ) /* SDCLK Frequency Select Value */ + +/********** SDHOST register ***********/ +/* Maximum block count can be set one time */ +#define SDHOST_MAX_BLOCK_COUNT (SDHOST_BLKCFG_CNT >> REG_BIT16_OFFSET) +#define SDHOST_BLOCK_COUNT_OFFSET (REG_BIT16_OFFSET ) + +/* SDHOST TMODE register */ +#define SDHOST_TMODE_DMADISABLE ((uint32_t)0x00000000U ) /* DMA Disable */ +#define SDHOST_TMODE_DMAENABLE (SDHOST_TMODE_DMAE ) /* DMA Enable */ + +#define SDHOST_TMODE_BLOCKCNTDISABLE ((uint32_t)0x00000000U ) /* DMA Disable */ +#define SDHOST_TMODE_BLOCKCNTENABLE (SDHOST_TMODE_BLOCKCNTE ) /* DMA Enable */ + +#define SDHOST_TMODE_NOACMDEN ((uint32_t)0x00000000U) /* No Auto CMD enable */ +#define SDHOST_TMODE_AC12EN (SDHOST_TMODE_AUTOCMDE_0) /* Auto CMD12 enable */ +#define SDHOST_TMODE_AC23EN (SDHOST_TMODE_AUTOCMDE_1) /* Auto CMD23 enable */ + +#define SDHOST_TMODE_DATDIR_WRITE ((uint32_t)0x00000000U ) /* Data Transfer Direction Select write */ +#define SDHOST_TMODE_DATDIR_READ (SDHOST_TMODE_DATDIR ) /* Data Transfer Direction Select read */ + +#define SDHOST_TMODE_SINGLEBLK ((uint32_t)0x00000000 ) /* Single Block Select */ +#define SDHOST_TMODE_MULTIBLK (SDHOST_TMODE_BLKSEL ) /* Multi Block Select */ + + +/* Transfer flag mask. */ +enum +{ + SDHOST_EnableDmaFlag = SDHOST_TMODE_DMAE, /* Enable DMA. */ + + SDHOST_CommandTypeSuspendFlag = SDHOST_TMODE_TYPE_0, /* Suspend command. */ + SDHOST_CommandTypeResumeFlag = SDHOST_TMODE_TYPE_1, /* Resume command. */ + SDHOST_CommandTypeAbortFlag = SDHOST_TMODE_TYPE, /* Abort command. */ + + SDHOST_EnableBlockCountFlag = SDHOST_TMODE_BLOCKCNTE, /* Enable block count. */ + SDHOST_EnableAutoCommand12Flag = SDHOST_TMODE_AUTOCMDE_0, /* Enable auto CMD12. */ + SDHOST_DataReadFlag = SDHOST_TMODE_DATDIR, /* Enable data read. */ + SDHOST_MultipleBlockFlag = SDHOST_TMODE_BLKSEL, /* Multiple block data read/write. */ + SDHOST_EnableAutoCommand23Flag = SDHOST_TMODE_AUTOCMDE_1, /* Enable auto CMD23. */ + + SDHOST_ResponseLength136Flag = SDHOST_TMODE_RTYPESEL_0, /* 136-bit response length. */ + SDHOST_ResponseLength48Flag = SDHOST_TMODE_RTYPESEL_1, /* 48-bit response length. */ + SDHOST_ResponseLength48BusyFlag = SDHOST_TMODE_RTYPESEL, /* 48-bit response length with busy status. */ + + SDHOST_EnableCrcCheckFlag = SDHOST_TMODE_CRCCK, /* Enable CRC check. */ + SDHOST_EnableIndexCheckFlag = SDHOST_TMODE_INDEXCK, /* Enable index check. */ + SDHOST_DataPresentFlag = SDHOST_TMODE_DPRESEL, /* Data present flag. */ +}; + +#define SDHOST_CMD_INDEX_OFFSET (REG_BIT24_OFFSET ) /* CMD index */ + +#define SDHOST_BOOTDUMMY ((uint32_t)0x5555AAAAU) /* dummy data */ + +/* SDHOST capability register */ +#define SDHOST_CAP0_SLOTTYPE_MASK (SDHOST_CAP0STS_STYP ) /* Slot Type */ +#define SDHOST_CAP0_SLOTTYPE_OFFSET (REG_BIT30_OFFSET ) /* Slot Type */ + +#define SDHOST_CAP0_ASYNCINT_MASK (SDHOST_CAP0STS_ASYNCINT ) /* Asynchronous Interrupt Support */ +#define SDHOST_CAP0_ASYNCINT_OFFSET (REG_BIT29_OFFSET ) /* Asynchronous Interrupt Support */ + +#define SDHOST_CAP0_VS33_MASK (SDHOST_CAP0STS_VS33 ) /* Voltage Support 3.3V */ +#define SDHOST_CAP0_VS33_OFFSET (REG_BIT24_OFFSET ) /* Voltage Support 3.3V */ + +#define SDHOST_CAP0_SRS_MASK (SDHOST_CAP0STS_SRS ) /* Suspend / Resume Support */ +#define SDHOST_CAP0_SRS_OFFSET (REG_BIT23_OFFSET ) /* Suspend / Resume Support */ + +#define SDHOST_CAP0_SDMA_MASK (SDHOST_CAP0STS_SDMA ) /* SDMA Support */ +#define SDHOST_CAP0_SDMA_OFFSET (REG_BIT22_OFFSET ) /* SDMA Support */ + +#define SDHOST_CAP0_HS_MASK (SDHOST_CAP0STS_HS ) /* High Speed Support */ +#define SDHOST_CAP0_HS_OFFSET (REG_BIT21_OFFSET ) /* High Speed Support */ + +#define SDHOST_CAP0_ADMA2_MASK (SDHOST_CAP0STS_ADMA2 ) /* ADMA2 Support */ +#define SDHOST_CAP0_ADMA2_OFFSET (REG_BIT19_OFFSET ) /* ADMA2 Support */ + +#define SDHOST_CAP0_EMBUS_MASK (SDHOST_CAP0STS_EMBUS ) /* Extended Media Bus Support */ +#define SDHOST_CAP0_EMBUS_OFFSET (REG_BIT18_OFFSET ) /* Extended Media Bus Support */ + +#define SDHOST_CAP0_MBL_MASK (SDHOST_CAP0STS_MBL ) /* Max Block Length */ +#define SDHOST_CAP0_MBL_OFFSET (REG_BIT16_OFFSET ) /* Max Block Length */ + +#define SDHOST_CAP0_BCLKF_MASK (SDHOST_CAP0STS_BCLKF ) /* Base Clock Frequency for SD Clock */ +#define SDHOST_CAP0_BCLKF_OFFSET (REG_BIT8_OFFSET ) /* Base Clock Frequency for SD Clock */ + +#define SDHOST_CAP0_TCLKU_MASK (SDHOST_CAP0STS_TCLKU ) /* Timeout Clock Unit */ +#define SDHOST_CAP0_TCLKU_OFFSET (REG_BIT7_OFFSET ) /* Timeout Clock Unit */ + +#define SDHOST_CAP1_SPIBMOD_MASK (SDHOST_CAP1STS_SPIBMOD ) /* SPI block mode */ +#define SDHOST_CAP1_SPIBMOD_OFFSET (REG_BIT25_OFFSET ) /* SPI block mode */ + +#define SDHOST_CAP1_SPIMOD_MASK (SDHOST_CAP1STS_SPIMOD ) /* SPI mode */ +#define SDHOST_CAP1_SPIMOD_OFFSET (REG_BIT24_OFFSET ) /* SPI mode */ + +#define SDHOST_CAP1_UTFSDR50_MASK (SDHOST_CAP1STS_UTFSDR50 ) /* Use Tuning for SDR50 */ +#define SDHOST_CAP1_UTFSDR50_OFFSET (REG_BIT13_OFFSET ) /* Use Tuning for SDR50 */ + +#define SDHOST_CAP1_DDR50_MASK (SDHOST_CAP1STS_DDR50 ) /* DDR50 Support */ +#define SDHOST_CAP1_DDR50_OFFSET (REG_BIT2_OFFSET ) /* DDR50 Support */ + +#define SDHOST_CAP1_SDR104_MASK (SDHOST_CAP1STS_SDR104 ) /* SDR104 Support */ +#define SDHOST_CAP1_SDR104_OFFSET (REG_BIT1_OFFSET ) /* SDR104 Support */ + +#define SDHOST_CAP1_SDR50_MASK (SDHOST_CAP1STS_SDR50 ) /* SDR50 Support */ + +/* SDHOST preset value register */ +#define SDHOST_PV0_DSCLKFS_MASK (SDHOST_PV0STS_CLKFS_DS ) /* SDCLK Frequency Select Value for Default Speed */ +#define SDHOST_PV0_DSCLKFS_OFFSET (REG_BIT16_OFFSET ) /* SDCLK Frequency Select Value for Default Speed */ + +#define SDHOST_PV0_INITCLKFS_MASK (SDHOST_PV0STS_CLKFS_INIT ) /* SDCLK Frequency Select Value for Initialization */ + +#define SDHOST_PV1_SDR12CLKFS_MASK (SDHOST_PV1STS_CLKFS_SDR12 ) /* SDCLK Frequency Select Value for SDR12*/ +#define SDHOST_PV1_SDR12CLKFS_OFFSET (REG_BIT16_OFFSET ) /* SDCLK Frequency Select Value for SDR12 */ + +#define SDHOST_PV1_HSCLKFS_MASK (SDHOST_PV1STS_CLKFS_HS ) /* SDCLK Frequency Select Value for High Speed */ + +#define SDHOST_PV2_SDR50CLKFS_MASK (SDHOST_PV2STS_CLKFS_SDR50 ) /* SDCLK Frequency Select Value for SDR50*/ +#define SDHOST_PV2_SDR50CLKFS_OFFSET (REG_BIT16_OFFSET ) /* SDCLK Frequency Select Value for SDR50 */ + +#define SDHOST_PV2_SDR25CLKFS_MASK (SDHOST_PV2STS_CLKFS_SDR25 ) /* SDCLK Frequency Select Value for SDR25 */ + +#define SDHOST_PV3_DDR50CLKFS_MASK (SDHOST_PV3STS_CLKFS_DDR50 ) /* SDCLK Frequency Select Value for DDR50*/ +#define SDHOST_PV3_DDR50CLKFS_OFFSET (REG_BIT16_OFFSET ) /* SDCLK Frequency Select Value for DDR50 */ + +#define SDHOST_PV3_SDR104CLKFS_MASK (SDHOST_PV3STS_CLKFS_SDR104 ) /* SDCLK Frequency Select Value for SDR104 */ + +/* boot config */ +#define SDHOST_BOOTMODENORMAL ((uint32_t)0x00000000U ) /* Normal boot */ +#define SDHOST_BOOTMODEALIERNATIVE (SDHOST_CTRL1_BOOTINALT ) /* Alternative boot */ + +#define SDHOST_BOOTNOACKCHECK ((uint32_t)0x00000000U ) /* Boot Ack Not Check */ +#define SDHOST_BOOTACKCHECK (SDHOST_CTRL1_BOOTACKC ) /* Boot Ack Check */ + + +/* ADMA2 Descriptor */ +/* The alignment size for ADDRESS field in ADMA2's descriptor. */ +#define SDHOST_ADMA2_ADDRESS_ALIGN (4U) +/* The alignment size for LENGTH filed in ADMA2's descriptor. */ +#define SDHOST_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA2 descriptor table: + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * ADMA2 action table: + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/**********************************tables below are created only for Doxygen***********************************/ +/* The bit shift for LENGTH field in ADMA2's descriptor. + * + * + * + *
ADMA2 descriptor table
Address field Length Reserved Attribute + *
63 32 31 16 15 06 05 04 03 02 01 00 + *
32-bit address 16-bit length 0000000000 Act2 Act1 0 Int End Valid + *
+ * + * + * + *
ADMA2 action
Act2 Act1 Comment Operation + *
0 0 No op Don't care + *
0 1 Reserved Read this line and go to next one + *
1 0 Transfer data Transfer data with address and length set in this descriptor line + *
1 1 Link descriptor Link to another descriptor + *
+ */ +#define SDHOST_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/* The bit mask for LENGTH field in ADMA2's descriptor. */ +#define SDHOST_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/* The maximum value of LENGTH field in ADMA2's descriptor. */ +#define SDHOST_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHOST_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +/* ADMA2 descriptor control and status mask. */ +enum +{ + SDHOST_Adma2DescriptorValidFlag = (1U << 0U), /* Valid flag. */ + SDHOST_Adma2DescriptorEndFlag = (1U << 1U), /* End flag. */ + SDHOST_Adma2DescriptorInterruptFlag = (1U << 2U), /* Interrupt flag. */ + SDHOST_Adma2DescriptorActivity1Flag = (1U << 4U), /* Activity 1 mask. */ + SDHOST_Adma2DescriptorActivity2Flag = (1U << 5U), /* Activity 2 mask. */ + + SDHOST_Adma2DescriptorTypeNop = (SDHOST_Adma2DescriptorValidFlag), /* No operation. */ + SDHOST_Adma2DescriptorTypeReserved = (SDHOST_Adma2DescriptorActivity1Flag | SDHOST_Adma2DescriptorValidFlag), + /* Reserved. */ + SDHOST_Adma2DescriptorTypeTransfer = (SDHOST_Adma2DescriptorActivity2Flag | SDHOST_Adma2DescriptorValidFlag), + /* Transfer type. */ + SDHOST_Adma2DescriptorTypeLink = (SDHOST_Adma2DescriptorActivity1Flag | SDHOST_Adma2DescriptorActivity2Flag | + SDHOST_Adma2DescriptorValidFlag), /* Link type. */ +}; + +/* ADMA descriptor configuration flag. */ +enum +{ + SDHOST_AdmaDescriptorSingleFlag = 0U, + /* Try to finish the transfer in a single ADMA descriptor. If transfer size is bigger than one + ADMA descriptor's ability, new another descriptor for data transfer. */ + SDHOST_AdmaDescriptorMultipleFlag = 1U, + /* Create multiple ADMA descriptors within the ADMA table, this is used for + mmc boot mode specifically, which need to modify the ADMA descriptor on the fly, + so the flag should be used combining with stop at block gap feature. */ +}; + + +/* Data transfer width. */ +typedef enum +{ + SDHOST_DataBusWidth1Bit = 0U, /* 1-bit mode */ + SDHOST_DataBusWidth4Bit = 1U, /* 4-bit mode */ + SDHOST_DataBusWidth8Bit = 2U, /* 8-bit mode */ +} SDHOST_BusWidth; + +/* Wakeup event. */ +enum +{ + SDHOST_WakeupEventOnCardInt = SDHOST_CTRL1_INTWKUP, /* Wakeup on card interrupt. */ + SDHOST_WakeupEventOnCardInsert = SDHOST_CTRL1_INSTWKUP, /* Wakeup on card insertion. */ + SDHOST_WakeupEventOnCardRemove = SDHOST_CTRL1_RMVWKUP, /* Wakeup on card removal. */ + SDHOST_WakeupEventsAll = + (SDHOST_WakeupEventOnCardInt | SDHOST_WakeupEventOnCardInsert | SDHOST_WakeupEventOnCardRemove), + /* All wakeup events */ +}; + +/* SDIO control flag. */ +enum +{ + SDHOST_StopAtBlockGapFlag = SDHOST_CTRL1_SABGREQ, /* Stop at block gap. */ + SDHOST_ReadWaitControlFlag = SDHOST_CTRL1_RWAITCTRL, /* Read wait control. */ + SDHOST_InterruptAtBlockGapFlag = SDHOST_CTRL1_INTATBG, /* Interrupt at block gap. */ +}; + + +/* Force event bit position. */ +enum +{ + SDHOST_ForceEventAutoCommand12NotExecuted = SDHOST_STSFE_ACMD12NE, /* Auto CMD12 not executed error. */ + SDHOST_ForceEventAutoCommand12Timeout = SDHOST_STSFE_ACMDTE, /* Auto CMD12 timeout error. */ + SDHOST_ForceEventAutoCommand12CrcError = SDHOST_STSFE_ACMDCRCE, /* Auto CMD12 CRC error. */ + SDHOST_ForceEventAutoCommandEndBitError = SDHOST_STSFE_ACMDEBE, /* Auto CMD end bit error. */ + SDHOST_ForceEventAutoCommand12IndexError = SDHOST_STSFE_ACMDINXE, /* Auto CMD12 index error. */ + SDHOST_ForceEventAutoCommand12NotIssued = SDHOST_STSFE_ACMD12E, /* Auto CMD12 not issued error. */ + SDHOST_ForceEventCommandTimeout = SDHOST_STSFE_CTE, /* Command timeout error. */ + SDHOST_ForceEventCommandCrcError = SDHOST_STSFE_CCRCE, /* Command CRC error. */ + SDHOST_ForceEventCommandEndBitError = SDHOST_STSFE_CEBE, /* Command end bit error. */ + SDHOST_ForceEventCommandIndexError = SDHOST_STSFE_CINXE, /* Command index error. */ + SDHOST_ForceEventDataTimeout = SDHOST_STSFE_DTE, /* Data timeout error. */ + SDHOST_ForceEventDataCrcError = SDHOST_STSFE_DCRCE, /* Data CRC error. */ + SDHOST_ForceEventDataEndBitError = SDHOST_STSFE_DEBE, /* Data end bit error. */ + SDHOST_ForceEventAutoCommand12Error = SDHOST_STSFE_ACMDE, /* Auto CMD12 error. */ + SDHOST_ForceEventAdmaError = SDHOST_STSFE_ADMAE, /* Adma error. */ +}; + + +/* Host SDMA Buffer Size. */ +typedef enum +{ + SDHOST_SDMABUFFERSIZE_4KB = ((uint32_t)0x00000000U), /* Detect A11. */ + SDHOST_SDMABUFFERSIZE_8KB = SDHOST_BLKCFG_HDBS_0, /* Detect A12. */ + SDHOST_SDMABUFFERSIZE_16KB = SDHOST_BLKCFG_HDBS_1, /* Detect A13. */ + SDHOST_SDMABUFFERSIZE_32KB = SDHOST_BLKCFG_HDBS_0 | SDHOST_BLKCFG_HDBS_1, /* Detect A14. */ + SDHOST_SDMABUFFERSIZE_64KB = SDHOST_BLKCFG_HDBS_2, /* Detect A15. */ + SDHOST_SDMABUFFERSIZE_128KB = SDHOST_BLKCFG_HDBS_2 | SDHOST_BLKCFG_HDBS_0, /* Detect A16. */ + SDHOST_SDMABUFFERSIZE_256KB = SDHOST_BLKCFG_HDBS_2 | SDHOST_BLKCFG_HDBS_1, /* Detect A17. */ + SDHOST_SDMABUFFERSIZE_512KB = SDHOST_BLKCFG_HDBS, /* NDetect A18. */ +}SDHOST_SDMA_Buffer_Size; + +/* card work mode */ +typedef enum +{ + SDMMC_DS = 0U, /* Default Speed */ + SDMMC_HS = 1U, /* High Speed */ + SDMMC_SDR12 = 2U, /* SDR12 */ + SDMMC_SDR25 = 3U, /* SDR25 */ + SDMMC_SDR50 = 4U, /* SDR50 */ + SDMMC_SDR104 = 5U, /* SDR104 */ + SDMMC_DDR50 = 6U, /* DDR50 */ + SDMMC_SPI = 7U, /* SPI mode */ +}SD_ModeConfig; + +/* Card detect signal source and test level */ +#define SDMMC_CARDDETECT_NORMAL ((uint32_t)0x00000000U) /* Select SDCD # (normal use)*/ +#define SDMMC_CARDDETECT_TEST (SDHOST_CTRL1_CDSD) /* Select card detection test level */ + +#define SDMMC_CARDTESTLEVEL_LOW ((uint32_t)0x00000000U) /* low level */ +#define SDMMC_CARDTESTLEVEL_HIGH (SDHOST_CTRL1_CDTL) /* high level */ + + +/* Private function */ +static SDMMC_STS SDMMC_TransferConfig(SDHOST_Module* SDHOSTx, uint32_t transferFlags, uint32_t blockSize, uint32_t blockCount,SDHOST_TMODE_struct *TMODE_struct); +static SDMMC_STS SDMMC_ReceiveCommandResponse(SDHOST_Module* SDHOSTx, SDMMC_CMD *command); +static uint32_t SDMMC_ReadDataPort(SDHOST_Module* SDHOSTx, SDMMC_DATA *data, uint32_t transferredWords); +static ErrorStatus SDMMC_ReadByDataPortBlocking(SDHOST_Module* SDHOSTx, SDMMC_DATA *data); +static uint32_t SDMMC_WriteDataPort(SDHOST_Module* SDHOSTx, SDMMC_DATA *data, uint32_t transferredWords); +static ErrorStatus SDMMC_WriteByDataPortBlocking(SDHOST_Module* SDHOSTx, SDMMC_DATA *data); +SDMMC_STS SDMMC_WaitCommandDone(SDHOST_Module* SDHOSTx, SDMMC_CMD *command, FunctionalState pollingCmdDone); +static SDMMC_STS SDMMC_TransferDataBlocking(SDHOST_Module* SDHOSTx, SDMMC_DATA *data, FunctionalState DMACmd); +void SDMMC_WriteData(SDHOST_Module* SDHOSTx, uint32_t data); +uint32_t SDMMC_ReadData(SDHOST_Module* SDHOSTx); + + +/* Public function */ +void SDMMC_DeInit(SDMMC_Module* SDMMCx); +ErrorStatus SDMMC_WrapperConfig(SDMMC_Module* SDMMCx, SDMMC_WrapperType *SDMMC_WrapperParam); +void SDMMC_StructWrapperInit(SDMMC_WrapperType *SDMMC_WrapperStruct); +ErrorStatus SDMMC_SoftWareReset(SDHOST_Module* SDHOSTx, uint32_t LineMask); +void SDMMC_SendCommand(SDHOST_Module* SDHOSTx, SDMMC_CMD *command,const SDHOST_TMODE_struct *TMODE_struct); +void SDMMC_GetCapability(SDHOST_Module* SDHOSTx, SDHOST_capability *capability); +void SDMMC_GetPresetvalue(SDHOST_Module* SDHOSTx, SDHOST_presetvalue *presetvalue); +void SDMMC_EnableSDCLK(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +SDMMC_STS SDMMC_WaitSDCLKStable(SDHOST_Module* SDHOSTx); +SDMMC_STS SDMMC_SetSdClock(SDHOST_Module* SDHOSTx, FunctionalState PresetCmd, uint32_t SDClock_KHz); +void SDMMC_ConfigemmcBoot(SDHOST_Module* SDHOSTx, const SDHOST_boot_config *config); +static SDMMC_STS SDMMC_ConfigInternalDma(SDHOST_Module* SDHOSTx, SDHOST_ADMAconfig *dmaConfig, const uint32_t *dataAddr, + FunctionalState enAutoCmd23,SDHOST_TMODE_struct *TMODE_struct); +static SDMMC_STS SDMMC_SetAdmaTableConfig(SDHOST_Module* SDHOSTx,SDHOST_ADMAconfig *dmaConfig, + SDMMC_DATA *dataConfig, SDHOST_TMODE_struct *TMODE_struct); +SDMMC_STS SDMMC_TransferBlocking(SDHOST_Module* SDHOSTx, SDHOST_ADMAconfig *dmaConfig, SDMMC_Transfer *transfer,SDHOST_TMODE_struct *TMODE_struct); +void SDMMC_EnableManualTuningOut(SDMMC_Module* SDMMCx, uint32_t delay,FunctionalState cmd); +void SDMMC_EnableManualTuningIN(SDMMC_Module* SDMMCx, uint32_t delay,FunctionalState cmd); +void SDMMC_FixedSampleClock(SDHOST_Module* SDHOSTx); +void SDMMC_EnableAutoTuning(SDHOST_Module* SDHOSTx, FunctionalState cmd); +void SDMMC_ConfigInt(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag, FunctionalState Cmd); +void SDMMC_EnableFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag, FunctionalState Cmd); +FlagStatus SDMMC_GetEnableFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag); +FlagStatus SDMMC_GetFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag); +void SDMMC_ClrFlag(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag); +void SDMMC_EnableForceEvent(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag, FunctionalState Cmd); +FlagStatus SDMMC_GetPresentFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_PreFlag); +FlagStatus SDMMC_GetACMDErrorStatusFlag(SDHOST_Module* SDHOSTx, uint32_t SDHOST_ACMDFlag); +FlagStatus SDMMC_GetADMAErrorStatusFlag(SDHOST_Module* SDHOSTx, uint32_t SDHOST_ADMAFlag); +void SDMMC_EnableHWReset(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +void SDMMC_ConfigWorkMode(SDHOST_Module* SDHOSTx, SD_ModeConfig mode); +void SDMMC_ConfigBusWidth(SDHOST_Module* SDHOSTx, SDHOST_BusWidth Width); +void SDMMC_EnableWakeupEvent(SDHOST_Module* SDHOSTx,uint32_t Wakeupevent, FunctionalState Cmd); +void SDMMC_EnableSdioControl(SDHOST_Module* SDHOSTx,uint32_t Sdioflag, FunctionalState Cmd); +void SDMMC_EnableContinueRequest(SDHOST_Module* SDHOSTx); +void SDMMC_EnableMmcBoot(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +void SDMMC_EnableVolSwitch(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +void SDMMC_EnablePower(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +void SDMMC_ConfigSDMABufferSize(SDHOST_Module* SDHOSTx, SDHOST_SDMA_Buffer_Size Size); +void SDMMC_TModeStructInit(SDHOST_TMODE_struct *TMODE_struct); +void SDMMC_ConfigCardDetectSignal(SDHOST_Module* SDHOSTx, uint32_t Signalsource, uint32_t Signallevel); +void SDMMC_EnableLED(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +void SDMMC_EnableAsyncInt(SDHOST_Module* SDHOSTx, FunctionalState Cmd); +void SDMMC_ConfigDATATimeoutValue(SDHOST_Module* SDHOSTx, uint32_t Count); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_78X_SDMMC_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdram.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdram.h new file mode 100644 index 0000000000..462a8e741e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_sdram.h @@ -0,0 +1,233 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_sdram.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_SDRAM_H__ +#define __N32H76X_78X_SDRAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + + +/** SDRAM Timing parameters structure definition **/ +typedef struct +{ + uint32_t RowActiveTime; /* Defines the minimum Self Refresh period in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 64 TRAS 1 */ + + uint32_t RowCycleTime; /* Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 64 TRC 2 */ + + uint32_t RowActToRowActDelay; /* Defines the delay between two active commands to different banks + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 64 TRRD 3 */ + + uint32_t PrechargeTime; /* Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 64 TRP 4 */ + + uint32_t WriteRecoveryTime; /* Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 64 TWR 5 */ + + uint32_t RefreshCycleTime; /* Defines the delay between any two consecutive commands in number + of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 64 TRFC 6 */ + + uint32_t RAStoCASDelay; /* Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 TRCD 7 */ + +} SDRAM_TimingType; + +/** Defines the number of SDRAM Devices **/ +typedef enum +{ + SDRAM_DEVICE_1 = 1, + SDRAM_DEVICE_2 +} SDRAM_DeviceType; + +/*** SDRAM Macro Definition Start ***/ +#define SDRAM_REG_BIT_MASK ((uint32_t)0x00000000U) +/** SDRAM Device Enable **/ +#define SDRAM_DEVICE_ENABLE (SDRAM_CFG_SDRAMEN) +#define SDRAM_DEVICE_DISABLE (~((uint32_t)SDRAM_CFG_SDRAMEN)) + +/** SDRAM Device Refresh Commands Enable **/ +#define SDRAM_DEVICE_REFRESH_ENABLE (SDRAM_CFG_REFRESHEN) +#define SDRAM_DEVICE_REFRESH_DISABLE (~((uint32_t)SDRAM_CFG_REFRESHEN)) + +/** SDRAM Device Auto Precharge Enable **/ +#define SDRAM_DEVICE_AUTOPRECHRG_ENABLE (SDRAM_CFG_AUTOPCHEN) +#define SDRAM_DEVICE_AUTOPRECHRG_DISABLE (~((uint32_t)SDRAM_CFG_AUTOPCHEN)) + +/** SDRAM Device Bus Width **/ +#define SDRAM_DEVICE_BUSWID_8BITS SDRAM_REG_BIT_MASK +#define SDRAM_DEVICE_BUSWID_16BITS (SDRAM_CFG_BUSWID_0) +#define SDRAM_DEVICE_BUSWID_32BITS (SDRAM_CFG_BUSWID_1) +#define SDRAM_DEVICE_BUSWID_MASK (~((uint32_t)(SDRAM_CFG_BUSWID))) + +/** SDRAM Device Burst Length **/ +#define SDRAM_DEVICE_BURSTLEN_1 SDRAM_REG_BIT_MASK +#define SDRAM_DEVICE_BURSTLEN_2 (SDRAM_CFG_BURSTLEN_0) +#define SDRAM_DEVICE_BURSTLEN_4 (SDRAM_CFG_BURSTLEN_0 | SDRAM_CFG_BURSTLEN_1) +#define SDRAM_DEVICE_BURSTLEN_8 (SDRAM_CFG_BURSTLEN_0 | SDRAM_CFG_BURSTLEN_1 | SDRAM_CFG_BURSTLEN_2) +#define SDRAM_DEVICE_BURSTLEN_MASK (~((uint32_t)(SDRAM_CFG_BURSTLEN))) + +/** SDRAM Device CAS Latency **/ +#define SDRAM_DEVICE_CASLTCY_0 SDRAM_REG_BIT_MASK +#define SDRAM_DEVICE_CASLTCY_1 (SDRAM_CFG_CASLATENCY_0) +#define SDRAM_DEVICE_CASLTCY_2 (SDRAM_CFG_CASLATENCY_1) +#define SDRAM_DEVICE_CASLTCY_3 (SDRAM_CFG_CASLATENCY_0 | SDRAM_CFG_CASLATENCY_1) +#define SDRAM_DEVICE_CASLTCY_MASK (~((uint32_t)(SDRAM_CFG_CASLATENCY))) + +/** SDRAM Device Prefetch Read Enable **/ +#define SDRAM_DEVICE_PREFETCHREAD_ENABLE (SDRAM_CFG_PREFCHRDEN) +#define SDRAM_DEVICE_PREFETCHREADG_DISABLE (~((uint32_t)SDRAM_CFG_PREFCHRDEN)) + +/** SDRAM Device Store On Miss Enable **/ +#define SDRAM_DEVICE_SOM_ENABLE (SDRAM_CFG_SOMEN) +#define SDRAM_DEVICE_SOM_DISABLE (~((uint32_t)SDRAM_CFG_SOMEN)) + +/** SDRAM Device Bank Interleaving Enable **/ +#define SDRAM_DEVICE_BANKIL_ENABLE (SDRAM_CFG_BANKINTRLEN) +#define SDRAM_DEVICE_BANKIL_DISABLE (~((uint32_t)SDRAM_CFG_BANKINTRLEN)) + +/** SDRAM Device Address Configration **/ +#define SDRAM_BANK4_ROW4096_COL256 SDRAM_REG_BIT_MASK +#define SDRAM_BANK4_ROW4096_COL512 (SDRAM_CFG_ADDCFG_0) +#define SDRAM_BANK4_ROW4096_COL1024 (SDRAM_CFG_ADDCFG_1) +#define SDRAM_BANK4_ROW4096_COL2048 (SDRAM_CFG_ADDCFG_0 | SDRAM_CFG_ADDCFG_1) + +#define SDRAM_BANK4_ROW8192_COL256 (SDRAM_CFG_ADDCFG_2) +#define SDRAM_BANK4_ROW8192_COL512 (SDRAM_CFG_ADDCFG_0 | SDRAM_CFG_ADDCFG_2) +#define SDRAM_BANK4_ROW8192_COL1024 (SDRAM_CFG_ADDCFG_1 | SDRAM_CFG_ADDCFG_2) +#define SDRAM_BANK4_ROW8192_COL2048 (SDRAM_CFG_ADDCFG_0 | SDRAM_CFG_ADDCFG_1 | SDRAM_CFG_ADDCFG_2) + +#define SDRAM_BANK4_ROW2048_COL256 (SDRAM_CFG_ADDCFG_3) +#define SDRAM_BANK4_ROW2048_COL512 (SDRAM_CFG_ADDCFG_0 | SDRAM_CFG_ADDCFG_3) +#define SDRAM_BANK4_ROW2048_COL1024 (SDRAM_CFG_ADDCFG_1 | SDRAM_CFG_ADDCFG_3) +#define SDRAM_BANK4_ROW2048_COL2048 (SDRAM_CFG_ADDCFG_0 | SDRAM_CFG_ADDCFG_1 | SDRAM_CFG_ADDCFG_3) + +#define SDRAM_DEVICE_ADDCFG_MASK (~((uint32_t)SDRAM_CFG_ADDCFG)) + +/** SDRAM Operatio Setup of Clock enable **/ +#define SDRAM_CLOCK_ENABLE (SDRAM_OS_CKEN) +#define SDRAM_CLOCK_DISABLE (~((uint32_t)SDRAM_OS_CKEN)) + +/** SDRAM Operatio Setup of Operation Code **/ +#define SDRAM_OPCODE_NONE SDRAM_REG_BIT_MASK +#define SDRAM_OPCODE_PRECHRG (SDRAM_OS_OPCODE_0) +#define SDRAM_OPCODE_REFRESH (SDRAM_OS_OPCODE_1) +#define SDRAM_OPCODE_LOADMODE (SDRAM_OS_OPCODE_0 | SDRAM_OS_OPCODE_1) +#define SDRAM_OPCODE_MASK (~((uint32_t)(SDRAM_OS_OPCODE))) + +/** SDRAM Operatio Setup of Chip Select **/ +#define SDRAM_CS_ALL SDRAM_REG_BIT_MASK +#define SDRAM_CS_SDRAM2_ONLY (SDRAM_OS_CS_0) +#define SDRAM_CS_SDRAM1_ONLY (SDRAM_OS_CS_1) +#define SDRAM_CS_NONE (SDRAM_OS_CS_0 | SDRAM_OS_CS_1) +#define SDRAM_CS_MASK (~((uint32_t)(SDRAM_OS_CS))) + +/** SDRAM Operatio Setup of Bank Address **/ +#define SDRAM_BANKADD_1 SDRAM_REG_BIT_MASK +#define SDRAM_BANKADD_2 (SDRAM_OS_BANKADD_0) +#define SDRAM_BANKADD_3 (SDRAM_OS_BANKADD_1) +#define SDRAM_BANKADD_4 (SDRAM_OS_BANKADD_0 | SDRAM_OS_BANKADD_1) +#define SDRAM_BANKADD_MASK (~((uint32_t)(SDRAM_OS_BANKADD))) + +/** SDRAM Operatio Setup of Address **/ +#define SDRAM_OS_ADDRESS_MASK (~((uint32_t)SDRAM_OS_ADD)) + +/** SDRAM Write Protection **/ +#define SDRAM_WP_SDRAM1_ENABLE (SDRAM_WP_WP1) +#define SDRAM_WP_SDRAM1_DISABLE (~((uint32_t)SDRAM_WP_WP1)) +#define SDRAM_WP_SDRAM2_ENABLE (SDRAM_WP_WP2) +#define SDRAM_WP_SDRAM2_DISABLE (~((uint32_t)SDRAM_WP_WP2)) + +#define SDRAM_REMAP_ENABLE (0x1U) +#define SDRAM_REMAP_DISABLE (0x0U) +/*** SDRAM Macro Definition End ***/ + +/** SDRAM Functions **/ +void SDRAM_DeInit(void); +void SDRAM_TimingInit(SDRAM_TimingType *Timing); +void SDRAM_RefreshIntervalInit(uint32_t RefreshIntervalTime); +void SDRAM_SetDeviceAddress(SDRAM_DeviceType DeviceNo, uint32_t BaseAddr, uint32_t AddrMask); +void SDRAM_EnableDevice(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_EnableRefreshCMD(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_EnableAutoPrecharge(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_EnablePrefetchRead(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_EnableSOM(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_EnableBankInterleave(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_ConfigBusWidth(SDRAM_DeviceType DeviceNo, uint32_t BusWidth); +void SDRAM_ConfigBurstLength(SDRAM_DeviceType DeviceNo, uint32_t BurstLength); +void SDRAM_ConfigCASLatency(SDRAM_DeviceType DeviceNo, uint32_t Latency); +void SDRAM_ConfigAddress(SDRAM_DeviceType DeviceNo, uint32_t Address); +void SDRAM_EnableClock(FunctionalState Cmd); +void SDRAM_SetOperationCode(uint32_t OperationCode); +void SDRAM_SetDeviceSelect(uint32_t ChipSelect); +void SDRAM_SetBank(uint32_t BankNo); +void SDRAM_SetAddress(uint32_t Address); +void SDRAM_EnableWriteProtection(SDRAM_DeviceType DeviceNo, FunctionalState Cmd); +void SDRAM_EnableAddressRemap(FunctionalState Cmd); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_SDRAM_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_shrtim.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_shrtim.h new file mode 100644 index 0000000000..1db51743f0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_shrtim.h @@ -0,0 +1,2292 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_shrtim.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef N32H76X_78X_SHRTIM_H +#define N32H76X_78X_SHRTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "n32h76x_78x.h" + +/*** SHRTIM structure definition start ***/ +static const uint16_t REG_OFFSET_TAB_TIMER[] = +{ + 0x00U, /* 0: MASTER */ + 0x80U, /* 1: TIMER A */ + 0x100U, /* 2: TIMER B */ + 0x180U, /* 3: TIMER C */ + 0x200U, /* 4: TIMER D */ + 0x280U, /* 5: TIMER E */ + 0x300U, /* 6: TIMER F */ +}; + +static const uint8_t REG_OFFSET_TAB_ADTGSRC[] = +{ + 0x00U, /* SHRTIM_ADCTRIG_1_GROUP1: SHRTIM_ADTG1SRC1 */ + 0x04U, /* SHRTIM_ADCTRIG_1_GROUP2: SHRTIM_ADTG1SRC2 */ + 0x08U, /* SHRTIM_ADCTRIG_2_GROUP1: SHRTIM_ADTG2SRC1 */ + 0x0CU, /* SHRTIM_ADCTRIG_2_GROUP2: SHRTIM_ADTG2SRC2 */ + 0x10U, /* SHRTIM_ADCTRIG_3_GROUP1: SHRTIM_ADTG3SRC1 */ + 0x14U, /* SHRTIM_ADCTRIG_3_GROUP2: SHRTIM_ADTG3SRC2 */ + 0x18U, /* SHRTIM_ADCTRIG_4_GROUP1: SHRTIM_ADTG4SRC1 */ + 0x1CU, /* SHRTIM_ADCTRIG_4_GROUP2: SHRTIM_ADTG4SRC2 */ + 0x50U, /* SHRTIM_ADCTRIG_5: SHRTIM_ADTGEX1 */ + 0x50U, /* SHRTIM_ADCTRIG_7: SHRTIM_ADTGEX1 */ + 0x50U, /* SHRTIM_ADCTRIG_9: SHRTIM_ADTGEX1 */ + 0x54U, /* SHRTIM_ADCTRIG_6: SHRTIM_ADTGEX2 */ + 0x54U, /* SHRTIM_ADCTRIG_8: SHRTIM_ADTGEX2 */ + 0x54U, /* SHRTIM_ADCTRIG_10: SHRTIM_ADTGEX2 */ +}; + +static const uint8_t REG_OFFSET_TAB_ADTGUPD[] = +{ + 0x00U, /* SHRTIM_ADCTRIG_1: SHRTIM_CTRL1 */ + 0x00U, /* SHRTIM_ADCTRIG_2: SHRTIM_CTRL1 */ + 0x00U, /* SHRTIM_ADCTRIG_3: SHRTIM_CTRL1 */ + 0x00U, /* SHRTIM_ADCTRIG_4: SHRTIM_CTRL1 */ + 0x98U, /* SHRTIM_ADCTRIG_5: SHRTIM_ADTGUPD */ + 0x98U, /* SHRTIM_ADCTRIG_6: SHRTIM_ADTGUPD */ + 0x98U, /* SHRTIM_ADCTRIG_7: SHRTIM_ADTGUPD */ + 0x98U, /* SHRTIM_ADCTRIG_8: SHRTIM_ADTGUPD */ + 0x98U, /* SHRTIM_ADCTRIG_9: SHRTIM_ADTGUPD */ + 0x98U, /* SHRTIM_ADCTRIG_10: SHRTIM_ADTGUPD */ +}; + +static const uint8_t REG_SHIFT_TAB_ADTGSRC[] = +{ + 0, /* SHRTIM_ADCTRIG1_SOURCE_GROUP1 */ + 0, /* SHRTIM_ADCTRIG1_SOURCE_GROUP2 */ + 0, /* SHRTIM_ADCTRIG2_SOURCE_GROUP1 */ + 0, /* SHRTIM_ADCTRIG2_SOURCE_GROUP2 */ + 0, /* SHRTIM_ADCTRIG3_SOURCE_GROUP1 */ + 0, /* SHRTIM_ADCTRIG3_SOURCE_GROUP2 */ + 0, /* SHRTIM_ADCTRIG4_SOURCE_GROUP1 */ + 0, /* SHRTIM_ADCTRIG4_SOURCE_GROUP2 */ + 0, /* SHRTIM_ADCTRIG_5 */ + 0, /* SHRTIM_ADCTRIG_6 */ + 8, /* SHRTIM_ADCTRIG_7 */ + 8, /* SHRTIM_ADCTRIG_8 */ + 16, /* SHRTIM_ADCTRIG_9 */ + 16, /* SHRTIM_ADCTRIG_10 */ +}; + +static const uint8_t REG_SHIFT_TAB_ADTGUPD[] = +{ + 16, /* SHRTIM_ADCTRIG_1 */ + 19, /* SHRTIM_ADCTRIG_2 */ + 22, /* SHRTIM_ADCTRIG_3 */ + 25, /* SHRTIM_ADCTRIG_4 */ + 0, /* SHRTIM_ADCTRIG_5 */ + 4, /* SHRTIM_ADCTRIG_6 */ + 8, /* SHRTIM_ADCTRIG_7 */ + 12, /* SHRTIM_ADCTRIG_8 */ + 16, /* SHRTIM_ADCTRIG_9 */ + 20 /* SHRTIM_ADCTRIG_10 */ +}; + +static const uint32_t REG_MASK_TAB_ADTGSRC[] = +{ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG1_SOURCE_GROUP1 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG1_SOURCE_GROUP2 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG2_SOURCE_GROUP1 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG2_SOURCE_GROUP2 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG3_SOURCE_GROUP1 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG3_SOURCE_GROUP2 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG4_SOURCE_GROUP1 */ + 0xFFFFFFFFU, /* SHRTIM_ADCTRIG4_SOURCE_GROUP2 */ + 0x0000003FU, /* SHRTIM_ADCTRIG_5 */ + 0x0000003FU, /* SHRTIM_ADCTRIG_6 */ + 0x00003F00U, /* SHRTIM_ADCTRIG_7 */ + 0x00003F00U, /* SHRTIM_ADCTRIG_8 */ + 0x003F0000U, /* SHRTIM_ADCTRIG_9 */ + 0x003F0000U, /* SHRTIM_ADCTRIG_10 */ +}; + +static const uint32_t REG_MASK_TAB_ADTGUPD[] = +{ + 0x00070000U, /* SHRTIM_ADCTRIG_1 */ + 0x00380000U, /* SHRTIM_ADCTRIG_2 */ + 0x01C00000U, /* SHRTIM_ADCTRIG_3 */ + 0x0E000000U, /* SHRTIM_ADCTRIG_4 */ + 0x00000007U, /* SHRTIM_ADCTRIG_5 */ + 0x00000070U, /* SHRTIM_ADCTRIG_6 */ + 0x00000700U, /* SHRTIM_ADCTRIG_7 */ + 0x00007000U, /* SHRTIM_ADCTRIG_8 */ + 0x00070000U, /* SHRTIM_ADCTRIG_9 */ + 0x00700000U /* SHRTIM_ADCTRIG_10 */ +}; + +static const uint8_t REG_OFFSET_TAB_ADCPSx[] = +{ + 0U, /* 0: SHRTIM_ADC1R */ + 6U, /* 1: SHRTIM_ADC2R */ + 12U, /* 2: SHRTIM_ADC3R */ + 18U, /* 3: SHRTIM_ADC4R */ + 24U, /* 4: SHRTIM_ADC5R */ + 32U, /* 5: SHRTIM_ADC6R */ + 38U, /* 6: SHRTIM_ADC7R */ + 44U, /* 7: SHRTIM_ADC8R */ + 50U, /* 8: SHRTIM_ADC9R */ + 56U /* 9: SHRTIM_ADC10R */ +}; + +static const uint16_t REG_OFFSET_TAB_TxSET[] = +{ + 0x00U, /* 0: TA1 */ + 0x08U, /* 1: TA2 */ + 0x80U, /* 2: TB1 */ + 0x88U, /* 3: TB2 */ + 0x100U, /* 4: TC1 */ + 0x108U, /* 5: TC2 */ + 0x180U, /* 6: TD1 */ + 0x188U, /* 7: TD2 */ + 0x200U, /* 8: TE1 */ + 0x208U, /* 9: TE2 */ + 0x280U, /* 10: TF1 */ + 0x288U /* 11: TF2 */ +}; + +static const uint16_t REG_OFFSET_TAB_TxOUT[] = +{ + 0x00U, /* 0: TA1 */ + 0x00U, /* 1: TA2 */ + 0x80U, /* 2: TB1 */ + 0x80U, /* 3: TB2 */ + 0x100U, /* 4: TC1 */ + 0x100U, /* 5: TC2 */ + 0x180U, /* 6: TD1 */ + 0x180U, /* 7: TD2 */ + 0x200U, /* 8: TE1 */ + 0x200U, /* 9: TE2 */ + 0x280U, /* 10: TF1 */ + 0x280U /* 11: TF2 */ +}; + +static const uint8_t REG_OFFSET_TAB_EXEVCTRL[] = +{ + 0x00U, /* SHRTIM_EVENT_1 */ + 0x00U, /* SHRTIM_EVENT_2 */ + 0x00U, /* SHRTIM_EVENT_3 */ + 0x00U, /* SHRTIM_EVENT_4 */ + 0x00U, /* SHRTIM_EVENT_5 */ + 0x04U, /* SHRTIM_EVENT_6 */ + 0x04U, /* SHRTIM_EVENT_7 */ + 0x04U, /* SHRTIM_EVENT_8 */ + 0x04U, /* SHRTIM_EVENT_9 */ + 0x04U /* SHRTIM_EVENT_10 */ +}; + +static const uint8_t REG_OFFSET_TAB_FALTIN[] = +{ + 0x00U, /* SHRTIM_FAULT_1 */ + 0x00U, /* SHRTIM_FAULT_2 */ + 0x00U, /* SHRTIM_FAULT_3 */ + 0x00U, /* SHRTIM_FAULT_4 */ + 0x04U, /* SHRTIM_FAULT_5 */ + 0x04U /* SHRTIM_FAULT_6 */ +}; + +static const uint32_t REG_MASK_TAB_UPDATETRIG[] = +{ + 0x20000000U, /* 0: MASTER */ + 0x01FF0000U, /* 1: TIMER A */ + 0x01FF0000U, /* 2: TIMER B */ + 0x01FF0000U, /* 3: TIMER C */ + 0x01FF0000U, /* 4: TIMER D */ + 0x01FF0000U, /* 5: TIMER E */ + 0x01FF0000U, /* 5: TIMER E */ + 0x01FF0000U /* 6: TIMER F */ +}; + +static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] = +{ + 12U, /* 0: MASTER */ + 0U, /* 1: TIMER A */ + 0U, /* 2: TIMER B */ + 0U, /* 3: TIMER C */ + 0U, /* 4: TIMER D */ + 0U, /* 5: TIMER E */ + 0U /* 6: TIMER F */ +}; + +static const uint8_t REG_SHIFT_TAB_EXEVx[] = +{ + 0U, /* SHRTIM_EVENT_1 */ + 6U, /* SHRTIM_EVENT_2 */ + 12U, /* SHRTIM_EVENT_3 */ + 18U, /* SHRTIM_EVENT_4 */ + 24U, /* SHRTIM_EVENT_5 */ + 0U, /* SHRTIM_EVENT_6 */ + 6U, /* SHRTIM_EVENT_7 */ + 12U, /* SHRTIM_EVENT_8 */ + 18U, /* SHRTIM_EVENT_9 */ + 24U /* SHRTIM_EVENT_10 */ +}; + +static const uint8_t REG_SHIFT_TAB_EXEVxCSEL[] = +{ + 0U, /* SHRTIM_EVENT_1 */ + 3U, /* SHRTIM_EVENT_2 */ + 6U, /* SHRTIM_EVENT_3 */ + 9U, /* SHRTIM_EVENT_4 */ + 12U, /* SHRTIM_EVENT_5 */ + 15U, /* SHRTIM_EVENT_6 */ + 18U, /* SHRTIM_EVENT_7 */ + 21U, /* SHRTIM_EVENT_8 */ + 24U, /* SHRTIM_EVENT_9 */ + 27U /* SHRTIM_EVENT_10 */ +}; + +static const uint8_t REG_SHIFT_TAB_FALTxCSEL[] = +{ + 0U, /* SHRTIM_FAULT_1 */ + 4U, /* SHRTIM_FAULT_2 */ + 8U, /* SHRTIM_FAULT_3 */ + 12U, /* SHRTIM_FAULT_4 */ + 16U, /* SHRTIM_FAULT_5 */ + 20U, /* SHRTIM_FAULT_6 */ +}; + +static const uint32_t REG_MASK_TAB_UPDATEGATING[] = +{ + SHRTIM_MCTRL_BRSTDMA, /* 0: MASTER */ + SHRTIM_TXCTRL_UPDGAT, /* 1: TIMER A */ + SHRTIM_TXCTRL_UPDGAT, /* 2: TIMER B */ + SHRTIM_TXCTRL_UPDGAT, /* 3: TIMER C */ + SHRTIM_TXCTRL_UPDGAT, /* 4: TIMER D */ + SHRTIM_TXCTRL_UPDGAT, /* 5: TIMER E */ + SHRTIM_TXCTRL_UPDGAT /* 6: TIMER F */ +}; + +static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] = +{ + 2U, /* 0: MASTER */ + 0U, /* 1: TIMER A */ + 0U, /* 2: TIMER B */ + 0U, /* 3: TIMER C */ + 0U, /* 4: TIMER D */ + 0U, /* 5: TIMER E */ + 0U /* 6: TIMER F */ +}; + +static const uint8_t REG_SHIFT_TAB_TxOUT[] = +{ + 0U, /* 0: TA1 */ + 16U, /* 1: TA2 */ + 0U, /* 2: TB1 */ + 16U, /* 3: TB2 */ + 0U, /* 4: TC1 */ + 16U, /* 5: TC2 */ + 0U, /* 6: TD1 */ + 16U, /* 7: TD2 */ + 0U, /* 8: TE1 */ + 16U, /* 9: TE2 */ + 0U, /* 10: TF1 */ + 16U /* 11: TF2 */ +}; + +static const uint8_t REG_SHIFT_TAB_OxSTS[] = +{ + 0U, /* 0: TA1 */ + 1U, /* 1: TA2 */ + 0U, /* 2: TB1 */ + 1U, /* 3: TB2 */ + 0U, /* 4: TC1 */ + 1U, /* 5: TC2 */ + 0U, /* 6: TD1 */ + 1U, /* 7: TD2 */ + 0U, /* 8: TE1 */ + 1U, /* 9: TE2 */ + 0U, /* 10: TF1 */ + 1U /* 11: TF2 */ +}; + +static const uint8_t REG_SHIFT_TAB_FALTxE[] = +{ + 0U, /* SHRTIM_FAULT_1 */ + 8U, /* SHRTIM_FAULT_2 */ + 16U, /* SHRTIM_FAULT_3 */ + 24U, /* SHRTIM_FAULT_4 */ + 0U, /* SHRTIM_FAULT_5 */ + 8U /* SHRTIM_FAULT_6 */ +}; + +static const uint8_t REG_SHIFT_TAB_FALTxF[] = +{ + 0U, /* SHRTIM_FAULT_1 */ + 8U, /* SHRTIM_FAULT_2 */ + 16U, /* SHRTIM_FAULT_3 */ + 24U, /* SHRTIM_FAULT_4 */ + 32U, /* SHRTIM_FAULT_5 */ + 40U /* SHRTIM_FAULT_6 */ +}; + +static const uint8_t REG_SHIFT_TAB_FALTx[] = +{ + 0, /* SHRTIM_FAULT_1 */ + 1, /* SHRTIM_FAULT_2 */ + 2, /* SHRTIM_FAULT_3 */ + 3, /* SHRTIM_FAULT_4 */ + 4, /* SHRTIM_FAULT_5 */ + 5 /* SHRTIM_FAULT_6 */ +}; + +static const uint8_t REG_SHIFT_TAB_ILV[] = +{ + 0U, /* 0: MASTER */ + 1U, /* 1: TIMER A */ + 1U, /* 2: TIMER B */ + 1U, /* 3: TIMER C */ + 1U, /* 4: TIMER D */ + 1U, /* 5: TIMER E */ + 1U, /* 6: TIMER F */ +}; + +static const uint32_t REG_MASK_TAB_ILV[] = +{ + 0x000000E0U, /* 0: MASTER */ + 0x000001A0U, /* 1: TIMER A */ + 0x000001A0U, /* 2: TIMER B */ + 0x000001A0U, /* 3: TIMER C */ + 0x000001A0U, /* 4: TIMER D */ + 0x000001A0U, /* 5: TIMER E */ + 0x000001A0U, /* 6: TIMER F */ +}; + +static const uint8_t REG_SHIFT_TAB_CPT[] = +{ + 12U, /* 1: TIMER A */ + 16U, /* 2: TIMER B */ + 20U, /* 3: TIMER C */ + 24U, /* 4: TIMER D */ + 28U, /* 5: TIMER E */ + 32U, /* 6: TIMER F */ +}; + +static const uint32_t REG_MASK_TAB_CPT[] = +{ + 0xFFFF0000U, /* 1: TIMER A */ + 0xFFF0F000U, /* 2: TIMER B */ + 0xFF0FF000U, /* 3: TIMER C */ + 0xF0FFF000U, /* 4: TIMER D */ + 0x0FFFF000U, /* 5: TIMER E */ + 0xFFFFF000U, /* 6: TIMER F */ +}; +/*** SHRTIM structure definition end ***/ + + + +/*** SHRTIM macro definitions start ***/ +#define SHRTIM_CTRL1_UDIS_MASK ((uint32_t)(SHRTIM_CTRL1_MUPDDIS |\ + SHRTIM_CTRL1_TAUPDDIS |\ + SHRTIM_CTRL1_TBUPDDIS |\ + SHRTIM_CTRL1_TCUPDDIS |\ + SHRTIM_CTRL1_TDUPDDIS |\ + SHRTIM_CTRL1_TEUPDDIS |\ + SHRTIM_CTRL1_TFUPDDIS)) + +#define SHRTIM_CTRL2_SWUPD_MASK ((uint32_t)(SHRTIM_CTRL2_MSWUPD |\ + SHRTIM_CTRL2_TASWUPD |\ + SHRTIM_CTRL2_TBSWUPD |\ + SHRTIM_CTRL2_TCSWUPD |\ + SHRTIM_CTRL2_TDSWUPD |\ + SHRTIM_CTRL2_TESWUPD |\ + SHRTIM_CTRL2_TFSWUPD)) + +#define SHRTIM_CTRL2_SWAP_MASK ((uint32_t)(SHRTIM_CTRL2_SWAPA |\ + SHRTIM_CTRL2_SWAPB |\ + SHRTIM_CTRL2_SWAPC |\ + SHRTIM_CTRL2_SWAPD |\ + SHRTIM_CTRL2_SWAPE |\ + SHRTIM_CTRL2_SWAPF)) + +#define SHRTIM_CTRL2_SWRST_MASK ((uint32_t)(SHRTIM_CTRL2_MSWCNTRST |\ + SHRTIM_CTRL2_TASWCNTRST |\ + SHRTIM_CTRL2_TBSWCNTRST |\ + SHRTIM_CTRL2_TCSWCNTRST |\ + SHRTIM_CTRL2_TDSWCNTRST |\ + SHRTIM_CTRL2_TESWCNTRST |\ + SHRTIM_CTRL2_TFSWCNTRST)) + +#define SHRTIM_OEN_OEN_MASK ((uint32_t)(SHRTIM_OEN_TA1OEN |\ + SHRTIM_OEN_TA2OEN |\ + SHRTIM_OEN_TB1OEN |\ + SHRTIM_OEN_TB2OEN |\ + SHRTIM_OEN_TC1OEN |\ + SHRTIM_OEN_TC2OEN |\ + SHRTIM_OEN_TD1OEN |\ + SHRTIM_OEN_TD2OEN |\ + SHRTIM_OEN_TE1OEN |\ + SHRTIM_OEN_TE2OEN |\ + SHRTIM_OEN_TF1OEN |\ + SHRTIM_OEN_TF2OEN)) + +#define SHRTIM_ODIS_ODIS_MASK ((uint32_t)(SHRTIM_ODIS_TA1ODIS |\ + SHRTIM_ODIS_TA2ODIS |\ + SHRTIM_ODIS_TB1ODIS |\ + SHRTIM_ODIS_TB2ODIS |\ + SHRTIM_ODIS_TC1ODIS |\ + SHRTIM_ODIS_TC2ODIS |\ + SHRTIM_ODIS_TD1ODIS |\ + SHRTIM_ODIS_TD2ODIS |\ + SHRTIM_ODIS_TE1ODIS |\ + SHRTIM_ODIS_TE2ODIS |\ + SHRTIM_ODIS_TF1ODIS |\ + SHRTIM_ODIS_TF2ODIS)) + +#define SHRTIM_OUT_CONFIG_MASK ((uint32_t)(SHRTIM_TXOUT_POL1 |\ + SHRTIM_TXOUT_IDLES1 |\ + SHRTIM_TXOUT_FALT1 |\ + SHRTIM_TXOUT_CHP1 |\ + SHRTIM_TXOUT_DIDL1)) + +#define SHRTIM_FALT_CONFIG_MASK ((uint32_t)(SHRTIM_FALTIN1_FALT1POL |\ + SHRTIM_FALTIN1_FALT1SRC0 )) + +#define SHRTIM_FALT_SRC_1_MASK ((uint32_t)(SHRTIM_FALTIN2_FALT6SRC1 |\ + SHRTIM_FALTIN2_FALT5SRC1 |\ + SHRTIM_FALTIN2_FALT4SRC1 |\ + SHRTIM_FALTIN2_FALT3SRC1 |\ + SHRTIM_FALTIN2_FALT2SRC1 |\ + SHRTIM_FALTIN2_FALT1SRC1)) + +#define SHRTIM_BM_CONFIG_MASK ((uint32_t)( SHRTIM_BMCTRL_BMPSC |\ + SHRTIM_BMCTRL_BMCK |\ + SHRTIM_BMCTRL_BMOM)) + +#define SHRTIM_FRZDIS_CONFIG_MASK ((uint32_t)(SHRTIM_FRZDIS_TFDBGEN |\ + SHRTIM_FRZDIS_TEDBGEN |\ + SHRTIM_FRZDIS_TDDBGEN |\ + SHRTIM_FRZDIS_TCDBGEN |\ + SHRTIM_FRZDIS_TBDBGEN |\ + SHRTIM_FRZDIS_TADBGEN |\ + SHRTIM_FRZDIS_MDBGEN)) + +#define SHRTIM_SFTDP_CONFIG_MASK ((uint32_t)(SHRTIM_SFTDP_SFTDPA1 |\ + SHRTIM_SFTDP_SFTDPA2 |\ + SHRTIM_SFTDP_SFTDPB1 |\ + SHRTIM_SFTDP_SFTDPB2 |\ + SHRTIM_SFTDP_SFTDPC1 |\ + SHRTIM_SFTDP_SFTDPC2 |\ + SHRTIM_SFTDP_SFTDPD1 |\ + SHRTIM_SFTDP_SFTDPD2 |\ + SHRTIM_SFTDP_SFTDPE1 |\ + SHRTIM_SFTDP_SFTDPE2 |\ + SHRTIM_SFTDP_SFTDPF1 |\ + SHRTIM_SFTDP_SFTDPF2)) + + +/** Flags defines which can be used with SHRTIM_ReadReg function **/ +#define SHRTIM_INTERRUPT_STATUS_FALT1ITF SHRTIM_INTSTS_FALT1ITF +#define SHRTIM_INTERRUPT_STATUS_FALT2ITF SHRTIM_INTSTS_FALT2ITF +#define SHRTIM_INTERRUPT_STATUS_FALT3ITF SHRTIM_INTSTS_FALT3ITF +#define SHRTIM_INTERRUPT_STATUS_FALT4ITF SHRTIM_INTSTS_FALT4ITF +#define SHRTIM_INTERRUPT_STATUS_FALT5ITF SHRTIM_INTSTS_FALT5ITF +#define SHRTIM_INTERRUPT_STATUS_FALT6ITF SHRTIM_INTSTS_FALT6ITF +#define SHRTIM_INTERRUPT_STATUS_SYSFALTITF SHRTIM_INTSTS_SYSFALTITF +#define SHRTIM_INTERRUPT_STATUS_BMPRDITF SHRTIM_INTSTS_BMPRDITF + +#define SHRTIM_MASTER_INTERRUPT_STATUS_MCMP1ITF SHRTIM_MINTSTS_MCMP1ITF +#define SHRTIM_MASTER_INTERRUPT_STATUS_MCMP2ITF SHRTIM_MINTSTS_MCMP2ITF +#define SHRTIM_MASTER_INTERRUPT_STATUS_MCMP3ITF SHRTIM_MINTSTS_MCMP3ITF +#define SHRTIM_MASTER_INTERRUPT_STATUS_MCMP4ITF SHRTIM_MINTSTS_MCMP4ITF +#define SHRTIM_MASTER_INTERRUPT_STATUS_MREPTITF SHRTIM_MINTSTS_MREPTITF +#define SHRTIM_MASTER_INTERRUPT_STATUS_SYNCINITF SHRTIM_MINTSTS_SYNCINITF +#define SHRTIM_MASTER_INTERRUPT_STATUS_MUPDITF SHRTIM_MINTSTS_MUPDITF + +#define SHRTIM_TX_INTERRUPT_STATUS_CMP1ITF SHRTIM_TXINTSTS_CMP1ITF +#define SHRTIM_TX_INTERRUPT_STATUS_CMP2ITF SHRTIM_TXINTSTS_CMP2ITF +#define SHRTIM_TX_INTERRUPT_STATUS_CMP3ITF SHRTIM_TXINTSTS_CMP3ITF +#define SHRTIM_TX_INTERRUPT_STATUS_CMP4ITF SHRTIM_TXINTSTS_CMP4ITF +#define SHRTIM_TX_INTERRUPT_STATUS_REPTITF SHRTIM_TXINTSTS_REPTITF +#define SHRTIM_TX_INTERRUPT_STATUS_UPDITF SHRTIM_TXINTSTS_UPDITF +#define SHRTIM_TX_INTERRUPT_STATUS_CPT1ITF SHRTIM_TXINTSTS_CPT1ITF +#define SHRTIM_TX_INTERRUPT_STATUS_CPT2ITF SHRTIM_TXINTSTS_CPT2ITF +#define SHRTIM_TX_INTERRUPT_STATUS_SET1ITF SHRTIM_TXINTSTS_SET1ITF +#define SHRTIM_TX_INTERRUPT_STATUS_RST1ITF SHRTIM_TXINTSTS_RST1ITF +#define SHRTIM_TX_INTERRUPT_STATUS_SET2ITF SHRTIM_TXINTSTS_SET2ITF +#define SHRTIM_TX_INTERRUPT_STATUS_RST2ITF SHRTIM_TXINTSTS_RST2ITF +#define SHRTIM_TX_INTERRUPT_STATUS_RSTROITF SHRTIM_TXINTSTS_RSTROITF +#define SHRTIM_TX_INTERRUPT_STATUS_DPITF SHRTIM_TXINTSTS_DPITF + +/** Defines which can be used with SHRTIM_ReadReg and SHRTIM_WriteReg functions **/ +#define SHRTIM_INTERRUPT_ENABLE_FALT1IEN SHRTIM_INTEN_FALT1IEN +#define SHRTIM_INTERRUPT_ENABLE_FALT2IEN SHRTIM_INTEN_FALT2IEN +#define SHRTIM_INTERRUPT_ENABLE_FALT3IEN SHRTIM_INTEN_FALT3IEN +#define SHRTIM_INTERRUPT_ENABLE_FALT4IEN SHRTIM_INTEN_FALT4IEN +#define SHRTIM_INTERRUPT_ENABLE_FALT5IEN SHRTIM_INTEN_FALT5IEN +#define SHRTIM_INTERRUPT_ENABLE_FALT6IEN SHRTIM_INTEN_FALT6IEN +#define SHRTIM_INTERRUPT_ENABLE_SYSFALTIEN SHRTIM_INTEN_SYSFALTIEN +#define SHRTIM_INTERRUPT_ENABLE_BMPRDIEN SHRTIM_INTEN_BMPRDIEN + +#define SHRTIM_MASTER_INTERRUPT_ENABLE_MCMP1IEN SHRTIM_MIDEN_MCMP1IEN +#define SHRTIM_MASTER_INTERRUPT_ENABLE_MCMP2IEN SHRTIM_MIDEN_MCMP2IEN +#define SHRTIM_MASTER_INTERRUPT_ENABLE_MCMP3IEN SHRTIM_MIDEN_MCMP3IEN +#define SHRTIM_MASTER_INTERRUPT_ENABLE_MCMP4IEN SHRTIM_MIDEN_MCMP4IEN +#define SHRTIM_MASTER_INTERRUPT_ENABLE_MREPTIEN SHRTIM_MIDEN_MREPTIEN +#define SHRTIM_MASTER_INTERRUPT_ENABLE_SYNCINIEN SHRTIM_MIDEN_SYNCINIEN +#define SHRTIM_MASTER_INTERRUPT_ENABLE_MUPDIEN SHRTIM_MIDEN_MUPDIEN + +#define SHRTIM_TX_INTERRUPT_ENABLE_CMP1IEN SHRTIM_TXIDEN_CMP1IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_CMP2IEN SHRTIM_TXIDEN_CMP2IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_CMP3IEN SHRTIM_TXIDEN_CMP3IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_CMP4IEN SHRTIM_TXIDEN_CMP4IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_REPTIEN SHRTIM_TXIDEN_REPTIEN +#define SHRTIM_TX_INTERRUPT_ENABLE_UPDIEN SHRTIM_TXIDEN_UPDIEN +#define SHRTIM_TX_INTERRUPT_ENABLE_CPT1IEN SHRTIM_TXIDEN_CPT1IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_CPT2IEN SHRTIM_TXIDEN_CPT2IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_SET1IEN SHRTIM_TXIDEN_SET1IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_RST1IEN SHRTIM_TXIDEN_RST1IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_SET2IEN SHRTIM_TXIDEN_SET2IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_RST2IEN SHRTIM_TXIDEN_RST2IEN +#define SHRTIM_TX_INTERRUPT_ENABLE_RSTRODEN SHRTIM_TXIDEN_RSTRODEN +#define SHRTIM_TX_INTERRUPT_ENABLE_DPIEN SHRTIM_TXIDEN_DPIEN + + +/** Defining the synchronization input source. **/ +#define SHRTIM_SYNCIN_SRC_NONE 0x00000000U /* SHRTIM is not synchronized and runs in standalone mode */ +#define SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_0 (SHRTIM_MCTRL_SYNCIN_0) /* The SHRTIM is synchronized with the on-chip timer, from ATIM1 trgo */ +#define SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_1 (SHRTIM_MCTRL_SYNCIN_1) /* The SHRTIM is synchronized with the on-chip timer from ATIM2 trgo */ +#define SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_2 (SHRTIM_MCTRL_SYNCIN_1 | SHRTIM_MCTRL_SYNCIN_0) /* The SHRTIM is synchronized with the on-chip timer, from ATIM3 trgo */ +#define SHRTIM_SYNCIN_SRC_EXTERNAL_EVENT_3 (SHRTIM_MCTRL_SYNCIN_2) /* A positive pulse on SYNCIN input triggers the SHRTIM */ +#define SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_4 (SHRTIM_MCTRL_SYNCIN_2 | SHRTIM_MCTRL_SYNCIN_0) /* The SHRTIM is synchronized with the on-chip timer, from shrtim_out_sync2 of another SHRTIM */ + + +/** Defining the source and event to be sent on the synchronization output. */ +#define SHRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /* A pulse is sent on SHRTIM_SCOUT output and shrtim_out_sync2 upon master timer start event */ +#define SHRTIM_SYNCOUT_SRC_MASTER_CMP1 (SHRTIM_MCTRL_SYNCOSRC_0) /* A pulse is sent on SHRTIM_SCOUT output and shrtim_out_sync2 upon master timer compare 1 event */ +#define SHRTIM_SYNCOUT_SRC_TIMA_START (SHRTIM_MCTRL_SYNCOSRC_1) /* A pulse is sent on SHRTIM_SCOUT output and shrtim_out_sync2 upon timer A start or reset events */ +#define SHRTIM_SYNCOUT_SRC_TIMA_CMP1 (SHRTIM_MCTRL_SYNCOSRC_1 | SHRTIM_MCTRL_SYNCOSRC_0) /* A pulse is sent on SHRTIM_SCOUT output and shrtim_out_sync2 upon timer A compare 1 event */ + + +/** Defining the routing and conditioning of the synchronization output event. */ +#define SHRTIM_SYNCOUT_DISABLED 0x00000000U /* Synchronization output event is disabled */ +#define SHRTIM_SYNCOUT_POSITIVE_PULSE (SHRTIM_SYNCOUT_SYNCOUTPUS_1) /* Synchronization output has a low idle level and issues a positive pulse of 16 fSHRTIM clock cycles length for the synchronization */ +#define SHRTIM_SYNCOUT_NEGATIVE_PULSE (SHRTIM_SYNCOUT_SYNCOUTPUS_1 | SHRTIM_SYNCOUT_SYNCOUTPUS_0) /* Synchronization output has a high idle level and issues a negative pulse of 16 fSHRTIM clock cycles length for the synchronization */ + + +/** Identifying a timing unit. **/ +#define SHRTIM_TIMER_NONE 0U /* Master timer identifier */ +#define SHRTIM_TIMER_MASTER SHRTIM_MCTRL_MCNTEN /* Master timer identifier */ +#define SHRTIM_TIMER_A SHRTIM_MCTRL_TACNTEN /* Timer A identifier */ +#define SHRTIM_TIMER_B SHRTIM_MCTRL_TBCNTEN /* Timer B identifier */ +#define SHRTIM_TIMER_C SHRTIM_MCTRL_TCCNTEN /* Timer C identifier */ +#define SHRTIM_TIMER_D SHRTIM_MCTRL_TDCNTEN /* Timer D identifier */ +#define SHRTIM_TIMER_E SHRTIM_MCTRL_TECNTEN /* Timer E identifier */ +#define SHRTIM_TIMER_F SHRTIM_MCTRL_TFCNTEN /* Timer F identifier */ + +#define SHRTIM_TIMER_X (SHRTIM_MCTRL_TFCNTEN | SHRTIM_MCTRL_TACNTEN |\ + SHRTIM_MCTRL_TBCNTEN | SHRTIM_MCTRL_TCCNTEN |\ + SHRTIM_MCTRL_TDCNTEN | SHRTIM_MCTRL_TECNTEN ) +#define SHRTIM_TIMER_ALL (SHRTIM_TIMER_MASTER | SHRTIM_TIMER_X) + +/** Identifying an SHRTIM output. **/ +#define SHRTIM_OUTPUT_TA1 SHRTIM_OEN_TA1OEN /* Timer A - Output 1 identifier */ +#define SHRTIM_OUTPUT_TA2 SHRTIM_OEN_TA2OEN /* Timer A - Output 2 identifier */ +#define SHRTIM_OUTPUT_TB1 SHRTIM_OEN_TB1OEN /* Timer B - Output 1 identifier */ +#define SHRTIM_OUTPUT_TB2 SHRTIM_OEN_TB2OEN /* Timer B - Output 2 identifier */ +#define SHRTIM_OUTPUT_TC1 SHRTIM_OEN_TC1OEN /* Timer C - Output 1 identifier */ +#define SHRTIM_OUTPUT_TC2 SHRTIM_OEN_TC2OEN /* Timer C - Output 2 identifier */ +#define SHRTIM_OUTPUT_TD1 SHRTIM_OEN_TD1OEN /* Timer D - Output 1 identifier */ +#define SHRTIM_OUTPUT_TD2 SHRTIM_OEN_TD2OEN /* Timer D - Output 2 identifier */ +#define SHRTIM_OUTPUT_TE1 SHRTIM_OEN_TE1OEN /* Timer E - Output 1 identifier */ +#define SHRTIM_OUTPUT_TE2 SHRTIM_OEN_TE2OEN /* Timer E - Output 2 identifier */ +#define SHRTIM_OUTPUT_TF1 SHRTIM_OEN_TF1OEN /* Timer F - Output 1 identifier */ +#define SHRTIM_OUTPUT_TF2 SHRTIM_OEN_TF2OEN /* Timer F - Output 2 identifier */ + +/** Identifying a compare unit. **/ +#define SHRTIM_COMPAREUNIT_2 SHRTIM_TXCTRL_DELCMP2M /* Compare unit 2 identifier */ +#define SHRTIM_COMPAREUNIT_4 SHRTIM_TXCTRL_DELCMP4M /* Compare unit 4 identifier */ + + +/** Identifying a capture unit. **/ +#define SHRTIM_CAPTUREUNIT_1 0 /* Capture unit 1 identifier */ +#define SHRTIM_CAPTUREUNIT_2 1 /* Capture unit 2 identifier */ + + +/** Identifying a fault channel. **/ +#define SHRTIM_FAULT_1 SHRTIM_TXFALT_FALT1EN /* Fault channel 1 identifier */ +#define SHRTIM_FAULT_2 SHRTIM_TXFALT_FALT2EN /* Fault channel 2 identifier */ +#define SHRTIM_FAULT_3 SHRTIM_TXFALT_FALT3EN /* Fault channel 3 identifier */ +#define SHRTIM_FAULT_4 SHRTIM_TXFALT_FALT4EN /* Fault channel 4 identifier */ +#define SHRTIM_FAULT_5 SHRTIM_TXFALT_FALT5EN /* Fault channel 5 identifier */ +#define SHRTIM_FAULT_6 SHRTIM_TXFALT_FALT6EN /* Fault channel 6 identifier */ + + +/** Identifying an external event channel. **/ +#define SHRTIM_EVENT_1 ((uint32_t)0x00000001U) /* External event channel 1 identifier */ +#define SHRTIM_EVENT_2 ((uint32_t)0x00000002U) /* External event channel 2 identifier */ +#define SHRTIM_EVENT_3 ((uint32_t)0x00000004U) /* External event channel 3 identifier */ +#define SHRTIM_EVENT_4 ((uint32_t)0x00000008U) /* External event channel 4 identifier */ +#define SHRTIM_EVENT_5 ((uint32_t)0x00000010U) /* External event channel 5 identifier */ +#define SHRTIM_EVENT_6 ((uint32_t)0x00000020U) /* External event channel 6 identifier */ +#define SHRTIM_EVENT_7 ((uint32_t)0x00000040U) /* External event channel 7 identifier */ +#define SHRTIM_EVENT_8 ((uint32_t)0x00000080U) /* External event channel 8 identifier */ +#define SHRTIM_EVENT_9 ((uint32_t)0x00000100U) /* External event channel 9 identifier */ +#define SHRTIM_EVENT_10 ((uint32_t)0x00000200U) /* External event channel 10 identifier */ + +#define SHRTIM_EXEV_SOURCE_1 ((uint32_t)0x00000000U) /* Eternal event source is from GPIO */ +#define SHRTIM_EXEV_SOURCE_2 ((uint32_t)0x00000001U) /* Eternal event source is from Comparator */ +#define SHRTIM_EXEV_SOURCE_3 ((uint32_t)0x00000002U) /* Eternal event source is from timer */ +#define SHRTIM_EXEV_SOURCE_4 ((uint32_t)0x00000003U) /* Eternal event source is from adc analog watch dog */ +#define SHRTIM_EXEV_SOURCE_5 ((uint32_t)0x00000004U) /* Eternal event source is from CAN */ + +/** Defining the state of an SHRTIM output. **/ +#define SHRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /* Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */ +#define SHRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /* Default operating state (e.g. after an SHRTIM reset, when the outputs are disabled by software or during a burst mode operation) */ +#define SHRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /* Safety state, entered in case of a shut-down request on FAULTx inputs */ + + +/** Identifying an ADC trigger source register. **/ +#define SHRTIM_ADCTRIG1_SOURCE_GROUP1 ((uint32_t)0x00000000U) /* ADC trigger 1's source group 1 identifier */ +#define SHRTIM_ADCTRIG1_SOURCE_GROUP2 ((uint32_t)0x00000001U) /* ADC trigger 1's source group 2 identifier */ +#define SHRTIM_ADCTRIG2_SOURCE_GROUP1 ((uint32_t)0x00000002U) /* ADC trigger 2's source group 1 identifier */ +#define SHRTIM_ADCTRIG2_SOURCE_GROUP2 ((uint32_t)0x00000003U) /* ADC trigger 2's source group 2 identifier */ +#define SHRTIM_ADCTRIG3_SOURCE_GROUP1 ((uint32_t)0x00000004U) /* ADC trigger 3's source group 1 identifier */ +#define SHRTIM_ADCTRIG3_SOURCE_GROUP2 ((uint32_t)0x00000005U) /* ADC trigger 3's source group 2 identifier */ +#define SHRTIM_ADCTRIG4_SOURCE_GROUP1 ((uint32_t)0x00000006U) /* ADC trigger 4's source group 1 identifier */ +#define SHRTIM_ADCTRIG4_SOURCE_GROUP2 ((uint32_t)0x00000007U) /* ADC trigger 4's source group 2 identifier */ +#define SHRTIM_ADCTRIG5_SOURCE ((uint32_t)0x00000008U) /* ADC trigger 5 identifier */ +#define SHRTIM_ADCTRIG6_SOURCE ((uint32_t)0x00000009U) /* ADC trigger 6 identifier */ +#define SHRTIM_ADCTRIG7_SOURCE ((uint32_t)0x0000000AU) /* ADC trigger 7 identifier */ +#define SHRTIM_ADCTRIG8_SOURCE ((uint32_t)0x0000000BU) /* ADC trigger 8 identifier */ +#define SHRTIM_ADCTRIG9_SOURCE ((uint32_t)0x0000000CU) /* ADC trigger 9 identifier */ +#define SHRTIM_ADCTRIG10_SOURCE ((uint32_t)0x0000000DU) /* ADC trigger 10 identifier */ + +/** Identifying the ADC trigger's **/ +#define SHRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /* ADC trigger 1's identifier */ +#define SHRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /* ADC trigger 2's identifier */ +#define SHRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /* ADC trigger 3's identifier */ +#define SHRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /* ADC trigger 4's identifier */ +#define SHRTIM_ADCTRIG_5 ((uint32_t)0x00000004U) /* ADC trigger 5's identifier */ +#define SHRTIM_ADCTRIG_6 ((uint32_t)0x00000005U) /* ADC trigger 6's identifier */ +#define SHRTIM_ADCTRIG_7 ((uint32_t)0x00000006U) /* ADC trigger 7's identifier */ +#define SHRTIM_ADCTRIG_8 ((uint32_t)0x00000007U) /* ADC trigger 8's identifier */ +#define SHRTIM_ADCTRIG_9 ((uint32_t)0x00000008U) /* ADC trigger 9's identifier */ +#define SHRTIM_ADCTRIG_10 ((uint32_t)0x00000009U) /* ADC trigger 10's identifier */ + +/** Defining the source triggering the update of the SHRTIM_ADCxR register (transfer from preload to active register). **/ +#define SHRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /* SHRTIM_ADCxR register update is triggered by the Master timer */ +#define SHRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /* SHRTIM_ADCxR register update is triggered by the Timer A */ +#define SHRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /* SHRTIM_ADCxR register update is triggered by the Timer B */ +#define SHRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /* SHRTIM_ADCxR register update is triggered by the Timer C */ +#define SHRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /* SHRTIM_ADCxR register update is triggered by the Timer D */ +#define SHRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /* SHRTIM_ADCxR register update is triggered by the Timer E */ +#define SHRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /* SHRTIM_ADCxR register update is triggered by the Timer F */ + +/** defining the events triggering ADC conversion for ADC Triggers 1 and 3. **/ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TCPRD SHRTIM_ADTG1SRC1_ADTG1TCPRD /* ADC trigger driven by timer C period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP5 SHRTIM_ADTG1SRC1_ADTG1TCCMP5 /* ADC trigger driven by timer C compare 5 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP4 SHRTIM_ADTG1SRC1_ADTG1TCCMP4 /* ADC trigger driven by timer C compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP3 SHRTIM_ADTG1SRC1_ADTG1TCCMP3 /* ADC trigger driven by timer C compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP2 SHRTIM_ADTG1SRC1_ADTG1TCCMP2 /* ADC trigger driven by timer C compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP1 SHRTIM_ADTG1SRC1_ADTG1TCCMP1 /* ADC trigger driven by timer C compare 1 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBRSTRO SHRTIM_ADTG1SRC1_ADTG1TBRSTRO /* ADC trigger driven by timer B reset and roll-over events */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBPRD SHRTIM_ADTG1SRC1_ADTG1TBPRD /* ADC trigger driven by timer B period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP5 SHRTIM_ADTG1SRC1_ADTG1TBCMP5 /* ADC trigger driven by timer B compare 5 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP4 SHRTIM_ADTG1SRC1_ADTG1TBCMP4 /* ADC trigger driven by timer B compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP3 SHRTIM_ADTG1SRC1_ADTG1TBCMP3 /* ADC trigger driven by timer B compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP2 SHRTIM_ADTG1SRC1_ADTG1TBCMP2 /* ADC trigger driven by timer B compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP1 SHRTIM_ADTG1SRC1_ADTG1TBCMP1 /* ADC trigger driven by timer B compare 1 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TARSTRO SHRTIM_ADTG1SRC1_ADTG1TARSTRO /* ADC trigger driven by timer A reset and roll-over events */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TAPRD SHRTIM_ADTG1SRC1_ADTG1TAPRD /* ADC trigger driven by timer A period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TACMP5 SHRTIM_ADTG1SRC1_ADTG1TACMP5 /* ADC trigger driven by timer A compare 5 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TACMP4 SHRTIM_ADTG1SRC1_ADTG1TACMP4 /* ADC trigger driven by timer A compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TACMP3 SHRTIM_ADTG1SRC1_ADTG1TACMP3 /* ADC trigger driven by timer A compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TACMP2 SHRTIM_ADTG1SRC1_ADTG1TACMP2 /* ADC trigger driven by timer A compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_TACMP1 SHRTIM_ADTG1SRC1_ADTG1TACMP1 /* ADC trigger driven by timer A compare 1 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_MPRD SHRTIM_ADTG1SRC1_ADTG1MPRD /* ADC trigger driven by master period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_MCMP4 SHRTIM_ADTG1SRC1_ADTG1MCMP4 /* ADC trigger driven by master compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_MCMP3 SHRTIM_ADTG1SRC1_ADTG1MCMP3 /* ADC trigger driven by master compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_MCMP2 SHRTIM_ADTG1SRC1_ADTG1MCMP2 /* ADC trigger driven by master compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP1_MCMP1 SHRTIM_ADTG1SRC1_ADTG1MCMP1 /* ADC trigger driven by master compare 1 event */ + +#define SHRTIM_ADTG13_SOURCE_GROUP2_EXEV5 SHRTIM_ADTG1SRC2_ADTG1EXEV5 /* ADC trigger driven by external event 5 */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_EXEV4 SHRTIM_ADTG1SRC2_ADTG1EXEV4 /* ADC trigger driven by external event 4 */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_EXEV3 SHRTIM_ADTG1SRC2_ADTG1EXEV3 /* ADC trigger driven by external event 3 */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_EXEV2 SHRTIM_ADTG1SRC2_ADTG1EXEV2 /* ADC trigger driven by external event 2 */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_EXEV1 SHRTIM_ADTG1SRC2_ADTG1EXEV1 /* ADC trigger driven by external event 1 */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFRSTRO SHRTIM_ADTG1SRC2_ADTG1TFRSTRO /* ADC trigger driven by timer F reset and roll-over events */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFPRD SHRTIM_ADTG1SRC2_ADTG1TFPRD /* ADC trigger driven by timer F period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP5 SHRTIM_ADTG1SRC2_ADTG1TFCMP5 /* ADC trigger driven by timer F compare 5 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP4 SHRTIM_ADTG1SRC2_ADTG1TFCMP4 /* ADC trigger driven by timer F compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP3 SHRTIM_ADTG1SRC2_ADTG1TFCMP3 /* ADC trigger driven by timer F compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP2 SHRTIM_ADTG1SRC2_ADTG1TFCMP2 /* ADC trigger driven by timer F compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP1 SHRTIM_ADTG1SRC2_ADTG1TFCMP1 /* ADC trigger driven by timer F compare 1 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TEPRD SHRTIM_ADTG1SRC2_ADTG1TEPRD /* ADC trigger driven by timer E period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TECMP5 SHRTIM_ADTG1SRC2_ADTG1TECMP5 /* ADC trigger driven by timer E compare 5 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TECMP4 SHRTIM_ADTG1SRC2_ADTG1TECMP4 /* ADC trigger driven by timer E compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TECMP3 SHRTIM_ADTG1SRC2_ADTG1TECMP3 /* ADC trigger driven by timer E compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TECMP2 SHRTIM_ADTG1SRC2_ADTG1TECMP2 /* ADC trigger driven by timer E compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TECMP1 SHRTIM_ADTG1SRC2_ADTG1TECMP1 /* ADC trigger driven by timer E compare 1 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TDPRD SHRTIM_ADTG1SRC2_ADTG1TDPRD /* ADC trigger driven by timer D period event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP5 SHRTIM_ADTG1SRC2_ADTG1TDCMP5 /* ADC trigger driven by timer D compare 5 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP4 SHRTIM_ADTG1SRC2_ADTG1TDCMP4 /* ADC trigger driven by timer D compare 4 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP3 SHRTIM_ADTG1SRC2_ADTG1TDCMP3 /* ADC trigger driven by timer D compare 3 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP2 SHRTIM_ADTG1SRC2_ADTG1TDCMP2 /* ADC trigger driven by timer D compare 2 event */ +#define SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP1 SHRTIM_ADTG1SRC2_ADTG1TDCMP1 /* ADC trigger driven by timer D compare 1 event */ + +/** defining the events triggering ADC conversion for ADC Triggers 2 and 4. **/ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCRSTRO SHRTIM_ADTG2SRC1_ADTG2TCRSTRO /* ADC trigger driven by timer C reset and roll-over events */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCPRD SHRTIM_ADTG2SRC1_ADTG2TCPRD /* ADC trigger driven by timer C period event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP5 SHRTIM_ADTG2SRC1_ADTG2TCCMP5 /* ADC trigger driven by timer C compare 5 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP4 SHRTIM_ADTG2SRC1_ADTG2TCCMP4 /* ADC trigger driven by timer C compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP3 SHRTIM_ADTG2SRC1_ADTG2TCCMP3 /* ADC trigger driven by timer C compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP2 SHRTIM_ADTG2SRC1_ADTG2TCCMP2 /* ADC trigger driven by timer C compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP1 SHRTIM_ADTG2SRC1_ADTG2TCCMP1 /* ADC trigger driven by timer C compare 1 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TBPRD SHRTIM_ADTG2SRC1_ADTG2TBPRD /* ADC trigger driven by timer B period event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP5 SHRTIM_ADTG2SRC1_ADTG2TBCMP5 /* ADC trigger driven by timer B compare 5 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP4 SHRTIM_ADTG2SRC1_ADTG2TBCMP4 /* ADC trigger driven by timer B compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP3 SHRTIM_ADTG2SRC1_ADTG2TBCMP3 /* ADC trigger driven by timer B compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP2 SHRTIM_ADTG2SRC1_ADTG2TBCMP2 /* ADC trigger driven by timer B compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP1 SHRTIM_ADTG2SRC1_ADTG2TBCMP1 /* ADC trigger driven by timer B compare 1 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TAPRD SHRTIM_ADTG2SRC1_ADTG2TAPRD /* ADC trigger driven by timer A period event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TACMP5 SHRTIM_ADTG2SRC1_ADTG2TACMP5 /* ADC trigger driven by timer A compare 5 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TACMP4 SHRTIM_ADTG2SRC1_ADTG2TACMP4 /* ADC trigger driven by timer A compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TACMP3 SHRTIM_ADTG2SRC1_ADTG2TACMP3 /* ADC trigger driven by timer A compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TACMP2 SHRTIM_ADTG2SRC1_ADTG2TACMP2 /* ADC trigger driven by timer A compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_TACMP1 SHRTIM_ADTG2SRC1_ADTG2TACMP1 /* ADC trigger driven by timer A compare 1 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_MPRD SHRTIM_ADTG2SRC1_ADTG2MPRD /* ADC trigger driven by master period event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_MCMP4 SHRTIM_ADTG2SRC1_ADTG2MCMP4 /* ADC trigger driven by master compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_MCMP3 SHRTIM_ADTG2SRC1_ADTG2MCMP3 /* ADC trigger driven by master compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_MCMP2 SHRTIM_ADTG2SRC1_ADTG2MCMP2 /* ADC trigger driven by master compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP1_MCMP1 SHRTIM_ADTG2SRC1_ADTG2MCMP1 /* ADC trigger driven by master compare 1 event */ + +#define SHRTIM_ADTG24_SOURCE_GROUP2_EXEV10 SHRTIM_ADTG2SRC2_ADTG2EXEV10 /* ADC trigger driven by external event 10 */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_EXEV9 SHRTIM_ADTG2SRC2_ADTG2EXEV9 /* ADC trigger driven by external event 9 */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_EXEV8 SHRTIM_ADTG2SRC2_ADTG2EXEV8 /* ADC trigger driven by external event 8 */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_EXEV7 SHRTIM_ADTG2SRC2_ADTG2EXEV7 /* ADC trigger driven by external event 7 */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_EXEV6 SHRTIM_ADTG2SRC2_ADTG2EXEV6 /* ADC trigger driven by external event 6 */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TFPRD SHRTIM_ADTG2SRC2_ADTG2TFPRD /* ADC trigger driven by timer F period event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP5 SHRTIM_ADTG2SRC2_ADTG2TFCMP5 /* ADC trigger driven by timer F compare 5 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP4 SHRTIM_ADTG2SRC2_ADTG2TFCMP4 /* ADC trigger driven by timer F compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP3 SHRTIM_ADTG2SRC2_ADTG2TFCMP3 /* ADC trigger driven by timer F compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP2 SHRTIM_ADTG2SRC2_ADTG2TFCMP2 /* ADC trigger driven by timer F compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP1 SHRTIM_ADTG2SRC2_ADTG2TFCMP1 /* ADC trigger driven by timer F compare 1 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TERSTRO SHRTIM_ADTG2SRC2_ADTG2TERSTRO /* ADC trigger driven by timer E reset and roll-over events */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TECMP5 SHRTIM_ADTG2SRC2_ADTG2TECMP5 /* ADC trigger driven by timer E compare 5 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TECMP4 SHRTIM_ADTG2SRC2_ADTG2TECMP4 /* ADC trigger driven by timer E compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TECMP3 SHRTIM_ADTG2SRC2_ADTG2TECMP3 /* ADC trigger driven by timer E compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TECMP2 SHRTIM_ADTG2SRC2_ADTG2TECMP2 /* ADC trigger driven by timer E compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TECMP1 SHRTIM_ADTG2SRC2_ADTG2TECMP1 /* ADC trigger driven by timer E compare 1 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDRSTRO SHRTIM_ADTG2SRC2_ADTG2TDRSTRO /* ADC trigger driven by timer D reset and roll-over events */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDPRD SHRTIM_ADTG2SRC2_ADTG2TDPRD /* ADC trigger driven by timer D period event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP5 SHRTIM_ADTG2SRC2_ADTG2TDCMP5 /* ADC trigger driven by timer D compare 5 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP4 SHRTIM_ADTG2SRC2_ADTG2TDCMP4 /* ADC trigger driven by timer D compare 4 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP3 SHRTIM_ADTG2SRC2_ADTG2TDCMP3 /* ADC trigger driven by timer D compare 3 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP2 SHRTIM_ADTG2SRC2_ADTG2TDCMP2 /* ADC trigger driven by timer D compare 2 event */ +#define SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP1 SHRTIM_ADTG2SRC2_ADTG2TDCMP1 /* ADC trigger driven by timer D compare 1 event */ + +/** defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9 **/ +#define SHRTIM_ADTG579_MCMP1 (uint32_t)0x00 /* Trigger on master compare 1 */ +#define SHRTIM_ADTG579_MCMP2 (uint32_t)0x01 /* Trigger on master compare 2 */ +#define SHRTIM_ADTG579_MCMP3 (uint32_t)0x02 /* Trigger on master compare 3 */ +#define SHRTIM_ADTG579_MCMP4 (uint32_t)0x03 /* Trigger on master compare 4 */ +#define SHRTIM_ADTG579_MPRD (uint32_t)0x04 /* Trigger on master period */ +#define SHRTIM_ADTG579_EXEV1 (uint32_t)0x05 /* Trigger on external event 1 */ +#define SHRTIM_ADTG579_EXEV2 (uint32_t)0x06 /* Trigger on external event 2 */ +#define SHRTIM_ADTG579_EXEV3 (uint32_t)0x07 /* Trigger on external event 3 */ +#define SHRTIM_ADTG579_EXEV4 (uint32_t)0x08 /* Trigger on external event 4 */ +#define SHRTIM_ADTG579_EXEV5 (uint32_t)0x09 /* Trigger on external event 5 */ +#define SHRTIM_ADTG579_TACMP1 (uint32_t)0x0A /* Trigger on timer A compare 1 */ +#define SHRTIM_ADTG579_TACMP2 (uint32_t)0x0B /* Trigger on timer A compare 2 */ +#define SHRTIM_ADTG579_TACMP3 (uint32_t)0x0C /* Trigger on timer A compare 3 */ +#define SHRTIM_ADTG579_TACMP4 (uint32_t)0x0D /* Trigger on timer A compare 4 */ +#define SHRTIM_ADTG579_TACMP5 (uint32_t)0x0E /* Trigger on timer A compare 5 */ +#define SHRTIM_ADTG579_TAPRD (uint32_t)0x0F /* Trigger on timer A period */ +#define SHRTIM_ADTG579_TARSTRO (uint32_t)0x10 /* Trigger on timer A reset and counter roll-over */ +#define SHRTIM_ADTG579_TBCMP1 (uint32_t)0x11 /* Trigger on timer B compare 1 */ +#define SHRTIM_ADTG579_TBCMP2 (uint32_t)0x12 /* Trigger on timer B compare 2 */ +#define SHRTIM_ADTG579_TBCMP3 (uint32_t)0x13 /* Trigger on timer B compare 3 */ +#define SHRTIM_ADTG579_TBCMP4 (uint32_t)0x14 /* Trigger on timer B compare 4 */ +#define SHRTIM_ADTG579_TBCMP5 (uint32_t)0x15 /* Trigger on timer B compare 5 */ +#define SHRTIM_ADTG579_TBPRD (uint32_t)0x16 /* Trigger on timer B period */ +#define SHRTIM_ADTG579_TBRSTRO (uint32_t)0x17 /* Trigger on timer B reset and counter roll-over */ +#define SHRTIM_ADTG579_TCCMP1 (uint32_t)0x18 /* Trigger on timer C compare 1 */ +#define SHRTIM_ADTG579_TCCMP2 (uint32_t)0x19 /* Trigger on timer C compare 2 */ +#define SHRTIM_ADTG579_TCCMP3 (uint32_t)0x1A /* Trigger on timer C compare 3 */ +#define SHRTIM_ADTG579_TCCMP4 (uint32_t)0x1B /* Trigger on timer C compare 4 */ +#define SHRTIM_ADTG579_TCCMP5 (uint32_t)0x1C /* Trigger on timer C compare 5 */ +#define SHRTIM_ADTG579_TCPRD (uint32_t)0x1D /* Trigger on timer C period */ +#define SHRTIM_ADTG579_TDCMP1 (uint32_t)0x1E /* Trigger on timer D compare 1 */ +#define SHRTIM_ADTG579_TDCMP2 (uint32_t)0x1F /* Trigger on timer D compare 2 */ +#define SHRTIM_ADTG579_TDCMP3 (uint32_t)0x20 /* Trigger on timer D compare 3 */ +#define SHRTIM_ADTG579_TDCMP4 (uint32_t)0x21 /* Trigger on timer D compare 4 */ +#define SHRTIM_ADTG579_TDCMP5 (uint32_t)0x22 /* Trigger on timer D compare 5 */ +#define SHRTIM_ADTG579_TDPRD (uint32_t)0x23 /* Trigger on timer D period */ +#define SHRTIM_ADTG579_TECMP1 (uint32_t)0x24 /* Trigger on timer E compare 1 */ +#define SHRTIM_ADTG579_TECMP2 (uint32_t)0x25 /* Trigger on timer E compare 2 */ +#define SHRTIM_ADTG579_TECMP3 (uint32_t)0x26 /* Trigger on timer E compare 3 */ +#define SHRTIM_ADTG579_TECMP4 (uint32_t)0x27 /* Trigger on timer E compare 4 */ +#define SHRTIM_ADTG579_TECMP5 (uint32_t)0x28 /* Trigger on timer E compare 5 */ +#define SHRTIM_ADTG579_TEPRD (uint32_t)0x29 /* Trigger on timer E period */ +#define SHRTIM_ADTG579_TFCMP1 (uint32_t)0x2A /* Trigger on timer F compare 1 */ +#define SHRTIM_ADTG579_TFCMP2 (uint32_t)0x2B /* Trigger on timer F compare 2 */ +#define SHRTIM_ADTG579_TFCMP3 (uint32_t)0x2C /* Trigger on timer F compare 3 */ +#define SHRTIM_ADTG579_TFCMP4 (uint32_t)0x2D /* Trigger on timer F compare 4 */ +#define SHRTIM_ADTG579_TFCMP5 (uint32_t)0x2E /* Trigger on timer F compare 5 */ +#define SHRTIM_ADTG579_TFPRD (uint32_t)0x2F /* Trigger on timer F period */ +#define SHRTIM_ADTG579_TFRSTRO (uint32_t)0x30 /* Trigger on timer F reset and counter roll-over */ + +/** defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10 **/ +#define SHRTIM_ADTG6810_MCMP1 (uint32_t)0x00 /* ADC extended trigger on master compare 1 */ +#define SHRTIM_ADTG6810_MCMP2 (uint32_t)0x01 /* ADC extended trigger on master compare 2 */ +#define SHRTIM_ADTG6810_MCMP3 (uint32_t)0x02 /* ADC extended trigger on master compare 3 */ +#define SHRTIM_ADTG6810_MCMP4 (uint32_t)0x03 /* ADC extended trigger on master compare 4 */ +#define SHRTIM_ADTG6810_MPRD (uint32_t)0x04 /* ADC extended trigger on master period */ +#define SHRTIM_ADTG6810_EXEV6 (uint32_t)0x05 /* ADC extended trigger on external event 6 */ +#define SHRTIM_ADTG6810_EXEV7 (uint32_t)0x06 /* ADC extended trigger on external event 7 */ +#define SHRTIM_ADTG6810_EXEV8 (uint32_t)0x07 /* ADC extended trigger on external event 8 */ +#define SHRTIM_ADTG6810_EXEV9 (uint32_t)0x08 /* ADC extended trigger on external event 9 */ +#define SHRTIM_ADTG6810_EXEV10 (uint32_t)0x09 /* ADC extended trigger on external event 10 */ +#define SHRTIM_ADTG6810_TACMP1 (uint32_t)0x0A /* ADC extended trigger on timer A compare 1 */ +#define SHRTIM_ADTG6810_TACMP2 (uint32_t)0x0B /* ADC extended trigger on timer A compare 2 */ +#define SHRTIM_ADTG6810_TACMP3 (uint32_t)0x0C /* ADC extended trigger on timer A compare 3 */ +#define SHRTIM_ADTG6810_TACMP4 (uint32_t)0x0D /* ADC extended trigger on timer A compare 4 */ +#define SHRTIM_ADTG6810_TACMP5 (uint32_t)0x0E /* ADC extended trigger on timer A compare 5 */ +#define SHRTIM_ADTG6810_TAPRD (uint32_t)0x0F /* ADC extended trigger on timer A period */ +#define SHRTIM_ADTG6810_TBCMP1 (uint32_t)0x10 /* ADC extended trigger on timer B compare 1 */ +#define SHRTIM_ADTG6810_TBCMP2 (uint32_t)0x11 /* ADC extended trigger on timer B compare 2 */ +#define SHRTIM_ADTG6810_TBCMP3 (uint32_t)0x12 /* ADC extended trigger on timer B compare 3 */ +#define SHRTIM_ADTG6810_TBCMP4 (uint32_t)0x13 /* ADC extended trigger on timer B compare 4 */ +#define SHRTIM_ADTG6810_TBCMP5 (uint32_t)0x14 /* ADC extended trigger on timer B compare 5 */ +#define SHRTIM_ADTG6810_TBPRD (uint32_t)0x15 /* ADC extended trigger on timer B period */ +#define SHRTIM_ADTG6810_TCCMP1 (uint32_t)0x16 /* ADC extended trigger on timer C compare 1 */ +#define SHRTIM_ADTG6810_TCCMP2 (uint32_t)0x17 /* ADC extended trigger on timer C compare 2 */ +#define SHRTIM_ADTG6810_TCCMP3 (uint32_t)0x18 /* ADC extended trigger on timer C compare 3 */ +#define SHRTIM_ADTG6810_TCCMP4 (uint32_t)0x19 /* ADC extended trigger on timer C compare 4 */ +#define SHRTIM_ADTG6810_TCCMP5 (uint32_t)0x1A /* ADC extended trigger on timer C compare 5 */ +#define SHRTIM_ADTG6810_TCPRD (uint32_t)0x1B /* ADC extended trigger on timer C period */ +#define SHRTIM_ADTG6810_TCRSTRO (uint32_t)0x1C /* ADC extended trigger on timer C reset and counter roll-over */ +#define SHRTIM_ADTG6810_TDCMP1 (uint32_t)0x1D /* ADC extended trigger on timer D compare 1 */ +#define SHRTIM_ADTG6810_TDCMP2 (uint32_t)0x1E /* ADC extended trigger on timer D compare 2 */ +#define SHRTIM_ADTG6810_TDCMP3 (uint32_t)0x1F /* ADC extended trigger on timer D compare 3 */ +#define SHRTIM_ADTG6810_TDCMP4 (uint32_t)0x20 /* ADC extended trigger on timer D compare 4 */ +#define SHRTIM_ADTG6810_TDCMP5 (uint32_t)0x21 /* ADC extended trigger on timer D compare 5 */ +#define SHRTIM_ADTG6810_TDPRD (uint32_t)0x22 /* ADC extended trigger on timer D period */ +#define SHRTIM_ADTG6810_TDRSTRO (uint32_t)0x23 /* ADC extended trigger on timer D reset and counter roll-over */ +#define SHRTIM_ADTG6810_TECMP1 (uint32_t)0x24 /* ADC extended trigger on timer E compare 1 */ +#define SHRTIM_ADTG6810_TECMP2 (uint32_t)0x25 /* ADC extended trigger on timer E compare 2 */ +#define SHRTIM_ADTG6810_TECMP3 (uint32_t)0x26 /* ADC extended trigger on timer E compare 3 */ +#define SHRTIM_ADTG6810_TECMP4 (uint32_t)0x27 /* ADC extended trigger on timer E compare 4 */ +#define SHRTIM_ADTG6810_TECMP5 (uint32_t)0x28 /* ADC extended trigger on timer E compare 5 */ +#define SHRTIM_ADTG6810_TERSTRO (uint32_t)0x29 /* ADC extended trigger on timer E reset and counter roll-over */ +#define SHRTIM_ADTG6810_TFCMP1 (uint32_t)0x2A /* ADC extended trigger on timer F compare 1 */ +#define SHRTIM_ADTG6810_TFCMP2 (uint32_t)0x2B /* ADC extended trigger on timer F compare 2 */ +#define SHRTIM_ADTG6810_TFCMP3 (uint32_t)0x2C /* ADC extended trigger on timer F compare 3 */ +#define SHRTIM_ADTG6810_TFCMP4 (uint32_t)0x2D /* ADC extended trigger on timer F compare 4 */ +#define SHRTIM_ADTG6810_TFCMP5 (uint32_t)0x2E /* ADC extended trigger on timer F compare 5 */ +#define SHRTIM_ADTG6810_TFPRD (uint32_t)0x2F /* ADC extended trigger on timer F period */ + +/** Defining timer high-resolution clock prescaler ratio. **/ +#define SHRTIM_PRESCALERRATIO_MUL32 0x00000000U /* fHRCK: fSHRTIM x 32 = 8 GHz - Resolution: 125 ps - Min PWM frequency: 122.1 kHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /* fHRCK: fSHRTIM x 16 = 4 GHz - Resolution: 250 ps - Min PWM frequency: 61.0 KHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /* fHRCK: fSHRTIM x 8 = 2 GHz - Resolution: 500 ps - Min PWM frequency: 30.5 kHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /* fHRCK: fSHRTIM x 4 = 1 GHz - Resolution: 1 ns - Min PWM frequency: 15.3 kHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /* fHRCK: fSHRTIM x 2 = 500 MHz - Resolution: 2 ns - Min PWM frequency: 7.63 kHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /* fHRCK: fSHRTIM = 250 MHz - Resolution: 4 ns - Min PWM frequency: 3.81 kHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /* fHRCK: fSHRTIM / 2 = 125 MHz - Resolution: 8 ns- Min PWM frequency: 1.91 kHz (fSHRTIM=250MHz) */ +#define SHRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /* fHRCK: fSHRTIM / 4 = 62.5 MHz - Resolution: 16 ns- Min PWM frequency: 0.95 Hz (fSHRTIM=250MHz) */ + +/** Defining timer counter operating mode. **/ +#define SHRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /* The timer operates in continuous (free-running) mode */ +#define SHRTIM_MODE_SINGLESHOT 0x00000000U /* The timer operates in non retriggerable single-shot mode */ +#define SHRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /* The timer operates in retriggerable single-shot mode */ + + +/** Defining on which output the DAC synchronization event is sent. **/ +#define SHRTIM_DACTRIG_NONE 0x00000000U /* No DAC synchronization event generated */ +#define SHRTIM_DACTRIG_DACTRIGOUT_1 (SHRTIM_MCTRL_DACTRIG_0) /* DAC synchronization event generated on DACTrigOut1 output upon timer update */ +#define SHRTIM_DACTRIG_DACTRIGOUT_2 (SHRTIM_MCTRL_DACTRIG_1) /* DAC synchronization event generated on DACTrigOut2 output upon timer update */ +#define SHRTIM_DACTRIG_DACTRIGOUT_3 (SHRTIM_MCTRL_DACTRIG_1 | SHRTIM_MCTRL_DACTRIG_0) /* DAC synchronization event generated on DACTrigOut3 output upon timer update */ + + +/** Defining whether the registers update is done synchronously with any other timer or master update. **/ +#define SHRTIM_UPDATETRIG_NONE 0x00000000U /* Register update is disabled */ +#define SHRTIM_UPDATETRIG_MASTER SHRTIM_TXCTRL_MUEN /* Register update is triggered by the master timer update */ +#define SHRTIM_UPDATETRIG_TIMER_A SHRTIM_TXCTRL_TAUEN /* Register update is triggered by the timer A update */ +#define SHRTIM_UPDATETRIG_TIMER_B SHRTIM_TXCTRL_TBUEN /* Register update is triggered by the timer B update */ +#define SHRTIM_UPDATETRIG_TIMER_C SHRTIM_TXCTRL_TCUEN /* Register update is triggered by the timer C update*/ +#define SHRTIM_UPDATETRIG_TIMER_D SHRTIM_TXCTRL_TDUEN /* Register update is triggered by the timer D update */ +#define SHRTIM_UPDATETRIG_TIMER_E SHRTIM_TXCTRL_TEUEN /* Register update is triggered by the timer E update */ +#define SHRTIM_UPDATETRIG_TIMER_F SHRTIM_TXCTRL_TFUEN /* Register update is triggered by the timer F update */ +#define SHRTIM_UPDATETRIG_REPETITION SHRTIM_TXCTRL_REPTUEN /* Register update is triggered when the counter rolls over and SHRTIM_TxREPT = 0*/ +#define SHRTIM_UPDATETRIG_RESET SHRTIM_TXCTRL_RSTROUEN /* Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */ + +/** Defining how the update occurs relatively to the burst DMA transaction and the + external update request on update enable inputs 1 to 3. **/ +#define SHRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /* Update done independently from the DMA burst transfer completion */ +#define SHRTIM_UPDATEGATING_DMABURST (SHRTIM_TXCTRL_UPDGAT_0) /* Update done when the DMA burst transfer is completed */ +#define SHRTIM_UPDATEGATING_DMABURST_UPDATE (SHRTIM_TXCTRL_UPDGAT_1) /* Update done on timer roll-over following a DMA burst transfer completion*/ +#define SHRTIM_UPDATEGATING_UPDEN1 (SHRTIM_TXCTRL_UPDGAT_1 | SHRTIM_TXCTRL_UPDGAT_0) /* Slave timer only - Update done on a rising edge of SHRTIM update enable input 1 */ +#define SHRTIM_UPDATEGATING_UPDEN2 (SHRTIM_TXCTRL_UPDGAT_2) /* Slave timer only - Update done on a rising edge of SHRTIM update enable input 2 */ +#define SHRTIM_UPDATEGATING_UPDEN3 (SHRTIM_TXCTRL_UPDGAT_2 | SHRTIM_TXCTRL_UPDGAT_0) /* Slave timer only - Update done on a rising edge of SHRTIM update enable input 3 */ +#define SHRTIM_UPDATEGATING_UPDEN1_UPDATE (SHRTIM_TXCTRL_UPDGAT_2 | SHRTIM_TXCTRL_UPDGAT_1) /* Slave timer only - Update done on the update event following a rising edge of SHRTIM update enable input 1 */ +#define SHRTIM_UPDATEGATING_UPDEN2_UPDATE (SHRTIM_TXCTRL_UPDGAT_2 | SHRTIM_TXCTRL_UPDGAT_1 | SHRTIM_TXCTRL_UPDGAT_0) /* Slave timer only - Update done on the update event following a rising edge of SHRTIM update enable input 2 */ +#define SHRTIM_UPDATEGATING_UPDEN3_UPDATE (SHRTIM_TXCTRL_UPDGAT_3) /* Slave timer only - Update done on the update event following a rising edge of SHRTIM update enable input 3 */ + + +/** Defining whether the compare register is behaving in regular mode + (compare match issued as soon as counter equal compare) or in auto-delayed mode. **/ +#define SHRTIM_COMPAREMODE_REGULAR 0x00000000U /* standard compare mode */ +#define SHRTIM_COMPAREMODE_DELAY_NOTIMEOUT (SHRTIM_TXCTRL_DELCMP2M_0) /* Compare event generated only if a capture has occurred */ +#define SHRTIM_COMPAREMODE_DELAY_CMP1 (SHRTIM_TXCTRL_DELCMP2M_1) /* Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ +#define SHRTIM_COMPAREMODE_DELAY_CMP3 (SHRTIM_TXCTRL_DELCMP2M_1 | SHRTIM_TXCTRL_DELCMP2M_0) /* Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ + +/** Defining the events that can be selected to trigger the reset of the timer counter. **/ +#define SHRTIM_RESETTRIG_NONE 0x00000000U /* No counter reset trigger */ +#define SHRTIM_RESETTRIG_UPDATE SHRTIM_TACNTRST_UPD /* The timer counter is reset upon update event */ +#define SHRTIM_RESETTRIG_CMP2 SHRTIM_TACNTRST_CMP2 /* The timer counter is reset upon Timer Compare 2 event */ +#define SHRTIM_RESETTRIG_CMP4 SHRTIM_TACNTRST_CMP4 /* The timer counter is reset upon Timer Compare 4 event */ +#define SHRTIM_RESETTRIG_MASTER_PER SHRTIM_TACNTRST_MPRD /* The timer counter is reset upon master timer period event */ +#define SHRTIM_RESETTRIG_MASTER_CMP1 SHRTIM_TACNTRST_MCMP1 /* The timer counter is reset upon master timer Compare 1 event */ +#define SHRTIM_RESETTRIG_MASTER_CMP2 SHRTIM_TACNTRST_MCMP2 /* The timer counter is reset upon master timer Compare 2 event */ +#define SHRTIM_RESETTRIG_MASTER_CMP3 SHRTIM_TACNTRST_MCMP3 /* The timer counter is reset upon master timer Compare 3 event */ +#define SHRTIM_RESETTRIG_MASTER_CMP4 SHRTIM_TACNTRST_MCMP4 /* The timer counter is reset upon master timer Compare 4 event */ +#define SHRTIM_RESETTRIG_EXEV_1 SHRTIM_TACNTRST_EXEV1 /* The timer counter is reset upon external event 1 */ +#define SHRTIM_RESETTRIG_EXEV_2 SHRTIM_TACNTRST_EXEV2 /* The timer counter is reset upon external event 2 */ +#define SHRTIM_RESETTRIG_EXEV_3 SHRTIM_TACNTRST_EXEV3 /* The timer counter is reset upon external event 3 */ +#define SHRTIM_RESETTRIG_EXEV_4 SHRTIM_TACNTRST_EXEV4 /* The timer counter is reset upon external event 4 */ +#define SHRTIM_RESETTRIG_EXEV_5 SHRTIM_TACNTRST_EXEV5 /* The timer counter is reset upon external event 5 */ +#define SHRTIM_RESETTRIG_EXEV_6 SHRTIM_TACNTRST_EXEV6 /* The timer counter is reset upon external event 6 */ +#define SHRTIM_RESETTRIG_EXEV_7 SHRTIM_TACNTRST_EXEV7 /* The timer counter is reset upon external event 7 */ +#define SHRTIM_RESETTRIG_EXEV_8 SHRTIM_TACNTRST_EXEV8 /* The timer counter is reset upon external event 8 */ +#define SHRTIM_RESETTRIG_EXEV_9 SHRTIM_TACNTRST_EXEV9 /* The timer counter is reset upon external event 9 */ +#define SHRTIM_RESETTRIG_EXEV_10 SHRTIM_TACNTRST_EXEV10 /* The timer counter is reset upon external event 10 */ +#define SHRTIM_RESETTRIG_OTHER1_CMP1 SHRTIM_TACNTRST_TBCMP1 /* The timer counter is reset upon other timer Compare 1 event */ +#define SHRTIM_RESETTRIG_OTHER1_CMP2 SHRTIM_TACNTRST_TBCMP2 /* The timer counter is reset upon other timer Compare 2 event */ +#define SHRTIM_RESETTRIG_OTHER1_CMP4 SHRTIM_TACNTRST_TBCMP4 /* The timer counter is reset upon other timer Compare 4 event */ +#define SHRTIM_RESETTRIG_OTHER2_CMP1 SHRTIM_TACNTRST_TCCMP1 /* The timer counter is reset upon other timer Compare 1 event */ +#define SHRTIM_RESETTRIG_OTHER2_CMP2 SHRTIM_TACNTRST_TCCMP2 /* The timer counter is reset upon other timer Compare 2 event */ +#define SHRTIM_RESETTRIG_OTHER2_CMP4 SHRTIM_TACNTRST_TCCMP4 /* The timer counter is reset upon other timer Compare 4 event */ +#define SHRTIM_RESETTRIG_OTHER3_CMP1 SHRTIM_TACNTRST_TDCMP1 /* The timer counter is reset upon other timer Compare 1 event */ +#define SHRTIM_RESETTRIG_OTHER3_CMP2 SHRTIM_TACNTRST_TDCMP2 /* The timer counter is reset upon other timer Compare 2 event */ +#define SHRTIM_RESETTRIG_OTHER3_CMP4 SHRTIM_TACNTRST_TDCMP4 /* The timer counter is reset upon other timer Compare 4 event */ +#define SHRTIM_RESETTRIG_OTHER4_CMP1 SHRTIM_TACNTRST_TECMP1 /* The timer counter is reset upon other timer Compare 1 event */ +#define SHRTIM_RESETTRIG_OTHER4_CMP2 SHRTIM_TACNTRST_TECMP2 /* The timer counter is reset upon other timer Compare 2 event */ +#define SHRTIM_RESETTRIG_OTHER4_CMP4 SHRTIM_TACNTRST_TECMP4 /* The timer counter is reset upon other timer Compare 4 event */ +#define SHRTIM_RESETTRIG_OTHER5_CMP1 SHRTIM_TACNTRST_TFCMP1 /* The timer counter is reset upon other timer Compare 1 event */ +#define SHRTIM_RESETTRIG_OTHER5_CMP2 SHRTIM_TACNTRST_TFCMP2 /* The timer counter is reset upon other timer Compare 2 event */ + +/** Defining the events that can be selected to trigger the capture of the timing unit counter. **/ +#define SHRTIM_CAPTURETRIG_NONE (uint64_t)0 /* Capture trigger is disabled */ +#define SHRTIM_CAPTURETRIG_SW (uint64_t)SHRTIM_TACPT1CTRL_SW /* The sw event triggers the Capture */ +#define SHRTIM_CAPTURETRIG_UPDATE (uint64_t)SHRTIM_TACPT1CTRL_UPD /* The update event triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_1 (uint64_t)SHRTIM_TACPT1CTRL_EXEV1 /* The External event 1 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_2 (uint64_t)SHRTIM_TACPT1CTRL_EXEV2 /* The External event 2 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_3 (uint64_t)SHRTIM_TACPT1CTRL_EXEV3 /* The External event 3 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_4 (uint64_t)SHRTIM_TACPT1CTRL_EXEV4 /* The External event 4 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_5 (uint64_t)SHRTIM_TACPT1CTRL_EXEV5 /* The External event 5 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_6 (uint64_t)SHRTIM_TACPT1CTRL_EXEV6 /* The External event 6 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_7 (uint64_t)SHRTIM_TACPT1CTRL_EXEV7 /* The External event 7 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_8 (uint64_t)SHRTIM_TACPT1CTRL_EXEV8 /* The External event 8 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_9 (uint64_t)SHRTIM_TACPT1CTRL_EXEV9 /* The External event 9 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_EXEV_10 (uint64_t)SHRTIM_TACPT1CTRL_EXEV10 /* The External event 10 triggers the Capture */ +#define SHRTIM_CAPTURETRIG_TA1_SET (uint64_t)(12U) <<32 /* Capture is triggered by TA1 output inactive to active transition */ +#define SHRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(13U) <<32 /* Capture is triggered by TA1 output active to inactive transition */ +#define SHRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(14U) <<32 /* Timer A Compare 1 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(15U) <<32 /* Timer A Compare 2 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TB1_SET (uint64_t)(16U) <<32 /* Capture is triggered by TB1 output inactive to active transition */ +#define SHRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(17U) <<32 /* Capture is triggered by TB1 output active to inactive transition */ +#define SHRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(18U) <<32 /* Timer B Compare 1 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(19U) <<32 /* Timer B Compare 2 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TC1_SET (uint64_t)(20U) <<32 /* Capture is triggered by TC1 output inactive to active transition */ +#define SHRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(21U) <<32 /* Capture is triggered by TC1 output active to inactive transition */ +#define SHRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(22U) <<32 /* Timer C Compare 1 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(23U) <<32 /* Timer C Compare 2 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TD1_SET (uint64_t)(24U) <<32 /* Capture is triggered by TD1 output inactive to active transition */ +#define SHRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(25U) <<32 /* Capture is triggered by TD1 output active to inactive transition */ +#define SHRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(26U) <<32 /* Timer D Compare 1 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(27U) <<32 /* Timer D Compare 2 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TE1_SET (uint64_t)(28U) <<32 /* Capture is triggered by TE1 output inactive to active transition */ +#define SHRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(29U) <<32 /* Capture is triggered by TE1 output active to inactive transition */ +#define SHRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(30U) <<32 /* Timer E Compare 1 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(31U) <<32 /* Timer E Compare 2 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TF1_SET (uint64_t)(0U) <<32 /* Capture is triggered by TF1 output inactive to active transition */ +#define SHRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(1U) <<32 /* Capture is triggered by TF1 output active to inactive transition */ +#define SHRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(2U) <<32 /* Timer F Compare 1 triggers Capture */ +#define SHRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(3U) <<32 /* Timer F Compare 2 triggers Capture */ + + +/** Defining all possible delayed protection modes for a timer + (also define the source and outputs on which the delayed protection schemes are applied). **/ +#define SHRTIM_DP_DELAYOUT1_EXEV6 0x00000000U /* Timers A, B, C: Output 1 delayed Idle on external Event 6 */ +#define SHRTIM_DP_DELAYOUT2_EXEV6 (SHRTIM_TXOUT_DP_0) /* Timers A, B, C: Output 2 delayed Idle on external Event 6 */ +#define SHRTIM_DP_DELAYBOTH_EXEV6 (SHRTIM_TXOUT_DP_1) /* Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */ +#define SHRTIM_DP_BALANCED_EXEV6 (SHRTIM_TXOUT_DP_1 | SHRTIM_TXOUT_DP_0) /* Timers A, B, C: Balanced Idle on external Event 6 */ +#define SHRTIM_DP_DELAYOUT1_EXEV7 (SHRTIM_TXOUT_DP_2) /* Timers A, B, C: Output 1 delayed Idle on external Event 7 */ +#define SHRTIM_DP_DELAYOUT2_EXEV7 (SHRTIM_TXOUT_DP_2 | SHRTIM_TXOUT_DP_0) /* Timers A, B, C: Output 2 delayed Idle on external Event 7 */ +#define SHRTIM_DP_DELAYBOTH_EXEV7 (SHRTIM_TXOUT_DP_2 | SHRTIM_TXOUT_DP_1) /* Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */ +#define SHRTIM_DP_BALANCED_EXEV7 (SHRTIM_TXOUT_DP_2 | SHRTIM_TXOUT_DP_1 | SHRTIM_TXOUT_DP_0) /* Timers A, B, C: Balanced Idle on external Event 7 */ + +#define SHRTIM_DP_DELAYOUT1_EXEV8 0x00000000U /* Timers D, E: Output 1 delayed Idle on external Event 8 */ +#define SHRTIM_DP_DELAYOUT2_EXEV8 (SHRTIM_TXOUT_DP_0) /* Timers D, E: Output 2 delayed Idle on external Event 8 */ +#define SHRTIM_DP_DELAYBOTH_EXEV8 (SHRTIM_TXOUT_DP_1) /* Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */ +#define SHRTIM_DP_BALANCED_EXEV8 (SHRTIM_TXOUT_DP_1 | SHRTIM_TXOUT_DP_0) /* Timers D, E: Balanced Idle on external Event 8 */ +#define SHRTIM_DP_DELAYOUT1_EXEV9 (SHRTIM_TXOUT_DP_2) /* Timers D, E: Output 1 delayed Idle on external Event 9 */ +#define SHRTIM_DP_DELAYOUT2_EXEV9 (SHRTIM_TXOUT_DP_2 | SHRTIM_TXOUT_DP_0) /* Timers D, E: Output 2 delayed Idle on external Event 9 */ +#define SHRTIM_DP_DELAYBOTH_EXEV9 (SHRTIM_TXOUT_DP_2 | SHRTIM_TXOUT_DP_1) /* Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */ +#define SHRTIM_DP_BALANCED_EXEV9 (SHRTIM_TXOUT_DP_2 | SHRTIM_TXOUT_DP_1 | SHRTIM_TXOUT_DP_0) /* Timers D, E: Balanced Idle on external Event 9 */ + +/** Identifying an software delay protection. **/ +#define SHRTIM_SOFT_DP_TA1 (SHRTIM_SFTDP_SFTDPA1) /* Timer A - channel 1 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TA2 (SHRTIM_SFTDP_SFTDPA2) /* Timer A - channel 2 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TB1 (SHRTIM_SFTDP_SFTDPB1) /* Timer B - channel 1 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TB2 (SHRTIM_SFTDP_SFTDPB2) /* Timer B - channel 2 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TC1 (SHRTIM_SFTDP_SFTDPC1) /* Timer C - channel 1 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TC2 (SHRTIM_SFTDP_SFTDPC2) /* Timer C - channel 2 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TD1 (SHRTIM_SFTDP_SFTDPD1) /* Timer D - channel 1 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TD2 (SHRTIM_SFTDP_SFTDPD2) /* Timer D - channel 2 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TE1 (SHRTIM_SFTDP_SFTDPE1) /* Timer E - channel 1 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TE2 (SHRTIM_SFTDP_SFTDPE2) /* Timer E - channel 2 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TF1 (SHRTIM_SFTDP_SFTDPF1) /* Timer F - channel 1 soft delay protection identifier */ +#define SHRTIM_SOFT_DP_TF2 (SHRTIM_SFTDP_SFTDPF2) /* Timer F - channel 2 soft delay protection identifier */ + +/** Defining how the timer behaves during a burst mode operation. **/ +#define SHRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /* Timer counter clock is maintained and the timer operates normally */ +#define SHRTIM_BURSTMODE_RESETCOUNTER (SHRTIM_BMCTRL_MBM) /* Timer counter clock is stopped and the counter is reset */ + +/** Defining the registers that can be written during a burst DMA operation. **/ +#define SHRTIM_BURSTDMA_NONE 0x00000000U /* No register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MCTRL (SHRTIM_BDMTUPD_MCTRL) /* MCTRL register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MINTCLR (SHRTIM_BDMTUPD_MINTCLR) /* MINTCLR register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MIDEN (SHRTIM_BDMTUPD_MIDEN) /* MIDEN register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MCNT (SHRTIM_BDMTUPD_MCNT) /* MCNT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MPRD (SHRTIM_BDMTUPD_MPRD) /* MPRD register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MREPT (SHRTIM_BDMTUPD_MREPT) /* MREPT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MCMPDAT1 (SHRTIM_BDMTUPD_MCMPDAT1) /* MCMPDAT1 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MCMPDAT2 (SHRTIM_BDMTUPD_MCMPDAT2) /* MCMPDAT2 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MCMPDAT3 (SHRTIM_BDMTUPD_MCMPDAT3) /* MCMPDAT3 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_MCMPDAT4 (SHRTIM_BDMTUPD_MCMPDAT4) /* MCMPDAT4 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCTRL (SHRTIM_BDTAUPD_TACTRL) /* TxCTRL register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXINTCLR (SHRTIM_BDTAUPD_TAINTCLR) /* TxINTCLR register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXIDEN (SHRTIM_BDTAUPD_TAIDEN) /* TxIDEN register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCNT (SHRTIM_BDTAUPD_TACNT) /* TxCNT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXPRD (SHRTIM_BDTAUPD_TAPRD) /* TxPRD register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXREPT (SHRTIM_BDTAUPD_TAREPT) /* TxREPT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCMP1DAT (SHRTIM_BDTAUPD_TACMP1DAT) /* TxCMP1DAT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCMP2DAT (SHRTIM_BDTAUPD_TACMP2DAT) /* TxCMP2DAT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCMP3DAT (SHRTIM_BDTAUPD_TACMP3DAT) /* TxCMP3DAT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCMP4DAT (SHRTIM_BDTAUPD_TACMP4DAT) /* TxCMP4DAT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXDT (SHRTIM_BDTAUPD_TADT) /* TxDT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXSET1 (SHRTIM_BDTAUPD_TASET1) /* TxSET1 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXRST1 (SHRTIM_BDTAUPD_TARST1) /* TxRST1 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXSET2 (SHRTIM_BDTAUPD_TASET2) /* TxSET2 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXRST2 (SHRTIM_BDTAUPD_TARST2) /* TxRST2 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXEXEVFLT1 (SHRTIM_BDTAUPD_TAEXEVFLT1) /* TxEXEVFLT1 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXEXEVFLT2 (SHRTIM_BDTAUPD_TAEXEVFLT2) /* TxEXEVFLT2 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCNTRST (SHRTIM_BDTAUPD_TACNTRST) /* TxCNTRST register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCHOP (SHRTIM_BDTAUPD_TACHOP) /* TxCHOP register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXOUT (SHRTIM_BDTAUPD_TAOUT) /* TxOUT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXFALT (SHRTIM_BDTAUPD_TAFALT) /* TxFALT register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXCTRL2 (SHRTIM_BDTAUPD_TACTRL2) /* TxCTRL2 register is updated by Burst DMA accesses */ +#define SHRTIM_BURSTDMA_TXEXEVFLT3 (SHRTIM_BDTAUPD_TAEXEVFLT3) /* TxEXEVFLT3 register is updated by Burst DMA accesses */ + + +/** Defining on which output the signal is currently applied in push-pull mode. **/ +#define SHRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /* Signal applied on output 1 and output 2 forced inactive */ +#define SHRTIM_CPPSTAT_OUTPUT2 (SHRTIM_TXINTSTS_CPPSTS) /* Signal applied on output 2 and output 1 forced inactive */ + + +/** Defining on which output the signal was applied, + in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered. **/ +#define SHRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /* Protection occurred when the output 1 was active and output 2 forced inactive */ +#define SHRTIM_IPPSTAT_OUTPUT2 (SHRTIM_TXINTSTS_IPPSTS) /* Protection occurred when the output 2 was active and output 1 forced inactive */ + +/** Defining the event filtering applied to external events by a timer. **/ +#define SHRTIM_EXEVFLT_NONE (0x00000000U) +#define SHRTIM_EXEVFLT_BLANKINGCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from counter reset/roll-over to Compare 1U */ +#define SHRTIM_EXEVFLT_BLANKINGCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from counter reset/roll-over to Compare 2U */ +#define SHRTIM_EXEVFLT_BLANKINGCMP3 (SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from counter reset/roll-over to Compare 3U */ +#define SHRTIM_EXEVFLT_BLANKINGCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from counter reset/roll-over to Compare 4U */ +/* Blanking Filter for TIMER A */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF1_TIMBCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR1 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF2_TIMBCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR2 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF3_TIMBOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR3 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF4_TIMCCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3) /* Blanking from another timing unit: TIMFLTR4 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF5_TIMCCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR5 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF6_TIMFCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR6 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF7_TIMDCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR7 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMAEEF8_TIMECMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from another timing unit: TIMFLTR8 source */ +/* Blanking Filter for TIMER B */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF1_TIMACMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR1 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF2_TIMACMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR2 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF3_TIMAOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR3 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF4_TIMCCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3) /* Blanking from another timing unit: TIMFLTR4 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF5_TIMCCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR5 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF6_TIMFCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR6 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF7_TIMDCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR7 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMBEEF8_TIMECMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from another timing unit: TIMFLTR8 source */ +/* Blanking Filter for TIMER C */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF1_TIMACMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR1 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF2_TIMBCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR2 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF3_TIMBCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR3 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF4_TIMFCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3) /* Blanking from another timing unit: TIMFLTR4 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF5_TIMDCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR5 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF6_TIMDCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR6 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF7_TIMDOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR7 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMCEEF8_TIMECMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from another timing unit: TIMFLTR8 source */ +/* Blanking Filter for TIMER D */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF1_TIMACMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR1 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF2_TIMBCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR2 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF3_TIMCCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR3 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF4_TIMCCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3) /* Blanking from another timing unit: TIMFLTR4 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF5_TIMCOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR5 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF6_TIMECMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR6 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF7_TIMECMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR7 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMDEEF8_TIMFCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from another timing unit: TIMFLTR8 source */ +/* Blanking Filter for TIMER E */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF1_TIMACMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR1 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF2_TIMBCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR2 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF3_TIMCCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR3 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF4_TIMFCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3) /* Blanking from another timing unit: TIMFLTR4 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF5_TIMFOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR5 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF6_TIMDCMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR6 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF7_TIMDCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR7 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMEEEF8_TIMDOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from another timing unit: TIMFLTR8 source */ +/* Blanking Filter for TIMER F */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF1_TIMACMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR1 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF2_TIMBCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR2 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF3_TIMCCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR3 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF4_TIMDCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3) /* Blanking from another timing unit: TIMFLTR4 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF5_TIMDCMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR5 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF6_TIMECMP1 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Blanking from another timing unit: TIMFLTR6 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF7_TIMECMP4 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Blanking from another timing unit: TIMFLTR7 source */ +#define SHRTIM_EXEVFLT_BLANKING_TIMFEEF8_TIMEOUT2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2) /* Blanking from another timing unit: TIMFLTR8 source */ + +#define SHRTIM_EXEVFLT_WINDOWINGCMP2 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Windowing from counter reset/roll-over to Compare 2U */ +#define SHRTIM_EXEVFLT_WINDOWINGCMP3 (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1) /* Windowing from counter reset/roll-over to Compare 3U */ +#define SHRTIM_EXEVFLT_WINDOWINGTIM (SHRTIM_TXEXEVFLT1_EXEV1FLT_3 | SHRTIM_TXEXEVFLT1_EXEV1FLT_2 | SHRTIM_TXEXEVFLT1_EXEV1FLT_1\ + | SHRTIM_TXEXEVFLT1_EXEV1FLT_0) /* Windowing from another timing unit: TIMWIN source */ + + +/** Defining whether or not the external event is memorized (latched) + and generated as soon as the blanking period is completed or the window ends. **/ +#define SHRTIM_EXEVLATCH_DISABLED 0x00000000U /* Event is ignored if it happens during a blank, or passed through during a window */ +#define SHRTIM_EXEVLATCH_ENABLED SHRTIM_TXEXEVFLT1_EXEV1LATCH /* Event is latched and delayed till the end of the blanking or windowing period */ + + +/** Defining division ratio between the timer clock frequency (fSHRTIM) + and the deadtime generator clock (fDTG). **/ +#define SHRTIM_DT_PRESCALER_MUL8 0x00000000U /* fDTG = fSHRTIM * 8 */ +#define SHRTIM_DT_PRESCALER_MUL4 (SHRTIM_TXDT_DTPSC_0) /* fDTG = fSHRTIM * 4 */ +#define SHRTIM_DT_PRESCALER_MUL2 (SHRTIM_TXDT_DTPSC_1) /* fDTG = fSHRTIM * 2 */ +#define SHRTIM_DT_PRESCALER_DIV1 (SHRTIM_TXDT_DTPSC_1 | SHRTIM_TXDT_DTPSC_0) /* fDTG = fSHRTIM */ +#define SHRTIM_DT_PRESCALER_DIV2 (SHRTIM_TXDT_DTPSC_2) /* fDTG = fSHRTIM / 2 */ +#define SHRTIM_DT_PRESCALER_DIV4 (SHRTIM_TXDT_DTPSC_2 | SHRTIM_TXDT_DTPSC_0) /* fDTG = fSHRTIM / 4 */ +#define SHRTIM_DT_PRESCALER_DIV8 (SHRTIM_TXDT_DTPSC_2 | SHRTIM_TXDT_DTPSC_1) /* fDTG = fSHRTIM / 8 */ +#define SHRTIM_DT_PRESCALER_DIV16 (SHRTIM_TXDT_DTPSC_2 | SHRTIM_TXDT_DTPSC_1 | SHRTIM_TXDT_DTPSC_0) /* fDTG = fSHRTIM / 16 */ + + +/** Defining whether the deadtime is positive or negative (overlapping signal) on rising edge. **/ +#define SHRTIM_DT_RISING_POSITIVE 0x00000000U /* Positive deadtime on rising edge */ +#define SHRTIM_DT_RISING_NEGATIVE (SHRTIM_TXDT_SDTR) /* Negative deadtime on rising edge */ + + +/** Defining whether the deadtime is positive or negative (overlapping signal) on falling edge. **/ +#define SHRTIM_DT_FALLING_POSITIVE 0x00000000U /* Positive deadtime on falling edge */ +#define SHRTIM_DT_FALLING_NEGATIVE (SHRTIM_TXDT_SDTF) /* Negative deadtime on falling edge */ + + +/** Defining the frequency of the generated high frequency carrier (fCHPFRQ). **/ +#define SHRTIM_CHP_PRESCALER_DIV16 0x00000000U /* fCHPFRQ = fSHRTIM / 16 */ +#define SHRTIM_CHP_PRESCALER_DIV32 (SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 32 */ +#define SHRTIM_CHP_PRESCALER_DIV48 (SHRTIM_TXCHOP_CARFRQ_1) /* fCHPFRQ = fSHRTIM / 48 */ +#define SHRTIM_CHP_PRESCALER_DIV64 (SHRTIM_TXCHOP_CARFRQ_1 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 64 */ +#define SHRTIM_CHP_PRESCALER_DIV80 (SHRTIM_TXCHOP_CARFRQ_2) /* fCHPFRQ = fSHRTIM / 80 */ +#define SHRTIM_CHP_PRESCALER_DIV96 (SHRTIM_TXCHOP_CARFRQ_2 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 96 */ +#define SHRTIM_CHP_PRESCALER_DIV112 (SHRTIM_TXCHOP_CARFRQ_2 | SHRTIM_TXCHOP_CARFRQ_1) /* fCHPFRQ = fSHRTIM / 112 */ +#define SHRTIM_CHP_PRESCALER_DIV128 (SHRTIM_TXCHOP_CARFRQ_2 | SHRTIM_TXCHOP_CARFRQ_1 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 128 */ +#define SHRTIM_CHP_PRESCALER_DIV144 (SHRTIM_TXCHOP_CARFRQ_3) /* fCHPFRQ = fSHRTIM / 144 */ +#define SHRTIM_CHP_PRESCALER_DIV160 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 160 */ +#define SHRTIM_CHP_PRESCALER_DIV176 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_1) /* fCHPFRQ = fSHRTIM / 176 */ +#define SHRTIM_CHP_PRESCALER_DIV192 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_1 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 192 */ +#define SHRTIM_CHP_PRESCALER_DIV208 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_2) /* fCHPFRQ = fSHRTIM / 208 */ +#define SHRTIM_CHP_PRESCALER_DIV224 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_2 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 224 */ +#define SHRTIM_CHP_PRESCALER_DIV240 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_2 | SHRTIM_TXCHOP_CARFRQ_1) /* fCHPFRQ = fSHRTIM / 240 */ +#define SHRTIM_CHP_PRESCALER_DIV256 (SHRTIM_TXCHOP_CARFRQ_3 | SHRTIM_TXCHOP_CARFRQ_2 | SHRTIM_TXCHOP_CARFRQ_1 | SHRTIM_TXCHOP_CARFRQ_0) /* fCHPFRQ = fSHRTIM / 256 */ + + +/** Defining the duty cycle of the generated high frequency carrier. + Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8). **/ +#define SHRTIM_CHP_DUTYCYCLE_0 0x00000000U /* Only 1st pulse is present */ +#define SHRTIM_CHP_DUTYCYCLE_125 (SHRTIM_TXCHOP_CARDCY_0) /* Duty cycle of the carrier signal is 12.5 % */ +#define SHRTIM_CHP_DUTYCYCLE_250 (SHRTIM_TXCHOP_CARDCY_1) /* Duty cycle of the carrier signal is 25 % */ +#define SHRTIM_CHP_DUTYCYCLE_375 (SHRTIM_TXCHOP_CARDCY_1 | SHRTIM_TXCHOP_CARDCY_0) /* Duty cycle of the carrier signal is 37.5 % */ +#define SHRTIM_CHP_DUTYCYCLE_500 (SHRTIM_TXCHOP_CARDCY_2) /* Duty cycle of the carrier signal is 50 % */ +#define SHRTIM_CHP_DUTYCYCLE_625 (SHRTIM_TXCHOP_CARDCY_2 | SHRTIM_TXCHOP_CARDCY_0) /* Duty cycle of the carrier signal is 62.5 % */ +#define SHRTIM_CHP_DUTYCYCLE_750 (SHRTIM_TXCHOP_CARDCY_2 | SHRTIM_TXCHOP_CARDCY_1) /* Duty cycle of the carrier signal is 75 % */ +#define SHRTIM_CHP_DUTYCYCLE_875 (SHRTIM_TXCHOP_CARDCY_2 | SHRTIM_TXCHOP_CARDCY_1 | SHRTIM_TXCHOP_CARDCY_0) /* Duty cycle of the carrier signal is 87.5 % */ + + +/** Defining the pulse width of the first pulse of the generated high frequency carrier. **/ +#define SHRTIM_CHP_PULSEWIDTH_16 0x00000000U /* tSTPW = tHRTIM x 16 */ +#define SHRTIM_CHP_PULSEWIDTH_32 (SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 32 */ +#define SHRTIM_CHP_PULSEWIDTH_48 (SHRTIM_TXCHOP_STARTPW_1) /* tSTPW = tHRTIM x 48 */ +#define SHRTIM_CHP_PULSEWIDTH_64 (SHRTIM_TXCHOP_STARTPW_1 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 64 */ +#define SHRTIM_CHP_PULSEWIDTH_80 (SHRTIM_TXCHOP_STARTPW_2) /* tSTPW = tHRTIM x 80 */ +#define SHRTIM_CHP_PULSEWIDTH_96 (SHRTIM_TXCHOP_STARTPW_2 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 96 */ +#define SHRTIM_CHP_PULSEWIDTH_112 (SHRTIM_TXCHOP_STARTPW_2 | SHRTIM_TXCHOP_STARTPW_1) /* tSTPW = tHRTIM x 112 */ +#define SHRTIM_CHP_PULSEWIDTH_128 (SHRTIM_TXCHOP_STARTPW_2 | SHRTIM_TXCHOP_STARTPW_1 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 128 */ +#define SHRTIM_CHP_PULSEWIDTH_144 (SHRTIM_TXCHOP_STARTPW_3) /* tSTPW = tHRTIM x 144 */ +#define SHRTIM_CHP_PULSEWIDTH_160 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 160 */ +#define SHRTIM_CHP_PULSEWIDTH_176 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_1) /* tSTPW = tHRTIM x 176 */ +#define SHRTIM_CHP_PULSEWIDTH_192 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_1 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 192 */ +#define SHRTIM_CHP_PULSEWIDTH_208 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_2) /* tSTPW = tHRTIM x 208 */ +#define SHRTIM_CHP_PULSEWIDTH_224 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_2 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 224 */ +#define SHRTIM_CHP_PULSEWIDTH_240 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_2 | SHRTIM_TXCHOP_STARTPW_1) /* tSTPW = tHRTIM x 240 */ +#define SHRTIM_CHP_PULSEWIDTH_256 (SHRTIM_TXCHOP_STARTPW_3 | SHRTIM_TXCHOP_STARTPW_2 | SHRTIM_TXCHOP_STARTPW_1 | SHRTIM_TXCHOP_STARTPW_0) /* tSTPW = tHRTIM x 256 */ + +/** Defining the events that can be selected to configure the set/reset crossbar of a timer output. **/ +#define SHRTIM_OUTPUTSET_NONE 0x00000000U /* Reset the output set crossbar */ +#define SHRTIM_OUTPUTSET_RESYNC (SHRTIM_TXSET1_RSYNC) /* Timer reset event coming solely from software or SYNC input forces an output level transition */ +#define SHRTIM_OUTPUTSET_TIMPER (SHRTIM_TXSET1_PRD) /* Timer period event forces an output level transition */ +#define SHRTIM_OUTPUTSET_TIMCMP1 (SHRTIM_TXSET1_CMP1) /* Timer compare 1 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_TIMCMP2 (SHRTIM_TXSET1_CMP2) /* Timer compare 2 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_TIMCMP3 (SHRTIM_TXSET1_CMP3) /* Timer compare 3 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_TIMCMP4 (SHRTIM_TXSET1_CMP4) /* Timer compare 4 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_MASTERPER (SHRTIM_TXSET1_MPRD) /* The master timer period event forces an output level transition */ +#define SHRTIM_OUTPUTSET_MASTERCMP1 (SHRTIM_TXSET1_MCMP1) /* Master Timer compare 1 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_MASTERCMP2 (SHRTIM_TXSET1_MCMP2) /* Master Timer compare 2 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_MASTERCMP3 (SHRTIM_TXSET1_MCMP3) /* Master Timer compare 3 event forces an output level transition */ +#define SHRTIM_OUTPUTSET_MASTERCMP4 (SHRTIM_TXSET1_MCMP4) /* Master Timer compare 4 event forces an output level transition */ +/* Timer Events mapping for Timer A */ +#define SHRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (SHRTIM_TXSET1_TIMEV1) /* Timer event 1 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (SHRTIM_TXSET1_TIMEV2) /* Timer event 2 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (SHRTIM_TXSET1_TIMEV3) /* Timer event 3 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (SHRTIM_TXSET1_TIMEV4) /* Timer event 4 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (SHRTIM_TXSET1_TIMEV5) /* Timer event 5 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (SHRTIM_TXSET1_TIMEV6) /* Timer event 6 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (SHRTIM_TXSET1_TIMEV7) /* Timer event 7 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (SHRTIM_TXSET1_TIMEV8) /* Timer event 8 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (SHRTIM_TXSET1_TIMEV9) /* Timer event 9 forces the output to its active state */ +/* Timer Events mapping for Timer B */ +#define SHRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (SHRTIM_TXSET1_TIMEV1) /* Timer event 1 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (SHRTIM_TXSET1_TIMEV2) /* Timer event 2 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (SHRTIM_TXSET1_TIMEV3) /* Timer event 3 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (SHRTIM_TXSET1_TIMEV4) /* Timer event 4 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (SHRTIM_TXSET1_TIMEV5) /* Timer event 5 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (SHRTIM_TXSET1_TIMEV6) /* Timer event 6 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (SHRTIM_TXSET1_TIMEV7) /* Timer event 7 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (SHRTIM_TXSET1_TIMEV8) /* Timer event 8 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (SHRTIM_TXSET1_TIMEV9) /* Timer event 9 forces the output to its active state */ +/* Timer Events mapping for Timer C */ +#define SHRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (SHRTIM_TXSET1_TIMEV1) /* Timer event 1 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (SHRTIM_TXSET1_TIMEV2) /* Timer event 2 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (SHRTIM_TXSET1_TIMEV3) /* Timer event 3 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (SHRTIM_TXSET1_TIMEV4) /* Timer event 4 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (SHRTIM_TXSET1_TIMEV5) /* Timer event 5 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (SHRTIM_TXSET1_TIMEV6) /* Timer event 6 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (SHRTIM_TXSET1_TIMEV7) /* Timer event 7 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (SHRTIM_TXSET1_TIMEV8) /* Timer event 8 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (SHRTIM_TXSET1_TIMEV9) /* Timer event 9 forces the output to its active state */ +/* Timer Events mapping for Timer D */ +#define SHRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (SHRTIM_TXSET1_TIMEV1) /* Timer event 1 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (SHRTIM_TXSET1_TIMEV2) /* Timer event 2 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (SHRTIM_TXSET1_TIMEV3) /* Timer event 3 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (SHRTIM_TXSET1_TIMEV4) /* Timer event 4 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (SHRTIM_TXSET1_TIMEV5) /* Timer event 5 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (SHRTIM_TXSET1_TIMEV6) /* Timer event 6 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (SHRTIM_TXSET1_TIMEV7) /* Timer event 7 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (SHRTIM_TXSET1_TIMEV8) /* Timer event 8 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (SHRTIM_TXSET1_TIMEV9) /* Timer event 9 forces the output to its active state */ +/* Timer Events mapping for Timer E */ +#define SHRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (SHRTIM_TXSET1_TIMEV1) /* Timer event 1 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (SHRTIM_TXSET1_TIMEV2) /* Timer event 2 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (SHRTIM_TXSET1_TIMEV3) /* Timer event 3 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (SHRTIM_TXSET1_TIMEV4) /* Timer event 4 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (SHRTIM_TXSET1_TIMEV5) /* Timer event 5 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (SHRTIM_TXSET1_TIMEV6) /* Timer event 6 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (SHRTIM_TXSET1_TIMEV7) /* Timer event 7 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (SHRTIM_TXSET1_TIMEV8) /* Timer event 8 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (SHRTIM_TXSET1_TIMEV9) /* Timer event 9 forces the output to its active state */ +/* Timer Events mapping for Timer F */ +#define SHRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (SHRTIM_TXSET1_TIMEV1) /* Timer event 1 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (SHRTIM_TXSET1_TIMEV2) /* Timer event 2 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (SHRTIM_TXSET1_TIMEV3) /* Timer event 3 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (SHRTIM_TXSET1_TIMEV4) /* Timer event 4 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (SHRTIM_TXSET1_TIMEV5) /* Timer event 5 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (SHRTIM_TXSET1_TIMEV6) /* Timer event 6 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (SHRTIM_TXSET1_TIMEV7) /* Timer event 7 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (SHRTIM_TXSET1_TIMEV8) /* Timer event 8 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (SHRTIM_TXSET1_TIMEV9) /* Timer event 9 forces the output to its active state */ +#define SHRTIM_OUTPUTSET_EXEV_1 (SHRTIM_TXSET1_EXEV1) /* External event 1 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_2 (SHRTIM_TXSET1_EXEV2) /* External event 2 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_3 (SHRTIM_TXSET1_EXEV3) /* External event 3 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_4 (SHRTIM_TXSET1_EXEV4) /* External event 4 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_5 (SHRTIM_TXSET1_EXEV5) /* External event 5 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_6 (SHRTIM_TXSET1_EXEV6) /* External event 6 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_7 (SHRTIM_TXSET1_EXEV7) /* External event 7 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_8 (SHRTIM_TXSET1_EXEV8) /* External event 8 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_9 (SHRTIM_TXSET1_EXEV9) /* External event 9 forces an output level transition */ +#define SHRTIM_OUTPUTSET_EXEV_10 (SHRTIM_TXSET1_EXEV10) /* External event 10 forces an output level transition */ +#define SHRTIM_OUTPUTSET_UPDATE (SHRTIM_TXSET1_UPD) /* Timer register update event forces an output level transition */ + +/** Defining the events that can be selected to configure the set crossbar of a timer output **/ +#define SHRTIM_OUTPUTRESET_NONE 0x00000000U /* Reset the output reset crossbar */ +#define SHRTIM_OUTPUTRESET_RESYNC (SHRTIM_TXRST1_RSYNC) /* Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMPER (SHRTIM_TXRST1_PRD) /* Timer period event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCMP1 (SHRTIM_TXRST1_CMP1) /* Timer compare 1 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCMP2 (SHRTIM_TXRST1_CMP2) /* Timer compare 2 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCMP3 (SHRTIM_TXRST1_CMP3) /* Timer compare 3 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCMP4 (SHRTIM_TXRST1_CMP4) /* Timer compare 4 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_MASTERPER (SHRTIM_TXRST1_MPRD) /* The master timer period event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_MASTERCMP1 (SHRTIM_TXRST1_MCMP1) /* Master Timer compare 1 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_MASTERCMP2 (SHRTIM_TXRST1_MCMP2) /* Master Timer compare 2 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_MASTERCMP3 (SHRTIM_TXRST1_MCMP3) /* Master Timer compare 3 event forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_MASTERCMP4 (SHRTIM_TXRST1_MCMP4) /* Master Timer compare 4 event forces the output to its inactive state */ +/* Timer Events mapping for Timer A */ +#define SHRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (SHRTIM_TXRST1_TIMEV1) /* Timer event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (SHRTIM_TXRST1_TIMEV2) /* Timer event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (SHRTIM_TXRST1_TIMEV3) /* Timer event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (SHRTIM_TXRST1_TIMEV4) /* Timer event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (SHRTIM_TXRST1_TIMEV5) /* Timer event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (SHRTIM_TXRST1_TIMEV6) /* Timer event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (SHRTIM_TXRST1_TIMEV7) /* Timer event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (SHRTIM_TXRST1_TIMEV8) /* Timer event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (SHRTIM_TXRST1_TIMEV9) /* Timer event 9 forces the output to its inactive state */ +/* Timer Events mapping for Timer B */ +#define SHRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (SHRTIM_TXRST1_TIMEV1) /* Timer event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (SHRTIM_TXRST1_TIMEV2) /* Timer event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (SHRTIM_TXRST1_TIMEV3) /* Timer event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (SHRTIM_TXRST1_TIMEV4) /* Timer event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (SHRTIM_TXRST1_TIMEV5) /* Timer event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (SHRTIM_TXRST1_TIMEV6) /* Timer event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (SHRTIM_TXRST1_TIMEV7) /* Timer event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (SHRTIM_TXRST1_TIMEV8) /* Timer event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (SHRTIM_TXRST1_TIMEV9) /* Timer event 9 forces the output to its inactive state */ +/* Timer Events mapping for Timer C */ +#define SHRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (SHRTIM_TXRST1_TIMEV1) /* Timer event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (SHRTIM_TXRST1_TIMEV2) /* Timer event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (SHRTIM_TXRST1_TIMEV3) /* Timer event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (SHRTIM_TXRST1_TIMEV4) /* Timer event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (SHRTIM_TXRST1_TIMEV5) /* Timer event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (SHRTIM_TXRST1_TIMEV6) /* Timer event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (SHRTIM_TXRST1_TIMEV7) /* Timer event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (SHRTIM_TXRST1_TIMEV8) /* Timer event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (SHRTIM_TXRST1_TIMEV9) /* Timer event 9 forces the output to its inactive state */ +/* Timer Events mapping for Timer D */ +#define SHRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (SHRTIM_TXRST1_TIMEV1) /* Timer event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (SHRTIM_TXRST1_TIMEV2) /* Timer event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (SHRTIM_TXRST1_TIMEV3) /* Timer event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (SHRTIM_TXRST1_TIMEV4) /* Timer event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (SHRTIM_TXRST1_TIMEV5) /* Timer event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (SHRTIM_TXRST1_TIMEV6) /* Timer event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (SHRTIM_TXRST1_TIMEV7) /* Timer event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (SHRTIM_TXRST1_TIMEV8) /* Timer event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (SHRTIM_TXRST1_TIMEV9) /* Timer event 9 forces the output to its inactive state */ +/* Timer Events mapping for Timer E */ +#define SHRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (SHRTIM_TXRST1_TIMEV1) /* Timer event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (SHRTIM_TXRST1_TIMEV2) /* Timer event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (SHRTIM_TXRST1_TIMEV3) /* Timer event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (SHRTIM_TXRST1_TIMEV4) /* Timer event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (SHRTIM_TXRST1_TIMEV5) /* Timer event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (SHRTIM_TXRST1_TIMEV6) /* Timer event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (SHRTIM_TXRST1_TIMEV7) /* Timer event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (SHRTIM_TXRST1_TIMEV8) /* Timer event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (SHRTIM_TXRST1_TIMEV9) /* Timer event 9 forces the output to its inactive state */ +/* Timer Events mapping for Timer F */ +#define SHRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (SHRTIM_TXRST1_TIMEV1) /* Timer event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (SHRTIM_TXRST1_TIMEV2) /* Timer event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (SHRTIM_TXRST1_TIMEV3) /* Timer event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (SHRTIM_TXRST1_TIMEV4) /* Timer event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (SHRTIM_TXRST1_TIMEV5) /* Timer event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (SHRTIM_TXRST1_TIMEV6) /* Timer event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (SHRTIM_TXRST1_TIMEV7) /* Timer event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (SHRTIM_TXRST1_TIMEV8) /* Timer event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (SHRTIM_TXRST1_TIMEV9) /* Timer event 9 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_1 (SHRTIM_TXRST1_EXEV1) /* External event 1 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_2 (SHRTIM_TXRST1_EXEV2) /* External event 2 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_3 (SHRTIM_TXRST1_EXEV3) /* External event 3 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_4 (SHRTIM_TXRST1_EXEV4) /* External event 4 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_5 (SHRTIM_TXRST1_EXEV5) /* External event 5 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_6 (SHRTIM_TXRST1_EXEV6) /* External event 6 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_7 (SHRTIM_TXRST1_EXEV7) /* External event 7 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_8 (SHRTIM_TXRST1_EXEV8) /* External event 8 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_9 (SHRTIM_TXRST1_EXEV9) /* External event 9 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_EXEV_10 (SHRTIM_TXRST1_EXEV10) /* External event 10 forces the output to its inactive state */ +#define SHRTIM_OUTPUTRESET_UPDATE (SHRTIM_TXRST1_UPD) /* Timer register update event forces the output to its inactive state */ + + +/** Defining the polarity of a timer output. **/ +#define SHRTIM_OUT_POSITIVE_POLARITY 0x00000000U /* Output is active HIGH */ +#define SHRTIM_OUT_NEGATIVE_POLARITY (SHRTIM_TXOUT_POL1) /* Output is active LOW */ + +/** Defining the interleaved mode of an SHRTIM Timer instance. + */ +#define SHRTIM_INTERLEAVED_MODE_DISABLED 0x000U /* SHRTIM interleaved Mode is disabled */ +#define SHRTIM_INTERLEAVED_MODE_DUAL SHRTIM_MCTRL_HLF /* SHRTIM interleaved Mode is Dual */ +#define SHRTIM_INTERLEAVED_MODE_TRIPLE SHRTIM_MCTRL_ILV_0 /* SHRTIM interleaved Mode is Triple */ +#define SHRTIM_INTERLEAVED_MODE_QUAD SHRTIM_MCTRL_ILV_1 /* SHRTIM interleaved Mode is Quad */ + +/** Defining the half mode of an SHRTIM Timer instance. **/ +#define SHRTIM_HALF_MODE_DISABLED 0x000U /* SHRTIM Half Mode is disabled */ +#define SHRTIM_HALF_MODE_ENABLE SHRTIM_MCTRL_HLF /* SHRTIM Half Mode is Half */ + +/** Defining the output level when output is in IDLE state **/ +#define SHRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /* Output at inactive level when in IDLE state */ +#define SHRTIM_OUT_IDLELEVEL_ACTIVE (SHRTIM_TXOUT_IDLES1) /* Output at active level when in IDLE state */ + + +/** Defining the output level when output is in FAULT state. **/ +#define SHRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /* The output is not affected by the fault input */ +#define SHRTIM_OUT_FAULTSTATE_ACTIVE (SHRTIM_TXOUT_FALT1_0) /* Output at active level when in FAULT state */ +#define SHRTIM_OUT_FAULTSTATE_INACTIVE (SHRTIM_TXOUT_FALT1_1) /* Output at inactive level when in FAULT state */ +#define SHRTIM_OUT_FAULTSTATE_HIGHZ (SHRTIM_TXOUT_FALT1_1 | SHRTIM_TXOUT_FALT1_0) /* Output is tri-stated when in FAULT state */ + +/** Defining whether or not chopper mode is enabled for a timer output. **/ +#define SHRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /* Output signal is not altered */ +#define SHRTIM_OUT_CHOPPERMODE_ENABLED (SHRTIM_TXOUT_CHP1) /* Output signal is chopped by a carrier signal */ + +/** Defining the idle state entry mode during a burst mode operation. + It is possible to delay the burst mode entry and force the output to an inactive state + during a programmable period before the output takes its idle state. **/ +#define SHRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /* The programmed Idle state is applied immediately to the Output */ +#define SHRTIM_OUT_BM_ENTRYMODE_DELAYED (SHRTIM_TXOUT_DIDL1) /* Deadtime is inserted on output before entering the idle mode */ + +/** Defining the level of a timer output. + */ +#define SHRTIM_OUT_LEVEL_INACTIVE 0x00000000U /* Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */ +#define SHRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /* Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */ + + +/** Defining available sources associated to external events. **/ +#define SHRTIM_EXEV1SRC_GPIO 0x00000000U /* External event source 1 for External Event 1 */ +#define SHRTIM_EXEV2SRC_GPIO 0x00000000U /* External event source 1 for External Event 2 */ +#define SHRTIM_EXEV3SRC_GPIO 0x00000000U /* External event source 1 for External Event 3 */ +#define SHRTIM_EXEV4SRC_GPIO 0x00000000U /* External event source 1 for External Event 4 */ +#define SHRTIM_EXEV5SRC_GPIO 0x00000000U /* External event source 1 for External Event 5 */ +#define SHRTIM_EXEV6SRC_GPIO 0x00000000U /* External event source 1 for External Event 6 */ +#define SHRTIM_EXEV7SRC_GPIO 0x00000000U /* External event source 1 for External Event 7 */ +#define SHRTIM_EXEV8SRC_GPIO 0x00000000U /* External event source 1 for External Event 8 */ +#define SHRTIM_EXEV9SRC_GPIO 0x00000000U /* External event source 1 for External Event 9 */ +#define SHRTIM_EXEV10SRC_GPIO 0x00000000U /* External event source 1 for External Event 10 */ +#define SHRTIM_EXEV1SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 1 */ +#define SHRTIM_EXEV2SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 2 */ +#define SHRTIM_EXEV3SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 3 */ +#define SHRTIM_EXEV4SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 4 */ +#define SHRTIM_EXEV5SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 5 */ +#define SHRTIM_EXEV6SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 6 */ +#define SHRTIM_EXEV7SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 7 */ +#define SHRTIM_EXEV8SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 8 */ +#define SHRTIM_EXEV9SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 9 */ +#define SHRTIM_EXEV10SRC_COMPx_OUT (SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 2 for External Event 10 */ +#define SHRTIM_EXEV1SRC_ATIM1_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 1 */ +#define SHRTIM_EXEV2SRC_GTIMA1_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 2 */ +#define SHRTIM_EXEV3SRC_GTIMA2_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 3 */ +#define SHRTIM_EXEV4SRC_ATIM2_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 4 */ +#define SHRTIM_EXEV5SRC_ATIM3_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 5 */ +#define SHRTIM_EXEV6SRC_ATIM4_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 6 */ +#define SHRTIM_EXEV7SRC_GTIMA6_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 7 */ +#define SHRTIM_EXEV8SRC_GTIMA4_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 8 */ +#define SHRTIM_EXEV9SRC_GTIMA7_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 9 */ +#define SHRTIM_EXEV10SRC_GTIMA5_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 3 for External Event 10 */ +#define SHRTIM_EXEV1SRC_ADC1_AWD1 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 1 */ +#define SHRTIM_EXEV2SRC_ADC1_AWD2 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 2 */ +#define SHRTIM_EXEV3SRC_ADC1_AWD3 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 3 */ +#define SHRTIM_EXEV4SRC_ADC2_AWD1 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 4 */ +#define SHRTIM_EXEV5SRC_ADC2_AWD2 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 5 */ +#define SHRTIM_EXEV6SRC_ADC2_AWD3 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 6 */ +#define SHRTIM_EXEV7SRC_ADC3_AWD1 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 7 */ +#define SHRTIM_EXEV8SRC_ADC3_AWD2 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 8 */ +#define SHRTIM_EXEV9SRC_GTIMA3_TRGO (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 9 */ +#define SHRTIM_EXEV10SRC_ADC3_AWD3 (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_0) /* External event source 4 for External Event 10 */ +#define SHRTIM1_EXEV1SRC_CAN2_RTP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 1 */ +#define SHRTIM1_EXEV2SRC_CAN2_TMP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 2 */ +#define SHRTIM1_EXEV3SRC_CAN2_SOC (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 3 */ +#define SHRTIM1_EXEV4SRC_CAN1_RTP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 4 */ +#define SHRTIM1_EXEV5SRC_CAN1_TMP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 5 */ +#define SHRTIM1_EXEV6SRC_CAN1_SOC (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 6 */ +#define SHRTIM2_EXEV1SRC_CAN4_RTP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 1 */ +#define SHRTIM2_EXEV2SRC_CAN4_TMP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 2 */ +#define SHRTIM2_EXEV3SRC_CAN4_SOC (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 3 */ +#define SHRTIM2_EXEV4SRC_CAN3_RTP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 4 */ +#define SHRTIM2_EXEV5SRC_CAN3_TMP (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 5 */ +#define SHRTIM2_EXEV6SRC_CAN3_SOC (SHRTIM_EXEVCTRL1_EXEV1SRC_1 | SHRTIM_EXEVCTRL1_EXEV1SRC_1) /* External event source 4 for External Event 6 */ + + +/** Select the analog comparator of external event source 2 **/ +#define SHRTIM_EXEVXSRC2_COMP1_OUT 0x00000000U /* Compx is comp1 out*/ +#define SHRTIM_EXEVXSRC2_COMP2_OUT (SHRTIM_EXEVCTRL5_EXEV1CSEL_0) /* Compx is comp2 out */ +#define SHRTIM_EXEVXSRC2_COMP3_OUT (SHRTIM_EXEVCTRL5_EXEV1CSEL_1) /* Compx is comp3 out */ +#define SHRTIM_EXEVXSRC2_COMP4_OUT (SHRTIM_EXEVCTRL5_EXEV1CSEL_1 | SHRTIM_EXEVCTRL5_EXEV1CSEL_0) /* Compx is comp4 out */ +#define SHRTIM_EXEVXSRC2_COMP5_OUT (SHRTIM_EXEVCTRL5_EXEV1CSEL_2) /* Compx is comp5 out */ +#define SHRTIM_EXEVXSRC2_COMP6_OUT (SHRTIM_EXEVCTRL5_EXEV1CSEL_2 | SHRTIM_EXEVCTRL5_EXEV1CSEL_0) /* Compx is comp6 out */ +#define SHRTIM_EXEVXSRC2_COMP7_OUT (SHRTIM_EXEVCTRL5_EXEV1CSEL_2 | SHRTIM_EXEVCTRL5_EXEV1CSEL_1) /* Compx is comp7 out */ +#define SHRTIM_EXEVXSRC2_COMP_NONE (SHRTIM_EXEVCTRL5_EXEV1CSEL_2 | SHRTIM_EXEVCTRL5_EXEV1CSEL_1 | SHRTIM_EXEVCTRL5_EXEV1CSEL_0) /* No comparator */ + +/** Defining the polarity of an external event. **/ +#define SHRTIM_EXEV_POLARITY_HIGH 0x00000000U /* External event is active high */ +#define SHRTIM_EXEV_POLARITY_LOW (SHRTIM_EXEVCTRL1_EXEV1POL) /* External event is active low */ + + +/** Defining the sensitivity (level-sensitive or edge-sensitive) of an external event. **/ +#define SHRTIM_EXEV_SENSITIVITY_LEVEL 0x00000000U /* External event is active on level */ +#define SHRTIM_EXEV_SENSITIVITY_RISINGEDGE (SHRTIM_EXEVCTRL1_EXEV1SENS_0) /* External event is active on Rising edge */ +#define SHRTIM_EXEV_SENSITIVITY_FALLINGEDGE (SHRTIM_EXEVCTRL1_EXEV1SENS_1) /* External event is active on Falling edge */ +#define SHRTIM_EXEV_SENSITIVITY_BOTHEDGES (SHRTIM_EXEVCTRL1_EXEV1SENS_1 | SHRTIM_EXEVCTRL1_EXEV1SENS_0) /* External event is active on Rising and Falling edges */ + + +/** Defining whether or not an external event is programmed in fast mode. **/ +#define SHRTIM_EXEV_FASTMODE_DISABLE 0x00000000U /* External Event is re-synchronized by the SHRTIM logic before acting on outputs */ +#define SHRTIM_EXEV_FASTMODE_ENABLE (SHRTIM_EXEVCTRL3_EXEV1FM) /* External Event is acting asynchronously on outputs (low latency mode) */ + + +/** Defining the frequency used to sample an external event input (fSAMPLING) + and the length (N) of the digital filter applied. **/ +#define SHRTIM_EXEV_FILTER_NONE 0x00000000U /* Filter disabled */ +#define SHRTIM_EXEV_FILTER_1 (SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fSHRTIM, N=2 */ +#define SHRTIM_EXEV_FILTER_2 (SHRTIM_EXEVCTRL3_EXEV1F_1) /* fSAMPLING = fSHRTIM, N=4 */ +#define SHRTIM_EXEV_FILTER_3 (SHRTIM_EXEVCTRL3_EXEV1F_1 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fSHRTIM, N=8 */ +#define SHRTIM_EXEV_FILTER_4 (SHRTIM_EXEVCTRL3_EXEV1F_2) /* fSAMPLING = fEXEVS/2, N=6 */ +#define SHRTIM_EXEV_FILTER_5 (SHRTIM_EXEVCTRL3_EXEV1F_2 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fEXEVS/2, N=8 */ +#define SHRTIM_EXEV_FILTER_6 (SHRTIM_EXEVCTRL3_EXEV1F_2 | SHRTIM_EXEVCTRL3_EXEV1F_1) /* fSAMPLING = fEXEVS/4, N=6 */ +#define SHRTIM_EXEV_FILTER_7 (SHRTIM_EXEVCTRL3_EXEV1F_2 | SHRTIM_EXEVCTRL3_EXEV1F_1 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fEXEVS/4, N=8 */ +#define SHRTIM_EXEV_FILTER_8 (SHRTIM_EXEVCTRL3_EXEV1F_3) /* fSAMPLING = fEXEVS/8, N=6 */ +#define SHRTIM_EXEV_FILTER_9 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fEXEVS/8, N=8 */ +#define SHRTIM_EXEV_FILTER_10 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_1) /* fSAMPLING = fEXEVS/16, N=5 */ +#define SHRTIM_EXEV_FILTER_11 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_1 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fEXEVS/16, N=6 */ +#define SHRTIM_EXEV_FILTER_12 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_2) /* fSAMPLING = fEXEVS/16, N=8 */ +#define SHRTIM_EXEV_FILTER_13 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_2 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fEXEVS/32, N=5 */ +#define SHRTIM_EXEV_FILTER_14 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_2 | SHRTIM_EXEVCTRL3_EXEV1F_1) /* fSAMPLING = fEXEVS/32, N=6 */ +#define SHRTIM_EXEV_FILTER_15 (SHRTIM_EXEVCTRL3_EXEV1F_3 | SHRTIM_EXEVCTRL3_EXEV1F_2 | SHRTIM_EXEVCTRL3_EXEV1F_1 | SHRTIM_EXEVCTRL3_EXEV1F_0) /* fSAMPLING = fEXEVS/32, N=8 */ + + +/** Defining division ratio between the timer clock frequency (fSHRTIM) and the external event signal sampling clock (fEXEVS) used by the digital filters. + */ +#define SHRTIM_EXEV_PRESCALER_DIV1 0x00000000U /* fEXEVS = fSHRTIM */ +#define SHRTIM_EXEV_PRESCALER_DIV2 (SHRTIM_EXEVCTRL4_EXEVSCD_0) /* fEXEVS = fSHRTIM / 2 */ +#define SHRTIM_EXEV_PRESCALER_DIV4 (SHRTIM_EXEVCTRL4_EXEVSCD_1) /* fEXEVS = fSHRTIM / 4 */ +#define SHRTIM_EXEV_PRESCALER_DIV8 (SHRTIM_EXEVCTRL4_EXEVSCD_1 | SHRTIM_EXEVCTRL4_EXEVSCD_0) /* fEXEVS = fSHRTIM / 8 */ + + +/** Defining the external event counter. **/ +#define SHRTIM_EXEV_COUNTER_A ((uint32_t)0U) /* External Event A Counter */ +#define SHRTIM_EXEV_COUNTER_B ((uint32_t)16U) /* External Event B Counter */ + + +/** Defining the external event reset mode. **/ +#define SHRTIM_EXEV_COUNTER_RSTMODE_UNCONDITIONAL ((uint32_t)0U) /* External Event counter is reset on each reset / roll-over event */ +#define SHRTIM_EXEV_COUNTER_RSTMODE_CONDITIONAL ((uint32_t)SHRTIM_TXEXEVFLT3_EXEVRSTM) /* External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */ + + +/** Defining whether a faults is be triggered by any external or internal fault source. **/ +#define SHRTIM_FALT_SRC_DIGITALINPUT 0x00000000U /* Fault source 1, Fault input is FLT input pin */ +#define SHRTIM_FALT_SRC_INTERNAL SHRTIM_FALTIN1_FALT1SRC0 /* Fault source 2, Fault input is FLT_Int signal (e.g. internal comparator) */ +#define SHRTIM_FALT_SRC_EXEVINPUT SHRTIM_FALTIN2_FALT1SRC1 /* Fault source 3, Fault input is external event pin */ +#define SHRTIM_FALT_SRC_DSMU SHRTIM_FALTIN2_FALT1SRC1 | SHRTIM_FALTIN2_FALT1SRC0/* Fault source 4, Fault input is DSMU */ + +/** Select the analog comparator of fault source 2. **/ +/** Select the analog comparator of external event source **/ +#define SHRTIM_FALTXSRC2_COMP1_OUT 0x00000000U /* Compx is comp1 out*/ +#define SHRTIM_FALTXSRC2_COMP2_OUT (SHRTIM_FALTIN5_FALT1CSEL_0) /* Compx is comp2 out */ +#define SHRTIM_FALTXSRC2_COMP3_OUT (SHRTIM_FALTIN5_FALT1CSEL_1) /* Compx is comp3 out */ +#define SHRTIM_FALTXSRC2_COMP4_OUT (SHRTIM_FALTIN5_FALT1CSEL_1 | SHRTIM_FALTIN5_FALT1CSEL_0) /* Compx is comp4 out */ +#define SHRTIM_FALTXSRC2_COMP5_OUT (SHRTIM_FALTIN5_FALT1CSEL_2) /* Compx is comp5 out */ +#define SHRTIM_FALTXSRC2_COMP6_OUT (SHRTIM_FALTIN5_FALT1CSEL_2 | SHRTIM_FALTIN5_FALT1CSEL_0) /* Compx is comp6 out */ +#define SHRTIM_FALTXSRC2_COMP7_OUT (SHRTIM_FALTIN5_FALT1CSEL_2 | SHRTIM_FALTIN5_FALT1CSEL_1) /* Compx is comp7 out */ +#define SHRTIM_FALTXSRC2_COMP_NONE (SHRTIM_FALTIN5_FALT1CSEL_2 | SHRTIM_FALTIN5_FALT1CSEL_1 | SHRTIM_FALTIN5_FALT1CSEL_0) /* No comparator */ + +/** Defining the polarity of a fault event. **/ +#define SHRTIM_FALT_POLARITY_LOW 0x00000000U /* Fault input is active low */ +#define SHRTIM_FALT_POLARITY_HIGH (SHRTIM_FALTIN1_FALT1POL) /* Fault input is active high */ + + +/** Defining the frequency used to sample the fault input (fSAMPLING) and the + length (N) of the digital filter applied. **/ +#define SHRTIM_FALT_FILTER_NONE 0x00000000U /* Filter disabled */ +#define SHRTIM_FALT_FILTER_1 (SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fSHRTIM, N=2 */ +#define SHRTIM_FALT_FILTER_2 (SHRTIM_FALTIN1_FALT1FLT_1) /* fSAMPLING= fSHRTIM, N=4 */ +#define SHRTIM_FALT_FILTER_3 (SHRTIM_FALTIN1_FALT1FLT_1 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fSHRTIM, N=8 */ +#define SHRTIM_FALT_FILTER_4 (SHRTIM_FALTIN1_FALT1FLT_2) /* fSAMPLING= fFALTS/2, N=6 */ +#define SHRTIM_FALT_FILTER_5 (SHRTIM_FALTIN1_FALT1FLT_2 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fFALTS/2, N=8 */ +#define SHRTIM_FALT_FILTER_6 (SHRTIM_FALTIN1_FALT1FLT_2 | SHRTIM_FALTIN1_FALT1FLT_1) /* fSAMPLING= fFALTS/4, N=6 */ +#define SHRTIM_FALT_FILTER_7 (SHRTIM_FALTIN1_FALT1FLT_2 | SHRTIM_FALTIN1_FALT1FLT_1 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fFALTS/4, N=8 */ +#define SHRTIM_FALT_FILTER_8 (SHRTIM_FALTIN1_FALT1FLT_3) /* fSAMPLING= fFALTS/8, N=6 */ +#define SHRTIM_FALT_FILTER_9 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fFALTS/8, N=8 */ +#define SHRTIM_FALT_FILTER_10 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_1) /* fSAMPLING= fFALTS/16, N=5 */ +#define SHRTIM_FALT_FILTER_11 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_1 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fFALTS/16, N=6 */ +#define SHRTIM_FALT_FILTER_12 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_2) /* fSAMPLING= fFALTS/16, N=8 */ +#define SHRTIM_FALT_FILTER_13 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_2 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fFALTS/32, N=5 */ +#define SHRTIM_FALT_FILTER_14 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_2 | SHRTIM_FALTIN1_FALT1FLT_1) /* fSAMPLING= fFALTS/32, N=6 */ +#define SHRTIM_FALT_FILTER_15 (SHRTIM_FALTIN1_FALT1FLT_3 | SHRTIM_FALTIN1_FALT1FLT_2 | SHRTIM_FALTIN1_FALT1FLT_1 | SHRTIM_FALTIN1_FALT1FLT_0) /* fSAMPLING= fFALTS/32, N=8 */ + + +/** Defining the division ratio between the timer clock frequency (fSHRTIM) and the fault signal sampling clock (fFALTS) used by the digital filters. **/ +#define SHRTIM_FALT_PRESCALER_DIV1 0x00000000U /* fFALTS = fSHRTIM */ +#define SHRTIM_FALT_PRESCALER_DIV2 (SHRTIM_FALTIN2_FALTSCD_0) /* fFALTS = fSHRTIM / 2 */ +#define SHRTIM_FALT_PRESCALER_DIV4 (SHRTIM_FALTIN2_FALTSCD_1) /* fFALTS = fSHRTIM / 4 */ +#define SHRTIM_FALT_PRESCALER_DIV8 (SHRTIM_FALTIN2_FALTSCD_1 | SHRTIM_FALTIN2_FALTSCD_0) /* fFALTS = fSHRTIM / 8 */ + +/** Defining the Blanking Source of a fault event. **/ +#define SHRTIM_FALT_BLANKING_RSTALIGNED 0x00000000U /* Fault blanking source is Reset-aligned */ +#define SHRTIM_FALT_BLANKING_MOVING (SHRTIM_FALTIN3_FALT1BLKS) /* Fault blanking source is Moving window */ + +#define SHRTIM_SYSTEM_FAULT_SHRPLLLOCKFAULT SHRTIM_FALTIN2_SFALTSPLLEN /* The flash ECC double detection error as SHRTIM system fault input enable */ +#define SHRTIM_SYSTEM_FAULT_PVD SHRTIM_FALTIN2_SFALTPVDEN /* The PVD error as SHRTIM system fault input enable */ +#define SHRTIM_SYSTEM_FAULT_LOCKUP SHRTIM_FALTIN2_SFALTLOCKUPEN /* The core lockup as SHRTIM system fault input enable */ +#define SHRTIM_SYSTEM_FAULT_SRAMPARITY SHRTIM_FALTIN2_SFALTSMPAREN /* The sram parity error as SHRTIM system fault input enable */ +#define SHRTIM_SYSTEM_FAULT_SRAMECC SHRTIM_FALTIN2_SFALTSMECCEN /* The sram ECC error as SHRTIM system fault input enable */ +#define SHRTIM_SYSTEM_FAULT_CLOCKSECURITY SHRTIM_FALTIN2_SFALTCKSECEN /* The clock security system error as SHRTIM system fault input enable */ + +/** Defining the Counter Reset Mode of a fault event. **/ +#define SHRTIM_FALT_COUNTERRST_UNCONDITIONAL 0x00000000U /* Fault counter is reset on each reset / roll-over event */ +#define SHRTIM_FALT_COUNTERRST_CONDITIONAL (SHRTIM_FALTIN3_FALT1RSTM) /* Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting period. */ + + +/** Defining if the burst mode is entered once or if it is continuously operating. **/ +#define SHRTIM_BM_MODE_SINGLESHOT 0x00000000U /* Burst mode operates in single shot mode */ +#define SHRTIM_BM_MODE_CONTINOUS (SHRTIM_BMCTRL_BMOM) /* Burst mode operates in continuous mode */ + + +/** Defining the clock source for the burst mode counter. **/ +#define SHRTIM_BM_CLKSRC_MASTER 0x00000000U /* Master timer counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_TIMER_A (SHRTIM_BMCTRL_BMCK_0) /* Timer A counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_TIMER_B (SHRTIM_BMCTRL_BMCK_1) /* Timer B counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_TIMER_C (SHRTIM_BMCTRL_BMCK_1 | SHRTIM_BMCTRL_BMCK_0) /* Timer C counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_TIMER_D (SHRTIM_BMCTRL_BMCK_2) /* Timer D counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_TIMER_E (SHRTIM_BMCTRL_BMCK_2 | SHRTIM_BMCTRL_BMCK_0) /* Timer E counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_TIMER_F (SHRTIM_BMCTRL_BMCK_3 | SHRTIM_BMCTRL_BMCK_1 | SHRTIM_BMCTRL_BMCK_0)/* Timer F counter reset/roll-over is used as clock source for the burst mode counter */ +#define SHRTIM_BM_CLKSRC_GTIMB1_OC1 (SHRTIM_BMCTRL_BMCK_2 | SHRTIM_BMCTRL_BMCK_1) /* On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ +#define SHRTIM_BM_CLKSRC_GTIMB2_OC1 (SHRTIM_BMCTRL_BMCK_2 | SHRTIM_BMCTRL_BMCK_1 | SHRTIM_BMCTRL_BMCK_0)/* On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ +#define SHRTIM_BM_CLKSRC_GTIMB3_OC1 (SHRTIM_BMCTRL_BMCK_3) /* On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ +#define SHRTIM_BM_CLKSRC_BTIM1_TRGO (SHRTIM_BMCTRL_BMCK_3 | SHRTIM_BMCTRL_BMCK_0) /* On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock */ +#define SHRTIM_BM_CLKSRC_FSHRTIM (SHRTIM_BMCTRL_BMCK_3 | SHRTIM_BMCTRL_BMCK_1) /* Prescaled fSHRTIM clock is used as clock source for the burst mode counter */ + + +/** Defining the prescaling ratio of the fSHRTIM clock for the burst mode controller (fBRST). **/ +#define SHRTIM_BM_PRESCALER_DIV1 0x00000000U /* fBRST = 1*/ +#define SHRTIM_BM_PRESCALER_DIV2 (SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/2*/ +#define SHRTIM_BM_PRESCALER_DIV4 (SHRTIM_BMCTRL_BMPSC_1) /* fBRST = fSHRTIM/4*/ +#define SHRTIM_BM_PRESCALER_DIV8 (SHRTIM_BMCTRL_BMPSC_1 | SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/8*/ +#define SHRTIM_BM_PRESCALER_DIV16 (SHRTIM_BMCTRL_BMPSC_2) /* fBRST = fSHRTIM/16*/ +#define SHRTIM_BM_PRESCALER_DIV32 (SHRTIM_BMCTRL_BMPSC_2 | SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/32*/ +#define SHRTIM_BM_PRESCALER_DIV64 (SHRTIM_BMCTRL_BMPSC_2 | SHRTIM_BMCTRL_BMPSC_1) /* fBRST = fSHRTIM/64*/ +#define SHRTIM_BM_PRESCALER_DIV128 (SHRTIM_BMCTRL_BMPSC_2 | SHRTIM_BMCTRL_BMPSC_1 | SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/128*/ +#define SHRTIM_BM_PRESCALER_DIV256 (SHRTIM_BMCTRL_BMPSC_3) /* fBRST = fSHRTIM/256*/ +#define SHRTIM_BM_PRESCALER_DIV512 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/512*/ +#define SHRTIM_BM_PRESCALER_DIV1024 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_1) /* fBRST = fSHRTIM/1024*/ +#define SHRTIM_BM_PRESCALER_DIV2048 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_1 | SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/2048*/ +#define SHRTIM_BM_PRESCALER_DIV4096 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_2) /* fBRST = fSHRTIM/4096*/ +#define SHRTIM_BM_PRESCALER_DIV8192 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_2 | SHRTIM_BMCTRL_BMPSC_0) /* fBRST = fSHRTIM/8192*/ +#define SHRTIM_BM_PRESCALER_DIV16384 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_2 | SHRTIM_BMCTRL_BMPSC_1) /* fBRST = fSHRTIM/16384*/ +#define SHRTIM_BM_PRESCALER_DIV32768 (SHRTIM_BMCTRL_BMPSC_3 | SHRTIM_BMCTRL_BMPSC_2 | SHRTIM_BMCTRL_BMPSC_1 | SHRTIM_BMCTRL_BMPSC_0)/* fBRST = fSHRTIM/32768*/ + + +/** Defining the events that can be used to trig the burst mode operation. **/ +#define SHRTIM_BM_TRIG_NONE 0x00000000U /* No trigger */ +#define SHRTIM_BM_TRIG_MASTER_RESET (SHRTIM_BMTG_MRSTRO) /* Master timer reset event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_MASTER_REPETITION (SHRTIM_BMTG_MREPT) /* Master timer repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_MASTER_CMP1 (SHRTIM_BMTG_MCMP1) /* Master timer compare 1 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_MASTER_CMP2 (SHRTIM_BMTG_MCMP2) /* Master timer compare 2 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_MASTER_CMP3 (SHRTIM_BMTG_MCMP3) /* Master timer compare 3 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_MASTER_CMP4 (SHRTIM_BMTG_MCMP4) /* Master timer compare 4 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMA_RESET (SHRTIM_BMTG_TARSTRO) /* Timer A reset event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMA_REPETITION (SHRTIM_BMTG_TAREPT) /* Timer A repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMA_CMP1 (SHRTIM_BMTG_TACMP1) /* Timer A compare 1 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMA_CMP2 (SHRTIM_BMTG_TACMP2) /* Timer A compare 2 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMB_RESET (SHRTIM_BMTG_TBRSTRO) /* Timer B reset event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMB_REPETITION (SHRTIM_BMTG_TBREPT) /* Timer B repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMB_CMP1 (SHRTIM_BMTG_TBCMP1) /* Timer B compare 1 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMB_CMP2 (SHRTIM_BMTG_TBCMP2) /* Timer B compare 2 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMC_RESET (SHRTIM_BMTG_TCRSTRO) /* Timer C resetevent is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMC_REPETITION (SHRTIM_BMTG_TCREPT) /* Timer C repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMC_CMP1 (SHRTIM_BMTG_TCCMP1) /* Timer C compare 1 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMD_RESET (SHRTIM_BMTG_TDRSTRO) /* Timer D reset event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMD_REPETITION (SHRTIM_BMTG_TDREPT) /* Timer D repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMD_CMP2 (SHRTIM_BMTG_TDCMP2) /* Timer D compare 2 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIME_REPETITION (SHRTIM_BMTG_TEREPT) /* Timer E repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIME_CMP1 (SHRTIM_BMTG_TECMP1) /* Timer E compare 1 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIME_CMP2 (SHRTIM_BMTG_TECMP2) /* Timer E compare 2 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMF_RESET (SHRTIM_BMTG_TFRSTRO) /* Timer F reset event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMF_REPETITION (SHRTIM_BMTG_TFREPT) /* Timer F repetition event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMF_CMP1 (SHRTIM_BMTG_TFCMP1) /* Timer F compare 1 event is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMA_EVENT7 (SHRTIM_BMTG_TAPRDEXEV7) /* Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_TIMD_EVENT8 (SHRTIM_BMTG_TDPRDEXEV8) /* Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_EVENT_7 (SHRTIM_BMTG_EXEV7) /* External event 7 conditioned by TIMA filters is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_EVENT_8 (SHRTIM_BMTG_EXEV8) /* External event 8 conditioned by TIMD filters is starting the burst mode operation */ +#define SHRTIM_BM_TRIG_EVENT_ONCHIP (SHRTIM_BMTG_OCEV) /* A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */ + + +/** Defining the operating state of the burst mode controller. **/ +#define SHRTIM_BM_STATUS_NORMAL 0x00000000U /* Normal operation */ +#define SHRTIM_BM_STATUS_BURST_ONGOING SHRTIM_BMCTRL_BMSTS /* Burst operation on-going */ + + +/** Defining the Counter Up Down Mode. **/ +#define SHRTIM_COUNTING_MODE_UP 0x00000000U /* counter is operating in up-counting mode */ +#define SHRTIM_COUNTING_MODE_UP_DOWN SHRTIM_TXCTRL2_UPDOWNM /* counter is operating in up-down counting mode */ + + +/** Defining the Roll-Over counter Mode. **/ +#define SHRTIM_ROLLOVER_MODE_PER 2U /* Event generated when counter reaches period value ('crest' mode) */ +#define SHRTIM_ROLLOVER_MODE_RST 1U /* Event generated when counter equals 0 ('valley' mode) */ +#define SHRTIM_ROLLOVER_MODE_BOTH 0U /* Event generated when counter reach both conditions (0 or SHRTIM_PERxR value) */ + + +/** Ddefining how the timer counter operates. **/ +#define SHRTIM_TRIGHALF_DISABLED 0x00000000U /* Timer Compare 2 register is behaving in standard mode */ +#define SHRTIM_TRIGHALF_ENABLED SHRTIM_TXCTRL2_TRGHLF /* Timer Compare 2 register is behaving in triggered-half mode */ + + +/** Defining the greater than compare 1 or 3 PWM Mode. **/ +#define SHRTIM_GTCMP1_EQUAL 0x00000000U /* event is generated when counter is equal to compare value */ +#define SHRTIM_GTCMP1_GREATER SHRTIM_TXCTRL2_GTCMP1 /* event is generated when counter is greater than compare value */ +#define SHRTIM_GTCMP3_EQUAL 0x00000000U /* event is generated when counter is equal to compare value */ +#define SHRTIM_GTCMP3_GREATER SHRTIM_TXCTRL2_GTCMP3 /* event is generated when counter is greater than compare value */ + + +/** Enabling the Dual DAC Reset trigger mechanism. **/ +#define SHRTIM_DUDACEN_DISABLED 0x00000000U /* Dual DAC trigger is generated on counter reset or roll-over event */ +#define SHRTIM_DUDACEN_ENABLED SHRTIM_TXCTRL2_DUDACEN /* Dual DAC trigger is generated on output 1 set event */ + + +/** Defining the Dual DAC Reset trigger. **/ +#define SHRTIM_DUDACRST_COUNTER 0x00000000U /* Dual DAC trigger is generated on counter reset or roll-over event */ +#define SHRTIM_DUDACRST_OUT1SET SHRTIM_TXCTRL2_DUDACRST /* Dual DAC trigger is generated on output 1 set event */ + + +/** Defining the Dual DAC Step trigger. **/ +#define SHRTIM_DUDACSTEP_CMP2 0x00000000U /* trigger is generated on compare 2 event */ +#define SHRTIM_DUDACSTEP_OUT1RST SHRTIM_TXCTRL2_DUDACSTEP /* trigger is generated on output 1 reset event */ + +#define SHRTIM_AUXOUTPUT_DEFAULT 0x00000000U /* Default Auxiliary output follows main outpput */ +#define SHRTIM_AUXOUTPUT_FOLLOW_CROSSBAR SHRTIM_EXTEND_AUXBYPA_1 /* Auxiliary output follows cross bar */ +#define SHRTIM_AUXOUTPUT_FOLLOW_MAINOUTPUT (SHRTIM_EXTEND_AUXBYPA_1 | SHRTIM_EXTEND_AUXBYPA_0)/* Auxiliary output follows main output */ +#define SHRITM_AUXOUTPUT_BYPASS SHRTIM_EXTEND_AUXBYPA /* Auxiliary output bypass */ + +/** Defining the some bit position **/ +#define SHRTIM_MCTRL_MCNTEN_Pos (16U) +#define SHRTIM_MCTRL_TACNTEN_Pos (17U) +#define SHRTIM_CTRL2_MSWCNTRST_Pos (8U) +#define SHRTIM_CTRL2_SWAPA_Pos (16U) +#define SHRTIM_TXCPT1_UDSTS1_Pos (16U) +#define SHRTIM_TXCPT2_UDSTS2_Pos (16U) +#define SHRTIM_TXCTRL2_ROM_Pos (6U) +#define SHRTIM_TXCTRL2_FEROM_Pos (14U) +#define SHRTIM_TXCTRL2_BMROM_Pos (12U) +#define SHRTIM_TXCTRL2_ADCROM_Pos (10U) +#define SHRTIM_TXCTRL2_OUTROM_Pos (8U) +#define SHRTIM_TXCTRL2_UPDOWNM_Pos (4U) +#define SHRTIM_TXEXEVFLT3_EXEVCNT_Pos (8U) +#define SHRTIM_TXEXEVFLT3_EXEVSEL_Pos (4U) +#define SHRTIM_TXDT_DTF_Pos (16U) +#define SHRTIM_TXINTSTS_O1DIPSTS_Pos (18U) +#define SHRTIM_TXINTSTS_O1BCKUP_Pos (20U) + + +/** +*\*\brief Write a value in SHRTIM register +*\*\param __INSTANCE__ SHRTIM Instance +*\*\param __REG__ Register to be written +*\*\param __VALUE__ Value to be written in the register +*\*\retval None + */ +#define SHRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** +*\*\brief Read a value in SHRTIM register +*\*\param __INSTANCE__ SHRTIM Instance +*\*\param __REG__ Register to be read +*\*\retval Register value + */ +#define SHRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/**** Function declaration start ***/ +void SHRTIM_SetSyncInSrc(SHRTIM_Module *SHRTIMx, uint32_t SyncInSrc); +uint32_t SHRTIM_GetSyncInSrc(SHRTIM_Module *SHRTIMx); +void SHRTIM_ConfigSyncOut(SHRTIM_Module *SHRTIMx, uint32_t Config, uint32_t Src); +void SHRTIM_SetSyncOutConfig(SHRTIM_Module *SHRTIMx, uint32_t SyncOutConfig); +uint32_t SHRTIM_GetSyncOutConfig(SHRTIM_Module *SHRTIMx); +void SHRTIM_SetSyncOutSrc(SHRTIM_Module *SHRTIMx, uint32_t SyncOutSrc); +uint32_t SHRTIM_GetSyncOutSrc(SHRTIM_Module *SHRTIMx); +void SHRTIM_SuspendUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timers); +void SHRTIM_ResumeUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timers); +void SHRTIM_ForceUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timers); +void SHRTIM_CounterReset(SHRTIM_Module *SHRTIMx, uint32_t Timers); +void SHRTIM_EnableSwapOutputs(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableSwapOutputs(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledSwapOutputs(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableOutput(SHRTIM_Module *SHRTIMx, uint32_t Outputs); +void SHRTIM_DisableOutput(SHRTIM_Module *SHRTIMx, uint32_t Outputs); +uint32_t SHRTIM_IsEnabledOutput(SHRTIM_Module *SHRTIMx, uint32_t Output); +uint32_t SHRTIM_IsDisabledOutput(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_ConfigADCTrig(SHRTIM_Module *SHRTIMx, uint32_t ADCTrigSrcReg, uint32_t ADCTrig, uint32_t Update, uint32_t Src); +void SHRTIM_SetADCTrigUpdate(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig, uint32_t Update); +uint32_t SHRTIM_GetADCTrigUpdate(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig); +void SHRTIM_SetADCTrigSrc(SHRTIM_Module *SHRTIMx, uint32_t ADCTrigSrcReg, uint32_t Src); +uint32_t SHRTIM_GetADCTrigSrc(SHRTIM_Module *SHRTIMx, uint32_t ADCTrigSrcReg); +void SHRTIM_SetADCPostScaler(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig, uint32_t PostScaler); +uint32_t SHRTIM_GetADCPostScaler(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig); +void SHRTIM_TIM_CounterEnable(SHRTIM_Module *SHRTIMx, uint32_t Timers); +void SHRTIM_TIM_CounterDisable(SHRTIM_Module *SHRTIMx, uint32_t Timers); +uint32_t SHRTIM_TIM_IsCounterEnabled(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Prescaler); +uint32_t SHRTIM_TIM_GetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCounterMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetCounterMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableResyncUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableResyncUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledResyncUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetInterleavedMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetInterleavedMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableStartOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableStartOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledStartOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableResetOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableResetOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledResetOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetDACTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t DACTrig); +uint32_t SHRTIM_TIM_GetDACTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnablePreload(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisablePreload(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledPreload(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetUpdateTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t UpdateTrig); +uint32_t SHRTIM_TIM_GetUpdateTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetUpdateGating(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t UpdateGating); +uint32_t SHRTIM_TIM_GetUpdateGating(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnablePushPullMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisablePushPullMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledPushPullMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCompareMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareUnit, + uint32_t Mode); +uint32_t SHRTIM_TIM_GetCompareMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareUnit); +void SHRTIM_TIM_SetCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Counter); +uint32_t SHRTIM_TIM_GetCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetPeriod(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Period); +uint32_t SHRTIM_TIM_GetPeriod(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetRepetition(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Repetition); +uint32_t SHRTIM_TIM_GetRepetition(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCompare1(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue); +uint32_t SHRTIM_TIM_GetCompare1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCompare2(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue); +uint32_t SHRTIM_TIM_GetCompare2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCompare3(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue); +uint32_t SHRTIM_TIM_GetCompare3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCompare4(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue); +uint32_t SHRTIM_TIM_GetCompare4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCompare5(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue); +uint32_t SHRTIM_TIM_GetCompare5(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetResetTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t ResetTrig); +uint32_t SHRTIM_TIM_GetResetTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_GetCapture1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_GetCapture1Direction(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_GetCapture2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_GetCapture2Direction(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCaptureTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CaptureUnit, + uint64_t CaptureTrig); +uint64_t SHRTIM_TIM_GetCaptureTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CaptureUnit); +void SHRTIM_TIM_EnableDeadTime(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableDeadTime(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledDeadTime(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetDPMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t DPMode); +uint32_t SHRTIM_TIM_GetDPMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableDP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableDP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledDP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableBIAR(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableBIAR(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledBIAR(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableSoftDP(SHRTIM_Module *SHRTIMx, uint32_t SoftDP); +uint32_t SHRTIM_TIM_IsEnabledSoftDP(SHRTIM_Module *SHRTIMx, uint32_t SoftDP); +void SHRTIM_TIM_EnableFault(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Faults); +void SHRTIM_TIM_DisableFault(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Faults); +uint32_t SHRTIM_TIM_IsEnabledFault(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Fault); +void SHRTIM_TIM_LockFault(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetBurstModeOption(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t BurtsModeOption); +uint32_t SHRTIM_TIM_GetBurstModeOption(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_ConfigBurstDMA(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Registers); +uint32_t SHRTIM_TIM_GetCurrentPushPullStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_GetIdlePushPullStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableEventWindowSelection(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisbleEventWindowSelection(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetEventFilter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter); +uint32_t SHRTIM_TIM_GetEventFilter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event); +void SHRTIM_TIM_SetEventLatchStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event, + uint32_t LatchStatus); +uint32_t SHRTIM_TIM_GetEventLatchStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event); +void SHRTIM_TIM_SetTriggeredHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetTriggeredHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetComp1Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetComp1Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetComp3Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetComp3Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetFaultEventRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetFaultEventRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetBMRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetBMRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetADCRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetADCRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetOutputRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetOutputRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetCountingMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetCountingMode(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetDualDacResetTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetDualDacResetTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetDualDacStepTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode); +uint32_t SHRTIM_TIM_GetDualDacStepTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_EnableDualDacTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_DisableDualDacTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_TIM_IsEnabledDualDacTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_TIM_SetEventCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter, + uint32_t Threshold); +uint32_t SHRTIM_TIM_GetEventCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter); +void SHRTIM_TIM_SetEventCounterSource(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter, + uint32_t Event); +uint32_t SHRTIM_TIM_GetEventCounterSource(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter); +void SHRTIM_TIM_SetEventCounterResetMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter, + uint32_t Mode); +uint32_t SHRTIM_TIM_GetEventCounterResetMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter); +void SHRTIM_TIM_ResetEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter); +void SHRTIM_TIM_EnableEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter); +void SHRTIM_TIM_DisableEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter); +uint32_t SHRTIM_TIM_IsEnabledEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter); +void SHRTIM_DT_Config(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Configuration); +void SHRTIM_DT_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Prescaler); +uint32_t SHRTIM_DT_GetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_SetRisingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t RisingValue); +uint32_t SHRTIM_DT_GetRisingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_SetRisingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t RisingSign); +uint32_t SHRTIM_DT_GetRisingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_SetFallingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t FallingValue); +uint32_t SHRTIM_DT_GetFallingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_SetFallingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t FallingSign); +uint32_t SHRTIM_DT_GetFallingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_LockRising(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_LockRisingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_LockFalling(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DT_LockFallingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_CHP_Config(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Configuration); +void SHRTIM_CHP_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Prescaler); +uint32_t SHRTIM_CHP_GetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_CHP_SetDutyCycle(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t DutyCycle); +uint32_t SHRTIM_CHP_GetDutyCycle(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_CHP_SetPulseWidth(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t PulseWidth); +uint32_t SHRTIM_CHP_GetPulseWidth(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_OUT_SetOutputSetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t SetSrc); +uint32_t SHRTIM_OUT_GetOutputSetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_SetOutputResetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t ResetSrc); +uint32_t SHRTIM_OUT_GetOutputResetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_Config(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t Configuration); +void SHRTIM_OUT_SetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t Polarity); +uint32_t SHRTIM_OUT_GetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_SetIdleLevel(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t IdleLevel); +uint32_t SHRTIM_OUT_GetIdleLevel(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_SetFaultState(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t FaultState); +uint32_t SHRTIM_OUT_GetFaultState(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_SetChopperMode(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t ChopperMode); +uint32_t SHRTIM_OUT_GetChopperMode(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_SetBMEntryMode(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t BMEntryMode); +uint32_t SHRTIM_OUT_GetBMEntryMode(SHRTIM_Module *SHRTIMx, uint32_t Output); +uint32_t SHRTIM_OUT_GetDPOutStatus(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_OUT_ForceLevel(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t OutputLevel); +uint32_t SHRTIM_OUT_GetLevel(SHRTIM_Module *SHRTIMx, uint32_t Output); +void SHRTIM_EXEV_Config(SHRTIM_Module *SHRTIMx, uint32_t Event, + uint32_t Src, uint32_t SrcCompSel, uint32_t Polarity, + uint32_t Sensitivity, uint32_t FastMode, uint32_t Filter, uint32_t Prescaler); +void SHRTIM_EXEV_SetSrc(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Src); +uint32_t SHRTIM_EXEV_GetSrc(SHRTIM_Module *SHRTIMx, uint32_t Event); +void SHRTIM_EXEV_SetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t SrcCompSel); +uint32_t SHRTIM_EXEV_GetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Event); +void SHRTIM_EXEV_SetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Polarity); +uint32_t SHRTIM_EXEV_GetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Event); +void SHRTIM_EXEV_SetSensitivity(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Sensitivity); +uint32_t SHRTIM_EXEV_GetSensitivity(SHRTIM_Module *SHRTIMx, uint32_t Event); +void SHRTIM_EXEV_SetFastMode(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t FastMode); +uint32_t SHRTIM_EXEV_GetFastMode(SHRTIM_Module *SHRTIMx, uint32_t Event); +void SHRTIM_EXEV_SetFilter(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Filter); +uint32_t SHRTIM_EXEV_GetFilter(SHRTIM_Module *SHRTIMx, uint32_t Event); +void SHRTIM_EXEV_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Prescaler); +uint32_t SHRTIM_EXEV_GetPrescaler(SHRTIM_Module *SHRTIMx); +void SHRTIM_FALT_Config(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Configuration, uint32_t SrcCompSel); +void SHRTIM_FALT_SetSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Src); +uint32_t SHRTIM_FALT_GetSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t SrcCompSel); +uint32_t SHRTIM_FALT_GetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Polarity); +uint32_t SHRTIM_FALT_GetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetFilter(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Filter); +uint32_t SHRTIM_FALT_GetFilter(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Prescaler); +uint32_t SHRTIM_FALT_GetPrescaler(SHRTIM_Module *SHRTIMx); +void SHRTIM_FALT_Lock(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_Enable(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_Disable(SHRTIM_Module *SHRTIMx, uint32_t Fault); +uint32_t SHRTIM_FALT_IsEnabled(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_EnableSysFault(SHRTIM_Module *SHRTIMx, uint32_t SysFault); +uint32_t SHRTIM_FALT_IsEnabledSysFault(SHRTIM_Module *SHRTIMx, uint32_t SysFault); +void SHRTIM_FALT_EnableBlanking(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_DisableBlanking(SHRTIM_Module *SHRTIMx, uint32_t Fault); +uint32_t SHRTIM_FALT_IsEnabledBlanking(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetBlankingSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Source); +uint32_t SHRTIM_FALT_GetBlankingSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Threshold); +uint32_t SHRTIM_FALT_GetCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_EnableSoftFault(SHRTIM_Module *SHRTIMx, uint32_t Fault); +uint32_t SHRTIM_FALT_IsEnabledSoftFault(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_SetResetMode(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Mode); +uint32_t SHRTIM_FALT_GetResetMode(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_FALT_ResetCounter(SHRTIM_Module *SHRTIMx, uint32_t Fault); +void SHRTIM_BM_Config(SHRTIM_Module *SHRTIMx, uint32_t Configuration); +void SHRTIM_BM_SetMode(SHRTIM_Module *SHRTIMx, uint32_t Mode); +uint32_t SHRTIM_BM_GetMode(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_SetClockSrc(SHRTIM_Module *SHRTIMx, uint32_t ClockSrc); +uint32_t SHRTIM_BM_GetClockSrc(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Prescaler); +uint32_t SHRTIM_BM_GetPrescaler(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_EnablePreload(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_DisablePreload(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_BM_IsEnabledPreload(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_SetTrig(SHRTIM_Module *SHRTIMx, uint32_t Trig); +uint32_t SHRTIM_BM_GetTrig(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_SetCompare(SHRTIM_Module *SHRTIMx, uint32_t CompareValue); +uint32_t SHRTIM_BM_GetCompare(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_SetPeriod(SHRTIM_Module *SHRTIMx, uint32_t Period); +uint32_t SHRTIM_BM_GetPeriod(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_Enable(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_Disable(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_BM_IsEnabled(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_Start(SHRTIM_Module *SHRTIMx); +void SHRTIM_BM_Stop(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_BM_GetStatus(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_FALT1(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_FALT1(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_FALT2(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_FALT2(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_FALT3(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_FALT3(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_FALT4(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_FALT4(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_FALT5(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_FALT5(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_FALT6(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_FALT6(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_SYSFALT(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_SYSFALT(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_BMPRD(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_BMPRD(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_SYNC(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsActiveFlag_SYNC(SHRTIM_Module *SHRTIMx); +void SHRTIM_ClearFlag_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CMP5(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CMP5(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_ClearFlag_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsActiveFlag_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_FALT1(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_FALT1(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_FALT1(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_FALT2(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_FALT2(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_FALT2(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_FALT3(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_FALT3(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_FALT3(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_FALT4(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_FALT4(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_FALT4(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_FALT5(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_FALT5(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_FALT5(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_FALT6(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_FALT6(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_FALT6(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_SYSFALT(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_SYSFALT(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_SYSFALT(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_BMPRD(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_BMPRD(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_BMPRD(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_SYNC(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableIT_SYNC(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledIT_SYNC(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableIT_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableIT_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableIT_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledIT_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_SYNC(SHRTIM_Module *SHRTIMx); +void SHRTIM_DisableDMAReq_SYNC(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledDMAReq_SYNC(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableDMAReq_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_EnableDMAReq_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDMAReq_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDMAReq_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDebugHaltAllTimers(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableDebugHaltAllTimers(SHRTIM_Module *SHRTIMx); +uint32_t SHRTIM_IsEnabledDebugHaltAllTimers(SHRTIM_Module *SHRTIMx); +void SHRTIM_EnableDebugHaltTimer(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_DisableDebugHaltTimer(SHRTIM_Module *SHRTIMx, uint32_t Timer); +uint32_t SHRTIM_IsEnabledDebugHaltTimer(SHRTIM_Module *SHRTIMx, uint32_t Timer); +void SHRTIM_SetAuxliaryBypass(SHRTIM_Module *SHRTIMx, uint32_t AuxBypa); +uint32_t SHRTIM_GetAuxliaryBypass(SHRTIM_Module *SHRTIMx); +/**** Function declaration end ***/ + +#ifdef __cplusplus +} +#endif + +#endif /* N32H76X_78X_SHRTIM_H */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_smu.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_smu.h new file mode 100644 index 0000000000..515b575421 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_smu.h @@ -0,0 +1,93 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_smu.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_SMU_H__ +#define __N32H76X_78X_SMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** n32h76x_78x_StdPeriph_Driver **/ + +/** SMU_Exported_Constants **/ + +/** USART Macro Definition Start **/ +#define FLASH_SUCCESS 0 +#define FLASH_FAILED 1 + +#define SMU_SUCCESS 0x1000 +#define SMU_ERR 0x101B + +#define GET_M4ADDR (0x1ff00601) +#define SET_M4ADDR (0x1ff00631) +#define GET_M7ADDR (0x1ff005c1) +#define SET_M7ADDR (0x1ff00501) +#define WR_FLASH (0x1fff7b81) +#define ER_FLASH (0x1fff7c81) + +uint32_t SMU_GetM4BootAddr( void ); +uint32_t SMU_SetM4BootAddr( uint32_t addr ); +uint32_t SMU_GetM7BootAddr( void ); +uint32_t SMU_SetM7BootAddr( uint32_t addr ); +uint32_t SMU_EraseFlash(uint32_t StrAddr); +uint32_t SMU_WriteFlash(uint32_t StrAddr, uint8_t *SrcBuf, uint32_t Len); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_SMU_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_spi.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_spi.h new file mode 100644 index 0000000000..480cf442f4 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_spi.h @@ -0,0 +1,359 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_spi.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __n32h76x_78x_SPI_H__ +#define __n32h76x_78x_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + + +/** SPI Init structure definition */ + +typedef struct +{ + uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SpiMode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t DataLen; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t CLKPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */ +} SPI_InitType; + +/** SPI_Exported_Constants **/ + +#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3) || \ + ((PERIPH) == SPI4) || \ + ((PERIPH) == SPI5) || \ + ((PERIPH) == SPI6) || \ + ((PERIPH) == SPI7)) + +#define IS_SPI_2OR3_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3)) + +/** SPI_data_direction **/ +#define SPI_DIR_MASK ((uint16_t)0x1FFFU) +#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000U) +#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x2000U) +#define SPI_DIR_DOUBLELINE_TONLY ((uint16_t)0x4000U) +#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000U) +#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000U) +#define IS_SPI_DIR_MODE(MODE) \ + (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \ + ((MODE) == SPI_DIR_DOUBLELINE_TONLY) || ((MODE) == SPI_DIR_SINGLELINE_RX) \ + || ((MODE) == SPI_DIR_SINGLELINE_TX)) + +/** SPI_mode **/ + +#define SPI_MODE_MASTER ((uint16_t)0x0840U) +#define SPI_MODE_SLAVE ((uint16_t)0x0000U) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE)) + + +/** SPI_data_size **/ + +#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0100U) +#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000U) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS)) + + +/** SPI_Clock_Polarity **/ + +#define SPI_CLKPOL_LOW ((uint16_t)0x0000U) +#define SPI_CLKPOL_HIGH ((uint16_t)0x0010U) +#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH)) + + +/** SPI_Clock_Phase **/ + +#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000U) +#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0020U) +#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE)) + +/** SPI_Slave_Select_management **/ + +#define SPI_NSS_SOFT ((uint16_t)0x1000U) +#define SPI_NSS_HARD ((uint16_t)0x0000U) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD)) + + +/** SPI_BaudRate_Prescaler **/ + +#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000U) +#define SPI_BR_PRESCALER_4 ((uint16_t)0x0001U) +#define SPI_BR_PRESCALER_8 ((uint16_t)0x0002U) +#define SPI_BR_PRESCALER_16 ((uint16_t)0x0003U) +#define SPI_BR_PRESCALER_32 ((uint16_t)0x0004U) +#define SPI_BR_PRESCALER_64 ((uint16_t)0x0005U) +#define SPI_BR_PRESCALER_128 ((uint16_t)0x0006U) +#define SPI_BR_PRESCALER_256 ((uint16_t)0x0007U) +#define IS_SPI_BR_PRESCALER(PRESCALER) \ + (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) \ + || ((PRESCALER) == SPI_BR_PRESCALER_8) || ((PRESCALER) == SPI_BR_PRESCALER_16) \ + || ((PRESCALER) == SPI_BR_PRESCALER_32) || ((PRESCALER) == SPI_BR_PRESCALER_64) \ + || ((PRESCALER) == SPI_BR_PRESCALER_128) || ((PRESCALER) == SPI_BR_PRESCALER_256)) \ + +/** SPI_MSB_LSB_transmission **/ + +#define SPI_FB_MSB ((uint16_t)0x0000U) +#define SPI_FB_LSB ((uint16_t)0x0080U) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB)) + + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE ((uint16_t)0x0000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CTRL2_CRCEN +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +/** SPI_I2S_DMA_transfer_requests **/ +#define SPI_I2S_DMA_TX ((uint16_t)0x0004U) +#define SPI_I2S_DMA_RX ((uint16_t)0x0002U) +#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFCU) == 0x00) && ((DMAREQ) != 0x00)) + + +/** SPI_NSS_internal_software_management **/ + +#define SPI_NSS_HIGH ((uint16_t)0x0800U) +#define SPI_NSS_LOW ((uint16_t)0x0000U) +#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW)) + + +/** SPI_CRC_Transmit_Receive **/ + +#define SPI_CRC_TX ((uint8_t)0x00U) +#define SPI_CRC_RX ((uint8_t)0x01U) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX)) + + +/** SPI_direction_transmit_receive **/ + +#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFFU) +#define SPI_BIDIRECTION_TX ((uint16_t)0x4000U) +#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX)) + + +/** SPI_I2S_interrupts_definition **/ + +#define SPI_I2S_INT_TE ((uint8_t)0x40) +#define SPI_I2S_INT_RNE ((uint8_t)0x51) +#define SPI_I2S_INT_ERR ((uint8_t)0x60) +#define SPI_I2S_INT_RXONLYC ((uint8_t)0xEC) +#define SPI_I2S_INT_RXFIFOF ((uint8_t)0xCB) +#define SPI_I2S_INT_RXFIFOHF ((uint8_t)0xB9) +#define SPI_I2S_INT_TXFIFOHE ((uint8_t)0xA8) +#define SPI_I2S_INT_MODERR ((uint8_t)0x64) +#define SPI_I2S_INT_CRCERR ((uint8_t)0x63) +#define SPI_I2S_INT_OVERERR ((uint8_t)0x65) +#define SPI_I2S_INT_UNDER ((uint8_t)0x66) +#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || \ + ((IT) == SPI_I2S_INT_RXFIFOF) || ((IT) == SPI_I2S_INT_RXFIFOHF)|| \ + ((IT) == SPI_I2S_INT_TXFIFOHE)|| ((IT) == SPI_I2S_INT_RXONLYC) || \ + ((IT) == SPI_I2S_INT_ERR)) + + +#define IS_SPI_I2S_GET_INT(IT) (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || \ + ((IT) == I2S_I2S_INT_UNDER) || ((IT) == SPI_I2S_INT_CRCERR) || \ + ((IT) == SPI_I2S_INT_MODERR) || ((IT) == SPI_I2S_INT_OVERERR)) + +/** SPI_I2S_flags_definition **/ +#define SPI_I2S_TE_FLAG ((uint16_t)0x0001U) +#define SPI_I2S_RNE_FLAG ((uint16_t)0x0002U) +#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0004U) +#define SPI_CRCERR_FLAG ((uint16_t)0x0008U) +#define SPI_MODERR_FLAG ((uint16_t)0x0010U) +#define SPI_I2S_OVER_FLAG ((uint16_t)0x0020U) +#define I2S_UNDER_FLAG ((uint16_t)0x0040U) +#define I2S_CHSIDE_FLAG ((uint16_t)0x0080U) +#define SPI_I2S_TXFIFOHE_FLAG ((uint16_t)0x0100U) +#define SPI_I2S_RXFIFOHF_FLAG ((uint16_t)0x0200U) +#define SPI_I2S_TXFIFOE_FLAG ((uint16_t)0x0400U) +#define SPI_I2S_RXFIFOF_FLAG ((uint16_t)0x0800U) +#define SPI_I2S_RXONLYC_FLAG ((uint16_t)0x1000U) + +#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG)) +#define IS_SPI_I2S_GET_FLAG(FLAG) ( \ + ((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || \ + ((FLAG) == SPI_MODERR_FLAG) || ((FLAG) == SPI_CRCERR_FLAG) || \ + ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) || \ + ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG) || \ + ((FLAG) == SPI_I2S_RXONLYC_FLAG ) || ((FLAG) == SPI_I2S_RXFIFOF_FLAG) || \ + ((FLAG) == SPI_I2S_TXFIFOE_FLAG) || ((FLAG) == SPI_I2S_RXFIFOHF_FLAG) || \ + ((FLAG) == SPI_I2S_TXFIFOHE_FLAG)) + +/** SPI_I2S_FIFO_Ctrl_definition **/ + +#define SPI_I2S_FIFO_CLR ((uint16_t)0x0200U) +#define SPI_I2S_FIFO_Enable ((uint16_t)0x0100U) +#define SPI_I2S_FIFO_Disable ((uint16_t)0xFEFFU) +#define IS_SPI_I2S_FIFO_CTRL(CTRL) (((CTRL) == SPI_I2S_FIFO_CLR) || ((CTRL) == SPI_I2S_FIFO_Enable) || \ + ((CTRL) == SPI_I2S_FIFO_Disable)) + +/** SPI_RX_FIFO_Level **/ + +#define SPI_RX_FIF0NUM_7 ((uint16_t)0x0070U) +#define SPI_RX_FIF0NUM_6 ((uint16_t)0x0060U) +#define SPI_RX_FIF0NUM_5 ((uint16_t)0x0050U) +#define SPI_RX_FIF0NUM_4 ((uint16_t)0x0040U) +#define SPI_RX_FIF0NUM_3 ((uint16_t)0x0030U) +#define SPI_RX_FIF0NUM_2 ((uint16_t)0x0020U) +#define SPI_RX_FIF0NUM_1 ((uint16_t)0x0010U) +#define SPI_RX_FIF0NUM_0 ((uint16_t)0x0000U) +#define IS_SPI_RX_FIFO_NUM(NUM) (((NSS) == SPI_RX_FIF0NUM_0) || \ + ((NSS) == SPI_RX_FIF0NUM_1) || \ + ((NSS) == SPI_RX_FIF0NUM_2) || \ + ((NSS) == SPI_RX_FIF0NUM_3) || \ + ((NSS) == SPI_RX_FIF0NUM_4) || \ + ((NSS) == SPI_RX_FIF0NUM_5) || \ + ((NSS) == SPI_RX_FIF0NUM_6) || \ + ((NSS) == SPI_RX_FIF0NUM_7)) + +/** SPI_TX_FIFO_Level **/ + +#define SPI_TX_FIF0NUM_7 ((uint16_t)0x0007U) +#define SPI_TX_FIF0NUM_6 ((uint16_t)0x0006U) +#define SPI_TX_FIF0NUM_5 ((uint16_t)0x0005U) +#define SPI_TX_FIF0NUM_4 ((uint16_t)0x0004U) +#define SPI_TX_FIF0NUM_3 ((uint16_t)0x0003U) +#define SPI_TX_FIF0NUM_2 ((uint16_t)0x0002U) +#define SPI_TX_FIF0NUM_1 ((uint16_t)0x0001U) +#define SPI_TX_FIF0NUM_0 ((uint16_t)0x0000U) +#define IS_SPI_TX_FIFO_NUM(NUM) (((NSS) == SPI_TX_FIF0NUM_0) || \ + ((NSS) == SPI_TX_FIF0NUM_1) || \ + ((NSS) == SPI_TX_FIF0NUM_2) || \ + ((NSS) == SPI_TX_FIF0NUM_3) || \ + ((NSS) == SPI_TX_FIF0NUM_4) || \ + ((NSS) == SPI_TX_FIF0NUM_5) || \ + ((NSS) == SPI_TX_FIF0NUM_6) || \ + ((NSS) == SPI_TX_FIF0NUM_7)) + + +/** SPI_CRC_polynomial **/ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) + + +/** SPI_Exported_Functions **/ + +void SPI_I2S_DeInit(const SPI_Module* SPIx); +void SPI_Init(SPI_Module* SPIx,const SPI_InitType* SPI_InitStruct); +void SPI_InitStruct(SPI_InitType* SPI_InitStruct); +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd); +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd); +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(const SPI_Module* SPIx); +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen); +void SPI_TransmitCrcNext(SPI_Module* SPIx, FunctionalState Cmd); +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd); +uint16_t SPI_GetCRCDat(const SPI_Module* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPoly(const SPI_Module* SPIx); +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection); +FlagStatus SPI_I2S_GetStatus(const SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); +INTStatus SPI_I2S_GetIntStatus(const SPI_Module* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_FIFO_Cmd(SPI_Module* SPIx, FunctionalState NewState); +void SPI_I2S_ClearFIFOBit(SPI_Module* SPIx, uint16_t SPI_I2S_FIFO_Clear); +void SPI_RxFIFOSizeConfig(SPI_Module* SPIx, uint16_t SPI_FIFOSize); +void SPI_TxFIFOSizeConfig(SPI_Module* SPIx, uint16_t SPI_FIFOSize); +uint16_t SPI_GetFIFOLevel(SPI_Module* SPIx); +uint16_t SPI_RX_FIFO_CNT_GET(const SPI_Module* SPIx); +uint16_t SPI_TX_FIFO_CNT_GET(const SPI_Module* SPIx); +void SPI_TRANSNUM_SET(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_TRANSNUM_GET(const SPI_Module* SPIx); +void SPI_DELAYTIME_SET(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_DELAYTIME_GET(const SPI_Module* SPIx); +void SPI_RX_FIFO_SET(SPI_Module* SPIx, uint16_t Data); +uint16_t SPI_RX_FIFO_GET(const SPI_Module* SPIx); +void SPI_SetCRCPoly(SPI_Module* SPIx, uint16_t SpiCrcPoly); +void SPIModeSelect(SPI_Module* SPIx); +void SPI_SetDataDirection(SPI_Module* SPIx, uint16_t DataDirection); +#ifdef __cplusplus +} +#endif + +#endif /*__n32h76x_78x_SPI_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_tim.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_tim.h new file mode 100644 index 0000000000..3e2975c0ce --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_tim.h @@ -0,0 +1,946 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_tim.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76x_78x_TIM_H +#define __N32H76x_78x_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/*** TIM Structure Definition Start ***/ + +/** TIM Init structure definition is used with ATIM and GPTIM. **/ +typedef struct +{ + uint32_t Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint32_t CounterMode; /* Specifies the counter mode. + This parameter can be a value of TIM_Counter_Mode */ + + uint32_t Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint32_t ClkDiv; /* Specifies the clock division. + This parameter can be a value of TIM_Clock_Division_CKD */ + + uint32_t RepetCnt; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + This parameter is valid only for ATIM. */ + + uint32_t CapCh1Sel; /* Channel 1 select capture in */ + + uint32_t CapCh2Sel; /* Channel 2 select capture in */ + + uint32_t CapCh3Sel; /* Channel 3 select capture in */ + + uint32_t CapCh4Sel; /* Channel 4 select capture in */ + + uint32_t EtrOrClr; /* ETR or CLR select as ocrefclear source */ + + uint32_t CapEtrClrSel; /* ocrefclear(ETR/CLR) select capture in */ +} TIM_TimeBaseInitType; + +/** TIM Output Compare Init structure definition **/ +typedef struct +{ + uint32_t OCMode; /* Specifies the TIM mode. + This parameter can be a value of TIM_Output_Compare_and_PWM_modes */ + + uint32_t OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of TIM_Output_Compare_state */ + + uint32_t OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of TIM_Output_Compare_N_state + This parameter is valid for ATIM and GTIMB1-10. */ + + uint32_t Pulse; /* Specifies the pulse value to be loaded into the Capture_Compare_Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint32_t OCPolarity; /* Specifies the output polarity. + This parameter can be a value of TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of TIM_Output_Compare_N_Polarity + This parameter is valid for ATIM and GTIMB1-10. */ + + uint32_t OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of TIM_Output_Compare_Idle_State + This parameter is valid for ATIM and GTIMB1-10. */ + + uint32_t OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of TIM_Output_Compare_N_Idle_State + This parameter is valid for ATIM and GTIMB1-10. */ +} OCInitType; + +/** TIM Input Capture Init structure definition **/ +typedef struct +{ + + uint32_t Channel; /* Specifies the TIM channel. + This parameter can be a value of TIM_Channel */ + + uint32_t ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /* Specifies the input. + This parameter can be a value of TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitType; + +/** BDTR structure definition is used only with TIM1 **/ +typedef struct +{ + + uint32_t OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of Lock_level */ + + uint32_t DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of Break_Input_enable_disable */ + + uint32_t BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of Break_Polarity */ + + uint32_t AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of TIM_AOE_Bit_Set_Reset */ + + uint32_t Bidirection; /* Specifies whether the bidirectional break input enabled or disabled. + This parameter can be a value of Enable or disable */ + + uint32_t Break2; /* Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /* Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of Break2_Polarity */ + + uint32_t Bidirection2; /* Specifies whether the bidirectional break2 input enabled or disabled. + This parameter can be a value of Enable or disable */ + +} TIM_BDTRInitType; + +/** Filter structure definition **/ +typedef struct +{ + uint32_t ThreshHold; /* Specifies the threshold value of filter, the range is [0, 64]. */ + + uint32_t WindowSize; /* Specifies the window size value of filter, the range is [0, 63]. */ + + uint32_t Prescaler; /* Specifies the prescaler value of filter, the range is [0, 65535] */ +}TIM_FiltInitType; + +/*** TIM Structure Definition End ***/ + +/*** TIM Macro Definition Start ***/ + +/** TIM register bit mask definition **/ +#define TIM_REG_BIT_MASK ((uint32_t)0x00000000) + +/** Whether it is an ATIM1-3 device **/ +#define IS_ATIM1_4_DEVICE(DEVICE) (((DEVICE) == ATIM1) || \ + ((DEVICE) == ATIM2) || \ + ((DEVICE) == ATIM3) || \ + ((DEVICE) == ATIM4)) + +/** Whether it is an GTIMA1-7 device **/ +#define IS_GTIMA1_7_DEVICE(DEVICE) (((DEVICE) == GTIMA1) || \ + ((DEVICE) == GTIMA2) || \ + ((DEVICE) == GTIMA3) || \ + ((DEVICE) == GTIMA4) || \ + ((DEVICE) == GTIMA5) || \ + ((DEVICE) == GTIMA6) || \ + ((DEVICE) == GTIMA7)) + +/** Whether it is an GTIMB1-10 device **/ +#define IS_GTIMB1_3_DEVICE(DEVICE) (((DEVICE) == GTIMB1) || \ + ((DEVICE) == GTIMB2) || \ + ((DEVICE) == GTIMB3)) +/** Whether it is an BTIM1-2 device **/ +#define IS_BTIM1_2_DEVICE(DEVICE) (((DEVICE) == BTIM1) || \ + ((DEVICE) == BTIM2)) + +/** TIM_External_Trigger_Prescaler **/ +#define TIM_EXT_TRG_PSC_OFF (TIM_REG_BIT_MASK) +#define TIM_EXT_TRG_PSC_DIV2 (TIM_SMCTRL_EXTPS_0) +#define TIM_EXT_TRG_PSC_DIV4 (TIM_SMCTRL_EXTPS_1) +#define TIM_EXT_TRG_PSC_DIV8 (TIM_SMCTRL_EXTPS) + +/** TIM_External_Trigger_Polarity **/ +#define TIM_EXT_TRIG_POLARITY_INVERTED (TIM_SMCTRL_EXTP) +#define TIM_EXT_TRIG_POLARITY_NONINVERTED (TIM_REG_BIT_MASK) + + +/** TIM_Counter_Mode **/ +#define TIM_CNT_MODE_UP (TIM_REG_BIT_MASK) +#define TIM_CNT_MODE_DOWN (TIM_CTRL1_DIR) +#define TIM_CNT_MODE_CENTER_ALIGN1 (TIM_CTRL1_CAMSEL_0) +#define TIM_CNT_MODE_CENTER_ALIGN2 (TIM_CTRL1_CAMSEL_1) +#define TIM_CNT_MODE_CENTER_ALIGN3 (TIM_CTRL1_CAMSEL) + +/** TIM_Clock_Division_CKD **/ +#define TIM_CLK_DIV1 (TIM_REG_BIT_MASK) +#define TIM_CLK_DIV2 (TIM_CTRL1_CLKD_0) +#define TIM_CLK_DIV4 (TIM_CTRL1_CLKD_1) + +/** TIM_Prescaler_Reload_Mode **/ +#define TIM_PSC_RELOAD_MODE_UPDATE (TIM_REG_BIT_MASK) +#define TIM_PSC_RELOAD_MODE_IMMEDIATE (TIM_EVTGEN_UDGN) + +/** Channel 1/2/3/4 & OCxclr select capture in **/ +#define TIM_CAPCH1SEL_0 (TIM_REG_BIT_MASK) +#define TIM_CAPCH1SEL_1 (TIM_INSEL_TI1S_0) +#define TIM_CAPCH1SEL_2 (TIM_INSEL_TI1S_1) +#define TIM_CAPCH1SEL_3 (TIM_INSEL_TI1S_0 | TIM_INSEL_TI1S_1) +#define TIM_CAPCH1SEL_4 (TIM_INSEL_TI1S_2) +#define TIM_CAPCH1SEL_5 (TIM_INSEL_TI1S_0 | TIM_INSEL_TI1S_2) +#define TIM_CAPCH1SEL_6 (TIM_INSEL_TI1S_1 | TIM_INSEL_TI1S_2) +#define TIM_CAPCH1SEL_7 (TIM_INSEL_TI1S_0 | TIM_INSEL_TI1S_1 | TIM_INSEL_TI1S_2) + +#define TIM_CAPCH2SEL_0 (TIM_REG_BIT_MASK) +#define TIM_CAPCH2SEL_1 (TIM_INSEL_TI2S_0) +#define TIM_CAPCH2SEL_2 (TIM_INSEL_TI2S_1) +#define TIM_CAPCH2SEL_3 (TIM_INSEL_TI2S_0 | TIM_INSEL_TI2S_1) +#define TIM_CAPCH2SEL_4 (TIM_INSEL_TI2S_2) +#define TIM_CAPCH2SEL_TIMXCAPLSE (TIM_CTRL1_C2SEL) + +#define TIM_CAPCH3SEL_0 (TIM_REG_BIT_MASK) +#define TIM_CAPCH3SEL_1 (TIM_INSEL_TI3S_0) +#define TIM_CAPCH3SEL_TIMXCAPLSI (TIM_CTRL1_C3SEL) + +#define TIM_CAPCH4SEL_0 (TIM_REG_BIT_MASK) +#define TIM_CAPCH4SEL_1 (TIM_INSEL_TI4S_0) +#define TIM_CAPCH4SEL_2 (TIM_INSEL_TI4S_1) +#define TIM_CAPCH4SEL_TIMXCAPHSEDIV128 (TIM_CTRL1_C4SEL) + +#define TIM_CAPETRSEL_0 (TIM_REG_BIT_MASK) +#define TIM_CAPETRSEL_1 (TIM_INSEL_ETRS_0) +#define TIM_CAPETRSEL_2 (TIM_INSEL_ETRS_1) +#define TIM_CAPETRSEL_3 (TIM_INSEL_ETRS_0 | TIM_INSEL_ETRS_1) +#define TIM_CAPETRSEL_4 (TIM_INSEL_ETRS_2) +#define TIM_CAPETRSEL_5 (TIM_INSEL_ETRS_0 | TIM_INSEL_ETRS_2) +#define TIM_CAPETRSEL_6 (TIM_INSEL_ETRS_1 | TIM_INSEL_ETRS_2) +#define TIM_CAPETRSEL_7 (TIM_INSEL_ETRS_0 | TIM_INSEL_ETRS_1 | TIM_INSEL_ETRS_2) +#define TIM_CAPETRSEL_8 (TIM_INSEL_ETRS_3) +#define TIM_CAPETRSEL_9 (TIM_INSEL_ETRS_0 | TIM_INSEL_ETRS_3) +#define TIM_CAPETRSEL_10 (TIM_INSEL_ETRS_1 | TIM_INSEL_ETRS_3) +#define TIM_CAPETRSEL_11 (TIM_INSEL_ETRS_0 | TIM_INSEL_ETRS_1 | TIM_INSEL_ETRS_3) +#define TIM_CAPETRSEL_12 (TIM_INSEL_ETRS_2 | TIM_INSEL_ETRS_3) +#define TIM_CAPETRSEL_13 (TIM_INSEL_ETRS_0 | TIM_INSEL_ETRS_2 | TIM_INSEL_ETRS_3) + +#define TIM_OCCLRSEL_0 (TIM_REG_BIT_MASK) +#define TIM_OCCLRSEL_1 (TIM_INSEL_CLRS_0) +#define TIM_OCCLRSEL_2 (TIM_INSEL_CLRS_1) +#define TIM_OCCLRSEL_3 (TIM_INSEL_CLRS_0 | TIM_INSEL_CLRS_1) +#define TIM_OCCLRSEL_4 (TIM_INSEL_CLRS_2) +#define TIM_OCCLRSEL_5 (TIM_INSEL_CLRS_0 | TIM_INSEL_CLRS_2) +#define TIM_OCCLRSEL_6 (TIM_INSEL_CLRS_1 | TIM_INSEL_CLRS_2) +#define TIM_OCCLRSEL_7 (TIM_INSEL_CLRS_0 | TIM_INSEL_CLRS_1 | TIM_INSEL_CLRS_2) +#define TIM_OCCLRSEL_COMP (TIM_CTRL1_CLRSEL) + +/** ETR input selection **/ +#define TIM_ETRSEL (TIM_REG_BIT_MASK) +#define TIM_CLRSEL (TIM_CTRL1_CLRSEL) + +/** ITR input selection **/ +#define TIM_TRIG_SEL_IN_TR0 (TIM_REG_BIT_MASK) +#define TIM_TRIG_SEL_IN_TR1 (TIM_INSEL_ITRS_0) +#define TIM_TRIG_SEL_IN_TR2 (TIM_INSEL_ITRS_1) +#define TIM_TRIG_SEL_IN_TR3 (TIM_INSEL_ITRS_0 | TIM_INSEL_ITRS_1) +#define TIM_TRIG_SEL_IN_TR4 (TIM_INSEL_ITRS_2) +#define TIM_TRIG_SEL_IN_TR5 (TIM_INSEL_ITRS_0 | TIM_INSEL_ITRS_2) +#define TIM_TRIG_SEL_IN_TR6 (TIM_INSEL_ITRS_1 | TIM_INSEL_ITRS_2) +#define TIM_TRIG_SEL_IN_TR7 (TIM_INSEL_ITRS_0 | TIM_INSEL_ITRS_1 | TIM_INSEL_ITRS_2) +#define TIM_TRIG_SEL_IN_TR8 (TIM_INSEL_ITRS_3) +#define TIM_TRIG_SEL_IN_TR9 (TIM_INSEL_ITRS_0 | TIM_INSEL_ITRS_3) +#define TIM_TRIG_SEL_IN_TR10 (TIM_INSEL_ITRS_1 | TIM_INSEL_ITRS_3) +#define TIM_TRIG_SEL_IN_TR11 (TIM_INSEL_ITRS_0 | TIM_INSEL_ITRS_1 | TIM_INSEL_ITRS_3) +#define TIM_TRIG_SEL_IN_TR12 (TIM_INSEL_ITRS_2 | TIM_INSEL_ITRS_3) +#define TIM_TRIG_SEL_IN_TR13 (TIM_INSEL_ITRS_0 | TIM_INSEL_ITRS_2 | TIM_INSEL_ITRS_3) +#define TIM_TRIG_SEL_IN_TR14 (TIM_INSEL_ITRS_1 | TIM_INSEL_ITRS_2 | TIM_INSEL_ITRS_3) + +/** OCCLR input selection **/ +#define IS_ITR_SEL(IMPORT) (((IMPORT) == TIM_TRIG_SEL_IN_TR0) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR1) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR2) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR3) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR4) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR5) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR6) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR7) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR8) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR9) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR10) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR11) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR12) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR13) || \ + ((IMPORT) == TIM_TRIG_SEL_IN_TR14)) + +/** TIM_Trigger_Selection **/ +#define TIM_TRIG_SEL_IN_TR (TIM_SMCTRL_TSEL_0) +#define TIM_TRIG_SEL_TI1F_ED (TIM_SMCTRL_TSEL_2) +#define TIM_TRIG_SEL_TI1FP1 (TIM_SMCTRL_TSEL_0 | TIM_SMCTRL_TSEL_2) +#define TIM_TRIG_SEL_TI2FP2 (TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_2) +#define TIM_TRIG_SEL_ETRF (TIM_SMCTRL_TSEL_0 | TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_2) + +/** TIM_Output_Compare_and_PWM_modes **/ +#define TIM_OCMODE_TIMING (TIM_REG_BIT_MASK) +#define TIM_OCMODE_ACTIVE (TIM_CCMOD1_OC1MD_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMOD1_OC1MD_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_1) +#define TIM_FORCED_ACTION_INACTIVE (TIM_CCMOD1_OC1MD_2) +#define TIM_FORCED_ACTION_ACTIVE (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_2) +#define TIM_OCMODE_PWM1 (TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2) +#define TIM_OCMODE_PWM2 (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2) +#define TIM_OCMODE_OPMOD_RETRIG1 (TIM_CCMOD1_OC1MD_3) +#define TIM_OCMODE_OPMOD_RETRIG2 (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_3) +#define TIM_OCMODE_COMBI_PWM1 (TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_3) +#define TIM_OCMODE_COMBI_PWM2 (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_3) + +/** TIM_Output_Compare_state **/ +#define TIM_OUTPUT_STATE_DISABLE (TIM_REG_BIT_MASK) +#define TIM_OUTPUT_STATE_ENABLE (TIM_CCEN_CC1EN) + +/** TIM_Output_Compare_N_state **/ +#define TIM_OUTPUT_NSTATE_DISABLE (TIM_REG_BIT_MASK) +#define TIM_OUTPUT_NSTATE_ENABLE (TIM_CCEN_CC1NEN) + +/** TIM_Output_Compare_Polarity **/ +#define TIM_OC_POLARITY_HIGH (TIM_REG_BIT_MASK) +#define TIM_OC_POLARITY_LOW (TIM_CCEN_CC1P) + +/** TIM_Output_Compare_N_Polarity **/ +#define TIM_OCN_POLARITY_HIGH (TIM_REG_BIT_MASK) +#define TIM_OCN_POLARITY_LOW (TIM_CCEN_CC1NP) + +/** TIM_Output_Compare_Idle_State **/ +#define TIM_OC_IDLE_STATE_SET (TIM_CTRL2_OI1) +#define TIM_OC_IDLE_STATE_RESET (TIM_REG_BIT_MASK) + +/** TIM_Output_Compare_N_Idle_State **/ +#define TIM_OCN_IDLE_STATE_SET (TIM_CTRL2_OI1N) +#define TIM_OCN_IDLE_STATE_RESET (TIM_REG_BIT_MASK) + +/** TIM_Channel **/ +#define TIM_CH_1 ((uint32_t)0x00000000) +#define TIM_CH_2 ((uint32_t)0x00000004) +#define TIM_CH_3 ((uint32_t)0x00000008) +#define TIM_CH_4 ((uint32_t)0x0000000C) +#define TIM_CH_5 ((uint32_t)0x00000010) +#define TIM_CH_6 ((uint32_t)0x00000014) + +/** TIM_Iutput_Capture_Polarity **/ +#define TIM_IC_POLARITY_RISING (TIM_REG_BIT_MASK) +#define TIM_IC_POLARITY_FALLING (TIM_CCEN_CC1P) + +/** TIM_Input_Capture_Selection **/ +#define TIM_IC_SELECTION_DIRECTTI (TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_IC_SELECTION_INDIRECTTI (TIM_CCMOD1_CC1SEL_1) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_IC_SELECTION_TRC (TIM_CCMOD1_CC1SEL) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/** TIM_Input_Capture_Prescaler **/ +#define TIM_IC_PSC_DIV1 (TIM_REG_BIT_MASK) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_IC_PSC_DIV2 (TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 2 events. */ +#define TIM_IC_PSC_DIV4 (TIM_CCMOD1_IC1PSC_1) /* Capture performed once every 4 events. */ +#define TIM_IC_PSC_DIV8 (TIM_CCMOD1_IC1PSC) /* Capture performed once every 8 events. */ + +/** OSSR_Off_State_Selection_for_Run_mode_state **/ +#define TIM_OSSR_STATE_ENABLE (TIM_BKDT_OSSR) +#define TIM_OSSR_STATE_DISABLE (TIM_REG_BIT_MASK) + +/** OSSI_Off_State_Selection_for_Idle_mode_state **/ +#define TIM_OSSI_STATE_ENABLE (TIM_BKDT_OSSI) +#define TIM_OSSI_STATE_DISABLE (TIM_REG_BIT_MASK) + +/** Lock_level **/ +#define TIM_LOCK_LEVEL_OFF (TIM_REG_BIT_MASK) +#define TIM_LOCK_LEVEL_1 (TIM_BKDT_LCKCFG_0) +#define TIM_LOCK_LEVEL_2 (TIM_BKDT_LCKCFG_1) +#define TIM_LOCK_LEVEL_3 (TIM_BKDT_LCKCFG) + +/** Break_Input_enable_disable **/ +#define TIM_BREAK_IN_ENABLE (TIM_BKDT_BKEN) +#define TIM_BREAK_IN_DISABLE (TIM_REG_BIT_MASK) +#define TIM_BREAK2_IN_ENABLE (TIM_BKDT_BK2EN) +#define TIM_BREAK2_IN_DISABLE (TIM_REG_BIT_MASK) + +/** Break_Polarity **/ +#define TIM_BREAK_POLARITY_LOW (TIM_REG_BIT_MASK) +#define TIM_BREAK_POLARITY_HIGH (TIM_BKDT_BKP) +#define TIM_BREAK2_POLARITY_LOW (TIM_REG_BIT_MASK) +#define TIM_BREAK2_POLARITY_HIGH (TIM_BKDT_BK2P) + +/** TIM_AOEN_Bit_Set_Reset **/ +#define TIM_AUTO_OUTPUT_ENABLE (TIM_BKDT_AOEN) +#define TIM_AUTO_OUTPUT_DISABLE (TIM_REG_BIT_MASK) + +/** Bidirectional break input enabled or disabled **/ +#define TIM_BREAK_BID_ENABLE (TIM_BKDT_BRKBID) +#define TIM_BREAK_BID_DISABLE (TIM_REG_BIT_MASK) + +/** Bidirectional break2 input enabled or disabled **/ +#define TIM_BREAK2_BID_ENABLE (TIM_BKDT_BRK2BID) +#define TIM_BREAK2_BID_DISABLE (TIM_REG_BIT_MASK) + +/** Break1 input source **/ +#define TIM_BREAK_LOCKUP (TIM_CTRL1_LBKPEN) +#define TIM_BREAK_PVD (TIM_CTRL1_PBKPEN) +#define TIM_BREAK_SMPAR (TIM_CTRL1_SMPARERREN) +#define TIM_BREAK_SMECC (TIM_CTRL1_SMECCERREN) +#define TIM_BREAK_IOM (TIM_AF1_IOMBRKEN) +#define TIM_BREAK_COMP1 (TIM_AF1_COMP1BRKEN) +#define TIM_BREAK_COMP2 (TIM_AF1_COMP2BRKEN) +#define TIM_BREAK_COMP3 (TIM_AF1_COMP3BRKEN) +#define TIM_BREAK_COMP4 (TIM_AF1_COMP4BRKEN) +#define TIM_BREAK_DSMU0 (TIM_AF1_DSMU0BRKEN) +#define TIM_BREAK_DSMU1 (TIM_AF1_DSMU1BRKEN) +#define TIM_BREAK_DSMU2 (TIM_AF1_DSMU2BRKEN) +#define TIM_BREAK_DSMU3 (TIM_AF1_DSMU3BRKEN) + +/** System break input **/ +#define IS_SYS_BREAK(SOURCE) (((SOURCE) == TIM_BREAK_LOCKUP) || \ + ((SOURCE) == TIM_BREAK_PVD) || \ + ((SOURCE) == TIM_BREAK_SMPAR) || \ + ((SOURCE) == TIM_BREAK_SMECC)) + + /** Polarity of break input from IOM **/ +#define TIM_BREAK_SOURCE_POLARITY_INVERT (TIM_AF1_IOMBRKP | TIM_AF1_COMP1BRKP | TIM_AF1_COMP2BRKP | TIM_AF1_COMP3BRKP | TIM_AF1_COMP4BRKP ) +#define TIM_BREAK_SOURCE_POLARITY_NONINVERT (TIM_REG_BIT_MASK) + +/** IOM as break2 input **/ +#define TIM_BREAK2_IOM (TIM_AF2_IOMBRK2EN) +#define TIM_BREAK2_COMP1 (TIM_AF2_COMP1BRK2EN) +#define TIM_BREAK2_COMP2 (TIM_AF2_COMP2BRK2EN) +#define TIM_BREAK2_COMP3 (TIM_AF2_COMP3BRK2EN) +#define TIM_BREAK2_COMP4 (TIM_AF2_COMP4BRK2EN) +#define TIM_BREAK2_DSMU0 (TIM_AF2_DSMU0BRK2EN) +#define TIM_BREAK2_DSMU1 (TIM_AF2_DSMU1BRK2EN) +#define TIM_BREAK2_DSMU2 (TIM_AF2_DSMU2BRK2EN) +#define TIM_BREAK2_DSMU3 (TIM_AF2_DSMU3BRK2EN) + + /** Polarity of break2 input from IOM **/ +#define TIM_BREAK2_SOURCE_POLARITY_INVERT (TIM_AF2_IOMBRK2P | TIM_AF2_COMP1BRK2P | TIM_AF2_COMP2BRK2P | TIM_AF2_COMP3BRK2P | TIM_AF2_COMP4BRK2P) +#define TIM_BREAK2_SOURCE_POLARITY_NONINVERT (TIM_REG_BIT_MASK) + +/** TIM_interrupt_sources **/ +#define TIM_INT_CC1 (TIM_DINTEN_CC1IEN) +#define TIM_INT_CC2 (TIM_DINTEN_CC2IEN) +#define TIM_INT_CC3 (TIM_DINTEN_CC3IEN) +#define TIM_INT_CC4 (TIM_DINTEN_CC4IEN) +#define TIM_INT_CC5 (TIM_DINTEN_CC5IEN) +#define TIM_INT_CC6 (TIM_DINTEN_CC6IEN) +#define TIM_INT_CC7 (TIM_DINTEN_CC7IEN) +#define TIM_INT_CC8 (TIM_DINTEN_CC8IEN) +#define TIM_INT_CC9 (TIM_DINTEN_CC9IEN) +#define TIM_INT_UPDATE (TIM_DINTEN_UIEN) +#define TIM_INT_TRIG (TIM_DINTEN_TIEN) +#define TIM_INT_BREAK (TIM_DINTEN_BIEN) +#define TIM_INT_COM (TIM_DINTEN_COMIEN) + +/** TIM_interrupt extra flag **/ +#define TIM_INT_BREAK2 (TIM_STS_BITF2) +#define TIM_INT_SYS_BREAK (TIM_STS_SBITF) + +/** TIM_Event_Source **/ +#define TIM_EVT_SRC_CC1 (TIM_EVTGEN_CC1GN) +#define TIM_EVT_SRC_CC2 (TIM_EVTGEN_CC2GN) +#define TIM_EVT_SRC_CC3 (TIM_EVTGEN_CC3GN) +#define TIM_EVT_SRC_CC4 (TIM_EVTGEN_CC4GN) +#define TIM_EVT_SRC_UPDATE (TIM_EVTGEN_UDGN) +#define TIM_EVT_SRC_COM (TIM_EVTGEN_CCUDGN) +#define TIM_EVT_SRC_TRIG (TIM_EVTGEN_TGN) +#define TIM_EVT_SRC_BREAK (TIM_EVTGEN_BGN) +#define TIM_EVT_SRC_BREAK2 (TIM_EVTGEN_BGN2) + +/** TIM_DMA_Base_address **/ +#define TIM_DMABASE_CTRL1 (TIM_REG_BIT_MASK) +#define TIM_DMABASE_CTRL2 (TIM_DCTRL_DBADDR_0) +#define TIM_DMABASE_STS (TIM_DCTRL_DBADDR_1) +#define TIM_DMABASE_EVTGEN (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1) +#define TIM_DMABASE_SMCTRL (TIM_DCTRL_DBADDR_2) +#define TIM_DMABASE_DMAINTEN (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_2) +#define TIM_DMABASE_CAPCMPMOD1 (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2) +#define TIM_DMABASE_CAPCMPMOD2 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2) +#define TIM_DMABASE_CAPCMPMOD3 (TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPEN (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPDAT1 (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPDAT2 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPDAT3 (TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPDAT4 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPDAT5 (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_CAPCMPDAT6 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3) +#define TIM_DMABASE_PSC (TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_AR (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_CNT (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_REPCNT (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_BKDT (TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_CAPCMPDAT7 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_CAPCMPDAT8 (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_CAPCMPDAT9 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_BKFR (TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_C1FILT (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_C2FILT (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_C3FILT (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_C4FILT (TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_FILTO (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_INSEL (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_AF1 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_2 | TIM_DCTRL_DBADDR_3 | TIM_DCTRL_DBADDR_4) +#define TIM_DMABASE_AF2 (TIM_DCTRL_DBADDR_5) +#define TIM_DMABASE_BKFR2 (TIM_DCTRL_DBADDR_0 | TIM_DCTRL_DBADDR_5) +#define TIM_DMABASE_SLIDFPSC (TIM_DCTRL_DBADDR_1 | TIM_DCTRL_DBADDR_5) + +/** TIM_DMA_Burst_Length **/ +#define TIM_DMABURST_LENGTH_1TRANSFER (TIM_REG_BIT_MASK) +#define TIM_DMABURST_LENGTH_2TRANSFERS (TIM_DCTRL_DBLEN_0) +#define TIM_DMABURST_LENGTH_3TRANSFERS (TIM_DCTRL_DBLEN_1) +#define TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1) +#define TIM_DMABURST_LENGTH_5TRANSFERS (TIM_DCTRL_DBLEN_2) +#define TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_2) +#define TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2) +#define TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2) +#define TIM_DMABURST_LENGTH_9TRANSFERS (TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3) +#define TIM_DMABURST_LENGTH_17TRANSFERS (TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_27TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_28TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_29TRANSFERS (TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_30TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_31TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_32TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_2 | TIM_DCTRL_DBLEN_3 | TIM_DCTRL_DBLEN_4) +#define TIM_DMABURST_LENGTH_33TRANSFERS (TIM_DCTRL_DBLEN_5) +#define TIM_DMABURST_LENGTH_34TRANSFERS (TIM_DCTRL_DBLEN_0 | TIM_DCTRL_DBLEN_5) +#define TIM_DMABURST_LENGTH_35TRANSFERS (TIM_DCTRL_DBLEN_1 | TIM_DCTRL_DBLEN_5) + +/** TIM_DMA_sources **/ +#define TIM_DMA_CC1 (TIM_DINTEN_CC1DEN) +#define TIM_DMA_CC2 (TIM_DINTEN_CC2DEN) +#define TIM_DMA_CC3 (TIM_DINTEN_CC3DEN) +#define TIM_DMA_CC4 (TIM_DINTEN_CC4DEN) +#define TIM_DMA_UPDATE (TIM_DINTEN_UDEN) +#define TIM_DMA_COM (TIM_DINTEN_COMDEN) +#define TIM_DMA_TRIG (TIM_DINTEN_TDEN) + +/** TIM_Slave_Mode **/ +#define TIM_SLAVE_MODE_DISABLE (TIM_REG_BIT_MASK) +#define TIM_SLAVE_MODE_RESET (TIM_SMCTRL_SMSEL_2) +#define TIM_SLAVE_MODE_GATED (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_2) +#define TIM_SLAVE_MODE_TRIG (TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_2) +#define TIM_SLAVE_MODE_EXT1 (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_2) +#define TIM_SLAVE_MODE_GATED_RESET (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_3) +#define TIM_SLAVE_MODE_TRIG_RESET (TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_3) + +/** TIM_EncoderMode **/ +#define TIM_ENCODE_QUA_MODE_TI1 (TIM_SMCTRL_SMSEL_0) +#define TIM_ENCODE_QUA_MODE_TI2 (TIM_SMCTRL_SMSEL_1) +#define TIM_ENCODE_QUA_MODE_TI12 (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_1) +#define TIM_ENCODE_QUA_MODE_SINGLE_TI1 (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_3) +#define TIM_ENCODE_QUA_MODE_SINGLE_TI2 (TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_3) +#define TIM_ENCODE_DUL_CLKPLUS_MODE1 (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_3) +#define TIM_ENCODE_DUL_CLKPLUS_MODE2 (TIM_SMCTRL_SMSEL_3) +#define TIM_ENCODE_SINGLE_CLKPLUS_MODE1 (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_3) +#define TIM_ENCODE_SINGLE_CLKPLUS_MODE2 (TIM_SMCTRL_SMSEL_0 | TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_3) + +/** TIM_Output_Compare_Preload_State **/ +#define TIM_OC_PRE_LOAD_ENABLE (TIM_CCMOD1_OC1PEN) +#define TIM_OC_PRE_LOAD_DISABLE (TIM_REG_BIT_MASK) + +/** TIM_Output_Compare_Fast_State **/ +#define TIM_OC_FAST_ENABLE (TIM_CCMOD1_OC1FEN) +#define TIM_OC_FAST_DISABLE (TIM_REG_BIT_MASK) + +/** TIM_Output_Compare_Clear_State **/ +#define TIM_OC_CLR_ENABLE (TIM_CCMOD1_OC1CEN) +#define TIM_OC_CLR_DISABLE (TIM_REG_BIT_MASK) + +/** Capture compare enable **/ +#define CAPCMPEN_CCE_SET (TIM_CCEN_CC1EN) +#define CAPCMPEN_CCNE_SET (TIM_CCEN_CC1NEN) + +/** TIM_Capture_Compare_state **/ +#define TIM_CAP_CMP_ENABLE (TIM_CCEN_CC1EN) +#define TIM_CAP_CMP_DISABLE (TIM_REG_BIT_MASK) + +/** TIM_Capture_Compare_N_state **/ +#define TIM_CAP_CMP_N_ENABLE (TIM_CCEN_CC1NEN) +#define TIM_CAP_CMP_N_DISABLE (TIM_REG_BIT_MASK) + +/** TIMx_CCOMD1 register address offset **/ +#define CAPCMPMOD_OFFSET ((uint32_t)0x00000018) + +/** TIM_Update_Source **/ +#define TIM_UPDATE_SRC_GLOBAL (TIM_REG_BIT_MASK) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UPDATE_SRC_REGULAR (TIM_CTRL1_UPRS) /* Source of update is counter overflow/underflow. */ + +/** TIM_One_Pulse_Mode **/ +#define TIM_OPMODE_SINGLE (TIM_CTRL1_ONEPM) +#define TIM_OPMODE_REPET (TIM_REG_BIT_MASK) + +/** TIM_Trigger_Output_Source **/ +#define TIM_TRGO_SRC_RESET (TIM_REG_BIT_MASK) +#define TIM_TRGO_SRC_ENABLE (TIM_CTRL2_MMSEL_0) +#define TIM_TRGO_SRC_UPDATE (TIM_CTRL2_MMSEL_1) +#define TIM_TRGO_SRC_OC1 (TIM_CTRL2_MMSEL_0 | TIM_CTRL2_MMSEL_1) +#define TIM_TRGO_SRC_OC1REF (TIM_CTRL2_MMSEL_2) +#define TIM_TRGO_SRC_OC2REF (TIM_CTRL2_MMSEL_0 | TIM_CTRL2_MMSEL_2) +#define TIM_TRGO_SRC_OC3REF (TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_2) +#define TIM_TRGO_SRC_OC4REF (TIM_CTRL2_MMSEL_0 | TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_2) +#define TIM_TRGO_SRC_OC4_7_8_9REF (TIM_CTRL2_MMSEL_3) + +/** TIM_Trigger_Output2_Source **/ +#define TIM_TRGO2_SRC_RESET (TIM_REG_BIT_MASK) +#define TIM_TRGO2_SRC_ENABLE (TIM_CTRL2_MMSEL2_0) +#define TIM_TRGO2_SRC_UPDATE (TIM_CTRL2_MMSEL2_1) +#define TIM_TRGO2_SRC_OC1 (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_1) +#define TIM_TRGO2_SRC_OC1REF (TIM_CTRL2_MMSEL2_2) +#define TIM_TRGO2_SRC_OC2REF (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_2) +#define TIM_TRGO2_SRC_OC3REF (TIM_CTRL2_MMSEL2_1 | TIM_CTRL2_MMSEL2_2) +#define TIM_TRGO2_SRC_OC4REF (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_1 | TIM_CTRL2_MMSEL2_2) +#define TIM_TRGO2_SRC_OC5REF (TIM_CTRL2_MMSEL2_3) +#define TIM_TRGO2_SRC_OC6REF (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_3) +#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CTRL2_MMSEL2_1 | TIM_CTRL2_MMSEL2_3) +#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_1 | TIM_CTRL2_MMSEL2_3) +#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CTRL2_MMSEL2_2 | TIM_CTRL2_MMSEL2_3) +#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_2 | TIM_CTRL2_MMSEL2_3) +#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CTRL2_MMSEL2_1 | TIM_CTRL2_MMSEL2_2 | TIM_CTRL2_MMSEL2_3) +#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CTRL2_MMSEL2_0 | TIM_CTRL2_MMSEL2_1 | TIM_CTRL2_MMSEL2_2 | TIM_CTRL2_MMSEL2_3) + + + +/** TIM_Master_Slave_Mode **/ +#define TIM_MASTER_SLAVE_MODE_ENABLE (TIM_SMCTRL_MSMD) +#define TIM_MASTER_SLAVE_MODE_DISABLE (TIM_REG_BIT_MASK) + +/** TIM_Legacy **/ +#define TIM_CC1EN (TIM_CCEN_CC1EN) +#define TIM_CC1NEN (TIM_CCEN_CC1NEN) +#define TIM_CC2EN (TIM_CCEN_CC2EN) +#define TIM_CC2NEN (TIM_CCEN_CC2NEN) +#define TIM_CC3EN (TIM_CCEN_CC3EN) +#define TIM_CC3NEN (TIM_CCEN_CC3NEN) +#define TIM_CC4EN (TIM_CCEN_CC4EN) +#define TIM_CC4NEN (TIM_CCEN_CC4NEN) +#define TIM_CC5EN (TIM_CCEN_CC5EN) +#define TIM_CC6EN (TIM_CCEN_CC6EN) + +/** TIM_Flags **/ +#define TIM_FLAG_UPDATE (TIM_STS_UDITF) +#define TIM_FLAG_CC1 (TIM_STS_CC1ITF) +#define TIM_FLAG_CC2 (TIM_STS_CC2ITF) +#define TIM_FLAG_CC3 (TIM_STS_CC3ITF) +#define TIM_FLAG_CC4 (TIM_STS_CC4ITF) +#define TIM_FLAG_CC5 (TIM_STS_CC5ITF) +#define TIM_FLAG_CC6 (TIM_STS_CC6ITF) +#define TIM_FLAG_CC7 (TIM_STS_CC7ITF) +#define TIM_FLAG_CC8 (TIM_STS_CC8ITF) +#define TIM_FLAG_CC9 (TIM_STS_CC9ITF) +#define TIM_FLAG_COM (TIM_STS_COMITF) +#define TIM_FLAG_TRIG (TIM_STS_TITF) +#define TIM_FLAG_BREAK (TIM_STS_BITF) +#define TIM_FLAG_BREAK2 (TIM_STS_BITF2) +#define TIM_FLAG_SYS_BREAK (TIM_STS_SBITF) +#define TIM_FLAG_CC1OF (TIM_STS_CC1OCF) +#define TIM_FLAG_CC2OF (TIM_STS_CC2OCF) +#define TIM_FLAG_CC3OF (TIM_STS_CC3OCF) +#define TIM_FLAG_CC4OF (TIM_STS_CC4OCF) + +/* TIM_CenterAlignTriggerSource */ +#define TIM_UP_COUNTING (TIM_REG_BIT_MASK) +#define TIM_DOWN_COUNTING (TIM_CTRL1_CMODE_0) +#define TIM_UP_DOWN_COUNTING (TIM_CTRL1_CMODE_1) + +/** TIM_Flags **/ +#define TIM_C1FILTO (TIM_FILTO_C1FILTO) +#define TIM_C2FILTO (TIM_FILTO_C2FILTO) +#define TIM_C3FILTO (TIM_FILTO_C3FILTO) +#define TIM_C4FILTO (TIM_FILTO_C4FILTO) + +/*** TIM Macro Definition End ***/ + + +/** TIM_Exported_Functions Start **/ + +void TIM_DeInit(TIM_Module* TIMx); +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_BreakFiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct); +void TIM_BreakFiltEnable(TIM_Module* TIMx,FunctionalState Cmd); +void TIM_Break2FiltEnable(TIM_Module* TIMx,FunctionalState Cmd); +void TIM_Break2FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct); +void TIM_BreakInputSourceEnable(TIM_Module* TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd); +void TIM_Break2InputSourceEnable(TIM_Module* TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd); +void TIM_BidirectionDisarm(TIM_Module* TIMx); +void TIM_BidirectionRearm(TIM_Module* TIMx); +void TIM_Bidirection2Disarm(TIM_Module* TIMx); +void TIM_Bidirection2Rearm(TIM_Module* TIMx); +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct); +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct); +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigInt(TIM_Module* TIMx, uint32_t TIM_IT, FunctionalState Cmd); +void TIM_GenerateEvent(TIM_Module* TIMx, uint32_t TIM_EventSource); +void TIM_ConfigDma(TIM_Module* TIMx, uint32_t TIM_DMABase, uint32_t TIM_DMABurstLength); +void TIM_EnableDma(TIM_Module* TIMx, uint32_t TIM_DMASource, FunctionalState Cmd); +void TIM_ConfigInternalClk(TIM_Module* TIMx); +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint32_t TIM_InputTriggerSource); +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint32_t TIM_TIxExternalCLKSource, uint32_t IcPolarity, uint32_t ICFilter); +void TIM_ConfigExtClkMode1(TIM_Module* TIMx,uint32_t TIM_ETRInputSource,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter); +void TIM_ConfigExtClkMode2(TIM_Module* TIMx,uint32_t TIM_ETRInputSource,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter); +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode); +void TIM_ConfigCntMode(TIM_Module* TIMx, uint32_t CntMode); +void TIM_ConfigEncoderInterface(TIM_Module* TIMx,uint32_t TIM_EncoderMode,uint32_t TIM_IC1Polarity,uint32_t TIM_IC2Polarity); +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint32_t TIM_ForcedAction); +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint32_t TIM_ForcedAction); +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint32_t TIM_ForcedAction); +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint32_t TIM_ForcedAction); +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint32_t TIM_ForcedAction); +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint32_t TIM_ForcedAction); +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc7Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc8Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc9Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload); +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint32_t TIM_OCFast); +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint32_t TIM_OCFast); +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint32_t TIM_OCFast); +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint32_t TIM_OCFast); +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint32_t TIM_OCFast); +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint32_t TIM_OCFast); +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint32_t TIM_OCClear); +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint32_t TIM_OCClear); +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint32_t TIM_OCClear); +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint32_t TIM_OCClear); +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint32_t TIM_OCClear); +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint32_t TIM_OCClear); +void TIM_ClrOcRefInputSource(TIM_Module* TIMx, uint32_t OCRefClearInputSelect,uint32_t OCRefClearInputSource); +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint32_t OcPolarity); +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity); +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint32_t OcPolarity); +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity); +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint32_t OcPolarity); +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity); +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint32_t OcPolarity); +void TIM_ConfigOc4NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity); +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint32_t OcPolarity); +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint32_t OcPolarity); +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint32_t Channel, uint32_t TIM_CCx); +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint32_t Channel, uint32_t TIM_CCxN); +void TIM_SelectOcMode(TIM_Module* TIMx, uint32_t Channel, uint32_t OcMode); +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint32_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint32_t TIM_OPMode); +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint32_t TIM_TRGOSource); +void TIM_SelectOutputTrig2(TIM_Module* TIMx, uint32_t TIM_TRGO2Source); +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint32_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint32_t TIM_MasterSlaveMode); +void TIM_SetCnt(TIM_Module* TIMx, uint32_t Counter); +void TIM_SetAutoReload(TIM_Module* TIMx, uint32_t Autoreload); +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1); +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2); +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3); +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4); +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5); +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6); +void TIM_SetCmp7(TIM_Module* TIMx, uint16_t Compare7); +void TIM_SetCmp8(TIM_Module* TIMx, uint16_t Compare8); +void TIM_SetCmp9(TIM_Module* TIMx, uint16_t Compare9); +void TIM_SetCmp1D(TIM_Module* TIMx, uint16_t compare1D); +void TIM_SetCmp2D(TIM_Module* TIMx, uint16_t compare2D); +void TIM_SetCmp3D(TIM_Module* TIMx, uint16_t compare3D); +void TIM_SetCmp4D(TIM_Module* TIMx, uint16_t compare4D); +void ConfigTI1(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter); +void ConfigTI2(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter); +void ConfigTI3(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter); +void ConfigTI4(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter); +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler); +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler); +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler); +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler); +void TIM_SelectInputTrig(TIM_Module* TIMx, uint32_t TIM_InputTriggerSource); +void TIM_ConfigExtTrig(TIM_Module* TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter); +void TIM_SelectETRInputSource(TIM_Module* TIMx, uint32_t TIM_ETRInputSource); +void TIM_SetClkDiv(TIM_Module* TIMx, uint32_t TIM_CKD); +uint16_t TIM_GetCap1(TIM_Module* TIMx); +uint16_t TIM_GetCap2(TIM_Module* TIMx); +uint16_t TIM_GetCap3(TIM_Module* TIMx); +uint16_t TIM_GetCap4(TIM_Module* TIMx); +uint16_t TIM_GetCap5(TIM_Module* TIMx); +uint16_t TIM_GetCap6(TIM_Module* TIMx); +uint16_t TIM_GetCap7(TIM_Module* TIMx); +uint16_t TIM_GetCap8(TIM_Module* TIMx); +uint16_t TIM_GetCap9(TIM_Module* TIMx); +uint16_t TIM_GetCap1D(TIM_Module* TIMx); +uint16_t TIM_GetCap2D(TIM_Module* TIMx); +uint16_t TIM_GetCap3D(TIM_Module* TIMx); +uint16_t TIM_GetCap4D(TIM_Module* TIMx); +uint32_t TIM_GetCnt(TIM_Module* TIMx); +uint16_t TIM_GetPrescaler(TIM_Module* TIMx); +uint32_t TIM_GetAutoReload(TIM_Module* TIMx); +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN); +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG); +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG); +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_SelectCenterAlignTrig(TIM_Module* TIMx, uint32_t TIM_CenterAlignTriggerSource); +void TIM_AsymmetricEnable(TIM_Module* TIMx, FunctionalState Cmd); +void TIM_OCxRefTriggerADC(TIM_Module* TIMx, uint32_t OCxRef, FunctionalState Cmd); +void TIM_IC1FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct); +void TIM_IC2FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct); +void TIM_IC3FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct); +void TIM_IC4FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct); +void TIM_IC1FiltEnable(TIM_Module* TIMx,FunctionalState Cmd); +void TIM_IC2FiltEnable(TIM_Module* TIMx,FunctionalState Cmd); +void TIM_IC3FiltEnable(TIM_Module* TIMx,FunctionalState Cmd); +void TIM_IC4FiltEnable(TIM_Module* TIMx,FunctionalState Cmd); +FlagStatus TIM_GetFiltStatus(TIM_Module* TIMx, uint32_t TIM_FiltFlag); + +/** TIM_Exported_Functions End **/ + +#ifdef __cplusplus +} + +#endif + +#endif /*__N32H76x_78x_TIM_H */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_usart.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_usart.h new file mode 100644 index 0000000000..4bf8d470be --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_usart.h @@ -0,0 +1,366 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_usart.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_USART_H__ +#define __N32H76X_78X_USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** USART Init Structure definition **/ + +typedef struct +{ + uint32_t BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint32_t WordLength; /* Specifies the number of data bits transmitted or received in a frame. */ + + uint32_t StopBits; /* Specifies the number of stop bits transmitted. */ + + uint32_t Parity; /* Specifies the parity mode. */ + + uint32_t Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. */ + + uint32_t HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled or disabled. */ + + uint32_t OverSampling; /* Specifies whether USART oversampling mode is 16 or 8. */ +} USART_InitType; + +/** USART Clock Init Structure definition **/ + +typedef struct +{ + uint32_t Clock; /* Specifies whether the USART clock is enabled or disabled. */ + + uint32_t Polarity; /* Specifies the steady state value of the serial clock. */ + + uint32_t Phase; /* Specifies the clock transition on which the bit capture is made. */ + + uint32_t LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ +} USART_ClockInitType; + +/*** USART Structure Definition End ***/ + +/*** USART Macro Definition Start ***/ + +#define USART_REG_BIT_MASK (uint32_t)0x00000000U + +/* USART CTRL1 Mask */ +#define USART_CTRL1_CLR_MASK ((uint32_t)(~(USART_CTRL1_RXEN \ + |USART_CTRL1_TXEN \ + |USART_CTRL1_PSEL \ + |USART_CTRL1_PCEN \ + |USART_8OVER \ + |USART_CTRL1_WL))) + +/** Configures the word length of USART **/ +#define USART_WL_8B ((uint32_t)USART_REG_BIT_MASK) /* 8 bits */ +#define USART_WL_9B ((uint32_t)USART_CTRL1_WL) /* 9 bits */ + +/** USART STOP bits **/ +#define CTRL2_STPB_CLR_MASK ((uint32_t)(~USART_CTRL2_STPB)) /* USART CTRL2 STOP Bits Mask */ +#define USART_STPB_1 ((uint32_t)USART_REG_BIT_MASK) /* 1 STOP bit */ +#define USART_STPB_0_5 ((uint32_t)USART_CTRL2_STPB_0) /* 0.5 STOP bit */ +#define USART_STPB_2 ((uint32_t)USART_CTRL2_STPB_1) /* 2 STOP bits */ +#define USART_STPB_1_5 ((uint32_t)(USART_CTRL2_STPB_1|USART_CTRL2_STPB_0)) /* 1.5 STOP bits */ + +/** USART parity selection **/ +#define USART_PE_NO (USART_REG_BIT_MASK) /* USART parity disable */ +#define USART_PE_EVEN ((uint32_t)USART_CTRL1_PCEN) /* Even parity */ +#define USART_PE_ODD ((uint32_t)(USART_CTRL1_PCEN | USART_CTRL1_PSEL)) /* Odd parity */ + +/** USART is configured as RX or TX **/ +#define USART_MODE_RX ((uint32_t)USART_CTRL1_RXEN) /* Transmitter enable */ +#define USART_MODE_TX ((uint32_t)USART_CTRL1_TXEN) /* Receiver enable */ + +/** USART Hardware Flow Control **/ +#define CTRL3_CLR_MASK ((uint32_t)(~USART_HFCTRL_RTS_CTS)) /* USART CTRL3 Mask */ +#define USART_HFCTRL_NONE ((uint32_t)USART_REG_BIT_MASK) +#define USART_HFCTRL_RTS ((uint32_t)USART_CTRL3_RTSEN) +#define USART_HFCTRL_CTS ((uint32_t)USART_CTRL3_CTSEN) +#define USART_HFCTRL_RTS_CTS ((uint32_t)(USART_CTRL3_RTSEN | USART_CTRL3_CTSEN)) + +/** USART oversampling configure **/ +#define USART_8OVER ((uint32_t)USART_CTRL1_OSPM) +#define USART_16OVER ((uint32_t)USART_REG_BIT_MASK) + +/* USART CTRL2 Clock Mask */ +#define CTRL2_CLOCK_CLR_MASK ((uint32_t)(~(USART_CLK_ENABLE \ + | USART_CTRL2_CLKPOL \ + | USART_CTRL2_CLKPHA \ + | USART_CTRL2_LBCLK))) +/** Clock **/ +#define USART_CLK_DISABLE ((uint32_t)USART_REG_BIT_MASK) +#define USART_CLK_ENABLE ((uint32_t)USART_CTRL2_CLKEN) + +/** USART_Clock_Polarity **/ +#define USART_CLKPOL_LOW ((uint32_t)USART_REG_BIT_MASK) +#define USART_CLKPOL_HIGH ((uint32_t)USART_CTRL2_CLKPOL) + +/** USART_Clock_Phase **/ +#define USART_CLKPHA_1EDGE ((uint32_t)USART_REG_BIT_MASK) +#define USART_CLKPHA_2EDGE ((uint32_t)USART_CTRL2_CLKPHA) + +/** USART_Last_Bit **/ +#define USART_CLKLB_DISABLE ((uint32_t)USART_REG_BIT_MASK) +#define USART_CLKLB_ENABLE ((uint32_t)USART_CTRL2_LBCLK) + + +#define CTRL1_UEN_SET ((uint32_t)USART_CTRL1_UEN) /* USART Enable Mask */ +#define CTRL1_UEN_RESET ((uint32_t)(~USART_CTRL1_UEN)) /* USART Disable Mask */ + +#define CTRL1_IFCEN_ENABLE ((uint32_t)USART_CTRL1_IFCEN) /* USART Idle frame Enable */ +#define CTRL1_IFCEN_DISABLE ((uint32_t)(~USART_CTRL1_IFCEN)) /* USART Idle frame Disable */ + +#define CTRL1_SWAP_ENABLE ((uint32_t)USART_CTRL1_SWAP) /* USART Idle frame Enable */ +#define CTRL1_SWAP_DISABLE ((uint32_t)(~USART_CTRL1_SWAP)) /* USART Idle frame Disable */ + +#define CTRL1_DEP_ENABLE ((uint32_t)USART_CTRL1_DEP) /* USART DE signal active high */ +#define CTRL1_DEP_DISABLE ((uint32_t)(~USART_CTRL1_DEP)) /* USART DE signal active low */ + +/* USART Driver enable mode */ +#define CTRL1_DEM_ENABLE ((uint32_t)USART_CTRL1_DEM) +#define CTRL1_DEM_DISABLE ((uint32_t)(~USART_CTRL1_DEM)) + +/* USART FEF Data Discard Enable */ +#define CTRL2_FEFLOSE_ENABLE ((uint32_t)USART_CTRL2_FEFLOSE) +#define CTRL2_FEFLOSE_DISABLE ((uint32_t)(~USART_CTRL2_FEFLOSE)) + +/* USART NEF Data Discard Enable */ +#define CTRL2_NEFLOSE_ENABLE ((uint32_t)USART_CTRL2_NEFLOSE) +#define CTRL2_NEFLOSE_DISABLE ((uint32_t)(~USART_CTRL2_NEFLOSE)) + +/* USART PEF Data Discard Enable */ +#define CTRL2_PEFLOSE_ENABLE ((uint32_t)USART_CTRL2_PEFLOSE) +#define CTRL2_PEFLOSE_DISABLE ((uint32_t)(~USART_CTRL2_PEFLOSE)) + +/* Receiver timeout enable */ +#define CTRL2_RTO_ENABLE ((uint32_t)USART_CTRL2_RTOEN) +#define CTRL2_RTO_DISABLE ((uint32_t)(~USART_CTRL2_RTOEN)) + + +/** USART_Interrupt_definition **/ +#define USART_INT_MASK ((uint32_t)0x0FFFFFFFU) /* USART Interrupt Mask */ +#define USART_CTRL1_INTMASK ((uint32_t)0x10000000U) +#define USART_CTRL2_INTMASK ((uint32_t)0x20000000U) +#define USART_CTRL3_INTMASK ((uint32_t)0x40000000U) +#define USART_FIFO_INTMASK ((uint32_t)0x80000000U) + +#define USART_INT_PEF ((uint32_t)(USART_CTRL1_INTMASK | USART_CTRL1_PEIEN)) +#define USART_INT_TXC ((uint32_t)(USART_CTRL1_INTMASK | USART_CTRL1_TXCIEN)) +#define USART_INT_TXDE ((uint32_t)(USART_CTRL1_INTMASK | USART_CTRL1_TXDEIEN)) +#define USART_INT_RXDNE ((uint32_t)(USART_CTRL1_INTMASK | USART_CTRL1_RXDNEIEN)) +#define USART_INT_IDLEF ((uint32_t)(USART_CTRL1_INTMASK | USART_CTRL1_IDLEIEN)) +#define USART_INT_RTOE ((uint32_t)(USART_CTRL2_INTMASK | USART_CTRL2_RTOIEN)) +#define USART_INT_LINBD ((uint32_t)(USART_CTRL2_INTMASK | USART_CTRL2_LINBDIEN)) +#define USART_INT_ERRF ((uint32_t)(USART_CTRL3_INTMASK | USART_CTRL3_ERRIEN)) +#define USART_INT_CTSF ((uint32_t)(USART_CTRL3_INTMASK | USART_CTRL3_CTSIEN)) + +#define USART_INT_TXFTE ((uint32_t)(USART_FIFO_INTMASK | USART_FIFO_TXFTIEN)) +#define USART_INT_RXFTE ((uint32_t)(USART_FIFO_INTMASK | USART_FIFO_RXFTIEN)) +#define USART_INT_RXFEE ((uint32_t)(USART_FIFO_INTMASK | USART_FIFO_RXFEIEN)) +#define USART_INT_TXFEE ((uint32_t)(USART_FIFO_INTMASK | USART_FIFO_TXFEIEN)) +#define USART_INT_RXFFE ((uint32_t)(USART_FIFO_INTMASK | USART_FIFO_RXFFIEN)) +#define USART_INT_TXFFE ((uint32_t)(USART_FIFO_INTMASK | USART_FIFO_TXFFIEN)) + + +#define CTRL2_ADDR_MASK ((uint32_t)(~USART_CTRL2_ADDR)) + +/** USART_DMA_Requests **/ +#define USART_DMAREQ_TX ((uint32_t)USART_CTRL3_DMATXEN) +#define USART_DMAREQ_RX ((uint32_t)USART_CTRL3_DMARXEN) + +/** USART_WakeUp_methods **/ +#define CTRL1_WUM_MASK ((uint32_t)(~USART_CTRL1_WUM)) +#define USART_WUM_IDLELINE ((uint32_t)USART_REG_BIT_MASK) +#define USART_WUM_ADDRMASK ((uint32_t)USART_CTRL1_WUM) + +/* USART mute mode */ +#define CTRL1_RCVWU_SET ((uint32_t)USART_CTRL1_RCVWU) +#define CTRL1_RCVWU_RESET ((uint32_t)(~USART_CTRL1_RCVWU)) + +/** USART_LIN_Break_Detection_Length **/ +#define CTRL2_LINBDL_MASK ((uint32_t)(~USART_CTRL2_LINBDL)) +#define USART_LINBDL_10B ((uint32_t)USART_REG_BIT_MASK) +#define USART_LINBDL_11B ((uint32_t)USART_CTRL2_LINBDL) + +/* USART LIN */ +#define CTRL2_LINMEN_SET ((uint32_t)USART_CTRL2_LINMEN) +#define CTRL2_LINMEN_RESET ((uint32_t)(~USART_CTRL2_LINMEN)) + +/* USART Break Character send Mask */ +#define CTRL1_SDBRK_SET ((uint32_t)USART_CTRL1_SDBRK) + +/* Guard Time Register */ +#define GTP_LSB_MASK ((uint32_t)(~USART_GTP_GTV)) +#define GTP_MSB_MASK ((uint32_t)(~USART_GTP_PSCV)) + +/* USART SCMEN Mask */ +#define CTRL3_SCMEN_SET ((uint32_t)USART_CTRL3_SCMEN) +#define CTRL3_SCMEN_RESET ((uint32_t)(~USART_CTRL3_SCMEN)) + +/* USART SC NACK Mask */ +#define CTRL3_SCNACK_SET ((uint32_t)USART_CTRL3_SCNACK) +#define CTRL3_SCNACK_RESET ((uint32_t)(~USART_CTRL3_SCNACK)) + +/* USART Half-Duplex Mask */ +#define CTRL3_HDMEN_SET ((uint32_t)USART_CTRL3_HDMEN) +#define CTRL3_HDMEN_RESET ((uint32_t)(~USART_CTRL3_HDMEN)) + +/** USART_IrDA_Low_Power **/ +#define CTRL3_IRDALP_MASK ((uint32_t)(~USART_CTRL3_IRDALP)) +#define USART_IRDAMODE_LOWPPWER ((uint32_t)USART_CTRL3_IRDALP) +#define USART_IRDAMODE_NORMAL ((uint32_t)USART_REG_BIT_MASK) + + /* USART IrDA Mask */ +#define CTRL3_IRDAMEN_SET ((uint32_t)USART_CTRL3_IRDAMEN) +#define CTRL3_IRDAMEN_RESET ((uint32_t)(~USART_CTRL3_IRDAMEN)) + +/** USART_Flags **/ +#define USART_FLAG_LOSEMASK ((uint32_t)USART_STS_FELOSEF | USART_STS_NELOSEF | USART_STS_PELOSEF) +#define USART_FLAG_FELOSE ((uint32_t)USART_STS_FELOSEF) +#define USART_FLAG_NELOSE ((uint32_t)USART_STS_NELOSEF) +#define USART_FLAG_PELOSE ((uint32_t)USART_STS_PELOSEF) +#define USART_FLAG_RTO ((uint32_t)USART_STS_RTOF) +#define USART_FLAG_FEF ((uint32_t)USART_STS_FEF) +#define USART_FLAG_NEF ((uint32_t)USART_STS_NEF) +#define USART_FLAG_OREF ((uint32_t)USART_STS_OREF) +#define USART_FLAG_PEF ((uint32_t)USART_STS_PEF) +#define USART_FLAG_LINBD ((uint32_t)USART_STS_LINBDF) +#define USART_FLAG_CTSF ((uint32_t)USART_STS_CTSF) +#define USART_FLAG_RXDNE ((uint32_t)USART_STS_RXDNE) +#define USART_FLAG_TXC ((uint32_t)USART_STS_TXC) +#define USART_FLAG_TXDE ((uint32_t)USART_STS_TXDE) +#define USART_FLAG_IDLEF ((uint32_t)USART_STS_IDLEF) +#define USART_FLAG_TXFT ((uint32_t)USART_STS_TXFT) +#define USART_FLAG_RXFT ((uint32_t)USART_STS_RXFT) +#define USART_FLAG_RXFE ((uint32_t)USART_STS_RXFE) +#define USART_FLAG_TXFE ((uint32_t)USART_STS_TXFE) +#define USART_FLAG_RXFF ((uint32_t)USART_STS_RXFF) +#define USART_FLAG_TXFF ((uint32_t)USART_STS_TXFF) + +/* FIFO depth*/ +#define USART_FIFO_DEEP1 ((uint32_t)0x00000000U) +#define USART_FIFO_DEEP2 ((uint32_t)0x00000001U) +#define USART_FIFO_DEEP4 ((uint32_t)0x00000002U) +#define USART_FIFO_DEEP6 ((uint32_t)0x00000003U) +#define USART_FIFO_DEEP7 ((uint32_t)0x00000004U) +#define USART_FIFO_DEEP8 ((uint32_t)0x00000005U) + +#define USART_CLEAR_FIFO ((uint32_t)USART_FIFO_CLR) + +/* Receiver timeout enable */ +#define USART_FIFO_ENABLE ((uint32_t)USART_FIFO_EN) +#define USART_FIFO_DISABLE ((uint32_t)(~USART_FIFO_EN)) + + +void USART_DeInit(USART_Module* USARTx); +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct); +void USART_StructInit(USART_InitType* USART_InitStruct); +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct); +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigInt(USART_Module* USARTx, uint32_t USART_INT, FunctionalState Cmd); +void USART_EnableDMA(USART_Module* USARTx, uint32_t USART_DMAReq, FunctionalState Cmd); +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr); +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint32_t USART_WakeUpMode); +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint32_t USART_LINBreakDetectLength); +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd); +void USART_SendData(USART_Module* USARTx, uint32_t Data); +uint32_t USART_ReceiveData(USART_Module* USARTx); +void USART_SendBreak(USART_Module* USARTx); +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler); +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd); +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd); +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd); +void USART_ConfigIrDAMode(USART_Module* USARTx, uint32_t USART_IrDAMode); +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd); +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint32_t USART_FLAG); +void USART_ClrFlag(USART_Module* USARTx, uint32_t USART_FLAG); +void USART_ClrRTOFlag(USART_Module* USARTx); +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint32_t USART_INT); +void USART_IdleFrameSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_PinSwapSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_CfgDriverAssertTime(USART_Module* USARTx,uint32_t Time); +void USART_CfgDriverdeassertTime(USART_Module* USARTx,uint32_t Time); +void USART_DriverPolaritySet(USART_Module* USARTx,FunctionalState Cmd); +void USART_DriverModeSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_FEFDiscardSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_NEFDiscardSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_PEFDiscardSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_RTOSet(USART_Module* USARTx,FunctionalState Cmd); +uint32_t USART_GetTxFIFO_Num(USART_Module* USARTx); +uint32_t USART_GetRxFIFO_Num(USART_Module* USARTx); +void USART_CfgRxFIFOThreshold(USART_Module* USARTx,uint32_t threshold); +void USART_CfgTxFIFOThreshold(USART_Module* USARTx,uint32_t threshold); +void USART_ClrFIFO(USART_Module* USARTx); +void USART_FIFOModeSet(USART_Module* USARTx,FunctionalState Cmd); +void USART_IdleFrameWidthSet(USART_Module* USARTx,uint32_t Width); +void USART_CfgRTOWidth(USART_Module* USARTx,uint32_t Width); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H76X_USART_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_vrefbuf.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_vrefbuf.h new file mode 100644 index 0000000000..6d6a3f043f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_vrefbuf.h @@ -0,0 +1,111 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_vrefbuf.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __N32H76X_78X_VREFBUF_H__ +#define __N32H76X_78X_VREFBUF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +/** VREFBUF Register list**/ +#define VREFBUF_STS_REG_ADDR ((uint32_t)AFEC_BASE + 0x34U) +#define VREFBUF_CTRL1_REG_ADDR ((uint32_t)AFEC_BASE + 0x48U) +#define VREFBUF_CTRL2_REG_ADDR ((uint32_t)AFEC_BASE + 0xDCU) +#define VREFBUF_TRIM1_REG_ADDR ((uint32_t)AFEC_BASE + 0x28U) +#define VREFBUF_TRIM2_REG_ADDR ((uint32_t)AFEC_BASE + 0xE8U) + +#define VREFBUF_EN_CTRL ((uint32_t)AFEC_BASE + 0x3CU) + +/** VREFBUF_Exported_Constants **/ +#define VREFBUF_EN_MASK (VREFBUF_CTRL1_EN) +#define VREFBUF_HIM_EN_MASK (VREFBUF_CTRL1_HIM) + +#define VREFBUF_VOLTAGE_SCALE_MASK (VREFBUF_CTRL2_VLSEL) +#define VREFBUF_VOLTAGE_SCALE_2_5V ((uint32_t)0x00000000U) +#define VREFBUF_VOLTAGE_SCALE_2_048V (VREFBUF_CTRL2_VLSEL_0) +#define VREFBUF_VOLTAGE_SCALE_1_8V (VREFBUF_CTRL2_VLSEL_1) +#define VREFBUF_VOLTAGE_SCALE_1_5V (VREFBUF_CTRL2_VLSEL_1 | VREFBUF_CTRL2_VLSEL_0) + +#define VREFBUF_READY_MASK (VREFBUF_STS_RDY) + +/** VREFBUF_Trimming_Constants **/ +#define VREFBUF_TRIMING_2_5V_POS ((uint8_t)16U) +#define VREFBUF_TRIMING_2_5V_MASK (VREFBUF_TRIM1_2_5V_MASK) +#define VREFBUF_TRIMING_2_0V_POS ((uint8_t)22U) +#define VREFBUF_TRIMING_2_0V_MASK (VREFBUF_TRIM1_2_048V_MASK) +#define VREFBUF_TRIMING_1_8V_POS ((uint8_t)0U) +#define VREFBUF_TRIMING_1_8V_MASK (VREFBUF_TRIM1_1_8V_MASK) +#define VREFBUF_TRIMING_1_5V_POS ((uint8_t)8U) +#define VREFBUF_TRIMING_1_5V_MASK (VREFBUF_TRIM1_1_5V_MASK) +/** VREFBUF_Exported_Functions **/ + +void VREFBUF_Enable(FunctionalState Cmd); +void VREFBUF_EnableHIM(FunctionalState Cmd); +void VREFBUF_SetVoltageScale(uint32_t Scale); +uint32_t VREFBUF_GetVoltageScale(void); +FlagStatus VREFBUF_IsVREFReady(void); + + +void VREFBUF_SetTrimming(uint32_t Value); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32H76X_78X_VREFBUF_H__ */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_wwdg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_wwdg.h new file mode 100644 index 0000000000..bbd4461c69 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_wwdg.h @@ -0,0 +1,107 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_wwdg.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __N32H76X_78X_WWDG_H__ +#define __N32H76X_78X_WWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" + +#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000) +#define WWDG_PRESCALER_DIV2 ((uint32_t)WWDG_CFG_TIMERB0) +#define WWDG_PRESCALER_DIV4 ((uint32_t)WWDG_CFG_TIMERB1) +#define WWDG_PRESCALER_DIV8 ((uint32_t)(WWDG_CFG_TIMERB1 | WWDG_CFG_TIMERB0)) + + +/** EWINT bit **/ +#define EARLY_WAKEUP_INT (WWDG_CFG_EWINT) +#define EARLY_WAKEUP_FLAG (WWDG_STS_EWINTF) + +/** CTRL register bit mask **/ +#define CTRL_ACTB_SET ((uint32_t)WWDG_CTRL_ACTB) + +/* CFG register bit mask **/ +#define CFG_TIMERB_MASK ((uint32_t)0xFFFF3FFFU) +#define CFG_W_MASK ((uint32_t)0xFFFFC000U) +#define BIT_MASK ((uint16_t)0x3FFF) + + +void WWDG_DeInit(WWDG_Module* WWDGx); +void WWDG_SetPrescalerDiv(WWDG_Module* WWDGx,uint32_t WWDG_Prescaler); +void WWDG_SetWValue(WWDG_Module* WWDGx,uint16_t WindowValue); +void WWDG_EnableInt(WWDG_Module* WWDGx); +void WWDG_SetCnt(WWDG_Module* WWDGx,uint16_t Counter); +void WWDG_Enable(WWDG_Module* WWDGx,uint16_t Counter); +FlagStatus WWDG_GetEWINTF(WWDG_Module* WWDGx); +void WWDG_ClrEWINTF(WWDG_Module* WWDGx); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32H78X__WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_xspi.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_xspi.h new file mode 100644 index 0000000000..c4642cdc52 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc/n32h76x_78x_xspi.h @@ -0,0 +1,505 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_xspi.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __n32h76x_78x_XSPI_H__ +#define __n32h76x_78x_XSPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32h76x_78x.h" +#include +#include "n32h76x_78x_rcc.h" +#include "n32h76x_78x_gpio.h" + +/** n32h76x_78x_StdPeriph_Driver **/ + +/** XSPI driver modules **/ + +#define XSPI_CTRLRO_SPI_MASK ((uint32_t)0x00001000) +#define XSPI_CTRLRO_XIP_MASK + +#define XSPI_WAITCYCLES_MASK ((uint32_t)~0x0000f800U) +#define XSPI_SPIFRF_MASK ((uint32_t)~0x00c00000U) +#define XSPI_TRANSTYPE_MASK ((uint32_t)~0x00000003U) +#define XSPI_DFS_MASK ((uint32_t)~0x0000001fU) +#define XSPI_ADDRL_MASK ((uint32_t)~0x0000003cU) +#define XSPI_INST_L_MASK ((uint32_t)~0x00000300U) +#define XSPI_NDF_MASK ((uint32_t)~0x0000ffffU) +#define XSPI_TMOD_MASK ((uint32_t)~0x00000c00U) +#define XSPI_RXFTLR_MASK ((uint32_t)~0x0000001fU) +#define XSPI_TXFTLR_MASK ((uint32_t)~0x001f0000U) +#define XSPI_TXFTLITR_MASK ((uint32_t)~0x0000001fU) +#define XSPI_TXFT_MASK ((uint32_t)~0x001f001fU) + +#define STANDRD_SPI_FORMAT XSPI_CTRL0_SPIFRF_STANDARD_FORMAT //((uint32_t)0x00000000) +#define DUAL_SPI_FORMAT XSPI_CTRL0_SPIFRF_DUAL_FORMAT //((uint32_t)0x00400000) +#define QUAD_SPI_FORMAT XSPI_CTRL0_SPIFRF_QUAD_FORMAT //((uint32_t)0x00800000) +#define OCTAL_SPI_FORMAT XSPI_CTRL0_SPIFRF_OCTAL_FORMAT //((uint32_t)0x00C00000) +#define IS_XSPI_DATA_FORMAT(FORMAT) (((FORMAT) == STANDRD_SPI_FORMAT) || \ + ((FORMAT) == DUAL_SPI_FORMAT) || \ + ((FORMAT) == QUAD_SPI_FORMAT) || \ + ((FORMAT) == OCTAL_SPI_FORMAT)) + +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define XSPI_TIME_OUT_CNT 200 + +/** XSPI_mode: XSPI_CTRL0 **/ +#define XSPI_Mode_Master XSPI_CTRL0_MST_MASTER //((uint32_t)0x80000000U) +#define XSPI_Mode_Slave XSPI_CTRL0_MST_SLAVE //((uint32_t)0x00000000U) +#define IS_XSPI_MODE(MODE) (((MODE) == QSPI_Mode_Master) || \ + ((MODE) == QSPI_Mode_Slave)) + + +/** @defgroup XSPI_data_direction + * @{ + */ + +#define TX_AND_RX XSPI_CTRL0_TMOD_TX_AND_RX // ((uint32_t)0x00000000) +#define TX_ONLY XSPI_CTRL0_TMOD_TX_ONLY // ((uint32_t)0x00000400) +#define RX_ONLY XSPI_CTRL0_TMOD_RX_ONLY // ((uint32_t)0x00000800) +#define EEPROM_READ XSPI_CTRL0_TMOD_EEPROM_READ // ((uint32_t)0x00000c00) +#define IS_XSPI_DIRECTION_MODE(MODE) (((MODE) == TX_AND_RX) || \ + ((MODE) == TX_ONLY) || \ + ((MODE) == RX_ONLY) || \ + ((MODE) == EEPROM_READ)) + +/** XSPI_Address_instruction_transfer_format.: XSPI_ENH_CTRL0 **/ +#define TRANS_TYPE_STANDRD XSPI_ENH_CTRL0_TRANSTYPE_STANDARD //((uint32_t)0x00000000) +#define TRANS_TYPE_STANDRD_FRF XSPI_ENH_CTRL0_TRANSTYPE_0 //((uint32_t)0x00000001) +#define TRANS_TYPE_FRF XSPI_ENH_CTRL0_TRANSTYPE_1 //((uint32_t)0x00000002) +#define IS_QSPI_ADDRINSTDFS(SIZE) (((SIZE) == ENSPI_INST_L_NONE) || \ + ((SIZE) == ENSPI_INST_L_04BIT) || \ + ((SIZE) == ENSPI_INST_L_08BIT) || \ + ((SIZE) == ENSPI_INST_L_16BIT)) + + +/** @defgroup QSPI_Address_length + * @{ + */ +#define ENSPI_ADDR_NONE ((uint32_t)0x00000000) +#define ENSPI_ADDR_04BIT ((uint32_t)0x00000004) +#define ENSPI_ADDR_08BIT ((uint32_t)0x00000008) +#define ENSPI_ADDR_16BIT ((uint32_t)0x00000010) +#define ENSPI_ADDR_24BIT ((uint32_t)0x00000018) +#define ENSPI_ADDR_28BIT ((uint32_t)0x0000001c) +#define ENSPI_ADDR_32BIT ((uint32_t)0x00000020) +#define ENSPI_ADDR_40BIT ((uint32_t)0x00000028) +#define ENSPI_ADDR_48BIT ((uint32_t)0x00000030) +#define ENSPI_ADDR_52BIT ((uint32_t)0x00000034) +#define ENSPI_ADDR_56BIT ((uint32_t)0x00000038) +#define ENSPI_ADDR_60BIT ((uint32_t)0x0000003C) +#define IS_QSPI_ADDRSIZE(SIZE) (((SIZE) == ENSPI_INST_L_NONE) || \ + ((SIZE) == ENSPI_INST_L_04BIT) || \ + ((SIZE) == ENSPI_INST_L_08BIT) || \ + ((SIZE) == ENSPI_INST_L_16BIT)) + + +/** @defgroup QSPI_instruction_length + * @{ + */ +#define ENSPI_INST_L_NONE ((uint32_t)0x00000000) +#define ENSPI_INST_L_04BIT ((uint32_t)0x00000100) +#define ENSPI_INST_L_08BIT ((uint32_t)0x00000200) +#define ENSPI_INST_L_16BIT ((uint32_t)0x00000300) +#define IS_QSPI_INSTSIZE(SIZE) (((SIZE) == ENSPI_INST_L_NONE) || \ + ((SIZE) == ENSPI_INST_L_04BIT) || \ + ((SIZE) == ENSPI_INST_L_08BIT) || \ + ((SIZE) == ENSPI_INST_L_16BIT)) + +/** QSPI_data_size : XSPI_CTRL0:DFS **/ +#define DFS_04_BIT XSPI_CTRL0_DFS_4_BIT //((uint32_t)0x00000003U) +#define DFS_08_BIT XSPI_CTRL0_DFS_8_BIT //((uint32_t)0x00000007U) +#define DFS_16_BIT XSPI_CTRL0_DFS_16_BIT //((uint32_t)0x0000000fU) +#define DFS_24_BIT XSPI_CTRL0_DFS_24_BIT //((uint32_t)0x00000017U) +#define DFS_32_BIT XSPI_CTRL0_DFS_32_BIT //((uint32_t)0x0000001fU) +#define IS_XSPI_DATASIZE(DATASIZE) (((DATASIZE) == DFS_04_BIT) || \ + ((DATASIZE) == DFS_08_BIT) || \ + ((DATASIZE) == DFS_16_BIT) || \ + ((DATASIZE) == DFS_24_BIT) || \ + ((DATASIZE) == DFS_32_BIT)) + + +/** @defgroup QSPI_Slave_Select_Toggle_Enable + * @{ + */ +#define SSTE_BIT1 XSPI_CTRL0_SSTE_EN //((uint32_t)0x00004000) +#define SSTE_BIT0 XSPI_CTRL0_SSTE_DISABLE //((uint32_t)0x00000000) +#define IS_XSPI_SSTE_BIT(BIT) (((BIT) == SSTE_BIT1) || \ + ((BIT) == SSTE_BIT0)) + + +/** @defgroup QSPI_Clock_Polarity + * @{ + */ +#define SCPOL_LOW XSPI_CTRL0_SCPOL_LOW //((uint32_t)0x00000000) +#define SCPOL_HIGH XSPI_CTRL0_SCPOL_HIGH //((uint32_t)0x00000200) +#define IS_XSPI_CPOL(CPOL) (((CPOL) == SCPOL_LOW) || \ + ((CPOL) == SCPOL_HIGH)) + +/** @defgroup QSPI_Clock_Phase + * @{ + */ + +#define START_BIT XSPI_CTRL0_SCPH_FIRST_EDGE //((uint32_t)0x00000000) +#define MIDDLE_BIT XSPI_CTRL0_SCPH_SECOND_EDGE //((uint32_t)0x00000100) +#define IS_XSPI_CPHA(CPHA) (((CPHA) == START_BIT) || \ + ((CPHA) == MIDDLE_BIT)) + + +/** @defgroup QSPI_flags_definition + * @{ + */ + +#define XSPI_FLAG_BUSY ((uint32_t)XSPI_STS_BUSY) /* Bit[0] BUSY (Transfer Busy Flag) */ +#define XSPI_FLAG_TFNF ((uint32_t)XSPI_STS_TXFNF) /* Bit[1] TXFNF (Transmit FIFO not Full)*/ +#define XSPI_FLAG_TFE ((uint32_t)XSPI_STS_TXFE) /* Bit[2] TXFE (Transmit FIFO not Empty)*/ +#define XSPI_FLAG_RFNE ((uint32_t)XSPI_STS_RXFNE) /* Bit[3] RXFNE (Receive FIFO not Empty)*/ +#define XSPI_FLAG_RFF ((uint32_t)XSPI_STS_RXFF) /* Bit[4] RXFF (Receive FIFO not Full)*/ +#define XSPI_FLAG_TXE ((uint32_t)XSPI_STS_TXE) /* Bit[5] TXE (Transmit FIFO error)*/ +#define XSPI_FLAG_DCOL ((uint32_t)XSPI_STS_DCERR) /* Bit[6] DCERR (Data Conflict Error)*/ + +#define IS_XSPI_GET_FLAG(FLAG) (((FLAG) == XSPI_FLAG_BUSY) || ((FLAG) == XSPI_FLAG_TFNF) || \ + ((FLAG) == XSPI_FLAG_TFE) || ((FLAG) == XSPI_FLAG_RFNE) || \ + ((FLAG) == XSPI_FLAG_RFF) || ((FLAG) == XSPI_FLAG_TXE) || \ + ((FLAG) == XSPI_FLAG_DCOL)) + + +/** @defgroup QSPI_clock_stretching_capability + * @{ + */ +#define CLK_STRETCH_EN ((uint32_t)XSPI_ENH_CTRL0_CLKSTREN)//Enables clock stretching capability in SPI transfers. +#define CLK_STRETCH_DISABLE ((uint32_t)0x00000000)//Enables clock stretching capability in SPI transfers. +#define IS_XSPI_CLK_SC(SIZE) (((SIZE) == CLK_STRETCH_EN) || \ + ((SIZE) == CLK_STRETCH_DISABLE)) +#define XSPI_DMAReq_Tx 0x02 +#define XSPI_DMAReq_Rx 0x01 +#define IS_XSPI_DMAREQ(REQ) (((REQ) == XSPI_DMAReq_Tx) || \ + ((REQ) == XSPI_DMAReq_Rx)) + + +#define XSPI_DMAATW_1BYTE ((uint32_t)0x00000000) +#define XSPI_DMAATW_2BYTE ((uint32_t)0x00000008) +#define XSPI_DMAATW_4BYTE ((uint32_t)0x00000010) +#define XSPI_DMAATW_8BYTE ((uint32_t)0x00000018) +#define IS_XSPI_DMAATW(ATW) (((ATW) == XSPI_DMAATW_1BYTE) || ((ATW) == XSPI_DMAATW_2BYTE)\ + ((ATW) == XSPI_DMAATW_4BYTE) || ((ATW) == XSPI_DMAATW_8BYTE)) +#define DMA_ADDR_INC ((uint32_t)0x00000040) +#define DMA_ADDR_NINC ((uint32_t)0x00000000) + +#define XSPI_SLV_OUT_DISABLED ((uint32_t)0x1000) //Slave Output is disabled +#define XSPI_SLV_OUT_EN ((uint32_t)0x0000) // Slave Output is enabled + +/** sets the number of data frames to be continuously received by the XSPI :XSPI_CTRL1**/ +#define CTRL1_NDF_CNT 1024 +#define CTRL1_NDF_0 0 +#define CTRL1_NDF_1 1 +#define CTRL1_NDF_8 8 +#define CTRL1_NDF_16 16 +#define CTRL1_NDF_63 63 +#define CTRL1_NDF_127 127 +#define CTRL1_NDF_255 255 +#define IS_XSPI_NDF(NDF) (((NDF) <= 0xFFFF)) + +/** SPI_BaudRate_Prescaler **/ +//Fsclk_out = Fssi_clk/BAUD,BAUD = {SCKDV*2} +#define CLOCK_DIVI_MAX 0XFFFE +#define CLOCK_DIVIDER 0X1f +#define XSPI_SCLKOUT_DISABLE ((uint32_t)0x00000000U) + +#define XSPI_IT_FLAG_TYPE_M ((uint8_t)0x01U) +#define XSPI_IT_FLAG_TYPE_S ((uint8_t)0x02U) +#define XSPI_IT_FLAG_TYPE_R ((uint8_t)0x03U) + +#define XSPI_IT_DONEM ((uint16_t)0X00B5U) +#define XSPI_IT_SPITEM ((uint16_t)0X00A5U) +#define XSPI_IT_AXIEM ((uint16_t)0X0085U) +#define XSPI_IT_TXUIM ((uint16_t)0X0071U) +#define XSPI_IT_XRXOIM ((uint16_t)0X0066U) +#define XSPI_IT_MMCIM ((uint16_t)0X0054U) +#define XSPI_IT_RXFFIM ((uint16_t)0X0045U) +#define XSPI_IT_RXFOIM ((uint16_t)0X0032U) +#define XSPI_IT_RXFUIM ((uint16_t)0X0023U) +#define XSPI_IT_TXFOIM ((uint16_t)0X0011U) +#define XSPI_IT_TXFEIM ((uint16_t)0X0005U) + +#define XSPI_DMAREQ_TX ((uint16_t)0x0002U) +#define XSPI_DMAREQ_RX ((uint16_t)0x0001U) + +#define IS_XSPI_CONFIG_CLEAR_IT(IT) (((IT) == XSPI_IT_DONEM) || ((IT) == XSPI_IT_SPITEM) || \ + ((IT) == XSPI_IT_AXIEM) || ((IT) == XSPI_IT_TXUIM || \ + ((IT) == XSPI_IT_XRXOIM || ((IT) == XSPI_IT_MSTIM) || \ + ((IT) == XSPI_IT_RXFIM || ((IT) == XSPI_IT_RXOIM) || \ + ((IT) == XSPI_IT_RXUIM || ((IT) == XSPI_IT_TXOIM) || \ + ((IT) == XSPI_IT_TXEIM)) + + +/** @defgroup SPI_wati_cycle + * @{ + */ +#define WAIT_CYCLES(X) ((uint32_t)X<<11) +#define ENSPI_WAIT_8CYCLES ((uint32_t)0x00004000) //WAIT_CYCLES +#define ENSPI_WAIT_4CYCLES ((uint32_t)0x00002000) +#define ENSPI_WAIT_2CYCLES ((uint32_t)0x00001000) + +#define NSS_SLECT (0X0F) //(0X01)//Ƭѡ + +/******** Bit definition for XIP_CTRL register ********/ +#define XIPR_PREFETCH_EN ((uint32_t)0x20000000) +#define CONT_XFER_EN ((uint32_t)0x00800000) +#define INST_EN ((uint32_t)0x00400000) +#define DFS_HC_ENABLE ((uint32_t)0x00040000) +#define DFS_HC_DISABLE ((uint32_t)0x00000000) +#define MD_BITS_EN ((uint32_t)0x00001000) + +//xip���ú궨�� +#define XIPR_ADDR_24BIT ((uint32_t)0x00000060) +#define XIPR_ADDR_32BIT ((uint32_t)0x00000080) +#define XIPR_ADDR_48BIT ((uint32_t)0x000000c0) + +#define XIPR_INST_16BIT ((uint32_t)0x00000600) +#define XIPR_INST_8BIT ((uint32_t)0x00000400) +#define XIPR_INST_4BIT ((uint32_t)0x00000200) +#define XIPR_INST_NONE ((uint32_t)0x00000000) + +#define XIPW_ADDR_24BIT ((uint32_t)0x00000060) +#define XIPW_ADDR_32BIT ((uint32_t)0x00000080) +#define XIPW_ADDR_48BIT ((uint32_t)0x000000c0) + +#define XIPW_INST_16BIT ((uint32_t)0x00000300) +#define XIPW_INST_8BIT ((uint32_t)0x00000200) +#define XIPW_INST_4BIT ((uint32_t)0x00000100) +#define XIPW_INST_NONE ((uint32_t)0x00000000) + +#define XIP_WAIT_CYCLES_20 ((uint32_t)0x00028000) +#define XIP_WAIT_CYCLES_8 ((uint32_t)0x00010000) +#define XIP_WAIT_CYCLES_6 ((uint32_t)0x0000c000) + +#define XIPR_TRANS_TYPE_STANDRD ((uint32_t)0x00000000) +#define XIPR_TRANS_TYPE_STANDRD_FRF ((uint32_t)0x00000004) +#define XIPR_TRANS_TYPE_FRF ((uint32_t)0x00000008) + +#define XIPW_TRANS_TYPE_STANDRD ((uint32_t)0x00000000) +#define XIPW_TRANS_TYPE_STANDRD_FRF ((uint32_t)0x00000004) +#define XIPW_TRANS_TYPE_FRF ((uint32_t)0x00000008) + +#define XIPR_DUAL_SPI_FORMAT ((uint32_t)0x00000001) +#define XIPR_QUAD_SPI_FORMAT ((uint32_t)0x00000002) +#define XIPR_OCTAL_SPI_FORMAT ((uint32_t)0x00000003) + +#define XIPW_DUAL_SPI_FORMAT ((uint32_t)0x00000001) +#define XIPW_QUAD_SPI_FORMAT ((uint32_t)0x00000002) +#define XIPW_OCTAL_SPI_FORMAT ((uint32_t)0x00000003) + +#define XIP_MBL_2 ((uint32_t)0x00000000)//XIP mode bit width +#define XIP_MBL_4 ((uint32_t)0x04000000)//XIP mode bit width +#define XIP_MBL_8 ((uint32_t)0x08000000)//XIP mode bit width +#define XIP_MBL_16 ((uint32_t)0x0C000000)//XIP mode bit width + +typedef enum +{ + XSPI_NULL = 0, + XSPI_SUCCESS, +} XSPI_STATUS; +//////////////////////////////////////////////////////////////////////////////////////////////////// +typedef struct +{ + /*XSPI_CTRL0*/ + uint32_t MST; + uint32_t DFS; + uint32_t FRF; //Frame Format Bits[7:6] + uint32_t SCPH; + uint32_t SCPOL; + uint32_t TMOD; + uint32_t SSTE; + uint32_t CFS; + uint32_t SPIFRF; //SPI Frame Format Bits[23:22] + uint32_t WAITCYCLES; + uint32_t INST_L; + uint32_t ADDR_L; + + /*XSPI_CTRL1*/ + uint32_t NDF; + + /*XSPI_MW_CTRL*/ + uint32_t MWMOD; + uint32_t MCDIR; + uint32_t MHSEN; + + /*XSPI_SLAVE_EN*/ + uint32_t SEN; + + /*XSPI_BAUD*/ + uint32_t CLKDIV; + + /*XSPI_TXFT*/ + //uint32_t TXFT; + uint32_t TXFTST; + uint32_t TXFTTEI; + + /*XSPI_RXFT*/ + uint32_t RXFT; + + /*XSPI_RS_DELAY*/ + uint32_t SDCN; + uint32_t SES; + + /*XSPI_ENH_CTRL0*/ + uint32_t ENHANCED_TRANSTYPE; + uint32_t ENHANCED_ADDR_L; + uint32_t ENHANCED_INST_L; + uint32_t ENHANCED_WAITCYCLES; + uint32_t ENHANCED_WRSPIDDREN; + uint32_t ENHANCED_WRINDDREN; + uint32_t ENHANCED_CLKSTREN; + + /*XSPI_DDR_TXDE*/ + uint32_t TXDE; + + /*XSPI_XIP_MODE*/ + uint32_t XIPMDBITS; + + /*XSPI_XIP_INCR_TOC*/ + uint32_t ITOC; + + /*XSPI_XIP_WRAP_TOC*/ + uint32_t WTOC; + + /*XSPI_XIP_CTRL*/ + uint32_t XIP_FRF; + uint32_t XIP_TRANSTYPE; + uint32_t XIP_ADDRL; + uint32_t XIP_INST_L; + uint32_t XIPMDBITS_EN; + uint32_t XIP_WAITCYCLES; + uint32_t XIPDFSHC; + uint32_t XIP_DDREN; + uint32_t XIP_WRINDDREN; + uint32_t XIPINSTEN; + uint32_t XIPCTEN; + uint32_t XIPMBL; + uint32_t XIPPREEN; + + /*XSPI_XIP_TOUT*/ + uint32_t XTOUT; + +} XSPI_InitType; + +enum DDR_SET_TYPE +{ + XSPI_INST_DDR_EN =0,// + XSPI_SPI_DDR_EN =1, + XSPI_INSTANDSPI_DDR_EN, + XIP_READ_INST_DDR_EN, + XIP_READ_IDDR_EN, + XIP_READ_INSTANDSPI_DDR_EN, + XIP_WRITE_INST_DDR_EN, + XIP_WRITE_IDDR_EN, + XIP_WRITE_INSTANDSPI_DDR_EN, +}; + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +void XSPI_DeInit(XSPI_Module* xSPIx); +void XSPI_Init(XSPI_Module* xSPIx, XSPI_InitType* XSPI_InitStruct); +void XSPI_StructInit(XSPI_InitType* XSPI_InitStruct); +void XSPI_Cmd(XSPI_Module* xSPIx, FunctionalState cmd); +void XSPI_XIP_Cmd(XSPI_Module* xSPIx, FunctionalState cmd); +void XSPI_SetTransType(XSPI_Module* xSPIx, uint32_t TransType); +void XSPI_SetWaitCycles(XSPI_Module* xSPIx, uint32_t WAITCYCLES); +void XSPI_SetRXFIFOLevel(XSPI_Module* xSPIx, uint32_t fifo_len); +void XSPI_SetTXFIFOLevel(XSPI_Module* xSPIx, uint32_t fifo_len); +void XSPI_SetTXFIFOStartLevel(XSPI_Module* xSPIx, uint32_t fifo_len); +uint8_t XSPI_GetRXFIFOLevel(XSPI_Module* xSPIx); +uint8_t XSPI_GetTXFIFOLevel(XSPI_Module* xSPIx); +uint32_t XSPI_GetDataPointer(XSPI_Module* xSPIx); +void XSPI_SetTxFifoStartTransferLevel(XSPI_Module* xSPIx,uint16_t Level); +uint32_t XSPI_ReadRxFifoNum(XSPI_Module* xSPIx); +uint32_t XSPI_ReadTxFifoNum(XSPI_Module* xSPIx); +void XSPI_SendData(XSPI_Module* xSPIx, uint32_t SendData); +uint32_t XSPI_ReceiveData(XSPI_Module* xSPIx); +FlagStatus XSPI_GetFlagStatus(XSPI_Module* xSPIx, uint32_t XSPI_FLAG); +uint16_t XSPI_GetINTStatus(XSPI_Module* xSPIx, uint16_t FLAG); +void XSPI_ClearITBit(XSPI_Module* xSPIx, uint16_t XSPI_IT); +void XSPI_ConfigInt(XSPI_Module* xSPIx, uint16_t XSPI_IT, FunctionalState Cmd); +void XSPI_ConfigDMATxLevel(XSPI_Module* xSPIx, uint32_t TxDataLevel); +void XSPI_ConfigDMARxLevel(XSPI_Module* xSPIx, uint32_t RxDataLevel); +void XSPI_EnableDMA(XSPI_Module* xSPIx, uint32_t XSPI_DMAReq, FunctionalState Cmd); +FlagStatus XSPI_GetBusyStatus(XSPI_Module* xSPIx); +FlagStatus XSPI_GetTxDataBusyStatus(XSPI_Module* xSPIx); +FlagStatus XSPI_GetTxDataEmptyStatus(XSPI_Module* xSPIx); +FlagStatus XSPI_GetRxHaveDataStatus(XSPI_Module* xSPIx); +FlagStatus XSPI_GetRxDataFullStatus(XSPI_Module* xSPIx); +FlagStatus XSPI_GetDataConflictErrorStatus(XSPI_Module* xSPIx); +void XSPI_ClrFifo(XSPI_Module* xSPIx); +uint32_t XSPI_GetFifoData(XSPI_Module* xSPIx, uint32_t* pData, uint32_t Len); +void XSPI_SendAndGetWords(XSPI_Module* xSPIx, uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt); +uint32_t XSPI_SendWordAndGetWords(XSPI_Module* xSPIx, uint32_t WrData, uint32_t* pRdData, uint8_t LastRd); +void XSPI_Slave_Enable(XSPI_Module* xSPIx, uint8_t cmdData); +//================ +uint8_t xSPI_Wait_Flag(XSPI_Module* xSPIx,uint32_t flag,uint8_t sta,uint64_t wtime); +uint8_t xSPI_Wait_TransferComplete(XSPI_Module* xSPIx,uint64_t wtime); +void xSPI_TXFifoLevel(XSPI_Module* xSPIx,u16 FifoLevel); +void xSPI_BaudRateSelect(XSPI_Module* xSPIx,uint32_t BAUDR_Value); +void xSPI_RXSampleDelay(XSPI_Module* xSPIx,uint32_t Sampling_Edge,uint32_t SampleDelay); +void SetXspi_InstAddrWaitcycle_phase(XSPI_Module* xSPIx, u32 inst_l, u32 addr_l, u32 wait_cycle); +void SetXspi_TransType(XSPI_Module* xSPIx, u32 type); +void Set_xSPI_DDR(XSPI_Module* xSPIx, u32 set_type); +void xSPI_Clear_RXFIFO(XSPI_Module* xSPIx); +#ifdef __cplusplus +} +#endif + +#endif /*__n32h76x_78x_XSPI_H__ */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/misc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/misc.c new file mode 100644 index 0000000000..401992ebba --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/misc.c @@ -0,0 +1,431 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file misc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "misc.h" + + +/** +*\*\name NVIC_PriorityGroupConfig +*\*\fun Configures the priority grouping: pre-emption priority and subpriority. +*\*\param NVIC_PriorityGroup : +*\*\ - NVIC_PriorityGroup_0 0 bits for pre-emption priority 4 bits for subpriority +*\*\ - NVIC_PriorityGroup_1 1 bits for pre-emption priority 3 bits for subpriority +*\*\ - NVIC_PriorityGroup_2 2 bits for pre-emption priority 2 bits for subpriority +*\*\ - NVIC_PriorityGroup_3 3 bits for pre-emption priority 1 bits for subpriority +*\*\ - NVIC_PriorityGroup_4 4 bits for pre-emption priority 0 bits for subpriority +*\*\return none +**/ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** +*\*\name NVIC_Init +*\*\fun Initializes the NVIC peripheral according to the specified parameters in the NVIC_structure_initializes. +*\*\param NVIC_InitStruct : +*\*\ - NVIC_IRQChannel : +*\*\ - IRQn_Type Interrupt Number Definition +*\*\ if NVIC_PriorityGroup is NVIC_PriorityGroup_0 : +*\*\ - NVIC_IRQChannelPreemptionPriority : +*\*\ - NVIC_PRE_PRIORITY_0 +*\*\ - NVIC_IRQChannelSubPriority : +*\*\ - NVIC_SUB_PRIORITY_0 +*\*\ - NVIC_SUB_PRIORITY_1 +*\*\ - NVIC_SUB_PRIORITY_2 +*\*\ - NVIC_SUB_PRIORITY_3 +*\*\ - NVIC_SUB_PRIORITY_4 +*\*\ - NVIC_SUB_PRIORITY_5 +*\*\ - NVIC_SUB_PRIORITY_6 +*\*\ - NVIC_SUB_PRIORITY_7 +*\*\ - NVIC_SUB_PRIORITY_8 +*\*\ - NVIC_SUB_PRIORITY_9 +*\*\ - NVIC_SUB_PRIORITY_10 +*\*\ - NVIC_SUB_PRIORITY_11 +*\*\ - NVIC_SUB_PRIORITY_12 +*\*\ - NVIC_SUB_PRIORITY_13 +*\*\ - NVIC_SUB_PRIORITY_14 +*\*\ - NVIC_SUB_PRIORITY_15 +*\*\ if NVIC_PriorityGroup is NVIC_PriorityGroup_1 : +*\*\ - NVIC_IRQChannelPreemptionPriority : +*\*\ - NVIC_PRE_PRIORITY_0 +*\*\ - NVIC_PRE_PRIORITY_1 +*\*\ - NVIC_IRQChannelSubPriority : +*\*\ - NVIC_SUB_PRIORITY_0 to NVIC_SUB_PRIORITY_7 +*\*\ if NVIC_PriorityGroup is NVIC_PriorityGroup_2 : +*\*\ - NVIC_IRQChannelPreemptionPriority : +*\*\ - NVIC_PRE_PRIORITY_0 to NVIC_PRE_PRIORITY_3 +*\*\ - NVIC_IRQChannelSubPriority : +*\*\ - NVIC_SUB_PRIORITY_0 to NVIC_SUB_PRIORITY_3 +*\*\ if NVIC_PriorityGroup is NVIC_PriorityGroup_3 : +*\*\ - NVIC_IRQChannelPreemptionPriority : +*\*\ - NVIC_PRE_PRIORITY_0 to NVIC_PRE_PRIORITY_7 +*\*\ - NVIC_IRQChannelSubPriority : +*\*\ - NVIC_SUB_PRIORITY_0 +*\*\ - NVIC_SUB_PRIORITY_1 +*\*\ if NVIC_PriorityGroup is NVIC_PriorityGroup_4 : +*\*\ - NVIC_IRQChannelPreemptionPriority : +*\*\ - NVIC_PRE_PRIORITY_0 +*\*\ - NVIC_PRE_PRIORITY_1 +*\*\ - NVIC_PRE_PRIORITY_2 +*\*\ - NVIC_PRE_PRIORITY_3 +*\*\ - NVIC_PRE_PRIORITY_4 +*\*\ - NVIC_PRE_PRIORITY_5 +*\*\ - NVIC_PRE_PRIORITY_6 +*\*\ - NVIC_PRE_PRIORITY_7 +*\*\ - NVIC_PRE_PRIORITY_8 +*\*\ - NVIC_PRE_PRIORITY_9 +*\*\ - NVIC_PRE_PRIORITY_10 +*\*\ - NVIC_PRE_PRIORITY_11 +*\*\ - NVIC_PRE_PRIORITY_12 +*\*\ - NVIC_PRE_PRIORITY_13 +*\*\ - NVIC_PRE_PRIORITY_14 +*\*\ - NVIC_PRE_PRIORITY_15 +*\*\ - NVIC_IRQChannelSubPriority : +*\*\ - NVIC_SUB_PRIORITY_0 +*\*\ - NVIC_IRQChannelCmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void NVIC_Init(NVIC_InitType* NVIC_InitStruct) +{ + uint32_t tmppriority; + uint32_t tmppre; + uint32_t tmpsub = 0x0FU; + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700U - ((SCB->AIRCR) & (uint32_t)0x700U)) >> 0x08U; + tmppre = (0x4U - tmppriority) & ((uint32_t)0x07U); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = (uint8_t)tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05U] = (uint32_t)0x01U + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1FU); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 + << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** +*\*\name NVIC_SetVectorTable +*\*\fun Sets the vector table location and Offset. +*\*\param NVIC_vecter_table specifies if the vector table is in RAM or FLASH memory. +*\*\ This parameter can be one of the following values: +*\*\ - NVIC_VectTab_RAM +*\*\ - NVIC_VectTab_FLASH +*\*\param offset Vector Table base offset field. This value must be a multiple of 0x200. +*\*\return none +**/ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80U); +} + + +/** +*\*\name NVIC_SystemLPConfig +*\*\fun Selects the condition for the system to enter low power mode. +*\*\param LowPowerMode Specifies the new mode for the system to enter low power mode. +*\*\ This parameter can be one of the following values: +*\*\ - NVIC_LP_SEVONPEND +*\*\ - NVIC_LP_SLEEPDEEP +*\*\ - NVIC_LP_SLEEPONEXIT +*\*\param - Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** +*\*\name SysTick_CLKSourceConfig +*\*\fun Configures the SysTick clock source. +*\*\param SysTick_CLKSource : +*\*\ - SysTick_CLKSource_HCLK_Div8 External clock selected as SysTick clock source. +*\*\ - SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source. +*\*\return none +**/ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + + + +#if (__MPU_PRESENT == 1) + + +/** +*\*\name MPU_Disable +*\*\fun Disables the MPU. +*\*\return none +**/ +void MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + + +/** +*\*\name MPU_Enable +*\*\fun Enables the MPU. +*\*\param MPU_Control : + * - MPU_HFNMI_PRIVDEF_NONE + * - MPU_HARDFAULT_NMI + * - MPU_PRIVILEGED_DEFAULT + * - MPU_HFNMI_PRIVDEF +*\*\return none +**/ +void MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + + +/** +*\*\name MPU_ConfigRegion +*\*\fun Initializes and configures the Region and the memory to be protected. +*\*\param MPU_Init : +*\*\ - DisableExec +*\*\ - MPU_INSTRUCTION_ACCESS_ENABLE +*\*\ - MPU_INSTRUCTION_ACCESS_DISABLE +*\*\ - AccessPermission +*\*\ - MPU_REGION_NO_ACCESS +*\*\ - MPU_REGION_PRIV_RW +*\*\ - MPU_REGION_PRIV_RW_URO +*\*\ - MPU_REGION_FULL_ACCESS +*\*\ - MPU_REGION_PRIV_RO +*\*\ - MPU_REGION_PRIV_RO_URO +*\*\ - TypeExtField +*\*\ - MPU_TEX_LEVEL0 +*\*\ - MPU_TEX_LEVEL1 +*\*\ - MPU_TEX_LEVEL2 +*\*\ - IsShareable +*\*\ - MPU_ACCESS_SHAREABLE +*\*\ - MPU_ACCESS_NOT_SHAREABLE +*\*\ - IsCacheable +*\*\ - MPU_ACCESS_CACHEABLE +*\*\ - MPU_ACCESS_NOT_CACHEABLE +*\*\ - IsBufferable +*\*\ - MPU_ACCESS_BUFFERABLE +*\*\ - MPU_ACCESS_NOT_BUFFERABLE +*\*\ - SubRegionDisable : +*\*\ - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF +*\*\ - SubRegionDisable +*\*\ - MPU_REGION_SIZE_32B +*\*\ - MPU_REGION_SIZE_64B +*\*\ - MPU_REGION_SIZE_128B +*\*\ - MPU_REGION_SIZE_256B +*\*\ - MPU_REGION_SIZE_512B +*\*\ - MPU_REGION_SIZE_1KB +*\*\ - MPU_REGION_SIZE_2KB +*\*\ - MPU_REGION_SIZE_4KB +*\*\ - MPU_REGION_SIZE_8KB +*\*\ - MPU_REGION_SIZE_16KB +*\*\ - MPU_REGION_SIZE_32KB +*\*\ - MPU_REGION_SIZE_64KB +*\*\ - MPU_REGION_SIZE_128KB +*\*\ - MPU_REGION_SIZE_256KB +*\*\ - MPU_REGION_SIZE_512KB +*\*\ - MPU_REGION_SIZE_1MB +*\*\ - MPU_REGION_SIZE_2MB +*\*\ - MPU_REGION_SIZE_4MB +*\*\ - MPU_REGION_SIZE_8MB +*\*\ - MPU_REGION_SIZE_16MB +*\*\ - MPU_REGION_SIZE_32MB +*\*\ - MPU_REGION_SIZE_64MB +*\*\ - MPU_REGION_SIZE_128MB +*\*\ - MPU_REGION_SIZE_256MB +*\*\ - MPU_REGION_SIZE_512MB +*\*\ - MPU_REGION_SIZE_1GB +*\*\ - MPU_REGION_SIZE_2GB +*\*\ - MPU_REGION_SIZE_4GB +*\*\return none +**/ +void MPU_ConfigRegion(MPU_Region_InitType *MPU_Init) +{ + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != 0UL) + { + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} + +#endif + + +/** +*\*\name CopyVectTable. +*\*\fun Copy the vector table from flash to TCM. +*\*\param SrcAddr none +*\*\param SrcAddr none +*\*\param size : the size of VECTABLE +*\*\return none +**/ +void CopyVectTable(uint32_t SrcAddr, uint32_t DesAddr, uint32_t size) +{ + uint32_t i; + volatile uint32_t* pSrcVect = (uint32_t*)(SrcAddr); + volatile uint32_t* pDestVect = (uint32_t*)(DesAddr); + uint32_t numVECT = (size / 4); + for(i = 0; i < numVECT; i++) + { + pDestVect[i] = pSrcVect[i]; + } + #ifndef CORE_CM4 + pDestVect[15] = pSrcVect[250]; + #endif + + SCB->VTOR = DesAddr; + __ISB(); + __DSB(); +} + + +#if defined(DUAL_CORE) +/** +*\*\name Get_CurrentCPU +*\*\fun Returns the current CPU. +*\*\param none +*\*\return CPU ID +**/ +uint32_t Get_CurrentCPU(void) +{ + if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U) + { + return CM7_CPU; + } + else + { + return CM4_CPU; + } +} +#else +/** +*\*\name Get_CurrentCPU +*\*\fun Returns the current CPU. +*\*\param none +*\*\return CPU ID +**/ +uint32_t Get_CurrentCPU(void) +{ + return CM7_CPU; +} + +#endif /*DUAL_CORE*/ + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_adc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_adc.c new file mode 100644 index 0000000000..35c523d132 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_adc.c @@ -0,0 +1,2669 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_adc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_adc.h" +#include "n32h76x_78x_rcc.h" + + +/* bit data handler */ +#define BIT_JUDGE_AND_HANDLER(IS_ENABLE, BIT_MASK) (((IS_ENABLE) != DISABLE ) ? (BIT_MASK) : (0x00000000U)) + +#define CTRL1_CLR_MASK ((uint32_t)0x0000F801U) +#define CTRL2_CLR_MASK ((uint32_t)0xFF000872U) +#define CTRL3_CLR_MASK ((uint32_t)0x00000002U) +#define RSEQ1_CLR_MASK ((uint32_t)0x00007C00U) + +#define ALL_ADC_ENALBE_MASK ((uint32_t)0x00001E00U) +#define ADCBUF_CTRL ((uint32_t)0x40010000U + 0x4C) + +///** ADC Driving Functions Declaration **/ +//static ErrorStatus ADC_WriteDataIntoInternalReg(ADC_Module* ADCx, uint8_t Addr, uint8_t Data); +//static ErrorStatus ADC_ReadDataFromInternalReg(ADC_Module* ADCx, uint8_t Addr, uint16_t *ReadOutData); + + + +/** +*\*\name ADC_DeInit. +*\*\fun Reset the ADC registers. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none +**/ +void ADC_DeInit(ADC_Module* ADCx) +{ + if (ADCx == ADC1) + { + RCC_EnableAHB1PeriphReset1(RCC_AHB1_PERIPHRST_ADC1); + } + else if (ADCx == ADC2) + { + RCC_EnableAHB1PeriphReset4(RCC_AHB1_PERIPHRST_ADC2); + } + else if (ADCx == ADC3) + { + RCC_EnableAHB1PeriphReset4(RCC_AHB1_PERIPHRST_ADC3); + } + else + { + /*no process*/ + } +} + +/** +*\*\name ADC_Init. +*\*\fun Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_InitStruct : +*\*\ - WorkMode +*\*\ - ADC_WORKMODE_INDEPENDENT +*\*\ - ADC_WORKMODE_DUAL_REG_INJECT_SIMULT +*\*\ - ADC_WORKMODE_DUAL_REG_SIMULT_ALTER_TRIG +*\*\ - ADC_WORKMODE_DUAL_INJ_SIMULT_INTERL +*\*\ - ADC_WORKMODE_DUAL_INJ_SIMULT +*\*\ - ADC_WORKMODE_DUAL_REG_SIMULT +*\*\ - ADC_WORKMODE_DUAL_INTERL +*\*\ - ADC_WORKMODE_DUAL_ALTER_TRIG +*\*\ - ADC_WORKMODE_TRIPPLE_REG_INJECT_SIMULT +*\*\ - ADC_WORKMODE_TRIPPLE_REG_SIMULT_ALTER_TRIG +*\*\ - ADC_WORKMODE_TRIPPLE_INJ_SIMULT_INTERL +*\*\ - ADC_WORKMODE_TRIPPLE_INJ_SIMULT +*\*\ - ADC_WORKMODE_TRIPPLE_REG_SIMULT +*\*\ - ADC_WORKMODE_TRIPPLE_INTERL +*\*\ - ADC_WORKMODE_TRIPPLE_ALTER_TRIG +*\*\ - MultiChEn +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - ContinueConvEn +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - ExtTrigSelect +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC1 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC3 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_CC1 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_CC3 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC1 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC3 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM4_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM4_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB1_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB2_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB3_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMA1_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB1_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB2_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB3_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMA1_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM1_TRGO1 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM1_TRGO3 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM2_TRGO1 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM2_TRGO3 +*\*\ - ADC_EXT_TRIG_REG_CONV_EXT_INT0_15 +*\*\ - ADC_EXT_TRIG_REG_CONV_SOFTWARE +*\*\ - DataTransferMode +*\*\ - ADC_REG_DR_TRANSFER +*\*\ - ADC_REG_DSMU_TRANSFER +*\*\ - ADC_REG_DMA_TRANSFER +*\*\ - DatAlign +*\*\ - ADC_DAT_ALIGN_R +*\*\ - ADC_DAT_ALIGN_L +*\*\ - Resolution +*\*\ - ADC_DATA_RES_12BIT +*\*\ - ADC_DATA_RES_10BIT +*\*\ - ChsNumber: This parameter must be between 1 to 20. +*\*\return none +**/ +void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct) +{ + uint32_t tempreg1; + uint8_t tempreg2; + /*---------------------------- ADCx CTRL1 Configuration -----------------*/ + /* Get the ADCx CTRL1 value */ + tempreg1 = ADCx->CTRL1; + /* Clear MUTIMODE and SCANMD bits */ + tempreg1 &= (~CTRL1_CLR_MASK); + /* Configure ADCx: Muti mode and scan conversion mode */ + /* Set MUTIMOD bits according to WorkMode value */ + /* Set SCANMD bit according to MultiChEn value */ + tempreg1 |= (uint32_t)(ADC_InitStruct->WorkMode | (uint32_t)ADC_InitStruct->MultiChEn ); + /* Write to ADCx CTRL1 */ + ADCx->CTRL1 = tempreg1; + + /*---------------------------- ADCx CTRL2 Configuration -----------------*/ + /* Get the ADCx CTRL2 value */ + tempreg1 = ADCx->CTRL2; + /* Clear CTU, ALIG ,DMNGT, EXTPRSEL and EXTRSEL bits */ + tempreg1 &= (~CTRL2_CLR_MASK); + /* Set ALIGN bit according to DatAlign value */ + /* Set EXTSEL and EXTPRSEL bits according to ExtTrigSelect value */ + /* Set CTU bit according to ContinueConvEn value */ + /* Set DMNGT and MDSMU bit according to DataTransferMode value */ + tempreg1 |= (uint32_t)(ADC_InitStruct->DatAlign | ADC_InitStruct->ExtTrigSelect + | ((uint32_t)ADC_InitStruct->ContinueConvEn << 1) | ADC_InitStruct->DataTransferMode); + /* Write to ADCx CTRL2 */ + ADCx->CTRL2 = tempreg1; + + /*---------------------------- ADCx CTRL3 Configuration -----------------*/ + /* Get the ADCx CTRL3 value */ + tempreg1 = ADCx->CTRL3; + /* Clear RES bits */ + tempreg1 &= (~CTRL3_CLR_MASK); + /* Configure ADCx resolution */ + /* Set RES bits according to Resolution value */ + tempreg1 |= ADC_InitStruct->Resolution; + /* Write to ADCx CTRL3 */ + ADCx->CTRL3 = tempreg1; + + /*---------------------------- ADCx RSEQ1 Configuration -----------------*/ + /* Get the ADCx RSEQ1 value */ + tempreg1 = ADCx->RSEQ1; + /* Clear L bits */ + tempreg1 &= (~RSEQ1_CLR_MASK); + /* Configure ADCx: regular channel sequence length */ + /* Set LEN bits according to ChsNumber value */ + tempreg2 = (uint8_t)(ADC_InitStruct->ChsNumber - 1U); + tempreg1 |= (uint32_t)tempreg2 << 10U; + /* Write to ADCx RSEQ1 */ + ADCx->RSEQ1 = tempreg1; +} + +/** +*\*\name ADC_InitStruct. +*\*\fun Fills all ADC_InitStruct member with default value. +*\*\param ADC_InitStruct : +*\*\ - WorkMode +*\*\ - MultiChEn +*\*\ - ContinueConvEn +*\*\ - ExtTrigSelect +*\*\ - DatAlign +*\*\ - ChsNumber +*\*\ - Resolution +*\*\return none +**/ +void ADC_InitStruct(ADC_InitType* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the WorkMode member */ + ADC_InitStruct->WorkMode = ADC_WORKMODE_INDEPENDENT; + /* initialize the MultiChEn member */ + ADC_InitStruct->MultiChEn = DISABLE; + /* Initialize the ContinueConvEn member */ + ADC_InitStruct->ContinueConvEn = DISABLE; + /* Initialize the ExtTrigSelect member */ + ADC_InitStruct->ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_ATIM1_CC1; + /* Initialize the DataTransferMode member */ + ADC_InitStruct->DataTransferMode = ADC_REG_DR_TRANSFER; + /* Initialize the DatAlign member */ + ADC_InitStruct->DatAlign = ADC_DAT_ALIGN_R; + /* Initialize the ChsNumber member */ + ADC_InitStruct->ChsNumber = 1; + /* Initialize the Resolution member */ + ADC_InitStruct->Resolution = ADC_DATA_RES_12BIT; +} + + +/** +*\*\name ADC_Enable. +*\*\fun Configures the specified ADC enable or disable. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the AD_ON bit to wake up the ADC from power down mode */ + ADCx->CTRL2 |= ADC_ON_EN_MASK; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CTRL2 &= (~ADC_ON_EN_MASK); + } +} +/** +*\*\name ADC_SetDMATransferMode. +*\*\fun Select the DMA mode for data transmission in multi-channels conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param DMAMode : +*\*\ - ADC_MULTI_REG_DMA_DISABLE :DMA Mode 0 +*\*\ - ADC_MULTI_REG_DMA_EACH_ADC :DMA Mode 1 +*\*\ - ADC_MULTI_REG_DMA_LIMIT_RES12_10B :DMA Mode 2 +*\*\return none +**/ +void ADC_SetDMATransferMode(ADC_Module *ADCx, uint32_t DMAMode) +{ + __IO uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->CTRL2; + /* Clear the old DMA mode value */ + tempreg &= (~ADC_MULTI_REG_DMA_MODE_MASK); + /* Set the DMA mode */ + tempreg |= DMAMode; + /* Store the new register value */ + ADCx->CTRL2 = tempreg; +} +/** +*\*\name ADC_EnableMutiAdcDSMU. +*\*\fun Configures Multi-adc DSMU mode for the specified ADC enable or disable. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableMutiAdcDSMU(ADC_Module *ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable multi-adc DSMU mode */ + ADCx->CTRL2 |= ADC_MUTI_ADC_DSMU_MASK; + } + else + { + /* Disable multi-adc DSMU mode */ + ADCx->CTRL2 &= (~ADC_MUTI_ADC_DSMU_MASK); + } +} +/** +*\*\name ADC_CalibrationOperation. +*\*\fun Starts the selected ADC differential or signal mode calibration process. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none +**/ +void ADC_CalibrationOperation(ADC_Module* ADCx) +{ + /* Set the flag of starting of calibration */ + ADCx->CTRL2 |= ADC_CALI_EN_MASK; +} + + +/** +*\*\name ADC_GetCalibrationStatus. +*\*\fun Gets the selected ADC calibration status. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return FlagStatus: +*\*\ - RESET : ADCx calibration is finished; +*\*\ - SET : ADCx calibration is not finished; +**/ +FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus; + + /* Check the status of CAL bit */ + if ((ADCx->CTRL2 & ADC_CALI_EN_MASK) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + + /* Return the CAL bit status */ + return bitstatus; +} +/** +*\*\name ADC_SetMultiTwoSamplingDelay. +*\*\fun Set ADC multimode delay between 2 sampling phases. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param MultiTwoSamplingDelay +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_1 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_2 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_3 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_4 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_5 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_6 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_7 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_8 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_9 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_10 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_11 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_12 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_13 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_14 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_15 +*\*\ - ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_16 +*\*\return none +*\*\note 1.When ADC resolution is 12, the maximum of the parameter 'MultiTwoSamplingDelay' \ +*\*\ can be set ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_12. +*\*\ 2.When ADC resolution is 10, the maximum of the parameter 'MultiTwoSamplingDelay' \ +*\*\ can be set ADC_ADC_MULTI_TWOSMP_DELAY_CYCLE_10. +**/ +void ADC_SetMultiTwoSamplingDelay(ADC_Module* ADCx, uint32_t MultiTwoSamplingDelay) +{ + __IO uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->DLYSMP; + /* Clear the old delay number */ + tempreg &= (~ADC_ADC_MULTI_TWOSMP_DELAY_MASK); + /* Set the delay number */ + tempreg |= MultiTwoSamplingDelay; + /* Store the new register value */ + ADCx->DLYSMP = tempreg; +} +/** +*\*\name ADC_SetIndenpentSamplingDelay. +*\*\fun Set ADC delay sampling phases in indenpent mode. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param MultiTwoSamplingDelay +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_1 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_2 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_3 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_4 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_5 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_6 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_7 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_8 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_9 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_10 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_11 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_12 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_13 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_14 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_15 +*\*\ - ADC_INDENPENT_TWOSMP_DELAY_CYCLE_16 +*\*\return none +**/ +void ADC_SetIndenpentSamplingDelay(ADC_Module* ADCx, uint32_t IndenpentSamplingDelay) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->DLYSMP; + /* Clear the old delay number */ + tempreg &= (~ADC_INDENPENT_TWOSMP_DELAY_MASK); + /* Set the delay number */ + tempreg |= IndenpentSamplingDelay; + /* Store the new register value */ + ADCx->DLYSMP = tempreg; +} +/** +*\*\name ADC_ConfigDiscModeChannelCount. +*\*\fun Configures the discontinuous numbers for the selected ADC regular +*\*\ group channels. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Number : specifies the discontinuous mode regular channel + * count value. This number must be range form 1 to 8. +*\*\return none +**/ +void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number) +{ + __IO uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->CTRL1; + /* Clear the old discontinuous mode channel count */ + tempreg &= (~ADC_DISC_NUM_MASK); + /* Set the discontinuous mode channel count */ + tempreg |= (((uint32_t)Number - 1UL) << 8U); + /* Store the new register value */ + ADCx->CTRL1 = tempreg; +} + +/** +*\*\name ADC_EnableAutoInjectedConv. +*\*\fun Enables or disables the selected ADC automatic injected group +*\*\ conversion after regular one +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 |= ADC_JAUTO_EN_MASK; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CTRL1 &= (~ADC_JAUTO_EN_MASK); + } +} + +/** +*\*\name ADC_EnableDiscMode. +*\*\fun Enables or disables the discontinuous mode on regular group +*\* channel for the specified ADC. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 |= ADC_DISC_REG_EN_MASK; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CTRL1 &= (~ADC_DISC_REG_EN_MASK); + } +} + +/** +*\*\name ADC_EnableInjectedDiscMode. +*\*\fun Enables or disables the discontinuous mode on injected group +*\* channel for the specified ADC. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 |= ADC_DISC_INJ_EN_MASK; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CTRL1 &= (~ADC_DISC_INJ_EN_MASK); + } +} + +/** +*\*\name ADC_ConfigRegularChannel. +*\*\fun Configures for the selected ADC regular channel its corresponding +*\*\ rank in the sequencer and its sample time. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_Channel : +*\*\ - ADC_CH_0 : ADC Channel0 selected +*\*\ - ADC_CH_1 : ADC Channel1 selected +*\*\ - ADC_CH_2 : ADC Channel2 selected +*\*\ - ADC_CH_3 : ADC Channel3 selected +*\*\ - ADC_CH_4 : ADC Channel4 selected +*\*\ - ADC_CH_5 : ADC Channel5 selected +*\*\ - ADC_CH_6 : ADC Channel6 selected +*\*\ - ADC_CH_7 : ADC Channel7 selected +*\*\ - ADC_CH_8 : ADC Channel8 selected +*\*\ - ADC_CH_9 : ADC Channel9 selected +*\*\ - ADC_CH_10 : ADC Channel10 selected +*\*\ - ADC_CH_11 : ADC Channel11 selected +*\*\ - ADC_CH_12 : ADC Channel12 selected +*\*\ - ADC_CH_13 : ADC Channel13 selected +*\*\ - ADC_CH_14 : ADC Channel14 selected +*\*\ - ADC_CH_15 : ADC Channel15 selected +*\*\ - ADC_CH_16 : ADC Channel16 selected +*\*\ - ADC_CH_17 : ADC Channel17 selected +*\*\ - ADC_CH_18 : ADC Channel18 selected +*\*\ - ADC_CH_19 : ADC Channel19 selected +*\*\param Rank : The rank in the regular group sequencer. This parameter must be between 1 to 20. +*\*\param ADC_SampleTime : The sample time value to be set for the selected channel. +*\*\ - ADC_SAMP_TIME_CYCLES_1 +*\*\ - ADC_SAMP_TIME_CYCLES_2 +*\*\ - ADC_SAMP_TIME_CYCLES_3 +*\*\ - ADC_SAMP_TIME_CYCLES_4 +*\*\ - ADC_SAMP_TIME_CYCLES_5 +*\*\ - ADC_SAMP_TIME_CYCLES_6 +*\*\ - ADC_SAMP_TIME_CYCLES_7 +*\*\ - ADC_SAMP_TIME_CYCLES_10 +*\*\ - ADC_SAMP_TIME_CYCLES_13 +*\*\ - ADC_SAMP_TIME_CYCLES_17 +*\*\ - ADC_SAMP_TIME_CYCLES_24 +*\*\ - ADC_SAMP_TIME_CYCLES_32 +*\*\ - ADC_SAMP_TIME_CYCLES_83 +*\*\ - ADC_SAMP_TIME_CYCLES_93 +*\*\ - ADC_SAMP_TIME_CYCLES_215 +*\*\ - ADC_SAMP_TIME_CYCLES_397 +*\*\return none +**/ +void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tempreg1, tempreg2; + __IO uint16_t index; + + if (ADC_Channel > ADC_CH_15) /* if ADC_CH_16 ... ADC_CH_19 is selected */ + { + /* Get the old register value */ + tempreg1 = ADCx->SAMPT3; + /* Calculate the mask to clear */ + tempreg2 = ADC_SAMP_TIME_CYCLES_MASK << (4U * (ADC_Channel - 16U)); + /* Clear the old channel sample time */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = ((uint32_t)ADC_SampleTime) << (4U * (ADC_Channel - 16U)); + /* Set the new channel sample time */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->SAMPT3 = tempreg1; + } + else if (ADC_Channel > ADC_CH_7) /* if ADC_CH_8 ... ADC_CH_15 is selected */ + { + /* Get the old register value */ + tempreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tempreg2 = ADC_SAMP_TIME_CYCLES_MASK << (4U * (ADC_Channel - 8U)); + /* Clear the old channel sample time */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = ((uint32_t)ADC_SampleTime) << (4U * (ADC_Channel - 8U)); + /* Set the new channel sample time */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tempreg1; + } + else /* if ADC_CH_0 ... ADC_CH_7 is selected */ + { + /* Get the old register value */ + tempreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tempreg2 = ADC_SAMP_TIME_CYCLES_MASK << (4U * (ADC_Channel)); + /* Clear the old channel sample time */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = ((uint32_t)ADC_SampleTime) << (4U * (ADC_Channel)); + /* Set the new channel sample time */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tempreg1; + } + + if (Rank < 7U) /* For Rank 1 to 6 */ + { + /* Get the old register value */ + tempreg1 = ADCx->RSEQ4; + /* Calculate the mask to clear */ + tempreg2 = ADC_RESQ_SEQ_MASK << (5U * (Rank - 1U)); + /* Clear the old SQx bits for the selected rank */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = (uint32_t)ADC_Channel << (5U * (Rank - 1U)); + /* Set the SQx bits for the selected rank */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->RSEQ4 = tempreg1; + } + else if (Rank < 13U) /* For Rank 7 to 12 */ + { + /* Get the old register value */ + tempreg1 = ADCx->RSEQ3; + /* Calculate the mask to clear */ + tempreg2 = ADC_RESQ_SEQ_MASK << (5U * (Rank - 7U)); + /* Clear the old SQx bits for the selected rank */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = (uint32_t)ADC_Channel << (5U * (Rank - 7U)); + /* Set the SQx bits for the selected rank */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->RSEQ3 = tempreg1; + } + else if (Rank < 19U) /* For Rank 13 to 18 */ + { + /* Get the old register value */ + tempreg1 = ADCx->RSEQ2; + /* Calculate the mask to clear */ + tempreg2 = ADC_RESQ_SEQ_MASK << (5U * (Rank - 13U)); + /* Clear the old SQx bits for the selected rank */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = (uint32_t)ADC_Channel << (5U * (Rank - 13U)); + /* Set the SQx bits for the selected rank */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->RSEQ2 = tempreg1; + } + else /* For Rank 19 to 20 */ + { + /* Get the old register value */ + tempreg1 = ADCx->RSEQ1; + /* Calculate the mask to clear */ + tempreg2 = ADC_RESQ_SEQ_MASK << (5U * (Rank - 19U)); + /* Clear the old SQx bits for the selected rank */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = (uint32_t)ADC_Channel << (5U * (Rank - 19U)); + /* Set the SQx bits for the selected rank */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->RSEQ1 = tempreg1; + } + /*delay 4*ADC_CLK at least for synchronizing*/ + for(index = 0;index<24;index++) + { + __NOP(); + } +} + +/** +*\*\name ADC_GetDat. +*\*\fun Get the last ADCx conversion result data for regular channel +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return The Data conversion value. +**/ +uint16_t ADC_GetDat(ADC_Module* ADCx) +{ + /* Return the selected ADC conversion value */ + return (uint16_t)ADCx->DAT; +} + +/** +*\*\name ADC_GetMutiModeConversionDat. +*\*\fun Get the last ADC conversion result data in dual-ADC or tripple-ADC mode. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return The Data conversion value in dual-ADC or tripple-ADC mode. +**/ +uint32_t ADC_GetMutiModeConversionDat(ADC_Module* ADCx) +{ + return (uint32_t)ADC1->DAT; +} +/** +*\*\name ADC_SetRegularTriggerEdge. +*\*\fun Set ADCx group regular conversion trigger polarity. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ExternalRegularTriggerEdge : +*\*\ - ADC_REG_TRIG_EXT_SOFTWARE +*\*\ - ADC_REG_TRIG_EXT_RISING +*\*\ - ADC_REG_TRIG_EXT_FALLING +*\*\ - ADC_REG_TRIG_EXT_RISINGFALLING +*\*\return none +**/ +void ADC_SetRegularTriggerEdge(ADC_Module* ADCx, uint32_t ExternalRegularTriggerEdge) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->CTRL2; + /* Clear the old external trigger polarity selection for regular group */ + tempreg &= (~ADC_REG_TRIG_EXT_MASK); + /* Set the external trigger polarity selection for regular group */ + tempreg |= ExternalRegularTriggerEdge; + /* Store the new register value */ + ADCx->CTRL2 = tempreg; +} +/** +*\*\name ADC_SetInjectTriggerEdge. +*\*\fun Set ADCx group injected conversion trigger polarity. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ExternalInjectTriggerEdge : +*\*\ - ADC_INJ_TRIG_EXT_SOFTWARE +*\*\ - ADC_INJ_TRIG_EXT_RISING +*\*\ - ADC_INJ_TRIG_EXT_FALLING +*\*\ - ADC_INJ_TRIG_EXT_RISINGFALLING +*\*\return none +**/ +void ADC_SetInjectTriggerEdge(ADC_Module* ADCx, uint32_t ExternalInjectTriggerEdge) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->CTRL2; + /* Clear the old external trigger polarity selection for injected group */ + tempreg &= (~ADC_INJ_TRIG_EXT_MASK); + /* Set the external trigger polarity selection for injected group */ + tempreg |= ExternalInjectTriggerEdge; + /* Store the new register value */ + ADCx->CTRL2 = tempreg; +} +/** +*\*\name ADC_ConfigExternalTrigRegularConv. +*\*\fun Configures the ADCx external trigger source for regular channels conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_ExternalTrigRegularConv : +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC1 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC3 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_CC1 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_CC3 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM1_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC1 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC3 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM2_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM4_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM3_TRGO2 +*\*\ - ADC_EXT_TRIG_REG_CONV_ATIM4_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB1_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB2_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB3_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMA1_TRGO +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB1_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB2_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMB3_CC2 +*\*\ - ADC_EXT_TRIG_REG_CONV_GTIMA1_CC4 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM1_TRGO1 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM1_TRGO3 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM2_TRGO1 +*\*\ - ADC_EXT_TRIG_REG_CONV_SHRTIM2_TRGO3 +*\*\ - ADC_EXT_TRIG_REG_CONV_EXT_INT0_15 +*\*\ - ADC_EXT_TRIG_REG_CONV_SOFTWARE +*\*\return none +**/ +void ADC_ConfigExternalTrigRegularConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigRegularConv) +{ + uint32_t tempreg; + + /* Get the old register value */ + tempreg = ADCx->CTRL2; + /* Clear the old external event selection for regular group */ + tempreg &= (~ADC_EXT_TRIG_REG_CONV_MASK); + /* Set the external event selection for regular group */ + tempreg |= ADC_ExternalTrigRegularConv; + /* Store the new register value */ + ADCx->CTRL2 = tempreg; +} +/** +*\*\name ADC_ConfigExternalTrigInjectedConv. +*\*\fun Configures the ADCx external trigger source for injected channels conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_ExternalTrigInjecConv : +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM1_CC1 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM1_CC2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM1_CC3 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM1_CC4 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM1_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM2_CC1 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM2_CC2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM2_CC3 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM1_TRGO2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM2_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM3_CC1 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM3_CC2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM3_CC3 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM3_CC4 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM2_TRGO2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM3_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM4_TRGO2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM3_TRGO2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_ATIM4_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMB1_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMB2_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMB3_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMA1_TRGO +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMB1_CC1 +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMB2_CC4 +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMB3_CC1 +*\*\ - ADC_EXT_TRIG_INJ_CONV_GTIMA1_CC3 +*\*\ - ADC_EXT_TRIG_INJ_CONV_SHRTIM1_TRGO2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_SHRTIM1_TRGO4 +*\*\ - ADC_EXT_TRIG_INJ_CONV_SHRTIM2_TRGO2 +*\*\ - ADC_EXT_TRIG_INJ_CONV_SHRTIM2_TRGO4 +*\*\ - ADC_EXT_TRIG_INJ_CONV_EXT_INT0_15 +*\*\ - ADC_EXT_TRIG_INJ_CONV_SOFTWARE +*\*\return none +**/ +void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tempreg; + + /* Get the old register value */ + tempreg = ADCx->CTRL2; + /* Clear the old external event selection for injected group */ + tempreg &= (~ADC_EXT_TRIG_INJ_CONV_MASK); + /* Set the external event selection for injected group */ + tempreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CTRL2 = tempreg; +} + +/** +*\*\name ADC_StartInjectedConv. +*\*\fun Enables or disables the selected ADC software start ADC group injected conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none +*\*\note setting of this feature is conditioned to ADC state: +*\*\ 1. ADC must be enabled without conversion on going on group injected, +*\*\ 2. without conversion stop command on going on group injected, +*\*\ 3. without ADC disable command on going. +**/ +void ADC_StartInjectedConv(ADC_Module *ADCx) +{ + /* Enable the selected ADC to start ADC group injected conversion */ + ADCx->CTRL3 |= ADC_INJ_START_MASK; +} + +/** +*\*\name ADC_StartRegularConv. +*\*\fun Enables or disables the selected ADC software start ADC group regular conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none +*\*\note setting of this feature is conditioned to ADC state: +*\*\ 1. ADC must be enabled without conversion on going on group regular, +*\*\ 2. without conversion stop command on going on group regular, +*\*\ 3. without ADC disable command on going. +**/ +void ADC_StartRegularConv(ADC_Module *ADCx) +{ + /* Enable the selected ADC to start ADC group regular conversion */ + ADCx->CTRL3 |= ADC_REG_START_MASK; +} + +/** +*\*\name ADC_EnableSoftwareStartConv. +*\*\fun Enables or disables the selected ADC software start conversion .. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CTRL2 |= ADC_REG_SWSTART_MASK; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CTRL2 &= (~ADC_REG_SWSTART_MASK); + } +} +/** +*\*\name ADC_GetSoftwareStartConvStatus. +*\*\fun Gets the selected ADC Software start conversion Status. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return The new state of ADC software start conversion (SET or RESET). +**/ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus ; + + if ((ADCx->CTRL2 & ADC_REG_SWSTART_MASK) != (uint32_t)RESET) + { + /* SOFT_START bit is set */ + bitstatus = SET; + } + else + { + /* SOFT_START bit is reset */ + bitstatus = RESET; + } + + return bitstatus; +} +/** +*\*\name ADC_EnableSoftwareStartInjectedConv. +*\*\fun Enables or disables the selected ADC start of the injected channels conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CTRL2 |= ADC_INJ_SWSTART_MASK; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CTRL2 &= (~ADC_INJ_SWSTART_MASK); + } +} +/** +*\*\name ADC_GetSoftwareStartInjectedConvCmdStatus. +*\*\fun Gets the selected ADC Software start injected conversion Status. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return The new state of ADC software start injected conversion (SET or RESET). +**/ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus ; + + /* Check the status of INJ_SWSTART bit */ + if ((ADCx->CTRL2 & ADC_INJ_SWSTART_MASK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name ADC_StopInjectedConv. +*\*\fun Stop ADC group injected channels conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none +**/ +void ADC_StopInjectedConv(ADC_Module* ADCx) +{ + ADCx->CTRL3 |= ADC_INJ_SWSTOP_MASK; +} +/** +*\*\name ADC_StopRegularConv. +*\*\fun Stop ADC group regular channels conversion. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none +**/ +void ADC_StopRegularConv(ADC_Module* ADCx) +{ + ADCx->CTRL3 |= ADC_REG_SWSTOP_MASK; +} + +/** +*\*\name ADC_SetRegularDataTransferMode. +*\*\fun Set ADC data transfer mode. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param DataTransferMode : Select Data Management configuration +*\*\ - ADC_REG_DR_TRANSFER +*\*\ - ADC_REG_DSMU_TRANSFER +*\*\ - ADC_REG_DMA_TRANSFER +*\*\return none +**/ +void ADC_SetRegularDataTransferMode(ADC_Module *ADCx, uint32_t DataTransferMode) +{ + uint32_t tempreg; + + /* Get the old register value */ + tempreg = ADCx->CTRL2; + /* Clear the old external event selection */ + tempreg &= (~ADC_DATA_TRANS_Mode_MASK); + /* Set the external event selection */ + tempreg |= DataTransferMode; + /* Store the new register value */ + ADCx->CTRL2 = tempreg; +} + +/** +*\*\name ADC_GetGainCompensationCmdStatus. +*\*\fun Gets the selected ADC gain compensation status. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return The new state of gain compensation (SET or RESET). +**/ +FlagStatus ADC_GetGainCompensationCmdStatus(ADC_Module* ADCx) +{ + FlagStatus bitstatus ; + + /* Check the status of GCOMPEN bit */ + if ((ADCx->CTRL3 & ADC_GAIN_COMPENSATION_EN_MASK) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name ADC_EnableTempSensor. +*\*\fun Enables or disables the temperature sensor +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableTempSensor(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* connect ADC3_CH18 with the temperature sensor */ + AFIO->ADCSW_CFG |= AFIO_ADCSW_CFG_SW_TEMP; + /* Enable the temperature sensor */ + ADC1->CTRL2 |= ADC_TS_EN_MASK; + } + else + { + /* Disconnect with the temperature sensor */ + AFIO->ADCSW_CFG &= (~AFIO_ADCSW_CFG_SW_TEMP); + /* Disable the temperature sensor */ + ADC1->CTRL2 &= (~ADC_TS_EN_MASK); + } +} + +/** +*\*\name ADC_EnableVrefint. +*\*\fun Enables or disables the Vrefint channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableVrefint(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Let ADC3_CH19 connected with the Vrefint */ + AFIO->ADCSW_CFG |= AFIO_ADCSW_CFG_VREF; + /* Enable the Vrefint channel*/ + ADC1->CTRL3 |= ADC_VREFINT_EN_MASK; + } + else + { + /* let ADC3_CH19 channel disconnected with the Vrefint */ + AFIO->ADCSW_CFG &= (~AFIO_ADCSW_CFG_VREF); + /* Disable the Vrefint channel*/ + ADC1->CTRL3 &= (~ADC_VREFINT_EN_MASK); + } +} + +/** +*\*\name ADC_ConfigInjectedChannel. +*\*\fun Configures for the selected ADC injected channel its corresponding +*\*\ rank in the sequencer and its sample time. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_Channel : +*\*\ - ADC_CH_0 : ADC Channel0 selected +*\*\ - ADC_CH_1 : ADC Channel1 selected +*\*\ - ADC_CH_2 : ADC Channel2 selected +*\*\ - ADC_CH_3 : ADC Channel3 selected +*\*\ - ADC_CH_4 : ADC Channel4 selected +*\*\ - ADC_CH_5 : ADC Channel5 selected +*\*\ - ADC_CH_6 : ADC Channel6 selected +*\*\ - ADC_CH_7 : ADC Channel7 selected +*\*\ - ADC_CH_8 : ADC Channel8 selected +*\*\ - ADC_CH_9 : ADC Channel9 selected +*\*\ - ADC_CH_10 : ADC Channel10 selected +*\*\ - ADC_CH_11 : ADC Channel11 selected +*\*\ - ADC_CH_12 : ADC Channel12 selected +*\*\ - ADC_CH_13 : ADC Channel13 selected +*\*\ - ADC_CH_14 : ADC Channel14 selected +*\*\ - ADC_CH_15 : ADC Channel15 selected +*\*\ - ADC_CH_16 : ADC Channel16 selected +*\*\ - ADC_CH_17 : ADC Channel17 selected +*\*\ - ADC_CH_18 : ADC Channel18 selected +*\*\ - ADC_CH_19 : ADC Channel19 selected +*\*\param Rank : The rank in the injected group sequencer. This parameter must be between 1 to 4. +*\*\param ADC_SampleTime : The sample time value to be set for the selected channel. +*\*\ - ADC_SAMP_TIME_CYCLES_1 +*\*\ - ADC_SAMP_TIME_CYCLES_2 +*\*\ - ADC_SAMP_TIME_CYCLES_3 +*\*\ - ADC_SAMP_TIME_CYCLES_4 +*\*\ - ADC_SAMP_TIME_CYCLES_5 +*\*\ - ADC_SAMP_TIME_CYCLES_6 +*\*\ - ADC_SAMP_TIME_CYCLES_7 +*\*\ - ADC_SAMP_TIME_CYCLES_10 +*\*\ - ADC_SAMP_TIME_CYCLES_13 +*\*\ - ADC_SAMP_TIME_CYCLES_17 +*\*\ - ADC_SAMP_TIME_CYCLES_24 +*\*\ - ADC_SAMP_TIME_CYCLES_32 +*\*\ - ADC_SAMP_TIME_CYCLES_83 +*\*\ - ADC_SAMP_TIME_CYCLES_93 +*\*\ - ADC_SAMP_TIME_CYCLES_215 +*\*\ - ADC_SAMP_TIME_CYCLES_397 +*\*\return none +**/ +void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tempreg1, tempreg2, tempreg3; + __IO uint16_t index; + + if (ADC_Channel > ADC_CH_15) /* if ADC_CH_16 ... ADC_CH_19 is selected */ + { + /* Get the old register value */ + tempreg1 = ADCx->SAMPT3; + /* Calculate the mask to clear */ + tempreg2 = ADC_SAMP_TIME_CYCLES_MASK << (4U * (ADC_Channel - 16U)); + /* Clear the old channel sample time */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = ((uint32_t)ADC_SampleTime) << (4U * (ADC_Channel - 16U)); + /* Set the new channel sample time */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->SAMPT3 = tempreg1; + } + else if (ADC_Channel > ADC_CH_7) /* if ADC_CH_8 ... ADC_CH_15 is selected */ + { + /* Get the old register value */ + tempreg1 = ADCx->SAMPT2; + /* Calculate the mask to clear */ + tempreg2 = ADC_SAMP_TIME_CYCLES_MASK << (4U * (ADC_Channel - 8U)); + /* Clear the old channel sample time */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = ((uint32_t)ADC_SampleTime) << (4U * (ADC_Channel - 8U)); + /* Set the new channel sample time */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->SAMPT2 = tempreg1; + } + else /* if ADC_CH_0 ... ADC_CH_7 is selected */ + { + /* Get the old register value */ + tempreg1 = ADCx->SAMPT1; + /* Calculate the mask to clear */ + tempreg2 = ADC_SAMP_TIME_CYCLES_MASK << (4U * ADC_Channel); + /* Clear the old channel sample time */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set */ + tempreg2 = ((uint32_t)ADC_SampleTime) << (4U * ADC_Channel); + /* Set the new channel sample time */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->SAMPT1 = tempreg1; + } + + /* Rank configuration */ + /* Get the old register value */ + tempreg1 = ADCx->JSEQ; + /* Get JLEN value: Number = JLEN+1 */ + tempreg3 = (tempreg1 & ADC_JESQ_LEN_MASK) >> 25U; + /* Calculate the mask to clear: ((Rank-1)+(4-JLEN-1)) */ + tempreg2 = ADC_JESQ_SEQ_MASK << (5U * (((uint32_t)Rank + 3U) - (tempreg3 + 1U))); + /* Clear the old JSEQx bits for the selected rank */ + tempreg1 &= ~tempreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JLEN-1)) */ + tempreg2 = (uint32_t)ADC_Channel << (5U * (((uint32_t)Rank + 3U) - (tempreg3 + 1U))); + /* Set the JSEQx bits for the selected rank */ + tempreg1 |= tempreg2; + /* Store the new register value */ + ADCx->JSEQ = tempreg1; + /*delay 4*ADC_CLK at least for synchronizing*/ + for(index = 0;index<24;index++) + { + __NOP(); + } +} + +/** +*\*\name ADC_ConfigInjectedSequencerLength. +*\*\fun Configures the sequencer length for injected channels +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Length : The sequencer length. This parameter must be a number between 1 to 4. +**/ +void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length) +{ + uint32_t tempreg1, tempreg2; + + /* Get the old register value */ + tempreg1 = ADCx->JSEQ; + /* Clear the old injected sequnence lenght JLEN bits */ + tempreg1 &= (~ADC_JESQ_LEN_MASK); + /* Set the injected sequnence lenght JLEN bits */ + tempreg2 = (uint32_t)Length - 1U; + tempreg1 |= tempreg2 << 25U; + /* Store the new register value */ + ADCx->JSEQ = tempreg1; +} + +/** +*\*\name ADC_SetOffsetConfig. +*\*\fun Set the specified channel conversion offset configuration. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_Offset : +*\*\ - ADC_REGESTER_OFFSET_1 +*\*\ - ADC_REGESTER_OFFSET_2 +*\*\ - ADC_REGESTER_OFFSET_3 +*\*\ - ADC_REGESTER_OFFSET_4 +*\*\param ADC_OffsetStruct : +*\*\ - OffsetData : Set the selected channel data offset .This parameter must be range from 0 to 0xfff. +*\*\ - OffsetChannel : Set the selected channel .This parameter must be range from 0 to 0x13. means CH0 - CH19. +*\*\ - OffsetDirPositiveEn : Enable or disable the selected channel offset positive direction. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - OffsetSatenEn : Enable or disable the selected channel offset saturation . +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - OffsetEn : Enable or disable the selected channel offset. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_SetOffsetConfig(ADC_Module* ADCx, uint8_t ADC_Offset, ADC_OffsetType* ADC_OffsetStruct) +{ + uint32_t tempreg, temp; + + tempreg = (uint32_t)ADCx; + tempreg += ADC_Offset; + /* Get register value */ + temp = *(__IO uint32_t*)tempreg; + temp &= (~(ADC_OFFSET_DATA_MASK | ADC_OFFSET_EN_MASK | ADC_OFFSET_CH_MASK | ADC_OFFSET_SATEN_EN_MASK | ADC_OFFSET_DIR_MASK )); + /* Set the selected channel offset direction and channel */ + temp |= ((uint32_t)ADC_OffsetStruct->OffsetData | (((uint32_t)ADC_OffsetStruct->OffsetChannel) << 26)); + + /* Set the selected channel offset direction, saturation, enable or disable*/ + temp |= (BIT_JUDGE_AND_HANDLER(ADC_OffsetStruct->OffsetDirPositiveEn, ADC_OFFSET_DIR_MASK) | \ + BIT_JUDGE_AND_HANDLER(ADC_OffsetStruct->OffsetSatenEn, ADC_OFFSET_SATEN_EN_MASK) | \ + BIT_JUDGE_AND_HANDLER(ADC_OffsetStruct->OffsetEn, ADC_OFFSET_EN_MASK)); + + *(__IO uint32_t*)tempreg = temp; +} +/** +*\*\name ADC_GetOffsetConfig. +*\*\fun Get the specified channel conversion offset configuration. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_Offset : +*\*\ - ADC_REGESTER_OFFSET_1 +*\*\ - ADC_REGESTER_OFFSET_2 +*\*\ - ADC_REGESTER_OFFSET_3 +*\*\ - ADC_REGESTER_OFFSET_4 +*\*\param ADC_OffsetStruct : +*\*\ - OffsetData : Set the selected channel data offset .This parameter must be range from 0 to 0xfff. +*\*\ - OffsetChannel : Set the selected channel .This parameter must be range from 0 to 0x13. means CH0 - CH19. +*\*\ - OffsetDirPositiveEn : Enable or disable the selected channel offset positive direction. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - OffsetSatenEn : Enable or disable the selected channel offset saturation . +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - OffsetEn : Enable or disable the selected channel offset. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_GetOffsetConfig(ADC_Module* ADCx, uint8_t ADC_Offset, ADC_OffsetType* ADC_OffsetStruct) +{ + uint32_t tempreg, temp; + + tempreg = (uint32_t)ADCx; + tempreg += ADC_Offset; + /* Get register value */ + temp = *(__IO uint32_t*)tempreg; + ADC_OffsetStruct->OffsetEn = ((temp & ADC_OFFSET_EN_MASK) != 0U) ? ENABLE : DISABLE; + ADC_OffsetStruct->OffsetSatenEn = ((temp & ADC_OFFSET_SATEN_EN_MASK) != 0U) ? ENABLE : DISABLE; + ADC_OffsetStruct->OffsetDirPositiveEn = ((temp & ADC_OFFSET_DIR_MASK) != 0U) ? ENABLE : DISABLE; + + ADC_OffsetStruct->OffsetChannel = (uint8_t)((temp & ADC_OFFSET_CH_MASK) >> 26); + ADC_OffsetStruct->OffsetData = (uint16_t)(temp & ADC_OFFSET_DATA_MASK); +} +/** +*\*\name ADC_EnableAnalogWatchdogEventToTim. +*\*\fun Enables or disables the selected ADC watch dog event output to TIM. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Awdg : +*\*\ - ADC_AWDG1 +*\*\ - ADC_AWDG2 +*\*\ - ADC_AWDG3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableAnalogWatchdogEventToTIM(ADC_Module* ADCx, ADC_AWDG Awdg, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable ADC watch dog event output to TIM */ + ADCx->AWDCTRL |= ((uint32_t)0x1u << (uint8_t)Awdg); + } + else + { + /* Disable ADC watch dog event output to TIM */ + ADCx->AWDCTRL &= ~(((uint32_t)0x1u << (uint8_t)Awdg)); + } +} +/** +*\*\name ADC_ConfigAnalogWatchdogThresholds. +*\*\fun Configures the high and low thresholds of the analog watchdog 1/2/3. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Awdg : +*\*\ - ADC_AWDG1 +*\*\ - ADC_AWDG2 +*\*\ - ADC_AWDG3 +*\*\param HighThreshold : the ADC analog watchdog 1/2/3 high threshold value. +*\*\ - This parameter must be a 12bit value. +*\*\param LowThreshold : the ADC analog watchdog 1/2/3 low threshold value. +*\*\ - This parameter must be a 12bit value. +*\*\return none +**/ +void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, ADC_AWDG Awdg, uint16_t HighThreshold, uint16_t LowThreshold) +{ + if(Awdg == ADC_AWDG1) + { + /* Set the ADCx high threshold of AWDG1 */ + ADCx->AWD1HIGH = HighThreshold; + /* Set the ADCx low threshold of AWDG1 */ + ADCx->AWD1LOW = LowThreshold; + } + else if(Awdg == ADC_AWDG2) + { + /* Set the ADCx high threshold of AWDG2 */ + ADCx->AWD2HIGH = HighThreshold; + /* Set the ADCx low threshold of AWDG2 */ + ADCx->AWD2LOW = LowThreshold; + } + else if(Awdg == ADC_AWDG3) + { + /* Set the ADCx high threshold of AWDG3 */ + ADCx->AWD3HIGH = HighThreshold; + /* Set the ADCx low threshold of AWDG3 */ + ADCx->AWD3LOW = LowThreshold; + } + else + { + /*no process */ + } +} +/** +*\*\name ADC_GetInjectedConversionDat. +*\*\fun Get the ADC injected channel conversion result. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_InjectedChannelOffset : +*\*\ - ADC_INJECT_DATA_OFFSET_1 +*\*\ - ADC_INJECT_DATA_OFFSET_2 +*\*\ - ADC_INJECT_DATA_OFFSET_3 +*\*\ - ADC_INJECT_DATA_OFFSET_4 +*\*\return The data conversion value. this date is range 0 - 0xFFFF. +**/ +uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannelOffset) +{ + uint32_t tempreg; + + tempreg = (uint32_t)ADCx; + tempreg += ADC_InjectedChannelOffset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t)(*(__IO uint32_t*)tempreg); +} + +/** +*\*\name ADC_ConfigAnalogWatchdog1WorkChannelType. +*\*\fun Enables or disables the analog watchdog 1 on single/all regular or injected channels. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_AnalogWatchdog : +*\*\ - ADC_ANALOG_WTDG_NONE +*\*\ - ADC_ANALOG_WTDG_SINGLEREG_ENABLE +*\*\ - ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE +*\*\ - ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE +*\*\ - ADC_ANALOG_WTDG_ALLREG_ENABLE +*\*\ - ADC_ANALOG_WTDG_ALLINJEC_ENABLE +*\*\ - ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE +*\*\return none. +**/ +void ADC_ConfigAnalogWatchdog1WorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tempreg; + + /* Get the old register value */ + tempreg = ADCx->CTRL1; + /* Clear AWD1EJCH, AWD1ERCH and AWD1SGLEN bits */ + tempreg &= (~(ADC_CTRL1_AWD1ERCH | ADC_CTRL1_AWD1SGLEN | ADC_CTRL1_AWD1EJCH)); + /* Set the analog watchdog enable mode */ + tempreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CTRL1 = tempreg; +} +/** +*\*\name ADC_SetAWDG1FilteringConfig. +*\*\fun Set ADC analog watchdog filtering configuration. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param FilteringCount : +*\*\ - ADC_AWDG1_FILTERING_NONE +*\*\ - ADC_AWDG1_FILTERING_2SAMPLES +*\*\ - ADC_AWDG1_FILTERING_3SAMPLES +*\*\ - ADC_AWDG1_FILTERING_4SAMPLES +*\*\ - ADC_AWDG1_FILTERING_5SAMPLES +*\*\ - ADC_AWDG1_FILTERING_6SAMPLES +*\*\ - ADC_AWDG1_FILTERING_7SAMPLES +*\*\ - ADC_AWDG1_FILTERING_8SAMPLES +*\*\return none. +**/ +void ADC_SetAWDG1FilteringConfig(ADC_Module *ADCx, uint32_t FilteringCount) +{ + uint32_t tempreg; + + /* Get the old register value */ + tempreg = ADCx->AWD1LOW; + /* Clear AWDFIL bits */ + tempreg &= (~ADC_AWDG1_FILTERING_MASK); + /* Set the AWDFIL bit */ + tempreg |= FilteringCount; + /* Store the new register value */ + ADCx->AWD1LOW = tempreg; +} +/** +*\*\name ADC_ConfigAnalogWatchdog1SingleChannel. +*\*\fun Configures the analog watchdog 1 guarded on single channel. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_AnalogWatchdog : +*\*\ - ADC_CH_0 : ADC Channel0 selected +*\*\ - ADC_CH_1 : ADC Channel1 selected +*\*\ - ADC_CH_2 : ADC Channel2 selected +*\*\ - ADC_CH_3 : ADC Channel3 selected +*\*\ - ADC_CH_4 : ADC Channel4 selected +*\*\ - ADC_CH_5 : ADC Channel5 selected +*\*\ - ADC_CH_6 : ADC Channel6 selected +*\*\ - ADC_CH_7 : ADC Channel7 selected +*\*\ - ADC_CH_8 : ADC Channel8 selected +*\*\ - ADC_CH_9 : ADC Channel9 selected +*\*\ - ADC_CH_10 : ADC Channel10 selected +*\*\ - ADC_CH_11 : ADC Channel11 selected +*\*\ - ADC_CH_12 : ADC Channel12 selected +*\*\ - ADC_CH_13 : ADC Channel13 selected +*\*\ - ADC_CH_14 : ADC Channel14 selected +*\*\ - ADC_CH_15 : ADC Channel15 selected +*\*\ - ADC_CH_16 : ADC Channel16 selected +*\*\ - ADC_CH_17 : ADC Channel17 selected +*\*\ - ADC_CH_18 : ADC Channel18 selected +*\*\ - ADC_CH_19 : ADC Channel19 selected +*\*\return none. +**/ +void ADC_ConfigAnalogWatchdog1SingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel) +{ + uint32_t tempreg; + + /* Get the old register value */ + tempreg = ADCx->CTRL1; + /* Clear the Analog watchdog 1 channel select bits */ + tempreg &= (~ADC_AWD1CH_MASK); + /* Set the Analog watchdog channel */ + tempreg |= ((uint32_t)ADC_Channel) << 16; + /* Store the new register value */ + ADCx->CTRL1 = tempreg; +} +/** +*\*\name ADC_SetAnalogWatchdog23MonitChannels. +*\*\fun Set ADC analog watchdog 2/3 monitored channels: a single channel, multiple channels or all channels. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param AWDG_RegEnOffset : +*\*\ - ADC_AWDG2_EN_OFFSET : config analog watchdog 2. +*\*\ - ADC_AWDG3_EN_OFFSET : config analog watchdog 3. +*\*\param AWDG_ChannelGroup : channels monitored: flexible on channels monitored, selection is +*\*\ channel wise, from from 1 to all channels. Specificity of this analog watchdog: +*\*\ Multiple channels can be selected.eg : 0x00000005 mean CH0 and CH2 are monitored. +*\*\ 0x00000000 mean this analog watchdog disable. +*\*\return none. +**/ +void ADC_SetAnalogWatchdog23MonitChannels(ADC_Module* ADCx, uint8_t AWDG_RegEnOffset, uint32_t AWDG_ChannelGroup) +{ + uint32_t tempreg, temp; + /* Get the old register value */ + tempreg = (uint32_t)ADCx; + tempreg += AWDG_RegEnOffset; + temp = *(__IO uint32_t*)tempreg; + /* Clear the Analog watchdog 2/3 channel select bits */ + temp &= (~ADC_AWDG23_EN_MASK); + /* Set the Analog watchdog channel */ + temp |= AWDG_ChannelGroup; + /* Store the new register value */ + *(__IO uint32_t*)tempreg = temp; +} +/** +*\*\name ADC_GetAnalogWatchdog23MonitChannels. +*\*\fun Get ADC analog watchdog 2/3 monitored channels. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param AWDG_RegEnOffset : +*\*\ - ADC_AWDG2_EN_OFFSET : analog watchdog 2. +*\*\ - ADC_AWDG3_EN_OFFSET : analog watchdog 3. +*\*\return channels monitored by this analog watchdog2/3. +**/ +uint32_t ADC_GetAnalogWatchdog23MonitChannels(ADC_Module* ADCx, uint8_t AWDG_RegEnOffset) +{ + uint32_t tempreg; + + tempreg = (uint32_t)ADCx; + tempreg += AWDG_RegEnOffset; + return ((*(__IO uint32_t*)tempreg) & ADC_AWDG23_EN_MASK); +} +/** +*\*\name ADC_SetAnalogWatchdog23IntConfig. +*\*\fun Enable or disable ADC analog watchdog 2/3 monitored channels interrupt. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param AWDG_RegIntEnOffset : +*\*\ - ADC_AWDG2_INTEN_OFFSET : config analog watchdog 2. +*\*\ - ADC_AWDG3_INTEN_OFFSET : config analog watchdog 3. +*\*\param AWDG_ChannelEn : channels monitored: flexible on channels monitored, selection is +*\*\ channel wise, from from 1 to all channels. Specificity of this analog watchdog: +*\*\ Multiple channels can be selected.eg : 0x00000005 mean CH0 and CH2 monitored enable interrupt. +*\*\ 0x00000000 mean this analog watchdog disable the interrupt. +*\*\return none. +**/ +void ADC_SetAnalogWatchdog23IntConfig(ADC_Module* ADCx, uint8_t AWDG_RegIntEnOffset, uint32_t AWDG_ChannelEn) +{ + uint32_t tempreg, temp; + + tempreg = (uint32_t)ADCx; + tempreg += AWDG_RegIntEnOffset; + temp = *(__IO uint32_t*)tempreg; + /* Clear the Analog watchdog 2/3 channel select bits */ + temp &= (~ADC_AWDG23_INTEN_MASK); + /* Set the Analog watchdog channel */ + temp |= AWDG_ChannelEn; + /* Store the new register value */ + *(__IO uint32_t*)tempreg = temp; +} + +/** +*\*\name ADC_GetAnalogWatchdog23MonitChannels. +*\*\fun Get ADC analog watchdog 2/3 monitored channels. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param AWDG_RegEnOffset : +*\*\ - ADC_AWDG2_EN_OFFSET : analog watchdog 2. +*\*\ - ADC_AWDG3_EN_OFFSET : analog watchdog 3. +*\*\return channels monitored by this analog watchdog2/3 enable the interrupt or not. +**/ +uint32_t ADC_GetAnalogWatchdog23IntConfig(ADC_Module* ADCx, uint8_t AWDG_RegEnOffset) +{ + uint32_t tempreg; + + tempreg = (uint32_t)ADCx; + tempreg += AWDG_RegEnOffset; + return ((*(__IO uint32_t*)tempreg) & ADC_AWDG23_INTEN_MASK); +} + +/** +*\*\name ADC_GetAnalogWatchdog23StatusFlag. +*\*\fun Get ADC analog watchdog 2/3 monitored channels status flag. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param AWDG_RegSTSOffset : +*\*\ - ADC_AWDG2_STS_OFFSET : analog watchdog 2. +*\*\ - ADC_AWDG3_STS_OFFSET : analog watchdog 3. +*\*\return channels monitored by this analog watchdog2/3 indicates outside the programmed +*\*\ thresholds or not. +**/ +uint32_t ADC_GetAnalogWatchdog23StatusFlag(ADC_Module* ADCx, uint8_t AWDG_RegSTSOffset) +{ + uint32_t tempreg; + + tempreg = (uint32_t)ADCx; + tempreg += AWDG_RegSTSOffset; + + return ((*(__IO uint32_t*)tempreg) & ADC_AWDG23_STATUS_MASK); +} + +/** +*\*\name ADC_ClearAnalogWatchdog23StatusFlag. +*\*\fun Clear ADC analog watchdog 2/3 monitored channels status flag. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param AWDG_RegSTSOffset : +*\*\ - ADC_AWDG2_STS_OFFSET : analog watchdog 2. +*\*\ - ADC_AWDG3_STS_OFFSET : analog watchdog 3. +*\*\param AWDG_ChannelFlag : channels monitored flag wil l be cleared. +*\*\ eg : 0x00000005 mean CH0 and CH2 status flag will be cleared. +*\*\return none. +**/ +void ADC_ClearAnalogWatchdog23StatusFlag(ADC_Module* ADCx, uint8_t AWDG_RegSTSOffset, uint32_t AWDG_ChannelFlag) +{ + uint32_t tempreg; + + tempreg = (uint32_t)ADCx; + tempreg += AWDG_RegSTSOffset; + + /* Clear the Analog watchdog channel flag */ + *(__IO uint32_t*)tempreg = AWDG_ChannelFlag; +} + + +/** +*\*\name ADC_GetFlagStatus. +*\*\fun Checks whether the specified ADC flag is set or not. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_FLAG : +*\*\ - ADC_FLAG_ENDC +*\*\ - ADC_FLAG_EOC_ANY +*\*\ - ADC_FLAG_JSTR +*\*\ - ADC_FLAG_JENDC +*\*\ - ADC_FLAG_JEOC_ANY +*\*\ - ADC_FLAG_STR +*\*\ - ADC_FLAG_AWDG1 +*\*\ - ADC_FLAG_RDY +*\*\ - ADC_FLAG_PDRDY +*\*\ - ADC_FLAG_EOSAMP +*\*\ - ADC_FLAG_ROSOVF +*\*\ - ADC_FLAG_JOSOVF +*\*\ - ADC_FLAG_ROSOVFDSMU +*\*\ - ADC_FLAG_REFLAG +*\*\ - ADC_FLAG_WEFLAG +*\*\return The new state of ADC_FLAG (SET or RESET). +**/ +FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint32_t ADC_FLAG) +{ + FlagStatus bitstatus ; + + /* Check the status of the specified ADC flag */ + if ((ADCx->STS & ((uint32_t)ADC_FLAG)) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** +*\*\name ADC_ClearFlag. +*\*\fun Clears pending flags of the specified ADC. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_FLAG : +*\*\ - ADC_FLAG_ENDC +*\*\ - ADC_FLAG_EOC_ANY +*\*\ - ADC_FLAG_JSTR +*\*\ - ADC_FLAG_JENDC +*\*\ - ADC_FLAG_JEOC_ANY +*\*\ - ADC_FLAG_STR +*\*\ - ADC_FLAG_AWDG1 +*\*\ - ADC_FLAG_RDY +*\*\ - ADC_FLAG_PDRDY +*\*\ - ADC_FLAG_EOSAMP +*\*\ - ADC_FLAG_ROSOVF +*\*\ - ADC_FLAG_JOSOVF +*\*\ - ADC_FLAG_ROSOVFDSMU +*\*\ - ADC_FLAG_REFLAG +*\*\ - ADC_FLAG_WEFLAG +*\*\return none. +**/ +void ADC_ClearFlag(ADC_Module* ADCx, uint32_t ADC_FLAG) +{ + /* Clear the selected ADC flags */ + ADCx->STS = ((uint32_t)ADC_FLAG & ADC_FLAG_ALL_MASK) ; +} + +/** +*\*\name ADC_ConfigInt. +*\*\fun Enables or disables the specified ADC interrupts. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_IT : +*\*\ - ADC_INT_ENDC +*\*\ - ADC_INT_ENDCA +*\*\ - ADC_INT_JENDC +*\*\ - ADC_INT_JENDCA +*\*\ - ADC_INT_AWD1 +*\*\ - ADC_INT_EOSAMP +*\*\ - ADC_INT_PDRDY +*\*\ - ADC_INT_RDY +*\*\ - ADC_INT_WRITEERR +*\*\ - ADC_INT_READERR +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void ADC_ConfigInt(ADC_Module* ADCx, uint32_t ADC_IT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CTRL1 |= (ADC_IT & ADC_INT_CONTROL_MASK); + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CTRL1 &= ~(ADC_IT & ADC_INT_CONTROL_MASK); + } +} +/** +*\*\name ADC_GetIntStatus. +*\*\fun Checks whether the specified ADC interrupt has occurred or not. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_IT : specifies the ADC interrupt source to check. +*\*\ - ADC_INT_ENDC +*\*\ - ADC_INT_ENDCA +*\*\ - ADC_INT_JENDC +*\*\ - ADC_INT_JENDCA +*\*\ - ADC_INT_AWD1 +*\*\ - ADC_INT_EOSAMP +*\*\ - ADC_INT_PDRDY +*\*\ - ADC_INT_RDY +*\*\ - ADC_INT_WRITEERR +*\*\ - ADC_INT_READERR +*\*\return The new state of ADC_IT (SET or RESET). +**/ +INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint32_t ADC_IT) +{ + INTStatus bitstatus; + uint32_t enablestatus; + uint32_t status; + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CTRL1 & ADC_IT); + status = ((ADC_IT >> 8)& ADC_FLAG_ALL_MASK); + + /* Check the status of the specified ADC interrupt */ + if(((ADCx->STS & status) != 0U) && (enablestatus != 0U)) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name ADC_ClearIntPendingBit. +*\*\fun Clears interrupt pending bits of the specified ADC. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_IT : +*\*\ - ADC_INT_ENDC +*\*\ - ADC_INT_ENDCA +*\*\ - ADC_INT_JENDC +*\*\ - ADC_INT_JENDCA +*\*\ - ADC_INT_AWD1 +*\*\ - ADC_INT_EOSAMP +*\*\ - ADC_INT_PDRDY +*\*\ - ADC_INT_RDY +*\*\ - ADC_INT_WRITEERR +*\*\ - ADC_INT_READERR +*\*\return none. +**/ +void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint32_t ADC_IT) +{ + /* Clear the selected ADC interrupt pending bits */ + ADCx->STS = ((ADC_IT >> 8)& ADC_FLAG_ALL_MASK) ; +} + + +/** +*\*\name ADC_SetChannelSingleDiff. +*\*\fun Set mode single-ended or differential input of the selected ADC channel. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Channel : +*\*\ - ADC_CH_1 +*\*\ - ADC_CH_2 +*\*\ - ADC_CH_3 +*\*\ - ADC_CH_4 +*\*\ - ADC_CH_5 +*\*\ - ADC_CH_6 +*\*\ - ADC_CH_7 +*\*\ - ADC_CH_8 +*\*\ - ADC_CH_9 +*\*\ - ADC_CH_10 +*\*\ - ADC_CH_11 +*\*\ - ADC_CH_12 +*\*\ - ADC_CH_13 +*\*\ - ADC_CH_14 +*\*\ - ADC_CH_15 +*\*\ - ADC_CH_16 +*\*\ - ADC_CH_17 +*\*\ - ADC_CH_18 +*\*\ - ADC_CH_19 +*\*\param SingleDiff : +*\*\ - ADC_SINGLE_ENDED +*\*\ - ADC_DIFFERENTIAL_ENDED +*\*\return none. +*\*\note Some channels are internally fixed to single-ended inputs: please refer to ADC chapter of user manual. +**/ +void ADC_SetChannelSingleDiff(ADC_Module* ADCx, uint32_t Channel, uint32_t SingleDiff) +{ + if (SingleDiff == ADC_DIFFERENTIAL_ENDED) + { + ADCx->DIFSEL |= ((uint32_t)0x01 << Channel); + } + else + { + ADCx->DIFSEL &= (~((uint32_t)0x01 << Channel)); + } +} + +/** +*\*\name ADC_SetGainCompensation. +*\*\fun Set ADC gain compensation. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param GainCompensationMode : +*\*\ - ADC_GAIN_COMPENSATION_MODE0 : Saturation range is max 0x0-0xFFF (12-bit) +*\*\ - ADC_GAIN_COMPENSATION_MODE1 : Saturation range is max 0x0-0x3FFF (14-bit) +*\*\param GainCompensationValue : +*\*\ when this value is 0, it means gain compensation will be disabled and value set to 0. +*\*\ when this value is 1 ~ 16383, gain compensation will be enabled with specified value. +*\*\return none. +**/ +void ADC_SetGainCompensation(ADC_Module *ADCx, uint32_t GainCompensationMode, uint32_t GainCompensationValue) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->CTRL3; + /* Clear saturaion and gain compensation enable select bits */ + tempreg &= (~ADC_GAIN_COMPENSATION_MODE_MASK); + + if(GainCompensationValue != 0U) + { + /*Enables the selected ADCx gain compensation mode**/ + tempreg |= GainCompensationMode; + } + else + { + /*no process*/ + } + + /* Store the new register value */ + ADCx->CTRL3 = tempreg; + ADCx->GCOMP = (GainCompensationValue & ADC_GAIN_COMPENSATION_VALUE_MASK); +} + +/** +*\*\name ADC_SetConvResultBitNum. +*\*\fun Set ADC resolution including 12bit,10bit . +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ResultBitNum : +*\*\ - ADC_DATA_RES_12BIT +*\*\ - ADC_DATA_RES_10BIT +*\*\return none. +**/ +void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum) +{ + if(ResultBitNum == ADC_DATA_RES_12BIT) + { + /* Set ADC resolution */ + ADCx->CTRL3 |= ADC_DATA_RES_12BIT; + } + else + { + /* Clear resolution select bits */ + ADCx->CTRL3 &= (~ADC_DATA_RES_12BIT); + } +} + +/** +*\*\name ADC_SelectClockMode. +*\*\fun Set Adc Clock mode from AHB or PLL. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ClockMode : +*\*\ - ADC_CLOCK_MODE_PLL +*\*\ - ADC_CLOCK_MODE_AHB +*\*\return none. +**/ +void ADC_SelectClockMode(ADC_Module* ADCx, uint32_t ClockMode) +{ + if(ClockMode == ADC_CLOCK_MODE_PLL) + { + ADCx->CTRL3 |= ADC_CLOCK_MODE_PLL; + } + else + { + ADCx->CTRL3 &= (~ADC_CLOCK_MODE_PLL); + } +} +/** +*\*\name ADC_SetBypassCalibration. +*\*\fun Enable or disable ADC calibration bypass mode. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + ADCx->CTRL3 |= ADC_BYPASS_CAL_MASK; + } + else + { + ADCx->CTRL3 &= (~ADC_BYPASS_CAL_MASK); + } +} + +/** +*\*\name ADC_EnableBatteryVoltageMonitor. +*\*\fun Enables or disables the specified ADC battery voltage monitor. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note if users wants to measure the VBAT/4, they should set this bit first. +**/ +void ADC_EnableBatteryVoltageMonitor(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Let ADC3_CH17 connected with the battery voltage */ + AFIO->ADCSW_CFG |= AFIO_ADCSW_CFG_VBAT; + /* Enable the selected ADC battery voltage monitor */ + ADC1->CTRL3 |= ADC_VOLT_MONITOR_EN_MASK; + } + else + { + /* let ADC3_CH17 channel disconnected with the battery voltage */ + AFIO->ADCSW_CFG &= (~AFIO_ADCSW_CFG_VBAT); + /* Disable the selected ADC battery voltage monitor */ + ADC1->CTRL3 &= (~ADC_VOLT_MONITOR_EN_MASK); + } +} + +/** +*\*\name ADC_ConfigOverSamplingRatioAndShift. +*\*\fun Set ADC oversampling rate times and shift bit. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Ratio : ADC oversampling ratio times +*\*\ - ADC_OVERSAMPE_RATE_TIMES_1 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_2 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_4 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_8 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_16 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_32 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_64 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_128 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_256 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_512 +*\*\ - ADC_OVERSAMPE_RATE_TIMES_1024 +*\*\param Shift : ADC oversampling data right shift +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_0 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_1 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_2 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_3 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_4 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_5 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_6 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_7 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_8 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_9 +*\*\ - ADC_OVERSAMPE_DATA_SHIFT_10 +*\*\return none +**/ +void ADC_ConfigOverSamplingRatioAndShift(ADC_Module *ADCx, uint32_t Ratio, uint32_t Shift) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->OSCFG; + /* Clear oversampling ratio and shift select bits */ + tempreg &= (~(ADC_OVERSAMPE_RATE_TIMES_MASK | ADC_OVERSAMPE_DATA_SHIFT_MASK)); + /* Set ADC oversampling ratio and shift bit */ + tempreg |= (Ratio | Shift); + /* Store the new register value */ + ADCx->OSCFG = tempreg; +} + +/** +*\*\name ADC_SetOverSamplingScope. +*\*\fun Set ADC oversampling scope. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param OversampleScope :This parameter can be one of the following values +*\*\ - ADC_OVERSAMPE_DISABLE +*\*\ - ADC_OVERSAMPE_REGULAR_CONTINUED +*\*\ - ADC_OVERSAMPE_REGULAR_RESUMED +*\*\ - ADC_OVERSAMPE_INJECTED +*\*\ - ADC_OVERSAMPE_REGULAR_INJECTED +*\*\return none +**/ +void ADC_SetOverSamplingScope(ADC_Module *ADCx, uint32_t OversampleScope) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->OSCFG; + /* Clear oversampling select bits */ + tempreg &= (~(ADC_OVERSAMPE_REG_EN_MASK | ADC_OVERSAMPE_INJ_EN_MASK | ADC_OVERSAMPE_MODE_MASK)); + /* Set ADC oversampling select bits */ + tempreg |= (OversampleScope); + /* Store the new register value */ + ADCx->OSCFG = tempreg; +} + +/** +*\*\name ADC_SetOverSamplingDiscont. +*\*\fun Set ADC oversampling discontinuous mode (triggered mode). +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ADC_EnableOverSamplingDiscont(ADC_Module *ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + ADCx->OSCFG |= ADC_OVERSAMPE_TRIG_REG_MASK; + } + else + { + ADCx->OSCFG &= (~ADC_OVERSAMPE_TRIG_REG_MASK); + } +} + +/** +*\*\name ADC_EnableFIFO. +*\*\fun Enables or disables the specified ADC FIFO. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void ADC_EnableFIFO(ADC_Module* ADCx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC FIFO */ + ADCx->FIFOCFG |= ADC_FIFO_EN_MASK; + } + else + { + /* Disable the selected ADC FIFO */ + ADCx->FIFOCFG &= (~ADC_FIFO_EN_MASK); + } +} +/** +*\*\name ADC_ClearFIFO. +*\*\fun Clear the specified ADC FIFO. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return none. +**/ +void ADC_ClearFIFO(ADC_Module* ADCx) +{ + /* Clear the selected ADC FIFO */ + ADCx->FIFOCFG |= ADC_FIFO_CLR_MASK; +} + +/** +*\*\name ADC_ConfigFIFOWaterLevel. +*\*\fun Configures the specified ADC FIFO water level . +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param FIFO_Level : This parameter must be between 1 to 16. +*\*\return none. +**/ +void ADC_ConfigFIFOWaterLevel(ADC_Module* ADCx, uint32_t FIFO_Level) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = ADCx->FIFOCFG; + /* Clear WL(water level) select bits */ + tempreg &= (~ADC_FIFO_WATER_LEVEL_MASK); + /* Set ADC WL(water level) select bits */ + tempreg |= ((FIFO_Level - 1U) << 6U); + /* Store the new register value */ + ADCx->FIFOCFG = tempreg; +} +/** +*\*\name ADC_GetFIFOInvalidedDataCount. +*\*\fun Get the total counts of invalided data . +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\return The the total counts of invalided data .This value is between 0 to 16. +**/ +uint8_t ADC_GetFIFOInvalidedDataCount(ADC_Module* ADCx) +{ + return (uint8_t)((ADCx->FIFOSTS & (ADC_FIFO_INVALIED_DATA_COUNT_MASK)) >> 5); +} +/** +*\*\name ADC_GetFIFOFlagStatus. +*\*\fun Checks whether the specified ADC flag in fifo mode is set or not. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_FIFOFLAG : +*\*\ - ADC_FIFO_FLAG_FULL +*\*\ - ADC_FIFO_FLAG_EMPTY +*\*\ - ADC_FIFO_FLAG_HALF_FULL +*\*\ - ADC_FIFO_FLAG_NOT_EMPTY +*\*\return The new state of ADC_FIFOFLAG (SET or RESET). +**/ +FlagStatus ADC_GetFIFOFlagStatus(ADC_Module* ADCx, uint16_t ADC_FIFOFLAG) +{ + FlagStatus bitstatus ; + + /* Check the status of the specified ADC flag */ + if ((ADCx->FIFOSTS & ((uint32_t)ADC_FIFOFLAG)) != (uint8_t)RESET) + { + /* ADC_FIFOFLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FIFOFLAG is reset */ + bitstatus = RESET; + } + + /* Return the ADC_FIFOFLAG status */ + return bitstatus; +} +/** +*\*\name ADC_ClearFIFOFlag. +*\*\fun Clears FIFO status bit of the specified ADC. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_FIFO_FLAG : +*\*\ - ADC_FIFO_FLAG_FULL +*\*\ - ADC_FIFO_FLAG_EMPTY +*\*\ - ADC_FIFO_FLAG_HALF_FULL +*\*\ - ADC_FIFO_FLAG_NOT_EMPTY +*\*\return none. +**/ +void ADC_ClearFIFOFlag(ADC_Module* ADCx, uint16_t ADC_FIFO_FLAG) +{ + /* Clear the selected ADC FIFO interrupt pending bits */ + ADCx->FIFOSTS = ((uint32_t)ADC_FIFO_FLAG) ; +} +/** +*\*\name ADC_ConfigFIFOInt. +*\*\fun Enables or disables the specified ADC interrupts in FIFO mode. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_FIFO_IT : +*\*\ - ADC_FIFO_INT_FULL +*\*\ - ADC_FIFO_INT_EMPTY +*\*\ - ADC_FIFO_INT_HALF_FULL +*\*\ - ADC_FIFO_INT_NOT_EMPTY +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void ADC_ConfigFIFOInt(ADC_Module* ADCx, uint16_t ADC_FIFO_IT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ADC FIFO interrupts */ + ADCx->FIFOCFG |= (uint32_t)ADC_FIFO_IT; + } + else + { + /* Disable the selected ADC FIFO interrupts */ + ADCx->FIFOCFG &= (~(uint32_t)ADC_FIFO_IT); + } +} +/** +*\*\name ADC_ClearFIFOIntPendingBit. +*\*\fun Clears FIFO interrupt pending bits of the specified ADC. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_FIFO_IT : +*\*\ - ADC_FIFO_INT_FULL +*\*\ - ADC_FIFO_INT_EMPTY +*\*\ - ADC_FIFO_INT_HALF_FULL +*\*\ - ADC_FIFO_INT_NOT_EMPTY +*\*\return none. +**/ +void ADC_ClearFIFOIntPendingBit(ADC_Module* ADCx, uint16_t ADC_FIFO_IT) +{ + /* Clear the selected ADC FIFO interrupt pending bits */ + ADCx->FIFOSTS |= ((uint32_t)ADC_FIFO_IT) ; +} + +//** +//*\*\name ADC_WriteDataIntoInternalReg. +//*\*\fun Write data into internal register of specified the address. +//*\*\param ADCx : +//*\*\ - ADC1 +//*\*\ - ADC2 +//*\*\ - ADC3 +//*\*\param Addr : The value is range of 0 - 7; +//*\*\param Data : The value is range of 0 - 255; +//*\*\return ErrorStatus. +//*\*\ - SUCCESS +//*\*\ - ERROR +//**/ +//static ErrorStatus ADC_WriteDataIntoInternalReg(ADC_Module* ADCx, uint8_t Addr, uint8_t Data) +//{ +// uint32_t tempreg; +// ErrorStatus status = SUCCESS; +// __IO uint32_t timeout = ADC_WRITE_READ_TIMEOUT_CYCLE; +// /* Get the old register value */ +// tempreg = ADCx->INTLRCFG; +// /* Clear WDATA[7:0], WEN, RWSTART and ADDR[2:0] select bits */ +// tempreg &= (~ADC_WRITE_REG_MASK); +// /* Set ADC WEN and ADDR[2:0] select bits */ +// tempreg |= (ADC_INTLRCFG_WEN | ((uint32_t)Addr <<27) | ((uint32_t)Data <<18) ); +// /* Store the new register value */ +// ADCx->INTLRCFG = tempreg; + +// /* Start write internal register */ +// ADCx->INTLRCFG |= ADC_WRITE_READ_START; +// /* Wait write internal register finishing */ +// while((ADCx->INTLRCFG & ADC_WRITE_READ_RDY) == (uint8_t)RESET) +// { +// timeout--; +// if (timeout == 0UL) +// { +// /* Time-out error */ +// status = ERROR; +// break; +// } +// } +// return status; +//} +///** +//*\*\name ADC_ReadDataFromInternalReg. +//*\*\fun Read data from internal register according to the address. +//*\*\param ADCx : +//*\*\ - ADC1 +//*\*\ - ADC2 +//*\*\ - ADC3 +//*\*\param Addr : The value is range of 0 - 7; +//*\*\param ReadOutData : The value is range of 0 - 255; 0xFFFFU is invalid data. +//*\*\return ErrorStatus. +//*\*\ - SUCCESS +//*\*\ - ERROR +//**/ +//static ErrorStatus ADC_ReadDataFromInternalReg(ADC_Module* ADCx, uint8_t Addr, uint16_t *ReadOutData) +//{ +// uint32_t tempreg; +// ErrorStatus status = SUCCESS; +// __IO uint32_t timeout = ADC_WRITE_READ_TIMEOUT_CYCLE; +// /* Get the old register value */ +// tempreg = ADCx->INTLRCFG; +// /* Clear WEN, RWSTART and ADDR[2:0] select bits */ +// tempreg &= (~ADC_READ_REG_MASK); +// /* Set ADC WEN and ADDR[2:0] select bits */ +// tempreg |= (((uint32_t)Addr <<27) ); +// /* Store the new register value */ +// ADCx->INTLRCFG = tempreg; + +// /* Start read internal register */ +// ADCx->INTLRCFG |= ADC_WRITE_READ_START; +// /* Wait read internal register finishing */ +// while((ADCx->INTLRCFG & ADC_WRITE_READ_RDY) == (uint8_t)RESET) +// { +// timeout--; +// if (timeout == 0UL) +// { +// /* Time-out error */ +// status = ERROR; +// *ReadOutData = 0xFF; +// break; +// } +// } +// if(status != ERROR) +// { +// /* Return valid data */ +// *ReadOutData = (uint16_t)((ADCx->INTLRCFG & ADC_RDATA_MASK) >> 13) ; +// } +// else +// { +// /* Return invalid data */ +// *ReadOutData = 0xFFFF; +// } +// return status; +//} + +/** +*\*\name ADC_ConfigClk. +*\*\fun Configures the ADC prescaler. +*\*\param ADCx : +*\*\ - ADC1 +*\*\ - ADC2 +*\*\ - ADC3 +*\*\param ADC_ClkMode : +*\*\ - ADC_CTRL3_CKMOD_AHB +*\*\ - ADC_CTRL3_CKMOD_PLL +*\*\param Pll_CLK_source : +*\*\ - RCC_ADCPLLCLK_SRC_PLL2B +*\*\ - RCC_ADCPLLCLK_SRC_PLL1B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3C +*\*\param RCC_ADCPrescaler : specifies the ADC prescaler. +*\*\param CLK_divider(ADCSYSCLK prescaler): +*\*\ - RCC_ADCSYSCLK_DIV1 +*\*\ - RCC_ADCSYSCLK_DIV2 +*\*\ - RCC_ADCSYSCLK_DIV3 +*\*\ - RCC_ADCSYSCLK_DIV4 +*\*\ - RCC_ADCSYSCLK_DIV5 +*\*\ - RCC_ADCSYSCLK_DIV6 +*\*\ - RCC_ADCSYSCLK_DIV7 +*\*\ - RCC_ADCSYSCLK_DIV8 +*\*\ - RCC_ADCSYSCLK_DIV9 +*\*\ - RCC_ADCSYSCLK_DIV10 +*\*\ - RCC_ADCSYSCLK_DIV11 +*\*\ - RCC_ADCSYSCLK_DIV12 +*\*\ - RCC_ADCSYSCLK_DIV13 +*\*\ - RCC_ADCSYSCLK_DIV14 +*\*\ - RCC_ADCSYSCLK_DIV15 +*\*\ - RCC_ADCSYSCLK_DIV16 +*\*\ - RCC_ADCSYSCLK_DIV17 +*\*\ - RCC_ADCSYSCLK_DIV18 +*\*\ - RCC_ADCSYSCLK_DIV19 +*\*\ - RCC_ADCSYSCLK_DIV20 +*\*\ - RCC_ADCSYSCLK_DIV21 +*\*\ - RCC_ADCSYSCLK_DIV22 +*\*\ - RCC_ADCSYSCLK_DIV23 +*\*\ - RCC_ADCSYSCLK_DIV24 +*\*\ - RCC_ADCSYSCLK_DIV25 +*\*\ - RCC_ADCSYSCLK_DIV26 +*\*\ - RCC_ADCSYSCLK_DIV27 +*\*\ - RCC_ADCSYSCLK_DIV28 +*\*\ - RCC_ADCSYSCLK_DIV29 +*\*\ - RCC_ADCSYSCLK_DIV30 +*\*\ - RCC_ADCSYSCLK_DIV31 +*\*\ - RCC_ADCSYSCLK_DIV32 +*\*\ - RCC_ADCSYSCLK_DIV33 +*\*\ - RCC_ADCSYSCLK_DIV34 +*\*\ - RCC_ADCSYSCLK_DIV35 +*\*\ - RCC_ADCSYSCLK_DIV36 +*\*\ - RCC_ADCSYSCLK_DIV37 +*\*\ - RCC_ADCSYSCLK_DIV38 +*\*\ - RCC_ADCSYSCLK_DIV39 +*\*\ - RCC_ADCSYSCLK_DIV40 +*\*\ - RCC_ADCSYSCLK_DIV41 +*\*\ - RCC_ADCSYSCLK_DIV42 +*\*\ - RCC_ADCSYSCLK_DIV43 +*\*\ - RCC_ADCSYSCLK_DIV44 +*\*\ - RCC_ADCSYSCLK_DIV45 +*\*\ - RCC_ADCSYSCLK_DIV46 +*\*\ - RCC_ADCSYSCLK_DIV47 +*\*\ - RCC_ADCSYSCLK_DIV48 +*\*\ - RCC_ADCSYSCLK_DIV49 +*\*\ - RCC_ADCSYSCLK_DIV50 +*\*\ - RCC_ADCSYSCLK_DIV51 +*\*\ - RCC_ADCSYSCLK_DIV52 +*\*\ - RCC_ADCSYSCLK_DIV53 +*\*\ - RCC_ADCSYSCLK_DIV54 +*\*\ - RCC_ADCSYSCLK_DIV55 +*\*\ - RCC_ADCSYSCLK_DIV56 +*\*\ - RCC_ADCSYSCLK_DIV57 +*\*\ - RCC_ADCSYSCLK_DIV58 +*\*\ - RCC_ADCSYSCLK_DIV59 +*\*\ - RCC_ADCSYSCLK_DIV60 +*\*\ - RCC_ADCSYSCLK_DIV61 +*\*\ - RCC_ADCSYSCLK_DIV62 +*\*\ - RCC_ADCSYSCLK_DIV63 +*\*\return none. +**/ +void ADC_ConfigClk(ADC_Module* ADCx, ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t Pll_CLK_source, uint32_t RCC_ADCPrescaler) +{ + if(ADC_ClkMode == ADC_CTRL3_CKMOD_AHB) + { + ADC_SelectClockMode(ADCx, (uint32_t)ADC_CTRL3_CKMOD_AHB); + } + else + { + ADC_SelectClockMode(ADCx, (uint32_t)ADC_CLOCK_MODE_PLL); + /* Enable ADC1 PLL clocks */ + RCC_EnableAHB1PeriphClk1(RCC_AHB1_PERIPHEN_M7_ADC1PLL, ENABLE); + + if(ADCx == ADC1) + { + RCC_ConfigAdc1PllClk(Pll_CLK_source); + } + else if(ADCx == ADC2) + { + RCC_ConfigAdc2PllClk(Pll_CLK_source); + } + else if(ADCx == ADC3) + { + RCC_ConfigAdc3PllClk(Pll_CLK_source); + } + else + { + /*no process*/ + } + } + + if(ADCx == ADC1) + { + RCC_ConfigAdc1SysClk(RCC_ADCPrescaler); + } + else if(ADCx == ADC2) + { + RCC_ConfigAdc2SysClk(RCC_ADCPrescaler); + } + else if(ADCx == ADC3) + { + RCC_ConfigAdc3SysClk(RCC_ADCPrescaler); + } + else + { + /*no process*/ + } +} + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_comp.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_comp.c new file mode 100644 index 0000000000..2f2c35379b --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_comp.c @@ -0,0 +1,785 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_comp.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_comp.h" +#include "n32h76x_78x_rcc.h" + + + +#define COMP3_4_FUNCTION_ENABLE_MASK (0x00010000u) + +/** COMP Driving Functions Declaration **/ + +/** +*\*\name COMP_DeInit. +*\*\fun Reset the COMP registers. +*\*\return none +**/ +void COMP_DeInit(void) +{ + RCC_EnableRDPeriphReset2(RCC_RD_PERIPHRST_COMP); + /*Disable COMP3/4 Function*/ + AFEC->TRIMR6 &= (~COMP3_4_FUNCTION_ENABLE_MASK); +} +/** +*\*\name COMP_StructInit. +*\*\fun Fills all COMP_initstruct member with default value. +*\*\param COMP_initstruct : +*\*\ - Blking +*\*\ - Hyst +*\*\ - PolRev +*\*\ - InpSel +*\*\ - InmSel +*\*\ - FilterEn +*\*\ - ClkPsc +*\*\ - SampWindow +*\*\ - Threshold +*\*\ - En +*\*\return none +**/ +void COMP_StructInit(COMP_InitType* COMP_InitStruct) +{ + /* Initialize the Blking */ + COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; + /* Initialize the Hyst */ + COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; + /* Initialize the PolRev */ + COMP_InitStruct->PolRev = DISABLE; + /* Initialize the InpSel */ + COMP_InitStruct->InpSel = COMPX_CTRL_INPSEL_RES; + /* Initialize the InmSel */ + COMP_InitStruct->InmSel = COMPX_CTRL_INMSEL_RES; + /* Initialize the FilterEn */ + COMP_InitStruct->FilterEn = DISABLE; + /* Initialize the ClkPsc */ + COMP_InitStruct->ClkPsc = 0; + /* Initialize the SampWindow */ + COMP_InitStruct->SampWindow = 0; + /* Initialize the Threshold */ + COMP_InitStruct->Threshold = 0; + /* Initialize the En */ + COMP_InitStruct->En = DISABLE; +} +/** +*\*\name COMP_Initializes. +*\*\fun Initializes the COMPx according to COMP_initstruct. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param COMP_initstruct : +*\*\ - Blking +*\*\ - COMP_CTRL_BLKING_NO +*\*\ - COMP_CTRL_BLKING_ATIM1_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMB1_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMB2_OC5 +*\*\ - COMP_CTRL_BLKING_ATIM2_OC5 +*\*\ - COMP_CTRL_BLKING_ATIM3_OC5 +*\*\ - COMP_CTRL_BLKING_ATIM4_OC1 +*\*\ - COMP_CTRL_BLKING_GTIMB3_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMA4_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMA2_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA1_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA3_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA5_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA6_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA7_OC3 +*\*\ - Hyst +*\*\ - COMP_CTRL_HYST_NO +*\*\ - COMP_CTRL_HYST_LOW: +*\*\ - COMP_CTRL_HYST_MID: +*\*\ - COMP_CTRL_HYST_HIGH: +*\*\ - PolRev +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - vpsel +*\*\ comp1 inp sel +*\*\ - COMP1_CTRL_INPSEL_PB0 +*\*\ - COMP1_CTRL_INPSEL_PB2 +*\*\ - COMP1_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC6_IOUT +*\*\ - COMP1_CTRL_INPSEL_VREF1 +*\*\ - COMP1_CTRL_INPSEL_PF5 +*\*\ comp2 inp sel +*\*\ - COMP2_CTRL_INPSEL_PE9 +*\*\ - COMP2_CTRL_INPSEL_PE11 +*\*\ - COMP2_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC6_IOUT +*\*\ - COMP2_CTRL_INPSEL_VREF2 +*\*\ - COMP2_CTRL_INPSEL_PB2 +*\*\ - COMP2_CTRL_INPSEL_PF7 +*\*\ comp3 inp sel +*\*\ - COMP3_CTRL_INPSEL_PF2 +*\*\ - COMP3_CTRL_INPSEL_PF15 +*\*\ - COMP3_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC6_IOUT +*\*\ comp4 inp sel +*\*\ - COMP4_CTRL_INPSEL_PH10 +*\*\ - COMP4_CTRL_INPSEL_PH7 +*\*\ - COMP4_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC6_IOUT +*\*\ - COMP4_CTRL_INPSEL_PF15 +*\*\ - COMP4_CTRL_INPSEL_PF10 +*\*\ - InmSel +*\*\ comp1 inm sel +*\*\ - COMP1_CTRL_INMSEL_PB1 +*\*\ - COMP1_CTRL_INMSEL_PC4 +*\*\ - COMP1_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC6_IOUT +*\*\ - COMP1_CTRL_INMSEL_VREF1 +*\*\ - COMP1_CTRL_INMSEL_PF3 +*\*\ comp2 inm sel +*\*\ - COMP2_CTRL_INMSEL_PE7 +*\*\ - COMP2_CTRL_INMSEL_PE10 +*\*\ - COMP2_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC6_IOUT +*\*\ - COMP2_CTRL_INMSEL_VREF2 +*\*\ - COMP2_CTRL_INMSEL_PF6 +*\*\ comp3 inm sel +*\*\ - COMP3_CTRL_INMSEL_PF1 +*\*\ - COMP3_CTRL_INMSEL_PF14 +*\*\ - COMP3_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC6_IOUT +*\*\ comp4 inm sel +*\*\ - COMP4_CTRL_INMSEL_PH9 +*\*\ - COMP4_CTRL_INMSEL_PH6 +*\*\ - COMP4_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC6_IOUT +*\*\ - COMP4_CTRL_INMSEL_PH8 +*\*\ - En +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - SampWindow +*\*\ - SampWindow Value ranges from 0~31. +*\*\ - Threshold +*\*\ - Threshold Value need > SampWindow/2. +*\*\ - FilterEn +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - ClkPsc +*\*\ - ClkPsc Value ranges from 0~65535. +*\*\return none +**/ +void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct) +{ + COMP_SingleType* pCS = &COMP->Cmp[COMPx]; + __IO uint32_t temp = 0; + + /* Get the old value from COMPx_FILC register*/ + temp = pCS->FILC; + /* Set SAMPW[4:0] select bits */ + temp = ( ((uint32_t)COMP_InitStruct->SampWindow) << 6 ) & COMP_FILC_SAMPW_MASK; + /* Set THRESH[4:0] select bits */ + temp += ( ((uint32_t)COMP_InitStruct->Threshold) << 1 ) & COMP_FILC_THRESH_MASK; + /* Set FILEN select bits */ + temp += ( (uint32_t)COMP_InitStruct->FilterEn )& COMP_FILC_FILEN_MASK; + /* Store the new register value */ + pCS->FILC = temp; + /* Set CLKPSC[15:0] select bits from COMPx_FILP register*/ + pCS->FILP = COMP_InitStruct->ClkPsc; + + /* Get the old value from COMPx_CTRL register*/ + temp = pCS->CTRL; + /* Clear BLKING[3:0], BLKINGEN, POL, INMSEL[3:0], INPSEL[3:0] select bits */ + temp &= (~(COMP_CTRL_BLKING_MASK | COMP_CTRL_HYST_MASK | COMP_POL_MASK | COMP_CTRL_INPSEL_MASK | COMP_CTRL_INMSEL_MASK | COMP_CTRL_EN_MASK)); + /* Set BLKING[3:0], BLKINGEN, POL, INMSEL[3:0], INPSEL[3:0] select bits */ + temp |= ((uint32_t)COMP_InitStruct->Blking | (uint32_t)COMP_InitStruct->Hyst | \ + (uint32_t)COMP_InitStruct->InpSel | (uint32_t)COMP_InitStruct->InmSel); + + if(COMP_InitStruct->PolRev != DISABLE) + { + temp |= COMP_OUTPOL_FLIP ; + } + else + { + temp &= (~COMP_OUTPOL_FLIP); + } + + if(COMP_InitStruct->En != DISABLE) + { + temp |= COMP_CTRL_EN_MASK ; + } + else + { + temp &= (~COMP_CTRL_EN_MASK); + } + + /* Store the new register value */ + pCS->CTRL = temp; +} +/** +*\*\name COMP_Enable. +*\*\fun Configures COMPx enable or disable. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void COMP_Enable(COMPX COMPx, FunctionalState Cmd) +{ + if(Cmd != DISABLE) + { + if( (COMPx == COMP3) || (COMPx == COMP4)) + { + /*Enable COMP3/4 Function*/ + AFEC->TRIMR6 |= COMP3_4_FUNCTION_ENABLE_MASK; + } + else + { + /* no process */ + } + + COMP->Cmp[COMPx].CTRL |= COMP_CTRL_EN_MASK; + } + else + { + COMP->Cmp[COMPx].CTRL &= (~COMP_CTRL_EN_MASK); + } +} +/** +*\*\name COMP_SetInpSel. +*\*\fun Select COMPx Non-inverting input. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param vpsel : +*\*\ comp1 inp sel +*\*\ - COMP1_CTRL_INPSEL_PB0 +*\*\ - COMP1_CTRL_INPSEL_PB2 +*\*\ - COMP1_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP1_CTRL_INPSEL_DAC6_IOUT +*\*\ - COMP1_CTRL_INPSEL_VREF1 +*\*\ - COMP1_CTRL_INPSEL_PF5 +*\*\ comp2 inp sel +*\*\ - COMP2_CTRL_INPSEL_PE9 +*\*\ - COMP2_CTRL_INPSEL_PE11 +*\*\ - COMP2_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP2_CTRL_INPSEL_DAC6_IOUT +*\*\ - COMP2_CTRL_INPSEL_VREF2 +*\*\ - COMP2_CTRL_INPSEL_PB2 +*\*\ - COMP2_CTRL_INPSEL_PF7 +*\*\ comp3 inp sel +*\*\ - COMP3_CTRL_INPSEL_PF2 +*\*\ - COMP3_CTRL_INPSEL_PF15 +*\*\ - COMP3_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP3_CTRL_INPSEL_DAC6_IOUT +*\*\ comp4 inp sel +*\*\ - COMP4_CTRL_INPSEL_PH10 +*\*\ - COMP4_CTRL_INPSEL_PH7 +*\*\ - COMP4_CTRL_INPSEL_DAC1_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC2_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC3_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC4_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC5_IOUT +*\*\ - COMP4_CTRL_INPSEL_DAC6_IOUT +*\*\ - COMP4_CTRL_INPSEL_PF15 +*\*\ - COMP4_CTRL_INPSEL_PF10 +*\*\return none +**/ +void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel) +{ + __IO uint32_t tmp ; + /* Get the old value from COMPx_CTRL register*/ + tmp = COMP->Cmp[COMPx].CTRL; + /* Clear INPSEL[3:0] select bits */ + tmp &= (~COMP_CTRL_INPSEL_MASK); + /* Set INPSEL[3:0] select bits */ + tmp |= (uint32_t)VpSel; + /* Store the new register value */ + COMP->Cmp[COMPx].CTRL = tmp; +} +/** +*\*\name COMP_SetInmSel. +*\*\fun Select COMPx inverting input. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param vmsel : +*\*\ comp1 inm sel +*\*\ - COMP1_CTRL_INMSEL_PB1 +*\*\ - COMP1_CTRL_INMSEL_PC4 +*\*\ - COMP1_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP1_CTRL_INMSEL_DAC6_IOUT +*\*\ - COMP1_CTRL_INMSEL_VREF1 +*\*\ - COMP1_CTRL_INMSEL_PF3 +*\*\ comp2 inm sel +*\*\ - COMP2_CTRL_INMSEL_PE7 +*\*\ - COMP2_CTRL_INMSEL_PE10 +*\*\ - COMP2_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP2_CTRL_INMSEL_DAC6_IOUT +*\*\ - COMP2_CTRL_INMSEL_VREF2 +*\*\ - COMP2_CTRL_INMSEL_PF6 +*\*\ comp3 inm sel +*\*\ - COMP3_CTRL_INMSEL_PF1 +*\*\ - COMP3_CTRL_INMSEL_PF14 +*\*\ - COMP3_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP3_CTRL_INMSEL_DAC6_IOUT +*\*\ comp4 inm sel +*\*\ - COMP4_CTRL_INMSEL_PH9 +*\*\ - COMP4_CTRL_INMSEL_PH6 +*\*\ - COMP4_CTRL_INMSEL_DAC1_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC2_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC3_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC4_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC5_IOUT +*\*\ - COMP4_CTRL_INMSEL_DAC6_IOUT +*\*\ - COMP4_CTRL_INMSEL_PH8 +*\*\return none +**/ +void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel) +{ + __IO uint32_t tmp ; + /* Get the old value from COMPx_CTRL register*/ + tmp = COMP->Cmp[COMPx].CTRL; + /* Clear INMSEL[3:0] select bits */ + tmp &= (~COMP_CTRL_INMSEL_MASK); + /* Set INMSEL[3:0] select bits */ + tmp |= (uint32_t)VmSel; + /* Store the new register value */ + COMP->Cmp[COMPx].CTRL = tmp; +} + +/** +*\*\name COMP_SetLowPowerMode. +*\*\fun Enables or disables working in low power mode for COMP. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void COMP_SetLowPowerMode(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable low power mode */ + COMP->LPR |= (uint32_t)COMP_LPMODE_LP_EN_MASK; + } + else + { + /* Disable low power mode */ + COMP->LPR &= (~(uint32_t)COMP_LPMODE_LP_EN_MASK); + } +} + +/** +*\*\name COMP_SetLock. +*\*\fun Configures which COMPx will be Locked. +*\*\param Lock : +*\*\ - COMP1_LOCK +*\*\ - COMP2_LOCK +*\*\ - COMP3_LOCK +*\*\ - COMP4_LOCK +*\*\return none +**/ +void COMP_SetLock(uint32_t Lock) +{ + COMP->LOCK = Lock; +} + +/** +*\*\name COMP_SetIntEn. +*\*\fun Configures COMPx interrupt enable or disable. +*\*\param IntEn : +*\*\ - COMP1_INTEN +*\*\ - COMP2_INTEN +*\*\ - COMP3_INTEN +*\*\ - COMP4_INTEN +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void COMP_SetIntEn(uint32_t IntEn, FunctionalState Cmd) +{ + if(Cmd != DISABLE) + { + COMP->INTEN |= IntEn; + } + else + { + COMP->INTEN &= ~IntEn; + } +} + +/** +*\*\name COMP_WindowModeEnable. +*\*\fun Configures COMPx window mode enable or disable. +*\*\param WinModeEn : +*\*\ - COMP_WINMODE_CMP12MD +*\*\ - COMP_WINMODE_CMP34MD +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void COMP_WindowModeEnable(uint32_t WinModeEn, FunctionalState Cmd) +{ + if(Cmd != DISABLE) + { + COMP->WINMODE |= WinModeEn; + } + else + { + COMP->WINMODE &= (~WinModeEn); + } +} +/** +*\*\name COMP_SetRefScl. +*\*\fun Configures the COMP reference voltage. +*\*\param Vv2Trim : +*\*\ - Value can be set from 0 to 63. +*\*\param Vv2En : +*\*\ - false +*\*\ - true +*\*\param Vv1Trim : +*\*\ - Value can be set from 0 to 63. +*\*\param Vv1En : +*\*\ - false +*\*\ - true +*\*\return none +**/ +void COMP_SetRefScl( uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En) +{ + __IO uint32_t temp = 0; + /* Get the old value from COMP1_CTRL register*/ + temp = COMP->Cmp[COMP1].CTRL; + /* Clear VV1EN, VV1TRM[5:0] select bits */ + temp &= (~(COMP_VREFSCL_VVEN_MSK | COMP_VREFSCL_VVTRM_MSK ) ); + /* Set VV1EN, VV1TRM[5:0] select bits */ + temp |= ((uint32_t)(Vv1En ? (1UL << 22U) : 0) + ((uint32_t)Vv1Trim << 23U )) ; + /* Store the new register value */ + COMP->Cmp[COMP1].CTRL = temp; + + /* Get the old value from COMP2_CTRL register*/ + temp = COMP->Cmp[COMP2].CTRL; + /* Clear VV2EN, VV2TRM[5:0] select bits */ + temp &= (~(COMP_VREFSCL_VVEN_MSK | COMP_VREFSCL_VVTRM_MSK ) ); + /* Set VV2EN, VV2TRM[5:0] select bits */ + temp |= ((uint32_t)(Vv2En ? (1UL << 22U) : 0) + ((uint32_t)Vv2Trim << 23U )) ; + /* Store the new register value */ + COMP->Cmp[COMP2].CTRL = temp; +} +/** +*\*\name COMP_GetOutStatus. +*\*\fun Get COMPx output status. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus COMP_GetOutStatus(COMPX COMPx) +{ + return ((COMP->Cmp[COMPx].CTRL & COMP_CTRL_OUT_MASK) != 0U) ? SET : RESET; +} + +/** +*\*\name COMP_GetIntStsOneComp. +*\*\fun Get COMPx interrupt Status. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\return +*\*\ - RESET : COMPx Interrupt status is reset; +*\*\ - SET : COMPx Interrupt status is set; +**/ +FlagStatus COMP_GetIntStsOneComp(COMPX COMPx) +{ + return ((COMP->INTSTS & ((uint32_t)0x01U << COMPx)) != 0U) ? SET : RESET; +} + +/** +*\*\name COMP_ClearIntStsOneComp. +*\*\fun Clear COMPx interrupt Status. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\return none +**/ +void COMP_ClearIntStsOneComp(COMPX COMPx) +{ + COMP->INTSTS &= ((~(0x01U << COMPx ))); +} + +/** +*\*\name COMP_OutToTimEnable. +*\*\fun Enable or disable the output channel to timer . +*\*\param TimEn : +*\*\ - COMP1_TIM_EN +*\*\ - COMP2_TIM_EN +*\*\ - COMP3_TIM_EN +*\*\ - COMP4_TIM_EN +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void COMP_OutToTimEnable(uint32_t TimEn, FunctionalState Cmd) +{ + if(Cmd != DISABLE) + { + COMP->OTIMEN |= TimEn; + } + else + { + COMP->OTIMEN &= (~TimEn); + } +} + +/** +*\*\name COMP_SetFilterPrescaler. +*\*\fun Set the COMP filter clock Prescaler value. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param FilPreVal : +*\*\ - Value can be set from 0 to 65535. +*\*\return none +**/ +void COMP_SetFilterPrescaler(COMPX COMPx, uint16_t FilPreVal) +{ + COMP->Cmp[COMPx].FILP = FilPreVal; +} + +/** +*\*\name COMP_SetFilterControl. +*\*\fun Configures the COMP filter control value. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param FilEn : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\param TheresNum : +*\*\ - Threshold Value need > SampWindow/2. +*\*\param SampPW : +*\*\ - Value can be set from 0 to 31. +*\*\return none +**/ +void COMP_SetFilterControl(COMPX COMPx, uint8_t FilEn, uint8_t TheresNum, uint8_t SampPW) +{ + COMP->Cmp[COMPx].FILC = (uint32_t)(FilEn & COMP_FILC_FILEN_MASK) + (((uint32_t)TheresNum << 1)&COMP_FILC_THRESH_MASK) + (((uint32_t)SampPW << 6)& COMP_FILC_SAMPW_MASK); +} + +/** +*\*\name COMP_SetVflagEnable. +*\*\fun Enable or disable using DAC stable value as Comparator's positive or negetive inputs. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\param InputMode : +*\*\ - COMP_VFLAG_P +*\*\ - COMP_VFLAG_N +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note COMP3 and COMP4 couldn't using this fuction. +**/ +void COMP_EnableVflag(COMPX COMPx, uint32_t InputMode, FunctionalState Cmd) +{ + if(Cmd != DISABLE) + { + COMP->Cmp[COMPx].FILC |= InputMode; + } + else + { + COMP->Cmp[COMPx].FILC &= (~InputMode); + } +} + + +/** +*\*\name COMP_SetHyst. +*\*\fun Configures COMPx hysteresis level. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param HYST : +*\*\ - COMP_CTRL_HYST_NO +*\*\ - COMP_CTRL_HYST_LOW +*\*\ - COMP_CTRL_HYST_MID +*\*\ - COMP_CTRL_HYST_HIGH +*\*\return none +**/ +void COMP_SetHyst(COMPX COMPx, COMP_CTRL_HYST HYST) +{ + uint32_t temp; + /* Get the old value from COMPx_CTRL register*/ + temp = COMP->Cmp[COMPx].CTRL; + /* Clear HYST[1:0] select bits */ + temp &= (~COMP_CTRL_HYST_MASK); + /* Set HYST[1:0] select bits */ + temp |= (uint32_t)HYST; + /* Store the new register value */ + COMP->Cmp[COMPx].CTRL = temp; +} + +/** +*\*\name COMP_SetBlanking. +*\*\fun Configures which TIMx output signal to control COMPx Blking. +*\*\param COMPx : +*\*\ - COMP1 +*\*\ - COMP2 +*\*\ - COMP3 +*\*\ - COMP4 +*\*\param BLK : +*\*\ - COMP_CTRL_BLKING_NO +*\*\ - COMP_CTRL_BLKING_ATIM1_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMB1_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMB2_OC5 +*\*\ - COMP_CTRL_BLKING_ATIM2_OC5 +*\*\ - COMP_CTRL_BLKING_ATIM3_OC5 +*\*\ - COMP_CTRL_BLKING_ATIM4_OC1 +*\*\ - COMP_CTRL_BLKING_GTIMB3_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMA4_OC5 +*\*\ - COMP_CTRL_BLKING_GTIMA2_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA1_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA3_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA5_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA6_OC3 +*\*\ - COMP_CTRL_BLKING_GTIMA7_OC3 +*\*\return none +**/ +void COMP_SetBlanking(COMPX COMPx, COMP_CTRL_BLKING BLK) +{ + uint32_t temp; + /* Get the old value from COMPx_CTRL register*/ + temp = COMP->Cmp[COMPx].CTRL; + /* Clear HYST[3:0] select bits */ + temp &= (~COMP_CTRL_BLKING_MASK); + /* Set HYST[3:0] select bits */ + temp |= (uint32_t)BLK; + /* Store the new register value */ + COMP->Cmp[COMPx].CTRL = temp; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_cordic.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_cordic.c new file mode 100644 index 0000000000..e2cc0d27c8 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_cordic.c @@ -0,0 +1,392 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_cordic.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_cordic.h" +#include "n32h76x_78x_rcc.h" + +/** CORDIC Private Defines **/ + +#define CORDIC_CTRLSTS_MASK ((uint32_t)0x07F807FFU) + + +/** CORDIC Driving Functions Declaration **/ + +/** +*\*\name CORDIC_DeInit. +*\*\fun DeInitializes the CORDIC peripheral. +*\*\param none +*\*\return none +**/ +void CORDIC_DeInit(void) +{ + /* CORDIC peripheral reset */ + RCC_EnableAHB2PeriphReset1(RCC_AHB2_PERIPHRST_CORDIC); +} + +/** +*\*\name CORDIC_Init. +*\*\fun Initialize the CORDIC module with CORDIC_InitParam of type CORDIC_InitType. +*\*\param CORDIC_InitParam : +*\*\ - Function +*\*\ - CORDIC_FUNCTION_COSINE +*\*\ - CORDIC_FUNCTION_SINE +*\*\ - CORDIC_FUNCTION_PHASE +*\*\ - CORDIC_FUNCTION_MODULUS +*\*\ - CORDIC_FUNCTION_ARCTANGENT +*\*\ - CORDIC_FUNCTION_HCOSINE +*\*\ - CORDIC_FUNCTION_HSINE +*\*\ - CORDIC_FUNCTION_HARCTANGENT +*\*\ - CORDIC_FUNCTION_NATURALLOG +*\*\ - CORDIC_FUNCTION_SQUAREROOT +*\*\ - Precision +*\*\ - CORDIC_PRECISION_1CYCLE +*\*\ - CORDIC_PRECISION_2CYCLES +*\*\ - CORDIC_PRECISION_3CYCLES +*\*\ - CORDIC_PRECISION_4CYCLES +*\*\ - CORDIC_PRECISION_5CYCLES +*\*\ - CORDIC_PRECISION_6CYCLES +*\*\ - CORDIC_PRECISION_7CYCLES +*\*\ - CORDIC_PRECISION_8CYCLES +*\*\ - CORDIC_PRECISION_9CYCLES +*\*\ - CORDIC_PRECISION_10CYCLES +*\*\ - CORDIC_PRECISION_11CYCLES +*\*\ - CORDIC_PRECISION_12CYCLES +*\*\ - CORDIC_PRECISION_13CYCLES +*\*\ - CORDIC_PRECISION_14CYCLES +*\*\ - CORDIC_PRECISION_15CYCLES +*\*\ - Scale +*\*\ - CORDIC_SCALE_0 +*\*\ - CORDIC_SCALE_1 +*\*\ - CORDIC_SCALE_2 +*\*\ - CORDIC_SCALE_3 +*\*\ - CORDIC_SCALE_4 +*\*\ - CORDIC_SCALE_5 +*\*\ - CORDIC_SCALE_6 +*\*\ - CORDIC_SCALE_7 +*\*\ - NbWrite +*\*\ - CORDIC_NBWRITE_1 +*\*\ - CORDIC_NBWRITE_2 +*\*\ - NbRead +*\*\ - CORDIC_NBREAD_1 +*\*\ - CORDIC_NBREAD_2 +*\*\ - InSize +*\*\ - CORDIC_INSIZE_16BITS +*\*\ - CORDIC_INSIZE_32BITS +*\*\ - OutSize +*\*\ - CORDIC_OUTSIZE_16BITS +*\*\ - CORDIC_OUTSIZE_32BITS +*\*\ - InSelect +*\*\ - CORDIC_INPUT_FIX +*\*\ - CORDIC_INPUT_FLOAT +*\*\ - OutSelect +*\*\ - CORDIC_OUTPUT_FIX +*\*\ - CORDIC_OUTPUT_FLOAT +*\*\ - CodinLimit +*\*\ - CORDIC_CODIN_LIMIT_DISABLE +*\*\ - CORDIC_CODIN_LIMIT_ENABLE +*\*\ - PhaseLimit +*\*\ - CORDIC_PHASE_LIMIT_DISABLE +*\*\ - CORDIC_PHASE_LIMIT_ENABLE +*\*\return none +**/ +void CORDIC_Init(CORDIC_InitType* CORDIC_InitParam) +{ + uint32_t TempValue; + + /* Configure the CORDIC_CTRLSTS register, including setting CODINLIMIT, PHASELIMIT, + FLOATOUT, FLOATIN, INSIZE, OUTSIZE, NUMWRITE, NUMREAD, SCALE[2:0], PRECISION[3:0], + FUNC[3:0] bits */ + TempValue = ((CORDIC_InitParam->Function) | (CORDIC_InitParam->Precision) + | (CORDIC_InitParam->Scale) | (CORDIC_InitParam->NbWrite) + | (CORDIC_InitParam->NbRead) | (CORDIC_InitParam->InSize) + | (CORDIC_InitParam->OutSize) | (CORDIC_InitParam->InSelect) + | (CORDIC_InitParam->OutSelect) | (CORDIC_InitParam->CodinLimit) + | (CORDIC_InitParam->PhaseLimit)); + + /* Write to CORDIC_CTRLSTS */ + MODIFY_REG(CORDIC->CTRLSTS, CORDIC_CTRLSTS_MASK, TempValue); +} + +/** +*\*\name CORDIC_StructInit. +*\*\fun Initializes the structure parameter of type CORDIC_InitType used to +*\*\ initialize CORDIC. This function is usually called before initializing +*\*\ a parameter of type CORDIC_InitType. +*\*\param CORDIC_InitParam : +*\*\ - Function +*\*\ - Precision +*\*\ - Scale +*\*\ - NbWrite +*\*\ - NbRead +*\*\ - InSize +*\*\ - OutSize +*\*\ - InSelect +*\*\ - OutSelect +*\*\ - CodinLimit +*\*\ - PhaseLimit +*\*\return none +**/ +void CORDIC_StructInit(CORDIC_InitType* CORDIC_InitParam) +{ + /** Set the default configuration **/ + + /* Default Select the function: cosine */ + CORDIC_InitParam->Function = CORDIC_FUNCTION_COSINE; + /* Default Set the number of iterations: 5 */ + CORDIC_InitParam->Precision = CORDIC_PRECISION_5CYCLES; + /* Default Select the Scaling Factor: 0 */ + CORDIC_InitParam->Scale = CORDIC_SCALE_0; + /* Default Select the number of CORDIC_WDAT register to write: 1 */ + CORDIC_InitParam->NbWrite = CORDIC_NBWRITE_1; + /* Default Select the number of CORDIC_RDAT register to read: 1 */ + CORDIC_InitParam->NbRead = CORDIC_NBREAD_1; + /* Default Select the input data width: 32bit */ + CORDIC_InitParam->InSize = CORDIC_INSIZE_32BITS; + /* Default Select the output data width: 32bit */ + CORDIC_InitParam->OutSize = CORDIC_OUTSIZE_32BITS; + /* Default Select the fixed-point input */ + CORDIC_InitParam->InSelect = CORDIC_INPUT_FIX; + /* Default Select the fixed-point output */ + CORDIC_InitParam->OutSelect = CORDIC_OUTPUT_FIX; + /* Default Disable Coordinate Limit function */ + CORDIC_InitParam->CodinLimit = CORDIC_CODIN_LIMIT_DISABLE; + /* Default Disable Phase Limit function */ + CORDIC_InitParam->PhaseLimit = CORDIC_PHASE_LIMIT_DISABLE; +} + +/** +*\*\name CORDIC_InterruptCmd. +*\*\fun Enables or disables the specified CORDIC interrupts. +*\*\param Interrupt: +*\*\ - CORDIC_INT +*\*\ - CORDIC_INT_INOVERFLOW +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void CORDIC_InterruptCmd(uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected CORDIC interrupt */ + SET_BIT(CORDIC->CTRLSTS, Interrupt); + } + else + { + /* Disable the selected CORDIC interrupt */ + CLEAR_BIT(CORDIC->CTRLSTS, Interrupt); + } +} + +/** +*\*\name CORDIC_DMAReadRequestCmd. +*\*\fun Enables or disables the CORDIC DMA read request. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void CORDIC_DMAReadRequestCmd(FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable CORDIC DMA read request */ + SET_BIT(CORDIC->CTRLSTS, CORDIC_CTRLSTS_DMAREN); + } + else + { + /* Disable CORDIC DMA read request */ + CLEAR_BIT(CORDIC->CTRLSTS, CORDIC_CTRLSTS_DMAREN); + } +} + +/** +*\*\name CORDIC_DMAWriteRequestCmd. +*\*\fun Enables or disables the CORDIC DMA write request. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void CORDIC_DMAWriteRequestCmd(FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable CORDIC DMA write request */ + SET_BIT(CORDIC->CTRLSTS, CORDIC_CTRLSTS_DMAWEN); + } + else + { + /* Disable CORDIC DMA write request */ + CLEAR_BIT(CORDIC->CTRLSTS, CORDIC_CTRLSTS_DMAWEN); + } +} + +/** +*\*\name CORDIC_GetRegisterAddr. +*\*\fun Get the CORDIC data register address used for DMA transfer. +*\*\param Direction: +*\*\ - CORDIC_AS_DMA_SRCADDR +*\*\ - CORDIC_AS_DMA_DSTADDR +*\*\return Address of data register. +**/ +uint32_t CORDIC_GetRegisterAddr(uint32_t Direction) +{ + uint32_t Address; + + /* Check the direction of transmission */ + if (Direction == CORDIC_AS_DMA_DSTADDR) + { + /* Get address of WDAT register */ + Address = (uint32_t) & (CORDIC->WDAT); + } + else + { + /* Get address of RDAT register */ + Address = (uint32_t) & (CORDIC->RDAT); + } + + /* Return address value */ + return Address; +} + +/** +*\*\name CORDIC_WriteData. +*\*\fun Write 32-bit input data for the CORDIC processing. +*\*\param pInData : +*\*\ - Points to the address of input data +*\*\return none +**/ +void CORDIC_WriteData(uint32_t *pInData) +{ + /* Write WDAT register */ + WRITE_REG(CORDIC->WDAT, *pInData); +} + +/** +*\*\name CORDIC_ReadData. +*\*\fun Return 32-bit output data of CORDIC processing. +*\*\param pOutData : +*\*\ - Points to the address where the output data is stored +*\*\return none. +**/ +void CORDIC_ReadData(uint32_t *pOutData) +{ + /* Read RDAT register */ + *pOutData = READ_REG(CORDIC->RDAT); +} + +/** +*\*\name CORDIC_GetFlagStatus. +*\*\fun Checks whether the specified CORDIC flag is set or not. +*\*\param Flag: +*\*\ - CORDIC_FLAG_RRF +*\*\ - CORDIC_FLAG_INOVF +*\*\ - CORDIC_FLAG_DMAWENF +*\*\ - CORDIC_FLAG_DMARENF +*\*\ - CORDIC_FLAG_INTENF +*\*\ - CORDIC_FLAG_INOVINTENF +*\*\return FlagStatus: +*\*\ - RESET : Corresponding flag bit is reset +*\*\ - SET : Corresponding flag bit is set +**/ +FlagStatus CORDIC_GetFlagStatus(uint32_t Flag) +{ + FlagStatus Status; + + /* Read and return the status of the corresponding flag bits */ + if(READ_BIT(CORDIC->CTRLSTS, Flag) != (uint32_t)RESET) + { + /* Flag is set */ + Status = SET; + } + else + { + /* Flag is reset */ + Status = RESET; + } + + /* Return flag status */ + return Status; +} + +/** +*\*\name CORDIC_ClearStatusFlag. +*\*\fun Clears the pending flag for the CORDIC. +*\*\param Flag : +*\*\ - CORDIC_FLAG_INOVF +*\*\ - CORDIC_FLAG_DMAWENF +*\*\ - CORDIC_FLAG_DMARENF +*\*\ - CORDIC_FLAG_INTENF +*\*\ - CORDIC_FLAG_INOVINTENF +*\*\return none +*\*\note The RRF flag cannot be cleared by a call to this function; +*\*\ the RRF flag is cleared by hardware when reading the data +*\*\ register is complete. +**/ +void CORDIC_ClearStatusFlag(uint32_t Flag) +{ + if (Flag == CORDIC_FLAG_INOVF) + { + /* Clear the input parameter overflow flag */ + SET_BIT(CORDIC->CTRLSTS, Flag); + } + else + { + /* Clear other flags except RRF */ + CLEAR_BIT(CORDIC->CTRLSTS, Flag); + } +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_crc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_crc.c new file mode 100644 index 0000000000..ebe92fd5c4 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_crc.c @@ -0,0 +1,469 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_crc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_crc.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name CRC_ResetCalculation. +*\*\fun Reset the CRC calculation unit. +*\*\param none +*\*\return none +*\*\note It also set the Data Register to the value stored in the CRC_INIT register. +**/ +void CRC_ResetCalculation(void) +{ + CRC->CTRL |= CRC_CTRL_RESET; + + while((CRC->CTRL & CRC_CTRL_RESET) != 0U) + { + } +} + + +/** +*\*\name CRC_DeInit. +*\*\fun Reset the CRC registers to their default values. +*\*\param none +*\*\return none +**/ +void CRC_DeInit(void) +{ + RCC_EnableAHB5PeriphReset2(RCC_AHB5_PERIPHRST_CRC); +} + + +/** +*\*\name CRC_SetInputByteOrder. +*\*\fun Configure the reversal of the byte order of the input data. +*\*\param ReverseMode This parameter can be one of the following values: +*\*\ - CRC_INDATA_BYTE_REVERSE_NONE +*\*\ - CRC_INDATA_BYTE_REVERSE_HALFWORD +*\*\ - CRC_INDATA_BYTE_REVERSE_WORD +*\*\return None +**/ +void CRC_SetInputByteOrder(uint32_t ReverseMode) +{ + CRC->CTRL = ((CRC->CTRL & (~CRC_CTRL_BYTEENDIAN)) | ReverseMode); +} + +/** +*\*\name CRC_SetInputBitOrder. +*\*\fun Configure the reversal of the bit order of the input data +*\*\param ReverseMode This parameter can be one of the following values: +*\*\ - CRC_INDATA_BIT_REVERSE_NONE +*\*\ - CRC_INDATA_BIT_REVERSE_BYTE +*\*\ - CRC_INDATA_BIT_REVERSE_HALFWORD +*\*\ - CRC_INDATA_BIT_REVERSE_WORD +*\*\return None +**/ +void CRC_SetInputBitOrder(uint32_t ReverseMode) +{ + CRC->CTRL = ((CRC->CTRL & (~CRC_CTRL_REVIN)) | ReverseMode); +} + +/** +*\*\name CRC_SetOutputBitOrder. +*\*\fun Configure the reversal of the bit order of the Output data +*\*\param ReverseMode This parameter can be one of the following values: +*\*\ - CRC_OUTDATA_REVERSE_NONE +*\*\ - CRC_OUTDATA_REVERSE_BIT +*\*\return None +**/ +void CRC_SetOutputBitOrder(uint32_t ReverseMode) +{ + CRC->CTRL = ((CRC->CTRL & (~CRC_CTRL_REVOUT)) | ReverseMode); +} + +/** +*\*\name CRC_SetInputDataXor. +*\*\fun Configure the CRC_DAT XOR calculation value before CRC calculation. +*\*\param xor_value: 32-bit data to be writting into CRC_INXORDAT register. +*\*\return None +**/ +void CRC_SetInputDataXor(uint32_t xor_value) +{ + CRC->INXORDAT = xor_value; +} + +/** +*\*\name CRC_SetOutputDataXor. +*\*\fun Configure the CRC_DAT XOR calculation value after CRC calculation. +*\*\param xor_value: 32-bit data to be writting into CRC_OUTXORDAT register +*\*\return None +**/ +void CRC_SetOutputDataXor(uint32_t xor_value) +{ + CRC->OUTXORDAT = xor_value; +} + +/** +*\*\name CRC_SetInitialData. +*\*\fun Initialize the Programmable initial CRC value. +*\*\param InitCrc: 32-bit data to be writting into CRC_INIT register +*\*\return None +**/ +void CRC_SetInitialData(uint32_t InitCrc) +{ + CRC->INIT = InitCrc; +} + +/** +*\*\name CRC_SetPolynomialCoef. +*\*\fun Initialize the Programmable polynomial value +*\*\ (coefficients of the polynomial to be used for CRC calculation). +*\*\param PolynomCoef Value to be writting into CRC_POL register +*\*\return None +**/ +void CRC_SetPolynomialCoef(uint32_t PolynomCoef) +{ + CRC->POL = PolynomCoef; +} + +/** +*\*\name CRC_SetPolynomialSize. +*\*\fun Configure size of the polynomial. +*\*\param PolySize This parameter can be one of the following values: +*\*\ - CRC_POLYLENGTH_32B +*\*\ - CRC_POLYLENGTH_16B +*\*\ - CRC_POLYLENGTH_8B +*\*\ - CRC_POLYLENGTH_7B +*\*\return None +**/ +void CRC_SetPolynomialSize(uint32_t PolySize) +{ + CRC->CTRL = ((CRC->CTRL & (~CRC_CTRL_POLYSIZE)) | PolySize); +} + +/** +*\*\name CRC_GetLRC. +*\*\fun Return the computed LRC value. +*\*\param None +*\*\return The computed LRC value + */ +uint32_t CRC_GetLRC(void) +{ + uint32_t temp; + + temp = CRC->LRC; + return temp; +} + +/** +*\*\name CRC_GetIDAT. +*\*\fun Return the data in independent data register. +*\*\param None +*\*\return Data in independent data register. +**/ +uint32_t CRC_GetIDAT(void) +{ + uint32_t temp; + + temp = CRC->IDAT; + return temp; +} + +/** +*\*\name CRC_WriteIDAT. +*\*\fun Write independent data register. +*\*\param Idat : Value to be programmed in independent register +*\*\return None +**/ +void CRC_WriteIDAT(uint32_t Idat) +{ + CRC->IDAT = Idat; +} + +/** +*\*\name CRC_Init. +*\*\fun Initialize the CRC according to the specified parameters in the CRC_InitType. +*\*\param CRC_InitStruct : +*\*\ - GeneratingPolynomial: The coefficients of the polynomial. +*\*\ - CRCLength +*\*\ - CRC_POLYLENGTH_32B +*\*\ - CRC_POLYLENGTH_16B +*\*\ - CRC_POLYLENGTH_8B +*\*\ - CRC_POLYLENGTH_7B +*\*\ - InitValue: 32-bit data +*\*\ - InputDataByteInversionMode +*\*\ - CRC_INDATA_BYTE_REVERSE_NONE +*\*\ - CRC_INDATA_BYTE_REVERSE_HALFWORD +*\*\ - CRC_INDATA_BYTE_REVERSE_WORD +*\*\ - InputDataBitInversionMode +*\*\ - CRC_INDATA_BIT_REVERSE_NONE +*\*\ - CRC_INDATA_BIT_REVERSE_BYTE +*\*\ - CRC_INDATA_BIT_REVERSE_HALFWORD +*\*\ - CRC_INDATA_BIT_REVERSE_WORD +*\*\ - OutputDataInversionMode +*\*\ - CRC_OUTPUTDATA_INVERSION_DISABLE +*\*\ - CRC_OUTPUTDATA_INVERSION_ENABLE +*\*\ - InputDataXor: 32-bit data +*\*\ - OutputDataXor: 32-bit data +*\*\return none +**/ +void CRC_Init(CRC_InitType *CRC_InitStruct) +{ + /* Set generating polynomial defined by user */ + CRC_SetPolynomialSize(CRC_InitStruct->CRCLength); + CRC_SetPolynomialCoef(CRC_InitStruct->GeneratingPolynomial); + + /* Set initial value defined by user */ + CRC_SetInitialData(CRC_InitStruct->InitValue); + + /* Set input data byte inversion mode */ + CRC_SetInputByteOrder(CRC_InitStruct->InputDataByteInversionMode); + /* Set input data bit inversion mode */ + CRC_SetInputBitOrder(CRC_InitStruct->InputDataBitInversionMode); + /* Set output data inversion mode */ + CRC_SetOutputBitOrder(CRC_InitStruct->OutputDataInversionMode); + + /* Set input data xor mode */ + CRC_SetInputDataXor(CRC_InitStruct->InputDataXor); + /* Set output data xor mode */ + CRC_SetOutputDataXor(CRC_InitStruct->OutputDataXor); +} + +/** +*\*\name CRC_StructInit. +*\*\fun Initialize the CRC structure +*\*\param CRC_InitStruct +*\*\ - GeneratingPolynomial +*\*\ - CRCLength +*\*\ - InitValue +*\*\ - InputDataByteInversionMode +*\*\ - InputDataBitInversionMode +*\*\ - OutputDataInversionMode +*\*\ - InputDataXor +*\*\ - OutputDataXor +*\*\return none +**/ +void CRC_StructInit(CRC_InitType *CRC_InitStruct) +{ + CRC_InitStruct->CRCLength = CRC_POLYLENGTH_32B; + CRC_InitStruct->GeneratingPolynomial = DEFAULT_CRC32_POLY; + CRC_InitStruct->InitValue = DEFAULT_CRC_INITVALUE; + CRC_InitStruct->InputDataByteInversionMode = CRC_INDATA_BYTE_REVERSE_NONE; + CRC_InitStruct->InputDataBitInversionMode = CRC_INDATA_BIT_REVERSE_NONE; + CRC_InitStruct->OutputDataInversionMode = CRC_OUTDATA_REVERSE_NONE; + CRC_InitStruct->InputDataXor = 0x00000000; + CRC_InitStruct->OutputDataXor = 0x00000000; +} + + +/** +*\*\name CRC_Handle_8 +*\*\fun Enter 8-bit input data to the CRC calculator. +*\*\param pBuffer pointer to the input data buffer +*\*\param BufferLength input data buffer length,count in Bytes +*\*\return 32-bit CRC result +*\*\note If CRC length is shorter than 32-bits,LSBs is used. +**/ +static uint32_t CRC_Handle_8( uint8_t *pBuffer, uint32_t BufferLength) +{ + uint32_t i; + uint16_t data; + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + CRC->DAT = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&CRC->DAT) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&CRC->DAT); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&CRC->DAT); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&CRC->DAT) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } + + /* Return the CRC computed value */ + return CRC->DAT; +} + +/** +*\*\name CRC_Handle_16 +*\*\fun Enter 16-bit input data to the CRC calculator. +*\*\param pBuffer pointer to the input data buffer +*\*\param BufferLength input data buffer length,count in Half-words +*\*\return 32-bit CRC result +*\*\note If CRC length is shorter than 32-bits,LSBS is used. +**/ +static uint32_t CRC_Handle_16(uint16_t *pBuffer, uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + { + CRC->DAT = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + } + + if ((BufferLength % 2U) != 0U) + { + pReg = (__IO uint16_t *)(__IO void *)(&CRC->DAT); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; + } + + /* Return the CRC computed value */ + return CRC->DAT; +} + +/** +*\*\name CRC_Accumulate +*\*\fun Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer +*\*\ starting with the previously computed CRC result as initialization value. +*\*\param InputDataFormat +*\*\ - CRC_INPUTDATA_FORMAT_WORDS +*\*\ - CRC_INPUTDATA_FORMAT_BYTES +*\*\ - CRC_INPUTDATA_FORMAT_HALFWORDS +*\*\param pBuffer pointer to the input data buffer, exact input data format is +*\*\ provided by InputDataFormat. +*\*\param BufferLength input data buffer length,and: +*\*\ - if InputDataFormat is CRC_INPUTDATA_FORMAT_WORDS,count in words(32bit) +*\*\ - if InputDataFormat is CRC_INPUTDATA_FORMAT_BYTES,count in bytes(8bit) +*\*\ - if InputDataFormat is CRC_INPUTDATA_FORMAT_HALFWORDS,count in half-words(16bit) +*\*\return 32-bit CRC result +*\*\note If the length of CRC result is shorter than 32-bits,only LSB is used. +**/ +uint32_t CRC_Accumulate(uint32_t InputDataFormat, void *pBuffer, uint32_t BufferLength) +{ + uint32_t i; + uint32_t temp = 0U; + uint32_t *pWord; + + switch (InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + pWord = (uint32_t *)pBuffer; + + /* Enter 32-bit input data to the CRC calculator */ + for (i = 0U; i < BufferLength; i++) + { + CRC->DAT = pWord[i]; + } + + temp = CRC->DAT; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8((uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16( (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + } + + /* Return the CRC computed value */ + return temp; +} + +/** +*\*\name CRC_Calculate +*\*\fun Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer +*\*\ starting with CRC_INIT as initialization value. +*\*\param InputDataFormat +*\*\ - CRC_INPUTDATA_FORMAT_WORDS +*\*\ - CRC_INPUTDATA_FORMAT_BYTES +*\*\ - CRC_INPUTDATA_FORMAT_HALFWORDS +*\*\param pBuffer pointer to the input data buffer, exact input data format is +*\*\ provided by InputDataFormat. +*\*\param BufferLength input data buffer length,and: +*\*\ - if InputDataFormat is CRC_INPUTDATA_FORMAT_WORDS,count in words(32bit) +*\*\ - if InputDataFormat is CRC_INPUTDATA_FORMAT_BYTES,count in bytes(8bit) +*\*\ - if InputDataFormat is CRC_INPUTDATA_FORMAT_HALFWORDS,count in half-words(16bit) +*\*\return 32-bit CRC result +*\*\note If the length of CRC result is shorter than 32-bits,only LSB is used. +**/ +uint32_t CRC_Calculate(uint32_t InputDataFormat, void *pBuffer, uint32_t BufferLength) +{ + /* Reset CRC Calculation Unit (CRC_INIT is written in CRC_DAT) */ + CRC_ResetCalculation(); + + /* Return the CRC computed value */ + return (CRC_Accumulate(InputDataFormat, pBuffer, BufferLength)); +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dac.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dac.c new file mode 100644 index 0000000000..191bac6c28 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dac.c @@ -0,0 +1,1340 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dac.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "string.h" +#include "n32h76x_78x_dac.h" +#include "n32h76x_78x_rcc.h" + + +/** DAC_Private_Types Definitions **/ + + +/* DCH registers offsets */ +#define DR8DACx_OFFSET ((uint32_t)0x00000010U) +#define DR8DACy_OFFSET ((uint32_t)0x0000001CU) +#define DR8D_OFFSET ((uint32_t)0x00000028U) + +/* DATO register offset */ +#define DATOx_OFFSET ((uint32_t)0x00000008U) +#define DATOy_OFFSET ((uint32_t)0x0000000CU) + + +/* bit data handler */ +#define BIT_JUDGE_AND_HANDLER(IS_ENABLE, BIT_MASK) (((IS_ENABLE) != DISABLE ) ? (BIT_MASK) : (0x00000000U)) + + +/** DAC Driving Functions Declaration **/ + +/** +*\*\name DAC_DeInit. +*\*\fun Reset the DAC registers. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\return none +**/ +void DAC_DeInit(DACX DACx) +{ + if(IS_DAC12(DACx)) + { + RCC_EnableAPB1PeriphReset2(RCC_APB1_PERIPHRST_DAC12); + } + else if(IS_DAC34(DACx)) + { + RCC_EnableAHB2PeriphReset1(RCC_AHB2_PERIPHRST_DAC34); + } + else if(IS_DAC56(DACx)) + { + RCC_EnableAHB2PeriphReset1(RCC_AHB2_PERIPHRST_DAC56); + } + else + { + /*no process */ + } +} + +/** +*\*\name DAC_StructInit. +*\*\fun Fills all DAC_StructInit member with default value. +*\*\param DAC_StructInit : +*\*\ - DAC_Trigger +*\*\ - DAC_Trigger2 +*\*\ - DAC_WaveGeneration +*\*\ - DAC_LFSRUnmask_TriangleAmplitude +*\*\ - DAC_OutputBuffer +*\*\ - DAC_TriggerEnable +*\*\ - DAC_DMADoubleDataMode +*\*\ - DAC_SignedFormat +*\*\ - DAC_ConnectOnChipPeripheral +*\*\ - DAC_ConnectExternalPin +*\*\return none +**/ +void DAC_StructInit(DAC_InitType* DAC_InitStruct) +{ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_Software; + /* Initialize the DAC_Trigger2 member */ + DAC_InitStruct->DAC_Trigger2 = DAC_Trigger2_Software; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DISABLE; + /* Initialize the DAC_TriggerEnable member */ + DAC_InitStruct->DAC_TriggerEnable = DISABLE; + /* Initialize the DAC_DMADoubleDataMode member */ + DAC_InitStruct->DAC_DMADoubleDataMode = DISABLE; + /* Initialize the DAC_SignedFormat member */ + DAC_InitStruct->DAC_SignedFormat = DISABLE; + /* Initialize the DAC_ConnectOnChipPeripheral member */ + DAC_InitStruct->DAC_ConnectOnChipPeripheral = DISABLE; + /* Initialize the DAC_ConnectExternalPin member */ + DAC_InitStruct->DAC_ConnectExternalPin = DISABLE; +} + +/** +*\*\name DAC_BaseAddrGet. +*\*\fun Get the specified DAC base address. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\return DAC_Module* : +*\*\ - DAC12 +*\*\ - DAC34 +*\*\ - DAC56 +**/ +static DAC_Module* DAC_BaseAddrGet(DACX DACx) +{ + DAC_Module* DAC_TEMP = NULL; + + if(IS_DAC12(DACx)) + { + DAC_TEMP = (DAC_Module*)DAC12; + } + else if(IS_DAC34(DACx)) + { + DAC_TEMP = (DAC_Module*)DAC34; + } + else if(IS_DAC56(DACx)) + { + DAC_TEMP = (DAC_Module*)DAC56; + } + else + { + /* no process */ + } + + return DAC_TEMP; +} +/** +*\*\name DAC_Init. +*\*\fun Enables or disables the specified DAC. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_InitStruct : +*\*\ - DAC_Trigger +*\*\ - DAC_Trigger_Software +*\*\ - DAC_Trigger_ATIM1_TRGO +*\*\ - DAC_Trigger_ATIM2_TRGO +*\*\ - DAC_Trigger_ATIM3_TRGO +*\*\ - DAC_Trigger_ATIM4_TRGO +*\*\ - DAC_Trigger_GTIMA1_TRGO +*\*\ - DAC_Trigger_GTIMA2_TRGO +*\*\ - DAC_Trigger_GTIMA3_TRGO +*\*\ - DAC_Trigger_GTIMA4_TRGO +*\*\ - DAC_Trigger_GTIMA5_TRGO +*\*\ - DAC_Trigger_GTIMA6_TRGO +*\*\ - DAC_Trigger_GTIMA7_TRGO +*\*\ - DAC_Trigger_GTIMB1_TRGO +*\*\ - DAC_Trigger_GTIMB2_TRGO +*\*\ - DAC_Trigger_GTIMB3_TRGO +*\*\ - DAC_Trigger_EXTI5 +*\*\ - DAC_Trigger_EXTI7 +*\*\ - DAC_Trigger_EXTI9 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRG1 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRG2 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRG3 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRG4 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRG5 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRG6 +*\*\ - DAC_Trigger_SHRTIM1_RST_TRGO123 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRG1 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRG2 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRG3 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRG4 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRG5 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRG6 +*\*\ - DAC_Trigger_SHRTIM2_RST_TRGO123 +*\*\ - DAC_Trigger2 +*\*\ - DAC_Trigger2_Software +*\*\ - DAC_Trigger2_ATIM1_TRGO +*\*\ - DAC_Trigger2_ATIM2_TRGO +*\*\ - DAC_Trigger2_ATIM3_TRGO +*\*\ - DAC_Trigger2_ATIM4_TRGO +*\*\ - DAC_Trigger2_GTIMA1_TRGO +*\*\ - DAC_Trigger2_GTIMA2_TRGO +*\*\ - DAC_Trigger2_GTIMA3_TRGO +*\*\ - DAC_Trigger2_GTIMA4_TRGO +*\*\ - DAC_Trigger2_GTIMA5_TRGO +*\*\ - DAC_Trigger2_GTIMA6_TRGO +*\*\ - DAC_Trigger2_GTIMA7_TRGO +*\*\ - DAC_Trigger2_GTIMB1_TRGO +*\*\ - DAC_Trigger2_GTIMB2_TRGO +*\*\ - DAC_Trigger2_GTIMB3_TRGO +*\*\ - DAC_Trigger2_EXTI6 +*\*\ - DAC_Trigger2_EXTI8 +*\*\ - DAC_Trigger2_EXTI10 +*\*\ - DAC_Trigger2_SHRTIM1_STEP_TRG1 +*\*\ - DAC_Trigger2_SHRTIM1_STEP_TRG2 +*\*\ - DAC_Trigger2_SHRTIM1_STEP_TRG3 +*\*\ - DAC_Trigger2_SHRTIM1_STEP_TRG4 +*\*\ - DAC_Trigger2_SHRTIM1_STEP_TRG5 +*\*\ - DAC_Trigger2_SHRTIM1_STEP_TRG6 +*\*\ - DAC_Trigger2_SHRTIM2_STEP_TRG1 +*\*\ - DAC_Trigger2_SHRTIM2_STEP_TRG2 +*\*\ - DAC_Trigger2_SHRTIM2_STEP_TRG3 +*\*\ - DAC_Trigger2_SHRTIM2_STEP_TRG4 +*\*\ - DAC_Trigger2_SHRTIM2_STEP_TRG5 +*\*\ - DAC_Trigger2_SHRTIM2_STEP_TRG6 +*\*\ - DAC_LFSRUnmask_TriangleAmplitude +*\*\ - DAC_LFSRUnmask_Bit0 +*\*\ - DAC_LFSRUnmask_Bits1_0 +*\*\ - DAC_LFSRUnmask_Bits2_0 +*\*\ - DAC_LFSRUnmask_Bits3_0 +*\*\ - DAC_LFSRUnmask_Bits4_0 +*\*\ - DAC_LFSRUnmask_Bits5_0 +*\*\ - DAC_LFSRUnmask_Bits6_0 +*\*\ - DAC_LFSRUnmask_Bits7_0 +*\*\ - DAC_LFSRUnmask_Bits8_0 +*\*\ - DAC_LFSRUnmask_Bits9_0 +*\*\ - DAC_LFSRUnmask_Bits10_0 +*\*\ - DAC_LFSRUnmask_Bits11_0 +*\*\ - DAC_TriangleAmplitude_1 +*\*\ - DAC_TriangleAmplitude_3 +*\*\ - DAC_TriangleAmplitude_7 +*\*\ - DAC_TriangleAmplitude_15 +*\*\ - DAC_TriangleAmplitude_31 +*\*\ - DAC_TriangleAmplitude_63 +*\*\ - DAC_TriangleAmplitude_127 +*\*\ - DAC_TriangleAmplitude_255 +*\*\ - DAC_TriangleAmplitude_511 +*\*\ - DAC_TriangleAmplitude_1023 +*\*\ - DAC_TriangleAmplitude_2047 +*\*\ - DAC_TriangleAmplitude_4095 +*\*\ - DAC_WaveGeneration +*\*\ - DAC_WaveGeneration_None +*\*\ - DAC_WaveGeneration_Noise +*\*\ - DAC_WaveGeneration_Triangle +*\*\ - DAC_WaveGeneration_SAWTOOTH_INC +*\*\ - DAC_WaveGeneration_SAWTOOTH_DEC +*\*\ - DAC_OutputBuffer +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - DAC_TriggerEnable +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - DAC_DMADoubleDataMode +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - DAC_SignedFormat +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - DAC_ConnectOnChipPeripheral +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - DAC_ConnectExternalPin +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note when DACx is DAC3/DAC4/DAC5/DAC6, DAC_OutputBuffer,the params of DAC_ConnectOnChipPeripheral,DAC_ConnectExternalPin will be ignored. +**/ +void DAC_Init(DACX DACx, DAC_InitType* DAC_InitStruct) +{ + __IO uint32_t tmpreg1; + uint8_t shift_bit; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + /* Operate DAC_SELCTRL Regersiter */ + tmpreg1 = DAC_Base->SELCTRL; + + if(IS_DAC135(DACx)) + { + shift_bit = 0U; + tmpreg1 &= ~(DACx_SELCTRL_SINCSEL_MASK | DACx_SELCTRL_MAxSEL_MASK | DACx_SELCTRL_TxSEL_MASK); + } + else + { + shift_bit = 16U; + tmpreg1 &= ~(DACy_SELCTRL_SINCSEL_MASK | DACy_SELCTRL_MAySEL_MASK | DACy_SELCTRL_TySEL_MASK); + } + + /*mask/amplitude,DAC_Trigger,DAC_Trigger2 */ + tmpreg1 |= ((DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude << shift_bit) | (DAC_InitStruct->DAC_Trigger << shift_bit) | (DAC_InitStruct->DAC_Trigger2 << shift_bit) ); + DAC_Base->SELCTRL = tmpreg1; + + /* Operate DAC_GCTRL Regersiter */ + tmpreg1 = DAC_Base->GCTRL; + tmpreg1 &= (~DAC_GCTRL_FREQ_MODE_MASK); + tmpreg1 |= DAC_HIGH_FREQ_MODE_BELOW_80M; + DAC_Base->GCTRL = tmpreg1; + + /* Operate DAC_CTRL Regersiter */ + tmpreg1 = DAC_Base->CTRL; + + if(IS_DAC12(DACx)) + { + if(IS_DAC13(DACx)) + { + shift_bit = 0; + tmpreg1 &= ~(DACx_CTRL_BUFF_EN_MASK | DACx_CTRL_TRIGGER_EN_MASK | DACx_CTRL_DMADOUBLEMODE_EN_MASK | DACx_CTRL_SINGFORMAT_EN_MASK | \ + DACx_CTRL_WAVE_TYPE_MASK | DACx_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK | DACx_CTRL_OUTPUT_TO_EXTPIN_EN_MASK ); + } + else + { + shift_bit = 16; + tmpreg1 &= ~(DACy_CTRL_BUFF_EN_MASK | DACy_CTRL_TRIGGER_EN_MASK | DACy_CTRL_DMADOUBLEMODE_EN_MASK | DACy_CTRL_SINGFORMAT_EN_MASK | \ + DACy_CTRL_WAVE_TYPE_MASK | DACy_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK | DACy_CTRL_OUTPUT_TO_EXTPIN_EN_MASK ); + } + + tmpreg1 |= ((BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_OutputBuffer, DACx_CTRL_BUFF_EN_MASK) << shift_bit) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_TriggerEnable, DACx_CTRL_TRIGGER_EN_MASK) << shift_bit) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_DMADoubleDataMode, DACx_CTRL_DMADOUBLEMODE_EN_MASK) << shift_bit) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_SignedFormat, DACx_CTRL_SINGFORMAT_EN_MASK) << shift_bit) | \ + (DAC_InitStruct->DAC_WaveGeneration << (shift_bit)) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_ConnectOnChipPeripheral, DACx_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK) << shift_bit) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_ConnectExternalPin, DACx_CTRL_OUTPUT_TO_EXTPIN_EN_MASK) << shift_bit) ); + } + else + { + if(IS_DAC135(DACx)) + { + shift_bit = 0; + tmpreg1 &= ~(DACx_CTRL_TRIGGER_EN_MASK | DACx_CTRL_DMADOUBLEMODE_EN_MASK | DACx_CTRL_SINGFORMAT_EN_MASK | \ + DACx_CTRL_WAVE_TYPE_MASK ); + } + else + { + shift_bit = 16; + tmpreg1 &= ~( DACy_CTRL_TRIGGER_EN_MASK | DACy_CTRL_DMADOUBLEMODE_EN_MASK | DACy_CTRL_SINGFORMAT_EN_MASK | DACy_CTRL_WAVE_TYPE_MASK ); + } + + tmpreg1 |= ((BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_TriggerEnable, DACx_CTRL_TRIGGER_EN_MASK) << shift_bit) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_DMADoubleDataMode, DACx_CTRL_DMADOUBLEMODE_EN_MASK) << shift_bit) | \ + (BIT_JUDGE_AND_HANDLER(DAC_InitStruct->DAC_SignedFormat, DACx_CTRL_SINGFORMAT_EN_MASK) << shift_bit) | \ + (DAC_InitStruct->DAC_WaveGeneration << (shift_bit)) ); + } + + DAC_Base->CTRL = tmpreg1; +} + + +/** +*\*\name DAC_Enable. +*\*\fun Enables or disables the specified DAC. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_Enable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_EN_MASK); + } + } +} + +/** +*\*\name DAC_DmaEnable. +*\*\fun Enables or disables the specified DAC DMA request. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_DmaEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_DMA_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_DMA_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_DMA_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_DMA_EN_MASK); + } + } +} + +/** +*\*\name DAC_SoftTrgEnable. +*\*\fun Enables or disables software trigger of the selected DAC. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_SoftTrgEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if (Cmd != DISABLE) + { + DAC_Base->SOTTR |= (DACx_CTRL_TRIGxEN_MASK); + } + else + { + DAC_Base->SOTTR &= ~(DACx_CTRL_TRIGxEN_MASK); + } + } + else + { + if (Cmd != DISABLE) + { + DAC_Base->SOTTR |= (DACy_CTRL_TRIGyEN_MASK); + } + else + { + DAC_Base->SOTTR &= ~(DACy_CTRL_TRIGyEN_MASK); + } + } +} +/** +*\*\name DAC_SoftTrgSawStepEnable. +*\*\fun Enables or disables software trigger step signal of the selected DAC sawtooth wave . +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_SoftTrgSawStepEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if (Cmd != DISABLE) + { + DAC_Base->SOTTR |= (DACx_CTRL_TRIGxSTEPEN_MASK); + } + else + { + DAC_Base->SOTTR &= ~(DACx_CTRL_TRIGxSTEPEN_MASK); + } + } + else + { + if (Cmd != DISABLE) + { + DAC_Base->SOTTR |= (DACy_CTRL_TRIGySTEPEN_MASK); + } + else + { + DAC_Base->SOTTR &= ~(DACy_CTRL_TRIGySTEPEN_MASK); + } + } +} + +/** +*\*\name DAC_DualSoftwareTrgEnable. +*\*\fun Enables or disables simultaneously the two DAC software triggers. +*\*\param DACx : +*\*\ - DAC12 +*\*\ - DAC34 +*\*\ - DAC56 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_DualSoftwareTrgEnable(DAC_Module *Dual_DACx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable software trigger for both DAC channels */ + Dual_DACx->SOTTR |= DACx_CTRL_TRIGALLEN_MASK; + } + else + { + /* Disable software trigger for both DAC channels */ + Dual_DACx->SOTTR &= (~DACx_CTRL_TRIGALLEN_MASK); + } +} +/** +*\*\name DAC_DualSoftwareTrgEnable. +*\*\fun Enables or disables software trigger step signal of simultaneously two DACs sawtooth wave . +*\*\param DACx : +*\*\ - DAC12 +*\*\ - DAC34 +*\*\ - DAC56 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_DualSoftwareTrgSawStepEnable(DAC_Module *Dual_DACx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable software trigger sawtooth step sign for both DAC channels */ + Dual_DACx->SOTTR |= DACy_CTRL_TRIGALLSTEPEN_MASK; + } + else + { + /* Disable software trigger sawtooth step sign for both DAC channels */ + Dual_DACx->SOTTR &= (~DACy_CTRL_TRIGALLSTEPEN_MASK); + } +} + +/** +*\*\name DAC_WaveGenerationConfig. +*\*\fun Configure the selected DAC wave generation. . +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_Wave : +*\*\ - DAC_WaveGeneration_None +*\*\ - DAC_WaveGeneration_Noise +*\*\ - DAC_WaveGeneration_Triangle +*\*\ - DAC_WaveGeneration_SAWTOOTH_INC +*\*\ - DAC_WaveGeneration_SAWTOOTH_DEC +*\*\return none +**/ +void DAC_WaveGenerationConfig(DACX DACx, uint32_t DAC_Wave) +{ + __IO uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = DAC_Base->CTRL; + + if(IS_DAC135(DACx)) + { + tempreg &= ~(DACx_CTRL_WAVE_TYPE_MASK); + tempreg |= (DAC_Wave); + } + else + { + tempreg &= ~(DACy_CTRL_WAVE_TYPE_MASK); + tempreg |= (DAC_Wave << 16); + } + + DAC_Base->CTRL = tempreg; +} + +/** +*\*\name DAC_SetData. +*\*\fun Set the data holding register value for the specified DAC. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_Align : +*\*\ - DAC_ALIGN_R_8BIT +*\*\ - DAC_ALIGN_L_12BIT +*\*\ - DAC_ALIGN_R_12BIT +*\*\param Data : Data to be loaded in the selected data holding register. +*\*\return none +**/ +void DAC_SetData(DACX DACx, uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = (uint32_t)DAC_Base; + + if(IS_DAC135(DACx)) + { + tempreg += DR8DACx_OFFSET; + } + else + { + tempreg += DR8DACy_OFFSET; + } + + tempreg += DAC_Align; + + /* Set the DACx selected data holding register */ + *(__IO uint32_t*)tempreg = Data; +} + +/** +*\*\name DAC_SetDualChData. +*\*\fun Set the data holding register value for the specified dual-DAC. +*\*\param DACx : +*\*\ - DAC12 +*\*\ - DAC34 +*\*\ - DAC56 +*\*\param DAC_Align : +*\*\ - DAC_ALIGN_R_8BIT +*\*\ - DAC_ALIGN_L_12BIT +*\*\ - DAC_ALIGN_R_12BIT +*\*\param Data2 : Data to be loaded in the selected DACy data holding register. +*\*\param Data1 : Data to be loaded in the selected DACx data holding register. +*\*\return none +**/ +void DAC_SetDualChData(DAC_Module *Dual_DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + __IO uint32_t tempreg; + uint32_t data; + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_ALIGN_R_8BIT) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tempreg = (uint32_t)Dual_DACx; + tempreg += DR8D_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t*)tempreg = data; +} + +/** +*\*\name DAC_GetOutputDataVal. +*\*\fun Get the last data output value of the selected DAC . +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\return The selected DAC data output value. +**/ +uint16_t DAC_GetOutputDataVal(DACX DACx) +{ + uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = (uint32_t)DAC_Base; + + if(IS_DAC135(DACx)) + { + tempreg += DATOx_OFFSET; + } + else + { + tempreg += DATOy_OFFSET; + } + + /* Returns the DACx data output register value */ + return (uint16_t)(*(__IO uint32_t*)tempreg); +} +/** +*\*\name DAC_SetSawtoothResetValue. +*\*\fun Set the swatooth waveform generation reset data. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param ResetValue: +*\*\ - the value is range from 0- 0xfff; +*\*\return none +**/ +void DAC_SetSawtoothResetValue(DACX DACx, uint16_t ResetValue) +{ + __IO uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + tempreg = DAC_Base->STRST; + + if(IS_DAC135(DACx)) + { + tempreg &= (~DAC_STRST_STRSTDATAx_MASK); + tempreg |= (uint32_t)ResetValue; + } + else + { + tempreg &= (~DAC_STRST_STRSTDATAy_MASK); + tempreg |= ((uint32_t)ResetValue << 16); + } + + DAC_Base->STRST = tempreg; +} +/** +*\*\name DAC_SetSawtoothStepValue. +*\*\fun Set the swatooth waveform generation step data. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param StepData: +*\*\ - the value is range from 0- 0xfff; +*\*\return none +**/ +void DAC_SetSawtoothStepValue(DACX DACx, uint16_t StepData) +{ + __IO uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + tempreg = DAC_Base->STINC; + + if(IS_DAC135(DACx)) + { + tempreg &= (~DAC_STINC_STINCDATAx_MASK); + tempreg |= (uint32_t)StepData; + } + else + { + tempreg &= (~DAC_STINC_STINCDATAy_MASK); + tempreg |= ((uint32_t)StepData << 16); + } + + DAC_Base->STINC = tempreg; +} + +/** +*\*\name DAC_CaliEnable. +*\*\fun Enables or disables the specified DACx calibration function. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\note only DACx enable buffer function and the function couldn't be used in DAC3/4/5/6. +*\*\return none +**/ +void DAC_CaliEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_CALIBATE_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_CALIBATE_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_CALIBATE_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_CALIBATE_EN_MASK); + } + } +} +/** +*\*\name DAC_ConnetToOnChipEnable. +*\*\fun Enables or disables the DACx output connected to on the chip. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\note The function couldn't be used in DAC3/4/5/6. +*\*\return none +**/ +void DAC_ConnetToOnChipEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_OUTPUT_TO_ONCHAIP_EN_MASK); + } + } +} +/** +*\*\name DAC_ConnetToExternalPinEnable. +*\*\fun Enables or disables the DACx output connected to external pin. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\note The function couldn't be used in DAC3/4/5/6. +*\*\return none +**/ +void DAC_ConnetToExternalPinEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_OUTPUT_TO_EXTPIN_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_OUTPUT_TO_EXTPIN_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_OUTPUT_TO_EXTPIN_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_OUTPUT_TO_EXTPIN_EN_MASK); + } + } +} +/** +*\*\name DAC_DMADoubleDataModeEnable. +*\*\fun Enables or disables the DACx DMA double data mode. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_DMADoubleDataModeEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_DMADOUBLEMODE_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_DMADOUBLEMODE_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_DMADOUBLEMODE_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_DMADOUBLEMODE_EN_MASK); + } + } +} +/** +*\*\name DAC_SignFormatModeEnable. +*\*\fun Enables or disables the DACx signed format mode. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_SignFormatModeEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_SINGFORMAT_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_SINGFORMAT_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_SINGFORMAT_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_SINGFORMAT_EN_MASK); + } + } +} +/** +*\*\name DAC_HighDriveAbilityEnable. +*\*\fun Enables or disables the DACx high driver ability output. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note The function couldn't be used in DAC3/4/5/6. +**/ +void DAC_HighDriveAbilityEnable(DACX DACx, FunctionalState Cmd) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACx_CTRL_HIGH_DRIVER_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACx_CTRL_HIGH_DRIVER_EN_MASK); + } + } + else + { + if(Cmd != DISABLE) + { + DAC_Base->CTRL |= DACy_CTRL_HIGH_DRIVER_EN_MASK; + } + else + { + DAC_Base->CTRL &= ~(DACy_CTRL_HIGH_DRIVER_EN_MASK); + } + } +} + +/** +*\*\name DAC_GetFlagSts. +*\*\fun Get the specified DAC status flag. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_FLAG: +*\*\ When DACx == DAC1/2, DAC_FLAG can be as follow: +*\*\ - DAC_FLAG_DMAUDR +*\*\ - DAC_FLAG_CALCOMPLETE +*\*\ - DAC_FLAG_DORSTAT +*\*\ - DAC_FLAG_TROVC +*\*\ When DACx == DAC3/4/5/6, DAC_FLAG can be as follow: +*\*\ - DAC_FLAG_DMAUDR +*\*\ - DAC_FLAG_DORSTAT +*\*\ - DAC_FLAG_TROVC +*\*\ - DAC_FLAG_VFLAGCOMP +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus DAC_GetFlagSts(DACX DACx, uint32_t DAC_FLAG) +{ + __IO uint32_t tempreg; + FlagStatus status ; + + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = DAC_Base->STS; + + if(IS_DAC135(DACx)) + { + status = ((tempreg & DAC_FLAG) != 0) ? SET : RESET; + } + else + { + status = ((tempreg & (DAC_FLAG << 16)) != 0) ? SET : RESET; + } + + return status; +} +/** +*\*\name DAC_ClearFlag. +*\*\fun Clear the specified DAC status flag. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_FLAG: +*\*\ - DAC_FLAG_DMAUDR +*\*\ - DAC_FLAG_TROVC +*\*\return none +**/ +void DAC_ClearFlag(DACX DACx, uint32_t DAC_FLAG) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + DAC_Base->STS = DAC_FLAG; + } + else + { + DAC_Base->STS = (DAC_FLAG << 16u); + } +} +/** +*\*\name DAC_ConfigInt. +*\*\fun Enables or disables the specified DAC interrupts. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_IT: +*\*\ - DAC_INT_DMAUDRIEN +*\*\ - DAC_INT_TROVIEN +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DAC_ConfigInt(DACX DACx, uint32_t DAC_IT, FunctionalState Cmd) +{ + __IO uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = DAC_Base->CTRL; + + if(IS_DAC135(DACx)) + { + if(Cmd != DISABLE) + { + tempreg |= DAC_IT; + } + else + { + tempreg &= (~DAC_IT); + } + } + else + { + if(Cmd != DISABLE) + { + tempreg |= (DAC_IT << 16u); + } + else + { + tempreg &= (~(DAC_IT << 16u) ); + } + } + + DAC_Base->CTRL = tempreg; +} +/** +*\*\name DAC_GetIntSts. +*\*\fun Get the specified DAC interrupts flag. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_IT: +*\*\ - DAC_INTFLAG_DMAUDR +*\*\ - DAC_INTFLAG_TROVC +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus DAC_GetIntSts(DACX DACx, uint32_t DAC_IT) +{ + __IO uint32_t tempreg; + FlagStatus status ; + + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = DAC_Base->STS; + + if(IS_DAC135(DACx)) + { + status = ((tempreg & DAC_IT) != 0u) ? SET : RESET; + } + else + { + status = ((tempreg & (DAC_IT << 16u) ) != 0u) ? SET : RESET; + } + + return status; +} +/** +*\*\name DAC_ClearITPendingBit. +*\*\fun Clears the DACx interrupt pending bit. +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\ - DAC3 +*\*\ - DAC4 +*\*\ - DAC5 +*\*\ - DAC6 +*\*\param DAC_IT: +*\*\ - DAC_INTFLAG_DMAUDR +*\*\ - DAC_INTFLAG_TROVC +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +void DAC_ClearITPendingBit(DACX DACx, uint32_t DAC_IT) +{ + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + + if(IS_DAC135(DACx)) + { + DAC_Base->STS = DAC_IT; + } + else + { + DAC_Base->STS = (DAC_IT << 16u); + } +} + + +/** +*\*\name DAC_ConfigClkPrescaler. +*\*\fun Configures the DAC_CLK prescaler. +*\*\param DACx : +*\*\ - DAC12 +*\*\ - DAC34 +*\*\ - DAC56 +*\*\param Prescaler: +*\*\ - when DACx is DAC12 , the value range from 1 - 0xff +*\*\ - when DACx is DAC34 or DAC56 ,the value range from 1 - 0x1f +*\*\return none +**/ +void DAC_ConfigClkPrescaler(DAC_Module* DACx, uint8_t Prescaler) +{ + if(DACx == DAC12) + { + DACx->GCTRL &= (~DAC12_GCTRL_PCS_MASK); + } + else + { + DACx->GCTRL &= (~DAC3456_GCTRL_PCS_MASK); + } + + DACx->GCTRL |= (((uint32_t)Prescaler - 1u) << 16u); +} + + +/** +*\*\name DAC_SetHighFrequencyMode. +*\*\fun Configures the high frequency interface mode for the selected DAC. +*\*\param DACx : +*\*\ - DAC12 +*\*\param mode: +*\*\ - DAC_HIGH_FREQ_MODE_DISABLE +*\*\ - DAC_HIGH_FREQ_MODE_BELOW_80M +*\*\ - DAC_HIGH_FREQ_MODE_BELOW_160M +*\*\ - DAC_HIGH_FREQ_MODE_ABOVE_160M +*\*\return none +**/ +void DAC_SetHighFrequencyMode(DAC_Module* DACx, uint32_t mode) +{ + uint32_t tempreg; + tempreg = DACx->GCTRL; + + tempreg &= (~DAC_GCTRL_FREQ_MODE_MASK); + tempreg |= mode; + + DACx->GCTRL = tempreg; +} + +/** +*\*\name DAC_SetUserTrimming. +*\*\fun Config the offset trimming value for the selected DAC . +*\*\param DACx : +*\*\ - DAC1 +*\*\ - DAC2 +*\*\param TrimmingValue: DAC new trimming value +*\*\ - the data is range from 0 - 31 +*\*\return none +*\*\note The function couldn't be used in DAC3/4/5/6. +**/ +void DAC_SetUserTrimming(DACX DACx, uint8_t TrimmingValue) +{ + __IO uint32_t tempreg; + DAC_Module* DAC_Base = DAC_BaseAddrGet(DACx); + tempreg = DAC_Base->CALC; + + if(IS_DAC135(DACx)) + { + tempreg &= (~DAC_CALC_OTRIMxVALUE_MASK); + tempreg |= (uint32_t)TrimmingValue; + } + else + { + tempreg &= (~DAC_CALC_OTRIMyVALUE_MASK); + tempreg |= (((uint32_t)TrimmingValue) << 16u); + } + + DAC_Base->CALC = tempreg ; +} + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dbg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dbg.c new file mode 100644 index 0000000000..bacd674966 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dbg.c @@ -0,0 +1,276 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dbg.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ + +#include "n32h76x_78x_dbg.h" + + +/** +*\*\name DBG_GetRevNum. +*\*\fun get the revision number. +*\*\param none +*\*\return revision number +**/ +uint32_t DBG_GetRevNum(void) +{ + return (uint32_t)((DBG->ID & DBG_REV_NUM_MASK) >> 24); +} + +/** +*\*\name DBG_GetDevNum. +*\*\fun get the device identifer. +*\*\param none +*\*\return Device identifier +*\*\ - 0x760 : N32H760 Series +*\*\ - 0x762 : N32H762 Series +*\*\ - 0x765 : N32H765 Series +*\*\ - 0x785 : N32H785 Series +*\*\ - 0x787 : N32H787 Series +*\*\ - 0x788 : N32H788 Series +**/ +uint32_t DBG_GetDevNum(void) +{ + return (uint32_t)((DBG->ID & DBG_DEV_NUM_MASK) >> 12); +} + + +/** +*\*\name DBG_SetExternalTriggerPinDirection. +*\*\fun Set the direction of the bi-directional trigger pin TRGIO. +*\*\param PinDirection : + - DBG_TRGIO_INPUT_DIRECTION + - DBG_TRGIO_OUTPUT_DIRECTION +*\*\return none +**/ +void DBG_SetExternalTriggerPinDirection(uint32_t PinDirection) +{ + if(PinDirection == DBG_TRGIO_OUTPUT_DIRECTION) + { + DBG->CTRL |= DBG_TRGIO_OUTPUT_DIRECTION; + } + else + { + DBG->CTRL &= (~DBG_TRGIO_OUTPUT_DIRECTION) ; + } +} + +/** +*\*\name DBG_M7ConfigPeriph. +*\*\fun Configures the specified peripheral run or stop when the M7 MCU under Debug mode. +*\*\param DBG_Periph : + - DBG_M7SLEEP * Keep debugger connection during M7 SLEEP mode * + - DBG_M7STOP * Keep debugger connection during M7 STOP mode * + - DBG_M7STANDBY * Keep debugger connection during M7 STANDBY mode * + - DBG_WWDG1_STOP * WWDG1 stopped when Core is halted. * + - DBG_WWDG2_STOP * WWDG2 stopped when Core is halted. * + - DBG_ATIM3_STOP * ATIM3 counter stopped when core is halted * + - DBG_ATIM4_STOP * ATIM4 counter stopped when core is halted * + - DBG_I2C7SMBUS_TIMEOUT * I2C7 counter stopped when core is halted * + - DBG_I2C8SMBUS_TIMEOUT * I2C8 counter stopped when core is halted * + - DBG_I2C9SMBUS_TIMEOUT * I2C9 counter stopped when core is halted * + - DBG_I2C10SMBUS_TIMEOUT * I2C10 counter stopped when core is halted * + - DBG_IWDG1_STOP * IWDG1 counter stopped when core is halted * + - DBG_IWDG2_STOP * IWDG2 counter stopped when core is halted * + - DBG_LPTIM1_STOP * LPTIM1 counter stopped when core is halted * + - DBG_LPTIM2_STOP * LPTIM2 counter stopped when core is halted * + - DBG_LPTIM3_STOP * LPTIM3 counter stopped when core is halted * + - DBG_LPTIM4_STOP * LPTIM4 counter stopped when core is halted * + - DBG_LPTIM5_STOP * LPTIM5 counter stopped when core is halted * + - DBG_RTC_STOP * RTC counter stopped when core is halted * + - DBG_CANFD3_STOP * CANFD3 counter stopped when core is halted * + - DBG_CANFD4_STOP * CANFD4 counter stopped when core is halted * + - DBG_CANFD7_STOP * CANFD7 counter stopped when core is halted * + - DBG_CANFD8_STOP * CANFD8 counter stopped when core is halted * + - DBG_I2C4SMBUS_TIMEOUT * I2C4 counter stopped when core is halted * + - DBG_I2C5SMBUS_TIMEOUT * I2C5 counter stopped when core is halted * + - DBG_I2C6SMBUS_TIMEOUT * I2C6 counter stopped when core is halted * + - DBG_ATIM1_STOP * ATIM1 counter stopped when core is halted * + - DBG_ATIM2_STOP * ATIM2 counter stopped when core is halted * + - DBG_GTIMA1_STOP * GTIMA1 counter stopped when core is halted * + - DBG_GTIMA2_STOP * GTIMA2 counter stopped when core is halted * + - DBG_GTIMA3_STOP * GTIMA3 counter stopped when core is halted * + - DBG_SHRTIM1_STOP * SHRTIM1 counter stopped when core is halted * + - DBG_SHRTIM2_STOP * SHRTIM2 counter stopped when core is halted * + - DBG_BTIM1_STOP * BTIM1 counter stopped when core is halted * + - DBG_BTIM2_STOP * BTIM2 counter stopped when core is halted * + - DBG_BTIM3_STOP * BTIM3 counter stopped when core is halted * + - DBG_BTIM4_STOP * BTIM4 counter stopped when core is halted * + - DBG_GTIMA4_STOP * GTIMA4 counter stopped when core is halted * + - DBG_GTIMA5_STOP * GTIMA5 counter stopped when core is halted * + - DBG_GTIMA6_STOP * GTIMA6 counter stopped when core is halted * + - DBG_GTIMA7_STOP * GTIMA7 counter stopped when core is halted * + - DBG_GTIMB1_STOP * GTIMB1 counter stopped when core is halted * + - DBG_GTIMB2_STOP * GTIMB2 counter stopped when core is halted * + - DBG_GTIMB3_STOP * GTIMB3 counter stopped when core is halted * + - DBG_I2C1SMBUS_TIMEOUT * I2C1 counter stopped when core is halted * + - DBG_I2C2SMBUS_TIMEOUT * I2C2 counter stopped when core is halted * + - DBG_I2C3SMBUS_TIMEOUT * I2C3 counter stopped when core is halted * + - DBG_CANFD1_STOP * CANFD1 counter stopped when core is halted * + - DBG_CANFD2_STOP * CANFD2 counter stopped when core is halted * + - DBG_CANFD5_STOP * CANFD5 counter stopped when core is halted * + - DBG_CANFD6_STOP * CANFD6 counter stopped when core is halted * +*\*\return none +**/ +void DBG_M7ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd) +{ + uint32_t Offset = ( (DBG_Periph & REGISTER_OFFSET_MASK) >> REGISTER_OFFSET_POS); + __IO uint32_t Register_Base = DBGMCU_BASE; + + Register_Base += Offset; + + if (Cmd != DISABLE) + { + *(uint32_t *)Register_Base |= DBG_Periph; + } + else + { + *(uint32_t *)Register_Base &= ~DBG_Periph; + } +} + +/** +*\*\name DBG_M4ConfigPeriph. +*\*\fun Configures the specified peripheral run or stop when the M4 MCU under Debug mode. +*\*\param DBG_Periph : + - DBG_M4SLEEP * Keep debugger connection during M4 SLEEP mode * + - DBG_M4STOP * Keep debugger connection during M4 STOP mode * + - DBG_M4STANDBY * Keep debugger connection during M4 STANDBY mode * + - DBG_WWDG1_STOP * WWDG1 stopped when Core is halted. * + - DBG_WWDG2_STOP * WWDG2 stopped when Core is halted. * + - DBG_ATIM3_STOP * ATIM3 counter stopped when core is halted * + - DBG_ATIM4_STOP * ATIM4 counter stopped when core is halted * + - DBG_I2C7SMBUS_TIMEOUT * I2C7 counter stopped when core is halted * + - DBG_I2C8SMBUS_TIMEOUT * I2C8 counter stopped when core is halted * + - DBG_I2C9SMBUS_TIMEOUT * I2C9 counter stopped when core is halted * + - DBG_I2C10SMBUS_TIMEOUT * I2C10 counter stopped when core is halted * + - DBG_IWDG1_STOP * IWDG1 counter stopped when core is halted * + - DBG_IWDG2_STOP * IWDG2 counter stopped when core is halted * + - DBG_LPTIM1_STOP * LPTIM1 counter stopped when core is halted * + - DBG_LPTIM2_STOP * LPTIM2 counter stopped when core is halted * + - DBG_LPTIM3_STOP * LPTIM3 counter stopped when core is halted * + - DBG_LPTIM4_STOP * LPTIM4 counter stopped when core is halted * + - DBG_LPTIM5_STOP * LPTIM5 counter stopped when core is halted * + - DBG_RTC_STOP * RTC counter stopped when core is halted * + - DBG_CANFD3_STOP * CANFD3 counter stopped when core is halted * + - DBG_CANFD4_STOP * CANFD4 counter stopped when core is halted * + - DBG_CANFD7_STOP * CANFD7 counter stopped when core is halted * + - DBG_CANFD8_STOP * CANFD8 counter stopped when core is halted * + - DBG_I2C4SMBUS_TIMEOUT * I2C4 counter stopped when core is halted * + - DBG_I2C5SMBUS_TIMEOUT * I2C5 counter stopped when core is halted * + - DBG_I2C6SMBUS_TIMEOUT * I2C6 counter stopped when core is halted * + - DBG_ATIM1_STOP * ATIM1 counter stopped when core is halted * + - DBG_ATIM2_STOP * ATIM2 counter stopped when core is halted * + - DBG_GTIMA1_STOP * GTIMA1 counter stopped when core is halted * + - DBG_GTIMA2_STOP * GTIMA2 counter stopped when core is halted * + - DBG_GTIMA3_STOP * GTIMA3 counter stopped when core is halted * + - DBG_SHRTIM1_STOP * SHRTIM1 counter stopped when core is halted * + - DBG_SHRTIM2_STOP * SHRTIM2 counter stopped when core is halted * + - DBG_BTIM1_STOP * BTIM1 counter stopped when core is halted * + - DBG_BTIM2_STOP * BTIM2 counter stopped when core is halted * + - DBG_BTIM3_STOP * BTIM3 counter stopped when core is halted * + - DBG_BTIM4_STOP * BTIM4 counter stopped when core is halted * + - DBG_GTIMA4_STOP * GTIMA4 counter stopped when core is halted * + - DBG_GTIMA5_STOP * GTIMA5 counter stopped when core is halted * + - DBG_GTIMA6_STOP * GTIMA6 counter stopped when core is halted * + - DBG_GTIMA7_STOP * GTIMA7 counter stopped when core is halted * + - DBG_GTIMB1_STOP * GTIMB1 counter stopped when core is halted * + - DBG_GTIMB2_STOP * GTIMB2 counter stopped when core is halted * + - DBG_GTIMB3_STOP * GTIMB3 counter stopped when core is halted * + - DBG_I2C1SMBUS_TIMEOUT * I2C1 counter stopped when core is halted * + - DBG_I2C2SMBUS_TIMEOUT * I2C2 counter stopped when core is halted * + - DBG_I2C3SMBUS_TIMEOUT * I2C3 counter stopped when core is halted * + - DBG_CANFD1_STOP * CANFD1 counter stopped when core is halted * + - DBG_CANFD2_STOP * CANFD2 counter stopped when core is halted * + - DBG_CANFD5_STOP * CANFD5 counter stopped when core is halted * + - DBG_CANFD6_STOP * CANFD6 counter stopped when core is halted * +*\*\return none +**/ +void DBG_M4ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd) +{ + uint32_t Offset = ( (DBG_Periph & REGISTER_OFFSET_MASK) >> REGISTER_OFFSET_POS); + __IO uint32_t Register_Base = DBGMCU_BASE; + + Register_Base += (Offset + 0x04u); + + if (Cmd != DISABLE) + { + *(uint32_t *)Register_Base |= DBG_Periph; + } + else + { + *(uint32_t *)Register_Base &= ~DBG_Periph; + } +} +/** +*\*\name DBG_GetFlashSize. +*\*\fun Get FLASH size of this chip. +*\*\param none +*\*\return FLASH size in bytes. +**/ +uint32_t DBG_GetFlashSize(void) +{ + uint32_t Flash_size = (DBG->ID & DBG_FLASH_SIZE_MASK); + + if(Flash_size != DBG_FLASH_SIZE_MASK) + { + Flash_size = (uint32_t)(Flash_size << 15); + } + else + { + Flash_size = 0; + } + + return Flash_size; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dcmu.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dcmu.c new file mode 100644 index 0000000000..1df55b4c97 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dcmu.c @@ -0,0 +1,314 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dcmu.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + *///mayan+ +#include "n32h76x_78x_dcmu.h" +#include "n32h76x_78x_rcc.h" + +/* DCMU Driving Functions Declaration */ + + +/* DCMU_Private_Defines */ +/** +*\*\name DCMU_Reset. +*\*\fun Resets the DCMUx peripheral +*\*\param none +*\*\return none +**/ +void DCMU_DeInit( void ) +{ + RCC_EnableDCMUReset(); +} + +#if defined(CORE_CM7) +/** +*\*\name DCMU_SelfReset. +*\*\fun Self-resets the DCMUx peripheral by CM7 or CM4 +*\*\param none +*\*\return none +**/ +void DCMU_SelfReset( void ) +{ + DCMU->CTRL |= DCMU_CTRL_RST_MASK; + __NOP(); + __NOP(); + + /* Wait for CPU reset bit in DCMU status register is completed */ + while( 0U != (DCMU->STS & DCMU_STS_RSTF_MASK) ) + { + __NOP(); + } +} +#endif + +/** +*\*\name DCMU_TransmitMsg. +*\*\fun Transmit Message through Blocking or NonBlocking Mode to counterpart MCU +*\*\param TxIdx : +*\*\ - TXMSG_IDX0 +*\*\ - TXMSG_IDX1 +*\*\ - TXMSG_IDX2 +*\*\ - TXMSG_IDX3 +*\*\param TxMsgData : +*\*\ - 32bit unsigned integer message data payload [0x00000000U--0xFFFFFFFFU] +*\*\param Mode : +*\*\ - NON_BLOCKING +*\*\ - BLOCKING +*\*\return none +**/ +void DCMU_TransmitMsg( uint8_t TxIdx, uint32_t TxMsgData, dcmu_wait_mode_t Mode) +{ + /* Wait until transmit message register is empty in blocking receive mode */ + if( BLOCKING == Mode) + { + while( 0u == (DCMU->STS & (1U << (DCMU_STS_TEF3_Pos + 3U - TxIdx)))) + { + __NOP(); + } + } + + /* NonBlocking and Blocking common code */ + DCMU->TXMSG[TxIdx] = TxMsgData; +} + +/** +*\*\name DCMU_ReceiveMsg. +*\*\fun Receive Message through Blocking or NonBlocking Mode from counterpart mcu +*\*\param RcvIdx : +*\*\ - RCVMSG_IDX0 +*\*\ - RCVMSG_IDX1 +*\*\ - RCVMSG_IDX2 +*\*\ - RCVMSG_IDX3 +*\*\param Mode : +*\*\ - NON_BLOCKING +*\*\ - BLOCKING +*\*\return uint32_t message data from counterpart mcu +**/ +uint32_t DCMU_ReceiveMsg( uint8_t RcvIdx, dcmu_wait_mode_t Mode) +{ + /* Wait until receive message register is full in blocking receive mode */ + if( BLOCKING == Mode) + { + while( 0u == (DCMU->STS & (1U << (DCMU_STS_RFF3_Pos + 3U - RcvIdx)))) + { + __NOP(); + } + } + + /* NonBlocking and Blocking mode common code */ + return DCMU->RCVMSG[RcvIdx]; +} + +/** +*\*\name DCMU_Set3BitFlagNumbers. +*\*\fun Set three bits flag number in order to transmit to counterpart +*\*\param FlagData : +*\*\ - 3 bits flag number data [0x0U - 0x7U] +*\*\param Mode : +*\*\ - NON_BLOCKING +*\*\ - BLOCKING +*\*\return none +**/ +void DCMU_Set3BitFlagNumbers( uint8_t FlagData, dcmu_wait_mode_t Mode) +{ + __IO uint32_t tempreg; + + /* Wait until receive flag is pending in case of blocking receive mode */ + if( BLOCKING == Mode) + { + while( 0u != (DCMU->STS & DCMU_STS_FUPF_MASK )) + { + __NOP(); + } + } + + /* NonBlocking and Blocking mode common code */ + tempreg = DCMU->CTRL; + tempreg &= ~(uint32_t)(DCMU_CTRL_TXFN_ALL_MASK); + tempreg |= (uint32_t)FlagData; + DCMU->CTRL = tempreg; + +} + +/** +*\*\name DCMU_Get3BitFlagNumbers. +*\*\fun Get three bits flag number received from counterpart +*\*\param none +*\*\return uint8_t received 3bits flag number data from counterpart mcu [0x00U-0x07U] +**/ +uint8_t DCMU_Get3BitFlagNumbers( void) +{ + return (uint8_t)(DCMU->STS & (uint32_t)( DCMU_STS_RCVFN_ALL_MASK)); +} + +/** +*\*\name DCMU_GetStatusFlags. +*\*\fun Get status flags from status register, only FUPF, EPF and RSTF flags are captured +*\*\param StatusMask : +*\*\ - DCMU_STS_EPF_MASK +*\*\ - DCMU_STS_FUPF_MASK +*\*\ - DCMU_STS_RSTF_MASK +*\*\return uint32_t the existing status flags +**/ +uint32_t DCMU_GetStatusFlags( uint32_t StatusMask) +{ + DCMU_Module *DCMUx = DCMU; + return DCMUx->STS & (uint32_t)(( DCMU_STS_EPF_MASK | DCMU_STS_RSTF_MASK | DCMU_STS_FUPF_MASK) & StatusMask); +} + +/** +*\*\name DCMU_GetIntPendingFlags. +*\*\fun Get interrupt pendding flags from status register and GPIF, TEIF and RFIF flags are captured +*\*\param IntPendingMask : +*\*\ - DCMU_STS_GPIF0_MASK +*\*\ - DCMU_STS_GPIF1_MASK +*\*\ - DCMU_STS_GPIF2_MASK +*\*\ - DCMU_STS_GPIF3_MASK +*\*\ - DCMU_STS_RFF0_MASK +*\*\ - DCMU_STS_RFF1_MASK +*\*\ - DCMU_STS_RFF2_MASK +*\*\ - DCMU_STS_RFF3_MASK +*\*\ - DCMU_STS_TEF0_MASK +*\*\ - DCMU_STS_TEF1_MASK +*\*\ - DCMU_STS_TEF2_MASK +*\*\ - DCMU_STS_TEF3_MASK +*\*\return uint32_t the existing interrupt pending flags which are in range of IntPendingMask +**/ +uint32_t DCMU_GetIntPendingFlags( uint32_t IntPendingMask) +{ + + return DCMU->STS & (uint32_t)( IntPendingMask & \ + ( DCMU_STS_GPIF_ALL_MASK | \ + DCMU_STS_TEF_ALL_MASK | \ + DCMU_STS_RFF_ALL_MASK ) ); +} + +/** +*\*\name GPIntPendingMask. +*\*\fun Clear general purpose interrupt pending as GPIF +*\*\param GPIntPendingMask : +*\*\ - DCMU_STS_GPIF0_MASK +*\*\ - DCMU_STS_GPIF1_MASK +*\*\ - DCMU_STS_GPIF2_MASK +*\*\ - DCMU_STS_GPIF3_MASK +*\*\return none +**/ +void DCMU_ClearIntPendingFlags( uint32_t GPIntPendingMask) +{ + __IO uint32_t tempreg; + + tempreg = DCMU->STS; + tempreg &= ~(uint32_t)(DCMU_STS_GPIF_ALL_MASK); + tempreg |= (uint32_t)(GPIntPendingMask & (uint32_t)(DCMU_STS_GPIF_ALL_MASK)); + DCMU->STS = tempreg; +} + +/** +*\*\name DCMU_ConfigInt. +*\*\fun Configure individual interrupts as enable or disabled +*\*\param IntMask : +*\*\ - DCMU_CTRL_GPIE0_MASK +*\*\ - DCMU_CTRL_GPIE1_MASK +*\*\ - DCMU_CTRL_GPIE2_MASK +*\*\ - DCMU_CTRL_GPIE3_MASK +*\*\ - DCMU_CTRL_RFIE0_MASK +*\*\ - DCMU_CTRL_RFIE1_MASK +*\*\ - DCMU_CTRL_RFIE2_MASK +*\*\ - DCMU_CTRL_RFIE3_MASK +*\*\ - DCMU_CTRL_TEIE0_MASK +*\*\ - DCMU_CTRL_TEIE1_MASK +*\*\ - DCMU_CTRL_TEIE2_MASK +*\*\ - DCMU_CTRL_TEIE3_MASK +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DCMU_ConfigInt( uint32_t IntMask, FunctionalState Cmd) +{ + __IO uint32_t tempreg; + + tempreg = DCMU->CTRL; + + if( ENABLE == Cmd) + { + tempreg |= (uint32_t)(IntMask & DCMU_CTRL_ALL_IE_MASK); + } + else + { + tempreg &= ~(uint32_t)IntMask; + } + + DCMU->CTRL = tempreg; +} + +/** +*\*\name DCMU_RequestGPInt. +*\*\fun Send request general purpose interrupt to counterpart mcu +*\*\param ReqGPIntMask : +*\*\ - DCMU_CTRL_GPIR0_MASK +*\*\ - DCMU_CTRL_GPIR1_MASK +*\*\ - DCMU_CTRL_GPIR2_MASK +*\*\ - DCMU_CTRL_GPIR3_MASK +*\*\return none +**/ +void DCMU_RequestGPInt( uint32_t ReqGPIntMask) +{ + __IO uint32_t tempreg; + + tempreg = DCMU->CTRL; + tempreg &= (~DCMU_CTRL_GPIR_ALL_MASK ); + tempreg |= ReqGPIntMask ; + + DCMU->CTRL = tempreg; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dma.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dma.c new file mode 100644 index 0000000000..a9d1bc707e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dma.c @@ -0,0 +1,1266 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dma.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_dma.h" + + +#define DMA_EVENT_MAX (5U) + + +/** +*\*\name DMA_ControllerCmd. +*\*\fun Enable or disable DMA Controller peripheral. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ControllerCmd(DMA_Module *const DMAy, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA Controller */ + SET_BIT(DMAy->CFG, DMA_CFG_EN); + } + else + { + /* Disable the DMA Controller */ + CLEAR_BIT(DMAy->CFG, DMA_CFG_EN); + } +} + +/** +*\*\name DMA_ControllerIsEnabled. +*\*\fun Check DMA Controller peripheral is enabled. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\return true or false +**/ +bool DMA_ControllerIsEnabled(DMA_Module *const DMAy) +{ + bool ret; + ret = READ_BIT(DMAy->CFG, DMA_CFG_EN) ? true : false; + return ret; +} + +/** +*\*\name DMA_ChannelCmd. +*\*\fun Enable or disable a DMA channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA channel */ + WRITE_REG(DMAy->CHEN, (DMA_CH_ENABLE << ChNum)); + } + else + { + /* Disable the DMA channel */ + WRITE_REG(DMAy->CHEN, (DMA_CH_DISABLE << ChNum)); + + while (READ_BIT((uint8_t)DMAy->CHEN, ((uint8_t)0x1U << ChNum)) != 0U) + { + /* Wait until channel is disabled */ + } + } +} + +/** +*\*\name DMA_ChannelIsEnabled. +*\*\fun Check whether a DMA channel enabled. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return true or false +**/ +bool DMA_ChannelIsEnabled(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + bool ret; + ret = READ_BIT((uint8_t)DMAy->CHEN, ((uint8_t)0x1U << ChNum)) ? true : false; + return ret; +} + +/** +*\*\name DMA_ChannelInit. +*\*\fun Initialize a DMA channel with provided channel configuration. +*\*\ The function sets up the following channel configuration parameters for +*\*\ a DMA channel specified paramters like: +*\*\ Source and Destination addresses (and linked list address if required). +*\*\ Source and Destination handshake method as software/hardware selection. +*\*\ Scatter/gather configuration and transfer flow and transfer type. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param DMA_ChInitParam : +*\*\ - Pointer to the DMA_ChInitType structure which will be initialized. +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return One of DMA_ChStatusType. +**/ +DMA_ChStatusType DMA_ChannelInit(DMA_Module *const DMAy, DMA_ChInitType *const DMA_ChInitParam, DMA_ChNumType ChNum) +{ + uint32_t TempValue; + DMA_ChStatusType RetStatus; + + /* Check whether the specified DMA controller is enabled */ + if (DMA_ControllerIsEnabled(DMAy) == ENABLE) + { + /* Checks whether the specified DMA channel is disabled */ + if (DMA_ChannelIsEnabled(DMAy, ChNum) == DISABLE) + { + /* Sets channel n source address register */ + WRITE_REG(DMAy->CH[ChNum].SA, DMA_ChInitParam->SrcAddr); + /* Sets channel n destination address register */ + WRITE_REG(DMAy->CH[ChNum].DA, DMA_ChInitParam->DstAddr); + /* Sets channel n linked list pointer register */ + WRITE_REG(DMAy->CH[ChNum].LLP, (uint32_t)DMA_ChInitParam->pLinkListItem); + /* Sets channel n control register */ + WRITE_REG(DMAy->CH[ChNum].CTRL, DMA_ChInitParam->ChCtrl); + + /* Sets channel n priority */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_CHPRIOR, ((uint64_t)DMA_ChInitParam->ChannelPriority << 0x5U)); + /* Sets channel n source handshaking interface polarity */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_SRCHSPOL, ((uint64_t)DMA_ChInitParam->SrcHsInterfacePol << 0x13U)); + /* Sets channel n destination handshaking interface polarity */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_DSTHSPOL, ((uint64_t)DMA_ChInitParam->DstHsInterfacePol << 0x12U)); + + /* Configure scatter and gather */ + if (DMA_ChInitParam->SrcGatherEn) + { + /* Write the DMA_CHnSG register */ + WRITE_REG(DMAy->CH[ChNum].SG, DMA_ChInitParam->SrcGatherCtrl); + } + + if (DMA_ChInitParam->DstScatterEn) + { + /* Write the DMA_CHnDS register */ + WRITE_REG(DMAy->CH[ChNum].DS, DMA_ChInitParam->DstScatterCtrl); + } + + /* Configure source handshaking hardware mode */ + if (DMA_ChInitParam->SrcHandshaking == DMA_CH_SRC_HANDSHAKING_HARDWARE) + { + if ((DMA_ChInitParam->TfrTypeFlowCtrl == DMA_CH_TRANSFER_FLOW_P2M_DMA) || \ + (DMA_ChInitParam->TfrTypeFlowCtrl == DMA_CH_TRANSFER_FLOW_P2P_DMA)) + { + TempValue = ((uint32_t)DMA_ChInitParam->SrcHsInterface & 0x7U); + /* Select hardware handshake I/F [0-7] */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_SRCPER, ((uint64_t)TempValue << 0x27U)); + + /* Enable hardware handshake to source peripheral */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_HSSELSRC); + } + } + + /* Configure destination handshaking hardware mode */ + if (DMA_ChInitParam->DstHandshaking == DMA_CH_DST_HANDSHAKING_HARDWARE) + { + /* Hardware handshaking interface configuration */ + if ((DMA_ChInitParam->TfrTypeFlowCtrl == DMA_CH_TRANSFER_FLOW_M2P_DMA) || \ + (DMA_ChInitParam->TfrTypeFlowCtrl == DMA_CH_TRANSFER_FLOW_P2P_DMA)) + { + TempValue = ((uint32_t)DMA_ChInitParam->DstHsInterface & 0x7U); + /* Select hardware handshake I/F [0-7] */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_DSTPER, ((uint64_t)TempValue << 0x2BU)); + + /* Enable hardware handshake to destionation peripheral */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_HSSELDST); + } + } + + /* Clear interrupt event status */ + DMA_ClearChannelEventStatus(DMAy, ChNum, (uint32_t)((uint32_t)DMA_CH_EVENT_TRANSFER_COMPLETE | \ + (uint32_t)DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE | \ + (uint32_t)DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | \ + (uint32_t)DMA_CH_EVENT_DST_TRANSACTION_COMPLETE | \ + (uint32_t)DMA_CH_EVENT_ERROR)); + + /* Configure the block tranfer type according to settings */ + switch (DMA_ChInitParam->TfrType) + { + case DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK: + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD: + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ADR); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS: + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ASR); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD: + SET_BIT(DMAy->CH[ChNum].CFG, (DMA_CHNCFG_ADR | DMA_CHNCFG_ASR)); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED: + SET_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_LLPDSTEN); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED: + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ASR); + SET_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_LLPDSTEN); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS: + SET_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_LLPSRCEN); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD: + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ADR); + SET_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_LLPSRCEN); + break; + + case DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED: + SET_BIT(DMAy->CH[ChNum].CTRL, (DMA_CHNCTRL_LLPSRCEN | DMA_CHNCTRL_LLPDSTEN)); + break; + + default: + break; + } + + RetStatus = DMA_CH_STS_OK; + } + else + { + RetStatus = DMA_CH_STS_BUSY; + } + } + else + { + RetStatus = DMA_CH_STS_ERROR; + } + + return RetStatus; +} + +/** +*\*\name DMA_ChannelStructInit. +*\*\fun Initializes the structure parameter of type DMA_ChInitType used to +*\*\ initialize DMA. This function is usually called before initializing +*\*\ a parameter of type DMA_ChInitType. +*\*\param DMA_ChInitParam : +*\*\ - Pointer to the DMA_ChInitType structure which will be initialized. +*\*\return none +**/ +void DMA_ChannelStructInit(DMA_ChInitType *const DMA_ChInitParam) +{ + DMA_ChInitParam->IntEn = true; + DMA_ChInitParam->DstTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + DMA_ChInitParam->SrcTfrWidth = DMA_CH_TRANSFER_WIDTH_8; + DMA_ChInitParam->DstAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + DMA_ChInitParam->SrcAddrCountMode = DMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + DMA_ChInitParam->DstBurstLen = DMA_CH_BURST_LENGTH_4; + DMA_ChInitParam->SrcBurstLen = DMA_CH_BURST_LENGTH_4; + DMA_ChInitParam->SrcGatherEn = false; + DMA_ChInitParam->DstScatterEn = false; + DMA_ChInitParam->DstMasterSelect = DMA_CH_AHB_MASTER_1; + DMA_ChInitParam->SrcMasterSelect = DMA_CH_AHB_MASTER_1; + DMA_ChInitParam->TfrTypeFlowCtrl = DMA_CH_TRANSFER_FLOW_P2P_DMA; + DMA_ChInitParam->BlkTfrSize = 0x2U; + DMA_ChInitParam->SrcAddr = 0x0U; + DMA_ChInitParam->DstAddr = 0x0U; + DMA_ChInitParam->pLinkListItem = NULL; + DMA_ChInitParam->SrcGatherInterval = 0x0U; + DMA_ChInitParam->SrcGatherCount = 0x0U; + DMA_ChInitParam->DstScatterInterval = 0x0U; + DMA_ChInitParam->DstScatterCount = 0x0U; + DMA_ChInitParam->TfrType = DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK; + DMA_ChInitParam->ChannelPriority = DMA_CH_PRIORITY_0; + DMA_ChInitParam->SrcHandshaking = DMA_CH_SRC_HANDSHAKING_SOFTWARE; + DMA_ChInitParam->SrcHsInterface = DMA_CH_HARDWARE_HANDSHAKING_IF_0; + DMA_ChInitParam->SrcHsInterfacePol = DMA_CH_HANDSHAKING_IF_POL_H; + DMA_ChInitParam->DstHandshaking = DMA_CH_DST_HANDSHAKING_SOFTWARE; + DMA_ChInitParam->DstHsInterface = DMA_CH_HARDWARE_HANDSHAKING_IF_0; + DMA_ChInitParam->DstHsInterfacePol = DMA_CH_HANDSHAKING_IF_POL_H; +} + +/** +*\*\name DMA_ChannelSuspend. +*\*\fun Suspend a DMA channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return none +**/ +void DMA_ChannelSuspend(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + /* Sets the CHSUSP bit of the CHnCFG register */ + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_CHSUSP); +} + +/** +*\*\name DMA_ChannelIsSuspended. +*\*\fun Check whether a DMA channel suspended. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return true or false +**/ +bool DMA_ChannelIsSuspended(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + bool ret; + ret = READ_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_CHSUSP) ? true : false; + return ret; +} + +/** +*\*\name DMA_ChannelResume. +*\*\fun Resume a DMA channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return none +**/ +void DMA_ChannelResume(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + /* Clear the CHSUSP bit of the CHnCFG register */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_CHSUSP); +} + +/** +*\*\name DMA_ChannelEventCmd. +*\*\fun Enable or disable a DMA event. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Event (The input parameter must be one or more of the following values (logical OR)): +*\*\ - DMA_CH_EVENT_TRANSFER_COMPLETE +*\*\ - DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE +*\*\ - DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE +*\*\ - DMA_CH_EVENT_DST_TRANSACTION_COMPLETE +*\*\ - DMA_CH_EVENT_ERROR +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelEventCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Event, FunctionalStatus Cmd) +{ + uint32_t TempIndex; + __IO uint32_t *pIntMaskRegBase = &DMAy->TCINTMSK; + + if (Cmd != DISABLE) + { + /* Enable the DMA Channel Interrupt Event */ + for (TempIndex = 0U; TempIndex < DMA_EVENT_MAX; TempIndex++) + { + if (Event & ((uint32_t)0x1U << TempIndex)) + { + WRITE_REG(*(pIntMaskRegBase + (TempIndex * 2U)), ((uint32_t)DMA_INT_UNMASK << ChNum)); + } + } + } + else + { + /* Disable the DMA Channel Interrupt Event */ + for (TempIndex = 0U; TempIndex < DMA_EVENT_MAX; TempIndex++) + { + if (Event & ((uint32_t)0x1U << TempIndex)) + { + WRITE_REG(*(pIntMaskRegBase + (TempIndex * 2U)), ((uint32_t)DMA_INT_MASK << ChNum)); + } + } + } +} + +/** +*\*\name DMA_ClearChannelEventStatus. +*\*\fun Clear a DMA channel event status. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Event (The input parameter must be one or more of the following values (logical OR)): +*\*\ - DMA_CH_EVENT_TRANSFER_COMPLETE +*\*\ - DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE +*\*\ - DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE +*\*\ - DMA_CH_EVENT_DST_TRANSACTION_COMPLETE +*\*\ - DMA_CH_EVENT_ERROR +*\*\return none +**/ +void DMA_ClearChannelEventStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Event) +{ + uint32_t TempIndex; + __IO uint32_t *pIntClearRegBase = &DMAy->TCINTCLR; + + /* Clear the DMA Channel Interrupt Event */ + for (TempIndex = 0U; TempIndex < DMA_EVENT_MAX; TempIndex++) + { + if (Event & ((uint32_t)0x1U << TempIndex)) + { + WRITE_REG(*(pIntClearRegBase + (TempIndex * 2U)), ((uint32_t)0x1U << ChNum)); + } + } +} + +/** +*\*\name DMA_GetCombinedStatus. +*\*\fun Get a DMA combined interrupt status. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\return DMA_INTCBESTS register value +**/ +uint8_t DMA_GetCombinedStatus(DMA_Module *const DMAy) +{ + return (uint8_t)(READ_REG(DMAy->INTCBESTS) & 0x1FU); +} + +/** +*\*\name DMA_GetChannelIntTfrStatus. +*\*\fun Gets the IntTfr interrupt event status for the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return SET or RESET +**/ +INTStatus DMA_GetChannelIntTfrStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + INTStatus RetStatus = RESET; + + /* Read the interrupt status of the corresponding register */ + if (READ_BIT(DMAy->TCINTSTS, (DMA_EVENT_TRANSFER_COMPLETE << ChNum)) != (uint32_t)RESET) + { + /* This status of the channel is SET */ + RetStatus = SET; + } + else + { + /* This status of the channel is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name DMA_GetChannelIntBlockStatus. +*\*\fun Gets the IntBlock interrupt event status for the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return SET or RESET +**/ +INTStatus DMA_GetChannelIntBlockStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + INTStatus RetStatus = RESET; + + /* Read the interrupt status of the corresponding register */ + if (READ_BIT(DMAy->BTCINTSTS, (DMA_EVENT_BLOCK_TRANSFER_COMPLETE << ChNum)) != (uint32_t)RESET) + { + /* This status of the channel is SET */ + RetStatus = SET; + } + else + { + /* This status of the channel is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name DMA_GetChannelIntSrcTranStatus. +*\*\fun Gets the IntSrcTran interrupt event status for the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return SET or RESET +**/ +INTStatus DMA_GetChannelIntSrcTranStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + INTStatus RetStatus = RESET; + + /* Read the interrupt status of the corresponding register */ + if (READ_BIT(DMAy->STCINTSTS, (DMA_EVENT_SRC_TRANSACTION_COMPLETE << ChNum)) != (uint32_t)RESET) + { + /* This status of the channel is SET */ + RetStatus = SET; + } + else + { + /* This status of the channel is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name DMA_GetChannelIntDstTranStatus. +*\*\fun Gets the IntDstTran interrupt event status for the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return SET or RESET +**/ +INTStatus DMA_GetChannelIntDstTranStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + INTStatus RetStatus = RESET; + + /* Read the interrupt status of the corresponding register */ + if (READ_BIT(DMAy->DTCINTSTS, (DMA_EVENT_DST_TRANSACTION_COMPLETE << ChNum)) != (uint32_t)RESET) + { + /* This status of the channel is SET */ + RetStatus = SET; + } + else + { + /* This status of the channel is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name DMA_GetChannelIntErrStatus. +*\*\fun Gets the IntErr interrupt event status for the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return SET or RESET +**/ +INTStatus DMA_GetChannelIntErrStatus(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + INTStatus RetStatus = RESET; + + /* Read the interrupt status of the corresponding register */ + if (READ_BIT(DMAy->ERRINTSTS, (DMA_EVENT_ERROR << ChNum)) != (uint32_t)RESET) + { + /* This status of the channel is SET */ + RetStatus = SET; + } + else + { + /* This status of the channel is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name DMA_ChannelSourceGatherCmd. +*\*\fun Enable or disable a DMA Channel source gather. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelSourceGatherCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Source gather */ + SET_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_SRCGATEN); + } + else + { + /* Disable the Source gather */ + CLEAR_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_SRCGATEN); + } +} + +/** +*\*\name DMA_SetChannelSourceGather. +*\*\fun Sets the source gather interval and count of the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Interval: +*\*\ - Source Gather Interval (0~0xFFFFF) +*\*\param Count: +*\*\ - Source contiguous transfer count between successive gather boundaries (0~0x1FF) +*\*\return none +**/ +void DMA_SetChannelSourceGather(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Interval, uint16_t Count) +{ + WRITE_REG(DMAy->CH[ChNum].SG, (Interval | (Count << 20U))); +} + +/** +*\*\name DMA_ChannelDestinationScatterCmd. +*\*\fun Enable or disable a DMA Channel destination scatter. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelDestinationScatterCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the destination scatter */ + SET_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_DSTSCAEN); + } + else + { + /* Disable the destination scatter */ + CLEAR_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_DSTSCAEN); + } +} + +/** +*\*\name DMA_SetChannelDestinationScatter. +*\*\fun Sets the destination scatter interval and count of the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Interval: +*\*\ - Destination scatter Interval (0~0xFFFFF) +*\*\param Count: +*\*\ - Destination contiguous transfer count between successive scatter boundaries (0~0x1FF) +*\*\return none +**/ +void DMA_SetChannelDestinationScatter(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Interval, uint16_t Count) +{ + WRITE_REG(DMAy->CH[ChNum].DS, (Interval | (Count << 20U))); +} + +/** +*\*\name DMA_SetChannelSourceAddress. +*\*\fun Sets the source address of the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param pAddr: +*\*\ - Pointer to source address +*\*\return none +**/ +void DMA_SetChannelSourceAddress(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t *pAddr) +{ + WRITE_REG(DMAy->CH[ChNum].SA, (uint32_t)pAddr); +} + +/** +*\*\name DMA_SetChannelDestinationAddress. +*\*\fun Sets the destination address of the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param pAddr: +*\*\ - Pointer to destination address +*\*\return none +**/ +void DMA_SetChannelDestinationAddress(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t *pAddr) +{ + WRITE_REG(DMAy->CH[ChNum].DA, (uint32_t)pAddr); +} + +/** +*\*\name DMA_SetChannelBlockSize. +*\*\fun Sets the block transfer size of the specified channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Size: +*\*\ - The transferred size +*\*\return none +**/ +void DMA_SetChannelBlockSize(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t Size) +{ + MODIFY_REG(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_BTS, ((uint64_t)Size << 32U)); +} + +/** +*\*\name DMA_GetTransferredNumber. +*\*\fun Gets the number of data that has been transmitted by the current channel. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\return Number of data sent +**/ +uint16_t DMA_GetTransferredNumber(DMA_Module *const DMAy, DMA_ChNumType ChNum) +{ + return (uint16_t)(READ_BIT(DMAy->CH[ChNum].CTRL, DMA_CHNCTRL_BTS) >> 32U); +} + +/** +*\*\name DMA_SetChannelLinkedListPointer. +*\*\fun Sets linked list pointer function. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param pStr: +*\*\ - Pointer to DMA linked list item structure +*\*\return none +**/ +void DMA_SetChannelLinkedListPointer(DMA_Module *const DMAy, DMA_ChNumType ChNum, DMA_LinkListItemType* pStr) +{ + WRITE_REG(DMAy->CH[ChNum].LLP, (uint32_t)pStr); +} + +/** +*\*\name DMA_TriggerSourceRequest. +*\*\fun Trigger a software source handshake request. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Type (The input parameters must be the following values): +*\*\ - DMA_CH_TRANSACTION_TYPE_SINGLE +*\*\ - DMA_CH_TRANSACTION_TYPE_BURST +*\*\param isLast: +*\*\ - true or false +*\*\return none +**/ +void DMA_TriggerSourceRequest(DMA_Module *const DMAy, DMA_ChNumType ChNum, DMA_ChTransacType Type, bool isLast) +{ + if (Type == DMA_CH_TRANSACTION_TYPE_SINGLE) + { + /* Enable Channel n Source Single Transaction Request */ + WRITE_REG(DMAy->SRCSGTREQ, (DMA_SSTR_ENABLE << ChNum)); + } + + if (isLast == true) + { + /* Enable Channel n Source Last Transaction Request */ + WRITE_REG(DMAy->SRCLTREQ, (DMA_SLTR_ENABLE << ChNum)); + } + + /* Enable Channel n Source Transaction Request */ + WRITE_REG(DMAy->SRCSWTREQ, (DMA_STR_ENABLE << ChNum)); +} + +/** +*\*\name DMA_TriggerDestinationRequest. +*\*\fun Trigger a software Destination handshake request. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Type (The input parameters must be the following values): +*\*\ - DMA_CH_TRANSACTION_TYPE_SINGLE +*\*\ - DMA_CH_TRANSACTION_TYPE_BURST +*\*\param isLast: +*\*\ - true or false +*\*\return none +**/ +void DMA_TriggerDestinationRequest(DMA_Module *const DMAy, DMA_ChNumType ChNum, DMA_ChTransacType Type, bool isLast) +{ + if (Type == DMA_CH_TRANSACTION_TYPE_SINGLE) + { + /* Enable Channel n Destination Single Transaction Request */ + WRITE_REG(DMAy->DSTSGTREQ, (DMA_DSTR_ENABLE << ChNum)); + } + + if (isLast == true) + { + /* Enable Channel n Destination Last Transaction Request */ + WRITE_REG(DMAy->DSTLTREQ, (DMA_DLTR_ENABLE << ChNum)); + } + + /* Enable Channel n Destination Transaction Request */ + WRITE_REG(DMAy->DSTSWTREQ, (DMA_DTR_ENABLE << ChNum)); +} + +/** +*\*\name DMA_ChannelSourceAddressReloadCmd. +*\*\fun Enable or disable a DMA Channel source address reload. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelSourceAddressReloadCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Automatic Source Reload */ + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ASR); + } + else + { + /* Disable the Automatic Source Reload */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ASR); + } +} + +/** +*\*\name DMA_ChannelDestinationAddressReloadCmd. +*\*\fun Enable or disable a DMA Channel destination address reload. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelDestinationAddressReloadCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Automatic Destination Reload */ + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ADR); + } + else + { + /* Disable the Automatic Destination Reload */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_ADR); + } +} + +/** +*\*\name DMA_ChannelBusLockCmd. +*\*\fun Enable or disable a DMA Channel bus lock. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelBusLockCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA Channel bus lock */ + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_LOCKB); + } + else + { + /* Disable the DMA Channel bus lock */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_LOCKB); + } +} + +/** +*\*\name DMA_ChannelLockCmd. +*\*\fun Enable or disable a DMA Channel lock. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DMA_ChannelLockCmd(DMA_Module *const DMAy, DMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA Channel lock */ + SET_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_LOCKCH); + } + else + { + /* Disable the DMA Channel lock */ + CLEAR_BIT(DMAy->CH[ChNum].CFG, DMA_CHNCFG_LOCKCH); + } +} + +/** +*\*\name DMA_SetChannelBusLockLevel. +*\*\fun Set DMA Channel bus lock level. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Level (The input parameters must be the following values): +*\*\ - DMA_CH_BUS_LOCK_LEVEL_OCDMATFR +*\*\ - DMA_CH_BUS_LOCK_LEVEL_OCDMABLKTFR +*\*\ - DMA_CH_BUS_LOCK_LEVEL_OCDMATRAN +*\*\return none +**/ +void DMA_SetChannelBusLockLevel(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint64_t Level) +{ + /* Set the DMA Channel bus lock level */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_LOCKBL, Level); +} + +/** +*\*\name DMA_SetChannelLockLevel. +*\*\fun Set DMA Channel lock level. +*\*\param DMAy (The input parameters must be the following values): +*\*\ - DMA1 +*\*\ - DMA2 +*\*\ - DMA3 +*\*\param ChNum (The input parameters must be the following values): +*\*\ - DMA_CHANNEL_0 +*\*\ - DMA_CHANNEL_1 +*\*\ - DMA_CHANNEL_2 +*\*\ - DMA_CHANNEL_3 +*\*\ - DMA_CHANNEL_4 +*\*\ - DMA_CHANNEL_5 +*\*\ - DMA_CHANNEL_6 +*\*\ - DMA_CHANNEL_7 +*\*\param Level (The input parameters must be the following values): +*\*\ - DMA_CH_LOCK_LEVEL_OCDMATFR +*\*\ - DMA_CH_LOCK_LEVEL_OCDMABLKTFR +*\*\ - DMA_CH_LOCK_LEVEL_OCDMATRAN +*\*\return none +**/ +void DMA_SetChannelLockLevel(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint64_t Level) +{ + /* Set the DMA Channel lock level */ + MODIFY_REG(DMAy->CH[ChNum].CFG, DMA_CHNCFG_LOCKCHL, Level); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dmamux.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dmamux.c new file mode 100644 index 0000000000..180ba1e311 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dmamux.c @@ -0,0 +1,1899 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dmamux.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_dmamux.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name DMAMUX_DeInit. +*\*\fun Reset the DMAMUX registers. +*\*\param DMAMUXx : +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\return none +**/ +void DMAMUX_DeInit(DMAMUX_ID DMAMUXx) +{ + if (DMAMUXx == DMAMUX1_ID) + { + RCC_EnableAHB1PeriphReset1(RCC_AHB1_PERIPHRST_DMAMUX1); + } + else if (DMAMUXx == DMAMUX2_ID) + { + RCC_EnableAXIPeriphReset1(RCC_AXI_PERIPHRST_DMAMUX2); + } + else + { + /*no process*/ + } +} + +/** +*\*\name DMAMUX_SetRequestID. +*\*\fun Set DMAMUX request ID for DMAMUX Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param Request (The input parameters must be the following values): +*\*\ - DMAMUX1_REQUEST_GENERATOR0 +*\*\ - DMAMUX1_REQUEST_GENERATOR1 +*\*\ - DMAMUX1_REQUEST_GENERATOR2 +*\*\ - DMAMUX1_REQUEST_GENERATOR3 +*\*\ - DMAMUX1_REQUEST_GENERATOR4 +*\*\ - DMAMUX1_REQUEST_GENERATOR5 +*\*\ - DMAMUX1_REQUEST_GENERATOR6 +*\*\ - DMAMUX1_REQUEST_GENERATOR7 +*\*\ - DMAMUX1_REQUEST_ADC1 +*\*\ - DMAMUX1_REQUEST_ADC2 +*\*\ - DMAMUX1_REQUEST_ADC3 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA0 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA1 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA2 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA3 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA4 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA5 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA6 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA0 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA1 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA2 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA3 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA4 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA5 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA6 +*\*\ - DMAMUX1_REQUEST_ATIM1_UP +*\*\ - DMAMUX1_REQUEST_ATIM1_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM1_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM1_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM1_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM1_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM1_COM +*\*\ - DMAMUX1_REQUEST_ATIM2_UP +*\*\ - DMAMUX1_REQUEST_ATIM2_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM2_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM2_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM2_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM2_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM2_COM +*\*\ - DMAMUX1_REQUEST_ATIM3_UP +*\*\ - DMAMUX1_REQUEST_ATIM3_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM3_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM3_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM3_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM3_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM3_COM +*\*\ - DMAMUX1_REQUEST_ATIM4_UP +*\*\ - DMAMUX1_REQUEST_ATIM4_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM4_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM4_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM4_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM4_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM4_COM +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA1_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA1_UP +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA2_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA2_UP +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA3_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA3_UP +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA4_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA4_UP +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA5_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA5_UP +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA6_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA6_UP +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA7_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA7_UP +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMB1_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMB1_UP +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMB2_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMB2_UP +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMB3_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMB3_UP +*\*\ - DMAMUX1_REQUEST_I2C1_RX +*\*\ - DMAMUX1_REQUEST_I2C1_TX +*\*\ - DMAMUX1_REQUEST_I2C2_RX +*\*\ - DMAMUX1_REQUEST_I2C2_TX +*\*\ - DMAMUX1_REQUEST_I2C3_RX +*\*\ - DMAMUX1_REQUEST_I2C3_TX +*\*\ - DMAMUX1_REQUEST_I2C4_RX +*\*\ - DMAMUX1_REQUEST_I2C4_TX +*\*\ - DMAMUX1_REQUEST_I2C5_RX +*\*\ - DMAMUX1_REQUEST_I2C5_TX +*\*\ - DMAMUX1_REQUEST_I2C6_RX +*\*\ - DMAMUX1_REQUEST_I2C6_TX +*\*\ - DMAMUX1_REQUEST_I2C7_RX +*\*\ - DMAMUX1_REQUEST_I2C7_TX +*\*\ - DMAMUX1_REQUEST_I2C8_RX +*\*\ - DMAMUX1_REQUEST_I2C8_TX +*\*\ - DMAMUX1_REQUEST_I2C9_RX +*\*\ - DMAMUX1_REQUEST_I2C9_TX +*\*\ - DMAMUX1_REQUEST_I2C10_RX +*\*\ - DMAMUX1_REQUEST_I2C10_TX +*\*\ - DMAMUX1_REQUEST_USART1_RX +*\*\ - DMAMUX1_REQUEST_USART1_TX +*\*\ - DMAMUX1_REQUEST_USART2_RX +*\*\ - DMAMUX1_REQUEST_USART2_TX +*\*\ - DMAMUX1_REQUEST_USART3_RX +*\*\ - DMAMUX1_REQUEST_USART3_TX +*\*\ - DMAMUX1_REQUEST_USART4_RX +*\*\ - DMAMUX1_REQUEST_USART4_TX +*\*\ - DMAMUX1_REQUEST_USART5_RX +*\*\ - DMAMUX1_REQUEST_USART5_TX +*\*\ - DMAMUX1_REQUEST_USART6_RX +*\*\ - DMAMUX1_REQUEST_USART6_TX +*\*\ - DMAMUX1_REQUEST_USART7_RX +*\*\ - DMAMUX1_REQUEST_USART7_TX +*\*\ - DMAMUX1_REQUEST_USART8_RX +*\*\ - DMAMUX1_REQUEST_USART8_TX +*\*\ - DMAMUX1_REQUEST_UART9_RX +*\*\ - DMAMUX1_REQUEST_UART9_TX +*\*\ - DMAMUX1_REQUEST_UART10_RX +*\*\ - DMAMUX1_REQUEST_UART10_TX +*\*\ - DMAMUX1_REQUEST_UART11_RX +*\*\ - DMAMUX1_REQUEST_UART11_TX +*\*\ - DMAMUX1_REQUEST_UART12_RX +*\*\ - DMAMUX1_REQUEST_UART12_TX +*\*\ - DMAMUX1_REQUEST_UART13_RX +*\*\ - DMAMUX1_REQUEST_UART13_TX +*\*\ - DMAMUX1_REQUEST_UART14_RX +*\*\ - DMAMUX1_REQUEST_UART14_TX +*\*\ - DMAMUX1_REQUEST_UART15_RX +*\*\ - DMAMUX1_REQUEST_UART15_TX +*\*\ - DMAMUX1_REQUEST_SPI1_RX +*\*\ - DMAMUX1_REQUEST_SPI1_TX +*\*\ - DMAMUX1_REQUEST_SPI2_RX +*\*\ - DMAMUX1_REQUEST_SPI2_TX +*\*\ - DMAMUX1_REQUEST_SPI3_RX +*\*\ - DMAMUX1_REQUEST_SPI3_TX +*\*\ - DMAMUX1_REQUEST_SPI4_RX +*\*\ - DMAMUX1_REQUEST_SPI4_TX +*\*\ - DMAMUX1_REQUEST_SPI5_RX +*\*\ - DMAMUX1_REQUEST_SPI5_TX +*\*\ - DMAMUX1_REQUEST_SPI6_RX +*\*\ - DMAMUX1_REQUEST_SPI6_TX +*\*\ - DMAMUX1_REQUEST_SPI7_RX +*\*\ - DMAMUX1_REQUEST_SPI7_TX +*\*\ - DMAMUX1_REQUEST_I2S1_RX +*\*\ - DMAMUX1_REQUEST_I2S1_TX +*\*\ - DMAMUX1_REQUEST_I2S2_RX +*\*\ - DMAMUX1_REQUEST_I2S2_TX +*\*\ - DMAMUX1_REQUEST_I2S3_RX +*\*\ - DMAMUX1_REQUEST_I2S3_TX +*\*\ - DMAMUX1_REQUEST_I2S4_RX +*\*\ - DMAMUX1_REQUEST_I2S4_TX +*\*\ - DMAMUX1_REQUEST_LPUART1_RX +*\*\ - DMAMUX1_REQUEST_LPUART1_TX +*\*\ - DMAMUX1_REQUEST_LPUART2_RX +*\*\ - DMAMUX1_REQUEST_LPUART2_TX +*\*\ - DMAMUX1_REQUEST_DAC1 +*\*\ - DMAMUX1_REQUEST_DAC2 +*\*\ - DMAMUX1_REQUEST_DSMU_CH1 +*\*\ - DMAMUX1_REQUEST_DSMU_CH2 +*\*\ - DMAMUX1_REQUEST_DSMU_CH3 +*\*\ - DMAMUX1_REQUEST_DSMU_CH4 +*\*\ - DMAMUX1_REQUEST_CANFD1 +*\*\ - DMAMUX1_REQUEST_CANFD2 +*\*\ - DMAMUX1_REQUEST_CANFD3 +*\*\ - DMAMUX1_REQUEST_CANFD4 +*\*\ - DMAMUX1_REQUEST_CANFD5 +*\*\ - DMAMUX1_REQUEST_CANFD6 +*\*\ - DMAMUX1_REQUEST_CANFD7 +*\*\ - DMAMUX1_REQUEST_CANFD8 +*\*\ - DMAMUX1_REQUEST_CORDIC_READ +*\*\ - DMAMUX1_REQUEST_CORDIC_WRITE +*\*\ - DMAMUX1_REQUEST_FMAC_READ +*\*\ - DMAMUX1_REQUEST_FMAC_WRITE +*\*\ - DMAMUX1_REQUEST_BTIM1 +*\*\ - DMAMUX1_REQUEST_BTIM2 +*\*\ - DMAMUX1_REQUEST_BTIM3 +*\*\ - DMAMUX1_REQUEST_BTIM4 +*\*\ - DMAMUX1_REQUEST_GTIMB1_COM +*\*\ - DMAMUX1_REQUEST_GTIMB2_COM +*\*\ - DMAMUX1_REQUEST_GTIMB3_COM +*\*\ - DMAMUX1_REQUEST_DAC3 +*\*\ - DMAMUX1_REQUEST_DAC4 +*\*\ - DMAMUX1_REQUEST_DAC5 +*\*\ - DMAMUX1_REQUEST_DAC6 +*\*\ - DMAMUX2_REQUEST_GENERATOR0 +*\*\ - DMAMUX2_REQUEST_GENERATOR1 +*\*\ - DMAMUX2_REQUEST_GENERATOR2 +*\*\ - DMAMUX2_REQUEST_GENERATOR3 +*\*\ - DMAMUX2_REQUEST_GENERATOR4 +*\*\ - DMAMUX2_REQUEST_GENERATOR5 +*\*\ - DMAMUX2_REQUEST_GENERATOR6 +*\*\ - DMAMUX2_REQUEST_GENERATOR7 +*\*\ - DMAMUX2_REQUEST_GENERATOR8 +*\*\ - DMAMUX2_REQUEST_GENERATOR9 +*\*\ - DMAMUX2_REQUEST_GENERATOR10 +*\*\ - DMAMUX2_REQUEST_GENERATOR11 +*\*\ - DMAMUX2_REQUEST_GENERATOR12 +*\*\ - DMAMUX2_REQUEST_GENERATOR13 +*\*\ - DMAMUX2_REQUEST_GENERATOR14 +*\*\ - DMAMUX2_REQUEST_GENERATOR15 +*\*\ - DMAMUX2_REQUEST_REQ_XSPI1_RX +*\*\ - DMAMUX2_REQUEST_REQ_XSPI1_TX +*\*\ - DMAMUX2_REQUEST_REQ_XSPI2_RX +*\*\ - DMAMUX2_REQUEST_REQ_XSPI2_TX +*\*\note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. +*\*\ DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. +*\*\ DMAMUX1 channel 16 to 23 are mapped to DMA3 channel 0 to 7. +*\*\ DMAMUX2 channel 0 to 15 are mapped to MDMA channel 0 to 15. +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_SetRequestID(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t Request) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_REQUEST_ID_MASK); + tempreg |= (Request); + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_REQUEST_ID_MASK); + tempreg |= (Request); + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } +} + +/** +*\*\name DMAMUX_GetRequestID. +*\*\fun Get DMAMUX request ID for DMAMUX Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\return (Returned value can be one of the following values); +*\*\ - DMAMUX1_REQUEST_GENERATOR0 +*\*\ - DMAMUX1_REQUEST_GENERATOR1 +*\*\ - DMAMUX1_REQUEST_GENERATOR2 +*\*\ - DMAMUX1_REQUEST_GENERATOR3 +*\*\ - DMAMUX1_REQUEST_GENERATOR4 +*\*\ - DMAMUX1_REQUEST_GENERATOR5 +*\*\ - DMAMUX1_REQUEST_GENERATOR6 +*\*\ - DMAMUX1_REQUEST_GENERATOR7 +*\*\ - DMAMUX1_REQUEST_ADC1 +*\*\ - DMAMUX1_REQUEST_ADC2 +*\*\ - DMAMUX1_REQUEST_ADC3 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA0 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA1 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA2 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA3 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA4 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA5 +*\*\ - DMAMUX1_REQUEST_SHRTIM1_DMA6 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA0 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA1 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA2 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA3 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA4 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA5 +*\*\ - DMAMUX1_REQUEST_SHRTIM2_DMA6 +*\*\ - DMAMUX1_REQUEST_ATIM1_UP +*\*\ - DMAMUX1_REQUEST_ATIM1_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM1_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM1_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM1_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM1_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM1_COM +*\*\ - DMAMUX1_REQUEST_ATIM2_UP +*\*\ - DMAMUX1_REQUEST_ATIM2_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM2_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM2_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM2_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM2_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM2_COM +*\*\ - DMAMUX1_REQUEST_ATIM3_UP +*\*\ - DMAMUX1_REQUEST_ATIM3_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM3_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM3_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM3_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM3_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM3_COM +*\*\ - DMAMUX1_REQUEST_ATIM4_UP +*\*\ - DMAMUX1_REQUEST_ATIM4_CH1 +*\*\ - DMAMUX1_REQUEST_ATIM4_CH2 +*\*\ - DMAMUX1_REQUEST_ATIM4_CH3 +*\*\ - DMAMUX1_REQUEST_ATIM4_CH4 +*\*\ - DMAMUX1_REQUEST_ATIM4_TRIG +*\*\ - DMAMUX1_REQUEST_ATIM4_COM +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA1_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA1_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA1_UP +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA2_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA2_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA2_UP +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA3_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA3_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA3_UP +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA4_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA4_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA4_UP +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA5_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA5_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA5_UP +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA6_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA6_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA6_UP +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMA7_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMA7_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMA7_UP +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMB1_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMB1_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMB1_UP +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMB2_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMB2_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMB2_UP +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH1 +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH2 +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH3 +*\*\ - DMAMUX1_REQUEST_GTIMB3_CH4 +*\*\ - DMAMUX1_REQUEST_GTIMB3_TRIG +*\*\ - DMAMUX1_REQUEST_GTIMB3_UP +*\*\ - DMAMUX1_REQUEST_I2C1_RX +*\*\ - DMAMUX1_REQUEST_I2C1_TX +*\*\ - DMAMUX1_REQUEST_I2C2_RX +*\*\ - DMAMUX1_REQUEST_I2C2_TX +*\*\ - DMAMUX1_REQUEST_I2C3_RX +*\*\ - DMAMUX1_REQUEST_I2C3_TX +*\*\ - DMAMUX1_REQUEST_I2C4_RX +*\*\ - DMAMUX1_REQUEST_I2C4_TX +*\*\ - DMAMUX1_REQUEST_I2C5_RX +*\*\ - DMAMUX1_REQUEST_I2C5_TX +*\*\ - DMAMUX1_REQUEST_I2C6_RX +*\*\ - DMAMUX1_REQUEST_I2C6_TX +*\*\ - DMAMUX1_REQUEST_I2C7_RX +*\*\ - DMAMUX1_REQUEST_I2C7_TX +*\*\ - DMAMUX1_REQUEST_I2C8_RX +*\*\ - DMAMUX1_REQUEST_I2C8_TX +*\*\ - DMAMUX1_REQUEST_I2C9_RX +*\*\ - DMAMUX1_REQUEST_I2C9_TX +*\*\ - DMAMUX1_REQUEST_I2C10_RX +*\*\ - DMAMUX1_REQUEST_I2C10_TX +*\*\ - DMAMUX1_REQUEST_USART1_RX +*\*\ - DMAMUX1_REQUEST_USART1_TX +*\*\ - DMAMUX1_REQUEST_USART2_RX +*\*\ - DMAMUX1_REQUEST_USART2_TX +*\*\ - DMAMUX1_REQUEST_USART3_RX +*\*\ - DMAMUX1_REQUEST_USART3_TX +*\*\ - DMAMUX1_REQUEST_USART4_RX +*\*\ - DMAMUX1_REQUEST_USART4_TX +*\*\ - DMAMUX1_REQUEST_USART5_RX +*\*\ - DMAMUX1_REQUEST_USART5_TX +*\*\ - DMAMUX1_REQUEST_USART6_RX +*\*\ - DMAMUX1_REQUEST_USART6_TX +*\*\ - DMAMUX1_REQUEST_USART7_RX +*\*\ - DMAMUX1_REQUEST_USART7_TX +*\*\ - DMAMUX1_REQUEST_USART8_RX +*\*\ - DMAMUX1_REQUEST_USART8_TX +*\*\ - DMAMUX1_REQUEST_UART9_RX +*\*\ - DMAMUX1_REQUEST_UART9_TX +*\*\ - DMAMUX1_REQUEST_UART10_RX +*\*\ - DMAMUX1_REQUEST_UART10_TX +*\*\ - DMAMUX1_REQUEST_UART11_RX +*\*\ - DMAMUX1_REQUEST_UART11_TX +*\*\ - DMAMUX1_REQUEST_UART12_RX +*\*\ - DMAMUX1_REQUEST_UART12_TX +*\*\ - DMAMUX1_REQUEST_UART13_RX +*\*\ - DMAMUX1_REQUEST_UART13_TX +*\*\ - DMAMUX1_REQUEST_UART14_RX +*\*\ - DMAMUX1_REQUEST_UART14_TX +*\*\ - DMAMUX1_REQUEST_UART15_RX +*\*\ - DMAMUX1_REQUEST_UART15_TX +*\*\ - DMAMUX1_REQUEST_SPI1_RX +*\*\ - DMAMUX1_REQUEST_SPI1_TX +*\*\ - DMAMUX1_REQUEST_SPI2_RX +*\*\ - DMAMUX1_REQUEST_SPI2_TX +*\*\ - DMAMUX1_REQUEST_SPI3_RX +*\*\ - DMAMUX1_REQUEST_SPI3_TX +*\*\ - DMAMUX1_REQUEST_SPI4_RX +*\*\ - DMAMUX1_REQUEST_SPI4_TX +*\*\ - DMAMUX1_REQUEST_SPI5_RX +*\*\ - DMAMUX1_REQUEST_SPI5_TX +*\*\ - DMAMUX1_REQUEST_SPI6_RX +*\*\ - DMAMUX1_REQUEST_SPI6_TX +*\*\ - DMAMUX1_REQUEST_SPI7_RX +*\*\ - DMAMUX1_REQUEST_SPI7_TX +*\*\ - DMAMUX1_REQUEST_I2S1_RX +*\*\ - DMAMUX1_REQUEST_I2S1_TX +*\*\ - DMAMUX1_REQUEST_I2S2_RX +*\*\ - DMAMUX1_REQUEST_I2S2_TX +*\*\ - DMAMUX1_REQUEST_I2S3_RX +*\*\ - DMAMUX1_REQUEST_I2S3_TX +*\*\ - DMAMUX1_REQUEST_I2S4_RX +*\*\ - DMAMUX1_REQUEST_I2S4_TX +*\*\ - DMAMUX1_REQUEST_LPUART1_RX +*\*\ - DMAMUX1_REQUEST_LPUART1_TX +*\*\ - DMAMUX1_REQUEST_LPUART2_RX +*\*\ - DMAMUX1_REQUEST_LPUART2_TX +*\*\ - DMAMUX1_REQUEST_DAC1 +*\*\ - DMAMUX1_REQUEST_DAC2 +*\*\ - DMAMUX1_REQUEST_DSMU_CH1 +*\*\ - DMAMUX1_REQUEST_DSMU_CH2 +*\*\ - DMAMUX1_REQUEST_DSMU_CH3 +*\*\ - DMAMUX1_REQUEST_DSMU_CH4 +*\*\ - DMAMUX1_REQUEST_CANFD1 +*\*\ - DMAMUX1_REQUEST_CANFD2 +*\*\ - DMAMUX1_REQUEST_CANFD3 +*\*\ - DMAMUX1_REQUEST_CANFD4 +*\*\ - DMAMUX1_REQUEST_CANFD5 +*\*\ - DMAMUX1_REQUEST_CANFD6 +*\*\ - DMAMUX1_REQUEST_CANFD7 +*\*\ - DMAMUX1_REQUEST_CANFD8 +*\*\ - DMAMUX1_REQUEST_CORDIC_READ +*\*\ - DMAMUX1_REQUEST_CORDIC_WRITE +*\*\ - DMAMUX1_REQUEST_FMAC_READ +*\*\ - DMAMUX1_REQUEST_FMAC_WRITE +*\*\ - DMAMUX1_REQUEST_BTIM1 +*\*\ - DMAMUX1_REQUEST_BTIM2 +*\*\ - DMAMUX1_REQUEST_BTIM3 +*\*\ - DMAMUX1_REQUEST_BTIM4 +*\*\ - DMAMUX1_REQUEST_GTIMB1_COM +*\*\ - DMAMUX1_REQUEST_GTIMB2_COM +*\*\ - DMAMUX1_REQUEST_GTIMB3_COM +*\*\ - DMAMUX1_REQUEST_DAC3 +*\*\ - DMAMUX1_REQUEST_DAC4 +*\*\ - DMAMUX1_REQUEST_DAC5 +*\*\ - DMAMUX1_REQUEST_DAC6 +*\*\ - DMAMUX2_REQUEST_GENERATOR0 +*\*\ - DMAMUX2_REQUEST_GENERATOR1 +*\*\ - DMAMUX2_REQUEST_GENERATOR2 +*\*\ - DMAMUX2_REQUEST_GENERATOR3 +*\*\ - DMAMUX2_REQUEST_GENERATOR4 +*\*\ - DMAMUX2_REQUEST_GENERATOR5 +*\*\ - DMAMUX2_REQUEST_GENERATOR6 +*\*\ - DMAMUX2_REQUEST_GENERATOR7 +*\*\ - DMAMUX2_REQUEST_GENERATOR8 +*\*\ - DMAMUX2_REQUEST_GENERATOR9 +*\*\ - DMAMUX2_REQUEST_GENERATOR10 +*\*\ - DMAMUX2_REQUEST_GENERATOR11 +*\*\ - DMAMUX2_REQUEST_GENERATOR12 +*\*\ - DMAMUX2_REQUEST_GENERATOR13 +*\*\ - DMAMUX2_REQUEST_GENERATOR14 +*\*\ - DMAMUX2_REQUEST_GENERATOR15 +*\*\ - DMAMUX2_REQUEST_REQ_XSPI1_RX +*\*\ - DMAMUX2_REQUEST_REQ_XSPI1_TX +*\*\ - DMAMUX2_REQUEST_REQ_XSPI2_RX +*\*\ - DMAMUX2_REQUEST_REQ_XSPI2_TX +*\*\note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. +*\*\ DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. +*\*\ DMAMUX1 channel 16 to 23 are mapped to DMA3 channel 0 to 7. +*\*\ DMAMUX2 channel 0 to 15 are mapped to MDMA channel 0 to 15. +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +uint32_t DMAMUX_GetRequestID(DMAMUX_ID DMAMUXx, uint32_t Channel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + + return (uint32_t)(tempreg & DMAMUX_REQUEST_ID_MASK); +} + +/** +*\*\name DMAMUX_SetSyncID. +*\*\fun Set DMAMUX synchronization ID on DMAMUX Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param SyncID (The input parameters must be the following values): +*\*\ - DMAMUX1_SYNC_DMAMUX1_EVT0_7 +*\*\ - DMAMUX1_SYNC_DMAMUX1_EVT8_15 +*\*\ - DMAMUX1_SYNC_DMAMUX1_EVT16_23 +*\*\ - DMAMUX1_SYNC_LPTIM5_OUT +*\*\ - DMAMUX1_SYNC_LPTIM4_OUT +*\*\ - DMAMUX1_SYNC_LPTIM3_OUT +*\*\ - DMAMUX1_SYNC_LPTIM2_OUT +*\*\ - DMAMUX1_SYNC_LPTIM1_OUT +*\*\ - DMAMUX1_SYNC_EXTI0 +*\*\ - DMAMUX2_SYNC_INTERNAL_USED +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_SetSyncID(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_SYNC_ID_MASK); + tempreg |= (SyncID); + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_SYNC_ID_MASK); + tempreg |= (SyncID); + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } +} + +/** +*\*\name DMAMUX_GetSyncID. +*\*\fun Get DMAMUX synchronization ID on DMAMUX Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\return (Returned value can be one of the following values): +*\*\ - DMAMUX1_SYNC_DMAMUX1_EVT0_7 +*\*\ - DMAMUX1_SYNC_DMAMUX1_EVT8_15 +*\*\ - DMAMUX1_SYNC_DMAMUX1_EVT16_23 +*\*\ - DMAMUX1_SYNC_LPTIM5_OUT +*\*\ - DMAMUX1_SYNC_LPTIM4_OUT +*\*\ - DMAMUX1_SYNC_LPTIM3_OUT +*\*\ - DMAMUX1_SYNC_LPTIM2_OUT +*\*\ - DMAMUX1_SYNC_LPTIM1_OUT +*\*\ - DMAMUX1_SYNC_EXTI0 +*\*\ - DMAMUX2_SYNC_INTERNAL_USED +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +uint32_t DMAMUX_GetSyncID(DMAMUX_ID DMAMUXx, uint32_t Channel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + + return (uint32_t)(tempreg & DMAMUX_SYNC_ID_MASK); +} + +/** +*\*\name DMAMUX_SetSyncRequestNumber. +*\*\fun Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param RequestNumber This parameter must be a value between Min_Data = 1 and Max_Data = 32. +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_SetSyncRequestNumber(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t RequestNumber) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_REQ_NUMBER_MASK); + tempreg |= ((RequestNumber - 1) << DMAMUX_REQ_NUMBER_Pos); + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_REQ_NUMBER_MASK); + tempreg |= ((RequestNumber - 1) << DMAMUX_REQ_NUMBER_Pos); + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } +} + +/** +*\*\name DMAMUX_GetSyncRequestNumber. +*\*\fun Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\return Between Min_Data = 1 and Max_Data = 32 +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +uint32_t DMAMUX_GetSyncRequestNumber(DMAMUX_ID DMAMUXx, uint32_t Channel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + + return (uint32_t)(((tempreg & DMAMUX_REQ_NUMBER_MASK) >> DMAMUX_REQ_NUMBER_Pos) + 1); +} + +/** +*\*\name DMAMUX_SetSyncPolarity. +*\*\fun Set the polarity of the signal on which the DMA request is synchronized. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param Polarity (The input parameters must be the following values). +*\*\ - DMAMUX_SYNC_NO_EVENT +*\*\ - DMAMUX_SYNC_POL_RISING +*\*\ - DMAMUX_SYNC_POL_FALLING +*\*\ - DMAMUX_SYNC_POL_RISING_FALLING +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_SetSyncPolarity(DMAMUX_ID DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_SYNC_POL_MASK); + tempreg |= (Polarity); + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + tempreg &= (~DMAMUX_SYNC_POL_MASK); + tempreg |= (Polarity); + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL = tempreg; + } +} + +/** +*\*\name DMAMUX_GetSyncPolarity. +*\*\fun Get the polarity of the signal on which the DMA request is synchronized. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\return Returned value can be one of the following values: +*\*\ - DMAMUX_SYNC_NO_EVENT +*\*\ - DMAMUX_SYNC_POL_RISING +*\*\ - DMAMUX_SYNC_POL_FALLING +*\*\ - DMAMUX_SYNC_POL_RISING_FALLING +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +uint32_t DMAMUX_GetSyncPolarity(DMAMUX_ID DMAMUXx, uint32_t Channel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + else + { + tempreg = ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL; + } + + return (uint32_t)(tempreg & DMAMUX_SYNC_POL_MASK); +} + +/** +*\*\name DMAMUX_EnableEventGeneration. +*\*\fun Enable or disable the Event Generation on DMAMUX channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_EnableEventGeneration(DMAMUX_ID DMAMUXx, uint32_t Channel, FunctionalState Cmd) +{ + if(DMAMUXx == DMAMUX1_ID) + { + if(Cmd == ENABLE) + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL |= DMAMUX_EVENT_GEN_MASK; + } + else + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL &= (~DMAMUX_EVENT_GEN_MASK); + } + } + else + { + if(Cmd == ENABLE) + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL |= DMAMUX_EVENT_GEN_MASK; + } + else + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL &= (~DMAMUX_EVENT_GEN_MASK); + } + } +} + +/** +*\*\name DMAMUX_EnableSync. +*\*\fun Enable or disable the synchronization mode on DMAMUX channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_EnableSync(DMAMUX_ID DMAMUXx, uint32_t Channel, FunctionalState Cmd) +{ + if(DMAMUXx == DMAMUX1_ID) + { + if(Cmd == ENABLE) + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL |= DMAMUX_SYN_ENABLE_MASK; + } + else + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL &= (~DMAMUX_SYN_ENABLE_MASK); + } + } + else + { + if(Cmd == ENABLE) + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL |= DMAMUX_SYN_ENABLE_MASK; + } + else + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL &= (~DMAMUX_SYN_ENABLE_MASK); + } + } +} + +/** +*\*\name DMAMUX_EnableRequestGen. +*\*\fun Enable or disable the Request Generator. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +void DMAMUX_EnableRequestGen(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, FunctionalState Cmd) +{ + if(DMAMUXx == DMAMUX1_ID) + { + if(Cmd == ENABLE) + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG |= DMAMUX_GEN_ENABLE_MASK; + } + else + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG &= (~DMAMUX_GEN_ENABLE_MASK); + } + } + else + { + if(Cmd == ENABLE) + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG |= DMAMUX_GEN_ENABLE_MASK; + } + else + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG &= (~DMAMUX_GEN_ENABLE_MASK); + } + } +} + +/** +*\*\name DMAMUX_SetRequestGenPolarity. +*\*\fun Set the polarity of the signal on which the DMA request is generated. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\param Polarity : +*\*\ - DMAMUX_REQ_GEN_NO_EVENT +*\*\ - DMAMUX_REQ_GEN_POL_RISING +*\*\ - DMAMUX_REQ_GEN_POL_FALLING +*\*\ - DMAMUX_REQ_GEN_POL_RISING_FALLING +*\*\return none +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +void DMAMUX_SetRequestGenPolarity(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + tempreg &= (~DMAMUX_REQ_GEN_POL_MASK); + tempreg |= (Polarity); + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG = tempreg; + } + else + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + tempreg &= (~DMAMUX_REQ_GEN_POL_MASK); + tempreg |= (Polarity); + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG = tempreg; + } +} + +/** +*\*\name DMAMUX_GetRequestGenPolarity. +*\*\fun Get the polarity of the signal on which the DMA request is generated.. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\return Returned value can be one of the following values: +*\*\ - DMAMUX_REQ_GEN_NO_EVENT +*\*\ - DMAMUX_REQ_GEN_POL_RISING +*\*\ - DMAMUX_REQ_GEN_POL_FALLING +*\*\ - DMAMUX_REQ_GEN_POL_RISING_FALLING +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +uint32_t DMAMUX_GetRequestGenPolarity(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + } + else + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + } + + return (uint32_t)(tempreg & DMAMUX_REQ_GEN_POL_MASK); +} + +/** +*\*\name DMAMUX_SetGenRequestNumber. +*\*\fun Set the number of DMA request that will be autorized after a generation event. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\param RequestNumber This parameter must be a value between Min_Data = 1 and Max_Data = 32: +*\*\return none +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +void DMAMUX_SetGenRequestNumber(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNumber) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * RequestGenChannel)))->CHCFG; + tempreg &= (~DMAMUX_REQ_GEN_NUMBER_MASK); + tempreg |= ((RequestNumber - 1) << DMAMUX_REQ_GEN_NUMBER_Pos); + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * RequestGenChannel)))->CHCFG = tempreg; + } + else + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * RequestGenChannel)))->CHCFG; + tempreg &= (~DMAMUX_REQ_GEN_NUMBER_MASK); + tempreg |= ((RequestNumber - 1) << DMAMUX_REQ_GEN_NUMBER_Pos); + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * RequestGenChannel)))->CHCFG = tempreg; + } +} + +/** +*\*\name DMAMUX_GetGenRequestNumber. +*\*\fun Get the number of DMA request that will be autorized after a generation event. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\return Between Min_Data = 1 and Max_Data = 32 +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +uint32_t DMAMUX_GetGenRequestNumber(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * RequestGenChannel)))->CHCFG; + } + else + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * RequestGenChannel)))->CHCFG; + } + + return (uint32_t)(((tempreg & DMAMUX_REQ_GEN_NUMBER_MASK) >> DMAMUX_REQ_GEN_NUMBER_Pos) + 1); +} + +/** +*\*\name DMAMUX_SetRequestSignalID. +*\*\fun Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\param RequestSignalID (The input parameters must be the following values): +*\*\ - DMAMUX1_REQ_GEN_DMAMUX1_EVT0_EVT7 +*\*\ - DMAMUX1_REQ_GEN_DMAMUX1_EVT8_EVT5 +*\*\ - DMAMUX1_REQ_GEN_DMAMUX1_EVT16_EVT23 +*\*\ - DMAMUX1_REQ_GEN_LPTIM4_OUT +*\*\ - DMAMUX1_REQ_GEN_LPTIM3_OUT +*\*\ - DMAMUX1_REQ_GEN_LPTIM2_OUT +*\*\ - DMAMUX1_REQ_GEN_LPTIM1_OUT +*\*\ - DMAMUX1_REQ_GEN_EXTI0 +*\*\ - DMAMUX1_REQ_GEN_CANFD1_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD2_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD3_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD4_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD5_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD6_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD7_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD8_INT0 +*\*\ - DMAMUX1_REQ_GEN_LPTIM5_OUT +*\*\ - DMAMUX1_REQ_GEN_ESC_INT +*\*\ - DMAMUX1_REQ_GEN_CANFD1_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD2_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD3_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD4_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD5_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD6_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD7_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD8_INT1 +*\*\ - DMAMUX2_DMA1_CH0_TC_INT +*\*\ - DMAMUX2_DMA1_CH1_TC_INT +*\*\ - DMAMUX2_DMA1_CH2_TC_INT +*\*\ - DMAMUX2_DMA1_CH3_TC_INT +*\*\ - DMAMUX2_DMA1_CH4_TC_INT +*\*\ - DMAMUX2_DMA1_CH5_TC_INT +*\*\ - DMAMUX2_DMA1_CH6_TC_INT +*\*\ - DMAMUX2_DMA1_CH7_TC_INT +*\*\ - DMAMUX2_DMA2_CH0_TC_INT +*\*\ - DMAMUX2_DMA2_CH1_TC_INT +*\*\ - DMAMUX2_DMA2_CH2_TC_INT +*\*\ - DMAMUX2_DMA2_CH3_TC_INT +*\*\ - DMAMUX2_DMA2_CH4_TC_INT +*\*\ - DMAMUX2_DMA2_CH5_TC_INT +*\*\ - DMAMUX2_DMA2_CH6_TC_INT +*\*\ - DMAMUX2_DMA2_CH7_TC_INT +*\*\ - DMAMUX2_DMA3_CH0_TC_INT +*\*\ - DMAMUX2_DMA3_CH1_TC_INT +*\*\ - DMAMUX2_DMA3_CH2_TC_INT +*\*\ - DMAMUX2_DMA3_CH3_TC_INT +*\*\ - DMAMUX2_DMA3_CH4_TC_INT +*\*\ - DMAMUX2_DMA3_CH5_TC_INT +*\*\ - DMAMUX2_DMA3_CH6_TC_INT +*\*\ - DMAMUX2_DMA3_CH7_TC_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_LCDC_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_GPU_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_JEPG_SGDMA_H2P_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_JEPG_SGDMA_P2H_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_MIPI_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_USB1_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_USB2_INT +*\*\ - DMAMUX2_REQ_GEN_SDMMC1_INT +*\*\ - DMAMUX2_REQ_GEN_SDMMC2_INT +*\*\ - DMAMUX2_REQ_GEN_DVP1_INT +*\*\ - DMAMUX2_REQ_GEN_DVP2_INT +*\*\ - DMAMUX2_REQ_GEN_EHT1_INT +*\*\ - DMAMUX2_REQ_GEN_EHT2_INT +*\*\ - DMAMUX2_REQ_GEN_SDPU_INT +*\*\return none +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +void DMAMUX_SetRequestSignalID(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + tempreg &= (~DMAMUX_REQ_GEN_SIG_ID_MASK); + tempreg |= (RequestSignalID); + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG = tempreg; + } + else + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + tempreg &= (~DMAMUX_REQ_GEN_SIG_ID_MASK); + tempreg |= (RequestSignalID); + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG = tempreg; + } +} + +/** +*\*\name DMAMUX_GetRequestSignalID. +*\*\fun Get DMAMUX external Request Signal ID set on DMAMUX Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\return Returned value can be one of the following values: +*\*\ - DMAMUX1_REQ_GEN_DMAMUX1_EVT0_EVT7 +*\*\ - DMAMUX1_REQ_GEN_DMAMUX1_EVT8_EVT5 +*\*\ - DMAMUX1_REQ_GEN_DMAMUX1_EVT16_EVT23 +*\*\ - DMAMUX1_REQ_GEN_LPTIM4_OUT +*\*\ - DMAMUX1_REQ_GEN_LPTIM3_OUT +*\*\ - DMAMUX1_REQ_GEN_LPTIM2_OUT +*\*\ - DMAMUX1_REQ_GEN_LPTIM1_OUT +*\*\ - DMAMUX1_REQ_GEN_EXTI0 +*\*\ - DMAMUX1_REQ_GEN_CANFD1_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD2_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD3_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD4_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD5_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD6_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD7_INT0 +*\*\ - DMAMUX1_REQ_GEN_CANFD8_INT0 +*\*\ - DMAMUX1_REQ_GEN_LPTIM5_OUT +*\*\ - DMAMUX1_REQ_GEN_ESC_INT +*\*\ - DMAMUX1_REQ_GEN_CANFD1_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD2_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD3_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD4_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD5_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD6_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD7_INT1 +*\*\ - DMAMUX1_REQ_GEN_CANFD8_INT1 +*\*\ - DMAMUX2_DMA1_CH0_TC_INT +*\*\ - DMAMUX2_DMA1_CH1_TC_INT +*\*\ - DMAMUX2_DMA1_CH2_TC_INT +*\*\ - DMAMUX2_DMA1_CH3_TC_INT +*\*\ - DMAMUX2_DMA1_CH4_TC_INT +*\*\ - DMAMUX2_DMA1_CH5_TC_INT +*\*\ - DMAMUX2_DMA1_CH6_TC_INT +*\*\ - DMAMUX2_DMA1_CH7_TC_INT +*\*\ - DMAMUX2_DMA2_CH0_TC_INT +*\*\ - DMAMUX2_DMA2_CH1_TC_INT +*\*\ - DMAMUX2_DMA2_CH2_TC_INT +*\*\ - DMAMUX2_DMA2_CH3_TC_INT +*\*\ - DMAMUX2_DMA2_CH4_TC_INT +*\*\ - DMAMUX2_DMA2_CH5_TC_INT +*\*\ - DMAMUX2_DMA2_CH6_TC_INT +*\*\ - DMAMUX2_DMA2_CH7_TC_INT +*\*\ - DMAMUX2_DMA3_CH0_TC_INT +*\*\ - DMAMUX2_DMA3_CH1_TC_INT +*\*\ - DMAMUX2_DMA3_CH2_TC_INT +*\*\ - DMAMUX2_DMA3_CH3_TC_INT +*\*\ - DMAMUX2_DMA3_CH4_TC_INT +*\*\ - DMAMUX2_DMA3_CH5_TC_INT +*\*\ - DMAMUX2_DMA3_CH6_TC_INT +*\*\ - DMAMUX2_DMA3_CH7_TC_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_LCDC_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_GPU_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_JEPG_SGDMA_H2P_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_JEPG_SGDMA_P2H_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_MIPI_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_USB1_INT +*\*\ - DMAMUX2_REQ_GEN_DMAMUX2_USB2_INT +*\*\ - DMAMUX2_REQ_GEN_SDMMC1_INT +*\*\ - DMAMUX2_REQ_GEN_SDMMC2_INT +*\*\ - DMAMUX2_REQ_GEN_DVP1_INT +*\*\ - DMAMUX2_REQ_GEN_DVP2_INT +*\*\ - DMAMUX2_REQ_GEN_EHT1_INT +*\*\ - DMAMUX2_REQ_GEN_EHT2_INT +*\*\ - DMAMUX2_REQ_GEN_SDPU_INT +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +uint32_t DMAMUX_GetRequestSignalID(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + } + else + { + tempreg = ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG; + } + + return (uint32_t)(tempreg & DMAMUX_REQ_GEN_SIG_ID_MASK); +} + +/** +*\*\name DMAMUX_GetSynOverrunStatus. +*\*\fun Get Synchronization Event Overrun Flag of Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +FlagStatus DMAMUX_GetSynOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t Channel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_ChannelStatus_TypeDef *)(DMAMUX1_BASE + DMAMUX_CH_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (Channel))))->STS; + } + else + { + tempreg = ((DMAMUX_ChannelStatus_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_CH_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (Channel))))->STS; + } + + return ((tempreg & (1 << Channel)) != 0U) ? SET : RESET; +} + + +/** +*\*\name DMAMUX_GetTrigOverrunStatus. +*\*\fun Get Request Generator x Trigger Event Overrun Flag. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +FlagStatus DMAMUX_GetTrigOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t tempreg; + + if(DMAMUXx == DMAMUX1_ID) + { + tempreg = ((DMAMUX_RequestGenStatus_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->RGSTS; + } + else + { + tempreg = ((DMAMUX_RequestGenStatus_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->RGSTS; + } + + return ((tempreg & (1 << RequestGenChannel)) != 0U) ? SET : RESET; +} + + +/** +*\*\name DMAMUX_ClearSynOverrunStatus. +*\*\fun Clear Synchronization Event Overrun Flag of Channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_ClearSynOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t Channel) +{ + if(DMAMUXx == DMAMUX1_ID) + { + ((DMAMUX_ChannelStatus_TypeDef *)(DMAMUX1_BASE + DMAMUX_CH_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (Channel))))->STS |= (uint32_t)(1 << Channel); + } + else + { + ((DMAMUX_ChannelStatus_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_CH_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (Channel))))->STS |= (uint32_t)(1 << Channel);; + } +} + + +/** +*\*\name DMAMUX_ClearTrigOverrunStatus. +*\*\fun Clear Request Generator x Trigger Event Overrun Flag. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\return none: +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +void DMAMUX_ClearTrigOverrunStatus(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel) +{ + if(DMAMUXx == DMAMUX1_ID) + { + ((DMAMUX_RequestGenStatus_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->RGCLR |= (uint32_t)(1 << RequestGenChannel); + } + else + { + ((DMAMUX_RequestGenStatus_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_STATUS_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->RGCLR |= (uint32_t)(1 << RequestGenChannel);; + } +} + + +/** +*\*\name DMAMUX_EnableSynEventOverrunInt. +*\*\fun Enable or disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param Channel (The input parameters must be the following values): +*\*\ - DMAMUX_CHANNEL_0 +*\*\ - DMAMUX_CHANNEL_1 +*\*\ - DMAMUX_CHANNEL_2 +*\*\ - DMAMUX_CHANNEL_3 +*\*\ - DMAMUX_CHANNEL_4 +*\*\ - DMAMUX_CHANNEL_5 +*\*\ - DMAMUX_CHANNEL_6 +*\*\ - DMAMUX_CHANNEL_7 +*\*\ - DMAMUX_CHANNEL_8 +*\*\ - DMAMUX_CHANNEL_9 +*\*\ - DMAMUX_CHANNEL_10 +*\*\ - DMAMUX_CHANNEL_11 +*\*\ - DMAMUX_CHANNEL_12 +*\*\ - DMAMUX_CHANNEL_13 +*\*\ - DMAMUX_CHANNEL_14 +*\*\ - DMAMUX_CHANNEL_15 +*\*\ - DMAMUX_CHANNEL_16 +*\*\ - DMAMUX_CHANNEL_17 +*\*\ - DMAMUX_CHANNEL_18 +*\*\ - DMAMUX_CHANNEL_19 +*\*\ - DMAMUX_CHANNEL_20 +*\*\ - DMAMUX_CHANNEL_21 +*\*\ - DMAMUX_CHANNEL_22 +*\*\ - DMAMUX_CHANNEL_23 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If DMAMUXx is DMAMUX2_ID, the maximum value of the Channel is DMAMUX_CHANNEL_15 +**/ +void DMAMUX_EnableSynEventOverrunInt(DMAMUX_ID DMAMUXx, uint32_t Channel, FunctionalState Cmd) +{ + if(DMAMUXx == DMAMUX1_ID) + { + if(Cmd == ENABLE) + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL |= DMAMUX_SYNOVERRUN_INTEN_MASK; + } + else + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX1_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL &= (~DMAMUX_SYNOVERRUN_INTEN_MASK); + } + } + else + { + if(Cmd == ENABLE) + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL |= DMAMUX_SYNOVERRUN_INTEN_MASK; + } + else + { + ((DMAMUX_Channel_TypeDef *)(DMAMUX2_MDMA_BASE + (DMAMUX_CHCTRL_SIZE * (Channel))))->CHCTRL &= (~DMAMUX_SYNOVERRUN_INTEN_MASK); + } + } +} + +/** +*\*\name DMAMUX_EnableTrigOverrunInt. +*\*\fun Enable or disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. +*\*\param DMAMUXx (The input parameters must be the following values): +*\*\ - DMAMUX1_ID +*\*\ - DMAMUX2_ID +*\*\param RequestGenChannel (The input parameters must be the following values): +*\*\ - DMAMUX_REQ_GEN_0 +*\*\ - DMAMUX_REQ_GEN_1 +*\*\ - DMAMUX_REQ_GEN_2 +*\*\ - DMAMUX_REQ_GEN_3 +*\*\ - DMAMUX_REQ_GEN_4 +*\*\ - DMAMUX_REQ_GEN_5 +*\*\ - DMAMUX_REQ_GEN_6 +*\*\ - DMAMUX_REQ_GEN_7 +*\*\ - DMAMUX_REQ_GEN_8 +*\*\ - DMAMUX_REQ_GEN_9 +*\*\ - DMAMUX_REQ_GEN_10 +*\*\ - DMAMUX_REQ_GEN_11 +*\*\ - DMAMUX_REQ_GEN_12 +*\*\ - DMAMUX_REQ_GEN_13 +*\*\ - DMAMUX_REQ_GEN_14 +*\*\ - DMAMUX_REQ_GEN_15 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If DMAMUXx is DMAMUX1_ID, the maximum value of the RequestGenChannel is DMAMUX_REQ_GEN_7 +**/ +void DMAMUX_EnableTrigOverrunInt(DMAMUX_ID DMAMUXx, uint32_t RequestGenChannel, FunctionalState Cmd) +{ + if(DMAMUXx == DMAMUX1_ID) + { + if(Cmd == ENABLE) + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG |= DMAMUX_TRIGOVERRUN_INTEN_MASK; + } + else + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX1_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG &= (~DMAMUX_TRIGOVERRUN_INTEN_MASK); + } + } + else + { + if(Cmd == ENABLE) + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG |= DMAMUX_TRIGOVERRUN_INTEN_MASK; + } + else + { + ((DMAMUX_RequestGen_TypeDef *)(DMAMUX2_MDMA_BASE + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_CHCTRL_SIZE * (RequestGenChannel))))->CHCFG &= (~DMAMUX_TRIGOVERRUN_INTEN_MASK); + } + } +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsi.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsi.c new file mode 100644 index 0000000000..2b89310822 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsi.c @@ -0,0 +1,1620 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dsi.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_dsi.h" +#include "stdio.h" + + +static DSI_StateTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, DSI_PKTCtrlTypeDef PacketCtrl); + +/** +*\*\name DSI_EnableWrapper. +*\*\fun Enable DSI Wrapper. +*\*\param hdsi: dsi host instance. +*\*\param cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSI_EnableWrapper(DSI_HandleTypeDef *hdsi, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + hdsi->InstanceWrap->DSI_WRPCTRL &= ~DSI_WRPCTRL_TRIGREQ; + } + else + { + hdsi->InstanceWrap->DSI_WRPCTRL |= DSI_WRPCTRL_TRIGREQ; + } +} + +/** +*\*\name DSI_Disable. +*\*\fun Disable DSI. +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +void DSI_Disable(DSI_HandleTypeDef *hdsi) +{ + hdsi->Instance->DSI_NUMLANES = DSI_REGISTER_MASK; +} + +/** +*\*\name DSI_EnableClockLane. +*\*\fun Enable or Disable DSI clock lane. +*\*\param hdsi: dsi host instance. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSI_EnableClockLane(DSI_HandleTypeDef *hdsi, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + hdsi->Instance->DSI_CLKLANEN = DSI_CLKLANEN_CLKLANEN; + } + else + { + hdsi->Instance->DSI_CLKLANEN &= ~DSI_CLKLANEN_CLKLANEN; + } +} + +/** +*\*\name DSI_EnableDataLane. +*\*\fun Configure DSI data lane number. +*\*\param hdsi: dsi host instance. +*\*\param datalinenum : +*\*\ - DSI_ONE_DATALANE_ENABLE +*\*\ - DSI_TWO_DATALANES_ENABLE +*\*\ - DSI_THREE_DATALANES_ENABLE +*\*\ - DSI_FOUR_DATALANES_ENABLE +*\*\return None. +**/ +void DSI_ConfigDataLaneNum(DSI_HandleTypeDef *hdsi, uint32_t datalinenum) +{ + hdsi->Instance->DSI_DATLANEN = datalinenum; +} + +/** +*\*\name DSI_SetVCID. +*\*\fun Configure DSI virtual channel ID. +*\*\param hdsi: dsi host instance. +*\*\param channel : +*\*\return None. +**/ +void DSI_SetVCID(DSI_HandleTypeDef *hdsi, uint32_t channel) +{ + hdsi->Instance->VID_VC = channel; +} + +/** +*\*\name DSI_CofigWrapULPSDL. +*\*\fun Configure DSI wrapper data lane number. +*\*\param hdsi: dsi host instance. +*\*\param datalinenum : +*\*\ - DSI_ULPS_ONE_DATA_LANE +*\*\ - DSI_ULPS_TWO_DATA_LANES +*\*\ - DSI_ULPS_THREE_DATA_LANES +*\*\ - DSI_ULPS_FOUR_DATA_LANES +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSI_CofigWrapULPSDL(DSI_HandleTypeDef *hdsi, uint32_t datalinenum, FunctionalState Cmd) +{ + uint32_t temp; + temp = hdsi->InstanceWrap->DSI_WRPCTRL; + temp &= ~DSI_WRPCTRL_ULPSDLEN; + if(Cmd != DISABLE) + { + temp |= datalinenum << DSI_WRPCTRL_ULPSDLEN_POS; + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } + else + { + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } +} + +/** +*\*\name DSI_EnableWrapULPSDL. +*\*\fun Configure DSI wrapper data lane number. +*\*\param hdsi: dsi host instance. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSI_EnableWrapULPSCL(DSI_HandleTypeDef *hdsi, FunctionalState Cmd) +{ + uint32_t temp; + + temp = hdsi->InstanceWrap->DSI_WRPCTRL; + temp &= ~DSI_WRPCTRL_ULPSCLEN; + if(Cmd != DISABLE) + { + temp |= DSI_WRPCTRL_ULPSCLEN; + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } + else + { + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } +} + +/** +*\*\name DSI_DisableSkewCal. +*\*\fun Disable DSI skew calibration . +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +void DSI_DisableSkewCal(DSI_HandleTypeDef *hdsi) +{ + hdsi->Instance->DSI_SKEWCALINE = DSI_REGISTER_MASK; +} + +/** +*\*\name DSI_DeInit. +*\*\fun De-initializes the DSI peripheral registers to their default reset +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +DSI_StateTypeDef DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if (hdsi == NULL) + { + return DSI_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = DSI_BUSY; + + /* Disable the DSI wrapper: write bit9 = 0 NEED TBD */ + DSI_EnableWrapper(hdsi, ENABLE); + + /* Disable the DSI host */ + DSI_Disable(hdsi); + + /* D-PHY clock lane and data lane disable */ + DSI_EnableClockLane(hdsi, DISABLE); + + /* Disable the skewcal*/ + DSI_DisableSkewCal(hdsi); + + /* Initialize the error code */ + hdsi->ErrorCode = DSI_NO_ERRORS; + + /* Initialize the DSI state*/ + hdsi->State = DSI_RESET; + + /* Release Lock */ + hdsi->Lock = DSI_UNLOCKED; + + return DSI_OK; +} + +/** +*\*\name DSI_InitHostWrap. +*\*\fun Initialize DSI host and wrapper . +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +void DSI_InitHostWrap(DSI_HandleTypeDef *hdsi) +{ + /* Base address of DSI Host/Wrapper registers to be set before calling De-Init */ + hdsi->Instance = DSI_HOST; + hdsi->InstanceWrap = DSI_HOST_WRAPPER; +} + +/** +*\*\name DSI_GetPHYStatus. +*\*\fun Get DSI PHY status. +*\*\param hdsi: dsi host instance. +*\*\return SET or RESET. +**/ +FlagStatus DSI_GetPHYStatus(DSI_HandleTypeDef *hdsi) +{ + FlagStatus bitstatus = RESET; + + hdsi->InstanceWrap->DSIPHY_PLLSTS = 1; + + if ((hdsi->InstanceWrap->DSIPHY_PLLSTS & DSIPHY_PLLSTS_PHYREADY) != DSIPHY_PLLSTS_PHYREADY) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +*\*\name DSI_InitHostWrap. +*\*\fun Initialize DSI PHY . +*\*\param hdsi: dsi host instance. +*\*\return DSI_StateTypeDef. +**/ +void DSI_InitPHY(DSI_HandleTypeDef *hdsi, DSI_PHY_InitTypeDef *PHY_InitParams) +{ + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + uint32_t tmp4 = 0; + uint32_t tmp5 = 0; + uint32_t tmp6 = 0; + uint32_t tmp7 = 0; + + // config wrap register 0x08: CFG_LN_SWAP_SEL + hdsi->InstanceWrap->DSIPHY_CTRL1 &= ~(DSIPHY_CTRL1_REFCKSEL | DSIPHY_CTRL1_EXTDCYCEL | DSIPHY_CTRL1_L4SEL | DSIPHY_CTRL1_L3SEL | DSIPHY_CTRL1_L2SEL | DSIPHY_CTRL1_L1SEL | DSIPHY_CTRL1_L0SEL); + tmp1 = ( PHY_InitParams->L4_Swap_Sel_Value << DSIPHY_CTRL1_L4SEL_POS); + tmp2 = ( PHY_InitParams->L3_Swap_Sel_Value << DSIPHY_CTRL1_L3SEL_POS); + tmp3 = ( PHY_InitParams->L2_Swap_Sel_Value << DSIPHY_CTRL1_L2SEL_POS); + tmp4 = ( PHY_InitParams->L1_Swap_Sel_Value << DSIPHY_CTRL1_L1SEL_POS); + tmp5 = ( PHY_InitParams->L0_Swap_Sel_Value << DSIPHY_CTRL1_L0SEL_POS); + + // config wrap register 0x08 + tmp6 = ( PHY_InitParams->RefCLK_In_Sel << DSIPHY_CTRL1_REFCKSEL_POS); + tmp7 = ( PHY_InitParams->EXTD_CYCLE_SEL << DSIPHY_CTRL1_EXTDCYCEL_POS); + hdsi->InstanceWrap->DSIPHY_CTRL1 |= (tmp1 | tmp2 | tmp3 | tmp4 | tmp5 | tmp6 | tmp7); + + // config wrap register 0x0c + tmp1 = ( PHY_InitParams->DLANE_HS_PER_TIME << DSIPHY_CTRL2_DLPRET_POS); + tmp2 = ( PHY_InitParams->DLANE_HS_ZERO_TIME << DSIPHY_CTRL2_DLZEROT_POS); + tmp3 = ( PHY_InitParams->DLANE_HS_TRAIL_TIME << DSIPHY_CTRL2_DLTRAT_POS); + tmp4 = ( PHY_InitParams->CLANE_HS_PER_TIME << DSIPHY_CTRL2_CLPRET_POS); + hdsi->InstanceWrap->DSIPHY_CTRL2 = (tmp1 | tmp2 | tmp3 | tmp4); + + // config wrap register 0x10 + tmp1 = ( PHY_InitParams->CLANE_HS_ZERO_TIME << DSIPHY_CTRL3_CLZEROT_POS); + tmp2 = ( PHY_InitParams->CLANE_HS_TRAIL_TIME << DSIPHY_CTRL3_CLTRLT_POS); + tmp3 = ( PHY_InitParams->CLANE_HS_CLK_PRE_TIME << DSIPHY_CTRL3_CLCLKPRET_POS); + tmp4 = ( PHY_InitParams->CLANE_HS_CLK_POST_TIME << DSIPHY_CTRL3_CLCLKPOST_POS); + hdsi->InstanceWrap->DSIPHY_CTRL3 = (tmp1 | tmp2 | tmp3 | tmp4); + + // config wrap register 0x64 + tmp1 = ( PHY_InitParams->PLL_FBK_FRA7_0 << 0); + tmp2 = ( PHY_InitParams->PLL_FBK_FRA15_8 << 8); + tmp3 = ( PHY_InitParams->PLL_FBK_FRA23_16 << 16); + hdsi->InstanceWrap->DSIPHY_PLLCTRL1 = (tmp1 | tmp2 | tmp3 ); + + // config wrap register 0x68 + tmp1 = ( PHY_InitParams->PLL_SSC_DELTA7_0 << DSIPHY_PLLCTRL2_SSCAMPOP_POS ); + tmp2 = ( PHY_InitParams->PLL_SSC_DELTA15_8 << 20 ); + tmp3 = ( PHY_InitParams->PLL_SSC_DELTA17_16 << 28 ); + hdsi->InstanceWrap->DSIPHY_PLLCTRL2 = (tmp1 | tmp2 | tmp3 |(PHY_InitParams->PLL_PRE_DIV << DSIPHY_PLLCTRL2_PREDIV_POS) | (PHY_InitParams->PLL_FBK_INT << DSIPHY_PLLCTRL2_FBKINT_POS)); + + // config wrap register 0x6c + tmp1 = ( PHY_InitParams->PLL_SSC_DELTA_INIT7_0 << 0 ); + tmp2 = ( PHY_InitParams->PLL_SSC_DELTA_INIT15_8 << 8 ); + tmp3 = ( PHY_InitParams->PLL_SSC_DELTA_INIT17_16 << 16 ); + tmp4 = ( PHY_InitParams->PLL_SSC_PRD7_0 << DSIPHY_PLLCTRL3_SSCPRD_POS ); + tmp5 = ( PHY_InitParams->PLL_SSC_PRD9_8 << 26 ); + hdsi->InstanceWrap->DSIPHY_PLLCTRL3 = (tmp5 | tmp4 | tmp3 | tmp2 | tmp1 ); + + // config wrap register 0x70 and 0x74, added default lane impedance, only for high speed TX, LPDT does not use HS TX + hdsi->InstanceWrap->DSIPHY_PLLCTRL4 |= 0x21084210; + hdsi->InstanceWrap->DSIPHY_PLLCTRL5 |= 0x84210; +} + +/** +*\*\name DSI_Start. +*\*\fun Initialize DSI PHY . +*\*\param hdsi: dsi host instance. +*\*\return DSI_StateTypeDef. +**/ +DSI_StateTypeDef DSI_Start(DSI_HandleTypeDef *hdsi) +{ + uint32_t temp; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + /* Enable the DSI host */ + // enable clock lane + DSI_EnableClockLane(hdsi, ENABLE); + + /* Request on Data Lanes */ + if(hdsi->HostInit.NumOfLanes == DSI_ONE_DATA_LANE) + { + temp = DSI_ONE_DATALANE_ENABLE; + } + else if(hdsi->HostInit.NumOfLanes == DSI_TWO_DATA_LANES) + { + temp = DSI_TWO_DATALANES_ENABLE; + } + else if(hdsi->HostInit.NumOfLanes == DSI_THREE_DATA_LANES) + { + temp = DSI_THREE_DATALANES_ENABLE; + } + else if(hdsi->HostInit.NumOfLanes == DSI_FOUR_DATA_LANES) + { + temp = DSI_FOUR_DATALANES_ENABLE; + } + // enable data lane + DSI_ConfigDataLaneNum(hdsi, temp); + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + return DSI_OK; +} + +/** +*\*\name DSI_EnterULPSData. +*\*\fun Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running(only data lanes are in ULPM) +*\*\param hdsi: dsi host instance. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return DSI_StateTypeDef. +**/ +DSI_StateTypeDef DSI_EnterULPSData(DSI_HandleTypeDef *hdsi, FunctionalState Cmd) +{ + uint32_t temp; + uint32_t timeout = DSI_TIME_OUT_VALUE; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* ULPS Request on Data Lanes */ + if(hdsi->HostInit.NumOfLanes == DSI_ONE_DATA_LANE) + { + temp = DSI_ULPS_ONE_DATA_LANE; + } + else if(hdsi->HostInit.NumOfLanes == DSI_TWO_DATA_LANES) + { + temp = DSI_ULPS_TWO_DATA_LANE; + } + else if(hdsi->HostInit.NumOfLanes == DSI_THREE_DATA_LANES) + { + temp = DSI_ULPS_THREE_DATA_LANE; + } + else if(hdsi->HostInit.NumOfLanes == DSI_FOUR_DATA_LANES) + { + temp = DSI_ULPS_FOUR_DATA_LANE; + } + DSI_CofigWrapULPSDL(hdsi, temp, ENABLE); + // wait data lane enter ULPS + while(((hdsi->InstanceWrap->DSI_WRPSTS & DSI_WRPCTRL_ULPSDLEN) != temp) && timeout--) + { + } + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + return DSI_OK; +} + +/** +*\*\name DSI_EnterULPSClock. +*\*\fun Enter the ULPM (Ultra Low Power Mode) with the C-PHY PLL running (only clock lanes are in ULPM) +*\*\param hdsi: dsi host instance. +*\*\return DSI_StateTypeDef. +**/ +DSI_StateTypeDef DSI_EnterULPSClock(DSI_HandleTypeDef *hdsi) +{ + uint32_t timeout = DSI_TIME_OUT_VALUE; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* ULPS Request on Clock Lanes */ + DSI_EnableWrapULPSCL(hdsi, ENABLE); + + // wait clock lane enter ULPS + while(((hdsi->InstanceWrap->DSI_WRPSTS & DSI_WRPCTRL_ULPSCLEN) != DSI_WRPCTRL_ULPSCLEN) && timeout--) + { + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + return DSI_OK; +} + +/** +*\*\name DSI_ExitULPSClock. +*\*\fun Exit the ULPM (Ultra Low Power Mode) with the C-PHY PLL running (only clock lanes are in ULPM) +*\*\param hdsi: dsi host instance. +*\*\return DSI_StateTypeDef. +**/ +DSI_StateTypeDef DSI_ExitULPSClock(DSI_HandleTypeDef *hdsi) +{ + uint32_t timeout = DSI_TIME_OUT_VALUE; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* Exit ULPS on Clock Lanes */ + DSI_EnableWrapULPSCL(hdsi, DISABLE); + + // wait clock lane enter ULPS + while(((hdsi->InstanceWrap->DSI_WRPSTS & DSI_WRPCTRL_ULPSCLEN) != 0) && timeout--) + { + } + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + return DSI_OK; +} + +/** +*\*\name DSI_EnterULPS. +*\*\fun Enter the ULPM (Ultra Low Power Mode)(both data and clock lanes are in ULPM) +*\*\param hdsi: dsi host instance. +*\*\return DSI_StateTypeDef. +**/ +DSI_StateTypeDef DSI_EnterULPS(DSI_HandleTypeDef *hdsi) +{ + DSI_StateTypeDef result; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* ULPS Request on Clock Lanes */ + result = DSI_EnterULPSClock(hdsi); + + if(result != DSI_OK) + { + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + return result; + } + + /* ULPS Request on Data Lanes */ + result = DSI_EnterULPSData(hdsi, ENABLE); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return result; +} + +/** +*\*\name DSI_ExitULPS. +*\*\fun Exit the ULPM (Ultra Low Power Mode)(both data and clock lanes are in ULPM) +*\*\param hdsi: dsi host instance. +*\*\return DSI_StateTypeDef. +**/ +DSI_StateTypeDef DSI_ExitULPS(DSI_HandleTypeDef *hdsi) +{ + DSI_StateTypeDef result; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* Exit ULPS on Data Lanes */ + result = DSI_EnterULPSData(hdsi, DISABLE); + if(result != DSI_OK) + { + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + return result; + } + + /* Exit ULPS on Clock Lanes */ + result = DSI_ExitULPSClock(hdsi); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return DSI_OK; +} + +/** +*\*\name DSI_EnableWrapperISkewCal. +*\*\fun Enable or disable Wrapper Initial skew calibration. +*\*\param hdsi: dsi host instance. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSI_EnableWrapperISkewCal(DSI_HandleTypeDef *hdsi, FunctionalState Cmd) +{ + uint32_t temp; + temp = hdsi->InstanceWrap->DSI_WRPCTRL; + if(Cmd != DISABLE) + { + temp |= DSI_WRPCTRL_ISKEWCAL; + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } + else + { + temp &= ~DSI_WRPCTRL_ISKEWCAL; + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } +} + +/** +*\*\name DSI_EnableWrapperPSkewCal. +*\*\fun Enable or disable Wrapper Period skew calibration. +*\*\param hdsi: dsi host instance. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSI_EnableWrapperPSkewCal(DSI_HandleTypeDef *hdsi, FunctionalState Cmd) +{ + uint32_t temp; + temp = hdsi->InstanceWrap->DSI_WRPCTRL; + if(Cmd != DISABLE) + { + temp |= DSI_WRPCTRL_PSKEWCAL; + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } + else + { + temp &= ~DSI_WRPCTRL_PSKEWCAL; + hdsi->InstanceWrap->DSI_WRPCTRL = temp; + } +} + +/** +*\*\name DSI_EnableInitialSkewCali. +*\*\fun Enable Wrapper Initialize skew calibration. +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +DSI_StateTypeDef DSI_EnableInitialSkewCalib(DSI_HandleTypeDef *hdsi) +{ + uint32_t timeout = DSI_TIME_OUT_VALUE; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + // enable initial skew + DSI_EnableWrapperISkewCal(hdsi, ENABLE); + + // wait for status + while((((hdsi->InstanceWrap->DSI_WRPSTS) & DSI_WRPCTRL_ISKEWCAL) == 0) && timeout--) + { + } + // clear status : write 1 + hdsi->InstanceWrap->DSI_WRPSTS |= (DSI_WRPSTS_ISKEWCALDN); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + + return DSI_OK; +} + +/** +*\*\name DSI_EnableInitialSkewCali. +*\*\fun Enable Wrapper Period skew calibration. +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +DSI_StateTypeDef DSI_EnablePeriodSkewCali(DSI_HandleTypeDef *hdsi) +{ + uint32_t timeout = DSI_TIME_OUT_VALUE; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + // enable period skew + DSI_EnableWrapperPSkewCal(hdsi, ENABLE); + + // wait for status + while((((hdsi->InstanceWrap->DSI_WRPSTS) & DSI_WRPSTS_PSKEWCALDN) == 0) && timeout--) + { + } + + // clear status: write 1 + hdsi->InstanceWrap->DSI_WRPSTS |= (DSI_WRPSTS_PSKEWCALDN); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + + return DSI_OK; + +} + +/** +*\*\name DSI_EnableInitialSkewCali. +*\*\fun Enable Wrapper reset trigger. +*\*\param hdsi: dsi host instance. +*\*\return None. +**/ +DSI_StateTypeDef DSI_EnableResetTrigger(DSI_HandleTypeDef *hdsi) +{ + uint32_t timeout = DSI_TIME_OUT_VALUE; + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + // set reset trigger and enable reset trigger send + hdsi->InstanceWrap->DSI_WRPCTRL &= ~DSI_WRPCTRL_TRIGSEND; + hdsi->InstanceWrap->DSI_WRPCTRL |= DSI_WRPCTRL_TRIGREQ; + + // wait for status + while((((hdsi->InstanceWrap->DSI_WRPSTS) & DSI_WRPSTS_TRIGACK) == 0) && timeout--) + { + } + // clear status: write 1 + hdsi->InstanceWrap->DSI_WRPSTS |= (DSI_WRPSTS_TRIGACK); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + + return DSI_OK; +} + +/** +*\*\name DSI_Wrapper_ConfigInt +*\*\fun Enables or disables the specified DSI Wrapper's interrupts. +*\*\param hdsi: dsi host instance. +*\*\param DSI_IT +*\*\ - DSI_WRAPPER_INT_BLKERRIEN +*\*\ - DSI_WRAPPER_INT_SPERRIEN +*\*\ - DSI_WRAPPER_INT_OVERRIEN +*\*\ - DSI_WRAPPER_INT_UNDERRIEN +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DSI_Wrapper_ConfigInt(DSI_HandleTypeDef *hdsi, uint32_t DSI_IT, FunctionalState Cmd) +{ + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + hdsi->InstanceWrap->DSI_WRPCTRL |= (uint32_t)DSI_IT; + } + else + { + /* Disable the Interrupt sources */ + hdsi->InstanceWrap->DSI_WRPCTRL &= (uint32_t)(~DSI_IT); + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; +} + + +/** +*\*\name DSI_Wrapper_GetFlagStatus +*\*\fun Checks whether the specified LCDC flag is set or not. +*\*\param hdsi: dsi host instance. +*\*\param DSI_FLAG +*\*\ - DSI_WRAPPER_FLAG_ISKEWCALDN +*\*\ - DSI_WRAPPER_FLAG_PSKEWCALDN +*\*\ - DSI_WRAPPER_FLAG_TRIGACK +*\*\ - DSI_WRAPPER_FLAG_BLKERRIEN +*\*\ - DSI_WRAPPER_FLAG_SPERRIEN +*\*\ - DSI_WRAPPER_FLAG_OVERRIEN +*\*\ - DSI_WRAPPER_FLAG_UNDERRIEN +*\*\return The new state of DSI Wrapper FLAG (SET or RESET). +**/ +FlagStatus DSI_Wrapper_GetFlagStatus(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG) +{ + FlagStatus bitstatus; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if ((hdsi->InstanceWrap->DSI_WRPSTS & DSI_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return bitstatus; +} + +/** +*\*\name DSI_Wrapper_ClearFlag +*\*\fun Clears the DSI Wrapper's pending flags. +*\*\param hdsi: dsi host instance. +*\*\param DSI_FLAG +*\*\ - DSI_WRAPPER_FLAG_ISKEWCALDN +*\*\ - DSI_WRAPPER_FLAG_PSKEWCALDN +*\*\ - DSI_WRAPPER_FLAG_TRIGACK +*\*\ - DSI_WRAPPER_FLAG_BLKERRIEN +*\*\ - DSI_WRAPPER_FLAG_SPERRIEN +*\*\ - DSI_WRAPPER_FLAG_OVERRIEN +*\*\ - DSI_WRAPPER_FLAG_UNDERRIEN +*\*\return none. +**/ +void DSI_Wrapper_ClearFlag(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG) +{ + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* Clear the flags */ + hdsi->InstanceWrap->DSI_WRPSTS |= (uint32_t)(DSI_FLAG); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; +} + +/** +*\*\name DSI_Wrapper_GetIntStatus +*\*\fun Checks whether the specified DSI Wrapper's interrupt has occurred or not. +*\*\param hdsi: dsi host instance. +*\*\param DSI_IT +*\*\ - DSI_WRAPPER_INT_BLKERRIEN +*\*\ - DSI_WRAPPER_INT_SPERRIEN +*\*\ - DSI_WRAPPER_INT_OVERRIEN +*\*\ - DSI_WRAPPER_INT_UNDERRIEN +*\*\return The new state of DSI_IT (SET or RESET). +**/ +INTStatus DSI_Wrapper_GetIntStatus(DSI_HandleTypeDef *hdsi, uint32_t DSI_IT) +{ + INTStatus bitstatus; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if ((hdsi->InstanceWrap->DSI_WRPCTRL & DSI_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + if ((bitstatus != (uint32_t)RESET) && ((hdsi->InstanceWrap->DSI_WRPSTS & (DSI_IT >> 2)) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return bitstatus; +} + + +/** +*\*\name DSI_Init. +*\*\fun Initialize the dsi host according to the specified parameters in the DSI_HandleTypeDef. +*\*\param hdsi: dsi host instance. +*\*\return DSI_OK or DSI_ERROR. +**/ +DSI_StateTypeDef DSI_Init(DSI_HandleTypeDef *hdsi) +{ + uint32_t temp; + /* Check the LCDC peripheral state */ + if(hdsi == NULL) + { + return DSI_ERROR; + } + + /* Change CDC peripheral state */ + hdsi->State = DSI_BUSY; + + /************************ Set the DSI HOST BASE parameter ************************/ + temp = hdsi->Instance->DSI_DISBST; + temp &= ~(DSI_DISBST_DISBST); + temp |= hdsi->HostInit.BurstSel; + hdsi->Instance->DSI_DISBST = temp; + + temp = hdsi->Instance->DSI_AUTOINSERT_EOTP; + temp &= ~(DSI_AUTOINSERT_EOTP_AUTOINSEOTP); + temp |= hdsi->HostInit.AutoInsertEOTP; + hdsi->Instance->DSI_AUTOINSERT_EOTP = temp; + + temp = hdsi->Instance->DSI_DISRXCRCCHK; + temp &= ~(DSI_DISRXCRCCHK_DISRXCRCCHK); + temp |= hdsi->HostInit.DisRXCRC; + hdsi->Instance->DSI_DISRXCRCCHK = temp; + + temp = hdsi->Instance->DSI_TPRE; + temp &= ~(DSI_TPRE_TPRE<ClockInit.ClockBeforeHS << DSI_TPRE_TPRE_POS); + hdsi->Instance->DSI_TPRE = temp; + + temp = hdsi->Instance->DSI_TPOST; + temp &= ~(DSI_TPOST_TPOST<ClockInit.ClockHS2LP << DSI_TPOST_TPOST_POS); + hdsi->Instance->DSI_TPOST = temp; + + temp = hdsi->Instance->DSI_TXGAP; + temp &= ~(DSI_TXGAP_TXGAP<ClockInit.ClockLP2HS << DSI_TXGAP_TXGAP_POS); + hdsi->Instance->DSI_TXGAP = temp; + + temp = hdsi->Instance->DSI_TWAKEUP; + temp &= ~(DSI_TWAKEUP_TWAKEUP<ClockInit.ClockExitULPS << DSI_TWAKEUP_TWAKEUP_POS); + hdsi->Instance->DSI_TWAKEUP = temp; + + temp = hdsi->Instance->DSI_CONTHSCLK; + temp &= ~(DSI_CONTHSCLK_CONTHSCLK << DSI_CONTHSCLK_CONTHSCLK_POS); + temp |= (hdsi->ClockInit.ContinuousHSCLK << DSI_CONTHSCLK_CONTHSCLK_POS); + hdsi->Instance->DSI_CONTHSCLK = temp; + + /************************ Set DSI HOST SKEWCAL Parameter ************************/ + temp = hdsi->Instance->DSI_SKEWCALTIMI; + temp &= ~(DSI_SKEWCALTIMI_SKEWVALTIMI << DSI_SKEWCALTIMI_SKEWVALTIMI_POS); + temp |= (hdsi->SkewcalInit.ClockInitialSkewcal << DSI_SKEWCALTIMI_SKEWVALTIMI_POS); + hdsi->Instance->DSI_SKEWCALTIMI = temp; + + temp = hdsi->Instance->DSI_SKEWCALTIMP; + temp &= ~(DSI_SKEWCALTIMP_SKEWVALTIMP << DSI_SKEWCALTIMP_SKEWVALTIMP_POS); + temp |= (hdsi->SkewcalInit.ClockPeriodicSkewcal << DSI_SKEWCALTIMP_SKEWVALTIMP_POS); + hdsi->Instance->DSI_SKEWCALTIMP = temp; + + temp = hdsi->Instance->DSI_ALTCALTIM; + temp &= ~(DSI_ALTCALTIM_ALTCALTIM << DSI_ALTCALTIM_ALTCALTIM_POS); + temp |= (hdsi->SkewcalInit.ClockAlternateCal << DSI_ALTCALTIM_ALTCALTIM_POS); + hdsi->Instance->DSI_ALTCALTIM = temp; + + temp = hdsi->Instance->DSI_SKEWCALINE; + temp &= ~(DSI_SKEWCALINE_SKEWCALINE << DSI_SKEWCALINE_SKEWCALINE_POS); + temp |= (hdsi->SkewcalInit.LinePeriodicSkewcal << DSI_SKEWCALINE_SKEWCALINE_POS); + hdsi->Instance->DSI_SKEWCALINE = temp; + + /* Config the num_lanes to enable the host controller */ + temp = hdsi->Instance->DSI_NUMLANES; + temp &= ~(DSI_NUMLANES_NUMLANES << DSI_NUMLANES_NUMLANES_POS); + temp |= (hdsi->HostInit.NumOfLanes << DSI_NUMLANES_NUMLANES_POS); + hdsi->Instance->DSI_NUMLANES = temp; + + /* Initialize the error code */ + hdsi->ErrorCode = DSI_NO_ERRORS; + + /* Initialize the LCDC state*/ + hdsi->State = DSI_READY; + + return DSI_OK; +} + +/** +*\*\name DSI_ConfigVideoMode. +*\*\fun Select video mode and configure the corresponding parameters +*\*\param hdsi: dsi host instance. +*\*\param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains the DSI video mode configuration parameters +*\*\return DSI_OK or DSI_ERROR. +**/ +DSI_StateTypeDef DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + uint32_t temp; + + /* Check the LCDC peripheral state */ + if(hdsi == NULL || VidCfg == NULL) + { + return DSI_ERROR; + } + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /************************ Set DSI HOST VID IF ************************/ + temp = hdsi->Instance->VID_PIXPERPKT; + temp &= ~(VID_PIXPERPKT_PIXPERPKT << VID_PIXPERPKT_PIXPERPKT_POS); + temp |= (VidCfg->PixelsPerPacket << VID_PIXPERPKT_PIXPERPKT_POS); + hdsi->Instance->VID_PIXPERPKT = temp; + + temp = hdsi->Instance->VID_PIXPLDSIZ; + temp &= ~(VID_PIXPLDSIZ_PIXPLDSIZ << VID_PIXPLDSIZ_PIXPLDSIZ_POS); + temp |= (VidCfg->PixelPayloadSize << VID_PIXPLDSIZ_PIXPLDSIZ_POS); + hdsi->Instance->VID_PIXPLDSIZ = temp; + + temp = hdsi->Instance->VID_PIXALIGN; + temp &= ~(VID_PIXALIGN_PIXALIGN << VID_PIXALIGN_PIXALIGN_POS); + temp |= (VidCfg->PixelAlignment << VID_PIXALIGN_PIXALIGN_POS); + hdsi->Instance->VID_PIXALIGN = temp; + + temp = hdsi->Instance->VID_PIXFMT; + temp &= ~(VID_PIXFMT_PIXFMT << VID_PIXFMT_PIXFMT_POS); + temp |= (VidCfg->PixelFormat << VID_PIXFMT_PIXFMT_POS); + hdsi->Instance->VID_PIXFMT = temp; + + temp = hdsi->Instance->VID_VSYNCPOL; + temp &= ~(VID_VSYNCPOL_VSYNCPOL << VID_VSYNCPOL_VSYNCPOL_POS); + temp |= (VidCfg->VSPolarity << VID_VSYNCPOL_VSYNCPOL_POS); + hdsi->Instance->VID_VSYNCPOL = temp; + + temp = hdsi->Instance->VID_HSYNCPOL; + temp &= ~(VID_HSYNCPOL_HSYNCPOL << VID_HSYNCPOL_HSYNCPOL_POS); + temp |= (VidCfg->HSPolarity << VID_HSYNCPOL_HSYNCPOL_POS); + hdsi->Instance->VID_HSYNCPOL = temp; + + temp = hdsi->Instance->VID_VIDEOMOD; + temp &= ~(VID_VIDEOMOD_VIDEOMOD << VID_VIDEOMOD_VIDEOMOD_POS); + temp |= (VidCfg->Mode << VID_VIDEOMOD_VIDEOMOD_POS); + hdsi->Instance->VID_VIDEOMOD = temp; + + temp = hdsi->Instance->VID_OVERIDE; + temp &= ~(VID_OVERIDE_OVERIDE << VID_OVERIDE_OVERIDE_POS); + temp |= (VidCfg->Override << VID_OVERIDE_OVERIDE_POS); + hdsi->Instance->VID_OVERIDE = temp; + + /* Only Override = 1 need to program timing register, Otherwise, the reset value is maintained */ + if (VidCfg->Override == VID_OVERIDE_OVERIDE) + { + temp = hdsi->Instance->VID_HSA; + temp &= ~(VID_HSA_HSA << VID_HSA_HSA_POS); + temp |= (VidCfg->HorizontalSyncActive << VID_HSA_HSA_POS); + hdsi->Instance->VID_HSA = temp; + + temp = hdsi->Instance->VID_HBP; + temp &= ~(VID_HBP_HBP << VID_HBP_HBP_POS); + temp |= (VidCfg->HorizontalBackPorch << VID_HBP_HBP_POS); + hdsi->Instance->VID_HBP = temp; + + temp = hdsi->Instance->VID_HFP; + temp &= ~(VID_HFP_HFP << VID_HFP_HFP_POS); + temp |= (VidCfg->HorizontalFrontPorch << VID_HFP_HFP_POS); + hdsi->Instance->VID_HFP = temp; + + temp = hdsi->Instance->VID_VBP; + temp &= ~(VID_VBP_VBP << VID_VBP_VBP_POS); + temp |= (VidCfg->VerticalBackPorch << VID_VBP_VBP_POS); + hdsi->Instance->VID_VBP = temp; + + temp = hdsi->Instance->VID_VFP; + temp &= ~(VID_VFP_VFP << VID_VFP_VFP_POS); + temp |= (VidCfg->VerticalFrontPorch << VID_VFP_VFP_POS); + hdsi->Instance->VID_VFP = temp; + + temp = hdsi->Instance->VID_VACT; + temp &= ~(VID_VACT_VACT << VID_VACT_VACT_POS); + temp |= (VidCfg->VerticalActive << VID_VACT_VACT_POS); + hdsi->Instance->VID_VACT = temp; + } + + temp = hdsi->Instance->VID_STD; + temp &= ~(VID_STD_STD << VID_STD_STD_POS); + temp |= (VidCfg->DelayFromStart << VID_STD_STD_POS); + hdsi->Instance->VID_STD = temp; + + temp = hdsi->Instance->VID_PKTPERLINE; + temp &= ~(VID_PKTPERLINE_PKTPERLINE << VID_PKTPERLINE_PKTPERLINE_POS); + temp |= (VidCfg->PacketsPerLine << VID_PKTPERLINE_PKTPERLINE_POS); + hdsi->Instance->VID_PKTPERLINE = temp; + + temp = hdsi->Instance->VID_BLLPMOD; + temp &= ~(VID_BLLPMOD_BLLPMOD << VID_BLLPMOD_BLLPMOD_POS); + temp |= (VidCfg->BLLPMode << VID_BLLPMOD_BLLPMOD_POS); + hdsi->Instance->VID_BLLPMOD = temp; + + temp = hdsi->Instance->VID_NULLPKTBLLP; + temp &= ~(VID_NULLPKTBLLP_NULLPKTBLLP << VID_NULLPKTBLLP_NULLPKTBLLP_POS); + temp |= (VidCfg->NULLPacketInBLLP << VID_NULLPKTBLLP_NULLPKTBLLP_POS); + hdsi->Instance->VID_NULLPKTBLLP = temp; + + temp = hdsi->Instance->VID_VC; + temp &= ~(VID_VC_VC << VID_VC_VC_POS); + temp |= (VidCfg->VirtualChannel << VID_VC_VC_POS); + hdsi->Instance->VID_VC = temp; + + temp = hdsi->Instance->VID_EXTPKTEN; + temp &= ~(VID_EXTPKTEN_EXTPKTEN << VID_EXTPKTEN_EXTPKTEN_POS); + temp |= (VidCfg->ExternalPacket << VID_EXTPKTEN_EXTPKTEN_POS); + hdsi->Instance->VID_EXTPKTEN = temp; + + temp = hdsi->Instance->VID_VSSPLD; + temp &= ~(VID_VSSPLD_VSSPLD << VID_VSSPLD_VSSPLD_POS); + temp |= (VidCfg->VerticalSyncStartPayload << VID_VSSPLD_VSSPLD_POS); + hdsi->Instance->VID_VSSPLD = temp; + + temp = hdsi->Instance->VID_PLDPERPKT; + temp &= ~(VID_PLDPERPKT_PLLPERPKT << VID_PLDPERPKT_PLLPERPKT_POS); + temp |= (VidCfg->PayloadPerPacket << VID_PLDPERPKT_PLLPERPKT_POS); + hdsi->Instance->VID_PLDPERPKT = temp; + + hdsi->Instance->VID_EN |= VID_EN_EN; + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return DSI_OK; +} + +/** +*\*\name DSI_ConfigTimeout. +*\*\fun Configure DSI host timeout parameters. +*\*\param hdsi: dsi host instance. +*\*\param hstxcnt: 0~0xFFFFFF, Hight speed TX timeout count. +*\*\param lprxcnt: 0~0xFFFFFF, Low power RX timeout count. +*\*\param btacnt: 0~0xFFFFFF, Bus turn around timeout count. +*\*\return DSI_OK. +**/ +DSI_StateTypeDef DSI_ConfigTimeout(DSI_HandleTypeDef *hdsi, uint32_t hstxcnt, uint32_t lprxcnt, uint32_t btacnt) +{ + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + hdsi->Instance->DSI_HSTXTOCNT = hstxcnt; + hdsi->Instance->DSI_LRXTOCNT = lprxcnt; + hdsi->Instance->DSI_BTATOCNT = btacnt; + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return DSI_OK; +} + +/** +*\*\name DSI_APBPKT_ShortWrite. +*\*\fun write short DCS or short Generic command. +*\*\param hdsi: dsi host instance. +*\*\param ChannelID: Virtual channel ID. +*\*\param Mode: DSI short packet data type. +*\*\ - DSI_DCS_SHORT_PKT_WRITE_P0 +*\*\ - DSI_DCS_SHORT_PKT_WRITE_P1 +*\*\ - DSI_GEN_SHORT_PKT_WRITE_P0 +*\*\ - DSI_GEN_SHORT_PKT_WRITE_P1 +*\*\ - DSI_GEN_SHORT_PKT_WRITE_P2 +*\*\param Speed: DSI short packet speed. +*\*\ - DSI_MODE_LPDT +*\*\ - DSI_MODE_HSDT +*\*\param Param1: DSC command or first generic parameter. +*\*\param Param2: DSC parameter or second generic parameter. +*\*\return none +**/ +DSI_StateTypeDef DSI_APBPKT_ShortWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t Speed, uint32_t Param1, uint32_t Param2) +{ + DSI_StateTypeDef status; + DSI_PKTCtrlTypeDef PacketCtrl; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + PacketCtrl.IsBTAEnable = 0; + PacketCtrl.IsBTAOnly = 0; + PacketCtrl.CmdType = Speed; + PacketCtrl.Header.ChannelID = ChannelID; + PacketCtrl.Header.DataType = Mode; + PacketCtrl.Header.WordCount = (Param2 << 8U | (Param1 & 0xff)); + + status = DSI_ShortWrite(hdsi, PacketCtrl); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return status; +} + +/** +*\*\name DSI_ShortWrite. +*\*\fun write short DCS or short Generic command. +*\*\param hdsi: dsi host instance. +*\*\param PacketCtrl: Pointer to parameter DSI_PKTCtrlType struct. +*\*\return DSI_State +**/ +static DSI_StateTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, DSI_PKTCtrlTypeDef PacketCtrl) +{ + uint32_t timeout = DSI_TIME_OUT_VALUE; + // wait for DPHY direction is tx + while(((hdsi->Instance->DSI_PKTSTS & DSI_PKTSTS_DPHYDIR) == DSI_PKTSTS_DPHYDIR) && timeout--); + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + /* Update the DSI packet header with new information */ + // write the TX packet header values into the register + hdsi->Instance->DSI_PKTCTRL = ((PacketCtrl.IsBTAOnly << 26U) | (PacketCtrl.IsBTAEnable << 25U) | (PacketCtrl.CmdType << 24U) | \ + (PacketCtrl.Header.DataType << 18U) | (PacketCtrl.Header.ChannelID << 16U) | (PacketCtrl.Header.WordCount)); + + // set TX send enable + hdsi->Instance->DSI_SENDPKT = DSI_SENDPKT_SENDPKT; + + timeout = DSI_TIME_OUT_VALUE; + // wait until tx done + if(PacketCtrl.IsBTAEnable == 0) + { + // write wait for not idle + while(((hdsi->Instance->DSI_PKTSTS & DSI_PKTSTS_NIDLE) == DSI_PKTSTS_NIDLE) && timeout--) + { + } + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + } + return DSI_OK; +} + +/** +*\*\name DSI_APBPKT_LongWrite. +*\*\fun write long DCS or long Generic command +*\*\param hdsi: dsi host instance. +*\*\param ChannelID: Virtual channel ID. +*\*\param Mode: DSI short packet data type. +*\*\ - DSI_DCS_LONG_PKT_WRITE +*\*\ - DSI_GEN_LONG_PKT_WRITE +*\*\param Speed: DSI short packet speed. +*\*\ - DSI_MODE_LPDT +*\*\ - DSI_MODE_HSDT +*\*\param ParametersTable: Pointer to parameter values table. +*\*\param NbParams: Number of parameters. +*\*\return DSI_State +**/ +DSI_StateTypeDef DSI_APBPKT_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t ChannelID, uint32_t Mode, uint32_t Speed, uint8_t *ParametersTable, uint32_t NbParams) +{ + DSI_StateTypeDef status; + DSI_PKTCtrlTypeDef PacketCtrl; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + PacketCtrl.IsBTAEnable = 0; + PacketCtrl.IsBTAOnly = 0; + PacketCtrl.CmdType = Speed; + + PacketCtrl.Header.ChannelID = ChannelID; + PacketCtrl.Header.DataType = Mode; + PacketCtrl.Header.WordCount = NbParams; + + status = DSI_LongWrite(hdsi, PacketCtrl, ParametersTable); + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return status; +} + +/** +*\*\name DSI_LongWrite. +*\*\fun write long DCS or long Generic command +*\*\param hdsi: dsi host instance. +*\*\param PacketCtrl: Pointer to parameter DSI_PKTCtrlType struct. +*\*\param ParametersTable: Pointer to parameter values table. +*\*\return DSI_State +**/ +DSI_StateTypeDef DSI_LongWrite(DSI_HandleTypeDef *hdsi, DSI_PKTCtrlTypeDef PacketCtrl, uint8_t *ParametersTable) +{ + uint32_t uicounter; + uint32_t indexBytes; + uint32_t count; + uint32_t fifoword; + uint8_t *pparams = ParametersTable; + uint32_t timeout = DSI_TIME_OUT_VALUE; + uint8_t longpacket_byte[100] = {0}; + uint32_t longpacket_fifo[100] = {0}; + + // wait for DPHY direction is tx + while(((hdsi->Instance->DSI_PKTSTS & DSI_PKTSTS_DPHYDIR) == DSI_PKTSTS_DPHYDIR) && timeout--); + + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + /* Configure the packet to send a long DCS command */ + // write the TX packet header values into the register + hdsi->Instance->DSI_PKTCTRL = ((PacketCtrl.IsBTAOnly << 26U) | (PacketCtrl.IsBTAEnable << 25U) | (PacketCtrl.CmdType << 24U) | \ + (PacketCtrl.Header.DataType << 18U) | (PacketCtrl.Header.ChannelID << 16U) | (PacketCtrl.Header.WordCount)); + + for(uint16_t i = 0; i < PacketCtrl.Header.WordCount; i++ ) + { + longpacket_byte[i] = *pparams; + pparams += 4; + } + // write the payload data + uicounter = (PacketCtrl.Header.WordCount + 3) / 4; + for (count = 0U; count < uicounter ; ++count) + { + indexBytes = count * 4; + fifoword = 0; + if(indexBytes < PacketCtrl.Header.WordCount) + { + fifoword |= (uint32_t)(longpacket_byte[indexBytes]) << 0; + } + if((indexBytes + 1) < PacketCtrl.Header.WordCount) + { + fifoword |= ((uint32_t)(longpacket_byte[indexBytes + 1]) << 8); + } + if((indexBytes + 2) < PacketCtrl.Header.WordCount) + { + fifoword |= ((uint32_t)(longpacket_byte[indexBytes + 2]) << 16); + } + if((indexBytes + 3) < PacketCtrl.Header.WordCount) + { + fifoword |= ((uint32_t)(longpacket_byte[indexBytes + 3]) << 24); + } + + longpacket_fifo[count] = fifoword; + } + for(uint16_t i = 0; i < uicounter; i++) + { + hdsi->Instance->DSI_TXPLD = longpacket_fifo[i]; + } + // set TX send enable + hdsi->Instance->DSI_SENDPKT = DSI_SENDPKT_SENDPKT; + + timeout = DSI_TIME_OUT_VALUE; + // wait until tx done + while(((hdsi->Instance->DSI_PKTSTS & DSI_PKTSTS_TXD) == DSI_PKTSTS_TXD) && timeout--) + { + } + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + return DSI_OK; +} + +/** +*\*\name DSI_APBPKT_Read. +*\*\fun Read command (DCS or generic) +*\*\param hdsi: dsi host instance. +*\*\param ChannelNbr: Virtual channel ID. +*\*\param Array: Array pointer to a buffer to store the payload of a read back operation. +*\*\param Size: Data size to be read (in byte). +*\*\param Mode: DSI short packet data type. +*\*\ - DSI_DCS_SHORT_PKT_READ +*\*\ - DSI_GEN_SHORT_PKT_READ_P0 +*\*\ - DSI_GEN_SHORT_PKT_READ_P1 +*\*\ - DSI_GEN_SHORT_PKT_READ_P2 +*\*\param DCSCmd: DCS get/read command. +*\*\param ParametersTable: Pointer to parameter values table. +*\*\return DSI_State +**/ +DSI_StateTypeDef DSI_APBPKT_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, uint32_t Size, uint32_t Mode, uint32_t DCSCmd, uint8_t *ParametersTable) +{ + uint32_t datasize = Size; + + DSI_PKTCtrlTypeDef PacketCtrl; + DSI_StateTypeDef status; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if (datasize > 2U) + { + /* step1: set max return packet size */ + if (DSI_APBPKT_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, DSI_MODE_LPDT, ((datasize) & 0xFFU), (((datasize) >> 8U) & 0xFFU)) != DSI_OK) + { + /* Process Unlocked */ + hdsi->Lock = DSI_UNLOCKED; + return DSI_ERROR; + } + } + + /* step2: send read cmd */ + PacketCtrl.IsBTAEnable = 1; + PacketCtrl.IsBTAOnly = 0; + PacketCtrl.CmdType = DSI_MODE_LPDT; + + PacketCtrl.Header.ChannelID = ChannelNbr; + PacketCtrl.Header.DataType = Mode; + + /* step3: dsi rx secondly*/ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + //levan, cmd need to be in the data 0 + PacketCtrl.Header.WordCount = (0x0 << 8U | (DCSCmd & 0xff)); + status = DSI_ShortWrite(hdsi, PacketCtrl); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + PacketCtrl.Header.WordCount = 0; + status = DSI_ShortWrite(hdsi, PacketCtrl); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + PacketCtrl.Header.WordCount = DCSCmd << 8U; + status = DSI_ShortWrite(hdsi, PacketCtrl); + PacketCtrl.Header.DataType = DSI_EOTP; + PacketCtrl.Header.WordCount = (0x0f << 8U | 0x0f); + PacketCtrl.IsBTAEnable = 1; + status = DSI_ShortWrite(hdsi, PacketCtrl); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + PacketCtrl.Header.WordCount = (DCSCmd << 8U | ParametersTable[0U]); + status = DSI_ShortWrite(hdsi, PacketCtrl); + } + else + { + /* Process Unlocked */ + hdsi->Lock = DSI_UNLOCKED; + return DSI_ERROR; + } + /* step4: dsi rx */ + status = DSI_Read(hdsi, (uint8_t *)Array, Size); + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return status; +} + +/** +*\*\name DSI_APBPKT_Read_BTA. +*\*\fun Read command (DCS or generic) +*\*\param hdsi: dsi host instance. +*\*\param ChannelNbr: Virtual channel ID. +*\*\param Array: Array pointer to a buffer to store the payload of a read back operation. +*\*\param Size: Data size to be read (in byte). +*\*\param Mode: DSI short packet data type. +*\*\ - DSI_DCS_SHORT_PKT_READ +*\*\ - DSI_GEN_SHORT_PKT_READ_P0 +*\*\ - DSI_GEN_SHORT_PKT_READ_P1 +*\*\ - DSI_GEN_SHORT_PKT_READ_P2 +*\*\return DSI_State +**/ +DSI_StateTypeDef DSI_APBPKT_Read_BTA(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, uint32_t Size, uint32_t Mode) +{ + uint32_t datasize = Size; + + DSI_PKTCtrlTypeDef PacketCtrl; + DSI_StateTypeDef status; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if (datasize > 2U) + { + /* step1: set max return packet size */ + if (DSI_APBPKT_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, DSI_MODE_LPDT, ((datasize) & 0xFFU), (((datasize) >> 8U) & 0xFFU)) != DSI_OK) + { + /* Process Unlocked */ + hdsi->Lock = DSI_UNLOCKED; + return DSI_ERROR; + } + } + + /* step2: send read cmd */ + PacketCtrl.IsBTAEnable = 0; + PacketCtrl.IsBTAOnly = 1; + PacketCtrl.CmdType = DSI_MODE_LPDT; + + PacketCtrl.Header.ChannelID = ChannelNbr; + PacketCtrl.Header.DataType = Mode; + + /* step3: dsi rx secondly*/ + PacketCtrl.Header.WordCount = 0; + status = DSI_ShortWrite(hdsi, PacketCtrl); + + /* step4: dsi rx */ + status = DSI_Read(hdsi, (uint8_t *)Array, Size); + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return status; +} + +/** +*\*\name DSI_Read. +*\*\fun DSI Read data +*\*\param hdsi: dsi host instance. +*\*\param RxArray: Array pointer to a buffer to store the payload of a read back operation. +*\*\param RxSize: Data size to be read (in byte). +*\*\return DSI_State +**/ +DSI_StateTypeDef DSI_Read(DSI_HandleTypeDef *hdsi, uint8_t *RxArray, uint32_t RxSize) +{ + uint8_t *pdata = RxArray; + uint32_t timeout = DSI_TIME_OUT_VALUE; + DSI_PKTHeaderTypeDef RxPKTHeader; + + //levan, wait until packet header has been received + while(((hdsi->Instance->DSI_PKTSTS & DSI_PKTSTS_RXPKTD) != DSI_PKTSTS_RXPKTD) && timeout--) + {} + if(timeout == 0xFFFFFFFF) + { + return DSI_TIMEOUT; + } + //then proceed with + // read rx packet header + RxPKTHeader.WordCount = hdsi->Instance->DSI_PKTRXHDR & 0x0000ffff; + RxPKTHeader.DataType = (hdsi->Instance->DSI_PKTRXHDR >> 16) & 0x3f; + RxPKTHeader.ChannelID = (hdsi->Instance->DSI_PKTRXHDR >> 22) & 0x03; + //levan added, for short packet, TODO for long packet + *pdata = (uint8_t) RxPKTHeader.WordCount & 0x00ff; + pdata++; + *pdata = (uint8_t) RxPKTHeader.WordCount>>8 & 0x00ff; + return DSI_OK; +} + + + +/** +*\*\name DSI_GetSTS +*\*\fun Get DSI flag status. +*\*\param hdsi: dsi host instance. +*\*\param DSI_FLAG (The input parameters must be the following values): +*\*\ - DSI_FLAG_SOT_ERROR +*\*\ - DSI_FLAG_SOTSYNC_ERROR +*\*\ - DSI_FLAG_EOTSYNC_ERROR +*\*\ - DSI_FLAG_ESCMOD_ERROR +*\*\ - DSI_FLAG_LPTXSYNC_ERROR +*\*\ - DSI_FLAG_TO_ERROR +*\*\ - DSI_FLAG_FCTRL_ERROR +*\*\ - DSI_FLAG_COTDET_ERROR +*\*\ - DSI_FLAG_ECCSB_ERROR +*\*\ - DSI_FLAG_ECCML_ERROR +*\*\ - DSI_FLAG_CRC_ERROR +*\*\ - DSI_FLAG_DATATYPE_ERROR +*\*\ - DSI_FLAG_VCIDINVLID_ERROR +*\*\ - DSI_FLAG_INVLID_TXLEN_ERROR +*\*\ - DSI_FLAG_PROVILT_ERROR +*\*\ - DSI_FLAG_BIT0_ERROR +*\*\ - DSI_FLAG_BIT1_ERROR +*\*\ - DSI_FLAG_BIT2_ERROR +*\*\ - DSI_FLAG_BIT3_ERROR +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus DSI_GetSTS(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG) +{ + FlagStatus bitstatus; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if ((hdsi->Instance->DSI_STS & DSI_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return bitstatus; +} + +/** +*\*\name DSI_GetERRSTS +*\*\fun Get DSI error flag status. +*\*\param hdsi: dsi host instance. +*\*\param DSI_FLAG (The input parameters must be the following values): +*\*\ - DSI_ERROR_FLAG_ECCSB +*\*\ - DSI_ERROR_FLAG_ECCML +*\*\ - DSI_ERROR_FLAG_CRC +*\*\ - DSI_ERROR_FLAG_HTXTO +*\*\ - DSI_ERROR_FLAG_LRXTO +*\*\ - DSI_ERROR_FLAG_BATTO +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus DSI_GetERRSTS(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG) +{ + FlagStatus bitstatus; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if ((hdsi->Instance->DSI_ERRSTS & DSI_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return bitstatus; +} + +/** +*\*\name DSI_GetPKTSTS +*\*\fun Get DSI packet flag status. +*\*\param hdsi: dsi host instance. +*\*\param DSI_FLAG (The input parameters must be the following values): +*\*\ - DSI_PKT_FLAG_NIDLE +*\*\ - DSI_PKT_FLAG_TXD +*\*\ - DSI_PKT_FLAG_DPHYDIR +*\*\ - DSI_PKT_FLAG_TXFOVER +*\*\ - DSI_PKT_FLAG_TXFUNDER +*\*\ - DSI_PKT_FLAG_RXFOVER +*\*\ - DSI_PKT_FLAG_RXFUNDER +*\*\ - DSI_PKT_FLAG_RXPKTD +*\*\ - DSI_PKT_FLAG_ALLRXPKTD +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus DSI_GetPKTSTS(DSI_HandleTypeDef *hdsi, uint32_t DSI_FLAG) +{ + FlagStatus bitstatus; + + /* Process locked */ + hdsi->Lock = DSI_LOCKED; + + if ((hdsi->Instance->DSI_STS & DSI_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Process unlocked */ + hdsi->Lock = DSI_UNLOCKED; + + return bitstatus; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsmu.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsmu.c new file mode 100644 index 0000000000..bfead8b08f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dsmu.c @@ -0,0 +1,1574 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dsmu.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_dsmu.h" +#include "n32h76x_78x_rcc.h" + +#ifndef NULL + #define NULL 0 +#endif + +/** DSMU Private variables **/ +static __IO uint32_t gDSMU_ChannelInitStatus = 0U; + +/** DSMU_Private_Functions DSMU Private Functions **/ +static uint32_t DSMU_GetChannelNumber(const DSMU_Channel_Submodule *DSMU_Channely); + +/** +*\*\name DSMU_DeInit. +*\*\fun Deinitialize the DSMU. +*\*\param none. +*\*\return none. +**/ +void DSMU_DeInit(void) +{ + /* Reset DSMU by RCC*/ + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_DSMU); + + /* Reset initial status of all channels */ + gDSMU_ChannelInitStatus = 0U; +} + +/** +*\*\name DSMU_ChannelInit. +*\*\fun Initialize the DSMU channel according to the specified parameters +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\param DSMU_ChannelyInitStruct +*\*\ - OutputClock: +*\*\ - Activation: +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - Selection: +*\*\ - DSMU_CHANNEL_OUTPUT_CLOCK_SYSTEM +*\*\ - DSMU_CHANNEL_OUTPUT_CLOCK_AUDIO +*\*\ - Divider: +*\*\ - This parameter must be a number between Min_Data = 2 and Max_Data = 256. +*\*\ - Input: +*\*\ - Multiplexer: +*\*\ - DSMU_CHANNEL_EXTERNAL_INPUTS +*\*\ - DSMU_CHANNEL_ADC_OUTPUT +*\*\ - DSMU_CHANNEL_INTERNAL_REGISTER +*\*\ - DataPacking: +*\*\ - DSMU_CHANNEL_STANDARD_MODE +*\*\ - DSMU_CHANNEL_INTERLEAVED_MODE +*\*\ - DSMU_CHANNEL_DUAL_MODE +*\*\ - Pins: +*\*\ - DSMU_CHANNEL_SAME_CHANNEL_PINS +*\*\ - DSMU_CHANNEL_FOLLOWING_CHANNEL_PINS +*\*\ - SerialInterface: +*\*\ - Type: +*\*\ - DSMU_CHANNEL_SPI_RISING +*\*\ - DSMU_CHANNEL_SPI_FALLING +*\*\ - DSMU_CHANNEL_MANCHESTER_RISING +*\*\ - DSMU_CHANNEL_MANCHESTER_FALLING +*\*\ - SpiClock: +*\*\ - DSMU_CHANNEL_SPI_CLOCK_EXTERNAL +*\*\ - DSMU_CHANNEL_SPI_CLOCK_INTERNAL +*\*\ - DSMU_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING +*\*\ - DSMU_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING +*\*\ - Awd: +*\*\ - FilterOrder: +*\*\ - DSMU_AWD_FASTSINC_ORDER +*\*\ - DSMU_AWD_SINC1_ORDER +*\*\ - DSMU_AWD_SINC2_ORDER +*\*\ - DSMU_AWD_SINC3_ORDER +*\*\ - Oversampling: +*\*\ - This parameter must be a number between Min_Data = 1 and Max_Data = 32. +*\*\ - Offset: +*\*\ - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. +*\*\ - RightBitShift: +*\*\ - This parameter must be a number between Min_Data = 0 and Max_Data = 31. +*\*\return ErrorStatus: +*\*\ - SUCCESS +*\*\ - ERROR +**/ +ErrorStatus DSMU_ChannelInit(DSMU_Channel_Submodule* DSMU_Channely, DSMU_Channel_InitType* DSMU_ChannelInitStruct) +{ + uint32_t tReg; + ErrorStatus status = SUCCESS; + + /* Check DSMU Channel handle */ + if(DSMU_ChannelInitStruct == NULL) + { + status = ERROR; + } + else + { + /* Configure output serial clock and enable global DSMU interface only for first channel */ + if(0U == gDSMU_ChannelInitStatus) + { + /* Disable the DSMU global interface */ + DSMU_Channel0->CHCFG1 &= ~(DSMU_CHYCFG1_DSMUEN); + + /* Reset clock source and divider */ + tReg = DSMU_Channel0->CHCFG1; + tReg &= ~(DSMU_CHYCFG1_CLKOUTSRC | DSMU_CHYCFG1_CLKOUTDIV); + + /* Set the output serial clock source */ + tReg |= DSMU_ChannelInitStruct->OutputClock.Selection; + + if(DSMU_ChannelInitStruct->OutputClock.Activation != DISABLE) + { + /* Set the output clock divider */ + tReg |= ((DSMU_ChannelInitStruct->OutputClock.Divider - 1U) << REG_BIT16_OFFSET); + } + + /* Write register */ + DSMU_Channel0->CHCFG1 = tReg; + + /* Enable the DSMU global interface */ + DSMU_Channel0->CHCFG1 |= DSMU_CHYCFG1_DSMUEN; + } + + /* Disable current channel */ + DSMU_Channely->CHCFG1 &= ~(DSMU_CHYCFG1_CHEN); + + /* Config register DSMU_CHCFG1 */ + tReg = DSMU_Channely->CHCFG1; + tReg &= ~( DSMU_CHYCFG1_DATPACK \ + | DSMU_CHYCFG1_DATMUX \ + | DSMU_CHYCFG1_CHINSEL \ + | DSMU_CHYCFG1_SITP \ + | DSMU_CHYCFG1_SPICLKSEL ); + + /* Set channel input parameters */ + tReg |= ( DSMU_ChannelInitStruct->Input.Multiplexer \ + | DSMU_ChannelInitStruct->Input.DataPacking \ + | DSMU_ChannelInitStruct->Input.Pins ); + + /* Set serial interface parameters */ + tReg |= ( DSMU_ChannelInitStruct->SerialInterface.Type \ + | DSMU_ChannelInitStruct->SerialInterface.SpiClock ); + + /* Write register */ + DSMU_Channely->CHCFG1 = tReg; + + /* Set analog watchdog parameters */ + tReg = DSMU_Channely->CHAWDSCDET; + tReg &= ~(DSMU_CHYAWDSCDET_AWDFORD | DSMU_CHYAWDSCDET_AWDFOSR); + tReg |= ( DSMU_ChannelInitStruct->Awd.FilterOrder \ + | ((DSMU_ChannelInitStruct->Awd.Oversampling - 1U) << REG_BIT16_OFFSET)); + DSMU_Channely->CHAWDSCDET = tReg; + + /* Set channel offset and right bit shift */ + tReg = DSMU_Channely->CHCFG2; + tReg &= ~(DSMU_CHYCFG2_CALOFFSET | DSMU_CHYCFG2_DATRBS); + tReg |= (((uint32_t) DSMU_ChannelInitStruct->Offset << REG_BIT8_OFFSET) \ + | (DSMU_ChannelInitStruct->RightBitShift << REG_BIT3_OFFSET)); + DSMU_Channely->CHCFG2 = tReg; + + /* Enable DSMU channel */ + DSMU_Channely->CHCFG1 |= DSMU_CHYCFG1_CHEN; + + /* Set channel initialize status */ + gDSMU_ChannelInitStatus |= 1UL << DSMU_GetChannelNumber(DSMU_Channely); + } + + return status; +} + +/** +*\*\name DSMU_InitChannelStruct. +*\*\fun Set the initialize structure of DSMU channel to default value. +*\*\param DSMU_ChannelyInitStruct +*\*\ - OutputClock: +*\*\ - Activation +*\*\ - Selection +*\*\ - Divider +*\*\ - Input: +*\*\ - Multiplexer +*\*\ - DataPacking +*\*\ - Pins +*\*\ - SerialInterface +*\*\ - Type +*\*\ - SpiClock +*\*\ - Awd: +*\*\ - FilterOrder +*\*\ - Oversampling +*\*\ - Offset +*\*\ - RightBitShift +*\*\return none. +**/ +void DSMU_InitChannelStruct(DSMU_Channel_InitType* DSMU_ChannelInitStruct) +{ + DSMU_ChannelInitStruct->OutputClock.Activation = DISABLE; + DSMU_ChannelInitStruct->OutputClock.Selection = DSMU_CHANNEL_OUTPUT_CLOCK_SYSTEM; + DSMU_ChannelInitStruct->OutputClock.Divider = 2U; + + DSMU_ChannelInitStruct->Input.Multiplexer = DSMU_CHANNEL_EXTERNAL_INPUTS; + DSMU_ChannelInitStruct->Input.DataPacking = DSMU_CHANNEL_STANDARD_MODE; + DSMU_ChannelInitStruct->Input.Pins = DSMU_CHANNEL_SAME_CHANNEL_PINS; + + DSMU_ChannelInitStruct->SerialInterface.Type = DSMU_CHANNEL_SPI_RISING; + DSMU_ChannelInitStruct->SerialInterface.SpiClock = DSMU_CHANNEL_SPI_CLOCK_EXTERNAL; + + DSMU_ChannelInitStruct->Awd.FilterOrder = DSMU_AWD_FASTSINC_ORDER; + DSMU_ChannelInitStruct->Awd.Oversampling = 1U; + + DSMU_ChannelInitStruct->Offset = 0; + DSMU_ChannelInitStruct->RightBitShift = 0U; +} + +/** +*\*\name DSMU_ChannelDeInit. +*\*\fun Deinitialize the DSMU channel +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\return None. +**/ +void DSMU_ChannelDeInit(DSMU_Channel_Submodule* DSMU_Channely) +{ + /* Disable the DSMU channel */ + DSMU_Channely->CHCFG1 &= ~(DSMU_CHYCFG1_CHEN); + + /* Clear channel initialize status */ + gDSMU_ChannelInitStatus &= ~(1U << DSMU_GetChannelNumber(DSMU_Channely)); + + /* Disable global DSMU at deinit of last channel */ + if(0U == gDSMU_ChannelInitStatus) + { + DSMU_Channel0->CHCFG1 &= ~(DSMU_CHYCFG1_DSMUEN); + } +} + +/** +*\*\name DSMU_ChannelCkAbEnable. +*\*\fun Enable clock absence detection +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\return none +**/ +void DSMU_ChannelCkAbEnable(DSMU_Channel_Submodule* DSMU_Channely) +{ + /* Enable clock absence detection */ + DSMU_Channely->CHCFG1 |= DSMU_CHYCFG1_CLKABEN; +} + +/** +*\*\name DSMU_ChannelCkAbDisable. +*\*\fun Disable clock absence detection +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\return none +**/ +void DSMU_ChannelCkAbDisable(DSMU_Channel_Submodule* DSMU_Channely) +{ + uint32_t channel; + + /* Disable clock absence detection */ + DSMU_Channely->CHCFG1 &= ~DSMU_CHYCFG1_CLKABEN; + + /* Clear clock absence flag */ + channel = DSMU_GetChannelNumber(DSMU_Channely); + DSMU_Filter0->FLTINTCLR = (1UL << (REG_BIT16_OFFSET + channel)); +} + +/** +*\*\name DSMU_ChannelScdStart. +*\*\fun This function allows to start short circuit detection and assignment break signal. +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\param Threshold Short circuit detector threshold. + - This parameter must be a number between Min_Data = 0 and Max_Data = 255. +*\*\param BreakSignal Break signals assigned to short circuit event. +*\*\ - DSMU_NO_BREAK_SIGNAL +*\*\ - DSMU_BREAK_SIGNAL_0 +*\*\ - DSMU_BREAK_SIGNAL_1 +*\*\ - DSMU_BREAK_SIGNAL_2 +*\*\ - DSMU_BREAK_SIGNAL_3 +*\*\return none +*\*\note Same mode has to be used for all channels +**/ +void DSMU_ChannelScdStart(DSMU_Channel_Submodule* DSMU_Channely, + uint32_t Threshold, uint32_t BreakSignal) +{ + uint32_t tReg; + + /* Configure threshold and break signals */ + tReg = DSMU_Channely->CHAWDSCDET; + tReg &= ~(DSMU_CHYAWDSCDET_BKSCDET | DSMU_CHYAWDSCDET_SCDETTH); + tReg |= ((BreakSignal << REG_BIT12_OFFSET) | Threshold); + DSMU_Channely->CHAWDSCDET = tReg; + + /* Start short circuit detection */ + DSMU_Channely->CHCFG1 |= DSMU_CHYCFG1_SCDETEN; +} + +/** +*\*\name DSMU_ChannelScdStop. +*\*\fun This function allows to stop short circuit detection. +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\return none +**/ +void DSMU_ChannelScdStop(DSMU_Channel_Submodule* DSMU_Channely) +{ + uint32_t channel; + + /* Stop short circuit detection */ + DSMU_Channely->CHCFG1 &= ~(DSMU_CHYCFG1_SCDETEN); + + /* Clear short circuit detection flag */ + channel = DSMU_GetChannelNumber(DSMU_Channely); + DSMU_Filter0->FLTINTCLR = (1UL << (REG_BIT24_OFFSET + channel)); +} + +/** +*\*\name DSMU_ChannelGetAwdValue. +*\*\fun This function allows to get analog watchdog value for current channel. +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\return Channel analog watchdog value. +**/ +int16_t DSMU_ChannelGetAwdValue(const DSMU_Channel_Submodule* DSMU_Channely) +{ + return (int16_t)(DSMU_Channely->CHAWDDAT); +} + +/** +*\*\name DSMU_ChannelModifyOffset. +*\*\fun This function allows to modify channel offset value. +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\param Offset DFSDM channel offset. + - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. +*\*\return none. +**/ +void DSMU_ChannelModifyOffset(DSMU_Channel_Submodule* DSMU_Channely, int32_t Offset) +{ + uint32_t tReg; + + tReg = DSMU_Channely->CHCFG2; + tReg &= (~(DSMU_CHYCFG2_CALOFFSET)); + tReg |= ((uint32_t) Offset << REG_BIT8_OFFSET); + DSMU_Channely->CHCFG2 = tReg; +} + +/** +*\*\name DSMU_ChannelWriteData. +*\*\fun This function allows to write data into input data register. +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\param data New data write by CPU. +*\*\return none. +**/ +void DSMU_ChannelWriteData(DSMU_Channel_Submodule* DSMU_Channely, uint32_t data) +{ + DSMU_Channely->CHDATIN = data; +} + +/** +*\*\name DSMU_FilterInit. +*\*\fun Initialize the DSMU filter according to the specified parameters +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param DSMU_FilterInitStruct +*\*\ - RegularParam: +*\*\ - DmaMode: +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - FastMode: +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - Trigger: +*\*\ - DSMU_FILTER_SW_TRIGGER +*\*\ - DSMU_FILTER_SYNC_TRIGGER +*\*\ - InjectedParam: +*\*\ - ScanMode: +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - DmaMode: +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - Trigger: +*\*\ - DSMU_FILTER_SW_TRIGGER +*\*\ - DSMU_FILTER_SYNC_TRIGGER +*\*\ - DSMU_FILTER_EXT_TRIGGER +*\*\ - ExtTrigger: +*\*\ - DSMU_FILTER_EXT_TRIG_ATIM1_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_ATIM2_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_ATIM3_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_ATIM4_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMB1_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMB2_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMB3_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMA1_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMA2_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMA3_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMA4_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_GTIMA5_TRGO +*\*\ - DSMU_FILTER_EXT_TRIG_ATIM1_TRGO2 +*\*\ - DSMU_FILTER_EXT_TRIG_ATIM3_TRGO2 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG1 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG2 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG3 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM1_ADC_TRG4 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG1 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG2 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG3 +*\*\ - DSMU_FILTER_EXT_TRIG_SHRTIM2_ADC_TRG4 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI6 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI7 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI8 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI9 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI10 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI11 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI12 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI13 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI14 +*\*\ - DSMU_FILTER_EXT_TRIG_EXTI15 +*\*\ - FilterParam: +*\*\ - SincOrder: +*\*\ - DSMU_FILTER_FASTSINC_ORDER +*\*\ - DSMU_FILTER_SINC1_ORDER +*\*\ - DSMU_FILTER_SINC2_ORDER +*\*\ - DSMU_FILTER_SINC3_ORDER +*\*\ - DSMU_FILTER_SINC4_ORDER +*\*\ - DSMU_FILTER_SINC5_ORDER +*\*\ - Oversampling: +*\*\ - This parameter must be a number between Min_Data = 1 and Max_Data = 1024. +*\*\ - IntOversampling: +*\*\ - This parameter must be a number between Min_Data = 1 and Max_Data = 256. +*\*\return ErrorStatus. +*\*\ - SUCCESS +*\*\ - ERROR +**/ +ErrorStatus DSMU_FilterInit(DSMU_Filter_Submodule* DSMU_Filterx, + DSMU_Filter_InitType* DSMU_FilterInitStruct) +{ + uint32_t tReg; + ErrorStatus status = SUCCESS; + + /* Check parameters compatibility */ + if ((DSMU_Filterx == DSMU_Filter0) && + ((DSMU_FilterInitStruct->RegularParam.Trigger == DSMU_FILTER_SYNC_TRIGGER) || + (DSMU_FilterInitStruct->InjectedParam.Trigger == DSMU_FILTER_SYNC_TRIGGER))) + { + status = ERROR; + } + else + { + /* Disable the filter */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_DFLTEN); + + /* Config FLTCTRL1 register */ + tReg = DSMU_Filterx->FLTCTRL1; + tReg &= ~( DSMU_FLTXCTRL1_FAST \ + | DSMU_FLTXCTRL1_RDMAEN \ + | DSMU_FLTXCTRL1_RSYNC \ + | DSMU_FLTXCTRL1_JEXTEN \ + | DSMU_FLTXCTRL1_JEXTSEL \ + | DSMU_FLTXCTRL1_JDMAEN \ + | DSMU_FLTXCTRL1_JSCAN \ + | DSMU_FLTXCTRL1_JSYNC ); + + /* Set regular parameters */ + if(DSMU_FilterInitStruct->RegularParam.FastMode != DISABLE) + { + tReg |= DSMU_FLTXCTRL1_FAST; + } + + if(DSMU_FilterInitStruct->RegularParam.DmaMode != DISABLE) + { + tReg |= DSMU_FLTXCTRL1_RDMAEN; + } + + /* Set injected parameters */ + if(DSMU_FilterInitStruct->InjectedParam.Trigger == DSMU_FILTER_EXT_TRIGGER) + { + tReg |= DSMU_FilterInitStruct->InjectedParam.ExtTrigger; + } + + if(DSMU_FilterInitStruct->InjectedParam.ScanMode != DISABLE) + { + tReg |= DSMU_FLTXCTRL1_JSCAN; + } + + if(DSMU_FilterInitStruct->InjectedParam.DmaMode != DISABLE) + { + tReg |= DSMU_FLTXCTRL1_JDMAEN; + } + + /* Write register */ + DSMU_Filterx->FLTCTRL1 = tReg; + + /* Set filter parameters */ + tReg = DSMU_Filterx->FLTFCTRL; + tReg &= ~(DSMU_FLTXFCTRL_FORD | DSMU_FLTXFCTRL_FOSR | DSMU_FLTXFCTRL_IOSR); + tReg |= ( DSMU_FilterInitStruct->FilterParam.SincOrder \ + | ((DSMU_FilterInitStruct->FilterParam.Oversampling - 1U) << REG_BIT16_OFFSET) \ + | (DSMU_FilterInitStruct->FilterParam.IntOversampling - 1U)); + DSMU_Filterx->FLTFCTRL = tReg; + + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; + } + + return status; +} + +/** +*\*\name DSMU_InitFilterStruct. +*\*\fun Set the initialize structure of DSMU filter to default value. +*\*\param DSMU_FilterInitStruct +*\*\ - RegularParam: +*\*\ - DmaMode +*\*\ - FastMode +*\*\ - Trigger +*\*\ - InjectedParam: +*\*\ - ScanMode +*\*\ - DmaMode +*\*\ - Trigger +*\*\ - ExtTrigger +*\*\ - FilterParam: +*\*\ - SincOrder +*\*\ - Oversampling +*\*\ - IntOversampling +*\*\return none. +**/ +void DSMU_InitFilterStruct(DSMU_Filter_InitType* DSMU_FilterInitStruct) +{ + DSMU_FilterInitStruct->RegularParam.Trigger = DSMU_FILTER_SW_TRIGGER; + DSMU_FilterInitStruct->RegularParam.FastMode = DISABLE; + DSMU_FilterInitStruct->RegularParam.DmaMode = DISABLE; + + DSMU_FilterInitStruct->InjectedParam.Trigger = DSMU_FILTER_SW_TRIGGER; + DSMU_FilterInitStruct->InjectedParam.ScanMode = DISABLE; + DSMU_FilterInitStruct->InjectedParam.DmaMode = DISABLE; + DSMU_FilterInitStruct->InjectedParam.ExtTrigger = DSMU_FILTER_EXT_TRIG_ATIM1_TRGO; + + DSMU_FilterInitStruct->FilterParam.SincOrder = DSMU_FILTER_FASTSINC_ORDER; + DSMU_FilterInitStruct->FilterParam.Oversampling = 1U; + DSMU_FilterInitStruct->FilterParam.IntOversampling = 1U; +} + +/** +*\*\name DSMU_FilterEnable. +*\*\fun Enable or Disable the DSMU filter. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return None. +**/ +void DSMU_FilterEnable(DSMU_Filter_Submodule* DSMU_Filterx, FunctionalState Cmd) +{ + if( Cmd != DISABLE) + { + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; + } + else + { + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_DFLTEN); + } +} + +/** +*\*\name DSMU_FilterConfigRegChannel. +*\*\fun This function allows to select regular channel and +*\*\ config continuous mode for regular conversion. +*\*\param DSMU_Filterx: +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param ChannelSelect: +*\*\ - DSMU_CHANNEL_SELECT_0 +*\*\ - DSMU_CHANNEL_SELECT_1 +*\*\ - DSMU_CHANNEL_SELECT_2 +*\*\ - DSMU_CHANNEL_SELECT_3 +*\*\ - DSMU_CHANNEL_SELECT_4 +*\*\ - DSMU_CHANNEL_SELECT_5 +*\*\ - DSMU_CHANNEL_SELECT_6 +*\*\ - DSMU_CHANNEL_SELECT_7 +*\*\param ContinuousMode Enable/disable continuous mode for regular conversion. +*\*\ - DSMU_CONTINUOUS_CONV_OFF +*\*\ - DSMU_CONTINUOUS_CONV_ON +*\*\return none +**/ +void DSMU_FilterConfigRegChannel(DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t ChannelSelect, + uint32_t ContinuousMode) +{ + /* Configure channel and continuous mode for regular conversion */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_RCH | DSMU_FLTXCTRL1_RCONT); + DSMU_Filterx->FLTCTRL1 |= ((ChannelSelect & DSMU_FLTXCTRL1_RCH) | ContinuousMode); +} + +/** +*\*\name DSMU_FilterConfigInjChannel. +*\*\fun This function allows to select channels for injected conversion. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param ChannelSelect: +*\*\ - DSMU_CHANNEL_SELECT_0 +*\*\ - DSMU_CHANNEL_SELECT_1 +*\*\ - DSMU_CHANNEL_SELECT_2 +*\*\ - DSMU_CHANNEL_SELECT_3 +*\*\ - DSMU_CHANNEL_SELECT_4 +*\*\ - DSMU_CHANNEL_SELECT_5 +*\*\ - DSMU_CHANNEL_SELECT_6 +*\*\ - DSMU_CHANNEL_SELECT_7 +*\*\return none +**/ +void DSMU_FilterConfigInjChannel(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t ChannelSelect) +{ + /* Configure channel for injected conversion */ + DSMU_Filterx->FLTJCHG = (ChannelSelect & DSMU_FLTXJCHG_JCHG); +} + +/** +*\*\name DSMU_FilterGetRegularValue. +*\*\fun This function allows to get regular conversion value. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Channel Corresponding channel number of regular conversion. +*\*\return Regular conversion value +**/ +int32_t DSMU_FilterGetRegularValue(const DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t* Channel) +{ + uint32_t reg; + int32_t value; + + /* Get value of data register for regular channel */ + reg = DSMU_Filterx->FLTRDATA; + + /* Extract channel and regular conversion value */ + *Channel = (reg & DSMU_FLTXRDAT_RDATCH); + + /* Regular conversion value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DSMU_FLTXRDAT_RDAT; + value = ((int32_t)reg) / 256; + + /* return regular conversion value */ + return value; +} + +/** +*\*\name DSMU_FilterGetInjectedValue. +*\*\fun This function allows to get injected conversion value. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Channel Corresponding channel number of injected conversion. +*\*\return Injected conversion value +**/ +int32_t DSMU_FilterGetInjectedValue(const DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t* Channel) +{ + uint32_t reg; + int32_t value; + + /* Get value of data register for injected channel */ + reg = DSMU_Filterx->FLTJDATA; + + /* Extract channel and injected conversion value */ + *Channel = (reg & DSMU_FLTXJDAT_JDATCH); + + /* Injected conversion value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DSMU_FLTXJDAT_JDAT; + value = ((int32_t)reg) / 256; + + /* return regular conversion value */ + return value; +} + +/** +*\*\name DSMU_FilterAwdStart. +*\*\fun This function allows to start filter analog watchdog. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param awdParam DSMU filter analog watchdog parameters. +*\*\ - DataSource: +*\*\ - DSMU_FILTER_AWD_FILTER_DATA +*\*\ - DSMU_FILTER_AWD_CHANNEL_DATA +*\*\ - ChannelSelect: +*\*\ - DSMU_CHANNEL_SELECT_0 +*\*\ - DSMU_CHANNEL_SELECT_1 +*\*\ - DSMU_CHANNEL_SELECT_2 +*\*\ - DSMU_CHANNEL_SELECT_3 +*\*\ - DSMU_CHANNEL_SELECT_4 +*\*\ - DSMU_CHANNEL_SELECT_5 +*\*\ - DSMU_CHANNEL_SELECT_6 +*\*\ - DSMU_CHANNEL_SELECT_7 +*\*\ - HighThreshold: +*\*\ - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. +*\*\ - LowThreshold: +*\*\ - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. +*\*\ - HighBreakSignal: +*\*\ - DSMU_NO_BREAK_SIGNAL +*\*\ - DSMU_BREAK_SIGNAL_0 +*\*\ - DSMU_BREAK_SIGNAL_1 +*\*\ - DSMU_BREAK_SIGNAL_2 +*\*\ - DSMU_BREAK_SIGNAL_3 +*\*\ - LowBreakSignal: +*\*\ - DSMU_NO_BREAK_SIGNAL +*\*\ - DSMU_BREAK_SIGNAL_0 +*\*\ - DSMU_BREAK_SIGNAL_1 +*\*\ - DSMU_BREAK_SIGNAL_2 +*\*\ - DSMU_BREAK_SIGNAL_3 +*\*\return none +**/ +void DSMU_FilterAwdStart(DSMU_Filter_Submodule* DSMU_Filterx, + DSMU_Filter_AwdParamType* awdParam) +{ + uint32_t tReg; + + /* Set analog watchdog data source */ + tReg = DSMU_Filterx->FLTCTRL1; + tReg &= ~(DSMU_FLTXCTRL1_AWDFSEL); + tReg |= awdParam->DataSource; + DSMU_Filterx->FLTCTRL1 = tReg; + + /* Set thresholds and break signals */ + tReg = DSMU_Filterx->FLTAWDHT; + tReg &= ~(DSMU_FLTXAWDHT_AWDHT | DSMU_FLTXAWDHT_BKAWDHT); + tReg |= (((uint32_t) awdParam->HighThreshold << REG_BIT8_OFFSET) \ + | awdParam->HighBreakSignal ); + DSMU_Filterx->FLTAWDHT = tReg; + + tReg = DSMU_Filterx->FLTAWDLT; + tReg &= ~(DSMU_FLTXAWDLT_AWDLT | DSMU_FLTXAWDLT_BKAWDLT); + tReg |= (((uint32_t) awdParam->LowThreshold << REG_BIT8_OFFSET) \ + | awdParam->LowBreakSignal ); + DSMU_Filterx->FLTAWDLT = tReg; + + /* Set channels and interrupt for analog watchdog */ + tReg = DSMU_Filterx->FLTCTRL2; + tReg &= ~(DSMU_FLTXCTRL2_AWDCH); + tReg |= (awdParam->ChannelSelect & DSMU_FLTXCTRL2_AWDCH); + DSMU_Filterx->FLTCTRL2 = tReg; +} + +/** +*\*\name DSMU_FilterAwdStop. +*\*\fun This function allows to stop filter analog watchdog. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\return none +**/ +void DSMU_FilterAwdStop(DSMU_Filter_Submodule* DSMU_Filterx) +{ + /* Reset channels for analog watchdog and deactivate interrupt */ + DSMU_Filterx->FLTCTRL2 &= ~(DSMU_FLTXCTRL2_AWDCH); + + /* Clear all analog watchdog flags */ + DSMU_Filterx->FLTAWDCLR = (DSMU_FLTXAWDCLR_CLRAWDHTF | DSMU_FLTXAWDCLR_CLRAWDLTF); + + /* Reset thresholds and break signals */ + DSMU_Filterx->FLTAWDHT &= ~(DSMU_FLTXAWDHT_AWDHT | DSMU_FLTXAWDHT_BKAWDHT); + DSMU_Filterx->FLTAWDLT &= ~(DSMU_FLTXAWDLT_AWDLT | DSMU_FLTXAWDLT_BKAWDLT); + + /* Reset analog watchdog data source */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_AWDFSEL); +} + +/** +*\*\name DSMU_FilterExdStart. +*\*\fun This function allows to start extreme detector feature. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param ChannelSelect: +*\*\ - DSMU_CHANNEL_SELECT_0 +*\*\ - DSMU_CHANNEL_SELECT_1 +*\*\ - DSMU_CHANNEL_SELECT_2 +*\*\ - DSMU_CHANNEL_SELECT_3 +*\*\ - DSMU_CHANNEL_SELECT_4 +*\*\ - DSMU_CHANNEL_SELECT_5 +*\*\ - DSMU_CHANNEL_SELECT_6 +*\*\ - DSMU_CHANNEL_SELECT_7 +*\*\return none +**/ +void DSMU_FilterExdStart(DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t ChannelSelect) +{ + uint32_t tReg; + + /* Set channels for extreme detector */ + tReg = DSMU_Filterx->FLTCTRL2; + tReg &= ~(DSMU_FLTXCTRL2_EXDETCH); + tReg |= (ChannelSelect & DSMU_FLTXCTRL2_EXDETCH); + DSMU_Filterx->FLTCTRL2 = tReg; +} + +/** +*\*\name DSMU_FilterExdStop. +*\*\fun This function allows to stop extreme detector feature. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\return none +**/ +void DSMU_FilterExdStop(DSMU_Filter_Submodule* DSMU_Filterx) +{ + __IO uint32_t reg1; + __IO uint32_t reg2; + + /* Reset channels for extreme detector */ + DSMU_Filterx->FLTCTRL2 &= ~(DSMU_FLTXCTRL2_EXDETCH); + + /* Clear extreme detector values */ + reg1 = DSMU_Filterx->FLTEXDETMAX; + reg2 = DSMU_Filterx->FLTEXDETMIN; + (void)(reg1); /* To avoid GCC warning */ + (void)(reg2); /* To avoid GCC warning */ +} + +/** +*\*\name DSMU_FilterGetExdMaxValue. +*\*\fun This function allows to get extreme detector maximum value. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Channel Corresponding channel. +*\*\return Extreme detector maximum value +*\*\ - This value is between Min_Data = -8388608 and Max_Data = 8388607. +**/ +int32_t DSMU_FilterGetExdMaxValue(const DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t* Channel) +{ + uint32_t reg; + int32_t value; + + /* Get value of extreme detector maximum register */ + reg = DSMU_Filterx->FLTEXDETMAX; + + /* Extract channel and extreme detector maximum value */ + *Channel = (reg & DSMU_FLTXEXDETMAX_EXDETMAXCH); + + /* Extreme detector maximum value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DSMU_FLTXEXDETMAX_EXDETMAX; + value = ((int32_t)reg) / 256; + + /* return extreme detector maximum value */ + return value; +} + +/** +*\*\name DSMU_FilterGetExdMinValue. +*\*\fun This function allows to get extreme detector minimum value. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Channel Corresponding channel. +*\*\return Extreme detector minimum value +*\*\ - This value is between Min_Data = -8388608 and Max_Data = 8388607. +**/ +int32_t DSMU_FilterGetExdMinValue(const DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t* Channel) +{ + uint32_t reg; + int32_t value; + + /* Get value of extreme detector minimum register */ + reg = DSMU_Filterx->FLTEXDETMIN; + + /* Extract channel and extreme detector minimum value */ + *Channel = (reg & DSMU_FLTXEXDETMIN_EXDETMINCH); + + /* Extreme detector minimum value is a signed value located on 24 MSB of register */ + /* So after applying a mask on these bits we have to perform a division by 256 (2 raised to the power of 8) */ + reg &= DSMU_FLTXEXDETMIN_EXDETMIN; + value = ((int32_t)reg) / 256; + + /* return extreme detector minimum value */ + return value; +} + +/** +*\*\name DSMU_FilterGetConvTimeValue. +*\*\fun This function allows to get conversion time value. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\return Conversion time value +*\*\note To get time in second, this value has to be divided by DSMU clock frequency. +**/ +uint32_t DSMU_FilterGetConvTimeValue(const DSMU_Filter_Submodule* DSMU_Filterx) +{ + uint32_t reg; + uint32_t value; + + /* Get value of conversion timer register */ + reg = DSMU_Filterx->FLTCOVTIM; + + /* Extract conversion time value */ + value = ((reg & DSMU_FLTXCOVTIM_COVCNT) >> REG_BIT4_OFFSET); + + /* return extreme detector minimum value */ + return value; +} + +/** +*\*\name DSMU_RegConvStart. +*\*\fun This function allows to really start regular conversion. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Trigger +*\*\ - DSMU_FILTER_SW_TRIGGER +*\*\ - DSMU_FILTER_SYNC_TRIGGER +*\*\return None +**/ +void DSMU_RegConvStart(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger) +{ + /* Check regular trigger */ + if(Trigger == DSMU_FILTER_SYNC_TRIGGER) /* Synchronous with DSMU_FLT0 */ + { + /* DSMU filter0 can not be start with synchronous triger */ + if(DSMU_Filterx != DSMU_Filter0) + { + /* Disable DSMU filter */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_DFLTEN); + + /* Set RSYNC bit in DSMU_FLTXCTRL1 register */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_RSYNC; + + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; + } + } + else /* Software trigger */ + { + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; + + /* Software start of regular conversion */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_RSWSTART; + } +} + +/** +*\*\name DSMU_RegConvStop. +*\*\fun This function allows to really stop regular conversion. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Trigger +*\*\ - DSMU_FILTER_SW_TRIGGER +*\*\ - DSMU_FILTER_SYNC_TRIGGER +*\*\return None +**/ +void DSMU_RegConvStop(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger) +{ + /* Disable DSMU filter */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_DFLTEN); + + /* If regular trigger was synchronous, reset RSYNC bit in DSMU_FLTXCTRL1 register */ + if(Trigger == DSMU_FILTER_SYNC_TRIGGER) + { + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_RSYNC); + } + + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; +} + +/** +*\*\name DSMU_InjConvStart. +*\*\fun This function allows to really start injected conversion. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Trigger +*\*\ - DSMU_FILTER_SW_TRIGGER +*\*\ - DSMU_FILTER_SYNC_TRIGGER +*\*\ - DSMU_FILTER_EXT_TRIGGER +*\*\param TiggerEdge +*\*\ - DSMU_FILTER_EXT_TRIG_DISABLE +*\*\ - DSMU_FILTER_EXT_TRIG_RISING_EDGE +*\*\ - DSMU_FILTER_EXT_TRIG_FALLING_EDGE +*\*\ - DSMU_FILTER_EXT_TRIG_BOTH_EDGES +*\*\return None +**/ +void DSMU_InjConvStart(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger, uint32_t TiggerEdge) +{ + uint32_t tReg; + + /* Check injected trigger */ + if(Trigger == DSMU_FILTER_SW_TRIGGER) + { + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; + + /* Software start of injected conversion */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_JSWSTART; + } + else /* external or synchronous trigger */ + { + /* Disable DSMU filter */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_DFLTEN); + + /* Get current register value*/ + tReg = DSMU_Filterx->FLTCTRL1; + + /* Clear JSYNC and JEXTEN[1:0] bits first */ + tReg &= ~(DSMU_FLTXCTRL1_JEXTEN | DSMU_FLTXCTRL1_JSYNC); + + /* Config JSYNC and JEXTEN[1:0] as expected */ + if(Trigger == DSMU_FILTER_SYNC_TRIGGER) + { + /* Set JSYNC bit in DSMU_FLTXCTRL1 register */ + tReg |= DSMU_FLTXCTRL1_JSYNC; + } + else /* external trigger */ + { + /* Set JEXTEN[1:0] bits in DSMU_FLTXCTRL1 register */ + tReg |= TiggerEdge; + } + + /* Write back */ + DSMU_Filterx->FLTCTRL1 = tReg; + + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; + } +} + +/** +*\*\name DSMU_InjConvStop. +*\*\fun This function allows to really stop injected conversion. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Trigger +*\*\ - DSMU_FILTER_SW_TRIGGER +*\*\ - DSMU_FILTER_SYNC_TRIGGER +*\*\ - DSMU_FILTER_EXT_TRIGGER +*\*\return None +**/ +void DSMU_InjConvStop(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t Trigger) +{ + /* Disable DSMU filter */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_DFLTEN); + + /* If injected trigger was synchronous, reset JSYNC bit in DSMU_FLTXCTRL1 register */ + if(Trigger == DSMU_FILTER_SYNC_TRIGGER) + { + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_JSYNC); + } + else if(Trigger == DSMU_FILTER_EXT_TRIGGER) + { + /* Reset JEXTEN[1:0] bits in DSMU_FLTXCTRL1 register */ + DSMU_Filterx->FLTCTRL1 &= ~(DSMU_FLTXCTRL1_JEXTEN); + } + else + { + /* Nothing to do */ + } + + /* Enable DSMU filter */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_DFLTEN; +} + +/** +*\*\name DSMU_GetFlagStatus. +*\*\fun Checks whether the DSMU flag has set or not. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param DSMU_Flag: +*\*\ This parameter must be one of the following: +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH0 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH1 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH2 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH3 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH4 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH5 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH6 +*\*\ - DSMU_FLAG_SHORT_CIRCUIT_CH7 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH0 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH1 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH2 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH3 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH4 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH5 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH6 +*\*\ - DSMU_FLAG_CLOCK_ABSENCE_CH7 +*\*\ - DSMU_FLAG_REGULAR_ACTIVE +*\*\ - DSMU_FLAG_INJECT_ACTIVE +*\*\ - DSMU_FLAG_ANALOG_WATCHDOG +*\*\ - DSMU_FLAG_REGULAR_OVERRUN +*\*\ - DSMU_FLAG_INJECT_OVERRUN +*\*\ - DSMU_FLAG_REGULAR_END +*\*\ - DSMU_FLAG_INJECT_END +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +*\*\note: DSMU_FLAG_SHORT_CIRCUIT_CH0~7 and DSMU_FLAG_CLOCK_ABSENCE_CH0~7 only exist in DSMU_Filter0->FLTSTS. +**/ +FlagStatus DSMU_GetFlagStatus(DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t DSMU_Flag) +{ + FlagStatus bitstatus; + uint32_t tFLTSTS; + + if(DSMU_Flag > DSMU_FLAG_REGULAR_ACTIVE) + { + tFLTSTS = DSMU_Filter0->FLTSTS; + } + else + { + tFLTSTS = DSMU_Filterx->FLTSTS; + } + + if ((tFLTSTS & DSMU_Flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name DSMU_ClearFlag. +*\*\fun Clears flags of the specified DSMU. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param DSMU_FlagClear : +*\*\ This parameter must be one of the following: +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH0 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH1 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH2 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH3 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH4 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH5 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH6 +*\*\ - DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH7 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH0 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH1 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH2 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH3 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH4 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH5 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH6 +*\*\ - DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH7 +*\*\ - DSMU_CLEAR_FLAG_REGULAR_OVERRUN +*\*\ - DSMU_CLEAR_FLAG_INJECT_OVERRUN +*\*\return none. +*\*\note: DSMU_CLEAR_FLAG_SHORT_CIRCUIT_CH0~7 and DSMU_CLEAR_FLAG_CLOCK_ABSENCE_CH0~7 only exist in DSMU_Filter0->FLTINTCLR. +**/ +void DSMU_ClearFlag(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_FlagClear) +{ + __IO uint32_t *pINTCLR; + + if(DSMU_FlagClear > DSMU_CLEAR_FLAG_REGULAR_OVERRUN) + { + pINTCLR = &(DSMU_Filter0->FLTINTCLR); + } + else + { + pINTCLR = &(DSMU_Filterx->FLTINTCLR); + } + + /* Clear the selected DSMU flags */ + *pINTCLR = (DSMU_FlagClear & DSMU_CLEAR_FLAG_ALL); +} + +/** +*\*\name DSMU_GetAwdFlagStatus. +*\*\fun Checks whether the DSMU analog watchdog flag has set or not. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param DSMU_AwdFlag : +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH0 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH1 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH2 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH3 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH4 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH5 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH6 +*\*\ - DSMU_AWD_FLAG_HIGH_THRESHLOD_CH7 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH0 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH1 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH2 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH3 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH4 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH5 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH6 +*\*\ - DSMU_AWD_FLAG_LOW_THRESHOLD_CH7 +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus DSMU_GetAwdFlagStatus(DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t DSMU_AwdFlag) +{ + FlagStatus bitstatus; + + if ((DSMU_Filterx->FLTAWDSTS & DSMU_AwdFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name DSMU_ClearAwdFlag. +*\*\fun Clears analog watch dog flag of the specified DSMU. +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param DSMU_AwdFlagClear : +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH0 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH1 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH2 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH3 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH4 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH5 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH6 +*\*\ - DSMU_CLEAR_AWD_FLAG_HIGH_THRESHLOD_CH7 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH0 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH1 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH2 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH3 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH4 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH5 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH6 +*\*\ - DSMU_CLEAR_AWD_FLAG_LOW_THRESHOLD_CH7 +*\*\return none. +**/ +void DSMU_ClearAwdFlag(DSMU_Filter_Submodule* DSMU_Filterx, uint32_t DSMU_AwdFlagClear) +{ + /* Clear the selected DSMU watch dog flag */ + DSMU_Filterx->FLTAWDCLR = (DSMU_AwdFlagClear & DSMU_CLEAR_AWD_FLAG_ALL); +} + +/** +*\*\name DSMU_ConfigInt +*\*\fun Enables or disables interrupt +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param DSMU_Int: +*\*\ This parameter must be one of the following: +*\*\ - DSMU_INT_CLOCK_ABSENCE +*\*\ - DSMU_INT_SHORT_CIRCUIT +*\*\ - DSMU_INT_ANALOG_WATCHDOG +*\*\ - DSMU_INT_REGULAR_OVERRUN +*\*\ - DSMU_INT_INJECT_OVERRUN +*\*\ - DSMU_INT_REGULAR_END +*\*\ - DSMU_INT_INJECT_END +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note: DSMU_INT_CLOCK_ABSENCE and DSMU_INT_SHORT_CIRCUIT only exist in DSMU_Filter0->FLTCTRL2. +**/ +void DSMU_ConfigInt(DSMU_Filter_Submodule* DSMU_Filterx, + uint32_t DSMU_Int, FunctionalState Cmd) +{ + __IO uint32_t *pCTRL2; + + if(DSMU_Int > DSMU_INT_ANALOG_WATCHDOG) + { + pCTRL2 = &(DSMU_Filter0->FLTCTRL2); + } + else + { + pCTRL2 = &(DSMU_Filterx->FLTCTRL2); + } + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + *pCTRL2 |= DSMU_Int; + } + else + { + /* Disable the Interrupt sources */ + *pCTRL2 &= (~DSMU_Int); + } +} + +/** +*\*\name DSMU_ConfigRegChDMA +*\*\fun Enables or disables regular channel DMA +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DSMU_ConfigRegChDMA(DSMU_Filter_Submodule* DSMU_Filterx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_RDMAEN; + } + else + { + /* Disable the Interrupt sources */ + DSMU_Filterx->FLTCTRL1 &= (~DSMU_FLTXCTRL1_RDMAEN); + } +} + +/** +*\*\name DSMU_ConfigInjChDMA +*\*\fun Enables or disables injected channel DMA +*\*\param DSMU_Filterx +*\*\ - DSMU_Filter0 +*\*\ - DSMU_Filter1 +*\*\ - DSMU_Filter2 +*\*\ - DSMU_Filter3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DSMU_ConfigInjChDMA(DSMU_Filter_Submodule* DSMU_Filterx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + DSMU_Filterx->FLTCTRL1 |= DSMU_FLTXCTRL1_JDMAEN; + } + else + { + /* Disable the Interrupt sources */ + DSMU_Filterx->FLTCTRL1 &= (~DSMU_FLTXCTRL1_JDMAEN); + } +} + +/** +*\*\fun This function allows to get the channel number from channel instance. +*\*\param DSMU_Channely +*\*\ - DSMU_Channel0 +*\*\ - DSMU_Channel1 +*\*\ - DSMU_Channel2 +*\*\ - DSMU_Channel3 +*\*\ - DSMU_Channel4 +*\*\ - DSMU_Channel5 +*\*\ - DSMU_Channel6 +*\*\ - DSMU_Channel7 +*\*\return Channel number. +**/ +static uint32_t DSMU_GetChannelNumber(const DSMU_Channel_Submodule* DSMU_Channely) +{ + uint32_t ChannelNum; + + /* Get channel from instance */ + if(DSMU_Channely == DSMU_Channel0) + { + ChannelNum = 0; + } + else if(DSMU_Channely == DSMU_Channel1) + { + ChannelNum = 1; + } + else if(DSMU_Channely == DSMU_Channel2) + { + ChannelNum = 2; + } + else if(DSMU_Channely == DSMU_Channel3) + { + ChannelNum = 3; + } + else if(DSMU_Channely == DSMU_Channel4) + { + ChannelNum = 4; + } + else if(DSMU_Channely == DSMU_Channel5) + { + ChannelNum = 5; + } + else if(DSMU_Channely == DSMU_Channel6) + { + ChannelNum = 6; + } + else /* DSMU_Channel7 */ + { + ChannelNum = 7; + } + + return ChannelNum; +} + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dvp.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dvp.c new file mode 100644 index 0000000000..327f58fd85 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_dvp.c @@ -0,0 +1,1169 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_dvp.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_dvp.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name DVP_DeInit. +*\*\fun Deinitializes the DVP peripheral registers to their default reset values. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\return none +**/ +void DVP_DeInit(DVP_Module *DVPx) +{ + if(DVPx == DVP1) + { + RCC_EnableAXIPeriphReset2(RCC_AXI_PERIPHRST_DVP1); + } + else + { + RCC_EnableAXIPeriphReset2(RCC_AXI_PERIPHRST_DVP2); + } +} + +/** +*\*\name DVP_Init. +*\*\fun Initializes the DVP peripheral according to the specified +*\*\ parameters in the DVP_InitParam . +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVP_InitParam (The input parameters must be the following values): +*\*\ - CaptureMode +*\*\ - DVP_CAPTURE_MODE_CONTINUE +*\*\ - DVP_CAPTURE_MODE_SINGLE +*\*\ - CropMode +*\*\ - DVP_NORMAL_MODE +*\*\ - DVP_CROP_MODE +*\*\ - SynchroMode +*\*\ - DVP_SYNC_MODE_SOFTWARE +*\*\ - DVP_SYNC_MODE_HARDWARE +*\*\ - CropStartX +*\*\ - CropStartY +*\*\ - CropEndX +*\*\ - CropEndY +*\*\ - BFilter +*\*\ - PixelClkPolarity +*\*\ - DVP_PIXEL_POLARITY_RISING +*\*\ - DVP_PIXEL_POLARITY_FALLING +*\*\ - HsyncPolarity +*\*\ - DVP_HSYNC_POLARITY_HIGH +*\*\ - DVP_HSYNC_POLARITY_LOW +*\*\ - VsyncPolarity +*\*\ - DVP_VSYNC_POLARITY_HIGH +*\*\ - DVP_VSYNC_POLARITY_LOW +*\*\ - DataInvert +*\*\ - DVP_DATA_INVERT +*\*\ - DVP_DATA_NOTINVERT +*\*\ - DataReverse +*\*\ - DVP_DATA_REVERSE +*\*\ - DVP_DATA_NOTREVERSE +*\*\ - DataMode +*\*\ - DVP_DATA_MODE1 +*\*\ - DVP_DATA_MODE2 +*\*\ - DVP_DATA_MODE3 +*\*\ - DVP_DATA_MODE4 +*\*\ - DVP_DATA_MODE5 +*\*\ - DVP_DATA_MODE6 +*\*\ - DVP_DATA_MODE7 +*\*\ - DVP_DATA_MODE8 +*\*\ - PixelByte +*\*\ - DVP_PIXEL_BYTE1 +*\*\ - DVP_PIXEL_BYTE2 +*\*\return none +**/ +void DVP_Init(DVP_Module *DVPx, DVP_InitType* DVP_InitParam) +{ + uint32_t tmpregister; + uint32_t tmp; + + if(DVP_InitParam->CropMode == DVP_CROP_MODE) + { + /*---------------------------- DVP_CSXY Configuration -----------------------*/ + tmp = ((uint32_t)DVP_InitParam->CropStartY << 16) | DVP_InitParam->CropStartX; + DVPx->CSXY = tmp; + /*---------------------------- DVP_CEXY Configuration -----------------------*/ + tmp = ((uint32_t)DVP_InitParam->CropEndY << 16) | DVP_InitParam->CropEndX; + DVPx->CEXY = tmp; + } + + /*---------------------------- DVP_CTRL Configuration -----------------------*/ + tmpregister = DVPx->CTRL; + tmpregister = tmpregister & DVP_VBFLT_MASK & DVP_CAPTURE_MODE_MASK & DVP_CROP_MODE_MASK; + tmpregister |= ((uint32_t)DVP_InitParam->VBFilter << 28) | DVP_InitParam->CaptureMode | DVP_InitParam->CropMode; + DVPx->CTRL = tmpregister; + + /*---------------------------- DVP_PORTCFG Configuration -----------------------*/ + tmp = DVPx->PORTCFG; + tmp |= DVP_InitParam->PixelClkPolarity | DVP_InitParam->HsyncPolarity + | DVP_InitParam->VsyncPolarity | DVP_InitParam->DataInvert + | DVP_InitParam->DataReverse | DVP_InitParam->DataMode + | DVP_InitParam->SynchroMode; + + if(DVP_InitParam->CropMode == DVP_CROP_MODE) + { + tmp |= DVP_InitParam->PixelByte; + } + + DVPx->PORTCFG = tmp; + +} + +/** +*\*\name DVP_StructInit. +*\*\fun Initializes the structure parameter of type DVP_InitType used to +*\*\ initialize DVP. This function is usually called before initializing +*\*\ a parameter of type DVP_InitType. +*\*\param DVP_InitParam : +*\*\ - Pointer to the DVP_InitType structure which will be initialized. +*\*\return none +**/ +void DVP_StructInit(DVP_InitType* DVP_InitParam) +{ + /* DVP_InitParam members default value */ + DVP_InitParam->CaptureMode = DVP_CAPTURE_MODE_CONTINUE; + DVP_InitParam->CropMode = DVP_NORMAL_MODE; + DVP_InitParam->SynchroMode = DVP_SYNC_MODE_HARDWARE; + DVP_InitParam->CropStartX = 0; + DVP_InitParam->CropStartY = 0; + DVP_InitParam->CropEndX = 0; + DVP_InitParam->CropEndY = 0; + DVP_InitParam->VBFilter = 8; + DVP_InitParam->PixelClkPolarity = DVP_PIXEL_POLARITY_RISING; + DVP_InitParam->HsyncPolarity = DVP_HSYNC_POLARITY_HIGH; + DVP_InitParam->VsyncPolarity = DVP_VSYNC_POLARITY_LOW; + DVP_InitParam->DataInvert = DVP_DATA_NOTINVERT; + DVP_InitParam->DataReverse = DVP_DATA_NOTREVERSE; + DVP_InitParam->DataMode = DVP_DATA_MODE1; + DVP_InitParam->PixelByte = DVP_PIXEL_BYTE1; + +} + +/** +*\*\name DVP_ConfigDma. +*\*\fun Initializes the structure parameter of type DVP_DMAInitType used to +*\*\ initialize DVP DMA. This function is usually called before initializing +*\*\ a parameter of type DVP_DMAInitType. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVP_DMAInitType : +*\*\ - FrameBufferNum +*\*\ - FrameBufferAddress1 +*\*\ - FrameBufferAddress2 +*\*\ - DisplayStatus +*\*\ - DVP_DISPLAY_ADDRESS +*\*\ - DVP_DISPLAY_NUMBER +*\*\ - BurstSize +*\*\ - DVP_BURST_SIZE_BYTE_8 +*\*\ - DVP_BURST_SIZE_BYTE_16 +*\*\ - DVP_BURST_SIZE_BYTE_24 +*\*\ - DVP_BURST_SIZE_BYTE_32 +*\*\ - DVP_BURST_SIZE_BYTE_40 +*\*\ - DVP_BURST_SIZE_BYTE_48 +*\*\ - DVP_BURST_SIZE_BYTE_56 +*\*\ - DVP_BURST_SIZE_BYTE_64 +*\*\ - FifoThreshold +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_8 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_16 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_32 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_64 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_128 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_256 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_512 +*\*\ - DVP_FIFO_THRSEHOLD_BYTE_1024 +*\*\ - FrameBufferSize +*\*\return none +**/ +void DVP_ConfigDma(DVP_Module *DVPx, DVP_DMAInitType* DVP_DMAInitParam) +{ + uint32_t tmpregister; + + /*---------------------------- DVP_FIFOCFG Configuration -----------------------*/ + tmpregister = DVPx->FIFOCFG; + tmpregister &= DVP_DISPLAY_STATUS_MASK & DVP_FIFO_THRSEHOLD_MASK & DVP_BURST_SIZE_MASK; + + tmpregister |= DVP_DMAInitParam->DisplayStatus | DVP_DMAInitParam->FifoThreshold | DVP_DMAInitParam->BurstSize; + DVPx->FIFOCFG = tmpregister; + + /*---------------------------- DVP_FBS Configuration -----------------------*/ + DVPx->FBS = (uint32_t)DVP_DMAInitParam->FrameBufferSize; + + /*---------------------------- DVP_SMADDRx Configuration -----------------------*/ + if(DVP_DMAInitParam->FrameBufferNum == 2u) + { + DVPx->SMADDR1 = DVP_DMAInitParam->FrameBufferAddress1; + DVPx->SMADDR2 = DVP_DMAInitParam->FrameBufferAddress2; + } + else + { + DVPx->SMADDR1 = DVP_DMAInitParam->FrameBufferAddress1; + } + +} + +/** +*\*\name DVP_DMAStructInit. +*\*\fun Initializes the structure parameter of type DVP_DMAInitType used to +*\*\ initialize DVP. This function is usually called before initializing +*\*\ a parameter of type DVP_DMAInitType. +*\*\param DVP_DMAInitParam : +*\*\ - Pointer to the DVP_DMAInitType structure which will be initialized. +*\*\return none +**/ +void DVP_DMAStructInit(DVP_DMAInitType* DVP_DMAInitParam) +{ + + /* DVP_DMAInitParam members default value */ + DVP_DMAInitParam->FrameBufferNum = 1; + DVP_DMAInitParam->FrameBufferAddress1 = 0; + DVP_DMAInitParam->FrameBufferAddress2 = 0; + DVP_DMAInitParam->DisplayStatus = DVP_DISPLAY_NUMBER; + DVP_DMAInitParam->BurstSize = DVP_BURST_SIZE_BYTE_8; + DVP_DMAInitParam->FifoThreshold = DVP_FIFO_THRSEHOLD_BYTE_8; + DVP_DMAInitParam->FrameBufferSize = 32; + +} + + +/** +*\*\name DVP_EnablePort. +*\*\fun DVP interface enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnablePort(DVP_Module *DVPx, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + /* Enable the DVP by setting ENABLE bit */ + DVPx->CTRL |= DVP_ENABLE; + } + else + { + /* Disable the DVP by clearing ENABLE bit */ + DVPx->INTSTS |= DVP_DISABLE; + } + +} + +/** +*\*\name DVP_EnableCrop. +*\*\fun DVP crop feature enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableCrop(DVP_Module *DVPx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DVP Crop feature */ + DVPx->CTRL |= DVP_CROP_MODE; + } + else + { + /* Disable the DVP Crop feature */ + DVPx->CTRL &= DVP_CROP_MODE_MASK; + } +} + +/** +*\*\name DVP_ConfigVBFLT. +*\*\fun VSYNC blanking glitch filtering control. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Filt:(The input parameters must be the following values) +*\*\ - 0~0xF +*\*\return none +**/ +void DVP_ConfigVBlankFilter(DVP_Module *DVPx, uint8_t Filt) +{ + + uint32_t tmpregister; + tmpregister = DVPx->CTRL; + tmpregister = (uint32_t)(tmpregister & (uint32_t)DVP_VBFLT_MASK); + tmpregister |= (uint32_t)Filt << 28u; + DVPx->CTRL = tmpregister; + +} + +/** +*\*\name DVP_ConfigInt. +*\*\fun DVP interrupts enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVPInt (The input parameters must be the following values): +*\*\ - DVP_INT_M1S +*\*\ - DVP_INT_M2S +*\*\ - DVP_INT_M1TC +*\*\ - DVP_INT_M2TC +*\*\ - DVP_INT_FO +*\*\ - DVP_INT_AHBERR +*\*\ - DVP_INT_MO +*\*\ - DVP_INT_SKIP +*\*\ - DVP_INT_CERR +*\*\ - DVP_INT_SERR +*\*\ - DVP_INT_FMS +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_ConfigInt(DVP_Module *DVPx, uint32_t DVPInt, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + DVPx->INTEN |= DVPInt; + } + else + { + /* Disable the Interrupt sources */ + DVPx->INTEN &= ~DVPInt; + } + +} + +/** +*\*\name DVP_GetFlagStatus. +*\*\fun Get DVP flag status. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVP_Flag (The input parameters must be the following values): +*\*\ - DVP_FLAG_M1S +*\*\ - DVP_FLAG_M2S +*\*\ - DVP_FLAG_M1TC +*\*\ - DVP_FLAG_M2TC +*\*\ - DVP_FLAG_M1FO +*\*\ - DVP_FLAG_M2FO +*\*\ - DVP_FLAG_AHBERR1 +*\*\ - DVP_FLAG_AHBERR2 +*\*\ - DVP_FLAG_M1O +*\*\ - DVP_FLAG_M2O +*\*\ - DVP_FLAG_SKIP +*\*\ - DVP_FLAG_CERR +*\*\ - DVP_FLAG_SERR +*\*\ - DVP_FLAG_FMS +*\*\return SET or RESET. +**/ +FlagStatus DVP_GetFlagStatus(DVP_Module *DVPx, uint32_t DVP_Flag) +{ + + FlagStatus bitstatus; + uint32_t tmpregister; + + tmpregister = DVPx->INTSTS; + + if ((tmpregister & DVP_Flag) != (uint32_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the DVP_Flag status */ + return bitstatus; + +} + + +/** +*\*\name DVP_ClearFlag. +*\*\fun Clears DVP flag status. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVP_Flag (The input parameters must be the following values): +*\*\ - DVP_FLAG_M1S +*\*\ - DVP_FLAG_M2S +*\*\ - DVP_FLAG_M1TC +*\*\ - DVP_FLAG_M2TC +*\*\ - DVP_FLAG_M1FO +*\*\ - DVP_FLAG_M2FO +*\*\ - DVP_FLAG_AHBERR1 +*\*\ - DVP_FLAG_AHBERR2 +*\*\ - DVP_FLAG_M1O +*\*\ - DVP_FLAG_M2O +*\*\ - DVP_FLAG_SKIP +*\*\ - DVP_FLAG_CERR +*\*\ - DVP_FLAG_SERR +*\*\ - DVP_FLAG_FMS +*\*\return none. +**/ +void DVP_ClearFlag(DVP_Module *DVPx, uint32_t DVP_Flag) +{ + + DVPx->INTSTS = DVP_Flag; + +} + +/** +*\*\name DVP_GetIntStatus. +*\*\fun Get DVP interrupt status. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVP_Int (The input parameters must be the following values): +*\*\ - DVP_INT_M1S +*\*\ - DVP_INT_M2S +*\*\ - DVP_INT_M1TC +*\*\ - DVP_INT_M2TC +*\*\ - DVP_INT_FO +*\*\ - DVP_INT_AHBERR +*\*\ - DVP_INT_MO +*\*\ - DVP_INT_SKIP +*\*\ - DVP_INT_CERR +*\*\ - DVP_INT_SERR +*\*\ - DVP_INT_FMS +*\*\return SET or RESET. +**/ +INTStatus DVP_GetIntStatus(DVP_Module *DVPx, uint32_t DVP_Int) +{ + + INTStatus bitstatus; + uint32_t intstatus, enablestatus; + + if(DVP_Int == DVP_INT_FO) + { + enablestatus = DVPx->INTEN & DVP_Int; + intstatus = DVPx->INTSTS & (DVP_FLAG_M1FO | DVP_FLAG_M2FO); + } + else if(DVP_Int == DVP_INT_AHBERR) + { + enablestatus = DVPx->INTEN & DVP_Int; + intstatus = DVPx->INTSTS & (DVP_FLAG_AHBERR1 | DVP_FLAG_AHBERR2); + } + else if(DVP_Int == DVP_INT_MO) + { + enablestatus = DVPx->INTEN & DVP_Int; + intstatus = DVPx->INTSTS & (DVP_FLAG_M1O | DVP_FLAG_M2O); + } + else + { + enablestatus = DVPx->INTEN & DVP_Int; + intstatus = DVPx->INTSTS & DVP_Int; + } + + if ((intstatus != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + +} + +/** +*\*\name DVP_ClrIntPendingBit. +*\*\fun Clear DVP interrupt status bits. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param DVP_Int (The input parameters must be the following values): +*\*\ - DVP_INT_M1S +*\*\ - DVP_INT_M2S +*\*\ - DVP_INT_M1TC +*\*\ - DVP_INT_M2TC +*\*\ - DVP_INT_FO +*\*\ - DVP_INT_AHBERR +*\*\ - DVP_INT_MO +*\*\ - DVP_INT_SKIP +*\*\ - DVP_INT_CERR +*\*\ - DVP_INT_SERR +*\*\ - DVP_INT_FMS +*\*\return none. +**/ +void DVP_ClrIntPendingBit(DVP_Module *DVPx, uint32_t DVP_Int) +{ + + if(DVP_Int == DVP_INT_FO) + { + DVPx->INTSTS = (DVP_FLAG_M1FO | DVP_FLAG_M2FO); + } + else if(DVP_Int == DVP_INT_AHBERR) + { + DVPx->INTSTS = (DVP_FLAG_AHBERR1 | DVP_FLAG_AHBERR2); + } + else if(DVP_Int == DVP_INT_MO) + { + DVPx->INTSTS = (DVP_FLAG_M1O | DVP_FLAG_M2O); + } + else + { + DVPx->INTSTS = DVP_Int; + } + +} + +/** +*\*\name DVP_ConfigPixelClockPolarity. +*\*\fun DVP port pixel clock polarity control. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param PLCK_POL (The input parameters must be the following values): +*\*\ - DVP_PIXEL_POLARITY_RISING +*\*\ - DVP_PIXEL_POLARITY_FALLING +*\*\return none. +**/ +void DVP_ConfigPixelClockPolarity(DVP_Module *DVPx, uint32_t PLCK_POL) +{ + + uint32_t tmpregister; + tmpregister = DVPx->PORTCFG; + tmpregister &= DVP_PIXEL_POLARITY_MASK; + tmpregister |= PLCK_POL; + DVPx->PORTCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_ConfigHSyncPolarity. +*\*\fun DVP HSYNC polarity control. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param HSYNC_POL (The input parameters must be the following values): +*\*\ - DVP_HSYNC_POLARITY_HIGH +*\*\ - DVP_HSYNC_POLARITY_LOW +*\*\return none. +**/ +void DVP_ConfigHSyncPolarity(DVP_Module *DVPx, uint32_t HSYNC_POL) +{ + + uint32_t tmpregister; + tmpregister = DVPx->PORTCFG; + tmpregister &= DVP_HSYNC_POLARITY_MASK; + tmpregister |= HSYNC_POL; + DVPx->PORTCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_ConfigVSyncPolarity. +*\*\fun DVP VSYNC polarity control. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param VSYNC_POL (The input parameters must be the following values): +*\*\ - DVP_VSYNC_POLARITY_HIGH +*\*\ - DVP_VSYNC_POLARITY_LOW +*\*\return none. +**/ +void DVP_ConfigVSyncPolarity(DVP_Module *DVPx, uint32_t VSYNC_POL) +{ + + uint32_t tmpregister; + tmpregister = DVPx->PORTCFG; + tmpregister &= DVP_VSYNC_POLARITY_MASK; + tmpregister |= VSYNC_POL; + DVPx->PORTCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_EnableDataInvert. +*\*\fun DVP data inversion enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableDataInvert(DVP_Module *DVPx, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + DVPx->PORTCFG |= (uint32_t)DVP_DATA_INVERT; + } + else + { + DVPx->PORTCFG &= DVP_DATA_INVERT_MASK; + } + +} + +/** +*\*\name DVP_EnableDataReverse. +*\*\fun DVP data Reverse enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableDataReverse(DVP_Module *DVPx, FunctionalState Cmd) +{ + + + if (Cmd != DISABLE) + { + DVPx->PORTCFG |= DVP_DATA_REVERSE; + } + else + { + DVPx->PORTCFG &= DVP_DATA_REVERSE_MASK; + } +} + + +/** +*\*\name DVP_ConfigEmbSyncPos. +*\*\fun Embedded Synchronization Code Position. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param SYNC_Pos (The input parameters must be the following values): +*\*\ - DVP_EMBSYNC_LSB +*\*\ - DVP_EMBSYNC_MSB +*\*\return none. +**/ +void DVP_ConfigEmbSyncPos(DVP_Module *DVPx, uint32_t SYNC_Pos) +{ + + uint32_t tmpregister; + tmpregister = DVPx->PORTCFG; + tmpregister &= DVP_EMBSYNC_POS_MASK; + tmpregister |= SYNC_Pos; + DVPx->PORTCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_ConfigEmbSyncData. +*\*\fun Embedded Synchronization Code Position. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param FrameStartValue/FrameEndValue/LineStartValue/LineEndValue (The input parameters must be the following values): +*\*\ - 0x00 ~ 0xFF +*\*\return none. +**/ +void DVP_ConfigEmbSyncData(DVP_Module *DVPx, uint8_t FrameStartValue, uint8_t FrameEndValue, uint8_t LineStartValue, uint8_t LineEndValue) +{ + + uint32_t temp_value; + temp_value = ((uint32_t)FrameStartValue | ((uint32_t)FrameEndValue << 8) + | ((uint32_t)LineStartValue << 16) | ((uint32_t)LineEndValue << 24)); + DVPx->EMSC |= temp_value; + +} + +/** +*\*\name DVP_ConfigEmbSyncDataMask. +*\*\fun Embedded Synchronization Code Position. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param FrameStartMask/FrameEndMask/LineStartMask/LineEndMask (The input parameters must be the following values): +*\*\ - 0x00 ~ 0xFF +*\*\return none. +**/ +void DVP_ConfigEmbSyncDataMask(DVP_Module *DVPx, uint8_t FrameStartMask, uint8_t FrameEndMask, uint8_t LineStartMask, uint8_t LineEndMask) +{ + + uint32_t temp_value; + temp_value = ((uint32_t)FrameStartMask | ((uint32_t)FrameEndMask << 8) + | ((uint32_t)LineStartMask << 16) | ((uint32_t)LineEndMask << 24)); + DVPx->EMSCM |= temp_value; + +} + +/** +*\*\name DVP_EnableEmbSyncMode. +*\*\fun Embedded Synchronization Mode enable bit. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableEmbSyncMode(DVP_Module *DVPx, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + DVPx->PORTCFG |= DVP_SYNC_MODE_SOFTWARE; + } + else + { + DVPx->PORTCFG &= DVP_EMBSYNC_MASK; + } + +} + +/** +*\*\name DVP_ConfigDataMode. +*\*\fun Config DVP data port mode. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Mode (The input parameters must be the following values): +*\*\ - DVP_DATA_MODE1 +*\*\ - DVP_DATA_MODE2 +*\*\ - DVP_DATA_MODE3 +*\*\ - DVP_DATA_MODE4 +*\*\ - DVP_DATA_MODE5 +*\*\ - DVP_DATA_MODE6 +*\*\ - DVP_DATA_MODE7 +*\*\ - DVP_DATA_MODE8 +*\*\return none. +**/ +void DVP_ConfigDataMode(DVP_Module *DVPx, uint32_t Mode) +{ + + uint32_t tmpregister; + tmpregister = DVPx->PORTCFG; + tmpregister &= DVP_DATA_MODE_MASK; + tmpregister |= Mode; + DVPx->PORTCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_ConfigPixelByte. +*\*\fun Config DVP pixel bytes. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Pixel_Byte (The input parameters must be the following values): +*\*\ - DVP_PIXEL_BYTE1 +*\*\ - DVP_PIXEL_BYTE2 +*\*\return none. +**/ +void DVP_ConfigPixelByte(DVP_Module *DVPx, uint32_t Pixel_Byte) +{ + + uint32_t tmpregister; + tmpregister = DVPx->PORTCFG; + tmpregister &= DVP_PIXEL_BYTE_MASK; + tmpregister |= Pixel_Byte; + DVPx->PORTCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_ConfigDATAByteOrder. +*\*\fun Config DVP DATA order. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Byte0 (The input parameters must be the following values): +*\*\ - DVP_BYTE0_ORDER1 +*\*\ - DVP_BYTE0_ORDER2 +*\*\ - DVP_BYTE0_ORDER3 +*\*\ - DVP_BYTE0_ORDER4 +*\*\param Byte1 (The input parameters must be the following values): +*\*\ - DVP_BYTE1_ORDER1 +*\*\ - DVP_BYTE1_ORDER2 +*\*\ - DVP_BYTE1_ORDER3 +*\*\ - DVP_BYTE1_ORDER4 +*\*\param Byte2 (The input parameters must be the following values): +*\*\ - DVP_BYTE2_ORDER1 +*\*\ - DVP_BYTE2_ORDER2 +*\*\ - DVP_BYTE2_ORDER3 +*\*\ - DVP_BYTE2_ORDER4 +*\*\param Byte3 (The input parameters must be the following values): +*\*\ - DVP_BYTE3_ORDER1 +*\*\ - DVP_BYTE3_ORDER2 +*\*\ - DVP_BYTE3_ORDER3 +*\*\ - DVP_BYTE3_ORDER4 +*\*\return none. +**/ +void DVP_ConfigDATAByteOrder(DVP_Module *DVPx, uint32_t Byte0, uint32_t Byte1, uint32_t Byte2, uint32_t Byte3) +{ + + uint32_t temp_value; + temp_value = (Byte0 | Byte1 | Byte2 | Byte3); + DVPx->PORTCFG &= DVP_BYTE_ORDER_MASK; + DVPx->PORTCFG |= temp_value; + +} + +/** +*\*\name DVP_ConfigInitSKIP. +*\*\fun Config Initial Frame Line Skip . +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Line (The input parameters must be the following values): +*\*\ - DVP_SKIP_LINE1 +*\*\ - DVP_SKIP_LINE2 +*\*\ - DVP_SKIP_LINE3 +*\*\ - DVP_SKIP_LINE4 +*\*\ - DVP_SKIP_LINE5 +*\*\ - DVP_SKIP_LINE6 +*\*\ - DVP_SKIP_LINE7 +*\*\ - DVP_SKIP_LINE8 +*\*\ - DVP_SKIP_LINE9 +*\*\ - DVP_SKIP_LINE10 +*\*\ - DVP_SKIP_LINE11 +*\*\ - DVP_SKIP_LINE12 +*\*\ - DVP_SKIP_LINE13 +*\*\ - DVP_SKIP_LINE14 +*\*\ - DVP_SKIP_LINE15 +*\*\return none. +**/ +void DVP_ConfigInitSKIP(DVP_Module *DVPx, uint32_t Line) +{ + + uint32_t temp_value; + temp_value = (uint32_t)(Line << 24); + DVPx->PORTCFG &= DVP_ISKIP_MASK; + DVPx->PORTCFG |= temp_value; + +} + +/** +*\*\name DVP_ConfigRepeatSKIP. +*\*\fun Config Repeat Frame Line Skip . +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Line (The input parameters must be the following values): +*\*\ - DVP_SKIP_LINE1 +*\*\ - DVP_SKIP_LINE2 +*\*\ - DVP_SKIP_LINE3 +*\*\ - DVP_SKIP_LINE4 +*\*\ - DVP_SKIP_LINE5 +*\*\ - DVP_SKIP_LINE6 +*\*\ - DVP_SKIP_LINE7 +*\*\ - DVP_SKIP_LINE8 +*\*\ - DVP_SKIP_LINE9 +*\*\ - DVP_SKIP_LINE10 +*\*\ - DVP_SKIP_LINE11 +*\*\ - DVP_SKIP_LINE12 +*\*\ - DVP_SKIP_LINE13 +*\*\ - DVP_ODD_LINE +*\*\ - DVP_EVEN_LINE +*\*\return none. +**/ +void DVP_ConfigRepeatSKIP(DVP_Module *DVPx, uint32_t Line) +{ + + uint32_t temp_value; + temp_value = (uint32_t)(Line << 28); + DVPx->PORTCFG &= DVP_RSKIP_MASK; + DVPx->PORTCFG |= temp_value; + +} + +/** +*\*\name DVP_EnableBuffer1. +*\*\fun Frame Buffer 1 enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableBuffer1(DVP_Module *DVPx, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + DVPx->FIFOCFG |= DVP_BUFFER1; + } + else + { + DVPx->FIFOCFG &= DVP_BUFFER1_MASK; + } + +} + +/** +*\*\name DVP_SetBuffer1Address. +*\*\fun Set Frame Buffer 1 Start Address. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Addres:(The input parameters must be the following values) +*\*\ - 0x00000000~0xFFFFFFFF +*\*\return none +**/ +void DVP_SetBuffer1Address(DVP_Module *DVPx, uint32_t Addres) +{ + + DVPx->SMADDR1 = (uint32_t)Addres; + +} + +/** +*\*\name DVP_EnableBuffer2. +*\*\fun Frame Buffer 2 enable. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableBuffer2(DVP_Module *DVPx, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + DVPx->FIFOCFG |= DVP_BUFFER2; + } + else + { + DVPx->FIFOCFG &= DVP_BUFFER2_MASK; + } + +} + +/** +*\*\name DVP_SetBuffer2Address. +*\*\fun Set Frame Buffer 2 Start Address. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Addres:(The input parameters must be the following values) +*\*\ - 0x00000000~0xFFFFFFFF +*\*\return none +**/ +void DVP_SetBuffer2Address(DVP_Module *DVPx, uint32_t Addres) +{ + + DVPx->SMADDR2 = (uint32_t)Addres; + +} + +/** +*\*\name DVP_SetBufferSize. +*\*\fun Set Frame Buffer Size. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Size:(The input parameters must be the following values) +*\*\ - 0 ~ 4194303 +*\*\return none +**/ +void DVP_SetBufferSize(DVP_Module *DVPx, uint32_t Size) +{ + + DVPx->FBS = (uint32_t)Size; + +} + +/** +*\*\name DVP_SetDisplayBufferStatus. +*\*\fun Set show current frame buffer status. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param State_Mode:(The input parameters must be the following values) +*\*\ - DVP_DISPLAY_ADDRESS +*\*\ - DVP_DISPLAY_NUMBER +*\*\return none +**/ +void DVP_SetDisplayBufferStatus(DVP_Module *DVPx, uint32_t State_Mode) +{ + + uint32_t tmpregister; + tmpregister = DVPx->FIFOCFG; + tmpregister &= DVP_DISPLAY_STATUS_MASK; + tmpregister |= State_Mode; + DVPx->FIFOCFG = (uint32_t)tmpregister; + +} + +/** +*\*\name DVP_GetDisplayBufferStatus1. +*\*\fun Get current frame buffer 1 status. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\return Frame Buffer 1 address or Number of data bytes +**/ +uint32_t DVP_GetDisplayBufferStatus1(DVP_Module *DVPx) +{ + + return DVPx->FPBC1; + +} + +/** +*\*\name DVP_GetDisplayBufferStatus2. +*\*\fun Get current frame buffer 2 status. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\return Frame Buffer 2 address or Number of data bytes +**/ +uint32_t DVP_GetDisplayBufferStatus2(DVP_Module *DVPx) +{ + + return DVPx->FPBC2; + +} + +/** +*\*\name DVP_EnableAcross1KBoundary. +*\*\fun Increamental bursting across 1K boundary is allowed/enabled +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void DVP_EnableAcross1KBoundary(DVP_Module *DVPx, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + DVPx->FIFOCFG |= DVP_1K_BOUNDARY_ENABLE; + } + else + { + DVPx->FIFOCFG &= DVP_1K_BOUNDARY_MASK; + } + +} + +/** +*\*\name DVP_ConfigCROPStart. +*\*\fun Config Y-coordinate and X-coordinate of crop image start point. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param (X,Y):(The input parameters must be the following values) +*\*\ - (0,0) ~ (2047,2047) +*\*\return none +**/ +void DVP_ConfigCROPStart(DVP_Module *DVPx, uint16_t X, uint16_t Y) +{ + + DVPx->CSXY = DVP_REG_BIT_FIELD_MASK; + DVPx->CSXY |= X; + DVPx->CSXY |= ((uint32_t)Y << 16); + +} + +/** +*\*\name DVP_ConfigCROPEnd. +*\*\fun Config Y-coordinate and X-coordinate of crop image end point. +*\*\param DVPx: +*\*\ - DVP1 +*\*\ - DVP2 +*\*\param (X,Y):(The input parameters must be the following values) +*\*\ - (0,0) ~ (2047,2047) +*\*\return none +**/ +void DVP_ConfigCROPEnd(DVP_Module *DVPx, uint16_t X, uint16_t Y) +{ + + DVPx->CEXY = DVP_REG_BIT_FIELD_MASK; + DVPx->CEXY |= X; + DVPx->CEXY |= ((uint32_t)Y << 16); + +} + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eccmon.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eccmon.c new file mode 100644 index 0000000000..86b83dce89 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eccmon.c @@ -0,0 +1,869 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_eccmon.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_eccmon.h" + +/** +*\*\brief Get ECCMON Monitor Type +*\*\param ECCON_OneMemType ECCMON One Memory Type ,can'T |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\return ECCMON_MonitorType Monitor Unit and Index for the MemType +**/ +static ECCMON_MonitorType ECCMON_GetMonitorType(uint32_t ECCON_OneMemType) +{ + ECCMON_MonitorType oneMonitor; + + switch (ECCON_OneMemType) + { + case ECCMON_AXI_SRAM1: + oneMonitor.MonitorUnit = ECCMON1P1; + oneMonitor.MonitorIndex = 1; + break; + + case ECCMON_AXI_SRAM2: + oneMonitor.MonitorUnit = ECCMON1P2; + oneMonitor.MonitorIndex = 0; + break; + + case ECCMON_AXI_SRAM3: + oneMonitor.MonitorUnit = ECCMON1P2; + oneMonitor.MonitorIndex = 1; + break; + + case ECCMON_ITCM: + oneMonitor.MonitorUnit = ECCMON1P3; + oneMonitor.MonitorIndex = 0; + break; + + case ECCMON_D0TCM: + oneMonitor.MonitorUnit = ECCMON1P4; + oneMonitor.MonitorIndex = 0; + break; + + case ECCMON_D1TCM: + oneMonitor.MonitorUnit = ECCMON1P4; + oneMonitor.MonitorIndex = 1; + break; + + case ECCMON_AHB_SRAM1: + oneMonitor.MonitorUnit = ECCMON2; + oneMonitor.MonitorIndex = 0; + break; + + case ECCMON_AHB_SRAM2: + oneMonitor.MonitorUnit = ECCMON2; + oneMonitor.MonitorIndex = 1; + break; + + case ECCMON_AHB_SRAM3: + oneMonitor.MonitorUnit = ECCMON2; + oneMonitor.MonitorIndex = 2; + break; + + case ECCMON_AHB_SRAM4: + oneMonitor.MonitorUnit = ECCMON2; + oneMonitor.MonitorIndex = 3; + break; + + case ECCMON_AHB_SRAM5_BANK1: + oneMonitor.MonitorUnit = ECCMON2; + oneMonitor.MonitorIndex = 4; + break; + + case ECCMON_AHB_SRAM5_BANK2: + oneMonitor.MonitorUnit = ECCMON2; + oneMonitor.MonitorIndex = 5; + break; + + case ECCMON_BACKUP_SRAM: + oneMonitor.MonitorUnit = ECCMON3; + oneMonitor.MonitorIndex = 0; + break; + + default: + break; + } + + return oneMonitor; +} + +/** +*\*\brief Initialize the ECCMON structure +*\*\param ECCMON_InitStruct ECCMON handle +*\*\ -MemType +*\*\ -CaptureSelect +*\*\ -ErrFlagOut +*\*\return none +**/ +void ECCMON_StructInit(ECCMON_InitType* ECCMON_InitStruct) +{ + ECCMON_InitStruct->MemType = ECCMON_NONE_SRAM; + ECCMON_InitStruct->CaptureSelect = ECCMON_CAPTURE_1_2BIT_ERROR; + ECCMON_InitStruct->ErrFlagOut = ECCMON_NO_ERROR_FLAG_OUT; +} + +/** +*\*\brief Initialize the ECCMON according to the specified parameters in the ECCMON_InitType. +*\*\param ECCMON_InitStruct ECCMON handle +*\*\ -MemType +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\ -CaptureSelect +*\*\ -ECCMON_CAPTURE_1_2BIT_ERROR +*\*\ -ECCMON_CAPTURE_1BIT_ERROR +*\*\ -ECCMON_CAPTURE_2BIT_ERROR +*\*\ -ECCMON_CAPTURE_NONE_ERROR +*\*\ -ErrFlagOut +*\*\ -ECCMON_NO_ERROR_FLAG_OUT +*\*\ -ECCMON_1BIT_ERROR_FLAG_OUT +*\*\ -ECCMON_2BIT_ERROR_FLAG_OUT +*\*\ -ECCMON_1_2BIT_ERROR_FLAG_OUT +*\*\return none +**/ +void ECCMON_Init(ECCMON_InitType* ECCMON_InitStruct) +{ + ECCMON_MonitorType oneMonitorType; + + for (uint8_t index = 0; index < 14U; index++) + { + if ((ECCMON_InitStruct->MemType & (1UL << index)) != 0x00UL) + { + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_InitStruct->MemType & (1UL << index)); + //set capture select + oneMonitorType.MonitorUnit->EINJ &= ~(ECCMON_CAPTURE_NONE_ERROR << (oneMonitorType.MonitorIndex * 2UL)); + oneMonitorType.MonitorUnit->EINJ |= ECCMON_InitStruct->CaptureSelect << (oneMonitorType.MonitorIndex * 2UL); + + //set eror flag out to FLAG_EN_OT + if ((ECCMON_InitStruct->ErrFlagOut & 0x01UL) != 0x00UL) + { + oneMonitorType.MonitorUnit->CTRL2 |= ECCMON_CTRL2_E1FOEN1 << oneMonitorType.MonitorIndex; + } + else + { + oneMonitorType.MonitorUnit->CTRL2 &= ~(ECCMON_CTRL2_E1FOEN1 << oneMonitorType.MonitorIndex); + } + + if ((ECCMON_InitStruct->ErrFlagOut & 0x02UL) != 0x00UL) + { + oneMonitorType.MonitorUnit->CTRL2 |= ECCMON_CTRL2_E2FOEN1 << oneMonitorType.MonitorIndex; + } + else + { + oneMonitorType.MonitorUnit->CTRL2 &= ~(ECCMON_CTRL2_E2FOEN1 << oneMonitorType.MonitorIndex); + } + } + + } + +} +/** +*\*\brief Initialize the ECCMON interrupt +*\*\param ECCMON_MemType ECCMON Memory Type ,can |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_IntType ECCMON intertupt Type +*\*\ -ECCMON_1BIT_ERROR_INT +*\*\ -ECCMON_2BIT_ERROR_INT +*\*\ -ECCMON_1_2BIT_ERROR_INT +*\*\return none +**/ +void ECCMON_ConfigInt(uint32_t ECCMON_MemType, uint32_t ECCMON_IntType) +{ + ECCMON_MonitorType oneMonitorType; + + for (uint8_t index = 0; index < 14U; index++) + { + if ((ECCMON_MemType & (1UL << index)) != 0x00UL) + { + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType & (1UL << index)); + + //set eror interrupt + if ((ECCMON_IntType & 0x01UL) != 0x00UL) + { + oneMonitorType.MonitorUnit->CTRL1 |= ECCMON_CTRL1_E1INTEN1 << oneMonitorType.MonitorIndex; + } + else + { + oneMonitorType.MonitorUnit->CTRL1 &= ~(ECCMON_CTRL1_E1INTEN1 << oneMonitorType.MonitorIndex); + } + + if ((ECCMON_IntType & 0x02UL) != 0x00UL) + { + oneMonitorType.MonitorUnit->CTRL1 |= ECCMON_CTRL1_E2INTEN1 << oneMonitorType.MonitorIndex; + } + else + { + oneMonitorType.MonitorUnit->CTRL1 &= ~(ECCMON_CTRL1_E2INTEN1 << oneMonitorType.MonitorIndex); + } + + } + + } +} + +/** +*\*\brief Inject Error for test +*\*\param ECCMON_MemType ECCMON Memory Type ,can |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_InjectType ECCMON Inject Type +*\*\ -ECCMON_NO_INJECT +*\*\ -ECCMON_INJECT_1BIT +*\*\ -ECCMON_INJECT_2BIT +*\*\return none +**/ +void ECCMON_InjectError(uint32_t ECCMON_MemType, uint32_t ECCMON_InjectType) +{ + ECCMON_MonitorType oneMonitorType; + + for (uint8_t index = 0; index < 14U; index++) + { + if ((ECCMON_MemType & (1UL << index)) != 0x00UL) + { + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType & (1UL << index)); + + //set eror inject + oneMonitorType.MonitorUnit->EINJ &= ~(ECCMON_INJECT_MASK << (2UL * oneMonitorType.MonitorIndex)); + oneMonitorType.MonitorUnit->EINJ |= ECCMON_InjectType << (2UL * oneMonitorType.MonitorIndex); + } + + } +} +/** +*\*\brief set Temporary data register bypass +*\*\ temporary data register is used to temporarily store read-modify-write data on partial write access +*\*\ the temporary data register is bypassed, the read-modify-write data is written back the memory +*\*\param ECCMON_MemType ECCMON Memory Type ,can |(or) operation +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\param FunctionalState Cmd +*\*\ -DISABLE +*\*\ -ENABLE +*\*\return none +**/ +void ECCMON_SetBypassTempRegister(uint32_t ECCMON_MemType, FunctionalState Cmd) +{ + ECCMON_MonitorType oneMonitorType; + + for (uint8_t index = 0; index < 14U; index++) + { + if ((ECCMON_MemType & (1UL << index)) != 0x00UL) + { + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType & (1UL << index)); + + if (Cmd != DISABLE) + { + //set bypass + oneMonitorType.MonitorUnit->CTRL1 |= ECCMON_CTRL1_TDRBYP1 << oneMonitorType.MonitorIndex; + } + else + { + oneMonitorType.MonitorUnit->CTRL1 &= ~(ECCMON_CTRL1_TDRBYP1 << oneMonitorType.MonitorIndex); + } + } + + } + +} + +/** +*\*\brief set Partial write on ECC 2-bit enable or disable +*\*\ allow or don't allow partial write to perform read-modify-write to the memory while ECC 2-bit error is detected. +*\*\param ECCMON_MemType ECCMON Memory Type ,can |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param FunctionalState Cmd +*\*\ -DISABLE +*\*\ -ENABLE +*\*\return none +**/ +void ECCMON_SetWriteOn2Bit(uint32_t ECCMON_MemType, FunctionalState Cmd) +{ + ECCMON_MonitorType oneMonitorType; + + for (uint8_t index = 0; index < 14U; index++) + { + if ((ECCMON_MemType & (1UL << index)) != 0x00UL) + { + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType & (1UL << index)); + + if (Cmd != DISABLE) + { + //set write on ECC 2-bit enable + oneMonitorType.MonitorUnit->CTRL2 |= ECCMON_CTRL2_WROE2EN1 << oneMonitorType.MonitorIndex; + } + else + { + oneMonitorType.MonitorUnit->CTRL2 &= ~(ECCMON_CTRL2_WROE2EN1 << oneMonitorType.MonitorIndex); + } + } + + } + +} +/** +*\*\brief set enable ECCMON +*\*\param ECCMON_MemType ECCMON Memory Type ,can |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ECCMON_Enable(uint32_t ECCMON_MemType, FunctionalState Cmd) +{ + ECCMON_MonitorType oneMonitorType; + + for (uint8_t index = 0; index < 14U; index++) + { + if ((ECCMON_MemType & (1UL << index)) != 0x00UL) + { + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType & (1UL << index)); + + if (Cmd != DISABLE) + { + //set ECC enable + oneMonitorType.MonitorUnit->CTRL1 |= ECCMON_CTRL1_ECCEN1 << oneMonitorType.MonitorIndex; + } + else + { + //set ECC enable + oneMonitorType.MonitorUnit->CTRL1 &= ~(ECCMON_CTRL1_ECCEN1 << oneMonitorType.MonitorIndex); + } + } + + } +} +/** +*\*\brief set enable ECCMON CLOCK +*\*\param none +*\*\return none +**/ +void ECCMON_EnableClk(void) +{ + /**note:No matter which ECCMON you want to use, you need to enable the three ECCMON clocks***/ + RCC_EnableAXIPeriphClk1(RCC_AXI_PERIPHEN_M7_ECCM1 | RCC_AXI_PERIPHEN_M4_ECCM1, ENABLE); + RCC_EnableAHB2PeriphClk1(RCC_AHB2_PERIPHEN_M7_ECCM2 | RCC_AHB2_PERIPHEN_M4_ECCM2, ENABLE); + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_ECCM3 | RCC_AHB5_PERIPHEN_M4_ECCM3, ENABLE); + +} +/** +*\*\brief Get the ECCMON Fail Address +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\return FailAddress +**/ +uint32_t ECCMON_GetFailAddress(uint32_t ECCMON_MemType) +{ + uint32_t readAddr, FailAddress ; + ECCMON_MonitorType oneMonitorType; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + + /* read Fail Address */ + readAddr = (*((&oneMonitorType.MonitorUnit->FEADR1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex))) & 0xFFFFFFFUL; + + //shift left by 2 bit for 32-bit memory, and shift left by 3 bit for 64-bit memory + switch (ECCMON_MemType) + { + case ECCMON_AXI_SRAM1://64 bit data + FailAddress = AXI_SRAM1_BASE_ADDR + (readAddr << 3); + break; + + case ECCMON_AXI_SRAM2://64 bit data + FailAddress = AXI_SRAM2_BASE_ADDR + (readAddr << 3); + break; + + case ECCMON_AXI_SRAM3://64 bit data + FailAddress = AXI_SRAM3_BASE_ADDR + (readAddr << 3); + break; + + case ECCMON_ITCM://64 bit data + FailAddress = ITCM_BASE_ADDR + (readAddr << 3); + break; + + case ECCMON_D0TCM://32 bit data + FailAddress = DTCM_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_D1TCM://32 bit data + FailAddress = DTCM_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_AHB_SRAM1://32 bit data + FailAddress = AHB_SRAM1_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_AHB_SRAM2://32 bit data + FailAddress = AHB_SRAM2_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_AHB_SRAM3://32 bit data + FailAddress = AHB_SRAM3_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_AHB_SRAM4://32 bit data + FailAddress = AHB_SRAM4_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_AHB_SRAM5_BANK1://32 bit data + FailAddress = AHB_SRAM5_BANK1_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_AHB_SRAM5_BANK2://32 bit data + FailAddress = AHB_SRAM5_BANK2_BASE_ADDR + (readAddr << 2); + break; + + case ECCMON_BACKUP_SRAM://32 bit data + FailAddress = BACKUP_SRAM_BASE_ADDR + (readAddr << 2); + break; + + default: + FailAddress = readAddr; + break; + } + + return FailAddress; +} +/** +*\*\brief Get the ECCMON Fail Data Low +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\return Fail Data Low +**/ +uint32_t ECCMON_GetFailDataLow(uint32_t ECCMON_MemType) +{ + ECCMON_MonitorType oneMonitorType; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + /* Return Fail Address */ + return (uint32_t) * ((&oneMonitorType.MonitorUnit->FEDATL1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex)); +} + +/** +*\*\brief Get the ECCMON Fail Data High +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\return Fail Data High +**/ +uint32_t ECCMON_GetFailDataHigh(uint32_t ECCMON_MemType) +{ + ECCMON_MonitorType oneMonitorType; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + /* Return Fail Address */ + return (uint32_t) * ((&oneMonitorType.MonitorUnit->FEDATH1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex)); +} + +/** +*\*\brief Get the ECCMON Fail ECC code +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\return Fail ECC code +**/ +uint32_t ECCMON_GetFailErrorCode(uint32_t ECCMON_MemType) +{ + ECCMON_MonitorType oneMonitorType; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + /* Return Fail Address */ + return (uint32_t) * ((&oneMonitorType.MonitorUnit->FECOD1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex)); +} + +/** +*\*\brief Get the ECCMON error context Flag +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_ERR_CONTEXT_FLAG +*\*\ -ECCMON_ERR_CONTEXT_FLAG_E1EAD +*\*\ -ECCMON_ERR_CONTEXT_FLAG_E2EAD +*\*\return Fail ECC code +**/ +FlagStatus ECCMON_GetErrorContextFlagStatus(uint32_t ECCMON_MemType, uint32_t ECCMON_ERR_CONTEXT_FLAG) +{ + FlagStatus bitstatus; + ECCMON_MonitorType oneMonitorType; + uint32_t registerFlag; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + + registerFlag = (uint32_t) * ((&oneMonitorType.MonitorUnit->FEADR1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex)); + + if ((registerFlag & ECCMON_ERR_CONTEXT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\brief Clear ECCMON error context Flag +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_ERR_CONTEXT_FLAG +*\*\ -ECCMON_ERR_CONTEXT_FLAG_E1EAD +*\*\ -ECCMON_ERR_CONTEXT_FLAG_E2EAD +*\*\return Fail ECC code +**/ +void ECCMON_ClrErrorContextFlag(uint32_t ECCMON_MemType, uint32_t ECCMON_ERR_CONTEXT_FLAG) +{ + ECCMON_MonitorType oneMonitorType; + __IO uint32_t *oneRegister; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + //get ECCMON_INTFx, x=oneMonitorType.MonitorIndex + oneRegister = (__IO uint32_t *)(&oneMonitorType.MonitorUnit->FEADR1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex); + + *oneRegister |= ECCMON_ERR_CONTEXT_FLAG; + +} + + +/** +*\*\brief Get the ECCMON Interrupt Flag +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_FLAG +*\*\ -ECCMON_FLAG_E1DCIFW +*\*\ -ECCMON_FLAG_E2DCIFW +*\*\ -ECCMON_FLAG_E1DCIFR +*\*\ -ECCMON_FLAG_E2DCIFR +*\*\return Fail ECC code +**/ +FlagStatus ECCMON_GetFlagStatus(uint32_t ECCMON_MemType, uint32_t ECCMON_FLAG) +{ + FlagStatus bitstatus; + ECCMON_MonitorType oneMonitorType; + uint32_t registerFlag; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + //get ECCMON_INTFx, x=oneMonitorType.MonitorIndex + registerFlag = (uint32_t) * ((&oneMonitorType.MonitorUnit->INTF1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex)); + + if ((registerFlag & ECCMON_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\brief Clear the ECCMON Interrupt Flag +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_FLAG +*\*\ -ECCMON_FLAG_E1DCIFW +*\*\ -ECCMON_FLAG_E2DCIFW +*\*\ -ECCMON_FLAG_E1DCIFR +*\*\ -ECCMON_FLAG_E2DCIFR +*\*\return Fail ECC code +**/ +void ECCMON_ClrFlag(uint32_t ECCMON_MemType, uint32_t ECCMON_FLAG) +{ + ECCMON_MonitorType oneMonitorType; + __IO uint32_t *oneRegister; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + //get ECCMON_INTFx, x=oneMonitorType.MonitorIndex + oneRegister = (__IO uint32_t *)(&oneMonitorType.MonitorUnit->INTF1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex); + + *oneRegister = ECCMON_FLAG; + +} +/** +*\*\brief Get the ECCMON Interrupt Flag +*\*\param ECCMON_MemType ECCMON Memory Type ,can not |(or) operation +*\*\ -ECCMON_AXI_SRAM1 +*\*\ -ECCMON_AXI_SRAM2 +*\*\ -ECCMON_AXI_SRAM3 +*\*\ -ECCMON_ITCM +*\*\ -ECCMON_D0TCM +*\*\ -ECCMON_D1TCM +*\*\ -ECCMON_AHB_SRAM1 +*\*\ -ECCMON_AHB_SRAM2 +*\*\ -ECCMON_AHB_SRAM3 +*\*\ -ECCMON_AHB_SRAM4 +*\*\ -ECCMON_AHB_SRAM5_BANK1 +*\*\ -ECCMON_AHB_SRAM5_BANK2 +*\*\ -ECCMON_BACKUP_SRAM +*\*\param ECCMON_INT +*\*\ -ECCMON_INT_E1DCIFW +*\*\ -ECCMON_INT_E2DCIFW +*\*\ -ECCMON_INT_E1DCIFR +*\*\ -ECCMON_INT_E2DCIFR +*\*\return Fail ECC code +**/ +INTStatus ECCMON_GetIntStatus(uint32_t ECCMON_MemType, uint32_t ECCMON_INT) +{ + FlagStatus bitstatus = RESET; + ECCMON_MonitorType oneMonitorType; + uint32_t registerFlag; + //Get ECCMON Monitor unit and index + oneMonitorType = ECCMON_GetMonitorType(ECCMON_MemType); + //get ECCMON_INTFx, x=oneMonitorType.MonitorIndex + registerFlag = (uint32_t) * ((&oneMonitorType.MonitorUnit->INTF1) + (ECCMON_GROUP_REG_ADDR_GAP * oneMonitorType.MonitorIndex)); + + //judge ECCMON_INT_E1DCIFW|ECCMON_INT_E1DCIFR and ECC 1-bit Error interrupt enable or disable + if (((ECCMON_INT & (ECCMON_INT_E1DCIFW | ECCMON_INT_E1DCIFR)) != 0x00UL) && + ((oneMonitorType.MonitorUnit->CTRL1 & (ECCMON_CTRL1_E1INTEN1 << oneMonitorType.MonitorIndex)) != 0x00UL)) + { + if ((registerFlag & ECCMON_INT) != 0x00UL) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + //judge ECCMON_INT_E2DCIFW|ECCMON_INT_E2DCIFR and ECC 2-bit Error interrupt enable or disable + if (((ECCMON_INT & (ECCMON_INT_E2DCIFW | ECCMON_INT_E2DCIFR)) != 0x00UL) && + ((oneMonitorType.MonitorUnit->CTRL1 & (ECCMON_CTRL1_E2INTEN1 << oneMonitorType.MonitorIndex)) != 0x00UL)) + { + if ((registerFlag & ECCMON_INT) != 0x00UL) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eth.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eth.c new file mode 100644 index 0000000000..69f3e97a54 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_eth.c @@ -0,0 +1,4988 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_eth.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_eth.h" + +/** ETH Private Defines **/ + +/* ETH Register MASK macro definition */ +#define ETH1_MACCFG_MASK ((uint32_t)0xFFFFFF7CU) +#define ETH2_MACCFG_MASK ((uint32_t)0xFFFB7F7CU) +#define ETH_MACEXTCFG_MASK ((uint32_t)0x7F073FFFU) +#define ETH_MACPFLT_MASK ((uint32_t)0x803107FFU) +#define ETH_MACWDGTO_MASK ((uint32_t)0x0000010FU) +#define ETH_MACTXFLWCTRL_MASK ((uint32_t)0xFFFF00F2U) +#define ETH_MACRXFLWCTRL_MASK ((uint32_t)0x00000003U) +#define ETH_MTLTXQOPMOD_MASK ((uint32_t)0x00000072U) +#define ETH_MTLRXQOPMOD_MASK ((uint32_t)0x0000007BU) +#define ETH_DMAMODE_MASK ((uint32_t)0x00087802U) +#define ETH_DMASBMODE_MASK ((uint32_t)0x0000D001U) +#define ETH_DMACH0CTRL_MASK ((uint32_t)0x001D3FFFU) +#define ETH_DMACH0TXCTRL_MASK ((uint32_t)0x007F1010U) +#define ETH_DMACH0RXCTRL_MASK ((uint32_t)0x807F0000U) +#define ETH_MACVLANTAG_MASK ((uint32_t)0x037FFFFFU) + +#define ETH_RXBUFFERSIZE_MASK ((uint32_t)0x00007FFEU) + +/* ETH MAC CSR Clock Frequency macro definition */ +#define ETH_MACCSR_CLOCK_FREQ_20M ((uint32_t)20000000U) +#define ETH_MACCSR_CLOCK_FREQ_35M ((uint32_t)35000000U) +#define ETH_MACCSR_CLOCK_FREQ_60M ((uint32_t)60000000U) +#define ETH_MACCSR_CLOCK_FREQ_100M ((uint32_t)100000000U) +#define ETH_MACCSR_CLOCK_FREQ_150M ((uint32_t)150000000U) +#define ETH_MACCSR_CLOCK_FREQ_250M ((uint32_t)250000000U) +#define ETH_MACCSR_CLOCK_FREQ_300M ((uint32_t)300000000U) +#define ETH_MACCSR_CLOCK_FREQ_500M ((uint32_t)500000000U) +#define ETH_MACCSR_CLOCK_FREQ_800M ((uint32_t)800000000U) + + +/* ETH Timeout values macro definition */ +#define ETH_SWRESET_TIMEOUT ((uint32_t)0xF0000000U) +#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)0xF0000000U) +#define ETH_PHY_LINKED_TIMEOUT ((uint32_t)0xF0000000U) +#define ETH_PHY_AUTONEGO_COMPLETED_TIMEOUT ((uint32_t)0xF0000000U) + +/* ETH Remote Wake-up Filter register length definition */ +#define ETH_WAKEUP_REGISTER_LEN ((uint32_t)8U) + +/* ETH Delay between consecutive write registers */ +#define ETH_WRITE_REG_DELAY ((uint32_t)5000U) + +/* ETH External PHY Configuration Delay */ +#define ETH_PHY_CONFIG_DELAY ((uint32_t)5000U) + +/* ETH tx descriptor index increment */ +#define __ETH_TXDESC_INDEX_INCR(Index, Offset) do { \ + (Index) += (Offset); \ + if ((Index) >= ETH_TX_DESC_NUMBER) \ + { \ + (Index) = ((Index) - ETH_TX_DESC_NUMBER); \ + } \ + } while (0) +/* ETH rx descriptor index increment */ +#define __ETH_RXDESC_INDEX_INCR(Index, Offset) do { \ + (Index) += (Offset); \ + if ((Index) >= ETH_RX_DESC_NUMBER) \ + { \ + (Index) = ((Index) - ETH_RX_DESC_NUMBER); \ + } \ + } while (0) + +/* ETH Tick&Delay through the DWT module */ +#define __ETH_TICK_START() CPU_DELAY_INTI() +#define __ETH_GET_TICK DWT_CYCCNT +#define __ETH_TICK_STOP() CPU_DELAY_DISABLE() +#define __ETH_DELAY(Cnt) do{ \ + /* Check that DWT is enabled or not */ \ + if ((DEM_CR & DEM_CR_TRCENA) == (uint32_t)RESET) \ + { \ + /* Enable and initialize DWT */ \ + __ETH_TICK_START(); \ + } \ + Cnt += __ETH_GET_TICK; \ + while (__ETH_GET_TICK < Cnt){}; \ + __ETH_TICK_STOP(); \ + } while (0) + +/* ETH MAC μs tick */ +#define ETH_MAC_US_TICK ((uint32_t)1000000U) + + +/** ETH Driving Functions Declaration **/ + +/** +*\*\name ETH_DeInit. +*\*\fun DeInitializes the ETH peripheral. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_DeInit(ETH_Module* ETHx) +{ + /* Check the ETHx parameter */ + if (ETHx == ETH1) + { + /* ETH1 peripheral reset */ + RCC_EnableAHB2PeriphReset1(RCC_AHB2_PERIPHRST_ETH1); + } + else if (ETHx == ETH2) + { + /* ETH2 peripheral reset */ + RCC_EnableAHB1PeriphReset2(RCC_AHB1_PERIPHRST_ETH2); + } + else + { + /* Do nothing */ + } +} + +/** +*\*\name ETH_StructInit. +*\*\fun Initializes the structure parameter of type ETH_InitType used to +*\*\ initialize ETH. This function is usually called before initializing +*\*\ a parameter of type ETH_InitType. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param ETH_InitParam : +*\*\ - Pointer to the ETH_InitType structure which will be initialized. +*\*\return none +**/ +void ETH_StructInit(ETH_Module* ETHx, ETH_InitType* ETH_InitParam) +{ + /** Set the default configuration **/ + + /* Default 7-byte preamble length */ + ETH_InitParam->TxPreambleLen = ETH_PREAMBLE_LEN_7BYTES; + /* Default Disable deferral check function in the half-duplex mode */ + ETH_InitParam->DeferralCheck = DISABLE; + /* Default Back-off time_limit = 10 slot times in the half-duplex mode */ + ETH_InitParam->BackOffLimit = ETH_BACK_OFF_LIMIT_10; + /* Default Enable MAC retry transmission in the half-duplex mode */ + ETH_InitParam->DisTxRetry = DISABLE; + /* Default Enable Carrier Sense During Transmission in the half-duplex mode */ + ETH_InitParam->DisCSDuringTransmit = DISABLE; + /* Default Enable Receive Own in the half-duplex mode */ + ETH_InitParam->DisRxOwn = DISABLE; + /* Default Disable Carrier Sense Before Transmission in the full-duplex mode */ + ETH_InitParam->CSBeforeTransmit = DISABLE; + /* Default Disable Loopback Mode */ + ETH_InitParam->Loopback = DISABLE; + /* Default Half-duplex mode */ + ETH_InitParam->Duplex = ETH_HALF_DUPLEX_MODE; + /* Set the default speed for ETH1/ETH2 */ + if (ETHx == ETH1) + { + /* Default Selects the speed mode: 1000Mbps */ + ETH_InitParam->SpeedSelect = ETH_SPEED_1000M; + } + else + { + /* Default Selects the speed mode: 10Mbps */ + ETH_InitParam->SpeedSelect = ETH_SPEED_10M; + } + /* Default Disable Jumbo Packet */ + ETH_InitParam->JumboPacket = DISABLE; + /* Default Enable Jabber timer on Tx path */ + ETH_InitParam->DisTxJabber = DISABLE; + /* Default Disable Packet Burst, Only ETH1 supports */ + ETH_InitParam->PacketBurst = DISABLE; + /* Default Enable Watchdog timer on Rx path */ + ETH_InitParam->DisRxWatchdog = DISABLE; + /* Default Disable Automatic Pad or CRC Stripping function */ + ETH_InitParam->AutoPadCRCStrip = DISABLE; + /* Default Disable CRC stripping for Type packets function */ + ETH_InitParam->CRCStripTypePacket = DISABLE; + /* Default Disable IEEE 802.3as Support for 2K Packets function */ + ETH_InitParam->Support2KPacket = DISABLE; + /* Default Disable Giant Packet Size Limit Control */ + ETH_InitParam->GiantPacketSizeLimitCtrl = DISABLE; + /* Default 96-bit Inter-Packet Gap */ + ETH_InitParam->InterPacketGapVal = ETH_INTER_PACKET_GAP_96BIT; + /* Default Disable Checksum Offload function */ + ETH_InitParam->ChecksumOffload = DISABLE; + /* Default Internal Signal Control Source Address Field */ + ETH_InitParam->SrcAddrCtrl = ETH_SRC_ADDR_CTRL_INTERNAL_SIGNALS; + /* Default Disable ARP Offload function */ + ETH_InitParam->ARPOffload = DISABLE; + + /* Default Set Giant Packet Size Limit value: 0 */ + ETH_InitParam->GiantPacketSizeLimit = 0U; + /* Default Enable CRC Checking for Rx Packets */ + ETH_InitParam->DisRxPacketCRCCheck = DISABLE; + /* Default Disable Slow Protocol Detection */ + ETH_InitParam->SPDetect = DISABLE; + /* Default Disable Unicast Slow Protocol Packet Detect */ + ETH_InitParam->USPPacketDetect = DISABLE; + /* Default Disable Extended Inter-Packet Gap */ + ETH_InitParam->ExtInterPacketGap = DISABLE; + /* Default Set the minimum Inter-Packet Gap value: 0 */ + ETH_InitParam->ExtInterPacketGapVal = 0U; + /* Default Disable ARP Packet Drop */ + ETH_InitParam->DropARPPacket = DISABLE; + + /* Default Disable Promiscuous Mode */ + ETH_InitParam->Promiscuous = DISABLE; + /* Default Disable Hash Unicast Filtering Mode */ + ETH_InitParam->HashUnicast = DISABLE; + /* Default Disable Hash Multicast Filtering Mode */ + ETH_InitParam->HashMulticast = DISABLE; + /* Default Disable DA Inverse Filtering Mode */ + ETH_InitParam->DAInverseFiltering = DISABLE; + /* Default Disable Pass All Multicast Mode */ + ETH_InitParam->PassAllMulticast = DISABLE; + /* Default Enable Broadcast Packets */ + ETH_InitParam->DisBroadcastPackets = DISABLE; + /* Default Set the control packets: Filter out all */ + ETH_InitParam->PassControlPackets = ETH_CTRL_PACKETS_FLTR_ALL; + /* Default Disable SA Inverse Filtering Mode */ + ETH_InitParam->SAInverseFiltering = DISABLE; + /* Default Disable SA Filter */ + ETH_InitParam->SAFilter = DISABLE; + /* Default Disable Hash or Perfect Filter */ + ETH_InitParam->HashOrPerfectFilter = DISABLE; + /* Default Disable VLAN Tag Filter */ + ETH_InitParam->VLANTagFilter = DISABLE; + /* Default Disable Layer 3 and Layer 4 Filter */ + ETH_InitParam->Layer3Layer4Filter = DISABLE; + /* Default Forward Non-TCP/UDP over IP Packets */ + ETH_InitParam->DropNonTcpUdpPackets = DISABLE; + /* Default Disable Receive All mode */ + ETH_InitParam->ReceiveAll = DISABLE; + + /* Default Set Watchdog Timeout value: 2K bytes */ + ETH_InitParam->WatchdogTimeout = ETH_WDG_TIMEOUT_2KBYTES; + /* Default Disable Programmable Watchdog function */ + ETH_InitParam->ProgramWatchdog = DISABLE; + + /* Default Disable Transmit Flow Control function */ + ETH_InitParam->TxFlowControl = DISABLE; + /* Default Set Pause Low Threshold value: Minus 4 time slots */ + ETH_InitParam->PauseLowThreshold = ETH_PAUSE_LOW_THRESHOLD_PT4; + /* Default Enable Zero-Quanta Pause function */ + ETH_InitParam->DisZeroQuantaPause = DISABLE; + /* Default Set Pause Time field value: 0 */ + ETH_InitParam->PauseTime = 0U; + /* Default Disable Receive Flow Control function */ + ETH_InitParam->RxFlowControl = DISABLE; + /* Default Disable Unicast Pause Packet Detect */ + ETH_InitParam->UPPacketDetect = DISABLE; + + /* Default Set TX Queue Operation Mode: Store and Forward Mode */ + ETH_InitParam->TxQueueOperateMode = ETH_TXQUEUE_OPERATE_STOREFORWARD; + /* Default Set RX Queue Operation Mode: Store and Forward Mode */ + ETH_InitParam->RxQueueOperateMode = ETH_RXQUEUE_OPERATE_STOREFORWARD; + /* Default Disable Forward Undersized Good Packets function */ + ETH_InitParam->ForwardUSGoodPacket = DISABLE; + /* Default Disable Forward Error Packets function */ + ETH_InitParam->ForwardErrorPacket = DISABLE; + /* Default Enable Dropping of TCP/IP Checksum Error Packets */ + ETH_InitParam->DisDropTCPIPCSErrorPacket = DISABLE; + + /* Default Set DMA Tx/Rx Arbitration Scheme: Rx:Tx = 1:1 */ + ETH_InitParam->TxRxArbitration = ETH_DMA_ARBITRA_WRR_RX1_TX1; + /* Default Disable Descriptor Cache function */ + ETH_InitParam->DescriptorCache = DISABLE; + /* Default Set AHB Master interface burst: Unspecified length (INCR) or SINGLE transfers */ + ETH_InitParam->BurstMode = ETH_BURST_MODE_UNFIXED; + /* Default Disable AHB Master interface address-aligned burst transfers on Read and Write channels */ + ETH_InitParam->AddrAlignedBeats = DISABLE; + /* Default Disable AHB Master to rebuild the pending beats of any initiated burst transfer with INCRx and SINGLE transfers */ + ETH_InitParam->RebuildINCRxBurst = DISABLE; + /* Default Set the maximum segment size: 0 */ + ETH_InitParam->MaxSegmentSize = 0U; + /* Default Disable PBL multiplication by eigh mode */ + ETH_InitParam->PBLx8mode = DISABLE; + /* Default Set the Word number to skip between two unchained descriptors: 0-bit */ + ETH_InitParam->DescriptorSkipLen = ETH_DESC_SKIP_LEN_0BIT; + /* Default Disable Operate on Second Packet mode */ + ETH_InitParam->OperateSecondPacket = DISABLE; + /* Default Disable TCP Segmentation function */ + ETH_InitParam->TCPSegment = DISABLE; + /* Default Set the maximum number of beats to be transferred in one DMA block data transfer: 1 */ + ETH_InitParam->TxBurstLength = ETH_TX_PROGRAM_BURST_LEN_1; + /* Default Disable Early Transmit Interrupt function */ + ETH_InitParam->EarlyTxInterruptCtrl = DISABLE; + /* Default Set the maximum number of beats to be transferred in one DMA block data transfer: 1 */ + ETH_InitParam->RxBurstLength = ETH_RX_PROGRAM_BURST_LEN_1; + /* Default Disable Early Receive Interrupt function */ + ETH_InitParam->EarlyRxInterruptCtrl = DISABLE; + /* Default Disable Rx Packet Flush function */ + ETH_InitParam->RxPacketFlush = DISABLE; +} + +/** +*\*\name ETH_DMATxDescListInit. +*\*\fun Initialize the ETH DMA transmit descriptor. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return none +**/ +void ETH_DMATxDescListInit(ETH_Module* ETHx, ETH_InfoType* pInfo) +{ + uint32_t TempIndex; + ETH_DMADescType* pTxDescriptor = NULL; + + /* Fill each DMATxDesc descriptor with the right values */ + for (TempIndex = 0U; TempIndex < ETH_TX_DESC_NUMBER; TempIndex++) + { + /* Get the descriptor address */ + pTxDescriptor = (pInfo->pTxDesc + TempIndex); + + pTxDescriptor->DESC0 = 0U; + pTxDescriptor->DESC1 = 0U; + pTxDescriptor->DESC2 = 0U; + pTxDescriptor->DESC3 = 0U; + /* Save Tx descritors adresses */ + pInfo->TxDescList.TxDesc[TempIndex] = (uint32_t)pTxDescriptor; + } + /* Set the current descriptor index to 0 */ + pInfo->TxDescList.CurTxDesc = 0U; + + /* Set Tx Descriptor Ring Length, The value written to the ETH_DMACH0TXDRLEN + register must be the number of descriptors - 1 */ + WRITE_REG(ETHx->DMACH0TXDRLEN, (ETH_TX_DESC_NUMBER -1U)); + + /* Set Tx Descriptor List Address */ + WRITE_REG(ETHx->DMACH0TXDLA, (uint32_t)pInfo->pTxDesc); + + /* Set Tx Descriptor Tail pointer */ + WRITE_REG(ETHx->DMACH0TXDTP, (uint32_t)pInfo->pTxDesc); +} + +/** +*\*\name ETH_DMARxDescListInit. +*\*\fun Initialize the ETH DMA Receive descriptor. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return none +**/ +void ETH_DMARxDescListInit(ETH_Module* ETHx, ETH_InfoType* pInfo) +{ + uint32_t TempIndex; + ETH_DMADescType* pRxDescriptor = NULL; + + /* Fill each DMATxDesc descriptor with the right values */ + for (TempIndex = 0U; TempIndex < ETH_RX_DESC_NUMBER; TempIndex++) + { + /* Get the descriptor address */ + pRxDescriptor = (pInfo->pRxDesc + TempIndex); + + pRxDescriptor->DESC0 = 0U; + pRxDescriptor->DESC1 = 0U; + pRxDescriptor->DESC2 = 0U; + pRxDescriptor->DESC3 = 0U; + pRxDescriptor->Buf1Addr = 0U; + pRxDescriptor->Buf2Addr = 0U; + /* Save Rx descritors adresses */ + pInfo->RxDescList.RxDesc[TempIndex] = (uint32_t)pRxDescriptor; + } + /* Set the current descriptor index to 0 */ + pInfo->RxDescList.CurRxDesc = 0U; + /* Set the first descriptor to 0 */ + pInfo->RxDescList.FirstAppDesc = 0U; + /* Set the number of descriptors for the last packet to 0 */ + pInfo->RxDescList.AppDescNbr = 0U; + /* Set to not generate a receive completion interrupt */ + pInfo->RxDescList.ItMode = 0U; + /* Set to a non-context descriptor */ + pInfo->RxDescList.AppContextDesc = 0U; + + /* Set Rx Descriptor Ring Length, The value written to the ETH_DMACH0RXCTRL2 + register must be the number of descriptors - 1 */ + WRITE_REG(ETHx->DMACH0RXCTRL2, (ETH_RX_DESC_NUMBER - 1U)); + + /* Set Rx Descriptor List Address */ + WRITE_REG(ETHx->DMACH0RXDLA, (uint32_t)pInfo->pRxDesc); + + /* Set Rx Descriptor Tail pointer */ + WRITE_REG(ETHx->DMACH0RXDTP, (uint32_t)(pInfo->pRxDesc + ((ETH_RX_DESC_NUMBER - 1U) * sizeof(ETH_DMADescType)))); +} + +/** +*\*\name ETH_ConfigMDCNormalClock. +*\*\fun Configure the normal clock frequency (1.0MHz ≤ MDC clock ≤ 2.5MHz) of the +*\*\ MDC based on the CSR clock frequency(HclkFreq), +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pClk: +*\*\ - pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. +*\*\return none +**/ +void ETH_ConfigMDCNormalClock(ETH_Module* ETHx, RCC_ClocksTypeDef* pClk) +{ + uint32_t HclkFreq; + + if (ETHx == ETH1) + { + /* CSR clock of ETH1 is the AHB2 clock */ + HclkFreq = pClk->AHB2ClkFreq; + } + else + { + /* CSR clock of ETH2 is the AHB1 clock */ + HclkFreq = pClk->AHB1ClkFreq; + } + + /* Set CR[3:0] bits by HclkFreq */ + if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_20M) && (HclkFreq < ETH_MACCSR_CLOCK_FREQ_35M)) + { + /* CSR Clock Range between 20-35 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV16); + } + else if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_35M) && (HclkFreq < ETH_MACCSR_CLOCK_FREQ_60M)) + { + /* CSR Clock Range between 35-60 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV26); + } + else if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_60M) && (HclkFreq < ETH_MACCSR_CLOCK_FREQ_100M)) + { + /* CSR Clock Range between 60-100 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV42); + } + else if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_100M) && (HclkFreq < ETH_MACCSR_CLOCK_FREQ_150M)) + { + /* CSR Clock Range between 100-150 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV62); + } + else if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_150M) && (HclkFreq <= ETH_MACCSR_CLOCK_FREQ_250M)) + { + /* CSR Clock Range between 150-250 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV102); + } + else if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_250M) && (HclkFreq < ETH_MACCSR_CLOCK_FREQ_300M)) + { + /* CSR Clock Range between 250-300 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV124); + } + else if((HclkFreq >= ETH_MACCSR_CLOCK_FREQ_300M) && (HclkFreq <= ETH_MACCSR_CLOCK_FREQ_500M)) + { + /* CSR Clock Range between 300-500 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV204); + } + else /* (HclkFreq >= ETH_MACCSR_CLOCK_FREQ_500M) && (HclkFreq <= ETH_MACCSR_CLOCK_FREQ_800M) */ + { + /* CSR Clock Range between 500-800 MHz */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, ETH_MDCNCLK_CRSCLK_DIV324); + } +} + +/** +*\*\name ETH_ConfigMDCFastClock. +*\*\fun Configure the fast clock frequency (MDC clock > 2.5MHz) of the MDC based +*\*\ on the CSR clock frequency(HclkFreq), +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param DivValue (The input parameters must be the following values): +*\*\ - ETH_MDCFCLK_CRSCLK_DIV4 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV6 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV8 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV10 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV12 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV14 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV16 +*\*\ - ETH_MDCFCLK_CRSCLK_DIV18 +*\*\return none +*\*\note Configure for fast clocks is only supported if the interface chip supports +*\*\ faster MDC clocks. +**/ +void ETH_ConfigMDCFastClock(ETH_Module* ETHx, uint32_t DivValue) +{ + /* Set CR[3:0] bits */ + MODIFY_REG(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_CR_MASK, DivValue); +} + +/** +*\*\name ETH_ReadPHYRegister. +*\*\fun Read a PHY register. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param PHYAddr : +*\*\ - PHY port address, must be a value from 0 to 31. +*\*\param PHYReg : +*\*\ - PHY register address, must be a value from 0 to 31. +*\*\param pRegValue : +*\*\ - Points to the address where the read PHY register value is stored. +*\*\return 0 or 1. +**/ +uint32_t ETH_ReadPHYRegister(ETH_Module* ETHx, uint32_t PHYAddr, uint32_t PHYReg, uint32_t* pRegValue) +{ + uint32_t TempReg; + uint32_t timeout = ETH_MDIO_BUS_TIMEOUT; + + /* Check for the Busy flag */ + if (READ_BIT(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_GB) != 0U) + { + /* PHY interface is busy, directly return 0 */ + return 0U; + } + + /* Get the ETH_MACMDIOADDR register value */ + TempReg = READ_REG(ETHx->MACMDIOADDR); + /* Set the PHY port address */ + MODIFY_REG(TempReg, ETH_MACMDIOADDR_PA, (PHYAddr << 21U)); + /* Set the PHY register address */ + MODIFY_REG(TempReg, ETH_MACMDIOADDR_RDA, (PHYReg << 16U)); + /* Set the read operation mode */ + MODIFY_REG(TempReg, ETH_MACMDIOADDR_GOC, (ETH_MACMDIOADDR_GOC0 | ETH_MACMDIOADDR_GOC1)); + + /* Set the MII Busy bit */ + SET_BIT(TempReg, ETH_MACMDIOADDR_GB); + + /* Write the set value into the MDII Address register */ + WRITE_REG(ETHx->MACMDIOADDR, TempReg); + + /* Wait for the Busy flag to clear */ + while (READ_BIT(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_GB) != 0U) + { + if (timeout == 0U) + { + /* Timeout, directly return 0 */ + return 0U; + } + + timeout--; + } + + /* Get MACMIIDR value */ + *pRegValue = READ_REG(ETHx->MACMDIODATA); + + /* Success, return 1 */ + return 1U; +} + +/** +*\*\name ETH_WritePHYRegister. +*\*\fun Write a PHY register. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param PHYAddr : +*\*\ - PHY port address, must be a value from 0 to 31. +*\*\param PHYReg : +*\*\ - PHY register address, must be a value from 0 to 31. +*\*\param PHYRegValue : +*\*\ - The value to write. +*\*\return 0 or 1. +**/ +uint32_t ETH_WritePHYRegister(ETH_Module* ETHx, uint32_t PHYAddr, uint32_t PHYReg, uint32_t PHYRegValue) +{ + uint32_t TempReg; + uint32_t timeout = ETH_MDIO_BUS_TIMEOUT; + + /* Check for the Busy flag */ + if (READ_BIT(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_GB) != 0U) + { + /* PHY interface is busy, directly return 0 */ + return 0U; + } + + /* Get the ETH_MACMDIOADDR register value */ + TempReg = READ_REG(ETHx->MACMDIOADDR); + /* Set the PHY port address */ + MODIFY_REG(TempReg, ETH_MACMDIOADDR_PA, (PHYAddr << 21U)); + /* Set the PHY register address */ + MODIFY_REG(TempReg, ETH_MACMDIOADDR_RDA, (PHYReg << 16U)); + /* Set the write operation mode */ + MODIFY_REG(TempReg, ETH_MACMDIOADDR_GOC, ETH_MACMDIOADDR_GOC0); + + /* Set the MII Busy bit */ + SET_BIT(TempReg, ETH_MACMDIOADDR_GB); + + /* Write the value to the MDIO data register */ + WRITE_REG(ETHx->MACMDIODATA, (uint16_t)PHYRegValue); + + /* Write the set value into the MDII Address register */ + WRITE_REG(ETHx->MACMDIOADDR, TempReg); + + /* Wait for the Busy flag to clear */ + while (READ_BIT(ETHx->MACMDIOADDR, ETH_MACMDIOADDR_GB) != 0U) + { + if (timeout == 0U) + { + /* Timeout, directly return 0 */ + return 0U; + } + + timeout--; + } + + /* Success, return 1 */ + return 1U; +} + +/** +*\*\name ETH_ExternalPHYInit. +*\*\fun Initialize the external PHY, including settings related to whether or +*\*\ not to enable the PHY auto-negotiation function. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param ETH_InitParam : +*\*\ - Pointer to the ETH_InitType structure which will be initialized. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_ExternalPHYInit(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_InitType* ETH_InitParam) +{ + uint32_t TickStart; + uint32_t rPHYRegVlaue; + uint32_t wPHYRegVlaue; + uint32_t TempDelay = ETH_PHY_CONFIG_DELAY; + + /* Put the PHY in reset mode */ + if (!(ETH_WritePHYRegister(ETHx, (uint32_t)pInfo->PHYInfo.phyAddr, + (uint32_t)pInfo->PHYInfo.bcRegAddr, + (uint32_t)pInfo->PHYInfo.phyReset))) + { + /* Return ERROR */ + return ETH_ERROR_WPHY; + } + + /* Delay to assure PHY reset */ + __ETH_DELAY(TempDelay); + + /* Check that DWT is enabled or not */ + if ((DEM_CR & DEM_CR_TRCENA) == (uint32_t)RESET) + { + /* Enable and initialize DWT */ + __ETH_TICK_START(); + } + + /* Get tick */ + TickStart = __ETH_GET_TICK; + /* Wait for linked status */ + do + { + /* Read the PHY register */ + if (!(ETH_ReadPHYRegister(ETHx, (uint32_t)pInfo->PHYInfo.phyAddr, + (uint32_t)pInfo->PHYInfo.bsRegAddr, + &rPHYRegVlaue))) + { + /* Return ERROR */ + return ETH_ERROR_RPHY; + } + + if ((__ETH_GET_TICK - TickStart) > ETH_PHY_LINKED_TIMEOUT) + { + /* Disable tick */ + __ETH_TICK_STOP(); + /* Return timeout */ + return ETH_ERROR_TIMEOUT; + } + } while ((rPHYRegVlaue & pInfo->PHYInfo.phyLinkOK) != pInfo->PHYInfo.phyLinkOK); + + /* Read the PHY register */ + if (!(ETH_ReadPHYRegister(ETHx, (uint32_t)pInfo->PHYInfo.phyAddr, + (uint32_t)pInfo->PHYInfo.bcRegAddr, + &rPHYRegVlaue))) + { + /* Return ERROR */ + return ETH_ERROR_RPHY; + } + + /* Check whether to enable AutoNegotiation */ + if (pInfo->AutoNegCmd != DISABLE) + { + wPHYRegVlaue = rPHYRegVlaue; + /* Enable PHY auto-negotiation */ + wPHYRegVlaue |= pInfo->PHYInfo.phyAutoNeg; + + /* Write the PHY register */ + if (!(ETH_WritePHYRegister(ETHx, (uint32_t)pInfo->PHYInfo.phyAddr, + (uint32_t)pInfo->PHYInfo.bcRegAddr, + wPHYRegVlaue))) + { + /* Return ERROR */ + return ETH_ERROR_WPHY; + } + + /* Delay to assure PHY set */ + __ETH_DELAY(TempDelay); + + /* Get tick */ + TickStart = __ETH_GET_TICK; + /* Wait until the auto-negotiation will be completed */ + do + { + /* Read the PHY register */ + if (!(ETH_ReadPHYRegister(ETHx, (uint32_t)pInfo->PHYInfo.phyAddr, + (uint32_t)pInfo->PHYInfo.bsRegAddr, + &rPHYRegVlaue))) + { + /* Return ERROR */ + return ETH_ERROR_RPHY; + } + + if ((__ETH_GET_TICK - TickStart) > ETH_PHY_AUTONEGO_COMPLETED_TIMEOUT) + { + /* Disable tick */ + __ETH_TICK_STOP(); + /* Return timeout */ + return ETH_ERROR_TIMEOUT; + } + } while ((rPHYRegVlaue & pInfo->PHYInfo.phyAutoNegOK) != pInfo->PHYInfo.phyAutoNegOK); + + /* Set the MAC speed and duplex mode parameters by the read link status */ + switch (pInfo->PHYInfo.phyGetLinkStatus(pInfo->PHYInfo.phyAddr, pInfo->PHYInfo.sdRegAddr)) + { + case ETH_LINK_10FULL: + /* 10M */ + ETH_InitParam->SpeedSelect = ETH_SPEED_10M; + /* Full-duplex */ + ETH_InitParam->Duplex = ETH_FULL_DUPLEX_MODE; + break; + case ETH_LINK_10HALF: + /* 10M */ + ETH_InitParam->SpeedSelect = ETH_SPEED_10M; + /* Half-duplex */ + ETH_InitParam->Duplex = ETH_HALF_DUPLEX_MODE; + break; + case ETH_LINK_100FULL: + /* 100M */ + ETH_InitParam->SpeedSelect = ETH_SPEED_100M; + /* Full-duplex */ + ETH_InitParam->Duplex = ETH_FULL_DUPLEX_MODE; + break; + case ETH_LINK_100HALF: + /* 100M */ + ETH_InitParam->SpeedSelect = ETH_SPEED_100M; + /* Half-duplex */ + ETH_InitParam->Duplex = ETH_HALF_DUPLEX_MODE; + break; + case ETH_LINK_1000FULL: + /* 1000M */ + ETH_InitParam->SpeedSelect = ETH_SPEED_1000M; + /* Full-duplex */ + ETH_InitParam->Duplex = ETH_FULL_DUPLEX_MODE; + break; + case ETH_LINK_1000HALF: + /* 1000M */ + ETH_InitParam->SpeedSelect = ETH_SPEED_1000M; + /* Half-duplex */ + ETH_InitParam->Duplex = ETH_HALF_DUPLEX_MODE; + break; + default: + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + } + else + { + wPHYRegVlaue = rPHYRegVlaue; + /* Disable PHY auto-negotiation */ + wPHYRegVlaue &= pInfo->PHYInfo.phyAutoNeg; + /* Clear the PHY speed bit */ + wPHYRegVlaue &= pInfo->PHYInfo.phySpeedMask; + /* Clear the PHY duplex bit */ + wPHYRegVlaue &= pInfo->PHYInfo.phyDuplexMask; + /* Set PHY speed, duplex mode */ + wPHYRegVlaue |= pInfo->PHYInfo.phyMode; + + /* Write the PHY register */ + if (!(ETH_WritePHYRegister(ETHx, (uint32_t)pInfo->PHYInfo.phyAddr, + (uint32_t)pInfo->PHYInfo.bcRegAddr, + wPHYRegVlaue))) + { + /* Return ERROR */ + return ETH_ERROR_WPHY; + } + + /* Delay to assure PHY set */ + __ETH_DELAY(TempDelay); + } + + /* Disable tick */ + __ETH_TICK_STOP(); + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_Init. +*\*\fun Initialize the ETH module with ETH_InitParam of type ETH_InitType, including +*\*\ ETH MAC initialization, MTL initialization, ETH DMA initialization, etc. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param ETH_InitParam : +*\*\ - Pointer to the ETH_InitType structure which will be initialized. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_Init(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_InitType* ETH_InitParam) +{ + uint32_t TickStart; + uint32_t TempValue; + RCC_ClocksTypeDef Clk; + EthFuncStatusType TempStatus; + + /* Check the pInfo and ETH_InitParam parameter */ + if ((pInfo == NULL) || (ETH_InitParam == NULL)) + { + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + + /* Enable AFIO Clock */ +#ifdef CORE_CM4 + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_AFIO, ENABLE); +#else /* CORE_CM7 */ + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE); +#endif + /* Check whether the media interface is GMII or MII or RMII */ + if (ETHx == ETH1) + { + /* ETH1 supports GMII, MII and RMII */ + if (pInfo->MediaInterface == ETH_GMII_MODE) + { + /* Enable GMII configuration in the AFIO register */ + AFIO_ConfigETH1Mode(ETH1_GMII_SEL); + } + else if (pInfo->MediaInterface == ETH_MII_MODE) + { + /* Enable MII configuration in the AFIO register */ + AFIO_ConfigETH1Mode(ETH1_MII_SEL); + } + else + { + /* Enable RMII configuration in the AFIO register */ + AFIO_ConfigETH1Mode(ETH1_RMII_SEL); + } + } + else + { + /* ETH2 supports MII and RMII */ + if (pInfo->MediaInterface == ETH_MII_MODE) + { + /* Enable MII configuration in the AFIO register */ + AFIO_ConfigETH2Mode(ETH2_MII_SEL); + } + else if (pInfo->MediaInterface == ETH_RMII_MODE) + { + /* Enable RMII configuration in the AFIO register */ + AFIO_ConfigETH2Mode(ETH2_RMII_SEL); + } + else + { + /* Returns ERROR if GMII is selected */ + return ETH_ERROR_MIF; + } + } + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + SET_BIT(ETHx->DMAMODE, ETH_DMAMODE_SWR); + + /* Check that DWT is enabled or not */ + if ((DEM_CR & DEM_CR_TRCENA) == (uint32_t)RESET) + { + /* Enable and initialize DWT */ + __ETH_TICK_START(); + } + + /* Get tick */ + TickStart = __ETH_GET_TICK; + /* Wait for software reset */ + while (READ_BIT(ETHx->DMAMODE, ETH_DMAMODE_SWR) != (uint32_t)RESET) + { + if ((__ETH_GET_TICK - TickStart) > ETH_SWRESET_TIMEOUT) + { + /* Disable tick */ + __ETH_TICK_STOP(); + + /* Return timeout */ + return ETH_ERROR_TIMEOUT; + } + } + + /* Disable tick */ + __ETH_TICK_STOP(); + + /* Get clock frequency value */ + RCC_GetClocksFreqValue(&Clk); + /* Check MDC clock mode */ + if (pInfo->MDCClockMode == ETH_MDCCLK_NORMAL) + { + /* Configure normal MDC clock */ + ETH_ConfigMDCNormalClock(ETHx, &Clk); + } + else + { + /* Configure Fast MDC Clock */ + ETH_ConfigMDCFastClock(ETHx, pInfo->CSRClkDiv); + } + + /* initialization the external PHY */ + TempStatus = ETH_ExternalPHYInit(ETHx, pInfo, ETH_InitParam); + /* Check if it has been successfully initialized */ + if (TempStatus != ETH_SUCCESS) + { + /* Return ERROR */ + return TempStatus; + } + + /** ETH MAC initialization configuration **/ + + /* Configure the ETH_MACCFG register, including setting PRELEN[1:0], DC, + BL[1:0], DR, DCRS, DO, ECRSFD, LM, DM, FES, PS, JE, JD, BE, WD, ACS, CST, + S2KP, GPSLCE, IPG[2:0], CSO, SARC[2:0], ARPOE bits */ + if (ETHx == ETH1) + { + /* ETH1 supports 10M/100M/1000M and packet bursting */ + TempValue = ((ETH_InitParam->TxPreambleLen) | (ETH_InitParam->DeferralCheck) + | (ETH_InitParam->BackOffLimit) | (ETH_InitParam->DisTxRetry) + | (ETH_InitParam->DisCSDuringTransmit) | (ETH_InitParam->DisRxOwn) + | (ETH_InitParam->CSBeforeTransmit) | (ETH_InitParam->Loopback) + | (ETH_InitParam->Duplex) | (ETH_InitParam->SpeedSelect) + | (ETH_InitParam->JumboPacket) | (ETH_InitParam->DisTxJabber) + | (ETH_InitParam->PacketBurst) + | (ETH_InitParam->DisRxWatchdog) | (ETH_InitParam->AutoPadCRCStrip) + | (ETH_InitParam->CRCStripTypePacket) | (ETH_InitParam->Support2KPacket) + | (ETH_InitParam->GiantPacketSizeLimitCtrl) + | (ETH_InitParam->InterPacketGapVal) | (ETH_InitParam->ChecksumOffload) + | (ETH_InitParam->SrcAddrCtrl) | (ETH_InitParam->ARPOffload)); + /* Write to ETH_MACCFG */ + MODIFY_REG(ETHx->MACCFG, ETH1_MACCFG_MASK, TempValue); + } + else + { + /* ETH2 supports 10M/100M and does not support packet bursting */ + TempValue = ((ETH_InitParam->TxPreambleLen) | (ETH_InitParam->DeferralCheck) + | (ETH_InitParam->BackOffLimit) | (ETH_InitParam->DisTxRetry) + | (ETH_InitParam->DisCSDuringTransmit) | (ETH_InitParam->DisRxOwn) + | (ETH_InitParam->CSBeforeTransmit) | (ETH_InitParam->Loopback) + | (ETH_InitParam->Duplex) | (ETH_InitParam->SpeedSelect) + | (ETH_InitParam->JumboPacket) | (ETH_InitParam->DisTxJabber) + | (ETH_InitParam->DisRxWatchdog) | (ETH_InitParam->AutoPadCRCStrip) + | (ETH_InitParam->CRCStripTypePacket) | (ETH_InitParam->Support2KPacket) + | (ETH_InitParam->GiantPacketSizeLimitCtrl) + | (ETH_InitParam->InterPacketGapVal) | (ETH_InitParam->ChecksumOffload) + | (ETH_InitParam->SrcAddrCtrl) | (ETH_InitParam->ARPOffload)); + /* Write to ETH_MACCFG */ + MODIFY_REG(ETHx->MACCFG, ETH2_MACCFG_MASK, TempValue); + } + + /* Configure the ETH_MACEXTCFG register, including setting GPSL, DCRCC, SPEN, + USP, EIPGEN, EIPG[4:0], APDIM bits */ + TempValue = ((ETH_InitParam->GiantPacketSizeLimit) | (ETH_InitParam->DisRxPacketCRCCheck) + | (ETH_InitParam->SPDetect) | (ETH_InitParam->USPPacketDetect) + | (ETH_InitParam->ExtInterPacketGap) | (ETH_InitParam->ExtInterPacketGapVal) + | (ETH_InitParam->DropARPPacket)); + /* Write to ETH_MACEXTCFG */ + MODIFY_REG(ETHx->MACEXTCFG, ETH_MACEXTCFG_MASK, TempValue); + + /* Configure the ETH_MACPFLT register, including setting PR, HUC, HMC, DAIF, + PM, DBF, PCF[1:0], SAIF, SAF, HPF, VTFE, IPFE, DNTU, RA bits */ + TempValue = ((ETH_InitParam->Promiscuous) | (ETH_InitParam->HashUnicast) + | (ETH_InitParam->HashMulticast) | (ETH_InitParam->DAInverseFiltering) + | (ETH_InitParam->PassAllMulticast) | (ETH_InitParam->DisBroadcastPackets) + | (ETH_InitParam->PassControlPackets) | (ETH_InitParam->SAInverseFiltering) + | (ETH_InitParam->SAFilter) | (ETH_InitParam->HashOrPerfectFilter) + | (ETH_InitParam->VLANTagFilter) | (ETH_InitParam->Layer3Layer4Filter) + | (ETH_InitParam->DropNonTcpUdpPackets)| (ETH_InitParam->ReceiveAll)); + /* Write to ETH_MACPFLT */ + MODIFY_REG(ETHx->MACPFLT, ETH_MACPFLT_MASK, TempValue); + + /* Configure the ETH_MACWDGTO register, including setting WTO[3:0], PWE bits */ + TempValue = ((ETH_InitParam->WatchdogTimeout) | (ETH_InitParam->ProgramWatchdog)); + /* Write to ETH_MACWDGTO */ + MODIFY_REG(ETHx->MACWDGTO, ETH_MACWDGTO_MASK, TempValue); + + /* Configure the ETH_MACTXFLWCTRL register, including setting TFE, PLT[2:0], + DZPQ, PT bits */ + TempValue = ((ETH_InitParam->TxFlowControl) | (ETH_InitParam->PauseLowThreshold) + | (ETH_InitParam->DisZeroQuantaPause) | (ETH_InitParam->PauseTime)); + /* Write to ETH_MACTXFLWCTRL */ + MODIFY_REG(ETHx->MACTXFLWCTRL, ETH_MACTXFLWCTRL_MASK, TempValue); + + /* Configure the ETH_MACRXFLWCTRL register, including setting RFE, UP bits */ + TempValue = ((ETH_InitParam->RxFlowControl) | (ETH_InitParam->UPPacketDetect)); + /* Write to ETH_MACRXFLWCTRL */ + MODIFY_REG(ETHx->MACRXFLWCTRL, ETH_MACRXFLWCTRL_MASK, TempValue); + + /** ETH MTL initialization configuration **/ + + /* Configure the ETH_MTLTXQOPMOD register, including setting TSF, TTC[2:0] bits */ + TempValue = (ETH_InitParam->TxQueueOperateMode); + /* Write to ETH_MTLTXQOPMOD */ + MODIFY_REG(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_MASK, TempValue); + + /* Configure the ETH_MTLRXQOPMOD register, including setting RTC[1:0], FUP, FEP, + RSF, DISTCPEF bits */ + TempValue = ((ETH_InitParam->RxQueueOperateMode) | (ETH_InitParam->ForwardUSGoodPacket) + | (ETH_InitParam->ForwardErrorPacket) | (ETH_InitParam->DisDropTCPIPCSErrorPacket)); + /* Write to ETH_MTLRXQOPMOD */ + MODIFY_REG(ETHx->MTLRXQOPMOD, ETH_MTLRXQOPMOD_MASK, TempValue); + + /** ETH DMA initialization configuration **/ + + /* Configure the ETH_DMAMODE register, including setting DA, TXPR, PR[2:0], DCHE bits */ + TempValue = (ETH_InitParam->TxRxArbitration | (ETH_InitParam->DescriptorCache)); + /* Write to ETH_DMAMODE */ + MODIFY_REG(ETHx->DMAMODE, ETH_DMAMODE_MASK, TempValue); + + /* Configure the ETH_DMASBMODE register, including setting FB, AAL, MB, RB bits */ + TempValue = ((ETH_InitParam->BurstMode) | (ETH_InitParam->AddrAlignedBeats) + | (ETH_InitParam->RebuildINCRxBurst)); + /* Write to ETH_DMASBMODE */ + MODIFY_REG(ETHx->DMASBMODE, ETH_DMASBMODE_MASK, TempValue); + + /* Configure the ETH_DMACH0CTRL register, including setting MSS[13:0] PBLx8, DSL[2:0] bits */ + TempValue = ((ETH_InitParam->MaxSegmentSize) | (ETH_InitParam->PBLx8mode) + | (ETH_InitParam->DescriptorSkipLen)); + /* Write to ETH_DMACH0CTRL */ + MODIFY_REG(ETHx->DMACH0CTRL, ETH_DMACH0CTRL_MASK, TempValue); + + /* Configure the ETH_DMACH0TXCTRL register, including setting OSF, TSE, TxPBL[5:0], ETIC bits */ + TempValue = ((ETH_InitParam->OperateSecondPacket) | (ETH_InitParam->TCPSegment) + | (ETH_InitParam->TxBurstLength) | (ETH_InitParam->EarlyTxInterruptCtrl)); + /* Write to ETH_DMACH0TXCTRL */ + MODIFY_REG(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_MASK, TempValue); + + /* Configure the ETH_DMACH0RXCTRL register, including setting RxPBL[5:0], ERIC, RPF bits */ + TempValue = ((ETH_InitParam->RxBurstLength) | (ETH_InitParam->EarlyRxInterruptCtrl) + | (ETH_InitParam->RxPacketFlush)); + /* Write to ETH_DMACH0RXCTRL */ + MODIFY_REG(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_MASK, TempValue); + + /* Set Receive Buffers Length (must be a multiple of 4) */ + if ((pInfo->RxBuffLen % 4U) != 0U) + { + /* Return Error */ + return ETH_ERROR_PARAM; + } + else + { + /* Write to ETH_DMACH0RXCTRL */ + MODIFY_REG(ETHx->DMACH0RXCTRL, ETH_RXBUFFERSIZE_MASK, (pInfo->RxBuffLen << 1U)); + } + + /* Initialize transmit DMA descriptor */ + ETH_DMATxDescListInit(ETHx, pInfo); + /* Initialize receive DMA descriptor */ + ETH_DMARxDescListInit(ETHx, pInfo); + + /* Set MAC address high 16 bits */ + WRITE_REG(ETHx->MACADDR0H, ((uint32_t)(pInfo->pMACAddr[5U] << 8U) | (uint32_t)(pInfo->pMACAddr[4U]))); + /* Set MAC address low 32 bits */ + WRITE_REG(ETHx->MACADDR0L, ((uint32_t)(pInfo->pMACAddr[3U] << 24U) | (uint32_t)(pInfo->pMACAddr[2U] << 16U) + | (uint32_t)(pInfo->pMACAddr[1U] << 8U) | (uint32_t)(pInfo->pMACAddr[0U]))); + + /* Set 1 μs tick counter, used to update certain EEE-related counters */ + if (ETHx == ETH1) + { + /* CSR clock of ETH1 is the AHB2 clock */ + WRITE_REG(ETHx->MAC1USTICCNT, (((uint32_t)Clk.AHB2ClkFreq / ETH_MAC_US_TICK) - 1U)); + } + else + { + /* CSR clock of ETH1 is the AHB2 clock */ + WRITE_REG(ETHx->MAC1USTICCNT, (((uint32_t)Clk.AHB1ClkFreq / ETH_MAC_US_TICK) - 1U)); + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_TxMACCmd. +*\*\fun Enables or disables the MAC transmission. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_TxMACCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MAC transmission */ + SET_BIT(ETHx->MACCFG, ETH_MACCFG_TE); + } + else + { + /* Disable the MAC transmission */ + CLEAR_BIT(ETHx->MACCFG, ETH_MACCFG_TE); + } +} + +/** +*\*\name ETH_RxMACCmd. +*\*\fun Enables or disables the MAC reception. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_RxMACCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MAC reception */ + SET_BIT(ETHx->MACCFG, ETH_MACCFG_RE); + } + else + { + /* Disable the MAC reception */ + CLEAR_BIT(ETHx->MACCFG, ETH_MACCFG_RE); + } +} + +/** +*\*\name ETH_SetHashTable. +*\*\fun Set the ETH Hash Table Value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pHashTable : +*\*\ - Pointer to a table of two 32 bit values, that contains the 64 +*\*\ bits of the hash table. +*\*\return none +**/ +void ETH_SetHashTable(ETH_Module* ETHx, uint32_t *pHashTable) +{ + /* Set the [31:0] bits of the hash table */ + WRITE_REG(ETHx->MACHASHTR0, pHashTable[0]); + /* Set the [63:32] bits of the hash table */ + WRITE_REG(ETHx->MACHASHTR1, pHashTable[1]); +} + +/** +*\*\name ETH_RxVLANTagStructInit. +*\*\fun Initializes the structure parameter of type ETH_RxVLANTagInitType used to +*\*\ initialize VLAN tag. This function is usually called before initializing +*\*\ a parameter of type ETH_RxVLANTagInitType. +*\*\param ETH_InitParam : +*\*\ - Pointer to the ETH_RxVLANTagInitType structure which will be initialized. +*\*\return none +**/ +void ETH_RxVLANTagStructInit(ETH_RxVLANTagInitType* ETH_RxVTInitParam) +{ + /** Set the default configuration **/ + + /* Default Disable VLAN Tag Hash Table Match */ + ETH_RxVTInitParam->VLANTagHashTableMatch = DISABLE; + /* Default Disable VLAN Tag in Rx status */ + ETH_RxVTInitParam->VLANTagInStatus = DISABLE; + /* Default Set the VLAN Tag Stripping on Receive: NONE */ + ETH_RxVTInitParam->StripVLANTag = ETH_VLANTAGRXSTRIPPING_NONE; + /* Default Set VLAN Type Check: DISABLE Check */ + ETH_RxVTInitParam->VLANTypeCheck = ETH_VLANTYPECHECK_DISABLE; + /* Default Disable VLAN Tag Inverse Match */ + ETH_RxVTInitParam->VLANTagInverceMatch = DISABLE; + /* Default Disable 12-Bit VLAN Tag Comparison */ + ETH_RxVTInitParam->VLANTagComparison12Bit = DISABLE; +} + +/** +*\*\name ETH_RxVLANTagInit. +*\*\fun Initialize VLAN tag processing on the receive path. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param ETH_RxVTInitParam : +*\*\ - Pointer to the ETH_RxVLANTagInitType structure which will be initialized. +*\*\return none +**/ +void ETH_RxVLANTagInit(ETH_Module* ETHx, ETH_RxVLANTagInitType* ETH_RxVTInitParam) +{ + uint32_t TempValue; + + /* Configure the ETH_MACVLANTAG register, including setting VTHM, EVLRXS, EVLS, DOVLTC, + ERSVLM, ESVL, VTIM, ETV, VL[15:0] bits */ + TempValue = ((ETH_RxVTInitParam->VLANTagInStatus) | (ETH_RxVTInitParam->VLANTagHashTableMatch) + | (ETH_RxVTInitParam->StripVLANTag) | (ETH_RxVTInitParam->VLANTypeCheck) + | (ETH_RxVTInitParam->VLANTagInverceMatch) | (ETH_RxVTInitParam->VLANTagComparison12Bit)); + /* Write to ETH_MACVLANTAG */ + MODIFY_REG(ETHx->MACVLANTAG, ETH_MACVLANTAG_MASK, TempValue); +} + +/** +*\*\name ETH_SetVLANHashTable. +*\*\fun Set the ETH VLAN Hash Table Value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param HashTable : +*\*\ - VLAN hash table 16 bit value. +*\*\return none +**/ +void ETH_SetVLANHashTable(ETH_Module* ETHx, uint16_t HashTable) +{ + /* Set the [16:0] bits of the VLAN hash table */ + WRITE_REG(ETHx->MACVHASHT, HashTable); +} + +/** +*\*\name ETH_SetRxVLANIdentifier. +*\*\fun Set the VLAN Identifier for Rx packets. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param VLANIdentifier : +*\*\ - VLAN Identifier value. +*\*\return none +**/ +void ETH_SetRxVLANIdentifier(ETH_Module* ETHx, uint32_t VLANIdentifier) +{ + /* Check if 12-bit compare is enabled */ + if (READ_BIT(ETHx->MACVLANTAG, ETH_MACVLANTAG_ETV) != (uint32_t)RESET) + { + /* Write 12-bit Identifier */ + MODIFY_REG(ETHx->MACVLANTAG, ETH_MACVLANTAG_VL_VID, VLANIdentifier); + } + else + { + /* Write 16-bit Identifier */ + MODIFY_REG(ETHx->MACVLANTAG, ETH_MACVLANTAG_VL, VLANIdentifier); + } +} + +/** +*\*\name ETH_InitiatePauseControlPacket. +*\*\fun Initiates a pause control packet transmission during TX flow control +*\*\ operation. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note The pause packet function is only valid when the MAC is configured +*\*\ in full-duplex mode. +*\*\note During control packet transmission, this bit remains set to 1 to +*\*\ indicate that packet transmission is in progress. When pause packet +*\*\ transmission is complete, the MAC resets this bit to 0. No write +*\*\ operations should be performed to this register until this bit is +*\*\ cleared. +**/ +void ETH_InitiatePauseControlPacket(ETH_Module* ETHx) +{ + /* Initiates pause control packet */ + SET_BIT(ETHx->MACTXFLWCTRL, ETH_MACTXFLWCTRL_FCB); +} + +/** +*\*\name ETH_ActivateBackpressure. +*\*\fun Activate backpressure function during TX flow control operation. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note Activate backpressure function is only valid when the MAC is configured +*\*\ in half-duplex mode. +*\*\note during backpressure, when the MAC receives a new frame, the transmitter +*\*\ starts sending a JAM pattern resulting in a collision. +*\*\note BPA is automatically disabled when the MAC is configured in full-duplex +*\*\ mode. +**/ +void ETH_ActivateBackpressure(ETH_Module* ETHx) +{ + /* Activate the MAC BackPressure operation */ + SET_BIT(ETHx->MACTXFLWCTRL, ETH_MACTXFLWCTRL_BPA); +} + +/** +*\*\name ETH_PowerDownCmd. +*\*\fun Enables or disables the ETH Power Down mode. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_PowerDownCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_PWRDWN); + } + else + { + /* Disable the MAC Power Down */ + CLEAR_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_PWRDWN); + } +} + +/** +*\*\name ETH_MagicPacketDetectionCmd. +*\*\fun Enables or disables the MAC Magic Packet Detection. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MagicPacketDetectionCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_MGKPKTEN); + } + else + { + /* Disable the MAC Magic Packet Detection */ + CLEAR_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_MGKPKTEN); + } +} + +/** +*\*\name ETH_WakeUpPacketDetectionCmd. +*\*\fun Enables or disables the MAC Remote Wake-Up Packet Detection. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_WakeUpPacketDetectionCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MAC Remote Wake-Up Packet Detection */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_RWKPKTEN); + } + else + { + /* Disable the MAC Remote Wake-Up Packet Detection */ + CLEAR_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_RWKPKTEN); + } +} + +/** +*\*\name ETH_GlobalUnicastWakeUpCmd. +*\*\fun Enables or disables any unicast packet filtered by the MAC +*\*\ address recognition to be a wake-up packet. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_GlobalUnicastWakeUpCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MAC Remote Wake-Up Packet Detection */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_GLBLUCAST); + } + else + { + /* Disable the MAC Remote Wake-Up Packet Detection */ + CLEAR_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_GLBLUCAST); + } +} + +/** +*\*\name ETH_ResetWakeUpPacketFilterRegPointer. +*\*\fun Reset Wakeup packet filter register pointer. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_ResetWakeUpPacketFilterRegPointer(ETH_Module* ETHx) +{ + /* Resets the Remote Wake-up packet Filter register pointer to 0x0000 */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_MACPMTCTRLSTS_RWKFILTRST); +} + +/** +*\*\name ETH_SetWakeUpPacketFilterRegister. +*\*\fun Populates the remote wakeup packet registers. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pBuffer : +*\*\ - Pointer on remote WakeUp Packet Filter Register buffer data (8 words). +*\*\return none +*\*\note When MAC RWK Packet Filter register is written, the content is transferred +*\*\ from CSR clock domain to PHY receive clock domain after the write operation, +*\*\ there should not be any further write to the MAC RWK Packet Filter register +*\*\ until the first write is updated in PHY receive clock domain. Otherwise, the +*\*\ second write operation does not get updated to the PHY receive clock domain. +*\*\ Therefore, the delay between two writes to the MAC RWK Packet Filter register +*\*\ should be at least 4 cycles of the PHY receive clock. +**/ +void ETH_SetWakeUpPacketFilterRegister(ETH_Module* ETHx, uint32_t *pBuffer) +{ + uint32_t TempIndex; + uint32_t TempDelay = ETH_WRITE_REG_DELAY; + + for (TempIndex = 0; TempIndex < ETH_WAKEUP_REGISTER_LEN; TempIndex++) + { + /* Write each time to the same register */ + WRITE_REG(ETHx->MACRWUPFLT, pBuffer[TempIndex]); + + /* Must be delayed at least 4 cycles of the PHY receive clock */ + __ETH_DELAY(TempDelay); + } +} + +/** +*\*\name ETH_CSRRegisterWrite1ClearCmd. +*\*\fun Enables or disables Write 1 clear mode for some CSR registers. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_CSRRegisterWrite1ClearCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enables Write 1 clear mode for some CSR registers */ + /* The application needs to set the corresponding bit to 1 to clear it */ + SET_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE); + } + else + { + /* Disable Write 1 clear mode for some CSR registers */ + /* The access mode for these register fields remains "read clear" */ + CLEAR_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE); + } +} + +/** +*\*\name ETH_SetMACAddress. +*\*\fun Set MAC address by application layer setting. Support configuring +*\*\ MAC address registers 0~3. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MAC_ADDR0_OFFSET +*\*\ - ETH_MAC_ADDR1_OFFSET +*\*\ - ETH_MAC_ADDR2_OFFSET +*\*\ - ETH_MAC_ADDR3_OFFSET +*\*\param pAddr: +*\*\ - Pointer on MAC address buffer +*\*\return none +**/ +void ETH_SetMACAddress(ETH_Module* ETHx, EthMacAddr0123Type Offset, uint8_t* pAddr) +{ + uint32_t TempValue; + uint32_t macAddrRegBaseH; + uint32_t macAddrRegBaseL; + + /* Get the MAC address high register base address */ + macAddrRegBaseH = (uint32_t)&(ETHx->MACADDR0H); + + /* Get the MAC address low register base address */ + macAddrRegBaseL = (uint32_t)&(ETHx->MACADDR0L); + + /* Set MAC addr high bits (32~47) */ + TempValue = (((uint32_t)(pAddr[5]) << 8) | (uint32_t)pAddr[4]); + (*(__IO uint32_t *) (macAddrRegBaseH + Offset)) = TempValue; + + /* Set MAC addr low bits (0~31) */ + TempValue = (((uint32_t)(pAddr[3]) << 24) | ((uint32_t)(pAddr[2]) << 16) | + ((uint32_t)(pAddr[1]) << 8) | (uint32_t)pAddr[0]); + (*(__IO uint32_t *) (macAddrRegBaseL + Offset)) = TempValue; +} + +/** +*\*\name ETH_GetMACAddress. +*\*\fun Get MAC address by application layer setting. Support get MAC address +*\*\ registers 0~3. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MAC_ADDR0_OFFSET +*\*\ - ETH_MAC_ADDR1_OFFSET +*\*\ - ETH_MAC_ADDR2_OFFSET +*\*\ - ETH_MAC_ADDR3_OFFSET +*\*\param pAddr: +*\*\ - Pointer on MAC address buffer +*\*\return none +**/ +void ETH_GetMACAddress(ETH_Module* ETHx, EthMacAddr0123Type Offset, uint8_t* pAddr) +{ + uint32_t TempValue; + uint32_t macAddrRegBaseH; + uint32_t macAddrRegBaseL; + + /* Get the MAC address high register base address */ + macAddrRegBaseH = (uint32_t)&(ETHx->MACADDR0H); + + /* Get the MAC address low register base address */ + macAddrRegBaseL = (uint32_t)&(ETHx->MACADDR0L); + + /* Get the MAC address high register value */ + TempValue = *(__IO uint32_t *) (macAddrRegBaseH + Offset); + /* Save MAC addr high bits (32~47) */ + pAddr[5] = ((TempValue >> 8) & (uint8_t)0xFF); + pAddr[4] = (TempValue & (uint8_t)0xFF); + + /* Get the MAC address low register value */ + TempValue = *(__IO uint32_t *) (macAddrRegBaseL + Offset); + /* Save MAC addr low bits (0~31) */ + pAddr[3] = ((TempValue >> 24) & (uint8_t)0xFF); + pAddr[2] = ((TempValue >> 16) & (uint8_t)0xFF); + pAddr[1] = ((TempValue >> 8) & (uint8_t)0xFF); + pAddr[0] = (TempValue & (uint8_t)0xFF); +} + +/** +*\*\name ETH_MACAddressPerfectFilterCmd. +*\*\fun Enables or disables the Address filter module uses the specified ETH +*\*\ MAC address (MAC address 1 ~ MAC address 3) for perfect filtering. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MACADDR1_OFFSET +*\*\ - ETH_MACADDR2_OFFSET +*\*\ - ETH_MACADDR3_OFFSET +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MACAddressPerfectFilterCmd(ETH_Module* ETHx, EthMacAddr123Type Offset, FunctionalStatus Cmd) +{ + uint32_t macAddrRegBaseH; + + /* Get the MAC address high register base address */ + macAddrRegBaseH = (uint32_t)&(ETHx->MACADDR0H); + + if (Cmd != DISABLE) + { + /* Enable the selected ETH MAC address (1~3) for perfect filtering */ + (*(__IO uint32_t *) (macAddrRegBaseH + Offset)) |= ETH_MACADDR1H_AE; + } + else + { + /* Disable the selected ETH MAC address (1~3) for perfect filtering */ + (*(__IO uint32_t *) (macAddrRegBaseH + Offset)) &= (~ETH_MACADDR1H_AE); + } +} + +/** +*\*\name ETH_SetMACAddressFilter. +*\*\fun Set the filter type for the specified ETH MAC address (MAC address 1 ~ +*\*\ MAC address 3). +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MACADDR1_OFFSET +*\*\ - ETH_MACADDR2_OFFSET +*\*\ - ETH_MACADDR3_OFFSET +*\*\param Filter (The input parameters must be the following values): +*\*\ - ETH_MACADDR_FILTER_SA +*\*\ - ETH_MACADDR_FILTER_DA +*\*\return none +**/ +void ETH_SetMACAddressFilter(ETH_Module* ETHx, EthMacAddr123Type Offset, EthMacAddrFilterType Filter) +{ + uint32_t macAddrRegBaseH; + + /* Get the MAC address high register base address */ + macAddrRegBaseH = (uint32_t)&(ETHx->MACADDR0H); + + if (Filter != ETH_MACADDR_FILTER_DA) + { + /* The selected ETH MAC address is used to compare with the SA fields of the + received frame */ + (*(__IO uint32_t *) (macAddrRegBaseH + Offset)) |= ETH_MACADDR1H_SA; + } + else + { + /* The selected ETH MAC address is used to compare with the DA fields of the + received frame */ + (*(__IO uint32_t *) (macAddrRegBaseH + Offset)) &= (~ETH_MACADDR1H_SA); + } +} + +/** +*\*\name ETH_SetMACAddressFilterMaskBytes. +*\*\fun Set the filter mask bytes for the specified ETH MAC address (MAC address 1 ~ +*\*\ MAC address 3). +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MACADDR1_OFFSET +*\*\ - ETH_MACADDR2_OFFSET +*\*\ - ETH_MACADDR3_OFFSET +*\*\param MaskByte (The input parameters must be the following values): +*\*\ - ETH_MACADDR_MASK_BYTE6 +*\*\ - ETH_MACADDR_MASK_BYTE5 +*\*\ - ETH_MACADDR_MASK_BYTE4 +*\*\ - ETH_MACADDR_MASK_BYTE3 +*\*\ - ETH_MACADDR_MASK_BYTE2 +*\*\ - ETH_MACADDR_MASK_BYTE1 +*\*\return none +**/ +void ETH_SetMACAddressFilterMaskBytes(ETH_Module* ETHx, EthMacAddr123Type Offset, uint32_t MaskByte) +{ + uint32_t macAddrRegBaseH; + + /* Get the MAC address high register base address */ + macAddrRegBaseH = (uint32_t)&(ETHx->MACADDR0H); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t*)(macAddrRegBaseH + Offset)) &= (~ETH_MACADDR_MASK_MBC); + + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t*)(macAddrRegBaseH + Offset)) |= MaskByte; +} + +/** +*\*\name ETH_MMCCountersReset. +*\*\fun Resets the MMC Counters. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MMCCountersReset(ETH_Module* ETHx) +{ + /* Resets the MMC Counters */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTRST); +} + +/** +*\*\name ETH_MMCCounterStopRolloverCmd. +*\*\fun Enables or disables the MMC Counter Stop Rollover. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MMCCounterStopRolloverCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MMC Counter Stop Rollover */ + /* The counter does not rollover to 0 after reaching the maximum value */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTSTOPRO); + } + else + { + /* Disable the MMC Counter Stop Rollover */ + CLEAR_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTSTOPRO); + } +} + +/** +*\*\name ETH_MMCResetOnReadCmd. +*\*\fun Enables or disables the MMC Reset On Read. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MMCResetOnReadCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MMC Counter reset on read */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_RSTONRD); + } + else + { + /* Disable the MMC Counter reset on read */ + CLEAR_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_RSTONRD); + } +} + +/** +*\*\name ETH_MMCCounterFreezeCmd. +*\*\fun Enables or disables the MMC Counter Freeze. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MMCCounterFreezeCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MMC Counter Freeze */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTFREEZ); + } + else + { + /* Disable the MMC Counter Freeze */ + CLEAR_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTFREEZ); + } +} + +/** +*\*\name ETH_MMCCounterHalfPreset. +*\*\fun Preset and Initialize the MMC counters to almost-half value: +*\*\ 0x7FFF_FFF0. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MMCCounterHalfPreset(ETH_Module* ETHx) +{ + /* Preset and Initialize the MMC counters to almost-half value */ + CLEAR_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTPRSTLVL); + + /* Enable counter preset function */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTPRST); +} + +/** +*\*\name ETH_MMCCounterFullPreset. +*\*\fun Preset and Initialize the MMC counters to almost-full value: +*\*\ 0xFFFF_FFF0. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MMCCounterFullPreset(ETH_Module* ETHx) +{ + /* Preset and Initialize the MMC counters to almost-full value */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTPRSTLVL); + + /* Enable counter preset function */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_CNTPRST); +} + +/** +*\*\name ETH_MMCCounterUpdateForDropBCPacketCmd. +*\*\fun Enables or disables the Update MMC Counters for Dropped Broadcast +*\*\ Packets. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MMCCounterUpdateForDropBCPacketCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable Update MMC Counters for Dropped Broadcast Packets */ + SET_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_UCDBC); + } + else + { + /* Disable Update MMC Counters for Dropped Broadcast Packets */ + CLEAR_BIT(ETHx->MMCCTRL, ETH_MMCCTRL_UCDBC); + } +} + +/** +*\*\name ETH_GetMMCCounterValue. +*\*\fun Get the specified ETH MMC counter value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MMC_SCGP_OFFSET +*\*\ - ETH_MMC_MCGP_OFFSET +*\*\ - ETH_MMC_PCG_OFFSET +*\*\ - ETH_MMC_BPG_OFFSET +*\*\ - ETH_MMC_MPG_OFFSET +*\*\ - ETH_MMC_CRCEP_OFFSET +*\*\ - ETH_MMC_AEP_OFFSET +*\*\ - ETH_MMC_UPG_OFFSET +*\*\return Corresponding counter value. +**/ +uint32_t ETH_GetMMCCounterValue(ETH_Module* ETHx, EthMmcAddrType Offset) +{ + uint32_t mmcRegBaseAddr; + + /* Get the ETH MMC register base address */ + mmcRegBaseAddr = (uint32_t)&(ETHx->MMCCTRL); + + /* Return the selected counter register value */ + return (*(__IO uint32_t *)(mmcRegBaseAddr + Offset)); +} + +/** +*\*\name ETH_MACTimeStampCmd. +*\*\fun Enables or disables the MAC timestamp. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MACTimeStampCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the time stamp for transmit and receive frames */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSENA); + } + else + { + /* Disable the time stamp for transmit and receive frames */ + CLEAR_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSENA); + } +} + +/** +*\*\name ETH_SetTimeStampUpdateMethod. +*\*\fun Selects the MAC timestamp Update method. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Method (The input parameters must be the following values): +*\*\ - ETH_MACTS_FINE_UPDATE +*\*\ - ETH_MACTS_COARSE_UPDATE +*\*\return none +**/ +void ETH_SetTimeStampUpdateMethod(ETH_Module* ETHx, uint32_t Method) +{ + if (Method == ETH_MACTS_FINE_UPDATE) + { + /* Selects the Fine Update method */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSCFUPDT); + } + else + { + /* Selects the Coarse Update method */ + CLEAR_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSCFUPDT); + } +} + +/** +*\*\name ETH_MACTimeStampInit. +*\*\fun Initialize the MAC timestamp. The system time is initialized +*\*\ (overwritten) with the values specified in the MAC System Time Seconds +*\*\ Update Register and the MAC System Time Nanoseconds Update Register. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MACTimeStampInit(ETH_Module* ETHx) +{ + /* Initialize the MAC Time Stamp */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSINIT); +} + +/** +*\*\name ETH_MACTimeStampUpdate. +*\*\fun Update the MAC timestamp. The system time is updated (added or +*\*\ subtracted) with the values specified in the MAC System Time Seconds +*\*\ Update Register and the MAC System Time Nanoseconds Update Register. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MACTimeStampUpdate(ETH_Module* ETHx) +{ + /* Update the MAC Time Stamp */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSUPDT); +} + +/** +*\*\name ETH_EnableTimeStampIntTrigger. +*\*\fun Enable the MAC TimeStamp interrupt trigger. the timestamp interrupt is +*\*\ generated when the System Time becomes greater than the value written +*\*\ in the Target Time register. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +// void ETH_EnableTimeStampIntTrigger(ETH_Module* ETHx) +// { +// /* Enable the MAC Time Stamp interrupt trigger */ +// SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TTSTRIG); +// } + +/** +*\*\name ETH_MACTimeStampAddendRegUpdate. +*\*\fun Update the MAC timestamp addend register. the content of the Timestamp +*\*\ Addend register is updated in the PTP block for fine correction. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MACTimeStampAddendRegUpdate(ETH_Module* ETHx) +{ + /* Update the MAC Time Stamp addend register */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSADDREG); +} + +/** +*\*\name ETH_MACTimeStampAllPacketsCmd. +*\*\fun Enables or disables the MAC timestamp for All Packets. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MACTimeStampAllPacketsCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable Timestamp for All Packets */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSENALL); + } + else + { + /* Disable Timestamp for all packets */ + CLEAR_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSENALL); + } +} + +/** +*\*\name ETH_MACTimeStampDigBinRolloverCmd. +*\*\fun Enables or disables the MAC timestamp Rollover for Digital or Binary. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MACTimeStampDigBinRolloverCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable Timestamp Digital or Binary Rollover */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSCTRLSSR); + } + else + { + /* Disables Timestamp Digital or Binary Rollover */ + CLEAR_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSCTRLSSR); + } +} + +/** +*\*\name ETH_PTPTypePacketProcesCmd. +*\*\fun Enables or disables the processing for selected PTP packet type. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param PacketType (The input parameters must be the following values): +*\*\ - ETH_MACPTP_TYPE_VERSION2 +*\*\ - ETH_MACPTP_TYPE_ETHERNET +*\*\ - ETH_MACPTP_TYPE_IPV6UDP +*\*\ - ETH_MACPTP_TYPE_IPV4UDP (default) +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_PTPTypePacketProcesCmd(ETH_Module* ETHx, uint32_t PacketType, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable processing for selected PTP packet types */ + SET_BIT(ETHx->MACTSCTRL, PacketType); + } + else + { + /* Disable processing for selected PTP packet types */ + CLEAR_BIT(ETHx->MACTSCTRL, PacketType); + } +} + +/** +*\*\name ETH_MACAddrPTPPacketFilterCmd. +*\*\fun Enables or disables the MAC address for PTP packet filtering. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MACAddrPTPPacketFilterCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable MAC address for PTP packet filtering */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSENMACADDR); + } + else + { + /* Disable MAC address for PTP packet filtering */ + CLEAR_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TSENMACADDR); + } +} + +/** +*\*\name ETH_MACTxTimeStampStatusModeCmd. +*\*\fun Enables or disables the MAC TX timestamp status mode. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MACTxTimeStampStatusModeCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable MAC TX timestamp status mode */ + SET_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TXTSSTSM); + } + else + { + /* Disable MAC TX timestamp status mode */ + CLEAR_BIT(ETHx->MACTSCTRL, ETH_MACTSCTRL_TXTSSTSM); + } +} + +/** +*\*\name ETH_SetSubSecondIncrementValue. +*\*\fun Sets the system time Sub-Second Increment value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IncValue : +*\*\ - 0~0xFF +*\*\return none +**/ +void ETH_SetSubSecondIncrementValue(ETH_Module* ETHx, uint8_t IncValue) +{ + /* Set the Sub-Second Increment Register */ + WRITE_REG(ETHx->MACSUBSINC, ((uint32_t)IncValue << 16)); +} + +/** +*\*\name ETH_SetTimeStampUpdateValue. +*\*\fun Sets the Time Stamp update value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param CalMode (The input parameters must be the following values): +*\*\ - ETH_MACTS_CALMODE_SUB +*\*\ - ETH_MACTS_CALMODE_ADD +*\*\param SecondValue : +*\*\ - 0~0xFFFFFFFF +*\*\param SubSecondValue : +*\*\ - 0~0x7FFFFFFF +*\*\return none +*\*\note When CalMode is set to ETH_MACTS_CALMODE_SUB, the seconds field +*\*\ and nanosecond field must be programmed with the complement of +*\*\ the corresponding part of the update value. +**/ +void ETH_SetTimeStampUpdateValue(ETH_Module* ETHx, uint32_t CalMode, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Set MAC System Time Seconds Update Register */ + WRITE_REG(ETHx->MACSYSTSUP, SecondValue); + /* Set MAC System Time Nanosecond Update Register */ + WRITE_REG(ETHx->MACSYSTNSUP, (CalMode | SubSecondValue)); +} + +/** +*\*\name ETH_SetTimeStampAddendValue. +*\*\fun Sets the Time Stamp addend value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param AddValue : +*\*\ - 0~0xFFFFFFFF +*\*\return none +**/ +void ETH_SetTimeStampAddendValue(ETH_Module* ETHx, uint32_t AddValue) +{ + /* Set the MAC Timestamp Add Register */ + WRITE_REG(ETHx->MACTSADD, AddValue); +} + +/** +*\*\name ETH_GetTimeStampRegValue. +*\*\fun Gets the specified ETH MAC TimeStamp register value. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Offset (The input parameters must be the following values): +*\*\ - ETH_MACTS_SSIR_OFFSET +*\*\ - ETH_MACTS_STSR_OFFSET +*\*\ - ETH_MACTS_STNSR_OFFSET +*\*\ - ETH_MACTS_STSUR_OFFSET +*\*\ - ETH_MACTS_STNSUR_OFFSET +*\*\ - ETH_MACTS_TAR_OFFSET +*\*\ - ETH_MACTS_TTSNSR_OFFSET +*\*\ - ETH_MACTS_TTSSR_OFFSET +*\*\ - ETH_MACTS_TICNSR_OFFSET +*\*\ - ETH_MACTS_TECNSR_OFFSET +*\*\ - ETH_MACTS_TILR_OFFSET +*\*\ - ETH_MACTS_TELR_OFFSET +*\*\ - ETH_MACTS_PTTSR_OFFSET +*\*\ - ETH_MACTS_PTTNSR_OFFSET +*\*\return Corresponding MAC TimeStamp value. +**/ +uint32_t ETH_GetTimeStampRegValue(ETH_Module* ETHx, EthTsAddrType Offset) +{ + uint32_t tsRegBaseAddr; + + /* Get the ETH MAC TimeStamp register base address */ + tsRegBaseAddr = (uint32_t)&(ETHx->MACTSCTRL); + + /* Return the selected MAC TimeStamp register value */ + return (*(__IO uint32_t *)(tsRegBaseAddr + Offset)); +} + +/** +*\*\name ETH_ConfigPPSOutput. +*\*\fun Configure the PPS output, e.g. configure the output frequency, +*\*\ which defaults to one pulse per second. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param OutputFreq (The input parameters must be the following values): +*\*\ - ETH_MACPPS_FREQCTRL_B2D1 +*\*\ - ETH_MACPPS_FREQCTRL_B4D2 +*\*\ - ETH_MACPPS_FREQCTRL_B8D4 +*\*\ - ETH_MACPPS_FREQCTRL_B16D8 +*\*\ - ETH_MACPPS_FREQCTRL_B32D16 +*\*\ - ETH_MACPPS_FREQCTRL_B64D32 +*\*\ - ETH_MACPPS_FREQCTRL_B128D64 +*\*\ - ETH_MACPPS_FREQCTRL_B256D128 +*\*\ - ETH_MACPPS_FREQCTRL_B512D256 +*\*\ - ETH_MACPPS_FREQCTRL_B1024D512 +*\*\ - ETH_MACPPS_FREQCTRL_B2048D1024 +*\*\ - ETH_MACPPS_FREQCTRL_B4096D2048 +*\*\ - ETH_MACPPS_FREQCTRL_B8192D4096 +*\*\ - ETH_MACPPS_FREQCTRL_B16384D8192 +*\*\ - ETH_MACPPS_FREQCTRL_B32768D16384 +*\*\return none +**/ +void ETH_ConfigPPSOutput(ETH_Module* ETHx, uint32_t OutputFreq) +{ + /* Set PPS Output Frequency Control field */ + MODIFY_REG(ETHx->MACPPSCTRL, ETH_MACPPSCTRL_PPSCTRL, OutputFreq); +} + +/** +*\*\name ETH_SetPPSTargetTimeValue. +*\*\fun Sets the PPS target time value with seconds field and nanosecond field. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param SecondValue : +*\*\ - 0~0xFFFFFFFF +*\*\param SubSecondValue : +*\*\ - 0~0x7FFFFFFF +*\*\return none +**/ +void ETH_SetPPSTargetTimeValue(ETH_Module* ETHx, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Set MAC PPS Target Time Seconds Register */ + WRITE_REG(ETHx->MACPPSTTS, SecondValue); + /* Set MAC PPS Target Time Nanosecond Register */ + WRITE_REG(ETHx->MACPPSTTNS, SubSecondValue); +} + + + +/** +*\*\name ETH_MTLDropTxStatusCmd. +*\*\fun Enables or disables the Drop Transmit Status. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_MTLDropTxStatusCmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Tx packet status received from the MAC is dropped in the MTL */ + SET_BIT(ETHx->MTLOPMOD, ETH_MTLOPMOD_DTXSTS); + } + else + { + /* Tx packet status received from the MAC is forwarded to the application */ + CLEAR_BIT(ETHx->MTLOPMOD, ETH_MTLOPMOD_DTXSTS); + } +} + +/** +*\*\name ETH_MTLCounterPreset. +*\*\fun Preset and Initialize the MTL counters to value: 0x7F0. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_MTLCounterPreset(ETH_Module* ETHx) +{ + /* Set the CNTPRST bit */ + SET_BIT(ETHx->MTLOPMOD, ETH_MTLOPMOD_CNTPRST); +} + +/** +*\*\name ETH_MTLCounterReset. +*\*\fun Reset all counters of MTL. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note The counter reset control bit is automatically cleared after 1 clock +*\*\ cycle. +**/ +void ETH_MTLCounterReset(ETH_Module* ETHx) +{ + /* Set the CNTCLR bit */ + SET_BIT(ETHx->MTLOPMOD, ETH_MTLOPMOD_CNTCLR); +} + +/** +*\*\name ETH_FlushTransmitQueue. +*\*\fun Clears the ETH transmit FIFO. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note The MTL Transmit Queue Operation Mode Register (ETH_MTLTXQOPMOD) +*\*\ should not be written until the flush operation is complete. +*\*\ This function causes all data in the Tx FIFO to be lost or flushed. +*\*\ However, data that has been accepted by the MAC transmitter will not +*\*\ be flushed. It will be scheduled for transmission and will result in +*\*\ underflow and short packets being sent. +**/ +void ETH_FlushTransmitQueue(ETH_Module* ETHx) +{ + /* Set the FTQ bit */ + SET_BIT(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_FTQ); +} + +/** +*\*\name ETH_GetMTLUnderflowPacketCounter. +*\*\fun Get the number of packets aborted by the controller due to Tx queue +*\*\ underflow. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return Counter value: 0~0x7FF. +**/ +uint16_t ETH_GetMTLUnderflowPacketCounter(ETH_Module* ETHx) +{ + /* Return the value of the Underflow Packet Counter */ + return ((uint16_t)READ_BIT(ETHx->MTLTXQUDF, ETH_MTLTXQUDF_UFFRMCNT)); +} + +/** +*\*\name ETH_GetMTLOverflowPacketCounter. +*\*\fun Gets the number of packets discarded due to Rx queue overflow. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return Counter value: 0~0x7FF. +**/ +uint16_t ETH_GetMTLOverflowPacketCounter(ETH_Module* ETHx) +{ + /* Return the value of the Overflow Packet Counter */ + return ((uint16_t)READ_BIT(ETHx->MTLRXQMPOFCNT, ETH_MTLRXQMPOFCNT_OVFPKTCNT)); +} + +/** +*\*\name ETH_GetMTLMissedPacketCounter. +*\*\fun Gets the number of packets lost due to the application performing +*\*\ packet refresh requests against this queue. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return Counter value: 0~0x7FF. +**/ +uint16_t ETH_GetMTLMissedPacketCounter(ETH_Module* ETHx) +{ + /* Return the value of the Missed Packet Counter */ + return ((uint16_t)READ_BIT(ETHx->MTLRXQMPOFCNT, ETH_MTLRXQMPOFCNT_MISPKTCNT)); +} + + + +/** +*\*\name ETH_SoftwareReset. +*\*\fun ETH software reset, the MAC and the DMA controller reset the logic +*\*\ and all internal registers of the DMA, MTL, and MAC. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note 1. The software reset status bit (SWR) is automatically cleared after +*\*\ the reset operation is completed. +*\*\ 2. Before reprogramming any ETH register, a value of zero should be +*\*\ read in SWR bit. +*\*\ 3. The SWR bit must be read at least 4 CSR clock cycles after it is +*\*\ written to 1. +**/ +void ETH_SoftwareReset(ETH_Module* ETHx) +{ + /* Set the SWR bit */ + SET_BIT(ETHx->DMAMODE, ETH_DMAMODE_SWR); +} + +/** +*\*\name ETH_TxDMACmd. +*\*\fun Enables or disables the DMA transmission. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_TxDMACmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA transmission */ + SET_BIT(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_ST); + } + else + { + /* Disable the DMA transmission */ + CLEAR_BIT(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_ST); + } +} + +/** +*\*\name ETH_RxDMACmd. +*\*\fun Enables or disables the DMA reception. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_RxDMACmd(ETH_Module* ETHx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA reception */ + SET_BIT(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_SR); + } + else + { + /* Disable the DMA reception */ + CLEAR_BIT(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_SR); + } +} + +/** +*\*\name ETH_ResumeDMATransmission. +*\*\fun Resume TX DMA by writing any value to transmit descriptor tail pointer +*\*\ register when TX DMA enters suspend mode. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note This function is only applicable when the DMA enters suspend mode. +**/ +void ETH_ResumeDMATransmission(ETH_Module* ETHx) +{ + /* Write ETH_DMACH0TXDTP register */ + WRITE_REG(ETHx->DMACH0TXDTP, 0U); +} + +/** +*\*\name ETH_ResumeDMAReception. +*\*\fun Resume RX DMA by writing any value to receive descriptor tail pointer +*\*\ register when RX DMA enters suspend mode. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +*\*\note This function is only applicable when the DMA enters suspend mode. +**/ +void ETH_ResumeDMAReception(ETH_Module* ETHx) +{ + /* Write ETH_DMACH0RXDTP register */ + WRITE_REG(ETHx->DMACH0RXDTP, 0U); +} + +/** +*\*\name ETH_SetRxInterruptWatchdogTimer. +*\*\fun Set the watchdog timer for the DMA receive interrupt. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param CntUnit (The input parameters must be the following values): +*\*\ - ETH_DMARXINT_WDGTIM_CNTUNIT_256 +*\*\ - ETH_DMARXINT_WDGTIM_CNTUNIT_512 +*\*\ - ETH_DMARXINT_WDGTIM_CNTUNIT_1024 +*\*\ - ETH_DMARXINT_WDGTIM_CNTUNIT_2048 +*\*\param CntValue : +*\*\ - Count value: 0~0x000000FF. +*\*\return none +*\*\note Timer cycles = count unit * count value (CntUnit * CntValue) system +*\*\ clock cycles. +**/ +void ETH_SetRxInterruptWatchdogTimer(ETH_Module* ETHx, uint32_t CntUnit, uint32_t CntValue) +{ + /* Set the RWTU bit and RWT bit */ + MODIFY_REG(ETHx->DMACH0RXINTWT, (ETH_DMACH0RXINTWT_RWTU | ETH_DMACH0RXINTWT_RWT), (CntUnit | CntValue)); +} + +/** +*\*\name ETH_GetCurrentTxDescriptorAddress. +*\*\fun Gets the address of the current application transmit descriptor read +*\*\ by the DMA. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return The value of the current Tx descriptor address. +**/ +uint32_t ETH_GetCurrentTxDescriptorAddress(ETH_Module* ETHx) +{ + /* Return the value of ETH_DMACH0CATXD */ + return (READ_REG(ETHx->DMACH0CATXD)); +} + +/** +*\*\name ETH_GetCurrentRxDescriptorAddress. +*\*\fun Gets the address of the current application receive descriptor read +*\*\ by the DMA. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return The value of the current Rx descriptor address. +**/ +uint32_t ETH_GetCurrentRxDescriptorAddress(ETH_Module* ETHx) +{ + /* Return the value of ETH_DMACH0CARXD */ + return (READ_REG(ETHx->DMACH0CARXD)); +} + +/** +*\*\name ETH_GetCurrentTxBufferAddress. +*\*\fun Gets the address of the current application transmit buffer read +*\*\ by the DMA. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return The value of the current Tx buffer address. +**/ +uint32_t ETH_GetCurrentTxBufferAddress(ETH_Module* ETHx) +{ + /* Return the value of ETH_DMACH0CATXB */ + return (READ_REG(ETHx->DMACH0CATXB)); +} + +/** +*\*\name ETH_GetCurrentRxBufferAddress. +*\*\fun Gets the address of the current application receive buffer read +*\*\ by the DMA. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return The value of the current Rx buffer address. +**/ +uint32_t ETH_GetCurrentRxBufferAddress(ETH_Module* ETHx) +{ + /* Return the value of ETH_DMACH0CARXB */ + return (READ_REG(ETHx->DMACH0CARXB)); +} + +/** +*\*\name ETH_GetTxDMAErrorType. +*\*\fun Get the type of TX DMA error that caused the fatal bus error. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return TX DMA Error Bits[2:0] Value: +*\*\ - bit[0]: +*\*\ - 1: Error during read transfer +*\*\ - 0: Error during write transfer +*\*\ - bit[1]: +*\*\ - 1: Error during descriptor access +*\*\ - 0: Error during data buffer access +*\*\ - bit[2]: +*\*\ - 1: Error during data transfer by Tx DMA +*\*\ - 0: No Error during data transfer by Tx DMA +*\*\ Invalid value: +*\*\ - 0xFF +*\*\note This function returns a valid value only if a fatal bus error occurs +*\*\ (FBE set to 1). And these error types do not generate interrupts. +**/ +uint8_t ETH_GetTxDMAErrorType(ETH_Module* ETHx) +{ + uint8_t ReturnValue; + + /* Check if a fatal bus error has occurred */ + if (READ_BIT(ETHx->DMACH0STS, ETH_DMACH0STS_FBE) != (uint32_t)RESET) + { + /* Return the value of the TX DMA error bits */ + ReturnValue = (uint8_t)(READ_BIT(ETHx->DMACH0STS, ETH_DMACH0STS_TEB) >> 16); + } + else + { + /* Return invalid value 0xFF */ + ReturnValue = (uint8_t)(0xFFU); + } + + return ReturnValue; +} + +/** +*\*\name ETH_GetRxDMAErrorType. +*\*\fun Get the type of RX DMA error that caused the fatal bus error. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return RX DMA Error Bits[2:0] Value: +*\*\ - bit[0]: +*\*\ - 1: Error during read transfer +*\*\ - 0: Error during write transfer +*\*\ - bit[1]: +*\*\ - 1: Error during descriptor access +*\*\ - 0: Error during data buffer access +*\*\ - bit[2]: +*\*\ - 1: Error during data transfer by Rx DMA +*\*\ - 0: No Error during data transfer by Rx DMA +*\*\ Invalid value: +*\*\ - 0xFF +*\*\note This function returns a valid value only if a fatal bus error occurs +*\*\ (FBE set to 1). And these error types do not generate interrupts. +**/ +uint8_t ETH_GetRxDMAErrorType(ETH_Module* ETHx) +{ + uint8_t ReturnValue; + + /* Check if a fatal bus error has occurred */ + if (READ_BIT(ETHx->DMACH0STS, ETH_DMACH0STS_FBE) != (uint32_t)RESET) + { + /* Return the value of the RX DMA error bits */ + ReturnValue = (uint8_t)(READ_BIT(ETHx->DMACH0STS, ETH_DMACH0STS_REB) >> 19); + } + else + { + /* Return invalid value 0xFF */ + ReturnValue = (uint8_t)(0xFFU); + } + + return ReturnValue; +} + +/** +*\*\name ETH_GetDMACh0DroppedPacketCounter. +*\*\fun Get the number of packet counters dropped by the DMA due to bus errors +*\*\ or programming the RPF field in the DMA Channel 0 Rx Control Register. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return Counter value: 0~0x7FF. +**/ +uint16_t ETH_GetDMACh0DroppedPacketCounter(ETH_Module* ETHx) +{ + /* Return the value of the Dropped Packet Counter */ + return ((uint16_t)READ_BIT(ETHx->DMACH0DPCNT, ETH_DMACH0DPCNT_DPC)); +} + +/** +*\*\name ETH_GetDMACh0ERICounter. +*\*\fun Get the number of counts for the number of times an ERI (Early Receive +*\*\ Interrupt) is valid. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return Counter value: 0~0xFFF. +**/ +uint16_t ETH_GetDMACh0ERICounter(ETH_Module* ETHx) +{ + /* Return the value of the ERI Counter */ + return ((uint16_t)READ_BIT(ETHx->DMACH0RXERICNT, ETH_DMACH0RXERICNT_ECNT)); +} + + + +/** +*\*\name ETH_RxDescAssignMemory. +*\*\fun Assign memory buffers to a DMA Rx descriptor. +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param Index : +*\*\ - Index of the DMA Rx descriptor. +*\*\param pBuffer1 : +*\*\ - Points to Buffer1 address. +*\*\param pBuffer2 : +*\*\ - Points to Buffer2 address, if available. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_RxDescAssignMemory(ETH_InfoType* pInfo, uint32_t Index, uint8_t* pBuffer1, uint8_t* pBuffer2) +{ + ETH_DMADescType* pRxDescriptor = NULL; + /* Get the descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pInfo->RxDescList.RxDesc[Index]; + + /* Check the parameter */ + if ((pBuffer1 == NULL) || (Index >= ETH_RX_DESC_NUMBER)) + { + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + + /* Write buffer1 address to RDES0 */ + pRxDescriptor->DESC0 = (uint32_t)pBuffer1; + /* Backup buffer1 address */ + pRxDescriptor->Buf1Addr = (uint32_t)pBuffer1; + /* Set buffer1 address valid bit to RDES3 */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_BUF1V); + + if (pBuffer2 != NULL) + { + /* Write buffer2 address to RDES2 */ + pRxDescriptor->DESC2 = (uint32_t)pBuffer2; + /* Backup buffer2 address */ + pRxDescriptor->Buf2Addr = (uint32_t)pBuffer2; + /* Set buffer2 address valid bit to RDES3 */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_BUF2V); + } + + /* Set OWN bit to RDES3 */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_OWN); + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_BuildRxDescriptors. +*\*\fun This function gives back Rx Desc of the last received Packet to the DMA, +*\*\ so ETH DMA will be able to use these descriptors to receive next Packets. +*\*\ It should be called after processing the received Packet. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_BuildRxDescriptors(ETH_Module* ETHx, ETH_InfoType* pInfo) +{ + uint32_t TempIndex; + uint32_t DescIndex; + uint32_t TotalAppDescNbr; + ETH_DMADescType* pRxDescriptor = NULL; + ETH_RxDescListType* pRxDescList = NULL; + + pRxDescList = &pInfo->RxDescList; + DescIndex = pRxDescList->FirstAppDesc; + TotalAppDescNbr = pRxDescList->AppDescNbr; + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + if (pRxDescList->AppDescNbr == 0U) + { + /* No Rx descriptors to build */ + return NO_DESC_TO_BUILD; + } + + if (pRxDescList->AppContextDesc != 0U) + { + /* A context descriptor is available */ + TotalAppDescNbr += 1U; + } + + for (TempIndex = 0; TempIndex < TotalAppDescNbr; TempIndex++) + { + /* Set Buffer1 address */ + WRITE_REG(pRxDescriptor->DESC0, pRxDescriptor->Buf1Addr); + /* Set Buffer1 valid bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_BUF1V); + + /* Check if Buffer2 is valid */ + if (pRxDescriptor->Buf2Addr != 0U) + { + /* Set Buffer2 address */ + WRITE_REG(pRxDescriptor->DESC2, pRxDescriptor->Buf2Addr); + /* Set Buffer2 valid bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_BUF2V); + } + + /* Set OWN bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_OWN); + + /* Check if interrupt mode */ + if (pRxDescList->ItMode != 0U) + { + /* Set IOC bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_IOC); + } + + if (TempIndex < (pRxDescList->AppDescNbr - 1U)) + { + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + } + } + + /* Set the Tail pointer address to the last rx descriptor hold by the app */ + WRITE_REG(ETHx->DMACH0RXDTP, (uint32_t)pRxDescriptor); + + /* Reset the Application desc number */ + pRxDescList->AppDescNbr = 0U; + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_PrepareTxDescriptors. +*\*\fun Prepare Tx DMA descriptor before transmission. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param pTxPacket : +*\*\ - Points to the TX packet, containing some configuration information +*\*\param ItMode : +*\*\ - Mode Selection: 1 indicates to interrupt mode, 0 indicates to polling mode. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_PrepareTxDescriptors(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_TxPacketType* pTxPacket, uint32_t ItMode) +{ + uint32_t TempIndex; + uint32_t DescIndex; + uint32_t DescCnt = 0; + uint32_t FirstDescIndex; + ETH_BufferType* pTxBuf = NULL; + ETH_DMADescType* pTxDescriptor = NULL; + ETH_TxDescListType* pTxDescList = NULL; + + pTxDescList = &pInfo->TxDescList; + pTxBuf = pTxPacket->pTxBuffer; + DescIndex = pTxDescList->CurTxDesc; + FirstDescIndex = pTxDescList->CurTxDesc; + pTxDescriptor = (ETH_DMADescType*)(pTxDescList->TxDesc[DescIndex]); + + /* Check if the current TX descriptor is owned by the application */ + if ((pTxDescriptor->DESC3 & ETH_DMATXND3RF_OWN) == ETH_DMATXND3RF_OWN) + { + /* Returns directly when the current TX descriptor is owned by the DMA */ + return DESC_OWNED_BY_DMA; + } + + /* Starting to configure TX context descriptors */ + /* If VLAN tag is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + { + // N32H487 does not support VLAN insertion or replacemen + + /* If inner VLAN is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET) + { + // N32H487 does not support double VLAN processing + } + } + + /* If tcp segementation is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + // N32H487 does not support TCP segementation + } + + /* If One-Step Timestamp Correction is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_OSTC) != (uint32_t)RESET) + { + /* Set One-Step Timestamp Correction Enable bit */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXCD3_OSTC); + /* Set One-Step Timestamp Correction Input Valid bit */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXCD3_TCMSSV); + } + + if(((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + || ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + || ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_OSTC) != (uint32_t)RESET)) + { + /* Set as context descriptor */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXCD3_CTXT); + /* Set own bit */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXCD3_OWN); + /* Increment current tx descriptor index */ + __ETH_TXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pTxDescriptor = (ETH_DMADescType*)(pTxDescList->TxDesc[DescIndex]); + + /* Incremental Descriptor Count */ + DescCnt += 1U; + + /* Check if the current TX descriptor is owned by the application */ + if ((pTxDescriptor->DESC3 & ETH_DMATXCD3_OWN) == ETH_DMATXCD3_OWN) + { + /* Get the first TX descriptor address */ + pTxDescriptor = (ETH_DMADescType*)(pTxDescList->TxDesc[FirstDescIndex]); + /* Clear the OWN bit of first Descriptor */ + CLEAR_BIT(pTxDescriptor->DESC3, ETH_DMATXCD3_OWN); + /* Returns directly when the current TX descriptor is owned by the DMA */ + return DESC_OWNED_BY_DMA; + } + } + + /* Starting to configure TX Normal descriptor */ + /* Set header or buffer 1 address */ + WRITE_REG(pTxDescriptor->DESC0, (uint32_t)pTxBuf->pBuf); + /* Set header or buffer 1 Length */ + MODIFY_REG(pTxDescriptor->DESC2, ETH_DMATXND2RF_B1L, pTxBuf->Len); + + /* If the next buffer exists */ + if (pTxBuf->pNext != NULL) + { + /* Get buffer address */ + pTxBuf = pTxBuf->pNext; + /* Set buffer 2 address */ + WRITE_REG(pTxDescriptor->DESC1, (uint32_t)pTxBuf->pBuf); + /* Set buffer 2 Length */ + MODIFY_REG(pTxDescriptor->DESC2, ETH_DMATXND2RF_B2L, (pTxBuf->Len << 16)); + } + else + { + /* Set buffer 2 address field to 0 */ + WRITE_REG(pTxDescriptor->DESC1, 0x0U); + /* Set buffer 2 Length field to 0 */ + MODIFY_REG(pTxDescriptor->DESC2, ETH_DMATXND2RF_B2L, 0); + } + + /* If tcp segementation is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + // N32H487 does not support TCP segementation + } + else + { + /* Set Frame Length */ + MODIFY_REG(pTxDescriptor->DESC3, ETH_DMATXND3RF_FL, pTxPacket->Length); + + /* If Checksum is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + { + /* Set Checksum Insertion Control bits */ + MODIFY_REG(pTxDescriptor->DESC3, ETH_DMATXND3RF_CIC, pTxPacket->ChecksumCtrl); + } + } + + /* If CRC Pad Control is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) + { + /* Set CRC Pad Control bits */ + MODIFY_REG(pTxDescriptor->DESC3, ETH_DMATXND3RF_CPC, pTxPacket->CRCPadCtrl); + } + + /* If VLAN Tag Control is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + { + // N32H487 does not support SA and VLAN Insertion on Tx option + } + + /* If Source Address Control is enabled for this packet */ + if ((pTxPacket->Attributes & ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET) + { + // N32H487 does not support SA and VLAN Insertion on Tx option + } + + /* Set as First Descriptor */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_FD); + /* Set as NORMAL descriptor */ + CLEAR_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_CTXT); + /* Set own bit of First descriptor */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_OWN); + + /* Only if the packet is splitted into more than one descriptors > 1 */ + while (pTxBuf->pNext != NULL) + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_LD); + + /* Increment current tx descriptor index */ + __ETH_TXDESC_INDEX_INCR(DescIndex, 1); + /* Get current descriptor address */ + pTxDescriptor = (ETH_DMADescType*)(pTxDescList->TxDesc[DescIndex]); + + /* Incremental Descriptor Count */ + DescCnt += 1U; + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_FD); + + /* Check if the current TX descriptor is owned by the application */ + if ((pTxDescriptor->DESC3 & ETH_DMATXND3RF_OWN) == ETH_DMATXND3RF_OWN) + { + DescIndex = FirstDescIndex; + /* Get the first TX descriptor address */ + pTxDescriptor = (ETH_DMADescType*)(pTxDescList->TxDesc[DescIndex]); + + /* Clear the OWN bit of all previous descriptors */ + for (TempIndex = 0; TempIndex < DescCnt; TempIndex++) + { + /* Clear the OWN bit of new Descriptor */ + CLEAR_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_OWN); + /* Increment current tx descriptor index */ + __ETH_TXDESC_INDEX_INCR(DescIndex, 1); + /* Get current descriptor address */ + pTxDescriptor = (ETH_DMADescType*)(pTxDescList->TxDesc[DescIndex]); + } + + /* Returns directly when the current TX descriptor is owned by the DMA */ + return DESC_OWNED_BY_DMA; + } + + /* Get the next Tx buffer in the list */ + pTxBuf = pTxBuf->pNext; + + /* Set header or buffer 1 address */ + WRITE_REG(pTxDescriptor->DESC0, (uint32_t)pTxBuf->pBuf); + /* Set header or buffer 1 Length */ + MODIFY_REG(pTxDescriptor->DESC2, ETH_DMATXND2RF_B1L, pTxBuf->Len); + + /* If the next buffer exists */ + if (pTxBuf->pNext != NULL) + { + /* Get buffer address */ + pTxBuf = pTxBuf->pNext; + /* Set buffer 2 address */ + WRITE_REG(pTxDescriptor->DESC1, (uint32_t)pTxBuf->pBuf); + /* Set buffer 2 Length */ + MODIFY_REG(pTxDescriptor->DESC2, ETH_DMATXND2RF_B2L, (pTxBuf->Len << 16)); + } + else + { + /* Set buffer 2 address field to 0 */ + WRITE_REG(pTxDescriptor->DESC1, 0x0U); + /* Set buffer 2 Length field to 0 */ + MODIFY_REG(pTxDescriptor->DESC2, ETH_DMATXND2RF_B2L, 0); + } + + /* Set Frame Length */ + MODIFY_REG(pTxDescriptor->DESC3, ETH_DMATXND3RF_FL, pTxPacket->Length); + + /* Set as NORMAL descriptor */ + CLEAR_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_CTXT); + /* Set own bit of this descriptor */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_OWN); + } + + /* + Note: + The LD bit is 0 and the Early Transmit Interrupt (ETIC) is turned on, + which controls the ETI; the LD bit is 1, which controls the Transmit + Interrupt (TI). + The ETI is generated after completing a data transfer from the buffer + of the descriptor for which the IOC is set, and the TI is generated + only after a complete packet is transferred to the TxFIFO. + */ + if (ItMode) + { + /* Set Interrupt on Completion bit */ + SET_BIT(pTxDescriptor->DESC2, ETH_DMATXND2RF_IOC); + } + else + { + /* Clear Interrupt on Completion bit */ + CLEAR_BIT(pTxDescriptor->DESC2, ETH_DMATXND2RF_IOC); + } + + /* Set as Last Descriptor */ + SET_BIT(pTxDescriptor->DESC3, ETH_DMATXND3RF_LD); + + /* Update current Tx descriptor index */ + pTxDescList->CurTxDesc = DescIndex; + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_Transmit. +*\*\fun Send packets via polling mode. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param pTxPacket : +*\*\ - Points to the TX packet, containing some configuration information +*\*\param Timeout : +*\*\ - timeout value +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_Transmit(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_TxPacketType* pTxPacket, uint32_t Timeout) +{ + uint32_t TickStart; + EthFuncStatusType TempStatus; + const ETH_DMADescType* pTxDescriptor; + + /* Check the pTxPacket parameter */ + if (pTxPacket == NULL) + { + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + + /* Config DMA Tx descriptor by Tx Packet info */ + TempStatus = ETH_PrepareTxDescriptors(ETHx, pInfo, pTxPacket, 0); + + /* Check if it has been successfully configured */ + if (TempStatus != ETH_SUCCESS) + { + /* Return ERROR */ + return TempStatus; + } + + /* Get the descriptor address */ + pTxDescriptor = (ETH_DMADescType*)(&pInfo->TxDescList)->TxDesc[pInfo->TxDescList.CurTxDesc]; + /* Increment current tx descriptor index */ + __ETH_TXDESC_INDEX_INCR(pInfo->TxDescList.CurTxDesc, 1U); + /* Send a polling command to the TX DMA by writing the address of the next idle + descriptor to the ETH_DMACH0TXDTP register, and then start the transfer */ + WRITE_REG(ETHx->DMACH0TXDTP, (uint32_t)pInfo->TxDescList.TxDesc[pInfo->TxDescList.CurTxDesc]); + + /* Check that DWT is enabled or not */ + if ((DEM_CR & DEM_CR_TRCENA) == (uint32_t)RESET) + { + /* Enable and initialize DWT */ + __ETH_TICK_START(); + } + + /* Get tick */ + TickStart = __ETH_GET_TICK; + + /* Wait for data to be transmitted or timeout occured */ + while ((pTxDescriptor->DESC3 & ETH_DMATXND3WBF_OWN) != (uint32_t)RESET) + { + /* Check for fatal bus error */ + if ((ETHx->DMACH0STS & ETH_DMACH0STS_FBE) != (uint32_t)RESET) + { + /* Return ERROR */ + return FATAL_BUS_ERROR; + } + + /* Check for the Timeout */ + if (((__ETH_GET_TICK - TickStart) > Timeout) || (Timeout == 0U)) + { + /* Disable tick */ + __ETH_TICK_STOP(); + + /* Return timeout */ + return ETH_ERROR_TIMEOUT; + } + } + + /* Disable tick */ + __ETH_TICK_STOP(); + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_TransmitIT. +*\*\fun Send packets via interrupt mode. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param pTxPacket : +*\*\ - Points to the TX packet, containing some configuration information +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_TransmitIT(ETH_Module* ETHx, ETH_InfoType* pInfo, ETH_TxPacketType* pTxPacket) +{ + EthFuncStatusType TempStatus; + + /* Check the pTxPacket parameter */ + if (pTxPacket == NULL) + { + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + + /* Config DMA Tx descriptor by Tx Packet info */ + TempStatus = ETH_PrepareTxDescriptors(ETHx, pInfo, pTxPacket, 1); + + /* Check if it has been successfully configured */ + if (TempStatus != ETH_SUCCESS) + { + /* Return ERROR */ + return TempStatus; + } + + /* Increment current tx descriptor index */ + __ETH_TXDESC_INDEX_INCR(pInfo->TxDescList.CurTxDesc, 1U); + /* Send a polling command to the TX DMA by writing the address of the next idle + descriptor to the ETH_DMACH0TXDTP register, and then start the transfer */ + WRITE_REG(ETHx->DMACH0TXDTP, (uint32_t)pInfo->TxDescList.TxDesc[pInfo->TxDescList.CurTxDesc]); + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_IsRxDataAvailable. +*\*\fun Checks the data of received packets. +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return 1 or 0. +**/ +uint8_t ETH_IsRxDataAvailable(ETH_InfoType* pInfo) +{ + uint32_t DescIndex; + uint32_t DescCnt = 0; + uint32_t AppDescCnt = 0; + uint32_t AppFirstDescIndex = 0; + ETH_DMADescType* pRxDescriptor = NULL; + ETH_RxDescListType* pRxDescList = NULL; + + pRxDescList = &pInfo->RxDescList; + DescIndex = pRxDescList->CurRxDesc; + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + /* Check the number of descriptors */ + if (pRxDescList->AppDescNbr != 0) + { + /* Data already received by not yet processed */ + return 0; + } + + /* Check if descriptor is not owned by DMA */ + while (((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_OWN) == (uint32_t)RESET) && (DescCnt < ETH_RX_DESC_NUMBER)) + { + /* Incremental Descriptor Count */ + DescCnt += 1U; + + /* Check if last descriptor */ + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_LD) != (uint32_t)RESET) + { + /* Increment the number of descriptors to be passed to the application */ + AppDescCnt += 1U; + + /* If the first descriptor */ + if (AppDescCnt == 1U) + { + /* Record the index corresponding to the first descriptor */ + AppFirstDescIndex = DescIndex; + } + + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + /* Check if descriptor is not owned by DMA */ + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_OWN) == (uint32_t)RESET) + { + /* Check for Context descriptor */ + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_CTXT) != (uint32_t)RESET) + { + /* Indicated as a context descriptor */ + pRxDescList->AppContextDesc = 1; + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + } + } + /* Saves the current descriptor index */ + pRxDescList->CurRxDesc = DescIndex; + /* Saves the first descriptor subscript */ + pRxDescList->FirstAppDesc = AppFirstDescIndex; + /* Saves the number of descriptors */ + pRxDescList->AppDescNbr = AppDescCnt; + + /* Packets received, return 1 */ + return 1; + } + /* Check if first descriptor */ + else if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_FD) != (uint32_t)RESET) + { + /* Record the index corresponding to the first descriptor */ + AppFirstDescIndex = DescIndex; + /* Increment the number of descriptors to be passed to the application */ + AppDescCnt = 1U; + + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + } + /* It should be an intermediate descriptor */ + else + { + /* Increment the number of descriptors to be passed to the application */ + AppDescCnt += 1U; + + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + } + } + + /* Build Descriptors if an incomplete Packet is received */ + if (AppDescCnt > 0U) + { + /* Get the first descriptor */ + DescIndex = AppFirstDescIndex; + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + for (DescCnt = 0; DescCnt < AppDescCnt; DescCnt++) + { + /* Write buffer1 address to RDES0 */ + pRxDescriptor->DESC0 = pRxDescriptor->Buf1Addr; + /* Set buffer1 address valid bit to RDES3 */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_BUF1V); + + if (pRxDescriptor->Buf2Addr != (uint32_t)RESET) + { + /* Write buffer2 address to RDES2 */ + pRxDescriptor->DESC2 = pRxDescriptor->Buf2Addr; + /* Set buffer2 address valid bit to RDES3 */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_BUF2V); + } + + /* Set OWN bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_OWN); + + if (pRxDescList->ItMode != (uint32_t)RESET) + { + /* Set IOC bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_IOC); + } + + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + } + } + + /* No received Packet */ + pRxDescList->AppDescNbr = 0U; + + /* No received Packet, return 0 */ + return 0; +} + +/** +*\*\name ETH_GetRxDataBuffer. +*\*\fun Used to fetch the data buffer when processing the received Packet. +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param pRxBuffer : +*\*\ - Points to the RX buffer, ETH_BufferType structure. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_GetRxDataBuffer(ETH_InfoType* pInfo, ETH_BufferType* pRxBuffer) +{ + uint32_t TempIndex; + uint32_t DescIndex; + uint32_t LastDescLen; + uint32_t AccumulatedLen = 0; + + ETH_BufferType* pRxBuf = NULL; + ETH_DMADescType* pRxDescriptor = NULL; + ETH_RxDescListType* pRxDescList = NULL; + + pRxBuf = pRxBuffer; + pRxDescList = &pInfo->RxDescList; + DescIndex = pRxDescList->FirstAppDesc; + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + /* Check the pRxBuffer parameter */ + if (pRxBuf == NULL) + { + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + + if (pRxDescList->AppDescNbr == 0U) + { + /* Check for data received */ + if (ETH_IsRxDataAvailable(pInfo) == 0U) + { + /* No data to be transferred to the application */ + return NO_DATA_TRANSFER; + } + else + { + /* Update the current descriptor index */ + DescIndex = pRxDescList->FirstAppDesc; + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + } + } + + /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */ + for (TempIndex = 0; TempIndex < (pRxDescList->AppDescNbr - 1); TempIndex++) + { + /* Get Address of the first buffer address */ + pRxBuf->pBuf = (uint8_t*)pRxDescriptor->Buf1Addr; + /* Get length of the first buffer address */ + pRxBuf->Len = pInfo->RxBuffLen; + + /* Check if the second buffer address of this descriptor is valid */ + if (pRxDescriptor->Buf2Addr != 0U) + { + /* Point to next buffer */ + pRxBuf = pRxBuf->pNext; + /* Get Address of the second buffer address */ + pRxBuf->pBuf = (uint8_t*)pRxDescriptor->Buf2Addr; + /* Get length of the second buffer address */ + pRxBuf->Len = pInfo->RxBuffLen; + } + + /* Get accumulated length until this descriptor */ + AccumulatedLen = READ_BIT(pRxDescriptor->DESC3, ETH_DMARXND3WBF_PL); + + /* Increment current rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get current descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + /* Point to next buffer */ + pRxBuf = pRxBuf->pNext; + } + + /* Get last descriptor data length */ + LastDescLen = READ_BIT(pRxDescriptor->DESC3, ETH_DMARXND3WBF_PL) - AccumulatedLen; + + /* Get Address of the first buffer address */ + pRxBuf->pBuf = (uint8_t*)pRxDescriptor->Buf1Addr; + + /* Data is in only one buffer */ + if (LastDescLen <= pInfo->RxBuffLen) + { + /* Record buffer length */ + pRxBuf->Len = LastDescLen; + } + /* Data is in two buffers */ + else if (pRxDescriptor->Buf2Addr != 0U) + { + /* Get the Length of the first buffer address */ + pRxBuf->Len = pInfo->RxBuffLen; + /* Point to next buffer */ + pRxBuf = pRxBuf->pNext; + /* Get the Address of the second buffer address */ + pRxBuf->pBuf = (uint8_t*)pRxDescriptor->Buf2Addr; + /* Get the Length of the second buffer address */ + pRxBuf->Len = LastDescLen - (pInfo->RxBuffLen); + } + else + { + /* Return ERROR */ + return ETH_ERROR_PARAM; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_GetRxDataLength. +*\*\fun Used to fetch the data length of last received Packet when processing the +*\*\ received Packet. +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return NO_DATA_TRANSFER or length of last received Packet. +**/ +uint32_t ETH_GetRxDataLength(ETH_InfoType* pInfo) +{ + uint32_t DescIndex; + ETH_DMADescType* pRxDescriptor = NULL; + ETH_RxDescListType* pRxDescList = NULL; + + pRxDescList = &pInfo->RxDescList; + DescIndex = pRxDescList->FirstAppDesc; + + if (pRxDescList->AppDescNbr == 0U) + { + /* Check for data received */ + if (ETH_IsRxDataAvailable(pInfo) == 0U) + { + /* No data to be transferred to the application */ + return (uint32_t)NO_DATA_TRANSFER; + } + } + + /* Get index of last descriptor */ + __ETH_RXDESC_INDEX_INCR(DescIndex, (pRxDescList->AppDescNbr - 1U)); + /* Point to last descriptor */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + /* Return the length of last received Packet */ + return READ_BIT(pRxDescriptor->DESC3, ETH_DMARXND3WBF_PL); +} + +/** +*\*\name ETH_GetRxPacketInfo. +*\*\fun Get the Rx Packet info (Packet type, VLAN tag, Filters status, ...). +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\param pRxPacket : +*\*\ - Points to the RX packet, containing some packet information. +*\*\return One of EthFuncStatusType. +**/ +EthFuncStatusType ETH_GetRxPacketInfo(ETH_InfoType* pInfo, ETH_RxPacketType* pRxPacket) +{ + uint32_t DescIndex; + ETH_DMADescType* pRxDescriptor = NULL; + ETH_RxDescListType* pRxDescList = NULL; + + pRxDescList = &pInfo->RxDescList; + DescIndex = pRxDescList->FirstAppDesc; + + if (pRxDescList->AppDescNbr == 0U) + { + /* Check for data received */ + if (ETH_IsRxDataAvailable(pInfo) == 0U) + { + /* No data to be transferred to the application */ + return NO_DATA_TRANSFER; + } + } + + /* Get index of last descriptor */ + __ETH_RXDESC_INDEX_INCR(DescIndex, (pRxDescList->AppDescNbr - 1U)); + /* Point to last descriptor */ + pRxDescriptor = (ETH_DMADescType*)pRxDescList->RxDesc[DescIndex]; + + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_ES) != (uint32_t)RESET) + { + /* Get packet error status from RDES3 */ + pRxPacket->ErrorCode = READ_BIT(pRxDescriptor->DESC3, (ETH_DMARXND3WBF_DE + | ETH_DMARXND3WBF_RE + | ETH_DMARXND3WBF_OE + | ETH_DMARXND3WBF_RWT + | ETH_DMARXND3WBF_GP + | ETH_DMARXND3WBF_CE)); + } + else + { + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_RS0V) != (uint32_t)RESET) + { + /* Check for Double VLAN packet types */ + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_LT) == ETH_DMARXND3WBF_LT_DVLAN) + { + // N32H487 does not support Double VLAN Tag + } + else + { + /* Get Outer VLAN Tag */ + pRxPacket->VlanTag = READ_BIT(pRxDescriptor->DESC0, ETH_DMARXND0WBF_OVT); + } + } + + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_RS1V) != (uint32_t)RESET) + { + /* Get Payload type */ + pRxPacket->PayloadType = READ_BIT(pRxDescriptor->DESC1, ETH_DMARXND1WBF_PT); + /* Get Header type */ + pRxPacket->PayloadType = READ_BIT(pRxDescriptor->DESC1, (ETH_DMARXND1WBF_IPV4 + | ETH_DMARXND1WBF_IPV6)); + /* Get Checksum status */ + pRxPacket->PayloadType = READ_BIT(pRxDescriptor->DESC1, (ETH_DMARXND1WBF_IPHE + | ETH_DMARXND1WBF_IPCB + | ETH_DMARXND1WBF_IPCE)); + } + + if ((pRxDescriptor->DESC3 & ETH_DMARXND3WBF_RS2V) != (uint32_t)RESET) + { + /* Get MAC Filtering Status */ + pRxPacket->MACFilterStatus = READ_BIT(pRxDescriptor->DESC2, (ETH_DMARXND2WBF_VFS + | ETH_DMARXND2WBF_SAF + | ETH_DMARXND2WBF_DAF + | ETH_DMARXND2WBF_HF)); + } + } + + /* Get the Rx Descriptors count */ + pRxPacket->DescriptorCnt = pRxDescList->AppDescNbr; + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** +*\*\name ETH_Start. +*\*\fun Turn on ETH via polling mode, including turning on TX and RX DMA engines, +*\*\ turning on TX and RX MAC controllers, etc. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none. +**/ +void ETH_Start(ETH_Module* ETHx) +{ + /* Start the MAC Transmitter */ + SET_BIT(ETHx->MACCFG, ETH_MACCFG_TE); + + /* Start the MAC Receiver */ + SET_BIT(ETHx->MACCFG, ETH_MACCFG_RE); + + /* Set the Flush Transmit Queue bit */ + SET_BIT(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_FTQ); + + /* Start the DMA Transmitter */ + SET_BIT(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_ST); + + /* Start the DMA Receiver */ + SET_BIT(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_SR); + + /* Clear Tx and Rx process stopped flags */ + SET_BIT(ETHx->DMACH0STS, (ETH_DMACH0STS_TPS | ETH_DMACH0STS_RPS)); +} + +/** +*\*\name ETH_StartIT. +*\*\fun Turn on ETH via interrupt mode, including turning on TX and RX DMA engines, +*\*\ turning on TX and RX MAC controllers, etc. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return none. +**/ +void ETH_StartIT(ETH_Module* ETHx, ETH_InfoType* pInfo) +{ + uint32_t TempIndex, DescIndex = 0; + ETH_DMADescType* pRxDescriptor = NULL; + + /* Get the descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pInfo->RxDescList.RxDesc[DescIndex]; + + /* Set IOC bit to all Rx descriptors */ + for (TempIndex = 0; TempIndex < ETH_RX_DESC_NUMBER; TempIndex++) + { + /* Set Interrupt on Completion bit */ + SET_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_IOC); + /* Increment rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get the descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pInfo->RxDescList.RxDesc[DescIndex]; + } + + /* Enable ETH DMA Transmit Interrupt, Receive Interrupt, Fatal Bus Error Interrupt, + Abnormal Interrupt Summary, Normal Interrupt Summary*/ + SET_BIT(ETHx->DMACH0INTEN, (ETH_DMACH0INTEN_TIE | ETH_DMACH0INTEN_RIE + | ETH_DMACH0INTEN_NIE | ETH_DMACH0INTEN_AIE + | ETH_DMACH0INTEN_FBEE)); + + /* Start the MAC Transmitter */ + SET_BIT(ETHx->MACCFG, ETH_MACCFG_TE); + + /* Start the MAC Receiver */ + SET_BIT(ETHx->MACCFG, ETH_MACCFG_RE); + + /* Set the Flush Transmit Queue bit */ + SET_BIT(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_FTQ); + + /* Start the DMA Transmitter */ + SET_BIT(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_ST); + + /* Start the DMA Receiver */ + SET_BIT(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_SR); + + /* Clear Tx and Rx process stopped flags */ + SET_BIT(ETHx->DMACH0STS, (ETH_DMACH0STS_TPS | ETH_DMACH0STS_RPS)); + + /* Save IT mode */ + pInfo->RxDescList.ItMode = 1U; +} + +/** +*\*\name ETH_Stop. +*\*\fun Turn off ETH in polling mode, including turning off TX and RX DMA engines, +*\*\ turning off TX and RX MAC controllers, etc. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none. +**/ +void ETH_Stop(ETH_Module* ETHx) +{ + /* Stop the DMA Transmitter */ + CLEAR_BIT(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_ST); + + /* Wait for any previous frame transmissions to complete */ + while (((ETHx->MTLTXQDBG & ETH_TRCSTS_MASK) == ETH_MTLTXQSTS_READ) + && ((ETHx->MTLTXQDBG & ETH_MTLTXQSTS_NOT_EMPTY) == ETH_MTLTXQSTS_NOT_EMPTY)) + { + } + + /* Stop the MAC Transmitter */ + CLEAR_BIT(ETHx->MACCFG, ETH_MACCFG_TE); + + /* Stop the MAC Receiver */ + CLEAR_BIT(ETHx->MACCFG, ETH_MACCFG_RE); + + /* Wait for all data to be transferred to system memory */ + while (((ETHx->MTLRXQDBG & ETH_RXQSTS_MASK) != ETH_MTLRXQSTS_EMPTY) + && ((ETHx->MTLRXQDBG & ETH_MTLRXQSTS_PACK_NBR) != (uint32_t)RESET)) + { + } + + /* Stop the DMA Receiver */ + CLEAR_BIT(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_SR); + + /* Set the Flush Transmit Queue bit */ + SET_BIT(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_FTQ); +} + +/** +*\*\name ETH_StopIT. +*\*\fun Turn off ETH in interrupt mode, including turning off TX and RX DMA engines, +*\*\ turning off TX and RX MAC controllers, etc. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param pInfo : +*\*\ - Pointer to an ETH_InfoType structure parameter containing various +*\*\ information about the operation of the ETH module. +*\*\return none. +**/ +void ETH_StopIT(ETH_Module* ETHx, ETH_InfoType* pInfo) +{ + uint32_t TempIndex, DescIndex = 0; + ETH_DMADescType* pRxDescriptor = NULL; + + /* Get the descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pInfo->RxDescList.RxDesc[DescIndex]; + + /* Disable ETH DMA Transmit Interrupt, Receive Interrupt, Fatal Bus Error Interrupt, + Abnormal Interrupt Summary, Normal Interrupt Summary*/ + CLEAR_BIT(ETHx->DMACH0INTEN, (ETH_DMACH0INTEN_TIE | ETH_DMACH0INTEN_RIE + | ETH_DMACH0INTEN_NIE | ETH_DMACH0INTEN_AIE + | ETH_DMACH0INTEN_FBEE)); + + /* Stop the DMA Transmitter */ + CLEAR_BIT(ETHx->DMACH0TXCTRL, ETH_DMACH0TXCTRL_ST); + + /* Wait for any previous frame transmissions to complete */ + while (((ETHx->MTLTXQDBG & ETH_TRCSTS_MASK) == ETH_MTLTXQSTS_READ) + && ((ETHx->MTLTXQDBG & ETH_MTLTXQSTS_NOT_EMPTY) == ETH_MTLTXQSTS_NOT_EMPTY)) + { + } + + /* Stop the MAC Transmitter */ + CLEAR_BIT(ETHx->MACCFG, ETH_MACCFG_TE); + + /* Stop the MAC Receiver */ + CLEAR_BIT(ETHx->MACCFG, ETH_MACCFG_RE); + + /* Wait for all data to be transferred to system memory */ + while (((ETHx->MTLRXQDBG & ETH_RXQSTS_MASK) != ETH_MTLRXQSTS_EMPTY) + && ((ETHx->MTLRXQDBG & ETH_MTLRXQSTS_PACK_NBR) != (uint32_t)RESET)) + { + } + + /* Stop the DMA Receiver */ + CLEAR_BIT(ETHx->DMACH0RXCTRL, ETH_DMACH0RXCTRL_SR); + + /* Set the Flush Transmit Queue bit */ + SET_BIT(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_FTQ); + + /* Clear IOC bit to all Rx descriptors */ + for (TempIndex = 0; TempIndex < ETH_RX_DESC_NUMBER; TempIndex++) + { + /* Clear Interrupt on Completion bit */ + CLEAR_BIT(pRxDescriptor->DESC3, ETH_DMARXND3RF_IOC); + /* Increment rx descriptor index */ + __ETH_RXDESC_INDEX_INCR(DescIndex, 1U); + /* Get the descriptor address */ + pRxDescriptor = (ETH_DMADescType*)pInfo->RxDescList.RxDesc[DescIndex]; + } + + /* Clear IT mode to */ + pInfo->RxDescList.ItMode = 0U; +} + + + +/** +*\*\name ETH_GetTxDescFlagStatus. +*\*\fun Checks whether the specified ETH DMA Tx Descriptor status flag +*\*\ bits is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_DMATXDESC_FLAG_IHE +*\*\ - ETH_DMATXDESC_FLAG_DB +*\*\ - ETH_DMATXDESC_FLAG_UF +*\*\ - ETH_DMATXDESC_FLAG_ED +*\*\ - ETH_DMATXDESC_FLAG_CC +*\*\ - ETH_DMATXDESC_FLAG_EC +*\*\ - ETH_DMATXDESC_FLAG_LC +*\*\ - ETH_DMATXDESC_FLAG_NC +*\*\ - ETH_DMATXDESC_FLAG_LOC +*\*\ - ETH_DMATXDESC_FLAG_PCE +*\*\ - ETH_DMATXDESC_FLAG_PF +*\*\ - ETH_DMATXDESC_FLAG_JT +*\*\ - ETH_DMATXDESC_FLAG_ES +*\*\ - ETH_DMATXDESC_FLAG_TTSS +*\*\ - ETH_DMATXDESC_FLAG_DE +*\*\ - ETH_DMATXDESC_FLAG_LD +*\*\ - ETH_DMATXDESC_FLAG_FD +*\*\return SET or RESET +**/ +FlagStatus ETH_GetTxDescFlagStatus(ETH_DMADescType* pTxDescriptor, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(pTxDescriptor->DESC3, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetRxDescExtendedFlagStatus. +*\*\fun Checks whether the specified ETH DMA Rx Descriptor Extended status +*\*\ flag bits is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_DMARXDESC_EXTFLAG_PT_NONE +*\*\ - ETH_DMARXDESC_EXTFLAG_PT_NUDP +*\*\ - ETH_DMARXDESC_EXTFLAG_PT_TCP +*\*\ - ETH_DMARXDESC_EXTFLAG_PT_ICNP +*\*\ - ETH_DMARXDESC_EXTFLAG_IPHE +*\*\ - ETH_DMARXDESC_EXTFLAG_IPV4 +*\*\ - ETH_DMARXDESC_EXTFLAG_IPV6 +*\*\ - ETH_DMARXDESC_EXTFLAG_IPCB +*\*\ - ETH_DMARXDESC_EXTFLAG_IPCE +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_NONE +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_SYNC +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_FU +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_DREQ +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_DRESP +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_PDREQ +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_PDRESP +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_PRFU +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_ANN +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_MAN +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_SIG +*\*\ - ETH_DMARXDESC_EXTFLAG_PMT_PRT +*\*\ - ETH_DMARXDESC_EXTFLAG_PFT +*\*\ - ETH_DMARXDESC_EXTFLAG_PV +*\*\ - ETH_DMARXDESC_EXTFLAG_TSA +*\*\ - ETH_DMARXDESC_EXTFLAG_TD +*\*\return SET or RESET +**/ +FlagStatus ETH_GetRxDescExtendedFlagStatus(ETH_DMADescType* pRxDescriptor, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(pRxDescriptor->DESC1, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetRxDescFilterFlagStatus. +*\*\fun Checks whether the specified ETH DMA Rx Descriptor Filter status flag +*\*\ bits is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_DMARXDESC_FLTFLAG_VFS +*\*\ - ETH_DMARXDESC_FLTFLAG_SAF +*\*\ - ETH_DMARXDESC_FLTFLAG_DAF +*\*\ - ETH_DMARXDESC_FLTFLAG_HF +*\*\return SET or RESET +**/ +FlagStatus ETH_GetRxDescFilterFlagStatus(ETH_DMADescType* pRxDescriptor, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(pRxDescriptor->DESC2, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetRxDescFlagStatus. +*\*\fun Checks whether the specified ETH DMA Rx Descriptor status flag bits +*\*\ is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_DMARXDESC_FLAG_ES +*\*\ - ETH_DMARXDESC_FLAG_LT_LP +*\*\ - ETH_DMARXDESC_FLAG_LT_TP +*\*\ - ETH_DMARXDESC_FLAG_LT_ARP +*\*\ - ETH_DMARXDESC_FLAG_LT_VLAN +*\*\ - ETH_DMARXDESC_FLAG_LT_DVLAN +*\*\ - ETH_DMARXDESC_FLAG_LT_MAC +*\*\ - ETH_DMARXDESC_FLAG_LT_OAM +*\*\ - ETH_DMARXDESC_FLAG_DE +*\*\ - ETH_DMARXDESC_FLAG_RE +*\*\ - ETH_DMARXDESC_FLAG_OE +*\*\ - ETH_DMARXDESC_FLAG_RWT +*\*\ - ETH_DMARXDESC_FLAG_GP +*\*\ - ETH_DMARXDESC_FLAG_CE +*\*\ - ETH_DMARXDESC_FLAG_RS0V +*\*\ - ETH_DMARXDESC_FLAG_RS1V +*\*\ - ETH_DMARXDESC_FLAG_RS2V +*\*\ - ETH_DMARXDESC_FLAG_LD +*\*\ - ETH_DMARXDESC_FLAG_FD +*\*\return SET or RESET +**/ +FlagStatus ETH_GetRxDescFlagStatus(ETH_DMADescType* pRxDescriptor, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(pRxDescriptor->DESC3, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetFlowControlBusyStatus. +*\*\fun Checks whether the ETH flow control busy bit is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return SET or RESET +*\*\note The Flow Control register should not be written to until this bit +*\*\ is cleared. +**/ +FlagStatus ETH_GetFlowControlBusyStatus(ETH_Module* ETHx) +{ + FlagStatus TempStatus; + + /* Read the status of the FCB bit */ + if(READ_BIT(ETHx->MACTXFLWCTRL, ETH_MACTXFLWCTRL_FCB) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMACInterruptStatus. +*\*\fun Checks whether the specified ETH MAC Interrupt flag is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MAC_INT_FLAG_PHY +*\*\ - ETH_MAC_INT_FLAG_PMT +*\*\ - ETH_MAC_INT_FLAG_MMCRX +*\*\ - ETH_MAC_INT_FLAG_MMCTX +*\*\ - ETH_MAC_INT_FLAG_TS +*\*\ - ETH_MAC_INT_FLAG_TX +*\*\ - ETH_MAC_INT_FLAG_RX +*\*\ - ETH_MAC_INT_FLAG_MDIO +*\*\return SET or RESET +**/ +INTStatus ETH_GetMACInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->MACINTSTS, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMACTxRxFlagStatus. +*\*\fun Checks whether the specified ETH MAC transmit-receive status +*\*\ flag bits is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_MACTX_FLAG_TJT +*\*\ - ETH_MACTX_FLAG_NCARR +*\*\ - ETH_MACTX_FLAG_LCARR +*\*\ - ETH_MACTX_FLAG_EXDEF +*\*\ - ETH_MACTX_FLAG_LCOL +*\*\ - ETH_MACTX_FLAG_EXCOL +*\*\ - ETH_MACRX_FLAG_RWT +*\*\return SET or RESET +**/ +FlagStatus ETH_GetMACTxRxFlagStatus(ETH_Module* ETHx, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(ETHx->MACRXTXSTS, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetPMTFlagStatus. +*\*\fun Checks whether the specified ETH PMT status flag bits is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_PMT_FLAG_WUPFRPR +*\*\ - ETH_PMT_FLAG_WUPR +*\*\ - ETH_PMT_FLAG_MPR +*\*\return SET or RESET +**/ +FlagStatus ETH_GetPMTFlagStatus(ETH_Module* ETHx, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(ETHx->MACPMTCTRLSTS, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMMCRxInterruptStatus. +*\*\fun Checks whether the specified ETH MMC RX Interrupt flag is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MMCRX_INT_FLAG_BCGPIS +*\*\ - ETH_MMCRX_INT_FLAG_MCGPIS +*\*\ - ETH_MMCRX_INT_FLAG_CRCERPIS +*\*\ - ETH_MMCRX_INT_FLAG_ALGNERPIS +*\*\ - ETH_MMCRX_INT_FLAG_UCGPIS +*\*\return SET or RESET +**/ +INTStatus ETH_GetMMCRxInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->MMCRXINT, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMMCTxInterruptStatus. +*\*\fun Checks whether the specified ETH MMC TX Interrupt flag is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MMCTX_INT_FLAG_SCOLGPIS +*\*\ - ETH_MMCTX_INT_FLAG_MCOLGPIS +*\*\ - ETH_MMCTX_INT_FLAG_GPKTIS +*\*\return SET or RESET +**/ +INTStatus ETH_GetMMCTxInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->MMCTXINT, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMACTimeStampFlagStatus. +*\*\fun Checks whether the specified ETH MAC Time Stamp flag is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_MACTS_FLAG_SOVF +*\*\ - ETH_MACTS_FLAG_TARGT0 +*\*\ - ETH_MACTS_FLAG_TRGTERR0 +*\*\ - ETH_MACTS_FLAG_TXTSSIS +*\*\return SET or RESET +**/ +FlagStatus ETH_GetMACTimeStampFlagStatus(ETH_Module* ETHx, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(ETHx->MACTSSTS, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetFlushTransmitQueueStatus. +*\*\fun Checks whether the ETH Flush Transmit Queue bit is cleared or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return SET or RESET +*\*\note The MTL Transmit Queue Operation Mode Register (ETH_MTLTXQOPMOD) +*\*\ should not be written until the Flush Transmit Queue bit is reset. +**/ +FlagStatus ETH_GetFlushTransmitQueueStatus(ETH_Module* ETHx) +{ + FlagStatus TempStatus; + + /* Read the status of the Flush Transmit Queue */ + if(READ_BIT(ETHx->MTLTXQOPMOD, ETH_MTLTXQOPMOD_FTQ) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMTLInterruptStatus. +*\*\fun Checks whether the specified ETH MTL Interrupt flag is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MTL_INT_FLAG_Q0IS +*\*\return SET or RESET +**/ +INTStatus ETH_GetMTLInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->MTLINTSTS, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMTLQueueInterruptStatus. +*\*\fun Checks whether the specified ETH MTL queue Interrupt flag is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MTLTXQUEUE_INT_FLAG_UNFIS +*\*\ - ETH_MTLRXQUEUE_INT_FLAG_OVFIS +*\*\return SET or RESET +**/ +INTStatus ETH_GetMTLQueueInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->MTLQINTCTRLSTS, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetMTLCounterFlagStatus. +*\*\fun Checks whether the specified ETH MTL Counter flag is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_MTLCOUNTER_FLAG_UFCNTOVF +*\*\ - ETH_MTLCOUNTER_FLAG_OVFCNTOVF +*\*\ - ETH_MTLCOUNTER_FLAG_MISCNTOVF +*\*\return SET or RESET +**/ +FlagStatus ETH_GetMTLCounterFlagStatus(ETH_Module* ETHx, uint32_t Flag) +{ + FlagStatus TempStatus; + + if (Flag == ETH_MTLCOUNTER_FLAG_UFCNTOVF) + { + /* Read the status of the corresponding flag bits */ + if(READ_BIT(ETHx->MTLTXQUDF, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + } + else + { + /* Read the status of the corresponding flag bits */ + if(READ_BIT(ETHx->MTLRXQMPOFCNT, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetSoftwareResetStatus. +*\*\fun Checks whether the ETH software reset bit (SWR) is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return SET or RESET +*\*\note 1. Before reprogramming any ETH register, a value of zero should be +*\*\ read in SWR bit. +*\*\ 2. The SWR bit must be read at least 4 CSR clock cycles after it is +*\*\ written to 1. +**/ +FlagStatus ETH_GetSoftwareResetStatus(ETH_Module* ETHx) +{ + FlagStatus TempStatus; + + /* Read the status of the ETH software reset */ + if(READ_BIT(ETHx->DMAMODE, ETH_DMAMODE_SWR) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetDMAInterruptStatus. +*\*\fun Checks whether the specified ETH DMA Interrupt flag is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_DMA_INT_FLAG_DMACH0 +*\*\ - ETH_DMA_INT_FLAG_MTL +*\*\ - ETH_DMA_INT_FLAG_MAC +*\*\return SET or RESET +**/ +INTStatus ETH_GetDMAInterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->DMAINTSTS, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetDMACh0TxProcessStatus. +*\*\fun Returns the ETH DMA Transmit Process Status. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return One of the following values: +*\*\ - ETH_DMACH0_TXPRO_FLAG_STOP +*\*\ - ETH_DMACH0_TXPRO_FLAG_RUN_FTTD +*\*\ - ETH_DMACH0_TXPRO_FLAG_RUN_WS +*\*\ - ETH_DMACH0_TXPRO_FLAG_RUN_RDS +*\*\ - ETH_DMACH0_TXPRO_FLAG_TSTMP_WS +*\*\ - ETH_DMACH0_TXPRO_FLAG_SUSPND +*\*\ - ETH_DMACH0_TXPRO_FLAG_RUN_CTD +**/ +uint32_t ETH_GetDMACh0TxProcessStatus(ETH_Module* ETHx) +{ + /* Return The new ETH DMA Transmit Process Status */ + return (READ_BIT(ETHx->DMADBGSTS, ETH_DMADBGSTS_TPS0)); +} + +/** +*\*\name ETH_GetDMACh0RxProcessStatus. +*\*\fun Returns the ETH DMA Receive Process Status. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return One of the following values: +*\*\ - ETH_DMACH0_RXPRO_FLAG_STOP +*\*\ - ETH_DMACH0_RXPRO_FLAG_RUN_FTTD +*\*\ - ETH_DMACH0_RXPRO_FLAG_RUN_WRP +*\*\ - ETH_DMACH0_RXPRO_FLAG_SUSPND +*\*\ - ETH_DMACH0_RXPRO_FLAG_RUN_CRD +*\*\ - ETH_DMACH0_RXPRO_FLAG_TSTMP +*\*\ - ETH_DMACH0_RXPRO_FLAG_RUN_TRP +**/ +uint32_t ETH_GetDMACh0RxProcessStatus(ETH_Module* ETHx) +{ + /* Return The new ETH DMA Receive Process Status */ + return (READ_BIT(ETHx->DMADBGSTS, ETH_DMADBGSTS_RPS0)); +} + +/** +*\*\name ETH_GetDMACh0FlagStatus. +*\*\fun Checks whether the specified ETH DMA-CH0 flag is set or not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_DMACH0_FLAG_TI +*\*\ - ETH_DMACH0_FLAG_TPS +*\*\ - ETH_DMACH0_FLAG_TBU +*\*\ - ETH_DMACH0_FLAG_RI +*\*\ - ETH_DMACH0_FLAG_RBU +*\*\ - ETH_DMACH0_FLAG_RPS +*\*\ - ETH_DMACH0_FLAG_RWT +*\*\ - ETH_DMACH0_FLAG_ETI +*\*\ - ETH_DMACH0_FLAG_ERI +*\*\ - ETH_DMACH0_FLAG_FBE +*\*\ - ETH_DMACH0_FLAG_CDE +*\*\ - ETH_DMACH0_FLAG_AIS +*\*\ - ETH_DMACH0_FLAG_NIS +*\*\return SET or RESET +**/ +FlagStatus ETH_GetDMACh0FlagStatus(ETH_Module* ETHx, uint32_t Flag) +{ + FlagStatus TempStatus; + + /* Read the status of the corresponding flag bits */ + if(READ_BIT(ETHx->DMACH0STS, Flag) != (uint32_t)RESET) + { + /* This flag is SET */ + TempStatus = SET; + } + else + { + /* This flag is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + +/** +*\*\name ETH_GetDMACh0InterruptStatus. +*\*\fun Checks whether the specified ETH DMA-CH0 Interrupt flag is set or +*\*\ not. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_DMACH0_INT_FLAG_TI +*\*\ - ETH_DMACH0_INT_FLAG_TPS +*\*\ - ETH_DMACH0_INT_FLAG_TBU +*\*\ - ETH_DMACH0_INT_FLAG_RI +*\*\ - ETH_DMACH0_INT_FLAG_RBU +*\*\ - ETH_DMACH0_INT_FLAG_RPS +*\*\ - ETH_DMACH0_INT_FLAG_RWT +*\*\ - ETH_DMACH0_INT_FLAG_ETI +*\*\ - ETH_DMACH0_INT_FLAG_ERI +*\*\ - ETH_DMACH0_INT_FLAG_FBE +*\*\ - ETH_DMACH0_INT_FLAG_CDE +*\*\ - ETH_DMACH0_INT_FLAG_AIS +*\*\ - ETH_DMACH0_INT_FLAG_NIS +*\*\return SET or RESET +**/ +INTStatus ETH_GetDMACh0InterruptStatus(ETH_Module* ETHx, uint32_t IntFlag) +{ + INTStatus TempStatus; + + /* Read the status of the corresponding INT bits */ + if(READ_BIT(ETHx->DMACH0STS, IntFlag) != (uint32_t)RESET) + { + /* This Interrupt is SET */ + TempStatus = SET; + } + else + { + /* This Interrupt is RESET */ + TempStatus = RESET; + } + + /* Return status */ + return TempStatus; +} + + + +/** +*\*\name ETH_ClearMACPHYInterruptFlag. +*\*\fun Clears the MAC PHY Interrupt pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_ClearMACPHYInterruptFlag(ETH_Module* ETHx) +{ + /* Check whether register write 1 clear is enabled or not */ + if (READ_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE) != (uint32_t)RESET) + { + /* Clear the ETH PHY Interrupt flag by write 1 */ + SET_BIT(ETHx->MACINTSTS, ETH_MACINTSTS_PHYIS); + } + else + { + /* Clear the ETH PHY Interrupt flag by read */ + READ_BIT(ETHx->MACINTSTS, ETH_MACINTSTS_PHYIS); + } +} + +/** +*\*\name ETH_ClearPMTFlag. +*\*\fun Clears the MAC PMT pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_PMT_FLAG_WUPR +*\*\ - ETH_PMT_FLAG_MPR +*\*\return none +**/ +void ETH_ClearPMTFlag(ETH_Module* ETHx, uint32_t Flag) +{ + /* Check whether register write 1 clear is enabled or not */ + if (READ_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE) != (uint32_t)RESET) + { + if (Flag == ETH_PMT_FLAG_WUPR) + { + /* Clear the ETH PMT flag by write 1 */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_PMT_FLAG_WUPR); + } + else + { + /* Clear the ETH PMT flag by write 1 */ + SET_BIT(ETHx->MACPMTCTRLSTS, ETH_PMT_FLAG_MPR); + } + } + else + { + /* Clear the ETH PMT flag by read */ + READ_REG(ETHx->MACPMTCTRLSTS); + } +} + +/** +*\*\name ETH_ClearMMCRxInterruptFlag. +*\*\fun Clears the MMC RX Interrupt pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MMCRX_INT_FLAG_BCGPIS +*\*\ - ETH_MMCRX_INT_FLAG_MCGPIS +*\*\ - ETH_MMCRX_INT_FLAG_CRCERPIS +*\*\ - ETH_MMCRX_INT_FLAG_ALGNERPIS +*\*\ - ETH_MMCRX_INT_FLAG_UCGPIS +*\*\return none +**/ +void ETH_ClearMMCRxInterruptFlag(ETH_Module* ETHx, uint32_t IntFlag) +{ + /* Clear the ETH MMC RX Interrupt flag by read */ + READ_BIT(ETHx->MMCRXINT, IntFlag); +} + +/** +*\*\name ETH_ClearMMCTxInterruptFlag. +*\*\fun Clears the MMC TX Interrupt pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MMCTX_INT_FLAG_SCOLGPIS +*\*\ - ETH_MMCTX_INT_FLAG_MCOLGPIS +*\*\ - ETH_MMCTX_INT_FLAG_GPKTIS +*\*\return none +**/ +void ETH_ClearMMCTxInterruptFlag(ETH_Module* ETHx, uint32_t IntFlag) +{ + /* Clear the ETH MMC TX Interrupt flag by read */ + READ_BIT(ETHx->MMCTXINT, IntFlag); +} + +/** +*\*\name ETH_ClearMACTimeStampFlag. +*\*\fun Clears the MAC Time Stamp pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_MACTS_FLAG_SOVF +*\*\ - ETH_MACTS_FLAG_TARGT0 +*\*\ - ETH_MACTS_FLAG_TRGTERR0 +*\*\ - ETH_MACTS_FLAG_TXTSSIS +*\*\return none +**/ +void ETH_ClearMACTimeStampFlag(ETH_Module* ETHx, uint32_t Flag) +{ + /* Check whether register write 1 clear is enabled or not */ + if (READ_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE) != (uint32_t)RESET) + { + if (Flag == ETH_MACTS_FLAG_TXTSSIS) + { + /* Clear the MAC Time Stamp flag by write register */ + WRITE_REG(ETHx->MACTXTSSTSS, 1U); + } + else + { + /* Clear the MAC Time Stamp flag by write 1 */ + SET_BIT(ETHx->MACTSSTS, Flag); + } + } + else + { + if (Flag == ETH_MACTS_FLAG_TXTSSIS) + { + /* Clear the MAC Time Stamp flag by read register */ + READ_REG(ETHx->MACTXTSSTSS); + } + else + { + /* Clear the MAC Time Stamp flag by read */ + READ_BIT(ETHx->MACTSSTS, Flag); + } + } +} + +/** +*\*\name ETH_ClearMACTxRxFlag. +*\*\fun Clears the MAC TX RX pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_MACTX_FLAG_TJT +*\*\ - ETH_MACTX_FLAG_NCARR +*\*\ - ETH_MACTX_FLAG_LCARR +*\*\ - ETH_MACTX_FLAG_EXDEF +*\*\ - ETH_MACTX_FLAG_LCOL +*\*\ - ETH_MACTX_FLAG_EXCOL +*\*\ - ETH_MACRX_FLAG_RWT +*\*\return none +**/ +void ETH_ClearMACTxRxFlag(ETH_Module* ETHx, uint32_t Flag) +{ + /* Check whether register write 1 clear is enabled or not */ + if (READ_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE) != (uint32_t)RESET) + { + /* Clear the ETH MAC TX RX Interrupt flag by write 1 */ + SET_BIT(ETHx->MACRXTXSTS, Flag); + } + else + { + /* Clear the ETH MAC TX RX Interrupt flag by read */ + READ_BIT(ETHx->MACRXTXSTS, Flag); + } +} + +/** +*\*\name ETH_ClearMACMDIOInterruptFlag. +*\*\fun Clears the MAC MDIO Interrupt pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\return none +**/ +void ETH_ClearMACMDIOInterruptFlag(ETH_Module* ETHx) +{ + /* Check whether register write 1 clear is enabled or not */ + if (READ_BIT(ETHx->MACCSRSWCTRL, ETH_MACCSRSWCTRL_RCWE) != (uint32_t)RESET) + { + /* Clear the ETH MDIO Interrupt flag by write 1 */ + SET_BIT(ETHx->MACINTSTS, ETH_MACINTSTS_MDIOIS); + } + else + { + /* Clear the ETH MDIO Interrupt flag by read */ + READ_BIT(ETHx->MACINTSTS, ETH_MACINTSTS_MDIOIS); + } +} + +/** +*\*\name ETH_ClearMTLQueueInterruptFlag. +*\*\fun Clears the MTL Queue Interrupt pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_MTLTXQUEUE_INT_FLAG_UNFIS +*\*\ - ETH_MTLRXQUEUE_INT_FLAG_OVFIS +*\*\return none +**/ +void ETH_ClearMTLQueueInterruptFlag(ETH_Module* ETHx, uint32_t IntFlag) +{ + /* Clear the selected ETH MTL Queue Interrupt flag */ + SET_BIT(ETHx->MTLQINTCTRLSTS, IntFlag); +} + +/** +*\*\name ETH_ClearDMACh0Flag. +*\*\fun Clears the DMA Channel 0 pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Flag (The input parameters must be the following values): +*\*\ - ETH_DMACH0_FLAG_TI +*\*\ - ETH_DMACH0_FLAG_TPS +*\*\ - ETH_DMACH0_FLAG_TBU +*\*\ - ETH_DMACH0_FLAG_RI +*\*\ - ETH_DMACH0_FLAG_RBU +*\*\ - ETH_DMACH0_FLAG_RPS +*\*\ - ETH_DMACH0_FLAG_RWT +*\*\ - ETH_DMACH0_FLAG_ETI +*\*\ - ETH_DMACH0_FLAG_ERI +*\*\ - ETH_DMACH0_FLAG_FBE +*\*\ - ETH_DMACH0_FLAG_CDE +*\*\ - ETH_DMACH0_FLAG_AIS +*\*\ - ETH_DMACH0_FLAG_NIS +*\*\return none +**/ +void ETH_ClearDMACh0Flag(ETH_Module* ETHx, uint32_t Flag) +{ + /* Clear the selected ETH DMA Channel 0 flag */ + SET_BIT(ETHx->DMACH0STS, Flag); +} + +/** +*\*\name ETH_ClearDMACh0InterruptFlag. +*\*\fun Clears the DMA Channel 0 Interrupt pending flag for the ETH. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - ETH_DMACH0_INT_FLAG_TI +*\*\ - ETH_DMACH0_INT_FLAG_TPS +*\*\ - ETH_DMACH0_INT_FLAG_TBU +*\*\ - ETH_DMACH0_INT_FLAG_RI +*\*\ - ETH_DMACH0_INT_FLAG_RBU +*\*\ - ETH_DMACH0_INT_FLAG_RPS +*\*\ - ETH_DMACH0_INT_FLAG_RWT +*\*\ - ETH_DMACH0_INT_FLAG_ETI +*\*\ - ETH_DMACH0_INT_FLAG_ERI +*\*\ - ETH_DMACH0_INT_FLAG_FBE +*\*\ - ETH_DMACH0_INT_FLAG_CDE +*\*\ - ETH_DMACH0_INT_FLAG_AIS +*\*\ - ETH_DMACH0_INT_FLAG_NIS +*\*\return none +**/ +void ETH_ClearDMACh0InterruptFlag(ETH_Module* ETHx, uint32_t IntFlag) +{ + /* Clear the selected ETH DMA Channel 0 Interrupt flag */ + SET_BIT(ETHx->DMACH0STS, IntFlag); +} + + + +/** +*\*\name ETH_ConfigMACInterrupt. +*\*\fun Enables or disables the specified ETH MAC interrupts. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - ETH_MAC_INT_PHY +*\*\ - ETH_MAC_INT_PMT +*\*\ - ETH_MAC_INT_TS +*\*\ - ETH_MAC_INT_TX +*\*\ - ETH_MAC_INT_RX +*\*\ - ETH_MAC_INT_MDIO +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_ConfigMACInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ETH MAC interrupts */ + SET_BIT(ETHx->MACINTEN, Interrupt); + } + else + { + /* Disable the selected ETH MAC interrupts */ + CLEAR_BIT(ETHx->MACINTEN, Interrupt); + } +} + +/** +*\*\name ETH_ConfigMMCRxInterrupt. +*\*\fun Enables or disables the specified ETH MMC RX interrupts. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - ETH_MMCRX_INT_BCGPIM +*\*\ - ETH_MMCRX_INT_MCGPIM +*\*\ - ETH_MMCRX_INT_CRCERPIM +*\*\ - ETH_MMCRX_INT_ALGNERPIM +*\*\ - ETH_MMCRX_INT_UCGPIM +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_ConfigMMCRxInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ETH MMC RX interrupts */ + CLEAR_BIT(ETHx->MMCRXINTMSK, Interrupt); + } + else + { + /* Disable the selected ETH MMC RX interrupts */ + SET_BIT(ETHx->MMCRXINTMSK, Interrupt); + } +} + +/** +*\*\name ETH_ConfigMMCTxInterrupt. +*\*\fun Enables or disables the specified ETH MMC TX interrupts. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - ETH_MMCTX_INT_SCOLGPIM +*\*\ - ETH_MMCTX_INT_MCOLGPIM +*\*\ - ETH_MMCTX_INT_GPKTIM +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_ConfigMMCTxInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ETH MMC TX interrupts */ + CLEAR_BIT(ETHx->MMCTXINTMSK, Interrupt); + } + else + { + /* Disable the selected ETH MMC TX interrupts */ + SET_BIT(ETHx->MMCTXINTMSK, Interrupt); + } +} + +/** +*\*\name ETH_ConfigMTLQueueInterrupt. +*\*\fun Enables or disables the specified ETH MTL Queue interrupts. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - ETH_MTLTXQUEUE_INT_UIE +*\*\ - ETH_MTLRXQUEUE_INT_OIE +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_ConfigMTLQueueInterrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ETH MTL Queue interrupts */ + SET_BIT(ETHx->MTLQINTCTRLSTS, Interrupt); + } + else + { + /* Disable the selected ETH MTL Queue interrupts */ + CLEAR_BIT(ETHx->MTLQINTCTRLSTS, Interrupt); + } +} + +/** +*\*\name ETH_ConfigDMACh0Interrupt. +*\*\fun Enables or disables the specified ETH DMA Channel 0 interrupts. +*\*\param ETHx (The input parameters must be the following values): +*\*\ - ETH1 +*\*\ - ETH2 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - ETH_DMACH0_INT_TI +*\*\ - ETH_DMACH0_INT_TPS +*\*\ - ETH_DMACH0_INT_TBU +*\*\ - ETH_DMACH0_INT_RI +*\*\ - ETH_DMACH0_INT_RBU +*\*\ - ETH_DMACH0_INT_RPS +*\*\ - ETH_DMACH0_INT_RWT +*\*\ - ETH_DMACH0_INT_ETI +*\*\ - ETH_DMACH0_INT_ERI +*\*\ - ETH_DMACH0_INT_FBE +*\*\ - ETH_DMACH0_INT_CDE +*\*\ - ETH_DMACH0_INT_AIS +*\*\ - ETH_DMACH0_INT_NIS +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void ETH_ConfigDMACh0Interrupt(ETH_Module* ETHx, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected ETH DMA Channel 0 interrupts */ + SET_BIT(ETHx->DMACH0INTEN, Interrupt); + } + else + { + /* Disable the selected ETH DMA Channel 0 interrupts */ + CLEAR_BIT(ETHx->DMACH0INTEN, Interrupt); + } +} + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_exti.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_exti.c new file mode 100644 index 0000000000..838895faa5 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_exti.c @@ -0,0 +1,702 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_exti.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_exti.h" +#include "misc.h" + +/** +*\*\name EXTI_DeInit. +*\*\fun Reset the EXTI registers. +*\*\param Core_Type (The input parameters must be the following values): +*\*\ - CORE_M7 +*\*\ - CORE_M4 +*\*\return none +**/ +void EXTI_DeInit(void) +{ + EXTI->RT_CFG[0] = 0x00000000; + EXTI->RT_CFG[1] = 0x00000000; + EXTI->FT_CFG[0] = 0x00000000; + EXTI->FT_CFG[1] = 0x00000000; + EXTI->TSSEL = 0x00000000; + + if(Get_CurrentCPU() != CM7_CPU) + { + EXTI->M4IMASK[0] = 0x00000000; + EXTI->M4IMASK[1] = 0x00000000; + + EXTI->M7EMASK[0] = 0x00000000; + EXTI->M7EMASK[1] = 0x00000000; + + EXTI->M4PEND[0] = 0xFFFFFFFF; + EXTI->M4PEND[1] = 0x0000FFFF; + + EXTI->M4IMASK_DRC[0] = 0x00000000; + EXTI->M4IMASK_DRC[1] = 0x00000000; + + EXTI->M4EMASK_DRC[0] = 0x00000000; + EXTI->M4EMASK_DRC[1] = 0x00000000; + } + else + { + EXTI->M7IMASK[0] = 0x00000000; + EXTI->M7IMASK[1] = 0x00000000; + + EXTI->M7EMASK[0] = 0x00000000; + EXTI->M7EMASK[1] = 0x00000000; + + EXTI->M7PEND[0] = 0xFFFFFFFF; + EXTI->M7PEND[1] = 0x0000FFFF; + + EXTI->M7IMASK_DRC[0] = 0x00000000; + EXTI->M7IMASK_DRC[1] = 0x00000000; + + EXTI->M7EMASK_DRC[0] = 0x00000000; + EXTI->M7EMASK_DRC[1] = 0x00000000; + } +} + +/** +*\*\name EXTI_InitPeripheral. +*\*\fun Initializes the EXTI according to EXTI_InitStruct. +*\*\param EXTI_InitStruct(The input parameters must be the following values) : +*\*\param EXTI_Line +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\ - EXTI_LINE24 +*\*\ - EXTI_LINE25 +*\*\ - EXTI_LINE49 +*\*\ - EXTI_LINE51 +*\*\ - EXTI_LINE52 +*\*\ - EXTI_LINE54 +*\*\ - EXTI_LINE55 +*\*\ - EXTI_LINE56 +*\*\ - EXTI_LINE62 +*\*\ - EXTI_LINE63 +*\*\ - EXTI_LINE64 +*\*\ - EXTI_LINE65 +*\*\ - EXTI_LINE66 +*\*\ - EXTI_LINE67 +*\*\ - EXTI_LINE68 +*\*\ - EXTI_LINE69 +*\*\ - EXTI_LINE70 +*\*\ - EXTI_LINE71 +*\*\ - EXTI_LINE72 +*\*\ - EXTI_LINE73 +*\*\ - EXTI_LINE74 +*\*\ - EXTI_LINE75 +*\*\ - EXTI_LINE76 +*\*\ - EXTI_LINE77 +*\*\ - EXTI_LINE78 +*\*\ - EXTI_LINE79 +*\*\ - EXTI_LINE80 +*\*\ - EXTI_LINE81 +*\*\ - EXTI_LINE82 +*\*\ - EXTI_LINE83 +*\*\ - EXTI_LINE84 +*\*\ - EXTI_LINE85 +*\*\ - EXTI_LINE86 +*\*\ - EXTI_LINE87 +*\*\ - EXTI_LINE88 +*\*\ - EXTI_LINE89 +*\*\ - EXTI_Mode +*\*\ - EXTI_Mode_Interrupt +*\*\ - EXTI_Mode_Event +*\*\ - EXTI_Trigger +*\*\ - EXTI_Trigger_Falling +*\*\ - EXTI_Trigger_Rising +*\*\ - EXTI_Trigger_Rising_Falling +*\*\ - EXTI_LineCmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct) +{ + uint32_t tmpregister; + uint32_t temp; + uint32_t exti_index; + uint32_t cpu_offset = 0; + uint8_t temp_index; + + if(Get_CurrentCPU() != CM7_CPU) + { + cpu_offset = 0x20; + } + + if(EXTI_InitStruct->EXTI_Line >= 100) + { + cpu_offset += 0xC0; + EXTI_InitStruct->EXTI_Line -= 100; + } + + temp_index = EXTI_InitStruct->EXTI_Line / 32; + exti_index = (uint32_t)0x00000001 << (EXTI_InitStruct->EXTI_Line % 32); + + tmpregister = (uint32_t)EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode + cpu_offset + 4 * temp_index; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line interrupt/event configuration */ + *(__IO uint32_t*)tmpregister &= ~exti_index; + + if(EXTI_InitStruct->EXTI_Mode == EXTI_Mode_Interrupt) + { + temp = tmpregister + 0x40; + } + else + { + temp = tmpregister - 0x40; + } + + /* Clear EXTI line interrupt/event configuration */ + *(__IO uint32_t*)temp &= ~exti_index; + + if(cpu_offset < 0xC0) + { + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RT_CFG[temp_index] |= exti_index; + EXTI->FT_CFG[temp_index] |= exti_index; + } + else + { + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG[temp_index] &= ~exti_index; + EXTI->FT_CFG[temp_index] &= ~exti_index; + + temp = (uint32_t)EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Trigger + 4 * temp_index; + + /* Clear EXTI line event/interrupt configuration */ + *(__IO uint32_t*)temp |= exti_index; + } + } + + /* Enable EXTI line event configuration */ + *(__IO uint32_t*)tmpregister |= exti_index; + } + else + { + /* Disable the selected external lines */ + *(__IO uint32_t*)tmpregister &= ~(exti_index); + } + +} + + +/** +*\*\name EXTI_InitStruct. +*\*\fun Fills each EXTI_InitStruct member with its default value. +*\*\param InitStruct : +*\*\ - - Pointer to the EXTI_InitType structure which will be initialized. +*\*\return none +**/ +void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct ) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINE0; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** +*\*\name EXTI_TriggerSWInt. +*\*\fun Generates a Software interrupt. +*\*\param EXTI_Line +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\ - EXTI_LINE49 +*\*\ - EXTI_LINE52 +*\*\ - EXTI_LINE62 +*\*\ - EXTI_LINE63 +*\*\ - EXTI_LINE64 +*\*\ - EXTI_LINE65 +*\*\ - EXTI_LINE66 +*\*\ - EXTI_LINE67 +*\*\ - EXTI_LINE68 +*\*\ - EXTI_LINE69 +*\*\ - EXTI_LINE70 +*\*\ - EXTI_LINE71 +*\*\ - EXTI_LINE72 +*\*\ - EXTI_LINE73 +*\*\ - EXTI_LINE74 +*\*\ - EXTI_LINE75 +*\*\ - EXTI_LINE81 +*\*\ - EXTI_LINE82 +*\*\ - EXTI_LINE86 +*\*\ - EXTI_LINE87 +*\*\ - EXTI_LINE88 +*\*\ - EXTI_LINE89 +*\*\return none +**/ +void EXTI_TriggerSWInt(uint32_t EXTI_Line) +{ + if(EXTI_Line < 100) + { + EXTI->SWIE[EXTI_Line / 32] |= (uint32_t)0x00000001 << (EXTI_Line % 32); + } +} + +/** +*\*\name EXTI_Flag_Status_Get. +*\*\fun Get EXTI line flag status. +*\*\param EXTI_Line +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\ - EXTI_LINE49 +*\*\ - EXTI_LINE52 +*\*\ - EXTI_LINE62 +*\*\ - EXTI_LINE63 +*\*\ - EXTI_LINE64 +*\*\ - EXTI_LINE65 +*\*\ - EXTI_LINE66 +*\*\ - EXTI_LINE67 +*\*\ - EXTI_LINE68 +*\*\ - EXTI_LINE69 +*\*\ - EXTI_LINE70 +*\*\ - EXTI_LINE71 +*\*\ - EXTI_LINE72 +*\*\ - EXTI_LINE73 +*\*\ - EXTI_LINE74 +*\*\ - EXTI_LINE75 +*\*\ - EXTI_LINE81 +*\*\ - EXTI_LINE82 +*\*\ - EXTI_LINE86 +*\*\ - EXTI_LINE87 +*\*\ - EXTI_LINE88 +*\*\ - EXTI_LINE89 +*\*\return SET or RESET +**/ +FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + uint32_t line_index; + + if(EXTI_Line < 100) + { + line_index = (uint32_t)0x00000001 << (EXTI_Line % 32); + + if (Get_CurrentCPU() != CM7_CPU) + { + if (( EXTI->M4PEND[EXTI_Line / 32] & line_index ) != ( uint32_t )RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + } + else + { + if (( EXTI->M7PEND[EXTI_Line / 32] & line_index ) != ( uint32_t )RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + } + } + + return bitstatus; +} + +/** +*\*\name EXTI_ClrStatusFlag. +*\*\fun Clear EXTI line flag status. +*\*\param EXTI_Line: +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\ - EXTI_LINE49 +*\*\ - EXTI_LINE52 +*\*\ - EXTI_LINE62 +*\*\ - EXTI_LINE63 +*\*\ - EXTI_LINE64 +*\*\ - EXTI_LINE65 +*\*\ - EXTI_LINE66 +*\*\ - EXTI_LINE67 +*\*\ - EXTI_LINE68 +*\*\ - EXTI_LINE69 +*\*\ - EXTI_LINE70 +*\*\ - EXTI_LINE71 +*\*\ - EXTI_LINE72 +*\*\ - EXTI_LINE73 +*\*\ - EXTI_LINE74 +*\*\ - EXTI_LINE75 +*\*\ - EXTI_LINE81 +*\*\ - EXTI_LINE82 +*\*\ - EXTI_LINE86 +*\*\ - EXTI_LINE87 +*\*\ - EXTI_LINE88 +*\*\ - EXTI_LINE89 +*\*\return none +**/ +void EXTI_ClrStatusFlag(uint32_t EXTI_Line) +{ + uint32_t line_index; + + if(EXTI_Line < 100) + { + line_index = (uint32_t)0x00000001 << (EXTI_Line % 32); + + if (Get_CurrentCPU() != CM7_CPU) + { + EXTI->M4PEND[EXTI_Line / 32] = line_index; + } + else + { + EXTI->M7PEND[EXTI_Line / 32] = line_index; + } + } +} + +/** +*\*\name EXTI_GetITStatus. +*\*\fun GET EXTI line interrupt status. +*\*\param EXTI_Line +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\ - EXTI_LINE49 +*\*\ - EXTI_LINE52 +*\*\ - EXTI_LINE62 +*\*\ - EXTI_LINE63 +*\*\ - EXTI_LINE64 +*\*\ - EXTI_LINE65 +*\*\ - EXTI_LINE66 +*\*\ - EXTI_LINE67 +*\*\ - EXTI_LINE68 +*\*\ - EXTI_LINE69 +*\*\ - EXTI_LINE70 +*\*\ - EXTI_LINE71 +*\*\ - EXTI_LINE72 +*\*\ - EXTI_LINE73 +*\*\ - EXTI_LINE74 +*\*\ - EXTI_LINE75 +*\*\ - EXTI_LINE81 +*\*\ - EXTI_LINE82 +*\*\ - EXTI_LINE86 +*\*\ - EXTI_LINE87 +*\*\ - EXTI_LINE88 +*\*\ - EXTI_LINE89 +*\*\return SET or RESET +**/ +ITStatus EXTI_GetITStatus( uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + uint32_t line_index; + uint8_t temp_index; + + if(EXTI_Line < 100) + { + temp_index = EXTI_Line / 32; + line_index = (uint32_t)0x00000001 << (EXTI_Line % 32); + + if (Get_CurrentCPU() != CM7_CPU) + { + enablestatus = EXTI->M4IMASK[temp_index] & line_index; + + if ((( EXTI->M4PEND[temp_index] & line_index ) != ( uint32_t )RESET) && ( enablestatus != ( uint32_t )RESET )) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + } + else + { + enablestatus = EXTI->M7IMASK[temp_index] & line_index; + + if ((( EXTI->M7PEND[temp_index] & line_index ) != ( uint32_t )RESET) && ( enablestatus != ( uint32_t )RESET )) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; + } + } + + return bitstatus; +} + +/** +*\*\name EXTI_ClrITPendBit. +*\*\fun Clear EXTI line interrupt pend bit. +*\*\param EXTI_Line +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\ - EXTI_LINE49 +*\*\ - EXTI_LINE52 +*\*\ - EXTI_LINE62 +*\*\ - EXTI_LINE63 +*\*\ - EXTI_LINE64 +*\*\ - EXTI_LINE65 +*\*\ - EXTI_LINE66 +*\*\ - EXTI_LINE67 +*\*\ - EXTI_LINE68 +*\*\ - EXTI_LINE69 +*\*\ - EXTI_LINE70 +*\*\ - EXTI_LINE71 +*\*\ - EXTI_LINE72 +*\*\ - EXTI_LINE73 +*\*\ - EXTI_LINE74 +*\*\ - EXTI_LINE75 +*\*\ - EXTI_LINE81 +*\*\ - EXTI_LINE82 +*\*\ - EXTI_LINE86 +*\*\ - EXTI_LINE87 +*\*\ - EXTI_LINE88 +*\*\ - EXTI_LINE89 +*\*\return none +**/ +void EXTI_ClrITPendBit( uint32_t EXTI_Line) +{ + uint32_t line_index; + + if(EXTI_Line < 100) + { + line_index = (uint32_t)0x00000001 << EXTI_Line % 32; + + if (Get_CurrentCPU() != CM7_CPU) + { + EXTI->M4PEND[EXTI_Line / 32] = line_index; + } + else + { + EXTI->M7PEND[EXTI_Line / 32] = line_index; + } + } +} + +/** +*\*\name EXTI_RTCTimeStampSel. +*\*\fun Select the input of TimeStamp event. +*\*\param EXTI_TSSEL_Line : +*\*\ - EXTI_TSSEL_LINE0 +*\*\ - EXTI_TSSEL_LINE1 +*\*\ - EXTI_TSSEL_LINE2 +*\*\ - EXTI_TSSEL_LINE3 +*\*\ - EXTI_TSSEL_LINE4 +*\*\ - EXTI_TSSEL_LINE5 +*\*\ - EXTI_TSSEL_LINE6 +*\*\ - EXTI_TSSEL_LINE7 +*\*\ - EXTI_TSSEL_LINE8 +*\*\ - EXTI_TSSEL_LINE9 +*\*\ - EXTI_TSSEL_LINE10 +*\*\ - EXTI_TSSEL_LINE11 +*\*\ - EXTI_TSSEL_LINE12 +*\*\ - EXTI_TSSEL_LINE13 +*\*\ - EXTI_TSSEL_LINE14 +*\*\ - EXTI_TSSEL_LINE15 +*\*\return none +**/ +void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line) +{ + uint32_t tempReg; + + tempReg = EXTI->TSSEL; + + tempReg &= ~EXTI_TSSEL_LINE_MASK; + tempReg |= EXTI_TSSEL_Line; + + EXTI->TSSEL = tempReg; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fdcan.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fdcan.c new file mode 100644 index 0000000000..eecb9475a2 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fdcan.c @@ -0,0 +1,4885 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_fdcan.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_fdcan.h" +#include "n32h76x_78x_rcc.h" + +static FDCAN_MsgRamType *pMsgRam[8]; + +/* Get bytes of data according to the DLC value */ +static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + +/* Private function */ +static ErrorStatus FDCAN_InitMsgRam(FDCAN_Module* FDCANx, FDCAN_InitType *FDCAN_InitParam); +static void FDCAN_CopyMsgToRAM(FDCAN_Module *FDCANx, FDCAN_TxHeaderType *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); +static uint8_t FDCAN_Get_Index(FDCAN_Module *FDCANx); + +/** + *\*\name FDCAN_DeInit. + *\*\fun Reset the FDCANx peripheral registers to their default reset values. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_DeInit(FDCAN_Module* FDCANx) +{ + if (FDCANx == FDCAN1) + { + RCC_EnableAPB1PeriphReset5(RCC_APB1_PERIPHRST_FDCAN1); + } + else if (FDCANx == FDCAN2) + { + RCC_EnableAPB1PeriphReset5(RCC_APB1_PERIPHRST_FDCAN2); + } + else if (FDCANx == FDCAN3) + { + RCC_EnableAPB2PeriphReset4(RCC_APB2_PERIPHRST_FDCAN3); + } + else if (FDCANx == FDCAN4) + { + RCC_EnableAPB2PeriphReset4(RCC_APB2_PERIPHRST_FDCAN4); + } + else if (FDCANx == FDCAN5) + { + RCC_EnableAPB1PeriphReset5(RCC_APB1_PERIPHRST_FDCAN5); + } + else if (FDCANx == FDCAN6) + { + RCC_EnableAPB1PeriphReset5(RCC_APB1_PERIPHRST_FDCAN6); + } + else if (FDCANx == FDCAN7) + { + RCC_EnableAPB2PeriphReset4(RCC_APB2_PERIPHRST_FDCAN7); + } + else if (FDCANx == FDCAN8) + { + RCC_EnableAPB2PeriphReset4(RCC_APB2_PERIPHRST_FDCAN8); + } + else + { + /* no process*/ + } +} + +/** + *\*\name FDCAN_Init. + *\*\fun Initializes the FDCAN peripheral according to the specified + *\*\ parameters in the FDCAN_InitParam.. + *\*\param FDCANx pointer to specified FDCAN,must be one of the following value: + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param FDCAN_InitParam: pointer to a FDCAN_InitType structure. + *\*\ - FrameFormat: + *\*\ - FDCAN_FRAME_CLASSIC + *\*\ - FDCAN_FRAME_FD_NO_BRS + *\*\ - FDCAN_FRAME_FD_BRS + *\*\ - Mode: + *\*\ - FDCAN_MODE_NORMAL + *\*\ - FDCAN_MODE_RESTRICTED_OPERATION + *\*\ - FDCAN_MODE_BUS_MONITORING + *\*\ - FDCAN_MODE_INTERNAL_LOOPBACK + *\*\ - FDCAN_MODE_EXTERNAL_LOOPBACK + *\*\ - Prescaler: Must be a value between 1 and 512. + *\*\ - SyncJumpWidth: Must be a value between 1 and 128. + *\*\ - TimeSeg1: Must be a value between 2 and 256. + *\*\ - TimeSeg2: Must be a value between 2 and 128. + *\*\ - DataPrescaler: Must be a value between 1 and 32. + *\*\ - DataSyncJumpWidth: Must be a value between 1 and 16. + *\*\ - DataTimeSeg1: Must be a value between 1 and 32. + *\*\ - DataTimeSeg2: Must be a value between 1 and 16. + *\*\ - MsgRamStrAddr: + *\*\ - FDCAN_START_ADDRESS_SRAM5BANK1 , 0x30050000 as FDCAN base address. + *\*\ - FDCAN_START_ADDRESS_SRAM5BANK2 , 0x30054000 as FDCAN base address. + *\*\ - MsgRamOffset: Must be a value between 0 and 0x1000. + *\*\ - StdFilterSize: Must be a value between 0 and 128. + *\*\ - ExtFilterSize: Must be a value between 0 and 64. + *\*\ - RxFifo0Size: Must be a value between 0 and 64. + *\*\ - RxFifo1Size: Must be a value between 0 and 64. + *\*\ - RxBufferSize: Must be a value between 0 and 64. + *\*\ - TxEventSize: Must be a value between 0 and 32. + *\*\ - TxBufferSize: Must be a value between 0 and 32. + *\*\ - RxFifo0DataSize: + *\*\ - FDCAN_DATA_BYTES_8 + *\*\ - FDCAN_DATA_BYTES_12 + *\*\ - FDCAN_DATA_BYTES_16 + *\*\ - FDCAN_DATA_BYTES_20 + *\*\ - FDCAN_DATA_BYTES_24 + *\*\ - FDCAN_DATA_BYTES_32 + *\*\ - FDCAN_DATA_BYTES_48 + *\*\ - FDCAN_DATA_BYTES_64 + *\*\ - RxFifo1DataSize: + *\*\ - FDCAN_DATA_BYTES_8 + *\*\ - FDCAN_DATA_BYTES_12 + *\*\ - FDCAN_DATA_BYTES_16 + *\*\ - FDCAN_DATA_BYTES_20 + *\*\ - FDCAN_DATA_BYTES_24 + *\*\ - FDCAN_DATA_BYTES_32 + *\*\ - FDCAN_DATA_BYTES_48 + *\*\ - FDCAN_DATA_BYTES_64 + *\*\ - RxBufferDataSize: + *\*\ - FDCAN_DATA_BYTES_8 + *\*\ - FDCAN_DATA_BYTES_12 + *\*\ - FDCAN_DATA_BYTES_16 + *\*\ - FDCAN_DATA_BYTES_20 + *\*\ - FDCAN_DATA_BYTES_24 + *\*\ - FDCAN_DATA_BYTES_32 + *\*\ - FDCAN_DATA_BYTES_48 + *\*\ - FDCAN_DATA_BYTES_64 + *\*\ - TxBufferDataSize: + *\*\ - FDCAN_DATA_BYTES_8 + *\*\ - FDCAN_DATA_BYTES_12 + *\*\ - FDCAN_DATA_BYTES_16 + *\*\ - FDCAN_DATA_BYTES_20 + *\*\ - FDCAN_DATA_BYTES_24 + *\*\ - FDCAN_DATA_BYTES_32 + *\*\ - FDCAN_DATA_BYTES_48 + *\*\ - FDCAN_DATA_BYTES_64 + *\*\ - TxFifoQueueMode: + *\*\ - FDCAN_TX_FIFO_MODE + *\*\ - FDCAN_TX_QUEUE_MODE + *\*\ - TxFifoQueueSize: Must be a value between 0 and 32. + *\*\ - AutoRetransmission: + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - TransmitPause: + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - ProtocolException: + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_Init(FDCAN_Module* FDCANx, FDCAN_InitType *FDCAN_InitParam) +{ + uint32_t timeout; + uint32_t tempReg; + const uint8_t SizeToReg[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}; + + /* Exit from Sleep mode */ + FDCANx->CCCR &= ~FDCAN_CCCR_CSR; + + /* Check Sleep mode acknowledge */ + timeout = 0; + + while ((FDCANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if (timeout > FDCAN_TIMEOUT_VALUE) + { + return ERROR; + } + + timeout++; + } + + /* Request initialisation */ + FDCANx->CCCR |= FDCAN_CCCR_INIT; + + /* Wait until the INIT bit into CCCR register is set */ + timeout = 0; + + while ((FDCANx->CCCR & FDCAN_CCCR_INIT) == 0U) + { + if (timeout > FDCAN_TIMEOUT_VALUE) + { + return ERROR; + } + + timeout++; + } + + /* Enable configuration change */ + FDCANx->CCCR |= FDCAN_CCCR_CCE; + + /* Configuration the CCCR register */ + tempReg = FDCANx->CCCR; + + /* Set the no automatic retransmission */ + if (FDCAN_InitParam->AutoRetransmission == ENABLE) + { + tempReg &= ~FDCAN_CCCR_DAR; + } + else + { + tempReg |= FDCAN_CCCR_DAR; + } + + /* Set the transmit pause feature */ + if (FDCAN_InitParam->TransmitPause == ENABLE) + { + tempReg |= FDCAN_CCCR_TXP; + } + else + { + tempReg &= ~FDCAN_CCCR_TXP; + } + + /* Set the Protocol Exception Handling */ + if (FDCAN_InitParam->ProtocolException == ENABLE) + { + tempReg &= ~FDCAN_CCCR_PXHD; + } + else + { + tempReg |= FDCAN_CCCR_PXHD; + } + + /* Set FDCAN Frame Format */ + tempReg &= ~(FDCAN_CCCR_BRSE | FDCAN_CCCR_FDOE); + tempReg |= FDCAN_InitParam->FrameFormat; + + /* Set FDCAN Operating Mode: + | Normal | Restricted | Bus | Internal | External + | | Operation | Monitoring | LoopBack | LoopBack + CCCR.TEST | 0 | 0 | 0 | 1 | 1 + CCCR.MON | 0 | 0 | 1 | 1 | 0 + TEST.LBCK | 0 | 0 | 0 | 1 | 1 + CCCR.ASM | 0 | 1 | 0 | 0 | 0 + */ + tempReg &= ~(FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM); + tempReg |= FDCAN_InitParam->Mode; + FDCANx->CCCR = tempReg; + + if ((FDCAN_InitParam->Mode & FDCAN_CCCR_TEST) == FDCAN_CCCR_TEST) + { + FDCANx->TEST |= FDCAN_TEST_LBCK; + } + else + { + FDCANx->TEST &= ~FDCAN_TEST_LBCK; + } + + /* Set the nominal bit timing register */ + FDCANx->NBTP = ( ((FDCAN_InitParam->SyncJumpWidth - 1UL) << FDCAN_NBTP_NSJW_OFFSET) \ + | ((FDCAN_InitParam->TimeSeg1 - 1UL) << FDCAN_NBTP_NTSEG1_OFFSET) \ + | ((FDCAN_InitParam->TimeSeg2 - 1UL) << FDCAN_NBTP_NTSEG2_OFFSET) \ + | ((FDCAN_InitParam->Prescaler - 1UL) << FDCAN_NBTP_NBRP_OFFSET) ); + + /* If FD operation with BRS is selected, set the data bit timing register */ + if (FDCAN_InitParam->FrameFormat == FDCAN_FRAME_FD_BRS) + { + FDCANx->DBTP = ( ((FDCAN_InitParam->DataSyncJumpWidth - 1UL) << FDCAN_DBTP_DSJW_OFFSET) \ + | ((FDCAN_InitParam->DataTimeSeg1 - 1UL) << FDCAN_DBTP_DTSEG1_OFFSET) \ + | ((FDCAN_InitParam->DataTimeSeg2 - 1UL) << FDCAN_DBTP_DTSEG2_OFFSET) \ + | ((FDCAN_InitParam->DataPrescaler - 1UL) << FDCAN_DBTP_DBRP_OFFSET) ); + } + + /* Select between Tx FIFO and Tx Queue operation modes */ + tempReg = FDCANx->TXBC & (~FDCAN_TXBC_TFQM); + + if (FDCAN_InitParam->TxFifoQueueSize > 0UL) + { + tempReg |= FDCAN_InitParam->TxFifoQueueMode; + } + + FDCANx->TXBC = tempReg; + + /* Configure Tx element size */ + if ((FDCAN_InitParam->TxBufferSize + FDCAN_InitParam->TxFifoQueueSize) > 0UL) + { + FDCANx->TXESC = (uint32_t)(SizeToReg[FDCAN_InitParam->TxBufferDataSize]); + } + else + { + FDCANx->TXESC = 0; + } + + tempReg = 0; + + /* Configure Rx FIFO 0 element size */ + if (FDCAN_InitParam->RxFifo0Size > 0U) + { + tempReg |= (uint32_t)(SizeToReg[FDCAN_InitParam->RxFifo0DataSize]) << FDCAN_RXESC_F0DS_OFFSET; + } + + /* Configure Rx FIFO 1 element size */ + if (FDCAN_InitParam->RxFifo1Size > 0U) + { + tempReg |= (uint32_t)(SizeToReg[FDCAN_InitParam->RxFifo1DataSize]) << FDCAN_RXESC_F1DS_OFFSET; + } + + /* Configure Rx buffer element size */ + if (FDCAN_InitParam->RxBufferSize > 0U) + { + tempReg |= (uint32_t)(SizeToReg[FDCAN_InitParam->RxBufferDataSize]) << FDCAN_RXESC_RBDS_OFFSET; + } + + FDCANx->RXESC = tempReg; + + /* By default operation mode is set to Event-driven communication. + If Time-triggered communication is needed, user should call the + FDCAN_TT_Init function just after the FDCAN_Init */ + if (FDCAN_Get_Index(FDCANx) <= 4) + { + FDCANx->TTOCF &= ~FDCAN_TTOCF_OM; + } + + /* Calculate each RAM block address and Return function status */ + return (FDCAN_InitMsgRam(FDCANx, FDCAN_InitParam)); +} + +/** + *\*\name FDCAN_EnterSleep. + *\*\fun Enter sleep mode. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_EnterSleep(FDCAN_Module *FDCANx) +{ + uint32_t timeout; + + /* Request clock stop */ + FDCANx->CCCR |= FDCAN_CCCR_CSR; + + timeout = 0; + + /* Wait until FDCAN is ready for power down */ + while ((FDCANx->CCCR & FDCAN_CCCR_CSA) == 0U) + { + if (timeout > FDCAN_TIMEOUT_VALUE) + { + return ERROR; + } + + timeout++; + } + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_ExitSleep. + *\*\fun Exit sleep mode + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_ExitSleep(FDCAN_Module *FDCANx) +{ + uint32_t timeout; + + /* Reset clock stop request */ + FDCANx->CCCR &= ~FDCAN_CCCR_CSR; + + timeout = 0; + + /* Wait until FDCAN exits sleep mode */ + while ((FDCANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if (timeout > FDCAN_TIMEOUT_VALUE) + { + return ERROR; + } + + timeout++; + } + + /* Enter normal operation */ + FDCANx->CCCR &= ~FDCAN_CCCR_INIT; + + timeout = 0; + + /* Wait until FDCAN exits sleep mode */ + while ((FDCANx->CCCR & FDCAN_CCCR_INIT) == FDCAN_CCCR_INIT) + { + if (timeout > FDCAN_TIMEOUT_COUNT) + { + return ERROR; + } + + timeout++; + } + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_ConfigFilter. + *\*\fun Configure the FDCAN reception filter according to the specified + *\*\ parameters in the FDCAN_FilterType structure. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param sFilterConfig pointer to an FDCAN_FilterTypeDef structure + *\*\ - IdType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - FilterIndex + *\*\ This parameter must be a value between: + *\*\ - 0 and 127, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 63, if IdType is FDCAN_EXTENDED_ID + *\*\ - FilterType + *\*\ - FDCAN_FILTER_RANGE + *\*\ - FDCAN_FILTER_DUAL + *\*\ - FDCAN_FILTER_MASK + *\*\ - FDCAN_FILTER_RANGE_NO_EIDM + *\*\ - FilterConfig + *\*\ -FDCAN_FILTER_DISABLE + *\*\ -FDCAN_FILTER_TO_RXFIFO0 + *\*\ -FDCAN_FILTER_TO_RXFIFO1 + *\*\ -FDCAN_FILTER_REJECT + *\*\ -FDCAN_FILTER_HP + *\*\ -FDCAN_FILTER_TO_RXFIFO0_HP + *\*\ -FDCAN_FILTER_TO_RXFIFO1_HP + *\*\ -FDCAN_FILTER_TO_RXBUFFER + *\*\ - FilterID1 + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ - FilterID2 + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ This parameter is ignored if FilterConfig is set to FDCAN_FILTER_TO_RXBUFFER + *\*\ - RxBufferIndex + *\*\ This parameter must be a value between 0 and 63. + *\*\ And it is ignored if FilterConfig is not FDCAN_FILTER_TO_RXBUFFER + *\*\return none + */ +void FDCAN_ConfigFilter(FDCAN_Module *FDCANx, FDCAN_FilterType *sFilterConfig) +{ + uint32_t *FilterAddress; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + if (sFilterConfig->IdType == FDCAN_STANDARD_ID) + { + /* Calculate filter address */ + FilterAddress = (uint32_t *)(pMsg->StdFilterStrAddr + (sFilterConfig->FilterIndex * 4UL)); + + /* Build filter element */ + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + *FilterAddress = ( (sFilterConfig->FilterType) | + (sFilterConfig->FilterConfig << FDCAN_ELEMENT_SFEC_OFFSET) | + (sFilterConfig->FilterID1 << FDCAN_ELEMENT_ID1_OFFSET) | + sFilterConfig->RxBufferIndex ); + } + else + { + *FilterAddress = ( (sFilterConfig->FilterType ) | + (sFilterConfig->FilterConfig << FDCAN_ELEMENT_SFEC_OFFSET) | + (sFilterConfig->FilterID1 << FDCAN_ELEMENT_ID1_OFFSET) | + sFilterConfig->FilterID2 ); + } + } + else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ + { + /* Calculate filter address */ + FilterAddress = (uint32_t *)(pMsg->ExtFilterStrAddr + (sFilterConfig->FilterIndex * FDCAN_EXT_FILTER_WORDS * 4UL)); + + /* Build first word of filter element */ + *FilterAddress = ((sFilterConfig->FilterConfig << FDCAN_ELEMENT_EFEC_OFFSET) | sFilterConfig->FilterID1); + + /* Increment FilterAddress pointer to second word of filter element */ + FilterAddress++; + + /* Build second word of filter element */ + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + *FilterAddress = (sFilterConfig->FilterType | sFilterConfig->RxBufferIndex); + } + else + { + *FilterAddress = (sFilterConfig->FilterType | sFilterConfig->FilterID2); + } + } +} + +/** + *\*\name FDCAN_ConfigGlobalFilter. + *\*\fun Configure the FDCAN global filter. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param NonMatchingStd : + *\*\ - FDCAN_ACCEPT_STD_IN_RX_FIFO0 + *\*\ - FDCAN_ACCEPT_STD_IN_RX_FIFO1 + *\*\ - FDCAN_REJECT_STD + *\*\param NonMatchingExt : + *\*\ - FDCAN_ACCEPT_EXT_IN_RX_FIFO0 + *\*\ - FDCAN_ACCEPT_EXT_IN_RX_FIFO1 + *\*\ - FDCAN_REJECT_EXT + *\*\param RejectRemoteStd : + *\*\ - FDCAN_FILTER_STD_REMOTE + *\*\ - FDCAN_REJECT_STD_REMOTE + *\*\param RejectRemoteExt : + *\*\ - FDCAN_FILTER_EXT_REMOTE + *\*\ - FDCAN_REJECT_EXT_REMOTE + *\*\return + */ +void FDCAN_ConfigGlobalFilter(FDCAN_Module *FDCANx, + uint32_t NonMatchingStd, + uint32_t NonMatchingExt, + uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt) +{ + /* Configure global filter */ + FDCANx->GFC = NonMatchingStd | NonMatchingExt | RejectRemoteStd | RejectRemoteExt; +} + +/** + *\*\name FDCAN_ConfigExtIdMask. + *\*\fun CConfigure the extended ID mask. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Mask :Extended ID Mask. + *\*\ This parameter must be a number between 0 and 0x1FFFFFFF + *\*\return none + */ +void FDCAN_ConfigExtIdMask(FDCAN_Module *FDCANx, uint32_t Mask) +{ + FDCANx->XIDAM = Mask; +} + +/** + *\*\name FDCAN_ConfigRxFifoMode. + *\*\fun Configure the Rx FIFO operation mode. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param RxFifo + *\*\ - FDCAN_RX_FIFO0 + *\*\ - FDCAN_RX_FIFO1 + *\*\param Mode + *\*\ - FDCAN_RX_FIFO_BLOCKING + *\*\ - FDCAN_RX_FIFO_OVERWRITE + *\*\return none + */ +void FDCAN_ConfigRxFifoMode(FDCAN_Module *FDCANx, uint32_t RxFifo, uint32_t Mode) +{ + __IO uint32_t *pReg; + + if (RxFifo == FDCAN_RX_FIFO0) + { + /* Select FIFO 0 Operation Mode */ + pReg = &(FDCANx->RXF0C); + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + /* Select FIFO 1 Operation Mode */ + pReg = &(FDCANx->RXF1C); + } + + if(Mode == FDCAN_RX_FIFO_OVERWRITE) + { + *pReg |= FDCAN_RX_FIFO_OVERWRITE; + } + else /* Mode == FDCAN_RX_FIFO_BLOCKING */ + { + *pReg &= ~FDCAN_RX_FIFO_OVERWRITE; + } +} + +/** + *\*\name FDCAN_ConfigFifoWatermark. + *\*\fun Configure the Tx/RX FIFO watermark. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param FIFO + *\*\ - FDCAN_RX_FIFO0 + *\*\ - FDCAN_RX_FIFO1 + *\*\ - FDCAN_TX_EVENT_FIFO + *\*\param Watermark level for FIFO watermark interrupt. + *\*\ This parameter must be a number between: + *\*\ - 0 and 32, if FIFO is FDCAN_TX_EVENT_FIFO + *\*\ - 0 and 64, if FIFO is FDCAN_RX_FIFO0 or FDCAN_RX_FIFO1 + *\*\return none + */ +void FDCAN_ConfigFifoWatermark(FDCAN_Module *FDCANx, uint32_t FIFO, uint32_t Watermark) +{ + __IO uint32_t *pReg; + uint32_t tempReg; + + /* Set the level for FIFO watermark interrupt */ + if (FIFO == FDCAN_TX_EVENT_FIFO) + { + pReg = &(FDCANx->TXEFC); + tempReg = *pReg & (~FDCAN_TXEFC_EFWM); + } + else if (FIFO == FDCAN_RX_FIFO0) + { + pReg = &(FDCANx->RXF0C); + tempReg = *pReg & (~FDCAN_RXF0C_F0WM); + } + else /* FIFO == FDCAN_RX_FIFO1 */ + { + pReg = &(FDCANx->RXF1C); + tempReg = *pReg & (~FDCAN_RXF1C_F1WM); + } + + tempReg |= Watermark << FDCAN_RXFXC_FXWM_OFFSET; + *pReg = tempReg; +} + +/** + *\*\name FDCAN_ConfigRamWatchdog. + *\*\fun Configure the RAM watchdog. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Value Start value of the Message RAM Watchdog Counter. + *\*\ This parameter must be a number between 0x00 and 0xFF + *\*\return none + */ +void FDCAN_ConfigRamWatchdog(FDCAN_Module *FDCANx, uint32_t Value) +{ + uint32_t tempReg; + + /* Configure the RAM watchdog counter start value */ + tempReg = FDCANx->RWD & (~FDCAN_RWD_WDC); + tempReg |= Value; + FDCANx->RWD = tempReg; +} + +/** + *\*\name FDCAN_ConfigTSPrescaler. + *\*\fun Configure the timestamp counter Prescaler. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Prescaler + *\*\ - FDCAN_TIMESTAMP_PRESC_1 + *\*\ - FDCAN_TIMESTAMP_PRESC_2 + *\*\ - FDCAN_TIMESTAMP_PRESC_3 + *\*\ - FDCAN_TIMESTAMP_PRESC_4 + *\*\ - FDCAN_TIMESTAMP_PRESC_5 + *\*\ - FDCAN_TIMESTAMP_PRESC_6 + *\*\ - FDCAN_TIMESTAMP_PRESC_7 + *\*\ - FDCAN_TIMESTAMP_PRESC_8 + *\*\ - FDCAN_TIMESTAMP_PRESC_9 + *\*\ - FDCAN_TIMESTAMP_PRESC_10 + *\*\ - FDCAN_TIMESTAMP_PRESC_11 + *\*\ - FDCAN_TIMESTAMP_PRESC_12 + *\*\ - FDCAN_TIMESTAMP_PRESC_13 + *\*\ - FDCAN_TIMESTAMP_PRESC_14 + *\*\ - FDCAN_TIMESTAMP_PRESC_15 + *\*\ - FDCAN_TIMESTAMP_PRESC_16 + *\*\return none + */ +void FDCAN_ConfigTSPrescaler(FDCAN_Module *FDCANx, uint32_t Prescaler) +{ + uint32_t tempReg; + + tempReg = FDCANx->TSCC & (~FDCAN_TSCC_TCP); + tempReg |= Prescaler; + FDCANx->TSCC = tempReg; +} + +/** + *\*\name FDCAN_Config_TS. + *\*\fun Config the timestamp mode. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Select + *\*\ - FDCAN_TIMESTAMP_DISABLE + *\*\ - FDCAN_TIMESTAMP_INTERNAL + *\*\ - FDCAN_TIMESTAMP_EXTERNAL + *\*\return none + */ +void FDCAN_Config_TS(FDCAN_Module *FDCANx, uint32_t Select) +{ + uint32_t tempReg; + + tempReg = FDCANx->TSCC & (~FDCAN_TSCC_TSS); + tempReg |= Select; + FDCANx->TSCC = tempReg; +} + +/** + *\*\name FDCAN_Get_TS. + *\*\fun Get the timestamp counter value. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return Value Timestamp counter value + */ +uint16_t FDCAN_Get_TS(FDCAN_Module *FDCANx) +{ + return (uint16_t)(FDCANx->TSCV); +} + +/** + *\*\name FDCAN_Reset_TS. + *\*\fun Reset the internal timestamp counter to zero. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_Reset_TS(FDCAN_Module *FDCANx) +{ + if ((FDCANx->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) + { + /* Reset timestamp counter. + Actually any write operation to TSCV clears the counter */ + FDCANx->TSCV = 0; + } +} + +/** + *\*\name FDCAN_ConfigTimeoutCounter. + *\*\fun Configure the timeout counter. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param TimeoutSelect : + *\*\ - FDCAN_TIMEOUT_CONTINUOUS + *\*\ - FDCAN_TIMEOUT_TX_EVENT_FIFO + *\*\ - FDCAN_TIMEOUT_RX_FIFO0 + *\*\ - FDCAN_TIMEOUT_RX_FIFO1 + *\*\param TimeoutPeriod :Start value of the timeout down-counter. + *\*\ This parameter must be a number between 0x0000 and 0xFFFF + *\*\return none + */ +void FDCAN_ConfigTimeoutCounter(FDCAN_Module *FDCANx, uint32_t TimeoutSelect, uint32_t TimeoutPeriod) +{ + uint32_t tempReg; + + tempReg = FDCANx->TOCC & (~(FDCAN_TOCC_TOS | FDCAN_TOCC_TOP)); + tempReg |= TimeoutSelect; + tempReg |= TimeoutPeriod << FDCAN_TOCC_TOP_OFFSET; + FDCANx->TOCC = tempReg; +} + +/** + *\*\name FDCAN_EnableTimeoutCounter. + *\*\fun Enable the timeout counter. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_EnableTimeoutCounter(FDCAN_Module *FDCANx) +{ + /* Enable timeout counter */ + FDCANx->TOCC |= FDCAN_TOCC_ETOC; +} + +/** + *\*\name FDCAN_DisableTimeoutCounter. + *\*\fun Disable the timeout counter. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_DisableTimeoutCounter(FDCAN_Module *FDCANx) +{ + /* Enable timeout counter */ + FDCANx->TOCC &= ~FDCAN_TOCC_ETOC; +} + +/** + *\*\name FDCAN_GetTimeoutCounter. + *\*\fun Get the timeout counter value. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return Timeout counter value + */ +uint16_t FDCAN_GetTimeoutCounter(FDCAN_Module *FDCANx) +{ + return (uint16_t)(FDCANx->TOCV); +} + +/** + *\*\name FDCAN_ResetTimeoutCounter. + *\*\fun Reset the timeout counter to its start value. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_ResetTimeoutCounter(FDCAN_Module *FDCANx) +{ + FDCANx->TOCV = 0; +} + +/** + *\*\name FDCAN_ConfigTxDelayCompensation. + *\*\fun Configure the transmitter delay compensation. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Offset :Transmitter Delay Compensation Offset. + *\*\ This parameter must be a number between 0x00 and 0x7F. + *\*\param Filter :Transmitter Delay Compensation Filter Window Length. + *\*\ This parameter must be a number between 0x00 and 0x7F. + *\*\return none + */ +void FDCAN_ConfigTxDelayCompensation(FDCAN_Module *FDCANx, uint32_t Offset, uint32_t Filter) +{ + uint32_t tempReg; + + tempReg = FDCANx->TDCR & (~(FDCAN_TDCR_TDCO | FDCAN_TDCR_TDCF)); + tempReg |= Offset << FDCAN_TDCR_TDCO_OFFSET; + tempReg |= Filter; + FDCANx->TDCR = tempReg; +} + +/** + *\*\name FDCAN_EnableTxDelayCompensation. + *\*\fun Enable the transmitter delay compensation. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_EnableTxDelayCompensation(FDCAN_Module *FDCANx) +{ + FDCANx->DBTP |= FDCAN_DBTP_TDC; +} + +/** + *\*\name FDCAN_DisableTxDelayCompensation. + *\*\fun Disable the transmitter delay compensation. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_DisableTxDelayCompensation(FDCAN_Module *FDCANx) +{ + FDCANx->DBTP &= ~FDCAN_DBTP_TDC; +} + +/** + *\*\name FDCAN_EnableISOMode. + *\*\fun Enable ISO 11898-1 protocol mode. + *\*\ CAN FD frame format is according to ISO 11898-1 standard. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_EnableISOMode(FDCAN_Module *FDCANx) +{ + /* Disable Non ISO protocol mode */ + FDCANx->CCCR &= ~FDCAN_CCCR_NISO; +} + +/** + *\*\name FDCAN_DisableISOMode. + *\*\fun Disable ISO 11898-1 protocol mode. + *\*\ CAN FD frame format is according to Bosch CAN FD specification V1.0. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_DisableISOMode(FDCAN_Module *FDCANx) +{ + /* Enable Non ISO protocol mode */ + FDCANx->CCCR |= FDCAN_CCCR_NISO; +} + +/** + *\*\name FDCAN_EnableEdgeFilter. + *\*\fun Enable edge filtering during bus integration. + *\*\ Two consecutive dominant tq are required to detect an edge for hard synchronization. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_EnableEdgeFilter(FDCAN_Module *FDCANx) +{ + /* Enable edge filtering */ + FDCANx->CCCR |= FDCAN_CCCR_EFBI; +} + +/** + *\*\name FDCAN_DisableEdgeFilter. + *\*\fun Disable edge filtering during bus integration. + *\*\ One dominant tq is required to detect an edge for hard synchronization. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_DisableEdgeFilter(FDCAN_Module *FDCANx) +{ + /* Disable edge filtering */ + FDCANx->CCCR &= ~FDCAN_CCCR_EFBI; +} + +/** + *\*\name FDCAN_Start. + *\*\fun Start the FDCAN module. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_Start(FDCAN_Module *FDCANx) +{ + /* Request leave initialisation */ + FDCANx->CCCR &= ~FDCAN_CCCR_INIT; +} + +/** + *\*\name FDCAN_Stop. + *\*\fun Stop the FDCAN module and enable access to configuration registers. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_Stop(FDCAN_Module *FDCANx) +{ + uint32_t timeout; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Request initialisation */ + FDCANx->CCCR |= FDCAN_CCCR_INIT; + + /* Wait until the INIT bit into CCCR register is set */ + timeout = 0; + + while ((FDCANx->CCCR & FDCAN_CCCR_INIT) == 0U) + { + if (timeout > FDCAN_TIMEOUT_COUNT) + { + return ERROR; + } + + timeout++; + } + + /* Exit from Sleep mode */ + FDCANx->CCCR &= ~FDCAN_CCCR_CSR; + + timeout = 0; + + /* Wait until FDCAN exits sleep mode */ + while ((FDCANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if (timeout > FDCAN_TIMEOUT_COUNT) + { + return ERROR; + } + + timeout++; + } + + /* Enable configuration change */ + FDCANx->CCCR |= FDCAN_CCCR_CCE; + + /* Reset Latest Tx FIFO/Queue Request Buffer Index */ + pMsg->LastTxFifoQReqBuf = 0; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_AddMsgToTxFifoQ. + *\*\fun Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param pTxHeader :pointer to a FDCAN_TxHeaderType structure. + *\*\ - IdType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - ID + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ - TxFrameType + *\*\ - FDCAN_DATA_FRAME + *\*\ - FDCAN_REMOTE_FRAME + *\*\ - DataLength + *\*\ - FDCAN_DLC_BYTES_0 + *\*\ - FDCAN_DLC_BYTES_1 + *\*\ - FDCAN_DLC_BYTES_2 + *\*\ - FDCAN_DLC_BYTES_3 + *\*\ - FDCAN_DLC_BYTES_4 + *\*\ - FDCAN_DLC_BYTES_5 + *\*\ - FDCAN_DLC_BYTES_6 + *\*\ - FDCAN_DLC_BYTES_7 + *\*\ - FDCAN_DLC_BYTES_8 + *\*\ - FDCAN_DLC_BYTES_12 + *\*\ - FDCAN_DLC_BYTES_16 + *\*\ - FDCAN_DLC_BYTES_20 + *\*\ - FDCAN_DLC_BYTES_24 + *\*\ - FDCAN_DLC_BYTES_32 + *\*\ - FDCAN_DLC_BYTES_48 + *\*\ - FDCAN_DLC_BYTES_64 + *\*\ - ErrorState + *\*\ - FDCAN_ESI_ACTIVE + *\*\ - FDCAN_ESI_PASSIVE + *\*\ - BitRateSwitch + *\*\ - FDCAN_BRS_OFF + *\*\ - FDCAN_BRS_ON + *\*\ - FDFormat + *\*\ - FDCAN_CLASSIC_CAN + *\*\ - FDCAN_FD_CAN + *\*\ - TxEventFifo + *\*\ - FDCAN_NO_TX_EVENTS + *\*\ - FDCAN_STORE_TX_EVENTS + *\*\ - MsgMarker + *\*\ This parameter must be a value between 0 and 0xFF + *\*\param pTxData :pointer to a buffer containing the payload of the Tx frame. + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_AddMsgToTxFifoQ(FDCAN_Module *FDCANx, FDCAN_TxHeaderType *pTxHeader, uint8_t *pTxData) +{ + uint32_t PutIndex; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Check that the Tx FIFO/Queue has an allocated area into the RAM */ + if ((FDCANx->TXBC & FDCAN_TXBC_TFQS) == 0U) + { + return ERROR; + } + + /* Check that the Tx FIFO/Queue is not full */ + if ((FDCANx->TXFQS & FDCAN_TXFQS_TFQF) != 0U) + { + return ERROR; + } + + /* Get the Tx FIFO PutIndex */ + PutIndex = ((FDCANx->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_OFFSET); + + /* Add the message to the Tx FIFO/Queue */ + FDCAN_CopyMsgToRAM(FDCANx, pTxHeader, pTxData, PutIndex); + + /* Activate the corresponding transmission request */ + FDCANx->TXBAR = (0x1UL << PutIndex); + + /* Store the Latest Tx FIFO/Queue Request Buffer Index */ + pMsg->LastTxFifoQReqBuf = (0x1UL << PutIndex); + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_AddMsgToTxBuffer. + *\*\fun Add a message to a dedicated Tx buffer + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param pTxHeader :pointer to a FDCAN_TxHeaderType structure. + *\*\ - IdType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - ID + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ - TxFrameType + *\*\ - FDCAN_DATA_FRAME + *\*\ - FDCAN_REMOTE_FRAME + *\*\ - DataLength + *\*\ - FDCAN_DLC_BYTES_0 + *\*\ - FDCAN_DLC_BYTES_1 + *\*\ - FDCAN_DLC_BYTES_2 + *\*\ - FDCAN_DLC_BYTES_3 + *\*\ - FDCAN_DLC_BYTES_4 + *\*\ - FDCAN_DLC_BYTES_5 + *\*\ - FDCAN_DLC_BYTES_6 + *\*\ - FDCAN_DLC_BYTES_7 + *\*\ - FDCAN_DLC_BYTES_8 + *\*\ - FDCAN_DLC_BYTES_12 + *\*\ - FDCAN_DLC_BYTES_16 + *\*\ - FDCAN_DLC_BYTES_20 + *\*\ - FDCAN_DLC_BYTES_24 + *\*\ - FDCAN_DLC_BYTES_32 + *\*\ - FDCAN_DLC_BYTES_48 + *\*\ - FDCAN_DLC_BYTES_64 + *\*\ - ErrorState + *\*\ - FDCAN_ESI_ACTIVE + *\*\ - FDCAN_ESI_PASSIVE + *\*\ - BitRateSwitch + *\*\ - FDCAN_BRS_OFF + *\*\ - FDCAN_BRS_ON + *\*\ - FDFormat + *\*\ - FDCAN_CLASSIC_CAN + *\*\ - FDCAN_FD_CAN + *\*\ - TxEventFifo + *\*\ - FDCAN_NO_TX_EVENTS + *\*\ - FDCAN_STORE_TX_EVENTS + *\*\ - MsgMarker + *\*\ This parameter must be a value between 0 and 0xFF + *\*\param pTxData :pointer to a buffer containing the payload of the Tx frame. + *\*\param BufferIndex : + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_AddMsgToTxBuffer(FDCAN_Module *FDCANx, FDCAN_TxHeaderType *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex) +{ + /* Check that the selected buffer has an allocated area into the RAM */ + if (POSITION_VAL(BufferIndex) >= ((FDCANx->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_OFFSET)) + { + return ERROR; + } + + /* Check if there is also transmission request pending for the selected buffer */ + if ((FDCANx->TXBRP & BufferIndex) != 0U) + { + return ERROR; + } + + /* Add the message to the Tx buffer */ + FDCAN_CopyMsgToRAM(FDCANx, pTxHeader, pTxData, POSITION_VAL(BufferIndex)); + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_EnableTxBufferRequest. + *\*\fun Enable transmission request. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param BufferIndex : + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return none + */ +void FDCAN_EnableTxBufferRequest(FDCAN_Module *FDCANx, uint32_t BufferIndex) +{ + /* Add transmission request */ + FDCANx->TXBAR = BufferIndex; +} + +/** + *\*\name FDCAN_GetLastTxFifoQReqBuf. + *\*\fun Get Tx buffer index of latest Tx FIFO/Queue request. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return Tx buffer index of last Tx FIFO/Queue request + *\*\ - 0: no Tx FIFO/Queue request have been submitted + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + */ +uint32_t FDCAN_GetLastTxFifoQReqBuf(FDCAN_Module *FDCANx) +{ + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Return Last Tx FIFO/Queue Request Buffer */ + return (pMsg->LastTxFifoQReqBuf); +} + +/** + *\*\name FDCAN_AbortTxRequest. + *\*\fun Abort transmission request. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param BufferIndex : + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return none + */ +void FDCAN_AbortTxRequest(FDCAN_Module *FDCANx, uint32_t BufferIndex) +{ + /* Add cancellation request */ + FDCANx->TXBCR = BufferIndex; +} + +/** + *\*\name FDCAN_GetRxMsg. + *\*\fun Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param RxLocation : + *\*\ - FDCAN_RX_FIFO0 + *\*\ - FDCAN_RX_FIFO1 + *\*\ - FDCAN_RX_BUFFER0 + *\*\ - FDCAN_RX_BUFFER1 + *\*\ - FDCAN_RX_BUFFER2 + *\*\ - FDCAN_RX_BUFFER3 + *\*\ - FDCAN_RX_BUFFER4 + *\*\ - FDCAN_RX_BUFFER5 + *\*\ - FDCAN_RX_BUFFER6 + *\*\ - FDCAN_RX_BUFFER7 + *\*\ - FDCAN_RX_BUFFER8 + *\*\ - FDCAN_RX_BUFFER9 + *\*\ - FDCAN_RX_BUFFER10 + *\*\ - FDCAN_RX_BUFFER11 + *\*\ - FDCAN_RX_BUFFER12 + *\*\ - FDCAN_RX_BUFFER13 + *\*\ - FDCAN_RX_BUFFER14 + *\*\ - FDCAN_RX_BUFFER15 + *\*\ - FDCAN_RX_BUFFER16 + *\*\ - FDCAN_RX_BUFFER17 + *\*\ - FDCAN_RX_BUFFER18 + *\*\ - FDCAN_RX_BUFFER19 + *\*\ - FDCAN_RX_BUFFER20 + *\*\ - FDCAN_RX_BUFFER21 + *\*\ - FDCAN_RX_BUFFER22 + *\*\ - FDCAN_RX_BUFFER23 + *\*\ - FDCAN_RX_BUFFER24 + *\*\ - FDCAN_RX_BUFFER25 + *\*\ - FDCAN_RX_BUFFER26 + *\*\ - FDCAN_RX_BUFFER27 + *\*\ - FDCAN_RX_BUFFER28 + *\*\ - FDCAN_RX_BUFFER29 + *\*\ - FDCAN_RX_BUFFER30 + *\*\ - FDCAN_RX_BUFFER31 + *\*\ - FDCAN_RX_BUFFER32 + *\*\ - FDCAN_RX_BUFFER33 + *\*\ - FDCAN_RX_BUFFER34 + *\*\ - FDCAN_RX_BUFFER35 + *\*\ - FDCAN_RX_BUFFER36 + *\*\ - FDCAN_RX_BUFFER37 + *\*\ - FDCAN_RX_BUFFER38 + *\*\ - FDCAN_RX_BUFFER39 + *\*\ - FDCAN_RX_BUFFER40 + *\*\ - FDCAN_RX_BUFFER41 + *\*\ - FDCAN_RX_BUFFER42 + *\*\ - FDCAN_RX_BUFFER43 + *\*\ - FDCAN_RX_BUFFER44 + *\*\ - FDCAN_RX_BUFFER45 + *\*\ - FDCAN_RX_BUFFER46 + *\*\ - FDCAN_RX_BUFFER47 + *\*\ - FDCAN_RX_BUFFER48 + *\*\ - FDCAN_RX_BUFFER49 + *\*\ - FDCAN_RX_BUFFER50 + *\*\ - FDCAN_RX_BUFFER51 + *\*\ - FDCAN_RX_BUFFER52 + *\*\ - FDCAN_RX_BUFFER53 + *\*\ - FDCAN_RX_BUFFER54 + *\*\ - FDCAN_RX_BUFFER55 + *\*\ - FDCAN_RX_BUFFER56 + *\*\ - FDCAN_RX_BUFFER57 + *\*\ - FDCAN_RX_BUFFER58 + *\*\ - FDCAN_RX_BUFFER59 + *\*\ - FDCAN_RX_BUFFER60 + *\*\ - FDCAN_RX_BUFFER61 + *\*\ - FDCAN_RX_BUFFER62 + *\*\ - FDCAN_RX_BUFFER63 + *\*\param pRxHeader :pointer to a FDCAN_RxHeaderType structure. + *\*\ - IdType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - ID + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ - RxFrameType + *\*\ - FDCAN_DATA_FRAME + *\*\ - FDCAN_REMOTE_FRAME + *\*\ - DataLength + *\*\ - FDCAN_DLC_BYTES_0 + *\*\ - FDCAN_DLC_BYTES_1 + *\*\ - FDCAN_DLC_BYTES_2 + *\*\ - FDCAN_DLC_BYTES_3 + *\*\ - FDCAN_DLC_BYTES_4 + *\*\ - FDCAN_DLC_BYTES_5 + *\*\ - FDCAN_DLC_BYTES_6 + *\*\ - FDCAN_DLC_BYTES_7 + *\*\ - FDCAN_DLC_BYTES_8 + *\*\ - FDCAN_DLC_BYTES_12 + *\*\ - FDCAN_DLC_BYTES_16 + *\*\ - FDCAN_DLC_BYTES_20 + *\*\ - FDCAN_DLC_BYTES_24 + *\*\ - FDCAN_DLC_BYTES_32 + *\*\ - FDCAN_DLC_BYTES_48 + *\*\ - FDCAN_DLC_BYTES_64 + *\*\ - ErrorState + *\*\ - FDCAN_ESI_ACTIVE + *\*\ - FDCAN_ESI_PASSIVE + *\*\ - BitRateSwitch + *\*\ - FDCAN_BRS_OFF + *\*\ - FDCAN_BRS_ON + *\*\ - FDFormat + *\*\ - FDCAN_CLASSIC_CAN + *\*\ - FDCAN_FD_CAN + *\*\ - RxTimestamp + *\*\ This parameter must be a value between 0 and 0xFFFF + *\*\ - FilterIndex + *\*\ This parameter must be a value between: + *\*\ - 0 and 127, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 63, if IdType is FDCAN_EXTENDED_ID + *\*\ - Matching + *\*\ - FDCAN_ACCEPT_MACHING_FIDX + *\*\ - FDCAN_ACCEPT_NON_MATCHING + *\*\param pRxData :pointer to a buffer containing the payload of the Rx frame. + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_GetRxMsg(FDCAN_Module *FDCANx, uint32_t RxLocation, FDCAN_RxHeaderType *pRxHeader, uint8_t *pRxData) +{ + uint32_t *RxAddress; + uint8_t *pData; + uint32_t Cnt; + uint32_t GetIndex; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + GetIndex = 0; + + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 has an allocated area into the RAM */ + if ((FDCANx->RXF0C & FDCAN_RXF0C_F0S) == 0UL) + { + return ERROR; + } + + /* Check that the Rx FIFO 0 is not empty */ + if ((FDCANx->RXF0S & FDCAN_RXF0S_F0FL) == 0UL) + { + return ERROR; + } + + /* Calculate Rx FIFO 0 element get index*/ + GetIndex = ((FDCANx->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXFXS_FXGI_OFFSET); + + /* Check that the Rx FIFO 0 is full & overwrite mode is on*/ + if(FDCAN_RXF0S_F0F == (FDCANx->RXF0S & FDCAN_RXF0S_F0F)) + { + if(FDCAN_RX_FIFO_OVERWRITE == (FDCANx->RXF0C & FDCAN_RXF0C_F0OM)) + { + /* When overwrite status is on discard first message in FIFO */ + if(GetIndex >= (pMsg->RxFifo0Size - 1UL)) + { + GetIndex = 0; + } + else + { + GetIndex++; + } + } + } + + /* Calculate Rx FIFO 0 element address */ + RxAddress = (uint32_t *)(pMsg->RxFIFO0StrAddr + (GetIndex * pMsg->RxFifo0DataSize * 4UL)); + } + else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 has an allocated area into the RAM */ + if ((FDCANx->RXF1C & FDCAN_RXF1C_F1S) == 0U) + { + return ERROR; + } + + /* Check that the Rx FIFO 0 is not empty */ + if ((FDCANx->RXF1S & FDCAN_RXF1S_F1FL) == 0U) + { + return ERROR; + } + + /* Calculate Rx FIFO 1 element index*/ + GetIndex = ((FDCANx->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXFXS_FXGI_OFFSET); + + /* Check that the Rx FIFO 1 is full & overwrite mode is on*/ + if(FDCAN_RXF1S_F1F == (FDCANx->RXF1S & FDCAN_RXF1S_F1F) ) + { + if(FDCAN_RX_FIFO_OVERWRITE == (FDCANx->RXF1C & FDCAN_RXF1C_F1OM)) + { + /* When overwrite status is on discard first message in FIFO */ + if(GetIndex >= (pMsg->RxFifo1Size - 1UL)) + { + GetIndex = 0; + } + else + { + GetIndex++; + } + } + } + + /* Calculate Rx FIFO 1 element address */ + RxAddress = (uint32_t *)(pMsg->RxFIFO1StrAddr + (GetIndex * pMsg->RxFifo1DataSize * 4UL)); + } + else /* Rx element is assigned to a dedicated Rx buffer */ + { + /* Check that the selected buffer has an allocated area into the RAM */ + if (RxLocation >= pMsg->RxBufferSize) + { + return ERROR; + } + + /* Calculate Rx buffer address */ + RxAddress = (uint32_t *)(pMsg->RxBufferStrAddr + (RxLocation * pMsg->RxBufferDataSize * 4U)); + } + + /* First word of Rx FIFO element */ + /* Retrieve IdType */ + pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_XTD; + + /* Retrieve Identifier */ + if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pRxHeader->ID = ((*RxAddress & FDCAN_ELEMENT_STDID) >> FDCAN_ELEMENT_STDID_OFFSET); + } + else /* Extended ID element */ + { + pRxHeader->ID = (*RxAddress & FDCAN_ELEMENT_EXTID); + } + + /* Retrieve RxFrameType */ + pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_RTR); + + /* Retrieve ErrorStateIndicator */ + pRxHeader->ErrorState = (*RxAddress & FDCAN_ELEMENT_ESI); + + /* Increment RxAddress pointer to second word of Rx FIFO element */ + RxAddress++; + + /* Retrieve RxTimestamp */ + pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_TS); + + /* Retrieve DataLength */ + pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_DLC); + + /* Retrieve BitRateSwitch */ + pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_BRS); + + /* Retrieve FDFormat */ + pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_FDF); + + /* Retrieve FilterIndex */ + pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_FIDX) >> FDCAN_ELEMENT_FIDX_OFFSET); + + /* Retrieve NonMatchingFrame */ + pRxHeader->Matching = (*RxAddress & FDCAN_ELEMENT_ANMF); + + /* Increment RxAddress pointer to payload of Rx FIFO element */ + RxAddress++; + + /* Retrieve Rx payload */ + pData = (uint8_t *)RxAddress; + + for (Cnt = 0; Cnt < DLCtoBytes[pRxHeader->DataLength >> FDCAN_ELEMENT_DLC_OFFSET]; Cnt++) + { + pRxData[Cnt] = pData[Cnt]; + } + + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */ + FDCANx->RXF0A = GetIndex; + } + else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */ + FDCANx->RXF1A = GetIndex; + } + else /* Rx element is assigned to a dedicated Rx buffer */ + { + /* Clear the New Data flag of the current Rx buffer */ + if (RxLocation < FDCAN_RX_BUFFER32) + { + FDCANx->NDAT1 = (1UL << RxLocation); + } + else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */ + { + FDCANx->NDAT2 = (1UL << (RxLocation & 0x1FUL)); + } + } + + return SUCCESS; +} + +/** + *\*\name FDCAN_GetTxEvent. + *\*\fun Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param pTxEvent pointer to a FDCAN_TxEventFifoType structure. + *\*\ - IdType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - ID + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ - TxFrameType + *\*\ - FDCAN_DATA_FRAME + *\*\ - FDCAN_REMOTE_FRAME + *\*\ - DataLength + *\*\ - FDCAN_DLC_BYTES_0 + *\*\ - FDCAN_DLC_BYTES_1 + *\*\ - FDCAN_DLC_BYTES_2 + *\*\ - FDCAN_DLC_BYTES_3 + *\*\ - FDCAN_DLC_BYTES_4 + *\*\ - FDCAN_DLC_BYTES_5 + *\*\ - FDCAN_DLC_BYTES_6 + *\*\ - FDCAN_DLC_BYTES_7 + *\*\ - FDCAN_DLC_BYTES_8 + *\*\ - FDCAN_DLC_BYTES_12 + *\*\ - FDCAN_DLC_BYTES_16 + *\*\ - FDCAN_DLC_BYTES_20 + *\*\ - FDCAN_DLC_BYTES_24 + *\*\ - FDCAN_DLC_BYTES_32 + *\*\ - FDCAN_DLC_BYTES_48 + *\*\ - FDCAN_DLC_BYTES_64 + *\*\ - ErrorState + *\*\ - FDCAN_ESI_ACTIVE + *\*\ - FDCAN_ESI_PASSIVE + *\*\ - BitRateSwitch; + *\*\ - FDCAN_BRS_OFF + *\*\ - FDCAN_BRS_ON + *\*\ - FDFormat; + *\*\ - FDCAN_CLASSIC_CAN + *\*\ - FDCAN_FD_CAN + *\*\ - TxTimestamp; + *\*\ This parameter must be a value between 0 and 0xFFFF + *\*\ - MsgMarker; + *\*\ This parameter must be a value between 0 and 0xFF + *\*\ - EventType; + *\*\ - FDCAN_TX_EVENT + *\*\ - FDCAN_TX_IN_SPITE_OF_ABORT + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_GetTxEvent(FDCAN_Module *FDCANx, FDCAN_TxEventFifoType *pTxEvent) +{ + uint32_t *TxEventAddress; + uint32_t GetIndex; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Check that the Tx Event FIFO has an allocated area into the RAM */ + if ((FDCANx->TXEFC & FDCAN_TXEFC_EFS) == 0UL) + { + return ERROR; + } + + /* Check that the Tx event FIFO is not empty */ + if ((FDCANx->TXEFS & FDCAN_TXEFS_EFFL) == 0UL) + { + return ERROR; + } + + /* Calculate Tx event FIFO element address */ + GetIndex = ((FDCANx->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_OFFSET); + TxEventAddress = (uint32_t *)(pMsg->TxEventFIFOStrAddr + (GetIndex * FDCAN_TX_EVENT_FIFO_WORDS * 4UL)); + + /* First word of Tx Event FIFO element */ + /* Retrieve IdType */ + pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_XTD; + + /* Retrieve Identifier */ + if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pTxEvent->ID = ((*TxEventAddress & FDCAN_ELEMENT_STDID) >> FDCAN_ELEMENT_STDID_OFFSET); + } + else /* Extended ID element */ + { + pTxEvent->ID = (*TxEventAddress & FDCAN_ELEMENT_EXTID); + } + + /* Retrieve TxFrameType */ + pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_RTR); + + /* Retrieve ErrorStateIndicator */ + pTxEvent->ErrorState = (*TxEventAddress & FDCAN_ELEMENT_ESI); + + /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */ + TxEventAddress++; + + /* Retrieve TxTimestamp */ + pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_TS); + + /* Retrieve DataLength */ + pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_DLC); + + /* Retrieve BitRateSwitch */ + pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_BRS); + + /* Retrieve FDFormat */ + pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_FDF); + + /* Retrieve EventType */ + pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_ET); + + /* Retrieve MessageMarker */ + pTxEvent->MsgMarker = ((*TxEventAddress & FDCAN_ELEMENT_MM) >> FDCAN_ELEMENT_MM_OFFSET); + + /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */ + FDCANx->TXEFA = GetIndex; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_GetHpMsgStatus. + *\*\fun Get high priority message status. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param HpMsgStatus pointer to an FDCAN_HpMsgStatus structure. + *\*\ - FilterList + *\*\ - FDCAN_HP_STANDARD_FILTER_LIST + *\*\ - FDCAN_HP_EXTENDED_FILTER_LIST + *\*\ - FilterIndex + *\*\ This parameter can be a value between: + *\*\ - 0 and 127, if FilterList is FDCAN_HP_STANDARD_FILTER_LIST + *\*\ - 0 and 63, if FilterList is FDCAN_HP_EXTENDED_FILTER_LIST + *\*\ - MsgStore + *\*\ - FDCAN_HP_STORAGE_NO_FIFO + *\*\ - FDCAN_HP_STORAGE_MSG_LOST + *\*\ - FDCAN_HP_STORAGE_RXFIFO0 + *\*\ - FDCAN_HP_STORAGE_RXFIFO1 + *\*\ - MsgIndex + *\*\ - FDCAN_HP_STORAGE_RXFIFO0 + *\*\ - FDCAN_HP_STORAGE_RXFIFO1 + *\*\return none + */ +void FDCAN_GetHpMsgStatus(FDCAN_Module *FDCANx, FDCAN_HpMsgStatus *HpMsgStatus) +{ + HpMsgStatus->FilterList = (FDCANx->HPMS & FDCAN_HPMS_FLST); + HpMsgStatus->FilterIndex = ((FDCANx->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_OFFSET); + HpMsgStatus->MsgStore = (FDCANx->HPMS & FDCAN_HPMS_MSI); + HpMsgStatus->MsgIndex = (FDCANx->HPMS & FDCAN_HPMS_BIDX); +} + +/** + *\*\name FDCAN_GetProtocolStatus. + *\*\fun Get protocol status. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param ProtocolStatus pointer to an FDCAN_ProtocolStatus structure. + *\*\ - uint32_t LastError + *\*\ - FDCAN_LAST_ERROR_NONE + *\*\ - FDCAN_LAST_ERROR_STUFF + *\*\ - FDCAN_LAST_ERROR_FORM + *\*\ - FDCAN_LAST_ERROR_ACK + *\*\ - FDCAN_LAST_ERROR_BIT1 + *\*\ - FDCAN_LAST_ERROR_BIT0 + *\*\ - FDCAN_LAST_ERROR_CRC + *\*\ - FDCAN_LAST_ERROR_NO_CHANGE + *\*\ - uint32_t LastDataError + *\*\ - FDCAN_LAST_DATA_ERROR_NONE + *\*\ - FDCAN_LAST_DATA_ERROR_STUFF + *\*\ - FDCAN_LAST_DATA_ERROR_FORM + *\*\ - FDCAN_LAST_DATA_ERROR_ACK + *\*\ - FDCAN_LAST_DATA_ERROR_BIT1 + *\*\ - FDCAN_LAST_DATA_ERROR_BIT0 + *\*\ - FDCAN_LAST_DATA_ERROR_CRC + *\*\ - FDCAN_LAST_DATA_ERROR_NO_CHANGE + *\*\ - uint32_t Activity + *\*\ - FDCAN_COM_STATE_SYNC + *\*\ - FDCAN_COM_STATE_IDLE + *\*\ - FDCAN_COM_STATE_RX + *\*\ - FDCAN_COM_STATE_TX + *\*\ - uint32_t Error + *\*\ - FDCAN_ERROR_ACTIVE + *\*\ - FDCAN_ERROR_PASSIVE + *\*\ - uint32_t Warning + *\*\ - FDCAN_WARNING_BELOW_96 + *\*\ - FDCAN_WARNING_REACH_96 + *\*\ - uint32_t BusOff + *\*\ - FDCAN_BUS_ON + *\*\ - FDCAN_BUS_OFF + *\*\ - uint32_t RxESIflag + *\*\ - FDCAN_ESI_NOT_SET + *\*\ - FDCAN_ESI_SET + *\*\ - uint32_t RxBRSflag + *\*\ - FDCAN_BRS_NOT_SET + *\*\ - FDCAN_BRS_SET + *\*\ - uint32_t RxFDFflag + *\*\ - FDCAN_FDMSG_NOT_RECEIVED + *\*\ - FDCAN_FDMSG_RECEIVED + *\*\ - uint32_t Exception + *\*\ - FDCAN_NO_EXCEPTION + *\*\ - FDCAN_HAVE_EXCEPTION + *\*\ - uint32_t TDCvalue + *\*\ This parameter can be a value between 0 and 127 + *\*\return none + */ +void FDCAN_GetProtocolStatus(FDCAN_Module *FDCANx, FDCAN_ProtocolStatus *ProtocolStatus) +{ + uint32_t StatusReg; + + /* Read the protocol status register */ + StatusReg = FDCANx->PSR; + + /* Fill the protocol status structure */ + ProtocolStatus->LastError = (StatusReg & FDCAN_PSR_LEC); + ProtocolStatus->LastDataError = (StatusReg & FDCAN_PSR_DLEC); + ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT); + ProtocolStatus->Error = (StatusReg & FDCAN_PSR_EP); + ProtocolStatus->Warning = (StatusReg & FDCAN_PSR_EW); + ProtocolStatus->BusOff = (StatusReg & FDCAN_PSR_BO); + ProtocolStatus->RxESIflag = (StatusReg & FDCAN_PSR_RESI); + ProtocolStatus->RxBRSflag = (StatusReg & FDCAN_PSR_RBRS); + ProtocolStatus->RxFDFflag = (StatusReg & FDCAN_PSR_RFDF); + ProtocolStatus->Exception = (StatusReg & FDCAN_PSR_PXE); + ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_OFFSET); +} + +/** + *\*\name FDCAN_GetErrorCounters. + *\*\fun Get error counter values. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param ErrorCounters pointer to an FDCAN_ErrorCounters structure. + *\*\ - TxErrorCnt + *\*\ This parameter can be a value between 0 and 255 + *\*\ - RxErrorCnt + *\*\ This parameter can be a value between 0 and 127 + *\*\ - RxErrorPassive + *\*\ - FDCAN_RX_ERROR_BELOW_128 + *\*\ - FDCAN_RX_ERROR_REACH_128 + *\*\ - ErrorLogging + *\*\ This parameter can be a value between 0 and 255. + *\*\return none + */ +void FDCAN_GetErrorCounters(FDCAN_Module *FDCANx, FDCAN_ErrorCounters *ErrorCounters) +{ + uint32_t CountersReg; + + /* Read the error counters register */ + CountersReg = FDCANx->ECR; + + /* Fill the error counters structure */ + ErrorCounters->TxErrorCnt = (CountersReg & FDCAN_ECR_TEC); + ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_OFFSET); + ErrorCounters->RxErrorPassive = (CountersReg & FDCAN_ECR_RP); + ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_OFFSET); +} + +/** + *\*\name FDCAN_CheckNewRxBufMsg. + *\*\fun Check if a new message is received in the selected Rx buffer. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Index Rx buffer index. + *\*\ - FDCAN_RX_BUFFER0 + *\*\ - FDCAN_RX_BUFFER1 + *\*\ - FDCAN_RX_BUFFER2 + *\*\ - FDCAN_RX_BUFFER3 + *\*\ - FDCAN_RX_BUFFER4 + *\*\ - FDCAN_RX_BUFFER5 + *\*\ - FDCAN_RX_BUFFER6 + *\*\ - FDCAN_RX_BUFFER7 + *\*\ - FDCAN_RX_BUFFER8 + *\*\ - FDCAN_RX_BUFFER9 + *\*\ - FDCAN_RX_BUFFER10 + *\*\ - FDCAN_RX_BUFFER11 + *\*\ - FDCAN_RX_BUFFER12 + *\*\ - FDCAN_RX_BUFFER13 + *\*\ - FDCAN_RX_BUFFER14 + *\*\ - FDCAN_RX_BUFFER15 + *\*\ - FDCAN_RX_BUFFER16 + *\*\ - FDCAN_RX_BUFFER17 + *\*\ - FDCAN_RX_BUFFER18 + *\*\ - FDCAN_RX_BUFFER19 + *\*\ - FDCAN_RX_BUFFER20 + *\*\ - FDCAN_RX_BUFFER21 + *\*\ - FDCAN_RX_BUFFER22 + *\*\ - FDCAN_RX_BUFFER23 + *\*\ - FDCAN_RX_BUFFER24 + *\*\ - FDCAN_RX_BUFFER25 + *\*\ - FDCAN_RX_BUFFER26 + *\*\ - FDCAN_RX_BUFFER27 + *\*\ - FDCAN_RX_BUFFER28 + *\*\ - FDCAN_RX_BUFFER29 + *\*\ - FDCAN_RX_BUFFER30 + *\*\ - FDCAN_RX_BUFFER31 + *\*\ - FDCAN_RX_BUFFER32 + *\*\ - FDCAN_RX_BUFFER33 + *\*\ - FDCAN_RX_BUFFER34 + *\*\ - FDCAN_RX_BUFFER35 + *\*\ - FDCAN_RX_BUFFER36 + *\*\ - FDCAN_RX_BUFFER37 + *\*\ - FDCAN_RX_BUFFER38 + *\*\ - FDCAN_RX_BUFFER39 + *\*\ - FDCAN_RX_BUFFER40 + *\*\ - FDCAN_RX_BUFFER41 + *\*\ - FDCAN_RX_BUFFER42 + *\*\ - FDCAN_RX_BUFFER43 + *\*\ - FDCAN_RX_BUFFER44 + *\*\ - FDCAN_RX_BUFFER45 + *\*\ - FDCAN_RX_BUFFER46 + *\*\ - FDCAN_RX_BUFFER47 + *\*\ - FDCAN_RX_BUFFER48 + *\*\ - FDCAN_RX_BUFFER49 + *\*\ - FDCAN_RX_BUFFER50 + *\*\ - FDCAN_RX_BUFFER51 + *\*\ - FDCAN_RX_BUFFER52 + *\*\ - FDCAN_RX_BUFFER53 + *\*\ - FDCAN_RX_BUFFER54 + *\*\ - FDCAN_RX_BUFFER55 + *\*\ - FDCAN_RX_BUFFER56 + *\*\ - FDCAN_RX_BUFFER57 + *\*\ - FDCAN_RX_BUFFER58 + *\*\ - FDCAN_RX_BUFFER59 + *\*\ - FDCAN_RX_BUFFER60 + *\*\ - FDCAN_RX_BUFFER61 + *\*\ - FDCAN_RX_BUFFER62 + *\*\ - FDCAN_RX_BUFFER63 + *\*\return ErrorStatus + *\*\ - ERROR : No new message on RxBufferIndex. + *\*\ - SUCCESS : New message received on RxBufferIndex. + */ +ErrorStatus FDCAN_CheckNewRxBufMsg(FDCAN_Module *FDCANx, uint32_t Index) +{ + __IO uint32_t *pReg; + uint32_t IndexBit; + + /* Get new data register point according to the Rx Buffer Index */ + if(Index < FDCAN_RX_BUFFER32) + { + pReg = &(FDCANx->NDAT1); + } + else /* FDCAN_RX_BUFFER32 <= Index <= FDCAN_RX_BUFFER63 */ + { + pReg = &(FDCANx->NDAT2); + } + + /* Check if the new data flag is set or not. */ + IndexBit = (0x1UL) << (Index & 0x1FUL); + + if(0UL == (*pReg & IndexBit)) + { + return ERROR; + } + + /* Clear the new data flag. */ + *pReg = IndexBit; + + return SUCCESS; +} + +/** + *\*\name FDCAN_CheckTxBufRequest. + *\*\fun Check if a transmission request is pending on the selected Tx buffer. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param IndexBit Rx buffer index bit. + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return Status + *\*\ - ERROR : No request pending on TxBufferIndex. + *\*\ - SUCCESS : Have request pending on RxBufferIndex. + */ +FlagStatus FDCAN_CheckTxBufRequest(FDCAN_Module *FDCANx, uint32_t IndexBit) +{ + FlagStatus status_value; + + /* Check pending transmission request on the selected buffer */ + if (0UL == (FDCANx->TXBRP & IndexBit)) + { + status_value = RESET; + } + else + { + status_value = SET; + } + + return status_value; +} + +/** + *\*\name FDCAN_CheckBufTxResult. + *\*\fun Check if a transmission is sent or not. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param IndexBit Rx buffer index bit. + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return Status + *\*\ - ERROR : Transmission is not finished or cacelled. + *\*\ - SUCCESS : Transmission is finished. + */ +FlagStatus FDCAN_CheckBufTxResult(FDCAN_Module *FDCANx, uint32_t IndexBit) +{ + FlagStatus status_value; + + /* Check pending transmission request on the selected buffer */ + if (0UL == (FDCANx->TXBTO & IndexBit)) + { + status_value = RESET; + } + else + { + status_value = SET; + } + + return status_value; +} + +/** + *\*\name FDCAN_CheckBufTxCancel. + *\*\fun Check if a transmission is cancelled. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param IndexBit Rx buffer index bit. + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return Status + *\*\ - ERROR : Transmission is not cacelled. + *\*\ - SUCCESS : Transmission is cacelled. + */ +FlagStatus FDCAN_CheckBufTxCancel(FDCAN_Module *FDCANx, uint32_t IndexBit) +{ + FlagStatus status_value; + + /* Check pending transmission request on the selected buffer */ + if (0UL == (FDCANx->TXBCF & IndexBit)) + { + status_value = RESET; + } + else + { + status_value = SET; + } + + return status_value; +} + +/** + *\*\name FDCAN_GetRxFifoFillLevel. + *\*\fun Return Rx FIFO fill level. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param RxFifo : + *\*\ - FDCAN_RX_FIFO0 + *\*\ - FDCAN_RX_FIFO1 + *\*\return Rx FIFO fill level. + */ +uint32_t FDCAN_GetRxFifoFillLevel(FDCAN_Module *FDCANx, uint32_t RxFifo) +{ + uint32_t FillLevel; + + if (RxFifo == FDCAN_RX_FIFO0) + { + FillLevel = FDCANx->RXF0S & FDCAN_RXF0S_F0FL; + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + FillLevel = FDCANx->RXF1S & FDCAN_RXF1S_F1FL; + } + + /* Return Rx FIFO fill level */ + return FillLevel; +} + +/** + *\*\name FDCAN_GetTxFifoFreeLevel. + *\*\fun Return Tx FIFO free level: number of consecutive free Tx FIFO. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return Tx FIFO free level. + */ +uint32_t FDCAN_GetTxFifoFreeLevel(FDCAN_Module *FDCANx) +{ + uint32_t FreeLevel; + + FreeLevel = FDCANx->TXFQS & FDCAN_TXFQS_TFFL; + + /* Return Tx FIFO free level */ + return FreeLevel; +} + +/** + *\*\name FDCAN_CheckRestrictedMode. + *\*\fun Check if the FDCAN peripheral entered Restricted Operation Mode. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return Status + *\*\ - FDCAN_MODE_NORMAL : Normal FDCAN operation. + *\*\ - FDCAN_MODE_RESTRICTED_OPERATION : Restricted Operation Mode active. + */ +uint32_t FDCAN_CheckRestrictedMode(FDCAN_Module *FDCANx) +{ + uint32_t OperationMode; + + /* Get Operation Mode */ + OperationMode = (FDCANx->CCCR & FDCAN_CCCR_ASM); + + return OperationMode; +} + +/** + *\*\name FDCAN_ExitRestrictedMode. + *\*\fun Exit Restricted Operation Mode. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +void FDCAN_ExitRestrictedMode(FDCAN_Module *FDCANx) +{ + /* Exit Restricted Operation mode */ + FDCANx->CCCR &= ~FDCAN_CCCR_ASM; +} + +/** + *\*\name FDCAN_ConfigIntLine. + *\*\fun Assign interrupts to either Interrupt line 0 or 1. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Int : + *\*\ - FDCAN_INT_RX_FIFO0_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO0_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO0_FULL + *\*\ - FDCAN_INT_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO1_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO1_FULL + *\*\ - FDCAN_INT_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_INT_TX_COMPLETE + *\*\ - FDCAN_INT_TX_ABORT_COMPLETE + *\*\ - FDCAN_INT_TX_FIFO_EMPTY + *\*\ - FDCAN_INT_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_INT_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_INT_TX_EVT_FIFO_FULL + *\*\ - FDCAN_INT_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_INT_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_INT_RAM_ACCESS_FAILURE + *\*\ - FDCAN_INT_TIMEOUT_OCCURRED + *\*\ - FDCAN_INT_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_INT_BITERROR_CORRECTED + *\*\ - FDCAN_INT_BITERROR_UNCORRECTED + *\*\ - FDCAN_INT_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_INT_ERROR_PASSIVE + *\*\ - FDCAN_INT_ERROR_WARNING + *\*\ - FDCAN_INT_BUS_OFF + *\*\ - FDCAN_INT_RAM_WATCHDOG + *\*\ - FDCAN_INT_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_INT_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_INT_RESERVED_ADDRESS_ACCESS + *\*\param IntLine : + *\*\ - FDCAN_INTERRUPT_LINE0 + *\*\ - FDCAN_INTERRUPT_LINE1 + *\*\return none + */ +void FDCAN_ConfigIntLine(FDCAN_Module *FDCANx, uint32_t Int, uint32_t IntLine) +{ + /* Assign list of interrupts to the selected line */ + if (IntLine == FDCAN_INTERRUPT_LINE0) + { + FDCANx->ILS &= (~Int); + } + else /* IntLine == FDCAN_INTERRUPT_LINE1 */ + { + FDCANx->ILS |= Int; + } +} + +/** + *\*\name FDCAN_EnableInt. + *\*\fun Enable the specified FDCAN interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Int : + *\*\ - FDCAN_INT_RX_FIFO0_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO0_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO0_FULL + *\*\ - FDCAN_INT_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO1_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO1_FULL + *\*\ - FDCAN_INT_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_INT_TX_COMPLETE + *\*\ - FDCAN_INT_TX_ABORT_COMPLETE + *\*\ - FDCAN_INT_TX_FIFO_EMPTY + *\*\ - FDCAN_INT_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_INT_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_INT_TX_EVT_FIFO_FULL + *\*\ - FDCAN_INT_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_INT_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_INT_RAM_ACCESS_FAILURE + *\*\ - FDCAN_INT_TIMEOUT_OCCURRED + *\*\ - FDCAN_INT_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_INT_BITERROR_CORRECTED + *\*\ - FDCAN_INT_BITERROR_UNCORRECTED + *\*\ - FDCAN_INT_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_INT_ERROR_PASSIVE + *\*\ - FDCAN_INT_ERROR_WARNING + *\*\ - FDCAN_INT_BUS_OFF + *\*\ - FDCAN_INT_RAM_WATCHDOG + *\*\ - FDCAN_INT_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_INT_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_INT_RESERVED_ADDRESS_ACCESS + *\*\return none + */ +void FDCAN_EnableInt(FDCAN_Module *FDCANx, uint32_t Int) +{ + FDCANx->IE |= Int; +} + +/** + *\*\name FDCAN_DisableInt. + *\*\fun Disable the specified FDCAN interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Int : + *\*\ - FDCAN_INT_RX_FIFO0_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO0_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO0_FULL + *\*\ - FDCAN_INT_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO1_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO1_FULL + *\*\ - FDCAN_INT_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_INT_TX_COMPLETE + *\*\ - FDCAN_INT_TX_ABORT_COMPLETE + *\*\ - FDCAN_INT_TX_FIFO_EMPTY + *\*\ - FDCAN_INT_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_INT_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_INT_TX_EVT_FIFO_FULL + *\*\ - FDCAN_INT_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_INT_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_INT_RAM_ACCESS_FAILURE + *\*\ - FDCAN_INT_TIMEOUT_OCCURRED + *\*\ - FDCAN_INT_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_INT_BITERROR_CORRECTED + *\*\ - FDCAN_INT_BITERROR_UNCORRECTED + *\*\ - FDCAN_INT_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_INT_ERROR_PASSIVE + *\*\ - FDCAN_INT_ERROR_WARNING + *\*\ - FDCAN_INT_BUS_OFF + *\*\ - FDCAN_INT_RAM_WATCHDOG + *\*\ - FDCAN_INT_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_INT_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_INT_RESERVED_ADDRESS_ACCESS + *\*\return none + */ +void FDCAN_DisableInt(FDCAN_Module *FDCANx, uint32_t Int) +{ + FDCANx->IE &= (~Int); +} + +/** + *\*\name FDCAN_GetIntFlag. + *\*\fun Check whether the specified FDCAN interrupt is set or not. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Flag : + *\*\ - FDCAN_FLAG_RESERVED_ADDRESS_ACCESS + *\*\ - FDCAN_FLAG_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_FLAG_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_FLAG_RAM_WATCHDOG + *\*\ - FDCAN_FLAG_BUS_OFF + *\*\ - FDCAN_FLAG_ERROR_WARNING + *\*\ - FDCAN_FLAG_ERROR_PASSIVE + *\*\ - FDCAN_FLAG_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_FLAG_BITERROR_UNCORRECTED + *\*\ - FDCAN_FLAG_BITERROR_CORRECTED + *\*\ - FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_FLAG_TIMEOUT_OCCURRED + *\*\ - FDCAN_FLAG_RAM_ACCESS_FAILURE + *\*\ - FDCAN_FLAG_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_FULL + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_FLAG_TX_FIFO_EMPTY + *\*\ - FDCAN_FLAG_TX_ABORT_COMPLETE + *\*\ - FDCAN_FLAG_TX_COMPLETE + *\*\ - FDCAN_FLAG_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_FLAG_RX_FIFO1_FULL + *\*\ - FDCAN_FLAG_RX_FIFO1_WATERMARK + *\*\ - FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_FLAG_RX_FIFO0_FULL + *\*\ - FDCAN_FLAG_RX_FIFO0_WATERMARK + *\*\ - FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE + *\*\return FlagStatus + *\*\ - RESET + *\*\ - SET + */ +FlagStatus FDCAN_GetIntFlag(FDCAN_Module *FDCANx, uint32_t Flag) +{ + FlagStatus status_value = SET; + + /* Check whether the specified FDCAN interrupt is enable or not. */ + if((FDCANx->IE & Flag) != Flag ) + { + status_value = RESET; + } + + /* Check whether the specified FDCAN interrupt flag is set or not. */ + if((FDCANx->IR & Flag) != Flag ) + { + status_value = RESET; + } + + return status_value; +} + +/** + *\*\name FDCAN_GetFlag. + *\*\fun Check whether the specified FDCAN flag is set or not. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Flag : + *\*\ - FDCAN_FLAG_RESERVED_ADDRESS_ACCESS + *\*\ - FDCAN_FLAG_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_FLAG_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_FLAG_RAM_WATCHDOG + *\*\ - FDCAN_FLAG_BUS_OFF + *\*\ - FDCAN_FLAG_ERROR_WARNING + *\*\ - FDCAN_FLAG_ERROR_PASSIVE + *\*\ - FDCAN_FLAG_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_FLAG_BITERROR_UNCORRECTED + *\*\ - FDCAN_FLAG_BITERROR_CORRECTED + *\*\ - FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_FLAG_TIMEOUT_OCCURRED + *\*\ - FDCAN_FLAG_RAM_ACCESS_FAILURE + *\*\ - FDCAN_FLAG_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_FULL + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_FLAG_TX_FIFO_EMPTY + *\*\ - FDCAN_FLAG_TX_ABORT_COMPLETE + *\*\ - FDCAN_FLAG_TX_COMPLETE + *\*\ - FDCAN_FLAG_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_FLAG_RX_FIFO1_FULL + *\*\ - FDCAN_FLAG_RX_FIFO1_WATERMARK + *\*\ - FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_FLAG_RX_FIFO0_FULL + *\*\ - FDCAN_FLAG_RX_FIFO0_WATERMARK + *\*\ - FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE + *\*\return FlagStatus + *\*\ - RESET + *\*\ - SET + */ +FlagStatus FDCAN_GetFlag(FDCAN_Module *FDCANx, uint32_t Flag) +{ + FlagStatus status_value; + + if((FDCANx->IR & Flag) == Flag ) + { + status_value = SET; + } + else + { + status_value = RESET; + } + + return status_value; +} + +/** + *\*\name FDCAN_ClearFlag. + *\*\fun Clear the specified FDCAN flags. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Flag : + *\*\ - FDCAN_FLAG_RESERVED_ADDRESS_ACCESS + *\*\ - FDCAN_FLAG_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_FLAG_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_FLAG_RAM_WATCHDOG + *\*\ - FDCAN_FLAG_BUS_OFF + *\*\ - FDCAN_FLAG_ERROR_WARNING + *\*\ - FDCAN_FLAG_ERROR_PASSIVE + *\*\ - FDCAN_FLAG_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_FLAG_BITERROR_UNCORRECTED + *\*\ - FDCAN_FLAG_BITERROR_CORRECTED + *\*\ - FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_FLAG_TIMEOUT_OCCURRED + *\*\ - FDCAN_FLAG_RAM_ACCESS_FAILURE + *\*\ - FDCAN_FLAG_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_FULL + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_FLAG_TX_FIFO_EMPTY + *\*\ - FDCAN_FLAG_TX_ABORT_COMPLETE + *\*\ - FDCAN_FLAG_TX_COMPLETE + *\*\ - FDCAN_FLAG_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_FLAG_RX_FIFO1_FULL + *\*\ - FDCAN_FLAG_RX_FIFO1_WATERMARK + *\*\ - FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_FLAG_RX_FIFO0_FULL + *\*\ - FDCAN_FLAG_RX_FIFO0_WATERMARK + *\*\ - FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE + *\*\return none + */ +void FDCAN_ClearFlag(FDCAN_Module *FDCANx, uint32_t Flag) +{ + FDCANx->IR = Flag; +} + +/** + *\*\name FDCAN_ActivateInt. + *\*\fun Activate the specified FDCAN interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Int : + *\*\ - FDCAN_INT_RX_FIFO0_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO0_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO0_FULL + *\*\ - FDCAN_INT_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO1_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO1_FULL + *\*\ - FDCAN_INT_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_INT_TX_COMPLETE + *\*\ - FDCAN_INT_TX_ABORT_COMPLETE + *\*\ - FDCAN_INT_TX_FIFO_EMPTY + *\*\ - FDCAN_INT_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_INT_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_INT_TX_EVT_FIFO_FULL + *\*\ - FDCAN_INT_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_INT_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_INT_RAM_ACCESS_FAILURE + *\*\ - FDCAN_INT_TIMEOUT_OCCURRED + *\*\ - FDCAN_INT_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_INT_BITERROR_CORRECTED + *\*\ - FDCAN_INT_BITERROR_UNCORRECTED + *\*\ - FDCAN_INT_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_INT_ERROR_PASSIVE + *\*\ - FDCAN_INT_ERROR_WARNING + *\*\ - FDCAN_INT_BUS_OFF + *\*\ - FDCAN_INT_RAM_WATCHDOG + *\*\ - FDCAN_INT_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_INT_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_INT_RESERVED_ADDRESS_ACCESS + *\*\param BufferIndexes : + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_ActivateInt(FDCAN_Module *FDCANx, uint32_t Int, uint32_t BufferIndexes) +{ + /* Check ActiveITs */ + if((Int & FDCAN_INT_MASK) == 0UL) + { + return ERROR; + } + + /* Enable Interrupt lines */ + if ((Int & FDCANx->ILS) == 0UL) + { + /* Enable Interrupt line 0 */ + FDCANx->ILE |= FDCAN_INTERRUPT_LINE0; + } + else if ((Int & FDCANx->ILS) == Int) + { + /* Enable Interrupt line 1 */ + FDCANx->ILE |= FDCAN_INTERRUPT_LINE1; + } + else + { + /* Enable Interrupt lines 0 and 1 */ + FDCANx->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); + } + + if ((Int & FDCAN_INT_TX_COMPLETE) != 0U) + { + /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, + but interrupt will only occur if TC is enabled in IE register */ + FDCANx->TXBTIE |= BufferIndexes; + } + + if ((Int & FDCAN_INT_TX_ABORT_COMPLETE) != 0U) + { + /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, + but interrupt will only occur if TCF is enabled in IE register */ + FDCANx->TXBCIE |= BufferIndexes; + } + + /* Enable the selected interrupts */ + FDCAN_EnableInt(FDCANx, Int); + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_DeactivateInt. + *\*\fun Deactivate the specified FDCAN interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Int : + *\*\ - FDCAN_INT_RX_FIFO0_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO0_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO0_FULL + *\*\ - FDCAN_INT_RX_FIFO0_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_FIFO1_NEW_MESSAGE + *\*\ - FDCAN_INT_RX_FIFO1_WATERMARK + *\*\ - FDCAN_INT_RX_FIFO1_FULL + *\*\ - FDCAN_INT_RX_FIFO1_MESSAGE_LOST + *\*\ - FDCAN_INT_RX_HIGH_PRIORITY_MSG + *\*\ - FDCAN_INT_TX_COMPLETE + *\*\ - FDCAN_INT_TX_ABORT_COMPLETE + *\*\ - FDCAN_INT_TX_FIFO_EMPTY + *\*\ - FDCAN_INT_TX_EVT_FIFO_NEW_DATA + *\*\ - FDCAN_INT_TX_EVT_FIFO_WATERMARK + *\*\ - FDCAN_INT_TX_EVT_FIFO_FULL + *\*\ - FDCAN_INT_TX_EVT_FIFO_ELT_LOST + *\*\ - FDCAN_INT_TIMESTAMP_WRAPAROUND + *\*\ - FDCAN_INT_RAM_ACCESS_FAILURE + *\*\ - FDCAN_INT_TIMEOUT_OCCURRED + *\*\ - FDCAN_INT_RX_BUFFER_NEW_MESSAGE + *\*\ - FDCAN_INT_BITERROR_CORRECTED + *\*\ - FDCAN_INT_BITERROR_UNCORRECTED + *\*\ - FDCAN_INT_ERROR_LOGGING_OVERFLOW + *\*\ - FDCAN_INT_ERROR_PASSIVE + *\*\ - FDCAN_INT_ERROR_WARNING + *\*\ - FDCAN_INT_BUS_OFF + *\*\ - FDCAN_INT_RAM_WATCHDOG + *\*\ - FDCAN_INT_ARB_PROTOCOL_ERROR + *\*\ - FDCAN_INT_DATA_PROTOCOL_ERROR + *\*\ - FDCAN_INT_RESERVED_ADDRESS_ACCESS + *\*\return none + */ +void FDCAN_DeactivateInt(FDCAN_Module *FDCANx, uint32_t Int) +{ + uint32_t IntLine; + uint32_t tempReg; + + /* Disable the selected interrupts */ + FDCAN_DisableInt(FDCANx, Int); + + if ((Int & FDCAN_INT_TX_COMPLETE) != 0U) + { + /* Disable Tx Buffer Transmission Interrupts */ + FDCANx->TXBTIE = 0; + } + + if ((Int & FDCAN_INT_TX_ABORT_COMPLETE) != 0U) + { + /* Disable Tx Buffer Cancellation Finished Interrupt */ + FDCANx->TXBCIE = 0; + } + + IntLine = FDCANx->ILS; + tempReg = FDCANx->ILE; + + if ((FDCANx->IE | IntLine) == IntLine) + { + /* Disable Interrupt line 0 */ + tempReg &= (~FDCAN_INTERRUPT_LINE0); + } + + if ((FDCANx->IE & IntLine) == 0U) + { + /* Disable Interrupt line 1 */ + tempReg &= (~FDCAN_INTERRUPT_LINE1); + } + + FDCANx->ILE = tempReg; +} + + + +/** + *\*\name FDCAN_TT_Init. + *\*\fun Initialize TT operation parameters. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param pTTParams pointer to a FDCAN_TT_InitType structure. + *\*\ - uint32_t OperationMode + *\*\ - FDCAN_TT_COMMUNICATION_LEVEL1 + *\*\ - FDCAN_TT_COMMUNICATION_LEVEL2 + *\*\ - FDCAN_TT_COMMUNICATION_LEVEL0 + *\*\ - uint32_t GapEnable + *\*\ - FDCAN_STRICTLY_TT_OPERATION + *\*\ - FDCAN_EXT_EVT_SYNC_TT_OPERATION + *\*\ - uint32_t TimeMaster + *\*\ - FDCAN_TT_SLAVE + *\*\ - FDCAN_TT_POTENTIAL_MASTER + *\*\ - uint32_t SyncDevLimit + *\*\ This parameter must be a value between 0 and 7 + *\*\ - uint32_t InitRefTrigOffset + *\*\ This parameter must be a value between 0 and 127 + *\*\ - uint32_t ExternalClkSync + *\*\ - FDCAN_TT_EXT_CLK_SYNC_DISABLE + *\*\ - FDCAN_TT_EXT_CLK_SYNC_ENABLE + *\*\ This parameter is ignored if OperationMode is FDCAN_TT_COMMUNICATION_LEVEL1 + *\*\ - uint32_t AppWdgLimit + *\*\ This parameter must be a value between 0 and 255. + *\*\ This parameter is ignored if OperationMode is FDCAN_TT_COMMUNICATION_LEVEL0 + *\*\ - uint32_t GlobalTimeFilter + *\*\ - FDCAN_TT_GLOB_TIME_FILT_DISABLE + *\*\ - FDCAN_TT_GLOB_TIME_FILT_ENABLE + *\*\ This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1 + *\*\ - uint32_t ClockCalibration + *\*\ - FDCAN_TT_AUTO_CLK_CALIB_DISABLE + *\*\ - FDCAN_TT_AUTO_CLK_CALIB_ENABLE + *\*\ This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL1 + *\*\ - uint32_t EvtTrigPolarity + *\*\ - FDCAN_TT_EVT_TRIG_POL_RISING + *\*\ - FDCAN_TT_EVT_TRIG_POL_FALLING + *\*\ This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0 + *\*\ - uint32_t BasicCycles + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_1 + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_2 + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_4 + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_8 + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_16 + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_32 + *\*\ - FDCAN_TT_CYCLES_PER_MATRIX_64 + *\*\ - uint32_t CycleStartSync + *\*\ - FDCAN_TT_NO_SYNC_PULSE + *\*\ - FDCAN_TT_SYNC_BASIC_CYCLE_START + *\*\ - FDCAN_TT_SYNC_MATRIX_START + *\*\ - uint32_t TxEnableWindow + *\*\ This parameter must be a value between 1 and 16 + *\*\ - uint32_t ExpTxTrigSize + *\*\ This parameter must be a value between 0 and 4095 + *\*\ - uint32_t TURNumerator + *\*\ This parameter must be a value between 0x10000 and 0x1FFFF + *\*\ - uint32_t TURDenominator + *\*\ This parameter must be a value between 0x0001 and 0x3FFF + *\*\ - uint32_t TrigMemorySize + *\*\ This parameter must be a value between 0 and 64 + *\*\ - uint32_t StopWatchTrigSel + *\*\ - FDCAN_TT_STOP_WATCH_TRIGGER_0 + *\*\ - FDCAN_TT_STOP_WATCH_TRIGGER_1 + *\*\ - FDCAN_TT_STOP_WATCH_TRIGGER_2 + *\*\ - FDCAN_TT_STOP_WATCH_TRIGGER_3 + *\*\ - uint32_t EventTrigSel + *\*\ - FDCAN_TT_EVENT_TRIGGER_0 + *\*\ - FDCAN_TT_EVENT_TRIGGER_1 + *\*\ - FDCAN_TT_EVENT_TRIGGER_2 + *\*\ - FDCAN_TT_EVENT_TRIGGER_3 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_Init(FDCAN_Module *FDCANx, FDCAN_TT_InitType *pTTParams) +{ + uint32_t RAMcounter; + uint32_t OffsetAddress; + uint32_t StartAddress; + uint32_t timeout; + uint32_t tempReg; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Stop local time in order to enable write access to the other bits of TURCF register */ + FDCANx->TURCF &= ~FDCAN_TURCF_ELT; + + /* Wait until the ELT bit into TURCF register is reset */ + timeout = 0; + + while ((FDCANx->TURCF & FDCAN_TURCF_ELT) != 0U) + { + if (timeout > FDCAN_TIMEOUT_VALUE) + { + return ERROR; + } + + timeout++; + } + + /* Configure TUR (Time Unit Ratio) */ + FDCANx->TURCF = (pTTParams->TURNumerator - 0x10000UL) \ + | (pTTParams->TURDenominator << FDCAN_TURCF_DC_OFFSET); + + /* Enable local time */ + FDCANx->TURCF |= FDCAN_TURCF_ELT; + + /* Configure TT operation */ + tempReg = (pTTParams->OperationMode) \ + | (pTTParams->TimeMaster) \ + | (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_OFFSET) \ + | (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_OFFSET); + + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + tempReg |= (pTTParams->GapEnable) \ + | (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_OFFSET) \ + | (pTTParams->EvtTrigPolarity); + } + + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1) + { + tempReg |= (pTTParams->ExternalClkSync) \ + | (pTTParams->GlobalTimeFilter) \ + | (pTTParams->ClockCalibration); + } + + FDCANx->TTOCF = tempReg; + + /* Configure system matrix limits */ + tempReg = pTTParams->CycleStartSync; + + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + tempReg |= ((pTTParams->TxEnableWindow - 1UL) << FDCAN_TTMLM_TXEW_OFFSET); + tempReg |= (pTTParams->ExpTxTrigSize << FDCAN_TTMLM_ENIT_OFFSET); + } + + if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER) + { + tempReg |= pTTParams->BasicCycles; + } + + FDCANx->TTMLM = tempReg; + + /* Configure input triggers: Stop watch and Event */ + tempReg = FDCANx->TTSS; + tempReg &= (~(FDCAN_TTSS_SSWT | FDCAN_TTSS_SEVT)); + tempReg |= (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel); + FDCANx->TTSS = tempReg; + + /* Configure trigger memory start address and elements number */ + if((FDCANx->TTSS & FDCAN_START_ADDRESS_RAMSEL) == FDCAN_START_ADDRESS_RAMSEL) + { + OffsetAddress = (pMsg->EndAddress - FDCAN_START_ADDRESS_SRAM5BANK2) / 4UL; + StartAddress = FDCAN_START_ADDRESS_SRAM5BANK2; + } + else + { + OffsetAddress = (pMsg->EndAddress - FDCAN_START_ADDRESS_SRAM5BANK1) / 4UL; + StartAddress = FDCAN_START_ADDRESS_SRAM5BANK1; + } + + FDCANx->TTTMC = (OffsetAddress << FDCAN_START_ADDRESS_OFFSET) | \ + (pTTParams->TrigMemorySize << FDCAN_SIZE_NUMBER_OFFSET); + + /* Recalculate End Address */ + pMsg->TTMemoryStrAddr = pMsg->EndAddress; + pMsg->EndAddress += (pTTParams->TrigMemorySize * FDCAN_TT_MEMORY_WORDS * 4UL); + + /* Check end address of the Message RAM */ + if (pMsg->EndAddress > (StartAddress + FDCAN_MESSAGE_RAM_SIZE) ) + { + return ERROR; + } + + /* Flush the allocated Message RAM area */ + for (RAMcounter = pMsg->TTMemoryStrAddr; RAMcounter < pMsg->EndAddress; RAMcounter += 4UL) + { + *(uint32_t *)(RAMcounter) = 0UL; + } + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_ConfigRefMsg. + *\*\fun Configure the reference message. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param IdType : + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\param ID Reference Identifier. + *\*\ This parameter must be a number between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\param Payload Enable or disable the additional payload. + *\*\ - FDCAN_TT_REF_MSG_NO_PAYLOAD + *\*\ - FDCAN_TT_REF_MSG_ADD_PAYLOAD + *\*\return none + */ +void FDCAN_TT_ConfigRefMsg(FDCAN_Module *FDCANx, uint32_t IdType, uint32_t ID, uint32_t Payload) +{ + uint32_t id_temp; + uint32_t tempReg; + + /* Configure reference message identifier type, identifier and payload */ + if (IdType == FDCAN_STANDARD_ID) + { + id_temp = ID << FDCAN_TTRMC_STD_ID_OFFSET; + } + else + { + id_temp = ID; + } + + tempReg = FDCANx->TTRMC & (~(FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS)); + tempReg |= (id_temp | IdType | Payload); + FDCANx->TTRMC = tempReg; +} + +/** + *\*\name FDCAN_TT_ConfigTrigger. + *\*\fun Configure the FDCAN trigger according to the specified parameters + *\*\ in the FDCAN_TriggerType structure. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param sTriggerConfig :pointer to an FDCAN_TriggerType structure + *\*\ - TriggerIndex + *\*\ This parameter must be a number between 0 and 63 + *\*\ - TimeMark + *\*\ This parameter must be a number between 0 and 0xFFFF + *\*\ - RepeatFactor + *\*\ - FDCAN_TT_REPEAT_EVERY_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_2ND_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_4TH_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_8TH_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_16TH_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_32ND_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_64TH_CYCLE + *\*\ - StartCycle + *\*\ This parameter must be a value between 0 and RepeatFactor. + *\*\ This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + *\*\ - TmEventInt + *\*\ - FDCAN_TT_TM_NO_INTERNAL_EVENT + *\*\ - FDCAN_TT_TM_GEN_INTERNAL_EVENT + *\*\ - TmEventExt + *\*\ - FDCAN_TT_TM_NO_EXTERNAL_EVENT + *\*\ - FDCAN_TT_TM_GEN_EXTERNAL_EVENT + *\*\ - TriggerType; + *\*\ - FDCAN_TT_TX_REF_TRIGGER + *\*\ - FDCAN_TT_TX_REF_TRIGGER_GAP + *\*\ - FDCAN_TT_TX_TRIGGER_SINGLE + *\*\ - FDCAN_TT_TX_TRIGGER_CONTINUOUS + *\*\ - FDCAN_TT_TX_TRIGGER_ARBITRATION + *\*\ - FDCAN_TT_TX_TRIGGER_MERGED + *\*\ - FDCAN_TT_WATCH_TRIGGER + *\*\ - FDCAN_TT_WATCH_TRIGGER_GAP + *\*\ - FDCAN_TT_RX_TRIGGER + *\*\ - FDCAN_TT_TIME_BASE_TRIGGER + *\*\ - FDCAN_TT_END_OF_LIST + *\*\ - FilterType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - TxBufferIndex + *\*\ - FDCAN_TX_BUFFER0 + *\*\ - FDCAN_TX_BUFFER1 + *\*\ - FDCAN_TX_BUFFER2 + *\*\ - FDCAN_TX_BUFFER3 + *\*\ - FDCAN_TX_BUFFER4 + *\*\ - FDCAN_TX_BUFFER5 + *\*\ - FDCAN_TX_BUFFER6 + *\*\ - FDCAN_TX_BUFFER7 + *\*\ - FDCAN_TX_BUFFER8 + *\*\ - FDCAN_TX_BUFFER9 + *\*\ - FDCAN_TX_BUFFER10 + *\*\ - FDCAN_TX_BUFFER11 + *\*\ - FDCAN_TX_BUFFER12 + *\*\ - FDCAN_TX_BUFFER13 + *\*\ - FDCAN_TX_BUFFER14 + *\*\ - FDCAN_TX_BUFFER15 + *\*\ - FDCAN_TX_BUFFER16 + *\*\ - FDCAN_TX_BUFFER17 + *\*\ - FDCAN_TX_BUFFER18 + *\*\ - FDCAN_TX_BUFFER19 + *\*\ - FDCAN_TX_BUFFER20 + *\*\ - FDCAN_TX_BUFFER21 + *\*\ - FDCAN_TX_BUFFER22 + *\*\ - FDCAN_TX_BUFFER23 + *\*\ - FDCAN_TX_BUFFER24 + *\*\ - FDCAN_TX_BUFFER25 + *\*\ - FDCAN_TX_BUFFER26 + *\*\ - FDCAN_TX_BUFFER27 + *\*\ - FDCAN_TX_BUFFER28 + *\*\ - FDCAN_TX_BUFFER29 + *\*\ - FDCAN_TX_BUFFER30 + *\*\ - FDCAN_TX_BUFFER31 + *\*\ - FilterIndex + *\*\ This parameter must be a number between: + *\*\ - 0 and 127, if FilterType is FDCAN_STANDARD_ID + *\*\ - 0 and 63, if FilterType is FDCAN_EXTENDED_ID + *\*\return none + */ +void FDCAN_TT_ConfigTrigger(FDCAN_Module *FDCANx, FDCAN_TriggerType *sTriggerConfig) +{ + uint32_t CycleCode; + uint32_t MsgNumber; + uint32_t *TriggerAddress; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Calculate trigger address */ + TriggerAddress = (uint32_t *)(pMsg->TTMemoryStrAddr + (sTriggerConfig->TriggerIndex * FDCAN_TT_MEMORY_WORDS * 4UL)); + + /* Calculate cycle code */ + if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE) + { + CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE; + } + else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */ + { + CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle; + } + + /* Write first word of trigger element to the message RAM */ + *TriggerAddress = ( (sTriggerConfig->TimeMark << FDCAN_ELEMENT_TM_OFFSET) \ + | (CycleCode << FDCAN_ELEMENT_CC_OFFSET) \ + | (sTriggerConfig->TmEventInt ) \ + | (sTriggerConfig->TmEventExt ) \ + | (sTriggerConfig->TriggerType) ); + + /* Increment TriggerAddress pointer to second word of trigger element */ + TriggerAddress++; + + /* Select message number depending on trigger type (transmission or reception) */ + if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER) + { + MsgNumber = sTriggerConfig->FilterIndex; + } + else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED)) + { + MsgNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex); + } + else + { + MsgNumber = 0; + } + + /* Write second word of trigger element to the message RAM */ + *TriggerAddress = (sTriggerConfig->FilterType >> 7U) | (MsgNumber << FDCAN_ELEMENT_MNR_OFFSET); +} + +/** + *\*\name FDCAN_TT_WaitLCKCReset. + *\*\fun Wait until the LCKC bit into TTOCN register is reset. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\return ErrorStatus + *\*\ - SUCCESS: Register is unlock + *\*\ - ERROR : Register is locked + */ +static ErrorStatus FDCAN_TT_WaitLCKCReset(FDCAN_Module *FDCANx) +{ + uint32_t timeout; + + /* Wait until the LCKC bit into TTOCN register is reset */ + timeout = 0; + + while ((FDCANx->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (timeout > FDCAN_TIMEOUT_COUNT) + { + return ERROR; + } + + timeout++; + } + + return SUCCESS; +} + + +/** + *\*\name FDCAN_TT_SetGlobalTime. + *\*\fun Schedule global time adjustment for the next reference message. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TimePreset :time preset value. + *\*\ This parameter must be a number between: + *\*\ - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset + *\*\ or + *\*\ - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset) + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_SetGlobalTime(FDCAN_Module *FDCANx, uint32_t TimePreset) +{ + uint32_t tempReg; + + /* Check that the external clock synchronization is enabled */ + if ((FDCANx->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS) + { + return ERROR; + } + + /* Check that no global time preset is pending */ + if ((FDCANx->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD) + { + return ERROR; + } + + /* Configure time preset */ + tempReg = FDCANx->TTGTP & (~(FDCAN_TTGTP_TP)); + tempReg |= TimePreset; + FDCANx->TTGTP = tempReg; + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Schedule time preset to take effect by the next reference message */ + FDCANx->TTOCN |= FDCAN_TTOCN_SGT; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_SetClockSync. + *\*\fun Schedule TUR numerator update for the next reference message. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param NewTURNumerator :new value of the TUR numerator. + *\*\ This parameter must be a number between 0x10000 and 0x1FFFF. + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_SetClockSync(FDCAN_Module *FDCANx, uint32_t NewTURNumerator) +{ + uint32_t tempReg; + + /* Check that the external clock synchronization is enabled */ + if ((FDCANx->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS) + { + return ERROR; + } + + /* Check that no external clock synchronization is pending */ + if ((FDCANx->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS) + { + return ERROR; + } + + /* Configure new TUR numerator */ + tempReg = FDCANx->TURCF & (~FDCAN_TURCF_NCL); + tempReg |= (NewTURNumerator - 0x10000UL); + FDCANx->TURCF = tempReg; + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Schedule TUR numerator update by the next reference message */ + FDCANx->TTOCN |= FDCAN_TTOCN_ECS; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_ConfigStopWatch. + *\*\fun Configure stop watch source and polarity. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param Source : + *\*\ - FDCAN_TT_STOP_WATCH_DISABLED + *\*\ - FDCAN_TT_STOP_WATCH_CYCLE_TIME + *\*\ - FDCAN_TT_STOP_WATCH_LOCAL_TIME + *\*\ - FDCAN_TT_STOP_WATCH_GLOBAL_TIME + *\*\param Polarity : + *\*\ - FDCAN_TT_STOP_WATCH_RISING + *\*\ - FDCAN_TT_STOP_WATCH_FALLING + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_ConfigStopWatch(FDCAN_Module *FDCANx, uint32_t Source, uint32_t Polarity) +{ + uint32_t tempReg; + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Select stop watch source and polarity */ + tempReg = FDCANx->TTOCN & (~(FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP)); + tempReg |= (Source | Polarity); + FDCANx->TTOCN = tempReg; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_ConfigRegTimeMark. + *\*\fun Configure register time mark pulse generation. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TimeMarkSource : + *\*\ - FDCAN_TT_REG_TIMEMARK_DIABLED + *\*\ - FDCAN_TT_REG_TIMEMARK_CYCLE_TIME + *\*\ - FDCAN_TT_REG_TIMEMARK_LOCAL_TIME + *\*\ - FDCAN_TT_REG_TIMEMARK_GLOBAL_TIME + *\*\param TimeMarkValue :time mark value (reference). + *\*\ This parameter must be a number between 0 and 0xFFFF. + *\*\param RepeatFactor : + *\*\ - FDCAN_TT_REPEAT_EVERY_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_2ND_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_4TH_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_8TH_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_16TH_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_32ND_CYCLE + *\*\ - FDCAN_TT_REPEAT_EVERY_64TH_CYCLE + *\*\param StartCycle :index of the first cycle in which the time mark becomes valid. + *\*\ This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + *\*\ This parameter must be a number between 0 and RepeatFactor. + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_ConfigRegTimeMark(FDCAN_Module *FDCANx, + uint32_t TimeMarkSource, uint32_t TimeMarkValue, + uint32_t RepeatFactor, uint32_t StartCycle) +{ + uint32_t timeout; + uint32_t tempReg; + uint32_t CycleCode; + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Disable the time mark compare function */ + FDCANx->TTOCN &= ~FDCAN_TTOCN_TMC; + + if (TimeMarkSource == FDCAN_TT_REG_TIMEMARK_DIABLED) + { + return SUCCESS; + } + + /* Calculate cycle code */ + if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE) + { + CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE; + } + else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */ + { + CycleCode = RepeatFactor + StartCycle; + } + + /* Wait until the LCKM bit into TTTMK register is reset */ + timeout = 0; + + while ((FDCANx->TTTMK & FDCAN_TTTMK_LCKM) != 0U) + { + /* Check for the Timeout */ + if (timeout > FDCAN_TIMEOUT_COUNT) + { + return ERROR; + } + + timeout++; + } + + /* Configure time mark value and cycle code */ + FDCANx->TTTMK = ((TimeMarkValue) | (CycleCode << FDCAN_TTTMK_TICC_OFFSET)); + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Update the register time mark compare source */ + tempReg = FDCANx->TTOCN & (~FDCAN_TTOCN_TMC); + tempReg |= TimeMarkSource; + FDCANx->TTOCN = tempReg; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_EnableRegTMPulse. + *\*\fun Enables or disables register time mark pulse generation. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_EnableRegTMPulse(FDCAN_Module *FDCANx, FunctionalState Cmd) +{ + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + if(Cmd == ENABLE) + { + /* Enable Register Time Mark Interrupt output on fdcan_rtp */ + FDCANx->TTOCN |= FDCAN_TTOCN_RTIE; + } + else + { + /* Disable Register Time Mark Interrupt output on fdcan_rtp */ + FDCANx->TTOCN &= (~FDCAN_TTOCN_RTIE); + } + + + /* Return function status */ + return SUCCESS; +} + + +/** + *\*\name FDCAN_TT_EnableTrigTMPulse. + *\*\fun Enables or disables trigger time mark pulse generation. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_EnableTrigTMPulse(FDCAN_Module *FDCANx, FunctionalState Cmd) +{ + if ((FDCANx->TTOCF & FDCAN_TTOCF_OM) == FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Feature not supported for TT Level 0 */ + return ERROR; + } + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + if(Cmd == ENABLE) + { + /* Enable Trigger Time Mark Interrupt output on fdcan_tmp */ + FDCANx->TTOCN |= FDCAN_TTOCN_TTIE; + } + else + { + /* Disable Trigger Time Mark Interrupt output on fdcan_rtp */ + FDCANx->TTOCN &= (~FDCAN_TTOCN_TTIE); + } + + /* Return function status */ + return SUCCESS; +} + + +/** + *\*\name FDCAN_TT_EnableGapPinCtrl. + *\*\fun Enables or disables gap control by input pin fdcan_evt. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_EnableGapPinCtrl(FDCAN_Module *FDCANx, FunctionalState Cmd) +{ + if ((FDCANx->TTOCF & FDCAN_TTOCF_OM) == FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Feature not supported for TT Level 0 */ + return ERROR; + } + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + if(Cmd == ENABLE) + { + /* Enable gap control by pin fdcan_evt */ + FDCANx->TTOCN |= FDCAN_TTOCN_GCS; + } + else + { + /* Disable gap control by pin fdcan_evt */ + FDCANx->TTOCN &= (~FDCAN_TTOCN_GCS); + } + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_EnableTMGapCtrl. + *\*\fun Enables or disables gap control (finish only) by register time mark interrupt. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_EnableTMGapCtrl(FDCAN_Module *FDCANx, FunctionalState Cmd) +{ + if ((FDCANx->TTOCF & FDCAN_TTOCF_OM) == FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Feature not supported for TT Level 0 */ + return ERROR; + } + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + if(Cmd == ENABLE) + { + /* Enable gap control by register time mark interrupt */ + FDCANx->TTOCN |= FDCAN_TTOCN_TMG; + } + else + { + /* Disable gap control by register time mark interrupt */ + FDCANx->TTOCN &= (~FDCAN_TTOCN_TMG); + } + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_SetNextIsGap. + *\*\fun Transmit next reference message with Next_is_Gap = "1". + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_SetNextIsGap(FDCAN_Module *FDCANx) +{ + /* Check that the node is configured for external event-synchronized TT operation */ + if ((FDCANx->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN) + { + return ERROR; + } + + if ((FDCANx->TTOCF & FDCAN_TTOCF_OM) == FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Feature not supported for TT Level 0 */ + return ERROR; + } + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Set Next is Gap */ + FDCANx->TTOCN |= FDCAN_TTOCN_NIG; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_SetEndOfGap. + *\*\fun Finish a Gap by requesting start of reference message. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_SetEndOfGap(FDCAN_Module *FDCANx) +{ + /* Check that the node is configured for external event-synchronized TT operation */ + if ((FDCANx->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN) + { + return ERROR; + } + + if ((FDCANx->TTOCF & FDCAN_TTOCF_OM) == FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Feature not supported for TT Level 0 */ + return ERROR; + } + + + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + /* Set Finish Gap */ + FDCANx->TTOCN |= FDCAN_TTOCN_FGP; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_ConfigExtSyncPhase. + *\*\fun Configure target phase used for external synchronization by event + *\*\ trigger input pin. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TargetPhase :defines target value of cycle time when a rising edge + *\*\ of fdcan_evt is expected. + *\*\ This parameter must be a number between 0 and 0xFFFF. + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_ConfigExtSyncPhase(FDCAN_Module *FDCANx, uint32_t TargetPhase) +{ + uint32_t tempReg; + + /* Check that no external schedule synchronization is pending */ + if ((FDCANx->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN) + { + return ERROR; + } + + /* Configure cycle time target phase */ + tempReg = FDCANx->TTGTP & (~FDCAN_TTGTP_CTP); + tempReg |= TargetPhase << FDCAN_TTGTP_CTP_OFFSET; + FDCANx->TTGTP = tempReg; + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_EnableExtSync. + *\*\fun Enable or disable external schedule synchronization. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_EnableExtSync(FDCAN_Module *FDCANx, FunctionalState Cmd) +{ + /* Wait until the LCKC bit into TTOCN register is reset */ + if(FDCAN_TT_WaitLCKCReset(FDCANx) != SUCCESS) + { + return ERROR; + } + + if(Cmd == ENABLE) + { + /* Enable external synchronization */ + FDCANx->TTOCN |= FDCAN_TTOCN_ESCN; + } + else + { + /* Disable external synchronization */ + FDCANx->TTOCN &= (~FDCAN_TTOCN_ESCN); + } + + /* Return function status */ + return SUCCESS; +} + + +/** + *\*\name FDCAN_TT_GetStatus. + *\*\fun Get TT operation status. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TTStatus pointer to an FDCAN_TT_Status structure. + *\*\ - ErrorLevel + *\*\ - FDCAN_TT_NO_ERROR + *\*\ - FDCAN_TT_WARNING + *\*\ - FDCAN_TT_ERROR + *\*\ - FDCAN_TT_SEVERE_ERROR + *\*\ - MasterState + *\*\ - FDCAN_TT_MASTER_OFF + *\*\ - FDCAN_TT_TIME_SLAVE + *\*\ - FDCAN_TT_BACKUP_TIME_MASTER + *\*\ - FDCAN_TT_CURRENT_TIME_MASTER + *\*\ - SyncState + *\*\ - FDCAN_TT_OUT_OF_SYNC + *\*\ - FDCAN_TT_SYNCHRONIZING + *\*\ - FDCAN_TT_IN_GAP + *\*\ - FDCAN_TT_IN_SCHEDULE + *\*\ - GTimeQuality + *\*\ - FDCAN_TT_GTIME_NOT_VALID + *\*\ - FDCAN_TT_GTIME_IN_MASTER_PHASE + *\*\ - ClockQuality + *\*\ - FDCAN_TT_LOCAL_CLOCK_NOT_SYNC + *\*\ - FDCAN_TT_SYNC_DEV_LESS_THAN_SDL + *\*\ - RefTrigOffset + *\*\ This parameter can be a number between 0 and 0xFF + *\*\ - GTimeDiscPending + *\*\ - FDCAN_TT_NO_GTIME_PENDING + *\*\ - FDCAN_TT_WATI_GTIMESYNC_PRESENT + *\*\ - GapFinished + *\*\ - FDCAN_TT_GAP_RESET + *\*\ - FDCAN_TT_GAP_FINISHED + *\*\ - MasterPriority + *\*\ This parameter can be a number between 0 and 0x7 + *\*\ - GapStarted + *\*\ - FDCAN_TT_NO_GAP + *\*\ - FDCAN_TT_GAP_STARTED + *\*\ - WaitForEvt + *\*\ - FDCAN_TT_GAP_NOT_ANNOUNCED + *\*\ - FDCAN_TT_REF_MSG_RECEIVED + *\*\ - AppWdgEvt + *\*\ - FDCAN_TT_WATCHDOG_VALID + *\*\ - FDCAN_TT_WATCHDOG_INVALID + *\*\ - ECSPending + *\*\ - FDCAN_TT_NO_EXT_CLOCK_SYNC + *\*\ - FDCAN_TT_WAIT_EXT_CLOCK_SYNC + *\*\ - PhaseLock + *\*\ - FDCAN_TT_PHASE_OUT_OF_RANGE + *\*\ - FDCAN_TT_PHASE_IN_RANGE + *\*\return none + */ +void FDCAN_TT_GetStatus(FDCAN_Module *FDCANx, FDCAN_TT_Status *TTStatus) +{ + uint32_t tempReg; + + /* Read the TT operation status register */ + tempReg = FDCANx->TTOST; + + /* Fill the TT operation status structure */ + TTStatus->ErrorLevel = (tempReg & FDCAN_TTOST_EL); + TTStatus->MasterState = (tempReg & FDCAN_TTOST_MS); + TTStatus->SyncState = (tempReg & FDCAN_TTOST_SYS); + TTStatus->GTimeQuality = (tempReg & FDCAN_TTOST_QGTP); + TTStatus->ClockQuality = (tempReg & FDCAN_TTOST_QCS); + TTStatus->RefTrigOffset = ((tempReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_OFFSET); + TTStatus->GTimeDiscPending = (tempReg & FDCAN_TTOST_WGTD); + TTStatus->GapFinished = (tempReg & FDCAN_TTOST_GFI); + TTStatus->MasterPriority = ((tempReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_OFFSET); + TTStatus->GapStarted = (tempReg & FDCAN_TTOST_GSI); + TTStatus->WaitForEvt = (tempReg & FDCAN_TTOST_WFE); + TTStatus->AppWdgEvt = (tempReg & FDCAN_TTOST_AWE); + TTStatus->ECSPending = (tempReg & FDCAN_TTOST_WECS); + TTStatus->PhaseLock = (tempReg & FDCAN_TTOST_SPL); +} + +/** + *\*\name FDCAN_TT_ConfigIntLine. + *\*\fun Assign TT interrupts to either Interrupt line 0 or 1. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Int : + *\*\ - FDCAN_TT_INT_BASIC_CYCLE_START + *\*\ - FDCAN_TT_INT_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_INT_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_INT_START_OF_GAP + *\*\ - FDCAN_TT_INT_REG_TIME_MARK + *\*\ - FDCAN_TT_INT_TRIG_TIME_MARK + *\*\ - FDCAN_TT_INT_STOP_WATCH + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_INT_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_INT_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_INT_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_INT_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_INT_CONFIG_ERROR + *\*\param IntLine : + *\*\ - FDCAN_INTERRUPT_LINE0 + *\*\ - FDCAN_INTERRUPT_LINE1 + *\*\return none + */ +void FDCAN_TT_ConfigIntLine(FDCAN_Module *FDCANx, uint32_t TT_Int, uint32_t IntLine) +{ + /* Assign list of interrupts to the selected line */ + if (IntLine == FDCAN_INTERRUPT_LINE0) + { + FDCANx->TTILS &= (~TT_Int); + } + else /* IntLine == FDCAN_INTERRUPT_LINE1 */ + { + FDCANx->TTILS |= TT_Int; + } +} + +/** + *\*\name FDCAN_TT_EnableInt. + *\*\fun Enable or disable the specified FDCAN TT interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Int : + *\*\ - FDCAN_TT_INT_BASIC_CYCLE_START + *\*\ - FDCAN_TT_INT_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_INT_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_INT_START_OF_GAP + *\*\ - FDCAN_TT_INT_REG_TIME_MARK + *\*\ - FDCAN_TT_INT_TRIG_TIME_MARK + *\*\ - FDCAN_TT_INT_STOP_WATCH + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_INT_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_INT_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_INT_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_INT_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_INT_CONFIG_ERROR + *\*\return none + */ +void FDCAN_TT_EnableInt(FDCAN_Module *FDCANx, uint32_t TT_Int, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + FDCANx->TTIE |= TT_Int; + } + else + { + FDCANx->TTIE &= (~TT_Int); + } +} + + +/** + *\*\name FDCAN_TT_GetIntFlag. + *\*\fun Check whether the specified FDCAN TT interrupt is set or not. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Flag : + *\*\ - FDCAN_TT_FLAG_BASIC_CYCLE_START + *\*\ - FDCAN_TT_FLAG_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_FLAG_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_FLAG_START_OF_GAP + *\*\ - FDCAN_TT_FLAG_REG_TIME_MARK + *\*\ - FDCAN_TT_FLAG_TRIG_TIME_MARK + *\*\ - FDCAN_TT_FLAG_STOP_WATCH + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_FLAG_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_FLAG_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_FLAG_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_FLAG_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_FLAG_WATCH_TRIGGER + *\*\ - FDCAN_TT_FLAG_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_FLAG_CONFIG_ERROR + *\*\return FlagStatus + *\*\ - RESET + *\*\ - SET + */ +FlagStatus FDCAN_TT_GetIntFlag(FDCAN_Module *FDCANx, uint32_t TT_Flag) +{ + /* Check whether the specified FDCAN TT interrupt is enable or not. */ + if((FDCANx->TTIE & TT_Flag) != TT_Flag ) + { + return RESET; + } + + /* Check whether the specified FDCAN TT interrupt flag is set or not. */ + if((FDCANx->TTIR & TT_Flag) != TT_Flag ) + { + return RESET; + } + + return SET; +} + +/** + *\*\name FDCAN_TT_GetFlag. + *\*\fun Check whether the specified FDCAN TT flag is set or not. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Flag : + *\*\ - FDCAN_TT_FLAG_BASIC_CYCLE_START + *\*\ - FDCAN_TT_FLAG_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_FLAG_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_FLAG_START_OF_GAP + *\*\ - FDCAN_TT_FLAG_REG_TIME_MARK + *\*\ - FDCAN_TT_FLAG_TRIG_TIME_MARK + *\*\ - FDCAN_TT_FLAG_STOP_WATCH + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_FLAG_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_FLAG_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_FLAG_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_FLAG_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_FLAG_WATCH_TRIGGER + *\*\ - FDCAN_TT_FLAG_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_FLAG_CONFIG_ERROR + *\*\return FlagStatus + *\*\ - RESET + *\*\ - SET + */ +FlagStatus FDCAN_TT_GetFlag(FDCAN_Module *FDCANx, uint32_t TT_Flag) +{ + /* Check whether the specified FDCAN TT interrupt flag is set or not. */ + if((FDCANx->TTIR & TT_Flag) != TT_Flag ) + { + return RESET; + } + else + { + return SET; + } +} + +/** + *\*\name FDCAN_TT_ClearFlag. + *\*\fun Clear the specified FDCAN TT flag. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Flag : + *\*\ - FDCAN_TT_FLAG_BASIC_CYCLE_START + *\*\ - FDCAN_TT_FLAG_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_FLAG_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_FLAG_START_OF_GAP + *\*\ - FDCAN_TT_FLAG_REG_TIME_MARK + *\*\ - FDCAN_TT_FLAG_TRIG_TIME_MARK + *\*\ - FDCAN_TT_FLAG_STOP_WATCH + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_FLAG_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_FLAG_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_FLAG_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_FLAG_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_FLAG_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_FLAG_WATCH_TRIGGER + *\*\ - FDCAN_TT_FLAG_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_FLAG_CONFIG_ERROR + *\*\return none + */ +void FDCAN_TT_ClearFlag(FDCAN_Module *FDCANx, uint32_t TT_Flag) +{ + FDCANx->TTIR = TT_Flag; +} + +/** + *\*\name FDCAN_TT_ActivateInt. + *\*\fun Activate the specified FDCAN TT interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Int : + *\*\ - FDCAN_TT_INT_BASIC_CYCLE_START + *\*\ - FDCAN_TT_INT_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_INT_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_INT_START_OF_GAP + *\*\ - FDCAN_TT_INT_REG_TIME_MARK + *\*\ - FDCAN_TT_INT_TRIG_TIME_MARK + *\*\ - FDCAN_TT_INT_STOP_WATCH + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_INT_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_INT_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_INT_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_INT_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_INT_CONFIG_ERROR + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus FDCAN_TT_ActivateInt(FDCAN_Module *FDCANx, uint32_t TT_Int) +{ + /* Check ActiveITs */ + if((TT_Int & FDCAN_TT_INT_MASK) == 0UL) + { + return ERROR; + } + + /* Enable Interrupt lines */ + if ((TT_Int & FDCANx->TTILS) == 0UL) + { + /* Enable Interrupt line 0 */ + FDCANx->ILE |= FDCAN_INTERRUPT_LINE0; + } + else if ((TT_Int & FDCANx->TTILS) == TT_Int) + { + /* Enable Interrupt line 1 */ + FDCANx->ILE |= FDCAN_INTERRUPT_LINE1; + } + else + { + /* Enable Interrupt lines 0 and 1 */ + FDCANx->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); + } + + /* Enable the selected TT interrupts */ + FDCAN_TT_EnableInt(FDCANx, TT_Int, ENABLE); + + return SUCCESS; +} + +/** + *\*\name FDCAN_TT_DeactivateInt. + *\*\fun Deactivate the specified FDCAN TT interrupts. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\param TT_Int : + *\*\ - FDCAN_TT_INT_BASIC_CYCLE_START + *\*\ - FDCAN_TT_INT_MATRIX_CYCLE_START + *\*\ - FDCAN_TT_INT_SYNC_MODE_CHANGE + *\*\ - FDCAN_TT_INT_START_OF_GAP + *\*\ - FDCAN_TT_INT_REG_TIME_MARK + *\*\ - FDCAN_TT_INT_TRIG_TIME_MARK + *\*\ - FDCAN_TT_INT_STOP_WATCH + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_WRAP + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_DISC + *\*\ - FDCAN_TT_INT_GLOBAL_TIME_ERROR + *\*\ - FDCAN_TT_INT_TX_COUNT_UNDERFLOW + *\*\ - FDCAN_TT_INT_TX_COUNT_OVERFLOW + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_1 + *\*\ - FDCAN_TT_INT_SCHEDULING_ERROR_2 + *\*\ - FDCAN_TT_INT_ERROR_LEVEL_CHANGE + *\*\ - FDCAN_TT_INT_INIT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_WATCH_TRIGGER + *\*\ - FDCAN_TT_INT_APPLICATION_WATCHDOG + *\*\ - FDCAN_TT_INT_CONFIG_ERROR + *\*\return none + */ +void FDCAN_TT_DeactivateInt(FDCAN_Module *FDCANx, uint32_t TT_Int) +{ + uint32_t IntLine; + uint32_t tempReg; + + /* Disable the selected TT interrupts */ + FDCAN_TT_EnableInt(FDCANx, TT_Int, DISABLE); + + IntLine = FDCANx->TTILS; + tempReg = FDCANx->ILE; + + if ((FDCANx->TTIE | IntLine) == IntLine) + { + /* Disable Interrupt line 0 */ + tempReg &= (~FDCAN_INTERRUPT_LINE0); + } + + if ((FDCANx->TTIE & IntLine) == 0U) + { + /* Disable Interrupt line 1 */ + tempReg &= (~FDCAN_INTERRUPT_LINE1); + } + + FDCANx->ILE = tempReg; +} + +/** + *\*\name FDCAN_InitMsgRam. + *\*\fun Calculate each RAM block start address and size, + *\*\ and also initialize global infomation parameter. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param FDCAN_InitParam:pointer to a FDCAN_InitType structure. + *\*\return ErrorStatus + *\*\ - ERROR + *\*\ - SUCCESS + */ +static ErrorStatus FDCAN_InitMsgRam(FDCAN_Module* FDCANx, FDCAN_InitType *FDCAN_InitParam) +{ + uint32_t ram; + uint32_t WordOffset; + uint32_t StartAddress; + uint32_t tempReg; + FDCAN_MsgRamType *pMsg; + + /* Config Message Ram base address,this address is shared by FDCAN1~8 */ + if(FDCAN_InitParam->MsgRamStrAddr == FDCAN_START_ADDRESS_SRAM5BANK1) + { + FDCANx->TTSS &= (~FDCAN_START_ADDRESS_RAMSEL); + StartAddress = FDCAN_START_ADDRESS_SRAM5BANK1; + } + else + { + FDCANx->TTSS |= FDCAN_START_ADDRESS_RAMSEL; + StartAddress = FDCAN_START_ADDRESS_SRAM5BANK2; + } + + FDCAN_ClearFlag(FDCANx, FDCAN_FLAG_RESERVED_ADDRESS_ACCESS); + + /* Config the message block for current FDCANx */ + pMsgRam[FDCAN_Get_Index(FDCANx)] = FDCAN_InitParam->pMsgInfo; + + pMsg = FDCAN_InitParam->pMsgInfo; + pMsg->RxFifo0Size = FDCAN_InitParam->RxFifo0Size; + pMsg->RxFifo1Size = FDCAN_InitParam->RxFifo1Size; + pMsg->RxBufferSize = FDCAN_InitParam->RxBufferSize; + pMsg->TxBufferSize = FDCAN_InitParam->TxBufferSize; + pMsg->RxFifo0DataSize = FDCAN_InitParam->RxFifo0DataSize; + pMsg->RxFifo1DataSize = FDCAN_InitParam->RxFifo1DataSize; + pMsg->RxBufferDataSize = FDCAN_InitParam->RxBufferDataSize; + pMsg->TxBufferDataSize = FDCAN_InitParam->TxBufferDataSize; + pMsg->LastTxFifoQReqBuf = 0; + + /* Config the registers raelated to Message Ram and global Message Ram paramter. + All address in register are actually the address offset, and counted in words. + Global Message Ram paramter counted in bytes */ + + /* Standard filter list start address */ + WordOffset = FDCAN_InitParam->MsgRamOffset; + tempReg = WordOffset << FDCAN_START_ADDRESS_OFFSET; + /* Standard filter elements number */ + tempReg |= FDCAN_InitParam->StdFilterSize << FDCAN_SIZE_NUMBER_OFFSET; + FDCANx->SIDFC = tempReg; + pMsg->StdFilterStrAddr = StartAddress + (WordOffset * 4UL); + + /* Extended filter list start address */ + WordOffset += FDCAN_InitParam->StdFilterSize; + tempReg = WordOffset << FDCAN_START_ADDRESS_OFFSET; + /* Extended filter elements number */ + tempReg |= FDCAN_InitParam->ExtFilterSize << FDCAN_SIZE_NUMBER_OFFSET; + FDCANx->XIDFC = tempReg; + pMsg->ExtFilterStrAddr = StartAddress + (WordOffset * 4UL); + + /* Rx FIFO 0 start address */ + WordOffset += (FDCAN_InitParam->ExtFilterSize * FDCAN_EXT_FILTER_WORDS); + tempReg = FDCANx->RXF0C & (~(FDCAN_RXF0C_F0SA | FDCAN_RXF0C_F0S)); + tempReg |= WordOffset << FDCAN_START_ADDRESS_OFFSET; + /* Rx FIFO 0 elements number */ + tempReg |= FDCAN_InitParam->RxFifo0Size << FDCAN_SIZE_NUMBER_OFFSET; + FDCANx->RXF0C = tempReg; + pMsg->RxFIFO0StrAddr = StartAddress + (WordOffset * 4UL); + + /* Rx FIFO 1 start address */ + WordOffset += (FDCAN_InitParam->RxFifo0Size * FDCAN_InitParam->RxFifo0DataSize); + tempReg = FDCANx->RXF1C & (~(FDCAN_RXF1C_F1SA | FDCAN_RXF1C_F1S)); + tempReg |= WordOffset << FDCAN_START_ADDRESS_OFFSET; + /* Rx FIFO 1 elements number */ + tempReg |= FDCAN_InitParam->RxFifo1Size << FDCAN_SIZE_NUMBER_OFFSET; + FDCANx->RXF1C = tempReg; + pMsg->RxFIFO1StrAddr = StartAddress + (WordOffset * 4UL); + + /* Rx buffer list start address */ + WordOffset += (FDCAN_InitParam->RxFifo1Size * FDCAN_InitParam->RxFifo1DataSize); + FDCANx->RXBC = WordOffset << FDCAN_START_ADDRESS_OFFSET; + pMsg->RxBufferStrAddr = StartAddress + (WordOffset * 4UL); + + /* Tx event FIFO start address */ + WordOffset += (FDCAN_InitParam->RxBufferSize * FDCAN_InitParam->RxBufferDataSize); + tempReg = FDCANx->TXEFC & (~(FDCAN_TXEFC_EFSA | FDCAN_TXEFC_EFS)); + tempReg |= WordOffset << FDCAN_START_ADDRESS_OFFSET; + /* Tx event FIFO elements number */ + tempReg |= FDCAN_InitParam->TxEventSize << FDCAN_SIZE_NUMBER_OFFSET; + FDCANx->TXEFC = tempReg; + pMsg->TxEventFIFOStrAddr = StartAddress + (WordOffset * 4UL); + + /* Tx buffer list start address */ + WordOffset += (FDCAN_InitParam->TxEventSize * FDCAN_TX_EVENT_FIFO_WORDS); + tempReg = FDCANx->TXBC & (~(FDCAN_TXBC_TBSA | FDCAN_TXBC_NDTB | FDCAN_TXBC_TFQS)); + tempReg |= WordOffset << FDCAN_START_ADDRESS_OFFSET; + /* Dedicated Tx buffers number */ + tempReg |= FDCAN_InitParam->TxBufferSize << FDCAN_SIZE_NUMBER_OFFSET; + pMsg->TxBufferStrAddr = StartAddress + (WordOffset * 4UL); + + /* Tx FIFO/queue elements number */ + tempReg |= FDCAN_InitParam->TxFifoQueueSize << FDCAN_TXBC_TFQS_OFFSET; + FDCANx->TXBC = tempReg; + WordOffset += (FDCAN_InitParam->TxBufferSize * FDCAN_InitParam->TxBufferDataSize); + pMsg->TxFIFOQueueStrAddr = StartAddress + (WordOffset * 4UL); + + WordOffset += (FDCAN_InitParam->TxFifoQueueSize * FDCAN_InitParam->TxBufferDataSize); + pMsg->EndAddress = StartAddress + (WordOffset * 4UL); + + /* Check last address of the Message RAM */ + if (pMsg->EndAddress > (StartAddress + FDCAN_MESSAGE_RAM_SIZE)) + { + return ERROR; + } + + /* Flush the allocated Message RAM area */ + for (ram = pMsg->StdFilterStrAddr; ram < pMsg->EndAddress; ram += 4UL) + { + *(uint32_t *)(ram) = 0UL; + } + + /* Return function status */ + return SUCCESS; +} + +/** + *\*\name FDCAN_CopyMsgToRAM. + *\*\fun Copy Tx message to the message RAM. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param pTxHeader :pointer to a FDCAN_TxHeaderType structure. + *\*\ - IdType + *\*\ - FDCAN_STANDARD_ID + *\*\ - FDCAN_EXTENDED_ID + *\*\ - ID + *\*\ This parameter must be a value between: + *\*\ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + *\*\ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + *\*\ - TxFrameType + *\*\ - FDCAN_DATA_FRAME + *\*\ - FDCAN_REMOTE_FRAME + *\*\ - DataLength + *\*\ - FDCAN_DLC_BYTES_0 + *\*\ - FDCAN_DLC_BYTES_1 + *\*\ - FDCAN_DLC_BYTES_2 + *\*\ - FDCAN_DLC_BYTES_3 + *\*\ - FDCAN_DLC_BYTES_4 + *\*\ - FDCAN_DLC_BYTES_5 + *\*\ - FDCAN_DLC_BYTES_6 + *\*\ - FDCAN_DLC_BYTES_7 + *\*\ - FDCAN_DLC_BYTES_8 + *\*\ - FDCAN_DLC_BYTES_12 + *\*\ - FDCAN_DLC_BYTES_16 + *\*\ - FDCAN_DLC_BYTES_20 + *\*\ - FDCAN_DLC_BYTES_24 + *\*\ - FDCAN_DLC_BYTES_32 + *\*\ - FDCAN_DLC_BYTES_48 + *\*\ - FDCAN_DLC_BYTES_64 + *\*\ - ErrorState + *\*\ - FDCAN_ESI_ACTIVE + *\*\ - FDCAN_ESI_PASSIVE + *\*\ - BitRateSwitch + *\*\ - FDCAN_BRS_OFF + *\*\ - FDCAN_BRS_ON + *\*\ - FDFormat + *\*\ - FDCAN_CLASSIC_CAN + *\*\ - FDCAN_FD_CAN + *\*\ - TxEventFifo + *\*\ - FDCAN_NO_TX_EVENTS + *\*\ - FDCAN_STORE_TX_EVENTS + *\*\ - MsgMarker + *\*\ This parameter must be a value between 0 and 0xFF + *\*\param pTxData pointer to a buffer containing the payload of the Tx frame. + *\*\param BufferIndex index of the buffer to be configured. + *\*\return none + */ +static void FDCAN_CopyMsgToRAM(FDCAN_Module *FDCANx, FDCAN_TxHeaderType *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex) +{ + uint32_t *TxAddress; + uint32_t Cnt; + uint8_t *pRam; + FDCAN_MsgRamType *pMsg; + + pMsg = pMsgRam[FDCAN_Get_Index(FDCANx)]; + + /* Calculate Tx element address */ + TxAddress = (uint32_t *)(pMsg->TxBufferStrAddr + (BufferIndex * pMsg->TxBufferDataSize * 4UL)); + + /* Build and write first word of Tx header element to ram */ + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + *TxAddress = ( pTxHeader->ErrorState \ + | FDCAN_STANDARD_ID \ + | pTxHeader->TxFrameType \ + | (pTxHeader->ID << FDCAN_ELEMENT_STDID_OFFSET) ); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + *TxAddress = ( pTxHeader->ErrorState \ + | FDCAN_EXTENDED_ID \ + | pTxHeader->TxFrameType \ + | pTxHeader->ID ); + } + + /* Increment TxAddress pointer to second word of Tx header element */ + TxAddress++; + + /* Build and write second word of Tx header element to ram */ + *TxAddress = ( (pTxHeader->MsgMarker << FDCAN_ELEMENT_MM_OFFSET) \ + | pTxHeader->TxEventFifo \ + | pTxHeader->FDFormat \ + | pTxHeader->BitRateSwitch \ + | pTxHeader->DataLength); + + /* Increment TxAddress pointer to Tx data */ + TxAddress++; + pRam = (uint8_t *)TxAddress; + + /* Write Tx payload to the message RAM */ + for (Cnt = 0; Cnt < DLCtoBytes[pTxHeader->DataLength >> FDCAN_ELEMENT_DLC_OFFSET]; Cnt++) + { + pRam[Cnt] = pTxData[Cnt]; + } +} + +/** + *\*\name FDCAN_ConfigExtTSDivider. + *\*\fun Config the clock diveder of external timestamp clock. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Div : + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_4 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_8 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_16 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_32 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_64 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_128 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_256 + *\*\ - FDCAN_EXT_TIMESTAMP_DIV_512 + *\*\return none + */ +void FDCAN_ConfigExtTSDivider(FDCAN_Module *FDCANx, uint32_t Div) +{ + uint32_t tempReg; + + tempReg = FDCANx->TTSS & (~FDCAN_TTSS_TS_SEL); + tempReg |= Div; + FDCANx->TTSS = tempReg; +} + +/** + *\*\name FDCAN_EnableExtTS. + *\*\fun Enalbe or disable the external timestamp. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void FDCAN_EnableExtTS(FDCAN_Module *FDCANx, FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = FDCANx->TTSS & (~FDCAN_TTSS_TS_EN); + + if(Cmd != DISABLE) + { + tempReg |= FDCAN_EXT_TIMESTAMP_ENABLE; + } + + FDCANx->TTSS = tempReg; +} + + +/** + *\*\name FDCAN_Get_Index. + *\*\fun Get the index number of FDCANx. + *\*\param FDCANx : + *\*\ - FDCAN1 + *\*\ - FDCAN2 + *\*\ - FDCAN3 + *\*\ - FDCAN4 + *\*\ - FDCAN5 + *\*\ - FDCAN6 + *\*\ - FDCAN7 + *\*\ - FDCAN8 + *\*\return none + */ +static uint8_t FDCAN_Get_Index(FDCAN_Module *FDCANx) +{ + uint32_t FDCANIndex; + + if(FDCANx == FDCAN1) + { + FDCANIndex = 0; + } + else if(FDCANx == FDCAN2) + { + FDCANIndex = 1; + } + else if(FDCANx == FDCAN3) + { + FDCANIndex = 2; + } + else if(FDCANx == FDCAN4) + { + FDCANIndex = 3; + } + else if(FDCANx == FDCAN5) + { + FDCANIndex = 4; + } + else if(FDCANx == FDCAN6) + { + FDCANIndex = 5; + } + else if(FDCANx == FDCAN7) + { + FDCANIndex = 6; + } + else + { + FDCANIndex = 7; + } + + return (uint8_t)FDCANIndex; +} + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_femc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_femc.c new file mode 100644 index 0000000000..6f08c95723 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_femc.c @@ -0,0 +1,951 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_femc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_femc.h" +#include "n32h76x_78x_rcc.h" +#include "stdio.h" + + +/** +*\*\name FEMC_Init. +*\*\fun Initializes the FEMC according to the specified parameters in the FEMC_InitStruct. +*\*\param FEMC_InitStruct : pointer to a FEMC_InitType +*\*\ structure that contains the configuration information for +*\*\ the FEMC specified Bank or Blocks. +*\*\return none +**/ +void FEMC_Init(FEMC_InitType *FEMC_InitStruct) +{ + /* Set FEMC timing.*/ + FEMC->FEMC_TCFG = ((( FEMC_InitStruct->TimingCfg.Trc << (0)) | \ + (FEMC_InitStruct->TimingCfg.Twc << (4)) | \ + (FEMC_InitStruct->TimingCfg.Tcere << (8)) | \ + (FEMC_InitStruct->TimingCfg.Twp << (11)) | \ + (FEMC_InitStruct->TimingCfg.Tpcclr << (14)) | \ + (FEMC_InitStruct->TimingCfg.Ttrar << (17)) | \ + (FEMC_InitStruct->TimingCfg.Twerr << (20))) & \ + (0x00FFFFFF)); + + /* Set FEMC chip configuration.*/ + FEMC->FEMC_OMCFG = ((FEMC_InitStruct->ChipCfg.ReadSyncMode | \ + FEMC_InitStruct->ChipCfg.ReadBurstLen | \ + FEMC_InitStruct->ChipCfg.WriteSyncMode | \ + FEMC_InitStruct->ChipCfg.WriteBurstLen | \ + FEMC_InitStruct->ChipCfg.MemWidth | \ + FEMC_InitStruct->ChipCfg.BAA | \ + FEMC_InitStruct->ChipCfg.ADV | \ + FEMC_InitStruct->ChipCfg.BLSS | \ + FEMC_InitStruct->ChipCfg.BurstAlign) & + (0x0000FFFF)); +} + +/** +*\*\name FEMC_InitStruct. +*\*\fun Fills each FEMC_InitStruct member with its default value. +*\*\param FEMC_InitStruct pointer to a FEMC_InitType structure which will be initialized. +*\*\return none +**/ +void FEMC_InitStruct(FEMC_InitType* FEMC_InitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FEMC_InitStruct->TimingCfg.Trc = 0; + FEMC_InitStruct->TimingCfg.Twc = 0; + FEMC_InitStruct->TimingCfg.Tcere = 0; + FEMC_InitStruct->TimingCfg.Twp = 0; + FEMC_InitStruct->TimingCfg.Tpcclr = 0; + FEMC_InitStruct->TimingCfg.Ttrar = 0; + FEMC_InitStruct->TimingCfg.Twerr = 0; + + FEMC_InitStruct->ChipCfg.ReadSyncMode = FEMC_MEM_READ_ASYNC; + FEMC_InitStruct->ChipCfg.ReadBurstLen = FEMC_MEM_READ_BURST_1; + FEMC_InitStruct->ChipCfg.WriteSyncMode = FEMC_MEM_WRITE_ASYNC; + FEMC_InitStruct->ChipCfg.WriteBurstLen = FEMC_MEM_WRITE_BURST_1; + FEMC_InitStruct->ChipCfg.MemWidth = FEMC_MEMORY_WIDTH_16BIT; + FEMC_InitStruct->ChipCfg.BAA = FEMC_BAA_PORT_DISABLE; + FEMC_InitStruct->ChipCfg.ADV = FEMC_ADV_PORT_DISABLE; + FEMC_InitStruct->ChipCfg.BLSS = FEMC_BLS_SYNC_CS; + FEMC_InitStruct->ChipCfg.BurstAlign = FEMC_BURST_SPLIT_ON_256; +} + +/** +*\*\name FEMC_EnableNorSram. +*\*\fun Enables or disables the specified NOR/SRAM Memory Bank. +*\*\param Chip: The chip number. +*\*\ - SRAM_NOR_CHIP_1: SRAM Chip 1 +*\*\ - SRAM_NOR_CHIP_2: SRAM Chip 2 +*\*\ - SRAM_NOR_CHIP_3: SRAM Chip 3 +*\*\ - SRAM_NOR_CHIP_4: SRAM Chip 4 +*\*\ - NAND_CHIP_1: NAND Chip 1 +*\*\ - NAND_CHIP_2: NAND Chip 2 +*\*\param Cmd: The command +*\*\ - FEMC_CMD_UPDATEREGS_AND_AXI: +*\*\ - FEMC_CMD_MDREGCONFIG: Configure mode register +*\*\ - FEMC_CMD_UPDATEREGS: Update mode register +*\*\ - FEMC_CMD_MDREGCONFIG_AND_UPDATEREGS: Configure mode register and update +*\*\param CrePolarity : +*\*\ - FEMC_CRE_POLARITY_LOW: CRE is LOW +*\*\ - FEMC_CRE_POLARITY_HIGH: CRE is HIGH when ModeReg write occurs +*\*\param Address: 0~0x000FFFFF +*\*\ The address parameter is valid when CMD type is MdRegConfig or MdRegConfig and UpdateRegs only. +*\*\return none +**/ +void FEMC_SetCommand(uint32_t Chip, uint32_t Cmd, uint32_t CrePolarity, uint32_t Address) +{ + /* Set FEMC_CTRL register for FEMC.*/ + FEMC->FEMC_CTRL = (Address | CrePolarity | Cmd | (Chip << 23)); +} + +/** +*\*\name FEMC_CheckChipStatus. +*\*\fun Check FEMC chip status register value. +*\*\param Chip: The chip number. +*\*\ - SRAM_NOR_CHIP_1: SRAM Chip 1 +*\*\ - SRAM_NOR_CHIP_2: SRAM Chip 2 +*\*\ - SRAM_NOR_CHIP_3: SRAM Chip 3 +*\*\ - SRAM_NOR_CHIP_4: SRAM Chip 4 +*\*\ - NAND_CHIP_1: NAND Chip 1 +*\*\ - NAND_CHIP_2: NAND Chip 2 +*\*\param ChipCfg: Pointer to a FEMC_ChipInitType structure +*\*\return SUCCESS or ERROR +**/ +ErrorStatus FEMC_CheckChipStatus(uint32_t Chip, FEMC_ChipInitType *ChipCfg) +{ + uint32_t temp_value; + uint32_t FEMC_OPMODE_Value = 0; + + temp_value = ((ChipCfg->ReadSyncMode | \ + ChipCfg->ReadBurstLen | \ + ChipCfg->WriteSyncMode | \ + ChipCfg->WriteBurstLen | \ + ChipCfg->MemWidth | \ + ChipCfg->BAA | \ + ChipCfg->ADV | \ + ChipCfg->BLSS | \ + ChipCfg->BurstAlign) & (0x0000FFFF)) ; + + switch(Chip) + { + case SRAM_NOR_CHIP_1: + FEMC_OPMODE_Value = FEMC->block1.FEMC_SNOMSTS; + temp_value |= (FEMC->FEMC_SNADD1 & (0xFFFF0000)); + break; + + case SRAM_NOR_CHIP_2: + FEMC_OPMODE_Value = FEMC->block2.FEMC_SNOMSTS; + temp_value |= (FEMC->FEMC_SNADD2 & (0xFFFF0000)); + break; + + case SRAM_NOR_CHIP_3: + FEMC_OPMODE_Value = FEMC->block3.FEMC_SNOMSTS; + temp_value |= (FEMC->FEMC_SNADD3 & (0xFFFF0000)); + break; + + case SRAM_NOR_CHIP_4: + FEMC_OPMODE_Value = FEMC->block4.FEMC_SNOMSTS; + temp_value |= (FEMC->FEMC_SNADD4 & (0xFFFF0000)); + break; + + case NAND_CHIP_1: + FEMC_OPMODE_Value = FEMC->bank1.FEMC_NOMSTS; + temp_value |= (FEMC->FEMC_NADD1 & (0xFFFF0000)); + break; + + case NAND_CHIP_2: + FEMC_OPMODE_Value = FEMC->bank2.FEMC_NOMSTS; + temp_value |= (FEMC->FEMC_NADD2 & (0xFFFF0000)); + break; + + default: + break; + } + + return (temp_value == FEMC_OPMODE_Value) ? SUCCESS : ERROR; +} + +/** +*\*\name FEMC_CheckTimingStatus. +*\*\fun Check FEMC timing status register value. +*\*\param Chip: The chip number. +*\*\ - SRAM_NOR_CHIP_1: SRAM Chip 1 +*\*\ - SRAM_NOR_CHIP_2: SRAM Chip 2 +*\*\ - SRAM_NOR_CHIP_3: SRAM Chip 3 +*\*\ - SRAM_NOR_CHIP_4: SRAM Chip 4 +*\*\ - NAND_CHIP_1: NAND Chip 1 +*\*\ - NAND_CHIP_2: NAND Chip 2 +*\*\param ChipCfg: Pointer to a FEMC_ChipInitType structure +*\*\return SUCCESS or ERROR +**/ +ErrorStatus FEMC_CheckTimingStatus(uint32_t Chip, FEMC_TimingInitType *TimingCfg) +{ + uint32_t temp_value; + uint32_t FEMC_Timing_Value = 0; + + temp_value = ((TimingCfg->Trc << (0)) | \ + (TimingCfg->Twc << (4)) | \ + (TimingCfg->Tcere << (8)) | \ + (TimingCfg->Twp << (11)) | \ + (TimingCfg->Tpcclr << (14)) | \ + (TimingCfg->Ttrar << (17)) | \ + (TimingCfg->Twerr << (20))) & (0x00FFFFFF); + + switch(Chip) + { + case SRAM_NOR_CHIP_1: + FEMC_Timing_Value = FEMC->block1.FEMC_SNTSTS; + break; + + case SRAM_NOR_CHIP_2: + FEMC_Timing_Value = FEMC->block2.FEMC_SNTSTS; + break; + + case SRAM_NOR_CHIP_3: + FEMC_Timing_Value = FEMC->block3.FEMC_SNTSTS; + break; + + case SRAM_NOR_CHIP_4: + FEMC_Timing_Value = FEMC->block4.FEMC_SNTSTS; + break; + + case NAND_CHIP_1: + FEMC_Timing_Value = FEMC->bank1.FEMC_NTSTS; + break; + + case NAND_CHIP_2: + FEMC_Timing_Value = FEMC->bank2.FEMC_NTSTS; + break; + + default: + break; + } + + return (temp_value == FEMC_Timing_Value) ? SUCCESS : ERROR; +} + +/** +*\*\name FEMC_SetRefreshPeriod. +*\*\fun Set FEMC refresh period value. +*\*\param PeriodVal: 0~0x0F The FEMC refresh period value +*\*\return none +**/ +void FEMC_SetRefreshPeriod(uint32_t PeriodVal) +{ + FEMC->FEMC_RPE = PeriodVal; +} + +/** +*\*\name FEMC_GetRefreshPeriod. +*\*\fun Get FEMC refresh period value. +*\*\param +*\*\return The FEMC refresh period value +**/ +uint32_t FEMC_GetRefreshPeriod(void) +{ + return (FEMC->FEMC_RPE & 0x0F); +} + +/** +*\*\name FEMC_SetAddressmatch. +*\*\fun Set address and mask value for specific chip region. +*\*\param Chip: The chip number. +*\*\ - SRAM_NOR_CHIP_1: SRAM Chip 1 +*\*\ - SRAM_NOR_CHIP_2: SRAM Chip 2 +*\*\ - SRAM_NOR_CHIP_3: SRAM Chip 3 +*\*\ - SRAM_NOR_CHIP_4: SRAM Chip 4 +*\*\ - NAND_CHIP_1: NAND Chip 1 +*\*\ - NAND_CHIP_2: NAND Chip 2 +*\*\param Address_Match_Value: 0, 0X00010000~ 0xFFFF0000 The address and mask value for specific chip region +*\*\return SUCCESS or ERROR +**/ +void FEMC_SetAddressmatch(uint32_t Chip, uint32_t Address_Match_Value) +{ + switch(Chip) + { + case SRAM_NOR_CHIP_1: + FEMC->FEMC_SNADD1 = Address_Match_Value; + break; + + case SRAM_NOR_CHIP_2: + FEMC->FEMC_SNADD2 = Address_Match_Value; + break; + + case SRAM_NOR_CHIP_3: + FEMC->FEMC_SNADD3 = Address_Match_Value; + break; + + case SRAM_NOR_CHIP_4: + FEMC->FEMC_SNADD4 = Address_Match_Value; + break; + + case NAND_CHIP_1: + FEMC->FEMC_NADD1 = Address_Match_Value; + break; + + case NAND_CHIP_2: + FEMC->FEMC_NADD2 = Address_Match_Value; + break; + + default: + break; + } + +} + +/** +*\*\name SRAM_MuxModeEnable. +*\*\fun Enable or disable the SRAM interface multiplexed mode. +*\*\param NewState: new state of the multiplexed mode. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_SRAMMuxModeEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_SNMOD |= FEMC_SNMOD_MUXEN; + } + else + { + FEMC->FEMC_SNMOD &= ~FEMC_SNMOD_MUXEN; + } +} + +/** +*\*\name FEMC_SRAMAGTMEnable. +*\*\fun Enable or disable aclk faster than SRAM clock. +*\*\param NewState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_SRAMAGTMEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_SNMOD |= FEMC_SNMOD_AGTM; + } + else + { + FEMC->FEMC_SNMOD &= ~FEMC_SNMOD_AGTM; + } +} + +/** +*\*\name FEMC_SRAMSYNCEnable. +*\*\fun Enable or disable the SRAM clock synchronous to aclk. +*\*\param NewState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_SRAMSYNCEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_SNMOD |= FEMC_SNMOD_SYNC; + } + else + { + FEMC->FEMC_SNMOD &= ~FEMC_SNMOD_SYNC; + } +} + +/** +*\*\name FEMC_NANDCSLEnable. +*\*\fun Enable or disable NAND chip select remains asserted between the address phase and data phase. +*\*\param NewState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_NANDCSLEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_NMOD |= FEMC_NMOD_CSL; + } + else + { + FEMC->FEMC_NMOD &= ~FEMC_NMOD_CSL; + } +} + + +/** +*\*\name FEMC_NANDAGTMEnable. +*\*\fun Enable or disable aclk faster than NAND clock. +*\*\param NewState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_NANDAGTMEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_NMOD |= FEMC_NMOD_AGTM; + } + else + { + FEMC->FEMC_NMOD &= ~FEMC_NMOD_AGTM; + } +} + +/** +*\*\name FEMC_NANDSYNCEnable. +*\*\fun Enable or disable the NAND clock synchronous to aclk. +*\*\param NewState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_NANDSYNCEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_NMOD |= FEMC_NMOD_SYNC; + } + else + { + FEMC->FEMC_NMOD &= ~FEMC_NMOD_SYNC; + } +} + +/** +*\*\name FEMC_RemapEnable. +*\*\fun Enable or disable the FEMC SRAM interface remap to SDRAM. +*\*\param NewState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_RemapEnable(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + FEMC->FEMC_REMAP |= FEMC_REMAP_REMAP; + } + else + { + FEMC->FEMC_REMAP &= ~FEMC_REMAP_REMAP; + } +} + +/** +*\*\name FEMC_ClrFlag. +*\*\fun Clears the FEMC's flags. +*\*\param FEMC_FLAG: +*\*\ - FEMC_SRAM_FLAG_CLEAR +*\*\ - FEMC_NAND_FLAG_CLEAR +*\*\return none +**/ +void FEMC_ClrFlag(uint32_t FEMC_FLAG) +{ + FEMC->FEMC_CCFG |= FEMC_FLAG; +} + +/** +*\*\name FEMC_GetFlag. +*\*\fun Checks whether the specified flag is set or not. +*\*\param FEMC_FLAG +*\*\ - FEMC_SRAM_FLAG +*\*\ - FEMC_NAND_FLAG +*\*\ - FEMC_ECC_FLAG +*\*\ - FEMC_SRAM_EN_FLAG +*\*\ - FEMC_NAND_EN_FLAG +*\*\ - FEMC_ECC_EN_FLAG +*\*\return FlagStatus +*\*\ - SET : the flag is set +*\*\ - RESET : the flag is reset +**/ +FlagStatus FEMC_GetFlag(uint32_t FEMC_FLAG) +{ + FlagStatus bitstatus; + + /* Check the status of the specified I2C flag */ + if ((FEMC->FEMC_STS & FEMC_FLAG) != (uint32_t)RESET) + { + /* FEMC_IT is set */ + bitstatus = SET; + } + else + { + /* FEMC_IT is reset */ + bitstatus = RESET; + } + + /* Return the FEMC_IT status */ + return bitstatus; +} + +/** +*\*\name FEMC_ITConfig. +*\*\fun Enables or disables the specified FEMC interrupts. +*\*\param FEMC_IT: +*\*\ - FEMC_IT_SRAM_EN +*\*\ - FEMC_IT_NAND_EN +*\*\ - FEMC_IT_ECC_EN +*\*\param NewState: new state of the multiplexed mode. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_ITConfig(uint32_t FEMC_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Enable the selected FEMC interrupts */ + FEMC->FEMC_CFG |= FEMC_IT; + } + else + { + /* Disable the selected FEMC interrupts */ + FEMC->FEMC_CCFG |= FEMC_IT; + } +} + +/** +*\*\name FEMC_ClrITFlag. +*\*\fun Clears the FEMC's interrupt pending flags. +*\*\param FEMC_FLAG: +*\*\ - FEMC_IT_SRAM_FLAG_CLEAR +*\*\ - FEMC_IT_NAND_FLAG_CLEAR +*\*\return none +**/ +void FEMC_ClrITFlag(uint32_t FEMC_FLAG) +{ + FEMC->FEMC_CCFG |= FEMC_FLAG; +} + +/** +*\*\name FEMC_GetITFlag. +*\*\fun Checks whether the specified interrupt flag is set or not. +*\*\param FEMC_IT_FLAG +*\*\ - FEMC_IT_SRAM_FLAG +*\*\ - FEMC_IT_NAND_FLAG +*\*\ - FEMC_IT_ECC_FLAG +*\*\return ITStatus +*\*\ - SET : the interrupt flag is set +*\*\ - RESET : the interrupt flag is reset +**/ +ITStatus FEMC_GetITFlag(uint32_t FEMC_IT_FLAG) +{ + ITStatus bitstatus; + + /* Check the status of the specified I2C flag */ + if ((FEMC->FEMC_STS & FEMC_IT_FLAG) != (uint32_t)RESET) + { + /* FEMC_IT is set */ + bitstatus = SET; + } + else + { + /* FEMC_IT is reset */ + bitstatus = RESET; + } + + /* Return the FEMC_IT status */ + return bitstatus; +} + +/** +*\*\name FEMC_AsyncADVConfig. +*\*\fun Enables or disables the ADC singal same as multiplexed mode in asynchronous mode. +*\*\param NewState: new state of the multiplexed mode. +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FEMC_AsyncADVConfig(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Enable the selected FEMC interrupts */ + FEMC->FEMC_CFG |= FEMC_CFG_ASYNCADV; + } + else + { + /* Disable the selected FEMC interrupts */ + FEMC->FEMC_CCFG |= FEMC_CFG_ASYNCADV; + } +} + +/** +*\*\name FEMC_GetSRAMType. +*\*\fun Get FEMC SRAM interface type. +*\*\return none +**/ +uint32_t FEMC_GetSRAMType(void) +{ + uint32_t status; + /* Enable the selected FEMC interrupts */ + status = FEMC->FEMC_STS1 & 0x03; + + return status; +} + +/** +*\*\name FEMC_ECC_Init. +*\*\fun Initialize FEMC ECC function. +*\*\param ECCInitType Pointer to a FEMC_ECCInitType structure +*\*\return none +**/ +void FEMC_ECC_Init(const FEMC_ECCInitType *ECCInitType) +{ + uint32_t temp_value; + + /* Check the pointer pstcInit */ + + temp_value = (( ECCInitType->BLKNum | \ + ECCInitType->Mode | \ + ECCInitType->ReadMode | \ + ECCInitType->JUMP | \ + ECCInitType->A8OUTMSK | \ + ECCInitType->ReadINT | \ + ECCInitType->ABTINT | \ + ECCInitType->EXTBLKEN | \ + ECCInitType->EXTBLKSize) & (0x00001FFF)); + FEMC->FEMC_ECCCFG = temp_value; + FEMC->FEMC_ECCMD0 = ECCInitType->CMD0; + FEMC->FEMC_ECCMD1 = ECCInitType->CMD1; +} + +/** +*\*\name FEMC_SetECCAddr. +*\*\fun Set the FEMC ECC data start address. +*\*\param address0: FEMC ECC data start address 0. +*\*\param address0: FEMC ECC data start address 1. +*\*\return none +**/ +void FEMC_SetECCAddr(uint32_t address0, uint32_t address1) +{ + FEMC->FEMC_ECCADDR0 = address0; + FEMC->FEMC_ECCADDR1 = address1; +} + +/** +*\*\name FEMC_GetECCFlag. +*\*\fun Get the FEMC ECC flag status. +*\*\param FEMC_ECC_Flag_Index +*\*\ - FEMC_ECC_FLAG_VALUE_VALID +*\*\ - FEMC_ECC_FLAG_FAIL +*\*\ - FEMC_ECC_FLAG_CAN_CORRECT +*\*\ - FEMC_ECC_FLAG_READ +*\*\param ECC_Block_Index +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX0 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX1 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX2 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX3 +*\*\ - FEMC_ECC_PAGE_BLOCK_EXTRA +*\*\return FlagStatus +*\*\ - SET : The state of specific flag is set +*\*\ - RESET : The state of specific flag is reset +**/ +FlagStatus FEMC_GetECCFlag(uint32_t FEMC_ECC_Flag_Index, uint32_t ECC_Block_Index) +{ + FlagStatus status = RESET; + + if(FEMC->FEMC_ECCSTS & (FEMC_ECC_Flag_Index << ECC_Block_Index)) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/** +*\*\name FEMC_GetECCITFlag. +*\*\fun Get the FEMC ECC interrupt status. +*\*\param ECC_Block_Index +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK0 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK1 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK2 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK3 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_EXTRA +*\*\ - FEMC_ECC_INT_FLAG_ABORT +*\*\return FlagStatus +*\*\ - SET : the flag is set +*\*\ - RESET : the flag is reset +**/ +FlagStatus FEMC_GetECCITFlag(uint32_t ECC_Block_Index) +{ + FlagStatus status = RESET; + + if(FEMC->FEMC_ECCSTS & ECC_Block_Index) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/** +*\*\name FEMC_ECCClrFlag. +*\*\fun Clear the FEMC ECC interrupt. +*\*\param ECC_Block_Index +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK0 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK1 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK2 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_BLOCK3 +*\*\ - FEMC_ECC_INT_FLAG_PAGE_EXTRA +*\*\ - FEMC_ECC_INT_FLAG_ABORT +*\*\return none +**/ +void FEMC_ECCClrFlag(uint32_t ECC_Block_Index) +{ + FEMC->FEMC_ECCSTS = ECC_Block_Index; +} + +/** +*\*\name FEMC_GetECCStatus. +*\*\fun Get the FEMC ECC status. +*\*\param none +*\*\return FlagStatus +*\*\ - SET : the ecc status is busy +*\*\ - RESET : the ecc status is idle +**/ +FlagStatus FEMC_GetECCBusyFlag(void) +{ + FlagStatus status = RESET; + + if(FEMC->FEMC_ECCSTS & FEMC_ECCSTS_BUSY) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/** +*\*\name FEMC_GetECCLastStatus. +*\*\fun Get the FEMC Last ECC status. +*\*\param none +*\*\return ECC_Last_Stats +*\*\ - Completed_Success +*\*\ - Unaligned_Range +*\*\ - Data_Stop +*\*\ - Data_Stop_No_Read +**/ +ECC_Last_Stats FEMC_GetECCLastSTS(void) +{ + ECC_Last_Stats status = COMPLETE; + + if((FEMC->FEMC_ECCSTS & FEMC_ECCSTS_LASTS) == FEMC_ECC_LAST_STATUS_COMPLETE) + { + status = COMPLETE; + } + else if((FEMC->FEMC_ECCSTS & FEMC_ECCSTS_LASTS) == FEMC_ECC_LAST_STATUS_UNALIGNADDR) + { + status = UNALIGNADDR; + } + else if((FEMC->FEMC_ECCSTS & FEMC_ECCSTS_LASTS) == FEMC_ECC_LAST_STATUS_DATASTOP) + { + status = DATASTOP; + } + else if((FEMC->FEMC_ECCSTS & FEMC_ECCSTS_LASTS) == FEMC_ECC_LAST_STATUS_DATASTOP_NOREAD) + { + status = DATASTOP_NOREAD; + } + + return status; +} + +/** +*\*\name FEMC_GetECCRWSTS. +*\*\fun Get the FEMC ECC write or read status. +*\*\param none +*\*\return FlagStatus +*\*\ - SET : the ecc is read status +*\*\ - RESET : the ecc is write status +**/ +FlagStatus FEMC_GetECCRWFlag(void) +{ + FlagStatus status = SET; + + if(FEMC->FEMC_ECCSTS & FEMC_ECCSTS_WRF) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/** +*\*\name FEMC_GetECCBlockSTS. +*\*\fun Get the FEMC ECC page block status. +*\*\param ECC_Block_Index +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX0 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX1 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX2 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX3 +*\*\ - FEMC_ECC_PAGE_BLOCK_EXTRA +*\*\param FEMC_Block_Flag_Index: specifies which flag status to get. +*\*\ - FEMC_ECC_BLOCK_FLAG_CAN_CORRECT: Indicates if the detected error is correctablea: 0 = not correctable,1 = correctable. +*\*\ - FEMC_ECC_BLOCK_FLAG_FAIL: Pass, fail flag for each ECC block:0 = pass,1 = fail. +*\*\ - FEMC_ECC_BLOCK_FLAG_READ: Read flags for ECC blocks:0 = not read,1 = read. +*\*\ - FEMC_ECC_BLOCK_FLAG_VALUE_VALID: Valid flag for each ECC block:0 = not valid,1 = valid. +*\*\ - FEMC_ECC_BLOCK_FLAG_INTERRUPT: Interrupt flag:0 = not set,1 = set. +*\*\return SET or RESET +**/ +FlagStatus FEMC_GetECCBlockSTS(uint32_t ECC_Block_Index, uint32_t FEMC_Block_Flag_Index) +{ + FlagStatus status = RESET; + + + if(ECC_Block_Index != FEMC_ECC_PAGE_BLOCK_EXTRA) + { + if(FEMC->FEMC_ECCBLK[ECC_Block_Index] & ((uint32_t)((FEMC_Block_Flag_Index) << 27))) + { + status = SET; + } + else + { + status = RESET; + } + } + else if(ECC_Block_Index == FEMC_ECC_PAGE_BLOCK_EXTRA) + { + if(FEMC->FEMC_ECCEBLK & ((uint32_t)((FEMC_Block_Flag_Index) << 27))) + { + status = SET; + } + else + { + status = RESET; + } + } + + return status; +} + +/** +*\*\name FEMC_GetECCBlockSTS. +*\*\fun Clear the FEMC ECC page block status. +*\*\param ECC_Block_Index +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX0 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX1 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX2 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX3 +*\*\ - FEMC_ECC_PAGE_BLOCK_EXTRA +*\*\param FEMC_Block_Flag_Index: specifies which flag status to get. +*\*\ - FEMC_ECC_BLOCK_FLAG_CAN_CORRECT: Indicates if the detected error is correctablea: 0 = not correctable,1 = correctable. +*\*\ - FEMC_ECC_BLOCK_FLAG_FAIL: Pass, fail flag for each ECC block:0 = pass,1 = fail. +*\*\ - FEMC_ECC_BLOCK_FLAG_READ: Read flags for ECC blocks:0 = not read,1 = read. +*\*\ - FEMC_ECC_BLOCK_FLAG_VALUE_VALID: Valid flag for each ECC block:0 = not valid,1 = valid. +*\*\ - FEMC_ECC_BLOCK_FLAG_INTERRUPT: Interrupt flag:0 = not set,1 = set. +*\*\return None +**/ +void FEMC_ClrECCBlockSTS(uint32_t ECC_Block_Index, uint32_t FEMC_Block_Flag_Index) +{ + uint32_t temp; + + if(ECC_Block_Index != FEMC_ECC_PAGE_BLOCK_EXTRA) + { + temp = FEMC->FEMC_ECCBLK[ECC_Block_Index]; + temp &= !((uint32_t)((FEMC_Block_Flag_Index) << 27)); + FEMC->FEMC_ECCBLK[ECC_Block_Index] = temp; + } + else if(ECC_Block_Index == FEMC_ECC_PAGE_BLOCK_EXTRA) + { + temp = FEMC->FEMC_ECCEBLK; + temp &= !((uint32_t)((FEMC_Block_Flag_Index) << 27)); + FEMC->FEMC_ECCEBLK = temp; + } +} + + + +/** +*\*\name FEMC_GetECCvalue. +*\*\fun Get the FEMC ECC value or result of each page frame. +*\*\param ECC_Block_Index +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX0 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX1 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX2 +*\*\ - FEMC_ECC_PAGE_BLOCK_INDEX3 +*\*\ - FEMC_ECC_PAGE_BLOCK_EXTRA +*\*\return The ecc value of specific page frame. +**/ +uint32_t FEMC_GetECCvalue(uint32_t ECC_Block_Index) +{ + uint32_t temp_value = 0; + + if(ECC_Block_Index != FEMC_ECC_PAGE_BLOCK_EXTRA) + { + temp_value = FEMC->FEMC_ECCBLK[ECC_Block_Index] & (FEMC_ECCBLK_VAL); + } + else if(ECC_Block_Index == FEMC_ECC_PAGE_BLOCK_EXTRA) + { + temp_value = FEMC->FEMC_ECCEBLK & (FEMC_ECCBLK_VAL); + } + + return temp_value; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fmac.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fmac.c new file mode 100644 index 0000000000..08a0fa13ab --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_fmac.c @@ -0,0 +1,712 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_fmac.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_fmac.h" +#include "n32h76x_78x_rcc.h" + +#ifndef NULL + #define NULL 0 +#endif + +/** +*\*\name FMAC_DeInit. +*\*\fun Deinitializes the FMAC peripheral registers to their default reset values +*\*\param none +*\*\return none +**/ +void FMAC_DeInit(void) +{ + /* Enable FMAC reset state */ + RCC_EnableAHB2PeriphReset1(RCC_AHB2_PERIPHRST_FMAC); +} + +/** +*\*\name FMAC_Init. +*\*\fun Initialize the FMAC peripheral +*\*\param FMAC_InitStruct : +*\*\ - InputBufBaseAddress +*\*\ - 0...255 +*\*\ - InputBufSize +*\*\ - 0...255 +*\*\ - InputBufThreshold +*\*\ - FMAC_THRESHOLD1 +*\*\ - FMAC_THRESHOLD2 +*\*\ - FMAC_THRESHOLD4 +*\*\ - FMAC_THRESHOLD8 +*\*\ - CoeffBufBaseAddress +*\*\ - 0...255 +*\*\ - CoeffBufSize +*\*\ - 0...255 +*\*\ - OutBufBaseAddress +*\*\ - 0...255 +*\*\ - OutBufSize +*\*\ - 0...255 +*\*\ - OutBufThreshold +*\*\ - FMAC_THRESHOLD1 +*\*\ - FMAC_THRESHOLD2 +*\*\ - FMAC_THRESHOLD4 +*\*\ - FMAC_THRESHOLD8 +*\*\ - Limit +*\*\ - FMAC_LIMIT_ENABLE +*\*\ - FMAC_LIMIT_DISABLE +*\*\ - Func +*\*\ - FMAC_FUNC_LOADX1 +*\*\ - FMAC_FUNC_LOADX2 +*\*\ - FMAC_FUNC_LOADY +*\*\ - FMAC_FUNC_CONVO_FIR +*\*\ - FMAC_FUNC_IIR_DIRECT_FORM_1 +*\*\ - P. +*\*\ - 0...255 +*\*\ - Q. +*\*\ - 0...255 +*\*\ - R. +*\*\ - 0...255 +*\*\return none +**/ +void FMAC_Init(FMAC_InitType * FMAC_InitStruct) +{ + /* configure the input buffer parameter */ + FMAC->X1BUFCFG = ((((uint32_t)FMAC_InitStruct->InputBufBaseAddress) & FMAC_X1BUFCFG_X1BASE) \ + | ((((uint32_t)FMAC_InitStruct->InputBufSize) << REG_BIT8_OFFSET) & FMAC_X1BUFCFG_X1BUFSIZE) \ + | (FMAC_InitStruct->InputBufThreshold & FMAC_X1BUFCFG_X1BUFWM) ); + + /* configure the coefficient parameter */ + FMAC->X2BUFCFG = ((((uint32_t)FMAC_InitStruct->CoeffBufBaseAddress) & FMAC_X2BUFCFG_X2BASE) \ + | ((((uint32_t)FMAC_InitStruct->CoeffBufSize) << REG_BIT8_OFFSET) & FMAC_X2BUFCFG_X2BUFSIZE)); + + /* configure the output buffer parameter */ + FMAC->YBUFCFG = ((((uint32_t)FMAC_InitStruct->OutBufBaseAddress) & FMAC_YBUFCFG_YBASE) \ + | ((((uint32_t)FMAC_InitStruct->OutBufSize) << REG_BIT8_OFFSET) & FMAC_YBUFCFG_YBUFSIZE) \ + | (FMAC_InitStruct->OutBufThreshold & FMAC_YBUFCFG_YBUFWM) ); + + /* configure the state of limit */ + if(FMAC_InitStruct->Limit == FMAC_LIMIT_ENABLE) + { + FMAC->CTRL |= FMAC_CTRL_LIMITEN; + } + else + { + FMAC->CTRL &= ~FMAC_CTRL_LIMITEN; + } +} + +/** +*\*\name FMAC_StructInit. +*\*\fun Initialize the FMAC filter parameter struct with the default values +*\*\param FMAC_InitStruct : +*\*\ - InputBufBaseAddress +*\*\ - InputBufSize +*\*\ - InputBufThreshold +*\*\ - CoeffBufBaseAddress +*\*\ - CoeffBufSize +*\*\ - OutBufBaseAddress +*\*\ - OutBufSize +*\*\ - OutBufThreshold +*\*\ - Limit +*\*\ - Func +*\*\ - P +*\*\ - Q +*\*\ - R +*\*\return none +**/ +void FMAC_StructInit(FMAC_InitType * FMAC_InitStruct) +{ + FMAC_InitStruct->InputBufBaseAddress = 0U; + FMAC_InitStruct->InputBufSize = 0U; + FMAC_InitStruct->InputBufThreshold = 0U; + FMAC_InitStruct->CoeffBufBaseAddress = 0U; + FMAC_InitStruct->CoeffBufSize = 0U; + FMAC_InitStruct->OutBufBaseAddress = 0U; + FMAC_InitStruct->OutBufSize = 0U; + FMAC_InitStruct->OutBufThreshold = 0U; + FMAC_InitStruct->Limit = 0U; + FMAC_InitStruct->Func = 0U; + FMAC_InitStruct->P = 0U; + FMAC_InitStruct->Q = 0U; + FMAC_InitStruct->R = 0U; +} + +/** +*\*\name FMAC_PreLoadData. +*\*\fun Preload data +*\*\param size : +*\*\ - 0~255 size of data +*\*\param array[]: +*\*\ - pointer to the buffer containing the data to be loaded +*\*\return none +**/ +void FMAC_PreLoadData(uint32_t size, int16_t array[]) +{ + uint32_t i; + + for(i = 0U; i < size; i++) + { + FMAC->WDAT = (uint32_t)array[i] & FMAC_WDAT_WDAT; + } +} + +/** +*\*\name FMAC_PreloadBufferData. +*\*\fun Preload three buffer data +*\*\param FMAC_PreloadStruct : +*\*\ - pInputData : +*\*\ - pointer to the input buffer containing the data to be computed +*\*\ - InputDataSize : +*\*\ - 0..255 +*\*\ - pCoeffA : +*\*\ - pointer to the buffer containing the data to be computed +*\*\ - CoeffASize : +*\*\ - 0..255 +*\*\ - pCoeffB : +*\*\ - pointer to the buffer containing the data to be computed +*\*\ - CoeffBSize : +*\*\ - 0..255 +*\*\ - pOutputData : +*\*\ - pointer to the output buffer containing the data to be computed +*\*\ - OutputDataSize : +*\*\ - 0..255 +*\*\return ErrorStatus: +*\*\ - SUCCESS FMAC preload success +*\*\ - ERROR FMAC preload timeout +**/ +ErrorStatus FMAC_PreloadBufferData(FMAC_PreLoadType * FMAC_PreloadStruct) +{ + uint32_t timeout; + ErrorStatus status = SUCCESS; + + if((NULL != FMAC_PreloadStruct->pInputData) && (0U != FMAC_PreloadStruct->InputDataSize)) + { + /* configure parameter of filter preload */ + FMAC->PARAMCFG = ((uint32_t)(FMAC_PreloadStruct->InputDataSize) & FMAC_PARAMCFG_P) \ + | FMAC_FUNC_LOADX1 \ + | FMAC_PARAMCFG_START; + + /* load the X1 buffer for input data */ + FMAC_PreLoadData(FMAC_PreloadStruct->InputDataSize, FMAC_PreloadStruct->pInputData); + + timeout = FMAC_TIMEOUT; + + while((FMAC->PARAMCFG & FMAC_PARAMCFG_START) != 0U) + { + if(0U == timeout) + { + status = ERROR; + break; + } + + timeout--; + } + } + + if(ERROR == status) + { + } + else if((NULL != FMAC_PreloadStruct->pCoeffB) && (0U != FMAC_PreloadStruct->CoeffBSize)) + { + /* configure parameter of filter preload */ + FMAC->PARAMCFG = (((uint32_t)FMAC_PreloadStruct->CoeffBSize) & FMAC_PARAMCFG_P) \ + | ((((uint32_t)FMAC_PreloadStruct->CoeffASize) << REG_BIT8_OFFSET) & FMAC_PARAMCFG_Q) \ + | FMAC_FUNC_LOADX2 \ + | FMAC_PARAMCFG_START; + /* load the X2 buffer for cofficientB */ + FMAC_PreLoadData(FMAC_PreloadStruct->CoeffBSize, FMAC_PreloadStruct->pCoeffB); + + + /* load the x2 buffer for cofficientA */ + if((NULL != FMAC_PreloadStruct->pCoeffA) && (0U != FMAC_PreloadStruct->CoeffASize)) + { + /* Load the buffer into the internal memory */ + FMAC_PreLoadData(FMAC_PreloadStruct->CoeffASize, FMAC_PreloadStruct->pCoeffA); + } + + timeout = FMAC_TIMEOUT; + + while((FMAC->PARAMCFG & FMAC_PARAMCFG_START) != 0U) + { + if(0U == timeout) + { + status = ERROR; + break; + } + + timeout--; + } + } + else + { + } + + if(ERROR == status) + { + } + else if((NULL != FMAC_PreloadStruct->pOutputData) && (0U != FMAC_PreloadStruct->OutputDataSize)) /* configure to preload output buffer */ + { + FMAC->PARAMCFG = ((uint32_t)FMAC_PreloadStruct->OutputDataSize & FMAC_PARAMCFG_P) \ + | FMAC_FUNC_LOADY \ + | FMAC_PARAMCFG_START; + + /* load the Y buffer for input data */ + FMAC_PreLoadData(FMAC_PreloadStruct->OutputDataSize, FMAC_PreloadStruct->pOutputData); + + timeout = FMAC_TIMEOUT; + + while((FMAC->PARAMCFG & FMAC_PARAMCFG_START) != 0U) + { + if(0U == timeout) + { + status = ERROR; + break; + } + + timeout--; + } + } + else + { + + } + + return status; +} + +/** +*\*\name FMAC_PreLoadStructInit. +*\*\fun Initialize the FMAC Preload struct with the default values +*\*\param FMAC_PreloadStruct : +*\*\ - pInputData +*\*\ - InputDataSize +*\*\ - pCoeffA +*\*\ - CoeffASize +*\*\ - pCoeffB +*\*\ - CoeffBSize +*\*\ - pOutputData +*\*\ - OutputDataSize +*\*\return none +**/ +void FMAC_PreLoadStructInit(FMAC_PreLoadType * FMAC_PreloadStruct) +{ + FMAC_PreloadStruct->pInputData = 0U; + FMAC_PreloadStruct->InputDataSize = 0U; + FMAC_PreloadStruct->pCoeffA = 0U; + FMAC_PreloadStruct->CoeffASize = 0U; + FMAC_PreloadStruct->pCoeffB = 0U; + FMAC_PreloadStruct->CoeffBSize = 0U; + FMAC_PreloadStruct->pOutputData = 0U; + FMAC_PreloadStruct->OutputDataSize = 0U; +} + +/** +*\*\name FMAC_ConfigParam. +*\*\fun Configure FMAC parameter +*\*\param FMAC_ParamStruct : +*\*\ - Func +*\*\ - FMAC_FUNC_LOADX1 +*\*\ - FMAC_FUNC_LOADX2 +*\*\ - FMAC_FUNC_LOADY +*\*\ - FMAC_FUNC_CONVO_FIR +*\*\ - FMAC_FUNC_IIR_DIRECT_FORM_1 +*\*\ - P +*\*\ - 0..255 +*\*\ - Q +*\*\ - 0..255 +*\*\ - R +*\*\ - 0..7 +*\*\return none +**/ +void FMAC_ConfigParam(FMAC_InitType* FMAC_ParamStruct) +{ + /* Stop execution */ + FMAC->PARAMCFG &= (~FMAC_PARAMCFG_START); + + /* Set filter parameter */ + FMAC->PARAMCFG = FMAC_ParamStruct->Func \ + | ((uint32_t)FMAC_ParamStruct->P) \ + | (((uint32_t)FMAC_ParamStruct->Q) << REG_BIT8_OFFSET) \ + | (((uint32_t)FMAC_ParamStruct->R) << REG_BIT16_OFFSET); +} + +/** +*\*\name FMAC_FilterStart. +*\*\fun Configure FMAC parameter and start filter +*\*\param FMAC_ParamStruct : +*\*\ - Func +*\*\ - FMAC_FUNC_LOADX1 +*\*\ - FMAC_FUNC_LOADX2 +*\*\ - FMAC_FUNC_LOADY +*\*\ - FMAC_FUNC_CONVO_FIR +*\*\ - FMAC_FUNC_IIR_DIRECT_FORM_1 +*\*\ - P +*\*\ - 0..255 +*\*\ - Q +*\*\ - 0..255 +*\*\ - R +*\*\ - 0..7 +*\*\return none +**/ +void FMAC_FilterStart(FMAC_InitType* FMAC_ParamStruct) +{ + /* Stop execution */ + FMAC->PARAMCFG &= (~FMAC_PARAMCFG_START); + + /* Set filter parameter and start execution */ + FMAC->PARAMCFG = FMAC_PARAMCFG_START \ + | FMAC_ParamStruct->Func \ + | ((uint32_t)FMAC_ParamStruct->P) \ + | (((uint32_t)FMAC_ParamStruct->Q) << REG_BIT8_OFFSET) \ + | (((uint32_t)FMAC_ParamStruct->R) << REG_BIT16_OFFSET); +} + +/** +*\*\name FMAC_Reset. +*\*\fun Reset FMAC, The write and read pointers, internal control logic,FAC_STS and FAC_PARAMCFG register is set to default value. +*\*\param none +*\*\return ErrorStatus: +*\*\ - SUCCESS FMAC reset done +*\*\ - ERROR FMAC reset timeout +**/ +ErrorStatus FMAC_Reset(void) +{ + uint32_t timeout = FMAC_RESET_TIMEOUT_VALUE; + ErrorStatus status = SUCCESS; + + /* Reset FMAC peripheral */ + FMAC->CTRL |= FMAC_CTRL_RESET; + + while((FMAC->CTRL & FMAC_CTRL_RESET) != 0U) + { + if(0U == timeout) + { + status = ERROR; + break; + } + + timeout--; + } + + return status; +} + +/** +*\*\name FMAC_Enable. +*\*\fun Enable or disable FMAC start execution. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FMAC_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected FMAC peripheral */ + FMAC->PARAMCFG |= FMAC_PARAMCFG_START; + } + else + { + /* Disable the selected FMAC peripheral */ + FMAC->PARAMCFG &= ~FMAC_PARAMCFG_START; + } +} + +/** +*\*\name FMAC_ConfigX1. +*\*\fun Configuration X1 paramer. +*\*\param Baseaddr +*\*\ - 0...255 +*\*\param Bufsize +*\*\ - 0...255 +*\*\param Threshold +*\*\ - FMAC_THRESHOLD1 +*\*\ - FMAC_THRESHOLD2 +*\*\ - FMAC_THRESHOLD4 +*\*\ - FMAC_THRESHOLD8 +*\*\return none +**/ +void FMAC_ConfigX1(uint8_t Baseaddr, uint8_t Bufsize, uint32_t Threshold) +{ + FMAC->X1BUFCFG = (uint32_t)Baseaddr | Threshold | ((uint32_t)Bufsize << REG_BIT8_OFFSET); +} + +/** +*\*\name FMAC_ConfigX2. +*\*\fun Configuration X2 paramer. +*\*\param Baseaddr +*\*\ - 0...255 +*\*\param Bufsize +*\*\ - 0...255 +*\*\return none +**/ +void FMAC_ConfigX2(uint8_t Baseaddr, uint8_t Bufsize) +{ + FMAC->X2BUFCFG = (uint32_t)Baseaddr | ((uint32_t)Bufsize << REG_BIT8_OFFSET); +} + +/** +*\*\name FMAC_ConfigY. +*\*\fun Configuration Y paramer. +*\*\param Baseaddr +*\*\ - 0...255 +*\*\param Bufsize +*\*\ - 0...255 +*\*\param Threshold +*\*\ - FMAC_THRESHOLD1 +*\*\ - FMAC_THRESHOLD2 +*\*\ - FMAC_THRESHOLD4 +*\*\ - FMAC_THRESHOLD8 +*\*\return none +**/ +void FMAC_ConfigY(uint8_t Baseaddr, uint8_t Bufsize, uint32_t Threshold) +{ + FMAC->YBUFCFG = (uint32_t)Baseaddr | Threshold | ((uint32_t)Bufsize << REG_BIT8_OFFSET); +} + +/** +*\*\name FMAC_WriteData +*\*\fun Write data +*\*\param none +*\*\return 16-bit data +**/ +void FMAC_WriteData(int16_t data) +{ + FMAC->WDAT = (uint32_t)data; +} + +/** +*\*\name FMAC_ReadData +*\*\fun Read output data +*\*\param none +*\*\return 16-bit data +**/ +int16_t FMAC_ReadData(void) +{ + int16_t value; + value = (int16_t)FMAC->RDAT; + return value; +} + +/** +*\*\name FMAC_EnableLimit +*\*\fun Enable or disable fmac limit +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FMAC_EnableLimit(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + FMAC->CTRL |= FMAC_LIMIT_ENABLE; + } + else + { + FMAC->CTRL &= ~FMAC_LIMIT_ENABLE; + } +} + +/** +*\*\name FMAC_EnableDma +*\*\fun Enable or disable fmac dma +*\*\param dma_req : +*\*\ - FMAC_DMA_READ: read buffer dma +*\*\ - FMAC_DMA_WRITE: write buffer dma +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FMAC_EnableDMA(uint32_t dma_req, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + FMAC->CTRL |= dma_req; + } + else + { + FMAC->CTRL &= ~dma_req; + } +} + +/** +*\*\name FMAC_ConfigInt +*\*\fun Enable or disable fmac interrupt +*\*\param interrupt : +*\*\ - FMAC_INT_READ: Read buffer interrupt +*\*\ - FMAC_INT_WRITE: Write buffer interrupt +*\*\ - FMAC_INT_OV: Overflow error interrupt +*\*\ - FMAC_INT_UN: Underflow error interrupt +*\*\ - FMAC_INT_SAT: Saturation error interrupt +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void FMAC_ConfigInt(uint32_t interrupt, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + FMAC->CTRL |= interrupt; + } + else + { + FMAC->CTRL &= ~interrupt; + } +} + +/** +*\*\name FMAC_FinishCalculate. +*\*\fun finish the filter calculate +*\*\param none +*\*\return none +**/ +ErrorStatus FMAC_FinishCalculate(void) +{ + ErrorStatus err; + + /* clear start */ + FMAC->PARAMCFG &= ~FMAC_PARAMCFG_START; + + /* disable read and write interrupt */ + CLEAR_BIT(FMAC->CTRL, FMAC_INT_READ | FMAC_INT_WRITE | FMAC_DMA_READ | FMAC_DMA_WRITE); + + /* reset register and pointer */ + if(FMAC_Reset() != SUCCESS) + { + err = ERROR; + } + else + { + err = SUCCESS; + } + + return err; +} + +/** +*\*\name FMAC_GetIntStatus +*\*\fun FMAC interrupt flag status +*\*\param IntFlag : +*\*\ - FMAC_INT_FLAG_YBUFEF: Read buffer interrupt +*\*\ - FMAC_INT_FLAG_X1BUFFF: Write buffer interrupt +*\*\ - FMAC_INT_FLAG_OVF: Overflow error interrupt +*\*\ - FMAC_INT_FLAG_UNF: Underflow error interrupt +*\*\ - FMAC_INT_FLAG_SATF: Saturation error interrupt +*\*\return none +**/ +FlagStatus FMAC_GetIntStatus(uint32_t IntFlag) +{ + FlagStatus bitstatus; + uint32_t tReg; + + if( (FMAC_INT_FLAG_YBUFEF == IntFlag) \ + || (FMAC_INT_FLAG_X1BUFFF == IntFlag) ) + { + tReg = ~(FMAC->STS); + } + else + { + tReg = FMAC->STS; + } + + tReg &= (IntFlag & FMAC_INT_FLAG_MASK); + + if(tReg == 0U) + { + bitstatus = RESET; + } + else if((FMAC->CTRL & ((IntFlag >> 16U) & FMAC_INT_FLAG_MASK)) == 0U) + { + bitstatus = RESET; + } + else + { + bitstatus = SET; + } + + return bitstatus; +} + +/** +*\*\name FMAC_GetFlagStatus +*\*\fun Get FMAC flag status +*\*\param Flag : +*\*\ - FMAC_FLAG_YBUFEF: Read buffer interrupt +*\*\ - FMAC_FLAG_X1BUFFF: Write buffer interrupt +*\*\ - FMAC_FLAG_OVF: Overflow error interrupt +*\*\ - FMAC_FLAG_UNF: Underflow error interrupt +*\*\ - FMAC_FLAG_SATF: Saturation error interrupt +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FMAC_GetFlagStatus(uint32_t Flag) +{ + FlagStatus bitstatus; + + if ((FMAC->STS & Flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_gpio.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_gpio.c new file mode 100644 index 0000000000..a23cece13b --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_gpio.c @@ -0,0 +1,2390 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_gpio.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Includes ------------------------------------------------------------------*/ +#include "n32h76x_78x_gpio.h" +#include "n32h76x_78x_rcc.h" + + +#define GPIO_MODE ((uint32_t)0x00000003) +//#define EXTI_MODE ((uint32_t)0x10000000) +//#define GPIO_MODE_IT ((uint32_t)0x00010000) +//#define GPIO_MODE_EVT ((uint32_t)0x00020000) +//#define RISING_EDGE ((uint32_t)0x00100000) +//#define FALLING_EDGE ((uint32_t)0x00200000) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) +//#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_FILT_STEGE_MASK ((uint32_t)0x0000001F) + + +/** +*\*\name GPIO_DeInit. +*\*\fun Reset the GPIOx peripheral registers to their default reset values. +*\*\param GPIOx : +*\*\ - GPIOA +*\*\ - GPIOB +*\*\ - GPIOC +*\*\ - GPIOD +*\*\ - GPIOE +*\*\ - GPIOF +*\*\ - GPIOG +*\*\ - GPIOH +*\*\ - GPIOI +*\*\ - GPIOJ +*\*\ - GPIOK +*\*\return none +*/ +void GPIO_DeInit(GPIO_Module* GPIOx) +{ + /* Configure the port pins */ + /*------------------------- GPIO Mode Configuration --------------------*/ + if (GPIOx == GPIOA) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOA); + } + else if (GPIOx == GPIOB) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOB); + } + else if (GPIOx == GPIOC) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOC); + } + else if (GPIOx == GPIOD) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOD); + } + else if (GPIOx == GPIOE) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOE); + } + else if (GPIOx == GPIOF) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOF); + } + else if (GPIOx == GPIOG) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOG); + } + else if (GPIOx == GPIOH) + { + RCC_EnableAHB5PeriphReset1(RCC_AHB5_PERIPHRST_GPIOH); + } + else if (GPIOx == GPIOI) + { + RCC_EnableAHB5PeriphReset2(RCC_AHB5_PERIPHRST_GPIOI); + } + else if (GPIOx == GPIOJ) + { + RCC_EnableAHB5PeriphReset2(RCC_AHB5_PERIPHRST_GPIOJ); + } + else if (GPIOx == GPIOK) + { + RCC_EnableAHB5PeriphReset2(RCC_AHB5_PERIPHRST_GPIOK); + } + else + { + return; + } +} + + +/** +*\*\name GPIO_InitPeripheral. +*\*\fun Initialize the GPIOx peripheral with the value of the GPIO_InitStruct structure. +*\*\param GPIOx : +*\*\ - GPIOA +*\*\ - GPIOB +*\*\ - GPIOC +*\*\ - GPIOD +*\*\ - GPIOE +*\*\ - GPIOF +*\*\ - GPIOG +*\*\ - GPIOH +*\*\ - GPIOI +*\*\ - GPIOJ +*\*\ - GPIOK +*\*\param GPIO_InitStructure : +*\*\ - Pin +*\*\ - GPIO_PIN_0 +*\*\ - GPIO_PIN_1 +*\*\ - GPIO_PIN_2 +*\*\ - GPIO_PIN_3 +*\*\ - GPIO_PIN_4 +*\*\ - GPIO_PIN_5 +*\*\ - GPIO_PIN_6 +*\*\ - GPIO_PIN_7 +*\*\ - GPIO_PIN_8 +*\*\ - GPIO_PIN_9 +*\*\ - GPIO_PIN_10 +*\*\ - GPIO_PIN_11 +*\*\ - GPIO_PIN_12 +*\*\ - GPIO_PIN_13 +*\*\ - GPIO_PIN_14 +*\*\ - GPIO_PIN_15 +*\*\ - GPIO_PIN_ALL +*\*\ - GPIO_Mode +*\*\ - GPIO_MODE_INPUT +*\*\ - GPIO_MODE_OUTPUT_PP +*\*\ - GPIO_MODE_OUTPUT_OD +*\*\ - GPIO_MODE_AF_PP +*\*\ - GPIO_MODE_AF_OD +*\*\ - GPIO_MODE_ANALOG +*\*\ - GPIO_Pull +*\*\ - GPIO_NO_PULL +*\*\ - GPIO_PULL_UP +*\*\ - GPIO_PULL_DOWN +*\*\ - GPIO_Slew_Rate +*\*\ - GPIO_SLEW_RATE_FAST +*\*\ - GPIO_SLEW_RATE_SLOW +*\*\ - GPIO_Current +*\*\ - GPIO_DC_2mA +*\*\ - GPIO_DC_4mA +*\*\ - GPIO_DC_8mA +*\*\ - GPIO_DC_12mA +*\*\ - GPIO_5VTOL_DC_1mA +*\*\ - GPIO_5VTOL_DC_2mA +*\*\ - GPIO_5VTOL_DC_4mA +*\*\ - GPIO_5VTOL_DC_6mA +*\*\ - GPIO_SDRAM_DC_1mA +*\*\ - GPIO_SDRAM_DC_2mA +*\*\ - GPIO_SDRAM_DC_4mA +*\*\ - GPIO_SDRAM_DC_5mA +*\*\ - GPIO_SDRAM_DC_8mA +*\*\ - GPIO_SDRAM_DC_12mA +*\*\ - GPIO_Alternate +*\*\ - GPIO_AF0 +*\*\ - GPIO_AF1 +*\*\ - GPIO_AF2 +*\*\ - GPIO_AF3 +*\*\ - GPIO_AF4 +*\*\ - GPIO_AF5 +*\*\ - GPIO_AF6 +*\*\ - GPIO_AF7 +*\*\ - GPIO_AF8 +*\*\ - GPIO_AF9 +*\*\ - GPIO_AF10 +*\*\ - GPIO_AF11 +*\*\ - GPIO_AF12 +*\*\ - GPIO_AF13 +*\*\ - GPIO_AF14 +*\*\ - GPIO_AF15 +*\*\ - GPIO_NO_AF +*\*\return none +**/ +void GPIO_InitPeripheral( GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct ) +{ + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + + /* Configure the port pins */ + + while ((( GPIO_InitStruct->Pin ) >> position ) != 0 ) + { + /* Get the IO position */ + iocurrent = ( GPIO_InitStruct->Pin ) & ( 1U << position ); + + if ( iocurrent ) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if (( GPIO_InitStruct->GPIO_Mode == GPIO_MODE_AF_PP) || (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_AF_OD ) || + (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_INPUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_MODE_ANALOG)) + { + /* Configure Alternate function mapped with the current IO */ + if(position & 0x08) + { + temp = GPIOx->AFH; + temp &= ~(( uint32_t )0xFU << (( uint32_t )( position & ( uint32_t )0x07U ) * 4U ) ) ; + temp |= (( uint32_t )( GPIO_InitStruct->GPIO_Alternate ) << ((( uint32_t )position & ( uint32_t )0x07U ) * 4U ) ) ; + GPIOx->AFH = temp; + } + else + { + temp = GPIOx->AFL; + temp &= ~(( uint32_t )0xFU << (( uint32_t )( position & ( uint32_t )0x07U ) * 4U ) ) ; + temp |= (( uint32_t )( GPIO_InitStruct->GPIO_Alternate ) << ((( uint32_t )position & ( uint32_t )0x07U ) * 4U ) ) ; + GPIOx->AFL = temp; + } + } + + /* In case of Output or Alternate function mode selection */ + if (( GPIO_InitStruct->GPIO_Mode == GPIO_MODE_OUTPUT_PP ) || ( GPIO_InitStruct->GPIO_Mode == GPIO_MODE_AF_PP ) || + ( GPIO_InitStruct->GPIO_Mode == GPIO_MODE_OUTPUT_OD ) || ( GPIO_InitStruct->GPIO_Mode == GPIO_MODE_AF_OD ) ) + { + /* Configure the IO Output Type */ + temp = GPIOx->POTYPE; + temp &= ~( GPIO_POTYPE_POT0 << position ) ; + temp |= ((( GPIO_InitStruct->GPIO_Mode & GPIO_OUTPUT_TYPE ) >> 4U ) << position ); + GPIOx->POTYPE = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->PMODE; + + temp &= ~( GPIO_PMODE_PMODE0 << ( position * 2U ) ); + + temp |= (( GPIO_InitStruct->GPIO_Mode & GPIO_MODE ) << ( position * 2U ) ); + + GPIOx->PMODE = temp; + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPD; + + temp &= ~( GPIO_PUPD_PUPD0 << ( position * 2U ) ); + + temp |= (( GPIO_InitStruct->GPIO_Pull ) << ( position * 2U ) ); + + GPIOx->PUPD = temp; + + /* Configure slew rate */ + temp = GPIOx->SR; + + temp &= ~(GPIO_SR_BIT_MASK << position); + + temp |= (GPIO_InitStruct->GPIO_Slew_Rate << position); + + GPIOx->SR = temp; + + /* Configure driver current */ + temp = GPIOx->DS; + + temp &= ~(GPIO_DS_BIT_MASK << ( position * 2U )); + + temp |= (GPIO_InitStruct->GPIO_Current << ( position * 2U )); + + GPIOx->DS = temp; + } + + position++; + } +} +/** + *\*\name GPIO_AFIOInitDefault. + *\*\fun Reset the AFIO peripheral registers to their default reset values. + *\*\param none + *\*\return none + */ +void GPIO_AFIOInitDefault(void) +{ + RCC_EnableAHB5PeriphReset2(RCC_AHB5_PERIPHRST_AFIO); +} +/** + *\*\name GPIO_InitStruct. + *\*\fun Assign default values to each InitStruct member. + *\*\param InitStruct : + *\*\ pointer to GPIO_InitType structure. + *\*\return none + */ +void GPIO_InitStruct(GPIO_InitType* InitStruct) +{ + /* Reset GPIO structure member */ + InitStruct->Pin = GPIO_PIN_NONE; + InitStruct->GPIO_Mode = GPIO_MODE_INPUT; + InitStruct->GPIO_Pull = GPIO_NO_PULL; + InitStruct->GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW; + InitStruct->GPIO_Current = GPIO_DC_2mA; + InitStruct->GPIO_Alternate = GPIO_NO_AF; +} + +/** + *\*\name GPIO_ReadInputDataBit. + *\*\fun Get the pin status on the specified input pin. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return the state on the input pin + */ +uint8_t GPIO_ReadInputDataBit( GPIO_Module* GPIOx, uint16_t GPIO_Pin ) +{ + uint8_t bitstatus = 0x00; + + if (( GPIOx->PID & GPIO_Pin ) != ( uint32_t )Bit_RESET ) + { + bitstatus = ( uint8_t )Bit_SET; + } + else + { + bitstatus = ( uint8_t )Bit_RESET; + } + + return bitstatus; +} + +/** + *\*\name GPIO_ReadInputData. + *\*\fun Get the input data on the designated GPIO port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\return the data value on the GPIO input port. + */ +uint16_t GPIO_ReadInputData( GPIO_Module* GPIOx ) +{ + return (( uint16_t )GPIOx->PID ); +} + +/** + *\*\name GPIO_ReadOutputDataBit. + *\*\fun Get the pin status on the specified input pin. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return the state on the input pin + */ +uint8_t GPIO_ReadOutputDataBit( GPIO_Module* GPIOx, uint16_t GPIO_Pin ) +{ + uint8_t bitstatus = 0x00; + + if (( GPIOx->POD & GPIO_Pin ) != ( uint32_t )Bit_RESET ) + { + bitstatus = ( uint8_t )Bit_SET; + } + else + { + bitstatus = ( uint8_t )Bit_RESET; + } + + return bitstatus; +} + + +/** + *\*\name GPIO_ReadOutputData. + *\*\fun Get the output data on the designated GPIO port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\return the data value on the GPIO output port. + */ +uint16_t GPIO_ReadOutputData( GPIO_Module* GPIOx ) +{ + return (( uint16_t )GPIOx->POD ); +} + +/** + *\*\name GPIO_SetBits. + *\*\fun Get the pin status on the specified input pin. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return the state on the input pin + */ +void GPIO_SetBits( GPIO_Module* GPIOx, uint16_t GPIO_Pin ) +{ + GPIOx->PBSC = GPIO_Pin; +} + +/** + *\*\name GPIO_ResetBits. + *\*\fun Reset the selected data port bits. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_ResetBits( GPIO_Module* GPIOx, uint16_t GPIO_Pin ) +{ + GPIOx->PBC = GPIO_Pin; +} + + +/** + *\*\name GPIO_WriteBit. + *\*\fun Reset the selected data port bits. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\param BitVal : + *\*\ - Bit_RESET + *\*\ - Bit_SET + *\*\return none + */ +void GPIO_WriteBit( GPIO_Module* GPIOx, uint16_t GPIO_Pin, Bit_OperateType BitVal ) +{ + if ( BitVal != Bit_RESET ) + { + GPIOx->PBSC = GPIO_Pin; + } + else + { + GPIOx->PBC = GPIO_Pin; + } +} + +/** + *\*\name GPIO_Write. + *\*\fun Write data on the designated GPIO data port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param data_value : + *\*\ the value to be written to the port output data register. + *\*\ - 0~0xFFFF + *\*\return none + */ +void GPIO_Write( GPIO_Module* GPIOx, uint16_t data_value) +{ + GPIOx->POD = data_value; +} + +/** + *\*\name GPIO_Pin_Toggle. + *\*\fun Toggle the specified port pin level. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_TogglePin(GPIO_Module *GPIOx, uint16_t Pin) +{ + GPIOx->POD ^= Pin; +} + + +/** + *\*\name GPIO_ConfigPinLock. + *\*\fun Toggle the specified port pin level. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin) +{ + __IO uint32_t tmp = GPIO_PLOCK_PLOCKK; + + if(GPIOx == GPIOK) + { + tmp = GPIO_PLOCK_PLOCKK >> 8; + } + + tmp |= Pin; + /* Set PLOCKK bit */ + GPIOx->PLOCK = tmp; + /* Reset PLOCKK bit */ + GPIOx->PLOCK = Pin; + /* Set PLOCKK bit */ + GPIOx->PLOCK = tmp; + /* Read PLOCKK bit*/ + tmp = GPIOx->PLOCK; + /* Read PLOCKK bit*/ + tmp = GPIOx->PLOCK; +} + + +/** +*\*\name GPIO_EXTILineConfig. +*\*\fun Selects the GPIO pin used as EXTI Line. +*\*\param EXTI_Line + - EXTI_LINE0 + - EXTI_LINE1 + - ...... + - EXTI_LINE15 +*\*\param GPIO_PinSource + - EXTI_GPIOA_Pin_0 + - ...... + - EXTI_GPIOA_Pin_15 + - EXTI_GPIOB_Pin_0 + - ...... + - EXTI_GPIOB_Pin_15 + - ...... + - EXTI_GPIOJ_Pin_0 + - ...... + - EXTI_GPIOJ_Pin_15 +*\*\return none +*/ +void GPIO_ConfigEXTILine(uint8_t EXTI_Line, uint8_t GPIO_PinSource) +{ + AFIO->EXTI_CFG[EXTI_Line / 4] |= GPIO_PinSource << (8 * (EXTI_Line % 4)); +} + +/** + *\*\name AFIO_ConfigSIPFLASHSEL. + *\*\fun Configure the SIP FLASH MODE SEL. + *\*\param AFIO_FLASH : + *\*\ - AFIO_FLASH0 + *\*\ - AFIO_FLASH1 + *\*\ - AFIO_FLASH2 + *\*\ - AFIO_FLASH3 + *\*\ - AFIO_FLASH4 + *\*\ - AFIO_DISFLASH + *\*\return none + */ +void AFIO_ConfigSIPFLASHSEL(uint32_t AFIO_FLASH) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + tempReg &= ~AFIO_RMP_CFG_SIP_FLASHSEL; + tempReg |= AFIO_FLASH; + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigSPINSSMode. + *\*\fun Configure the SPIx NSS mode during idle. + *\*\param AFIO_SPIx_NSS : + *\*\ - AFIO_SPI1_NSS + *\*\ - AFIO_SPI2_NSS + *\*\ - AFIO_SPI3_NSS + *\*\ - AFIO_SPI4_NSS + *\*\ - AFIO_SPI5_NSS + *\*\ - AFIO_SPI6_NSS + *\*\ - AFIO_SPI7_NSS + *\*\param NSS_Mode : + *\*\ - AFIO_SPI_NSS_HIGH_IMPEDANCE + *\*\ - AFIO_SPI_NSS_HIGH_LEVEL + *\*\return none + */ +void AFIO_ConfigSPINSSMode(uint32_t AFIO_SPIx_NSS, uint32_t NSS_Mode) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + + if(NSS_Mode != AFIO_SPI_NSS_HIGH_IMPEDANCE) + { + tempReg |= AFIO_SPIx_NSS; + } + else + { + tempReg &= ~AFIO_SPIx_NSS; + } + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_Config_EXTI_Filter. + *\*\fun Enable or disable EXTI analog filter. + *\*\param EXTI_Filter : + *\*\ - AFIO_EXTI_FILTER_ENABLE + *\*\ - AFIO_EXTI_FILTER_DISABLE + *\*\return none + */ +void AFIO_ConfigEXTIFilter(uint32_t EXTI_Filter) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG ; + + if(EXTI_Filter != AFIO_EXTI_FILTER_ENABLE) + { + tempReg |= AFIO_EXTI_FILTER_DISABLE; + } + else + { + tempReg &= ~AFIO_EXTI_FILTER_DISABLE; + } + + AFIO->RMP_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigSIPSDRAMPrior. +*\*\fun Configure SIP SDRAM prority. +*\*\param priority : +*\*\ - AFIO_SIP_SDRAM_PRIORITY_HIGH +*\*\ - AFIO_SIP_SDRAM_PRIORITY_LOW +*\*\return none +**/ +void AFIO_ConfigSIPSDRAMPrior(uint32_t priority) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + + if(priority != AFIO_SIP_SDRAM_PRIORITY_LOW) + { + tempReg |= AFIO_SIP_SDRAM_PRIORITY_HIGH; + } + else + { + tempReg &= ~AFIO_SIP_SDRAM_PRIORITY_HIGH; + } + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigSPII2SMode. + *\*\fun SEL only for pads sharing SPI/I2S. + *\*\param AFIO_SPIx_I2Sx : + *\*\ - AFIO_SELECT_SPI1 + *\*\ - AFIO_SELECT_SPI2 + *\*\ - AFIO_SELECT_SPI3 + *\*\ - AFIO_SELECT_SPI4 + *\*\param PADS_Mode : + *\*\ - SPI_MODE + *\*\ - I2S_MODE + *\*\return none + */ +void AFIO_ConfigSPII2SMode(uint32_t AFIO_SPIx_I2Sx, uint32_t PADS_Mode) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + + if(PADS_Mode != I2S_MODE) + { + tempReg |= AFIO_SPIx_I2Sx; + } + else + { + tempReg &= ~AFIO_SPIx_I2Sx; + } + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_SDMMCClkSel. + *\*\fun SDMMC clk external or feedback clk input. + *\*\param AFIO_clk_sel : + *\*\ - SDMMC1_CLKFB + *\*\ - SDMMC2_CLKFB + *\*\param cmd : + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void AFIO_SDMMCClkSel(uint32_t AFIO_clk_sel, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + + if(cmd != DISABLE) + { + tempReg |= AFIO_clk_sel; + } + else + { + tempReg &= ~AFIO_clk_sel; + } + + AFIO->RMP_CFG = tempReg; +} + + +/** + *\*\name AFIO_I2SFullpuplexSel. + *\*\fun To enable full duplex mode for I2S1-4 + *\*\param AFIO_I2S_sel : + *\*\ - I2S1_FULLDUPLEX + *\*\ - I2S2_FULLDUPLEX + *\*\ - I2S3_FULLDUPLEX + *\*\ - I2S4_FULLDUPLEX + *\*\return none + */ +void AFIO_I2SFullpuplexSel(uint32_t AFIO_clk_sel) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + + tempReg &= ~AFIO_RMP_CFG_I2S_FDUP; + tempReg |= AFIO_clk_sel; + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigXSPIBigEndian. + *\*\fun Enable or disable the big endian for XSPI XIP mode. + *\*\param AFIO_BigEndian_sel : + *\*\ - XSPI1_ENDIAN + *\*\ - XSPI2_ENDIAN + *\*\param Endian : + *\*\ - XSPI_LITTLE_ENDIAN + *\*\ - XSPI_BIG_ENDIAN + *\*\return none + */ +void AFIO_ConfigXSPIBigEndian(uint32_t xspi_endian, uint32_t Endian) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG ; + + if(Endian != XSPI_LITTLE_ENDIAN) + { + tempReg |= xspi_endian; + } + else + { + tempReg &= ~xspi_endian; + } + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigFEMCNANDSRAM. + *\*\fun To select between Nand and Sram. + *\*\param Nand_Sram_sel : + *\*\ - FEMC_NAND_SEL + *\*\ - FEMC_SRAM_SEL + *\*\return none + */ +void AFIO_ConfigFEMCNANDSRAM(uint32_t Nand_Sram_sel) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG ; + + if(Nand_Sram_sel == FEMC_NAND_SEL) + { + tempReg |= FEMC_NAND_SEL; + } + else + { + tempReg &= ~FEMC_NAND_SEL; + } + + AFIO->RMP_CFG = tempReg; +} + + +/** + *\*\name AFIO_FEMCNOByteStrobe. + *\*\fun ANDed of NBLs for Flashes do or not support byte strobes. + *\*\param Byte_Strobes_sel : + *\*\ - NO_BYTE_STROBE + *\*\ - BYTE_STROBE + *\*\return none + */ +void AFIO_FEMCNOByteStrobe(uint32_t Byte_Strobes_sel) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG ; + + if(Byte_Strobes_sel == NO_BYTE_STROBE) + { + tempReg |= NO_BYTE_STROBE; + } + else + { + tempReg &= ~NO_BYTE_STROBE; + } + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigETH1Mode. + *\*\fun For the ETH1 PHY selection. + *\*\param ETH1_PHY_sel : + *\*\ ETH1_GMII_SEL + *\*\ ETH1_RGMII_SEL + *\*\ ETH1_RMII_SEL + *\*\ ETH1_MII_SEL + *\*\return none + */ +void AFIO_ConfigETH1Mode(uint32_t ETH1_PHY_sel) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG; + + tempReg &= ~AFIO_RMP_CFG_ETH1_PHY; + + tempReg |= ETH1_PHY_sel; + + AFIO->RMP_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigETH2Mode. + *\*\fun For the ETH2 PHY selection. + *\*\param ETH2_PHY_sel : + *\*\ - ETH2_RMII_SEL + *\*\ - ETH2_MII_SEL + *\*\return none + */ +void AFIO_ConfigETH2Mode(uint32_t ETH2_PHY_sel) +{ + uint32_t tempReg; + + tempReg = AFIO->RMP_CFG ; + + if(ETH2_PHY_sel == ETH2_RMII_SEL) + { + tempReg |= ETH2_RMII_SEL; + } + else + { + tempReg &= ~ETH2_RMII_SEL; + } + + AFIO->RMP_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigSHRT1FALTPin. +*\*\fun SHRTIM1 GPIO FAULT PIN Config +*\*\param channel_pin : +*\*\ - SHRT1_FAULT_CHANNEL_PA15 +*\*\ - SHRT1_FAULT_CHANNEL_PB3 +*\*\ - SHRT1_FAULT_CHANNEL_PC11 +*\*\ - SHRT1_FAULT_CHANNEL_PD4 +*\*\ - SHRT1_FAULT_CHANNEL_PE4 +*\*\ - SHRT1_FAULT_CHANNEL_PG9 +*\*\ - SHRT1_FAULT_CHANNEL_PG10 +*\*\ - SHRT1_FAULT_CHANNEL_PI6 +*\*\ - SHRT1_FAULT_CHANNEL_PI15 +*\*\ - SHRT1_FAULT_CHANNEL_PK2 +*\*\param channel_num : +*\*\ - SHRT_FAULT_CHANNEL_1 +*\*\ - SHRT_FAULT_CHANNEL_2 +*\*\ - SHRT_FAULT_CHANNEL_3 +*\*\ - SHRT_FAULT_CHANNEL_4 +*\*\ - SHRT_FAULT_CHANNEL_5 +*\*\ - SHRT_FAULT_CHANNEL_6 +*\*\return none +**/ +void AFIO_ConfigSHRT1FALTPin(SHRT1_FAULT_CHANNEL channel_pin, SHRT_FAULT_CHANNEL_NUM channel_num) +{ + uint32_t tempReg; + + tempReg = AFIO->SHRT1_FALT_CFG; + tempReg &= ~(AFIO_SHRT1_FALT_CFG_SHRT_FALT1 << ((channel_num) * 4)); + tempReg |= channel_pin << (channel_num * 4); + AFIO->SHRT1_FALT_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigSHRT2FALTPin. +*\*\fun SHRTIM2 GPIO FAULT PIN Config +*\*\param channel_pin : +*\*\ - SHRT2_FAULT_CHANNEL_PC5 +*\*\ - SHRT2_FAULT_CHANNEL_PD1 +*\*\ - SHRT2_FAULT_CHANNEL_PD15 +*\*\ - SHRT2_FAULT_CHANNEL_PF9 +*\*\ - SHRT2_FAULT_CHANNEL_PF13 +*\*\ - SHRT2_FAULT_CHANNEL_PG1 +*\*\ - SHRT2_FAULT_CHANNEL_PI0 +*\*\ - SHRT2_FAULT_CHANNEL_PI9 +*\*\ - SHRT2_FAULT_CHANNEL_PI13 +*\*\ - SHRT2_FAULT_CHANNEL_PJ0 +*\*\ - SHRT2_FAULT_CHANNEL_PK1 +*\*\ - SHRT2_FAULT_CHANNEL_PK6 +*\*\param channel_num : +*\*\ - SHRT_FAULT_CHANNEL_1 +*\*\ - SHRT_FAULT_CHANNEL_2 +*\*\ - SHRT_FAULT_CHANNEL_3 +*\*\ - SHRT_FAULT_CHANNEL_4 +*\*\ - SHRT_FAULT_CHANNEL_5 +*\*\ - SHRT_FAULT_CHANNEL_6 +*\*\return none +**/ +void AFIO_ConfigSHRT2FALTPin(SHRT2_FAULT_CHANNEL channel_pin, SHRT_FAULT_CHANNEL_NUM channel_num) +{ + uint32_t tempReg; + + tempReg = AFIO->SHRT2_FALT_CFG; + tempReg &= ~(AFIO_SHRT2_FALT_CFG_SHRT_FALT1 << ((channel_num) * 4)); + tempReg |= channel_pin << (channel_num * 4); + AFIO->SHRT2_FALT_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigSHRT1EXEVPin. +*\*\fun SHRTIM1 external event pin Config +*\*\param channel_pin : +*\*\ - SHRT1_EXEV_CHANNEL_PB4 +*\*\ - SHRT1_EXEV_CHANNEL_PB5 +*\*\ - SHRT1_EXEV_CHANNEL_PB6 +*\*\ - SHRT1_EXEV_CHANNEL_PB7 +*\*\ - SHRT1_EXEV_CHANNEL_PC10 +*\*\ - SHRT1_EXEV_CHANNEL_PC12 +*\*\ - SHRT1_EXEV_CHANNEL_PD5 +*\*\ - SHRT1_EXEV_CHANNEL_PD8 +*\*\ - SHRT1_EXEV_CHANNEL_PD9 +*\*\ - SHRT1_EXEV_CHANNEL_PE6 +*\*\ - SHRT1_EXEV_CHANNEL_PG0 +*\*\ - SHRT1_EXEV_CHANNEL_PG11 +*\*\ - SHRT1_EXEV_CHANNEL_PG12 +*\*\ - SHRT1_EXEV_CHANNEL_PG13 +*\*\ - SHRT1_EXEV_CHANNEL_PI14 +*\*\ - SHRT1_EXEV_CHANNEL_PJ5 +*\*\ - SHRT1_EXEV_CHANNEL_PK3 +*\*\ - SHRT1_EXEV_CHANNEL_PK4 +*\*\param channel_num : +*\*\ - SHRT_EXEV_CHANNEL_1 +*\*\ - SHRT_EXEV_CHANNEL_2 +*\*\ - SHRT_EXEV_CHANNEL_3 +*\*\ - SHRT_EXEV_CHANNEL_4 +*\*\ - SHRT_EXEV_CHANNEL_5 +*\*\ - SHRT_EXEV_CHANNEL_6 +*\*\ - SHRT_EXEV_CHANNEL_7 +*\*\ - SHRT_EXEV_CHANNEL_8 +*\*\ - SHRT_EXEV_CHANNEL_9 +*\*\ - SHRT_EXEV_CHANNEL_10 +*\*\return none +**/ +void AFIO_ConfigSHRT1EXEVPin(SHRT1_EXEV_CHANNEL channel_pin, SHRT_EXEV_CHANNEL_NUM channel_num) +{ + uint32_t tempReg; + uint32_t temp_index; + + temp_index = channel_num / 5; + + tempReg = AFIO->SHRT1_EXEV_CFG[temp_index]; + + tempReg &= ~(AFIO_SHRT1_EXEV_CFG1_SHRT_EXEV1 << ((channel_num % 5) * 5)); + + tempReg |= channel_pin << ((channel_num % 5) * 5); + + AFIO->SHRT1_EXEV_CFG[temp_index] = tempReg; +} + +/** +*\*\name AFIO_ConfigSHRT2EXEVPin. +*\*\fun SHRTIM2 external event pin Config +*\*\param channel_pin : +*\*\ - SHRT2_EXEV_CHANNEL_PA2 +*\*\ - SHRT2_EXEV_CHANNEL_PC4 +*\*\ - SHRT2_EXEV_CHANNEL_PD0 +*\*\ - SHRT2_EXEV_CHANNEL_PD11 +*\*\ - SHRT2_EXEV_CHANNEL_PE3 +*\*\ - SHRT2_EXEV_CHANNEL_PE14 +*\*\ - SHRT2_EXEV_CHANNEL_PF10 +*\*\ - SHRT2_EXEV_CHANNEL_PG8 +*\*\ - SHRT2_EXEV_CHANNEL_PG15 +*\*\ - SHRT2_EXEV_CHANNEL_PH7 +*\*\ - SHRT2_EXEV_CHANNEL_PH8 +*\*\ - SHRT2_EXEV_CHANNEL_PH10 +*\*\ - SHRT2_EXEV_CHANNEL_PH11 +*\*\ - SHRT2_EXEV_CHANNEL_PH12 +*\*\ - SHRT2_EXEV_CHANNEL_PI11 +*\*\ - SHRT2_EXEV_CHANNEL_PJ2 +*\*\ - SHRT2_EXEV_CHANNEL_J14 +*\*\ - SHRT2_EXEV_CHANNEL_PK0 +*\*\param channel_num : +*\*\ - SHRT_EXEV_CHANNEL_1 +*\*\ - SHRT_EXEV_CHANNEL_2 +*\*\ - SHRT_EXEV_CHANNEL_3 +*\*\ - SHRT_EXEV_CHANNEL_4 +*\*\ - SHRT_EXEV_CHANNEL_5 +*\*\ - SHRT_EXEV_CHANNEL_6 +*\*\ - SHRT_EXEV_CHANNEL_7 +*\*\ - SHRT_EXEV_CHANNEL_8 +*\*\ - SHRT_EXEV_CHANNEL_9 +*\*\ - SHRT_EXEV_CHANNEL_10 +*\*\return none +**/ +void AFIO_ConfigSHRT2EXEVPin(SHRT2_EXEV_CHANNEL channel_pin, SHRT_EXEV_CHANNEL_NUM channel_num) +{ + uint32_t tempReg; + uint32_t temp_index; + + temp_index = channel_num / 5; + + tempReg = AFIO->SHRT2_EXEV_CFG[temp_index]; + + tempReg &= ~(AFIO_SHRT2_EXEV_CFG1_SHRT_EXEV1 << ((channel_num % 5) * 5)); + + tempReg |= channel_pin << ((channel_num % 5) * 5); + + AFIO->SHRT2_EXEV_CFG[temp_index] = tempReg; +} + +/** +*\*\name AFIO_ConfigPinTol5VGPIOA. +*\*\fun Enable or disable the PA_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PA0 +*\*\ - AFIO_TOL5V_PA0_C +*\*\ - AFIO_TOL5V_PA1 +*\*\ - AFIO_TOL5V_PA1_C +*\*\ - AFIO_TOL5V_PA2 +*\*\ - AFIO_TOL5V_PA3 +*\*\ - AFIO_TOL5V_PA4 +*\*\ - AFIO_TOL5V_PA5 +*\*\ - AFIO_TOL5V_PA6 +*\*\ - AFIO_TOL5V_PA7 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOA(uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG1; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG1 = tempReg; +} + +/** +*\*\name AFIO_ConfigPinTol5VGPIOB. +*\*\fun Enable or disable the PB_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PB0 +*\*\ - AFIO_TOL5V_PB1 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOB(uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG2; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG2 = tempReg; +} +/** +*\*\name AFIO_ConfigPinTol5VGPIOC. +*\*\fun Enable or disable the PC_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PC0 +*\*\ - AFIO_TOL5V_PC1 +*\*\ - AFIO_TOL5V_PC2 +*\*\ - AFIO_TOL5V_PC2_C +*\*\ - AFIO_TOL5V_PC3 +*\*\ - AFIO_TOL5V_PC3_C +*\*\ - AFIO_TOL5V_PC4 +*\*\ - AFIO_TOL5V_PC5 +*\*\ - AFIO_TOL5V_PC6 +*\*\ - AFIO_TOL5V_PC8 +*\*\ - AFIO_TOL5V_PC13 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOC(uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG3; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG3 = tempReg; +} + +/** +*\*\name AFIO_ConfigPinTol5VGPIOF. +*\*\fun Enable or disable the PF_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PF3 +*\*\ - AFIO_TOL5V_PF4 +*\*\ - AFIO_TOL5V_PF5 +*\*\ - AFIO_TOL5V_PF6 +*\*\ - AFIO_TOL5V_PF7 +*\*\ - AFIO_TOL5V_PF8 +*\*\ - AFIO_TOL5V_PF9 +*\*\ - AFIO_TOL5V_PF10 +*\*\ - AFIO_TOL5V_PF11 +*\*\ - AFIO_TOL5V_PF12 +*\*\ - AFIO_TOL5V_PF13 +*\*\ - AFIO_TOL5V_PF14 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOF( uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG4; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG4 = tempReg; +} + +/** +*\*\name AFIO_ConfigPinTol5VGPIOH. +*\*\fun Enable or disable the PH_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PH2 +*\*\ - AFIO_TOL5V_PH3 +*\*\ - AFIO_TOL5V_PH4 +*\*\ - AFIO_TOL5V_PH5 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOH( uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG5; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG5 = tempReg; +} + +/** +*\*\name AFIO_ConfigPinTol5VGPIOI. +*\*\fun Enable or disable the PI_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PI8 +*\*\ - AFIO_TOL5V_PI15 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOI( uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG6; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG6 = tempReg; +} + +/** +*\*\name AFIO_ConfigPinTol5VGPIOJ. +*\*\fun Enable or disable the PJ_5V tolerance. +*\*\param Pin : +*\*\ - AFIO_TOL5V_PJ0 +*\*\ - AFIO_TOL5V_PJ3 +*\*\ - AFIO_TOL5V_PJ4 +*\*\ - AFIO_TOL5V_PJ5 +*\*\ - AFIO_TOL5V_PJ6 +*\*\ - AFIO_TOL5V_PJ7 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinTol5VGPIOJ( uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->TOL5V_CFG7; + + if(cmd != DISABLE) + { + tempReg |= Pin; + } + else + { + tempReg &= ~(Pin); + } + + AFIO->TOL5V_CFG7 = tempReg; +} + +/** + *\*\name AFIO_SIPInitPeripheral. + *\*\fun Configure the Sip Pin Pull up or down + *\*\param sip_index : + *\*\ - AFIO_SIP_DAT7 + *\*\ - AFIO_SIP_DAT6 + *\*\ - AFIO_SIP_DAT5 + *\*\ - AFIO_SIP_DAT4 + *\*\ - AFIO_SIP_DAT3 + *\*\ - AFIO_SIP_DAT2 + *\*\ - AFIO_SIP_DAT1 + *\*\ - AFIO_SIP_DAT0 + *\*\param pupd : + *\*\ - AFIO_SIP_Mode_NO_PULL + *\*\ - AFIO_SIP_Mode_PULL_UP + *\*\ - AFIO_SIP_Mode_PULL_DOWN + *\*\param slew_rate : + *\*\ - SIP_Mode_FAST + *\*\ - SIP_Mode_SLOW + *\*\param driver_stength : + *\*\ - SIP_DC_2mA + *\*\ - SIP_DC_4mA + *\*\ - SIP_DC_8mA + *\*\ - SIP_DC_12mA + *\*\return none + */ +void AFIO_SIPInitPeripheral(uint8_t sip_index, uint32_t pupd, uint32_t slew_rate, uint32_t driver_stength) +{ + uint32_t temp = 0x00U; + + temp = AFIO->SIP_PUPD; + + temp &= ~(AFIO_SIP_MASK << (2 * sip_index)); + + temp |= (pupd << (2 * sip_index)); + + AFIO->SIP_PUPD = temp; + + + temp = AFIO->SIPSR; + + temp &= ~(GPIO_SR_BIT_MASK << (sip_index)); + + temp |= (slew_rate << ( sip_index)); + + AFIO->SIPSR = temp; + + temp = AFIO->SIPDS; + + temp &= ~(GPIO_DS_BIT_MASK << (2 * sip_index)); + + temp |= (driver_stength << (2 * sip_index)); + + AFIO->SIPDS = temp; +} + +/** + * @brief Configur ADC external trigger. + * @param ADCETRType choose whether to configure rule conversion or injection conversion . + * This parameter can be AFIO_ADC_ETRI and AFIO_ADC_ETRR. + * @param ADCTrigRemap specifies the external trigger line be configured. + * This parameter can be AFIO_ADC_TRIG_EXTI_x where x can be (0..15) or AFIO_ADC_TRIG_TIM8_CHy where y can be(3..4). + */ + +/** +*\*\name AFIO_ConfigADCExtLineTrigSource. +*\*\fun Configurate ADC external line trigger. +*\*\param ADC_num : +*\*\ - AFIO_ADC_1 +*\*\ - AFIO_ADC_2 +*\*\ - AFIO_ADC_3 +*\*\param ADCETRType : +*\*\ - AFIO_ADC_ETRI +*\*\ - AFIO_ADC_ETRR +*\*\param ADC_trigger : +*\*\ - AFIO_ADC_TRIG_EXTI_0 +*\*\ - AFIO_ADC_TRIG_EXTI_1 +*\*\ - AFIO_ADC_TRIG_EXTI_2 +*\*\ - AFIO_ADC_TRIG_EXTI_3 +*\*\ - AFIO_ADC_TRIG_EXTI_4 +*\*\ - AFIO_ADC_TRIG_EXTI_5 +*\*\ - AFIO_ADC_TRIG_EXTI_6 +*\*\ - AFIO_ADC_TRIG_EXTI_7 +*\*\ - AFIO_ADC_TRIG_EXTI_8 +*\*\ - AFIO_ADC_TRIG_EXTI_9 +*\*\ - AFIO_ADC_TRIG_EXTI_10 +*\*\ - AFIO_ADC_TRIG_EXTI_11 +*\*\ - AFIO_ADC_TRIG_EXTI_12 +*\*\ - AFIO_ADC_TRIG_EXTI_13 +*\*\ - AFIO_ADC_TRIG_EXTI_14 +*\*\ - AFIO_ADC_TRIG_EXTI_15 +*\*\return none +**/ +void AFIO_ConfigADCExtLineTrigSource(AFIO_ADC_NUM ADC_num, AFIO_ADC_ETRType ADCETRType, AFIO_ADC_Trig_RemapType ADCTrigRemap) +{ + uint32_t tmpregister = 0x00; + + /* Check the parameters */ + tmpregister = AFIO->ADCRMP_CFG; + + /* clear AFIO_ADCRMP_CFG register bit*/ + tmpregister &= (~(AFIO_ADCRMP_CFG_ADC3_EXTIRRSEL << (ADC_num * 8 + ADCETRType * 4))); + + /* select which external line is connected*/ + tmpregister |= ADCTrigRemap << (ADC_num * 8 + ADCETRType * 4); + + AFIO->ADCRMP_CFG = tmpregister; +} + +/** +*\*\name AFIO_ConfigADCSWPA0_C. +*\*\fun Config ADC PA0_C channel. +*\*\param ADCsw +*\*\ - ADC_SW_PA0_C_ADC2_INP0 +*\*\ - ADC_SW_PA0_C_ADC2_INP1 +*\*\ - ADC_SW_PA0_C_ADC1_INP0 +*\*\ - ADC_SW_PA0_C_ADC1_INP1 +*\*\ - ADC_SW_PA0_C_CLOSE +*\*\return none +**/ +void AFIO_ConfigADCSWPA0_C(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_PA0_C_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigADCSWPC2_C. +*\*\fun Config ADC PC2_C channel +*\*\param ADCsw +*\*\ - ADC_SW_PC2_C_ADC2_INP0 +*\*\ - ADC_SW_PC2_C_ADC2_INP1 +*\*\ - ADC_SW_PC2_C_ADC3_INP0 +*\*\ - ADC_SW_PC2_C_ADC3_INP1 +*\*\ - ADC_SW_PC2_C_CLOSE +*\*\return none +**/ +void AFIO_ConfigADCSWPC2_C(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_PC2_C_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigADCSWPC3_C. +*\*\fun Config ADC PC3_C channel +*\*\param ADCsw +*\*\ - ADC_SW_PC3_C_ADC2_INP1 +*\*\ - ADC_SW_PC3_C_ADC3_INP2 +*\*\ - ADC_SW_PC3_C_CLOSE +*\*\return none +**/ +void AFIO_ConfigADCSWPC3_C(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_PC3_C_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigADCSWPA1_C. +*\*\fun Config ADC PA1_C channel +*\*\param ADCsw +*\*\ - ADC_SW_PA1_C_ADC2_INP1 +*\*\ - ADC_SW_PA1_C_ADC1_INP1 +*\*\ - ADC_SW_PA1_C_CLOSE +*\*\return none +**/ +void AFIO_ConfigADCSWPA1_C(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_PA1_C_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigADCSWPI15. +*\*\fun Config ADC PI15 channel +*\*\param ADCsw +*\*\ - ADC_SW_PI15_ADC2_INP17 +*\*\ - ADC_SW_PI15_ADC3_INP17 +*\*\ - ADC_SW_PI15_CLOSE +*\*\return none +**/ +void AFIO_ConfigADCSWPI15(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_PI15_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWVBATEnable. +*\*\fun Enable or disable ADC VBAT channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWVBATEnable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_VBAT_ADC3_INP17; + } + else + { + tempReg &= ~ADC_SW_VBAT_ADC3_INP17; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWPJ0Enable. +*\*\fun Enable or disable ADC PJ0 channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWPJ0Enable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_PJ0_ADC2_INP16; + } + else + { + tempReg &= ~ADC_SW_PJ0_ADC2_INP16; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWPJ3Enable. +*\*\fun Enable or disable ADC PJ3 channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWPJ3Enable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_PJ3_ADC3_INP18; + } + else + { + tempReg &= ~ADC_SW_PJ3_ADC3_INP18; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWTEMPEnable. +*\*\fun Enable or disable ADC TEMP channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWTEMPEnable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_TEMP_ADC3_INP18; + } + else + { + tempReg &= ~ADC_SW_TEMP_ADC3_INP18; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWPJ4Enable. +*\*\fun Enable or disable ADC PJ4 channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWPJ4Enable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_PJ4_ADC3_INP19; + } + else + { + tempReg &= ~ADC_SW_PJ4_ADC3_INP19; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWPJ5Enable. +*\*\fun Enable or disable ADC PJ5 channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWPJ5Enable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_PJ5_ADC2_INP16; + } + else + { + tempReg &= ~ADC_SW_PJ5_ADC2_INP16; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWPJ6Enable. +*\*\fun Enable or disable ADC PJ6 channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWPJ6Enable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_PJ6_ADC3_INP18; + } + else + { + tempReg &= ~ADC_SW_PJ6_ADC3_INP18; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWPJ7Enable. +*\*\fun Enable or disable ADC PJ7 channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWPJ7Enable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_PJ7_ADC3_INP19; + } + else + { + tempReg &= ~ADC_SW_PJ7_ADC3_INP19; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ADCSWVREFEnable. +*\*\fun Enable or disable ADC VREF channel +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void AFIO_ADCSWVREFEnable(FunctionalState Cmd) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + + if (Cmd != DISABLE) + { + tempReg |= ADC_SW_VREF_ADC3_INP19; + } + else + { + tempReg &= ~ADC_SW_VREF_ADC3_INP19; + } + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigADCSWDAC246OUT. +*\*\fun Config ADC DAC2/4/6_OUT channel +*\*\param ADCsw +*\*\ - ADC_SW_DAC2_OUT_ADC2_INP17 +*\*\ - ADC_SW_DAC4_OUT_ADC2_INP17 +*\*\ - ADC_SW_DAC6_OUT_ADC2_INP17 +*\*\ - ADC_SW_DAC246_OUT_ADC2_DISABLE +*\*\return none +**/ +void AFIO_ConfigADCSWDAC246OUT(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_DAC246_OUT_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** +*\*\name AFIO_ConfigADCSWDAC135OUT. +*\*\fun Config ADC DAC1/3/5_OUT channel +*\*\param ADCsw +*\*\ - ADC_SW_DAC1_OUT_ADC2_INP16 +*\*\ - ADC_SW_DAC3_OUT_ADC2_INP16 +*\*\ - ADC_SW_DAC5_OUT_ADC2_INP16 +*\*\ - ADC_SW_DAC135_OUT_ADC2_DISABLE +*\*\return none +**/ +void AFIO_ConfigADCSWDAC135OUT(uint32_t ADCsw) +{ + uint32_t tempReg; + + tempReg = AFIO->ADCSW_CFG; + tempReg &= ~ADC_SW_DAC135_OUT_MSK; + tempReg |= ADCsw; + + AFIO->ADCSW_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigIOFilter. + *\*\fun Configure IO filter cycle which is counted in AHB clock. + *\*\param Filter_Cycle : + *\*\ - 0~127 + *\*\return none + */ +void AFIO_ConfigIOFilter(uint8_t Filter_Cycle) +{ + uint32_t tempReg; + + tempReg = AFIO->FILTER_CFG; + tempReg &= ~AFIO_FILTER_CFG_IOFLTCFG; + tempReg |= Filter_Cycle; + AFIO->FILTER_CFG = tempReg; +} + +/** + *\*\name AFIO_ConfigPinFilter. + *\*\fun Enable or disable the analog filter function for GPIOx pin. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\ - GPIOJ + *\*\ - GPIOK + *\*\param Pin : + *\*\ - GPIO_Pin_0 + *\*\ - GPIO_Pin_1 + *\*\ - GPIO_Pin_2 + *\*\ - GPIO_Pin_3 + *\*\ - GPIO_Pin_4 + *\*\ - GPIO_Pin_5 + *\*\ - GPIO_Pin_6 + *\*\ - GPIO_Pin_7 + *\*\ - GPIO_Pin_8 + *\*\ - GPIO_Pin_9 + *\*\ - GPIO_Pin_10 + *\*\ - GPIO_Pin_11 + *\*\ - GPIO_Pin_12 + *\*\ - GPIO_Pin_13 + *\*\ - GPIO_Pin_14 + *\*\ - GPIO_Pin_15 + *\*\ - GPIO_Pin_ALL + *\*\param cmd : + *\*\ - DISABLE + *\*\ - ENABLE + *\*\return none + */ +void AFIO_ConfigPinAnFilter(GPIO_Module* GPIOx, uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + uint32_t RegNum; + uint32_t BitMask; + uint32_t GPIO_Index; + + GPIO_Index = (uint32_t)GPIOx; + GPIO_Index = GPIO_GET_INDEX(GPIO_Index); + + RegNum = GPIO_Index / 2UL; + + if(GPIO_Index == 8 || GPIO_Index == 9) //GPIOI, GPIOJ + { + BitMask = Pin << (16UL * ((GPIO_Index + 1) & 0x1UL)); + } + else + { + BitMask = Pin << (16UL * (GPIO_Index & 0x1UL)); + } + + tempReg = AFIO->EFT_CFG[RegNum]; + + if(cmd != DISABLE) + { + tempReg |= BitMask; + } + else + { + tempReg &= ~(BitMask); + } + + AFIO->EFT_CFG[RegNum] = tempReg; +} +/** +*\*\name AFIO_ConfigDigitalPinFilter. +*\*\fun Enable or disable the digital filter function for GPIOx pin. +*\*\param GPIOx : +*\*\ - GPIOA +*\*\ - GPIOB +*\*\ - GPIOC +*\*\ - GPIOD +*\*\ - GPIOE +*\*\ - GPIOF +*\*\ - GPIOG +*\*\ - GPIOH +*\*\ - GPIOI +*\*\ - GPIOJ +*\*\ - GPIOK +*\*\param Pin : +*\*\ - GPIO_Pin_0 +*\*\ - GPIO_Pin_1 +*\*\ - GPIO_Pin_2 +*\*\ - GPIO_Pin_3 +*\*\ - GPIO_Pin_4 +*\*\ - GPIO_Pin_5 +*\*\ - GPIO_Pin_6 +*\*\ - GPIO_Pin_7 +*\*\ - GPIO_Pin_8 +*\*\ - GPIO_Pin_9 +*\*\ - GPIO_Pin_10 +*\*\ - GPIO_Pin_11 +*\*\ - GPIO_Pin_12 +*\*\ - GPIO_Pin_13 +*\*\ - GPIO_Pin_14 +*\*\ - GPIO_Pin_15 +*\*\ - GPIO_Pin_ALL +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigPinFilter(GPIO_Module* GPIOx, uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + uint32_t RegNum; + uint32_t BitMask; + uint32_t GPIO_Index; + + GPIO_Index = (uint32_t)GPIOx; + GPIO_Index = GPIO_GET_INDEX(GPIO_Index); + + RegNum = GPIO_Index / 2UL; + + if(GPIO_Index == 8 || GPIO_Index == 9) //GPIOI, GPIOJ + { + BitMask = Pin << (16UL * ((GPIO_Index + 1) & 0x1UL)); + } + else + { + BitMask = Pin << (16UL * (GPIO_Index & 0x1UL)); + } + + tempReg = AFIO->DIGEFT_CFG[RegNum]; + + if(cmd != DISABLE) + { + tempReg |= BitMask; + } + else + { + tempReg &= ~(BitMask); + } + + AFIO->DIGEFT_CFG[RegNum] = tempReg; +} + +/** + *\*\name AFIO_ConfigHSMODE. + *\*\fun Enable or disable HS_EN pad interface connection for SDRAM PAD model. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ - GPIOC + *\*\ - GPIOD + *\*\ - GPIOE + *\*\ - GPIOF + *\*\ - GPIOG + *\*\ - GPIOH + *\*\ - GPIOI + *\*\param Pin : + *\*\ - GPIO_Pin_0 + *\*\ - GPIO_Pin_1 + *\*\ - GPIO_Pin_2 + *\*\ - GPIO_Pin_3 + *\*\ - GPIO_Pin_4 + *\*\ - GPIO_Pin_5 + *\*\ - GPIO_Pin_6 + *\*\ - GPIO_Pin_7 + *\*\ - GPIO_Pin_8 + *\*\ - GPIO_Pin_9 + *\*\ - GPIO_Pin_10 + *\*\ - GPIO_Pin_11 + *\*\ - GPIO_Pin_12 + *\*\ - GPIO_Pin_13 + *\*\ - GPIO_Pin_14 + *\*\ - GPIO_Pin_15 + *\*\ - GPIO_Pin_ALL + *\*\param cmd : + *\*\ - DISABLE + *\*\ - ENABLE + *\*\note Most of pins support ,but some pins don't support. + *\*\return none + */ +void AFIO_ConfigHSMODE(GPIO_Module* GPIOx, uint32_t Pin, FunctionalState cmd) +{ + uint32_t tempReg; + uint32_t RegNum; + uint32_t BitMask; + uint32_t GPIO_Index; + + GPIO_Index = (uint32_t)GPIOx; + GPIO_Index = GPIO_GET_INDEX(GPIO_Index); + + RegNum = GPIO_Index / 2UL; + BitMask = Pin << (16UL * ((GPIO_Index + 1) & 0x1UL)); + tempReg = AFIO->HSMODE_CFG[RegNum]; + + if(cmd != DISABLE) + { + tempReg |= BitMask; + } + else + { + tempReg &= ~(BitMask); + } + + AFIO->HSMODE_CFG[RegNum] = tempReg; +} + +/** +*\*\name AFIO_ConfigXSPIDecNonce. +*\*\fun Set the XSPI DEC NONCE counter value. +*\*\param nonce_num +*\*\ - 0 +*\*\ - 1 +*\*\ - 2 +*\*\param data: 0x00000000~ 0xFFFFFFFF +*\*\return none +**/ +void AFIO_ConfigXSPIDecNonce(uint8_t nonce_num, u32 data) +{ + if(nonce_num == 0x00) + { + AFIO->XSPI1_NONCE0 = data; + } + else if(nonce_num == 0x01) + { + AFIO->XSPI1_NONCE1 = data; + } + else if(nonce_num == 0x02) + { + AFIO->XSPI1_NONCE2 = data; + } +} + +/** +*\*\name AFIO_ConfigSDRAMVREFRemap. +*\*\fun Config SDRAM VREF counter value. +*\*\param pin +*\*\ - AFIO_SDRAM_PIN_PA4 +*\*\ - AFIO_SDRAM_PIN_PA5 +*\*\ - AFIO_SDRAM_PIN_PA7 +*\*\ - AFIO_SDRAM_PIN_PB5 +*\*\ - AFIO_SDRAM_PIN_PB6 +*\*\ - ... +*\*\ - AFIO_SDRAM_PIN_PI7 +*\*\ - AFIO_SDRAM_PIN_PI9 +*\*\ - AFIO_SDRAM_PIN_PI10 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigSDRAMVREFRemap(AFIO_SDRAM_PIN pin, FunctionalState cmd) +{ + uint8_t temp; + uint32_t temp_reg; + + temp = pin / 32; + temp_reg = AFIO->SDRAM_VREF_EN[temp]; + + if(cmd != DISABLE) + { + temp_reg |= (uint32_t)(0x00000001) << (pin % 32); + } + else + { + temp_reg &= ~(uint32_t)(0x00000001) << (pin % 32); + } + + AFIO->SDRAM_VREF_EN[temp] = temp_reg; +} + +/** +*\*\name AFIO_ConfigSDRAMVREFData. +*\*\fun Config SDRAM VREF counter value. +*\*\param reg_index: +*\*\ - 0 +*\*\ - 1 +*\*\ - 2 +*\*\param data: when reg_index = 0 or 1, data range 0~0xFFFFFFFF, when reg_index = 2, data range 0~0x1FF +*\*\return none +**/ +void AFIO_ConfigSDRAMVREFData(uint8_t reg_index, uint32_t data) +{ + AFIO->SDRAM_VREF_EN[reg_index] = data; +} + + +/** +*\*\name AFIO_ConfigSDRAMDSNRemap. +*\*\fun Config SDRAM DSN counter value. +*\*\param pin +*\*\ - AFIO_SDRAM_PIN_PA4 +*\*\ - AFIO_SDRAM_PIN_PA5 +*\*\ - AFIO_SDRAM_PIN_PA7 +*\*\ - AFIO_SDRAM_PIN_PB5 +*\*\ - AFIO_SDRAM_PIN_PB6 +*\*\ - ... +*\*\ - AFIO_SDRAM_PIN_PI7 +*\*\ - AFIO_SDRAM_PIN_PI9 +*\*\ - AFIO_SDRAM_PIN_PI10 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigSDRAMDSNRemap(AFIO_SDRAM_PIN pin, FunctionalState cmd) +{ + uint8_t temp; + uint32_t temp_reg; + + temp = pin / 32; + temp_reg = AFIO->SDRAMDSN_CFG[temp]; + + if(cmd != DISABLE) + { + temp_reg |= (uint32_t)(0x00000001) << (pin % 32); + } + else + { + temp_reg &= ~(uint32_t)(0x00000001) << (pin % 32); + } + + AFIO->SDRAMDSN_CFG[temp] = temp_reg; +} + +/** +*\*\name AFIO_ConfigSDRAMDSNData. +*\*\fun Config SDRAM DSN counter value. +*\*\param reg_index: +*\*\ - 0 +*\*\ - 1 +*\*\ - 2 +*\*\param data: when reg_index = 0 or 1, data range 0~0xFFFFFFFF, when reg_index = 2, data range 0~0x1FF +*\*\return none +**/ +void AFIO_ConfigSDRAMDSNData(uint8_t reg_index, uint32_t data) +{ + AFIO->SDRAMDSN_CFG[reg_index] = data; +} + +/** +*\*\name AFIO_ConfigSDRAMDSPRemap. +*\*\fun Config SDRAM DSP counter value. +*\*\param pin +*\*\ - AFIO_SDRAM_PIN_PA4 +*\*\ - AFIO_SDRAM_PIN_PA5 +*\*\ - AFIO_SDRAM_PIN_PA7 +*\*\ - AFIO_SDRAM_PIN_PB5 +*\*\ - AFIO_SDRAM_PIN_PB6 +*\*\ - ... +*\*\ - AFIO_SDRAM_PIN_PI7 +*\*\ - AFIO_SDRAM_PIN_PI9 +*\*\ - AFIO_SDRAM_PIN_PI10 +*\*\param cmd : +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void AFIO_ConfigSDRAMDSPRemap(AFIO_SDRAM_PIN pin, FunctionalState cmd) +{ + uint8_t temp; + uint32_t temp_reg; + + temp = pin / 32; + temp_reg = AFIO->SDRAMDSP_CFG[temp]; + + if(cmd != DISABLE) + { + temp_reg |= (uint32_t)(0x00000001) << (pin % 32); + } + else + { + temp_reg &= ~(uint32_t)(0x00000001) << (pin % 32); + } + + AFIO->SDRAMDSP_CFG[temp] = temp_reg; +} + +/** +*\*\name AFIO_ConfigSDRAMDSPData. +*\*\fun Config SDRAM DSP counter value. +*\*\param reg_index: +*\*\ - 0 +*\*\ - 1 +*\*\ - 2 +*\*\param data: when reg_index = 0 or 1, data range 0~0xFFFFFFFF, when reg_index = 2, data range 0~0x1FF +*\*\return none +**/ +void AFIO_ConfigSDRAMDSPData(uint8_t reg_index, uint32_t data) +{ + AFIO->SDRAMDSP_CFG[reg_index] = data; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2c.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2c.c new file mode 100644 index 0000000000..7f271ee44e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2c.c @@ -0,0 +1,1733 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_i2c.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_i2c.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name I2C_DeInit. +*\*\fun Deinitializes the I2Cx peripheral registers to their default reset values. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\return None +**/ +void I2C_DeInit(I2C_Module* I2Cx) +{ + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_EnableAPB1PeriphReset4(RCC_APB1_PERIPHRST_I2C1); + } + else if (I2Cx == I2C2) + { + /* Enable I2C2 reset state */ + RCC_EnableAPB1PeriphReset4(RCC_APB1_PERIPHRST_I2C2); + } + else if (I2Cx == I2C3) + { + /* Enable I2C3 reset state */ + RCC_EnableAPB1PeriphReset4(RCC_APB1_PERIPHRST_I2C3); + } + else if (I2Cx == I2C4) + { + /* Enable I2C4 reset state */ + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_I2C4); + } + else if (I2Cx == I2C5) + { + /* Enable I2C5 reset state */ + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_I2C5); + } + else if (I2Cx == I2C6) + { + /* Enable I2C6 reset state */ + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_I2C6);; + } + else if (I2Cx == I2C7) + { + /* Enable I2C7 reset state */ + RCC_EnableAPB5PeriphReset2(RCC_APB5_PERIPHRST_I2C7); + } + else if (I2Cx == I2C8) + { + /* Enable I2C8 reset state */ + RCC_EnableAPB5PeriphReset2(RCC_APB5_PERIPHRST_I2C8); + } + else if (I2Cx == I2C9) + { + /* Enable I2C9 reset state */ + RCC_EnableAPB5PeriphReset2(RCC_APB5_PERIPHRST_I2C9); + } + else + { + /* Enable I2C10 reset state */ + RCC_EnableAPB5PeriphReset2(RCC_APB5_PERIPHRST_I2C10); + } + +} + + + +/** +*\*\name I2C_Init. +*\*\fun Initializes the I2C peripheral according to the specified parameters in the I2C_InitStruct. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param I2C_InitStruct (The input parameters must be the following values): +*\*\ - Timing +*\*\ - HSTiming +*\*\ - OwnAddress1: +*\*\ - between 0 to 0x3FF +*\*\ - AddressingMode(only for Address1): +*\*\ - I2C_ADDRESSINGMODE_7BIT +*\*\ - I2C_ADDRESSINGMODE_10BIT +*\*\ - DualAddressMode: +*\*\ - I2C_DUALADDRESS_DISABLE +*\*\ - I2C_DUALADDRESS_ENABLE +*\*\ - OwnAddress2: +*\*\ - between 0 to 0xFF +*\*\ - OwnAddress2Masks: +*\*\ - I2C_ADDRESS2MASK_NONE AD2[7:1] are compared. +*\*\ - I2C_ADDRESS2MASK_1 AD2[1] dont care. Only AD2[7:2] are compared. +*\*\ - I2C_ADDRESS2MASK_2_1 AD2[2:1] dont care. Only AD2[7:3] are compared. +*\*\ - I2C_ADDRESS2MASK_3_1 AD2[3:1] dont care. Only AD2[7:4] are compared. +*\*\ - I2C_ADDRESS2MASK_4_1 AD2[4:1] dont care. Only AD2[7:5] are compared. +*\*\ - I2C_ADDRESS2MASK_5_1 AD2[5:1] dont care. Only AD2[7:6] are compared. +*\*\ - I2C_ADDRESS2MASK_6_1 AD2[6:1] dont care. Only AD2[7] is compared. +*\*\ - I2C_ADDRESS2MASK_7_1 AD2[7:1] dont care. No comparison is done. +*\*\ - GeneralCallMode: +*\*\ - I2C_GENERALCALL_DISABLE +*\*\ - I2C_GENERALCALL_ENABLE +*\*\ - NoStretchMode: +*\*\ - I2C_NOSTRCH_DISABLE +*\*\ - I2C_NOSTRCH_ENABLE +*\*\return Status +**/ +void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct) +{ + uint32_t temp_value; + + /* Disable the selected I2C peripheral */ + I2C_Enable(I2Cx, DISABLE); + + /*---------------------------- I2Cx BUSTIM Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + I2Cx->BUSTIM = I2C_InitStruct->Timing & TIMING_CLEAR_MASK; + I2Cx->HSBUSTM = I2C_InitStruct->HSTiming & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx ADR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + I2Cx->ADR1 &= (~I2C_ADR1_AD1EN); + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (I2C_InitStruct->AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + I2Cx->ADR1 = (I2C_ADR1_AD1EN | I2C_InitStruct->OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + I2Cx->ADR1 = (I2C_ADR1_AD1EN | I2C_ADR1_AD1MODE | I2C_InitStruct->OwnAddress1); + } + + /*---------------------------- I2Cx CTRL2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (I2C_InitStruct->AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + I2Cx->CTRL2 |= (I2C_CTRL2_ADR10); + } + + /*---------------------------- I2Cx ADR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + I2Cx->ADR2 &= (~I2C_DUALADDRESS_ENABLE); + /* Configure I2Cx: Dual mode and Own Address2 */ + I2Cx->ADR2 = (I2C_InitStruct->DualAddressMode | I2C_InitStruct->OwnAddress2 | I2C_InitStruct->OwnAddress2Masks); + + /*---------------------------- I2Cx CTRL1 Configuration ----------------------*/ + temp_value = I2Cx->CTRL1; + temp_value &= CTRL1_CLEAR_MASK; + /* Configure I2Cx: Generalcall and NoStretch mode */ + temp_value |= (I2C_InitStruct->GeneralCallMode | I2C_InitStruct->NoStretchMode); + I2Cx->CTRL1 = temp_value; + + /*--------------------------------------------------------------------------------*/ + /* Enable the selected I2C peripheral */ + I2C_Enable(I2Cx, ENABLE); + +} + +/** +*\*\name I2C_Initializes_Structure. +*\*\fun Fills each I2C_InitStruct member with its default value. +*\*\param (The input parameters must be the following values): +*\*\ - Timing +*\*\ - HSTiming +*\*\ - OwnAddress1 +*\*\ - AddressingMode +*\*\ - DualAddressMode +*\*\ - OwnAddress2 +*\*\ - OwnAddress2Masks +*\*\ - GeneralCallMode +*\*\ - NoStretchMode +*\*\return none +**/ +void I2C_InitStruct(I2C_InitType* I2C_StructInit) +{ + /*Reset I2C init structure parameters values */ + I2C_StructInit->Timing = 0x50012526; + I2C_StructInit->HSTiming = 0x0; + I2C_StructInit->OwnAddress1 = 0x0; + I2C_StructInit->AddressingMode = I2C_ADDRESSINGMODE_7BIT; + I2C_StructInit->DualAddressMode = I2C_DUALADDRESS_DISABLE; + I2C_StructInit->OwnAddress2 = 0x0; + I2C_StructInit->OwnAddress2Masks = I2C_ADDRESS2MASK_NONE; + I2C_StructInit->GeneralCallMode = I2C_GENERALCALL_DISABLE; + I2C_StructInit->NoStretchMode = I2C_NOSTRCH_DISABLE; + +} + +/** +*\*\name I2C_Enable. +*\*\fun Enables or disables the specified I2C peripheral. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= CTRL1_SPEN_SET; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CTRL1 &= CTRL1_SPEN_RESET; + } +} + +/** +*\*\name I2C_ConfigSendAddress. +*\*\fun Configure slave address and transfer direction in master mode. +*\*\param I2Cx (The input parameters must be the following values): +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param address (The input parameters must be the following values) +*\*\ - 0 to 0x3FF +*\*\param mode (The input parameters must be the following values): +*\*\ - I2C_DIRECTION_SEND Transmitter mode +*\*\ - I2C_DIRECTION_RECV Receiver mode +*\*\return none +**/ +void I2C_ConfigSendAddress(I2C_Module* I2Cx, uint32_t address, uint32_t direction) +{ + uint32_t temp_value; + + temp_value = I2Cx->CTRL2; + temp_value &= I2C_SADR_RWN_MASK; + /* Test on the direction to set/reset the read/write bit */ + temp_value |= ((address & I2C_SADR_MASK) | direction); + + I2Cx->CTRL2 = temp_value; +} + +/** +*\*\name I2C_Enable10bitAddressHeader. +*\*\fun 10-bit address header executes complete sequence in master receive mode. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_Enable10bitAddressHeader(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL2 |= CTRL2_HDR10_ENABLE; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL2 &= CTRL2_HDR10_DISABLE; + } +} + +/** +*\*\name I2C_EnableAutomaticEnd. +*\*\fun Enable I2C automatic end mode in master mode. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableAutomaticEnd(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL2 |= CTRL2_AUTO_STOP; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL2 &= CTRL2_SOFTWARE_STOP; + } +} + +/** +*\*\name I2C_EnableReload. +*\*\fun Enable I2C reload mode. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableReload(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL2 |= CTRL2_REFILL_ENABLE; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL2 &= CTRL2_REFILL_DISABLE; + } +} + + +/** +*\*\name I2C_GenerateStart. +*\*\fun Generates I2Cx communication START condition. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Generate a START condition */ + I2Cx->CTRL2 |= CTRL2_START_ENABLE; + } + else + { + /* Disable the START condition generation */ + I2Cx->CTRL2 &= CTRL2_START_DISABLE; + } +} + +/** +*\*\name I2C_GenerateStop. +*\*\fun Generates I2Cx communication STOP condition. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CTRL2 |= CTRL2_STOP_ENABLE; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CTRL2 &= CTRL2_STOP_DISABLE; + } +} + + +/** +*\*\name I2C_ConfigAck. +*\*\fun Enables or disables the specified I2C acknowledge feature. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CTRL2 &= CTRL2_ACK; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CTRL2 |= CTRL2_NACK; + } +} + + +/** +*\*\name I2C_ConfigOwnAddr2. +*\*\fun Configures the specified I2C own address2. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Address +*\*\ - 7bit I2C own address2 +*\*\return none +**/ +void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address) +{ + uint32_t tmpregister; + + /* Get the old register value */ + tmpregister = I2Cx->ADR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpregister &= ADR2_AD2_RESET; + + /* Set I2Cx Own address2 */ + tmpregister |= (uint16_t)((uint16_t)Address & ADR2_AD2_SET); + + /* Store the new register value */ + I2Cx->ADR2 = tmpregister; +} + + +/** +*\*\name I2C_EnableDualAddr. +*\*\fun Enables or disables the specified I2C dual addressing mode. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->ADR2 |= ADR2_ENABLE; + } + else + { + /* Disable dual addressing mode */ + I2Cx->ADR2 &= ADR2_DISABLE; + } +} + + +/** +*\*\name I2C_EnableGeneralCall. +*\*\fun Enables or disables the specified I2C general call feature. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable generall call */ + I2Cx->CTRL1 |= CTRL1_GENC_SET; + } + else + { + /* Disable generall call */ + I2Cx->CTRL1 &= CTRL1_GENC_RESET; + } +} + +/** +*\*\name I2C_EnableSlaveByteControl. +*\*\fun Enables or disables slave byte control. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSlaveByteControl(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CTRL1 |= CTRL1_SBCTL_SET; + } + else + { + /* Disable slave byte control */ + I2Cx->CTRL1 &= CTRL1_SBCTL_RESET; + } +} + +/** +*\*\name I2C_EnableSMBusAlert. +*\*\fun Enables or disables SMBus alert. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSMBusAlert(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CTRL1 |= CTRL1_ALRTEN_SET; + } + else + { + /* Disable slave byte control */ + I2Cx->CTRL1 &= CTRL1_ALRTEN_RESET; + } +} + +/** +*\*\name I2C_EnableSMBusDefaultAddr. +*\*\fun Enables or disables SMBus device default address. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSMBusDefaultAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CTRL1 |= CTRL1_SMBD_SET; + } + else + { + /* Disable slave byte control */ + I2Cx->CTRL1 &= CTRL1_SMBD_RESET; + } +} + +/** +*\*\name I2C_EnableSMBusHostAddr. +*\*\fun Enables or disables SMBus host address. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSMBusHostAddr(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CTRL1 |= CTRL1_SMBH_SET; + } + else + { + /* Disable slave byte control */ + I2Cx->CTRL1 &= CTRL1_SMBH_RESET; + } +} + +/** +*\*\name I2C_SendData. +*\*\fun Sends a data byte through the I2Cx peripheral. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Data +*\*\return none +**/ +void I2C_SendData(I2C_Module* I2Cx, uint8_t Data) +{ + /* Write in the DAT register the data to be sent */ + I2Cx->WDR = Data; +} + +/** +*\*\name I2C_RecvData. +*\*\fun Returns the most recent received data by the I2Cx peripheral. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\return The value of the received data +**/ +uint8_t I2C_RecvData(I2C_Module* I2Cx) +{ + /* Return the data in the DAT register */ + return (uint8_t)I2Cx->RDR; +} + + +/** +*\*\name I2C_SendCRC. +*\*\fun Enables or disables the specified I2C CRC transfer. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_SendCRC(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected I2C CRC transmission */ + I2Cx->CTRL2 |= CTRL2_CRCBYTE_ENABLE; + } + else + { + /* Disable the selected I2C CRC transmission */ + I2Cx->CTRL2 &= CTRL2_CRCBYTE_DISABLE; + } +} + +/** +*\*\name I2C_EnableCRC. +*\*\fun Enables or disables the CRC value calculation of the transferred bytes. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableCRC(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CTRL1 |= CTRL1_CRCEN_SET; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CTRL1 &= CTRL1_CRCEN_RESET; + } +} + + + +/** +*\*\name I2C_EnableQuickCommand. +*\*\fun Enables or disables Quick Command(For Master or Slave mode). +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableQuickCommand(I2C_Module* I2Cx, FunctionalState Cmd) +{ + + if( Cmd == DISABLE) + { + I2Cx->QCMD &= QCMD_DISABLE; + } + else + { + I2Cx->QCMD |= QCMD_ENABLE; + } +} + +/** +*\*\name I2C_ConfigQuickCommandAddr. +*\*\fun Configures SMB Quick command address(For Slave mode only). +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Address +*\*\ - 7bit own address +*\*\return none +**/ +void I2C_ConfigQuickCommandAddr(I2C_Module* I2Cx, uint8_t Address) +{ + uint32_t tmpregister; + + /* Get the old register value */ + tmpregister = I2Cx->QCMD; + + /* Reset address bit [6:1] */ + tmpregister &= QCMDAD_MASK; + + /* Set address */ + tmpregister |= Address; + + /* Store the new register value */ + I2Cx->QCMD = tmpregister; +} + +/** +*\*\name I2C_EnableTXFIFO. +*\*\fun Enables or disables the TX FIFO. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableTXFIFO(I2C_Module* I2Cx, FunctionalState Cmd) +{ + + if( Cmd == DISABLE) + { + I2Cx->FIFOCSR &= TFE_DISABLE; + } + else + { + I2Cx->FIFOCSR |= TFE_ENABLE; + } +} + +/** +*\*\name I2C_EnableRXFIFO. +*\*\fun Enables or disables the RX FIFO. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableRXFIFO(I2C_Module* I2Cx, FunctionalState Cmd) +{ + + if( Cmd == DISABLE) + { + I2Cx->FIFOCSR &= RFE_DISABLE; + } + else + { + I2Cx->FIFOCSR |= RFE_ENABLE; + } +} + +/** +*\*\name I2C_EnableTXDMA. +*\*\fun Enables or disables the TX DMA request. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableTXDMA(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->CTRL1 &= CTRL1_DMAWREN_TRANSMISSION_RESET; + } + else + { + I2Cx->CTRL1 |= CTRL1_DMAWREN_TRANSMISSION_SET; + } +} + +/** +*\*\name I2C_EnableRXDMA. +*\*\fun Enables or disables the RX DMA request. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableRXDMA(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->CTRL1 &= CTRL1_DMARDEN_RECEPTION_RESET; + } + else + { + I2Cx->CTRL1 |= CTRL1_DMARDEN_RECEPTION_SET; + } +} + + +/** +*\*\name I2C_SetTransferByteNumber. +*\*\fun Set the number of data bytes that will be transferred of I2C peripheral. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Number_Of_bytes: +*\*\ - 0 ~ 255 +*\*\return none +*\*\note The number of bytes is greater than or equal to 2. +**/ +void I2C_SetTransferByteNumber(I2C_Module* I2Cx, uint8_t Number_Of_bytes) +{ + uint32_t temp_value; + + temp_value = I2Cx->CTRL2; + temp_value &= (BYTENUM_Mask); + temp_value |= ((uint32_t)Number_Of_bytes << 16); + I2Cx->CTRL2 = temp_value; + +} + + +/** +*\*\name I2C_SetTXFIFO_ILEVEL. +*\*\fun Config TX FIFO empty level. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param TX_ILEVEL: +*\*\ - 0 ~ 15 +*\*\return none +**/ +void I2C_SetTXFIFO_ILEVEL(I2C_Module* I2Cx, uint8_t TX_ILEVEL) +{ + uint32_t temp_value; + + /* Config TX FIFO emptly level */ + temp_value = I2Cx->FIFOCSR; + temp_value &= (FIFO_TX_ILEVEL_Mask); + temp_value |= (((uint32_t)TX_ILEVEL & 0xF) << 24); + I2Cx->FIFOCSR = temp_value; +} + +/** +*\*\name I2C_SetRXFIFO_ILEVEL. +*\*\fun Config RX FIFO level to generate interrupt. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param RX_ILEVEL: +*\*\ - 0 ~ 15 +*\*\return none +**/ +void I2C_SetRXFIFO_ILEVEL(I2C_Module* I2Cx, uint8_t RX_ILEVEL) +{ + uint32_t temp_value; + + /* Config RX FIFO emptly level */ + temp_value = I2Cx->FIFOCSR; + temp_value &= (FIFO_RX_ILEVEL_Mask); + temp_value |= (((uint32_t)RX_ILEVEL & 0xF) << 16); + I2Cx->FIFOCSR = temp_value; +} + +/** +*\*\name I2C_GetTXFIFO_FLEVEL. +*\*\fun Returns TX FIFO data number. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\return FIFO data. +**/ +uint8_t I2C_GetTXFIFO_FLEVEL(I2C_Module* I2Cx) +{ + uint32_t tmpregister; + + /* Return the data in the FIFODAT register */ + tmpregister = ((I2Cx->FIFOCSR & FIFO_TX_FLEVEL_Mask) >> 8); + + return (uint8_t)tmpregister; +} + +/** +*\*\name I2C_GetRXFIFO_FLEVEL. +*\*\fun Returns RX FIFO data number. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\return FIFO data. +**/ +uint8_t I2C_GetRXFIFO_FLEVEL(I2C_Module* I2Cx) +{ + uint32_t tmpregister; + + /* Return the data in the FIFODAT register */ + tmpregister = (I2Cx->FIFOCSR & FIFO_RX_FLEVEL_Mask); + + return (uint8_t)tmpregister; +} + +/** +*\*\name I2C_EnableSCLTimeoutDetection. +*\*\fun Enable or disable clk timeout. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSCLTimeoutDetection(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->TMOUTR &= ~TMOUTEN_ENABLE; + } + else + { + I2Cx->TMOUTR |= TMOUTEN_ENABLE; + } +} + +/** +*\*\name I2C_EnableExtenClkTimeout. +*\*\fun Enable or disable extended clk timeout. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableExtenClkTimeout(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->TMOUTR &= ~TMEXTEN_ENABLE; + } + else + { + I2Cx->TMOUTR |= TMEXTEN_ENABLE; + } +} + +/** +*\*\name I2C_SetBusTimeoutA. +*\*\fun Configure bus timeout A. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param bus_timeout +*\*\ - 0x0 ~ 0xFFF +*\*\return none +**/ +void I2C_SetBusTimeoutA(I2C_Module* I2Cx, uint32_t bus_timeout) +{ + uint32_t temp_value; + + temp_value = I2Cx->TMOUTR; + temp_value &= I2C_TMOUTA_MASK; + temp_value |= (bus_timeout & 0xFFFU); + I2Cx->TMOUTR = temp_value; +} + +/** +*\*\name I2C_SetBusTimeoutB. +*\*\fun Configure bus timeout B. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param bus_timeout +*\*\ - 0x0 ~ 0xFFF +*\*\return none +**/ +void I2C_SetBusTimeoutB(I2C_Module* I2Cx, uint32_t bus_timeout) +{ + uint32_t temp_value; + + temp_value = I2Cx->TMOUTR; + temp_value &= I2C_TMOUTB_MASK; + temp_value |= ((bus_timeout << 16) & 0xFFF0000U); + I2Cx->TMOUTR = temp_value; +} + +/** +*\*\name I2C_ConfigIdleClockTimeout. +*\*\fun Configure idle clock timeout detection. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param bus_timeout +*\*\ - I2C_TMOUTA_DETECT_SCL_LOW +*\*\ - I2C_TMOUTA_DETECT_BUS_IDLE +*\*\return none +**/ +void I2C_ConfigIdleClockTimeout(I2C_Module* I2Cx, uint32_t bus_timeout) +{ + uint32_t temp_value; + + temp_value = I2Cx->TMOUTR; + temp_value &= (~I2C_TMOUTA_DETECT_BUS_IDLE); + temp_value |= bus_timeout; + I2Cx->TMOUTR = temp_value; +} + +/** +*\*\name I2C_EnableAnalogFilter. +*\*\fun Enables or disables Analog Filter. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableAnalogFilter(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->CTRL1 |= CTRL1_AF_SET; + } + else + { + I2Cx->CTRL1 &= CTRL1_AF_RESET; + } +} +/** +*\*\name I2C_Enable_SDA_Analog_Filter. +*\*\fun Enables or disables SDA Analog Filter. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSDAAnalogFilter(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->GFLTRCTRL |= SDAAFENN_ENABLE; + + } + else + { + I2Cx->GFLTRCTRL &= SDAAFENN_DISABLE ; + } +} + +/** +*\*\name I2C_EnableSCLAnalogFilter. +*\*\fun Enables or disables SCL Analog Filter. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_EnableSCLAnalogFilter(I2C_Module* I2Cx, FunctionalState Cmd) +{ + if( Cmd == DISABLE) + { + I2Cx->GFLTRCTRL |= SCLAFENN_ENABLE; + } + else + { + + I2Cx->GFLTRCTRL &= SCLAFENN_DISABLE ; + } +} + + +/** +*\*\name I2C_SetSCLAnalogFilterWidth. +*\*\fun SCL analog filter width selection. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param width : +*\*\ - I2C_ANALOG_FILTER_WIDTH_5NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_15NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_25NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_35NS +*\*\return none +**/ +void I2C_SetSCLAnalogFilterWidth(I2C_Module* I2Cx, uint32_t width) +{ + uint32_t temp_value; + + temp_value = I2Cx->GFLTRCTRL; + /* Clear SCLAFW[1:0] bits */ + temp_value &= I2C_SCLAFW_MASK; + /* Set SCLAFW[1:0] bits according to width value */ + temp_value |= (width << 4); + /* Store the new value */ + I2Cx->GFLTRCTRL = temp_value; + +} + + +/** +*\*\name I2C_SetSDAAnalogFilterWidth. +*\*\fun SDA analog filter width selection. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param width : +*\*\ - I2C_ANALOG_FILTER_WIDTH_5NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_15NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_25NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_35NS +*\*\return none +**/ +void I2C_SetSDAAnalogFilterWidth(I2C_Module* I2Cx, uint32_t width) +{ + uint32_t temp_value; + + temp_value = I2Cx->GFLTRCTRL; + /* Clear SDAAFW[1:0] bits */ + temp_value &= I2C_SDAAFW_MASK; + /* Set SDAAFW[1:0] bits according to width value */ + temp_value |= width; + /* Store the new value */ + I2Cx->GFLTRCTRL = temp_value; + +} + + +/** +*\*\name I2C_SetDigitalFilterWidth. +*\*\fun SCL digital filter width selection. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param width : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x001 ~ 0x3FF The numbers which filters spikes with a length of up to DF10{DFX,DF} *tI2CCLK. + Details pls check I2C user manual. +*\*\return none +**/ +void I2C_SetDigitalFilterWidth(I2C_Module* I2Cx, uint32_t width) +{ + uint32_t temp_value; + + temp_value = I2Cx->CTRL1; + /* Clear DFX[29:24] bits and DF[11:8] bits */ + temp_value &= (CTRL1_DF10_RESET); + + /* Set DFX[29:24] bits and DF[11:8] bits according to width value */ + temp_value |= (((width & 0xF) << 8) | ((width & 0x3F0) << 20)); + /* Store the new value */ + I2Cx->CTRL1 = temp_value; + +} + +/** +*\*\name I2C_ClrFlag. +*\*\fun Clears the I2Cx's pending flags. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param I2C_FLAG : +*\*\ - I2C_FLAG_ADR Address matched(Slave mode) +*\*\ - I2C_FLAG_NAKF NACK flag received +*\*\ - I2C_FLAG_STOPF STOP detection flag +*\*\ - I2C_FLAG_BSER BUS Error flag +*\*\ - I2C_FLAG_ABLO Arbitration lost flag +*\*\ - I2C_FLAG_OVF Overrun/Underrun flag(Slave mode) +*\*\ - I2C_FLAG_CRCERR CRC Error flag in reception +*\*\ - I2C_FLAG_TMOUT Timeout or tLOW detection flag +*\*\ - I2C_FLAG_ALRT SMBUS alert flag +*\*\return none +**/ +void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + /* Clear the selected I2C flag */ + I2Cx->INTCLR |= I2C_FLAG; +} + + +/** +*\*\name I2C_ConfigInt. +*\*\fun Enables or disables the specified I2C interrupts. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param I2C_IT : +*\*\ - I2C_INT_WDR TX interrupt enable +*\*\ - I2C_INT_RDR RX interrupt enable +*\*\ - I2C_INT_ADR Address match interrupt enable +*\*\ - I2C_INT_NACK Not acknowledge received Interrupt enable +*\*\ - I2C_INT_STOP Stop detection interrupt enable +*\*\ - I2C_INT_TFC Transfer complete interrupt enable +*\*\ - I2C_INT_ERR Error interrupt enable +*\*\ - I2C_INT_RXFIFO FIFO RX interrupt enable +*\*\ - I2C_INT_TXFIFO FIFO TX interrupt enable +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2C_ConfigInt(I2C_Module* I2Cx, uint32_t I2C_IT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CTRL1 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CTRL1 &= (uint32_t)~I2C_IT; + } +} + +/** +*\*\name I2C_GetCRC. +*\*\fun Get the PEC value for the specified I2C. +*\*\param I2Cx (The input parameters must be the following values): +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\return The PEC value +**/ +uint8_t I2C_GetCRC(I2C_Module* I2Cx) +{ + /* Return the selected I2C PEC value */ + return (uint8_t)(I2Cx->CRCR); +} + +/** +*\*\name I2C_GetReceiveAddress. +*\*\fun Get the received address value for the specified I2C. +*\*\param I2Cx (The input parameters must be the following values): +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\return The received address value +**/ +uint8_t I2C_GetReceiveAddress(I2C_Module* I2Cx) +{ + /* Return the selected I2C PEC value */ + return (uint8_t)((I2Cx->STSINT & STSINT_ADRRCV_MASK) >> 17); +} + +/** +*\*\name I2C_GetFlag. +*\*\fun Checks whether the specified I2C flag is set or not. +*\*\param I2Cx : +*\*\ - I2C1 +*\*\ - I2C2 +*\*\ - I2C3 +*\*\ - I2C4 +*\*\ - I2C5 +*\*\ - I2C6 +*\*\ - I2C7 +*\*\ - I2C8 +*\*\ - I2C9 +*\*\ - I2C10 +*\*\param I2C_FLAG : +*\*\ - I2C_FLAG_WRE Write data register empty +*\*\ - I2C_FLAG_WRAVL Write availabe +*\*\ - I2C_FLAG_RDAVL Receive data availabe +*\*\ - I2C_FLAG_ADR Address matched(Slave mode) +*\*\ - I2C_FLAG_NAKF NACK flag received +*\*\ - I2C_FLAG_STOPF STOP detection flag +*\*\ - I2C_FLAG_TFC Transfer Complete(Master mode) +*\*\ - I2C_FLAG_TFCR Transfer Complete Refill +*\*\ - I2C_FLAG_BSER BUS Error flag +*\*\ - I2C_FLAG_ABLO Arbitration lost flag +*\*\ - I2C_FLAG_OVF Overrun/Underrun flag(Slave mode) +*\*\ - I2C_FLAG_CRCERR CRC Error flag in reception +*\*\ - I2C_FLAG_TMOUT Timeout or tLOW detection flag +*\*\ - I2C_FLAG_ALRT SMBUS alert flag +*\*\ - I2C_FLAG_QADR Quick command address matched +*\*\ - I2C_FLAG_BUSY BUS busy flag +*\*\ - I2C_FLAG_DIR Transfer direction +*\*\ - I2C_FLAG_FRXNE Receive FIFO not empty flag +*\*\ - I2C_FLAG_FTXIS Transmit FIFO empty flag +*\*\return SET or RESET +*\*\note none. +**/ +FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus; + + if ((I2Cx->STSINT & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2s.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2s.c new file mode 100644 index 0000000000..d1d259c33f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2s.c @@ -0,0 +1,1159 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_i2s.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_i2s.h" +#include "n32h76x_78x_spi.h" +#include "n32h76x_78x.h" + + +/* SPI registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0xF9F7U) +#define I2SCFG_CLR_MASK ((uint16_t)0x05FCU) +#define I2SPR_CLEAR_Mask ((uint16_t)0x0FFFU) + +/* SPI or I2S mode selection masks */ +#define SPI_MODE_ENABLE ((uint16_t)0xFFFDU) +#define I2S_MODE_ENABLE ((uint16_t)0x0002U) + +/* I2S I2SE mask */ +#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0001U) +#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFFFEU) + + + +/** +*\*\name I2S_InitStruct. +*\*\fun Fills each I2S_InitStruct member with its default value. +*\*\param I2S_InitStruct : +*\*\ - I2sMode +*\*\ - Standard +*\*\ - DataFormat +*\*\ - MCLKEnable +*\*\ - AudioFrequency +*\*\ - CLKPOL +*\*\return none +**/ +void I2S_InitStruct(I2S_InitType* I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2sMode member */ + I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX; + + /* Initialize the Standard member */ + I2S_InitStruct->Standard = I2S_STD_PHILLIPS; + + /* Initialize the DataFormat member */ + I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS; + + /* Initialize the MCLKEnable member */ + I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE; + + /* Initialize the AudioFrequency member */ + I2S_InitStruct->ClkSrcFrequency = I2S_AUDIO_FREQ_DEFAULT; + + /* Initialize the CLKPOL member */ + I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW; +} + + +/** +*\*\name I2S_Mode_Select. +*\*\fun Select working on SPI mode or I2S mode. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param Mode : +*\*\ - SEL_SPI_Mode +*\*\ - SEL_I2S_Mode +*\*\return none +*\*\note Must be used with I2S or SPI OFF. +**/ +void I2S_SPIModeSelect(I2S_Module* I2Sx, uint16_t Mode) +{ + /* Clear MODSEL bit */ + I2Sx->I2SCFGR &= I2S_MODE_MASK; + /* Select the mode */ + I2Sx->I2SCFGR |= Mode; +} + +/** +*\*\name I2S_Mode_Config. +*\*\fun Config the I2s I2sMode. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param I2sMode : +*\*\ - I2S_MODE_SlAVE_TX +*\*\ - I2S_MODE_SlAVE_RX +*\*\ - I2S_MODE_MASTER_TX +*\*\ - I2S_MODE_MASTER_RX +*\*\return none +*\*\note Must be used with I2S OFF. +**/ +void I2S_ModeConfig(I2S_Module* I2Sx, uint16_t I2sMode) +{ + /* Clear SPI_I2SCFGR MODCFG bits */ + I2Sx->I2SCFGR &= I2S_MODE_MASK; + /* Set SPI_I2SCFGR MODCFG bits */ + I2Sx->I2SCFGR |= I2sMode; +} + +/** +*\*\name I2S_Standard_Config. +*\*\fun Config the I2s Standard. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param I2sMode : +*\*\ - I2S_STD_PHILLIPS +*\*\ - I2S_STD_MSB_ALIGN +*\*\ - I2S_STD_LSB_ALIGN +*\*\ - I2S_STD_PCM_SHORTFRAME +*\*\ - I2S_STD_PCM_LONGFRAME +*\*\return none +**/ +void I2S_StandardConfig(I2S_Module* I2Sx, uint16_t Standard) +{ + /* Clear SPI_I2SCFGR STDSEL and PCMFSYNC bit */ + I2Sx->I2SCFGR &= I2S_STANDARD_MASK; + /* Set SPI_I2SCFGR STDSEL and PCMFSYNC bit */ + I2Sx->I2SCFGR |= Standard; +} + +/** +*\*\name I2S_DataFormat_Config. +*\*\fun Config the I2s DataFormat. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param DataFormat : +*\*\ - I2S_DATA_FMT_16BITS +*\*\ - I2S_DATA_FMT_16BITS_EXTENDED +*\*\ - I2S_DATA_FMT_24BITS +*\*\ - I2S_DATA_FMT_32BITS +*\*\return none +**/ +void I2S_DataFormatConfig(I2S_Module* I2Sx, uint16_t DataFormat) +{ + /* Clear SPI_I2SCFGR CHBITS and TDATLEN bit */ + I2Sx->I2SCFGR &= I2S_DATA_FORMAT_MASK; + /* Set SPI_I2SCFGR CHBITS and TDATLEN bit */ + I2Sx->I2SCFGR |= DataFormat; +} + +/** +*\*\name I2S_MCLK_Enable. +*\*\fun Enable the I2s MCLK. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_MclkEnable(I2S_Module* I2Sx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set SPI_I2SPREDIV MCLKOEN bit */ + I2Sx->I2SPR |= I2S_MCLK_ENABLE; + } + else + { + /* Clear SPI_I2SPREDIV MCLKOEN bit */ + I2Sx->I2SPR &= I2S_MCLK_DISABLE; + } +} + +/** +*\*\name I2S_Config_MCLKEnable_And_AudioFrequency. +*\*\fun Config the I2s MCLKEnable and AudioFrequency. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param AudioFrequency : +*\*\ - I2S_AUDIO_FREQ_192K +*\*\ - I2S_AUDIO_FREQ_96K +*\*\ - I2S_AUDIO_FREQ_48K +*\*\ - I2S_AUDIO_FREQ_44K +*\*\ - I2S_AUDIO_FREQ_32K +*\*\ - I2S_AUDIO_FREQ_22K +*\*\ - I2S_AUDIO_FREQ_16K +*\*\ - I2S_AUDIO_FREQ_11K +*\*\ - I2S_AUDIO_FREQ_8K +*\*\ - I2S_AUDIO_FREQ_DEFAULT +*\*\return none +**/ +void I2S_AudioFrequencyConfig(I2S_Module* I2Sx, uint32_t AudioFrequency) +{ + uint16_t i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0;/// + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if (AudioFrequency == I2S_AUDIO_FREQ_DEFAULT) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + /* Check the frame length (For the SPI_I2SCFGR CHBITSbit) */ + if (I2Sx->I2SCFGR & SPI_I2SCFG_CHLEN) + { + /* Packet length is 32 bits */ + packetlength = 2; + } + else + { + /* Packet length is 16 bits */ + packetlength = 1; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SysClkFreq; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + /* Get the I2Sx->I2SPREDIV MCLKOEN bit state */ + if (I2Sx->I2SPR & I2S_MCLK_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / AudioFrequency)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / AudioFrequency)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to I2Sx I2SPREDIV register the computed value */ + I2Sx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (I2Sx->I2SPR & I2S_MCLK_ENABLE))); +} + +/** +*\*\name I2S_CLKPOL_Config. +*\*\fun Config the I2s CLKPOL. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param CLKPOL : +*\*\ - I2S_CLKPOL_LOW +*\*\ - I2S_CLKPOL_HIGH +*\*\return none +**/ +void I2S_ClkPolConfig(I2S_Module* I2Sx, uint16_t CLKPOL) +{ + /* Clear SPI_I2SPREDIV CLKPOL bit */ + I2Sx->I2SCFGR &= I2S_CLKPOL_MASK; + /* Set SPI_I2SPREDIV CLKPOL bit */ + I2Sx->I2SCFGR |= CLKPOL; +} + + +/** +*\*\name SPI_I2S_EnableInt. +*\*\fun Enables or disables the specified SPI/I2S interrupts. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_I2S_INT_TE +*\*\ - SPI_I2S_INT_RNE +*\*\ - SPI_I2S_INT_ERR +*\*\ - SPI_I2S_INT_RXONLYC +*\*\ - SPI_I2S_INT_RXFIFOF +*\*\ - SPI_I2S_INT_RXFIFOHF +*\*\ - SPI_I2S_INT_TXFIFOHE +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_EnableInt(I2S_Module* I2Sx, uint8_t I2S_IT, FunctionalState Cmd) +{ + uint16_t itpos, itmask; + + /* Get the SPI/I2S IT index */ + itpos = I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + I2Sx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + I2Sx->CR2 &= (uint16_t)~itmask; + } +} + +/** +*\*\name I2S_Data_Transmit. +*\*\fun Transmits a Data through the I2Sx/I2Sx peripheral. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param Data \* Data to be transmitted *\ +*\*\return none +**/ +void I2S_TransmitData(I2S_Module* I2Sx, uint16_t Data) +{ + /* Write in the SPI_DAT register the data to be sent */ + I2Sx->DR = Data; +} + +/** +*\*\name I2S_DataFifoTransmit. +*\*\fun Transmits a Data using FIFO through the I2Sx/I2Sx peripheral. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\param Data \* Data to be transmitted *\ +*\*\return none +**/ +void I2S_DataFifoTransmit(I2S_Module* I2Sx, uint16_t Data) +{ + /* Write in the SPI_DAT register the data to be sent */ + I2Sx->DR = Data; +} + +/** +*\*\name I2S_ReceiveData. +*\*\fun Get SPI/I2S data from SPI_DAT register. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\return The data in the SPI_DAT register +**/ +uint16_t I2S_ReceiveData(I2S_Module* I2Sx) +{ + /* Return the data in the SPI_DAT register */ + return I2Sx->DR; +} + +/** +*\*\name I2S_DataFifoGet. +*\*\fun Get SPI/I2S data from RXFIFO register. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\return The data in the SPI_DAT register +**/ +uint16_t I2S_DataFifoGet(I2S_Module* I2Sx) +{ + /* Return the data in the SPI_DAT register */ + return I2Sx->RXFIFO; +} + +/** +*\*\name I2S_Rx_Fifo_Num_Get. +*\*\fun Get I2S Receive Data Counter in FIFO. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\return The RX FIFO Data Count +**/ +uint16_t I2S_Rx_Fifo_Num_Get(I2S_Module* I2Sx) +{ + /* Return The RX Data Count in FIFO*/ + return ((I2Sx->FIFOCNT & I2S_FIFO_NUM_RX_CNT) >> 4); +} + +/** +*\*\name I2S_Tx_Fifo_Num_Get. +*\*\fun Get I2S Send Data Counter in FIFO. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\return The TX Data Count in FIFO +**/ +uint16_t I2S_Tx_Fifo_Num_Get(I2S_Module* I2Sx) +{ + /* Return The TX Data Count in FIFO */ + return ((I2Sx->FIFOCNT & I2S_FIFO_NUM_TX_CNT)); +} + +/** +*\*\name I2S_Tx_Fifo_Half_Full_Threshold_Cfg. +*\*\fun Configure TX FIFO Half Empty Threshold Value. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\return None +**/ +void I2S_Tx_Fifo_Half_Full_Threshold_Cfg(I2S_Module* I2Sx, uint8_t threshold) +{ + /* Configure TX FIFO Half Empty Threshold Value */ + I2Sx->FIFONUM |= (threshold & I2S_FIFO_BURST_NUM_TX); +} + +/** +*\*\name I2S_Rx_Fifo_Half_Full_Threshold_Cfg. +*\*\fun Configure RX FIFO Half Empty Threshold Value. +*\*\param I2Sx : +*\*\ - I2S1 +*\*\ - I2S2 +*\*\ - I2S3 +*\*\ - I2S4 +*\*\return None +**/ +void I2S_Rx_Fifo_Half_Full_Threshold_Cfg(I2S_Module* I2Sx, uint8_t threshold) +{ + /* Configure RX FIFO Half Empty Threshold Value */ + I2Sx->FIFONUM |= ((threshold >> 4) & I2S_FIFO_BURST_NUM_RX); +} + +/** +*\*\name SPI_I2S_GetStatus. +*\*\fun Checks whether the specified SPI/I2S flag is set or not. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_FLAG : +*\*\ - SPI_I2S_BUSY_FLAG +*\*\ - SPI_I2S_OVER_FLAG +*\*\ - SPI_MODERR_FLAG +*\*\ - SPI_CRCERR_FLAG +*\*\ - I2S_UNDER_FLAG +*\*\ - I2S_CHSIDE_FLAG +*\*\ - SPI_I2S_TE_FLAG +*\*\ - SPI_I2S_RNE_FLAG +*\*\ - SPI_I2S_RXONLYC_FLAG +*\*\ - SPI_I2S_RXFIFOF_FLAG +*\*\ - SPI_I2S_TXFIFOE_FLAG +*\*\ - SPI_I2S_RXFIFOHF_FLAG +*\*\ - SPI_I2S_TXFIFOHE_FLAG +*\*\return The new state of SPI_I2S_FLAG (SET or RESET). +**/ +FlagStatus I2S_GetStatus(I2S_Module* I2Sx, uint8_t i2s_flag) +{ + FlagStatus bitstatus; + + /* Check the status of the specified SPI/I2S flag */ + if ((I2Sx->SR & i2s_flag) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** +*\*\name I2S_GetIntStatus. +*\*\fun Checks whether the specified SPI/I2S interrupt has occurred or not. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_I2S_INT_TE +*\*\ - SPI_I2S_INT_RNE +*\*\ - SPI_I2S_INT_RXONLYC +*\*\ - SPI_I2S_INT_RXFIFOF +*\*\ - SPI_I2S_INT_RXFIFOHF +*\*\ - SPI_I2S_INT_TXFIFOHE +*\*\ - SPI_I2S_INT_CRCERR +*\*\ - SPI_I2S_INT_MODERR +*\*\ - SPI_I2S_INT_OVERERR +*\*\ - I2S_I2S_INT_UNDER +*\*\return The new state of SPI_I2S_IT (SET or RESET). +**/ + +INTStatus I2S_GetIntStatus(const I2S_Module* I2sx, uint8_t I2S_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (I2sx->CR2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((I2sx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + + +/** +*\*\name I2S_ClrITPendingBit. +*\*\fun Clears the SPIx CRC Error (CRCERR) interrupt pending bit. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_INT_CRCERR +*\*\return none. +**/ +void I2S_ClrITPendingBit(I2S_Module* I2Sx, uint8_t I2S_IT) +{ + uint16_t itpos; + + /* Get the SPI IT index */ + itpos = 0x0001 << (I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + I2Sx->SR = (uint16_t)~itpos; +} + + +void I2S_Reset(I2S_Module* I2Sx) +{ + if (I2Sx == I2S1) + { + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_I2S1); + } + + else if (I2Sx == I2S2) + { + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_I2S2); + } + + else if (I2Sx == I2S3) + { + RCC_EnableAPB1PeriphReset4(RCC_APB1_PERIPHRST_I2S3); + } + + else if (I2Sx == I2S4) + { + RCC_EnableAPB1PeriphReset4(RCC_APB1_PERIPHRST_I2S4); + } +} + +/** +*\*\name I2S_Init. +*\*\fun Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct. +*\*\param SPIx : +*\*\ - SPI2 +*\*\ - SPI3 +*\*\param I2S_InitStruct : +*\*\ - I2sMode +*\*\ - I2S_MODE_SlAVE_TX +*\*\ - I2S_MODE_SlAVE_RX +*\*\ - I2S_MODE_MASTER_TX +*\*\ - I2S_MODE_MASTER_RX +*\*\ - Standard +*\*\ - I2S_STD_PHILLIPS +*\*\ - I2S_STD_MSB_ALIGN +*\*\ - I2S_STD_LSB_ALIGN +*\*\ - I2S_STD_PCM_SHORTFRAME +*\*\ - I2S_STD_PCM_LONGFRAME +*\*\ - DataFormat +*\*\ - I2S_DATA_FMT_16BITS +*\*\ - I2S_DATA_FMT_16BITS_EXTENDED +*\*\ - I2S_DATA_FMT_24BITS +*\*\ - I2S_DATA_FMT_32BITS +*\*\ - MCLKEnable +*\*\ - I2S_MCLK_ENABLE +*\*\ - I2S_MCLK_DISABLE +*\*\ - AudioFrequency +*\*\ - I2S_AUDIO_FREQ_192K +*\*\ - I2S_AUDIO_FREQ_96K +*\*\ - I2S_AUDIO_FREQ_48K +*\*\ - I2S_AUDIO_FREQ_44K +*\*\ - I2S_AUDIO_FREQ_32K +*\*\ - I2S_AUDIO_FREQ_22K +*\*\ - I2S_AUDIO_FREQ_16K +*\*\ - I2S_AUDIO_FREQ_11K +*\*\ - I2S_AUDIO_FREQ_8K +*\*\ - I2S_AUDIO_FREQ_DEFAULT +*\*\ - CLKPOL +*\*\ - I2S_CLKPOL_LOW +*\*\ - I2S_CLKPOL_HIGH +*\*\ - ClkSrcFrequency +*\*\ - RCC_Clocks.SysclkFreq +*\*\ - RCC_Clocks.HclkFreq +*\*\ - RCC_Clocks.Pclk1Freq +*\*\ - RCC_Clocks.Pclk2Freq +*\*\ - RCC_Clocks.AdcPllClkFreq +*\*\ - RCC_Clocks.AdcHclkFreq +*\*\ - RCC_Clocks.ShrtpllFreq +*\*\ - user defined +**/ +void I2S_Init(I2S_Module* I2Sx, const I2S_InitType* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; +// RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + I2Sx->I2SCFGR &= I2SCFG_CLR_MASK; + I2Sx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = I2Sx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + + if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT) + { + i2sodd = ( uint16_t )0; + i2sdiv = ( uint16_t )2; + } + + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if ( I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS ) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the source clock value: based on System Clock value */ + sourceclock = I2S_InitStruct->ClkSrcFrequency; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if ( I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE ) + { + /* MCLK output is enabled */ + tmp = ( uint16_t )((((( sourceclock / 256 ) * 10 ) / I2S_InitStruct->AudioFrequency ) ) + 5 ); + } + else + { + /* MCLK output is disabled */ + tmp = ( uint16_t )((((( sourceclock / ( 32 * packetlength ) ) * 10 ) / I2S_InitStruct->AudioFrequency ) ) + 5 ); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = ( uint16_t )( tmp & ( uint16_t )0x0001 ); + + /* Compute the i2sdiv prescaler */ + i2sdiv = ( uint16_t )(( tmp - i2sodd ) / 2 ); + + /* Get the Mask for the Odd bit (SPI_I2SPR[10]) register */ + i2sodd = ( uint16_t )( i2sodd << 10 ); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if (( i2sdiv < 2 ) || ( i2sdiv > 0x3FF ) ) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + I2Sx->I2SPR = ( uint16_t )( i2sdiv | ( uint16_t )( i2sodd | ( uint16_t )I2S_InitStruct->MCLKEnable ) ); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= ( uint16_t )( I2S_MODE_ENABLE | ( uint16_t )( I2S_InitStruct->I2sMode | \ + ( uint16_t )( I2S_InitStruct->Standard | ( uint16_t )( I2S_InitStruct->DataFormat | \ + ( uint16_t )I2S_InitStruct->CLKPOL ) ) ) ); + + /* Write to SPIx I2SCFGR */ + I2Sx->I2SCFGR = tmpreg; +} + +/** +*\*\name I2S_Enable. +*\*\fun Enables or disables the specified SPI peripheral (in I2S mode). +*\*\param SPIx : +*\*\ - SPI2 +*\*\ - SPI3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_Enable(I2S_Module* I2Sx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + I2Sx->I2SCFGR |= I2SCFG_I2SEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + I2Sx->I2SCFGR &= I2SCFG_I2SEN_DISABLE; + } +} + +/* I2S_EXT */ +/** +*\*\name I2S_EXTInit. +*\*\fun Initializes the I2Sx_EXT peripheral according to the specified parameters in the I2S_EXT_InitStruct. +*\*\param I2Sx_EXT : +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\param I2S_InitStruct: +*\*\ - I2sMode +*\*\ - I2S_MODE_SlAVE_TX +*\*\ - I2S_MODE_SlAVE_RX +*\*\ - I2S_MODE_MASTER_TX +*\*\ - I2S_MODE_MASTER_RX +*\*\ - Standard +*\*\ - I2S_STD_PHILLIPS +*\*\ - I2S_STD_MSB_ALIGN +*\*\ - I2S_STD_LSB_ALIGN +*\*\ - I2S_STD_PCM_SHORTFRAME +*\*\ - I2S_STD_PCM_LONGFRAME +*\*\ - DataFormat +*\*\ - I2S_DATA_FMT_16BITS +*\*\ - I2S_DATA_FMT_16BITS_EXTENDED +*\*\ - I2S_DATA_FMT_24BITS +*\*\ - I2S_DATA_FMT_32BITS +*\*\ - CLKPOL +*\*\ - I2S_CLKPOL_LOW +*\*\ - I2S_CLKPOL_HIGH +*\*\return none +**/ +void I2S_EXTInit(I2S_EXT_Module* I2Sx_EXT, const I2S_InitType* I2S_EXT_InitStruct) +{ + uint16_t tmpregister; + RCC_ClocksTypeDef RCC_Clocks; + + /*----------------------- I2Sx_EXT I2S_CFGR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CLKPOL, TDATLEN and CHLEN bits */ + I2Sx_EXT->I2S_CFGR &= I2SCFG_CLR_MASK; + + /* Get the SPI_I2S_CFGR register value */ + tmpregister = I2Sx_EXT->I2S_CFGR; + + + + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + + + + /* Configure the I2S with the SPI_InitStruct values */ + tmpregister |= (uint16_t)( + I2S_MODE_ENABLE + | (uint16_t)(I2S_EXT_InitStruct->I2sMode + | (uint16_t)(I2S_EXT_InitStruct->Standard + | (uint16_t)(I2S_EXT_InitStruct->DataFormat | (uint16_t)I2S_EXT_InitStruct->CLKPOL)))); + + /* Write to I2Sx_EXT SPI_I2S_CFGR */ + I2Sx_EXT->I2S_CFGR = tmpregister; +} + + +/** +*\*\name I2S_EXT_InitStruct. +*\*\fun Fills each I2S_EXT_InitStruct member with its default value. +*\*\param I2S_EXT_InitStruct : +*\*\ - I2sMode +*\*\ - Standard +*\*\ - DataFormat +*\*\ - CLKPOL +*\*\return none +**/ +void I2S_EXTInitStruct(I2S_InitType* I2S_EXT_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2sMode member */ + I2S_EXT_InitStruct->I2sMode = I2S_MODE_SlAVE_TX; + + /* Initialize the Standard member */ + I2S_EXT_InitStruct->Standard = I2S_STD_PHILLIPS; + + /* Initialize the DataFormat member */ + I2S_EXT_InitStruct->DataFormat = I2S_DATA_FMT_16BITS; + + /* Initialize the CLKPOL member */ + I2S_EXT_InitStruct->CLKPOL = I2S_CLKPOL_LOW; +} + +/** +*\*\name I2S_EXTEnable. +*\*\fun Enables or disables the specified I2S EXT peripheral. +*\*\param I2Sx_EXT : +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_EXTEnable(I2S_EXT_Module* I2Sx_EXT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected I2S_EXT peripheral */ + I2Sx_EXT->I2S_CFGR |= I2SCFG_I2SEN_ENABLE; + } + else + { + /* Disable the selected I2S_EXT peripheral */ + I2Sx_EXT->I2S_CFGR &= I2SCFG_I2SEN_DISABLE; + } +} + +/** +*\*\name I2S_EXT_TransmitData. +*\*\fun Transmits a Data through the I2Sx_EXT peripheral. +*\*\param I2Sx : +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\param Data \* Data to be transmitted *\ +*\*\return none +**/ +void I2S_EXTTransmitData(I2S_EXT_Module* I2Sx, uint16_t Data) +{ + /* Write in the DAT register the data to be sent */ + I2Sx->I2S_DAT = Data; +} + + +/** +*\*\name I2S_EXTReceiveData. +*\*\fun Returns the most recent received data by the I2Sx_EXT peripheral. +*\*\param I2Sx : +*\*\ - I2S1_EXT +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\ - I2S4_EXT +*\*\return The data in the I2S_DAT register. +**/ +uint16_t I2S_EXTReceiveData(const I2S_EXT_Module* I2Sx) +{ + /* Return the data in the DAT register */ + return I2Sx->I2S_DAT; +} + + +/** +*\*\name I2S_EXTEnableDma. +*\*\fun Enables or disables the I2Sx DMA interface. +*\*\param I2Sx : +*\*\ - I2S1_EXT +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\ - I2S4_EXT +*\*\param I2S_EXT_DMAReq : +*\*\ - I2S_EXT_DMA_TX +*\*\ - I2S_EXT_DMA_RX +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_EXTEnableDma(I2S_EXT_Module* I2Sx, uint16_t I2S_EXT_DMAReq, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected I2S_EXT DMA requests */ + I2Sx->I2S_CTRL2 |= I2S_EXT_DMAReq; + } + else + { + /* Disable the selected I2S_EXT DMA requests */ + I2Sx->I2S_CTRL2 &= (uint16_t)~I2S_EXT_DMAReq; + } +} + +/** +*\*\name I2S_EXTEnableInt. +*\*\fun Enables or disables the specified I2S_EXT interrupts. +*\*\param I2Sx : +*\*\ - I2S1_EXT +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\ - I2S4_EXT +*\*\param I2S_EXT_IT : +*\*\ - I2S_EXT_INT_TEINTEN +*\*\ - I2S_EXT_INT_RNEINTEN +*\*\ - I2S_EXT_INT_ERRINTEN +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_EXTEnableInt(I2S_EXT_Module* I2Sx, uint8_t I2S_EXT_IT, FunctionalState Cmd) +{ + uint16_t itmask; + + /* Set the IT mask */ + itmask = I2S_EXT_IT; + + if (Cmd != DISABLE) + { + /* Enable the selected I2S interrupt */ + I2Sx->I2S_CTRL2 |= itmask; + } + else + { + /* Disable the selected I2S interrupt */ + I2Sx->I2S_CTRL2 &= (uint16_t)~itmask; + } +} + +/** +*\*\name I2S_EXT_GetStatus. +*\*\fun Checks whether the specified I2S_EXT flag is set or not. +*\*\param I2Sx : +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\param I2S_EXT_FLAG : +*\*\ - I2S_EXT_BUSY_FLAG +*\*\ - I2S_EXT_OVER_FLAG +*\*\ - I2S_EXT_UNDER_FLAG +*\*\ - I2S_EXT_CHSIDE_FLAG +*\*\ - I2S_EXT_TE_FLAG +*\*\ - I2S_EXT_RNE_FLAG +*\*\return The new state of I2S_EXT_FLAG (SET or RESET). +**/ +FlagStatus I2S_EXTGetStatus(const I2S_EXT_Module* I2Sx, uint16_t I2S_EXT_FLAG) +{ + FlagStatus bitstatus; + + /* Check the status of the specified I2S_EXT flag */ + if ((I2Sx->I2S_STS & I2S_EXT_FLAG) != (uint16_t)RESET) + { + /* I2S_EXT_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2S_EXT_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2S_EXT_FLAG status */ + return bitstatus; +} + +/** +*\*\name I2S_EXTGetIntStatus. +*\*\fun Checks whether the specified I2S_EXT interrupt has occurred or not. +*\*\param I2Sx : +*\*\ - I2S2_EXT +*\*\ - I2S3_EXT +*\*\param I2S_EXT_IT : +*\*\ - I2S_EXT_TE_FLAG +*\*\ - I2S_EXT_RNE_FLAG +*\*\ - I2S_EXT_BUSY_FLAG +*\*\ - I2S_EXT_OVER_FLAG +*\*\ - I2S_EXT_UNDER_FLAG +*\*\ - I2S_EXT_CHSIDE_FLAG +*\*\return The new state of I2S_EXT_IT (SET or RESET). +**/ + +INTStatus I2S_EXTGetIntStatus(const I2S_EXT_Module* I2Sx, uint8_t I2S_EXT_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (I2S_EXT_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = I2S_EXT_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (I2Sx->I2S_CTRL2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((I2Sx->I2S_STS & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + + /* Return the SPI_I2S_IT status */ + return bitstatus; + +} + +/** +*\*\name I2S_EXTClrITPendingBit. +*\*\fun Clears the SPI_EXTx CRC Error (CRCERR) interrupt pending bit. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_INT_CRCERR +*\*\return none. +**/ +void I2S_EXTClrITPendingBit(I2S_EXT_Module* I2Sx, uint8_t I2S_EXT_IT) +{ + uint16_t itpos; + + /* Get the SPI IT index */ + itpos = 0x0001 << (I2S_EXT_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + I2Sx->I2S_STS = (uint16_t)~itpos; +} + +/** +*\*\name SPI_I2S_EnableDma. +*\*\fun Enables or disables the SPIx/I2Sx DMA interface. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_DMAReq : +*\*\ - SPI_I2S_DMA_TX +*\*\ - SPI_I2S_DMA_RX +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void I2S_EnableDma(I2S_Module* I2Sx, uint16_t I2S_DMAReq, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + I2Sx->CR2 |= I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + I2Sx->CR2 &= (uint16_t)~I2S_DMAReq; + } +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_iwdg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_iwdg.c new file mode 100644 index 0000000000..2da6c3f7d7 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_iwdg.c @@ -0,0 +1,193 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_iwdg.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_iwdg.h" + +/** +*\*\name IWDG_WriteConfig. +*\*\fun Enables or disables write protection to IWDG_PREDIV and IWDG_RELV registers. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 +*\*\param IWDG_WriteAccess +*\*\ - IWDG_WRITE_ENABLE +*\*\ - IWDG_WRITE_DISABLE +*\*\return none +**/ +void IWDG_WriteConfig(IWDG_Module* IWDGx, IWDOG_WRITE_CONFIG IWDG_WriteAccess) +{ + /* Check the parameters */ + IWDGx->KEY = (uint32_t)IWDG_WriteAccess; +} + +/** +*\*\name IWDG_SetPrescalerDiv. +*\*\fun IWDG_Prescaler specifies the IWDG prescaler value. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 +*\*\param IWDG_Prescaler : +*\*\ - IWDG_PRESCALER_DIV4 +*\*\ - IWDG_PRESCALER_DIV8 +*\*\ - IWDG_PRESCALER_DIV16 +*\*\ - IWDG_PRESCALER_DIV32 +*\*\ - IWDG_PRESCALER_DIV64 +*\*\ - IWDG_PRESCALER_DIV128 +*\*\ - IWDG_PRESCALER_DIV256 +*\*\return none +**/ +void IWDG_SetPrescalerDiv(IWDG_Module* IWDGx, uint8_t IWDG_Prescaler) +{ + IWDGx->PREDIV = IWDG_Prescaler; +} + + +/** +*\*\name IWDG_CntReload. +*\*\fun Sets IWDG reload value. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 +*\*\param Reload : +*\*\ -0x000 ~ 0xFFF +*\*\return none +**/ +void IWDG_CntReload(IWDG_Module* IWDGx, uint16_t Reload) +{ + IWDGx->RELV = Reload; +} + + +/** +*\*\name IWDG_ReloadKey. +*\*\fun Reload IWDG counter with value defined in IWDG_RELV register. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 +*\*\param none +*\*\return none +**/ +void IWDG_ReloadKey(IWDG_Module* IWDGx) +{ + IWDGx->KEY = KEY_ReloadKey; +} + + +/** +*\*\name IWDG_Enable. +*\*\fun Start watch dog counter. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 +*\*\param none +*\*\return none +**/ +void IWDG_Enable(IWDG_Module* IWDGx) +{ + IWDGx->KEY = KEY_EnableKey; +} + +/** +*\*\name IWDG_Freeze_Enable. +*\*\fun Freeze or unfreeze IWDG while IWDG is running in run mode. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return none +**/ +void IWDG_Freeze_Enable(IWDG_Module* IWDGx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + IWDGx->KEY = IWDG_FREEZE; + } + else + { + IWDGx->KEY = IWDG_UNFREEZE; + } + +} + +/** +*\*\name IWDG_GetStatus. +*\*\fun Checks whether the specified IWDG flag is set or not. +*\*\param IWDGx (The input parameters must be the following values): +*\*\ - IWDG1 +*\*\ - IWDG2 +*\*\param IWDG_FLAG : +*\*\ - IWDG_PVU_FLAG +*\*\ - IWDG_CRVU_FLAG +*\*\ - IWDG_FRZF_FLAG +*\*\return FlagStatus : +*\*\ - RESET +*\*\ - SET +**/ +FlagStatus IWDG_GetStatus(IWDG_Module* IWDGx, IWDG_STATUS_FLAG IWDG_FLAG) +{ + FlagStatus bitstatus; + + if ((IWDGx->STS & (uint32_t)IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_jpeg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_jpeg.c new file mode 100644 index 0000000000..039cee120e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_jpeg.c @@ -0,0 +1,1617 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_jpeg.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ + +#include "n32h76x_78x_jpeg.h" + +/***** JPEG CTRL module ****/ + +/** +*\*\name JPEG_ConfigType. +*\*\fun Choose JPEG operation type. +*\*\param Type +*\*\ - JPEG_ENCODE +*\*\ - JPEG_DECODE +*\*\return none. +**/ +void JPEG_ConfigType(uint32_t Type) +{ + if(Type == JPEG_DECODE) + { + JPEG_CTRL->CTRL &= (~(JPEG_ENCODE)); + } + else + { + JPEG_CTRL->CTRL |= JPEG_ENCODE; + } +} + +/** +*\*\name JPEG_ConfigSwap. +*\*\fun Swap Data for YCbCr 4:2:2 Format in BRC. +*\*\param Type +*\*\ - JPEG_SWAP +*\*\ - JPEG_NOSWAP +*\*\return none. +**/ +void JPEG_ConfigSwap(uint32_t Type) +{ + if(Type == JPEG_NOSWAP) + { + JPEG_CTRL->CTRL &= (~(JPEG_SWAP)); + } + else + { + JPEG_CTRL->CTRL |= JPEG_SWAP; + } +} + + +/***** JPEG SGDMA module ****/ + +/** +*\*\name SGDMA_Reset. +*\*\fun Reset the SGDMA P2H/H2P module. +*\*\param SGDMAx : +*\*\ - JPEG_SGDMA_P2H +*\*\ - JPEG_SGDMA_H2P +*\*\return none +**/ +void SGDMA_Reset(JPEG_SGDMA_Module *SGDMAx) +{ + /* Module soft reset */ + if((SGDMAx->STS & JPEGDMA_STS_BUSY) == JPEGDMA_STS_BUSY) + { + SGDMAx->CTRL |= JPEGDMA_CTRL_HARDRST; + } + else + { + SGDMAx->CTRL |= JPEGDMA_CTRL_CLR; + } +} + +/** +*\*\name SGDMA_H2P_Init. +*\*\fun Initializes the SGDMA_H2P peripheral according to SGDMA_H2P_InitStruct. +*\*\param SGDMA_H2P_InitStruct +*\*\ - h2p_desc +*\*\ - desc_flags : Descriptor flag bits +*\*\ - linkenable: Link Enable +*\*\ - BITEQ0 : 0 +*\*\ - BITEQ1 : 1 +*\*\ - startframe: Start of Frame +*\*\ - BITEQ0 : 0 +*\*\ - BITEQ1 : 1 +*\*\ - endframe: End of Frame +*\*\ - BITEQ0 : 0 +*\*\ - BITEQ1 : 1 +*\*\ - desccons: Descriptor Consumed +*\*\ - BITEQ0 : 0 +*\*\ - BITEQ1 : 1 +*\*\ - blk_size : Block_Size +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - blk_used : Block_Used +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - blk_addr_low : The starting address of the data block [31:0] +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - blk_addr_high : The starting address of the data block [63:32] +*\*\ - 0x00000000 +*\*\ - link_addr_low : Link to the next descriptor. Used when Link Enable = 1 +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - link_addr_high : Link to the next descriptor. Used when Link Enable = 1 +*\*\ - 0x00000000 +*\*\ - max_burstsize : Maximum allowed size for an AXI4 MM burst +*\*\ - 0x00000000 ~ 0x00000100 +*\*\ - SGlist_size : Scatter-Gather List Size +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - SGlist_Head : Scatter-Gather List Head index pointer +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - SGlist_Tail : Scatter-Gather List Tail index pointer +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - SGlist_Threshold : Almost Out Of Descriptors Threshold +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - desclist_type : The descriptor list structure type +*\*\ - SGDMA_DESCLIST_LIST +*\*\ - SGDMA_DESCLIST_RING +*\*\ - descstored_type : The descriptor storage location +*\*\ - SGDMA_DESC_CSR +*\*\ - SGDMA_DESC_MEMORY +*\*\ - DMA_EOF_type : DMA operation mode on EOF +*\*\ - SGDMA_EOF_PAUSEDMA +*\*\ - SGDMA_EOF_RESUMEDMA +*\*\ - DMA_burst_type : DMA burst type +*\*\ - SGDMA_BURST_FIXED +*\*\ - SGDMA_BURST_INCR +*\*\return none. +**/ +void SGDMA_H2P_Init(SGDMA_H2P_InitType* SGDMA_H2P_InitStruct) +{ + uint32_t resg_temp; + + SGDMA_Reset(JPEG_SGDMA_H2P); + /* Module enable */ + JPEG_SGDMA_H2P->CTRL |= JPEGDMA_CTRL_EN; + + /* Maximum allowed size for an AXI4 MM burst */ + JPEG_SGDMA_H2P->MBSIZE = SGDMA_H2P_InitStruct->max_burstsize; + + /* H2P DMA initial configuration */ + resg_temp = JPEG_SGDMA_H2P->CTRL; + resg_temp &= (~(JPEGDMA_CTRL_MMODE | JPEGDMA_CTRL_OPMODE)); + resg_temp |= SGDMA_H2P_InitStruct->desclist_type; + resg_temp |= SGDMA_H2P_InitStruct->descstored_type; + resg_temp |= SGDMA_H2P_InitStruct->DMA_burst_type; + resg_temp |= SGDMA_H2P_InitStruct->DMA_EOF_type; + JPEG_SGDMA_H2P->CTRL = resg_temp; + + /* Determine descriptor location */ + if(SGDMA_H2P_InitStruct->descstored_type == SGDMA_DESC_MEMORY) + { + /* Set base address of the SG List */ + JPEG_SGDMA_H2P->SGLPL = (uint32_t)&SGDMA_H2P_InitStruct->h2p_desc; + } + else + { + JPEG_SGDMA_H2P->DESCF = *(uint32_t*)(&SGDMA_H2P_InitStruct->h2p_desc); + JPEG_SGDMA_H2P->DESC_MBADDL = SGDMA_H2P_InitStruct->h2p_desc.blk_addr_low; + JPEG_SGDMA_H2P->DESC_MBADDH = SGDMA_H2P_InitStruct->h2p_desc.blk_addr_high; + JPEG_SGDMA_H2P->DESC_MBSIZE = SGDMA_H2P_InitStruct->h2p_desc.blk_size; + JPEG_SGDMA_H2P->DESC_MUS = SGDMA_H2P_InitStruct->h2p_desc.blk_used; + /* Determine if linkenable is enabled */ + if(SGDMA_H2P_InitStruct->h2p_desc.desc_flags.bits.linkenable != DISABLE) + { + JPEG_SGDMA_H2P->DESC_LINKL = SGDMA_H2P_InitStruct->h2p_desc.link_addr_low; + JPEG_SGDMA_H2P->DESC_LINKH = SGDMA_H2P_InitStruct->h2p_desc.link_addr_high; + } + else + { + /* no process */ + } + } + + /* Set size of the SG List */ + JPEG_SGDMA_H2P->SGL_SIZE = SGDMA_H2P_InitStruct->SGlist_size; + JPEG_SGDMA_H2P->SGL_HEAD = SGDMA_H2P_InitStruct->SGlist_Head; + JPEG_SGDMA_H2P->SGL_TAIL = SGDMA_H2P_InitStruct->SGlist_Tail; + JPEG_SGDMA_H2P->AOODT = SGDMA_H2P_InitStruct->SGlist_Threshold; +} + + +/** +*\*\name SGDMA_P2H_Init. +*\*\fun Initializes the SGDMA_H2P peripheral according to SGDMA_H2P_InitStruct. +*\*\param SGDMA_P2H_InitStruct +*\*\ - p2h_desc +*\*\ - desc_flags : Descriptor flag bits +*\*\ - linkenable: Link Enable +*\*\ - 0 : DISABLE +*\*\ - 1 : ENABLE +*\*\ - startframe: Start of Frame +*\*\ - 0 : DISABLE +*\*\ - 1 : ENABLE +*\*\ - endframe: End of Frame +*\*\ - 0 : DISABLE +*\*\ - 1 : ENABLE +*\*\ - desccons: Descriptor Consumed +*\*\ - 0 : DISABLE +*\*\ - 1 : ENABLE +*\*\ - blk_size : Block_Size +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - blk_used : Block_Used +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - blk_addr_low : The starting address of the data block [31:0] +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - blk_addr_high : The starting address of the data block [63:32] +*\*\ - 0x00000000 +*\*\ - link_addr_low : Link to the next descriptor. Used when Link Enable = 1 +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - link_addr_high : Link to the next descriptor. Used when Link Enable = 1 +*\*\ - 0x00000000 +*\*\ - max_burstsize : Maximum allowed size for an AXI4 MM burst +*\*\ - 0x00000000 ~ 0x00000100 +*\*\ - SGlist_size : Scatter-Gather List Size +*\*\ - 0x00000000 ~ 0x0000FFFF +*\*\ - desclist_type : The descriptor list structure type +*\*\ - SGDMA_DESCLIST_LIST +*\*\ - SGDMA_DESCLIST_RING +*\*\ - descstored_type : The descriptor storage location +*\*\ - SGDMA_DESC_CSR +*\*\ - SGDMA_DESC_MEMORY +*\*\ - DMA_EOF_type : DMA operation mode on EOF +*\*\ - SGDMA_EOF_PAUSEDMA +*\*\ - SGDMA_EOF_RESUMEDMA +*\*\ - DMA_burst_type : DMA burst type +*\*\ - SGDMA_BURST_FIXED +*\*\ - SGDMA_BURST_INCR +*\*\return none. +**/ +void SGDMA_P2H_Init(SGDMA_P2H_InitType* SGDMA_P2H_InitStruct) +{ + uint32_t resg_temp; + + SGDMA_Reset(JPEG_SGDMA_P2H); + /* Module enable */ + JPEG_SGDMA_P2H->CTRL |= JPEGDMA_CTRL_EN; + + /* Maximum allowed size for an AXI4 MM burst */ + JPEG_SGDMA_P2H->MBSIZE = SGDMA_P2H_InitStruct->max_burstsize; + + /* H2P DMA initial configuration */ + resg_temp = JPEG_SGDMA_P2H->CTRL; + resg_temp &= (~(JPEGDMA_CTRL_MMODE | JPEGDMA_CTRL_OPMODE)); + resg_temp |= SGDMA_P2H_InitStruct->desclist_type; + resg_temp |= SGDMA_P2H_InitStruct->descstored_type; + resg_temp |= SGDMA_P2H_InitStruct->DMA_burst_type; + resg_temp |= SGDMA_P2H_InitStruct->DMA_EOF_type; + JPEG_SGDMA_P2H->CTRL = resg_temp; + + /* Determine descriptor location */ + if(SGDMA_P2H_InitStruct->descstored_type == SGDMA_DESC_MEMORY) + { + /* Set base address of the SG List */ + JPEG_SGDMA_P2H->SGLPL = (uint32_t)&SGDMA_P2H_InitStruct->p2h_desc; + } + else + { + JPEG_SGDMA_P2H->DESCF = *(uint32_t*)(&SGDMA_P2H_InitStruct->p2h_desc); + JPEG_SGDMA_P2H->DESC_MBADDL = SGDMA_P2H_InitStruct->p2h_desc.blk_addr_low; + JPEG_SGDMA_P2H->DESC_MBADDH = SGDMA_P2H_InitStruct->p2h_desc.blk_addr_high; + JPEG_SGDMA_P2H->DESC_MBSIZE = SGDMA_P2H_InitStruct->p2h_desc.blk_size; + JPEG_SGDMA_P2H->DESC_MUS = SGDMA_P2H_InitStruct->p2h_desc.blk_used; + /* Determine if linkenable is enabled */ + if(SGDMA_P2H_InitStruct->p2h_desc.desc_flags.bits.linkenable != DISABLE) + { + JPEG_SGDMA_P2H->DESC_LINKL = SGDMA_P2H_InitStruct->p2h_desc.link_addr_low; + JPEG_SGDMA_P2H->DESC_LINKH = SGDMA_P2H_InitStruct->p2h_desc.link_addr_high; + } + else + { + /* no process */ + } + } + + /* Set size of the SG List */ + JPEG_SGDMA_P2H->SGL_SIZE = SGDMA_P2H_InitStruct->SGlist_size; + JPEG_SGDMA_P2H->SGL_HEAD = SGDMA_P2H_InitStruct->SGlist_Head; + JPEG_SGDMA_P2H->SGL_TAIL = SGDMA_P2H_InitStruct->SGlist_Tail; + JPEG_SGDMA_P2H->AOODT = SGDMA_P2H_InitStruct->SGlist_Threshold; +} + +/** +*\*\name SGDMA_Start. +*\*\fun Start the SGDMA P2H/H2P module. +*\*\param SGDMAx : +*\*\ - JPEG_SGDMA_P2H +*\*\ - JPEG_SGDMA_H2P +*\*\return none +**/ +void SGDMA_Start(JPEG_SGDMA_Module *SGDMAx) +{ + /* DMA start */ + SGDMAx->CTRL |= JPEGDMA_CTRL_START; +} + +/** +*\*\name SGDMA_ConfigInt +*\*\fun Enables or disables the specified SGDMA interrupts. +*\*\param SGDMAx (The input parameters must be the following values): +*\*\ - JPEG_SGDMA_P2H +*\*\ - JPEG_SGDMA_H2P +*\*\param SGDMA_INT (The input parameters must be the following values): +*\*\ - SGDMA_INTSTS_WDATAERREN AXI MM Write Error when writing data +*\*\ - SGDMA_INTSTS_RDATAERR AXI MM Read Error when reading data +*\*\ - SGDMA_INTSTS_WDESCERR AXI MM Write Error when writing a descriptor +*\*\ - SGDMA_INTSTS_RDESCERR AXI MM Read Error when reading a descriptor +*\*\ - SGDMA_INTSTS_EOD End-Of-Descriptor +*\*\ - SGDMA_INTSTS_AOOD Channel is Almost Out of Descriptors +*\*\ - SGDMA_INTSTS_OOD Out Of Descriptors +*\*\ - SGDMA_INTSTS_EOFIN End-Of-Frame sampled at the input of the channel +*\*\ - SGDMA_INTSTS_EOFOUT End-Of-Frame sampled at the output of the channel +*\*\ - SGDMA_INTSTS_GINT Global interrupt status bit for the Channel +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SGDMA_ConfigInt(JPEG_SGDMA_Module* SGDMAx, uint32_t SGDMA_INT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SGDMAx->IE |= SGDMA_INT; + } + else + { + SGDMAx->IE &= (~SGDMA_INT); + } +} + + +/** +*\*\name SGDMAx_GetFlagStatus. +*\*\fun Check whether the specified SGDMA flag is set or not. +*\*\param SGDMAx : +*\*\ - JPEG_SGDMA_P2H +*\*\ - JPEG_SGDMA_H2P +*\*\param Flag : +*\*\ - SGDMA_INTSTS_WDATAERREN AXI MM Write Error when writing data +*\*\ - SGDMA_INTSTS_RDATAERR AXI MM Read Error when reading data +*\*\ - SGDMA_INTSTS_WDESCERR AXI MM Write Error when writing a descriptor +*\*\ - SGDMA_INTSTS_RDESCERR AXI MM Read Error when reading a descriptor +*\*\ - SGDMA_INTSTS_EOD End-Of-Descriptor +*\*\ - SGDMA_INTSTS_AOOD Channel is Almost Out of Descriptors +*\*\ - SGDMA_INTSTS_OOD Out Of Descriptors +*\*\ - SGDMA_INTSTS_EOFIN End-Of-Frame sampled at the input of the channel +*\*\ - SGDMA_INTSTS_EOFOUT End-Of-Frame sampled at the output of the channel +*\*\ - SGDMA_INTSTS_GINT Global interrupt status bit for the Channel +*\*\ - SGDMA_INTSTS_BUSY H2P/P2H is processing a transfer +*\*\return FlagStatus +*\*\ - RESET +*\*\ - SET +**/ +FlagStatus SGDMAx_GetFlagStatus(JPEG_SGDMA_Module* SGDMAx, uint32_t Flag) +{ + FlagStatus status_value; + if((SGDMAx->STS & Flag) == Flag ) + { + status_value = SET; + } + else + { + status_value = RESET; + } + return status_value; +} + + +/** +*\*\name SGDMAx_GetIntStatus. +*\*\fun Check whether the specified SGDMA interrupt is set or not. +*\*\param SGDMAx : +*\*\ - JPEG_SGDMA_P2H +*\*\ - JPEG_SGDMA_H2P +*\*\param Flag : +*\*\ - SGDMA_INTSTS_WDATAERREN AXI MM Write Error when writing data +*\*\ - SGDMA_INTSTS_RDATAERR AXI MM Read Error when reading data +*\*\ - SGDMA_INTSTS_WDESCERR AXI MM Write Error when writing a descriptor +*\*\ - SGDMA_INTSTS_RDESCERR AXI MM Read Error when reading a descriptor +*\*\ - SGDMA_INTSTS_EOD End-Of-Descriptor +*\*\ - SGDMA_INTSTS_AOOD Channel is Almost Out of Descriptors +*\*\ - SGDMA_INTSTS_OOD Out Of Descriptors +*\*\ - SGDMA_INTSTS_EOFIN End-Of-Frame sampled at the input of the channel +*\*\ - SGDMA_INTSTS_EOFOUT End-Of-Frame sampled at the output of the channel +*\*\ - SGDMA_INTSTS_GINT Global interrupt status bit for the Channel +*\*\return FlagStatus +*\*\ - RESET +*\*\ - SET +**/ +FlagStatus SGDMAx_GetIntStatus(JPEG_SGDMA_Module* SGDMAx, uint32_t Flag) +{ + FlagStatus status_value; + if((SGDMAx->INTSTS & Flag) == Flag ) + { + status_value = SET; + } + else + { + status_value = RESET; + } + return status_value; +} + +/** +*\*\name SGDMAx_GetFlagStatus. +*\*\fun Clears the SGDMAx's pending flags.. +*\*\param SGDMAx : +*\*\ - JPEG_SGDMA_P2H +*\*\ - JPEG_SGDMA_H2P +*\*\param Flag : +*\*\ - SGDMA_INTSTS_EOD End-Of-Descriptor +*\*\ - SGDMA_INTSTS_AOOD Channel is Almost Out of Descriptors +*\*\ - SGDMA_INTSTS_OOD Out Of Descriptors +*\*\ - SGDMA_INTSTS_EOFIN End-Of-Frame sampled at the input of the channel +*\*\ - SGDMA_INTSTS_EOFOUT End-Of-Frame sampled at the output of the channel +*\*\return none +**/ +void SGDMAx_ClrFlag(JPEG_SGDMA_Module* SGDMAx, uint32_t Flag) +{ + SGDMAx->STS = Flag; +} + + +/***** JPEG BRC module ****/ +/** +*\*\name JPEGBRC_Init. +*\*\fun Initializes the JPEG BRC peripheral according to JPEGBRC_InitStruct. +*\*\param JPEGBRC_InitStruct +*\*\ - buffer_addr +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - buffer_size +*\*\ - 0x0000 ~ 0xFFFF +*\*\ - upsample_mode +*\*\ - 0x00 ~ 0x03 +*\*\return FlagStatus +*\*\ - ERROR +*\*\ - SUCCESS +**/ +ErrorStatus JPEGBRC_Init(JPEGBRC_InitType* JPEGBRC_InitStruct) +{ + ErrorStatus status_value; + uint32_t timeout_value = 0x10000; + + /* BRC module init*/ + JPEG_BRC->INIT |= JPEGBRC_INIT_INIT; + while(timeout_value--) + { + if((JPEG_BRC->INIT & JPEGBRC_INIT_INITF) == JPEGBRC_INIT_INITF) + { + JPEG_BRC->INIT &= (~JPEGBRC_INIT_INIT); + break; + } + } + + if(timeout_value == 0) + { + status_value = ERROR; + } + else + { + status_value = SUCCESS; + } + + if(status_value == SUCCESS) + { + JPEG_BRC->BUFBADDR = JPEGBRC_InitStruct->buffer_addr; + JPEG_BRC->BUFSIZE = JPEGBRC_InitStruct->buffer_size; + JPEG_BRC->USMODE = JPEGBRC_InitStruct->upsample_mode; + } + return status_value; +} + +/** +*\*\name JPEGBRC_Enable +*\*\fun Enables or disables the specified JPEGBRC peripheral. +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void JPEGBRC_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable JPEGBRC modelu */ + JPEG_BRC->EN |= JPEGBRC_EN_EN; + } + else + { + /* Disable JPEGBRC modelu */ + JPEG_BRC->EN &= (~JPEGBRC_EN_EN); + } +} + + +/***** JPEG RBC module ****/ +/** +*\*\name JPEGRBC_Init. +*\*\fun Initializes the JPEG BRC peripheral according to JPEGRBC_InitStruct. +*\*\param JPEGRBC_InitStruct +*\*\ - pixel_format +*\*\ - JPEGRBC_4_4_4_NONINTERLEAVED +*\*\ - JPEGRBC_4_2_2_NONINTERLEAVED +*\*\ - JPEGRBC_4_2_0_NONINTERLEAVED +*\*\ - JPEGRBC_MONOCHROME +*\*\ - JPEGRBC_4_4_4_INTERLEAVED +*\*\ - JPEGRBC_4_2_2_INTERLEAVED +*\*\ - JPEGRBC_4_2_0_INTERLEAVED +*\*\ - sample_order +*\*\ - JPEGRBC_MSBSAMPLE +*\*\ - JPEGRBC_LSBSAMPLE +*\*\ - frame_width +*\*\ - 0x0000 ~ 0xFFFF +*\*\ - frame_height +*\*\ - 0x0001 ~ 0x10000 +*\*\ - component0names +*\*\ - 0x00 ~ 0xFF +*\*\ - component1names +*\*\ - 0x00 ~ 0xFF +*\*\ - component2names +*\*\ - 0x00 ~ 0xFF +*\*\ - C0startaddress +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\ - C0buffersize +*\*\ - 0x001 ~ 0x400 +*\*\return FlagStatus +*\*\ - ERROR +*\*\ - SUCCESS +**/ +ErrorStatus JPEGRBC_Init(JPEGRBC_InitType* JPEGRBC_InitStruct) +{ + ErrorStatus status_value = SUCCESS; + uint32_t timeout_value = 0x10000; + uint32_t width_mcus; + uint32_t height_mcus; + + JPEG_RBC->PFORM = JPEGRBC_InitStruct->pixel_format; + JPEG_RBC->CNAME = (JPEGRBC_InitStruct->component0names | \ + (JPEGRBC_InitStruct->component1names << REG_BIT8_OFFSET) | \ + (JPEGRBC_InitStruct->component2names << REG_BIT16_OFFSET)); + JPEG_RBC->C0SADD = JPEGRBC_InitStruct->C0startaddress; + JPEG_RBC->C0EADD = JPEGRBC_InitStruct->C0buffersize; + JPEG_RBC->FRMH = JPEGRBC_InitStruct->frame_height - 1; + JPEG_RBC->HHALF = ((JPEGRBC_InitStruct->frame_height + 1U) >> REG_BIT1_OFFSET) - 1; + + if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_4_4_4_NONINTERLEAVED) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width; + /* Round up by multiples of 8 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 7U) >> (REG_BIT3_OFFSET); + /* Round up by multiples of 8 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 7U) >> (REG_BIT3_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus - 1U); + JPEG_RBC->BPS12 = (width_mcus * height_mcus - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BLSS0 = width_mcus * 8U; + JPEG_RBC->BLSS12 = width_mcus * 8U; + + JPEG_RBC->BPRS0 = (width_mcus - 1U); + JPEG_RBC->BPRS12 = (width_mcus - 1U); + + } + else if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_4_2_2_NONINTERLEAVED) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width; + /* Round up by multiples of 8 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 7U) >> (REG_BIT3_OFFSET); + /* Round up by multiples of 8 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 7U) >> (REG_BIT3_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus - 1U); + + JPEG_RBC->BLSS0 = width_mcus * 8U; + + JPEG_RBC->BPRS0 = (width_mcus - 1U); + /* Round up by multiples of 16 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 15U) >> (REG_BIT4_OFFSET); + JPEG_RBC->BPS12 = (width_mcus * height_mcus - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BLSS12 = width_mcus * 8U; + + JPEG_RBC->BPRS12 = (width_mcus - 1U); + } + else if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_4_2_0_NONINTERLEAVED) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width; + /* Round up by multiples of 8 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 7U) >> (REG_BIT3_OFFSET); + /* Round up by multiples of 8 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 7U) >> (REG_BIT3_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + + JPEG_RBC->BLSS0 = width_mcus * 8U; + + JPEG_RBC->BPRS0 = (width_mcus - 1U); + + /* Round up by multiples of 16 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 15U) >> (REG_BIT4_OFFSET); + /* Round up by multiples of 16 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 15U) >> (REG_BIT4_OFFSET); + JPEG_RBC->BPS12 = (width_mcus * height_mcus - 1U); + + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BLSS12 = width_mcus * 8U; + + JPEG_RBC->BPRS12 = (width_mcus - 1U); + } + else if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_MONOCHROME) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width; + /* Round up by multiples of 8 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 7U) >> (REG_BIT3_OFFSET); + /* Round up by multiples of 8 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 7U) >> (REG_BIT3_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus - 1U); + JPEG_RBC->BPS12 = (width_mcus * height_mcus - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BPRS0 = (width_mcus - 1U); + JPEG_RBC->BPRS12 = (width_mcus - 1U); + + JPEG_RBC->BLSS0 = width_mcus * 8U; + JPEG_RBC->BLSS12 = width_mcus * 8U; + } + else if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_4_4_4_INTERLEAVED) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width * 3U; + /* Round up by multiples of 8 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 7U) >> (REG_BIT3_OFFSET); + /* Round up by multiples of 8 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 7U) >> (REG_BIT3_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus *3U - 1U); + JPEG_RBC->BPS12 = (width_mcus * height_mcus *3U - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BLSS0 = width_mcus * 8U * 3U; + JPEG_RBC->BLSS12 = width_mcus * 8U * 3U; + + JPEG_RBC->BPRS0 = (width_mcus * 3U - 1U); + JPEG_RBC->BPRS12 = (width_mcus * 3U - 1U); + } + else if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_4_2_2_INTERLEAVED) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width * 2U; + /* Round up by multiples of 16 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 15U) >> (REG_BIT4_OFFSET); + /* Round up by multiples of 8 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 7U) >> (REG_BIT3_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus *4U - 1U); + JPEG_RBC->BPS12 = (width_mcus * height_mcus *4U - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BLSS0 = width_mcus * 8 * 4U; + JPEG_RBC->BLSS12 = width_mcus * 8 * 4U; + + JPEG_RBC->BPRS0 = (width_mcus * 4U - 1U); + JPEG_RBC->BPRS12 = (width_mcus * 4U - 1U); + } + else if(JPEGRBC_InitStruct->pixel_format == JPEGRBC_4_2_0_INTERLEAVED) + { + JPEG_RBC->FRMW = JPEGRBC_InitStruct->frame_width * 3U; + /* Round up by multiples of 16 */ + width_mcus = (JPEGRBC_InitStruct->frame_width + 15U) >> (REG_BIT4_OFFSET); + /* Round up by multiples of 16 */ + height_mcus = (JPEGRBC_InitStruct->frame_height + 15U) >> (REG_BIT4_OFFSET); + JPEG_RBC->BPS0 = (width_mcus * height_mcus *6U - 1U); + JPEG_RBC->BPS12 = (width_mcus * height_mcus *6U - 1U); + + JPEG_RBC->ROWS0 = height_mcus - 1U; + JPEG_RBC->ROWS12 = height_mcus - 1U; + + JPEG_RBC->BLSS0 = width_mcus * 8U * 6U; + JPEG_RBC->BLSS12 = width_mcus * 8U * 6U; + + JPEG_RBC->BPRS0 = (width_mcus * 6U - 1U); + JPEG_RBC->BPRS12 = (width_mcus * 6U - 1U); + } + else + { + /* no process */ + } + + /* RBC module init*/ + JPEG_RBC->INIT |= JPEGRBC_INIT_INIT; + while((JPEG_RBC->INIT & JPEGRBC_INIT_INITF) != JPEGRBC_INIT_INITF) + { + timeout_value--; + if(timeout_value == 0U) + { + status_value = ERROR; + break; + } + } + JPEG_RBC->INIT &= (~JPEGRBC_INIT_INIT); + + return status_value; +} + + +/** +*\*\name JPEGRBC_Enable +*\*\fun Enables or disables the specified JPEGRBC peripheral. +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void JPEGRBC_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable JPEGRBC module */ + JPEG_RBC->EN |= JPEGRBC_EN_EN; + } + else + { + /* Disable JPEGRBC module */ + JPEG_RBC->EN &= (~JPEGRBC_EN_EN); + } +} + +/***** JPEG DEC module ****/ + +/** +*\*\name JPEGDEC_Enable +*\*\fun Enables or disables the specified JPEGDEC peripheral. +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void JPEGDEC_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable JPEGDEC modelu */ + JPEG_DEC->MODE |= JPEGDEC_MODE_EN; + } + else + { + /* Disable JPEGDEC modelu */ + JPEG_DEC->MODE &= (~JPEGDEC_MODE_EN); + } +} + + +/** +*\*\name JPEGDEC_GetFlagStatus. +*\*\fun Check whether the specified JPEGDEC flag is set or not. +*\*\param Flag : +*\*\ - JPEGDEC_ERROR_HTERR A Huffman table referenced in a scan (SOS header) is invalid +*\*\ - JPEGDEC_ERROR_QTERR A Quantisation table referenced in a component referenced in a scan (SOS header) selected an invalid Quantisation table +*\*\ - JPEGDEC_ERROR_CERR A component referenced in the scan header (SOS) was not defined in the previous frame header (SOF) +*\*\ - JPEGDEC_ERROR_HUF Huffman decode error detected +*\*\ - JPEGDEC_ERROR_UNEXP Unexpected marker detected +*\*\ - JPEGDEC_ERROR_UNK Unknown marker detected +*\*\return FlagStatus +*\*\ - RESET +*\*\ - SET +**/ +FlagStatus JPEGDEC_GetFlagStatus(uint32_t Flag) +{ + FlagStatus status_value; + if((JPEG_DEC->ERROR & Flag) == Flag ) + { + status_value = SET; + } + else + { + status_value = RESET; + } + return status_value; +} + + +/** +*\*\name JPEGDEC_GetUNKErrorAddress. +*\*\fun Get Unknown marker error address. +*\*\param none +*\*\return address +*\*\ - 0x00000000~0xFFFFFFFF +**/ +uint32_t JPEGDEC_GetUNKErrorAddress(void) +{ + return JPEG_DEC->UNLOC; +} + +/** +*\*\name JPEGDEC_GetUNEXPErrorAddress. +*\*\fun Get Unexpected marker error address. +*\*\param none +*\*\return address +*\*\ - 0x00000000~0xFFFFFFFF +**/ +uint32_t JPEGDEC_GetUNEXPErrorAddress(void) +{ + return JPEG_DEC->UELOC; +} + +/** +*\*\name JPEGDEC_GetHESYMErrorAddress. +*\*\fun Get the Huffman symbol that is in error. +*\*\param none +*\*\return address +*\*\ - 0x0000~0xFFFF +**/ +uint16_t JPEGDEC_GetHESYMErrorAddress(void) +{ + return ((uint16_t)JPEG_DEC->HESYM & JPEGDEC_HESYM_HESYM); +} + +/** +*\*\name JPEGDEC_GetHESYMECSErrorAddress. +*\*\fun Get Huffman ECS Number Symbol. +*\*\param none +*\*\return address +*\*\ - 0x00000000~0xFFFFFFFF +**/ +uint32_t JPEGDEC_GetHESYMECSErrorAddress(void) +{ + return JPEG_DEC->HESYMECS; +} + +/** +*\*\name JPEGDEC_GetHUFSErrorAddress. +*\*\fun Get Unexpected marker error address. +*\*\param none +*\*\return address +*\*\ - 0x00000000~0xFFFFFFFF +**/ +uint32_t JPEGDEC_GetHUFSErrorAddress(void) +{ + return JPEG_DEC->HUF_SELOC; +} + + +/** +*\*\name JPEGDEC_TableAccessRequest. +*\*\fun JPEG DEC Table Access Request. +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return status +*\*\ - ERROR +*\*\ - SUCCESS +**/ +ErrorStatus JPEGDEC_TableAccessRequest(FunctionalState Cmd) +{ + ErrorStatus status = SUCCESS; + uint32_t count_value = 0; + + if(Cmd == DISABLE) + { + JPEG_DEC->TAB_ACCREQ &= (~JPEGDEC_TAB_ACCREQ_AQEQ); + } + else + { + JPEG_DEC->TAB_ACCREQ |= JPEGDEC_TAB_ACCREQ_AQEQ; + + while((JPEG_DEC->TAB_ACCREQ & JPEGDEC_TAB_ACCREQ_AOK) != JPEGDEC_TAB_ACCREQ_AOK) + { + count_value++; + if(count_value > 0x1000) + { + status = ERROR; + break; + } + } + } + + return status; +} + +/** +*\*\name JPEGDEC_GetHUFSErrorAddress. +*\*\fun Get Unexpected marker error address. +*\*\param TableAddress +*\*\ - JPEGDEC_EOB0_ADDRESS +*\*\ - JPEGDEC_EOB1_ADDRESS +*\*\ - JPEGDEC_EOB2_ADDRESS +*\*\ - JPEGDEC_EOB3_ADDRESS +*\*\param EOBSymbol +*\*\ - 0x0000~0xFFFF +*\*\param EOBSymbolMask +*\*\ - 0x0000~0xFFFF +*\*\return none +**/ +void JPEGDEC_SetHUFTable_EOB(uint32_t TableAddress,uint32_t EOBSymbol,uint32_t EOBSymbolMask) +{ + *(uint32_t*)(JPEG_DEC_BASE + TableAddress) = (EOBSymbol | (EOBSymbolMask << REG_BIT16_OFFSET)); +} + + +/** +*\*\name JPEGDEC_SetHuffTable. +*\*\fun Set Huffman table parameters. +*\*\param TableType +*\*\ - JPEGDEC_HUFFTABLE +*\*\ - JPEGDEC_DVECTORTABLE +*\*\ - JPEGDEC_IVECTORTABLE +*\*\ - JPEGDEC_HUFFACCTABLE +*\*\param Tableselector +*\*\ - JPEGDEC_DCTABLE +*\*\ - JPEGDEC_ACTABLE +*\*\param TableNum +*\*\ - JPEGDEC_HUFFTABLE_0 +*\*\ - JPEGDEC_HUFFTABLE_1 +*\*\ - JPEGDEC_HUFFTABLE_2 +*\*\ - JPEGDEC_HUFFTABLE_3 +*\*\param &Value +*\*\ - 0x00000000~0xFFFFFFFF +*\*\param Count +*\*\ - 0x00000000~0xFFFFFFFF +*\*\return status +*\*\ - ERROR +*\*\ - SUCCESS +**/ +ErrorStatus JPEGDEC_SetHuffTable(uint32_t TableType,uint32_t Tableselector,uint32_t TableNum,uint32_t* Value,uint32_t Count) +{ + ErrorStatus status = SUCCESS; + uint32_t regtemp = 0U; + + regtemp = (TableType | Tableselector | TableNum); + JPEG_DEC->HUF_ADDR = regtemp; + + if(Count > JPEG_DEC->HUF_REM) + { + status = ERROR; + } + else + { + /* no process */ + } + + for(regtemp = 0;regtempHUF_DATA = Value[regtemp]; + } + + return status; +} + + +/** +*\*\name JPEGDEC_SetQuantiTable. +*\*\fun Set Quantisation table parameters. +*\*\param TableAddress +*\*\ - JPEGDEC_QT0_ADDRESS +*\*\ - JPEGDEC_QT1_ADDRESS +*\*\ - JPEGDEC_QT2_ADDRESS +*\*\ - JPEGDEC_QT3_ADDRESS +*\*\param &Value +*\*\ - 0x00000000~0xFFFFFFFF +*\*\param Count +*\*\ - 0x00~0x40 +*\*\return none +**/ +void JPEGDEC_SetQuantiTable(uint32_t TableAddress,uint8_t* Value,uint32_t Count) +{ + uint32_t num; + + for(num = 0;numheader_size + 3U)/4U) + \ + ((JPEGENC_InitStruct->hufftab0_header_size + 3U)/4U) + \ + ((JPEGENC_InitStruct->hufftab1_header_size + 3U)/4U) + \ + ((JPEGENC_InitStruct->hufftab2_header_size + 3U)/4U) + \ + ((JPEGENC_InitStruct->hufftab3_header_size + 3U)/4U) + \ + ((JPEGENC_InitStruct->footer_size + 3U)/4U); + + /* Total size exceeds limit, error returned */ + if(size_word > 0x200U) + { + return ERROR; + } + + /* Huffman tables0 */ + if(JPEGENC_InitStruct->HuffmanTable0.DCcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 12U;cnt_value++) + { + JPEG_ENC->HT0.DCOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable0.DCcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable0.ACcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 160U;cnt_value++) + { + JPEG_ENC->HT0.ACOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable0.ACcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable0.DCcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT0.DCCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable0.DCcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable0.ACcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT0.ACCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable0.ACcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + JPEG_ENC->HT0.EOBS = JPEGENC_InitStruct->HuffmanTable0.EOBS; + JPEG_ENC->HT0.ZRLS = JPEGENC_InitStruct->HuffmanTable0.ZRLS; + + /* Huffman tables1 */ + if(JPEGENC_InitStruct->HuffmanTable1.DCcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 12U;cnt_value++) + { + JPEG_ENC->HT1.DCOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable1.DCcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable1.ACcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 160U;cnt_value++) + { + JPEG_ENC->HT1.ACOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable1.ACcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable1.DCcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT1.DCCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable1.DCcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable1.ACcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT1.ACCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable1.ACcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + JPEG_ENC->HT1.EOBS = JPEGENC_InitStruct->HuffmanTable1.EOBS; + JPEG_ENC->HT1.ZRLS = JPEGENC_InitStruct->HuffmanTable1.ZRLS; + + /* Huffman tables2 */ + if(JPEGENC_InitStruct->HuffmanTable2.DCcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 12U;cnt_value++) + { + JPEG_ENC->HT2.DCOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable2.DCcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable2.ACcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 160U;cnt_value++) + { + JPEG_ENC->HT2.ACOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable2.ACcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable2.DCcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT2.DCCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable2.DCcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable2.ACcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT2.ACCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable2.ACcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + JPEG_ENC->HT2.EOBS = JPEGENC_InitStruct->HuffmanTable2.EOBS; + JPEG_ENC->HT2.ZRLS = JPEGENC_InitStruct->HuffmanTable2.ZRLS; + + /* Huffman tables3 */ + if(JPEGENC_InitStruct->HuffmanTable3.DCcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 12U;cnt_value++) + { + JPEG_ENC->HT3.DCOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable3.DCcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable3.ACcode_offset != NULL) + { + for(cnt_value = 0U;cnt_value < 160U;cnt_value++) + { + JPEG_ENC->HT3.ACOL[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable3.ACcode_offset[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable3.DCcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT3.DCCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable3.DCcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + if(JPEGENC_InitStruct->HuffmanTable3.ACcode_start != NULL) + { + for(cnt_value = 0U;cnt_value < 16U;cnt_value++) + { + JPEG_ENC->HT3.ACCODE[cnt_value] = (uint32_t)JPEGENC_InitStruct->HuffmanTable3.ACcode_start[cnt_value]; + } + } + else + { + /* no process */ + } + + JPEG_ENC->HT3.EOBS = JPEGENC_InitStruct->HuffmanTable3.EOBS; + JPEG_ENC->HT3.ZRLS = JPEGENC_InitStruct->HuffmanTable3.ZRLS; + + /* File frame header */ + if(JPEGENC_InitStruct->header_address != NULL) + { + size_word = ((JPEGENC_InitStruct->header_size + 3U)/4U); + + pbuffer = (uint32_t*)JPEGENC_InitStruct->header_address; + + for(cnt_value = 0; cnt_value< size_word;cnt_value++) + { + JPEG_ENC->HFBUFFER[cnt_value] = pbuffer[cnt_value]; + } + + JPEG_ENC->HEADD = JPEGENC_InitStruct->header_size - 1; + position_temp = size_word; + } + else + { + JPEG_ENC->HEADD = 0x00U; + } + + /* Huffman table0 frame header */ + if(JPEGENC_InitStruct->hufftab0_header_address != NULL) + { + size_word = ((JPEGENC_InitStruct->hufftab0_header_size + 3U)/4U); + + pbuffer = (uint32_t*)JPEGENC_InitStruct->hufftab0_header_address; + + for(cnt_value = 0; cnt_value< size_word;cnt_value++) + { + JPEG_ENC->HFBUFFER[cnt_value + position_temp] = pbuffer[cnt_value]; + } + + JPEG_ENC->HUFTAB0E = position_temp * 4U + JPEGENC_InitStruct->hufftab0_header_size - 1; + position_temp = position_temp + size_word; + } + else + { + JPEG_ENC->HUFTAB0E = 0x00U; + } + + /* Huffman table1 frame header */ + if(JPEGENC_InitStruct->hufftab1_header_address != NULL) + { + size_word = ((JPEGENC_InitStruct->hufftab1_header_size + 3U)/4U); + + pbuffer = (uint32_t*)JPEGENC_InitStruct->hufftab1_header_address; + + for(cnt_value = 0; cnt_value< size_word;cnt_value++) + { + JPEG_ENC->HFBUFFER[cnt_value + position_temp] = pbuffer[cnt_value]; + } + + JPEG_ENC->HUFTAB1E = position_temp * 4U + JPEGENC_InitStruct->hufftab1_header_size - 1; + position_temp = position_temp + size_word; + } + else + { + JPEG_ENC->HUFTAB1E = 0x00U; + } + + /* Huffman table2 frame header */ + if(JPEGENC_InitStruct->hufftab2_header_address != NULL) + { + size_word = ((JPEGENC_InitStruct->hufftab2_header_size + 3U)/4U); + + pbuffer = (uint32_t*)JPEGENC_InitStruct->hufftab2_header_address; + + for(cnt_value = 0; cnt_value< size_word;cnt_value++) + { + JPEG_ENC->HFBUFFER[cnt_value + position_temp] = pbuffer[cnt_value]; + } + + JPEG_ENC->HUFTAB2E = position_temp * 4U + JPEGENC_InitStruct->hufftab2_header_size - 1; + position_temp = position_temp + size_word; + } + else + { + JPEG_ENC->HUFTAB2E = 0x00U; + } + + /* Huffman table3 frame header */ + if(JPEGENC_InitStruct->hufftab3_header_address != NULL) + { + size_word = ((JPEGENC_InitStruct->hufftab3_header_size + 3U)/4U); + + pbuffer = (uint32_t*)JPEGENC_InitStruct->hufftab3_header_address; + + for(cnt_value = 0; cnt_value< size_word;cnt_value++) + { + JPEG_ENC->HFBUFFER[cnt_value + position_temp] = pbuffer[cnt_value]; + } + + JPEG_ENC->HUFTAB0E = position_temp * 4U + JPEGENC_InitStruct->hufftab3_header_size - 1; + position_temp = position_temp + size_word; + } + else + { + JPEG_ENC->HUFTAB3E = 0x00U; + } + + /* File frame footer */ + if(JPEGENC_InitStruct->footer_address != NULL) + { + size_word = ((JPEGENC_InitStruct->footer_size + 3U)/4U); + + pbuffer = (uint32_t*)JPEGENC_InitStruct->footer_address; + + for(cnt_value = 0; cnt_value< size_word;cnt_value++) + { + JPEG_ENC->HFBUFFER[cnt_value + position_temp] = pbuffer[cnt_value]; + } + + JPEG_ENC->FEADD = position_temp * 4U + JPEGENC_InitStruct->footer_size - 1; + } + else + { + JPEG_ENC->FEADD = 0x00U; + } + + /* Header parts out select */ + JPEG_ENC->HSEL = JPEGENC_InitStruct->output_select; + + /* Quantisation table 0 */ + if(JPEGENC_InitStruct->QT0_address != NULL) + { + for(cnt_value = 0; cnt_value< 64U;cnt_value++) + { + JPEG_ENC->QT0[cnt_value] = (uint32_t)JPEGENC_InitStruct->QT0_address[cnt_value]; + } + } + else + { + /* no process */ + } + + /* Quantisation table 1 */ + if(JPEGENC_InitStruct->QT1_address != NULL) + { + for(cnt_value = 0; cnt_value< 64U;cnt_value++) + { + JPEG_ENC->QT1[cnt_value] = (uint32_t)JPEGENC_InitStruct->QT1_address[cnt_value]; + } + } + else + { + /* no process */ + } + + /* Quantisation table 2 */ + if(JPEGENC_InitStruct->QT2_address != NULL) + { + for(cnt_value = 0; cnt_value< 64U;cnt_value++) + { + JPEG_ENC->QT2[cnt_value] = (uint32_t)JPEGENC_InitStruct->QT2_address[cnt_value]; + } + } + else + { + /* no process */ + } + + /* Quantisation table 3 */ + if(JPEGENC_InitStruct->QT3_address != NULL) + { + for(cnt_value = 0; cnt_value< 64U;cnt_value++) + { + JPEG_ENC->QT3[cnt_value] = (uint32_t)JPEGENC_InitStruct->QT3_address[cnt_value]; + } + } + else + { + /* no process */ + } + + /* restart interval configure */ + JPEG_ENC->RICTRL = (JPEGENC_InitStruct->restart_interval | (JPEGENC_InitStruct->interval_num - 1U)); + + /* JPEG ENC CTRL register */ + JPEG_ENC->CTRL = ((JPEGENC_InitStruct->Corereset << REG_BIT1_OFFSET) |\ + (JPEGENC_InitStruct->C0HT_select << REG_BIT4_OFFSET) |\ + (JPEGENC_InitStruct->C1HT_select << REG_BIT6_OFFSET) |\ + (JPEGENC_InitStruct->C2HT_select << REG_BIT8_OFFSET) |\ + (JPEGENC_InitStruct->C3HT_select << REG_BIT10_OFFSET) |\ + (JPEGENC_InitStruct->C0QT_select << REG_BIT12_OFFSET) |\ + (JPEGENC_InitStruct->C1QT_select << REG_BIT14_OFFSET) |\ + (JPEGENC_InitStruct->C2QT_select << REG_BIT16_OFFSET) |\ + (JPEGENC_InitStruct->C3QT_select << REG_BIT18_OFFSET)); + + return status; +} + + +/** +*\*\name JPEGENC_Enable +*\*\fun Enables or disables table output in output stream. +*\*\param outputsel (The input parameters must be the following values): +*\*\ - JPEGENC_OUTPUT_QT0 +*\*\ - JPEGENC_OUTPUT_QT1 +*\*\ - JPEGENC_OUTPUT_QT2 +*\*\ - JPEGENC_OUTPUT_QT3 +*\*\ - JPEGENC_OUTPUT_HT0 +*\*\ - JPEGENC_OUTPUT_HT1 +*\*\ - JPEGENC_OUTPUT_HT2 +*\*\ - JPEGENC_OUTPUT_HT3 +*\*\ - JPEGENC_OUTPUT_ONLY +*\*\ - JPEGENC_OUTPUT_NOECS +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void JPEGENC_OutputEnable(uint32_t outputsel,FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + JPEG_ENC->HSEL |= outputsel; + } + else + { + JPEG_ENC->HSEL &= (~outputsel); + } +} + + +/** +*\*\name JPEGENC_Enable +*\*\fun Enables or disables the specified JPEGENC peripheral. +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void JPEGENC_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable JPEGENC module */ + JPEG_ENC->CTRL |= JPEGENC_CTRL_EN; + } + else + { + /* Disable JPEGENC module */ + JPEG_ENC->HSEL &= (~JPEGENC_CTRL_EN); + } +} + + +/** +*\*\name JPEGENC_DynamicAdjustEnable +*\*\fun Enables or disables dynamic adjustment. +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void JPEGENC_DynamicAdjustEnable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + JPEG_ENC->DYNRCFG |= JPEGENC_DYNRCFG_DYNEN; + } + else + { + JPEG_ENC->DYNRCFG &= JPEGENC_DYNRCFG_DYNEN; + } +} + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lcdc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lcdc.c new file mode 100644 index 0000000000..7fc3595537 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lcdc.c @@ -0,0 +1,1160 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_lcdc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ + +#include "n32h76x_78x_lcdc.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name LCDC_DeInit +*\*\fun Deinitializes the LCDC registers. +*\*\param none +*\*\return none +**/ +void LCDC_DeInit(void) +{ + RCC_EnableAXIPeriphReset2(RCC_AXI_PERIPHRST_LCDC); +} + +/** +*\*\name LCDC_Init +*\*\fun Initializes the LCDC. +*\*\param LCDC_InitStruct: refer to the definition of LCDC_InitType +*\*\ - LCDC_HSPolarity +*\*\ * LCDC_HSPolarity_LOW +*\*\ * LCDC_HSPolarity_HIGH +*\*\ - LCDC_VSPolarity +*\*\ * LCDC_VSPolarity_LOW +*\*\ * LCDC_VSPolarity_HIGH +*\*\ - LCDC_DEPolarity +*\*\ * LCDC_DEPolarity_LOW +*\*\ * LCDC_DEPolarity_HIGH +*\*\ - LCDC_PCPolarity +*\*\ * LCDC_PCPolarity_IPC +*\*\ * LCDC_PCPolarity_IIPC +*\*\ - LCDC_HorizontalSync +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_VerticalSync +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedHBP +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedVBP +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedActiveW +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedActiveH +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_TotalWidth +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_TotalHeight +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_BackgroundRedValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BackgroundGreenValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BackgroundBlueValue +*\*\ * 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_Init(LCDC_InitType* LCDC_InitStruct) +{ + uint32_t tmpgctrl; + uint32_t tmpbgcctrl; + + /* Configure the HS, VS, DE and PC polarity */ + /* Get the LCDC_GCTRL register value */ + tmpgctrl = LCDC->GCTRL; + /* Clear PCLKPOL/DEPOL/VSPOL/HSPOL bits */ + tmpgctrl &= ~(LCDC_GCTRL_HSPOL | LCDC_GCTRL_VSPOL | LCDC_GCTRL_DEPOL | LCDC_GCTRL_PCLKPOL); + /* Set PCLKPOL/DEPOL/VSPOL/HSPOL bits */ + tmpgctrl |= (uint32_t)(LCDC_InitStruct->LCDC_HSPolarity | LCDC_InitStruct->LCDC_VSPolarity | LCDC_InitStruct->LCDC_DEPolarity | LCDC_InitStruct->LCDC_PCPolarity); + /* Write to LCDC_GCTRL */ + LCDC->GCTRL = (uint32_t)tmpgctrl; + + /* Set Synchronization size */ + LCDC->SYNCCTRL = (uint32_t)((LCDC_InitStruct->LCDC_HorizontalSync << 16) | LCDC_InitStruct->LCDC_VerticalSync); + + /* Set Accumulated Back porch */ + LCDC->BPCTRL = (uint32_t)((LCDC_InitStruct->LCDC_AccumulatedHBP << 16) | LCDC_InitStruct->LCDC_AccumulatedVBP); + + /* Set Accumulated Active Width */ + LCDC->AWCTRL = (uint32_t)((LCDC_InitStruct->LCDC_AccumulatedActiveW << 16) | LCDC_InitStruct->LCDC_AccumulatedActiveH); + + /* Set Total Width */ + LCDC->TWCTRL = (uint32_t)((LCDC_InitStruct->LCDC_TotalWidth << 16) | LCDC_InitStruct->LCDC_TotalHeight); + + /* Configure the background color value */ + /* Get the LCDC_BGCCTRL register value */ + tmpbgcctrl = LCDC->BGCCTRL; + /* Clear BCR/BCG/BCB bits */ + tmpbgcctrl &= ~(LCDC_BGCCTRL_BCR | LCDC_BGCCTRL_BCG | LCDC_BGCCTRL_BCB); + /* Set BCR/BCG/BCB bits */ + tmpbgcctrl |= (uint32_t)((LCDC_InitStruct->LCDC_BackgroundRedValue << 16) | (LCDC_InitStruct->LCDC_BackgroundGreenValue << 8) | LCDC_InitStruct->LCDC_BackgroundBlueValue); + /* Write to LCDC_BGCCTRL */ + LCDC->BGCCTRL = (uint32_t)tmpbgcctrl; +} + +/** +*\*\name LCDC_StructInit +*\*\fun Fills each LCDC_InitStruct member with its default value. +*\*\param LCDC_InitStruct: refer to the definition of LCDC_InitType +*\*\ - LCDC_HSPolarity +*\*\ * LCDC_HSPolarity_LOW +*\*\ * LCDC_HSPolarity_HIGH +*\*\ - LCDC_VSPolarity +*\*\ * LCDC_VSPolarity_LOW +*\*\ * LCDC_VSPolarity_HIGH +*\*\ - LCDC_DEPolarity +*\*\ * LCDC_DEPolarity_LOW +*\*\ * LCDC_DEPolarity_HIGH +*\*\ - LCDC_PCPolarity +*\*\ * LCDC_PCPolarity_LOW +*\*\ * LCDC_PCPolarity_HIGH +*\*\ - LCDC_HorizontalSync +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_VerticalSync +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedHBP +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedVBP +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedActiveW +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_AccumulatedActiveH +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_TotalWidth +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_TotalHeight +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_BackgroundRedValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BackgroundGreenValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BackgroundBlueValue +*\*\ * 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_StructInit(LCDC_InitType* LCDC_InitStruct) +{ + /* Set the default configuration */ + LCDC_InitStruct->LCDC_HSPolarity = LCDC_HSPolarity_LOW; + LCDC_InitStruct->LCDC_VSPolarity = LCDC_VSPolarity_LOW; + LCDC_InitStruct->LCDC_DEPolarity = LCDC_DEPolarity_LOW; + LCDC_InitStruct->LCDC_PCPolarity = LCDC_PCPolarity_IPC; + LCDC_InitStruct->LCDC_HorizontalSync = 0x00; + LCDC_InitStruct->LCDC_VerticalSync = 0x00; + LCDC_InitStruct->LCDC_AccumulatedHBP = 0x00; + LCDC_InitStruct->LCDC_AccumulatedVBP = 0x00; + LCDC_InitStruct->LCDC_AccumulatedActiveW = 0x00; + LCDC_InitStruct->LCDC_AccumulatedActiveH = 0x00; + LCDC_InitStruct->LCDC_TotalWidth = 0x00; + LCDC_InitStruct->LCDC_TotalHeight = 0x00; + LCDC_InitStruct->LCDC_BackgroundRedValue = 0x00; + LCDC_InitStruct->LCDC_BackgroundGreenValue = 0x00; + LCDC_InitStruct->LCDC_BackgroundBlueValue = 0x00; +} + +/** +*\*\name LCDC_Enable +*\*\fun Enables or disables the specified LCDC peripheral. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LCDC_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the LCDC */ + LCDC->GCTRL |= (uint32_t)LCDC_GCTRL_EN; + } + else + { + /* Disable the LCDC */ + LCDC->GCTRL &= (uint32_t)(~LCDC_GCTRL_EN); + } +} + +/** +*\*\name LCDC_DitherEnable +*\*\fun Enables or disables the dither. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LCDC_DitherEnable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the dither */ + LCDC->GCTRL |= (uint32_t)LCDC_GCTRL_DEN; + } + else + { + /* Disable the dither */ + LCDC->GCTRL &= (uint32_t)(~LCDC_GCTRL_DEN); + } + +} + +/** +*\*\name LCDC_GetDitherWidth +*\*\fun Get the dither RGB width. +*\*\param none +*\*\return LCDC_RGBType: +*\*\ - LCDC_Blue Dither blue width +*\*\ - LCDC_Green Dither green width +*\*\ - LCDC_Red Dither red width +**/ +LCDC_RGBType LCDC_GetDitherWidth(void) +{ + LCDC_RGBType LCDC_RGB_DitherStruct; + + LCDC->GCTRL &= ~(LCDC_GCTRL_DBW | LCDC_GCTRL_DGW | LCDC_GCTRL_DRW); + + LCDC_RGB_DitherStruct.LCDC_Blue = (uint32_t)((LCDC->GCTRL >> 4) & 0x7); + LCDC_RGB_DitherStruct.LCDC_Green = (uint32_t)((LCDC->GCTRL >> 8) & 0x7); + LCDC_RGB_DitherStruct.LCDC_Red = (uint32_t)((LCDC->GCTRL >> 12) & 0x7); + + return LCDC_RGB_DitherStruct; +} + +/** +*\*\name LCDC_DitherStructInit +*\*\fun Fills each LCDC_RGB_DitherStruct member with its default value. +*\*\param LCDC_RGB_DitherStruct +*\*\ - LCDC_Blue Dither blue width +*\*\ - LCDC_Green Dither green width +*\*\ - LCDC_Red Dither red width +*\*\return none +**/ +void LCDC_DitherStructInit(LCDC_RGBType* LCDC_RGB_DitherStruct) +{ + LCDC_RGB_DitherStruct->LCDC_Blue = 0x02; + LCDC_RGB_DitherStruct->LCDC_Green = 0x02; + LCDC_RGB_DitherStruct->LCDC_Red = 0x02; +} + +/** +*\*\name LCDC_LINTPConfig +*\*\fun Define the position of the line interrupt. +*\*\param LCDC_LINTPosition +*\*\ - 0x0000 ~ 0xFFFF +*\*\return none +**/ +void LCDC_LINTPConfig(uint32_t LCDC_LINTPosition) +{ + /* Sets the Line Interrupt position */ + LCDC->LINTPCTRL = LCDC_LINTPosition; +} + +/** +*\*\name LCDC_ReloadConfig +*\*\fun Reload registers with new parameters. +*\*\param LCDC_Reload +*\*\ - LCDC_IMReload +*\*\ - LCDC_VBReload +*\*\return none +**/ +void LCDC_ReloadConfig(uint32_t LCDC_Reload) +{ + /* Sets the Reload type */ + LCDC->SRCTRL = (uint32_t)LCDC_Reload; +} + +/** +*\*\name LCDC_LayerReloadConfig +*\*\fun Reload layers registers with new parameters. +*\*\param LCDC_Reload +*\*\ - LCDC_LayerIMReload +*\*\ - LCDC_LayerVBReload +*\*\ - LCDC_LayerMGReload +*\*\return none +**/ +void LCDC_LayerReloadConfig(LCDC_Layer_Module* LCDC_Layerx, uint32_t LCDC_LayerReload) +{ + /* Sets the reload type */ + LCDC_Layerx->LSRCTRL = (uint32_t)LCDC_LayerReload; +} + +/** +*\*\name LCDC_LayerInit +*\*\fun Initializes the LCDC Layer according to the specified parameters in the LCDC_Layer_InitStruct. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param LCDC_Layer_InitStruct: refer to the definition of LCDC_Layer_InitType +*\*\ - LCDC_HorizontalStart +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_HorizontalStop +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_HorizontalScalerStop + +*\*\ - LCDC_VerticalStart +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_VerticalStop +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_VerticalScalerStop + +*\*\ - LCDC_PixelFormat +*\*\ * LCDC_Pixel_Format_ARGB8888 +*\*\ * LCDC_Pixel_Format_ABGR8888 +*\*\ * LCDC_Pixel_Format_RGBA8888 +*\*\ * LCDC_Pixel_Format_BGRA8888 +*\*\ * LCDC_Pixel_Format_RGB565 +*\*\ * LCDC_Pixel_Format_BGR565 +*\*\ * LCDC_Pixel_Format_RGB888 +*\*\ * LCDC_Pixel_Format_Custom +*\*\ - LCDC_ConstantAlpha +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_DefaultAlpha +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BlendingFactor1 +*\*\ * LCDC_BlendingFactor1_CA +*\*\ * LCDC_BlendingFactor1_PAxCA +*\*\ - LCDC_BlendingFactor2 +*\*\ * LCDC_BlendingFactor2_CA +*\*\ * LCDC_BlendingFactor2_PAxCA +*\*\ - LCDC_CFBStartAdress +*\*\ * 0x00000000 ~ 0xFFFFFFFF +*\*\ - LCDC_AFB0StartAdress + +*\*\ - LCDC_AFB1StartAdress + +*\*\ - LCDC_CFBLineLength +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_CFBPitch +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_CFBLineNumber +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_DefaultColorBlue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_DefaultColorGreen +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_DefaultColorRed +*\*\ * 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_LayerInit(LCDC_Layer_Module* LCDC_Layerx, LCDC_Layer_InitType* LCDC_Layer_InitStruct) +{ + uint32_t tmpwhpctrl; + uint32_t tmpwvpctrl; + uint32_t tmppfctrl; + uint32_t tmpdcctrl; + uint32_t tmpcactrl; + uint32_t tmpbfctrl; + uint32_t tmpcfbaddr; + uint32_t tmpcfblen; + uint32_t tmpcfblnum; + /* Configures the horizontal start and stop position */ + /* Get the LCDC_WHPCTRL register value */ + tmpwhpctrl = LCDC_Layerx->WHPCTRL; + /* Clear WHSTPOS/WHSPPOS bits */ + tmpwhpctrl &= ~(LCDC_WHPCTRL_WHSTPOS | LCDC_WHPCTRL_WHSPPOS); + /* Set WHSTPOS/WHSPPOS bits */ + tmpwhpctrl |= (uint32_t)((LCDC_Layer_InitStruct->LCDC_HorizontalStop << 16) | (LCDC_Layer_InitStruct->LCDC_HorizontalStart)); + /* Write to LCDC_WHPCTRL */ + LCDC_Layerx->WHPCTRL = (uint32_t)tmpwhpctrl; + + /* Configures the vertical start and stop position */ + /* Get the LCDC_WVPCTRL register value */ + tmpwvpctrl = LCDC_Layerx->WVPCTRL; + /* Clear WVSTPOS/WVSPPOS bits */ + tmpwvpctrl &= ~(LCDC_WVPCTRL_WVSTPOS | LCDC_WVPCTRL_WVSPPOS); + /* Set WVSTPOS/WVSPPOS bits */ + tmpwvpctrl |= (uint32_t)((LCDC_Layer_InitStruct->LCDC_VerticalStop << 16) | (LCDC_Layer_InitStruct->LCDC_VerticalStart)); + /* Write to LCDC_WVPCTRL */ + LCDC_Layerx->WVPCTRL = (uint32_t)tmpwvpctrl; + + /* Specifies the pixel format */ + /* Get the LCDC_PFCTRL register value */ + tmppfctrl = LCDC_Layerx->PFCTRL; + /* Clear PF bits */ + tmppfctrl &= ~LCDC_PFCTRL_PF; + /* Set PF bits */ + tmppfctrl |= (uint32_t)(LCDC_Layer_InitStruct->LCDC_PixelFormat); + /* Write to LCDC_PFCTRL */ + LCDC_Layerx->PFCTRL = (uint32_t)tmppfctrl; + + /* Configures the default color values */ + /* Get the LCDC_DCCTRL register value */ + tmpdcctrl = LCDC_Layerx->DCCTRL; + /* Clear DCA/DCR/DCG/DCB bits */ + tmpdcctrl &= ~(LCDC_DCCTRL_DCA | LCDC_DCCTRL_DCR | LCDC_DCCTRL_DCG | LCDC_DCCTRL_DCB); + /* Set DCA/DCR/DCG/DCB bits */ + tmpdcctrl |= (uint32_t)((LCDC_Layer_InitStruct->LCDC_DefaultAlpha << 24) | (LCDC_Layer_InitStruct->LCDC_DefaultColorRed << 16) | \ + (LCDC_Layer_InitStruct->LCDC_DefaultColorGreen << 8) | (LCDC_Layer_InitStruct->LCDC_DefaultColorBlue)); + /* Write to LCDC_DCCTRL */ + LCDC_Layerx->DCCTRL = (uint32_t)tmpdcctrl; + + /* Specifies the constant alpha value */ + /* Get the LCDC_CACTRL register value */ + tmpcactrl = LCDC_Layerx->CACTRL; + /* Clear CA bits */ + tmpcactrl &= ~LCDC_CACTRL_CA; + /* Set CA bits */ + tmpcactrl |= (uint32_t)(LCDC_Layer_InitStruct->LCDC_ConstantAlpha); + /* Write to LCDC_CACTRL */ + LCDC_Layerx->CACTRL = (uint32_t)tmpcactrl; + + /* Specifies the blending factors */ + /* Get the LCDC_BFCTRL register value */ + tmpbfctrl = LCDC_Layerx->BFCTRL; + /* Clear BF1/BF2 bits */ + tmpbfctrl &= ~(LCDC_BFCTRL_BF1 | LCDC_BFCTRL_BF2); + /* Set BF1/BF2 bits */ + tmpbfctrl |= (uint32_t)((LCDC_Layer_InitStruct->LCDC_BlendingFactor1) | (LCDC_Layer_InitStruct->LCDC_BlendingFactor2)); + /* Write to LCDC_BFCTRL */ + LCDC_Layerx->BFCTRL = (uint32_t)tmpbfctrl; + + /* Configures the color frame buffer start address */ + /* Get the LCDC_CFBADDR register value */ + tmpcfbaddr = LCDC_Layerx->CFBADDR; + /* Clear CFBADDR bits */ + tmpcfbaddr &= ~(LCDC_CFBADDR_CFBADDR); + /* Set CFBADDR bits */ + tmpcfbaddr |= (uint32_t)(LCDC_Layer_InitStruct->LCDC_CFBStartAdress); + /* Write to LCDC_CFBADDR */ + LCDC_Layerx->CFBADDR = (uint32_t)tmpcfbaddr; + + /* Configures the color frame buffer pitch in byte */ + /* Get the LCDC_CFBLEN register value */ + tmpcfblen = LCDC_Layerx->CFBLEN; + /* Clear CFBLLEN/CFBP bits */ + tmpcfblen &= ~(LCDC_CFBLEN_CFBLLEN | LCDC_CFBLEN_CFBP); + /* Set CFBLLEN/CFBP bits */ + tmpcfblen |= (uint32_t)((LCDC_Layer_InitStruct->LCDC_CFBPitch << 16) | (LCDC_Layer_InitStruct->LCDC_CFBLineLength)); + /* Write to LCDC_CFBLEN */ + LCDC_Layerx->CFBLEN = (uint32_t)tmpcfblen; + + /* Configures the frame buffer line number */ + /* Get the LCDC_CFBLNUM register value */ + tmpcfblnum = LCDC_Layerx->CFBLNUM; + /* Clear CFBLNUM bits */ + tmpcfblnum &= ~(LCDC_CFBLNUM_CFBLNUM); + /* Set CFBLNUM bits */ + tmpcfblnum |= (uint32_t)(LCDC_Layer_InitStruct->LCDC_CFBLineNumber); + /* Write to LCDC_CFBLNUM */ + LCDC_Layerx->CFBLNUM = (uint32_t)tmpcfblnum; + +} + +/** +*\*\name LCDC_LayerStructInit +*\*\fun Fills each LCDC_Layer_InitStruct member with its default value. +*\*\param LCDC_Layer_InitStruct: refer to the definition of LCDC_Layer_InitType +*\*\ - LCDC_HorizontalStart +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_HorizontalStop +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_HorizontalScalerStop + +*\*\ - LCDC_VerticalStart +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_VerticalStop +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_VerticalScalerStop + +*\*\ - LCDC_PixelFormat +*\*\ * LCDC_Pixel_Format_ARGB8888 +*\*\ * LCDC_Pixel_Format_ABGR8888 +*\*\ * LCDC_Pixel_Format_RGBA8888 +*\*\ * LCDC_Pixel_Format_BGRA8888 +*\*\ * LCDC_Pixel_Format_RGB565 +*\*\ * LCDC_Pixel_Format_BGR565 +*\*\ * LCDC_Pixel_Format_RGB888 +*\*\ * LCDC_Pixel_Format_Custom +*\*\ - LCDC_ConstantAlpha +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_DefaultAlpha +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BlendingFactor1 +*\*\ * LCDC_BlendingFactor1_CA +*\*\ * LCDC_BlendingFactor1_PAxCA +*\*\ - LCDC_BlendingFactor2 +*\*\ * LCDC_BlendingFactor2_CA +*\*\ * LCDC_BlendingFactor2_PAxCA +*\*\ - LCDC_CFBStartAdress +*\*\ * 0x00000000 ~ 0xFFFFFFFF +*\*\ - LCDC_AFB0StartAdress + +*\*\ - LCDC_AFB1StartAdress + +*\*\ - LCDC_CFBLineLength +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_CFBPitch +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_CFBLineNumber +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - LCDC_DefaultColorBlue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_DefaultColorGreen +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_DefaultColorRed +*\*\ * 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_LayerStructInit(LCDC_Layer_InitType* LCDC_Layer_InitStruct) +{ + /* Set the default configuration */ + LCDC_Layer_InitStruct->LCDC_HorizontalStart = 0x00; + LCDC_Layer_InitStruct->LCDC_HorizontalStop = 0x00; + LCDC_Layer_InitStruct->LCDC_HorizontalScalerStop = 0x00; + LCDC_Layer_InitStruct->LCDC_VerticalStart = 0x00; + LCDC_Layer_InitStruct->LCDC_VerticalStop = 0x00; + LCDC_Layer_InitStruct->LCDC_VerticalScalerStop = 0x00; + LCDC_Layer_InitStruct->LCDC_PixelFormat = LCDC_Pixel_Format_ARGB8888; + LCDC_Layer_InitStruct->LCDC_ConstantAlpha = 0xFF; + LCDC_Layer_InitStruct->LCDC_DefaultAlpha = 0x00; + LCDC_Layer_InitStruct->LCDC_BlendingFactor1 = LCDC_BlendingFactor1_PAxCA; + LCDC_Layer_InitStruct->LCDC_BlendingFactor2 = LCDC_BlendingFactor2_PAxCA; + LCDC_Layer_InitStruct->LCDC_CFBStartAdress = 0x00; + LCDC_Layer_InitStruct->LCDC_AFB0StartAdress = 0x00; + LCDC_Layer_InitStruct->LCDC_AFB1StartAdress = 0x00; + LCDC_Layer_InitStruct->LCDC_CFBLineLength = 0x00; + LCDC_Layer_InitStruct->LCDC_CFBLineNumber = 0x00; + LCDC_Layer_InitStruct->LCDC_CFBPitch = 0x00; + LCDC_Layer_InitStruct->LCDC_DefaultColorBlue = 0x00; + LCDC_Layer_InitStruct->LCDC_DefaultColorGreen = 0x00; + LCDC_Layer_InitStruct->LCDC_DefaultColorRed = 0x00; +} + +void LCDC_LayerEnable(LCDC_Layer_Module* LCDC_Layerx , FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the LCDC layer */ + LCDC_Layerx->LCTRL |= (uint32_t)LCDC_LCTRL_LEN; + } + else + { + /* Disable the LCDC layer */ + LCDC_Layerx->LCTRL &= (uint32_t)(~LCDC_LCTRL_LEN); + } +} + +LCDC_PosType LCDC_GetPosStatus(void) +{ + LCDC_PosType LCDC_Pos_InitStruct; + + LCDC->CPSTS &= ~(LCDC_CPSTS_CYPOS | LCDC_CPSTS_CXPOS); + + LCDC_Pos_InitStruct.LCDC_POSX = (uint32_t)(LCDC->CPSTS >> 16); + LCDC_Pos_InitStruct.LCDC_POSY = (uint32_t)(LCDC->CPSTS & 0xFFFF); + + return LCDC_Pos_InitStruct; +} + +void LCDC_PosStructInit(LCDC_PosType* LCDC_Pos_InitStruct) +{ + LCDC_Pos_InitStruct->LCDC_POSX = 0x00; + LCDC_Pos_InitStruct->LCDC_POSY = 0x00; +} + +FlagStatus LCDC_GetCDStatus(uint32_t LCDC_CD) +{ + FlagStatus bitstatus; + + if ((LCDC->CDSTS & LCDC_CD) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name LCDC_ColorKeyingConfig +*\*\fun Set and configure the color keying. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param LCDC_ColorKeying_InitStruct: refer to the definition of LCDC_ColorKeying_InitType +*\*\ - LCDC_ColorKeyBlue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_ColorKeyGreen +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_ColorKeyRed +*\*\ * 0x00 ~ 0xFF +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LCDC_ColorKeyingConfig(LCDC_Layer_Module* LCDC_Layerx, LCDC_ColorKeying_InitType* LCDC_ColorKeying_InitStruct, FunctionalState Cmd) +{ + uint32_t tmpckctrl; + + if (Cmd != DISABLE) + { + /* Enable LCDC color keying by setting COLKEN bit */ + LCDC_Layerx->LCTRL |= (uint32_t)LCDC_LCTRL_CKEN; + + /* Sets the color keying values */ + tmpckctrl = LCDC_Layerx ->CKCTRL; + tmpckctrl &= (LCDC_CKCTRL_CKR | LCDC_CKCTRL_CKG | LCDC_CKCTRL_CKB); + tmpckctrl |= ((LCDC_ColorKeying_InitStruct->LCDC_ColorKeyRed << 16) | (LCDC_ColorKeying_InitStruct->LCDC_ColorKeyGreen << 8) | (LCDC_ColorKeying_InitStruct->LCDC_ColorKeyBlue)); + LCDC_Layerx->LCTRL = (uint32_t)tmpckctrl; + } + else + { + /* Disable LCDC color keying by clearing COLKEN bit */ + LCDC_Layerx->LCTRL &= (uint32_t)(~LCDC_LCTRL_CKEN); + } + + /* Reload shadow register */ + LCDC->SRCTRL = (uint32_t)LCDC_IMReload; +} + +/** +*\*\name LCDC_ColorKeyingStructInit +*\*\fun Fills each LCDC_ColorKeying_InitStruct member with its default value. +*\*\param LCDC_ColorKeying_InitStruct: refer to the definition of LCDC_ColorKeying_InitType +*\*\ - LCDC_ColorKeyBlue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_ColorKeyGreen +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_ColorKeyRed +*\*\ * 0x00 ~ 0xFF +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LCDC_ColorKeyingStructInit(LCDC_ColorKeying_InitType* LCDC_ColorKeying_InitStruct) +{ + /* Initialize the color keying values */ + LCDC_ColorKeying_InitStruct->LCDC_ColorKeyBlue = 0x00; + LCDC_ColorKeying_InitStruct->LCDC_ColorKeyGreen = 0x00; + LCDC_ColorKeying_InitStruct->LCDC_ColorKeyRed = 0x00; +} + +/** +*\*\name LCDC_CLUTEnable +*\*\fun Enables or disables CLUT. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LCDC_CLUTEnable(LCDC_Layer_Module* LCDC_Layerx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable CLUT by setting CLUTEN bit */ + LCDC_Layerx->LCTRL |= (uint32_t)LCDC_LCTRL_CLUTEN; + } + else + { + /* Disable CLUT by clearing CLUTEN bit */ + LCDC_Layerx->LCTRL &= (uint32_t)(~LCDC_LCTRL_CLUTEN); + } + + /* Reload shadow register */ + LCDC->SRCTRL = (uint32_t)LCDC_IMReload; +} + +/** +*\*\name LCDC_CLUTInit +*\*\fun Configure the CLUT. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param LCDC_CLUT_InitStruct: refer to the definition of LCDC_CLUT_InitType +*\*\ - LCDC_CLUTAdress +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_RedValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_GreenValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BlueValue +*\*\ * 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_CLUTInit(LCDC_Layer_Module* LCDC_Layerx, LCDC_CLUT_InitType* LCDC_CLUT_InitStruct) +{ + uint32_t tmpclutwr; + + /* Set the CLUT address and RGB value */ + tmpclutwr = LCDC_Layerx ->CLUTWR; + tmpclutwr &= (LCDC_CLUTWR_CLUTADDR | LCDC_CLUTWR_CLUTR | LCDC_CLUTWR_CLUTG | LCDC_CLUTWR_CLUTB); + tmpclutwr |= ((LCDC_CLUT_InitStruct->LCDC_CLUTAdress << 24) | (LCDC_CLUT_InitStruct->LCDC_RedValue << 16) | \ + (LCDC_CLUT_InitStruct->LCDC_GreenValue << 8) | (LCDC_CLUT_InitStruct->LCDC_BlueValue)); + + LCDC_Layerx->CLUTWR = (uint32_t)tmpclutwr; +} + +/** +*\*\name LCDC_CLUTStructInit +*\*\fun Fills each LCDC_CLUT_InitStruct member with its default value. +*\*\param LCDC_CLUT_InitStruct: refer to the definition of LCDC_CLUT_InitType +*\*\ - LCDC_CLUTAdress +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_RedValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_GreenValue +*\*\ * 0x00 ~ 0xFF +*\*\ - LCDC_BlueValue +*\*\ * 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_CLUTStructInit(LCDC_CLUT_InitType* LCDC_CLUT_InitStruct) +{ + /* Initialize the CLUT address and RGB values */ + LCDC_CLUT_InitStruct->LCDC_CLUTAdress = 0x00; + LCDC_CLUT_InitStruct->LCDC_RedValue = 0x00; + LCDC_CLUT_InitStruct->LCDC_GreenValue = 0x00; + LCDC_CLUT_InitStruct->LCDC_BlueValue = 0x00; +} + + +/** +*\*\name LCDC_LayerPosition +*\*\fun Reconfigure the layer position. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param OffsetX +*\*\ - 0x0000 ~ 0xFFFF +*\*\param OffsetY +*\*\ - 0x0000 ~ 0xFFFF +*\*\return none +**/ +void LCDC_LayerPosition(LCDC_Layer_Module* LCDC_Layerx, uint16_t OffsetX, uint16_t OffsetY) +{ + uint32_t tmpbpctrl; + uint32_t tmppfctrl; + uint32_t tmpcfblen; + uint32_t tmpcfblnum; + uint32_t horizontal_start; + uint32_t horizontal_stop; + uint32_t vertical_start; + uint32_t vertical_stop; + uint8_t tmp; + + LCDC_Layerx->WHPCTRL &= ~(LCDC_WHPCTRL_WHSTPOS | LCDC_WHPCTRL_WHSPPOS); + LCDC_Layerx->WVPCTRL &= ~(LCDC_WVPCTRL_WVSTPOS | LCDC_WVPCTRL_WVSPPOS); + + /* Reconfigures the horizontal and vertical start position */ + tmpbpctrl = LCDC->BPCTRL; + horizontal_start = (tmpbpctrl >> 16) + 1 + OffsetX; + vertical_start = (tmpbpctrl & 0xFFFF) + 1 + OffsetY; + + tmppfctrl = LCDC_Layerx ->PFCTRL; + + if((tmppfctrl == LCDC_Pixel_Format_ARGB8888) | (tmppfctrl == LCDC_Pixel_Format_ABGR8888) | (tmppfctrl == LCDC_Pixel_Format_RGBA8888) | (tmppfctrl == LCDC_Pixel_Format_BGRA8888)) + { + tmp = 4; + } + else if(tmppfctrl == LCDC_Pixel_Format_RGB888) + { + tmp = 3; + } + else if((tmppfctrl == LCDC_Pixel_Format_RGB565) | (tmppfctrl == LCDC_Pixel_Format_BGR565)) + { + tmp = 2; + } + else + { + + } + + tmpcfblen = LCDC_Layerx->CFBLEN; + horizontal_stop = (((tmpcfblen & 0xFFFF) - 3) / tmp) + horizontal_start - 1; + + tmpcfblnum = LCDC_Layerx->CFBLNUM; + vertical_stop = (tmpcfblnum & 0xFFFF) + vertical_start - 1; + + LCDC_Layerx->WHPCTRL = horizontal_start | (horizontal_stop << 16); + LCDC_Layerx->WVPCTRL = vertical_start | (vertical_stop << 16); +} + +/** +*\*\name LCDC_LayerAlpha +*\*\fun Reconfigure constant alpha. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param ConstantAlpha +*\*\ - 0x00 ~ 0xFF +*\*\return none +**/ +void LCDC_LayerAlpha(LCDC_Layer_Module* LCDC_Layerx, uint8_t ConstantAlpha) +{ + LCDC_Layerx -> CACTRL = ConstantAlpha; +} + +/** +*\*\name LCDC_LayerAddress +*\*\fun Reconfigure layer address. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param Address +*\*\ - 0x00000000 ~ 0xFFFFFFFF +*\*\return none +**/ +void LCDC_LayerAddress(LCDC_Layer_Module* LCDC_Layerx, uint32_t Address) +{ + LCDC_Layerx -> CFBADDR = Address; +} + +/** +*\*\name LCDC_LayerSize +*\*\fun Reconfigure layer size. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param Width +*\*\ - layer window width +*\*\param Height +*\*\ - layer window height +*\*\return none +**/ +void LCDC_LayerSize(LCDC_Layer_Module* LCDC_Layerx, uint32_t Width, uint32_t Height) +{ + uint8_t tmp; + uint32_t tmppfctrl; + uint32_t tmpwhpctrl; + uint32_t tmpwvpctrl; + uint32_t horizontal_start; + uint32_t horizontal_stop; + uint32_t vertical_start; + uint32_t vertical_stop; + + tmppfctrl = LCDC_Layerx ->PFCTRL; + + if((tmppfctrl == LCDC_Pixel_Format_ARGB8888) | (tmppfctrl == LCDC_Pixel_Format_ABGR8888) | (tmppfctrl == LCDC_Pixel_Format_RGBA8888) | (tmppfctrl == LCDC_Pixel_Format_BGRA8888)) + { + tmp = 4; + } + else if(tmppfctrl == LCDC_Pixel_Format_RGB888) + { + tmp = 3; + } + else if((tmppfctrl == LCDC_Pixel_Format_RGB565) | (tmppfctrl == LCDC_Pixel_Format_BGR565)) + { + tmp = 2; + } + else + { + + } + + /* update horizontal and vertical stop */ + tmpwhpctrl = LCDC_Layerx->WHPCTRL; + horizontal_start = (tmpwhpctrl & 0xFFFF); + horizontal_stop = Width + horizontal_start - 1; + + tmpwvpctrl = LCDC_Layerx->WVPCTRL; + vertical_start = (tmpwvpctrl & 0xFFFF); + vertical_stop = Height + vertical_start - 1; + + LCDC_Layerx->WHPCTRL = horizontal_start | (horizontal_stop << 16); + LCDC_Layerx->WVPCTRL = vertical_start | (vertical_stop << 16); + + /* Reconfigures the color frame buffer pitch in byte */ + LCDC_Layerx->CFBLEN = ((Width * tmp) << 16) | ((Width * tmp) + 3); + + /* Reconfigures the frame buffer line number */ + LCDC_Layerx->CFBLNUM = Height; +} + +/** +*\*\name LCDC_LayerPixelFormat +*\*\fun Reconfigure layer pixel format. +*\*\param LCDC_Layerx: refer to the definition of LCDC_Layer_Module +*\*\ - LCDC_Layer1 +*\*\ - LCDC_Layer2 +*\*\ - LCDC_Layer3 +*\*\ - LCDC_Layer4 +*\*\param PixelFormat +*\*\ - LCDC_Pixel_Format_ARGB8888 +*\*\ - LCDC_Pixel_Format_ABGR8888 +*\*\ - LCDC_Pixel_Format_RGBA8888 +*\*\ - LCDC_Pixel_Format_BGRA8888 +*\*\ - LCDC_Pixel_Format_RGB565 +*\*\ - LCDC_Pixel_Format_BGR565 +*\*\ - LCDC_Pixel_Format_RGB888 +*\*\return none +**/ +void LCDC_LayerPixelFormat(LCDC_Layer_Module* LCDC_Layerx, uint32_t PixelFormat) +{ + uint8_t tmp; + uint32_t tmppfctrl; + uint32_t tmpcfblen; + + tmppfctrl = LCDC_Layerx ->PFCTRL; + + if((tmppfctrl == LCDC_Pixel_Format_ARGB8888) | (tmppfctrl == LCDC_Pixel_Format_ABGR8888) | (tmppfctrl == LCDC_Pixel_Format_RGBA8888) | (tmppfctrl == LCDC_Pixel_Format_BGRA8888)) + { + tmp = 4; + } + else if(tmppfctrl == LCDC_Pixel_Format_RGB888) + { + tmp = 3; + } + else if((tmppfctrl == LCDC_Pixel_Format_RGB565) | (tmppfctrl == LCDC_Pixel_Format_BGR565)) + { + tmp = 2; + } + else + { + + } + + tmpcfblen = (LCDC_Layerx->CFBLEN >> 16); + tmpcfblen = (tmpcfblen / tmp); + + if((PixelFormat == LCDC_Pixel_Format_ARGB8888) | (PixelFormat == LCDC_Pixel_Format_ABGR8888) | (PixelFormat == LCDC_Pixel_Format_RGBA8888) | (PixelFormat == LCDC_Pixel_Format_BGRA8888)) + { + tmp = 4; + } + else if(PixelFormat == LCDC_Pixel_Format_RGB888) + { + tmp = 3; + } + else if((PixelFormat == LCDC_Pixel_Format_RGB565) | (PixelFormat == LCDC_Pixel_Format_BGR565)) + { + tmp = 2; + } + else + { + + } + + /* Reconfigures the color frame buffer pitch in byte */ + LCDC_Layerx->CFBLEN = ((tmpcfblen * tmp) << 16) | ((tmpcfblen * tmp) + 3); + + /* Reconfigures the color frame buffer start address */ + LCDC_Layerx->PFCTRL = PixelFormat; +} + +/** +*\*\name LCDC_ConfigInt +*\*\fun Enables or disables the specified LCDC's interrupts. +*\*\param LCDC_IT +*\*\ - LCDC_INT_LIEN +*\*\ - LCDC_INT_FUIEN +*\*\ - LCDC_INT_BEIEN +*\*\ - LCDC_INT_RRIEN +*\*\ - LCDC_INT_STNSIGIEN +*\*\ - LCDC_INT_STNSYNCIEN +*\*\ - LCDC_INT_FUKIEN +*\*\ - LCDC_INT_CRCIEN +*\*\ - LCDC_INT_RFEIEN +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LCDC_ConfigInt(uint32_t LCDC_IT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + LCDC->INTEN |= (uint32_t)LCDC_IT; + } + else + { + /* Disable the Interrupt sources */ + LCDC->INTEN &= (uint32_t)(~LCDC_IT); + } +} + +/** +*\*\name LCDC_GetFlagStatus +*\*\fun Checks whether the specified LCDC flag is set or not. +*\*\param LCDC_FLAG +*\*\ - LCDC_FLAG_L +*\*\ - LCDC_FLAG_FU +*\*\ - LCDC_FLAG_BE +*\*\ - LCDC_FLAG_RR +*\*\ - LCDC_FLAG_STNSIG +*\*\ - LCDC_FLAG_STNSYNC +*\*\ - LCDC_FLAG_CRC +*\*\ - LCDC_FLAG_RFE +*\*\return The new state of LCDC_FLAG (SET or RESET). +**/ +FlagStatus LCDC_GetFlagStatus(uint32_t LCDC_FLAG) +{ + FlagStatus bitstatus; + + if ((LCDC->INTSTS & LCDC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name LCDC_ClearFlag +*\*\fun Clears the LCDC's pending flags. +*\*\param LCDC_FLAG +*\*\ - LCDC_FLAG_L +*\*\ - LCDC_FLAG_FU +*\*\ - LCDC_FLAG_BE +*\*\ - LCDC_FLAG_RR +*\*\ - LCDC_FLAG_STNSIG +*\*\ - LCDC_FLAG_STNSYNC +*\*\ - LCDC_FLAG_CRC +*\*\ - LCDC_FLAG_RFE +*\*\return none. +**/ +void LCDC_ClearFlag(uint32_t LCDC_FLAG) +{ + /* Clear the flags */ + LCDC->INTCLR = LCDC_FLAG; +} + +/** +*\*\name LCDC_GetIntStatus +*\*\fun Checks whether the specified LCDC's interrupt has occurred or not. +*\*\param LCDC_IT +*\*\ - LCDC_INT_LIEN +*\*\ - LCDC_INT_FUIEN +*\*\ - LCDC_INT_BEIEN +*\*\ - LCDC_INT_RRIEN +*\*\ - LCDC_INT_STNSIGIEN +*\*\ - LCDC_INT_STNSYNCIEN +*\*\ - LCDC_INT_FUKIEN +*\*\ - LCDC_INT_CRCIEN +*\*\ - LCDC_INT_RFEIEN +*\*\return The new state of LCDC_IT (SET or RESET). +**/ +INTStatus LCDC_GetIntStatus(uint32_t LCDC_IT) +{ + INTStatus bitstatus; + + if ((LCDC->INTSTS & LCDC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + if (((LCDC->INTEN & LCDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name LCDC_ClrIntPendingBit +*\*\fun Clears the LCDC's interrupt pending bits. +*\*\param LCDC_IT +*\*\ - LCDC_INT_LIEN +*\*\ - LCDC_INT_FUIEN +*\*\ - LCDC_INT_BEIEN +*\*\ - LCDC_INT_RRIEN +*\*\ - LCDC_INT_STNSIGIEN +*\*\ - LCDC_INT_STNSYNCIEN +*\*\ - LCDC_INT_FUKIEN +*\*\ - LCDC_INT_CRCIEN +*\*\ - LCDC_INT_RFEIEN +*\*\return none. +**/ +void LCDC_ClrIntPendingBit(uint32_t LCDC_IT) +{ + /* Clear the IT pending Bit */ + LCDC->INTCLR = LCDC_IT; +} + + + + + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lptim.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lptim.c new file mode 100644 index 0000000000..8c8745df75 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lptim.c @@ -0,0 +1,1220 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_lptim.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_lptim.h" + +/** +*\*\name LPTIM_DeInit. +*\*\fun Set LPTIMx registers to their reset values. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return none +**/ +void LPTIM_DeInit(LPTIM_Module* LPTIMx) +{ + if (LPTIMx == LPTIM1) + { + /* Reset LPTIM1 */ + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPTIM1); + } + else if (LPTIMx == LPTIM2) + { + /* Reset LPTIM2 */ + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPTIM2); + } + else if (LPTIMx == LPTIM3) + { + /* Reset LPTIM3 */ + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPTIM3); + } + else if (LPTIMx == LPTIM4) + { + /* Reset LPTIM4 */ + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPTIM4); + } + else if (LPTIMx == LPTIM5) + { + /* Reset LPTIM5 */ + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPTIM5); + } + else + { + + } +} + +/** +*\*\name LPTIM_StructInit. +*\*\fun Set each fields of the LPTIM_InitStruct structure to its default value. +*\*\param LPTIM_InitStruct: +*\*\ - Pointer to the LPTIM_InitType structure which will be initialized. +*\*\return none +**/ +void LPTIM_StructInit(LPTIM_InitType* LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LPTIM_OUTPUT_WAVEFORM_PWM; + LPTIM_InitStruct->Polarity = LPTIM_OUTPUT_POLARITY_REGULAR; +} + +/** +*\*\name LPTIM_Init. +*\*\fun Configure the LPTIMx peripheral according to the specified parameters. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param LPTIM_InitStruct: +*\*\ - Pointer to a LPTIM_InitType structure. +*\*\return SUCCESS or ERROR. +**/ +ErrorStatus LPTIM_Init(LPTIM_Module* LPTIMx, LPTIM_InitType* LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + + /* The LPTIMx_CFG register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LPTIM_IsEnabled(LPTIMx) == 1UL) + { + result = ERROR; + } + else + { + /* Set CLKSEL bitfield according to ClockSource value */ + /* Set CLKPRE bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFG, + (LPTIM_CFG_CLKSEL | LPTIM_CFG_CLKPRE | LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); + } + + return result; +} + +/** +*\*\name LPTIM_Cmd. +*\*\fun Enables or disables the specified LPTIM instance. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void LPTIM_Cmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected LPTIM instance */ + SET_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); + } + else + { + /* Disable the selected LPTIM instance */ + CLEAR_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN); + } +} + +/** +*\*\name LPTIM_IsEnabled. +*\*\fun Indicates whether the LPTIM instance is enabled. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return 1 or 0 +**/ +uint32_t LPTIM_IsEnabled(LPTIM_Module* LPTIMx) +{ + uint32_t Temp; + + /* Read the corresponding bit, set 1 to return 1, otherwise, return 0 */ + Temp = (((READ_BIT(LPTIMx->CTRL, LPTIM_CTRL_LPTIMEN) == LPTIM_CTRL_LPTIMEN) ? 1UL : 0UL)); + + return Temp; +} + +/** +*\*\name LPTIM_StartCounter. +*\*\fun Starts the LPTIM counter in the desired mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param OperatingMode (The input parameters must be the following values): +*\*\ - LPTIM_OPERATING_MODE_CONTINUOUS +*\*\ - LPTIM_OPERATING_MODE_ONESHOT +*\*\return none +*\*\note LPTIM instance must be enabled before starting the counter. +**/ +void LPTIM_StartCounter(LPTIM_Module* LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CTRL, LPTIM_CTRL_TSTCM | LPTIM_CTRL_SNGMST, OperatingMode); +} + +/** +*\*\name LPTIM_SetUpdateMode. +*\*\fun Set the LPTIM registers update mode (enable/disable register preload). +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param UpdateMode (The input parameters must be the following values): +*\*\ - LPTIM_UPDATE_MODE_IMMEDIATE +*\*\ - LPTIM_UPDATE_MODE_ENDOFPERIOD +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +**/ +void LPTIM_SetUpdateMode(LPTIM_Module* LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_RELOAD, UpdateMode); +} + +/** +*\*\name LPTIM_GetUpdateMode. +*\*\fun Get the LPTIM registers update mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return LPTIM_UPDATE_MODE_IMMEDIATE or LPTIM_UPDATE_MODE_ENDOFPERIOD +**/ +uint32_t LPTIM_GetUpdateMode(LPTIM_Module* LPTIMx) +{ + uint32_t Mode; + + /* Read the corresponding bit */ + Mode = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_RELOAD)); + + return Mode; +} + +/** +*\*\name LPTIM_SetAutoReloadValue. +*\*\fun Set the auto reload value. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param AutoReload: +*\*\ - Value between Min_Data=0x00 and Max_Data=0xFFFF +*\*\return none +*\*\note The LPTIMx_ARR register content must only be modified when the LPTIM +*\*\ is enabled. +*\*\note After a write to the LPTIMx_ARR register a new write operation to the +*\*\ same register can only be performed when the previous write operation +*\*\ is completed. Any successive write before the ARRUPD flag be set, will +*\*\ lead to unpredictable results. +**/ +void LPTIM_SetAutoReloadValue(LPTIM_Module* LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARRVAL, AutoReload); +} + +/** +*\*\name LPTIM_GetAutoReloadValue. +*\*\fun Get actual auto reload value. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF +**/ +uint32_t LPTIM_GetAutoReloadValue(LPTIM_Module* LPTIMx) +{ + uint32_t Value; + + /* Read the corresponding bit */ + Value = (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARRVAL)); + + return Value; +} + +/** +*\*\name LPTIM_SetCompareValue. +*\*\fun Set the compare value. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param CompareValue: +*\*\ - Value between Min_Data=0x00 and Max_Data=0xFFFF +*\*\return none +*\*\note After a write to the LPTIMx_CMP register a new write operation to the +*\*\ same register can only be performed when the previous write operation +*\*\ is completed. Any successive write before the CMPUPD flag be set, will +*\*\ lead to unpredictable results. +**/ +void LPTIM_SetCompareValue(LPTIM_Module* LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMPVAL, CompareValue); +} + +/** +*\*\name LPTIM_GetCompareValue. +*\*\fun Get actual compare value. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF +**/ +uint32_t LPTIM_GetCompareValue(LPTIM_Module* LPTIMx) +{ + uint32_t Value; + + /* Read the corresponding bit */ + Value = (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMPVAL)); + + return Value; +} + +/** +*\*\name LPTIM_GetCounterValue. +*\*\fun Get actual counter value. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Counter value +*\*\note When the LPTIM instance is running with an asynchronous clock, reading +*\*\ the LPTIMx_CNT register may return unreliable values. So in this case it +*\*\ is necessary to perform two consecutive read accesses and verify that the +*\*\ two returned values are identical. +**/ +uint32_t LPTIM_GetCounterValue(LPTIM_Module* LPTIMx) +{ + uint32_t Value; + + /* Read the corresponding bit */ + Value = (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNTVAL)); + + return Value; +} + +/** +*\*\name LPTIM_SetCounterMode. +*\*\fun Set the counter mode (selection of the LPTIM counter clock source). +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param CounterMode (The input parameters must be the following values): +*\*\ - LPTIM_COUNTER_MODE_INTERNAL +*\*\ - LPTIM_COUNTER_MODE_EXTERNAL +*\*\return none +*\*\note The counter mode can be set only when the LPTIM instance is disabled. +**/ +void LPTIM_SetCounterMode(LPTIM_Module* LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CNTMEN, CounterMode); +} + +/** +*\*\name LPTIM_GetCounterMode. +*\*\fun Get the counter mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return LPTIM_COUNTER_MODE_INTERNAL or LPTIM_COUNTER_MODE_EXTERNAL +**/ +uint32_t LPTIM_GetCounterMode(LPTIM_Module* LPTIMx) +{ + uint32_t Mode; + + /* Read the corresponding bit */ + Mode = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CNTMEN)); + + return Mode; +} + +/** +*\*\name LPTIM_ConfigOutput. +*\*\fun Configure the LPTIM instance output. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Waveform (The input parameters must be the following values): +*\*\ - LPTIM_OUTPUT_WAVEFORM_PWM +*\*\ - LPTIM_OUTPUT_WAVEFORM_SETONCE +*\*\param Polarity (The input parameters must be the following values): +*\*\ - LPTIM_OUTPUT_POLARITY_REGULAR +*\*\ - LPTIM_OUTPUT_POLARITY_INVERSE +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note Regarding the LPTIM output polarity the change takes effect immediately, +*\*\ so the output default value will change immediately after the polarity +*\*\ is re-configured, even before the timer is enabled. +**/ +void LPTIM_ConfigOutput(LPTIM_Module* LPTIMx, uint32_t Waveform, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE | LPTIM_CFG_WAVEPOL, Waveform | Polarity); +} + +/** +*\*\name LPTIM_SetWaveform. +*\*\fun Set waveform shape. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Waveform (The input parameters must be the following values): +*\*\ - LPTIM_OUTPUT_WAVEFORM_PWM +*\*\ - LPTIM_OUTPUT_WAVEFORM_SETONCE +*\*\return none +**/ +void LPTIM_SetWaveform(LPTIM_Module* LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVE, Waveform); +} + +/** +*\*\name LPTIM_GetWaveform. +*\*\fun Get actual waveform shape. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return LPTIM_OUTPUT_WAVEFORM_PWM or LPTIM_OUTPUT_WAVEFORM_SETONCE +**/ +uint32_t LPTIM_GetWaveform(LPTIM_Module* LPTIMx) +{ + uint32_t Waveform; + + /* Read the corresponding bit */ + Waveform = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVE)); + + return Waveform; +} + +/** +*\*\name LPTIM_SetPolarity. +*\*\fun Set output polarity. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Polarity (The input parameters must be the following values): +*\*\ - LPTIM_OUTPUT_POLARITY_REGULAR +*\*\ - LPTIM_OUTPUT_POLARITY_INVERSE +*\*\return none +**/ +void LPTIM_SetPolarity(LPTIM_Module* LPTIMx, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_WAVEPOL, Polarity); +} + +/** +*\*\name LPTIM_GetPolarity. +*\*\fun Get actual output polarity. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return LPTIM_OUTPUT_POLARITY_REGULAR or LPTIM_OUTPUT_POLARITY_INVERSE +**/ +uint32_t LPTIM_GetPolarity(LPTIM_Module* LPTIMx) +{ + uint32_t Polarity; + + /* Read the corresponding bit */ + Polarity = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_WAVEPOL)); + + return Polarity; +} + +/** +*\*\name LPTIM_SetPrescaler. +*\*\fun Set actual prescaler division ratio. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Prescaler (The input parameters must be the following values): +*\*\ - LPTIM_PRESCALER_DIV1 +*\*\ - LPTIM_PRESCALER_DIV2 +*\*\ - LPTIM_PRESCALER_DIV4 +*\*\ - LPTIM_PRESCALER_DIV8 +*\*\ - LPTIM_PRESCALER_DIV16 +*\*\ - LPTIM_PRESCALER_DIV32 +*\*\ - LPTIM_PRESCALER_DIV64 +*\*\ - LPTIM_PRESCALER_DIV128 +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note When the LPTIM is configured to be clocked by an internal clock +*\*\ source and the LPTIM counter is configured to be updated by active +*\*\ edges detected on the LPTIM external Input1, the internal clock +*\*\ provided to the LPTIM must not be prescaled. +**/ +void LPTIM_SetPrescaler(LPTIM_Module* LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPRE, Prescaler); +} + +/** +*\*\name LPTIM_GetPrescaler. +*\*\fun Get actual prescaler division ratio. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_PRESCALER_DIV1 +*\*\ - LPTIM_PRESCALER_DIV2 +*\*\ - LPTIM_PRESCALER_DIV4 +*\*\ - LPTIM_PRESCALER_DIV8 +*\*\ - LPTIM_PRESCALER_DIV16 +*\*\ - LPTIM_PRESCALER_DIV32 +*\*\ - LPTIM_PRESCALER_DIV64 +*\*\ - LPTIM_PRESCALER_DIV128 +**/ +uint32_t LPTIM_GetPrescaler(LPTIM_Module* LPTIMx) +{ + uint32_t Prescaler; + + /* Read the corresponding bit */ + Prescaler = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPRE)); + + return Prescaler; +} + +/** +*\*\name LPTIM_TimeoutCmd. +*\*\fun Enables or disables the LPTIM timeout function. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note The first trigger event will start the timer, any successive trigger +*\*\ event will reset the counter and the timer will restart. +*\*\note The timeout value corresponds to the compare value; if no trigger +*\*\ occurs within the expected time frame, the MCU is waked-up by the +*\*\ compare match event. +*\*\note A trigger event arriving when the timer is already started will be +*\*\ ignored. +**/ +void LPTIM_TimeoutCmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the LPTIM timeout function */ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); + } + else + { + /* Disable the LPTIM timeout function */ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN); + } +} + +/** +*\*\name LPTIM_IsEnabledTimeout. +*\*\fun Indicate whether the timeout function is enabled. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return 1 or 0 +**/ +uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module* LPTIMx) +{ + uint32_t Temp; + + /* Read the corresponding bit, set 1 to return 1, otherwise, return 0 */ + Temp = (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_TIMOUTEN) == LPTIM_CFG_TIMOUTEN) ? 1UL : 0UL)); + + return Temp; +} + +/** +*\*\name LPTIM_SoftwareTrigger. +*\*\fun Configure the Software trigger. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return none +**/ +void LPTIM_SoftwareTrigger(LPTIM_Module* LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN); +} + +/** +*\*\name LPTIM_ConfigTrigger. +*\*\fun Configure the external trigger used as a trigger event for the LPTIM. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Source (The input parameters must be the following values): +*\*\ - LPTIM_TRIG_SOURCE_GPIO +*\*\ - LPTIM_TRIG_SOURCE_RTCALARMA +*\*\ - LPTIM_TRIG_SOURCE_RTCALARMB +*\*\ - LPTIM_TRIG_SOURCE_RTCTAMP1 +*\*\ - LPTIM_TRIG_SOURCE_RTCTAMP2 +*\*\ - LPTIM_TRIG_SOURCE_RTCTAMP3 +*\*\ - LPTIM_TRIG_SOURCE_COMP1 +*\*\ - LPTIM_TRIG_SOURCE_COMP2 +*\*\ - LPTIM_TRIG_SOURCE_COMP3 +*\*\ - LPTIM_TRIG_SOURCE_COMP4 +*\*\param Filter (The input parameters must be the following values): +*\*\ - LPTIM_TRIG_FILTER_NONE +*\*\ - LPTIM_TRIG_FILTER_2 +*\*\ - LPTIM_TRIG_FILTER_4 +*\*\ - LPTIM_TRIG_FILTER_8 +*\*\param Polarity (The input parameters must be the following values): +*\*\ - LPTIM_TRIG_POLARITY_RISING +*\*\ - LPTIM_TRIG_POLARITY_FALLING +*\*\ - LPTIM_TRIG_POLARITY_RISING_FALLING +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note An internal clock source must be present when a digital filter is +*\*\ required for the trigger. +**/ +void LPTIM_ConfigTrigger(LPTIM_Module* LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_TRGSEL | LPTIM_CFG_TRIGFLT | LPTIM_CFG_TRGEN, Source | Filter | Polarity); +} + +/** +*\*\name LPTIM_GetTriggerSource. +*\*\fun Get actual external trigger source. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_TRIG_SOURCE_GPIO +*\*\ - LPTIM_TRIG_SOURCE_RTCALARMA +*\*\ - LPTIM_TRIG_SOURCE_RTCALARMB +*\*\ - LPTIM_TRIG_SOURCE_RTCTAMP1 +*\*\ - LPTIM_TRIG_SOURCE_RTCTAMP2 +*\*\ - LPTIM_TRIG_SOURCE_RTCTAMP3 +*\*\ - LPTIM_TRIG_SOURCE_COMP1 +*\*\ - LPTIM_TRIG_SOURCE_COMP2 +*\*\ - LPTIM_TRIG_SOURCE_COMP3 +*\*\ - LPTIM_TRIG_SOURCE_COMP4 +**/ +uint32_t LPTIM_GetTriggerSource(LPTIM_Module* LPTIMx) +{ + uint32_t Source; + + /* Read the corresponding bit */ + Source = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGSEL)); + + return Source; +} + +/** +*\*\name LPTIM_GetTriggerFilter. +*\*\fun Get actual external trigger filter. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_TRIG_FILTER_NONE +*\*\ - LPTIM_TRIG_FILTER_2 +*\*\ - LPTIM_TRIG_FILTER_4 +*\*\ - LPTIM_TRIG_FILTER_8 +**/ +uint32_t LPTIM_GetTriggerFilter(LPTIM_Module* LPTIMx) +{ + uint32_t Filter; + + /* Read the corresponding bit */ + Filter = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRIGFLT)); + + return Filter; +} + +/** +*\*\name LPTIM_GetTriggerPolarity. +*\*\fun Get actual external trigger polarity. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_TRIG_POLARITY_RISING +*\*\ - LPTIM_TRIG_POLARITY_FALLING +*\*\ - LPTIM_TRIG_POLARITY_RISING_FALLING +**/ +uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module* LPTIMx) +{ + uint32_t Polarity; + + /* Read the corresponding bit */ + Polarity = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_TRGEN)); + + return Polarity; +} + +/** +*\*\name LPTIM_SetClockSource. +*\*\fun Set the source of the clock used by the LPTIM instance. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param ClockSource (The input parameters must be the following values): +*\*\ - LPTIM_CLK_SOURCE_INTERNAL +*\*\ - LPTIM_CLK_SOURCE_EXTERNAL +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +**/ +void LPTIM_SetClockSource(LPTIM_Module* LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKSEL, ClockSource); +} + +/** +*\*\name LPTIM_GetClockSource. +*\*\fun Get actual LPTIM instance clock source. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_CLK_SOURCE_INTERNAL +*\*\ - LPTIM_CLK_SOURCE_EXTERNAL +**/ +uint32_t LPTIM_GetClockSource(LPTIM_Module* LPTIMx) +{ + uint32_t Source; + + /* Read the corresponding bit */ + Source = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKSEL)); + + return Source; +} + +/** +*\*\name LPTIM_ConfigClock. +*\*\fun Configure the active edge or edges used by the counter when the +*\*\ LPTIM is clocked by an external clock source. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param ClockFilter (The input parameters must be the following values): +*\*\ - LPTIM_CLK_FILTER_NONE +*\*\ - LPTIM_CLK_FILTER_2 +*\*\ - LPTIM_CLK_FILTER_4 +*\*\ - LPTIM_CLK_FILTER_8 +*\*\param ClockPolarity (The input parameters must be the following values): +*\*\ - LPTIM_CLK_POLARITY_RISING +*\*\ - LPTIM_CLK_POLARITY_FALLING +*\*\ - LPTIM_CLK_POLARITY_RISING_FALLING +*\*\ - LPTIM_CLK_POLARITY_RISING_FALLING_NO +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note When both external clock signal edges are considered active ones, +*\*\ the LPTIM must also be clocked by an internal clock source with a +*\*\ frequency equal to at least four times the external clock frequency. +*\*\note An internal clock source must be present when a digital filter is +*\*\ required for external clock. +**/ +void LPTIM_ConfigClock(LPTIM_Module* LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKFLT | LPTIM_CFG_CLKPOL, ClockFilter | ClockPolarity); +} + +/** +*\*\name LPTIM_GetClockPolarity. +*\*\fun Get actual clock polarity. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_CLK_POLARITY_RISING +*\*\ - LPTIM_CLK_POLARITY_FALLING +*\*\ - LPTIM_CLK_POLARITY_RISING_FALLING +*\*\ - LPTIM_CLK_POLARITY_RISING_FALLING_NO +**/ +uint32_t LPTIM_GetClockPolarity(LPTIM_Module* LPTIMx) +{ + uint32_t Polarity; + + /* Read the corresponding bit */ + Polarity = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); + + return Polarity; +} + +/** +*\*\name LPTIM_GetClockFilter. +*\*\fun Get actual clock digital filter. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_CLK_FILTER_NONE +*\*\ - LPTIM_CLK_FILTER_2 +*\*\ - LPTIM_CLK_FILTER_4 +*\*\ - LPTIM_CLK_FILTER_8 +**/ +uint32_t LPTIM_GetClockFilter(LPTIM_Module* LPTIMx) +{ + uint32_t Filter; + + /* Read the corresponding bit */ + Filter = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKFLT)); + + return Filter; +} + +/** +*\*\name LPTIM_SetEncoderModeClockPolarity. +*\*\fun Configure clock polarity in encoder mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param ClockPolarity (The input parameters must be the following values): +*\*\ - LPTIM_ENCODER_MODE_RISING +*\*\ - LPTIM_ENCODER_MODE_FALLING +*\*\ - LPTIM_ENCODER_MODE_RISING_FALLING +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +**/ +void LPTIM_SetEncoderModeClockPolarity(LPTIM_Module* LPTIMx, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFG, LPTIM_CFG_CLKPOL, ClockPolarity); +} + +/** +*\*\name LPTIM_GetEncoderModeClockPolarity. +*\*\fun Get clock polarity in encoder mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return Returned value can be one of the following values: +*\*\ - LPTIM_ENCODER_MODE_RISING +*\*\ - LPTIM_ENCODER_MODE_FALLING +*\*\ - LPTIM_ENCODER_MODE_RISING_FALLING +**/ +uint32_t LPTIM_GetEncoderModeClockPolarity(LPTIM_Module* LPTIMx) +{ + uint32_t Mode; + + /* Read the corresponding bit */ + Mode = (uint32_t)(READ_BIT(LPTIMx->CFG, LPTIM_CFG_CLKPOL)); + + return Mode; +} + +/** +*\*\name LPTIM_EncoderModeCmd. +*\*\fun Enables or disables the encoder mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note In this mode the LPTIM instance must be clocked by an internal clock +*\*\ source. Also, the prescaler division ratio must be equal to 1. +*\*\note LPTIM instance must be configured in continuous mode prior enabling +*\*\ the encoder mode. +**/ +void LPTIM_EncoderModeCmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the encoder mode */ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); + } + else + { + /* Disable the encoder mode */ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_ENC); + } +} + +/** +*\*\name LPTIM_NoEncoderModeCmd. +*\*\fun Enables or disables the Non-encoder mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +*\*\note In this mode the LPTIM instance must be clocked by an internal clock +*\*\ source. Also, the prescaler division ratio must be equal to 1. +*\*\note LPTIM instance must be configured in continuous mode prior enabling +*\*\ the encoder mode. +**/ +void LPTIM_NoEncoderModeCmd(LPTIM_Module* LPTIMx, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Non-encoder mode */ + SET_BIT(LPTIMx->CFG, LPTIM_CFG_NENC); + } + else + { + /* Disable the Non-encoder mode */ + CLEAR_BIT(LPTIMx->CFG, LPTIM_CFG_NENC); + } +} + +/** +*\*\name LPTIM_IsEnabledEncoderMode. +*\*\fun Indicates whether the LPTIM operates in encoder mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return 1 or 0 +**/ +uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module* LPTIMx) +{ + uint32_t Temp; + + /* Read the corresponding bit, set 1 to return 1, otherwise, return 0 */ + Temp = (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_ENC) == LPTIM_CFG_ENC) ? 1UL : 0UL)); + + return Temp; +} + +/** +*\*\name LPTIM_IsEnabledNoEncoderMode. +*\*\fun Indicates whether the LPTIM operates in Non-encoder mode. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\return 1 or 0 +**/ +uint32_t LPTIM_IsEnabledNoEncoderMode(LPTIM_Module* LPTIMx) +{ + uint32_t Temp; + + /* Read the corresponding bit, set 1 to return 1, otherwise, return 0 */ + Temp = (((READ_BIT(LPTIMx->CFG, LPTIM_CFG_NENC) == LPTIM_CFG_NENC) ? 1UL : 0UL)); + + return Temp; +} + +/** +*\*\name LPTIM_ClearIntFlag. +*\*\fun Clear the specified LPTIM Interrupt status flags. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param IntFlag (The input parameters must be the following values): +*\*\ - LPTIM_COMP_MATCH_FLAG +*\*\ - LPTIM_AUTO_RELOAD_FLAG +*\*\ - LPTIM_EXT_TRIG_EDGE_EVENT_FLAG +*\*\ - LPTIM_COMP_UPDATE_FLAG +*\*\ - LPTIM_AUTO_RELOAD_UPDATE_FLAG +*\*\ - LPTIM_COUNTER_DIR_UP_FLAG +*\*\ - LPTIM_COUNTER_DIR_DOWN_FLAG +*\*\return none +**/ +void LPTIM_ClearIntFlag(LPTIM_Module* LPTIMx, uint32_t IntFlag) +{ + SET_BIT(LPTIMx->INTCLR, IntFlag); +} + +/** +*\*\name LPTIM_IsActiveIntStatus. +*\*\fun Inform application whether the specified LPTIM interrupt has occurred. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param IntSts (The input parameters must be the following values): +*\*\ - LPTIM_COMP_MATCH_STATUS +*\*\ - LPTIM_AUTO_RELOAD_STATUS +*\*\ - LPTIM_EXT_TRIG_EDGE_EVENT_STATUS +*\*\ - LPTIM_COMP_UPDATE_STATUS +*\*\ - LPTIM_AUTO_RELOAD_UPDATE_STATUS +*\*\ - LPTIM_COUNTER_DIR_UP_STATUS +*\*\ - LPTIM_COUNTER_DIR_DOWN_STATUS +*\*\return 1 or 0 +**/ +uint32_t LPTIM_IsActiveIntStatus(LPTIM_Module* LPTIMx, uint32_t IntSts) +{ + uint32_t Temp; + + /* Read the corresponding bit, set 1 to return 1, otherwise, return 0 */ + Temp = (((READ_BIT(LPTIMx->INTSTS, IntSts) == IntSts) ? 1UL : 0UL)); + + return Temp; +} + +/** +*\*\name LPTIM_ConfigInt. +*\*\fun Enables or disables the specified LPTIM interrupts. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - LPTIM_COMP_MATCH_INT +*\*\ - LPTIM_AUTO_RELOAD_INT +*\*\ - LPTIM_EXT_TRIG_EDGE_EVENT_INT +*\*\ - LPTIM_COMP_UPDATE_INT +*\*\ - LPTIM_AUTO_RELOAD_UPDATE_INT +*\*\ - LPTIM_COUNTER_DIR_UP_INT +*\*\ - LPTIM_COUNTER_DIR_DOWN_INT +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note This function must be called when the LPTIM instance is disabled. +**/ +void LPTIM_ConfigInt(LPTIM_Module* LPTIMx, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + SET_BIT(LPTIMx->INTEN, Interrupt); + } + else + { + CLEAR_BIT(LPTIMx->INTEN, Interrupt); + } +} + +/** +*\*\name LPTIM_IsEnabledInt. +*\*\fun Indicates whether the specified LPTIM interrupts is enabled. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - LPTIM_COMP_MATCH_INT +*\*\ - LPTIM_AUTO_RELOAD_INT +*\*\ - LPTIM_EXT_TRIG_EDGE_EVENT_INT +*\*\ - LPTIM_COMP_UPDATE_INT +*\*\ - LPTIM_AUTO_RELOAD_UPDATE_INT +*\*\ - LPTIM_COUNTER_DIR_UP_INT +*\*\ - LPTIM_COUNTER_DIR_DOWN_INT +*\*\return 1 or 0 +**/ +uint32_t LPTIM_IsEnabledInt(LPTIM_Module* LPTIMx, uint32_t Interrupt) +{ + uint32_t Temp; + + /* Read the corresponding bit, set 1 to return 1, otherwise, return 0 */ + Temp = (((READ_BIT(LPTIMx->INTEN, Interrupt) == Interrupt) ? 1UL : 0UL)); + + return Temp; +} + +/** +*\*\name LPTIM_ConfigInput1. +*\*\fun Select the connection for Input1 of LPTIM. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param ConnectSelect (The input parameters must be the following values): +*\*\ - LPTIM_INPUT1_CONNECT_GPIO +*\*\ - LPTIM_INPUT1_CONNECT_COMP1 +*\*\ - LPTIM_INPUT1_CONNECT_COMP2 +*\*\ - LPTIM_INPUT1_CONNECT_COMP3 +*\*\ - LPTIM_INPUT1_CONNECT_COMP4 +*\*\return none +**/ +void LPTIM_ConfigInput1(LPTIM_Module* LPTIMx, uint32_t ConnectSelect) +{ + MODIFY_REG(LPTIMx->OPT, LPTIM_OPT_OPT1, ConnectSelect); +} + +/** +*\*\name LPTIM_ConfigInput2. +*\*\fun Select the connection for Input2 of LPTIM. +*\*\param LPTIMx (The input parameters must be the following values): +*\*\ - LPTIM1 +*\*\ - LPTIM2 +*\*\ - LPTIM3 +*\*\ - LPTIM4 +*\*\ - LPTIM5 +*\*\param ConnectSelect (The input parameters must be the following values): +*\*\ - LPTIM_INPUT2_CONNECT_GPIO +*\*\ - LPTIM_INPUT2_CONNECT_COMP1 +*\*\ - LPTIM_INPUT2_CONNECT_COMP2 +*\*\ - LPTIM_INPUT2_CONNECT_COMP3 +*\*\ - LPTIM_INPUT2_CONNECT_COMP4 +*\*\return none +**/ +void LPTIM_ConfigInput2(LPTIM_Module* LPTIMx, uint32_t ConnectSelect) +{ + MODIFY_REG(LPTIMx->OPT, LPTIM_OPT_OPT2, ConnectSelect); +} + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lpuart.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lpuart.c new file mode 100644 index 0000000000..9e6e4b84aa --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_lpuart.c @@ -0,0 +1,675 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_lpuart.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_lpuart.h" +#include "n32h76x_78x_rcc.h" + + +/** +*\*\name LPUART_DeInit. +*\*\fun Deinitializes the LPUART peripheral registers to their default reset values +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\return none +*/ + +void LPUART_DeInit(LPUART_Module* LPUARTx) +{ + if (LPUARTx == LPUART1) + { + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPUART1); + } + else + { + if(LPUARTx == LPUART2) + { + RCC_EnableRDPeriphReset1(RCC_RD_PERIPHRST_LPUART2); + } + + } + +} + +/** +*\*\name LPUART_Init. +*\*\fun Initializes the LPUART peripheral according to the specified parameters in the LPUART_InitStruct. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_InitStruct pointer to a LPUART_InitType structure +*\*\ that contains the configuration information for the specified LPUART peripheral . +*\*\return none +*/ + +void LPUART_Init(LPUART_Module* LPUARTx, LPUART_InitType* LPUART_InitStruct) +{ + uint32_t tmpregister = 0x00, clocksrc = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t tmpdivider = 0x00, lastdivider = 0x00, i = 0x00; + uint32_t lpuartdiv = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + const uint8_t ApbPresTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + /*---------------------------- LPUART BRCFG1 & 2 Configuration -----------------------*/ + /* Configure the LPUART Baud Rate -------------------------------------------*/ + + if (LPUARTx == LPUART1) + { + clocksrc = ((uint32_t)(RCC->RDSEL1 & RCC_RDSEL1_LPUART1SEL)); + } + else + { + if(LPUARTx == LPUART2) + { + clocksrc = ((uint32_t)(RCC->RDSEL1 & RCC_RDSEL1_LPUART2SEL)) << 4; + } + } + + if (clocksrc == RCC_LPUARTCLK_SRC_LSE) + { + apbclock = 0x8000; // 32.768kHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_HSI) + { + apbclock = HSI_VALUE; + } + else if (clocksrc == RCC_LPUARTCLK_SRC_MSI) + { + apbclock = MSI_VALUE; // 16MHz + } + else if (clocksrc == RCC_LPUARTCLK_SRC_SYSBUSDIV) + { + lpuartdiv = ((uint32_t)((RCC->RDDIV1 & RCC_RDDIV1_LPUARTDIV) >> 24)); + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + apbclock = (RCC_ClocksStatus.SysBusDivClkFreq) >> (ApbPresTable[lpuartdiv]); + } + else //(clocksrc ==RCC_LPUARTCLK_SRC_HSE) + { + apbclock = HSE_VALUE; + } + + /* Determine the integer part */ + integerdivider = apbclock / (LPUART_InitStruct->BaudRate); + + /* Configure sampling method */ + if(integerdivider <= 10) + { + LPUART_ConfigSamplingMethod(LPUARTx, LPUART_SMPCNT_1B); + } + else + { + LPUART_ConfigSamplingMethod(LPUARTx, LPUART_SMPCNT_3B); + } + + /* Write to LPUART BRCFG1 */ + LPUARTx->BRCFG1 = (uint32_t)integerdivider; + + /* Determine the fractional part */ + fractionaldivider = ((apbclock % (LPUART_InitStruct->BaudRate)) * 10000) / (LPUART_InitStruct->BaudRate); + + tmpregister = 0x00; + tmpdivider = fractionaldivider; + + /* Implement the fractional part in the register */ + for( i = 0; i < 8; i++) + { + lastdivider = tmpdivider; + tmpdivider = lastdivider + fractionaldivider; + + if((tmpdivider / 10000) ^ (lastdivider / 10000)) + { + tmpregister |= (0x01 << i); + } + } + + /* Write to LPUART BRCFG2 */ + LPUARTx->BRCFG2 = (uint32_t)tmpregister; + + // /*---------------------------- LPUART CTRL Configuration -----------------------*/ + tmpregister = LPUARTx->CTRL; + /* Clear RXEN, TXEN, RTST[1:0], PC, RTSEN,CTSEN and PEN bits */ + tmpregister &= CTRL_CLR_MASK; + /* Configure the LPUART Parity, Mode, RtsThrehold and HardwareFlowControl ----------------------- */ + /* Set PC and PEN bits according to Parity value */ + /* Set the RXEN and TXEN bit according to Mode */ + /* Set RTST[1:0] bits according to RtsThrehold */ + /* Set RTSEN and CTSEN bits according to HardwareFlowControl */ + tmpregister |= (uint32_t)LPUART_InitStruct->Parity | LPUART_InitStruct->Mode | LPUART_InitStruct->RtsThreshold | LPUART_InitStruct->HardwareFlowControl; + /* Write to LPUART CTRL */ + LPUARTx->CTRL = (uint32_t)tmpregister; +} + +/** +*\*\name LPUART_StructInit. +*\*\fun Fills each LPUART_InitStruct member with its default value. +*\*\param LPUART_InitStruct pointer to a LPUART_InitType structure +*\*\ which will be initialized. +*\*\return none +*/ + +void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct) +{ + /* LPUART_InitStruct members default value */ + LPUART_InitStruct->BaudRate = 9600; + LPUART_InitStruct->Parity = LPUART_PE_NO; + LPUART_InitStruct->Mode = LPUART_MODE_RX | LPUART_MODE_TX; + LPUART_InitStruct->RtsThreshold = LPUART_RTSTH_FIFOFU; + LPUART_InitStruct->HardwareFlowControl = LPUART_HFCTRL_NONE; +} + +/** +*\*\name LPUART_FlushRxFifo. +*\*\fun Flushes Receiver FIFO. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\return none +*/ + +void LPUART_FlushRxFifo(LPUART_Module* LPUARTx) +{ + /* Clear LPUART Flush Receiver FIFO */ + LPUARTx->CTRL |= LPUART_FLUSHRXF_ENABLE; + + while(LPUART_GetFlagStatus(LPUARTx, LPUART_FLAG_RXFIFO_NE) != RESET) + { + } + + LPUARTx->CTRL &= LPUART_FLUSHRXF_DISABLE; +} + +/** +*\*\name LPUART_FlushTxFifo. +*\*\fun Flushes transmit FIFO. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\return none +*/ +void LPUART_FlushTxFifo(LPUART_Module* LPUARTx) +{ + /* Clear LPUART Flush transmit FIFO */ + LPUARTx->CTRL |= LPUART_FLUSHTXF_ENABLE; + + while(LPUART_GetFlagStatus(LPUARTx, LPUART_FLAG_TXFIFO_NE) != RESET) + { + } + + LPUARTx->CTRL &= LPUART_FLUSHTXF_DISABLE; +} + +/** +*\*\name LPUART_ConfigInt. +*\*\fun Enables or disables the specified LPUART interrupts. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_INT specifies the LPUART interrupt sources to be enabled or disabled. +*\*\ This parameter can be one of the following values: +*\*\ - LPUART_INT_TXFIFO_NE TX FIFO Non-Empty Interrupt +*\*\ - LPUART_INT_TXFIFO_HF TX FIFO Half Full Interrupt +*\*\ - LPUART_INT_TXFIFO_QF TX FIFO 1/4 Interrupt +*\*\ - LPUART_INT_TXFIFO_FU TX FIFO Full Interrupt Enable +*\*\ - LPUART_INT_TXFIFO_OV TX FIFO Overflow Interrupt +*\*\ - LPUART_INT_WUF Wake-Up Interrupt +*\*\ - LPUART_INT_RXFIFO_NE RX FIFO Non-Empty Interrupt +*\*\ - LPUART_INT_RXFIFO_HF RX FIFO Half Full Interrupt +*\*\ - LPUART_INT_RXFIFO_FU RX FIFO Full Interrupt Enable +*\*\ - LPUART_INT_RXFIFO_OV RX FIFO Overflow Interrupt +*\*\ - LPUART_INT_TXC TX Complete Interrupt +*\*\ - LPUART_INT_PE Parity Check Error Interrupt +*\*\ - LPUART_INT_IDLEF IDLE_FRAMEIE Interrupt +*\*\ - LPUART_INT_FE FRAME_ERROR Interrupt +*\*\ - LPUART_INT_TXFIFO_EM TX FIFO Empty Interrupt +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*/ + +void LPUART_ConfigInt(LPUART_Module* LPUARTx, uint32_t LPUART_INT, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + LPUARTx->INTEN |= LPUART_INT; + } + else + { + LPUARTx->INTEN &= (~LPUART_INT); + } +} + +/** +*\*\name LPUART_EnableDMA. +*\*\fun Enables or disables the LPUART's DMA interface. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_DMAReq specifies the DMA request. +*\*\ This parameter can be one of the following values: +*\*\ - LPUART_DMAREQ_TX LPUART DMA transmit request +*\*\ - LPUART_DMAREQ_RX LPUART DMA receive request +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*/ + +void LPUART_EnableDMA(LPUART_Module* LPUARTx, uint32_t LPUART_DMAReq, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA transfer by setting the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUARTx->CTRL |= LPUART_DMAReq; + } + else + { + /* Disable the DMA transfer by clearing the DMA_RXEN and/or DMA_TXEN bits in the LPUART_CTRL register */ + LPUARTx->CTRL &= (uint32_t)(~LPUART_DMAReq); + } +} + +/** +*\*\name LPUART_ConfigWakeUpMethod. +*\*\fun Selects the LPUART WakeUp method. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_WakeUpMethod specifies the LPUART wakeup method. +*\*\ This parameter can be one of the following values: +*\*\ - LPUART_WUSTP_STARTBIT WakeUp by Start Bit Detection +*\*\ - LPUART_WUSTP_RXNE WakeUp by RXNE Detection +*\*\ - LPUART_WUSTP_BYTE WakeUp by A Configurable Received Byte +*\*\ - LPUART_WUSTP_FRAME_2 WakeUp by A Programmed 2-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_3 WakeUp by A Programmed 3-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_4 WakeUp by A Programmed 4-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_5 WakeUp by A Programmed 5-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_6 WakeUp by A Programmed 6-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_7 WakeUp by A Programmed 7-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_8 WakeUp by A Programmed 8-Byte Frame +*\*\ - LPUART_WUSTP_FRAME_MANY WakeUp by A Programmed MANY-Byte Frame +*\*\return none +*/ + +void LPUART_ConfigWakeUpMethod(LPUART_Module* LPUARTx, uint32_t LPUART_WakeUpMethod) +{ + LPUARTx->CTRL &= CTRL_WUSTP_MASK; + LPUARTx->CTRL |= LPUART_WakeUpMethod; +} + +/** +*\*\name LPUART_EnableWakeUpStop. +*\*\fun Enables or disables LPUART Wakeup in STOP2 mode. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*/ +void LPUART_EnableWakeUpStop(LPUART_Module* LPUARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable Wakeup in STOP2 mode by setting the WUSTP bit in the CTRL register */ + LPUARTx->CTRL |= LPUART_WUSTP_ON; + } + else + { + /* Disable Wakeup in STOP2 mode by clearing the WUSTP bit in the CTRL register */ + LPUARTx->CTRL &= (~LPUART_WUSTP_ON); + } +} + +/** +*\*\name LPUART_ConfigSamplingMethod. +*\*\fun Selects the LPUART Sampling method. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_SamplingMethod specifies the LPAURT sampling method. +*\*\ This parameter can be one of the following values: +*\*\ - LPUART_SMPCNT_3B 3 Sample bit +*\*\ - LPUART_SMPCNT_1B 1 Sample bit +*\*\return none +*/ +void LPUART_ConfigSamplingMethod(LPUART_Module* LPUARTx, uint32_t LPUART_SamplingMethod) +{ + + LPUARTx->CTRL &= CTRL_SMPCNT_MASK; + LPUARTx->CTRL |= LPUART_SamplingMethod; +} + +/** +*\*\name LPUART_EnableLoopBack. +*\*\fun Enables or disables LPUART Loop Back Self-Test. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*/ +void LPUART_EnableLoopBack(LPUART_Module* LPUARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable LPUART Loop Back Self-Test by setting the LOOKBACK bit in the CTRL register */ + LPUARTx->CTRL |= LPUART_LOOPBACK_ENABLE; + } + else + { + /* Disable LPUART Loop Back Self-Test by clearing the LOOKBACK bit in the CTRL register */ + LPUARTx->CTRL &= LPUART_LOOPBACK_DISABLE; + } +} + +/** +*\*\name LPUART_SendData. +*\*\fun Transmits single data through the LPUART peripheral. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param Data the data to transmit. +*\*\return none +*/ + +void LPUART_SendData(LPUART_Module* LPUARTx, uint8_t Data) +{ + /* Transmit Data */ + LPUARTx->TXDAT = (Data & (uint8_t)0xFF); +} + +/** +*\*\name LPUART_ReceiveData. +*\*\fun Returns the most recent received data by the LPUART peripheral. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\return The received data. +*/ + +uint8_t LPUART_ReceiveData(LPUART_Module* LPUARTx) +{ + /* Receive Data */ + return (uint8_t)(LPUARTx->RXDAT & (uint8_t)0xFF); +} + +/** +*\*\name LPUART_ConfigWakeUpData. +*\*\fun SConfigures LPUART detected byte or frame match for wakeup CPU from STOPS mode. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_WakeUpData specifies the LPUART detected byte or frame match for wakeup CPU from STOP2 mode. +*\*\return none +*/ + +void LPUART_ConfigWakeUpData(LPUART_Module* LPUARTx, uint32_t LPUART_WakeUpData1, uint32_t LPUART_WakeUpData2) +{ + LPUARTx->WUDAT1 = LPUART_WakeUpData1; + LPUARTx->WUDAT2 = LPUART_WakeUpData2; +} + +/** +*\*\name LPUART_GetFlagStatus. +*\*\fun Checks whether the specified LPUART flag is set or not. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_FLAG specifies the flag to check. +*\*\ This parameter can be one of the following values: +*\*\ - LPUART_FLAG_PEF Parity Check Error Flag. +*\*\ - LPUART_FLAG_TXC TX Complete Flag. +*\*\ - LPUART_FLAG_RXFIFO_OV RX FIFO Overflow Flag. +*\*\ - LPUART_FLAG_RXFIFO_FU RX FIFO Full Flag. +*\*\ - LPUART_FLAG_RXFIFO_HF RX FIFO Half Full Flag. +*\*\ - LPUART_FLAG_RXFIFO_NE RX FIFO Non-Empty Flag. +*\*\ - LPUART_FLAG_CTS CTS Change(Hardware Flow Control) Flag. +*\*\ - LPUART_FLAG_WUF from STOP2 mode Flag. +*\*\ - LPUART_FLAG_NEF Noise Detection Flag. +*\*\ - LPUART_FLAG_TXFIFO_OV TX FIFO Overflow Flag. +*\*\ - LPUART_FLAG_TXFIFO_FU TX FIFO Full Flag. +*\*\ - LPUART_FLAG_TXFIFO_QF TX FIFO 1/4 Full Flag. +*\*\ - LPUART_FLAG_TXFIFO_HF TX FIFO Half Full Flag. +*\*\ - LPUART_FLAG_TXFIFO_NE TX FIFO Non-Empty Flag. +*\*\ - LPUART_FLAG_IDLEF IDLE frame detected. +*\*\ - LPUART_FLAG_FRAME_ER frame error detected. +*\*\ - LPUART_FLAG_TXFIFO_EM TX FIFO Empty Flag. +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +*/ + +FlagStatus LPUART_GetFlagStatus(LPUART_Module* LPUARTx, uint32_t LPUART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if ((LPUARTx->STS & LPUART_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name LPUART_ClrFlag. +*\*\fun Clears the LPUART's pending flags. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_FLAG specifies the flag to clear. +*\*\ This parameter can be one of the following values: +*\*\ - LPUART_FLAG_PEF Parity Check Error Flag. +*\*\ - LPUART_FLAG_TXC TX Complete Flag. +*\*\ - LPUART_FLAG_RXFIFO_OV RX FIFO Overflow Flag. +*\*\ - LPUART_FLAG_RXFIFO_FU RX FIFO Full Flag. +*\*\ - LPUART_FLAG_RXFIFO_HF RX FIFO Half Full Flag. +*\*\ - LPUART_FLAG_RXFIFO_NE RX FIFO Non-Empty Flag. +*\*\ - LPUART_FLAG_WUF from STOP2 mode Flag. +*\*\ - LPUART_FLAG_NEF Noise Detection Flag. +*\*\ - LPUART_FLAG_TXFIFO_OV TX FIFO Overflow Flag. +*\*\ - LPUART_FLAG_TXFIFO_FU TX FIFO Full Flag. +*\*\ - LPUART_FLAG_TXFIFO_QF TX FIFO 1/4 Full Flag. +*\*\ - LPUART_FLAG_TXFIFO_HF TX FIFO Half Full Flag. +*\*\ - LPUART_FLAG_TXFIFO_NE TX FIFO Non-Empty Flag. +*\*\ - LPUART_FLAG_IDLEF IDLE frame detected. +*\*\ - LPUART_FLAG_FRAME_ER frame error detected. +*\*\return none +*/ +void LPUART_ClrFlag(LPUART_Module* LPUARTx, uint32_t LPUART_FLAG) +{ + LPUARTx->STS = (uint32_t)LPUART_FLAG; +} + +/** +*\*\name LPUART_GetIntStatus. +*\*\fun Checks whether the specified LPUART interrupt has set or not. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_INT (The input parameters must be the following values): +*\*\ - LPUART_INT_TXFIFO_NE TX FIFO Non-Empty Interrupt +*\*\ - LPUART_INT_TXFIFO_HF TX FIFO Half Full Interrupt +*\*\ - LPUART_INT_TXFIFO_QF TX FIFO 1/4 Interrupt +*\*\ - LPUART_INT_TXFIFO_FU TX FIFO Full Interrupt Enable +*\*\ - LPUART_INT_TXFIFO_OV TX FIFO Overflow Interrupt +*\*\ - LPUART_INT_WUF Wake-Up Interrupt +*\*\ - LPUART_INT_RXFIFO_NE RX FIFO Non-Empty Interrupt +*\*\ - LPUART_INT_RXFIFO_HF RX FIFO Half Full Interrupt +*\*\ - LPUART_INT_RXFIFO_FU RX FIFO Full Interrupt Enable +*\*\ - LPUART_INT_RXFIFO_OV RX FIFO Overflow Interrupt +*\*\ - LPUART_INT_TXC TX Complete Interrupt +*\*\ - LPUART_INT_PE Parity Check Error Interrupt +*\*\ - LPUART_INT_IDLEF IDLE_FRAMEIE Interrupt +*\*\ - LPUART_INT_FE FRAME_ERROR Interrupt +*\*\ - LPUART_INT_TXFIFO_EM TX FIFO Empty Interrupt +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +*/ + +INTStatus LPUART_GetIntStatus(LPUART_Module* LPUARTx, uint32_t LPUART_INT) +{ + uint32_t itmask = 0x00; + INTStatus bitstatus = RESET; + + /* Get the interrupt position */ + itmask = LPUART_INT & LPUART_INT_MASK; + itmask &= LPUARTx->INTEN; + + if (itmask != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name LPUART_ClrIntPendingBit. +*\*\fun Clears the LPUART's interrupt pending bits. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param LPUART_INT (The input parameters must be the following values): +*\*\ - LPUART_INT_TXFIFO_NE TX FIFO Non-Empty Interrupt +*\*\ - LPUART_INT_TXFIFO_HF TX FIFO Half Full Interrupt +*\*\ - LPUART_INT_TXFIFO_QF TX FIFO 1/4 Interrupt +*\*\ - LPUART_INT_TXFIFO_FU TX FIFO Full Interrupt Enable +*\*\ - LPUART_INT_TXFIFO_OV TX FIFO Overflow Interrupt +*\*\ - LPUART_INT_WUF Wake-Up Interrupt +*\*\ - LPUART_INT_RXFIFO_NE RX FIFO Non-Empty Interrupt +*\*\ - LPUART_INT_RXFIFO_HF RX FIFO Half Full Interrupt +*\*\ - LPUART_INT_RXFIFO_FU RX FIFO Full Interrupt Enable +*\*\ - LPUART_INT_RXFIFO_OV RX FIFO Overflow Interrupt +*\*\ - LPUART_INT_TXC TX Complete Interrupt +*\*\ - LPUART_INT_PE Parity Check Error Interrupt +*\*\ - LPUART_INT_IDLEF IDLE_FRAMEIE Interrupt +*\*\ - LPUART_INT_FE FRAME_ERROR Interrupt +*\*\ - LPUART_INT_TXFIFO_EM TX FIFO Empty Interrupt +*\*\return none +*/ + +void LPUART_ClrIntPendingBit(LPUART_Module* LPUARTx, uint32_t LPUART_INT) +{ + uint32_t itmask = 0x00; + + itmask = LPUART_INT & LPUART_INT_MASK; + + if(LPUART_INT == LPUART_INT_WUF) + { + itmask = (itmask << 0x01); + } + else if (LPUART_INT > LPUART_INT_WUF) + { + itmask = (itmask << 0x02); + } + + LPUARTx->STS = itmask; +} + +/** +*\*\name LPUART_IdleFrameSet. +*\*\fun Idle frame controllable enable or disable. +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*/ +void LPUART_IdleFrameSet(LPUART_Module* LPUARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + LPUARTx->CTRL |= LPUART_IDLEF_ENABLE; + } + else + { + LPUARTx->CTRL &= LPUART_IDLEF_DISABLE; + } +} + +/** +*\*\name LPUART_ConfigRXByte. +*\*\fun A configuration byte can be configured to receive how many bytes of data to wake +*\*\param LPUARTx (The input parameters must be the following values): +*\*\ - LPUART1 +*\*\ - LPUART2 +*\*\param Cmd:LPUART_RXNUMWU +*\*\return none +*/ + +void LPUART_ConfigRXByte(LPUART_Module* LPUARTx, uint8_t LPUART_RXNUMWU) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)(LPUART_RXNUMWU & 0x1F)) << 19; + LPUARTx->CTRL |= tmp; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mdma.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mdma.c new file mode 100644 index 0000000000..287ae865e5 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mdma.c @@ -0,0 +1,1289 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_mdma.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_mdma.h" + + +/** +*\*\name MDMA_ControllerCmd. +*\*\fun Enable or disable MDMA Controller peripheral. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_ControllerCmd(MDMA_Module *const MDMAy, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MDMA Controller */ + SET_BIT(MDMAy->CFG, MDMA_CFG_EN); + } + else + { + /* Disable the MDMA Controller */ + CLEAR_BIT(MDMAy->CFG, MDMA_CFG_EN); + } +} + +/** +*\*\name MDMA_ControllerIsEnabled. +*\*\fun Check MDMA Controller peripheral is enabled. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\return true or false +**/ +bool MDMA_ControllerIsEnabled(MDMA_Module *const MDMAy) +{ + bool ret; + ret = READ_BIT(MDMAy->CFG, MDMA_CFG_EN) ? true : false; + return ret; +} + +/** +*\*\name MDMA_ControllerSoftReset. +*\*\fun Software Reset MDMA Controller. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\return none +**/ +void MDMA_ControllerSoftReset(MDMA_Module *const MDMAy) +{ + /* Sets MDMA reset request bit */ + SET_BIT(MDMAy->SWRST, MDMA_SWRST_RSTREQ); + + /* Wait until reset request bit is 0 */ + while ((READ_BIT(MDMAy->SWRST, MDMA_SWRST_RSTREQ))) + { + /* Wait for reset to complete */ + } +} + +/** +*\*\name MDMA_ChannelCmd. +*\*\fun Enable or disable a MDMA channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_ChannelCmd(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MDMA channel */ + WRITE_REG(MDMAy->CHEN, (MDMA_CH_ENABLE << ChNum)); + } + else + { + /* Disable the MDMA channel */ + WRITE_REG(MDMAy->CHEN, (MDMA_CH_DISABLE << ChNum)); + + while (READ_BIT((uint16_t)MDMAy->CHEN, ((uint16_t)0x1U << ChNum)) != 0U) + { + /* Wait until channel is disabled */ + } + } +} + +/** +*\*\name MDMA_ChannelIsEnabled. +*\*\fun Check whether a MDMA channel enabled. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return true or false +**/ +bool MDMA_ChannelIsEnabled(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + bool ret; + ret = READ_BIT((uint16_t)MDMAy->CHEN, ((uint16_t)0x1U << ChNum)) ? true : false; + return ret; +} + +/** +*\*\name MDMA_ChannelInit. +*\*\fun Initialize a MDMA channel with provided channel configuration +*\*\ The function sets up the following channel configuration parameters for +*\*\ a MDMA channel specified paramters like: +*\*\ Source and Destination addresses ( and linked list address if required) +*\*\ Source and Destination handshake method as software/hardware selection +*\*\ and transfer flow and transfer type +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param MDMA_ChInitParam : +*\*\ - Pointer to the MDMA_ChInitType structure which will be initialized. +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return One of MDMA_ChStatusType. +**/ +MDMA_ChStatusType MDMA_ChannelInit(MDMA_Module *const MDMAy, MDMA_ChInitType *const MDMA_ChInitParam, MDMA_ChNumType ChNum) +{ + uint32_t TempValue; + MDMA_ChStatusType RetStatus; + + /* Check whether the specified MDMA controller is enabled */ + if (MDMA_ControllerIsEnabled(MDMAy) == ENABLE) + { + /* Checks whether the specified MDMA channel is disabled */ + if (MDMA_ChannelIsEnabled(MDMAy, ChNum) == DISABLE) + { + /* Sets channel n source multi-block transfer type */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_SMBTT, ((uint64_t)MDMA_ChInitParam->SrcMultBlkTfrType << 0x00U)); + /* Sets channel n destination multi-block transfer type */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_DMBTT, ((uint64_t)MDMA_ChInitParam->DstMultBlkTfrType << 0x02U)); + + /* Sets channel n transfer type and flow control */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_TTFC, ((uint64_t)MDMA_ChInitParam->TfrTypeFlowCtrl << 0x20U)); + /* Sets channel n priority */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_CHPRIOR, ((uint64_t)MDMA_ChInitParam->ChannelPriority << 0x2FU)); + + /* Configure source handshaking hardware mode */ + if (MDMA_ChInitParam->SrcHandshaking == MDMA_CH_SRC_HANDSHAKING_HARDWARE) + { + TempValue = ((uint32_t)MDMA_ChInitParam->SrcHsInterface & 0xFU); + /* Select hardware handshake I/F [0-15] */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_SRCPER, ((uint64_t)TempValue << 0x4U)); + + /* Sets source hardware handshaking interface polarity */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_SRCHHIPOL, ((uint64_t)MDMA_ChInitParam->SrcHsInterfacePol << 0x25U)); + + /* Enable hardware handshake to source peripheral */ + CLEAR_BIT(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_HSSELSRC); + } + + /* Configure destination handshaking hardware mode */ + if (MDMA_ChInitParam->DstHandshaking == MDMA_CH_DST_HANDSHAKING_HARDWARE) + { + TempValue = ((uint32_t)MDMA_ChInitParam->DstHsInterface & 0xFU); + /* Select hardware handshake I/F [0-15] */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_DSTPER, ((uint64_t)TempValue << 0xBU)); + + /* Sets destination hardware handshaking interface polarity */ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_DSTHHIPOL, ((uint64_t)MDMA_ChInitParam->DstHsInterfacePol << 0x26U)); + + /* Enable hardware handshake to destionation peripheral */ + CLEAR_BIT(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_HSSELDST); + } + + /* Sets channel n source address register */ + WRITE_REG(MDMAy->CH[ChNum].SA, MDMA_ChInitParam->SrcAddr); + /* Sets channel n destination address register */ + WRITE_REG(MDMAy->CH[ChNum].DA, MDMA_ChInitParam->DstAddr); + /* Sets channel n linked list pointer register */ + WRITE_REG(MDMAy->CH[ChNum].LLP, (uint32_t)MDMA_ChInitParam->pLinkListItem); + /* Sets channel n block transfer size register */ + WRITE_REG(MDMAy->CH[ChNum].BTS, MDMA_ChInitParam->BlkSize); + /* Sets channel n control register */ + WRITE_REG(MDMAy->CH[ChNum].CTRL, MDMA_ChInitParam->ChCtrl); + + /* Clear the MDMA all common register interrupt status */ + WRITE_REG(MDMAy->CRINTCLR, MDMA_COMMON_INT_CLEAR); + /* Clear the all interrupt status for the specified MDMA channel */ + WRITE_REG(MDMAy->CH[ChNum].INTCLR, MDMA_CH_INT_CLEAR); + + /* Disable common register interrupt status */ + CLEAR_BIT(MDMAy->CRINTSTSEN, MDMA_COMMON_INT_STS_MASK); + /* Disable common register interrupt signal */ + CLEAR_BIT(MDMAy->CRINTSGLEN, MDMA_COMMON_INT_SGL_MASK); + /* Disable Channel n interrupt status */ + CLEAR_BIT(MDMAy->CH[ChNum].INTSTSEN, MDMA_CH_INT_STS_MASK); + /* Disable Channel n interrupt signal */ + CLEAR_BIT(MDMAy->CH[ChNum].INTSGLEN, MDMA_CH_INT_SGL_MASK); + + RetStatus = MDMA_CH_STS_OK; + } + else + { + RetStatus = MDMA_CH_STS_BUSY; + } + } + else + { + RetStatus = MDMA_CH_STS_ERROR; + } + + return RetStatus; +} + +/** +*\*\name MDMA_ChannelStructInit. +*\*\fun Initializes the structure parameter of type MDMA_ChInitType used to +*\*\ initialize MDMA. This function is usually called before initializing +*\*\ a parameter of type MDMA_ChInitType. +*\*\param MDMA_ChInitParam : +*\*\ - Pointer to the MDMA_ChInitType structure which will be initialized. +*\*\return none +**/ +void MDMA_ChannelStructInit(MDMA_ChInitType *const MDMA_ChInitParam) +{ + MDMA_ChInitParam->SrcMasterSel = MDMA_CH_MASTER_1; + MDMA_ChInitParam->DstMasterSel = MDMA_CH_MASTER_1; + MDMA_ChInitParam->SrcAddrInc = MDMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + MDMA_ChInitParam->DstAddrInc = MDMA_CH_ADDRESS_COUNT_MODE_INCREMENT; + MDMA_ChInitParam->SrcTfrWidth = MDMA_CH_TRANSFER_WIDTH_32; + MDMA_ChInitParam->DstTfrWidth = MDMA_CH_TRANSFER_WIDTH_32; + MDMA_ChInitParam->SrcBurstTranLen = MDMA_CH_BURST_TRAN_LEN_1; + MDMA_ChInitParam->DstBurstTranLen = MDMA_CH_BURST_TRAN_LEN_1; + MDMA_ChInitParam->NonPosLastWriteEn = false; + MDMA_ChInitParam->SrcBurstLenEn = false; + MDMA_ChInitParam->SrcBurstLen = 0x0U; + MDMA_ChInitParam->DstBurstLenEn = false; + MDMA_ChInitParam->DstBurstLen = 0x0U; + MDMA_ChInitParam->IocBlkTfr = false; + MDMA_ChInitParam->SdwLlILast = false; + MDMA_ChInitParam->SdwLlIValid = false; + + MDMA_ChInitParam->SrcAddr = 0x0U; + MDMA_ChInitParam->DstAddr = 0x0U; + MDMA_ChInitParam->pLinkListItem = NULL; + MDMA_ChInitParam->BlkSize = 0x0U; + + MDMA_ChInitParam->ChannelPriority = MDMA_CH_PRIORITY_15; + MDMA_ChInitParam->SrcHandshaking = MDMA_CH_SRC_HANDSHAKING_SOFTWARE; + MDMA_ChInitParam->SrcHsInterface = MDMA_CH_HARDWARE_HANDSHAKING_IF_0; + MDMA_ChInitParam->SrcHsInterfacePol = MDMA_CH_HARDWARE_HANDSHAKING_IF_POL_H; + MDMA_ChInitParam->DstHandshaking = MDMA_CH_DST_HANDSHAKING_SOFTWARE; + MDMA_ChInitParam->DstHsInterface = MDMA_CH_HARDWARE_HANDSHAKING_IF_0; + MDMA_ChInitParam->DstHsInterfacePol = MDMA_CH_HARDWARE_HANDSHAKING_IF_POL_H; + + MDMA_ChInitParam->TfrTypeFlowCtrl = MDMA_CH_TRANSFER_FLOW_P2P_MDMA; + MDMA_ChInitParam->SrcMultBlkTfrType = MDMA_CH_MULTI_BLOCK_CONTIGUOUS; + MDMA_ChInitParam->DstMultBlkTfrType = MDMA_CH_MULTI_BLOCK_CONTIGUOUS; +} + +/** +*\*\name MDMA_ChannelSuspend. +*\*\fun Suspend a MDMA channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return none +**/ +void MDMA_ChannelSuspend(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + /* Suspend the MDMA channel */ + WRITE_REG(MDMAy->CHSUSP, (MDMA_CH_SUSPEND << ChNum)); +} + +/** +*\*\name MDMA_ChannelIsSuspended. +*\*\fun Check whether a MDMA channel suspended. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return true or false +**/ +bool MDMA_ChannelIsSuspended(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + bool ret; + ret = READ_BIT((uint16_t)MDMAy->CHSUSP, ((uint16_t)0x1U << ChNum)) ? true : false; + return ret; +} + +/** +*\*\name MDMA_ChannelResume. +*\*\fun Resume a MDMA channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return none +**/ +void MDMA_ChannelResume(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + /* Resume the MDMA channel */ + WRITE_REG(MDMAy->CHSUSP, (MDMA_CH_RESUME << ChNum)); +} + +/** +*\*\name MDMA_GlobalInterruptCmd. +*\*\fun Enable or disable MDMA globally interrupt. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_GlobalInterruptCmd(MDMA_Module *const MDMAy, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MDMA global interrupt */ + SET_BIT(MDMAy->CFG, MDMA_CFG_GLBINTEN); + } + else + { + /* Disable the MDMA global interrupt */ + CLEAR_BIT(MDMAy->CFG, MDMA_CFG_GLBINTEN); + } +} + +/** +*\*\name MDMA_CommonInterruptStatusCmd. +*\*\fun Enable or disable MDMA common register interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param Interrupt (The input parameter must be one or more of the following values (logical OR)): +*\*\ - MDMA_COMMON_INT_SIURDEI +*\*\ - MDMA_COMMON_INT_SICRWOHEI +*\*\ - MDMA_COMMON_INT_SICRR2WOEI +*\*\ - MDMA_COMMON_INT_SICRW2ROEI +*\*\ - MDMA_COMMON_INT_SICRDEI +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_CommonInterruptStatusCmd(MDMA_Module *const MDMAy, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MDMA corresponding common register interrupt status */ + SET_BIT(MDMAy->CRINTSTSEN, Interrupt); + } + else + { + /* Disable the MDMA corresponding common register interrupt status */ + CLEAR_BIT(MDMAy->CRINTSTSEN, Interrupt); + } +} + +/** +*\*\name MDMA_CommonInterruptSignalCmd. +*\*\fun Enable or disable MDMA common register interrupt signal. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param Interrupt (The input parameter must be one or more of the following values (logical OR)): +*\*\ - MDMA_COMMON_INT_SIURDEI +*\*\ - MDMA_COMMON_INT_SICRWOHEI +*\*\ - MDMA_COMMON_INT_SICRR2WOEI +*\*\ - MDMA_COMMON_INT_SICRW2ROEI +*\*\ - MDMA_COMMON_INT_SICRDEI +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_CommonInterruptSignalCmd(MDMA_Module *const MDMAy, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the MDMA corresponding common register interrupt signal */ + SET_BIT(MDMAy->CRINTSGLEN, Interrupt); + } + else + { + /* Disable the MDMA corresponding common register interrupt signal */ + CLEAR_BIT(MDMAy->CRINTSGLEN, Interrupt); + } +} + +/** +*\*\name MDMA_ClearCommonInterruptStatus. +*\*\fun Clear MDMA common register interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param Interrupt (The input parameter must be one or more of the following values (logical OR)): +*\*\ - MDMA_COMMON_INT_SIURDEI +*\*\ - MDMA_COMMON_INT_SICRWOHEI +*\*\ - MDMA_COMMON_INT_SICRR2WOEI +*\*\ - MDMA_COMMON_INT_SICRW2ROEI +*\*\ - MDMA_COMMON_INT_SICRDEI +*\*\return none +**/ +void MDMA_ClearCommonInterruptStatus(MDMA_Module *const MDMAy, uint32_t Interrupt) +{ + /* Clear the MDMA corresponding common register interrupt status */ + WRITE_REG(MDMAy->CRINTCLR, Interrupt); +} + +/** +*\*\name MDMA_GetCombinedStatus. +*\*\fun Get the MDMA combined interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\return MDMA_INTSTS register value +**/ +uint64_t MDMA_GetCombinedStatus(MDMA_Module *const MDMAy) +{ + return (uint64_t)(READ_REG(MDMAy->INTSTS) & 0x10000FFFFUL); +} + +/** +*\*\name MDMA_GetCommonInterruptStatus. +*\*\fun Get MDMA common register interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - MDMA_COMMON_INT_SIURDEI +*\*\ - MDMA_COMMON_INT_SICRWOHEI +*\*\ - MDMA_COMMON_INT_SICRR2WOEI +*\*\ - MDMA_COMMON_INT_SICRW2ROEI +*\*\ - MDMA_COMMON_INT_SICRDEI +*\*\return SET or RESET +**/ +INTStatus MDMA_GetCommonInterruptStatus(MDMA_Module *const MDMAy, uint32_t Interrupt) +{ + INTStatus RetStatus = RESET; + + /* Read the status of the corresponding interrupt */ + if (READ_BIT(MDMAy->CRINTSTS, Interrupt) != (uint32_t)RESET) + { + /* This status of the interrupt is SET */ + RetStatus = SET; + } + else + { + /* This status of the interrupt is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name MDMA_ChannelInterruptStatusCmd. +*\*\fun Enable or disable a MDMA channel interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Interrupt (The input parameter must be one or more of the following values (logical OR)): +*\*\ - MDMA_CH_INT_CH_ABORTED +*\*\ - MDMA_CH_INT_CH_DISABLED +*\*\ - MDMA_CH_INT_CH_SUSPENDED +*\*\ - MDMA_CH_INT_CH_SRC_SUSPENDED +*\*\ - MDMA_CH_INT_CH_LOCK_CLEARED +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_HOLD_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_CH_EN_ERR +*\*\ - MDMA_CH_INT_SLV_IF_R2WO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W2RO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_DEC_ERR +*\*\ - MDMA_CH_INT_SLV_IF_MULTI_BLK_TYPE_ERR +*\*\ - MDMA_CH_INT_SDW_REG_LLI_INVALID_ERR +*\*\ - MDMA_CH_INT_LLI_W_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_R_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_W_DEC_ERR +*\*\ - MDMA_CH_INT_LLI_R_DEC_ERR +*\*\ - MDMA_CH_INT_DST_SLV_ERR +*\*\ - MDMA_CH_INT_SRC_SLV_ERR +*\*\ - MDMA_CH_INT_DST_DEC_ERR +*\*\ - MDMA_CH_INT_SRC_DEC_ERR +*\*\ - MDMA_CH_INT_DST_TRAN_COMPLE +*\*\ - MDMA_CH_INT_SRC_TRAN_COMPLE +*\*\ - MDMA_CH_INT_DMA_TRF_DONE +*\*\ - MDMA_CH_INT_BLK_TRF_DONE +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_ChannelInterruptStatusCmd(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the corresponding interrupt status for the specified MDMA channel */ + SET_BIT(MDMAy->CH[ChNum].INTSTSEN, Interrupt); + } + else + { + /* Disable the corresponding interrupt status for the specified MDMA channel */ + CLEAR_BIT(MDMAy->CH[ChNum].INTSTSEN, Interrupt); + } +} + +/** +*\*\name MDMA_ChannelInterruptSignalCmd. +*\*\fun Enable or disable a MDMA channel interrupt signal. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Interrupt (The input parameter must be one or more of the following values (logical OR)): +*\*\ - MDMA_CH_INT_CH_ABORTED +*\*\ - MDMA_CH_INT_CH_DISABLED +*\*\ - MDMA_CH_INT_CH_SUSPENDED +*\*\ - MDMA_CH_INT_CH_SRC_SUSPENDED +*\*\ - MDMA_CH_INT_CH_LOCK_CLEARED +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_HOLD_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_CH_EN_ERR +*\*\ - MDMA_CH_INT_SLV_IF_R2WO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W2RO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_DEC_ERR +*\*\ - MDMA_CH_INT_SLV_IF_MULTI_BLK_TYPE_ERR +*\*\ - MDMA_CH_INT_SDW_REG_LLI_INVALID_ERR +*\*\ - MDMA_CH_INT_LLI_W_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_R_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_W_DEC_ERR +*\*\ - MDMA_CH_INT_LLI_R_DEC_ERR +*\*\ - MDMA_CH_INT_DST_SLV_ERR +*\*\ - MDMA_CH_INT_SRC_SLV_ERR +*\*\ - MDMA_CH_INT_DST_DEC_ERR +*\*\ - MDMA_CH_INT_SRC_DEC_ERR +*\*\ - MDMA_CH_INT_DST_TRAN_COMPLE +*\*\ - MDMA_CH_INT_SRC_TRAN_COMPLE +*\*\ - MDMA_CH_INT_DMA_TRF_DONE +*\*\ - MDMA_CH_INT_BLK_TRF_DONE +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void MDMA_ChannelInterruptSignalCmd(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt, FunctionalStatus Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the corresponding interrupt signal for the specified MDMA channel */ + SET_BIT(MDMAy->CH[ChNum].INTSGLEN, Interrupt); + } + else + { + /* Disable the corresponding interrupt signal for the specified MDMA channel */ + CLEAR_BIT(MDMAy->CH[ChNum].INTSGLEN, Interrupt); + } +} + +/** +*\*\name MDMA_ClearChannelInterruptStatus. +*\*\fun Clear MDMA Channel interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Interrupt (The input parameter must be one or more of the following values (logical OR)): +*\*\ - MDMA_CH_INT_CH_ABORTED +*\*\ - MDMA_CH_INT_CH_DISABLED +*\*\ - MDMA_CH_INT_CH_SUSPENDED +*\*\ - MDMA_CH_INT_CH_SRC_SUSPENDED +*\*\ - MDMA_CH_INT_CH_LOCK_CLEARED +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_HOLD_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_CH_EN_ERR +*\*\ - MDMA_CH_INT_SLV_IF_R2WO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W2RO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_DEC_ERR +*\*\ - MDMA_CH_INT_SLV_IF_MULTI_BLK_TYPE_ERR +*\*\ - MDMA_CH_INT_SDW_REG_LLI_INVALID_ERR +*\*\ - MDMA_CH_INT_LLI_W_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_R_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_W_DEC_ERR +*\*\ - MDMA_CH_INT_LLI_R_DEC_ERR +*\*\ - MDMA_CH_INT_DST_SLV_ERR +*\*\ - MDMA_CH_INT_SRC_SLV_ERR +*\*\ - MDMA_CH_INT_DST_DEC_ERR +*\*\ - MDMA_CH_INT_SRC_DEC_ERR +*\*\ - MDMA_CH_INT_DST_TRAN_COMPLE +*\*\ - MDMA_CH_INT_SRC_TRAN_COMPLE +*\*\ - MDMA_CH_INT_DMA_TRF_DONE +*\*\ - MDMA_CH_INT_BLK_TRF_DONE +*\*\return none +**/ +void MDMA_ClearChannelInterruptStatus(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt) +{ + /* Clear the corresponding interrupt for the specified MDMA channel */ + WRITE_REG(MDMAy->CH[ChNum].INTCLR, Interrupt); +} + +/** +*\*\name MDMA_GetChannelInterruptStatus. +*\*\fun Get MDMA Channel interrupt status. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Interrupt (The input parameters must be the following values): +*\*\ - MDMA_CH_INT_CH_ABORTED +*\*\ - MDMA_CH_INT_CH_DISABLED +*\*\ - MDMA_CH_INT_CH_SUSPENDED +*\*\ - MDMA_CH_INT_CH_SRC_SUSPENDED +*\*\ - MDMA_CH_INT_CH_LOCK_CLEARED +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_HOLD_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W_ON_CH_EN_ERR +*\*\ - MDMA_CH_INT_SLV_IF_R2WO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_W2RO_ERR +*\*\ - MDMA_CH_INT_SLV_IF_DEC_ERR +*\*\ - MDMA_CH_INT_SLV_IF_MULTI_BLK_TYPE_ERR +*\*\ - MDMA_CH_INT_SDW_REG_LLI_INVALID_ERR +*\*\ - MDMA_CH_INT_LLI_W_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_R_SLV_ERR +*\*\ - MDMA_CH_INT_LLI_W_DEC_ERR +*\*\ - MDMA_CH_INT_LLI_R_DEC_ERR +*\*\ - MDMA_CH_INT_DST_SLV_ERR +*\*\ - MDMA_CH_INT_SRC_SLV_ERR +*\*\ - MDMA_CH_INT_DST_DEC_ERR +*\*\ - MDMA_CH_INT_SRC_DEC_ERR +*\*\ - MDMA_CH_INT_DST_TRAN_COMPLE +*\*\ - MDMA_CH_INT_SRC_TRAN_COMPLE +*\*\ - MDMA_CH_INT_DMA_TRF_DONE +*\*\ - MDMA_CH_INT_BLK_TRF_DONE +*\*\return SET or RESET +**/ +INTStatus MDMA_GetChannelInterruptStatus(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Interrupt) +{ + INTStatus RetStatus = RESET; + + /* Read the status of the corresponding interrupt */ + if (READ_BIT(MDMAy->CH[ChNum].INTSTS, Interrupt) != (uint32_t)RESET) + { + /* This status of the interrupt is SET */ + RetStatus = SET; + } + else + { + /* This status of the interrupt is RESET */ + RetStatus = RESET; + } + + /* Return status */ + return RetStatus; +} + +/** +*\*\name MDMA_SetChannelSourceAddress. +*\*\fun Sets the source address of the specified channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Addr: +*\*\ - Source address +*\*\return none +**/ +void MDMA_SetChannelSourceAddress(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint64_t Addr) +{ + WRITE_REG(MDMAy->CH[ChNum].SA, Addr); +} + +/** +*\*\name MDMA_SetChannelDestinationAddress. +*\*\fun Sets the destination address of the specified channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Addr: +*\*\ - Destination address +*\*\return none +**/ +void MDMA_SetChannelDestinationAddress(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint64_t Addr) +{ + WRITE_REG(MDMAy->CH[ChNum].DA, Addr); +} + +/** +*\*\name MDMA_SetChannelBlockSize. +*\*\fun Sets block size lenght for specific channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Size: +*\*\ - Block tranfer size for tranfering +*\*\return none +**/ +void MDMA_SetChannelBlockSize(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t Size) +{ + WRITE_REG(MDMAy->CH[ChNum].BTS, Size); +} + +/** +*\*\name MDMA_GetTransferredNumber. +*\*\fun Gets the number of data that has been transmitted by the current channel. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return Number of data sent +**/ +uint32_t MDMA_GetTransferredNumber(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + return READ_REG(MDMAy->CH[ChNum].BTS); +} + +/** +*\*\name MDMA_SetChannelLinkedListPointer. +*\*\fun Sets linked list pointer function. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param StrAddr: +*\*\ - MDMA linked list item structure address +*\*\return none +**/ +void MDMA_SetChannelLinkedListPointer(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint64_t StrAddr) +{ + WRITE_REG(MDMAy->CH[ChNum].LLP, StrAddr); +} + +/** +*\*\name MDMA_SetChannelSrcMultiBlockType. +*\*\fun Sets channel source multi block transfer type. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Type (The input parameters must be the following values): +*\*\ - MDMA_CH_MULTI_BLOCK_CONTIGUOUS +*\*\ - MDMA_CH_MULTI_BLOCK_RELOAD +*\*\ - MDMA_CH_MULTI_BLOCK_LINKED_LIST +*\*\return none +**/ +void MDMA_SetChannelSrcMultiBlockType(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChMultBlkTfrType Type) +{ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_SMBTT, ((uint64_t)Type << 0U)); +} + +/** +*\*\name MDMA_SetChannelDstMultiBlockType. +*\*\fun Sets channel destination multi block transfer type. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Type (The input parameters must be the following values): +*\*\ - MDMA_CH_MULTI_BLOCK_CONTIGUOUS +*\*\ - MDMA_CH_MULTI_BLOCK_RELOAD +*\*\ - MDMA_CH_MULTI_BLOCK_LINKED_LIST +*\*\return none +**/ +void MDMA_SetChannelDstMultiBlockType(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChMultBlkTfrType Type) +{ + MODIFY_REG(MDMAy->CH[ChNum].CFG, MDMA_CHNCFG_DMBTT, ((uint64_t)Type << 2U)); +} + +/** +*\*\name MDMA_TriggerSourceRequest. +*\*\fun Trigger a software source handshake request. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Type (The input parameters must be the following values): +*\*\ - MDMA_CH_SOFTWARE_HANDSHAKING_TFR_SINGLE +*\*\ - MDMA_CH_SOFTWARE_HANDSHAKING_TFR_BURST +*\*\param isLast: +*\*\ - true or false +*\*\return none +**/ +void MDMA_TriggerSourceRequest(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChSwHsTfrType Type, bool isLast) +{ + if (Type == MDMA_CH_SOFTWARE_HANDSHAKING_TFR_SINGLE) + { + /* Enable Channel n Source peripheral request for a single dma transfer */ + WRITE_REG(MDMAy->CH[ChNum].SHSRC, (MDMA_CHNSHSRC_SHSRWE | MDMA_CHNSHSRC_SHSR)); + } + else + { + /* Enable Channel n Source peripheral request for a burst dma transfer */ + WRITE_REG(MDMAy->CH[ChNum].SHSRC, (MDMA_CHNSHSRC_SHRWE | MDMA_CHNSHSRC_SHR)); + } + + if (isLast == true) + { + /* Indication that the curent transfer is the last transfer */ + WRITE_REG(MDMAy->CH[ChNum].SHSRC, (MDMA_CHNSHSRC_SHLRWE | MDMA_CHNSHSRC_SHLR)); + } +} + +/** +*\*\name MDMA_TriggerDestinationRequest. +*\*\fun Trigger a software Destination handshake request. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\param Type (The input parameters must be the following values): +*\*\ - MDMA_CH_SOFTWARE_HANDSHAKING_TFR_SINGLE +*\*\ - MDMA_CH_SOFTWARE_HANDSHAKING_TFR_BURST +*\*\param isLast: +*\*\ - true or false +*\*\return none +**/ +void MDMA_TriggerDestinationRequest(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, MDMA_ChSwHsTfrType Type, bool isLast) +{ + if (Type == MDMA_CH_SOFTWARE_HANDSHAKING_TFR_SINGLE) + { + /* Enable Channel n Destination peripheral request for a single dma transfer */ + WRITE_REG(MDMAy->CH[ChNum].SHDST, (MDMA_CHNSHDST_SHSRWE | MDMA_CHNSHDST_SHSR)); + } + else + { + /* Enable Channel n Destination peripheral request for a burst dma transfer */ + WRITE_REG(MDMAy->CH[ChNum].SHDST, (MDMA_CHNSHDST_SHRWE | MDMA_CHNSHDST_SHR)); + } + + if (isLast == true) + { + /* Indication that the curent transfer is the last transfer */ + WRITE_REG(MDMAy->CH[ChNum].SHDST, (MDMA_CHNSHDST_SHLRWE | MDMA_CHNSHDST_SHLR)); + } +} + +/** +*\*\name MDMA_BlockTransferResumeRequest. +*\*\fun Requests for resumption of block transfer during Linked-List-based +*\*\ multi-block transfer. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return none +**/ +void MDMA_BlockTransferResumeRequest(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + /* Request for resuming the block transfer */ + WRITE_REG(MDMAy->CH[ChNum].BTRR, MDMA_CHNBTRR_RESREQ); +} + +/** +*\*\name MDMA_SetChannelLinkedListItemValid. +*\*\fun Set the MDMA channel LLI valid. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return none +**/ +void MDMA_SetChannelLinkedListItemValid(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + SET_BIT(MDMAy->CH[ChNum].CTRL, MDMA_CHNCTRL_SRLLI); +} + +/** +*\*\name MDMA_ChannelLinkedListItemIsValid. +*\*\fun Check whether a MDMA channel LLI valid. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return true or false +**/ +bool MDMA_ChannelLinkedListItemIsValid(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + bool ret; + ret = READ_BIT(MDMAy->CH[ChNum].CTRL, MDMA_CHNCTRL_SRLLI) ? true : false; + return ret; +} + +/** +*\*\name MDMA_SetChannelLastLinkedListItem. +*\*\fun Set the current LLI to the last LLI. +*\*\param MDMAy (The input parameters must be the following values): +*\*\ - MDMA +*\*\param ChNum (The input parameters must be the following values): +*\*\ - MDMA_CHANNEL_0 +*\*\ - MDMA_CHANNEL_1 +*\*\ - MDMA_CHANNEL_2 +*\*\ - MDMA_CHANNEL_3 +*\*\ - MDMA_CHANNEL_4 +*\*\ - MDMA_CHANNEL_5 +*\*\ - MDMA_CHANNEL_6 +*\*\ - MDMA_CHANNEL_7 +*\*\ - MDMA_CHANNEL_8 +*\*\ - MDMA_CHANNEL_9 +*\*\ - MDMA_CHANNEL_10 +*\*\ - MDMA_CHANNEL_11 +*\*\ - MDMA_CHANNEL_12 +*\*\ - MDMA_CHANNEL_13 +*\*\ - MDMA_CHANNEL_14 +*\*\ - MDMA_CHANNEL_15 +*\*\return none +**/ +void MDMA_SetChannelLastLinkedListItem(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum) +{ + SET_BIT(MDMAy->CH[ChNum].CTRL, MDMA_CHNCTRL_LSRLLI); +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mmu.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mmu.c new file mode 100644 index 0000000000..daf8da9f11 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_mmu.c @@ -0,0 +1,598 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_mmu.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_mmu.h" + +/** +*\*\name MMU_ConfigReset. +*\*\fun This function Config MMU reset . +*\*\param Cmd: +*\*\ - ENABLE : Enable the Interrupt +*\*\ - DISABLE : Disable the Interrupt +*\*\return none +**/ +void MMU_ConfigReset(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + MMU->CTRL |= MMU_RESET; + } + else + { + MMU->CTRL &= (~MMU_RESET); + } +} + +/** +*\*\name MMU_ConfigInt. +*\*\fun This function Config MMU Interrupt . +*\*\param Cmd: +*\*\ - ENABLE : Enable the Interrupt +*\*\ - DISABLE : Disable the Interrupt +*\*\return none +**/ +void MMU_ConfigInt(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + MMU->CTRL |= MMU_INT_EN; + } + else + { + MMU->CTRL &= (~MMU_INT_EN); + } +} + +/** +*\*\name MMU_GetFlagStatus. +*\*\fun Checks whether the specified MMU flag is set or not. +*\*\param MMU_FLAG: (The input parameters must be the following values): +*\*\ - MMU_XSPI_LOCK_FLAG +*\*\ - MMU_ITCM_RERR_FLAG +*\*\ - MMU_ITCM_WERR_FLAG +*\*\ - MMU_BKSRAM_RERR_FLAG +*\*\ - MMU_BKSRAM_WERR_FLAG +*\*\ - MMU_AHBSRAM5_RERR_FLAG +*\*\ - MMU_AHBSRAM5_WERR_FLAG +*\*\ - MMU_AHBSRAM4_RERR_FLAG +*\*\ - MMU_AHBSRAM4_WERR_FLAG +*\*\ - MMU_AHBSRAM3_RERR_FLAG +*\*\ - MMU_AHBSRAM3_WERR_FLAG +*\*\ - MMU_AHBSRAM2_RERR_FLAG +*\*\ - MMU_AHBSRAM2_WERR_FLAG +*\*\ - MMU_AHBSRAM1_RERR_FLAG +*\*\ - MMU_AHBSRAM1_WERR_FLAG +*\*\ - MMU_AXISRAM3_RERR_FLAG +*\*\ - MMU_AXISRAM3_WERR_FLAG +*\*\ - MMU_AXISRAM2_RERR_FLAG +*\*\ - MMU_AXISRAM2_WERR_FLAG +*\*\ - MMU_AXISRAM1_RERR_FLAG +*\*\ - MMU_AXISRAM1_WERR_FLAG +*\*\ - MMU_OB_LOCK_FLAG +*\*\ - MMU_FLASH_LOCK_FLAG +*\*\ - MMU_XSPI_RERR_FLAG +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus MMU_GetFlagStatus(uint32_t MMU_FLAG) +{ + FlagStatus bitstatus; + + if ((MMU->STS & MMU_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name MMU_ClrFlag. +*\*\fun Clears the MMU's pending flags. +*\*\param MMU_FLAG: (The input parameters must be the following values): +*\*\ - MMU_ITCM_RERR_FLAG +*\*\ - MMU_ITCM_WERR_FLAG +*\*\ - MMU_BKSRAM_RERR_FLAG +*\*\ - MMU_BKSRAM_WERR_FLAG +*\*\ - MMU_AHBSRAM5_RERR_FLAG +*\*\ - MMU_AHBSRAM5_WERR_FLAG +*\*\ - MMU_AHBSRAM4_RERR_FLAG +*\*\ - MMU_AHBSRAM4_WERR_FLAG +*\*\ - MMU_AHBSRAM3_RERR_FLAG +*\*\ - MMU_AHBSRAM3_WERR_FLAG +*\*\ - MMU_AHBSRAM2_RERR_FLAG +*\*\ - MMU_AHBSRAM2_WERR_FLAG +*\*\ - MMU_AHBSRAM1_RERR_FLAG +*\*\ - MMU_AHBSRAM1_WERR_FLAG +*\*\ - MMU_AXISRAM3_RERR_FLAG +*\*\ - MMU_AXISRAM3_WERR_FLAG +*\*\ - MMU_AXISRAM2_RERR_FLAG +*\*\ - MMU_AXISRAM2_WERR_FLAG +*\*\ - MMU_AXISRAM1_RERR_FLAG +*\*\ - MMU_AXISRAM1_WERR_FLAG +*\*\ - MMU_XSPI_RERR_FLAG +*\*\return none +**/ +void MMU_ClrFlag(uint32_t MMU_FLAG) +{ + MMU->STS &= (~MMU_FLAG); +} + + +/** +*\*\name MMU_EnableRTAD. +*\*\fun This function Enable RTADx. +*\*\param RTADx : +*\*\ - MMU_RTAD1 +*\*\ - MMU_RTAD2 +*\*\ - MMU_RTAD3 +*\*\ - MMU_RTAD4 +*\*\param Cmd : +*\*\ - ENABLE Enable the RTADx +*\*\ - DISABLE Disable the RTADx +*\*\return none +**/ +void MMU_EnableRTAD(uint32_t RTADx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + *(uint32_t *)(MMU_BASE + (MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL))) |= MMU_RTAD_ENABLE; + } + else + { + *(uint32_t *)(MMU_BASE + (MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL))) &= (~MMU_RTAD_ENABLE); + } +} + +/** +*\*\name MMU_GetRTADRegionKey. +*\*\fun RTAD Partial Area KEY Configuration. +*\*\param region_key : +*\*\ - MMU_RTAD_REGION1_PART0_KEY MMU Region1 Part0 Key Register Offset Address +*\*\ - MMU_RTAD_REGION1_PART1_KEY MMU Region1 Part1 Key Register Offset Address +*\*\ - MMU_RTAD_REGION1_PART2_KEY MMU Region1 Part2 Key Register Offset Address +*\*\ - MMU_RTAD_REGION1_PART3_KEY MMU Region1 Part3 Key Register Offset Address +*\*\ - MMU_RTAD_REGION2_PART0_KEY MMU Region2 Part0 Key Register Offset Address +*\*\ - MMU_RTAD_REGION2_PART1_KEY MMU Region2 Part1 Key Register Offset Address +*\*\ - MMU_RTAD_REGION2_PART2_KEY MMU Region2 Part2 Key Register Offset Address +*\*\ - MMU_RTAD_REGION2_PART3_KEY MMU Region2 Part3 Key Register Offset Address +*\*\ - MMU_RTAD_REGION3_PART0_KEY MMU Region3 Part0 Key Register Offset Address +*\*\ - MMU_RTAD_REGION3_PART1_KEY MMU Region3 Part1 Key Register Offset Address +*\*\ - MMU_RTAD_REGION3_PART2_KEY MMU Region3 Part2 Key Register Offset Address +*\*\ - MMU_RTAD_REGION3_PART3_KEY MMU Region3 Part3 Key Register Offset Address +*\*\ - MMU_RTAD_REGION4_PART0_KEY MMU Region4 Part0 Key Register Offset Address +*\*\ - MMU_RTAD_REGION4_PART1_KEY MMU Region4 Part1 Key Register Offset Address +*\*\ - MMU_RTAD_REGION4_PART2_KEY MMU Region4 Part2 Key Register Offset Address +*\*\ - MMU_RTAD_REGION4_PART3_KEY MMU Region4 Part3 Key Register Offset Address +*\*\param key : The Key to Config +*\*\return none +**/ +uint32_t MMU_GetRTADRegionKey(uint32_t region) +{ + uint32_t key_temp; + key_temp = *(uint32_t *)(MMU_BASE + region); + return key_temp; +} + +/** +*\*\name MMU_ConfigRTADCFGLock. +*\*\fun This function Config RTADx Config Key Lock / Unlock. +*\*\param RTADx : +*\*\ - MMU_RTAD1 +*\*\ - MMU_RTAD2 +*\*\ - MMU_RTAD3 +*\*\ - MMU_RTAD4 +*\*\param Cmd : +*\*\ - ENABLE Enable the RTADx +*\*\ - DISABLE Disable the RTADx +*\*\return none +**/ +void MMU_ConfigRTADCFGLock(uint32_t RTADx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + *(uint32_t *)(MMU_BASE + (MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL))) |= MMU_RTAD_CFG_LOCK; + } + else + { + *(uint32_t *)(MMU_BASE + (MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL))) &= (~MMU_RTAD_CFG_LOCK); + } +} + +/** +*\*\name MMU_ConfigRTADKeyLock. +*\*\fun This function Config RTADx Key Lock / Unlock. +*\*\param RTADx : +*\*\ - MMU_RTAD1 +*\*\ - MMU_RTAD2 +*\*\ - MMU_RTAD3 +*\*\ - MMU_RTAD4 +*\*\param Cmd : +*\*\ - ENABLE Enable the RTADx +*\*\ - DISABLE Disable the RTADx +*\*\return none +**/ +void MMU_ConfigRTADKeyLock(uint32_t RTADx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + *(uint32_t *)(MMU_BASE + MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL)) |= MMU_RTAD_KEY_LOCK; + } + else + { + *(uint32_t *)(MMU_BASE + MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL)) &= (~MMU_RTAD_KEY_LOCK); + } +} + +/** +*\*\name MMU_ConfigRTADMode. +*\*\fun This function Config RTADx Work Mode. +*\*\param RTADx : +*\*\ - MMU_RTAD1 +*\*\ - MMU_RTAD2 +*\*\ - MMU_RTAD3 +*\*\ - MMU_RTAD4 +*\*\param mode : +*\*\ - MMU_RTAD_MODE_DEC_INST RTAD Work as Decryption Instruction +*\*\ - MMU_RTAD_MODE_DEC_DATA RTAD Work as Decryption Data / Literal +*\*\ - MMU_RTAD_MODE_DEC_ALL RTAD Work as Decryption Instruction and Data / Literal +*\*\return none +**/ +void MMU_ConfigRTADMode(uint32_t RTADx, uint32_t mode) +{ + /* Clear the Mode Field */ + *(uint32_t *)(MMU_BASE + MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL)) &= (~MMU_RTAD_MODE_MASK); + + /* Config the Mode */ + *(uint32_t *)(MMU_BASE + MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL)) |= (mode); +} + +/** +*\*\name MMU_ConfigRTADProperty. +*\*\fun This function Config RTADx Property. +*\*\param RTADx : +*\*\ - MMU_RTAD1 +*\*\ - MMU_RTAD2 +*\*\ - MMU_RTAD3 +*\*\ - MMU_RTAD4 +*\*\param property : +*\*\ - MMU_RTAD_PROPERTY_INST Instruction Can Fetch this Region +*\*\ - MMU_RTAD_PROPERTY_DATA Data Can Fetch this Region +*\*\ - MMU_RTAD_PROPERTY_ALL Instruction and Data Can Fetch this Region +*\*\return none +**/ +void MMU_ConfigRTADProperty(uint32_t RTADx, uint32_t property) +{ + /* Clear the Mode Field */ + *(uint32_t *)(MMU_BASE + MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL)) &= (~MMU_RTAD_PROPERTY_MASK); + + /* Config the Mode */ + *(uint32_t *)(MMU_BASE + MMU_RTAD_ADDRESS_OFFSET + ((RTADx - 1UL) * 4UL)) |= (property); +} + +/** +*\*\name MMU_ConfigRTADRegionAddress. +*\*\fun This function Config the Region Address. +*\*\param region : +*\*\ - MMU_RTAD_REGION1 +*\*\ - MMU_RTAD_REGION2 +*\*\ - MMU_RTAD_REGION3 +*\*\ - MMU_RTAD_REGION4 +*\*\param begin_addr : 0x0000~0x1FFF, The Region begin Address,Granularity size 4KB +*\*\param end_addr : 0x0000~0x1FFF, The Region end Address,Granularity size 4KB +*\*\return none +**/ +void MMU_ConfigRTADRegionAddress(uint32_t region, uint32_t begin_addr, uint32_t end_addr) +{ + *(uint32_t *)(MMU_BASE + MMU_RTR_ADDRESS_OFFSET + ((region - 1UL) * 4UL)) = (begin_addr | (end_addr << MMU_RTR_ENDADDR_OFFSET)); +} + +/** +*\*\name MMU_GetRTADCRC. +*\*\fun This function Return RTADx CRC Value. +*\*\param none +*\*\return uint32_t : The RTAD CRC +**/ +uint32_t MMU_GetRTADCRC(void) +{ + return ((uint32_t) MMU->RTCRC); +} + +/** +*\*\name MMU_EnableModuleMemory. +*\*\fun This function Config the Module Memory Enable / Disable. +*\*\param RTADx : +*\*\ - MMU_MEMORY_ETH1 Enable ETH1 Memory +*\*\ - MMU_MEMORY_ETH2 Enable ETH2 Memory +*\*\ - MMU_MEMORY_USB1 Enable USB1 Memory +*\*\ - MMU_MEMORY_USB2 Enable USB2 Memory +*\*\ - MMU_MEMORY_SDMMC1 Enable SDMMC1 Memory +*\*\ - MMU_MEMORY_SDMMC2 Enable SDMMC2 Memory +*\*\ - MMU_MEMORY_DVP1 Enable DVP1 Memory +*\*\ - MMU_MEMORY_DVP2 Enable DVP2 Memory +*\*\ - MMU_MEMORY_DMA1 Enable DMA1 Memory +*\*\ - MMU_MEMORY_DMA2 Enable DMA2 Memory +*\*\ - MMU_MEMORY_DMA3 Enable DMA3 Memory +*\*\ - MMU_MEMORY_MDMA Enable MDMA Memory +*\*\ - MMU_MEMORY_JPEG Enable JPEG Memory +*\*\ - MMU_MEMORY_LCDC Enable LCDC Memory +*\*\ - MMU_MEMORY_GPU Enable GPU Memory +*\*\ - MMU_MEMORY_SDPU Enable SDPU Memory +*\*\param Cmd : +*\*\ ENABLE Enable the Memory +*\*\ DISABLE Disable the Memory +*\*\return none +**/ +void MMU_EnableModuleMemory(uint32_t module, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + *(uint32_t *)(MMU_BASE + MMU_MEMORY_ADDRESS_OFFSET + ((module - 1UL) * 4UL)) |= MMU_MEMORY_EN; + } + else + { + *(uint32_t *)(MMU_BASE + MMU_MEMORY_ADDRESS_OFFSET + ((module - 1UL) * 4UL)) &= (~MMU_MEMORY_EN); + } +} + +/** +*\*\name MMU_GetModuleUserID. +*\*\fun This function Get Module User ID +*\*\param RTADx : +*\*\ - MMU_MEMORY_ETH1 Enable ETH1 Memory +*\*\ - MMU_MEMORY_ETH2 Enable ETH2 Memory +*\*\ - MMU_MEMORY_USB1 Enable USB1 Memory +*\*\ - MMU_MEMORY_USB2 Enable USB2 Memory +*\*\ - MMU_MEMORY_SDMMC1 Enable SDMMC1 Memory +*\*\ - MMU_MEMORY_SDMMC2 Enable SDMMC2 Memory +*\*\ - MMU_MEMORY_DVP1 Enable DVP1 Memory +*\*\ - MMU_MEMORY_DVP2 Enable DVP2 Memory +*\*\ - MMU_MEMORY_DMA1 Enable DMA1 Memory +*\*\ - MMU_MEMORY_DMA2 Enable DMA2 Memory +*\*\ - MMU_MEMORY_DMA3 Enable DMA3 Memory +*\*\ - MMU_MEMORY_MDMA Enable MDMA Memory +*\*\ - MMU_MEMORY_JPEG Enable JPEG Memory +*\*\ - MMU_MEMORY_LCDC Enable LCDC Memory +*\*\ - MMU_MEMORY_GPU Enable GPU Memory +*\*\ - MMU_MEMORY_SDPU Enable SDPU Memory +*\*\return UID: The corresponding bit set to 1 indicates that it is enabled by the corresponding user. +*\*\ - [0]:other_id(SDRAM,external SRAM,etc), [1]: nonsec_tcm/sram, [2]: sec_tcm/sram, [3]:non_sec_flash, +*\*\ - [4] pfoer_flash, [5]: sec_flash, [6]: bootrom_api, [7]:sec_bootrom +**/ +uint8_t MMU_GetModuleUserID(uint32_t module) +{ + uint32_t UID_temp; + UID_temp = *(uint32_t *)(MMU_BASE + MMU_MEMORY_ADDRESS_OFFSET + ((module - 1UL) * 4UL)); + return ((uint8_t) (UID_temp >> MMU_MEMORY_UID_OFFSET)); +} + +/** +*\*\name MMU_GetModuleMasterID. +*\*\fun This function Get the Module Master ID. +*\*\param RTADx : +*\*\ - MMU_MEMORY_ETH1 Enable ETH1 Memory +*\*\ - MMU_MEMORY_ETH2 Enable ETH2 Memory +*\*\ - MMU_MEMORY_USB1 Enable USB1 Memory +*\*\ - MMU_MEMORY_USB2 Enable USB2 Memory +*\*\ - MMU_MEMORY_SDMMC1 Enable SDMMC1 Memory +*\*\ - MMU_MEMORY_SDMMC2 Enable SDMMC2 Memory +*\*\ - MMU_MEMORY_DVP1 Enable DVP1 Memory +*\*\ - MMU_MEMORY_DVP2 Enable DVP2 Memory +*\*\ - MMU_MEMORY_DMA1 Enable DMA1 Memory +*\*\ - MMU_MEMORY_DMA2 Enable DMA2 Memory +*\*\ - MMU_MEMORY_DMA3 Enable DMA3 Memory +*\*\ - MMU_MEMORY_MDMA Enable MDMA Memory +*\*\ - MMU_MEMORY_JPEG Enable JPEG Memory +*\*\ - MMU_MEMORY_LCDC Enable LCDC Memory +*\*\ - MMU_MEMORY_GPU Enable GPU Memory +*\*\ - MMU_MEMORY_SDPU Enable SDPU Memory +*\*\return MID: The corresponding bit set to 1 indicates that it is enabled by the corresponding master. +*\*\ - [0]: CM7,[1]: CM4,[2]: DEBUG +**/ +uint8_t MMU_GetModuleMasterID(uint32_t module) +{ + uint32_t MID_temp; + MID_temp = *(uint32_t *)(MMU_BASE + MMU_MEMORY_ADDRESS_OFFSET + ((module - 1UL) * 4UL)); + return ((uint8_t) (MID_temp >> MMU_MEMORY_MID_OFFSET)); +} + +/** +*\*\name MMU_GetReadErrorAddress. +*\*\fun This function Get the Read Error Address. +*\*\param readerroraddr : The Read Error Register Offset Address +*\*\ - MMU_XRAD_ADDR_OFFSET XSPI read error address +*\*\ - MMU_X1RAD_ADDR_OFFSET AXI SRAM1 read error address +*\*\ - MMU_X2RAD_ADDR_OFFSET AXI SRAM2 read error address +*\*\ - MMU_X3RAD_ADDR_OFFSET AXI SRAM3 read error address +*\*\ - MMU_H1RAD_ADDR_OFFSET AHB SRAM1 read error address +*\*\ - MMU_H2RAD_ADDR_OFFSET AHB SRAM2 read error address +*\*\ - MMU_H3RAD_ADDR_OFFSET AHB SRAM3 read error address +*\*\ - MMU_H4RAD_ADDR_OFFSET AHB SRAM4 read error address +*\*\ - MMU_H5RAD_ADDR_OFFSET AHB SRAM5 read error address +*\*\ - MMU_BKRAD_ADDR_OFFSET Backup SRAM read error address +*\*\ - MMU_ITRAD_ADDR_OFFSET ITCM SRAM read error address +*\*\return uint32_t error address +**/ +uint32_t MMU_GetReadErrorAddress(uint32_t readerroraddr) +{ + return ((uint32_t) (*(uint32_t *)(MMU_BASE + readerroraddr))); +} + +/** +*\*\name MMU_GetWriteErrorAddress. +*\*\fun This function Get the Write Error Address. +*\*\param writeerroraddr : The Write Error Register Offset Address +*\*\ - MMU_X1WAD_ADDR_OFFSET AXI SRAM1 read error address +*\*\ - MMU_X2WAD_ADDR_OFFSET AXI SRAM2 read error address +*\*\ - MMU_X3WAD_ADDR_OFFSET AXI SRAM3 read error address +*\*\ - MMU_H1WAD_ADDR_OFFSET AHB SRAM1 read error address +*\*\ - MMU_H2WAD_ADDR_OFFSET AHB SRAM2 read error address +*\*\ - MMU_H3WAD_ADDR_OFFSET AHB SRAM3 read error address +*\*\ - MMU_H4WAD_ADDR_OFFSET AHB SRAM4 read error address +*\*\ - MMU_H5WAD_ADDR_OFFSET AHB SRAM5 read error address +*\*\ - MMU_BKWAD_ADDR_OFFSET Backup SRAM read error address +*\*\ - MMU_ITWAD_ADDR_OFFSET ITCM SRAM read error address +*\*\return uint32_t error address +**/ +uint32_t MMU_GetWriteErrorAddress(uint32_t writeerroraddr) +{ + return ((uint32_t) (*(uint32_t *)(MMU_BASE + writeerroraddr))); +} + +/** +*\*\name MMU_GetWriteErrorMasterID. +*\*\fun This function Get Write Error Master ID. +*\*\param writeerrordebug: The Write Error ID Register Offset Address +*\*\ - MMU_X1WD_ADDR_OFFSET AXI SRAM1 read error debug +*\*\ - MMU_X2WD_ADDR_OFFSET AXI SRAM2 read error debug +*\*\ - MMU_X3WD_ADDR_OFFSET AXI SRAM3 read error debug +*\*\ - MMU_H1WD_ADDR_OFFSET AHB SRAM1 read error debug +*\*\ - MMU_H2WD_ADDR_OFFSET AHB SRAM2 read error debug +*\*\ - MMU_H3WD_ADDR_OFFSET AHB SRAM3 read error debug +*\*\ - MMU_H4WD_ADDR_OFFSET AHB SRAM4 read error debug +*\*\ - MMU_H5WD_ADDR_OFFSET AHB SRAM5 read error debug +*\*\ - MMU_BKWD_ADDR_OFFSET Backup SRAM read error debug +*\*\ - MMU_ITWD_ADDR_OFFSET ITCM SRAM read error debug +*\*\return MID: The corresponding bit set to 1 indicates that it is enabled by the corresponding master. +*\*\ - [0]: DEBUG,[1]: other non-cpu master(ETH/USB/etc),[2]: CM7,[3]: CM4 +**/ +uint32_t MMU_GetWriteErrorMasterID(uint32_t writeerrordebug) +{ + uint32_t MID_temp; + MID_temp = *(uint32_t *)(MMU_BASE + writeerrordebug); + return ((uint8_t) (MID_temp >> MMU_WERRDEBUG_MID_OFFSET)); +} + +/** +*\*\name MMU_GetWriteErrorUserID. +*\*\fun This function Get Write Error User ID. +*\*\param writeerrordebug : The Write Error ID Register Offset Address +*\*\ - MMU_X1WD_ADDR_OFFSET AXI SRAM1 read error debug +*\*\ - MMU_X2WD_ADDR_OFFSET AXI SRAM2 read error debug +*\*\ - MMU_X3WD_ADDR_OFFSET AXI SRAM3 read error debug +*\*\ - MMU_H1WD_ADDR_OFFSET AHB SRAM1 read error debug +*\*\ - MMU_H2WD_ADDR_OFFSET AHB SRAM2 read error debug +*\*\ - MMU_H3WD_ADDR_OFFSET AHB SRAM3 read error debug +*\*\ - MMU_H4WD_ADDR_OFFSET AHB SRAM4 read error debug +*\*\ - MMU_H5WD_ADDR_OFFSET AHB SRAM5 read error debug +*\*\ - MMU_BKWD_ADDR_OFFSET Backup SRAM read error debug +*\*\ - MMU_ITWD_ADDR_OFFSET ITCM SRAM read error debug +*\*\return UID: The corresponding bit set to 1 indicates that it is enabled by the corresponding user. +*\*\ - [0]:other_id(SDRAM,external SRAM,etc), [1]: nonsec_tcm/sram, [2]: sec_tcm/sram, [3]:non_sec_flash, +*\*\ - [4] pfoer_flash, [5]: sec_flash, [6]: bootrom_api, [7]:sec_bootrom +**/ +uint32_t MMU_GetWriteErrorUserID(uint32_t writeerrordebug) +{ + uint32_t UID_temp; + UID_temp = *(uint32_t *)(MMU_BASE + writeerrordebug); + return ((uint8_t) UID_temp); +} + +/** +*\*\name MMU_GetReadErrorMasterID. +*\*\fun This function Get Read Error Master ID. +*\*\param readerrordebug : The Read Error ID Register Offset Address +*\*\ - MMU_XRD_ADDR_OFFSET XSPI read error debug +*\*\ - MMU_X1RD_ADDR_OFFSET AXI SRAM1 read error debug +*\*\ - MMU_X2RD_ADDR_OFFSET AXI SRAM2 read error debug +*\*\ - MMU_X3RD_ADDR_OFFSET AXI SRAM3 read error debug +*\*\ - MMU_H1RD_ADDR_OFFSET AHB SRAM1 read error debug +*\*\ - MMU_H2RD_ADDR_OFFSET AHB SRAM2 read error debug +*\*\ - MMU_H3RD_ADDR_OFFSET AHB SRAM3 read error debug +*\*\ - MMU_H4RD_ADDR_OFFSET AHB SRAM4 read error debug +*\*\ - MMU_H5RD_ADDR_OFFSET AHB SRAM5 read error debug +*\*\ - MMU_BKRD_ADDR_OFFSET Backup SRAM read error debug +*\*\ - MMU_ITRD_ADDR_OFFSET ITCM SRAM read error debug +*\*\return MID: The corresponding bit set to 1 indicates that it is enabled by the corresponding master. +*\*\ - [0]: DEBUG,[1]: other non-cpu master(ETH/USB/etc),[2]: CM7,[3]: CM4 +**/ +uint32_t MMU_GetReadErrorMasterID(uint32_t readerrordebug) +{ + uint32_t MID_temp; + MID_temp = *(uint32_t *)(MMU_BASE + readerrordebug); + return ((uint8_t) (MID_temp >> MMU_WERRDEBUG_MID_OFFSET)); +} + +/** +*\*\name MMU_GetReadErrorUserID. +*\*\fun This function Get Read Error User ID. +*\*\param readerrordebug : The Read Error ID Register Offset Address +*\*\ - MMU_XRD_ADDR_OFFSET XSPI read error debug +*\*\ - MMU_X1RD_ADDR_OFFSET AXI SRAM1 read error debug +*\*\ - MMU_X2RD_ADDR_OFFSET AXI SRAM2 read error debug +*\*\ - MMU_X3RD_ADDR_OFFSET AXI SRAM3 read error debug +*\*\ - MMU_H1RD_ADDR_OFFSET AHB SRAM1 read error debug +*\*\ - MMU_H2RD_ADDR_OFFSET AHB SRAM2 read error debug +*\*\ - MMU_H3RD_ADDR_OFFSET AHB SRAM3 read error debug +*\*\ - MMU_H4RD_ADDR_OFFSET AHB SRAM4 read error debug +*\*\ - MMU_H5RD_ADDR_OFFSET AHB SRAM5 read error debug +*\*\ - MMU_BKRD_ADDR_OFFSET Backup SRAM read error debug +*\*\ - MMU_ITRD_ADDR_OFFSET ITCM SRAM read error debug +*\*\return UID: The corresponding bit set to 1 indicates that it is enabled by the corresponding user. +*\*\ - [0]:other_id(SDRAM,external SRAM,etc), [1]: nonsec_tcm/sram, [2]: sec_tcm/sram, [3]:non_sec_flash, +*\*\ - [4] pfoer_flash, [5]: sec_flash, [6]: bootrom_api, [7]:sec_bootrom +**/ +uint32_t MMU_GetReadErrorUserID(uint32_t readerrordebug) +{ + uint32_t UID_temp; + UID_temp = *(uint32_t *)(MMU_BASE + readerrordebug); + return ((uint8_t) UID_temp); +} + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_otpc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_otpc.c new file mode 100644 index 0000000000..d3eb6d9e4a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_otpc.c @@ -0,0 +1,555 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_otpc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_otpc.h" + +/** +*\*\name OTPC_Unlock. +*\*\fun This function Unlock the CTRL Register. +*\*\param none +*\*\return none +**/ +void OTPC_Unlock(void) +{ + /* Unlock the OTPC_CTRL */ + OTPC->KEY = OTPC_KEY1; + OTPC->KEY = OTPC_KEY2; +} + +/** +*\*\name OTPC_Lock. +*\*\fun This function Lock the CTRL Register. +*\*\param none +*\*\return none +**/ +void OTPC_Lock(void) +{ + /* Lock the OTPC_CTRL */ + OTPC->CTRL |= OTPC_CMD_LOCK; +} + +/** +*\*\name OTPC_GetLockStatus. +*\*\fun This function return the Unlock status. +*\*\param none +*\*\return FlagStatus: +*\*\ SET OTPC_CTRL is Locked +*\*\ RESET OTPC_CTRL is Unlock +**/ +FlagStatus OTPC_GetLockStatus(void) +{ + FlagStatus bitstatus; + + /* Return the Lock status */ + if ((OTPC->CTRL & OTPC_CMD_LOCK) == OTPC_CMD_LOCK) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} +/** +*\*\name OTPC_SetUsCount. +*\*\fun This function Sets the us Conter. +*\*\param us_count : 0x00000000 - 0x000001FF +*\*\return none +**/ +void OTPC_SetUsCount(uint32_t us_count) +{ + /* Set the us Counter */ + OTPC->USC = (OTPC_USC_MASK & us_count); +} +/** +*\*\name OTPC_GetFlagStatus. +*\*\fun This function return the Flag status. +*\*\param optc_flag +*\*\ - OTPC_FLAG_BE Busy Error Flag +*\*\ - OTPC_FLAG_OORE Read / Write out of Range Error Flag +*\*\ - OTPC_FLAG_RDPE Read Protection Error Flag +*\*\ - OTPC_FLAG_WRPE Write Protection Error Flag +*\*\ - OTPC_FLAG_PGE Program Error Flag +*\*\ - OTPC_FLAG_KEYE Key Error Flag +*\*\ - OTPC_FLAG_BUSY Busy Flag +*\*\return FlagStatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus OTPC_GetFlagStatus(uint32_t optc_flag) +{ + FlagStatus bitstatus; + + if ((OTPC->STS & optc_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name OTPC_ClearFlag. +*\*\fun This function Clear the Flag status. +*\*\param optc_flag +*\*\ - OTPC_FLAG_BE Busy Error Flag +*\*\ - OTPC_FLAG_OORE Read / Write out of Range Error Flag +*\*\ - OTPC_FLAG_RDPE Read Protection Error Flag +*\*\ - OTPC_FLAG_WRPE Write Protection Error Flag +*\*\ - OTPC_FLAG_PGE Program Error Flag +*\*\return none +**/ +void OTPC_ClearFlag(uint32_t optc_flag) +{ + /* Write 1 Clear the Flags */ + OTPC->STS = optc_flag; +} + +/** +*\*\name OTPC_ConfigInterrupt. +*\*\fun This function Enable the OTPC Interrupt. +*\*\param otpc_int: +*\*\ - OTPC_INT_BE Busy Error Interrupt Enable +*\*\ - OTPC_INT_OORE Read / Write out of Range Error Interrupt Enable +*\*\ - OTPC_INT_RDPE Read Protection Error Interrupt Enable +*\*\ - OTPC_INT_WRPE Write Protection Error Interrupt Enable +*\*\ - OTPC_INT_PGE Program Error Interrupt Enable +*\*\ FunctionalState: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void OTPC_ConfigInterrupt(uint32_t otpc_int, FunctionalState cmd) +{ + if(cmd == ENABLE) + { + OTPC->CTRL |= otpc_int; + } + else + { + OTPC->CTRL &= (~otpc_int); + } +} + +/** +*\*\name OTPC_ClearFlag. +*\*\fun This function Check the Error Flag. +*\*\param none +*\*\return FlagStatus +*\*\ - RESET No Error Occur +*\*\ - SET Has Error Occur +**/ +FlagStatus OTPC_CheckError(void) +{ + FlagStatus bitstatus; + + /* Check the Error Flag */ + if((OTPC->STS & OTPC_ALLERROR_STS) == RESET) + { + bitstatus = RESET; + } + else + { + /* Has Error Occur */ + bitstatus = SET; + } + + return bitstatus; +} + +/** +*\*\name OTPC_WaitForLastOperation. +*\*\fun This function Wait For the Last Operation is Complete. +*\*\param none +*\*\return OTPC_STS +*\*\ - OTPC_ERR_TIMEOUT Last Operation TimeOut Error Occur +*\*\ - OTPC_COMPLETE Last Operation Complete without any Errors +*\*\ - OTPC_UNCOMPLETE Last Operation has Error Occur +**/ +OTPC_STS OTPC_WaitForLastOperation(void) +{ + FlagStatus flag_status = SET; + OTPC_STS status_temp; + uint32_t time_out = OTPC_TIME_OUT; + + while((flag_status != RESET) && (time_out != 0)) + { + /* Get Busy Flag */ + flag_status = OTPC_GetFlagStatus(OTPC_FLAG_BUSY); + time_out--; + } + + if(time_out == 0) + { + status_temp = OTPC_ERR_TIMEOUT; + } + else if(OTPC_CheckError() == SET) + { + status_temp = OTPC_UNCOMPLETE; + } + else + { + status_temp = OTPC_COMPLETE; + } + + return status_temp; +} + +/** +*\*\name OTPC_WriteEnable. +*\*\fun This function Enable the OTPC Operation as Write. +*\*\param none +*\*\return none +**/ +void OTPC_WriteEnable(void) +{ + OTPC->CTRL |= OTPC_CMD_WRITE; +} + +/** +*\*\name OTPC_ReadEnable. +*\*\fun This function Enable the OTPC Operation as Read. +*\*\param none +*\*\return none +**/ +void OTPC_ReadEnable(void) +{ + OTPC->CTRL &= OTPC_CMD_READ; +} + +/** +*\*\name OTPC_ConfigAddr. +*\*\fun This function Set the Operate Address. +*\*\param addr : 0x00000500 - 0x000005FF +*\*\return none +**/ +void OTPC_SetAddr(uint32_t addr) +{ + OTPC->ADDR = addr; +} + +/** +*\*\name OTPC_SetWriteData. +*\*\fun This function Set the Write data. +*\*\param data : The data need to be Programed +*\*\return none +**/ +void OTPC_SetWriteData(uint32_t data) +{ + OTPC->WDATA = data; +} + +/** +*\*\name OTPC_ProgramWord. +*\*\fun This function Program data at addr. +*\*\param addr : 0x00000500 - 0x000005FF +*\*\ data : The data need to be Programed +*\*\return OTPC_STS +*\*\ - OTPC_ERR_TIMEOUT Last Operation TimeOut Error Occur +*\*\ - OTPC_COMPLETE Last Operation Complete without any Error +*\*\ - OTPC_UNCOMPLETE Last Operation has Error Occur +*\*\note During the write operation, NRST cannot be reset +**/ +OTPC_STS OTPC_ProgramWord(uint32_t addr, uint32_t data) +{ + OTPC_STS otpc_status; + OTPC_ClearFlag(OTPC_ERROR_STS); + /* Get Last Operation Status */ + otpc_status = OTPC_WaitForLastOperation(); + + /* Last Operation Not Complete and Errors Occur */ + if(otpc_status == OTPC_COMPLETE) + { + OTPC_WriteEnable(); + OTPC_SetWriteData(data); + OTPC_SetAddr(addr); + /* Get Last Operation Status */ + otpc_status = OTPC_WaitForLastOperation(); + } + + return otpc_status; +} + +/** +*\*\name OTPC_ReadWord. +*\*\fun This function Read data at addr. +*\*\param addr : 0x00000300 - 0x000003CF,0x00000500 - 0x000005FF +*\*\ *data : The Point of the data need to be Read; +*\*\return OTPC_STS +*\*\ - OTPC_ERR_TIMEOUT Last Operation TimeOut Error Occur +*\*\ - OTPC_COMPLETE Last Operation Complete without any Error +*\*\ - OTPC_UNCOMPLETE Last Operation has Error Occur +**/ +OTPC_STS OTPC_ReadWord(uint32_t addr, uint32_t *data) +{ + /* Get Last Operation Status */ + OTPC_STS otpc_status = OTPC_WaitForLastOperation(); + + /* Last Operation Not Complete and Errors Occur */ + if(otpc_status != OTPC_COMPLETE) + { + /* no process */ + } + else + { + OTPC_ReadEnable(); + OTPC_SetAddr(addr); + otpc_status = OTPC_WaitForLastOperation(); + } + + if(otpc_status != OTPC_COMPLETE) + { + /* no process */ + } + else + { + *data = OTPC->RDATA; + } + + return otpc_status; +} + +/** +*\*\name OTPC_GetUserCfgVaildNum. +*\*\fun This function Check the 16 Copies region is programble. +*\*\param ConfigUser +*\*\ - OTPC_SEC_JTAG_REG +*\*\ - OTPC_SEC_MODE_REG +*\*\ - OTPC_RDP2_REG +*\*\ - OTPC_BTM_REG +*\*\ - OTPC_BOR_REG +*\*\ - OTPC_IWDG_REG +*\*\ - OTPC_TCM_SIZE_REG +*\*\ - OTPC_JTAG_KEY_REG +*\*\ - OTPC_REK_UNIT1_REG +*\*\ - OTPC_REK_UNIT2_REG +*\*\ - OTPC_REK_UNIT3_REG +*\*\ - OTPC_REK_UNIT4_REG +*\*\ - OTPC_IDK_UNIT1_REG +*\*\ - OTPC_IDK_UNIT2_REG +*\*\ - OTPC_IDK_UNIT3_REG +*\*\ - OTPC_IDK_UNIT4_REG +*\*\return value_temp : The quantity containing 1 in the lower 16 bits indicates the remaining programmable quantity +**/ +uint32_t OTPC_GetUserCfgVaildNum(uint32_t ConfigUser) +{ + uint32_t value_temp; + value_temp = *(uint32_t*)(OTPC_BASE + ConfigUser); + value_temp &= OTPC_VARIOUS_REG_MASK; + return value_temp; +} + +/** +*\*\name OTPC_CheckUserMemoryUnused. +*\*\fun This function Check the User Memory Unused region is programble. +*\*\param addr : 0x0500 ~ 0x05FF +*\*\return FlagStatus : +*\*\ - SET The Check Address is Programble +*\*\ - RESET The Check Address is not Programble +**/ +FlagStatus OTPC_CheckUserMemoryUnused(uint32_t addr) +{ + FlagStatus value_stauts; + uint32_t base_addr; + uint32_t vaild_bit; + + /* Get the register address corresponding to the address FLAG */ + base_addr = OTPC_BASE + OTPC_UMUU_BASE_REG + (((addr - OTPC_UNUSE_STARTADDRESS) / OTPC_UNUSE_PAGESIZE) * 4U); + /* Get the register bit corresponding to the address FLAG */ + vaild_bit = (addr - OTPC_UNUSE_STARTADDRESS) % OTPC_UNUSE_PAGESIZE; + + if(((*(uint32_t*)base_addr) & (0x01UL << vaild_bit)) == RESET) + { + value_stauts = RESET; + } + else + { + value_stauts = SET; + } + + return value_stauts; +} + + +/** +*\*\name OTPC_GetReload. +*\*\fun This function Return the OTPC_CFG_RELOAD Values. +*\*\param DBGReloadValue pointer to an OTPC_DBGReloadValue structure. +*\*\ - NRST_IWDG_OTPValue +*\*\ - bit13: nRST_STOP_C_M7; When entering STOP0/STOP2 mode, the system will automatically reset +*\*\ - 0: Reset +*\*\ - 1: No reset +*\*\ - bit12: nRST_STOP_C_M4; When entering STOP0/STOP2 mode, the system will automatically reset +*\*\ - 0: Reset +*\*\ - 1: No reset +*\*\ - bit11: nRST_STDBY_C_M7; When entering Standby mode, the system will automatically reset +*\*\ - 0: Reset +*\*\ - 1: No reset +*\*\ - bit10: nRST_STDBY_C_M4; When entering Standby mode, the system will automatically reset +*\*\ - 0: Reset +*\*\ - 1: No reset +*\*\ - bit9 : IWDG_SW_M7; iwdg control selection +*\*\ - 0: hardware +*\*\ - 1: software +*\*\ - bit8 : IWDG_SW_M4; iwdg control selection +*\*\ - 0: hardware +*\*\ - 1: software +*\*\ - bit7 : IWDG_STOP0_M7; IWDG's activity status in STOP0 mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit6 : IWDG_STOP0_M4; IWDG's activity status in STOP0 mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit5 : IWDG_STOP2_M7; IWDG's activity status in STOP2 mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit4 : IWDG_STOP2_M4; IWDG's activity status in STOP2 mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit3 : IWDG_STANDBY_M7; IWDG's activity status in STANDBY mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit2 : IWDG_STANDBY_M4; IWDG's activity status in STANDBY mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit1 : IWDG_SLEEP_M7; IWDG's activity status in SLEEP mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - bit0 : IWDG_SLEEP_M4; IWDG's activity status in SLEEP mode +*\*\ - 0: Freeze +*\*\ - 1: Active +*\*\ - BOR_OTPValue +*\*\ - 0x00~0x07 +*\*\ - SEC_JTAG_OTPValue +*\*\ - 0x0F/0x09: JTAG/SWD Enable +*\*\ - others: JTAG/SWD Disable +*\*\ - L2MODE +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - L1MODE +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - L0MODE +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - ROOTMODE +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - INITMODE +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - TCM_SIZE_OTPValue +*\*\ - 0x00~0x3F,For detailed description, please refer to the System Security section of the User Manual, OTP Options byte +*\*\return none +**/ +void OTPC_GetReload(OTPC_DBGReloadValue* DBGReloadValue) +{ + DBGReloadValue->NRST_IWDG_OTPValue = ((OTPC->CRLD1) & OTPC_CRLD1_NRIWDG) >> OTPC_CRLD1_NRIWDG_OFFSET; + DBGReloadValue->BOR_OTPValue = ((OTPC->CRLD1) & OTPC_CRLD1_BOR) >> OTPC_CRLD1_BOR_OFFSET; + DBGReloadValue->SEC_JTAG_OTPValue = ((OTPC->CRLD1) & OTPC_CRLD1_SJAG); + + if((OTPC->CRLD2 & OTPC_CRLD2_L2MD) == RESET) + { + DBGReloadValue->L2MODE = RESET; + } + else + { + DBGReloadValue->L2MODE = SET; + } + + if((OTPC->CRLD2 & OTPC_CRLD2_L1MD) == RESET) + { + DBGReloadValue->L1MODE = RESET; + } + else + { + DBGReloadValue->L1MODE = SET; + } + + if((OTPC->CRLD2 & OTPC_CRLD2_L0MD) == RESET) + { + DBGReloadValue->L0MODE = RESET; + } + else + { + DBGReloadValue->L0MODE = SET; + } + + if((OTPC->CRLD2 & OTPC_CRLD2_ROOTMD) == RESET) + { + DBGReloadValue->ROOTMODE = RESET; + } + else + { + DBGReloadValue->ROOTMODE = SET; + } + + if((OTPC->CRLD2 & OTPC_CRLD2_INITMD) == RESET) + { + DBGReloadValue->INITMODE = RESET; + } + else + { + DBGReloadValue->INITMODE = SET; + } + + DBGReloadValue->TCM_SIZE_OTPValue = ((OTPC->CRLD2) & OTPC_CRLD2_TCMSZ); +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_pwr.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_pwr.c new file mode 100644 index 0000000000..582ed609dd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_pwr.c @@ -0,0 +1,1580 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_pwr.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_pwr.h" +#include "n32h76x_78x_rcc.h" +#include "misc.h" + +#define GRAPHIC_MODULE_MASK ((uint32_t)0x0000001FU) +#define HSC1_MODULE_MASK ((uint32_t)0x00000700U) +#define HSC2_MODULE_MASK ((uint32_t)0x000000E0U) +/** +*\*\name PWR_DeInit. +*\*\fun Deinitializes the PWR peripheral registers to their default reset values. +*\*\param none +*\*\return none +**/ +void PWR_DeInit(void) +{ + RCC_EnableAHB5PeriphReset2(RCC_AHB5_PERIPHRST_PWR); +} + +/** +*\*\name PWR_BackupAccessEnable. +*\*\fun Enables or disables access to the RTC and backup registers. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_BackupAccessEnable(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + PWR->SYSCTRL1 |= PWR_DBKPEN; + } + else + { + PWR->SYSCTRL1 &= ~PWR_DBKPEN; + } +} + +/** +*\*\name PWR_PvdEnable. +*\*\fun Enables or disables the Power Voltage Detector(PVD). +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_PvdEnable(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + PWR->SYSCTRL1 |= PWR_PVDEN; + } + else + { + PWR->SYSCTRL1 &= ~PWR_PVDEN; + } +} + +/** +*\*\name PWR_AvdEnable. +*\*\fun Enables or disables the Power Analog Voltage Detector(AVD). +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_AvdEnable(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + PWR->SYSCTRL1 |= PWR_AVDEN; + } + else + { + PWR->SYSCTRL1 &= ~PWR_AVDEN; + } +} + +/** +*\*\name PWR_EnableMRInStandby. +*\*\fun Enables or disables the MR power when the system enters into standby mode . +*\*\param Cmd: +*\*\ - ENABLE : MR is on when system enters into Standby mode. +*\*\ - DISABLE : MR is off when system enters into Standby mode. +*\*\return none +**/ +void PWR_EnableMRInStandby(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + PWR->SYSCTRL2 &= ~PWR_MROFF_IN_STANDBY; + } + else + { + PWR->SYSCTRL2 |= PWR_MROFF_IN_STANDBY; + } +} + + +/** +*\*\name PWR_ConfigDigitalFilterOnNRST. +*\*\fun Config the digital glitch filtered pulse width on NRST . +*\*\param cycle_cnt(The input parameters must be the following values): +*\*\ - 0x000U - 0xFFFU . +*\*\param Cmd: +*\*\ - ENABLE . +*\*\ - DISABLE. +*\*\return none +**/ +void PWR_ConfigDigitalFilterOnNRST(uint32_t cycle_cnt, FunctionalState Cmd) +{ + __IO uint32_t tempreg; + /* Get the old register value */ + tempreg = PWR->SYSCTRL1; + if(Cmd == ENABLE) + { + tempreg &= ~(PWR_NRST_DGF_BP | PWR_NRST_DGF_CNT_MASK); + tempreg |= (cycle_cnt << PWR_NRST_DGF_CNT_BIT_OFFSET); + } + else + { + tempreg |= PWR_NRST_DGF_BP; + } + /* Set new configuration */ + PWR->SYSCTRL1 = tempreg; +} + +/** +*\*\name PWR_EnableBKPLDO. +*\*\fun Enables or disables the backup LDO. +*\*\param Cmd: +*\*\ - ENABLE : Enable the backup LDO. +*\*\ - DISABLE : Disable the backup LDO. +*\*\return none +**/ +void PWR_EnableBKPLDO(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + PWR->SYSCTRL1 |= ~PWR_BKPLDOEN; + } + else + { + PWR->SYSCTRL1 &= PWR_BKPLDOEN; + } +} + + +/** +*\*\name PWR_PVDLevelConfig. +*\*\fun Configures the voltage threshold detected by the Power Voltage Detector(PVD). +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_PVD_LEVEL_2V28 PVD level is 2.28V +*\*\ - PWR_PVD_LEVEL_2V38 PVD level is 2.38V +*\*\ - PWR_PVD_LEVEL_2V48 PVD level is 2.48V +*\*\ - PWR_PVD_LEVEL_2V58 PVD level is 2.58V +*\*\ - PWR_PVD_LEVEL_2V68 PVD level is 2.68V +*\*\ - PWR_PVD_LEVEL_2V78 PVD level is 2.78V +*\*\ - PWR_PVD_LEVEL_2V88 PVD level is 2.88V +*\*\ - PWR_PVD_LEVEL_3V28 PVD level is 3.28V +*\*\ - PWR_PVD_LEVEL_3V38 PVD level is 3.38V +*\*\ - PWR_PVD_LEVEL_3V48 PVD level is 3.48V +*\*\ - PWR_PVD_LEVEL_3V58 PVD level is 3.58V +*\*\return none +**/ +void PWR_PVDLevelConfig(uint32_t level) +{ + uint32_t temp_value; + + temp_value = *(__IO uint32_t *)PVD_ContrlBaseAddress; + /* Clear MSB and PLS[2:0] bits bit */ + temp_value &= PWR_PVD_LEVEL_MASK; + /* Set PLS[3:0] bits according to level value */ + temp_value |= level; + /* Store the new value */ + *(__IO uint32_t *)PVD_ContrlBaseAddress = temp_value; +} + +/** +*\*\name PWR_AVDLevelConfig. +*\*\fun Configure the voltage threshold to be detected by the Analog Power Voltage Detector(AVD). +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_AVD_LEVEL_2V28 AVD level is 2.28V +*\*\ - PWR_AVD_LEVEL_2V38 AVD level is 2.38V +*\*\ - PWR_AVD_LEVEL_2V48 AVD level is 2.48V +*\*\ - PWR_AVD_LEVEL_2V58 AVD level is 2.58V +*\*\ - PWR_AVD_LEVEL_2V68 AVD level is 2.68V +*\*\ - PWR_AVD_LEVEL_2V78 AVD level is 2.78V +*\*\ - PWR_AVD_LEVEL_2V88 AVD level is 2.88V +*\*\ - PWR_AVD_LEVEL_3V28 AVD level is 3.28V +*\*\ - PWR_AVD_LEVEL_3V38 AVD level is 3.38V +*\*\ - PWR_AVD_LEVEL_3V48 AVD level is 3.48V +*\*\ - PWR_AVD_LEVEL_3V58 AVD level is 3.58V +*\*\return none +**/ +void PWR_AVDLevelConfig(uint32_t level) +{ + uint32_t temp_value; + + temp_value = *(__IO uint32_t *)AVD_ContrlBaseAddress; + /* Clear ALS[3:0] bits bit */ + temp_value &= PWR_AVD_LEVEL_MASK; + /* Set ALS[3:0] bits according to level value */ + temp_value |= level; + /* Store the new value */ + *(__IO uint32_t *)AVD_ContrlBaseAddress = temp_value; +} + +/** +*\*\name PWR_VDDDPORLevelConfig. +*\*\fun Configure the voltage Power-on reset (POR) / power-down reset (PDR) of VDDD. +*\*\param mode (The input parameters must be the following values): +*\*\ - SYSTEM_RUN_MODE +*\*\ - SYSTEM_LOW_POWER_MODE +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_VDDD_POR_Level_0V70 POR level is 0.70V, PDR level is 0.65V +*\*\ - PWR_VDDD_POR_Level_0V75 POR level is 0.75V, PDR level is 0.70V +*\*\ - PWR_VDDD_POR_Level_0V80 POR level is 0.80V, PDR level is 0.75V +*\*\return none +**/ +void PWR_VDDDPORLevelConfig(SYSTEM_POWER_TYPE mode, uint32_t level) +{ + __IO uint32_t temp_value; + uint32_t bitoffset ; + + temp_value = PWR->SYSCTRL4; + if(mode == SYSTEM_RUN_MODE) + { + bitoffset = PWR_VDDD_POR_LEVEL_OFFSET; + } + else + { + bitoffset = PWR_VDDD_LPPOR_LEVEL_OFFSET; + } + /* Clear ALS[3:0] bits bit */ + temp_value &= ~(PWR_VDDD_POR_Level_MASK << bitoffset); + /* Set ALS[3:0] bits according to level value */ + temp_value |= (level << bitoffset); + /* Store the new value */ + PWR->SYSCTRL4 = temp_value; +} + +/** +*\*\name PWR_DCDCPORLevelConfig. +*\*\fun Configure the voltage Power-on reset (POR) / power-down reset (PDR) of DCDC. +*\*\param mode (The input parameters must be the following values): +*\*\ - SYSTEM_RUN_MODE +*\*\ - SYSTEM_LOW_POWER_MODE +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_DCDC_POR_Level_0V80 POR level is 0.80V, PDR level is 0.75V +*\*\ - PWR_DCDC_POR_Level_0V85 POR level is 0.85V, PDR level is 0.80V +*\*\ - PWR_DCDC_POR_Level_0V90 POR level is 0.90V, PDR level is 0.85V +*\*\return none +**/ +void PWR_DCDCPORLevelConfig(SYSTEM_POWER_TYPE mode, uint32_t level) +{ + __IO uint32_t* ControlRegAddr; + __IO uint32_t temp_value; + uint32_t bitoffset ; + + if(mode == SYSTEM_RUN_MODE) + { + bitoffset = PWR_DCDC_POR_LEVEL_OFFSET; + temp_value = *(__IO uint32_t *)DCDC_ContrlBaseAddress; + ControlRegAddr = (__IO uint32_t*)DCDC_ContrlBaseAddress; + } + else + { + bitoffset = PWR_DCDC_LPPOR_LEVEL_OFFSET; + ControlRegAddr = &PWR->SYSCTRL4; + temp_value = PWR->SYSCTRL4; + } + /* Clear ALS[3:0] bits bit */ + temp_value &= ~(PWR_DCDC_POR_Level_MASK << bitoffset); + /* Set ALS[3:0] bits according to level value */ + temp_value |= (level << bitoffset); + /* Store the new value */ + *ControlRegAddr = temp_value; +} + +/** +*\*\name PWR_MLDOOutputVoltageConfig. +*\*\fun Configure the voltage output of LDO. +*\*\param mode (The input parameters must be the following values): +*\*\ - SYSTEM_RUN_MODE +*\*\ - SYSTEM_LOW_POWER_MODE +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_0V80 LDO level is 0.80V +*\*\ - PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_0V85 LDO level is 0.85V +*\*\ - PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_0V90 LDO level is 0.90V +*\*\return none +**/ +void PWR_MLDOOutputVoltageConfig(SYSTEM_POWER_TYPE mode, uint32_t level) +{ + __IO uint32_t temp_value; + uint32_t bitoffset ; + /* Get the old register value */ + temp_value = PWR->SYSCTRL4; + if(mode == SYSTEM_RUN_MODE) + { + bitoffset = PWR_MLDO_VOLT_OUTPUT_LEVEL_OFFSET; + } + else + { + bitoffset = PWR_MLDO_LP_VOLT_OUTPUT_LEVEL_OFFSET; + } + /* Clear ALS[3:0] bits bit */ + temp_value &= ~(PWR_MLDO_VOLTAGE_OUTPUT_LEVEL_MASK << bitoffset); + /* Set ALS[3:0] bits according to level value */ + temp_value |= (level << bitoffset); + /* Store the new value */ + PWR->SYSCTRL4 = temp_value; +} + +/** +*\*\name PWR_DCDCOutputVoltageConfig. +*\*\fun Configure the voltage output of DCDC. +*\*\param mode (The input parameters must be the following values): +*\*\ - SYSTEM_RUN_MODE +*\*\ - SYSTEM_LOW_POWER_MODE +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_0V80 DCDC level is 0.80V +*\*\ - PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_0V85 DCDC level is 0.85V +*\*\ - PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_0V90 DCDC level is 0.90V +*\*\return none +**/ +void PWR_DCDCOutputVoltageConfig(SYSTEM_POWER_TYPE mode, uint32_t level) +{ + __IO uint32_t* ControlRegAddr; + __IO uint32_t temp_value; + uint32_t bitoffset ; + + if(mode == SYSTEM_RUN_MODE) + { + bitoffset = PWR_DCDC_VOLT_OUTPUT_LEVEL_OFFSET; + temp_value = *(__IO uint32_t *)DCDC_ContrlBaseAddress; + ControlRegAddr = (__IO uint32_t*)DCDC_ContrlBaseAddress; + } + else + { + bitoffset = PWR_DCDC_LP_VOLT_OUTPUT_LEVEL_OFFSET; + ControlRegAddr = &PWR->SYSCTRL4; + temp_value = PWR->SYSCTRL4; + } + /* Clear ALS[3:0] bits bit */ + temp_value &= ~(PWR_DCDC_VOLTAGE_OUTPUT_LEVEL_MASK << bitoffset); + /* Set ALS[3:0] bits according to level value */ + temp_value |= (level << bitoffset); + /* Store the new value */ + *ControlRegAddr = temp_value; +} + +/** +*\*\name PWR_BKPLDOOutputVoltageConfig. +*\*\fun Configure the voltage output of BKPLDO. +*\*\param mode (The input parameters must be the following values): +*\*\ - SYSTEM_RUN_MODE +*\*\ - SYSTEM_LOW_POWER_MODE +*\*\param level (The input parameters must be the following values): +*\*\ - PWR_BKPLDO_VOLTAGE_OUTPUT_LEVEL_0V80 BKPLDO level is 0.80V +*\*\ - PWR_BKPLDO_VOLTAGE_OUTPUT_LEVEL_0V90 BKPLDO level is 0.90V +*\*\return none +**/ +void PWR_BKPLDOOutputVoltageConfig(SYSTEM_POWER_TYPE mode, uint32_t level) +{ + __IO uint32_t temp_value; + uint32_t bitoffset ; + /* Get the old register value */ + temp_value = PWR->SYSCTRL4; + if(mode == SYSTEM_RUN_MODE) + { + bitoffset = PWR_BKPLDO_VOLT_OUTPUT_LEVEL_OFFSET; + } + else + { + bitoffset = PWR_BKPLDO_LP_VOLT_OUTPUT_LEVEL_OFFSET; + } + /* Clear bits bit */ + temp_value &= ~(PWR_BKPLDO_VOLTAGE_OUTPUT_LEVEL_MASK << bitoffset); + /* Set bits according to level value */ + temp_value |= (level << bitoffset); + /* Store the new value */ + PWR->SYSCTRL4 = temp_value; +} + +/** +*\*\name PWR_EnableLPMRVoltageOutput. +*\*\fun Enables or disables the Voltage scaling of MR in Low power mode. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_EnableLPMRVoltageOutput(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + PWR->SYSCTRL4 |= PWR_MR_LPVSELEN; + } + else + { + PWR->SYSCTRL4 &= ~PWR_MR_LPVSELEN; + } +} +/** +*\*\name PWR_EnableOPTC_LPMode. +*\*\fun Configure the OPTC PWR Mode. +*\*\param ChipStatus (The input parameters must be the following values): +*\*\ - PWR_SYSTEM_RUN +*\*\ - PWR_SYSTEM_STOP0 +*\*\ - PWR_SYSTEM_STOP2 +*\*\param OPTC_Mode : +*\*\ - OPTC_POWER_ENTER_STANDBY_MODE +*\*\ - OPTC_POWER_ENTER_DEEPSTANDBY_MODE +*\*\ - OPTC_POWER_ENTER_RUN_MODE +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_EnableOPTC_LPMode(SYSTEM_OPTC_STATUS ChipStatus, uint32_t OPTC_Mode, FunctionalState Cmd) +{ + __IO uint32_t tempreg; + /* Get the old register value */ + tempreg = PWR->SYSCTRL2; + if(Cmd == ENABLE) + { + if(ChipStatus == PWR_SYSTEM_RUN) + { + /* Clear the old value */ + tempreg &= (~(OPTC_POWER_ENTER_MODE_MASK<<22U)); + /* Set the new values */ + tempreg |= (OPTC_Mode << 22U); + } + else if(ChipStatus == PWR_SYSTEM_STOP0) + { + /* Clear the old value */ + tempreg &= (~(OPTC_POWER_ENTER_MODE_MASK<<20U)); + /* Set the new values */ + tempreg |= (OPTC_Mode << 20U); + } + else + { + /* Clear the old value */ + tempreg &= (~(OPTC_POWER_ENTER_MODE_MASK<<18U)); + /* Set the new values */ + tempreg |= (OPTC_Mode << 18U); + } + } + else + { + if(ChipStatus == PWR_SYSTEM_RUN) + { + /* Clear the old value */ + tempreg &= (~(OPTC_POWER_ENTER_MODE_MASK<<22U)); + } + else if(ChipStatus == PWR_SYSTEM_STOP0) + { + /* Clear the old value */ + tempreg &= (~(OPTC_POWER_ENTER_MODE_MASK<<20U)); + } + else + { + /* Clear the old value */ + tempreg &= (~(OPTC_POWER_ENTER_MODE_MASK<<18U)); + } + } + /* Set the power supply configuration */ + PWR->SYSCTRL2 = tempreg; +} + +/** +*\*\name PWR_EnableTCMPiece. +*\*\fun Enable the TCM Piece PWR. +*\*\param PieceIndex (The input parameters must be the following values): +*\*\ - 0-63 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_EnableTCMPiece(uint32_t PieceIndex, FunctionalState Cmd) +{ + __IO uint32_t* ControlRegAddr; + __IO uint32_t* ReadyRegAddr; + if(Cmd == ENABLE) + { + if(PieceIndex < 32U ) + { + ReadyRegAddr = &PWR->M7TCMPRDY0; + if(*ReadyRegAddr & (1U<< PieceIndex)) + { + return; + } + ControlRegAddr = &PWR->M7TCMPG0; + } + else + { + PieceIndex = PieceIndex - 32U; + ReadyRegAddr = &PWR->M7TCMPRDY1; + if(*ReadyRegAddr & (1UL<< PieceIndex)) + { + return; + } + ControlRegAddr = &PWR->M7TCMPG1; + } + /* Enable TCM Piece Bit */ + *ControlRegAddr &= ~(1UL<< PieceIndex); + /* Wait TCM Piece Power on Ready */ + while((*ReadyRegAddr & (1UL<< PieceIndex)) != (1UL<< PieceIndex)); + } + else + { + if(PieceIndex < 32U ) + { + ReadyRegAddr = &PWR->M7TCMPRDY0; + if((*ReadyRegAddr & (1UL<< PieceIndex)) == RESET ) + { + return; + } + ControlRegAddr = &PWR->M7TCMPG0; + } + else + { + PieceIndex = PieceIndex-32U; + ReadyRegAddr = &PWR->M7TCMPRDY1; + if((*ReadyRegAddr & (1UL<< PieceIndex)) == RESET ) + { + return; + } + ControlRegAddr = &PWR->M7TCMPG1; + } + /* Disable TCM Piece Bit */ + *ControlRegAddr |= (1UL<< PieceIndex); + /* Wait TCM Piece Power down Ready */ + while((*ReadyRegAddr & (1UL<< PieceIndex)) == (1UL<< PieceIndex)) ; + } +} +/** +*\*\name PWR_TCMModeSelInSTOP2. +*\*\fun Config TCM memory the low power mode when the system enter into STOP2 Enable the. +*\*\param PieceIndex (The input parameters must be the following values): +*\*\ - 0-63 +*\*\param Mode : +*\*\ - SYSTEM_MEMORY_STATUS_PD +*\*\ - SYSTEM_MEMORY_STATUS_RETENTION_1 +*\*\ - SYSTEM_MEMORY_STATUS_RETENTION_2 +*\*\return none +**/ +void PWR_TCMModeSelInSTOP2(uint32_t PieceIndex, uint32_t Mode) +{ + __IO uint32_t* ControlRegAddrLow; + __IO uint32_t* ControlRegAddrHigh; + if(PieceIndex < 32U ) + { + ControlRegAddrLow = &PWR->M7TCMRET1N0; + ControlRegAddrHigh = &PWR->M7TCMRET2N0; + } + else + { + PieceIndex = PieceIndex - 32U; + ControlRegAddrLow = &PWR->M7TCMRET1N1; + ControlRegAddrHigh = &PWR->M7TCMRET2N1; + } + if(Mode == SYSTEM_MEMORY_STATUS_PD) + { + /* Set [M7TCMRET2Nx M7TCMRET1Nx] = [00]*/ + *ControlRegAddrLow &= ~(1UL<< PieceIndex); + *ControlRegAddrHigh &= ~(1UL<< PieceIndex); + } + else if(Mode == SYSTEM_MEMORY_STATUS_RETENTION_1) + { + /* Set [M7TCMRET2Nx M7TCMRET1Nx] = [11]*/ + *ControlRegAddrLow |= (1UL<< PieceIndex); + *ControlRegAddrHigh |= (1UL<< PieceIndex); + } + else if(Mode == SYSTEM_MEMORY_STATUS_RETENTION_2) + { + /* Set [M7TCMRET2Nx M7TCMRET1Nx] = [10]*/ + *ControlRegAddrLow &= ~(1UL<< PieceIndex); + *ControlRegAddrHigh |= (1UL<< PieceIndex); + } + else + { + /* no process*/ + } +} +/** +*\*\name PWR_SystemMemoryModeSelInSTOP2. +*\*\fun Config system memory the low power mode when the system enter into STOP2. +*\*\param SysMemoryType (The input parameters must be the following values): +*\*\ - SYSTEM_MEMORY_AXISRAM +*\*\ - SYSTEM_MEMORY_AHBSRAM1 +*\*\ - SYSTEM_MEMORY_AHBSRAM2 +*\*\ - SYSTEM_MEMORY_AHBSRAM3 +*\*\ - SYSTEM_MEMORY_AHBSRAM4 +*\*\ - SYSTEM_MEMORY_AHBSRAM5S1 +*\*\ - SYSTEM_MEMORY_AHBSRAM5S2 +*\*\param Mode : +*\*\ - SYSTEM_MEMORY_STATUS_PD +*\*\ - SYSTEM_MEMORY_STATUS_RETENTION_1 +*\*\ - SYSTEM_MEMORY_STATUS_RETENTION_2 +*\*\return none +**/ +void PWR_SystemMemoryModeSelInSTOP2(SYSTEM_MEMORY_TYPE SysMemoryType, uint32_t Mode) +{ + __IO uint32_t tempreg; + uint32_t bitoffset ; + + bitoffset = SYSTEM_MEMORY_AXISRAM_BITOFFSET; + bitoffset += 2u*((uint32_t)SysMemoryType); + + /* Get the old register value */ + tempreg = PWR->SYSMEMLPCTRL; + /* Clear the old value */ + tempreg &= (~(SYSTEM_MEMORY_STATUS_MASK<< bitoffset)); + /* Set the new values */ + tempreg |= (Mode << bitoffset); + /* Store the new values */ + PWR->SYSMEMLPCTRL = tempreg; +} + +/** +*\*\name PWR_SystemMemoryModeSelInSTOP0. +*\*\fun Config system memory the low power mode when the system enter into STOP0. +*\*\param Mode (The input parameters must be the following values): +*\*\ - ALL_SYSTEM_MEMORY_STATUS_CHIP_DISABLE +*\*\ - ALL_SYSTEM_MEMORY_STATUS_PRECHARGE +*\*\ - ALL_SYSTEM_MEMORY_STATUS_RETENTION_1 +*\*\return none +**/ +void PWR_SystemMemoryModeSelInSTOP0(uint32_t Mode) +{ + __IO uint32_t tempreg; + + /* Get the old register value */ + tempreg = PWR->SYSMEMLPCTRL; + /* Clear the old value */ + tempreg &= (~ALL_SYSTEM_MEMORY_STATUS_MASK); + /* Set the new values */ + tempreg |= Mode; + /* Store the new values */ + PWR->SYSMEMLPCTRL = tempreg; +} + +/** +*\*\name PWR_EnableSystemMemory. +*\*\fun Enable or disable system memory power when the system in SYSTEM_RUN mode. +*\*\param SysMemoryType (The input parameters must be the following values): +*\*\ - SYSTEM_MEMORY_AXISRAM +*\*\ - SYSTEM_MEMORY_AHBSRAM1 +*\*\ - SYSTEM_MEMORY_AHBSRAM2 +*\*\ - SYSTEM_MEMORY_AHBSRAM3 +*\*\ - SYSTEM_MEMORY_AHBSRAM4 +*\*\ - SYSTEM_MEMORY_AHBSRAM5S1 +*\*\ - SYSTEM_MEMORY_AHBSRAM5S2 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_EnableSystemMemory(SYSTEM_MEMORY_TYPE SysMemoryType, FunctionalState Cmd) +{ + uint8_t bitoffset ; + + bitoffset = (uint8_t)SysMemoryType; + if(Cmd == ENABLE) + { + /* Enable system memory power */ + PWR->SYSMEMLPCTRL &= (~((uint32_t)0x01u << bitoffset)); + } + else + { + /* Disable system memory power */ + PWR->SYSMEMLPCTRL |= ((uint32_t)0x01u << bitoffset); + } +} +/** +*\*\name PWR_HSC1_HSC2_GRAPHIC_DomainEnable. +*\*\fun Enables or disables HSC1/HSC2/Grpahic Domain power. +*\*\param DOMAIN_Type: +*\*\ - HSC1_Domain +*\*\ - HSC2_Domain +*\*\ - GRAPHIC_Domain +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +static void PWR_HSC1_HSC2_GRAPHIC_DomainEnable(DOMAIN_Type DomainType, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /*Select the switcher mode */ + PWR->SYSCTRL3 |= (PWR_SYSCTRL3_GRC_PSWACK1<< DomainType); + /*Enable the domain power */ + PWR->SYSCTRL3 |= (PWR_SYSCTRL3_GRC_PWREN<< DomainType); + /*wait power on ready flag */ + while( (PWR->SYSCTRL3& (PWR_SYSCTRL3_GRC_PWRRDY<< DomainType)) != (PWR_SYSCTRL3_GRC_PWRRDY<< DomainType)); + /*Set domain out of reset state*/ + PWR->SYSCTRL3 |= (PWR_SYSCTRL3_GRC_FUCEN<< DomainType); + /* remove isolation on domain output signals*/ + PWR->SYSCTRL3 |= (PWR_SYSCTRL3_GRC_ISNEN<< DomainType); + } + else + { + /* Apply isolation on domain domain output signals*/ + PWR->SYSCTRL3 &= ~(PWR_SYSCTRL3_GRC_ISNEN<< DomainType); + /*Set domain domain reset state*/ + PWR->SYSCTRL3 &= ~(PWR_SYSCTRL3_GRC_FUCEN<< DomainType); + /*Disable the domain power */ + PWR->SYSCTRL3 &= ~(PWR_SYSCTRL3_GRC_PWREN<< DomainType); + + /*wait the power down ready flag */ + while((PWR->SYSCTRL3& (PWR_SYSCTRL3_GRC_PWRRDY<< DomainType)) == (PWR_SYSCTRL3_GRC_PWRRDY<< DomainType)); + } +} + + +/** +*\*\name PWR_ESC_DomainEnable. +*\*\fun Enables or disables ESC Domain power. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +static void PWR_ESC_DomainEnable(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /*Select the switcher mode */ + PWR->ESCCTRL |= (ESC_PSWACK1); + /*Enable the ESC power */ + PWR->ESCCTRL |= (ESC_POWER_ENABLE); + /*wait power on ready flag */ + while((PWR->ESCCTRL& (ESC_POWER_RDY)) != ESC_POWER_RDY); + /*Set ESC out of reset state*/ + PWR->ESCCTRL |= (ESC_FUNCTION_ENABLE); + /* remove isolation on ESC output signals*/ + PWR->ESCCTRL |= (ESC_ISOLATION_ENABLE); + } + else + { + /* Apply isolation on ESC output signals*/ + PWR->ESCCTRL &= ~(ESC_ISOLATION_ENABLE); + /*Set ESC reset state*/ + PWR->ESCCTRL &= ~(ESC_FUNCTION_ENABLE); + /*Disable the ESC power */ + PWR->ESCCTRL &= ~(ESC_POWER_ENABLE); + + /*wait the power down ready flag */ + while((PWR->ESCCTRL& ESC_POWER_RDY) == ESC_POWER_RDY); + } +} + +/** +*\*\name PWR_MDMA_DomainEnable. +*\*\fun Enables or disables MDMA power. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_MDMA_DomainEnable(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /*Select the switcher mode */ + PWR->MDMACTRL |= (MDMA_PSWACK1); + /*Enable the MDMA power */ + PWR->MDMACTRL |= (MDMA_POWER_ENABLE); + /*wait power on ready flag */ + while((PWR->MDMACTRL& (MDMA_POWER_RDY)) != MDMA_POWER_RDY); + /*Set MDMA out of reset state*/ + PWR->MDMACTRL |= (MDMA_FUNCTION_ENABLE); + /* remove isolation on MDMA output signals*/ + PWR->MDMACTRL |= (MDMA_ISOLATION_ENABLE); + } + else + { + /* Apply isolation on MDMA output signals*/ + PWR->MDMACTRL &= ~(MDMA_ISOLATION_ENABLE); + /*Set MDMA reset state*/ + PWR->MDMACTRL &= ~(MDMA_FUNCTION_ENABLE); + /*Disable the MDMA power */ + PWR->MDMACTRL &= ~(MDMA_POWER_ENABLE); + + /*wait the power down ready flag */ + while((PWR->MDMACTRL& MDMA_POWER_RDY) == MDMA_POWER_RDY); + } +} + +/** +*\*\name PWR_SHRTIM_DomainEnable. +*\*\fun Enables or disables shrtimx power. +*\*\param shrtimx : +*\*\ - Power_SHRTIM1 +*\*\ - Power_SHRTIM2 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_SHRTIM_DomainEnable(SHRTIM_PowerType shrtimx, FunctionalState Cmd) //test +{ + if(Cmd == ENABLE) + { + if((PWR->SHRTIMCTRL& SHRTIMA_POWER_RDY) != SHRTIMA_POWER_RDY) + { + /*Power on SHRTIM AFE First */ + /*Select the switcher mode */ + PWR->SHRTIMCTRL |= (SHRTIMA_PSWACK1); + /*Enable the SHRTIM AFE power */ + PWR->SHRTIMCTRL |= (SHRTIMA_POWER_ENABLE); + /*wait power on ready flag */ + while((PWR->SHRTIMCTRL& SHRTIMA_POWER_RDY) != SHRTIMA_POWER_RDY); + /*Set SHRTIM AFE out of reset state*/ + PWR->SHRTIMCTRL |= (SHRTIMA_FUNCTION_ENABLE); + /* remove isolation on SHRTIM AFE output signals*/ + PWR->SHRTIMCTRL |= (SHRTIMA_ISOLATION_ENABLE); + } + else + { + /*no process*/ + } + + /*Then power on SHRTIM1 or SHRTIM2 */ + /*Select the switcher mode */ + PWR->SHRTIMCTRL |= (SHRTIM1_PSWACK1<<(8U*(uint32_t)shrtimx)); + /*Enable the SHRTIM AFE power */ + PWR->SHRTIMCTRL |= (SHRTIM1_POWER_ENABLE<<(8U*(uint32_t)shrtimx)); + /*wait power on ready flag */ + while((PWR->SHRTIMCTRL& (SHRTIM1_POWER_RDY<<(8U*(uint32_t)shrtimx))) != (SHRTIM1_POWER_RDY<< (8U*(uint32_t)shrtimx))); + /*Set SHRTIM AFE out of reset state*/ + PWR->SHRTIMCTRL |= (SHRTIM1_FUNCTION_ENABLE<<(8U*(uint32_t)shrtimx)); + /* remove isolation on SHRTIM AFE output signals*/ + PWR->SHRTIMCTRL |= (SHRTIM1_ISOLATION_ENABLE<<(8U*(uint32_t)shrtimx)); + } + else + { + /*Power off SHRTIM1 or SHRTIM2 First */ + /* Apply isolation on SHRTIM AFE output signals*/ + PWR->SHRTIMCTRL &= ~(SHRTIM1_ISOLATION_ENABLE<<(8U*(uint32_t)shrtimx)); + /*Set SHRTIM AFE reset state*/ + PWR->SHRTIMCTRL &= ~(SHRTIM1_FUNCTION_ENABLE<<(8U*(uint32_t)shrtimx)); + /*Disable the SHRTIM AFE power */ + PWR->SHRTIMCTRL &= ~(SHRTIM1_POWER_ENABLE<<(8U*(uint32_t)shrtimx)); + + /*wait the power down ready flag */ + while((PWR->SHRTIMCTRL& (SHRTIM1_POWER_RDY<<(8U*(uint32_t)shrtimx))) == (SHRTIM1_POWER_RDY<<(8U*(uint32_t)shrtimx))); + + /*if Both SHRTIM1 and SHRTIM2 off, then power off SHRTIM AFE */ + if( (((PWR->SHRTIMCTRL&SHRTIM2_POWER_RDY) != SHRTIM2_POWER_RDY )&&(shrtimx == Power_SHRTIM1)) + ||(((PWR->SHRTIMCTRL&SHRTIM1_POWER_RDY) != SHRTIM1_POWER_RDY )&&(shrtimx == Power_SHRTIM2)) ) + { + /* Apply isolation on SHRTIM AFE output signals*/ + PWR->SHRTIMCTRL &= ~(SHRTIMA_ISOLATION_ENABLE); + /*Set SHRTIM AFE reset state*/ + PWR->SHRTIMCTRL &= ~(SHRTIMA_FUNCTION_ENABLE); + /*Disable the SHRTIM AFE power */ + PWR->SHRTIMCTRL &= ~(SHRTIMA_POWER_ENABLE); + + /*wait the power down ready flag */ + while((PWR->SHRTIMCTRL& SHRTIMA_POWER_RDY) == SHRTIMA_POWER_RDY); + } + else + { + /*no process*/ + } + } +} + +/** +*\*\name PWR_MoudlePowerEnable. +*\*\fun Enables or disables the specified module power. +*\*\param module : +*\*\ - GRAPHIC_GPU_PWRCTRL +*\*\ - GRAPHIC_LCDC_PWRCTRL +*\*\ - GRAPHIC_JPEG_PWRCTRL +*\*\ - GRAPHIC_DSI_PWRCTRL +*\*\ - GRAPHIC_DVP_PWRCTRL +*\*\ - HSC2_ETH2_PWRCTRL +*\*\ - HSC2_USB2_PWRCTRL +*\*\ - HSC2_SDMMC2_PWRCTRL +*\*\ - HSC1_ETH1_PWRCTRL +*\*\ - HSC1_USB1_PWRCTRL +*\*\ - HSC1_SDMMC1_PWRCTRL +*\*\ - FMAC_PWRCTRL +*\*\ - ESC_PWRCTRL +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_MoudlePowerEnable(uint32_t module, FunctionalState Cmd) +{ + if( (module == GRAPHIC_GPU_PWRCTRL) ||(module == GRAPHIC_LCDC_PWRCTRL)|| \ + (module == GRAPHIC_JPEG_PWRCTRL)||(module == GRAPHIC_DSI_PWRCTRL) || (module == GRAPHIC_DVP_PWRCTRL)) + { + if(Cmd == ENABLE) + { + PWR->IPMEMCTRL &= (~module); + while((PWR->IPMEMCTRLSTS & module ) != module); + if( (PWR->SYSCTRL3&PWR_SYSCTRL3_GRC_PWRRDY) != PWR_SYSCTRL3_GRC_PWRRDY) + { + PWR_HSC1_HSC2_GRAPHIC_DomainEnable(GRAPHIC_Domain, ENABLE); + } + else + { + /*no process*/ + } + } + else + { + if((PWR->IPMEMCTRLSTS&GRAPHIC_MODULE_MASK) == module) + { + PWR_HSC1_HSC2_GRAPHIC_DomainEnable(GRAPHIC_Domain, DISABLE); + } + else + { + /*no process*/ + } + PWR->IPMEMCTRL |= module; + while((PWR->IPMEMCTRLSTS & module ) == module); + } + } + else if((module == HSC2_ETH2_PWRCTRL) ||(module == HSC2_USB2_PWRCTRL)||(module == HSC2_SDMMC2_PWRCTRL)) + { + if(Cmd == ENABLE) + { + PWR->IPMEMCTRL &= (~module); + while((PWR->IPMEMCTRLSTS & module ) != module); + if( (PWR->SYSCTRL3&PWR_SYSCTRL3_HSC2_PWRRDY) != PWR_SYSCTRL3_HSC2_PWRRDY) + { + PWR_HSC1_HSC2_GRAPHIC_DomainEnable(HSC2_Domain, ENABLE); + } + else + { + /*no process*/ + } + } + else + { + if((PWR->IPMEMCTRLSTS&HSC2_MODULE_MASK) == module) + { + PWR_HSC1_HSC2_GRAPHIC_DomainEnable(HSC2_Domain, DISABLE); + } + else + { + /*no process*/ + } + PWR->IPMEMCTRL |= module; + while((PWR->IPMEMCTRLSTS & module ) == module); + } + } + else if((module == HSC1_ETH1_PWRCTRL) ||(module == HSC1_USB1_PWRCTRL)||(module == HSC1_SDMMC1_PWRCTRL)) + { + if(Cmd == ENABLE) + { + PWR->IPMEMCTRL &= (~module); + while((PWR->IPMEMCTRLSTS & module ) != module); + if( (PWR->SYSCTRL3&PWR_SYSCTRL3_HSC1_PWRRDY) != PWR_SYSCTRL3_HSC1_PWRRDY) + { + PWR_HSC1_HSC2_GRAPHIC_DomainEnable(HSC1_Domain, ENABLE); + } + else + { + /*no process*/ + } + } + else + { + if((PWR->IPMEMCTRLSTS&HSC1_MODULE_MASK) == module) + { + PWR_HSC1_HSC2_GRAPHIC_DomainEnable(HSC1_Domain, DISABLE); + } + else + { + /*no process*/ + } + PWR->IPMEMCTRL |= module; + while((PWR->IPMEMCTRLSTS & module ) == module); + } + } + else if(module == ESC_PWRCTRL) + { + if(Cmd == ENABLE) + { + PWR->IPMEMCTRL &= (~ESC_PWRCTRL); + while((PWR->IPMEMCTRLSTS & ESC_PWRRDY_FLAG ) != ESC_PWRRDY_FLAG); + PWR_ESC_DomainEnable(ENABLE); + } + else + { + PWR_ESC_DomainEnable(DISABLE); + PWR->IPMEMCTRL |= ESC_PWRCTRL; + while((PWR->IPMEMCTRLSTS & ESC_PWRRDY_FLAG) == ESC_PWRRDY_FLAG); + } + } + else if(module == FMAC_PWRCTRL) + { + if(Cmd == ENABLE) + { + PWR->IPMEMCTRL &= (~FMAC_PWRCTRL); + while((PWR->IPMEMCTRLSTS & FMAC_PWRRDY_FLAG ) != FMAC_PWRRDY_FLAG); + } + else + { + PWR->IPMEMCTRL |= FMAC_PWRCTRL; + while((PWR->IPMEMCTRLSTS & FMAC_PWRRDY_FLAG) == FMAC_PWRRDY_FLAG); + } + } + else + { + /*no process */ + } +} + +/** +*\*\name PWR_EnableBKPSRAMRetainInStandbyMode. +*\*\fun Enable or disable BKP SRAM retain in standby mode. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void PWR_EnableBKPSRAMRetainInStandbyMode(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /* Set BSRSTBRET bit */ + //*ControlRegAddr |= PWR_STBRET_ENABLE; + PWR->M4CTRL2 |= PWR_STBRET_ENABLE; + PWR->M7CTRL2 |= PWR_STBRET_ENABLE; + } + else + { + /* Reset BSRSTBRET bit */ + //*ControlRegAddr &= (~PWR_STBRET_ENABLE); + PWR->M4CTRL2 &= (~PWR_STBRET_ENABLE); + PWR->M7CTRL2 &= (~PWR_STBRET_ENABLE); + } +} + + +/** +*\*\name PWR_EnableBKPSRAMRetainInVbatMode. +*\*\fun Enable or disable BKP SRAM retain in Vbat mode. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void PWR_EnableBKPSRAMRetainInVbatMode(FunctionalState Cmd) +{ + __IO uint32_t* ControlRegAddr; + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRL2; + } + else + { + ControlRegAddr = &PWR->M4CTRL2; + } + if(Cmd == ENABLE) + { + /* Set BSRVBRET bit */ + *ControlRegAddr |= PWR_VBATRET_ENABLE; + } + else + { + /* Reset BSRVBRET bit */ + *ControlRegAddr &= (~PWR_VBATRET_ENABLE); + } +} + +/** +*\*\name PWR_WakeUpPinEnable. +*\*\fun Enables the Wakeup Pin functionality. +*\*\param pin (The input parameters must be the following values): +*\*\ - WAKEUP_PIN0EN WKUP0(PA0) +*\*\ - WAKEUP_PIN1EN WKUP1(PA2) +*\*\ - WAKEUP_PIN2EN WKUP2(PC13) +*\*\ - WAKEUP_PIN3EN WKUP3(PI8) +*\*\ - WAKEUP_PIN4EN WKUP4(PI11) +*\*\ - WAKEUP_PIN5EN WKUP5(PC1) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_WakeUpPinEnable(uint32_t pin, FunctionalState Cmd) +{ + __IO uint32_t* ControlRegAddr; + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRLSTS; + } + else + { + ControlRegAddr = &PWR->M4CTRLSTS; + } + + if(Cmd == ENABLE) + { + /* Set WKUPxEN bit */ + *ControlRegAddr |= pin; + } + else + { + /* Clear WKUPxEN bit*/ + *ControlRegAddr &= (~pin); + } +} + +/** +*\*\name PWR_WakeUpPinPolarity. +*\*\fun Enables the Wakeup Pin polarity. +*\*\param pin (The input parameters must be the following values): +*\*\ - WAKEUP_PIN0POL WKUP0(PA0) +*\*\ - WAKEUP_PIN1POL WKUP1(PA2) +*\*\ - WAKEUP_PIN2POL WKUP2(PC13) +*\*\ - WAKEUP_PIN3POL WKUP3(PI8) +*\*\ - WAKEUP_PIN4POL WKUP4(PI11) +*\*\ - WAKEUP_PIN5POL WKUP5(PC1) +*\*\param polarity (The input parameters must be the following values): +*\*\ - POL_HIGH +*\*\ - POL_LOW +*\*\return none +**/ +void PWR_WakeUpPinPolarity(uint32_t pin, WAKEUP_PIN_POL polarity) +{ + __IO uint32_t* ControlRegAddr; + + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRLSTS; + } + else + { + ControlRegAddr = &PWR->M4CTRLSTS; + } + + if(polarity == POL_LOW) + { + /* Set WKUPxPOL bit */ + *ControlRegAddr |= pin; + } + else + { + /* Clear WKUPxPOL bit*/ + *ControlRegAddr &= (~pin); + } +} + + +/** +*\*\name PWR_GetFlagStatus. +*\*\fun Checks whether the specified PWR flag is set or not. +*\*\param PWR_FLAG (specifies the flag to check): +*\*\ This parameter can be one of the following values: +*\*\ - PWR_FLAG_WKUP0 PA0 Wake Up flag +*\*\ - PWR_FLAG_WKUP1 PA2 Wake Up flag +*\*\ - PWR_FLAG_WKUP2 PC13 Wake Up flag +*\*\ - PWR_FLAG_WKUP3 PI8 Wake Up flag +*\*\ - PWR_FLAG_WKUP4 PI11 Wake Up flag +*\*\ - PWR_FLAG_WKUP5 PC1 Wake Up flag +*\*\ - PWR_FLAG_WKUPP RTC Wake Up flag +*\*\ - PWR_FLAG_STANDBY StandBy mode flag +*\*\ - PWR_FLAG_VBAT VBAT mode flag +*\*\return The new state of PWR_FLAG +*\*\ - SET +*\*\ - RESET + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus; + __IO uint32_t* ControlRegAddr; + + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRLSTS; + } + else + { + ControlRegAddr = &PWR->M4CTRLSTS; + } + /* Check the parameters */ + if (((*ControlRegAddr) & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +*\*\name PWR_GetSystemFlagStatus. +*\*\fun Checks whether the specified System PWR flag is set or not. +*\*\param PWR_FLAG (specifies the flag to check): +*\*\ This parameter can be one of the following values: +*\*\ - PWR_SYSFLAG_PVDO +*\*\ - PWR_SYSFLAG_AVDO +*\*\ - PWR_SYSFLAG_OTPRDY +*\*\ - PWR_FLAG_DCDCBP +*\*\return The new state of PWR_FLAG +*\*\ - SET +*\*\ - RESET + */ +FlagStatus PWR_GetSystemFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus; + + /* Check the parameters */ + if ((PWR->SYSCTRLSTS & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} +/** +*\*\name PWR_ClearFlag. +*\*\fun Clears the PWR's pending flags. +*\*\param PWR_FLAG (specifies the flag to clear): +*\*\ This parameter can be one of the following values: +*\*\ - PWR_CLR_WKUPx PA0/PA2/PC13/PI8/PI11/PC1/RTC Wake Up flag +*\*\ - PWR_CLR_STANDBY StandBy mode flag +*\*\ - PWR_CLR_VBAT VBAT mode flag +*\*\return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + __IO uint32_t* ControlRegAddr; + + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRL1; + } + else + { + ControlRegAddr = &PWR->M4CTRL1; + } + /* Clear PWR_CLR_WKUPx or PWR_CLR_STANDBY PWR_CLR_VBAT bit */ + *ControlRegAddr |= PWR_FLAG; +} + + +/** +*\*\name PWR_WakeUpRTCEnable. +*\*\fun Enables the Wakeup RTC functionality. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_WakeUpRTCEnable(FunctionalState Cmd) +{ + __IO uint32_t* ControlRegAddr; + + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRL2; + } + else + { + ControlRegAddr = &PWR->M4CTRL2; + } + if(Cmd == ENABLE) + { + *ControlRegAddr |= WAKEUP_RTCEN; + } + else + { + *ControlRegAddr &= ~WAKEUP_RTCEN; + } +} + +/** +*\*\name PWR_WakeUpNRSTEnable. +*\*\fun Enable or Disable NRST Wakeup functionality in standby mode. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void PWR_WakeUpNRSTEnable(FunctionalState Cmd) +{ + __IO uint32_t* ControlRegAddr; + + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRL2; + } + else + { + ControlRegAddr = &PWR->M4CTRL2; + } + if(Cmd == ENABLE) + { + *ControlRegAddr |= WAKEUP_NRSTEN; + } + else + { + *ControlRegAddr &= ~WAKEUP_NRSTEN; + } +} + + +/** +*\*\name PWR_EnterSLEEPMode. +*\*\fun System Enters SLEEP mode. +*\*\param SLEEPONEXIT (The input parameters must be the following values): +*\*\ - PWR_SLEEP_ON_EXIT +*\*\ - PWR_SLEEP_NOW +*\*\param PWR_STOPEntry (The input parameters must be the following values): +*\*\ - PWR_SLEEPENTRY_WFI enter SLEEP mode with WFI instruction +*\*\ - PWR_SLEEPENTRY_WFE enter SLEEP mode with WFE instruction +*\*\return none +**/ +void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry) +{ + __IO uint32_t* ControlRegAddr; + + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr = &PWR->M7CTRL2; + } + else + { + ControlRegAddr = &PWR->M4CTRL2; + } + /* Clear STOP2S bits */ + *ControlRegAddr &= ~PWR_STOP2EN; + + /* CLEAR SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP); + + /* Select SLEEPONEXIT mode entry ------------------------------------------*/ + if(SLEEPONEXIT == 1) + { + /* the MCU enters Sleep mode as soon as it exits the lowest priority ISR */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT; + } + else if(SLEEPONEXIT == 0) + { + /* Sleep-now */ + SCB->SCR &= (uint32_t)(~(uint32_t)SCB_SCR_SLEEPONEXIT); + } + else + { + /* no process */ + } + + /* Select SLEEP mode entry ------------------------------------------------*/ + if(PWR_SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + +/** +*\*\name PWR_EnterSTOP0Mode. +*\*\fun System Enters STOP0 mode. +*\*\param PWR_STOPEntry (The input parameters must be the following values): +*\*\ - PWR_STOPENTRY_WFI enter STOP mode with WFI instruction +*\*\ - PWR_STOPENTRY_WFE enter STOP mode with WFE instruction +*\*\return none +**/ +void PWR_EnterSTOP0Mode(uint8_t PWR_STOPEntry) +{ + __IO uint32_t* ControlRegAddr1; + __IO uint32_t* ControlRegAddr2; + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr1 = &PWR->M7CTRL1; + ControlRegAddr2 = &PWR->M7CTRL2; + } + else + { + ControlRegAddr1 = &PWR->M4CTRL1; + ControlRegAddr2 = &PWR->M4CTRL2; + } + /* Clear PDDS */ + *ControlRegAddr1 &= ~PWR_PDSEN; + /* Clear STOP2S bits */ + *ControlRegAddr2 &= ~PWR_STOP2EN; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry -----------------------------*/ + if (PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)(~(uint32_t)SCB_SCR_SLEEPDEEP); +} + + +/** +*\*\name PWR_EnterSTOP2Mode. +*\*\fun System Enters STOP2 mode. +*\*\param PWR_STOPEntry (The input parameters must be the following values): +*\*\ - PWR_STOPENTRY_WFI enter STOP mode with WFI instruction +*\*\ - PWR_STOPENTRY_WFE enter STOP mode with WFE instruction +*\*\return none +**/ +void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry) +{ + __IO uint32_t* ControlRegAddr1; + __IO uint32_t* ControlRegAddr2; + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr1 = &PWR->M7CTRL1; + ControlRegAddr2 = &PWR->M7CTRL2; + } + else + { + ControlRegAddr1 = &PWR->M4CTRL1; + ControlRegAddr2 = &PWR->M4CTRL2; + } + /* Clear PDDS */ + *ControlRegAddr1 &= ~PWR_PDSEN; + /* Clear STOP2S bits */ + *ControlRegAddr2 |= PWR_STOP2EN; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry -----------------------------*/ + if (PWR_STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)(~(uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** +*\*\name PWR_EnterSTANDBYMode. +*\*\fun System Enters STANDBY mode. +*\*\param none +*\*\return none +**/ +void PWR_EnterSTANDBYMode(void) +{ + __IO uint32_t* ControlRegAddr1; + __IO uint32_t* ControlRegAddr2; + /*Get contrl register address*/ + if(Get_CurrentCPU() == CM7_CPU) + { + ControlRegAddr1 = &PWR->M7CTRL1; + ControlRegAddr2 = &PWR->M7CTRL2; + } + else + { + ControlRegAddr1 = &PWR->M4CTRL1; + ControlRegAddr2 = &PWR->M4CTRL2; + } + /* Clear Wake-up flag */ + *ControlRegAddr1 |= PWR_CLR_WKUPx; + /* Clear STOP2S bits */ + *ControlRegAddr2 &= ~PWR_STOP2EN; + /* Set PDDS bit to select STANDBY mode */ + *ControlRegAddr1 |= PWR_PDSEN; + /*Off BG , 1A version ,1B version will remove this*/ + PWR->SYSCTRL2 &= ~0x400U; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + +/* This option is used to ensure that store operations are completed */ +#if defined(__CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); + +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rcc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rcc.c new file mode 100644 index 0000000000..0fba98007e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rcc.c @@ -0,0 +1,9078 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_rcc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_rcc.h" +#include + +/** RCC Private Defines **/ +#define __RCC_DELAY_US(usec) do{ \ + uint32_t delay_end; \ + CPU_DELAY_INTI(); \ + /* Delay*/ \ + delay_end = DWT_CYCCNT + (usec * (600000000/1000000)); \ + while(DWT_CYCCNT < delay_end){}; \ + CPU_DELAY_DISABLE(); \ + }while(0) + + +/** RCC Driving Functions Declaration **/ +/** + *\*\name RCC_Reset + *\*\fun Resets the RCC clock configuration to the default reset state. + *\*\param None + *\*\return None + */ +void RCC_DeInit(void) +{ + + /* Set HSIEN bit */ + RCC->SRCCTRL1 |= (uint32_t)0x00000001U; + + /* Reset SCLKSW, MSIEN ,HSEBP, HSEEN bits */ + RCC->SRCCTRL1 &= (uint32_t)0xFCFFFFABU; + + /* Reset M7HYPSEL,AXIHYPSEL*/ + RCC->SRCCTRL2 &= (uint32_t)0xFFFCFFFFU; + + /* Reset SYSBUSDIV1, SYSBUSDIV2 */ + RCC->SYSBUSDIV1 = RCC_REG_BIT_MASK; + RCC->SYSBUSDIV2 = RCC_REG_BIT_MASK; + + /* Reset PLL1CTRL1 */ + RCC->PLL1CTRL1 = (uint32_t)0x19030004U; + + /* Reset PLL2CTRL1 */ + RCC->PLL2CTRL1 &= (uint32_t)0x19030005U; + + /* Reset PLL3CTRL1 */ + RCC->PLL3CTRL1 &= (uint32_t)0x19030005U; + + /* Reset CFG2 register */ + RCC->CFG2 = 0x55ACCCCCU; + + /* Reset CFG3 register */ + RCC->CFG3 = 0x00000044U; + + /* Reset CFG4 register */ + RCC->CFG4 = 0xFFFFFDFEU; + + /* Reset CFG5 register */ + RCC->CFG5 = 0x02C10000U; + + /* Disable all interrupts and clear pending bits */ + RCC->CLKINT1 = RCC_REG_BIT_MASK; + RCC->CLKINT2 = RCC_REG_BIT_MASK; + RCC->CLKINT3 = RCC_REG_BIT_MASK; +} + +/** +*\*\name RCC_ConfigHse. +*\*\fun Configures the External High Speed oscillator (HSE). +*\*\param RCC_HSE : +*\*\ - RCC_HSE_DISABLE HSE oscillator OFF +*\*\ - RCC_HSE_ENABLE HSE oscillator ON +*\*\ - RCC_HSE_BYPASS HSE oscillator bypassed with external clock +*\*\return none: +*\*\note HSE can not be stopped if it is used directly or through the PLL as system clock +**/ +void RCC_ConfigHse(uint32_t RCC_HSE) +{ + if(RCC_HSE == RCC_HSE_DISABLE) + { + /* Reset HSEEN bit */ + RCC->SRCCTRL1 &= (~(RCC_HSE_ENABLE | RCC_HSE_BYPASS)); + } + else + { + /* Reset HSERDCNTEN bit */ + RCC->SRCCTRL1 &= (~RCC_HSE_RDCNTEN); + + if (RCC_HSE == RCC_HSE_BYPASS) + { + if((RCC->SRCCTRL1 & RCC_HSE_ENABLE) == RCC_HSE_ENABLE) + { + /* Reset HSEEN bit */ + RCC->SRCCTRL1 &= (~RCC_HSE_ENABLE); + } + + /* Set HSEBP bits */ + RCC->SRCCTRL1 |= RCC_HSE_BYPASS; + } + + /* Set HSEEN bit */ + RCC->SRCCTRL1 |= RCC_HSE_ENABLE; + __RCC_DELAY_US(50); + /* Set HSERDCNTEN bit */ + RCC->SRCCTRL1 |= (RCC_HSE_RDCNTEN); + + } +} + +/** +*\*\name RCC_WaitHseStable. +*\*\fun Waits for HSE start-up. +*\*\param none +*\*\return ErrorStatus: + *\*\ - SUCCESS HSE oscillator is stable and ready to use + *\*\ - ERROR HSE oscillator not yet ready +**/ +ErrorStatus RCC_WaitHseStable(void) +{ + __IO uint32_t counter_value = 0; + uint32_t timeout_value; + uint32_t status_value; + RCC_ClocksTypeDef sysclk_value; + ErrorStatus bitstatus; + + RCC_GetClocksFreqValue(&sysclk_value); + timeout_value = (HSE_STARTUP_TIMEOUT / ((uint32_t)600000000 / sysclk_value.SysClkFreq)); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + status_value = (RCC->SRCCTRL1 & RCC_HSE_STABLE_FLAG); + counter_value++; + } + while ((counter_value != timeout_value) && (status_value != RCC_HSE_STABLE_FLAG)); + + if ((RCC->SRCCTRL1 & RCC_HSE_STABLE_FLAG) == RCC_HSE_STABLE_FLAG) + { + bitstatus = SUCCESS; + } + else + { + bitstatus = ERROR; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableHsi. +*\*\fun Enables the Internal High Speed oscillator (HSI). +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note HSI can not be stopped if it is used directly or through the PLL as system clock. +**/ +void RCC_EnableHsi(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /* Set HSIEN bit */ + RCC->SRCCTRL1 |= RCC_HSI_ENABLE; + } + else + { + /* Reset HSIEN bit */ + RCC->SRCCTRL1 &= (~RCC_HSI_ENABLE); + } +} + +/** +*\*\name RCC_WaitHsiStable. +*\*\fun Waits for HSI start-up. +*\*\param none +*\*\return ErrorStatus: + *\*\ - SUCCESS HSI oscillator is stable and ready to use + *\*\ - ERROR HSI oscillator not yet ready +**/ +ErrorStatus RCC_WaitHsiStable(void) +{ + __IO uint32_t counter_value = 0; + uint32_t timeout_value; + uint32_t status_value; + RCC_ClocksTypeDef sysclk_value; + ErrorStatus bitstatus; + + RCC_GetClocksFreqValue(&sysclk_value); + timeout_value = (HSI_STARTUP_TIMEOUT / ((uint32_t)600000000 / sysclk_value.SysClkFreq)); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + status_value = (RCC->SRCCTRL1 & RCC_HSI_STABLE_FLAG); + counter_value++; + } + while ((counter_value != timeout_value) && (status_value != RCC_HSI_STABLE_FLAG)); + + if ((RCC->SRCCTRL1 & RCC_HSI_STABLE_FLAG) == RCC_HSI_STABLE_FLAG) + { + bitstatus = SUCCESS; + } + else + { + bitstatus = ERROR; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableMsi. +*\*\fun Enables the Internal High Speed oscillator (MSI). +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note MSI can not be stopped if it is used directly or through the PLL as system clock. +**/ +void RCC_EnableMsi(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /* Set MSIEN bit */ + RCC->SRCCTRL1 |= RCC_MSI_ENABLE; + } + else + { + /* Reset MSIEN bit */ + RCC->SRCCTRL1 &= (~RCC_MSI_ENABLE); + } +} + +/** +*\*\name RCC_WaitMsiStable. +*\*\fun Waits for MSI start-up. +*\*\param none +*\*\return ErrorStatus: + *\*\ - SUCCESS MSI oscillator is stable and ready to use + *\*\ - ERROR MSI oscillator not yet ready +**/ +ErrorStatus RCC_WaitMsiStable(void) +{ + __IO uint32_t counter_value = 0; + uint32_t timeout_value; + uint32_t status_value; + RCC_ClocksTypeDef sysclk_value; + ErrorStatus bitstatus; + + RCC_GetClocksFreqValue(&sysclk_value); + timeout_value = (MSI_STARTUP_TIMEOUT / ((uint32_t)600000000 / sysclk_value.SysClkFreq)); + + /* Wait till MSI is ready and if Time out is reached exit */ + do + { + status_value = (RCC->SRCCTRL1 & RCC_MSI_STABLE_FLAG); + counter_value++; + } + while ((counter_value != timeout_value) && (status_value != RCC_MSI_STABLE_FLAG)); + + if ((RCC->SRCCTRL1 & RCC_MSI_STABLE_FLAG) == RCC_MSI_STABLE_FLAG) + { + bitstatus = SUCCESS; + } + else + { + bitstatus = ERROR; + } + + return bitstatus; +} + +/** +*\*\name RCC_ConfigLse. +*\*\fun Configures the External High Speed oscillator (LSE). +*\*\param RCC_LSE : +*\*\ - RCC_LSE_DISABLE LSE oscillator OFF +*\*\ - RCC_LSE_ENABLE LSE oscillator ON +*\*\ - RCC_LSE_BYPASS LSE oscillator bypassed with external clock +*\*\return none: +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_ConfigLse(uint32_t RCC_LSE) +{ + + if(RCC_LSE == RCC_LSE_DISABLE) + { + RCC->BDCTRL &= (~(RCC_LSE_ENABLE | RCC_LSERDY_ENABLE)); + + while((RCC->BDCTRL & RCC_BDCTRL_LSERDF) == RCC_BDCTRL_LSERDF) + {} + + __RCC_DELAY_US(10); + RCC->BDCTRL &= (~(RCC_LSE_BYPASS | RCC_LSE_LSELDO)); + + } + else + { + if (RCC_LSE == RCC_LSE_BYPASS) + { + if((RCC->BDCTRL & RCC_LSE_ENABLE) == RCC_LSE_ENABLE) + { + RCC->BDCTRL &= (~RCC_LSE_ENABLE); + } + + /* Set LSEBP bits */ + RCC->BDCTRL |= RCC_LSE_BYPASS; + } + else + { + /* Reset LSEBP bits */ + RCC->BDCTRL &= (~RCC_LSE_BYPASS); + } + + /* Reset LSERDCNTEN bit */ + RCC->BDCTRL &= (~RCC_LSE_RDCNTEN); + /* Set LSEEN bit */ + RCC->BDCTRL |= RCC_LSE_LSELDO; + __RCC_DELAY_US(60); + if (RCC_LSE == RCC_LSE_ENABLE) + { + /* Set da_lse_agcopt bits */ + AFEC->TRIMR7 |= 0x00400000; + } + /* Set LSEEN bit */ + RCC->BDCTRL |= (RCC_LSE_ENABLE | RCC_LSERDY_ENABLE); + __RCC_DELAY_US(10); + /* Set LSERDCNTEN bit */ + RCC->BDCTRL |= (RCC_LSE_RDCNTEN); + } + +} + +/** +*\*\name RCC_WaitLseStable. +*\*\fun Waits for LSE start-up. +*\*\param none +*\*\return ErrorStatus: + *\*\ - SUCCESS LSE oscillator is stable and ready to use + *\*\ - ERROR LSE oscillator not yet ready +**/ +ErrorStatus RCC_WaitLseStable(void) +{ + __IO uint32_t counter_value = 0; + uint32_t timeout_value; + uint32_t status_value; + RCC_ClocksTypeDef sysclk_value; + ErrorStatus bitstatus; + + RCC_GetClocksFreqValue(&sysclk_value); + timeout_value = (LSE_STARTUP_TIMEOUT / ((uint32_t)600000000 / sysclk_value.SysClkFreq)); + + /* Wait till LSE is ready and if Time out is reached exit */ + do + { + status_value = (RCC->BDCTRL & RCC_LSE_STABLE_FLAG); + counter_value++; + } + while ((counter_value != timeout_value) && (status_value != RCC_LSE_STABLE_FLAG)); + + if ((RCC->BDCTRL & RCC_LSE_STABLE_FLAG) == RCC_LSE_STABLE_FLAG) + { + bitstatus = SUCCESS; + } + else + { + bitstatus = ERROR; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableLsi. +*\*\fun Enables the Internal Low Speed oscillator (LSI). +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableLsi(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /* Set LSIEN bit */ + RCC->BDCTRL |= (RCC_LSI_ENABLE | RCC_LSIRDY_ENABLE); + } + else + { + /* Reset PLLEN bit */ + RCC->BDCTRL &= (~(RCC_LSI_ENABLE | RCC_LSIRDY_ENABLE)); + } + +} + +/** +*\*\name RCC_WaitLsiStable. +*\*\fun Waits for LSI start-up. +*\*\param none +*\*\return ErrorStatus: + *\*\ - SUCCESS LSI oscillator is stable and ready to use + *\*\ - ERROR LSI oscillator not yet ready +**/ +ErrorStatus RCC_WaitLsiStable(void) +{ + __IO uint32_t counter_value = 0; + uint32_t timeout_value; + uint32_t status_value; + RCC_ClocksTypeDef sysclk_value; + ErrorStatus bitstatus; + + RCC_GetClocksFreqValue(&sysclk_value); + timeout_value = (LSI_STARTUP_TIMEOUT / ((uint32_t)600000000 / sysclk_value.SysClkFreq)); + + /* Wait till LSI is ready and if Time out is reached exit */ + do + { + status_value = (RCC->BDCTRL & RCC_LSI_STABLE_FLAG); + counter_value++; + } + while ((counter_value != timeout_value) && (status_value != RCC_LSI_STABLE_FLAG)); + + if ((RCC->BDCTRL & RCC_LSI_STABLE_FLAG) == RCC_LSI_STABLE_FLAG) + { + bitstatus = SUCCESS; + } + else + { + bitstatus = ERROR; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableSecondaryLsi. +*\*\fun Enables the Secondary Internal Low Speed oscillator (LSI). +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableSecondaryLsi(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + /* Set LSIEN bit */ + RCC->BDCTRL |= RCC_SECLSI_ENABLE; + } + else + { + /* Reset PLLEN bit */ + RCC->BDCTRL &= (~RCC_SECLSI_ENABLE); + } + +} + +/** +*\*\name RCC_WaitSecondaryLsiStable. +*\*\fun Waits for SECLSI start-up. +*\*\param none +*\*\return ErrorStatus: + *\*\ - SUCCESS SECLSI oscillator is stable and ready to use + *\*\ - ERROR SECLSI oscillator not yet ready +**/ +ErrorStatus RCC_WaitSecondaryLsiStable(void) +{ + __IO uint32_t counter_value = 0; + uint32_t timeout_value; + uint32_t status_value; + RCC_ClocksTypeDef sysclk_value; + ErrorStatus bitstatus; + + RCC_GetClocksFreqValue(&sysclk_value); + timeout_value = (SECLSI_STARTUP_TIMEOUT / ((uint32_t)600000000 / sysclk_value.SysClkFreq)); + + /* Wait till SECLSI is ready and if Time out is reached exit */ + do + { + status_value = (RCC->BDCTRL & RCC_SECLSI_STABLE_FLAG); + counter_value++; + } + while ((counter_value != timeout_value) && (status_value != RCC_SECLSI_STABLE_FLAG)); + + if ((RCC->BDCTRL & RCC_SECLSI_STABLE_FLAG) == RCC_SECLSI_STABLE_FLAG) + { + bitstatus = SUCCESS; + } + else + { + bitstatus = ERROR; + } + + return bitstatus; +} + +/** +*\*\name RCC_ConfigSysclk. +*\*\fun Configures the system clock (SYSCLK). +*\*\param sysclk_source(clock source used as system clock): +*\*\ - RCC_SYSCLK_SRC_HSI HSI selected as system clock +*\*\ - RCC_SYSCLK_SRC_MSI HSI selected as system clock +*\*\ - RCC_SYSCLK_SRC_HSE HSE selected as system clock +*\*\ - RCC_SYSCLK_SRC_PLL1A PLL1A selected as system clock +*\*\return none +**/ +void RCC_ConfigSysclk(uint32_t sysclk_source) +{ + uint32_t reg_value; + + reg_value = RCC->SRCCTRL1; + /* Clear SCLKSW bits */ + reg_value &= RCC_SYSCLK_SRC_MASK; + /* Set SCLKSW bits */ + reg_value |= sysclk_source; + /* Store the new value */ + RCC->SRCCTRL1 = reg_value; + +} + +/** +*\*\name RCC_GetSysclkSrc. +*\*\fun Returns the clock source used as system clock. +*\*\param none +*\*\return (The clock source used as system clock): +*\*\ - RCC_SYSCLK_STS_HSI HSI used as system clock +*\*\ - RCC_SYSCLK_STS_MSI HSI used as system clock +*\*\ - RCC_SYSCLK_STS_HSE HSE used as system clock +*\*\ - RCC_SYSCLK_STS_PLL1A PLL1A used as system clock +**/ +uint32_t RCC_GetSysclkSrc(void) +{ + return ((uint32_t)(RCC->SRCCTRL1 & RCC_SYSCLK_STS_MASK)); +} + + +/** +*\*\name RCC_ConfigHSIclkDivider . +*\*\fun Obtained by dividing the HSI 64M clk. +*\*\param CLK_divider +*\*\ - RCC_HSICLK_DIV1 +*\*\ - RCC_HSICLK_DIV2 +*\*\ - RCC_HSICLK_DIV4 +*\*\ - RCC_HSICLK_DIV8 +*\*\ - RCC_HSICLK_DIV16 +*\*\ - RCC_HSICLK_DIV32 +*\*\ - RCC_HSICLK_DIV64 +*\*\ - RCC_HSICLK_DIV128 +*\*\ - RCC_HSICLK_DIV256 +*\*\ - RCC_HSICLK_DIV512 +*\*\return none. +*\*\note All HSI are divided clocks except PLL clock sources +**/ +void RCC_ConfigHSIclkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear HSIDIV bits */ + reg_value &= RCC_HSICLK_DIV_MASK; + /* Set the HSIDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigMSIclkDivider . +*\*\fun Obtained by dividing the MSI 64M clk. +*\*\param CLK_divider +*\*\ - RCC_MSICLK_DIV1 +*\*\ - RCC_MSICLK_DIV2 +*\*\ - RCC_MSICLK_DIV4 +*\*\ - RCC_MSICLK_DIV8 +*\*\ - RCC_MSICLK_DIV16 +*\*\ - RCC_MSICLK_DIV32 +*\*\ - RCC_MSICLK_DIV64 +*\*\ - RCC_MSICLK_DIV128 +*\*\ - RCC_MSICLK_DIV256 +*\*\ - RCC_MSICLK_DIV512 +*\*\return none. +*\*\note All MSI are divided clocks except PLL clock sources +**/ +void RCC_ConfigMSIclkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear MSIDIV bits */ + reg_value &= RCC_MSICLK_DIV_MASK; + /* Set the MSIDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigM7Clk. +*\*\fun Config the M7 clock source selection. +*\*\param CLK_source: +*\*\ - RCC_M7HYPERCLK_SRC_PLL1A +*\*\ - RCC_M7HYPERCLK_SRC_PLL2A +*\*\return none +*\*\note none +**/ +void RCC_ConfigM7Clk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->SRCCTRL2; + /* Clear M7HYPSEL bits */ + reg_value &= RCC_M7HYPERCLK_SRC_MASK; + /* Set the M7HYPSEL bits */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->SRCCTRL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigAXIClk. +*\*\fun Config the AXI clock source selection. +*\*\param CLK_source: +*\*\ - RCC_AXIHYPERCLK_SRC_PLL1A +*\*\ - RCC_AXIHYPERCLK_SRC_PLL2A +*\*\return none +*\*\note none +**/ +void RCC_ConfigAXIClk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->SRCCTRL2; + /* Clear AXIHYPSEL bits */ + reg_value &= RCC_AXIHYPERCLK_SRC_MASK; + /* Set the AXIHYPSEL bits */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->SRCCTRL2 = reg_value; + +} + +/** +*\*\name RCC_CalculatePLLParam. +*\*\fun Configures the SHRTPLL clock source and multiplication factor. +*\*\param fin(SHRTPLL input frequency): +*\*\ 1000000 ~ 64000000 (Hz) +*\*\param fout(SHRTPLL output frequency): +*\*\ 75000000 ~ 1250000000 (Hz) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: +*\*\ - SUCCESS +*\*\ - ERROR +*\*\note fout = fin*(CLKF[25:0]/16384)/(CLKR[5:0] +1) +**/ +ErrorStatus RCC_CalculatePLLParam(uint64_t fin, uint64_t fout, uint32_t* nr, uint32_t* nf, uint32_t* wb) +{ + ErrorStatus status; + uint64_t err_t; + uint32_t nr_t; + uint32_t nf_all; + uint32_t nf_int; + uint64_t err = (uint64_t)0xFFFFFFFFU; + + /* get NR NF WB parameter */ + if ((fin > REF_MAX) || (fin < REF_MIN) || (fout > VCO_MAX) || (fout < VCO_MIN)) + { + status = ERROR; + } + else + { + for ( nr_t = NR_MAX; nr_t >= NR_MIN; nr_t--) + { + nf_all = (uint32_t)floor(fout * nr_t * 256 / fin); + nf_int = nf_all / 256; + + if ((nf_int > NF_MAX) || (nf_int < NF_MIN)) + { + continue; + } + + if((fin * nf_all / nr_t / 256) > fout) + { + err_t = ((fin * nf_all / nr_t / 256) - fout); + } + else + { + err_t = (fout - (fin * nf_all / nr_t / 256)); + } + + if (err_t <= err) + { + err = err_t; + *nr = nr_t; + *nf = nf_all; + } + else + { + /* In other cases, the cycle continues*/ + } + } + + *wb = (uint32_t)floor((*nf / 2 / 256) - 1); + + if(*wb > 2047) + { + *wb = 2047; + } + + *nr = *nr - 1; + *nf = *nf * 64; + status = SUCCESS; + } + + return status; +} + +/** +*\*\name RCC_ConfigSHRPll. +*\*\fun Configures the SHRPLL clock source and multiplication factor. +*\*\param PLL_source(SHRPLL entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as SHRPLL clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as SHRPLL clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as SHRPLL clock entry +*\*\param fin(SHRPLL input frequency): +*\*\ 4000000 ~ 50000000 (Hz) +*\*\param fout(SHRPLL output frequency): +*\*\ 100000000 ~ 312500000 (Hz) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note fout = fin*(CLKF[25:0]/16384)/(CLKR[5:0] +1)/4 +**/ +ErrorStatus RCC_ConfigSHRPll(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + uint32_t nrtmp = 0; + uint32_t nftmp = 0; + uint32_t wbtmp = 0; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->SHRPLLCTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->SHRPLLCTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->SHRPLLCTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get NR NF WB parameter */ + fout = fout * 4; + + if(RCC_CalculatePLLParam(fin, fout, &nrtmp, &nftmp, &wbtmp) == SUCCESS) + { + /* get the register value */ + temp_value1 = RCC->SHRPLLCTRL1; + temp_value2 = RCC->SHRPLLCTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->SHRPLLCTRL1 = temp_value1; + RCC->SHRPLLCTRL2 = temp_value2; + + /* Enable PLL module power */ + RCC->SHRPLLCTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->SHRPLLCTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->SHRPLLCTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->SHRPLLCTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->SHRPLLCTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + } + else + { + status = ERROR; + } + + } + + return status; +} + +/** +*\*\name RCC_ConfigPll1. +*\*\fun Configures the PLL1 clock source and multiplication factor. +*\*\param PLL_source(PLL1 entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as PLL1 clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as PLL1 clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as PLL1 clock entry +*\*\param fin(PLL1 input frequency): +*\*\ 1000000 ~ 64000000 (Hz) +*\*\param fout(PLL1 output frequency): +*\*\ 400000000 ~ 8000000000 (Hz) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note fout = fin*(CLKF[25:0]/16384)/(CLKR[5:0] +1) +**/ +ErrorStatus RCC_ConfigPll1(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + uint32_t nrtmp = 0; + uint32_t nftmp = 0; + uint32_t wbtmp = 0; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->PLL1CTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->PLL1CTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->PLL1CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->PLL1CTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + RCC->PLL1CTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get NR NF WB parameter */ + if(RCC_CalculatePLLParam(fin, fout, &nrtmp, &nftmp, &wbtmp) == SUCCESS) + { + /* get the register value */ + temp_value1 = RCC->PLL1CTRL1; + temp_value2 = RCC->PLL1CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->PLL1CTRL1 = temp_value1; + RCC->PLL1CTRL2 = temp_value2; + + /* Enable PLL module power */ + RCC->PLL1CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL1CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL1CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->PLL1CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL1CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL1CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL1CTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + } + else + { + status = ERROR; + } + + } + + return status; +} + +/** +*\*\name RCC_ConfigPll2. +*\*\fun Configures the PLL2 clock source and multiplication factor. +*\*\param PLL_source(PLL2 entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as PLL2 clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as PLL2 clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as PLL2 clock entry +*\*\param fin(PLL2 input frequency): +*\*\ 1000000 ~ 64000000 (Hz) +*\*\param fout(PLL2 output frequency): +*\*\ 400000000 ~ 800000000 (Hz) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note fout = fin*(CLKF[25:0]/16384)/(CLKR[5:0] +1) +**/ +ErrorStatus RCC_ConfigPll2(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + uint32_t nrtmp = 0; + uint32_t nftmp = 0; + uint32_t wbtmp = 0; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->PLL2CTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->PLL2CTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->PLL2CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->PLL2CTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + //RCC->PLL2CTRL1 &= (~RCC_PLL_LDO_ENABLE); + RCC->PLL3CTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get NR NF WB parameter */ + if(RCC_CalculatePLLParam(fin, fout, &nrtmp, &nftmp, &wbtmp) == SUCCESS) + { + /* get the register value */ + temp_value1 = RCC->PLL2CTRL1; + temp_value2 = RCC->PLL2CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->PLL2CTRL1 = temp_value1; + RCC->PLL2CTRL2 = temp_value2; + + /* Enable PLL module power */ + //RCC->PLL2CTRL1 |= RCC_PLL_LDO_ENABLE; + RCC->PLL3CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL2CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL2CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->PLL2CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL2CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL2CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL2CTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + } + else + { + status = ERROR; + } + + } + + return status; +} + +/** +*\*\name RCC_ConfigPll3. +*\*\fun Configures the PLL3 clock source and multiplication factor. +*\*\param PLL_source(PLL3 entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as PLL3 clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as PLL3 clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as PLL3 clock entry +*\*\param fin(PLL3 input frequency): +*\*\ 1000000 ~ 64000000 (Hz) +*\*\param fout(PLL3 output frequency): +*\*\ 400000000 ~ 800000000 (Hz) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note fout = fin*(CLKF[25:0]/16384)/(CLKR[5:0] +1) +**/ +ErrorStatus RCC_ConfigPll3(uint32_t PLL_source, uint64_t fin, uint64_t fout, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + uint32_t nrtmp = 0; + uint32_t nftmp = 0; + uint32_t wbtmp = 0; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->PLL3CTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->PLL3CTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->PLL3CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->PLL3CTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + //RCC->PLL3CTRL1 &= (~RCC_PLL_LDO_ENABLE); + RCC->PLL2CTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get NR NF WB parameter */ + if(RCC_CalculatePLLParam(fin, fout, &nrtmp, &nftmp, &wbtmp) == SUCCESS) + { + /* get the register value */ + temp_value1 = RCC->PLL3CTRL1; + temp_value2 = RCC->PLL3CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->PLL3CTRL1 = temp_value1; + RCC->PLL3CTRL2 = temp_value2; + + /* Enable PLL module power */ + //RCC->PLL3CTRL1 |= RCC_PLL_LDO_ENABLE; + RCC->PLL2CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL3CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL3CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->PLL3CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL3CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL3CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL3CTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + } + else + { + status = ERROR; + } + + } + + return status; +} + +/** +*\*\name RCC_ConfigSHRPll. +*\*\fun Configures the SHRPLL clock source and multiplication factor. +*\*\param PLL_source(SHRPLL entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as SHRPLL clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as SHRPLL clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as SHRPLL clock entry +*\*\param nrtmp(SHRPLLCLKR parameter) +*\*\param nftmp(SHRPLLCLKF parameter) +*\*\param wbtmp(SHRPLLBWAJ parameter) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note Directly enter the nrtmp, nrtmp and wbtmp configuration parameters without spending a long time calculating the results +**/ +ErrorStatus RCC_ConfigSHRPll_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->SHRPLLCTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->SHRPLLCTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->SHRPLLCTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get NR NF WB parameter */ + /* get the register value */ + temp_value1 = RCC->SHRPLLCTRL1; + temp_value2 = RCC->SHRPLLCTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->SHRPLLCTRL1 = temp_value1; + RCC->SHRPLLCTRL2 = temp_value2; + + /* Enable PLL module power */ + RCC->SHRPLLCTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->SHRPLLCTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->SHRPLLCTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->SHRPLLCTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->SHRPLLCTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->SHRPLLCTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + } + + return status; +} + +/** +*\*\name RCC_ConfigPll1. +*\*\fun Configures the PLL1 clock source and multiplication factor. +*\*\param PLL_source(PLL1 entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as PLL1 clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as PLL1 clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as PLL1 clock entry +*\*\param nrtmp(PLL1CLKR parameter) +*\*\param nftmp(PLL1CLKF parameter) +*\*\param wbtmp(PLL1BWAJ parameter) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note Directly enter the nrtmp, nrtmp and wbtmp configuration parameters without spending a long time calculating the results +**/ +ErrorStatus RCC_ConfigPll1_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->PLL1CTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->PLL1CTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->PLL1CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->PLL1CTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + RCC->PLL1CTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get the register value */ + temp_value1 = RCC->PLL1CTRL1; + temp_value2 = RCC->PLL1CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->PLL1CTRL1 = temp_value1; + RCC->PLL1CTRL2 = temp_value2; + + /* Enable PLL module power */ + RCC->PLL1CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL1CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL1CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->PLL1CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL1CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL1CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL1CTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + + + } + + return status; +} + +/** +*\*\name RCC_ConfigPll2. +*\*\fun Configures the PLL2 clock source and multiplication factor. +*\*\param PLL_source(PLL2 entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as PLL2 clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as PLL2 clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as PLL2 clock entry +*\*\param nrtmp(PLL2CLKR parameter) +*\*\param nftmp(PLL2CLKF parameter) +*\*\param wbtmp(PLL2BWAJ parameter) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note Directly enter the nrtmp, nrtmp and wbtmp configuration parameters without spending a long time calculating the results +**/ +ErrorStatus RCC_ConfigPll2_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->PLL2CTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->PLL2CTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->PLL2CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->PLL2CTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + //RCC->PLL2CTRL1 &= (~RCC_PLL_LDO_ENABLE); + RCC->PLL3CTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get the register value */ + temp_value1 = RCC->PLL2CTRL1; + temp_value2 = RCC->PLL2CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->PLL2CTRL1 = temp_value1; + RCC->PLL2CTRL2 = temp_value2; + + /* Enable PLL module power */ + //RCC->PLL2CTRL1 |= RCC_PLL_LDO_ENABLE; + RCC->PLL3CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL2CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL2CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->PLL2CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL2CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL2CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL2CTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + + } + + return status; +} + +/** +*\*\name RCC_ConfigPll3. +*\*\fun Configures the PLL3 clock source and multiplication factor. +*\*\param PLL_source(PLL3 entry clock source): +*\*\ - RCC_PLL_SRC_HSI HSI oscillator clock selected as PLL3 clock entry +*\*\ - RCC_PLL_SRC_MSI MSI oscillator clock selected as PLL3 clock entry +*\*\ - RCC_PLL_SRC_HSE HSE oscillator clock selected as PLL3 clock entry +*\*\param nrtmp(PLL3CLKR parameter) +*\*\param nftmp(PLL3CLKF parameter) +*\*\param wbtmp(PLL3BWAJ parameter) +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus: + *\*\ - SUCCESS + *\*\ - ERROR +*\*\note Directly enter the nrtmp, nrtmp and wbtmp configuration parameters without spending a long time calculating the results +**/ +ErrorStatus RCC_ConfigPll3_NoCalculate(uint32_t PLL_source, uint32_t nrtmp, uint32_t nftmp, uint32_t wbtmp, FunctionalState Cmd) +{ + uint32_t temp_value1, temp_value2; + ErrorStatus status; + + if(Cmd == DISABLE) + { + /* Disable PLL */ + RCC->PLL3CTRL1 &= (~RCC_PLL_ENABLE); + /* Enable PLL reset */ + RCC->PLL3CTRL1 |= RCC_PLL_RESET_ENABLE; + + while((RCC->PLL3CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_REG_BIT_MASK) + {} + + /* Disable power to analog circuitry in PLL */ + RCC->PLL3CTRL1 |= RCC_PLL_POWER_DOWN; + /* Disable PLL module power */ + //RCC->PLL3CTRL1 &= (~RCC_PLL_LDO_ENABLE); + RCC->PLL2CTRL1 &= (~RCC_PLL_LDO_ENABLE); + status = SUCCESS; + } + else + { + /* get the register value */ + temp_value1 = RCC->PLL3CTRL1; + temp_value2 = RCC->PLL3CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits */ + temp_value1 |= (uint32_t)(wbtmp & 0xFFF); + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= (uint32_t)((nrtmp << 26) | (nftmp & 0x3FFFFFF)); + + /* Store the new value */ + RCC->PLL3CTRL1 = temp_value1; + RCC->PLL3CTRL2 = temp_value2; + + /* Enable PLL module power */ + //RCC->PLL3CTRL1 |= RCC_PLL_LDO_ENABLE; + RCC->PLL2CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL3CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL3CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= PLL_source; + RCC->PLL3CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL3CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL3CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL3CTRL1 |= RCC_PLL_ENABLE; + status = SUCCESS; + + } + + return status; +} + +/** +*\*\name RCC_ConfigPLL1CDivider . +*\*\fun Configure PLL1 prescaler value to PLL1C. +*\*\param CLK_divider +*\*\ - RCC_PLLC_DIV1 +*\*\ - RCC_PLLC_DIV2 +*\*\ - RCC_PLLC_DIV3 +*\*\ - RCC_PLLC_DIV4 +*\*\ - RCC_PLLC_DIV5 +*\*\ - RCC_PLLC_DIV6 +*\*\ - RCC_PLLC_DIV7 +*\*\ - RCC_PLLC_DIV8 +*\*\ - RCC_PLLC_DIV9 +*\*\ - RCC_PLLC_DIV10 +*\*\ - RCC_PLLC_DIV11 +*\*\ - RCC_PLLC_DIV12 +*\*\ - RCC_PLLC_DIV13 +*\*\ - RCC_PLLC_DIV14 +*\*\ - RCC_PLLC_DIV15 +*\*\ - RCC_PLLC_DIV16 +*\*\ - RCC_PLLC_DIV17 +*\*\ - RCC_PLLC_DIV18 +*\*\ - RCC_PLLC_DIV19 +*\*\ - RCC_PLLC_DIV20 +*\*\ - RCC_PLLC_DIV21 +*\*\ - RCC_PLLC_DIV22 +*\*\ - RCC_PLLC_DIV23 +*\*\ - RCC_PLLC_DIV24 +*\*\ - RCC_PLLC_DIV25 +*\*\ - RCC_PLLC_DIV26 +*\*\ - RCC_PLLC_DIV27 +*\*\ - RCC_PLLC_DIV28 +*\*\ - RCC_PLLC_DIV29 +*\*\ - RCC_PLLC_DIV30 +*\*\ - RCC_PLLC_DIV31 +*\*\ - RCC_PLLC_DIV32 +*\*\ - RCC_PLLC_DIV33 +*\*\ - RCC_PLLC_DIV34 +*\*\ - RCC_PLLC_DIV35 +*\*\ - RCC_PLLC_DIV36 +*\*\ - RCC_PLLC_DIV37 +*\*\ - RCC_PLLC_DIV38 +*\*\ - RCC_PLLC_DIV39 +*\*\ - RCC_PLLC_DIV40 +*\*\ - RCC_PLLC_DIV41 +*\*\ - RCC_PLLC_DIV42 +*\*\ - RCC_PLLC_DIV43 +*\*\ - RCC_PLLC_DIV44 +*\*\ - RCC_PLLC_DIV45 +*\*\ - RCC_PLLC_DIV46 +*\*\ - RCC_PLLC_DIV47 +*\*\ - RCC_PLLC_DIV48 +*\*\ - RCC_PLLC_DIV49 +*\*\ - RCC_PLLC_DIV50 +*\*\ - RCC_PLLC_DIV51 +*\*\ - RCC_PLLC_DIV52 +*\*\ - RCC_PLLC_DIV53 +*\*\ - RCC_PLLC_DIV54 +*\*\ - RCC_PLLC_DIV55 +*\*\ - RCC_PLLC_DIV56 +*\*\ - RCC_PLLC_DIV57 +*\*\ - RCC_PLLC_DIV58 +*\*\ - RCC_PLLC_DIV59 +*\*\ - RCC_PLLC_DIV60 +*\*\ - RCC_PLLC_DIV61 +*\*\ - RCC_PLLC_DIV62 +*\*\ - RCC_PLLC_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL1CDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL1DIV; + /* Clear RCC_PLL1C_DIV bits */ + reg_value &= RCC_PLLC_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL1DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL1BDivider . +*\*\fun Configure PLL1 divider value to PLL1B. +*\*\param CLK_divider +*\*\ - RCC_PLLB_DIV1 +*\*\ - RCC_PLLB_DIV2 +*\*\ - RCC_PLLB_DIV3 +*\*\ - RCC_PLLB_DIV4 +*\*\ - RCC_PLLB_DIV5 +*\*\ - RCC_PLLB_DIV6 +*\*\ - RCC_PLLB_DIV7 +*\*\ - RCC_PLLB_DIV8 +*\*\ - RCC_PLLB_DIV9 +*\*\ - RCC_PLLB_DIV10 +*\*\ - RCC_PLLB_DIV11 +*\*\ - RCC_PLLB_DIV12 +*\*\ - RCC_PLLB_DIV13 +*\*\ - RCC_PLLB_DIV14 +*\*\ - RCC_PLLB_DIV15 +*\*\ - RCC_PLLB_DIV16 +*\*\ - RCC_PLLB_DIV17 +*\*\ - RCC_PLLB_DIV18 +*\*\ - RCC_PLLB_DIV19 +*\*\ - RCC_PLLB_DIV20 +*\*\ - RCC_PLLB_DIV21 +*\*\ - RCC_PLLB_DIV22 +*\*\ - RCC_PLLB_DIV23 +*\*\ - RCC_PLLB_DIV24 +*\*\ - RCC_PLLB_DIV25 +*\*\ - RCC_PLLB_DIV26 +*\*\ - RCC_PLLB_DIV27 +*\*\ - RCC_PLLB_DIV28 +*\*\ - RCC_PLLB_DIV29 +*\*\ - RCC_PLLB_DIV30 +*\*\ - RCC_PLLB_DIV31 +*\*\ - RCC_PLLB_DIV32 +*\*\ - RCC_PLLB_DIV33 +*\*\ - RCC_PLLB_DIV34 +*\*\ - RCC_PLLB_DIV35 +*\*\ - RCC_PLLB_DIV36 +*\*\ - RCC_PLLB_DIV37 +*\*\ - RCC_PLLB_DIV38 +*\*\ - RCC_PLLB_DIV39 +*\*\ - RCC_PLLB_DIV40 +*\*\ - RCC_PLLB_DIV41 +*\*\ - RCC_PLLB_DIV42 +*\*\ - RCC_PLLB_DIV43 +*\*\ - RCC_PLLB_DIV44 +*\*\ - RCC_PLLB_DIV45 +*\*\ - RCC_PLLB_DIV46 +*\*\ - RCC_PLLB_DIV47 +*\*\ - RCC_PLLB_DIV48 +*\*\ - RCC_PLLB_DIV49 +*\*\ - RCC_PLLB_DIV50 +*\*\ - RCC_PLLB_DIV51 +*\*\ - RCC_PLLB_DIV52 +*\*\ - RCC_PLLB_DIV53 +*\*\ - RCC_PLLB_DIV54 +*\*\ - RCC_PLLB_DIV55 +*\*\ - RCC_PLLB_DIV56 +*\*\ - RCC_PLLB_DIV57 +*\*\ - RCC_PLLB_DIV58 +*\*\ - RCC_PLLB_DIV59 +*\*\ - RCC_PLLB_DIV60 +*\*\ - RCC_PLLB_DIV61 +*\*\ - RCC_PLLB_DIV62 +*\*\ - RCC_PLLB_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL1BDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL1DIV; + /* Clear RCC_PLL1B_DIV bits */ + reg_value &= RCC_PLLB_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL1DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL1ADivider . +*\*\fun Configure PLL1 divider value to PLL1A. +*\*\param CLK_divider +*\*\ - RCC_PLLA_DIV1 +*\*\ - RCC_PLLA_DIV2 +*\*\ - RCC_PLLA_DIV3 +*\*\ - RCC_PLLA_DIV4 +*\*\ - RCC_PLLA_DIV5 +*\*\ - RCC_PLLA_DIV6 +*\*\ - RCC_PLLA_DIV7 +*\*\ - RCC_PLLA_DIV8 +*\*\ - RCC_PLLA_DIV9 +*\*\ - RCC_PLLA_DIV10 +*\*\ - RCC_PLLA_DIV11 +*\*\ - RCC_PLLA_DIV12 +*\*\ - RCC_PLLA_DIV13 +*\*\ - RCC_PLLA_DIV14 +*\*\ - RCC_PLLA_DIV15 +*\*\ - RCC_PLLA_DIV16 +*\*\ - RCC_PLLA_DIV17 +*\*\ - RCC_PLLA_DIV18 +*\*\ - RCC_PLLA_DIV19 +*\*\ - RCC_PLLA_DIV20 +*\*\ - RCC_PLLA_DIV21 +*\*\ - RCC_PLLA_DIV22 +*\*\ - RCC_PLLA_DIV23 +*\*\ - RCC_PLLA_DIV24 +*\*\ - RCC_PLLA_DIV25 +*\*\ - RCC_PLLA_DIV26 +*\*\ - RCC_PLLA_DIV27 +*\*\ - RCC_PLLA_DIV28 +*\*\ - RCC_PLLA_DIV29 +*\*\ - RCC_PLLA_DIV30 +*\*\ - RCC_PLLA_DIV31 +*\*\ - RCC_PLLA_DIV32 +*\*\ - RCC_PLLA_DIV33 +*\*\ - RCC_PLLA_DIV34 +*\*\ - RCC_PLLA_DIV35 +*\*\ - RCC_PLLA_DIV36 +*\*\ - RCC_PLLA_DIV37 +*\*\ - RCC_PLLA_DIV38 +*\*\ - RCC_PLLA_DIV39 +*\*\ - RCC_PLLA_DIV40 +*\*\ - RCC_PLLA_DIV41 +*\*\ - RCC_PLLA_DIV42 +*\*\ - RCC_PLLA_DIV43 +*\*\ - RCC_PLLA_DIV44 +*\*\ - RCC_PLLA_DIV45 +*\*\ - RCC_PLLA_DIV46 +*\*\ - RCC_PLLA_DIV47 +*\*\ - RCC_PLLA_DIV48 +*\*\ - RCC_PLLA_DIV49 +*\*\ - RCC_PLLA_DIV50 +*\*\ - RCC_PLLA_DIV51 +*\*\ - RCC_PLLA_DIV52 +*\*\ - RCC_PLLA_DIV53 +*\*\ - RCC_PLLA_DIV54 +*\*\ - RCC_PLLA_DIV55 +*\*\ - RCC_PLLA_DIV56 +*\*\ - RCC_PLLA_DIV57 +*\*\ - RCC_PLLA_DIV58 +*\*\ - RCC_PLLA_DIV59 +*\*\ - RCC_PLLA_DIV60 +*\*\ - RCC_PLLA_DIV61 +*\*\ - RCC_PLLA_DIV62 +*\*\ - RCC_PLLA_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL1ADivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL1DIV; + /* Clear RCC_PLL1A_DIV bits */ + reg_value &= RCC_PLLA_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL1DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL2CDivider . +*\*\fun Configure PLL2 divider value to PLL2C. +*\*\param CLK_divider +*\*\ - RCC_PLLC_DIV1 +*\*\ - RCC_PLLC_DIV2 +*\*\ - RCC_PLLC_DIV3 +*\*\ - RCC_PLLC_DIV4 +*\*\ - RCC_PLLC_DIV5 +*\*\ - RCC_PLLC_DIV6 +*\*\ - RCC_PLLC_DIV7 +*\*\ - RCC_PLLC_DIV8 +*\*\ - RCC_PLLC_DIV9 +*\*\ - RCC_PLLC_DIV10 +*\*\ - RCC_PLLC_DIV11 +*\*\ - RCC_PLLC_DIV12 +*\*\ - RCC_PLLC_DIV13 +*\*\ - RCC_PLLC_DIV14 +*\*\ - RCC_PLLC_DIV15 +*\*\ - RCC_PLLC_DIV16 +*\*\ - RCC_PLLC_DIV17 +*\*\ - RCC_PLLC_DIV18 +*\*\ - RCC_PLLC_DIV19 +*\*\ - RCC_PLLC_DIV20 +*\*\ - RCC_PLLC_DIV21 +*\*\ - RCC_PLLC_DIV22 +*\*\ - RCC_PLLC_DIV23 +*\*\ - RCC_PLLC_DIV24 +*\*\ - RCC_PLLC_DIV25 +*\*\ - RCC_PLLC_DIV26 +*\*\ - RCC_PLLC_DIV27 +*\*\ - RCC_PLLC_DIV28 +*\*\ - RCC_PLLC_DIV29 +*\*\ - RCC_PLLC_DIV30 +*\*\ - RCC_PLLC_DIV31 +*\*\ - RCC_PLLC_DIV32 +*\*\ - RCC_PLLC_DIV33 +*\*\ - RCC_PLLC_DIV34 +*\*\ - RCC_PLLC_DIV35 +*\*\ - RCC_PLLC_DIV36 +*\*\ - RCC_PLLC_DIV37 +*\*\ - RCC_PLLC_DIV38 +*\*\ - RCC_PLLC_DIV39 +*\*\ - RCC_PLLC_DIV40 +*\*\ - RCC_PLLC_DIV41 +*\*\ - RCC_PLLC_DIV42 +*\*\ - RCC_PLLC_DIV43 +*\*\ - RCC_PLLC_DIV44 +*\*\ - RCC_PLLC_DIV45 +*\*\ - RCC_PLLC_DIV46 +*\*\ - RCC_PLLC_DIV47 +*\*\ - RCC_PLLC_DIV48 +*\*\ - RCC_PLLC_DIV49 +*\*\ - RCC_PLLC_DIV50 +*\*\ - RCC_PLLC_DIV51 +*\*\ - RCC_PLLC_DIV52 +*\*\ - RCC_PLLC_DIV53 +*\*\ - RCC_PLLC_DIV54 +*\*\ - RCC_PLLC_DIV55 +*\*\ - RCC_PLLC_DIV56 +*\*\ - RCC_PLLC_DIV57 +*\*\ - RCC_PLLC_DIV58 +*\*\ - RCC_PLLC_DIV59 +*\*\ - RCC_PLLC_DIV60 +*\*\ - RCC_PLLC_DIV61 +*\*\ - RCC_PLLC_DIV62 +*\*\ - RCC_PLLC_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL2CDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL2DIV; + /* Clear RCC_PLL2C_DIV bits */ + reg_value &= RCC_PLLC_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL2DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL2BDivider . +*\*\fun Configure PLL2 divider value to PLL2B. +*\*\param CLK_divider +*\*\ - RCC_PLLB_DIV1 +*\*\ - RCC_PLLB_DIV2 +*\*\ - RCC_PLLB_DIV3 +*\*\ - RCC_PLLB_DIV4 +*\*\ - RCC_PLLB_DIV5 +*\*\ - RCC_PLLB_DIV6 +*\*\ - RCC_PLLB_DIV7 +*\*\ - RCC_PLLB_DIV8 +*\*\ - RCC_PLLB_DIV9 +*\*\ - RCC_PLLB_DIV10 +*\*\ - RCC_PLLB_DIV11 +*\*\ - RCC_PLLB_DIV12 +*\*\ - RCC_PLLB_DIV13 +*\*\ - RCC_PLLB_DIV14 +*\*\ - RCC_PLLB_DIV15 +*\*\ - RCC_PLLB_DIV16 +*\*\ - RCC_PLLB_DIV17 +*\*\ - RCC_PLLB_DIV18 +*\*\ - RCC_PLLB_DIV19 +*\*\ - RCC_PLLB_DIV20 +*\*\ - RCC_PLLB_DIV21 +*\*\ - RCC_PLLB_DIV22 +*\*\ - RCC_PLLB_DIV23 +*\*\ - RCC_PLLB_DIV24 +*\*\ - RCC_PLLB_DIV25 +*\*\ - RCC_PLLB_DIV26 +*\*\ - RCC_PLLB_DIV27 +*\*\ - RCC_PLLB_DIV28 +*\*\ - RCC_PLLB_DIV29 +*\*\ - RCC_PLLB_DIV30 +*\*\ - RCC_PLLB_DIV31 +*\*\ - RCC_PLLB_DIV32 +*\*\ - RCC_PLLB_DIV33 +*\*\ - RCC_PLLB_DIV34 +*\*\ - RCC_PLLB_DIV35 +*\*\ - RCC_PLLB_DIV36 +*\*\ - RCC_PLLB_DIV37 +*\*\ - RCC_PLLB_DIV38 +*\*\ - RCC_PLLB_DIV39 +*\*\ - RCC_PLLB_DIV40 +*\*\ - RCC_PLLB_DIV41 +*\*\ - RCC_PLLB_DIV42 +*\*\ - RCC_PLLB_DIV43 +*\*\ - RCC_PLLB_DIV44 +*\*\ - RCC_PLLB_DIV45 +*\*\ - RCC_PLLB_DIV46 +*\*\ - RCC_PLLB_DIV47 +*\*\ - RCC_PLLB_DIV48 +*\*\ - RCC_PLLB_DIV49 +*\*\ - RCC_PLLB_DIV50 +*\*\ - RCC_PLLB_DIV51 +*\*\ - RCC_PLLB_DIV52 +*\*\ - RCC_PLLB_DIV53 +*\*\ - RCC_PLLB_DIV54 +*\*\ - RCC_PLLB_DIV55 +*\*\ - RCC_PLLB_DIV56 +*\*\ - RCC_PLLB_DIV57 +*\*\ - RCC_PLLB_DIV58 +*\*\ - RCC_PLLB_DIV59 +*\*\ - RCC_PLLB_DIV60 +*\*\ - RCC_PLLB_DIV61 +*\*\ - RCC_PLLB_DIV62 +*\*\ - RCC_PLLB_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL2BDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL2DIV; + /* Clear RCC_PLL2B_DIV bits */ + reg_value &= RCC_PLLB_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL2DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL2ADivider . +*\*\fun Configure PLL2 divider value to PLL2A. +*\*\param CLK_divider +*\*\ - RCC_PLLA_DIV1 +*\*\ - RCC_PLLA_DIV2 +*\*\ - RCC_PLLA_DIV3 +*\*\ - RCC_PLLA_DIV4 +*\*\ - RCC_PLLA_DIV5 +*\*\ - RCC_PLLA_DIV6 +*\*\ - RCC_PLLA_DIV7 +*\*\ - RCC_PLLA_DIV8 +*\*\ - RCC_PLLA_DIV9 +*\*\ - RCC_PLLA_DIV10 +*\*\ - RCC_PLLA_DIV11 +*\*\ - RCC_PLLA_DIV12 +*\*\ - RCC_PLLA_DIV13 +*\*\ - RCC_PLLA_DIV14 +*\*\ - RCC_PLLA_DIV15 +*\*\ - RCC_PLLA_DIV16 +*\*\ - RCC_PLLA_DIV17 +*\*\ - RCC_PLLA_DIV18 +*\*\ - RCC_PLLA_DIV19 +*\*\ - RCC_PLLA_DIV20 +*\*\ - RCC_PLLA_DIV21 +*\*\ - RCC_PLLA_DIV22 +*\*\ - RCC_PLLA_DIV23 +*\*\ - RCC_PLLA_DIV24 +*\*\ - RCC_PLLA_DIV25 +*\*\ - RCC_PLLA_DIV26 +*\*\ - RCC_PLLA_DIV27 +*\*\ - RCC_PLLA_DIV28 +*\*\ - RCC_PLLA_DIV29 +*\*\ - RCC_PLLA_DIV30 +*\*\ - RCC_PLLA_DIV31 +*\*\ - RCC_PLLA_DIV32 +*\*\ - RCC_PLLA_DIV33 +*\*\ - RCC_PLLA_DIV34 +*\*\ - RCC_PLLA_DIV35 +*\*\ - RCC_PLLA_DIV36 +*\*\ - RCC_PLLA_DIV37 +*\*\ - RCC_PLLA_DIV38 +*\*\ - RCC_PLLA_DIV39 +*\*\ - RCC_PLLA_DIV40 +*\*\ - RCC_PLLA_DIV41 +*\*\ - RCC_PLLA_DIV42 +*\*\ - RCC_PLLA_DIV43 +*\*\ - RCC_PLLA_DIV44 +*\*\ - RCC_PLLA_DIV45 +*\*\ - RCC_PLLA_DIV46 +*\*\ - RCC_PLLA_DIV47 +*\*\ - RCC_PLLA_DIV48 +*\*\ - RCC_PLLA_DIV49 +*\*\ - RCC_PLLA_DIV50 +*\*\ - RCC_PLLA_DIV51 +*\*\ - RCC_PLLA_DIV52 +*\*\ - RCC_PLLA_DIV53 +*\*\ - RCC_PLLA_DIV54 +*\*\ - RCC_PLLA_DIV55 +*\*\ - RCC_PLLA_DIV56 +*\*\ - RCC_PLLA_DIV57 +*\*\ - RCC_PLLA_DIV58 +*\*\ - RCC_PLLA_DIV59 +*\*\ - RCC_PLLA_DIV60 +*\*\ - RCC_PLLA_DIV61 +*\*\ - RCC_PLLA_DIV62 +*\*\ - RCC_PLLA_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL2ADivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL2DIV; + /* Clear RCC_PLL2A_DIV bits */ + reg_value &= RCC_PLLA_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL2DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL3CDivider . +*\*\fun Configure PLL3 divider value to PLL3C. +*\*\param CLK_divider +*\*\ - RCC_PLLC_DIV1 +*\*\ - RCC_PLLC_DIV2 +*\*\ - RCC_PLLC_DIV3 +*\*\ - RCC_PLLC_DIV4 +*\*\ - RCC_PLLC_DIV5 +*\*\ - RCC_PLLC_DIV6 +*\*\ - RCC_PLLC_DIV7 +*\*\ - RCC_PLLC_DIV8 +*\*\ - RCC_PLLC_DIV9 +*\*\ - RCC_PLLC_DIV10 +*\*\ - RCC_PLLC_DIV11 +*\*\ - RCC_PLLC_DIV12 +*\*\ - RCC_PLLC_DIV13 +*\*\ - RCC_PLLC_DIV14 +*\*\ - RCC_PLLC_DIV15 +*\*\ - RCC_PLLC_DIV16 +*\*\ - RCC_PLLC_DIV17 +*\*\ - RCC_PLLC_DIV18 +*\*\ - RCC_PLLC_DIV19 +*\*\ - RCC_PLLC_DIV20 +*\*\ - RCC_PLLC_DIV21 +*\*\ - RCC_PLLC_DIV22 +*\*\ - RCC_PLLC_DIV23 +*\*\ - RCC_PLLC_DIV24 +*\*\ - RCC_PLLC_DIV25 +*\*\ - RCC_PLLC_DIV26 +*\*\ - RCC_PLLC_DIV27 +*\*\ - RCC_PLLC_DIV28 +*\*\ - RCC_PLLC_DIV29 +*\*\ - RCC_PLLC_DIV30 +*\*\ - RCC_PLLC_DIV31 +*\*\ - RCC_PLLC_DIV32 +*\*\ - RCC_PLLC_DIV33 +*\*\ - RCC_PLLC_DIV34 +*\*\ - RCC_PLLC_DIV35 +*\*\ - RCC_PLLC_DIV36 +*\*\ - RCC_PLLC_DIV37 +*\*\ - RCC_PLLC_DIV38 +*\*\ - RCC_PLLC_DIV39 +*\*\ - RCC_PLLC_DIV40 +*\*\ - RCC_PLLC_DIV41 +*\*\ - RCC_PLLC_DIV42 +*\*\ - RCC_PLLC_DIV43 +*\*\ - RCC_PLLC_DIV44 +*\*\ - RCC_PLLC_DIV45 +*\*\ - RCC_PLLC_DIV46 +*\*\ - RCC_PLLC_DIV47 +*\*\ - RCC_PLLC_DIV48 +*\*\ - RCC_PLLC_DIV49 +*\*\ - RCC_PLLC_DIV50 +*\*\ - RCC_PLLC_DIV51 +*\*\ - RCC_PLLC_DIV52 +*\*\ - RCC_PLLC_DIV53 +*\*\ - RCC_PLLC_DIV54 +*\*\ - RCC_PLLC_DIV55 +*\*\ - RCC_PLLC_DIV56 +*\*\ - RCC_PLLC_DIV57 +*\*\ - RCC_PLLC_DIV58 +*\*\ - RCC_PLLC_DIV59 +*\*\ - RCC_PLLC_DIV60 +*\*\ - RCC_PLLC_DIV61 +*\*\ - RCC_PLLC_DIV62 +*\*\ - RCC_PLLC_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL3CDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL3DIV; + /* Clear RCC_PLL3C_DIV bits */ + reg_value &= RCC_PLLC_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL3DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL3BDivider . +*\*\fun Configure PLL3 divider value to PLL3B. +*\*\param CLK_divider +*\*\ - RCC_PLLB_DIV1 +*\*\ - RCC_PLLB_DIV2 +*\*\ - RCC_PLLB_DIV3 +*\*\ - RCC_PLLB_DIV4 +*\*\ - RCC_PLLB_DIV5 +*\*\ - RCC_PLLB_DIV6 +*\*\ - RCC_PLLB_DIV7 +*\*\ - RCC_PLLB_DIV8 +*\*\ - RCC_PLLB_DIV9 +*\*\ - RCC_PLLB_DIV10 +*\*\ - RCC_PLLB_DIV11 +*\*\ - RCC_PLLB_DIV12 +*\*\ - RCC_PLLB_DIV13 +*\*\ - RCC_PLLB_DIV14 +*\*\ - RCC_PLLB_DIV15 +*\*\ - RCC_PLLB_DIV16 +*\*\ - RCC_PLLB_DIV17 +*\*\ - RCC_PLLB_DIV18 +*\*\ - RCC_PLLB_DIV19 +*\*\ - RCC_PLLB_DIV20 +*\*\ - RCC_PLLB_DIV21 +*\*\ - RCC_PLLB_DIV22 +*\*\ - RCC_PLLB_DIV23 +*\*\ - RCC_PLLB_DIV24 +*\*\ - RCC_PLLB_DIV25 +*\*\ - RCC_PLLB_DIV26 +*\*\ - RCC_PLLB_DIV27 +*\*\ - RCC_PLLB_DIV28 +*\*\ - RCC_PLLB_DIV29 +*\*\ - RCC_PLLB_DIV30 +*\*\ - RCC_PLLB_DIV31 +*\*\ - RCC_PLLB_DIV32 +*\*\ - RCC_PLLB_DIV33 +*\*\ - RCC_PLLB_DIV34 +*\*\ - RCC_PLLB_DIV35 +*\*\ - RCC_PLLB_DIV36 +*\*\ - RCC_PLLB_DIV37 +*\*\ - RCC_PLLB_DIV38 +*\*\ - RCC_PLLB_DIV39 +*\*\ - RCC_PLLB_DIV40 +*\*\ - RCC_PLLB_DIV41 +*\*\ - RCC_PLLB_DIV42 +*\*\ - RCC_PLLB_DIV43 +*\*\ - RCC_PLLB_DIV44 +*\*\ - RCC_PLLB_DIV45 +*\*\ - RCC_PLLB_DIV46 +*\*\ - RCC_PLLB_DIV47 +*\*\ - RCC_PLLB_DIV48 +*\*\ - RCC_PLLB_DIV49 +*\*\ - RCC_PLLB_DIV50 +*\*\ - RCC_PLLB_DIV51 +*\*\ - RCC_PLLB_DIV52 +*\*\ - RCC_PLLB_DIV53 +*\*\ - RCC_PLLB_DIV54 +*\*\ - RCC_PLLB_DIV55 +*\*\ - RCC_PLLB_DIV56 +*\*\ - RCC_PLLB_DIV57 +*\*\ - RCC_PLLB_DIV58 +*\*\ - RCC_PLLB_DIV59 +*\*\ - RCC_PLLB_DIV60 +*\*\ - RCC_PLLB_DIV61 +*\*\ - RCC_PLLB_DIV62 +*\*\ - RCC_PLLB_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL3BDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL3DIV; + /* Clear RCC_PLL3B_DIV bits */ + reg_value &= RCC_PLLB_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL3DIV = reg_value; +} + +/** +*\*\name RCC_ConfigPLL3ADivider . +*\*\fun Configure PLL3 divider value to PLL3A. +*\*\param CLK_divider +*\*\ - RCC_PLLA_DIV1 +*\*\ - RCC_PLLA_DIV2 +*\*\ - RCC_PLLA_DIV3 +*\*\ - RCC_PLLA_DIV4 +*\*\ - RCC_PLLA_DIV5 +*\*\ - RCC_PLLA_DIV6 +*\*\ - RCC_PLLA_DIV7 +*\*\ - RCC_PLLA_DIV8 +*\*\ - RCC_PLLA_DIV9 +*\*\ - RCC_PLLA_DIV10 +*\*\ - RCC_PLLA_DIV11 +*\*\ - RCC_PLLA_DIV12 +*\*\ - RCC_PLLA_DIV13 +*\*\ - RCC_PLLA_DIV14 +*\*\ - RCC_PLLA_DIV15 +*\*\ - RCC_PLLA_DIV16 +*\*\ - RCC_PLLA_DIV17 +*\*\ - RCC_PLLA_DIV18 +*\*\ - RCC_PLLA_DIV19 +*\*\ - RCC_PLLA_DIV20 +*\*\ - RCC_PLLA_DIV21 +*\*\ - RCC_PLLA_DIV22 +*\*\ - RCC_PLLA_DIV23 +*\*\ - RCC_PLLA_DIV24 +*\*\ - RCC_PLLA_DIV25 +*\*\ - RCC_PLLA_DIV26 +*\*\ - RCC_PLLA_DIV27 +*\*\ - RCC_PLLA_DIV28 +*\*\ - RCC_PLLA_DIV29 +*\*\ - RCC_PLLA_DIV30 +*\*\ - RCC_PLLA_DIV31 +*\*\ - RCC_PLLA_DIV32 +*\*\ - RCC_PLLA_DIV33 +*\*\ - RCC_PLLA_DIV34 +*\*\ - RCC_PLLA_DIV35 +*\*\ - RCC_PLLA_DIV36 +*\*\ - RCC_PLLA_DIV37 +*\*\ - RCC_PLLA_DIV38 +*\*\ - RCC_PLLA_DIV39 +*\*\ - RCC_PLLA_DIV40 +*\*\ - RCC_PLLA_DIV41 +*\*\ - RCC_PLLA_DIV42 +*\*\ - RCC_PLLA_DIV43 +*\*\ - RCC_PLLA_DIV44 +*\*\ - RCC_PLLA_DIV45 +*\*\ - RCC_PLLA_DIV46 +*\*\ - RCC_PLLA_DIV47 +*\*\ - RCC_PLLA_DIV48 +*\*\ - RCC_PLLA_DIV49 +*\*\ - RCC_PLLA_DIV50 +*\*\ - RCC_PLLA_DIV51 +*\*\ - RCC_PLLA_DIV52 +*\*\ - RCC_PLLA_DIV53 +*\*\ - RCC_PLLA_DIV54 +*\*\ - RCC_PLLA_DIV55 +*\*\ - RCC_PLLA_DIV56 +*\*\ - RCC_PLLA_DIV57 +*\*\ - RCC_PLLA_DIV58 +*\*\ - RCC_PLLA_DIV59 +*\*\ - RCC_PLLA_DIV60 +*\*\ - RCC_PLLA_DIV61 +*\*\ - RCC_PLLA_DIV62 +*\*\ - RCC_PLLA_DIV63 +*\*\return none. +**/ +void RCC_ConfigPLL3ADivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->PLL3DIV; + /* Clear RCC_PLL3A_DIV bits */ + reg_value &= RCC_PLLA_DIV_MASK; + /* Set the DIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->PLL3DIV = reg_value; +} + +/** +*\*\name RCC_ConfigAXIHyperDivider. +*\*\fun Obtained by dividing the m7_hyp_div_clk. +*\*\param CLK_divider +*\*\ - RCC_AXICLK_HYP_DIV1 +*\*\ - RCC_AXICLK_HYP_DIV2 +*\*\ - RCC_AXICLK_HYP_DIV4 +*\*\ - RCC_AXICLK_HYP_DIV8 +*\*\ - RCC_AXICLK_HYP_DIV16 +*\*\ - RCC_AXICLK_HYP_DIV32 +*\*\ - RCC_AXICLK_HYP_DIV64 +*\*\ - RCC_AXICLK_HYP_DIV128 +*\*\ - RCC_AXICLK_HYP_DIV256 +*\*\ - RCC_AXICLK_HYP_DIV512 +*\*\return none. +**/ +void RCC_ConfigAXIHyperDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear AXIHYPDIV bits */ + reg_value &= RCC_AXICLK_HYP_DIV_MASK; + /* Set the AXIHYPDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigM7HyperDivider . +*\*\fun Configure PLL2A divider value to m7_hyp_div_clk. +*\*\param CLK_divider +*\*\ - RCC_M7CLK_HYP_DIV1 +*\*\ - RCC_M7CLK_HYP_DIV2 +*\*\ - RCC_M7CLK_HYP_DIV4 +*\*\ - RCC_M7CLK_HYP_DIV8 +*\*\ - RCC_M7CLK_HYP_DIV16 +*\*\ - RCC_M7CLK_HYP_DIV32 +*\*\ - RCC_M7CLK_HYP_DIV64 +*\*\ - RCC_M7CLK_HYP_DIV128 +*\*\ - RCC_M7CLK_HYP_DIV256 +*\*\ - RCC_M7CLK_HYP_DIV512 +*\*\return none. +**/ +void RCC_ConfigM7HyperDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear M7HYPDIV bits */ + reg_value &= RCC_M7CLK_HYP_DIV_MASK; + /* Set the M7HYPDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigAXIclkDivider . +*\*\fun Obtained by dividing the sys_div_clk. +*\*\param CLK_divider +*\*\ - RCC_AXICLK_DIV1 +*\*\ - RCC_AXICLK_DIV2 +*\*\ - RCC_AXICLK_DIV4 +*\*\ - RCC_AXICLK_DIV8 +*\*\ - RCC_AXICLK_DIV16 +*\*\ - RCC_AXICLK_DIV32 +*\*\ - RCC_AXICLK_DIV64 +*\*\ - RCC_AXICLK_DIV128 +*\*\ - RCC_AXICLK_DIV256 +*\*\ - RCC_AXICLK_DIV512 +*\*\return none. +**/ +void RCC_ConfigAXIclkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear AXIDIV bits */ + reg_value &= RCC_AXICLK_DIV_MASK; + /* Set the AXIDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigSysbusDivider . +*\*\fun Configure sys_div_clk divider value to sys_bus_div_clk. +*\*\param CLK_divider +*\*\ - RCC_BUSCLK_DIV1 +*\*\ - RCC_BUSCLK_DIV2 +*\*\ - RCC_BUSCLK_DIV4 +*\*\ - RCC_BUSCLK_DIV8 +*\*\ - RCC_BUSCLK_DIV16 +*\*\ - RCC_BUSCLK_DIV32 +*\*\ - RCC_BUSCLK_DIV64 +*\*\ - RCC_BUSCLK_DIV128 +*\*\ - RCC_BUSCLK_DIV256 +*\*\ - RCC_BUSCLK_DIV512 +*\*\return none. +**/ +void RCC_ConfigSysbusDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear BUSDIV bits */ + reg_value &= RCC_BUSCLK_DIV_MASK; + /* Set the BUSDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigSysclkDivider . +*\*\fun Configure sys_clk divider value to sys_div_clk. +*\*\param CLK_divider +*\*\ - RCC_SYSCLK_DIV1 +*\*\ - RCC_SYSCLK_DIV2 +*\*\ - RCC_SYSCLK_DIV4 +*\*\ - RCC_SYSCLK_DIV8 +*\*\ - RCC_SYSCLK_DIV16 +*\*\ - RCC_SYSCLK_DIV32 +*\*\ - RCC_SYSCLK_DIV64 +*\*\ - RCC_SYSCLK_DIV128 +*\*\ - RCC_SYSCLK_DIV256 +*\*\ - RCC_SYSCLK_DIV512 +*\*\return none. +**/ +void RCC_ConfigSysclkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV1; + /* Clear SCLKDIV bits */ + reg_value &= RCC_SYSCLK_DIV_MASK; + /* Set the SCLKDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->SYSBUSDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigAPBclkDivider . +*\*\fun Configure AHB1 clock divider value to APB1 clock. +*\*\param APB1_divider +*\*\ - RCC_APB1CLK_DIV1 +*\*\ - RCC_APB1CLK_DIV2 +*\*\ - RCC_APB1CLK_DIV4 +*\*\ - RCC_APB1CLK_DIV8 +*\*\ - RCC_APB1CLK_DIV16 +*\*\param APB2_divider +*\*\ - RCC_APB2CLK_DIV1 +*\*\ - RCC_APB2CLK_DIV2 +*\*\ - RCC_APB2CLK_DIV4 +*\*\ - RCC_APB2CLK_DIV8 +*\*\ - RCC_APB2CLK_DIV16 +*\*\param APB5_divider +*\*\ - RCC_APB5CLK_DIV1 +*\*\ - RCC_APB5CLK_DIV2 +*\*\ - RCC_APB5CLK_DIV4 +*\*\ - RCC_APB5CLK_DIV8 +*\*\ - RCC_APB5CLK_DIV16 +*\*\param APB6_divider +*\*\ - RCC_APB6CLK_DIV1 +*\*\ - RCC_APB6CLK_DIV2 +*\*\ - RCC_APB6CLK_DIV4 +*\*\ - RCC_APB6CLK_DIV8 +*\*\ - RCC_APB6CLK_DIV16 +*\*\return none. +**/ +void RCC_ConfigAPBclkDivider(uint32_t APB1_divider, uint32_t APB2_divider, uint32_t APB5_divider, uint32_t APB6_divider) +{ + uint32_t reg_value; + + reg_value = RCC->SYSBUSDIV2; + /* Clear APB1DIV bits */ + reg_value &= RCC_APBCLK_DIV_MASK; + /* Set the APB1DIV bits */ + reg_value |= (APB1_divider | APB2_divider | APB5_divider | APB6_divider); + /* Store the new value */ + RCC->SYSBUSDIV2 = reg_value; +} + + +/** +*\*\name RCC_EnableAHB1PeriphReset1. +*\*\fun AHB1 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB1_PERIPHRST_SDMMC2 +*\*\ - RCC_AHB1_PERIPHRST_SDHOST2 +*\*\ - RCC_AHB1_PERIPHRST_USB2WRAP +*\*\ - RCC_AHB1_PERIPHRST_USB2POR +*\*\ - RCC_AHB1_PERIPHRST_USB2 +*\*\ - RCC_AHB1_PERIPHRST_DMAMUX1 +*\*\ - RCC_AHB1_PERIPHRST_ADC1 +*\*\return none. +**/ +void RCC_EnableAHB1PeriphReset1(uint32_t AHB_periph) +{ + RCC->AHB1RST1 |= AHB_periph; + RCC->AHB1RST1 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAHB1PeriphReset2. +*\*\fun AHB1 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB1_PERIPHRST_ETH2 +*\*\return none. +**/ +void RCC_EnableAHB1PeriphReset2(uint32_t AHB_periph) +{ + RCC->AHB1RST2 |= AHB_periph; + RCC->AHB1RST2 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAHB1PeriphReset3. +*\*\fun AHB1 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB1_PERIPHRST_ECCMAC +*\*\ - RCC_AHB1_PERIPHRST_DMA1 +*\*\ - RCC_AHB1_PERIPHRST_DMA2 +*\*\ - RCC_AHB1_PERIPHRST_DMA3 +*\*\return none. +**/ +void RCC_EnableAHB1PeriphReset3(uint32_t AHB_periph) +{ + RCC->AHB1RST3 |= AHB_periph; + RCC->AHB1RST3 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAHB1PeriphReset4. +*\*\fun AHB1 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB1_PERIPHRST_ADC2 +*\*\ - RCC_AHB1_PERIPHRST_ADC3 +*\*\return none. +**/ +void RCC_EnableAHB1PeriphReset4(uint32_t AHB_periph) +{ + RCC->AHB1RST4 |= AHB_periph; + RCC->AHB1RST4 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAPB1PeriphReset1. +*\*\fun APB1 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB1_PERIPHRST_BTIM1 +*\*\ - RCC_APB1_PERIPHRST_BTIM2 +*\*\ - RCC_APB1_PERIPHRST_BTIM3 +*\*\ - RCC_APB1_PERIPHRST_BTIM4 +*\*\ - RCC_APB1_PERIPHRST_GTIMB1 +*\*\ - RCC_APB1_PERIPHRST_GTIMB2 +*\*\ - RCC_APB1_PERIPHRST_GTIMB3 +*\*\ - RCC_APB1_PERIPHRST_GTIMA4 +*\*\return none. +**/ +void RCC_EnableAPB1PeriphReset1(uint32_t APB_periph) +{ + RCC->APB1RST1 |= APB_periph; + RCC->APB1RST1 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB1PeriphReset2. +*\*\fun APB1 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB1_PERIPHRST_GTIMA5 +*\*\ - RCC_APB1_PERIPHRST_GTIMA6 +*\*\ - RCC_APB1_PERIPHRST_GTIMA7 +*\*\ - RCC_APB1_PERIPHRST_SPI3 +*\*\ - RCC_APB1_PERIPHRST_DAC12 +*\*\ - RCC_APB1_PERIPHRST_WWDG2 +*\*\return none. +**/ +void RCC_EnableAPB1PeriphReset2(uint32_t APB_periph) +{ + RCC->APB1RST2 |= APB_periph; + RCC->APB1RST2 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB1PeriphReset3. +*\*\fun APB1 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB1_PERIPHRST_USART1 +*\*\ - RCC_APB1_PERIPHRST_USART2 +*\*\ - RCC_APB1_PERIPHRST_USART3 +*\*\ - RCC_APB1_PERIPHRST_USART4 +*\*\ - RCC_APB1_PERIPHRST_UART9 +*\*\ - RCC_APB1_PERIPHRST_UART10 +*\*\ - RCC_APB1_PERIPHRST_UART11 +*\*\ - RCC_APB1_PERIPHRST_UART12 +*\*\return none. +**/ +void RCC_EnableAPB1PeriphReset3(uint32_t APB_periph) +{ + RCC->APB1RST3 |= APB_periph; + RCC->APB1RST3 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB1PeriphReset4. +*\*\fun APB1 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB1_PERIPHRST_I2S3 +*\*\ - RCC_APB1_PERIPHRST_I2S4 +*\*\ - RCC_APB1_PERIPHRST_I2C1 +*\*\ - RCC_APB1_PERIPHRST_I2C2 +*\*\ - RCC_APB1_PERIPHRST_I2C3 +*\*\return none. +**/ +void RCC_EnableAPB1PeriphReset4(uint32_t APB_periph) +{ + RCC->APB1RST4 |= APB_periph; + RCC->APB1RST4 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB1PeriphReset5. +*\*\fun APB1 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB1_PERIPHRST_FDCAN1 +*\*\ - RCC_APB1_PERIPHRST_FDCAN2 +*\*\ - RCC_APB1_PERIPHRST_FDCAN5 +*\*\ - RCC_APB1_PERIPHRST_FDCAN6 +*\*\ - RCC_APB1_PERIPHRST_CAHI +*\*\ - RCC_APB1_PERIPHRST_CAHD +*\*\return none. +**/ +void RCC_EnableAPB1PeriphReset5(uint32_t APB_periph) +{ + RCC->APB1RST5 |= APB_periph; + RCC->APB1RST5 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAHB2PeriphReset1. +*\*\fun AHB2 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB2_PERIPHRST_DAC56 +*\*\ - RCC_AHB2_PERIPHRST_DAC34 +*\*\ - RCC_AHB2_PERIPHRST_USB1WRAP +*\*\ - RCC_AHB2_PERIPHRST_USB1POR +*\*\ - RCC_AHB2_PERIPHRST_USB1 +*\*\ - RCC_AHB2_PERIPHRST_ETH1 +*\*\ - RCC_AHB2_PERIPHRST_ECCM2 +*\*\ - RCC_AHB2_PERIPHRST_CORDIC +*\*\ - RCC_AHB2_PERIPHRST_SDPU +*\*\ - RCC_AHB2_PERIPHRST_FMAC +*\*\return none. +**/ +void RCC_EnableAHB2PeriphReset1(uint32_t AHB_periph) +{ + RCC->AHB2RST1 |= AHB_periph; + RCC->AHB2RST1 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAPB2PeriphReset1. +*\*\fun APB2 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB2_PERIPHRST_ATIM1 +*\*\ - RCC_APB2_PERIPHRST_ATIM2 +*\*\ - RCC_APB2_PERIPHRST_GTIMA1 +*\*\ - RCC_APB2_PERIPHRST_GTIMA2 +*\*\ - RCC_APB2_PERIPHRST_GTIMA3 +*\*\ - RCC_APB2_PERIPHRST_SHRTIM1 +*\*\ - RCC_APB2_PERIPHRST_SHRTIM2 +*\*\return none. +**/ +void RCC_EnableAPB2PeriphReset1(uint32_t APB_periph) +{ + RCC->APB2RST1 |= APB_periph; + RCC->APB2RST1 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB2PeriphReset2. +*\*\fun APB2 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB2_PERIPHRST_I2S1 +*\*\ - RCC_APB2_PERIPHRST_I2S2 +*\*\ - RCC_APB2_PERIPHRST_SPI1 +*\*\ - RCC_APB2_PERIPHRST_SPI2 +*\*\ - RCC_APB2_PERIPHRST_DSMU +*\*\ - RCC_APB2_PERIPHRST_I2C4 +*\*\ - RCC_APB2_PERIPHRST_I2C5 +*\*\ - RCC_APB2_PERIPHRST_I2C6 +*\*\return none. +**/ +void RCC_EnableAPB2PeriphReset2(uint32_t APB_periph) +{ + RCC->APB2RST2 |= APB_periph; + RCC->APB2RST2 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB2PeriphReset3. +*\*\fun APB2 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB2_PERIPHRST_USART5 +*\*\ - RCC_APB2_PERIPHRST_USART6 +*\*\ - RCC_APB2_PERIPHRST_USART7 +*\*\ - RCC_APB2_PERIPHRST_USART8 +*\*\ - RCC_APB2_PERIPHRST_UART13 +*\*\ - RCC_APB2_PERIPHRST_UART14 +*\*\ - RCC_APB2_PERIPHRST_UART15 +*\*\return none. +**/ +void RCC_EnableAPB2PeriphReset3(uint32_t APB_periph) +{ + RCC->APB2RST3 |= APB_periph; + RCC->APB2RST3 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB2PeriphReset4. +*\*\fun APB2 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB2_PERIPHRST_FDCAN3 +*\*\ - RCC_APB2_PERIPHRST_FDCAN4 +*\*\ - RCC_APB2_PERIPHRST_FDCAN7 +*\*\ - RCC_APB2_PERIPHRST_FDCAN8 +*\*\return none. +**/ +void RCC_EnableAPB2PeriphReset4(uint32_t APB_periph) +{ + RCC->APB2RST4 |= APB_periph; + RCC->APB2RST4 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAHB5PeriphReset1. +*\*\fun AHB5 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB5_PERIPHRST_GPIOA +*\*\ - RCC_AHB5_PERIPHRST_GPIOB +*\*\ - RCC_AHB5_PERIPHRST_GPIOC +*\*\ - RCC_AHB5_PERIPHRST_GPIOD +*\*\ - RCC_AHB5_PERIPHRST_GPIOE +*\*\ - RCC_AHB5_PERIPHRST_GPIOF +*\*\ - RCC_AHB5_PERIPHRST_GPIOG +*\*\ - RCC_AHB5_PERIPHRST_GPIOH +*\*\return none. +**/ +void RCC_EnableAHB5PeriphReset1(uint32_t AHB_periph) +{ + RCC->AHB5RST1 |= AHB_periph; + RCC->AHB5RST1 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAHB5PeriphReset2. +*\*\fun AHB5 peripheral reset. +*\*\param AHB_periph specifies the AHB peripheral to reset. +*\*\ - RCC_AHB5_PERIPHRST_GPIOI +*\*\ - RCC_AHB5_PERIPHRST_GPIOJ +*\*\ - RCC_AHB5_PERIPHRST_GPIOK +*\*\ - RCC_AHB5_PERIPHRST_ECCM3 +*\*\ - RCC_AHB5_PERIPHRST_PWR +*\*\ - RCC_AHB5_PERIPHRST_CRC +*\*\ - RCC_AHB5_PERIPHRST_SEMA4 +*\*\ - RCC_AHB5_PERIPHRST_AFIO +*\*\return none. +**/ +void RCC_EnableAHB5PeriphReset2(uint32_t AHB_periph) +{ + RCC->AHB5RST2 |= AHB_periph; + RCC->AHB5RST2 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableAPB5PeriphReset1. +*\*\fun APB5 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB5_PERIPHRST_ATIM3 +*\*\ - RCC_APB5_PERIPHRST_ATIM4 +*\*\ - RCC_APB5_PERIPHRST_SPI4 +*\*\ - RCC_APB5_PERIPHRST_SPI5 +*\*\ - RCC_APB5_PERIPHRST_SPI6 +*\*\ - RCC_APB5_PERIPHRST_SPI7 +*\*\return none. +**/ +void RCC_EnableAPB5PeriphReset1(uint32_t APB_periph) +{ + RCC->APB5RST1 |= APB_periph; + RCC->APB5RST1 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAPB5PeriphReset2. +*\*\fun APB5 peripheral reset. +*\*\param APB_periph specifies the APB peripheral to reset. +*\*\ - RCC_APB5_PERIPHRST_I2C7 +*\*\ - RCC_APB5_PERIPHRST_I2C8 +*\*\ - RCC_APB5_PERIPHRST_I2C9 +*\*\ - RCC_APB5_PERIPHRST_I2C10 +*\*\return none. +**/ +void RCC_EnableAPB5PeriphReset2(uint32_t APB_periph) +{ + RCC->APB5RST2 |= APB_periph; + RCC->APB5RST2 &= ~APB_periph; +} + +/** +*\*\name RCC_EnableAXIPeriphReset1. +*\*\fun AXI/AHB6/APB6 peripheral reset. +*\*\param AXI_periph specifies the AXI/AHB6/APB6 peripheral to reset. +*\*\ - RCC_AXI_PERIPHRST_JPEGD +*\*\ - RCC_AXI_PERIPHRST_JPEGE +*\*\ - RCC_AXI_PERIPHRST_DMAMUX2 +*\*\ - RCC_AXI_PERIPHRST_MDMA +*\*\ - RCC_AXI_PERIPHRST_SDMMC1 +*\*\ - RCC_AXI_PERIPHRST_SDHOST1 +*\*\ - RCC_AXI_PERIPHRST_ECCM1 +*\*\ - RCC_AXI_PERIPHRST_OTPC +*\*\return none. +**/ +void RCC_EnableAXIPeriphReset1(uint32_t AXI_periph) +{ + RCC->AXIRST1 |= AXI_periph; + RCC->AXIRST1 &= ~AXI_periph; +} + +/** +*\*\name RCC_EnableAXIPeriphReset2. +*\*\fun AXI/AHB6/APB6 peripheral reset. +*\*\param AXI_periph specifies the AXI/AHB6/APB6 peripheral to reset. +*\*\ - RCC_AXI_PERIPHRST_DSICFG +*\*\ - RCC_AXI_PERIPHRST_DSI +*\*\ - RCC_AXI_PERIPHRST_LCDC +*\*\ - RCC_AXI_PERIPHRST_DVP1 +*\*\ - RCC_AXI_PERIPHRST_DVP2 +*\*\ - RCC_AXI_PERIPHRST_WWDG1 +*\*\return none. +**/ +void RCC_EnableAXIPeriphReset2(uint32_t AXI_periph) +{ + RCC->AXIRST2 |= AXI_periph; + RCC->AXIRST2 &= ~AXI_periph; +} + +/** +*\*\name RCC_EnableAXIPeriphReset3. +*\*\fun AXI/AHB6/APB6 peripheral reset. +*\*\param AXI_periph specifies the AXI/AHB6/APB6 peripheral to reset. +*\*\ - RCC_AXI_PERIPHRST_GPU +*\*\return none. +**/ +void RCC_EnableAXIPeriphReset3(uint32_t AXI_periph) +{ + RCC->AXIRST3 |= AXI_periph; + RCC->AXIRST3 &= ~AXI_periph; +} + +/** +*\*\name RCC_EnableAXIPeriphReset4. +*\*\fun AXI/AHB6/APB6 peripheral reset. +*\*\param AXI_periph specifies the AXI/AHB6/APB6 peripheral to reset. +*\*\ - RCC_AXI_PERIPHRST_XSPI1 +*\*\ - RCC_AXI_PERIPHRST_XSPI2 +*\*\ - RCC_AXI_PERIPHRST_FEMCCFG +*\*\ - RCC_AXI_PERIPHRST_FEMC +*\*\ - RCC_AXI_PERIPHRST_SDRAM +*\*\return none. +**/ +void RCC_EnableAXIPeriphReset4(uint32_t AXI_periph) +{ + RCC->AXIRST4 |= AXI_periph; + RCC->AXIRST4 &= ~AXI_periph; +} + +/** +*\*\name RCC_EnableAHB9PeriphReset1. +*\*\fun AHB9 peripheral reset. +*\*\param AHB_periph specifies the AHB9 peripheral to reset. +*\*\ - RCC_AHB9_PERIPHRST_ESC +*\*\return none. +**/ +void RCC_EnableAHB9PeriphReset1(uint32_t AHB_periph) +{ + RCC->AHB9RST1 |= AHB_periph; + RCC->AHB9RST1 &= ~AHB_periph; +} + +/** +*\*\name RCC_EnableRDPeriphReset1. +*\*\fun Retention domain peripheral reset. +*\*\param RD_periph specifies the Retention domain peripheral to reset. +*\*\ - RCC_RD_PERIPHRST_LPTIM1 +*\*\ - RCC_RD_PERIPHRST_LPTIM2 +*\*\ - RCC_RD_PERIPHRST_LPTIM3 +*\*\ - RCC_RD_PERIPHRST_LPTIM4 +*\*\ - RCC_RD_PERIPHRST_LPTIM5 +*\*\ - RCC_RD_PERIPHRST_LPUART1 +*\*\ - RCC_RD_PERIPHRST_LPUART2 +*\*\return none. +**/ +void RCC_EnableRDPeriphReset1(uint32_t RD_periph) +{ + RCC->RDRST1 |= RD_periph; + RCC->RDRST1 &= ~RD_periph; +} + +/** +*\*\name RCC_EnableRDPeriphReset2. +*\*\fun Retention domain peripheral reset. +*\*\param RD_periph specifies the Retention domain peripheral to reset. +*\*\ - RCC_RD_PERIPHRST_COMP +*\*\return none. +**/ +void RCC_EnableRDPeriphReset2(uint32_t RD_periph) +{ + RCC->RDRST2 |= RD_periph; + RCC->RDRST2 &= ~RD_periph; +} + +/** +*\*\name RCC_EnableAHB1PeriphClk1. +*\*\fun Enables the AHB1 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB1_PERIPHEN_M7_SDMMC2 +*\*\ - RCC_AHB1_PERIPHEN_M4_SDMMC2 +*\*\ - RCC_AHB1_PERIPHEN_M7_SDMMC2LP +*\*\ - RCC_AHB1_PERIPHEN_M4_SDMMC2LP +*\*\ - RCC_AHB1_PERIPHEN_M7_USB2 +*\*\ - RCC_AHB1_PERIPHEN_M4_USB2 +*\*\ - RCC_AHB1_PERIPHEN_M7_USB2LP +*\*\ - RCC_AHB1_PERIPHEN_M4_USB2LP +*\*\ - RCC_AHB1_PERIPHEN_M7_DMAMUX1 +*\*\ - RCC_AHB1_PERIPHEN_M4_DMAMUX1 +*\*\ - RCC_AHB1_PERIPHEN_M7_DMAMUX1LP +*\*\ - RCC_AHB1_PERIPHEN_M4_DMAMUX1LP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC1PLL +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC1PLL +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC1PLLLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC1PLLLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC1SYS +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC1SYS +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC1SYSLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC1SYSLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC1BUS +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC1BUS +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC1BUSLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC1BUSLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB1PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB1EN1 |= AHB_periph; + } + else + { + RCC->AHB1EN1 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAHB1PeriphClk2. +*\*\fun Enables the AHB1 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB1_PERIPHEN_M7_ETH2TX +*\*\ - RCC_AHB1_PERIPHEN_M4_ETH2TX +*\*\ - RCC_AHB1_PERIPHEN_M7_ETH2TXLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ETH2TXLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ETH2RX +*\*\ - RCC_AHB1_PERIPHEN_M4_ETH2RX +*\*\ - RCC_AHB1_PERIPHEN_M7_ETH2RXLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ETH2RXLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ETH2MAC +*\*\ - RCC_AHB1_PERIPHEN_M4_ETH2MAC +*\*\ - RCC_AHB1_PERIPHEN_M7_ETH2MACLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ETH2MACLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB1PeriphClk2(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB1EN2 |= AHB_periph; + } + else + { + RCC->AHB1EN2 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAHB1PeriphClk3. +*\*\fun Enables the AHB1 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB1_PERIPHEN_M7_ECCMAC +*\*\ - RCC_AHB1_PERIPHEN_M4_ECCMAC +*\*\ - RCC_AHB1_PERIPHEN_M7_ECCMACLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ECCMACLP +*\*\ - RCC_AHB1_PERIPHEN_M7_DMA1 +*\*\ - RCC_AHB1_PERIPHEN_M4_DMA1 +*\*\ - RCC_AHB1_PERIPHEN_M7_DMA1LP +*\*\ - RCC_AHB1_PERIPHEN_M4_DMA1LP +*\*\ - RCC_AHB1_PERIPHEN_M7_DMA2 +*\*\ - RCC_AHB1_PERIPHEN_M4_DMA2 +*\*\ - RCC_AHB1_PERIPHEN_M7_DMA2LP +*\*\ - RCC_AHB1_PERIPHEN_M4_DMA2LP +*\*\ - RCC_AHB1_PERIPHEN_M7_DMA3 +*\*\ - RCC_AHB1_PERIPHEN_M4_DMA3 +*\*\ - RCC_AHB1_PERIPHEN_M7_DMA3LP +*\*\ - RCC_AHB1_PERIPHEN_M4_DMA3LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB1PeriphClk3(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB1EN3 |= AHB_periph; + } + else + { + RCC->AHB1EN3 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAHB1PeriphClk4. +*\*\fun Enables the AHB1 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC2PLL +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC2PLL +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC2PLLLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC2PLLLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC2SYS +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC2SYS +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC2SYSLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC2SYSLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC2BUS +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC2BUS +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC2BUSLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC2BUSLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC3PLL +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC3PLL +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC3PLLLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC3PLLLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC3SYS +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC3SYS +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC3SYSLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC3SYSLP +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC3BUS +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC3BUS +*\*\ - RCC_AHB1_PERIPHEN_M7_ADC3BUSLP +*\*\ - RCC_AHB1_PERIPHEN_M4_ADC3BUSLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB1PeriphClk4(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB1EN4 |= AHB_periph; + } + else + { + RCC->AHB1EN4 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAPB1PeriphClk1. +*\*\fun Enables the APB1 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM1 +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM1 +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM1LP +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM1LP +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM2 +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM2 +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM2LP +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM2LP +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM3 +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM3 +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM3LP +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM3LP +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM4 +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM4 +*\*\ - RCC_APB1_PERIPHEN_M7_BTIM4LP +*\*\ - RCC_APB1_PERIPHEN_M4_BTIM4LP +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMB1 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMB1 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMB1LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMB1LP +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMB2 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMB2 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMB2LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMB2LP +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMB3 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMB3 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMB3LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMB3LP +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA4 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA4 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA4LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA4LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB1PeriphClk1(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB1EN1 |= APB_periph; + } + else + { + RCC->APB1EN1 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB1PeriphClk2. +*\*\fun Enables the APB1 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA5 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA5 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA5LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA5LP +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA6 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA6 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA6LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA6LP +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA7 +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA7 +*\*\ - RCC_APB1_PERIPHEN_M7_GTIMA7LP +*\*\ - RCC_APB1_PERIPHEN_M4_GTIMA7LP +*\*\ - RCC_APB1_PERIPHEN_M7_SPI3 +*\*\ - RCC_APB1_PERIPHEN_M4_SPI3 +*\*\ - RCC_APB1_PERIPHEN_M7_SPI3LP +*\*\ - RCC_APB1_PERIPHEN_M4_SPI3LP +*\*\ - RCC_APB1_PERIPHEN_M7_DAC12 +*\*\ - RCC_APB1_PERIPHEN_M4_DAC12 +*\*\ - RCC_APB1_PERIPHEN_M7_DAC12LP +*\*\ - RCC_APB1_PERIPHEN_M4_DAC12LP +*\*\ - RCC_APB1_PERIPHEN_M7_WWDG2 +*\*\ - RCC_APB1_PERIPHEN_M4_WWDG2 +*\*\ - RCC_APB1_PERIPHEN_M7_WWDG2LP +*\*\ - RCC_APB1_PERIPHEN_M4_WWDG2LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB1PeriphClk2(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB1EN2 |= APB_periph; + } + else + { + RCC->APB1EN2 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB1PeriphClk3. +*\*\fun Enables the APB1 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB1_PERIPHEN_M7_USART1 +*\*\ - RCC_APB1_PERIPHEN_M4_USART1 +*\*\ - RCC_APB1_PERIPHEN_M7_USART1LP +*\*\ - RCC_APB1_PERIPHEN_M4_USART1LP +*\*\ - RCC_APB1_PERIPHEN_M7_USART2 +*\*\ - RCC_APB1_PERIPHEN_M4_USART2 +*\*\ - RCC_APB1_PERIPHEN_M7_USART2LP +*\*\ - RCC_APB1_PERIPHEN_M4_USART2LP +*\*\ - RCC_APB1_PERIPHEN_M7_USART3 +*\*\ - RCC_APB1_PERIPHEN_M4_USART3 +*\*\ - RCC_APB1_PERIPHEN_M7_USART3LP +*\*\ - RCC_APB1_PERIPHEN_M4_USART3LP +*\*\ - RCC_APB1_PERIPHEN_M7_USART4 +*\*\ - RCC_APB1_PERIPHEN_M4_USART4 +*\*\ - RCC_APB1_PERIPHEN_M7_USART4LP +*\*\ - RCC_APB1_PERIPHEN_M4_USART4LP +*\*\ - RCC_APB1_PERIPHEN_M7_UART9 +*\*\ - RCC_APB1_PERIPHEN_M4_UART9 +*\*\ - RCC_APB1_PERIPHEN_M7_UART9LP +*\*\ - RCC_APB1_PERIPHEN_M4_UART9LP +*\*\ - RCC_APB1_PERIPHEN_M7_UART10 +*\*\ - RCC_APB1_PERIPHEN_M4_UART10 +*\*\ - RCC_APB1_PERIPHEN_M7_UART10LP +*\*\ - RCC_APB1_PERIPHEN_M4_UART10LP +*\*\ - RCC_APB1_PERIPHEN_M7_UART11 +*\*\ - RCC_APB1_PERIPHEN_M4_UART11 +*\*\ - RCC_APB1_PERIPHEN_M7_UART11LP +*\*\ - RCC_APB1_PERIPHEN_M4_UART11LP +*\*\ - RCC_APB1_PERIPHEN_M7_UART12 +*\*\ - RCC_APB1_PERIPHEN_M4_UART12 +*\*\ - RCC_APB1_PERIPHEN_M7_UART12LP +*\*\ - RCC_APB1_PERIPHEN_M4_UART12LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB1PeriphClk3(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB1EN3 |= APB_periph; + } + else + { + RCC->APB1EN3 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB1PeriphClk4. +*\*\fun Enables the APB1 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB1_PERIPHEN_M7_I2S3 +*\*\ - RCC_APB1_PERIPHEN_M4_I2S3 +*\*\ - RCC_APB1_PERIPHEN_M7_I2S3LP +*\*\ - RCC_APB1_PERIPHEN_M4_I2S3LP +*\*\ - RCC_APB1_PERIPHEN_M7_I2S4 +*\*\ - RCC_APB1_PERIPHEN_M4_I2S4 +*\*\ - RCC_APB1_PERIPHEN_M7_I2S4LP +*\*\ - RCC_APB1_PERIPHEN_M4_I2S4LP +*\*\ - RCC_APB1_PERIPHEN_M7_I2C1 +*\*\ - RCC_APB1_PERIPHEN_M4_I2C1 +*\*\ - RCC_APB1_PERIPHEN_M7_I2C1LP +*\*\ - RCC_APB1_PERIPHEN_M4_I2C1LP +*\*\ - RCC_APB1_PERIPHEN_M7_I2C2 +*\*\ - RCC_APB1_PERIPHEN_M4_I2C2 +*\*\ - RCC_APB1_PERIPHEN_M7_I2C2LP +*\*\ - RCC_APB1_PERIPHEN_M4_I2C2LP +*\*\ - RCC_APB1_PERIPHEN_M7_I2C3 +*\*\ - RCC_APB1_PERIPHEN_M4_I2C3 +*\*\ - RCC_APB1_PERIPHEN_M7_I2C3LP +*\*\ - RCC_APB1_PERIPHEN_M4_I2C3LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB1PeriphClk4(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB1EN4 |= APB_periph; + } + else + { + RCC->APB1EN4 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB1PeriphClk5. +*\*\fun Enables the APB1 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN1 +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN1 +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN1LP +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN1LP +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN2 +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN2 +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN2LP +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN2LP +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN5 +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN5 +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN5LP +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN5LP +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN6 +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN6 +*\*\ - RCC_APB1_PERIPHEN_M7_FDCAN6LP +*\*\ - RCC_APB1_PERIPHEN_M4_FDCAN6LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB1PeriphClk5(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB1EN5 |= APB_periph; + } + else + { + RCC->APB1EN5 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAHB2PeriphClk1. +*\*\fun Enables the AHB2 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB2_PERIPHEN_M7_USB1 +*\*\ - RCC_AHB2_PERIPHEN_M4_USB1 +*\*\ - RCC_AHB2_PERIPHEN_M7_USB1LP +*\*\ - RCC_AHB2_PERIPHEN_M4_USB1LP +*\*\ - RCC_AHB2_PERIPHEN_M7_ECCM2 +*\*\ - RCC_AHB2_PERIPHEN_M4_ECCM2 +*\*\ - RCC_AHB2_PERIPHEN_M7_ECCM2LP +*\*\ - RCC_AHB2_PERIPHEN_M4_ECCM2LP +*\*\ - RCC_AHB2_PERIPHEN_M7_CORDIC +*\*\ - RCC_AHB2_PERIPHEN_M4_CORDIC +*\*\ - RCC_AHB2_PERIPHEN_M7_CORDICLP +*\*\ - RCC_AHB2_PERIPHEN_M4_CORDICLP +*\*\ - RCC_AHB2_PERIPHEN_M7_SDPU +*\*\ - RCC_AHB2_PERIPHEN_M4_SDPU +*\*\ - RCC_AHB2_PERIPHEN_M7_SDPULP +*\*\ - RCC_AHB2_PERIPHEN_M4_SDPULP +*\*\ - RCC_AHB2_PERIPHEN_M7_FMAC +*\*\ - RCC_AHB2_PERIPHEN_M4_FMAC +*\*\ - RCC_AHB2_PERIPHEN_M7_FMACLP +*\*\ - RCC_AHB2_PERIPHEN_M4_FMACLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB2PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB2EN1 |= AHB_periph; + } + else + { + RCC->AHB2EN1 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAHB2PeriphClk2. +*\*\fun Enables the AHB2 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB2_PERIPHEN_M7_DAC56 +*\*\ - RCC_AHB2_PERIPHEN_M4_DAC56 +*\*\ - RCC_AHB2_PERIPHEN_M7_DAC56LP +*\*\ - RCC_AHB2_PERIPHEN_M4_DAC56LP +*\*\ - RCC_AHB2_PERIPHEN_M7_DAC34 +*\*\ - RCC_AHB2_PERIPHEN_M4_DAC34 +*\*\ - RCC_AHB2_PERIPHEN_M7_DAC34LP +*\*\ - RCC_AHB2_PERIPHEN_M4_DAC34LP +*\*\ - RCC_AHB2_PERIPHEN_M7_ETH1TX +*\*\ - RCC_AHB2_PERIPHEN_M4_ETH1TX +*\*\ - RCC_AHB2_PERIPHEN_M7_ETH1TXLP +*\*\ - RCC_AHB2_PERIPHEN_M4_ETH1TXLP +*\*\ - RCC_AHB2_PERIPHEN_M7_ETH1RX +*\*\ - RCC_AHB2_PERIPHEN_M4_ETH1RX +*\*\ - RCC_AHB2_PERIPHEN_M7_ETH1RXLP +*\*\ - RCC_AHB2_PERIPHEN_M4_ETH1RXLP +*\*\ - RCC_AHB2_PERIPHEN_M7_ETH1MAC +*\*\ - RCC_AHB2_PERIPHEN_M4_ETH1MAC +*\*\ - RCC_AHB2_PERIPHEN_M7_ETH1MACLP +*\*\ - RCC_AHB2_PERIPHEN_M4_ETH1MACLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB2PeriphClk2(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB2EN2 |= AHB_periph; + } + else + { + RCC->AHB2EN2 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAPB2PeriphClk1. +*\*\fun Enables the APB2 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB2_PERIPHEN_M7_ATIM1 +*\*\ - RCC_APB2_PERIPHEN_M4_ATIM1 +*\*\ - RCC_APB2_PERIPHEN_M7_ATIM1LP +*\*\ - RCC_APB2_PERIPHEN_M4_ATIM1LP +*\*\ - RCC_APB2_PERIPHEN_M7_ATIM2 +*\*\ - RCC_APB2_PERIPHEN_M4_ATIM2 +*\*\ - RCC_APB2_PERIPHEN_M7_ATIM2LP +*\*\ - RCC_APB2_PERIPHEN_M4_ATIM2LP +*\*\ - RCC_APB2_PERIPHEN_M7_GTIMA1 +*\*\ - RCC_APB2_PERIPHEN_M4_GTIMA1 +*\*\ - RCC_APB2_PERIPHEN_M7_GTIMA1LP +*\*\ - RCC_APB2_PERIPHEN_M4_GTIMA1LP +*\*\ - RCC_APB2_PERIPHEN_M7_GTIMA2 +*\*\ - RCC_APB2_PERIPHEN_M4_GTIMA2 +*\*\ - RCC_APB2_PERIPHEN_M7_GTIMA2LP +*\*\ - RCC_APB2_PERIPHEN_M4_GTIMA2LP +*\*\ - RCC_APB2_PERIPHEN_M7_GTIMA3 +*\*\ - RCC_APB2_PERIPHEN_M4_GTIMA3 +*\*\ - RCC_APB2_PERIPHEN_M7_GTIMA3LP +*\*\ - RCC_APB2_PERIPHEN_M4_GTIMA3LP +*\*\ - RCC_APB2_PERIPHEN_M7_SHRTIM1 +*\*\ - RCC_APB2_PERIPHEN_M4_SHRTIM1 +*\*\ - RCC_APB2_PERIPHEN_M7_SHRTIM1LP +*\*\ - RCC_APB2_PERIPHEN_M4_SHRTIM1LP +*\*\ - RCC_APB2_PERIPHEN_M7_SHRTIM2 +*\*\ - RCC_APB2_PERIPHEN_M4_SHRTIM2 +*\*\ - RCC_APB2_PERIPHEN_M7_SHRTIM2LP +*\*\ - RCC_APB2_PERIPHEN_M4_SHRTIM2LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB2PeriphClk1(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB2EN1 |= APB_periph; + } + else + { + RCC->APB2EN1 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB2PeriphClk2. +*\*\fun Enables the APB2 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB2_PERIPHEN_M7_I2S1 +*\*\ - RCC_APB2_PERIPHEN_M4_I2S1 +*\*\ - RCC_APB2_PERIPHEN_M7_I2S1LP +*\*\ - RCC_APB2_PERIPHEN_M4_I2S1LP +*\*\ - RCC_APB2_PERIPHEN_M7_I2S2 +*\*\ - RCC_APB2_PERIPHEN_M4_I2S2 +*\*\ - RCC_APB2_PERIPHEN_M7_I2S2LP +*\*\ - RCC_APB2_PERIPHEN_M4_I2S2LP +*\*\ - RCC_APB2_PERIPHEN_M7_SPI1 +*\*\ - RCC_APB2_PERIPHEN_M4_SPI1 +*\*\ - RCC_APB2_PERIPHEN_M7_SPI1LP +*\*\ - RCC_APB2_PERIPHEN_M4_SPI1LP +*\*\ - RCC_APB2_PERIPHEN_M7_SPI2 +*\*\ - RCC_APB2_PERIPHEN_M4_SPI2 +*\*\ - RCC_APB2_PERIPHEN_M7_SPI2LP +*\*\ - RCC_APB2_PERIPHEN_M4_SPI2LP +*\*\ - RCC_APB2_PERIPHEN_M7_DSMU +*\*\ - RCC_APB2_PERIPHEN_M4_DSMU +*\*\ - RCC_APB2_PERIPHEN_M7_DSMULP +*\*\ - RCC_APB2_PERIPHEN_M4_DSMULP +*\*\ - RCC_APB2_PERIPHEN_M7_I2C4 +*\*\ - RCC_APB2_PERIPHEN_M4_I2C4 +*\*\ - RCC_APB2_PERIPHEN_M7_I2C4LP +*\*\ - RCC_APB2_PERIPHEN_M4_I2C4LP +*\*\ - RCC_APB2_PERIPHEN_M7_I2C5 +*\*\ - RCC_APB2_PERIPHEN_M4_I2C5 +*\*\ - RCC_APB2_PERIPHEN_M7_I2C5LP +*\*\ - RCC_APB2_PERIPHEN_M4_I2C5LP +*\*\ - RCC_APB2_PERIPHEN_M7_I2C6 +*\*\ - RCC_APB2_PERIPHEN_M4_I2C6 +*\*\ - RCC_APB2_PERIPHEN_M7_I2C6LP +*\*\ - RCC_APB2_PERIPHEN_M4_I2C6LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB2PeriphClk2(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB2EN2 |= APB_periph; + } + else + { + RCC->APB2EN2 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB2PeriphClk3. +*\*\fun Enables the APB2 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB2_PERIPHEN_M7_USART5 +*\*\ - RCC_APB2_PERIPHEN_M4_USART5 +*\*\ - RCC_APB2_PERIPHEN_M7_USART5LP +*\*\ - RCC_APB2_PERIPHEN_M4_USART5LP +*\*\ - RCC_APB2_PERIPHEN_M7_USART6 +*\*\ - RCC_APB2_PERIPHEN_M4_USART6 +*\*\ - RCC_APB2_PERIPHEN_M7_USART6LP +*\*\ - RCC_APB2_PERIPHEN_M4_USART6LP +*\*\ - RCC_APB2_PERIPHEN_M7_USART7 +*\*\ - RCC_APB2_PERIPHEN_M4_USART7 +*\*\ - RCC_APB2_PERIPHEN_M7_USART7LP +*\*\ - RCC_APB2_PERIPHEN_M4_USART7LP +*\*\ - RCC_APB2_PERIPHEN_M7_USART8 +*\*\ - RCC_APB2_PERIPHEN_M4_USART8 +*\*\ - RCC_APB2_PERIPHEN_M7_USART8LP +*\*\ - RCC_APB2_PERIPHEN_M4_USART8LP +*\*\ - RCC_APB2_PERIPHEN_M7_UART13 +*\*\ - RCC_APB2_PERIPHEN_M4_UART13 +*\*\ - RCC_APB2_PERIPHEN_M7_UART13LP +*\*\ - RCC_APB2_PERIPHEN_M4_UART13LP +*\*\ - RCC_APB2_PERIPHEN_M7_UART14 +*\*\ - RCC_APB2_PERIPHEN_M4_UART14 +*\*\ - RCC_APB2_PERIPHEN_M7_UART14LP +*\*\ - RCC_APB2_PERIPHEN_M4_UART14LP +*\*\ - RCC_APB2_PERIPHEN_M7_UART15 +*\*\ - RCC_APB2_PERIPHEN_M4_UART15 +*\*\ - RCC_APB2_PERIPHEN_M7_UART15LP +*\*\ - RCC_APB2_PERIPHEN_M4_UART15LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB2PeriphClk3(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB2EN3 |= APB_periph; + } + else + { + RCC->APB2EN3 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB2PeriphClk4. +*\*\fun Enables the APB2 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN3 +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN3 +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN3LP +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN3LP +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN4 +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN4 +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN4LP +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN4LP +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN7 +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN7 +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN7LP +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN7LP +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN8 +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN8 +*\*\ - RCC_APB2_PERIPHEN_M7_FDCAN8LP +*\*\ - RCC_APB2_PERIPHEN_M4_FDCAN8LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB2PeriphClk4(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB2EN4 |= APB_periph; + } + else + { + RCC->APB2EN4 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAHB5PeriphClk1. +*\*\fun Enables the AHB5 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOA +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOA +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOALP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOALP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOB +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOB +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOBLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOBLP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOC +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOC +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOCLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOCLP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOD +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOD +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIODLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIODLP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOE +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOE +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOELP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOELP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOF +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOF +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOFLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOFLP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOG +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOG +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOGLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOGLP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOH +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOH +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOHLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOHLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB5PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB5EN1 |= AHB_periph; + } + else + { + RCC->AHB5EN1 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAHB5PeriphClk2. +*\*\fun Enables the AHB5 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOI +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOI +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOILP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOILP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOJ +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOJ +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOJLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOJLP +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOK +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOK +*\*\ - RCC_AHB5_PERIPHEN_M7_GPIOKLP +*\*\ - RCC_AHB5_PERIPHEN_M4_GPIOKLP +*\*\ - RCC_AHB5_PERIPHEN_M7_ECCM3 +*\*\ - RCC_AHB5_PERIPHEN_M4_ECCM3 +*\*\ - RCC_AHB5_PERIPHEN_M7_ECCM3LP +*\*\ - RCC_AHB5_PERIPHEN_M4_ECCM3LP +*\*\ - RCC_AHB5_PERIPHEN_PWR +*\*\ - RCC_AHB5_PERIPHEN_PWRLP +*\*\ - RCC_AHB5_PERIPHEN_M7_CRC +*\*\ - RCC_AHB5_PERIPHEN_M4_CRC +*\*\ - RCC_AHB5_PERIPHEN_M7_CRCLP +*\*\ - RCC_AHB5_PERIPHEN_M4_CRCLP +*\*\ - RCC_AHB5_PERIPHEN_M7_SEMA4 +*\*\ - RCC_AHB5_PERIPHEN_M4_SEMA4 +*\*\ - RCC_AHB5_PERIPHEN_M7_SEMA4LP +*\*\ - RCC_AHB5_PERIPHEN_M4_SEMA4LP +*\*\ - RCC_AHB5_PERIPHEN_M7_AFIO +*\*\ - RCC_AHB5_PERIPHEN_M4_AFIO +*\*\ - RCC_AHB5_PERIPHEN_M7_AFIOLP +*\*\ - RCC_AHB5_PERIPHEN_M4_AFIOLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB5PeriphClk2(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB5EN2 |= AHB_periph; + } + else + { + RCC->AHB5EN2 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableAPB5PeriphClk1. +*\*\fun Enables the APB5 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB5_PERIPHEN_M7_ATIM3 +*\*\ - RCC_APB5_PERIPHEN_M4_ATIM3 +*\*\ - RCC_APB5_PERIPHEN_M7_ATIM3LP +*\*\ - RCC_APB5_PERIPHEN_M4_ATIM3LP +*\*\ - RCC_APB5_PERIPHEN_M7_ATIM4 +*\*\ - RCC_APB5_PERIPHEN_M4_ATIM4 +*\*\ - RCC_APB5_PERIPHEN_M7_ATIM4LP +*\*\ - RCC_APB5_PERIPHEN_M4_ATIM4LP +*\*\ - RCC_APB5_PERIPHEN_M7_AFEC +*\*\ - RCC_APB5_PERIPHEN_M4_AFEC +*\*\ - RCC_APB5_PERIPHEN_M7_AFECLP +*\*\ - RCC_APB5_PERIPHEN_M4_AFECLP +*\*\ - RCC_APB5_PERIPHEN_M7_SPI4 +*\*\ - RCC_APB5_PERIPHEN_M4_SPI4 +*\*\ - RCC_APB5_PERIPHEN_M7_SPI4LP +*\*\ - RCC_APB5_PERIPHEN_M4_SPI4LP +*\*\ - RCC_APB5_PERIPHEN_M7_SPI5 +*\*\ - RCC_APB5_PERIPHEN_M4_SPI5 +*\*\ - RCC_APB5_PERIPHEN_M7_SPI5LP +*\*\ - RCC_APB5_PERIPHEN_M4_SPI5LP +*\*\ - RCC_APB5_PERIPHEN_M7_SPI6 +*\*\ - RCC_APB5_PERIPHEN_M4_SPI6 +*\*\ - RCC_APB5_PERIPHEN_M7_SPI6LP +*\*\ - RCC_APB5_PERIPHEN_M4_SPI6LP +*\*\ - RCC_APB5_PERIPHEN_M7_SPI7 +*\*\ - RCC_APB5_PERIPHEN_M4_SPI7 +*\*\ - RCC_APB5_PERIPHEN_M7_SPI7LP +*\*\ - RCC_APB5_PERIPHEN_M4_SPI7LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB5PeriphClk1(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB5EN1 |= APB_periph; + } + else + { + RCC->APB5EN1 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAPB5PeriphClk2. +*\*\fun Enables the APB5 peripheral clock. +*\*\param APB_periph (APB peripheral to gates its clock): +*\*\ - RCC_APB5_PERIPHEN_M7_I2C7 +*\*\ - RCC_APB5_PERIPHEN_M4_I2C7 +*\*\ - RCC_APB5_PERIPHEN_M7_I2C7LP +*\*\ - RCC_APB5_PERIPHEN_M4_I2C7LP +*\*\ - RCC_APB5_PERIPHEN_M7_I2C8 +*\*\ - RCC_APB5_PERIPHEN_M4_I2C8 +*\*\ - RCC_APB5_PERIPHEN_M7_I2C8LP +*\*\ - RCC_APB5_PERIPHEN_M4_I2C8LP +*\*\ - RCC_APB5_PERIPHEN_M7_I2C9 +*\*\ - RCC_APB5_PERIPHEN_M4_I2C9 +*\*\ - RCC_APB5_PERIPHEN_M7_I2C9LP +*\*\ - RCC_APB5_PERIPHEN_M4_I2C9LP +*\*\ - RCC_APB5_PERIPHEN_M7_I2C10 +*\*\ - RCC_APB5_PERIPHEN_M4_I2C10 +*\*\ - RCC_APB5_PERIPHEN_M7_I2C10LP +*\*\ - RCC_APB5_PERIPHEN_M4_I2C10LP +*\*\ - RCC_APB5_PERIPHEN_EXTI +*\*\ - RCC_APB5_PERIPHEN_EXTILP +*\*\ - RCC_APB5_PERIPHEN_M7_RTCPCLK +*\*\ - RCC_APB5_PERIPHEN_M4_RTCPCLK +*\*\ - RCC_APB5_PERIPHEN_M7_RTCPCLKLP +*\*\ - RCC_APB5_PERIPHEN_M4_RTCPCLKLP +*\*\ - RCC_APB5_PERIPHEN_IWDG1PCLK +*\*\ - RCC_APB5_PERIPHEN_IWDG1PCLKLP +*\*\ - RCC_APB5_PERIPHEN_IWDG2PCLK +*\*\ - RCC_APB5_PERIPHEN_IWDG2PCLKLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAPB5PeriphClk2(uint32_t APB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB5EN2 |= APB_periph; + } + else + { + RCC->APB5EN2 &= ~APB_periph; + } +} + +/** +*\*\name RCC_EnableAHB9PeriphClk1. +*\*\fun Enables the AHB9 peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB9_PERIPHEN_M7_ESC +*\*\ - RCC_AHB9_PERIPHEN_M4_ESC +*\*\ - RCC_AHB9_PERIPHEN_M7_ESCLP +*\*\ - RCC_AHB9_PERIPHEN_M4_ESCLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAHB9PeriphClk1(uint32_t AHB_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AHB9EN1 |= AHB_periph; + } + else + { + RCC->AHB9EN1 &= ~AHB_periph; + } +} + +/** +*\*\name RCC_EnableRDPeriphClk1. +*\*\fun Enables the Retention domain peripheral clock. +*\*\param RD_periph (RD peripheral to gates its clock): +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM1 +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM1 +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM1LP +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM1LP +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM2 +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM2 +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM2LP +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM2LP +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM3 +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM3 +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM3LP +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM3LP +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM4 +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM4 +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM4LP +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM4LP +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM5 +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM5 +*\*\ - RCC_RD_PERIPHEN_M7_LPTIM5LP +*\*\ - RCC_RD_PERIPHEN_M4_LPTIM5LP +*\*\ - RCC_RD_PERIPHEN_M7_LPUART1 +*\*\ - RCC_RD_PERIPHEN_M4_LPUART1 +*\*\ - RCC_RD_PERIPHEN_M7_LPUART1LP +*\*\ - RCC_RD_PERIPHEN_M4_LPUART1LP +*\*\ - RCC_RD_PERIPHEN_M7_LPUART2 +*\*\ - RCC_RD_PERIPHEN_M4_LPUART2 +*\*\ - RCC_RD_PERIPHEN_M7_LPUART2LP +*\*\ - RCC_RD_PERIPHEN_M4_LPUART2LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableRDPeriphClk1(uint32_t RD_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDEN1 |= RD_periph; + } + else + { + RCC->RDEN1 &= ~RD_periph; + } +} + +/** +*\*\name RCC_EnableRDPeriphClk2. +*\*\fun Enables the Retention domain peripheral clock. +*\*\param RD_periph (RD peripheral to gates its clock): +*\*\ - RCC_RD_PERIPHEN_M7_COMP +*\*\ - RCC_RD_PERIPHEN_M4_COMP +*\*\ - RCC_RD_PERIPHEN_M7_COMPLP +*\*\ - RCC_RD_PERIPHEN_M4_COMPLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableRDPeriphClk2(uint32_t RD_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDEN2 |= RD_periph; + } + else + { + RCC->RDEN2 &= ~RD_periph; + } +} + +/** +*\*\name RCC_EnableAXIPeriphClk1. +*\*\fun Enables the AXI peripheral clock. +*\*\param AXI_periph (AXI peripheral to gates its clock): +*\*\ - RCC_AXI_PERIPHEN_M7_JPEGD +*\*\ - RCC_AXI_PERIPHEN_M4_JPEGD +*\*\ - RCC_AXI_PERIPHEN_M7_JPEGDLP +*\*\ - RCC_AXI_PERIPHEN_M4_JPEGDLP +*\*\ - RCC_AXI_PERIPHEN_M7_JPEGE +*\*\ - RCC_AXI_PERIPHEN_M4_JPEGE +*\*\ - RCC_AXI_PERIPHEN_M7_JPEGELP +*\*\ - RCC_AXI_PERIPHEN_M4_JPEGELP +*\*\ - RCC_AXI_PERIPHEN_M7_DMAMUX2 +*\*\ - RCC_AXI_PERIPHEN_M4_DMAMUX2 +*\*\ - RCC_AXI_PERIPHEN_M7_DMAMUX2LP +*\*\ - RCC_AXI_PERIPHEN_M4_DMAMUX2LP +*\*\ - RCC_AXI_PERIPHEN_M7_MDMA +*\*\ - RCC_AXI_PERIPHEN_M4_MDMA +*\*\ - RCC_AXI_PERIPHEN_M7_MDMALP +*\*\ - RCC_AXI_PERIPHEN_M4_MDMALP +*\*\ - RCC_AXI_PERIPHEN_M7_SDMMC1 +*\*\ - RCC_AXI_PERIPHEN_M4_SDMMC1 +*\*\ - RCC_AXI_PERIPHEN_M7_SDMMC1LP +*\*\ - RCC_AXI_PERIPHEN_M4_SDMMC1LP +*\*\ - RCC_AXI_PERIPHEN_M7_ECCM1 +*\*\ - RCC_AXI_PERIPHEN_M4_ECCM1 +*\*\ - RCC_AXI_PERIPHEN_M7_ECCM1LP +*\*\ - RCC_AXI_PERIPHEN_M4_ECCM1LP +*\*\ - RCC_AXI_PERIPHEN_M7_OTPC +*\*\ - RCC_AXI_PERIPHEN_M4_OTPC +*\*\ - RCC_AXI_PERIPHEN_M7_OTPCLP +*\*\ - RCC_AXI_PERIPHEN_M4_OTPCLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAXIPeriphClk1(uint32_t AXI_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AXIEN1 |= AXI_periph; + } + else + { + RCC->AXIEN1 &= ~AXI_periph; + } +} + +/** +*\*\name RCC_EnableAXIPeriphClk2. +*\*\fun Enables the AXI peripheral clock. +*\*\param AXI_periph (AXI peripheral to gates its clock): +*\*\ - RCC_AXI_PERIPHEN_M7_DSI +*\*\ - RCC_AXI_PERIPHEN_M4_DSI +*\*\ - RCC_AXI_PERIPHEN_M7_DSILP +*\*\ - RCC_AXI_PERIPHEN_M4_DSILP +*\*\ - RCC_AXI_PERIPHEN_M7_LCDC +*\*\ - RCC_AXI_PERIPHEN_M4_LCDC +*\*\ - RCC_AXI_PERIPHEN_M7_LCDCLP +*\*\ - RCC_AXI_PERIPHEN_M4_LCDCLP +*\*\ - RCC_AXI_PERIPHEN_M7_LCDCAPB +*\*\ - RCC_AXI_PERIPHEN_M4_LCDCAPB +*\*\ - RCC_AXI_PERIPHEN_M7_LCDCAPBLP +*\*\ - RCC_AXI_PERIPHEN_M4_LCDCAPBLP +*\*\ - RCC_AXI_PERIPHEN_M7_DVP1 +*\*\ - RCC_AXI_PERIPHEN_M4_DVP1 +*\*\ - RCC_AXI_PERIPHEN_M7_DVP1LP +*\*\ - RCC_AXI_PERIPHEN_M4_DVP1LP +*\*\ - RCC_AXI_PERIPHEN_M7_DVP1APB +*\*\ - RCC_AXI_PERIPHEN_M4_DVP1APB +*\*\ - RCC_AXI_PERIPHEN_M7_DVP1APBLP +*\*\ - RCC_AXI_PERIPHEN_M4_DVP1APBLP +*\*\ - RCC_AXI_PERIPHEN_M7_DVP2 +*\*\ - RCC_AXI_PERIPHEN_M4_DVP2 +*\*\ - RCC_AXI_PERIPHEN_M7_DVP2LP +*\*\ - RCC_AXI_PERIPHEN_M4_DVP2LP +*\*\ - RCC_AXI_PERIPHEN_M7_DVP2APB +*\*\ - RCC_AXI_PERIPHEN_M4_DVP2APB +*\*\ - RCC_AXI_PERIPHEN_M7_DVP2APBLP +*\*\ - RCC_AXI_PERIPHEN_M4_DVP2APBLP +*\*\ - RCC_AXI_PERIPHEN_M7_WWDG1 +*\*\ - RCC_AXI_PERIPHEN_M4_WWDG1 +*\*\ - RCC_AXI_PERIPHEN_M7_WWDG1LP +*\*\ - RCC_AXI_PERIPHEN_M4_WWDG1LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAXIPeriphClk2(uint32_t AXI_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AXIEN2 |= AXI_periph; + } + else + { + RCC->AXIEN2 &= ~AXI_periph; + } +} + + +/** +*\*\name RCC_EnableAXIPeriphClk3. +*\*\fun Enables the AXI peripheral clock. +*\*\param AXI_periph (AXI peripheral to gates its clock): +*\*\ - RCC_AXI_PERIPHEN_M7_TASRAM2 +*\*\ - RCC_AXI_PERIPHEN_M4_TASRAM2 +*\*\ - RCC_AXI_PERIPHEN_M7_TASRAM2LP +*\*\ - RCC_AXI_PERIPHEN_M4_TASRAM2LP +*\*\ - RCC_AXI_PERIPHEN_M7_TASRAM3 +*\*\ - RCC_AXI_PERIPHEN_M4_TASRAM3 +*\*\ - RCC_AXI_PERIPHEN_M7_TASRAM3LP +*\*\ - RCC_AXI_PERIPHEN_M4_TASRAM3LP +*\*\ - RCC_AXI_PERIPHEN_M7_TCM +*\*\ - RCC_AXI_PERIPHEN_M4_TCM +*\*\ - RCC_AXI_PERIPHEN_M7_TCMLP +*\*\ - RCC_AXI_PERIPHEN_M4_TCMLP +*\*\ - RCC_AXI_PERIPHEN_M7_TCMAXI +*\*\ - RCC_AXI_PERIPHEN_M4_TCMAXI +*\*\ - RCC_AXI_PERIPHEN_M7_TCMAXILP +*\*\ - RCC_AXI_PERIPHEN_M4_TCMAXILP +*\*\ - RCC_AXI_PERIPHEN_M7_TCMAPB +*\*\ - RCC_AXI_PERIPHEN_M4_TCMAPB +*\*\ - RCC_AXI_PERIPHEN_M7_TCMAPBLP +*\*\ - RCC_AXI_PERIPHEN_M4_TCMAPBLP +*\*\ - RCC_AXI_PERIPHEN_M7_ASRAM1 +*\*\ - RCC_AXI_PERIPHEN_M4_ASRAM1 +*\*\ - RCC_AXI_PERIPHEN_M7_ASRAM1LP +*\*\ - RCC_AXI_PERIPHEN_M4_ASRAM1LP +*\*\ - RCC_AXI_PERIPHEN_M7_AXIROM +*\*\ - RCC_AXI_PERIPHEN_M4_AXIROM +*\*\ - RCC_AXI_PERIPHEN_M7_AXIROMLP +*\*\ - RCC_AXI_PERIPHEN_M4_AXIROMLP +*\*\ - RCC_AXI_PERIPHEN_M7_GPU +*\*\ - RCC_AXI_PERIPHEN_M4_GPU +*\*\ - RCC_AXI_PERIPHEN_M7_GPULP +*\*\ - RCC_AXI_PERIPHEN_M4_GPULP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAXIPeriphClk3(uint32_t AXI_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AXIEN3 |= AXI_periph; + } + else + { + RCC->AXIEN3 &= ~AXI_periph; + } +} + +/** +*\*\name RCC_EnableAXIPeriphClk4. +*\*\fun Enables the AXI peripheral clock. +*\*\param AXI_periph (AXI peripheral to gates its clock): +*\*\ - RCC_AXI_PERIPHEN_M7_XSPI1 +*\*\ - RCC_AXI_PERIPHEN_M4_XSPI1 +*\*\ - RCC_AXI_PERIPHEN_M7_XSPI1LP +*\*\ - RCC_AXI_PERIPHEN_M4_XSPI1LP +*\*\ - RCC_AXI_PERIPHEN_M7_XSPI2 +*\*\ - RCC_AXI_PERIPHEN_M4_XSPI2 +*\*\ - RCC_AXI_PERIPHEN_M7_XSPI2LP +*\*\ - RCC_AXI_PERIPHEN_M4_XSPI2LP +*\*\ - RCC_AXI_PERIPHEN_M7_FEMC +*\*\ - RCC_AXI_PERIPHEN_M4_FEMC +*\*\ - RCC_AXI_PERIPHEN_M7_FEMCLP +*\*\ - RCC_AXI_PERIPHEN_M4_FEMCLP +*\*\ - RCC_AXI_PERIPHEN_M7_SDRAM +*\*\ - RCC_AXI_PERIPHEN_M4_SDRAM +*\*\ - RCC_AXI_PERIPHEN_M7_SDRAMLP +*\*\ - RCC_AXI_PERIPHEN_M4_SDRAMLP +*\*\ - RCC_AXI_PERIPHEN_M7_DSIULPS +*\*\ - RCC_AXI_PERIPHEN_M4_DSIULPS +*\*\ - RCC_AXI_PERIPHEN_M7_DSIULPSLP +*\*\ - RCC_AXI_PERIPHEN_M4_DSIULPSLP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableAXIPeriphClk4(uint32_t AXI_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->AXIEN4 |= AXI_periph; + } + else + { + RCC->AXIEN4 &= ~AXI_periph; + } +} + +/** +*\*\name RCC_ConfigETH2PtpClk. +*\*\fun Config the Ethernet2 PTP clock. +*\*\param CLK_source(Ethernet2 PTP clock source): +*\*\ - RCC_ETHPTPCLK_SRC_SYSBUSDIV +*\*\ - RCC_ETHPTPCLK_SRC_PERIPH +*\*\ - RCC_ETHPTPCLK_SRC_PLL2C +*\*\ - RCC_ETHPTPCLK_SRC_PLL3A +*\*\param CLK_divider(Ethernet2 PTP clock source (sys_bus_div_clk) divider) +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV1 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV2 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV4 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV8 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV16 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV32 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV64 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV128 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV256 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV512 +*\*\return none +*\*\note if select RCC_ETHPTPCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by ETH2SYSDIV[3:0] +**/ +void RCC_ConfigETH2PtpClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AHB1SEL1; + /* Clear ETH2PTPSEL[1:0] bits */ + reg_value &= RCC_ETHPTPCLK_SRC_MASK; + /* Set ETH2PTPSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AHB1SEL1 = reg_value; + + if(CLK_source == RCC_ETHPTPCLK_SRC_SYSBUSDIV) + { + reg_value1 = RCC->AHB1DIV1; + /* Clear ETH2SYSDIV[3:0] bits */ + reg_value1 &= RCC_ETHPTPCLK_SYSBUSDIV_MASK; + /* Set the ETH2SYSDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AHB1DIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigETH1PtpClk. +*\*\fun Config the Ethernet1 PTP clock. +*\*\param CLK_source(Ethernet1 PTP clock source): +*\*\ - RCC_ETHPTPCLK_SRC_SYSBUSDIV +*\*\ - RCC_ETHPTPCLK_SRC_PERIPH +*\*\ - RCC_ETHPTPCLK_SRC_PLL2C +*\*\ - RCC_ETHPTPCLK_SRC_PLL3A +*\*\param CLK_divider(Ethernet1 PTP clock source (sys_bus_div_clk) divider) +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV1 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV2 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV4 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV8 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV16 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV32 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV64 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV128 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV256 +*\*\ - RCC_ETHPTPCLK_SYSBUSDIV512 +*\*\return none +*\*\note if select RCC_ETHPTPCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by ETH1SYSDIV[3:0] +**/ +void RCC_ConfigETH1PtpClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AHB2SEL1; + /* Clear ETH1PTPSEL[1:0] bits */ + reg_value &= RCC_ETHPTPCLK_SRC_MASK; + /* Set ETH1PTPSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AHB2SEL1 = reg_value; + + if(CLK_source == RCC_ETHPTPCLK_SRC_SYSBUSDIV) + { + reg_value1 = RCC->AHB2DIV1; + /* Clear ETH1SYSDIV[3:0] bits */ + reg_value1 &= RCC_ETHPTPCLK_SYSBUSDIV_MASK; + /* Set the ETH1SYSDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AHB2DIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigETH1GMIITXClk. +*\*\fun Configures ETH1 125 MHz GMII TX clock source. +*\*\param CLK_source: +*\*\ - RCC_ETH1GMIITXCLK_SRC_PLL3A +*\*\ - RCC_ETH1GMIITXCLK_SRC_PLL2B +*\*\ - RCC_ETH1GMIITXCLK_SRC_IOM +*\*\ - RCC_ETH1GMIITXCLK_SRC_PLL1C +*\*\return none +**/ +void RCC_ConfigETH1GMIITXClk(uint32_t CLK_source) +{ + uint32_t temp_value; + + temp_value = RCC->AHB2SEL1; + + /* Clear ETH1GMIITXSEL[1:0] bits */ + temp_value &= RCC_ETH1GMIITXCLK_SRC_MASK; + /* Set ETH1GMIITXSEL[1:0] bits according to CLK_source value*/ + temp_value |= CLK_source; + + /* Store the new value */ + RCC->AHB2SEL1 = temp_value; + +} + +/** +*\*\name RCC_ConfigSDMMC2KerClk. +*\*\fun Config the SDMMC2 kernel clock. +*\*\param CLK_source(SDMMC2 kernel clock source): +*\*\ - RCC_SDMMC2KERCLK_SRC_SYSBUSDIV +*\*\ - RCC_SDMMC2KERCLK_SRC_PERIPH +*\*\ - RCC_SDMMC2KERCLK_SRC_PLL2A +*\*\ - RCC_SDMMC2KERCLK_SRC_PLL3A +*\*\ - RCC_SDMMC2KERCLK_SRC_PLL1B +*\*\param CLK_divider(SDMMC2 kernel clock source (sys_bus_div_clk) divider) +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV1 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV2 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV4 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV8 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV16 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV32 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV64 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV128 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV256 +*\*\ - RCC_SDMMC2KERCLK_SYSBUSDIV512 +*\*\return none +*\*\note if select RCC_SDMMC2KERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by SDMMC2SYSDIV[3:0] +**/ +void RCC_ConfigSDMMC2KerClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AHB1SEL1; + /* Clear SDMMC2KERSEL[2:0] bits */ + reg_value &= RCC_SDMMC2KERCLK_SRC_MASK; + /* Set SDMMC2KERSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AHB1SEL1 = reg_value; + + if(CLK_source == RCC_SDMMC2KERCLK_SRC_SYSBUSDIV) + { + reg_value1 = RCC->AHB1DIV1; + /* Clear SDMMC2SYSDIV[3:0] bits */ + reg_value1 &= RCC_SDMMC2KERCLK_SYSBUSDIV_MASK; + /* Set the SDMMC2SYSDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AHB1DIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigSDMMC1KerClk. +*\*\fun Config the SDMMC1 kernel clock. +*\*\param CLK_source(SDMMC1 kernel clock source): +*\*\ - RCC_SDMMC1KERCLK_SRC_AXIDIV +*\*\ - RCC_SDMMC1KERCLK_SRC_PERIPH +*\*\ - RCC_SDMMC1KERCLK_SRC_PLL2A +*\*\ - RCC_SDMMC1KERCLK_SRC_PLL3A +*\*\ - RCC_SDMMC1KERCLK_SRC_PLL1B +*\*\param CLK_divider(SDMMC1 kernel clock source (axi_bus_clk) divider) +*\*\ - RCC_SDMMC1KERCLK_AXIDIV1 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV2 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV4 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV8 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV16 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV32 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV64 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV128 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV256 +*\*\ - RCC_SDMMC1KERCLK_AXIDIV512 +*\*\return none +*\*\note if select RCC_SDMMC1KERCLK_SRC_AXIDIV then set the AXI clock divider by SDMMC1AXIDIV[3:0] +**/ +void RCC_ConfigSDMMC1KerClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL1; + /* Clear SDMMC1KERSEL[2:0] bits */ + reg_value &= RCC_SDMMC1KERCLK_SRC_MASK; + /* Set SDMMC1KERSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + + if(CLK_source == RCC_SDMMC1KERCLK_SRC_AXIDIV) + { + reg_value1 = RCC->AXIDIV1; + /* Clear SDMMC1AXIDIV[3:0] bits */ + reg_value1 &= RCC_SDMMC1KERCLK_AXIDIV_MASK; + /* Set the SDMMC1AXIDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigDSMUKerClk. +*\*\fun Config the DSMU kernel clock. +*\*\param CLK_source(DSMU kernel clock source): +*\*\ - RCC_DSMUKERCLK_SRC_APB2 +*\*\ - RCC_DSMUKERCLK_SRC_SYSBUSDIV +*\*\param CLK_divider(DSMU kernel clock source (sys_bus_div_clk) divider) +*\*\ - RCC_DSMUKERCLK_SYSBUSDIV1 +*\*\ - RCC_DSMUKERCLK_SYSBUSDIV2 +*\*\ - RCC_DSMUKERCLK_SYSBUSDIV4 +*\*\ - RCC_DSMUKERCLK_SYSBUSDIV8 +*\*\ - RCC_DSMUKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note if select RCC_DSMUKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2DSMUDIV[2:0] +**/ +void RCC_ConfigDSMUKerClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->APB2SEL1; + /* Clear DSMUKERSEL bits */ + reg_value &= RCC_DSMUKERCLK_SRC_MASK; + /* Set DSMUKERSEL bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + + if(CLK_source == RCC_DSMUKERCLK_SRC_SYSBUSDIV) + { + reg_value1 = RCC->APB2DIV1; + /* Clear APB2DSMUDIV[2:0] bits */ + reg_value1 &= RCC_DSMUKERCLK_SYSBUSDIV_MASK; + /* Set the APB2DSMUDIV[2:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->APB2DIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigDSMUKerAClk. +*\*\fun Config the DSMU kernel A clock. +*\*\param CLK_source(DSMU kernel A clock source): +*\*\ - RCC_DSMUKERACLK_SRC_APB2 +*\*\ - RCC_DSMUKERACLK_SRC_PLL1B +*\*\ - RCC_DSMUKERACLK_SRC_PLL2B +*\*\ - RCC_DSMUKERACLK_SRC_PLL3A +*\*\ - RCC_DSMUKERACLK_SRC_CKIN +*\*\ - RCC_DSMUKERACLK_SRC_PERIPH +*\*\param CLK_pinsel(DSMU kernel A clock source CKIN pin select) +*\*\ - RCC_DSMUKERACLK_CKIN_I2S1 +*\*\ - RCC_DSMUKERACLK_CKIN_I2S2 +*\*\ - RCC_DSMUKERACLK_CKIN_I2S3 +*\*\ - RCC_DSMUKERACLK_CKIN_I2S4 +*\*\return none +*\*\note if select RCC_DSMUKERACLK_SRC_CKIN then set the I2S CKIN pin by I2SSEL[1:0] +**/ +void RCC_ConfigDSMUKerAClk(uint32_t CLK_source, uint32_t CLK_pinsel) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->APB2SEL1; + /* Clear DSMUKERASEL[2:0] bits */ + reg_value &= RCC_DSMUKERACLK_SRC_MASK; + /* Set DSMUKERASEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + + if(CLK_source == RCC_DSMUKERACLK_SRC_CKIN) + { + reg_value1 = RCC->CFG3; + /* Clear I2SSEL[1:0] bits */ + reg_value1 &= RCC_DSMUKERACLK_CKIN_MASK; + /* Set the I2SSEL[1:0] bits */ + reg_value1 |= CLK_pinsel; + /* Store the new value */ + RCC->CFG3 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigUSBRefClk. +*\*\fun Config the USB1/2 reference clock divider from HSE. +*\*\param CLK_divider(USB reference clock divider) +*\*\ - RCC_USBREFCLK_HSE_DIV1 +*\*\ - RCC_USBREFCLK_HSE_DIV2 +*\*\return none +*\*\note none +**/ +void RCC_ConfigUSBRefClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->AHB2DIV1; + /* Clear USBHSEDIV[3:0] bits */ + reg_value &= RCC_USBREFCLK_HSE_DIV_MASK; + /* Set the USBHSEDIV[3:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->AHB2DIV1 = reg_value; + +} + +/** +*\*\name RCC_ConfigAdc1PllClk. +*\*\fun Configures the ADC PLL clock source. +*\*\param CLK_source(ADC PLL clock source): +*\*\ - RCC_ADCPLLCLK_SRC_PLL2B +*\*\ - RCC_ADCPLLCLK_SRC_PLL1B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3C +*\*\return none +**/ +void RCC_ConfigAdc1PllClk(uint32_t CLK_source) +{ + uint32_t temp_value; + + temp_value = RCC->AHB1SEL1; + + /* Clear ADC1PLLSEL[1:0] bits */ + temp_value &= RCC_ADC1PLLCLK_SRC_MASK; + /* Set ADC1PLLSEL[1:0] bits according to CLK_source value*/ + temp_value |= CLK_source; + + /* Store the new value */ + RCC->AHB1SEL1 = temp_value; + +} + +/** +*\*\name RCC_ConfigAdc1SysClk. +*\*\fun Configures the prescaler from sys_bus_div_clk. +*\*\param CLK_divider: +*\*\ - RCC_ADCSYSCLK_DIV1 +*\*\ - RCC_ADCSYSCLK_DIV2 +*\*\ - RCC_ADCSYSCLK_DIV3 +*\*\ - RCC_ADCSYSCLK_DIV4 +*\*\ - RCC_ADCSYSCLK_DIV5 +*\*\ - RCC_ADCSYSCLK_DIV6 +*\*\ - RCC_ADCSYSCLK_DIV7 +*\*\ - RCC_ADCSYSCLK_DIV8 +*\*\ - RCC_ADCSYSCLK_DIV9 +*\*\ - RCC_ADCSYSCLK_DIV10 +*\*\ - RCC_ADCSYSCLK_DIV11 +*\*\ - RCC_ADCSYSCLK_DIV12 +*\*\ - RCC_ADCSYSCLK_DIV13 +*\*\ - RCC_ADCSYSCLK_DIV14 +*\*\ - RCC_ADCSYSCLK_DIV15 +*\*\ - RCC_ADCSYSCLK_DIV16 +*\*\ - RCC_ADCSYSCLK_DIV17 +*\*\ - RCC_ADCSYSCLK_DIV18 +*\*\ - RCC_ADCSYSCLK_DIV19 +*\*\ - RCC_ADCSYSCLK_DIV20 +*\*\ - RCC_ADCSYSCLK_DIV21 +*\*\ - RCC_ADCSYSCLK_DIV22 +*\*\ - RCC_ADCSYSCLK_DIV23 +*\*\ - RCC_ADCSYSCLK_DIV24 +*\*\ - RCC_ADCSYSCLK_DIV25 +*\*\ - RCC_ADCSYSCLK_DIV26 +*\*\ - RCC_ADCSYSCLK_DIV27 +*\*\ - RCC_ADCSYSCLK_DIV28 +*\*\ - RCC_ADCSYSCLK_DIV29 +*\*\ - RCC_ADCSYSCLK_DIV30 +*\*\ - RCC_ADCSYSCLK_DIV31 +*\*\ - RCC_ADCSYSCLK_DIV32 +*\*\ - RCC_ADCSYSCLK_DIV33 +*\*\ - RCC_ADCSYSCLK_DIV34 +*\*\ - RCC_ADCSYSCLK_DIV35 +*\*\ - RCC_ADCSYSCLK_DIV36 +*\*\ - RCC_ADCSYSCLK_DIV37 +*\*\ - RCC_ADCSYSCLK_DIV38 +*\*\ - RCC_ADCSYSCLK_DIV39 +*\*\ - RCC_ADCSYSCLK_DIV40 +*\*\ - RCC_ADCSYSCLK_DIV41 +*\*\ - RCC_ADCSYSCLK_DIV42 +*\*\ - RCC_ADCSYSCLK_DIV43 +*\*\ - RCC_ADCSYSCLK_DIV44 +*\*\ - RCC_ADCSYSCLK_DIV45 +*\*\ - RCC_ADCSYSCLK_DIV46 +*\*\ - RCC_ADCSYSCLK_DIV47 +*\*\ - RCC_ADCSYSCLK_DIV48 +*\*\ - RCC_ADCSYSCLK_DIV49 +*\*\ - RCC_ADCSYSCLK_DIV50 +*\*\ - RCC_ADCSYSCLK_DIV51 +*\*\ - RCC_ADCSYSCLK_DIV52 +*\*\ - RCC_ADCSYSCLK_DIV53 +*\*\ - RCC_ADCSYSCLK_DIV54 +*\*\ - RCC_ADCSYSCLK_DIV55 +*\*\ - RCC_ADCSYSCLK_DIV56 +*\*\ - RCC_ADCSYSCLK_DIV57 +*\*\ - RCC_ADCSYSCLK_DIV58 +*\*\ - RCC_ADCSYSCLK_DIV59 +*\*\ - RCC_ADCSYSCLK_DIV60 +*\*\ - RCC_ADCSYSCLK_DIV61 +*\*\ - RCC_ADCSYSCLK_DIV62 +*\*\ - RCC_ADCSYSCLK_DIV63 +*\*\return none +**/ +void RCC_ConfigAdc1SysClk(uint32_t CLK_divider) +{ + uint32_t temp_value; + + temp_value = RCC->AHB1DIV2; + /* Clear ADC1SYSDIV[5:0] bits */ + temp_value &= RCC_ADC1SYSCLK_DIV_MASK; + /* Set ADC1SYSDIV[5:0] bits according to CLK_divider value */ + temp_value |= CLK_divider; + + /* Store the new value */ + RCC->AHB1DIV2 = temp_value; +} + +/** +*\*\name RCC_ConfigAdc2PllClk. +*\*\fun Configures the ADC PLL clock source. +*\*\param CLK_source(ADC PLL clock source): +*\*\ - RCC_ADCPLLCLK_SRC_PLL2B +*\*\ - RCC_ADCPLLCLK_SRC_PLL1B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3C +*\*\return none +**/ +void RCC_ConfigAdc2PllClk(uint32_t CLK_source) +{ + uint32_t temp_value; + + temp_value = RCC->AHB1SEL1; + + /* Clear ADC2PLLSEL[1:0] bits */ + temp_value &= RCC_ADC2PLLCLK_SRC_MASK; + /* Set ADC2PLLSEL[1:0] bits according to CLK_source value*/ + temp_value |= (CLK_source << 4); + + /* Store the new value */ + RCC->AHB1SEL1 = temp_value; + +} + +/** +*\*\name RCC_ConfigAdc2SysClk. +*\*\fun Configures the ADCSYSCLK prescaler. +*\*\param CLK_divider(ADCSYSCLK prescaler): +*\*\ - RCC_ADCSYSCLK_DIV1 +*\*\ - RCC_ADCSYSCLK_DIV2 +*\*\ - RCC_ADCSYSCLK_DIV3 +*\*\ - RCC_ADCSYSCLK_DIV4 +*\*\ - RCC_ADCSYSCLK_DIV5 +*\*\ - RCC_ADCSYSCLK_DIV6 +*\*\ - RCC_ADCSYSCLK_DIV7 +*\*\ - RCC_ADCSYSCLK_DIV8 +*\*\ - RCC_ADCSYSCLK_DIV9 +*\*\ - RCC_ADCSYSCLK_DIV10 +*\*\ - RCC_ADCSYSCLK_DIV11 +*\*\ - RCC_ADCSYSCLK_DIV12 +*\*\ - RCC_ADCSYSCLK_DIV13 +*\*\ - RCC_ADCSYSCLK_DIV14 +*\*\ - RCC_ADCSYSCLK_DIV15 +*\*\ - RCC_ADCSYSCLK_DIV16 +*\*\ - RCC_ADCSYSCLK_DIV17 +*\*\ - RCC_ADCSYSCLK_DIV18 +*\*\ - RCC_ADCSYSCLK_DIV19 +*\*\ - RCC_ADCSYSCLK_DIV20 +*\*\ - RCC_ADCSYSCLK_DIV21 +*\*\ - RCC_ADCSYSCLK_DIV22 +*\*\ - RCC_ADCSYSCLK_DIV23 +*\*\ - RCC_ADCSYSCLK_DIV24 +*\*\ - RCC_ADCSYSCLK_DIV25 +*\*\ - RCC_ADCSYSCLK_DIV26 +*\*\ - RCC_ADCSYSCLK_DIV27 +*\*\ - RCC_ADCSYSCLK_DIV28 +*\*\ - RCC_ADCSYSCLK_DIV29 +*\*\ - RCC_ADCSYSCLK_DIV30 +*\*\ - RCC_ADCSYSCLK_DIV31 +*\*\ - RCC_ADCSYSCLK_DIV32 +*\*\ - RCC_ADCSYSCLK_DIV33 +*\*\ - RCC_ADCSYSCLK_DIV34 +*\*\ - RCC_ADCSYSCLK_DIV35 +*\*\ - RCC_ADCSYSCLK_DIV36 +*\*\ - RCC_ADCSYSCLK_DIV37 +*\*\ - RCC_ADCSYSCLK_DIV38 +*\*\ - RCC_ADCSYSCLK_DIV39 +*\*\ - RCC_ADCSYSCLK_DIV40 +*\*\ - RCC_ADCSYSCLK_DIV41 +*\*\ - RCC_ADCSYSCLK_DIV42 +*\*\ - RCC_ADCSYSCLK_DIV43 +*\*\ - RCC_ADCSYSCLK_DIV44 +*\*\ - RCC_ADCSYSCLK_DIV45 +*\*\ - RCC_ADCSYSCLK_DIV46 +*\*\ - RCC_ADCSYSCLK_DIV47 +*\*\ - RCC_ADCSYSCLK_DIV48 +*\*\ - RCC_ADCSYSCLK_DIV49 +*\*\ - RCC_ADCSYSCLK_DIV50 +*\*\ - RCC_ADCSYSCLK_DIV51 +*\*\ - RCC_ADCSYSCLK_DIV52 +*\*\ - RCC_ADCSYSCLK_DIV53 +*\*\ - RCC_ADCSYSCLK_DIV54 +*\*\ - RCC_ADCSYSCLK_DIV55 +*\*\ - RCC_ADCSYSCLK_DIV56 +*\*\ - RCC_ADCSYSCLK_DIV57 +*\*\ - RCC_ADCSYSCLK_DIV58 +*\*\ - RCC_ADCSYSCLK_DIV59 +*\*\ - RCC_ADCSYSCLK_DIV60 +*\*\ - RCC_ADCSYSCLK_DIV61 +*\*\ - RCC_ADCSYSCLK_DIV62 +*\*\ - RCC_ADCSYSCLK_DIV63 +*\*\return none +**/ +void RCC_ConfigAdc2SysClk(uint32_t CLK_divider) +{ + uint32_t temp_value; + + temp_value = RCC->AHB1DIV2; + /* Clear ADC2SYSDIV[5:0] bits */ + temp_value &= RCC_ADC2SYSCLK_DIV_MASK; + /* Set ADC2SYSDIV[5:0] bits according to CLK_divider value */ + temp_value |= (CLK_divider << 8); + + /* Store the new value */ + RCC->AHB1DIV2 = temp_value; +} + +/** +*\*\name RCC_ConfigAdc3PllClk. +*\*\fun Configures the ADC PLL clock source. +*\*\param CLK_source(ADC PLL clock source): +*\*\ - RCC_ADCPLLCLK_SRC_PLL2B +*\*\ - RCC_ADCPLLCLK_SRC_PLL1B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3B +*\*\ - RCC_ADCPLLCLK_SRC_PLL3C +*\*\return none +**/ +void RCC_ConfigAdc3PllClk(uint32_t CLK_source) +{ + uint32_t temp_value; + + temp_value = RCC->AHB1SEL1; + + /* Clear ADC3PLLSEL[1:0] bits */ + temp_value &= RCC_ADC3PLLCLK_SRC_MASK; + /* Set ADC3PLLSEL[1:0] bits according to CLK_source value*/ + temp_value |= (CLK_source << 8); + + /* Store the new value */ + RCC->AHB1SEL1 = temp_value; + +} + +/** +*\*\name RCC_ConfigAdc3SysClk. +*\*\fun Configures the ADCSYSCLK prescaler. +*\*\param CLK_divider(ADCSYSCLK prescaler): +*\*\ - RCC_ADCSYSCLK_DIV1 +*\*\ - RCC_ADCSYSCLK_DIV2 +*\*\ - RCC_ADCSYSCLK_DIV3 +*\*\ - RCC_ADCSYSCLK_DIV4 +*\*\ - RCC_ADCSYSCLK_DIV5 +*\*\ - RCC_ADCSYSCLK_DIV6 +*\*\ - RCC_ADCSYSCLK_DIV7 +*\*\ - RCC_ADCSYSCLK_DIV8 +*\*\ - RCC_ADCSYSCLK_DIV9 +*\*\ - RCC_ADCSYSCLK_DIV10 +*\*\ - RCC_ADCSYSCLK_DIV11 +*\*\ - RCC_ADCSYSCLK_DIV12 +*\*\ - RCC_ADCSYSCLK_DIV13 +*\*\ - RCC_ADCSYSCLK_DIV14 +*\*\ - RCC_ADCSYSCLK_DIV15 +*\*\ - RCC_ADCSYSCLK_DIV16 +*\*\ - RCC_ADCSYSCLK_DIV17 +*\*\ - RCC_ADCSYSCLK_DIV18 +*\*\ - RCC_ADCSYSCLK_DIV19 +*\*\ - RCC_ADCSYSCLK_DIV20 +*\*\ - RCC_ADCSYSCLK_DIV21 +*\*\ - RCC_ADCSYSCLK_DIV22 +*\*\ - RCC_ADCSYSCLK_DIV23 +*\*\ - RCC_ADCSYSCLK_DIV24 +*\*\ - RCC_ADCSYSCLK_DIV25 +*\*\ - RCC_ADCSYSCLK_DIV26 +*\*\ - RCC_ADCSYSCLK_DIV27 +*\*\ - RCC_ADCSYSCLK_DIV28 +*\*\ - RCC_ADCSYSCLK_DIV29 +*\*\ - RCC_ADCSYSCLK_DIV30 +*\*\ - RCC_ADCSYSCLK_DIV31 +*\*\ - RCC_ADCSYSCLK_DIV32 +*\*\ - RCC_ADCSYSCLK_DIV33 +*\*\ - RCC_ADCSYSCLK_DIV34 +*\*\ - RCC_ADCSYSCLK_DIV35 +*\*\ - RCC_ADCSYSCLK_DIV36 +*\*\ - RCC_ADCSYSCLK_DIV37 +*\*\ - RCC_ADCSYSCLK_DIV38 +*\*\ - RCC_ADCSYSCLK_DIV39 +*\*\ - RCC_ADCSYSCLK_DIV40 +*\*\ - RCC_ADCSYSCLK_DIV41 +*\*\ - RCC_ADCSYSCLK_DIV42 +*\*\ - RCC_ADCSYSCLK_DIV43 +*\*\ - RCC_ADCSYSCLK_DIV44 +*\*\ - RCC_ADCSYSCLK_DIV45 +*\*\ - RCC_ADCSYSCLK_DIV46 +*\*\ - RCC_ADCSYSCLK_DIV47 +*\*\ - RCC_ADCSYSCLK_DIV48 +*\*\ - RCC_ADCSYSCLK_DIV49 +*\*\ - RCC_ADCSYSCLK_DIV50 +*\*\ - RCC_ADCSYSCLK_DIV51 +*\*\ - RCC_ADCSYSCLK_DIV52 +*\*\ - RCC_ADCSYSCLK_DIV53 +*\*\ - RCC_ADCSYSCLK_DIV54 +*\*\ - RCC_ADCSYSCLK_DIV55 +*\*\ - RCC_ADCSYSCLK_DIV56 +*\*\ - RCC_ADCSYSCLK_DIV57 +*\*\ - RCC_ADCSYSCLK_DIV58 +*\*\ - RCC_ADCSYSCLK_DIV59 +*\*\ - RCC_ADCSYSCLK_DIV60 +*\*\ - RCC_ADCSYSCLK_DIV61 +*\*\ - RCC_ADCSYSCLK_DIV62 +*\*\ - RCC_ADCSYSCLK_DIV63 +*\*\return none +**/ +void RCC_ConfigAdc3SysClk(uint32_t CLK_divider) +{ + uint32_t temp_value; + + temp_value = RCC->AHB1DIV2; + /* Clear ADC3SYSDIV[5:0] bits */ + temp_value &= RCC_ADC3SYSCLK_DIV_MASK; + /* Set ADC3SYSDIV[5:0] bits according to CLK_divider value */ + temp_value |= (CLK_divider << 16); + + /* Store the new value */ + RCC->AHB1DIV2 = temp_value; +} + + +/** +*\*\name RCC_ConfigBTIMKerClk. +*\*\fun Config the BTIM1/2/3/4 kernel clock divider from ahb1. +*\*\param CLK_divider +*\*\ - RCC_BTIMKERCLK_AHB1_DIV1 +*\*\ - RCC_BTIMKERCLK_AHB1_DIV2 +*\*\ - RCC_BTIMKERCLK_AHB1_DIV4 +*\*\ - RCC_BTIMKERCLK_AHB1_DIV8 +*\*\ - RCC_BTIMKERCLK_AHB1_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigBTIMKerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1BTIMDIV[2:0] bits */ + reg_value &= RCC_BTIMKERCLK_AHB1_DIV_MASK; + /* Set the APB1BTIMDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigGTIMA1_3_KerClk. +*\*\fun Config the GTIMA1/2/3 kernel clock divider from ahb2. +*\*\param CLK_divider +*\*\ - RCC_GTIMKERCLK_AHB2_DIV1 +*\*\ - RCC_GTIMKERCLK_AHB2_DIV2 +*\*\ - RCC_GTIMKERCLK_AHB2_DIV4 +*\*\ - RCC_GTIMKERCLK_AHB2_DIV8 +*\*\ - RCC_GTIMKERCLK_AHB2_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigGTIMA1_3_KerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB2DIV1; + /* Clear APB2GTIMDIV[2:0] bits */ + reg_value &= RCC_GTIMKERCLK_AHB2_DIV_MASK; + /* Set the APB2GTIMDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB2DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigGTIMA4_7_KerClk. +*\*\fun Config the GTIMA4/5/6/7 kernel clock divider from ahb1. +*\*\param CLK_divider +*\*\ - RCC_GTIMKERCLK_AHB1_DIV1 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV2 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV4 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV8 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigGTIMA4_7_KerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1GTIMDIV[2:0] bits */ + reg_value &= RCC_GTIMKERCLK_AHB1_DIV_MASK; + /* Set the APB1GTIMDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigGTIMB1_3_KerClk. +*\*\fun Config the GTIMB1/2/3 kernel clock divider from ahb1. +*\*\param CLK_divider +*\*\ - RCC_GTIMKERCLK_AHB1_DIV1 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV2 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV4 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV8 +*\*\ - RCC_GTIMKERCLK_AHB1_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigGTIMB1_3_KerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1GTIMDIV[2:0] bits */ + reg_value &= RCC_GTIMKERCLK_AHB1_DIV_MASK; + /* Set the APB1GTIMDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigATIM1_2_KerClk. +*\*\fun Config the ATIM1/2 kernel clock divider from ahb2. +*\*\param CLK_divider +*\*\ - RCC_ATIMKERCLK_AHB2_DIV1 +*\*\ - RCC_ATIMKERCLK_AHB2_DIV2 +*\*\ - RCC_ATIMKERCLK_AHB2_DIV4 +*\*\ - RCC_ATIMKERCLK_AHB2_DIV8 +*\*\ - RCC_ATIMKERCLK_AHB2_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigATIM1_2_KerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB2DIV1; + /* Clear APB2ATIMDIV[2:0] bits */ + reg_value &= RCC_ATIMKERCLK_AHB2_DIV_MASK; + /* Set the APB2ATIMDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB2DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigATIM3_4_KerClk. +*\*\fun Config the ATIM3/4 kernel clock divider from ahb5. +*\*\param CLK_divider +*\*\ - RCC_ATIMKERCLK_AHB5_DIV1 +*\*\ - RCC_ATIMKERCLK_AHB5_DIV2 +*\*\ - RCC_ATIMKERCLK_AHB5_DIV4 +*\*\ - RCC_ATIMKERCLK_AHB5_DIV8 +*\*\ - RCC_ATIMKERCLK_AHB5_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigATIM3_4_KerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB5DIV1; + /* Clear APB5ATIMDIV[2:0] bits */ + reg_value &= RCC_ATIMKERCLK_AHB5_DIV_MASK; + /* Set the APB5ATIMDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB5DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigUSARTPClk. +*\*\fun Config the USART1/2 PCLK divider from ahb1. +*\*\param CLK_divider +*\*\ - RCC_USARTPCLK_AHB1_DIV1 +*\*\ - RCC_USARTPCLK_AHB1_DIV2 +*\*\ - RCC_USARTPCLK_AHB1_DIV4 +*\*\ - RCC_USARTPCLK_AHB1_DIV8 +*\*\ - RCC_USARTPCLK_AHB1_DIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigUSARTPClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1USARTDIV[2:0] bits */ + reg_value &= RCC_USARTPCLK_AHB1_DIV_MASK; + /* Set the APB1USARTDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigI2S1KerClkSource. +*\*\fun Config the I2S1 kernel clock source. +*\*\param CLK_source(I2S kernel clock source): +*\*\ - RCC_I2SKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2SKERCLK_SRC_PLL3B +*\*\ - RCC_I2SKERCLK_SRC_HSI +*\*\ - RCC_I2SKERCLK_SRC_CLKIN +*\*\return none +*\*\note if select RCC_I2SKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2I2SDIV[2:0] +**/ +void RCC_ConfigI2S1KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL1; + /* Clear I2S1KERSEL[1:0] bits */ + reg_value &= RCC_I2S1KERCLK_SRC_MASK; + /* Set I2S1KERSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2S2KerClkSource. +*\*\fun Config the I2S2 kernel clock source. +*\*\param CLK_source(I2S kernel clock source): +*\*\ - RCC_I2SKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2SKERCLK_SRC_PLL3B +*\*\ - RCC_I2SKERCLK_SRC_HSI +*\*\ - RCC_I2SKERCLK_SRC_CLKIN +*\*\return none +*\*\note if select RCC_I2SKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2I2SDIV[2:0] +**/ +void RCC_ConfigI2S2KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL1; + /* Clear I2S2KERSEL[1:0] bits */ + reg_value &= RCC_I2S2KERCLK_SRC_MASK; + /* Set I2S2KERSEL[1:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 2); + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2S1_2_KerSysDivider. +*\*\fun Config the I2S1/2 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_I2SKERCLK_SYSBUSDIV1 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV2 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV4 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV8 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigI2S1_2_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB2DIV1; + /* Clear APB2I2SDIV[2:0] bits */ + reg_value &= RCC_I2S1_2_KERCLK_SYSBUSDIV_MASK; + /* Set the APB2I2SDIV[2:0] bits */ + reg_value |= (CLK_divider << 8); + /* Store the new value */ + RCC->APB2DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigI2S3KerClkSource. +*\*\fun Config the I2S3 kernel clock source. +*\*\param CLK_source(I2S kernel clock source): +*\*\ - RCC_I2SKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2SKERCLK_SRC_PLL3B +*\*\ - RCC_I2SKERCLK_SRC_HSI +*\*\ - RCC_I2SKERCLK_SRC_CLKIN +*\*\return none +*\*\note if select RCC_I2SKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1I2SDIV[2:0] +**/ +void RCC_ConfigI2S3KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear I2S3KERSEL[1:0] bits */ + reg_value &= RCC_I2S3KERCLK_SRC_MASK; + /* Set I2S3KERSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2S4KerClkSource. +*\*\fun Config the I2S4 kernel clock source. +*\*\param CLK_source(I2S kernel clock source): +*\*\ - RCC_I2SKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2SKERCLK_SRC_PLL3B +*\*\ - RCC_I2SKERCLK_SRC_HSI +*\*\ - RCC_I2SKERCLK_SRC_CLKIN +*\*\return none +*\*\note if select RCC_I2SKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1I2SDIV[2:0] +**/ +void RCC_ConfigI2S4KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear I2S4KERSEL[1:0] bits */ + reg_value &= RCC_I2S4KERCLK_SRC_MASK; + /* Set I2S4KERSEL[1:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 2); + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2S3_4_KerSysDivider. +*\*\fun Config the I2S3/4 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_I2SKERCLK_SYSBUSDIV1 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV2 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV4 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV8 +*\*\ - RCC_I2SKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigI2S3_4_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1I2SDIV[2:0] bits */ + reg_value &= RCC_I2S3_4_KERCLK_SYSBUSDIV_MASK; + /* Set the APB1I2SDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + + + +/** +*\*\name RCC_ConfigI2C1KerClkSource. +*\*\fun Config the I2C1 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1I2CDIV[2:0] +**/ +void RCC_ConfigI2C1KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear I2C1KERSEL[2:0] bits */ + reg_value &= RCC_I2C1KERCLK_SRC_MASK; + /* Set I2C1KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 8); + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C2KerClkSource. +*\*\fun Config the I2C2 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1I2CDIV[2:0] +**/ +void RCC_ConfigI2C2KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear I2C2KERSEL[2:0] bits */ + reg_value &= RCC_I2C2KERCLK_SRC_MASK; + /* Set I2C2KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 4); + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C3KerClkSource. +*\*\fun Config the I2C3 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1I2CDIV[2:0] +**/ +void RCC_ConfigI2C3KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear I2C3KERSEL[2:0] bits */ + reg_value &= RCC_I2C3KERCLK_SRC_MASK; + /* Set I2C3KERSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C1_3_KerSysDivider. +*\*\fun Config the I2C1/2/3 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_I2CKERCLK_SYSBUSDIV1 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV2 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV4 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV8 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigI2C1_3_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1I2CDIV[2:0] bits */ + reg_value &= RCC_I2C1_3_KERCLK_SYSBUSDIV_MASK; + /* Set the APB1I2CDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigI2C4KerClkSource. +*\*\fun Config the I2C4 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2I2CDIV[2:0] +**/ +void RCC_ConfigI2C4KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL1; + /* Clear I2C4KERSEL[2:0] bits */ + reg_value &= RCC_I2C4KERCLK_SRC_MASK; + /* Set I2C4KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 8); + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C5KerClkSource. +*\*\fun Config the I2C5 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2I2CDIV[2:0] +**/ +void RCC_ConfigI2C5KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL1; + /* Clear I2C5KERSEL[2:0] bits */ + reg_value &= RCC_I2C5KERCLK_SRC_MASK; + /* Set I2C5KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 12); + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C6KerClkSource. +*\*\fun Config the I2C6 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2I2CDIV[2:0] +**/ +void RCC_ConfigI2C6KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL1; + /* Clear I2C6KERSEL[2:0] bits */ + reg_value &= RCC_I2C6KERCLK_SRC_MASK; + /* Set I2C6KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 16); + /* Store the new value */ + RCC->APB2SEL1 = reg_value; + +} + + +/** +*\*\name RCC_ConfigI2C4_6_KerSysDivider. +*\*\fun Config the I2C4/5/6 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_I2CKERCLK_SYSBUSDIV1 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV2 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV4 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV8 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigI2C4_6_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB2DIV1; + /* Clear APB2I2CDIV[2:0] bits */ + reg_value &= RCC_I2C4_6_KERCLK_SYSBUSDIV_MASK; + /* Set the APB2I2CDIV[2:0] bits */ + reg_value |= (CLK_divider << 8); + /* Store the new value */ + RCC->APB2DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigI2C7KerClkSource. +*\*\fun Config the I2C7 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB5I2CDIV[2:0] +**/ +void RCC_ConfigI2C7KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB5SEL1; + /* Clear I2C7KERSEL[2:0] bits */ + reg_value &= RCC_I2C7KERCLK_SRC_MASK; + /* Set I2C7KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 8); + /* Store the new value */ + RCC->APB5SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C8KerClkSource. +*\*\fun Config the I2C8 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB5I2CDIV[2:0] +**/ +void RCC_ConfigI2C8KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB5SEL1; + /* Clear I2C8KERSEL[2:0] bits */ + reg_value &= RCC_I2C8KERCLK_SRC_MASK; + /* Set I2C8KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 4); + /* Store the new value */ + RCC->APB5SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C9KerClkSource. +*\*\fun Config the I2C9 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB5I2CDIV[2:0] +**/ +void RCC_ConfigI2C9KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB5SEL1; + /* Clear I2C9KERSEL[2:0] bits */ + reg_value &= RCC_I2C9KERCLK_SRC_MASK; + /* Set I2C9KERSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB5SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigI2C10KerClkSource. +*\*\fun Config the I2C10 kernel clock source. +*\*\param CLK_source(I2C kernel clock source): +*\*\ - RCC_I2CKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_I2CKERCLK_SRC_PLL3C +*\*\ - RCC_I2CKERCLK_SRC_HSI +*\*\ - RCC_I2CKERCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_I2CKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB5I2CDIV[2:0] +**/ +void RCC_ConfigI2C10KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB5SEL1; + /* Clear I2C10KERSEL[2:0] bits */ + reg_value &= RCC_I2C10KERCLK_SRC_MASK; + /* Set I2C10KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 4); + /* Store the new value */ + RCC->APB5SEL1 = reg_value; + +} + + +/** +*\*\name RCC_ConfigI2C7_10_KerSysDivider. +*\*\fun Config the I2C7/8/9/10 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_I2CKERCLK_SYSBUSDIV1 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV2 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV4 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV8 +*\*\ - RCC_I2CKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigI2C7_10_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB5DIV1; + /* Clear APB5I2CDIV[2:0] bits */ + reg_value &= RCC_I2C7_10_KERCLK_SYSBUSDIV_MASK; + /* Set the APB5I2CDIV[2:0] bits */ + reg_value |= (CLK_divider << 24); + /* Store the new value */ + RCC->APB5DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigFDCAN1KerClkSource. +*\*\fun Config the FDCAN1 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN1KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear FDCAN1KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN1KERCLK_SRC_MASK; + /* Set FDCAN1KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 8); + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN2KerClkSource. +*\*\fun Config the FDCAN2 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN2KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL1; + /* Clear FDCAN2KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN2KERCLK_SRC_MASK; + /* Set FDCAN2KERSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->APB1SEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN5KerClkSource. +*\*\fun Config the FDCAN5 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN5KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL2; + /* Clear FDCAN5KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN5KERCLK_SRC_MASK; + /* Set FDCAN5KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 20); + /* Store the new value */ + RCC->APB1SEL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN6KerClkSource. +*\*\fun Config the FDCAN6 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB1FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN6KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB1SEL2; + /* Clear FDCAN6KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN6KERCLK_SRC_MASK; + /* Set FDCAN6KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 12); + /* Store the new value */ + RCC->APB1SEL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN1_2_5_6_KerSysDivider. +*\*\fun Config the FDCAN1/2/5/6 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV1 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV2 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV4 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV8 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigFDCAN1_2_5_6_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB1DIV1; + /* Clear APB1FDCANDIV[2:0] bits */ + reg_value &= RCC_FDCAN1_2_5_6_KERCLK_SYSBUSDIV_MASK; + /* Set the APB1FDCANDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB1DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigFDCAN3KerClkSource. +*\*\fun Config the FDCAN3 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN3KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL2; + /* Clear FDCAN3KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN3KERCLK_SRC_MASK; + /* Set FDCAN3KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 20); + /* Store the new value */ + RCC->APB2SEL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN4KerClkSource. +*\*\fun Config the FDCAN4 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN4KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL2; + /* Clear FDCAN4KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN4KERCLK_SRC_MASK; + /* Set FDCAN4KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 12); + /* Store the new value */ + RCC->APB2SEL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN7KerClkSource. +*\*\fun Config the FDCAN7 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN7KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL2; + /* Clear FDCAN7KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN7KERCLK_SRC_MASK; + /* Set FDCAN7KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 4); + /* Store the new value */ + RCC->APB2SEL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN8KerClkSource. +*\*\fun Config the FDCAN8 kernel clock source. +*\*\param CLK_source(FDCAN kernel clock source): +*\*\ - RCC_FDCANKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_FDCANKERCLK_SRC_PLL1C +*\*\ - RCC_FDCANKERCLK_SRC_PLL2C +*\*\ - RCC_FDCANKERCLK_SRC_PLL3B +*\*\ - RCC_FDCANKERCLK_SRC_PERIPH +*\*\return none +*\*\note if select RCC_FDCANKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by APB2FDCANDIV[2:0] +**/ +void RCC_ConfigFDCAN8KerClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->APB2SEL2; + /* Clear FDCAN8KERSEL[2:0] bits */ + reg_value &= RCC_FDCAN8KERCLK_SRC_MASK; + /* Set FDCAN8KERSEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 4); + /* Store the new value */ + RCC->APB2SEL2 = reg_value; + +} + +/** +*\*\name RCC_ConfigFDCAN3_4_7_8_KerSysDivider. +*\*\fun Config the FDCAN3/4/7/8 kernel clock source (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV1 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV2 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV4 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV8 +*\*\ - RCC_FDCANKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigFDCAN3_4_7_8_KerSysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB2DIV1; + /* Clear APB2FDCANDIV[2:0] bits */ + reg_value &= RCC_FDCAN3_4_7_8_KERCLK_SYSBUSDIV_MASK; + /* Set the APB2FDCANDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB2DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigEXTISysDivider. +*\*\fun Config the EXTI (sys_bus_div_clk) divider. +*\*\param CLK_divider +*\*\ - RCC_EXTICLK_SYSBUSDIV1 +*\*\ - RCC_EXTICLK_SYSBUSDIV2 +*\*\ - RCC_EXTICLK_SYSBUSDIV4 +*\*\ - RCC_EXTICLK_SYSBUSDIV8 +*\*\ - RCC_EXTICLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigEXTISysDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->APB5DIV1; + /* Clear APB5EXTIDIV[2:0] bits */ + reg_value &= RCC_EXTI_SYSBUSDIV_MASK; + /* Set the APB5EXTIDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->APB5DIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigRtcClk. +*\*\fun Config the RTC clock. +*\*\param CLK_source: +*\*\ - RCC_RTCCLK_SRC_LSE +*\*\ - RCC_RTCCLK_SRC_LSI +*\*\ - RCC_RTCCLK_SRC_HSEDIV +*\*\param CLK_divider: +*\*\ - RCC_RTCCLK_HSEDIV1 +*\*\ - RCC_RTCCLK_HSEDIV2 +*\*\ - RCC_RTCCLK_HSEDIV3 +*\*\ - RCC_RTCCLK_HSEDIV4 +*\*\ - RCC_RTCCLK_HSEDIV5 +*\*\ - RCC_RTCCLK_HSEDIV6 +*\*\ - RCC_RTCCLK_HSEDIV7 +*\*\ - RCC_RTCCLK_HSEDIV8 +*\*\ - RCC_RTCCLK_HSEDIV9 +*\*\ - RCC_RTCCLK_HSEDIV10 +*\*\ - RCC_RTCCLK_HSEDIV11 +*\*\ - RCC_RTCCLK_HSEDIV12 +*\*\ - RCC_RTCCLK_HSEDIV13 +*\*\ - RCC_RTCCLK_HSEDIV14 +*\*\ - RCC_RTCCLK_HSEDIV15 +*\*\ - RCC_RTCCLK_HSEDIV16 +*\*\ - RCC_RTCCLK_HSEDIV17 +*\*\ - RCC_RTCCLK_HSEDIV18 +*\*\ - RCC_RTCCLK_HSEDIV19 +*\*\ - RCC_RTCCLK_HSEDIV20 +*\*\ - RCC_RTCCLK_HSEDIV21 +*\*\ - RCC_RTCCLK_HSEDIV22 +*\*\ - RCC_RTCCLK_HSEDIV23 +*\*\ - RCC_RTCCLK_HSEDIV24 +*\*\ - RCC_RTCCLK_HSEDIV25 +*\*\ - RCC_RTCCLK_HSEDIV26 +*\*\ - RCC_RTCCLK_HSEDIV27 +*\*\ - RCC_RTCCLK_HSEDIV28 +*\*\ - RCC_RTCCLK_HSEDIV29 +*\*\ - RCC_RTCCLK_HSEDIV30 +*\*\ - RCC_RTCCLK_HSEDIV31 +*\*\ - RCC_RTCCLK_HSEDIV32 +*\*\ - RCC_RTCCLK_HSEDIV33 +*\*\ - RCC_RTCCLK_HSEDIV34 +*\*\ - RCC_RTCCLK_HSEDIV35 +*\*\ - RCC_RTCCLK_HSEDIV36 +*\*\ - RCC_RTCCLK_HSEDIV37 +*\*\ - RCC_RTCCLK_HSEDIV38 +*\*\ - RCC_RTCCLK_HSEDIV39 +*\*\ - RCC_RTCCLK_HSEDIV40 +*\*\ - RCC_RTCCLK_HSEDIV41 +*\*\ - RCC_RTCCLK_HSEDIV42 +*\*\ - RCC_RTCCLK_HSEDIV43 +*\*\ - RCC_RTCCLK_HSEDIV44 +*\*\ - RCC_RTCCLK_HSEDIV45 +*\*\ - RCC_RTCCLK_HSEDIV46 +*\*\ - RCC_RTCCLK_HSEDIV47 +*\*\ - RCC_RTCCLK_HSEDIV48 +*\*\ - RCC_RTCCLK_HSEDIV49 +*\*\ - RCC_RTCCLK_HSEDIV50 +*\*\ - RCC_RTCCLK_HSEDIV51 +*\*\ - RCC_RTCCLK_HSEDIV52 +*\*\ - RCC_RTCCLK_HSEDIV53 +*\*\ - RCC_RTCCLK_HSEDIV54 +*\*\ - RCC_RTCCLK_HSEDIV55 +*\*\ - RCC_RTCCLK_HSEDIV56 +*\*\ - RCC_RTCCLK_HSEDIV57 +*\*\ - RCC_RTCCLK_HSEDIV58 +*\*\ - RCC_RTCCLK_HSEDIV59 +*\*\ - RCC_RTCCLK_HSEDIV60 +*\*\ - RCC_RTCCLK_HSEDIV61 +*\*\ - RCC_RTCCLK_HSEDIV62 +*\*\ - RCC_RTCCLK_HSEDIV63 +*\*\return none +*\*\note if select RCC_RTCCLK_SRC_HSEDIV then set the HSE divider by RTCHSEDIV[5:0] +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_ConfigRtcClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->BDCTRL; + /* Clear RTCSEL[2:0] bits */ + reg_value &= RCC_RTCCLK_SRC_MASK; + /* Set RTCSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->BDCTRL = reg_value; + + if(CLK_source == RCC_RTCCLK_SRC_HSEDIV) + { + reg_value1 = RCC->CFG5; + /* Clear RTCHSEDIV[5:0] bits */ + reg_value1 &= RCC_RTCCLK_HSEDIV_MASK; + /* Set the RTCHSEDIV[5:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->CFG5 = reg_value1; + } + +} + +/** +*\*\name RCC_EnableRtcClk. +*\*\fun Enables the RTC clock. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note This function must be used only after the RTC clock was selected +*\*\ using the RCC_ConfigRtcClk function. +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableRtcClk(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + RCC->BDCTRL |= RCC_RTC_ENABLE; + } + else + { + RCC->BDCTRL &= (~RCC_RTC_ENABLE); + } +} + +/** +*\*\name RCC_EnableBackupReset. +*\*\fun Reset Backup domain . +*\*\param none +*\*\return none. +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableBackupReset(void) +{ + RCC->BDCTRL |= (RCC_BKUP_RESET); + RCC->BDCTRL &= (~RCC_BKUP_RESET); +} + +/** +*\*\name RCC_EnableDCMUReset. +*\*\fun Reset DCMU. +*\*\param none +*\*\return none. +**/ +void RCC_EnableDCMUReset(void) +{ + RCC->CFG4 |= (RCC_DCMU_RESET); + RCC->CFG4 &= (~RCC_DCMU_RESET); +} + +/** +*\*\name RCC_ConfigLPTIM1Clk. +*\*\fun Config the LPTIM1 clock source. +*\*\param CLK_source: +*\*\ - RCC_LPTIMCLK_SRC_APB5 +*\*\ - RCC_LPTIMCLK_SRC_LSI +*\*\ - RCC_LPTIMCLK_SRC_LSE +*\*\ - RCC_LPTIMCLK_SRC_HSE +*\*\ - RCC_LPTIMCLK_SRC_HSI +*\*\ - RCC_LPTIMCLK_SRC_MSI +*\*\ - RCC_LPTIMCLK_SRC_COMP1 +*\*\ - RCC_LPTIMCLK_SRC_COMP2 +*\*\ - RCC_LPTIMCLK_SRC_COMP3 +*\*\ - RCC_LPTIMCLK_SRC_COMP4 +*\*\return none +*\*\note none +**/ +void RCC_ConfigLPTIM1Clk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPTIM1SEL[3:0] bits */ + reg_value &= RCC_LPTIM1CLK_SRC_MASK; + /* Set LPTIM1SEL[3:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_EnableLPTIM1CompGate. +*\*\fun Enable gate signal from COMPx to LPTIM1. +*\*\param COMP_sel(select one COMPx) : +*\*\ -RCC_GATEEN_LPTIM1_COMP1 +*\*\ -RCC_GATEEN_LPTIM1_COMP2 +*\*\ -RCC_GATEEN_LPTIM1_COMP3 +*\*\ -RCC_GATEEN_LPTIM1_COMP4 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If the LPTIM clock source is COMP, you need to enable this gate +**/ +void RCC_EnableLPTIM1CompGate(uint32_t COMP_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL1 |= COMP_sel; + } + else + { + RCC->RDCTRL1 &= ~COMP_sel; + } + +} + +/** +*\*\name RCC_ConfigLPTIM2Clk. +*\*\fun Config the LPTIM2 clock source. +*\*\param CLK_source: +*\*\ - RCC_LPTIMCLK_SRC_APB5 +*\*\ - RCC_LPTIMCLK_SRC_LSI +*\*\ - RCC_LPTIMCLK_SRC_LSE +*\*\ - RCC_LPTIMCLK_SRC_HSE +*\*\ - RCC_LPTIMCLK_SRC_HSI +*\*\ - RCC_LPTIMCLK_SRC_MSI +*\*\ - RCC_LPTIMCLK_SRC_COMP1 +*\*\ - RCC_LPTIMCLK_SRC_COMP2 +*\*\ - RCC_LPTIMCLK_SRC_COMP3 +*\*\ - RCC_LPTIMCLK_SRC_COMP4 +*\*\return none +*\*\note none +**/ +void RCC_ConfigLPTIM2Clk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPTIM2SEL[3:0] bits */ + reg_value &= RCC_LPTIM2CLK_SRC_MASK; + /* Set LPTIM2SEL[3:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 4); + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_EnableLPTIM2CompGate. +*\*\fun Enable gate signal from COMPx to LPTIM2. +*\*\param COMP_sel(select one COMPx) : +*\*\ -RCC_GATEEN_LPTIM2_COMP1 +*\*\ -RCC_GATEEN_LPTIM2_COMP2 +*\*\ -RCC_GATEEN_LPTIM2_COMP3 +*\*\ -RCC_GATEEN_LPTIM2_COMP4 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If the LPTIM clock source is COMP, you need to enable this gate +**/ +void RCC_EnableLPTIM2CompGate(uint32_t COMP_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL1 |= COMP_sel; + } + else + { + RCC->RDCTRL1 &= ~COMP_sel; + } + +} + +/** +*\*\name RCC_ConfigLPTIM3Clk. +*\*\fun Config the LPTIM3 clock source. +*\*\param CLK_source: +*\*\ - RCC_LPTIMCLK_SRC_APB5 +*\*\ - RCC_LPTIMCLK_SRC_LSI +*\*\ - RCC_LPTIMCLK_SRC_LSE +*\*\ - RCC_LPTIMCLK_SRC_HSE +*\*\ - RCC_LPTIMCLK_SRC_HSI +*\*\ - RCC_LPTIMCLK_SRC_MSI +*\*\ - RCC_LPTIMCLK_SRC_COMP1 +*\*\ - RCC_LPTIMCLK_SRC_COMP2 +*\*\ - RCC_LPTIMCLK_SRC_COMP3 +*\*\ - RCC_LPTIMCLK_SRC_COMP4 +*\*\return none +*\*\note none +**/ +void RCC_ConfigLPTIM3Clk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPTIM3SEL[3:0] bits */ + reg_value &= RCC_LPTIM3CLK_SRC_MASK; + /* Set LPTIM3SEL[3:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 8); + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_EnableLPTIM3CompGate. +*\*\fun Enable gate signal from COMPx to LPTIM3. +*\*\param COMP_sel(select one COMPx) : +*\*\ -RCC_GATEEN_LPTIM3_COMP1 +*\*\ -RCC_GATEEN_LPTIM3_COMP2 +*\*\ -RCC_GATEEN_LPTIM3_COMP3 +*\*\ -RCC_GATEEN_LPTIM3_COMP4 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If the LPTIM clock source is COMP, you need to enable this gate +**/ +void RCC_EnableLPTIM3CompGate(uint32_t COMP_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL2 |= COMP_sel; + } + else + { + RCC->RDCTRL2 &= ~COMP_sel; + } + +} + +/** +*\*\name RCC_ConfigLPTIM4Clk. +*\*\fun Config the LPTIM4 clock source. +*\*\param CLK_source: +*\*\ - RCC_LPTIMCLK_SRC_APB5 +*\*\ - RCC_LPTIMCLK_SRC_LSI +*\*\ - RCC_LPTIMCLK_SRC_LSE +*\*\ - RCC_LPTIMCLK_SRC_HSE +*\*\ - RCC_LPTIMCLK_SRC_HSI +*\*\ - RCC_LPTIMCLK_SRC_MSI +*\*\ - RCC_LPTIMCLK_SRC_COMP1 +*\*\ - RCC_LPTIMCLK_SRC_COMP2 +*\*\ - RCC_LPTIMCLK_SRC_COMP3 +*\*\ - RCC_LPTIMCLK_SRC_COMP4 +*\*\return none +*\*\note none +**/ +void RCC_ConfigLPTIM4Clk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPTIM4SEL[3:0] bits */ + reg_value &= RCC_LPTIM4CLK_SRC_MASK; + /* Set LPTIM4SEL[3:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 12); + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_EnableLPTIM4CompGate. +*\*\fun Enable gate signal from COMPx to LPTIM4. +*\*\param COMP_sel(select one COMPx) : +*\*\ -RCC_GATEEN_LPTIM4_COMP1 +*\*\ -RCC_GATEEN_LPTIM4_COMP2 +*\*\ -RCC_GATEEN_LPTIM4_COMP3 +*\*\ -RCC_GATEEN_LPTIM4_COMP4 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If the LPTIM clock source is COMP, you need to enable this gate +**/ +void RCC_EnableLPTIM4CompGate(uint32_t COMP_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL2 |= COMP_sel; + } + else + { + RCC->RDCTRL2 &= ~COMP_sel; + } + +} + +/** +*\*\name RCC_ConfigLPTIM5Clk. +*\*\fun Config the LPTIM5 clock source. +*\*\param CLK_source: +*\*\ - RCC_LPTIMCLK_SRC_APB5 +*\*\ - RCC_LPTIMCLK_SRC_LSI +*\*\ - RCC_LPTIMCLK_SRC_LSE +*\*\ - RCC_LPTIMCLK_SRC_HSE +*\*\ - RCC_LPTIMCLK_SRC_HSI +*\*\ - RCC_LPTIMCLK_SRC_MSI +*\*\ - RCC_LPTIMCLK_SRC_COMP1 +*\*\ - RCC_LPTIMCLK_SRC_COMP2 +*\*\ - RCC_LPTIMCLK_SRC_COMP3 +*\*\ - RCC_LPTIMCLK_SRC_COMP4 +*\*\return none +*\*\note none +**/ +void RCC_ConfigLPTIM5Clk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPTIM5SEL[3:0] bits */ + reg_value &= RCC_LPTIM5CLK_SRC_MASK; + /* Set LPTIM5SEL[3:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 16); + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_EnableLPTIM5CompGate. +*\*\fun Enable gate signal from COMPx to LPTIM5. +*\*\param COMP_sel(select one COMPx) : +*\*\ -RCC_GATEEN_LPTIM5_COMP1 +*\*\ -RCC_GATEEN_LPTIM5_COMP2 +*\*\ -RCC_GATEEN_LPTIM5_COMP3 +*\*\ -RCC_GATEEN_LPTIM5_COMP4 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note If the LPTIM clock source is COMP, you need to enable this gate +**/ +void RCC_EnableLPTIM5CompGate(uint32_t COMP_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL3 |= COMP_sel; + } + else + { + RCC->RDCTRL3 &= ~COMP_sel; + } + +} + +/** +*\*\name RCC_ConfigLPUART1ClkSource. +*\*\fun Config the LPUART1 kernel clock Source. +*\*\param CLK_source: +*\*\ - RCC_LPUARTCLK_SRC_SYSBUSDIV +*\*\ - RCC_LPUARTCLK_SRC_HSI +*\*\ - RCC_LPUARTCLK_SRC_LSE +*\*\ - RCC_LPUARTCLK_SRC_HSE +*\*\ - RCC_LPUARTCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_LPUARTCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by LPUARTDIV[2:0] +**/ +void RCC_ConfigLPUART1ClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPUART1SEL[2:0] bits */ + reg_value &= RCC_LPUART1CLK_SRC_MASK; + /* Set LPUART1SEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->RDSEL1 = reg_value; +} + +/** +*\*\name RCC_ConfigLPUART2ClkSource. +*\*\fun Config the LPUART2 kernel clock Source. +*\*\param CLK_source: +*\*\ - RCC_LPUARTCLK_SRC_SYSBUSDIV +*\*\ - RCC_LPUARTCLK_SRC_HSI +*\*\ - RCC_LPUARTCLK_SRC_LSE +*\*\ - RCC_LPUARTCLK_SRC_HSE +*\*\ - RCC_LPUARTCLK_SRC_MSI +*\*\return none +*\*\note if select RCC_LPUARTCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by LPUARTDIV[2:0] +**/ +void RCC_ConfigLPUART2ClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear LPUART2SEL[2:0] bits */ + reg_value &= RCC_LPUART2CLK_SRC_MASK; + /* Set LPUART2SEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 4); + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigLPUART1_2_ClkDivider. +*\*\fun Config the LPUART1/2 kernel clock system divider. +*\*\param CLK_divider: +*\*\ - RCC_LPUARTCLK_SYSBUSDIV1 +*\*\ - RCC_LPUARTCLK_SYSBUSDIV2 +*\*\ - RCC_LPUARTCLK_SYSBUSDIV4 +*\*\ - RCC_LPUARTCLK_SYSBUSDIV8 +*\*\ - RCC_LPUARTCLK_SYSBUSDIV16 +*\*\return none +*\*\note if select RCC_LPUARTCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by LPUARTDIV[2:0] +**/ +void RCC_ConfigLPUART1_2_ClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->RDDIV1; + /* Clear LPUARTDIV[2:0] bits */ + reg_value &= RCC_LPUARTCLK_SYSBUSDIV_MASK; + /* Set the LPUARTDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->RDDIV1 = reg_value; + +} + + +/** +*\*\name RCC_ConfigCOMPLsxClk. +*\*\fun Config the COMP low speed clock source. +*\*\param CLK_source: +*\*\ - RCC_COMPLSXCLK_SRC_LSI +*\*\ - RCC_COMPLSXCLK_SRC_LSE +*\*\return none +*\*\note none +**/ +void RCC_ConfigCOMPLsxClk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->RDSEL1; + /* Clear COMPSEL bits */ + reg_value &= RCC_COMPLSXCLK_SRC_MASK; + /* Set COMPSEL bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->RDSEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigCOMPKerClk. +*\*\fun Config the COMP kernel clock divider from sys_bus_div_clk. +*\*\param CLK_divider +*\*\ - RCC_COMPKERCLK_SYSBUSDIV1 +*\*\ - RCC_COMPKERCLK_SYSBUSDIV2 +*\*\ - RCC_COMPKERCLK_SYSBUSDIV4 +*\*\ - RCC_COMPKERCLK_SYSBUSDIV8 +*\*\ - RCC_COMPKERCLK_SYSBUSDIV16 +*\*\return none +*\*\note none +**/ +void RCC_ConfigCOMPKerClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->RDDIV1; + /* Clear COMPDIV[2:0] bits */ + reg_value &= RCC_COMPKERCLK_SYSBUSDIV_MASK; + /* Set the COMPDIV[2:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->RDDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigFEMCM0Clk. +*\*\fun Config the FEMC M0 clock. +*\*\param CLK_source: +*\*\ - RCC_FEMCCLK_SRC_AXIDIV +*\*\ - RCC_FEMCCLK_SRC_PERIPH +*\*\ - RCC_FEMCCLK_SRC_PLL2C +*\*\ - RCC_FEMCCLK_SRC_PLL3B +*\*\ - RCC_FEMCCLK_SRC_PLL1B +*\*\param CLK_divider: +*\*\ - RCC_FEMCCLK_AXIDIV1 +*\*\ - RCC_FEMCCLK_AXIDIV2 +*\*\ - RCC_FEMCCLK_AXIDIV3 +*\*\ - RCC_FEMCCLK_AXIDIV4 +*\*\ - RCC_FEMCCLK_AXIDIV5 +*\*\ - RCC_FEMCCLK_AXIDIV6 +*\*\ - RCC_FEMCCLK_AXIDIV7 +*\*\ - RCC_FEMCCLK_AXIDIV8 +*\*\ - RCC_FEMCCLK_AXIDIV9 +*\*\ - RCC_FEMCCLK_AXIDIV10 +*\*\ - RCC_FEMCCLK_AXIDIV11 +*\*\ - RCC_FEMCCLK_AXIDIV12 +*\*\ - RCC_FEMCCLK_AXIDIV13 +*\*\ - RCC_FEMCCLK_AXIDIV14 +*\*\ - RCC_FEMCCLK_AXIDIV15 +*\*\return none +*\*\note if select RCC_FEMCCLK_SRC_AXIDIV then set the AXI clock divider by FEMCM0SYSDIV[3:0] +**/ +void RCC_ConfigFEMCM0Clk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL2; + /* Clear FEMCM0SEL[2:0] bits */ + reg_value &= RCC_FEMCM0CLK_SRC_MASK; + /* Set FEMCM0SEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL2 = reg_value; + + if(CLK_source == RCC_FEMCCLK_SRC_AXIDIV) + { + reg_value1 = RCC->AXIDIV2; + /* Clear FEMCM0AXIDIV[3:0] bits */ + reg_value1 &= RCC_FEMCM0CLK_AXIDIV_MASK; + /* Set the FEMCM0AXIDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV2 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigFEMCM1Clk. +*\*\fun Config the FEMC M1 clock. +*\*\param CLK_source: +*\*\ - RCC_FEMCCLK_SRC_AXIDIV +*\*\ - RCC_FEMCCLK_SRC_PERIPH +*\*\ - RCC_FEMCCLK_SRC_PLL2C +*\*\ - RCC_FEMCCLK_SRC_PLL3B +*\*\ - RCC_FEMCCLK_SRC_PLL1B +*\*\param CLK_divider: +*\*\ - RCC_FEMCCLK_AXIDIV1 +*\*\ - RCC_FEMCCLK_AXIDIV2 +*\*\ - RCC_FEMCCLK_AXIDIV3 +*\*\ - RCC_FEMCCLK_AXIDIV4 +*\*\ - RCC_FEMCCLK_AXIDIV5 +*\*\ - RCC_FEMCCLK_AXIDIV6 +*\*\ - RCC_FEMCCLK_AXIDIV7 +*\*\ - RCC_FEMCCLK_AXIDIV8 +*\*\ - RCC_FEMCCLK_AXIDIV9 +*\*\ - RCC_FEMCCLK_AXIDIV10 +*\*\ - RCC_FEMCCLK_AXIDIV11 +*\*\ - RCC_FEMCCLK_AXIDIV12 +*\*\ - RCC_FEMCCLK_AXIDIV13 +*\*\ - RCC_FEMCCLK_AXIDIV14 +*\*\ - RCC_FEMCCLK_AXIDIV15 +*\*\return none +*\*\note if select RCC_FEMCCLK_SRC_AXIDIV then set the AXI clock divider by FEMCM1SYSDIV[3:0] +**/ +void RCC_ConfigFEMCM1Clk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL2; + /* Clear FEMCM1SEL[2:0] bits */ + reg_value &= RCC_FEMCM1CLK_SRC_MASK; + /* Set FEMCM1SEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source << 4); + /* Store the new value */ + RCC->AXISEL2 = reg_value; + + if(CLK_source == RCC_FEMCCLK_SRC_AXIDIV) + { + reg_value1 = RCC->AXIDIV2; + /* Clear FEMCM1AXIDIV[3:0] bits */ + reg_value1 &= RCC_FEMCM1CLK_AXIDIV_MASK; + /* Set the FEMCM1AXIDIV[3:0] bits */ + reg_value1 |= (CLK_divider << 4); + /* Store the new value */ + RCC->AXIDIV2 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigDSIRefClk. +*\*\fun Config the DSI reference clock divider from HSE. +*\*\param CLK_divider: +*\*\ - RCC_DSIREFCLK_HSE_DIV1 +*\*\ - RCC_DSIREFCLK_HSE_DIV2 +*\*\return none +*\*\note none +**/ +void RCC_ConfigDSIRefClk(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->CFG5; + /* Clear DSIHSEDIV[3:0] bits */ + reg_value &= RCC_DSIREFCLK_HSE_DIV_MASK; + /* Set the DSIHSEDIV[3:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->CFG5 = reg_value; + +} + +/** +*\*\name RCC_ConfigDSIKerClk. +*\*\fun Config the DSI kernel clock divider from HSE. +*\*\param CLK_source: +*\*\ - RCC_DSIKERCLK_SRC_REF +*\*\ - RCC_DSIKERCLK_SRC_PLL3C +*\*\return none +*\*\note none +**/ +void RCC_ConfigDSIKerClk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->AXISEL1; + /* Clear DSIKERSEL[1:0] bits */ + reg_value &= RCC_DSIKERCLK_SRC_MASK; + /* Set the DSIKERSEL[1:0] bits */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigDSIPpitxClk. +*\*\fun Config the DSI PPI TXCLKESC clock. +*\*\param CLK_source: +*\*\ - RCC_DSIPPICLK_SRC_REFDIV +*\*\ - RCC_DSIPPICLK_SRC_PLL2B +*\*\ - RCC_DSIPPICLK_SRC_PERIPH +*\*\ - RCC_DSIPPICLK_SRC_AXIDIV +*\*\param CLK_divider: +*\*\ - RCC_DSIPPICLK_DIV1 +*\*\ - RCC_DSIPPICLK_DIV2 +*\*\ - RCC_DSIPPICLK_DIV4 +*\*\ - RCC_DSIPPICLK_DIV8 +*\*\ - RCC_DSIPPICLK_DIV16 +*\*\ - RCC_DSIPPICLK_DIV32 +*\*\ - RCC_DSIPPICLK_DIV64 +*\*\ - RCC_DSIPPICLK_DIV128 +*\*\ - RCC_DSIPPICLK_DIV256 +*\*\ - RCC_DSIPPICLK_DIV512 +*\*\return none +*\*\note if select RCC_DSIPPICLK_SRC_REFDIV then set the REF clock divider by DSIREFDIV[3:0], +*\*\ if select RCC_DSIPPICLK_SRC_AXIDIV then set the AXI clock divider by DSIAXIPPIDIV[3:0] +**/ +void RCC_ConfigDSIPpitxClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL1; + /* Clear DSIPPITXSEL[1:0] bits */ + reg_value &= RCC_DSIPPICLK_SRC_MASK; + /* Set DSIPPITXSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + + if(CLK_source == RCC_DSIPPICLK_SRC_REFDIV) + { + reg_value1 = RCC->AXIDIV1; + /* Clear DSIREFDIV[3:0] bits */ + reg_value1 &= RCC_DSIPPICLK_REFDIV_MASK; + /* Set the DSIREFDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV1 = reg_value1; + } + else if(CLK_source == RCC_DSIPPICLK_SRC_AXIDIV) + { + reg_value1 = RCC->AXIDIV2; + /* Clear DSIAXIPPIDIV[3:0] bits */ + reg_value1 &= RCC_DSIPPICLK_AXIDIV_MASK; + /* Set the DSIAXIPPIDIV[3:0] bits */ + reg_value1 |= (CLK_divider << 4); + /* Store the new value */ + RCC->AXIDIV2 = reg_value1; + } + else + { + /* no process */ + } + +} + +/** +*\*\name RCC_ConfigDSIUlpsClk. +*\*\fun Config the DSI ULPS TXCLKESC clock. +*\*\param CLK_source: +*\*\ - RCC_DSIULPSCLK_SRC_REFDIV +*\*\ - RCC_DSIULPSCLK_SRC_PLL3C +*\*\param CLK_divider: +*\*\ - RCC_DSIULPSCLK_REFDIV1 +*\*\ - RCC_DSIULPSCLK_REFDIV2 +*\*\ - RCC_DSIULPSCLK_REFDIV4 +*\*\ - RCC_DSIULPSCLK_REFDIV8 +*\*\ - RCC_DSIULPSCLK_REFDIV16 +*\*\ - RCC_DSIULPSCLK_REFDIV32 +*\*\ - RCC_DSIULPSCLK_REFDIV64 +*\*\ - RCC_DSIULPSCLK_REFDIV128 +*\*\ - RCC_DSIULPSCLK_REFDIV256 +*\*\ - RCC_DSIULPSCLK_REFDIV512 +*\*\return none +*\*\note if select RCC_DSIULPSCLK_SRC_REFDIV then set the REF clock divider by DSIREFULPSDIV[3:0] +**/ +void RCC_ConfigDSIUlpsClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL1; + /* Clear DSIULPSSEL[1:0] bits */ + reg_value &= RCC_DSIULPSCLK_SRC_MASK; + /* Set DSIULPSSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + + if(CLK_source == RCC_DSIULPSCLK_SRC_REFDIV) + { + reg_value1 = RCC->AXIDIV2; + /* Clear DSIREFULPSDIV[3:0] bits */ + reg_value1 &= RCC_DSIULPSCLK_REFDIV_MASK; + /* Set the DSIREFULPSDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV2 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigLCDCPixelClk. +*\*\fun Config the LCDC pixel clock. +*\*\param CLK_source: +*\*\ - RCC_LCDCPIXELCLK_SRC_AXIDIV +*\*\ - RCC_LCDCPIXELCLK_SRC_PERIPH +*\*\ - RCC_LCDCPIXELCLK_SRC_PLL2C +*\*\ - RCC_LCDCPIXELCLK_SRC_PLL3B +*\*\param CLK_divider: +*\*\ - RCC_LCDCPIXELCLK_AXIDIV1 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV2 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV4 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV8 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV16 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV32 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV64 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV128 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV256 +*\*\ - RCC_LCDCPIXELCLK_AXIDIV512 +*\*\return none +*\*\note if select RCC_LCDCPIXELCLK_SRC_AXIDIV then set the AXI clock divider by LCDCAXIDIV[3:0] +**/ +void RCC_ConfigLCDCPixelClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL1; + /* Clear LCDCKERSEL[1:0] bits */ + reg_value &= RCC_LCDCPIXELCLK_SRC_MASK; + /* Set LCDCKERSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + + if(CLK_source == RCC_LCDCPIXELCLK_SRC_AXIDIV) + { + reg_value1 = RCC->AXIDIV1; + /* Clear LCDCAXIDIV[3:0] bits */ + reg_value1 &= RCC_LCDCPIXELCLK_AXIDIV_MASK; + /* Set the LCDCAXIDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigDVP1MClkSource. +*\*\fun Config the DVP1 M clock source. +*\*\param CLK_source: +*\*\ - RCC_DVPMCLK_SRC_AXIDIV +*\*\ - RCC_DVPMCLK_SRC_PERIPH +*\*\ - RCC_DVPMCLK_SRC_PLL2C +*\*\ - RCC_DVPMCLK_SRC_PLL3A +*\*\return none +*\*\note if select RCC_DVPMCLK_SRC_AXIDIV then set the AXI clock divider by DVPMAXIDIV[3:0] +**/ +void RCC_ConfigDVP1MClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->AXISEL1; + /* Clear DVP1MSEL[1:0] bits */ + reg_value &= RCC_DVP1MCLK_SRC_MASK; + /* Set DVP1MSEL[1:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigDVP2MClkSource. +*\*\fun Config the DVP2 M clock source. +*\*\param CLK_source: +*\*\ - RCC_DVPMCLK_SRC_AXIDIV +*\*\ - RCC_DVPMCLK_SRC_PERIPH +*\*\ - RCC_DVPMCLK_SRC_PLL2C +*\*\ - RCC_DVPMCLK_SRC_PLL3A +*\*\return none +*\*\note if select RCC_DVPMCLK_SRC_AXIDIV then set the AXI clock divider by DVPMAXIDIV[3:0] +**/ +void RCC_ConfigDVP2MClkSource(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->AXISEL1; + /* Clear DVP2MSEL[1:0] bits */ + reg_value &= RCC_DVP2MCLK_SRC_MASK; + /* Set DVP2MSEL[1:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 2); + /* Store the new value */ + RCC->AXISEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigDVP1_2_MClkDivider. +*\*\fun Config the DVP1/2 M clock AXI divider. +*\*\param CLK_divider: +*\*\ - RCC_DVPMCLK_AXIDIV1 +*\*\ - RCC_DVPMCLK_AXIDIV2 +*\*\ - RCC_DVPMCLK_AXIDIV4 +*\*\ - RCC_DVPMCLK_AXIDIV8 +*\*\ - RCC_DVPMCLK_AXIDIV16 +*\*\ - RCC_DVPMCLK_AXIDIV32 +*\*\ - RCC_DVPMCLK_AXIDIV64 +*\*\ - RCC_DVPMCLK_AXIDIV128 +*\*\ - RCC_DVPMCLK_AXIDIV256 +*\*\ - RCC_DVPMCLK_AXIDIV512 +*\*\return none +**/ +void RCC_ConfigDVP1_2_MClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->AXIDIV1; + /* Clear DVPMAXIDIV[3:0] bits */ + reg_value &= RCC_DVPMCLK_AXIDIV_MASK; + /* Set the DVPMAXIDIV[3:0] bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV1 = reg_value; +} + +/** +*\*\name RCC_ConfigXSPI1SSIClk. +*\*\fun Config the XSPI1 SSI clock. +*\*\param CLK_source: +*\*\ - RCC_XSPISSICLK_SRC_AXI +*\*\ - RCC_XSPISSICLK_SRC_PLL3C +*\*\ - RCC_XSPISSICLK_SRC_PLL1B +*\*\ - RCC_XSPISSICLK_SRC_PLL2A +*\*\ - RCC_XSPISSICLK_SRC_PLL2C +*\*\return none +**/ +void RCC_ConfigXSPI1SSIClk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->AXISEL1; + /* Clear XSPI1SSISEL[2:0] bits */ + reg_value &= RCC_XSPI1SSICLK_SRC_MASK; + /* Set XSPI1SSISEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigXSPI2SSIClk. +*\*\fun Config the XSPI2 SSI clock. +*\*\param CLK_source: +*\*\ - RCC_XSPISSICLK_SRC_AXI +*\*\ - RCC_XSPISSICLK_SRC_PLL3C +*\*\ - RCC_XSPISSICLK_SRC_PLL1B +*\*\ - RCC_XSPISSICLK_SRC_PLL2A +*\*\ - RCC_XSPISSICLK_SRC_PLL2C +*\*\return none +**/ +void RCC_ConfigXSPI2SSIClk(uint32_t CLK_source) +{ + uint32_t reg_value; + + reg_value = RCC->AXISEL1; + /* Clear XSPI2SSISEL[2:0] bits */ + reg_value &= RCC_XSPI2SSICLK_SRC_MASK; + /* Set XSPI2SSISEL[2:0] bits according to CLK_source value */ + reg_value |= (CLK_source >> 4); + /* Store the new value */ + RCC->AXISEL1 = reg_value; + +} + +/** +*\*\name RCC_ConfigSDRAMMemClk. +*\*\fun Config the SDRAM memory clock. +*\*\param CLK_source: +*\*\ - RCC_SDRAMMEMCLK_SRC_AXIDIV +*\*\ - RCC_SDRAMMEMCLK_SRC_PERIPH +*\*\ - RCC_SDRAMMEMCLK_SRC_PLL2A +*\*\ - RCC_SDRAMMEMCLK_SRC_PLL3A +*\*\ - RCC_SDRAMMEMCLK_SRC_PLL1B +*\*\param CLK_divider: +*\*\ - RCC_SDRAMMEMCLK_AXIDIV1 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV2 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV4 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV8 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV16 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV32 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV64 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV128 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV256 +*\*\ - RCC_SDRAMMEMCLK_AXIDIV512 +*\*\return none +*\*\note if select RCC_SDRAMMEMCLK_SRC_AXIDIV then set the AXI clock divider by SDRAMMEMDIV[3:0] +**/ +void RCC_ConfigSDRAMMemClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AXISEL2; + /* Clear SDRAMMEMSEL[2:0] bits */ + reg_value &= RCC_SDRAMMEMCLK_SRC_MASK; + /* Set SDRAMMEMSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AXISEL2 = reg_value; + + if(CLK_source == RCC_SDRAMMEMCLK_SRC_AXIDIV) + { + reg_value1 = RCC->AXIDIV2; + /* Clear SDRAMMEMDIV[3:0] bits */ + reg_value1 &= RCC_SDRAMMEMCLK_AXIDIV_MASK; + /* Set the SDRAMMEMDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AXIDIV2 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigETHERCATKerClk. +*\*\fun Config the ETHERCAT kernel clock. +*\*\param CLK_source: +*\*\ - RCC_ESCKERCLK_SRC_SYSBUSDIV +*\*\ - RCC_ESCKERCLK_SRC_PLL2B +*\*\ - RCC_ESCKERCLK_SRC_PLL3A +*\*\ - RCC_ESCKERCLK_SRC_PLL3C +*\*\ - RCC_ESCKERCLK_SRC_PLL1B +*\*\param CLK_divider: +*\*\ - RCC_ESCKERCLK_SYSBUSDIV1 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV2 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV4 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV8 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV16 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV32 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV64 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV128 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV256 +*\*\ - RCC_ESCKERCLK_SYSBUSDIV512 +*\*\return none +*\*\note if select RCC_ESCKERCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by ESCSYSDIV[3:0] +*\*\note You need to make sure that the ETHERCAT kernel clock frequency is 100MHz +**/ +void RCC_ConfigETHERCATKerClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->AHB9SEL1; + /* Clear ESCKERSEL[2:0] bits */ + reg_value &= RCC_ESCKERCLK_SRC_MASK; + /* Set ESCKERSEL[2:0] bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->AHB9SEL1 = reg_value; + + if(CLK_source == RCC_ESCKERCLK_SRC_SYSBUSDIV) + { + reg_value1 = RCC->AHB9DIV1; + /* Clear ESCSYSDIV[3:0] bits */ + reg_value1 &= RCC_ESCKERCLK_SYSBUSDIV_MASK; + /* Set the ESCSYSDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->AHB9DIV1 = reg_value1; + } + +} + +/** +*\*\name RCC_ConfigTRNGClk. +*\*\fun Config the TRNG clock. +*\*\param CLK_source: +*\*\ - RCC_TRNGCLK_SRC_SYSBUSDIV +*\*\ - RCC_TRNGCLK_SRC_HSI +*\*\param CLK_divider: +*\*\ - RCC_TRNGCLK_SYSBUSDIV1 +*\*\ - RCC_TRNGCLK_SYSBUSDIV2 +*\*\ - RCC_TRNGCLK_SYSBUSDIV4 +*\*\ - RCC_TRNGCLK_SYSBUSDIV8 +*\*\ - RCC_TRNGCLK_SYSBUSDIV16 +*\*\ - RCC_TRNGCLK_SYSBUSDIV32 +*\*\ - RCC_TRNGCLK_SYSBUSDIV64 +*\*\ - RCC_TRNGCLK_SYSBUSDIV128 +*\*\ - RCC_TRNGCLK_SYSBUSDIV256 +*\*\ - RCC_TRNGCLK_SYSBUSDIV512 +*\*\return none +*\*\note if select RCC_TRNGCLK_SRC_SYSBUSDIV then set the (sys_bus_div_clk) divider by TRNGDIV[3:0] +**/ +void RCC_ConfigTRNGClk(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t reg_value; + uint32_t reg_value1; + + reg_value = RCC->CFG5; + /* Clear TRNGSEL bits */ + reg_value &= RCC_TRNGCLK_SRC_MASK; + /* Set TRNGSEL bits according to CLK_source value */ + reg_value |= CLK_source; + /* Store the new value */ + RCC->CFG5 = reg_value; + + if(CLK_source == RCC_TRNGCLK_SRC_SYSBUSDIV) + { + reg_value1 = RCC->CFG5; + /* Clear TRNGDIV[3:0] bits */ + reg_value1 &= RCC_TRNGCLK_SYSBUSDIV_MASK; + /* Set the TRNGDIV[3:0] bits */ + reg_value1 |= CLK_divider; + /* Store the new value */ + RCC->CFG5 = reg_value1; + } + +} + +/** +*\*\name RCC_EnableTRNGClk. +*\*\fun Enables the TRNG clock. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableTRNGClk(FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + RCC->CFG5 |= RCC_TRNG_ENABLE; + } + else + { + RCC->CFG5 &= (~RCC_TRNG_ENABLE); + } +} + +/** +*\*\name RCC_EnableCFG2PeriphClk1. +*\*\fun Enables the CFG2 register peripheral clock. +*\*\param CFG2_periph (CFG2 peripheral to gates its clock): +*\*\ - RCC_CFG2_PERIPHEN_M4_CAHI +*\*\ - RCC_CFG2_PERIPHEN_M4_CAHIPCLK +*\*\ - RCC_CFG2_PERIPHEN_M4_CAHD +*\*\ - RCC_CFG2_PERIPHEN_M4_CAHDPCLK +*\*\ - RCC_CFG2_PERIPHEN_M7_MMU +*\*\ - RCC_CFG2_PERIPHEN_M7_MMULP +*\*\ - RCC_CFG2_PERIPHEN_M4_MMU +*\*\ - RCC_CFG2_PERIPHEN_M4_MMULP +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAMBKP +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAMBKP +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAMBKPLP +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAMBKPLP +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM1 +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM1 +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM1LP +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM1LP +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM2 +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM2 +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM2LP +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM2LP +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM3 +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM3 +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM3LP +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM3LP +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM4 +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM4 +*\*\ - RCC_CFG2_PERIPHEN_M7_SRAM4LP +*\*\ - RCC_CFG2_PERIPHEN_M4_SRAM4LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableCFG2PeriphClk1(uint32_t CFG2_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CFG2 |= CFG2_periph; + } + else + { + RCC->CFG2 &= ~CFG2_periph; + } +} + + +/** +*\*\name RCC_EnableCFG4PeriphClk1. +*\*\fun Enables the CFG4 register peripheral clock. +*\*\param CFG4_periph (CFG4 peripheral to gates its clock): +*\*\ - RCC_CFG4_PERIPHEN_AHB1BUS +*\*\ - RCC_CFG4_PERIPHEN_AHB2BUS +*\*\ - RCC_CFG4_PERIPHEN_AHB5BUS +*\*\ - RCC_CFG4_PERIPHEN_AHB6BUS +*\*\ - RCC_CFG4_PERIPHEN_AXIBUS +*\*\ - RCC_CFG4_PERIPHEN_APB1BUS +*\*\ - RCC_CFG4_PERIPHEN_APB2BUS +*\*\ - RCC_CFG4_PERIPHEN_APB5BUS +*\*\ - RCC_CFG4_PERIPHEN_APB6BUS +*\*\ - RCC_CFG4_PERIPHEN_AHB9BUS +*\*\ - RCC_CFG4_PERIPHEN_M7AXIMATRIX_GPV +*\*\ - RCC_CFG4_PERIPHEN_M4AXIMATRIX_GPV +*\*\ - RCC_CFG4_PERIPHEN_HSICG +*\*\ - RCC_CFG4_PERIPHEN_HSIKERCG +*\*\ - RCC_CFG4_PERIPHEN_HSECG +*\*\ - RCC_CFG4_PERIPHEN_HSEKERCG +*\*\ - RCC_CFG4_PERIPHEN_MSICG +*\*\ - RCC_CFG4_PERIPHEN_MSIKERCG +*\*\ - RCC_CFG4_PERIPHEN_M7AXIMATRIX +*\*\ - RCC_CFG4_PERIPHEN_AXIGGPV +*\*\ - RCC_CFG4_PERIPHEN_M4AXIMATRIX +*\*\ - RCC_CFG4_PERIPHEN_M7DCMUCLK +*\*\ - RCC_CFG4_PERIPHEN_M4DCMUCLK +*\*\ - RCC_CFG4_PERIPHEN_AHBMATRIX1 +*\*\ - RCC_CFG4_PERIPHEN_AHBMATRIX2 +*\*\ - RCC_CFG4_PERIPHEN_AHBMATRIX3 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableCFG4PeriphClk1(uint32_t CFG4_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CFG4 |= CFG4_periph; + } + else + { + RCC->CFG4 &= ~CFG4_periph; + } +} + +/** +*\*\name RCC_EnableCFG5PeriphClk1. +*\*\fun Enables the CFG5 register peripheral clock. +*\*\param CFG5_periph (CFG5 peripheral to gates its clock): +*\*\ - RCC_CFG5_PERIPHEN_M7_SRAM5 +*\*\ - RCC_CFG5_PERIPHEN_M4_SRAM5 +*\*\ - RCC_CFG5_PERIPHEN_M7_SRAM5LP +*\*\ - RCC_CFG5_PERIPHEN_M4_SRAM5LP +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_EnableCFG5PeriphClk1(uint32_t CFG5_periph, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CFG5 |= CFG5_periph; + } + else + { + RCC->CFG5 &= ~CFG5_periph; + } +} + +/** +*\*\name RCC_ConfigMco1. +*\*\fun Configures the MCO1 clock source and divider. +*\*\param CLK_source: +*\*\ - RCC_MCO1_SRC_LSI +*\*\ - RCC_MCO1_SRC_HSI +*\*\ - RCC_MCO1_SRC_MSI +*\*\ - RCC_MCO1_SRC_LSE +*\*\ - RCC_MCO1_SRC_HSE +*\*\ - RCC_MCO1_SRC_PLL3B +*\*\param CLK_divider: +*\*\ - RCC_MCO1_DIV1 +*\*\ - RCC_MCO1_DIV2 +*\*\ - RCC_MCO1_DIV4 +*\*\ - RCC_MCO1_DIV8 +*\*\ - RCC_MCO1_DIV16 +*\*\ - RCC_MCO1_DIV32 +*\*\ - RCC_MCO1_DIV64 +*\*\ - RCC_MCO1_DIV128 +*\*\return none +*\*\return none +**/ +void RCC_ConfigMco1(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t temp_value; + + temp_value = RCC->CFG3; + /* Clear MCO1SEL[3:0] and MCO1DIV[3:0] bits */ + temp_value &= RCC_MCO1_SRC_MASK; + temp_value &= RCC_MCO1_DIV_MASK; + /* Set MCO1SEL[3:0] bits according to CLK_source value */ + temp_value |= CLK_source; + /* Set MCO1DIV[3:0] bits according to CLK_divider value */ + temp_value |= CLK_divider; + + /* Store the new value */ + RCC->CFG3 = temp_value; +} + +/** +*\*\name RCC_ConfigMco2. +*\*\fun Configures the MCO2 clock source and divider. +*\*\param CLK_source: +*\*\ - RCC_MCO2_SRC_SYSCLK +*\*\ - RCC_MCO2_SRC_PLL1A +*\*\ - RCC_MCO2_SRC_PLL2A +*\*\ - RCC_MCO2_SRC_PLL3A +*\*\ - RCC_MCO2_SRC_SHRPLL +*\*\ - RCC_MCO2_SRC_LSE +*\*\param CLK_divider: +*\*\ - RCC_MCO2_DIV1 +*\*\ - RCC_MCO2_DIV2 +*\*\ - RCC_MCO2_DIV4 +*\*\ - RCC_MCO2_DIV8 +*\*\ - RCC_MCO2_DIV16 +*\*\ - RCC_MCO2_DIV32 +*\*\ - RCC_MCO2_DIV64 +*\*\ - RCC_MCO2_DIV128 +*\*\return none +**/ +void RCC_ConfigMco2(uint32_t CLK_source, uint32_t CLK_divider) +{ + uint32_t temp_value; + + temp_value = RCC->CFG3; + /* Clear MCO2SEL[3:0] and MCO2DIV[3:0] bits */ + temp_value &= RCC_MCO2_SRC_MASK; + temp_value &= RCC_MCO2_DIV_MASK; + /* Set MCO2SEL[3:0] bits according to CLK_source value */ + temp_value |= CLK_source; + /* Set MCO2DIV[3:0] bits according to CLK_divider value */ + temp_value |= CLK_divider; + + /* Store the new value */ + RCC->CFG3 = temp_value; +} + +/** +*\*\name RCC_EnableFDCANStopRequest1. +*\*\fun Sending a stop request to the FDCAN module when enabled. +*\*\param FDCAN_sel(select FDCANx) : +*\*\ -RCC_STOPEN_FDCAN1 +*\*\ -RCC_STOPEN_FDCAN2 +*\*\ -RCC_STOPEN_FDCAN5 +*\*\ -RCC_STOPEN_FDCAN6 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note Hardware clears this bit after receiving a shutdown answer from the CAN module +**/ +void RCC_EnableFDCANStopRequest1(uint32_t FDCAN_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB1EN5 |= FDCAN_sel; + } + else + { + RCC->APB1EN5 &= ~FDCAN_sel; + } + +} + +/** +*\*\name RCC_GetFDCANStopAckFlag1 +*\*\fun Checks whether the specified FDCAN Stop Ack flag is set or not. +*\*\param RCC_flag (The input parameters must be the following values): +*\*\ -RCC_FLAG_STOPACK_FDCAN1 +*\*\ -RCC_FLAG_STOPACK_FDCAN2 +*\*\ -RCC_FLAG_STOPACK_FDCAN5 +*\*\ -RCC_FLAG_STOPACK_FDCAN6 +*\*\return FlagStatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus RCC_GetFDCANStopAckFlag1(uint32_t RCC_flag) +{ + FlagStatus bitstatus; + + if ((RCC->APB1EN5 & RCC_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableFDCANStopRequest2. +*\*\fun Sending a stop request to the FDCAN module when enabled. +*\*\param FDCAN_sel(select FDCANx) : +*\*\ -RCC_STOPEN_FDCAN3 +*\*\ -RCC_STOPEN_FDCAN4 +*\*\ -RCC_STOPEN_FDCAN7 +*\*\ -RCC_STOPEN_FDCAN8 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note Hardware clears this bit after receiving a shutdown answer from the CAN module +**/ +void RCC_EnableFDCANStopRequest2(uint32_t FDCAN_sel, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->APB2EN4 |= FDCAN_sel; + } + else + { + RCC->APB2EN4 &= ~FDCAN_sel; + } + +} + +/** +*\*\name RCC_GetFDCANStopAckFlag2 +*\*\fun Checks whether the specified FDCAN Stop Ack flag is set or not. +*\*\param RCC_flag (The input parameters must be the following values): +*\*\ -RCC_FLAG_STOPACK_FDCAN3 +*\*\ -RCC_FLAG_STOPACK_FDCAN4 +*\*\ -RCC_FLAG_STOPACK_FDCAN7 +*\*\ -RCC_FLAG_STOPACK_FDCAN8 +*\*\return FlagStatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus RCC_GetFDCANStopAckFlag2(uint32_t RCC_flag) +{ + FlagStatus bitstatus; + + if ((RCC->APB2EN4 & RCC_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name RCC_ConfigPeriphClk. +*\*\fun Configures the Periph clock source. +*\*\param CLK_source(Periph clock source): +*\*\ - RCC_PERIPHCLK_SRC_HSI +*\*\ - RCC_PERIPHCLK_SRC_MSI +*\*\ - RCC_PERIPHCLK_SRC_HSE +*\*\return none +*\*\note If the module clock source is selected as periph, then needs to config PERSW[1:0] +**/ +void RCC_ConfigPeriphClk(uint32_t CLK_source) +{ + uint32_t temp_value; + + temp_value = RCC->CFG3; + + /* Clear PERSW[1:0] bits */ + temp_value &= RCC_PERIPHCLK_SRC_MASK; + /* Set PERSW[1:0] bits according to CLK_source value*/ + temp_value |= CLK_source; + + /* Store the new value */ + RCC->CFG3 = temp_value; + +} + +/** +*\*\name RCC_EnableModuleResetRequest. +*\*\fun Configure whether to generate a reset request when the corresponding module event occurs. +*\*\param Module_sel(select module) : +*\*\ -RCC_RSTEN_WWDG1 +*\*\ -RCC_RSTEN_WWDG2 +*\*\ -RCC_RSTEN_BOR +*\*\ -RCC_RSTEN_C1LP +*\*\ -RCC_RSTEN_C2LP +*\*\ -RCC_RSTEN_BKPEMC +*\*\ -RCC_RSTEN_RETEMC +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableModuleResetRequest(uint32_t Module_sel, FunctionalState Cmd) +{ + if(Module_sel <= RCC_RSTEN_WWDG2) + { + if (Cmd != DISABLE) + { + RCC->CFG1 |= Module_sel; + } + else + { + RCC->CFG1 &= ~Module_sel; + } + } + else + { + if (Cmd != DISABLE) + { + RCC->BDCTRL |= Module_sel; + } + else + { + RCC->BDCTRL &= ~Module_sel; + } + } + + +} + +/** +*\*\name RCC_ConfigInt1. +*\*\fun Enables the specified RCC interrupts. +*\*\param Interrupt(the RCC interrupt sources to be enabled): +*\*\ - RCC_INT_LSECSS +*\*\ - RCC_INT_BOR +*\*\ - RCC_INT_PLL1RD +*\*\ - RCC_INT_PLL2RD +*\*\ - RCC_INT_PLL3RD +*\*\ - RCC_INT_SHRPLLRD +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_ConfigInt1(uint32_t Interrupt, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CLKINT1 |= (((uint32_t)Interrupt) << 1); + } + else + { + RCC->CLKINT1 &= (~(((uint32_t)Interrupt) << 1)); + } + +} + +/** +*\*\name RCC_ConfigInt2. +*\*\fun Enables the specified RCC interrupts. +*\*\param Interrupt(the RCC interrupt sources to be enabled): +*\*\ - RCC_INT_HSERD +*\*\ - RCC_INT_HSIRD +*\*\ - RCC_INT_MSIRD +*\*\ - RCC_INT_LSERD +*\*\ - RCC_INT_LSIRD +*\*\ - RCC_INT_HSICALE +*\*\ - RCC_INT_MSICALE +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_ConfigInt2(uint32_t Interrupt, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CLKINT2 |= (((uint32_t)Interrupt) << 1); + } + else + { + RCC->CLKINT2 &= (~(((uint32_t)Interrupt) << 1)); + } + +} + +/** +*\*\name RCC_ConfigInt3. +*\*\fun Enables the specified RCC interrupts. +*\*\param Interrupt(the RCC interrupt sources to be enabled): +*\*\ - RCC_INT_PLL1LKF +*\*\ - RCC_INT_PLL2LKF +*\*\ - RCC_INT_PLL3LKF +*\*\ - RCC_INT_SHRPLLLKF +*\*\ - RCC_INT_LSIF +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RCC_ConfigInt3(uint32_t Interrupt, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CLKINT3 |= (((uint32_t)Interrupt) << 1); + } + else + { + RCC->CLKINT3 &= (~(((uint32_t)Interrupt) << 1)); + } + +} + +/** +*\*\name RCC_GetIntStatus1. +*\*\fun Checks whether the specified RCC interrupt has occurred or not. +*\*\param interrupt_flag(RCC interrupt source to check): +*\*\ - RCC_INT_LSECSS +*\*\ - RCC_INT_HSECSS +*\*\ - RCC_INT_BOR +*\*\ - RCC_INT_PLL1RD +*\*\ - RCC_INT_PLL2RD +*\*\ - RCC_INT_PLL3RD +*\*\ - RCC_INT_SHRPLLRD +*\*\return The new state of interrupt_flag +*\*\ - SET +*\*\ - RESET +**/ +INTStatus RCC_GetIntStatus1(uint32_t interrupt_flag) +{ + INTStatus bitstatus; + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT1 & interrupt_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RCC_GetIntStatus2. +*\*\fun Checks whether the specified RCC interrupt has occurred or not. +*\*\param interrupt_flag(RCC interrupt source to check): +*\*\ - RCC_INT_HSERD +*\*\ - RCC_INT_HSIRD +*\*\ - RCC_INT_MSIRD +*\*\ - RCC_INT_LSERD +*\*\ - RCC_INT_LSIRD +*\*\ - RCC_INT_HSICALE +*\*\ - RCC_INT_MSICALE +*\*\return The new state of interrupt_flag +*\*\ - SET +*\*\ - RESET +**/ +INTStatus RCC_GetIntStatus2(uint32_t interrupt_flag) +{ + INTStatus bitstatus; + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT2 & interrupt_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RCC_GetIntStatus3. +*\*\fun Checks whether the specified RCC interrupt has occurred or not. +*\*\param interrupt_flag(RCC interrupt source to check): +*\*\ - RCC_INT_PLL1LKF +*\*\ - RCC_INT_PLL2LKF +*\*\ - RCC_INT_PLL3LKF +*\*\ - RCC_INT_SHRPLLLKF +*\*\ - RCC_INT_LSIF +*\*\return The new state of interrupt_flag +*\*\ - SET +*\*\ - RESET +**/ +INTStatus RCC_GetIntStatus3(uint32_t interrupt_flag) +{ + INTStatus bitstatus; + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CLKINT3 & interrupt_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name RCC_ClrIntPendingBit1. +*\*\fun Clears the RCC's interrupt pending bits. +*\*\param interrupt_clear(interrupt pending bit to clear): +*\*\ - RCC_INT_LSECSS +*\*\ - RCC_INT_HSECSS +*\*\ - RCC_INT_BOR +*\*\ - RCC_INT_PLL1RD +*\*\ - RCC_INT_PLL2RD +*\*\ - RCC_INT_PLL3RD +*\*\ - RCC_INT_SHRPLLRD +*\*\return none +**/ +void RCC_ClrIntPendingBit1(uint32_t interrupt_clear) +{ + /* Software set this bit to clear INT flag. */ + RCC->CLKINT1 |= (((uint32_t)interrupt_clear) >> 1);; +} + +/** +*\*\name RCC_ClrIntPendingBit2. +*\*\fun Clears the RCC's interrupt pending bits. +*\*\param interrupt_clear(interrupt pending bit to clear): +*\*\ - RCC_INT_HSERD +*\*\ - RCC_INT_HSIRD +*\*\ - RCC_INT_MSIRD +*\*\ - RCC_INT_LSERD +*\*\ - RCC_INT_LSIRD +*\*\ - RCC_INT_HSICALE +*\*\ - RCC_INT_MSICALE +*\*\return none +**/ +void RCC_ClrIntPendingBit2(uint32_t interrupt_clear) +{ + /* Software set this bit to clear INT flag. */ + RCC->CLKINT2 |= (((uint32_t)interrupt_clear) >> 1);; +} + +/** +*\*\name RCC_ClrIntPendingBit3. +*\*\fun Clears the RCC's interrupt pending bits. +*\*\param interrupt_clear(interrupt pending bit to clear): +*\*\ - RCC_INT_PLL1LKF +*\*\ - RCC_INT_PLL2LKF +*\*\ - RCC_INT_PLL3LKF +*\*\ - RCC_INT_SHRPLLLKF +*\*\ - RCC_INT_LSIF +*\*\return none +**/ +void RCC_ClrIntPendingBit3(uint32_t interrupt_clear) +{ + /* Software set this bit to clear INT flag. */ + RCC->CLKINT3 |= (((uint32_t)interrupt_clear) >> 1);; +} + +/** +*\*\name RCC_GetFlagStatus. +*\*\fun Checks whether the specified RCC flag is set or not. +*\*\param RCC_flag: +*\*\ - RCC_FLAG_HSIRD HSI clock ready +*\*\ - RCC_FLAG_HSERD HSE clock ready +*\*\ - RCC_FLAG_MSIRD MSI clock ready +*\*\ - RCC_FLAG_AFEHSIRD AFE HSI clock ready +*\*\ - RCC_FLAG_AFEMSIRD AFE MSI clock ready +*\*\ - RCC_FLAG_MSICALE MSI calibration error status flag +*\*\ - RCC_FLAG_HSICALE HSI calibration error status flag +*\*\ - RCC_FLAG_BOR BOR status flag +*\*\ - RCC_FLAG_LSIRD LSI clock ready +*\*\ - RCC_FLAG_LSERD LSE clock ready +*\*\ - RCC_FLAG_LSECSS LSE Clock Safety System flag +*\*\ - RCC_FLAG_LSISECRD Secondary LSI clock ready +*\*\ - RCC_FLAG_RTCHSFSW RTC HSE source fail status +*\*\ - RCC_FLAG_RTCLSFSW RTC LSE source fail status +*\*\ - RCC_FLAG_LSIPF LSI primary failure status +*\*\ - RCC_FLAG_AFELSIRD AFE LSI clock ready +*\*\ - RCC_FLAG_AFELSERD AFE LSE clock ready +*\*\ - RCC_FLAG_PINRST PIN reset flag +*\*\ - RCC_FLAG_PORRST POR/PDR reset flag +*\*\ - RCC_FLAG_CM7SFTRST M7 Software reset flag +*\*\ - RCC_FLAG_CM4SFTRST M4 Software reset flag +*\*\ - RCC_FLAG_IWDG2RST IWDG2 reset flag +*\*\ - RCC_FLAG_IWDG1RST IWDG1 reset flag +*\*\ - RCC_FLAG_WWDG2RST WWDG2 reset flag +*\*\ - RCC_FLAG_WWDG1RST WWDG1 reset flag +*\*\ - RCC_FLAG_MMURST MMU reset flag +*\*\ - RCC_FLAG_BORRST BOR reset flag +*\*\ - RCC_FLAG_BKPEMCRST Backup EMC reset flag +*\*\ - RCC_FLAG_RETEMCRST VDDDRET EMC reset flag +*\*\ - RCC_FLAG_C2LPRST C2 Low-power reset flag +*\*\ - RCC_FLAG_C1LPRST C1 Low-power reset flag +*\*\ - RCC_FLAG_SHRPLLG SHRPLL clock gate flag +*\*\ - RCC_FLAG_PLL3G PLL3 clock gate flag +*\*\ - RCC_FLAG_PLL2G PLL2 clock gate flag +*\*\ - RCC_FLAG_PLL1G PLL1 clock gate flag +*\*\ - RCC_FLAG_SHRPLLF SHRPLL fail state flag +*\*\ - RCC_FLAG_PLL3F PLL3 fail state flag +*\*\ - RCC_FLAG_PLL2F PLL2 fail state flag +*\*\ - RCC_FLAG_PLL1F PLL1 fail state flag +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_flag) +{ + uint32_t temp_value; + uint32_t reg_value; + FlagStatus bitstatus; + + /* Get the RCC register index */ + temp_value = (uint32_t)RCC_flag >> RCC_FLAG_OFFSET; + + switch(temp_value) + { + case 1: /* The flag to check is in SRCCTRL1 register */ + reg_value = RCC->SRCCTRL1; + break; + + case 2: /* The flag to check is in SRCCTRL2 register */ + reg_value = RCC->SRCCTRL2; + break; + + case 3:/* The flag to check is in BDCTRL register */ + reg_value = RCC->BDCTRL; + break; + + case 4:/* The flag to check is in CTRLSTS register */ + reg_value = RCC->CTRLSTS; + break; + + default:/* The flag to check is in PLLFD register */ + reg_value = RCC->PLLFD; + break; + } + + /* Get the flag position */ + temp_value = (uint32_t)RCC_flag & RCC_FLAG_MASK; + + if ((reg_value & ((uint32_t)1 << temp_value)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RCC_ClearResetFlag. +*\*\fun Clears the RCC reset flags. +*\*\param none +*\*\return none +*\*\note Clear the following flags: +*\*\ - RCC_FLAG_PINRST PIN reset flag +*\*\ - RCC_FLAG_PORRST POR/PDR reset flag +*\*\ - RCC_FLAG_CM7SFTRST M7 Software reset flag +*\*\ - RCC_FLAG_CM4SFTRST M4 Software reset flag +*\*\ - RCC_FLAG_IWDG2RST IWDG2 reset flag +*\*\ - RCC_FLAG_IWDG1RST IWDG1 reset flag +*\*\ - RCC_FLAG_WWDG2RST WWDG2 reset flag +*\*\ - RCC_FLAG_WWDG1RST WWDG1 reset flag +*\*\ - RCC_FLAG_MMURST MMU reset flag +*\*\ - RCC_FLAG_BORRST BOR reset flag +*\*\ - RCC_FLAG_BKPEMCRST Backup EMC reset flag +*\*\ - RCC_FLAG_RETEMCRST VDDDRET EMC reset flag +*\*\ - RCC_FLAG_C2LPRST C2 Low-power reset flag +*\*\ - RCC_FLAG_C1LPRST C1 Low-power reset flag +**/ +void RCC_ClearResetFlag(void) +{ + /* Set RMRSTF bit to clear the reset flags */ + RCC->CTRLSTS |= RCC_REMOVE_RESET_FLAG; + /* RMRSTF bit should be reset */ + RCC->CTRLSTS &= ~RCC_REMOVE_RESET_FLAG; +} + +/** + *\*\name RCC_EnableCM4. + *\*\fun Enable CM4 core reset and startup. + *\*\param CM4_BaseAddr: the Vector Table location add offset address of CM4 core; + *\*\return none + */ +void RCC_EnableCM4(uint32_t CM4_BaseAddr) +{ + /*Config CM4 vector address in MMU register*/ + *(uint32_t*)0x511050ac = CM4_BaseAddr; + /*Enable CM7 reset CM4 Reset bit*/ + RCC->M4RSTREL |= RCC_RSTEN_M4REL ; +} + +/** +*\*\name RCC_GetClocksFreq. +*\*\fun Returns the frequencies of different on chip clocks. +*\*\param RCC_Clocks: +*\*\ pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. +*\*\return none +*\*\note The result of this function could be not correct when using +*\*\ fractional value for HSE crystal. +**/ +void RCC_GetClocksFreqValue(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t hsi_value, msi_value; + uint32_t pll_value, temp_value, temp_value1, sysdiv_value, hyper_value; + const uint8_t SysPresTable[16] = {0, 1, 2, 2, 3, 3, 3, 4, 5, 6, 7, 8, 9, 9, 9, 9}; + const uint8_t ApbPresTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + + + temp_value = RCC->PLL1CTRL1 & RCC_PLL1CTRL1_PLL1SRC; + + if(temp_value == RCC_PLL_SRC_HSE) + { + pll_value = HSE_VALUE; + } + else if(temp_value == RCC_PLL_SRC_MSI) + { + pll_value = MSI_VALUE; + } + else + { + pll_value = HSI_VALUE; + } + + temp_value = (((RCC->PLL1CTRL2 & RCC_PLL1CTRL2_PLL1CLKR) >> 26) + 1); + temp_value1 = (RCC->PLL1CTRL2 & RCC_PLL1CTRL2_PLL1CLKF); + pll_value = (uint32_t)((((uint64_t)pll_value * (uint64_t)temp_value1) >> 14) / temp_value); + + temp_value = (RCC->PLL1DIV & RCC_PLL1DIV_PLL1ADIV); + + if(temp_value > 0) + { + RCC_Clocks->PLL1AClkFreq = pll_value / temp_value; + } + + temp_value = ((RCC->PLL1DIV & RCC_PLL1DIV_PLL1BDIV) >> 8); + + if(temp_value > 0) + { + RCC_Clocks->PLL1BClkFreq = pll_value / temp_value; + } + + temp_value = ((RCC->PLL1DIV & RCC_PLL1DIV_PLL1CDIV) >> 16); + + if(temp_value > 0) + { + RCC_Clocks->PLL1CClkFreq = pll_value / temp_value; + } + + temp_value = RCC->PLL2CTRL1 & RCC_PLL2CTRL1_PLL2SRC; + + if(temp_value == RCC_PLL_SRC_HSE) + { + pll_value = HSE_VALUE; + } + else if(temp_value == RCC_PLL_SRC_MSI) + { + pll_value = MSI_VALUE; + } + else + { + pll_value = HSI_VALUE; + } + + temp_value = (((RCC->PLL2CTRL2 & RCC_PLL2CTRL2_PLL2CLKR) >> 26) + 1); + temp_value1 = (RCC->PLL2CTRL2 & RCC_PLL2CTRL2_PLL2CLKF); + pll_value = (uint32_t)((((uint64_t)pll_value * (uint64_t)temp_value1) >> 14) / temp_value); + + temp_value = (RCC->PLL2DIV & RCC_PLL2DIV_PLL2ADIV); + + if( temp_value > 0) + { + RCC_Clocks->PLL2AClkFreq = pll_value / temp_value; + } + + temp_value = ((RCC->PLL2DIV & RCC_PLL2DIV_PLL2BDIV) >> 8); + + if(temp_value > 0) + { + RCC_Clocks->PLL2BClkFreq = pll_value / temp_value; + } + + temp_value = ((RCC->PLL2DIV & RCC_PLL2DIV_PLL2CDIV) >> 16); + + if(temp_value > 0) + { + RCC_Clocks->PLL2CClkFreq = pll_value / temp_value; + } + + temp_value = RCC->PLL3CTRL1 & RCC_PLL3CTRL1_PLL3SRC; + + if(temp_value == RCC_PLL_SRC_HSE) + { + pll_value = HSE_VALUE; + } + else if(temp_value == RCC_PLL_SRC_MSI) + { + pll_value = MSI_VALUE; + } + else + { + pll_value = HSI_VALUE; + } + + temp_value = (((RCC->PLL3CTRL2 & RCC_PLL3CTRL2_PLL3CLKR) >> 26) + 1); + temp_value1 = (RCC->PLL3CTRL2 & RCC_PLL3CTRL2_PLL3CLKF); + pll_value = (uint32_t)((((uint64_t)pll_value * (uint64_t)temp_value1) >> 14) / temp_value); + + temp_value = (RCC->PLL3DIV & RCC_PLL3DIV_PLL3ADIV); + + if(temp_value > 0) + { + RCC_Clocks->PLL3AClkFreq = pll_value / temp_value; + } + + temp_value = ((RCC->PLL3DIV & RCC_PLL3DIV_PLL3BDIV) >> 8); + + if(temp_value > 0) + { + RCC_Clocks->PLL3BClkFreq = pll_value / temp_value; + } + + temp_value = ((RCC->PLL3DIV & RCC_PLL3DIV_PLL3CDIV) >> 16); + + if(temp_value > 0) + { + RCC_Clocks->PLL3CClkFreq = pll_value / temp_value; + } + + hsi_value = HSI_VALUE >> (SysPresTable[(RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_HSIDIV) >> 20]); + msi_value = MSI_VALUE >> (SysPresTable[(RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_MSIDIV) >> 4]); + + temp_value = RCC->SRCCTRL1 & RCC_SRCCTRL1_SCLKSTS; + + if(temp_value == RCC_SYSCLK_STS_HSE) + { + RCC_Clocks->SysClkFreq = HSE_VALUE; + } + else if(temp_value == RCC_SYSCLK_STS_MSI) + { + RCC_Clocks->SysClkFreq = msi_value; + } + else if(temp_value == RCC_SYSCLK_STS_PLL1A) + { + RCC_Clocks->SysClkFreq = RCC_Clocks->PLL1AClkFreq; + } + else + { + RCC_Clocks->SysClkFreq = hsi_value; + } + + sysdiv_value = RCC_Clocks->SysClkFreq >> (SysPresTable[RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_SCLKDIV]); + hyper_value = RCC_Clocks->PLL2AClkFreq >> (SysPresTable[(RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_M7HYPDIV) >> 16]); + + RCC_Clocks->SysBusDivClkFreq = sysdiv_value >> (SysPresTable[(RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_BUSDIV) >> 8]); + RCC_Clocks->M4ClkFreq = RCC_Clocks->SysBusDivClkFreq; + + if((RCC->SRCCTRL2 & RCC_SRCCTRL2_M7HYPSEL) == RCC_M7HYPERCLK_SRC_PLL2A) + { + RCC_Clocks->M7ClkFreq = hyper_value; + } + else + { + RCC_Clocks->M7ClkFreq = sysdiv_value; + } + + if((RCC->SRCCTRL2 & RCC_SRCCTRL2_AXIHYPSEL) == RCC_AXIHYPERCLK_SRC_PLL2A) + { + RCC_Clocks->AXIClkFreq = hyper_value >> (SysPresTable[(RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_AXIHYPDIV) >> 24]); + } + else + { + RCC_Clocks->AXIClkFreq = sysdiv_value >> (SysPresTable[(RCC->SYSBUSDIV1 & RCC_SYSBUSDIV1_AXIDIV) >> 12]); + } + + RCC_Clocks->AHB1ClkFreq = RCC_Clocks->SysBusDivClkFreq; + RCC_Clocks->AHB2ClkFreq = RCC_Clocks->SysBusDivClkFreq; + RCC_Clocks->AHB5ClkFreq = RCC_Clocks->SysBusDivClkFreq; + RCC_Clocks->AHB6ClkFreq = RCC_Clocks->AXIClkFreq; + RCC_Clocks->AHB9ClkFreq = RCC_Clocks->SysBusDivClkFreq; + + RCC_Clocks->APB1ClkFreq = RCC_Clocks->AHB1ClkFreq >> (ApbPresTable[RCC->SYSBUSDIV2 & RCC_SYSBUSDIV2_APB1DIV]); + RCC_Clocks->APB2ClkFreq = RCC_Clocks->AHB2ClkFreq >> (ApbPresTable[(RCC->SYSBUSDIV2 & RCC_SYSBUSDIV2_APB2DIV) >> 8]); + RCC_Clocks->APB5ClkFreq = RCC_Clocks->AHB5ClkFreq >> (ApbPresTable[(RCC->SYSBUSDIV2 & RCC_SYSBUSDIV2_APB5DIV) >> 16]); + RCC_Clocks->APB6ClkFreq = RCC_Clocks->AHB6ClkFreq >> (ApbPresTable[(RCC->SYSBUSDIV2 & RCC_SYSBUSDIV2_APB6DIV) >> 24]); + + temp_value = RCC->CFG3 & RCC_CFG3_PERSW; + + if(temp_value == RCC_PERIPHCLK_SRC_HSE) + { + RCC_Clocks->PeriphClkFreq = HSE_VALUE; + } + else if(temp_value == RCC_PERIPHCLK_SRC_MSI) + { + RCC_Clocks->PeriphClkFreq = msi_value; + } + else + { + RCC_Clocks->PeriphClkFreq = hsi_value; + } + +} + +/** +*\*\name RCC_SetSysClkToMode0. +*\*\fun Configure the M7 clock is 600MHz, +*\*\ M4, AXI, AHB(1,2,5,6,9) clock is 300MHz, +*\*\ APB(1,2,5,6) clock is 150MHz. +*\*\param none +*\*\return none +*\*\note M7 from PLL1A, AXI from PLL1A, M4 from PLL1A. +**/ +void RCC_SetSysClkToMode0(void) +{ + uint32_t temp_value1, temp_value2; + + /* Configure sys_div_clk is sys_clk(PLL1A) = 600M = M7 clock*/ + RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); + /* Configure sys_bus_div_clk is sys_div_clk/2 = 300M = M4 clock = AHB1\2\5\9*/ + RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); + /* Configure AXI clock is sys_div_clk/2 = 300M = AHB6*/ + RCC_ConfigAXIclkDivider(RCC_AXICLK_DIV2); + RCC_ConfigAXIHyperDivider(RCC_AXICLK_HYP_DIV2); + + __RCC_DELAY_US(1); + /* Configure APB1 clock is AHB1/2 = 150M */ + /* Configure APB2 clock is AHB2/2 = 150M */ + /* Configure APB5 clock is AHB5/2 = 150M */ + /* Configure APB6 clock is AHB6/2 = 150M */ + RCC_ConfigAPBclkDivider(RCC_APB1CLK_DIV2, RCC_APB2CLK_DIV2, RCC_APB5CLK_DIV2, RCC_APB6CLK_DIV2); + + /* configure PLL1 source is HSI, frequency is 600M */ + //RCC_ConfigPll1(RCC_PLL_SRC_HSI,64000000,600000000,ENABLE); + /* get the register value */ + temp_value1 = RCC->PLL1CTRL1; + temp_value2 = RCC->PLL1CTRL2; + + /* Clear BWAJ[11:0] bits */ + temp_value1 &= RCC_PLL_BWAJ_MASK; + /* Clear CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 &= RCC_PLL_CLKR_CLKF_MASK; + + /* Set BWAJ[11:0] bits - 600M */ + temp_value1 |= 0x3U; + /* Set CLKF[25:0] and CLKR[5:0] bits */ + temp_value2 |= 0x25800U; + + /* Store the new value */ + RCC->PLL1CTRL1 = temp_value1; + RCC->PLL1CTRL2 = temp_value2; + + /* Enable PLL module power */ + RCC->PLL1CTRL1 |= RCC_PLL_LDO_ENABLE; + __RCC_DELAY_US(10); + + /* Enable power to analog circuitry in PLL */ + RCC->PLL1CTRL1 &= (~RCC_PLL_POWER_DOWN); + + /* Select Clock Source */ + temp_value1 = RCC->PLL1CTRL1; + temp_value1 &= RCC_PLL_SRC_MASK; + temp_value1 |= RCC_PLL_SRC_HSI; + RCC->PLL1CTRL1 = temp_value1; + __RCC_DELAY_US(10); + + /* Clear PLL reset */ + RCC->PLL1CTRL1 &= (~RCC_PLL_RESET_ENABLE); + + while((RCC->PLL1CTRL1 & RCC_PLL_LOCK_FLAG) != RCC_PLL_LOCK_FLAG) + {} + + /* Enable PLL */ + RCC->PLL1CTRL1 |= RCC_PLL_ENABLE; + /* configure PLL1 source is HSI, frequency is 600M end*/ + + __RCC_DELAY_US(1); + + /* configure PLL1A is 600M */ + RCC_ConfigPLL1ADivider(RCC_PLLA_DIV1);//600M + + /* configure sys_clk source is PLL1A */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL1A); + + /* Check if sys_clk source is PLL1A */ + while(RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A) + {} + +} + +/** +*\*\name RCC_SetSysClkToMode1. +*\*\fun Configure the M7 clock is 600MHz, +*\*\ M4, AXI, AHB(1,2,5,6,9) clock is 300MHz, +*\*\ APB(1,2,5,6) clock is 150MHz. +*\*\param none +*\*\return none +*\*\note M7 from PLL2A, AXI from PLL2A, M4 from PLL1A. +**/ +void RCC_SetSysClkToMode1(void) +{ + /* Configure sys_div_clk is sys_clk(PLL1A) = 600M = M7 clock*/ + RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); + /* Configure sys_bus_div_clk is sys_div_clk/2 = 300M = M4 clock = AHB1\2\5\9*/ + RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); + RCC_ConfigAXIclkDivider(RCC_AXICLK_DIV2); + + /* Configure m7_hyp_div_clk is PLL2A = 600M*/ + RCC_ConfigM7HyperDivider(RCC_M7CLK_HYP_DIV1); + /* Configure AXI clock is m7_hyp_div_clk/2 = 300M = AHB6*/ + RCC_ConfigAXIHyperDivider(RCC_AXICLK_HYP_DIV2); + + __RCC_DELAY_US(1); + /* Configure APB1 clock is AHB1/2 = 150M */ + /* Configure APB2 clock is AHB2/2 = 150M */ + /* Configure APB5 clock is AHB5/2 = 150M */ + /* Configure APB6 clock is AHB6/2 = 150M */ + RCC_ConfigAPBclkDivider(RCC_APB1CLK_DIV2, RCC_APB2CLK_DIV2, RCC_APB5CLK_DIV2, RCC_APB6CLK_DIV2); + + /* configure PLL1 source is HSI, frequency is 600M */ + RCC_ConfigPll1(RCC_PLL_SRC_HSI, 64000000, 600000000, ENABLE); + __RCC_DELAY_US(1); + + /* configure PLL1A is 600M */ + RCC_ConfigPLL1ADivider(RCC_PLLA_DIV1); + + /* configure sys_clk source is PLL1A */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL1A); + + /* Check if sys_clk source is PLL1A */ + while(RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A) + {} + + /* configure PLL2 source is HSI, frequency is 600M */ + RCC_ConfigPll2(RCC_PLL_SRC_HSI, 64000000, 600000000, ENABLE); + __RCC_DELAY_US(1); + + /* configure PLL2A is 600M */ + RCC_ConfigPLL2ADivider(RCC_PLLA_DIV1); + /* configure AXI clock source is PLL2A */ + RCC_ConfigAXIClk(RCC_AXIHYPERCLK_SRC_PLL2A); + /* configure M7 clock source is PLL2A */ + RCC_ConfigM7Clk(RCC_M7HYPERCLK_SRC_PLL2A); + +} + +/** +*\*\name RCC_SetSysClkToMode2. +*\*\fun Configure the M7 clock is 600MHz, +*\*\ M4, AXI, AHB(1,2,5,6,9) clock is 300MHz, +*\*\ APB(1,2,5,6) clock is 150MHz. +*\*\param none +*\*\return none +*\*\note M7 from PLL2A, AXI from PLL1A, M4 from PLL1A. +**/ +void RCC_SetSysClkToMode2(void) +{ + /* Configure sys_div_clk is sys_clk(PLL1A) = 600M = M7 clock*/ + RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); + /* Configure sys_bus_div_clk is sys_div_clk/2 = 300M = M4 clock = AHB1\2\5\9*/ + RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); + /* Configure AXI clock is sys_div_clk/2 = 300M = AHB6*/ + RCC_ConfigAXIclkDivider(RCC_AXICLK_DIV2); + RCC_ConfigAXIHyperDivider(RCC_AXICLK_HYP_DIV2); + /* Configure m7_hyp_div_clk is PLL2A = 600M*/ + RCC_ConfigM7HyperDivider(RCC_M7CLK_HYP_DIV1); + + __RCC_DELAY_US(1); + /* Configure APB1 clock is AHB1/2 = 150M */ + /* Configure APB2 clock is AHB2/2 = 150M */ + /* Configure APB5 clock is AHB5/2 = 150M */ + /* Configure APB6 clock is AHB6/2 = 150M */ + RCC_ConfigAPBclkDivider(RCC_APB1CLK_DIV2, RCC_APB2CLK_DIV2, RCC_APB5CLK_DIV2, RCC_APB6CLK_DIV2); + + /* configure PLL1 source is HSI, frequency is 600M */ + RCC_ConfigPll1(RCC_PLL_SRC_HSI, 64000000, 600000000, ENABLE); + __RCC_DELAY_US(1); + + /* configure PLL1A is 600M */ + RCC_ConfigPLL1ADivider(RCC_PLLA_DIV1); + + /* configure sys_clk source is PLL1A */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL1A); + + /* Check if sys_clk source is PLL1A */ + while(RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A) + {} + + /* configure PLL2 source is HSI, frequency is 600M */ + RCC_ConfigPll2(RCC_PLL_SRC_HSI, 64000000, 600000000, ENABLE); + __RCC_DELAY_US(1); + + /* configure PLL2A is 600M */ + RCC_ConfigPLL2ADivider(RCC_PLLA_DIV1); + /* configure M7 clock source is PLL2A */ + RCC_ConfigM7Clk(RCC_M7HYPERCLK_SRC_PLL2A); + +} + +/** +*\*\name RCC_SetHsiCalibValue. +*\*\fun Adjusts the HSI calibration value. +*\*\param calibration_value(the calibration trimming value): +*\*\ This parameter must be a number between 0 and 0x1FF +*\*\return none +**/ +void RCC_SetHsiCalibValue(uint16_t calibration_value) +{ + uint32_t temp_value; + + temp_value = RCC->SRCCTRL3; + /* Clear HSITRIM[8:0] bits */ + temp_value &= RCC_HSITRIM_MASK; + /* Set the HSITRIM[8:0] bits according to calibration_value value */ + temp_value |= ((uint32_t)calibration_value & 0x1FFU); + /* Store the new value */ + RCC->SRCCTRL3 = temp_value; +} + + +/** +*\*\name RCC_SetMsiCalibValue. +*\*\fun Adjusts the MSI calibration value. +*\*\param calibration_value(the calibration trimming value): +*\*\ This parameter must be a number between 0 and 0x1F +*\*\return none +**/ +void RCC_SetMsiCalibValue(uint16_t calibration_value) +{ + uint32_t temp_value; + + temp_value = RCC->SRCCTRL2; + /* Clear MSITRIM[8:0] bits */ + temp_value &= RCC_MSITRIM_MASK; + /* Set the MSITRIM[8:0] bits according to calibration_value value */ + temp_value |= ((uint32_t)calibration_value & 0x1FU); + /* Store the new value */ + RCC->SRCCTRL2 = temp_value; +} + +/** +*\*\name RCC_EnableHSEClockSecuritySystem. +*\*\fun Enables the HSE Clock Security System. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableHSEClockSecuritySystem(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->SRCCTRL1 |= RCC_HSECSS_ENABLE; + } + else + { + RCC->SRCCTRL1 &= (~RCC_HSECSS_ENABLE); + } +} + +/** +*\*\name RCC_SelectLSISourceControl. +*\*\fun Selection of LSI clock source control. +*\*\param CLK_source: +*\*\ - RCC_LSI_SRCCTRL_BY_HARDWARE +*\*\ - RCC_LSI_SRCCTRL_BY_SOFTWARE +*\*\return none. +*\*\note If RCC_LSI_SRCCTRL_BY_SOFTWARE is selected, the clock source is switched by enabling the LSICSSEN. +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_SelectLSISourceControl(uint32_t CLK_source) +{ + if (CLK_source == RCC_LSI_SRCCTRL_BY_SOFTWARE) + { + RCC->BDCTRL |= CLK_source; + } + else + { + RCC->BDCTRL &= CLK_source; + } +} + +/** +*\*\name RCC_EnableLSIClockSecuritySystem. +*\*\fun Enables the LSI Clock Security System. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableLSIClockSecuritySystem(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->BDCTRL |= RCC_LSICSS_ENABLE; + } + else + { + RCC->BDCTRL &= (~RCC_LSICSS_ENABLE); + } +} + +/** +*\*\name RCC_EnableLSIClockSecuritySystem. +*\*\fun Set by software to acknowledge the failure of LSI. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +*\*\note BDCTRL is protected, you need to enable the PWR clock first, +*\*\ then configure PWR_SYSCTRL1.DBKP to 1 to change it. +**/ +void RCC_EnableLSIFailAcknowledge(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->BDCTRL |= RCC_LSI_FAILACK_ENABLE; + } + else + { + RCC->BDCTRL &= (~RCC_LSI_FAILACK_ENABLE); + } +} + +/** +*\*\name RCC_EnableLSECalibrationCount. +*\*\fun LSE calibration count enable. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLSECalibrationCount(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->LSEOS |= RCC_LSE_CALCNT_ENABLE; + } + else + { + RCC->LSEOS &= (~RCC_LSE_CALCNT_ENABLE); + } +} + +/** +*\*\name RCC_GetLSECalibrationCount +*\*\fun Get number of LSI clock counts in half cycle of LSE/128 clock. +*\*\param none +*\*\return Calibration Count +**/ +uint8_t RCC_GetLSECalibrationCount(void) +{ + return (uint8_t)((RCC->LSEOS & RCC_LSE_CALCNT_MASK) >> 16); +} + +/** +*\*\name RCC_GetLSECSSFlag +*\*\fun Checks whether the specified LSE CSS flag is set or not. +*\*\param RCC_flag (The input parameters must be the following values): +*\*\ -RCC_FLAG_LSECSS_CALCNTRD +*\*\ -RCC_FLAG_LSECSS_OFFSET +*\*\return FlagStatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus RCC_GetLSECSSFlag(uint32_t RCC_flag) +{ + FlagStatus bitstatus; + + if ((RCC->LSEOS & RCC_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableLSEOffsetDetection. +*\*\fun Enable frequency offset detection in LSE clock. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLSEOffsetDetection(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->LSEOS |= RCC_LSE_OFFSET_ENABLE; + } + else + { + RCC->LSEOS &= (~RCC_LSE_OFFSET_ENABLE); + } +} + +/** +*\*\name RCC_SetLSEOffsetThreshold. +*\*\fun Threshold value for detection of frequency offset greater than 10% in LSE clock. +*\*\param threshold_value: +*\*\ This parameter must be a number between 0 and 0xFF +*\*\return none +**/ +void RCC_SetLSEOffsetThreshold(uint8_t threshold_value) +{ + uint32_t temp_value; + + temp_value = RCC->LSEOS; + /* Clear LSEOSTHR[7:0] bits */ + temp_value &= RCC_LSEOSTHR_MASK; + /* Set the LSEOSTHR[7:0] bits according to threshold_value */ + temp_value |= (uint32_t)threshold_value; + /* Store the new value */ + RCC->LSEOS = temp_value; +} + +/** +*\*\name RCC_EnableHSECalibrationCount. +*\*\fun HSE calibration count enable. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableHSECalibrationCount(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->HSECAL |= RCC_HSE_CALCNT_ENABLE; + } + else + { + RCC->HSECAL &= (~RCC_HSE_CALCNT_ENABLE); + } +} + +/** +*\*\name RCC_GetHSECalibrationCount +*\*\fun Get number of HSI clock counts in half cycle of HSE/128 clock. +*\*\param none +*\*\return Calibration Count +**/ +uint16_t RCC_GetHSECalibrationCount(void) +{ + return (uint16_t)(RCC->HSECAL & RCC_HSE_CALCNT_MASK); +} + +/** +*\*\name RCC_GetHSECSSFlag +*\*\fun Checks whether the specified HSE CSS flag is set or not. +*\*\param RCC_flag (The input parameters must be the following values): +*\*\ -RCC_FLAG_HSECSS_CALCNTRD +*\*\ -RCC_FLAG_HSECSS_OFFSET +*\*\ -RCC_FLAG_HSECSS_MAXPD +*\*\ -RCC_FLAG_HSECSS_MINND +*\*\return FlagStatus +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus RCC_GetHSECSSFlag(uint32_t RCC_flag) +{ + FlagStatus bitstatus; + uint32_t reg_value; + + if(RCC_flag == RCC_FLAG_HSECSS_CALCNTRD) + { + reg_value = RCC->HSECAL; + } + else + { + reg_value = RCC->HSEOS; + } + + if ((reg_value & RCC_flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RCC_EnableHSECSSCheck. +*\*\fun Enable different HSE CSS detection type . +*\*\param Chk_type : +*\*\ - RCC_HSECSS_OFFSET enable frequency offset detection +*\*\ - RCC_HSECSS_MAXPD enable detection of positive deviation +*\*\ - RCC_HSECSS_MINND enable detection of negative deviation +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableHSECSSCheck(uint32_t Chk_type, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->HSEOS |= Chk_type; + } + else + { + RCC->HSEOS &= ~Chk_type; + } + +} + +/** +*\*\name RCC_SetHSEOffsetThreshold. +*\*\fun Threshold value for detection of frequency offset greater than 5% in HSE clock. +*\*\param threshold_value: +*\*\ This parameter must be a number between 0 and 0xFF +*\*\return none +**/ +void RCC_SetHSEOffsetThreshold(uint8_t threshold_value) +{ + uint32_t temp_value; + + temp_value = RCC->HSEOS; + /* Clear HSEOSTHR[7:0] bits */ + temp_value &= RCC_HSEOSTHR_MASK; + /* Set the HSEOSTHR[7:0] bits according to threshold_value */ + temp_value |= ((uint32_t)threshold_value << 8); + /* Store the new value */ + RCC->HSEOS = temp_value; +} + +/** +*\*\name RCC_SetHSEPositiveDeviationMAXThreshold. +*\*\fun Threshold value for detection of positive deviation in HSE clock at maximum frequency. +*\*\param threshold_value: +*\*\ This parameter must be a number between 0 and 0xFF +*\*\return none +**/ +void RCC_SetHSEPositiveDeviationMAXThreshold(uint8_t threshold_value) +{ + uint32_t temp_value; + + temp_value = RCC->HSEOS; + /* Clear HSEMAXPDTHR[7:0] bits */ + temp_value &= RCC_HSEMAXPDTHR_MASK; + /* Set the HSEMAXPDTHR[7:0] bits according to threshold_value */ + temp_value |= ((uint32_t)threshold_value << 24); + /* Store the new value */ + RCC->HSEOS = temp_value; +} + +/** +*\*\name RCC_SetHSENegativeDeviationMINThreshold. +*\*\fun Threshold value for detection of negative deviation in HSE clock at minimum frequency. +*\*\param threshold_value: +*\*\ This parameter must be a number between 0 and 0xFF +*\*\return none +**/ +void RCC_SetHSENegativeDeviationMINThreshold(uint8_t threshold_value) +{ + uint32_t temp_value; + + temp_value = RCC->HSEOS; + /* Clear HSEMINNDTHR[7:0] bits */ + temp_value &= RCC_HSEMINNDTHR_MASK; + /* Set the HSEMINNDTHR[7:0] bits according to threshold_value */ + temp_value |= ((uint32_t)threshold_value << 16); + /* Store the new value */ + RCC->HSEOS = temp_value; +} + + +/** +*\*\name RCC_SetLSICSSDelayValue. +*\*\fun This delay represents the estimated time required for the primary +*\*\ LSI clock to be stable during chip power up. +*\*\param delay_value: +*\*\ This parameter must be a number between 0 and 0xFFFFFFFF +*\*\return none +**/ +void RCC_SetLSICSSDelayValue(uint32_t delay_value) +{ + /* Store the new value */ + RCC->LSICSSDL = delay_value; +} + +/** +*\*\name RCC_SetLSEReadyDelayValue. +*\*\fun Config counter delay of LSE clock ready signal. +*\*\param delay_value: +*\*\ This parameter must be a number between 0 and 0xFFFFFFFF +*\*\return none +**/ +void RCC_SetLSEReadyDelayValue(uint32_t delay_value) +{ + /* Store the new value */ + RCC->LSERDDL = delay_value; +} + +/** +*\*\name RCC_SetMSIReadyDelayValue. +*\*\fun Config counter delay of MSI clock ready signal. +*\*\param delay_value: +*\*\ This parameter must be a number between 0 and 0xFFFFFFFF +*\*\return none +**/ +void RCC_SetMSIReadyDelayValue(uint32_t delay_value) +{ + /* Store the new value */ + RCC->MSIRDDL = delay_value; +} + +/** +*\*\name RCC_SetHSEReadyDelayValue. +*\*\fun Config counter delay of HSE clock ready signal. +*\*\param delay_value: +*\*\ This parameter must be a number between 0 and 0xFFFFFFFF +*\*\return none +**/ +void RCC_SetHSEReadyDelayValue(uint32_t delay_value) +{ + /* Store the new value */ + RCC->HSERDDL = delay_value; +} + + +/** +*\*\name RCC_EnablePLLFailDetection. +*\*\fun Enable different pll fail detection. +*\*\param Chk_type : +*\*\ - RCC_FAIL_DETECT_EN_SHRPLL +*\*\ - RCC_FAIL_DETECT_EN_PLL3 +*\*\ - RCC_FAIL_DETECT_EN_PLL2 +*\*\ - RCC_FAIL_DETECT_EN_PLL1 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnablePLLFailDetection(uint32_t Chk_type, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->PLLFD |= Chk_type; + } + else + { + RCC->PLLFD &= ~Chk_type; + } + +} + + +/** +*\*\name RCC_EnableLPTIM1Filter. +*\*\fun Control signal to select filtered or non-filtered LPTIM1 comparator clock source. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLPTIM1Filter(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL1 |= RCC_LPTIM1FILT_ENABLE; + } + else + { + RCC->RDCTRL1 &= (~RCC_LPTIM1FILT_ENABLE); + } +} + +/** +*\*\name RCC_SelectLPTIM1FilterSource. +*\*\fun Control signal to select the sample clock for the digital filter used at LPTIM1. +*\*\param CLK_source: +*\*\ - RCC_LPTIM1_FILTCLK_SRC_APB5 +*\*\ - RCC_LPTIM1_FILTCLK_SRC_MSI +*\*\return none. +**/ +void RCC_SelectLPTIM1FilterSource(uint32_t CLK_source) +{ + if (CLK_source == RCC_LPTIM1_FILTCLK_SRC_MSI) + { + RCC->RDCTRL1 |= CLK_source; + } + else + { + RCC->RDCTRL1 &= CLK_source; + } +} + +/** +*\*\name RCC_ConfigLPTIM1FilterWidth. +*\*\fun Config LPTIM1 counter value indicating minimum pulse width in terms of APB5 or MSI clock cycles. +*\*\param width_value : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x01 ~ 0x1F The numbers of APB5 or MSI cycles. +*\*\return none +**/ +void RCC_ConfigLPTIM1FilterWidth(uint8_t width_value) +{ + uint32_t temp_value; + + temp_value = RCC->RDCTRL1; + /* Clear LPTIM1FLTDFC[4:0] bits */ + temp_value &= I2C_LPTIM1FLTDFC_MASK; + /* Set LPTIM1FLTDFC[4:0] bits according to width value */ + temp_value |= ((uint32_t)width_value & 0x1FU); + /* Store the new value */ + RCC->RDCTRL1 = temp_value; +} + +/** +*\*\name RCC_EnableLPTIM2Filter. +*\*\fun Control signal to select filtered or non-filtered LPTIM2 comparator clock source. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLPTIM2Filter(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL1 |= RCC_LPTIM2FILT_ENABLE; + } + else + { + RCC->RDCTRL1 &= (~RCC_LPTIM2FILT_ENABLE); + } +} + +/** +*\*\name RCC_SelectLPTIM2FilterSource. +*\*\fun Control signal to select the sample clock for the digital filter used at LPTIM2. +*\*\param CLK_source: +*\*\ - RCC_LPTIM2_FILTCLK_SRC_APB5 +*\*\ - RCC_LPTIM2_FILTCLK_SRC_MSI +*\*\return none. +**/ +void RCC_SelectLPTIM2FilterSource(uint32_t CLK_source) +{ + if (CLK_source == RCC_LPTIM2_FILTCLK_SRC_MSI) + { + RCC->RDCTRL1 |= CLK_source; + } + else + { + RCC->RDCTRL1 &= CLK_source; + } +} + +/** +*\*\name RCC_ConfigLPTIM2FilterWidth. +*\*\fun Config LPTIM2 counter value indicating minimum pulse width in terms of APB5 or MSI clock cycles. +*\*\param width_value : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x01 ~ 0x1F The numbers of APB5 or MSI cycles. +*\*\return none +**/ +void RCC_ConfigLPTIM2FilterWidth(uint8_t width_value) +{ + uint32_t temp_value; + + temp_value = RCC->RDCTRL1; + /* Clear LPTIM2FLTDFC[4:0] bits */ + temp_value &= I2C_LPTIM2FLTDFC_MASK; + /* Set LPTIM2FLTDFC[4:0] bits according to width value */ + temp_value |= (((uint32_t)width_value & 0x1FU) << 16); + /* Store the new value */ + RCC->RDCTRL1 = temp_value; +} + +/** +*\*\name RCC_EnableLPTIM3Filter. +*\*\fun Control signal to select filtered or non-filtered LPTIM3 comparator clock source. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLPTIM3Filter(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL2 |= RCC_LPTIM3FILT_ENABLE; + } + else + { + RCC->RDCTRL2 &= (~RCC_LPTIM3FILT_ENABLE); + } +} + +/** +*\*\name RCC_SelectLPTIM3FilterSource. +*\*\fun Control signal to select the sample clock for the digital filter used at LPTIM3. +*\*\param CLK_source: +*\*\ - RCC_LPTIM3_FILTCLK_SRC_APB5 +*\*\ - RCC_LPTIM3_FILTCLK_SRC_MSI +*\*\return none. +**/ +void RCC_SelectLPTIM3FilterSource(uint32_t CLK_source) +{ + if (CLK_source == RCC_LPTIM3_FILTCLK_SRC_MSI) + { + RCC->RDCTRL2 |= CLK_source; + } + else + { + RCC->RDCTRL2 &= CLK_source; + } +} + +/** +*\*\name RCC_ConfigLPTIM3FilterWidth. +*\*\fun Config LPTIM3 counter value indicating minimum pulse width in terms of APB5 or MSI clock cycles. +*\*\param width_value : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x01 ~ 0x1F The numbers of APB5 or MSI cycles. +*\*\return none +**/ +void RCC_ConfigLPTIM3FilterWidth(uint8_t width_value) +{ + uint32_t temp_value; + + temp_value = RCC->RDCTRL2; + /* Clear LPTIM3FLTDFC[4:0] bits */ + temp_value &= I2C_LPTIM3FLTDFC_MASK; + /* Set LPTIM3FLTDFC[4:0] bits according to width value */ + temp_value |= ((uint32_t)width_value & 0x1FU); + /* Store the new value */ + RCC->RDCTRL2 = temp_value; +} + +/** +*\*\name RCC_EnableLPTIM4Filter. +*\*\fun Control signal to select filtered or non-filtered LPTIM4 comparator clock source. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLPTIM4Filter(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL2 |= RCC_LPTIM4FILT_ENABLE; + } + else + { + RCC->RDCTRL2 &= (~RCC_LPTIM4FILT_ENABLE); + } +} + +/** +*\*\name RCC_SelectLPTIM4FilterSource. +*\*\fun Control signal to select the sample clock for the digital filter used at LPTIM4. +*\*\param CLK_source: +*\*\ - RCC_LPTIM4_FILTCLK_SRC_APB5 +*\*\ - RCC_LPTIM4_FILTCLK_SRC_MSI +*\*\return none. +**/ +void RCC_SelectLPTIM4FilterSource(uint32_t CLK_source) +{ + if (CLK_source == RCC_LPTIM4_FILTCLK_SRC_MSI) + { + RCC->RDCTRL2 |= CLK_source; + } + else + { + RCC->RDCTRL2 &= CLK_source; + } +} + +/** +*\*\name RCC_ConfigLPTIM4FilterWidth. +*\*\fun Config LPTIM4 counter value indicating minimum pulse width in terms of APB5 or MSI clock cycles. +*\*\param width_value : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x01 ~ 0x1F The numbers of APB5 or MSI cycles. +*\*\return none +**/ +void RCC_ConfigLPTIM4FilterWidth(uint8_t width_value) +{ + uint32_t temp_value; + + temp_value = RCC->RDCTRL2; + /* Clear LPTIM4FLTDFC[4:0] bits */ + temp_value &= I2C_LPTIM4FLTDFC_MASK; + /* Set LPTIM4FLTDFC[4:0] bits according to width value */ + temp_value |= (((uint32_t)width_value & 0x1FU) << 16); + /* Store the new value */ + RCC->RDCTRL2 = temp_value; +} + +/** +*\*\name RCC_EnableLPTIM5Filter. +*\*\fun Control signal to select filtered or non-filtered LPTIM5 comparator clock source. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableLPTIM5Filter(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->RDCTRL3 |= RCC_LPTIM5FILT_ENABLE; + } + else + { + RCC->RDCTRL3 &= (~RCC_LPTIM5FILT_ENABLE); + } +} + +/** +*\*\name RCC_SelectLPTIM5FilterSource. +*\*\fun Control signal to select the sample clock for the digital filter used at LPTIM5. +*\*\param CLK_source: +*\*\ - RCC_LPTIM5_FILTCLK_SRC_APB5 +*\*\ - RCC_LPTIM5_FILTCLK_SRC_MSI +*\*\return none. +**/ +void RCC_SelectLPTIM5FilterSource(uint32_t CLK_source) +{ + if (CLK_source == RCC_LPTIM5_FILTCLK_SRC_MSI) + { + RCC->RDCTRL3 |= CLK_source; + } + else + { + RCC->RDCTRL3 &= CLK_source; + } +} + +/** +*\*\name RCC_ConfigLPTIM5FilterWidth. +*\*\fun Config LPTIM5 counter value indicating minimum pulse width in terms of APB5 or MSI clock cycles. +*\*\param width_value : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x01 ~ 0x1F The numbers of APB5 or MSI cycles. +*\*\return none +**/ +void RCC_ConfigLPTIM5FilterWidth(uint8_t width_value) +{ + uint32_t temp_value; + + temp_value = RCC->RDCTRL3; + /* Clear LPTIM5FLTDFC[4:0] bits */ + temp_value &= I2C_LPTIM5FLTDFC_MASK; + /* Set LPTIM5FLTDFC[4:0] bits according to width value */ + temp_value |= ((uint32_t)width_value & 0x1FU); + /* Store the new value */ + RCC->RDCTRL3 = temp_value; +} + +/** +*\*\name RCC_SetWWDG1ResetDelayValue. +*\*\fun Counter threshold used to delay the assertion of WWDG1 reset when WWDG1 reset request event occurs. +*\*\param delay_value: +*\*\ This parameter must be a number between 0 and 0xF +*\*\return none +**/ +void RCC_SetWWDG1ResetDelayValue(uint8_t delay_value) +{ + uint32_t temp_value; + + temp_value = RCC->CFG1; + /* Clear WWDG1RSTDLCNT[3:0] bits */ + temp_value &= RCC_WWDG1RSTDLCNT_MASK; + /* Set the WWDG1RSTDLCNT[3:0] bits according to delay_value */ + temp_value |= (((uint32_t)delay_value & 0xFU) << 16); + /* Store the new value */ + RCC->CFG1 = temp_value; +} + +/** +*\*\name RCC_SetWWDG2ResetDelayValue. +*\*\fun Counter threshold used to delay the assertion of WWDG2 reset when WWDG2 reset request event occurs. +*\*\param delay_value: +*\*\ This parameter must be a number between 0 and 0xF +*\*\return none +**/ +void RCC_SetWWDG2ResetDelayValue(uint8_t delay_value) +{ + uint32_t temp_value; + + temp_value = RCC->CFG1; + /* Clear WWDG2RSTDLCNT[3:0] bits */ + temp_value &= RCC_WWDG2RSTDLCNT_MASK; + /* Set the WWDG2RSTDLCNT[3:0] bits according to delay_value */ + temp_value |= (((uint32_t)delay_value & 0xFU) << 20); + /* Store the new value */ + RCC->CFG1 = temp_value; +} + +/** +*\*\name RCC_ConfigM7TraceClkDivider . +*\*\fun Configure M7 trace clock prescalar values. +*\*\param CLK_divider +*\*\ - RCC_TRACECLK_DIV1 +*\*\ - RCC_TRACECLK_DIV2 +*\*\ - RCC_TRACECLK_DIV4 +*\*\ - RCC_TRACECLK_DIV8 +*\*\ - RCC_TRACECLK_DIV16 +*\*\ - RCC_TRACECLK_DIV32 +*\*\ - RCC_TRACECLK_DIV64 +*\*\ - RCC_TRACECLK_DIV128 +*\*\ - RCC_TRACECLK_DIV256 +*\*\ - RCC_TRACECLK_DIV512 +*\*\return none. +**/ +void RCC_ConfigM7TraceClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->CFG1; + /* Clear M7TRACEDIV bits */ + reg_value &= RCC_M7TRACECLK_DIV_MASK; + /* Set the M7TRACEDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->CFG1 = reg_value; +} + +/** +*\*\name RCC_ConfigM4TraceClkDivider . +*\*\fun Configure M4 trace clock prescalar values. +*\*\param CLK_divider +*\*\ - RCC_TRACECLK_DIV1 +*\*\ - RCC_TRACECLK_DIV2 +*\*\ - RCC_TRACECLK_DIV4 +*\*\ - RCC_TRACECLK_DIV8 +*\*\ - RCC_TRACECLK_DIV16 +*\*\ - RCC_TRACECLK_DIV32 +*\*\ - RCC_TRACECLK_DIV64 +*\*\ - RCC_TRACECLK_DIV128 +*\*\ - RCC_TRACECLK_DIV256 +*\*\ - RCC_TRACECLK_DIV512 +*\*\return none. +**/ +void RCC_ConfigM4TraceClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->CFG1; + /* Clear M4TRACEDIV bits */ + reg_value &= RCC_M4TRACECLK_DIV_MASK; + /* Set the M4TRACEDIV bits */ + reg_value |= (CLK_divider >> 4); + /* Store the new value */ + RCC->CFG1 = reg_value; +} + + +/** +*\*\name RCC_ConfigM7SystickClkDivider . +*\*\fun Configure M7 systick prescalar values from fclk. +*\*\param CLK_divider +*\*\ - RCC_STCLK_DIV1 +*\*\ - RCC_STCLK_DIV2 +*\*\ - RCC_STCLK_DIV4 +*\*\ - RCC_STCLK_DIV8 +*\*\ - RCC_STCLK_DIV16 +*\*\ - RCC_STCLK_DIV32 +*\*\ - RCC_STCLK_DIV64 +*\*\ - RCC_STCLK_DIV128 +*\*\ - RCC_STCLK_DIV256 +*\*\ - RCC_STCLK_DIV512 +*\*\return none. +**/ +void RCC_ConfigM7SystickClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->CFG3; + /* Clear M7STCLKDIV bits */ + reg_value &= RCC_M7STCLK_DIV_MASK; + /* Set the M7STCLKDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->CFG3 = reg_value; +} + +/** +*\*\name RCC_ConfigM4SystickClkDivider . +*\*\fun Configure M4 systick prescalar values from fclk. +*\*\param CLK_divider +*\*\ - RCC_STCLK_DIV2 +*\*\ - RCC_STCLK_DIV4 +*\*\ - RCC_STCLK_DIV8 +*\*\ - RCC_STCLK_DIV16 +*\*\ - RCC_STCLK_DIV32 +*\*\ - RCC_STCLK_DIV64 +*\*\ - RCC_STCLK_DIV128 +*\*\ - RCC_STCLK_DIV256 +*\*\ - RCC_STCLK_DIV512 +*\*\return none. +*\*\note DIV1 is not supported +**/ +void RCC_ConfigM4SystickClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->CFG3; + /* Clear M4STCLKDIV bits */ + reg_value &= RCC_M4STCLK_DIV_MASK; + /* Set the M4STCLKDIV bits */ + reg_value |= (CLK_divider >> 4); + /* Store the new value */ + RCC->CFG3 = reg_value; +} + +/** +*\*\name RCC_EnableDualCoreDebugClk. +*\*\fun Dual core debug clock enable. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableDualCoreDebugClk(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->CFG5 |= RCC_DUALCORE_DBG_ENABLE; + } + else + { + RCC->CFG5 &= (~RCC_DUALCORE_DBG_ENABLE); + } +} + +/** +*\*\name RCC_ConfigRTCHSIClkDivider . +*\*\fun RTC HSI clock prescalar values. +*\*\param CLK_divider +*\*\ - RCC_RTCCLK_HSIDIV1 +*\*\ - RCC_RTCCLK_HSIDIV2 +*\*\ - RCC_RTCCLK_HSIDIV4 +*\*\ - RCC_RTCCLK_HSIDIV8 +*\*\ - RCC_RTCCLK_HSIDIV16 +*\*\ - RCC_RTCCLK_HSIDIV32 +*\*\ - RCC_RTCCLK_HSIDIV64 +*\*\ - RCC_RTCCLK_HSIDIV128 +*\*\ - RCC_RTCCLK_HSIDIV256 +*\*\ - RCC_RTCCLK_HSIDIV512 +*\*\return none. +**/ +void RCC_ConfigRTCHSIClkDivider(uint32_t CLK_divider) +{ + uint32_t reg_value; + + reg_value = RCC->CFG5; + /* Clear RTCHSIDIV bits */ + reg_value &= RCC_RTCCLK_HSIDIV_MASK; + /* Set the RTCHSIDIV bits */ + reg_value |= CLK_divider; + /* Store the new value */ + RCC->CFG5 = reg_value; +} + +/** +*\*\name RCC_EnablePLLSoftwareLock. +*\*\fun Enable this bit if hardware PLL lock fail. +*\*\param lock_type : +*\*\ - RCC_SOFTLOCK_EN_SHRPLL +*\*\ - RCC_SOFTLOCK_EN_PLL3 +*\*\ - RCC_SOFTLOCK_EN_PLL2 +*\*\ - RCC_SOFTLOCK_EN_PLL1 +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnablePLLSoftwareLock(uint32_t lock_type, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->PLLSFTLK |= lock_type; + } + else + { + RCC->PLLSFTLK &= ~lock_type; + } + +} + +/** +*\*\name RCC_EnableSHRTIMAFEReset. +*\*\fun Used to assert POR reset to SHRTIM AFE. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableSHRTIMAFEReset(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->PLLSFTLK &= (~RCC_SHRTIMAFE_RESET_ENABLE); + } + else + { + RCC->PLLSFTLK |= RCC_SHRTIMAFE_RESET_ENABLE; + } +} + +/** +*\*\name RCC_EnableSDRAMDelayChain. +*\*\fun SDRAM Delay chain enable. +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void RCC_EnableSDRAMDelayChain(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + RCC->PLLSFTLK |= RCC_SDRAM_DELAY_ENABLE; + } + else + { + RCC->PLLSFTLK &= (~RCC_SDRAM_DELAY_ENABLE); + } +} + +/** +*\*\name RCC_ConfigSDRAMDelay . +*\*\fun Increase SDRAM clock latency. +*\*\param CLK_delay +*\*\ - RCC_SDRAM_DELAY_0_2NS Increase SDRAM clock latency by 0.2ns +*\*\ - RCC_SDRAM_DELAY_0_4NS Increase SDRAM clock latency by 0.4ns +*\*\ - RCC_SDRAM_DELAY_0_6NS Increase SDRAM clock latency by 0.6ns +*\*\ - RCC_SDRAM_DELAY_0_8NS Increase SDRAM clock latency by 0.8ns +*\*\ - RCC_SDRAM_DELAY_1_0NS Increase SDRAM clock latency by 1.0ns +*\*\ - RCC_SDRAM_DELAY_1_2NS Increase SDRAM clock latency by 1.2ns +*\*\ - RCC_SDRAM_DELAY_1_4NS Increase SDRAM clock latency by 1.4ns +*\*\ - RCC_SDRAM_DELAY_1_6NS Increase SDRAM clock latency by 1.6ns +*\*\ - RCC_SDRAM_DELAY_1_8NS Increase SDRAM clock latency by 1.8ns +*\*\ - RCC_SDRAM_DELAY_2_0NS Increase SDRAM clock latency by 2.0ns +*\*\ - RCC_SDRAM_DELAY_2_2NS Increase SDRAM clock latency by 2.2ns +*\*\ - RCC_SDRAM_DELAY_2_4NS Increase SDRAM clock latency by 2.4ns +*\*\ - RCC_SDRAM_DELAY_2_6NS Increase SDRAM clock latency by 2.6ns +*\*\ - RCC_SDRAM_DELAY_2_8NS Increase SDRAM clock latency by 2.8ns +*\*\ - RCC_SDRAM_DELAY_3_0NS Increase SDRAM clock latency by 3.0ns +*\*\ - RCC_SDRAM_DELAY_3_2NS Increase SDRAM clock latency by 3.2ns +*\*\return none. +**/ +void RCC_ConfigSDRAMDelay(uint32_t CLK_delay) +{ + uint32_t reg_value; + + reg_value = RCC->PLLSFTLK; + /* Clear SDRAMDLSEL bits */ + reg_value &= RCC_SDRAM_DELAY_MASK; + /* Set the SDRAMDLSEL bits */ + reg_value |= CLK_delay; + /* Store the new value */ + RCC->PLLSFTLK = reg_value; +} + +/** +*\*\name RCC_ConfigHSEDriveStrength . +*\*\fun Config HSE drive strength. +*\*\param CLK_driver +*\*\ - 0x0 ~ 0x7 (min drive strength ~ max drive strength) +*\*\ - default value: 0x4 +*\*\return none. +**/ +void RCC_ConfigHSEDriveStrength(uint32_t CLK_driver) +{ + uint32_t reg_value; + + reg_value = AFEC->TRIMR1; + /* Clear SDRAMDLSEL bits */ + reg_value &= 0xFFF1FFFFU; + /* Set the SDRAMDLSEL bits */ + reg_value |= (CLK_driver << 17U); + /* Store the new value */ + AFEC->TRIMR1 = reg_value; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rtc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rtc.c new file mode 100644 index 0000000000..45667f3915 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_rtc.c @@ -0,0 +1,2412 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_rtc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_rtc.h" + +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** +*\*\name RTC_DeInit. +*\*\fun Deinitializes the RTC registers to their default reset values. +*\*\param none +*\*\return ErrorStatus +*\*\ - SUCCESS: RTC registers are deinitialized +*\*\ - ERROR: RTC registers are not deinitialized +*\*\ +**/ +ErrorStatus RTC_DeInit(void) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus; + ErrorStatus status; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TSH, DAT and CTRL registers */ + RTC->TSH = (uint32_t)0x00000000; + RTC->DATE = (uint32_t)0x00002101; + + /* Reset All CTRL bits except CTRL[2:0] */ + RTC->CTRL &= (uint32_t)0x00000007; + + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } + while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + /* Reset all RTC CTRL register bits */ + RTC->CTRL &= (uint32_t)0x00000000; + RTC->WKUPT = (uint32_t)0x0000FFFF; + RTC->PRE = (uint32_t)0x007F00FF; + RTC->ALARMA = (uint32_t)0x00000000; + RTC->ALARMB = (uint32_t)0x00000000; + RTC->CALIB = (uint32_t)0x00000000; + RTC->ALRMASS = (uint32_t)0x00000000; + RTC->ALRMBSS = (uint32_t)0x00000000; + + /* Reset INTSTS register and exit initialization mode */ + RTC->INITSTS = (uint32_t)0x00000000; + + RTC->OPT = (uint32_t)0x00000000; + + + /* Wait till the RTC RSYF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** +*\*\name RTC_Init. +*\*\fun RTC_InitStruct pointer to a RTC_InitType structure that contains +*\*\ the configuration information for the RTC peripheral +*\*\param RTC_InitStruct +*\*\ - RTC_HourFormat +*\*\ - RTC_24HOUR_FORMAT +*\*\ - RTC_12HOUR_FORMAT +*\*\ - RTC_AsynchPrediv the value is selected in the 1-0x7F range +*\*\ - RTC_SynchPrediv the value must lower than 0x7FFF +*\*\return ErrorStatus +*\*\ - SUCCESS: RTC registers are deinitialized +*\*\ - ERROR: RTC registers are not deinitialized +*\*\ +**/ +ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct) +{ + ErrorStatus status; + uint16_t i; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Clear RTC CTRL HFMT Bit */ + RTC->CTRL &= ((uint32_t) ~(RTC_CTRL_HFMT)); + /* Set RTC_CTRL register */ + RTC->CTRL |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /* Configure the RTC PRE */ + RTC->PRE = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRE |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + /* Delay for the RTC prescale effect */ + for(i = 0; i < 0x2FF; i++) + { + /* NOP */ + }; + + return status; +} + +/** +*\*\name RTC_StructInit. +*\*\fun Fills each RTC_InitStruct member with its default value. +*\*\param RTC_InitStruct : RTC_InitStruct pointer to a RTC_InitType structure which will beinitialized. +*\*\ - RTC_HourFormat +*\*\ - RTC_24HOUR_FORMAT +*\*\ - RTC_12HOUR_FORMAT +*\*\ - RTC_AsynchPrediv the value is selected in the 1-0x7F range +*\*\ - RTC_SynchPrediv the value must lower than 0x7FFF +*\*\return none +**/ +void RTC_StructInit(RTC_InitType* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_24HOUR_FORMAT; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** +*\*\name RTC_EnableWriteProtection. +*\*\fun Enable or disable the RTC registers write protection. + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableWriteProtection(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + } +} + +/** +*\*\name RTC_EnterInitMode. +*\*\fun Enters the RTC Initialization mode. +*\*\param none +*\*\return ErrorStatus +*\*\ - SUCCESS: RTC is in Init mode +*\*\ - ERROR: RTC is not in Init mode +**/ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status; + uint32_t initstatus; + + /* Check if the Initialization mode is set */ + if ((RTC->INITSTS & RTC_INITSTS_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + RTC->INITSTS = (uint32_t)RTC_INITSTS_INITM; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do + { + initstatus = RTC->INITSTS & RTC_INITSTS_INITF; + initcounter++; + } + while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_INITF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + } + else + { + status = SUCCESS; + } + + return (status); +} + +/** +*\*\name RTC_ExitInitMode. +*\*\fun When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. +*\*\param none +*\*\return none +**/ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->INITSTS &= (uint32_t)~RTC_INITSTS_INITM; +} + +/** +*\*\name RTC_WaitForSynchro. +*\*\fun Waits until the RTC Time and Date registers (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. +*\*\param none +*\*\return ErrorStatus : +*\*\ - SUCCESS: RTC registers are synchronised +*\*\ - ERROR: RTC registers are not synchronised +**/ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status; + uint32_t synchrostatus; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear RSYF flag */ + RTC->INITSTS &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised and 5500ms timeout */ + do + { + synchrostatus = RTC->INITSTS & RTC_INITSTS_RSYF; + synchrocounter++; + } + while ((synchrocounter < SYNCHRO_TIMEOUT) && (synchrostatus == 0x00U)); + + if ((RTC->INITSTS & RTC_INITSTS_RSYF) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (status); +} + + +/** +*\*\name RTC_EnableRefClock. +*\*\fun Enables or disables the RTC reference clock detection. + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return none +**/ +ErrorStatus RTC_EnableRefClock(FunctionalState Cmd) +{ + ErrorStatus status; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + if (Cmd != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CTRL |= RTC_CTRL_REFCLKEN; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CTRL &= ~RTC_CTRL_REFCLKEN; + } + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + status = SUCCESS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + + +/** +*\*\name RTC_EnableBypassShadow. +*\*\fun When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableBypassShadow(FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Set the BYPS bit */ + RTC->CTRL |= (uint8_t)RTC_CTRL_BYPS; + } + else + { + /* Reset the BYPS bit */ + RTC->CTRL &= (uint8_t)~RTC_CTRL_BYPS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigTime. +*\*\fun Calendar value read from Shadow register. + *\*\param RTC_Format : + *\*\ - RTC_FORMAT_BIN + *\*\ - RTC_FORMAT_BCD +*\*\param RTC_TimeStruct : RTC_TimeStruct pointer to a RTC_TimeType structure that contains +*\*\ the time configuration information for the RTC.When the user does not need to configure this +*\*\ parameter, note that NULL can be passed in. +*\*\ - Hours +*\*\ - if RTC_AM_H12 is select the value in the 0-23 range +*\*\ - if RTC_PM_H12 is select the value in the 1-12 range +*\*\ - Minutes the value set in the 0-59 range +*\*\ - Seconds the value set in the 0-59 range +*\*\ - H12 +*\*\ - RTC_AM_H12 +*\*\ - RTC_PM_H12 +*\*\return none +**/ +ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister; + ErrorStatus status; + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = (((uint32_t)(RTC_TimeStruct->Hours) << 16) | ((uint32_t)(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_TimeStruct->Seconds) | ((uint32_t)(RTC_TimeStruct->H12) << 16)); + } + else + { + tmpregister = + (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->Seconds)) | (((uint32_t)RTC_TimeStruct->H12) << 16)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_TSH register */ + RTC->TSH = (uint32_t)(tmpregister & RTC_TR_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(status != ERROR) + { + status = RTC_WaitForSynchro(); + } + + return status; +} + +/** +*\*\name RTC_TimeStructInit. +*\*\fun Fills each RTC_TimeStruct member with its default value +*\*\ (Time = 00h:00 min:00sec). +*\*\param RTC_TimeStruct : RTC_TimeStruct pointer to a RTC_TimeType structure that contains +*\*\ the time configuration information for the RTC. +*\*\ - Hours +*\*\ - if RTC_AM_H12 is select the value in the 0-23 range +*\*\ - if RTC_PM_H12 is select the value in the 1-12 range +*\*\ - Minutes the value set in the 0-59 range +*\*\ - Seconds the value set in the 0-59 range +*\*\ - H12 +*\*\ - RTC_AM_H12 +*\*\ - RTC_PM_H12 +*\*\return none +**/ +void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->H12 = RTC_AM_H12; + RTC_TimeStruct->Hours = 0; + RTC_TimeStruct->Minutes = 0; + RTC_TimeStruct->Seconds = 0; +} + +/** +*\*\name RTC_GetTime. +*\*\fun Get the RTC current Time. +*\*\param RTC_Format : specifies the format of the returned parameters. +*\*\ - RTC_FORMAT_BIN +*\*\ - RTC_FORMAT_BCD +*\*\param RTC_TimeStruct : RTC_TimeStruct pointer to a RTC_TimeType structure. +*\*\return none +**/ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct) +{ + uint32_t tmpregister; + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->TSH & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->Hours = (uint8_t)((tmpregister & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16); + RTC_TimeStruct->Minutes = (uint8_t)((tmpregister & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8); + RTC_TimeStruct->Seconds = (uint8_t)(tmpregister & (RTC_TSH_SCT | RTC_TSH_SCU)); + RTC_TimeStruct->H12 = (uint8_t)((tmpregister & (RTC_TSH_APM)) >> 16); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Hours); + RTC_TimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Minutes); + RTC_TimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->Seconds); + } +} + +/** +*\*\name RTC_GetSubSecond. +*\*\fun Gets the RTC current Calendar Subseconds value. +*\*\return RTC current Calendar Subseconds value. +**/ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpregister; + + /* Get subseconds values from the correspondent registers*/ + tmpregister = (uint32_t)(RTC->SUBS); + + return (tmpregister); +} + +/** +*\*\name RTC_SetDate. +*\*\fun Set RTC Calendar current date. +*\*\param RTC_Format : specifies the format of the returned parameters. +*\*\ - RTC_FORMAT_BIN +*\*\ - RTC_FORMAT_BCD +*\*\param RTC_DateStruct : RTC_DateStruct pointer to a RTC_DateType structure that contains +*\*\ the date configuration information for the RTC,note that NULL can be passed in. +*\*\ - WeekDay +*\*\ - RTC_WEEKDAY_MONDAY +*\*\ - RTC_WEEKDAY_TUESDAY +*\*\ - RTC_WEEKDAY_WEDNESDAY +*\*\ - RTC_WEEKDAY_THURSDAY +*\*\ - RTC_WEEKDAY_FRIDAY +*\*\ - RTC_WEEKDAY_SATURDAY +*\*\ - RTC_WEEKDAY_SUNDAY +*\*\ - Month +*\*\ - RTC_MONTH_JANUARY +*\*\ - RTC_MONTH_FEBRURY +*\*\ - RTC_MONTH_MARCH +*\*\ - RTC_MONTH_APRIL +*\*\ - RTC_MONTH_MAY +*\*\ - RTC_MONTH_JUNE +*\*\ - RTC_MONTH_JULY +*\*\ - RTC_MONTH_AUGUST +*\*\ - RTC_MONTH_SEPTEMBER +*\*\ - RTC_MONTH_OCTOBER +*\*\ - RTC_MONTH_NOVEMBER +*\*\ - RTC_MONTH_DECEMBER +*\*\ - Date the value in the 1-31 range +*\*\ - Year the value in the 0-99 range +*\*\return ErrorStatus +*\*\ - SUCCESS: RTC Date register is configured +*\*\ - ERROR: RTCDate register is not configured +**/ +ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister; + ErrorStatus status; + + if ((RTC_Format == RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & (uint8_t)0x10) == (uint8_t)0x10)) + { + RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint8_t)0xEF) + (uint8_t)0x0A; + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = ((((uint32_t)RTC_DateStruct->Year) << 16) | (((uint32_t)RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_DateStruct->Date) | (((uint32_t)RTC_DateStruct->WeekDay) << 13)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Year) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Month) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->Date)) | ((uint32_t)RTC_DateStruct->WeekDay << 13)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Set the RTC_DATE register */ + RTC->DATE = (uint32_t)(tmpregister & RTC_DATE_RESERVED_MASK); + + /* Exit Initialization mode */ + RTC_ExitInitMode(); + + /* If RTC_CTRL_BYPS bit = 0, wait for synchro else this check is not needed */ + if ((RTC->CTRL & RTC_CTRL_BYPS) == RESET) + { + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + /* Waits until the RTC Time and Date registers + (RTC_TSH and RTC_DATE) are synchronized with RTC APB clock. */ + if(ERROR != status) + { + status = RTC_WaitForSynchro(); + } + + return status; +} + + +/** +*\*\name RTC_DateStructInit. +*\*\fun Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00). +*\*\param RTC_DateStruct : RTC_DateStruct pointer to a RTC_DateType structure that contains +*\*\ the date configuration information for the RTC. +*\*\ - WeekDay +*\*\ - RTC_WEEKDAY_MONDAY +*\*\ - RTC_WEEKDAY_TUESDAY +*\*\ - RTC_WEEKDAY_WEDNESDAY +*\*\ - RTC_WEEKDAY_THURSDAY +*\*\ - RTC_WEEKDAY_FRIDAY +*\*\ - RTC_WEEKDAY_SATURDAY +*\*\ - RTC_WEEKDAY_SUNDAY +*\*\ - Month +*\*\ - RTC_MONTH_JANUARY +*\*\ - RTC_MONTH_FEBRURY +*\*\ - RTC_MONTH_MARCH +*\*\ - RTC_MONTH_APRIL +*\*\ - RTC_MONTH_MAY +*\*\ - RTC_MONTH_JUNE +*\*\ - RTC_MONTH_JULY +*\*\ - RTC_MONTH_AUGUST +*\*\ - RTC_MONTH_SEPTEMBER +*\*\ - RTC_MONTH_OCTOBER +*\*\ - RTC_MONTH_NOVEMBER +*\*\ - RTC_MONTH_DECEMBER +*\*\ - Date the value in the 1-31 range +*\*\ - Year the value in the 0-99 range +*\*\return none +**/ +void RTC_DateStructInit(RTC_DateType* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Date = 1; + RTC_DateStruct->Month = RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0; +} +/** +*\*\name RTC_GetDate. +*\*\fun Get the RTC current date. +*\*\param RTC_Format : specifies the format of the returned parameters. +*\*\ - RTC_FORMAT_BIN +*\*\ - RTC_FORMAT_BCD +*\*\param RTC_DateType : RTC_DateStruct pointer to a RTC_DateType structure that will +*\*\ contain the returned current date configuration. +*\*\return none +**/ +void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct) +{ + uint32_t tmpregister; + + /* Get the RTC_TSH register */ + tmpregister = (uint32_t)(RTC->DATE & RTC_DATE_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_DateStruct->Year = (uint8_t)((tmpregister & (RTC_DATE_YRT | RTC_DATE_YRU)) >> 16); + RTC_DateStruct->Month = (uint8_t)((tmpregister & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_DateStruct->Date = (uint8_t)(tmpregister & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_DateStruct->WeekDay = (uint8_t)((tmpregister & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Year); + RTC_DateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Month); + RTC_DateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->Date); + } +} + +/** +*\*\name RTC_SetAlarm. +*\*\fun Set the specified RTC Alarm. +*\*\param RTC_Format : specifies the format of the returned parameters. +*\*\ - RTC_FORMAT_BIN +*\*\ - RTC_FORMAT_BCD +*\*\param RTC_Alarm : RTC_Alarm specifies the alarm to be configured. +*\*\ - RTC_A_ALARM +*\*\ - RTC_B_ALARM +*\*\param RTC_AlarmStruct : RTC_AlarmStruct pointer to a RTC_AlarmType structure that +*\*\ contains the alarm configuration parameters. +*\*\ - AlarmTime RTC_TimeStruct pointer to a RTC_TimeType structure that contains +*\*\ the time configuration information for the RTC. +*\*\ - Hours +*\*\ - if RTC_AM_H12 is select the value in the 0-23 range +*\*\ - if RTC_PM_H12 is select the value in the 1-12 range +*\*\ - Minutes the value set in the 0-59 range +*\*\ - Seconds the value set in the 0-59 range +*\*\ - H12 +*\*\ - RTC_AM_H12 +*\*\ - RTC_PM_H12 +*\*\ - AlarmMask +*\*\ - RTC_ALARMMASK_NONE +*\*\ - RTC_ALARMMASK_WEEKDAY +*\*\ - RTC_ALARMMASK_HOURS +*\*\ - RTC_ALARMMASK_MINUTES +*\*\ - RTC_ALARMMASK_SECONDS +*\*\ - RTC_ALARMMASK_ALL +*\*\ - DateWeekMode +*\*\ - RTC_ALARM_SEL_WEEKDAY_DATE +*\*\ - RTC_ALARM_SEL_WEEKDAY_WEEKDAY +*\*\ - DateWeekValue +*\*\ - RTC_WEEKDAY_MONDAY +*\*\ - RTC_WEEKDAY_TUESDAY +*\*\ - RTC_WEEKDAY_WEDNESDAY +*\*\ - RTC_WEEKDAY_THURSDAY +*\*\ - RTC_WEEKDAY_FRIDAY +*\*\ - RTC_WEEKDAY_SATURDAY +*\*\ - RTC_WEEKDAY_SUNDAY +*\*\return none +**/ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister; + + /* Check the input parameters format */ + if (RTC_Format != RTC_FORMAT_BIN) + { + tmpregister = + (((uint32_t)(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.Minutes) << 8) | ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) | ((uint32_t)(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + else + { + tmpregister = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Hours) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Minutes) << 8) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->AlarmTime.Seconds)) + | ((uint32_t)(RTC_AlarmStruct->AlarmTime.H12) << 16) + | ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->DateWeekValue) << 24) + | ((uint32_t)RTC_AlarmStruct->DateWeekMode) | ((uint32_t)RTC_AlarmStruct->AlarmMask)); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm register */ + if (RTC_Alarm == RTC_A_ALARM) + { + RTC->ALARMA = (uint32_t)tmpregister; + } + else + { + RTC->ALARMB = (uint32_t)tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_AlarmStructInit. +*\*\fun Fills each RTC_AlarmStruct member with its default value +*\*\ (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = +*\*\ all fields are masked). +*\*\param RTC_AlarmStruct : RTC_AlarmStruct pointer to a RTC_AlarmType structure that +*\*\ contains the alarm configuration parameters. +*\*\ - AlarmTime RTC_TimeStruct pointer to a RTC_TimeType structure that contains +*\*\ the time configuration information for the RTC. +*\*\ - Hours +*\*\ - if RTC_AM_H12 is select the value in the 0-23 range +*\*\ - if RTC_PM_H12 is select the value in the 1-12 range +*\*\ - Minutes the value set in the 0-59 range +*\*\ - Seconds the value set in the 0-59 range +*\*\ - H12 +*\*\ - RTC_AM_H12 +*\*\ - RTC_PM_H12 +*\*\ - AlarmMask +*\*\ - RTC_ALARMMASK_NONE +*\*\ - RTC_ALARMMASK_WEEKDAY +*\*\ - RTC_ALARMMASK_HOURS +*\*\ - RTC_ALARMMASK_MINUTES +*\*\ - RTC_ALARMMASK_SECONDS +*\*\ - RTC_ALARMMASK_ALL +*\*\ - DateWeekMode +*\*\ - RTC_ALARM_SEL_WEEKDAY_DATE +*\*\ - RTC_ALARM_SEL_WEEKDAY_WEEKDAY +*\*\ - DateWeekValue +*\*\ - RTC_WEEKDAY_MONDAY +*\*\ - RTC_WEEKDAY_TUESDAY +*\*\ - RTC_WEEKDAY_WEDNESDAY +*\*\ - RTC_WEEKDAY_THURSDAY +*\*\ - RTC_WEEKDAY_FRIDAY +*\*\ - RTC_WEEKDAY_SATURDAY +*\*\ - RTC_WEEKDAY_SUNDAY +*\*\return none +**/ +void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.H12 = RTC_AM_H12; + RTC_AlarmStruct->AlarmTime.Hours = 0; + RTC_AlarmStruct->AlarmTime.Minutes = 0; + RTC_AlarmStruct->AlarmTime.Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->DateWeekMode = RTC_ALARM_SEL_WEEKDAY_DATE; + RTC_AlarmStruct->DateWeekValue = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = RTC_ALARMMASK_NONE; +} + +/** +*\*\name RTC_GetAlarm. +*\*\fun Get the RTC Alarm value and masks. +*\*\param RTC_Format : specifies the format of the output parameters. +*\*\ - RTC_FORMAT_BIN +*\*\ - RTC_FORMAT_BCD +*\*\param RTC_Alarm : specifies the alarm to be read. +*\*\ - RTC_A_ALARM +*\*\ - RTC_B_ALARM +*\*\param RTC_AlarmStruct : pointer to a RTC_AlarmType structure that will +*\*\ contains the output alarm configuration values. +*\*\ +*\*\return none +**/ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct) +{ + uint32_t tmpregister; + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)(RTC->ALARMA); + } + else + { + tmpregister = (uint32_t)(RTC->ALARMB); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->AlarmTime.Hours = (uint8_t)((tmpregister & (RTC_ALARMA_HOT | RTC_ALARMA_HOU)) >> 16); + RTC_AlarmStruct->AlarmTime.Minutes = (uint8_t)((tmpregister & (RTC_ALARMA_MIT | RTC_ALARMA_MIU)) >> 8); + RTC_AlarmStruct->AlarmTime.Seconds = (uint8_t)(tmpregister & (RTC_ALARMA_SET | RTC_ALARMA_SEU)); + RTC_AlarmStruct->AlarmTime.H12 = (uint8_t)((tmpregister & RTC_ALARMA_APM) >> 16); + RTC_AlarmStruct->DateWeekValue = (uint8_t)((tmpregister & (RTC_ALARMA_DTT | RTC_ALARMA_DTU)) >> 24); + RTC_AlarmStruct->DateWeekMode = (uint32_t)(tmpregister & RTC_ALARMA_WKDSEL); + RTC_AlarmStruct->AlarmMask = (uint32_t)(tmpregister & RTC_ALARMMASK_ALL); + + if (RTC_Format == RTC_FORMAT_BIN) + { + RTC_AlarmStruct->AlarmTime.Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Hours); + RTC_AlarmStruct->AlarmTime.Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Minutes); + RTC_AlarmStruct->AlarmTime.Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->AlarmTime.Seconds); + RTC_AlarmStruct->DateWeekValue = RTC_Bcd2ToByte(RTC_AlarmStruct->DateWeekValue); + } +} + +/** +*\*\name RTC_EnableAlarm. +*\*\fun Enables or disables the specified RTC Alarm. +*\*\param RTC_Alarm : specifies the alarm to be configured. +*\*\ - RTC_A_ALARM +*\*\ - RTC_B_ALARM + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return ErrorStatus : +*\*\ - SUCCESS: RTC Alarm set succeed +*\*\ - ERROR: RTC Alarm set failed +**/ +ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd) +{ + __IO uint32_t alarmcounter = 0x00; + uint32_t alarmstatus; + ErrorStatus status; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm state */ + if (Cmd != DISABLE) + { + RTC->CTRL |= (uint32_t)RTC_Alarm; + + status = SUCCESS; + } + else + { + /* Disable the Alarm in RTC_CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_Alarm; + + /* Wait till RTC ALxWF flag is set and if Time out is reached exit */ + do + { + alarmstatus = RTC->INITSTS & (RTC_Alarm >> 8); + alarmcounter++; + } + while ((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); + + if ((RTC->INITSTS & (RTC_Alarm >> 8)) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** +*\*\name RTC_ConfigAlarmSubSecond. +*\*\fun Configure the RTC AlarmA/B Subseconds value and mask +*\*\param RTC_Alarm : specifies the alarm to be configured. +*\*\ - RTC_A_ALARM : select Alarm A. +*\*\ - RTC_B_ALARM : select Alarm B. +*\*\param RTC_AlarmSubSecondValue : specifies the Subseconds value, the value in the 0-0x00007FFF range +*\*\param RTC_AlarmSubSecondMask : specifies the Subseconds Mask. +*\*\ - RTC_SUBS_MASK_ALL : Alarm SS fields are masked There is no comparison on sub seconds for Alarm. +*\*\ - RTC_SUBS_MASK_SS14_1 : SS[14:1] are don't care in Alarm comparison Only SS[0] is compared +*\*\ - RTC_SUBS_MASK_SS14_2 : SS[14:2] are don't care in Alarm comparison Only SS[1:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_3 : SS[14:3] are don't care in Alarm comparison Only SS[2:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_4 : SS[14:4] are don't care in Alarm comparison Only SS[3:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_5 : SS[14:5] are don't care in Alarm comparison Only SS[4:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_6 : SS[14:6] are don't care in Alarm comparison Only SS[5:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_7 : SS[14:7] are don't care in Alarm comparison Only SS[6:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_8 : SS[14:8] are don't care in Alarm comparison Only SS[7:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_9 : SS[14:9] are don't care in Alarm comparison Only SS[8:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_10 : SS[14:10] are don't care in Alarm comparison Only SS[9:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_11 : SS[14:11] are don't care in Alarm comparison Only SS[10:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_12 : SS[14:12] are don't care in Alarm comparison Only SS[11:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_13 : SS[14:13] are don't care in Alarm comparison Only SS[12:0] are compared +*\*\ - RTC_SUBS_MASK_SS14_14 : SS[14] is don't care in Alarm comparison Only SS[13:0] are compared. +*\*\ - RTC_SUBS_MASK_NONE : SS[14:0] are compared and must match to activate alarm. +*\*\return None +**/ +void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpregister; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpregister = (uint32_t)(uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); + + if (RTC_Alarm == RTC_A_ALARM) + { + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASS = tmpregister; + } + else + { + /* Configure the Alarm B SubSecond register */ + RTC->ALRMBSS = tmpregister; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + + +/** +*\*\name RTC_GetAlarmSubSecond. +*\*\fun Gets the RTC Alarm Subseconds value. +*\*\param RTC_Alarm : specifies the alarm to be read. +*\*\ - RTC_A_ALARM : select Alarm A. +*\*\ - RTC_B_ALARM : select Alarm B. +*\*\return RTC Alarm Subseconds value. +**/ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpregister; + + /* Get the RTC_ALARMx register */ + if (RTC_Alarm == RTC_A_ALARM) + { + tmpregister = (uint32_t)((RTC->ALRMASS) & RTC_ALRMASS_SSV); + } + else + { + tmpregister = (uint32_t)((RTC->ALRMBSS) & RTC_ALRMBSS_SSV); + } + + return (tmpregister); +} + + + +/** +*\*\name RTC_ConfigWakeUpClock. +*\*\fun Configures the RTC Wakeup clock source. +*\*\param RTC_WakeUpClock : RTC_WakeUpClock Wakeup Clock source. +*\*\ - RTC_WKUPCLK_RTCCLK_DIV16 : RTC Wakeup Counter Clock = RTCCLK/16. +*\*\ - RTC_WKUPCLK_RTCCLK_DIV8 : RTC Wakeup Counter Clock = RTCCLK/8. +*\*\ - RTC_WKUPCLK_RTCCLK_DIV4 : RTC Wakeup Counter Clock = RTCCLK/4. +*\*\ - RTC_WKUPCLK_RTCCLK_DIV2 : RTC Wakeup Counter Clock = RTCCLK/2. +*\*\ - RTC_WKUPCLK_CK_SPRE_16BITS : RTC Wakeup Counter Clock = CK_SPRE. +*\*\ - RTC_WKUPCLK_CK_SPRE_17BITS : RTC Wakeup Counter Clock = CK_SPRE,and wakeup timer count is 2^16. +*\*\return none +**/ +void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the Wakeup Timer clock source bits in CTRL register */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WKUPSEL; + + /* Configure the clock source */ + RTC->CTRL |= (uint32_t)RTC_WakeUpClock; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_SetWakeUpCounter. +*\*\fun Configures the RTC Wakeup counter. +*\*\param RTC_WakeUpCounter : specifies the WakeUp counter, the value in the 0-0xFFFF range +*\*\return none +**/ +void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Wakeup Timer counter */ + RTC->WKUPT = (uint32_t)RTC_WakeUpCounter; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_GetWakeUpCounter. +*\*\fun Returns the RTC WakeUp timer counter value. +*\*\param none +*\*\return The RTC WakeUp Counter value. +**/ +uint32_t RTC_GetWakeUpCounter(void) +{ + /* Get the counter value */ + return ((uint32_t)(RTC->WKUPT & RTC_WKUPT_WKUPT)); +} + +/** +*\*\name RTC_EnableWakeUp +*\*\fun Enables or disables the RTC WakeUp timer. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return ErrorStatus : +*\*\ - SUCCESS: RTC wakeup configured succeed +*\*\ - ERROR: RTC wakeup configured failed +**/ +ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd) +{ + __IO uint32_t wutcounter = 0x00; + uint32_t wutwfstatus; + ErrorStatus status; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the Wakeup Timer */ + RTC->CTRL |= (uint32_t)RTC_CTRL_WTEN; + status = SUCCESS; + } + else + { + /* Disable the Wakeup Timer */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_WTEN; + + /* Wait till RTC WTWF flag is set and if Time out is reached exit */ + do + { + wutwfstatus = RTC->INITSTS & RTC_INITSTS_WTWF; + wutcounter++; + } + while ((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); + + if ((RTC->INITSTS & RTC_INITSTS_WTWF) == RESET) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return status; +} + +/** +*\*\name RTC_ConfigDayLightSaving +*\*\fun Adds or substract one hour from the current time. +*\*\param RTC_DayLightSaving : the value of hour adjustment. +*\*\ - RTC_DAYLIGHT_SAVING_SUB1H : Substract one hour (winter time). +*\*\ - RTC_DAYLIGHT_SAVING_ADD1H : Add one hour (summer time). +*\*\param RTC_StoreOperation : Specifies the value to be written in the BCK bit +*\*\ in CTRL register to store the operation. +*\*\ - RTC_STORE_OPERATION_RESET : BCK Bit Reset. +*\*\ - RTC_STORE_OPERATION_SET : BCK Bit Set. +*\*\return none +**/ +void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_BAKP); + /* Clear the SU1H and AD1H bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_SU1H & RTC_CTRL_AD1H); + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_GetStoreOperation +*\*\fun Returns the RTC Day Light Saving stored operation. +*\*\return RTC Day Light Saving stored operation. +*\*\ - RTC_STORE_OPERATION_RESET +*\*\ - RTC_STORE_OPERATION_SET +**/ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CTRL & RTC_CTRL_BAKP); +} + +/** +*\*\name RTC_EnableCalOVDetect +*\*\fun Enable the RTC calendar overflow detection mechanism. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableCalOVDetect(FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Set the CAOVEN bit */ + RTC->CTRL |= (uint8_t)RTC_CTRL_CAOVEN; + } + else + { + /* Reset the CAOVEN bit */ + RTC->CTRL &= (uint8_t)~RTC_CTRL_CAOVEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigOutput +*\*\fun Configures the RTC output source. +*\*\param RTC_Output : RTC_Output Specifies which signal will be routed to the RTC output. +*\*\ - RTC_OUTPUT_DIS : No output selected +*\*\ - RTC_OUTPUT_ALA : signal of AlarmA mapped to output. +*\*\ - RTC_OUTPUT_ALB : signal of AlarmB mapped to output. +*\*\ - RTC_OUTPUT_WKUP: signal of WakeUp mapped to output. +*\*\param RTC_OutputPolarity : Specifies the polarity of the output signal. +*\*\ - RTC_OUTPOL_HIGH: The output pin is high when the ALRAF/ALRBF/WUTF is high (depending on OSEL). +*\*\ - RTC_OUTPOL_LOW : The output pin is low when the ALRAF/ALRBF/WUTF is high (depending on OSEL). +*\*\return none +**/ +void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + __IO uint32_t temp = 0; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the bits to be configured */ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_OUTSEL | RTC_CTRL_OPOL); + + /* Configure the output selection and polarity */ + RTC->CTRL |= (uint32_t)(RTC_Output | RTC_OutputPolarity); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_EnableTampOutput +*\*\fun Enable or disable the RTC tamper output . +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableTampOutput(FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the RTC tamper output */ + RTC->CTRL |= (uint32_t)RTC_CTRL_TAMPOE; + } + else + { + /* Disable the RTC tamper output */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_TAMPOE; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_EnableCalibOutput +*\*\fun Enable or disable the RTC calibration clock to be output through the relative pin. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableCalibOutput(FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the RTC clock output */ + RTC->CTRL |= (uint32_t)RTC_CTRL_COEN; + } + else + { + /* Disable the RTC clock output */ + RTC->CTRL &= (uint32_t)~RTC_CTRL_COEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigCalibOutput +*\*\fun Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 256Hz). +*\*\param RTC_CalibOutput Select the Calibration output Selection . +*\*\ - RTC_CALIB_OUTPUT_256HZ : A signal has a regular waveform at 256Hz. +*\*\ - RTC_CALIB_OUTPUT_1HZ : A signal has a regular waveform at 1Hz. +*\*\return none +**/ +void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /*clear flags before config*/ + RTC->CTRL &= (uint32_t) ~(RTC_CTRL_CALOSEL); + + /* Configure the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)RTC_CalibOutput; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigSmoothCalib +*\*\fun Configures the Smooth Calibration Settings. +*\*\param RTC_SmoothCalibPeriod : RTC_SmoothCalibPeriod Select the Smooth Calibration Period. +*\*\ - SMOOTH_CALIB_32SEC : The smooth calibration periode is 32s. +*\*\ - SMOOTH_CALIB_16SEC : The smooth calibration periode is 16s. +*\*\ - SMOOTH_CALIB_8SEC : The smooth calibartion periode is 8s. +*\*\param RTC_SmoothCalibPlusPulses : Set or reset the CALP bit. +*\*\ - RTC_SMOOTH_CALIB_PLUS_PULSES_SET : Add one RTCCLK puls every 2**11 pulses. +*\*\ - RTC_SMOOTH_CALIB_PLUS_PULSES_RESET : No RTCCLK pulses are added. +*\*\param RTC_SmouthCalibMinusPulsesValue : Set the value of CALM[8:0] bits, the value in the 0-0x000001FF range +*\*\return ErrorStatus +*\*\ - SUCCESS : RTC Calib registers are configured +*\*\ - ERROR : RTC Calib registers are not configured +**/ +ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue) +{ + ErrorStatus status; + uint32_t recalpfcount = 0; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* check if a calibration is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_RECPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_RECPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALIB = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses + | (uint32_t)RTC_SmouthCalibMinusPulsesValue); + + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + +/** +*\*\name RTC_EnableInterEventTimeStamp +*\*\fun Enables or disables the RTC internal event trigger TimeStamp functionality. + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableInterEventTimeStamp(FunctionalState Cmd) +{ + uint32_t tmpregister; + + /* Get the RTC_CTRL register and clear the bits to be configured */ + tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_IETSEN)); + + /* Get the new configuration */ + if (Cmd != DISABLE) + { + tmpregister |= (uint32_t)(RTC_CTRL_IETSEN); + } + else + { + tmpregister &= ~(uint32_t)(RTC_CTRL_IETSEN); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CTRL = (uint32_t)tmpregister; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_EnableTimeStamp +*\*\fun Enables or disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge. +*\*\param RTC_TimeStampEdge : Specifies the pin edge on which the TimeStamp is activated. +*\*\ - RTC_TIMESTAMP_EDGE_RISING : the Time stamp event occurs on the rising edge of the related pin. +*\*\ - RTC_TIMESTAMP_EDGE_FALLING : the Time stamp event occurs on the falling edge of the related pin. + *\*\param Cmd : + *\*\ - ENABLE + *\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd) +{ + uint32_t tmpregister; + + /* Get the RTC_CTRL register and clear the bits to be configured */ + tmpregister = (uint32_t)(RTC->CTRL & (uint32_t) ~(RTC_CTRL_TEDGE | RTC_CTRL_TSEN)); + + /* Get the new configuration */ + if (Cmd != DISABLE) + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge | RTC_CTRL_TSEN); + } + else + { + tmpregister |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CTRL = (uint32_t)tmpregister; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_GetTimeStamp +*\*\fun Get the RTC TimeStamp value and masks. +*\*\param RTC_Format : specifies the format of the output parameters. +*\*\ - RTC_FORMAT_BIN : Binary data format +*\*\ - RTC_FORMAT_BCD : BCD data format +*\*\param RTC_StampTimeStruct : pointer to a RTC_TimeType structure that will +*\*\ contains the TimeStamp time values. +*\*\param RTC_StampDateStruct : pointer to a RTC_DateType structure that will +*\*\ contains the TimeStamp date values. +*\*\return none +**/ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct) +{ + uint32_t tmptime, tmpdate; + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->Hours = (uint8_t)((tmptime & (RTC_TST_HOT | RTC_TST_HOU)) >> 16); + RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TST_MIT | RTC_TST_MIU)) >> 8); + RTC_StampTimeStruct->Seconds = (uint8_t)(tmptime & (RTC_TST_SET | RTC_TST_SEU)); + RTC_StampTimeStruct->H12 = (uint8_t)((tmptime & (RTC_TST_APM)) >> 16); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->Month = (uint8_t)((tmpdate & (RTC_DATE_MOT | RTC_DATE_MOU)) >> 8); + RTC_StampDateStruct->Date = (uint8_t)(tmpdate & (RTC_DATE_DAT | RTC_DATE_DAU)); + RTC_StampDateStruct->WeekDay = (uint8_t)((tmpdate & (RTC_DATE_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_FORMAT_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Hours); + RTC_StampTimeStruct->Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Minutes); + RTC_StampTimeStruct->Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Month); + RTC_StampDateStruct->Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->Date); + RTC_StampDateStruct->WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->WeekDay); + } +} + +/** +*\*\name RTC_GetTimeStampSubSecond +*\*\fun Get the RTC timestamp Subseconds value. +*\*\param none +*\*\return RTC current timestamp Subseconds value. +**/ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSS); +} + + +/** +*\*\name RTC_ConfigOutputType +*\*\fun Configures the RTC Output Pin mode. +*\*\param RTC_OutputType : specifies the RTC Output (PC13) pin mode. +*\*\ - RTC_OUTPUT_OPENDRAIN : RTC Output (PC13) is configured in Open Drain mode. +*\*\ - RTC_OUTPUT_PUSHPULL : RTC Output (PC13) is configured in Push Pull mode. +*\*\return none +**/ +void RTC_ConfigOutputType(uint32_t RTC_OutputType) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + RTC->OPT &= (uint32_t) ~(RTC_OPT_TYPE); + RTC->OPT |= (uint32_t)(RTC_OutputType); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigPWREvtSig +*\*\fun Configures the RTC PWR event signal type. +*\*\param signal_type : +*\*\ - RTC_PWR_SIGNAL_PULSE +*\*\ - RTC_PWR_SIGNAL_LEVEL +*\*\return none +**/ +void RTC_ConfigPWREvtSig(uint32_t signal_type) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + RTC->OPT &= (uint32_t) ~(RTC_OPT_PWREST); + + RTC->OPT |= (uint32_t)(signal_type); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigOutputPullUp +*\*\fun Configures the RTC Output PullUp . +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_ConfigOutputPullUp(FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + RTC->OPT &= (uint32_t) ~(RTC_OPT_OUTPU); + + if(Cmd != DISABLE) + { + RTC->OPT |= (uint32_t)(RTC_OPT_OUTPU); + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_EnableOutput2 +*\*\fun Enable or disable the RTC output2 . +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableOutput2(FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Enable the RTC output2 */ + RTC->OPT |= (uint32_t)RTC_OPT_OUTMAP; + } + else + { + /* Disable the RTC output2 */ + RTC->OPT &= (uint32_t)~RTC_OPT_OUTMAP; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_ConfigOutputDuty +*\*\fun Configures the RTC Output duty cycle. +*\*\param Cmd : +*\*\ - RTC_Output_Duty_50 +*\*\ - RTC_Output_Duty_DIV +*\*\return none +**/ +void RTC_ConfigOutputDuty(uint32_t duty_cycle) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + RTC->OPT &= (uint32_t) ~(RTC_Output_Duty_DIV); + + RTC->OPT |= (uint32_t)(duty_cycle); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + + +/** +*\*\name RTC_ConfigSynchroShift +*\*\fun Configures the Synchronization Shift Control Settings. +*\*\param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. +*\*\ - RTC_SHIFT_SUB1S_DISABLE : Add one second to the clock calendar. +*\*\ - RTC_SHIFT_SUB1S_ENABLE : No effect. +*\*\param RTC_ShiftSubFS : Select the number of Second Fractions to Substitute. +*\*\ This parameter can be one any value from 0 to 0x7FFF. +*\*\return ErrorStatus : +*\*\ - SUCCESS : RTC Shift registers are configured +*\*\ - ERROR : RTC Shift registers are not configured +**/ +ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status; + uint32_t shpfcount = 0; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Check if a Shift is pending*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->INITSTS & RTC_INITSTS_SHOPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->INITSTS & RTC_INITSTS_SHOPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if ((RTC->CTRL & RTC_CTRL_REFCLKEN) == RESET) + { + /* Configure the Shift settings */ + RTC->SCTRL = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + else + { + status = ERROR; + } + } + else + { + status = ERROR; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + + return (ErrorStatus)(status); +} + + +/** +*\*\name RTC_ConfigInt +*\*\fun Enables or disables the specified RTC interrupts. +*\*\param RTC_INT : specifies the RTC interrupt sources to be enabled . +*\*\ - RTC_INT_TS : TimeStamp interrupt mask. +*\*\ - RTC_INT_WUT : WakeUp Timer interrupt mask. +*\*\ - RTC_INT_ALRB : Alarm B interrupt mask. +*\*\ - RTC_INT_ALRA : Alarm A interrupt mask. +*\*\ - RTC_INT_CAOV : Calendar overflow interrupt mask. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (Cmd != DISABLE) + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL |= (uint32_t)RTC_INT; + } + else + { + /* Configure the Interrupts in the RTC_CTRL register */ + RTC->CTRL &= (uint32_t) ~(RTC_INT); + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_GetFlagStatus +*\*\fun Checks whether the specified RTC flag is set or not. +*\*\param RTC_FLAG : specifies the flag to check. +*\*\ - RTC_FLAG_BPRAM_ERFRF : BKP_SRAM erase operation is in progress flag +*\*\ - RTC_FLAG_ITISF : Internal Time Stamp event flag. +*\*\ - RTC_FLAG_CALOVF : Calendar Overflow flag. +*\*\ - RTC_FLAG_TAMP8F : Tamp8 detect flag. +*\*\ - RTC_FLAG_TAMP7F : Tamp7 detect flag. +*\*\ - RTC_FLAG_TAMP6F : Tamp6 detect flag. +*\*\ - RTC_FLAG_TAMP5F : Tamp5 detect flag. +*\*\ - RTC_FLAG_TAMP4F : Tamp4 detect flag. +*\*\ - RTC_FLAG_RECPF : RECALPF event flag. +*\*\ - RTC_FLAG_TAMP3F : Tamp3 detect flag. +*\*\ - RTC_FLAG_TAMP2F : Tamp2 detect flag. +*\*\ - RTC_FLAG_TAMP1F : Tamp1 detect flag. +*\*\ - RTC_FLAG_TISOVF : Time Stamp OverFlow flag. +*\*\ - RTC_FLAG_TISF : Time Stamp event flag. +*\*\ - RTC_FLAG_WTF : WakeUp Timer flag. +*\*\ - RTC_FLAG_ALBF : Alarm B flag. +*\*\ - RTC_FLAG_ALAF : Alarm A flag. +*\*\ - RTC_FLAG_INITF : Initialization mode flag. +*\*\ - RTC_FLAG_RSYF : Registers Synchronized flag. +*\*\ - RTC_FLAG_INITSF : Registers Configured flag. +*\*\ - RTC_FLAG_SHOPF : Shift operation pending flag. +*\*\ - RTC_FLAG_WTWF : WakeUp Timer Write flag. +*\*\ - RTC_FLAG_ALBWF : Alarm B Write flag. +*\*\ - RTC_FLAG_ALAWF : Alarm A write flag. +*\*\return FlagStatus +*\*\ - SET : the flag is set +*\*\ - RESET : the flag is reset +**/ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus; + uint32_t tmpregister; + + /* Get all the flags */ + tmpregister = (uint32_t)(RTC->INITSTS & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + if ((tmpregister & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RTC_ClrFlag +*\*\fun Clears the RTC's flags. +*\*\param RTC_FLAG : RTC_FLAG specifies the RTC flag to clear. +*\*\ - RTC_FLAG_ITISF : Internal Time Stamp event flag. +*\*\ - RTC_FLAG_CALOVF : Calendar Overflow flag. +*\*\ - RTC_FLAG_TAMP8F : Tamp8 detect flag. +*\*\ - RTC_FLAG_TAMP7F : Tamp7 detect flag. +*\*\ - RTC_FLAG_TAMP6F : Tamp6 detect flag. +*\*\ - RTC_FLAG_TAMP5F : Tamp5 detect flag. +*\*\ - RTC_FLAG_TAMP4F : Tamp4 detect flag. +*\*\ - RTC_FLAG_TAMP3F : Tamp3 detect flag. +*\*\ - RTC_FLAG_TAMP2F : Tamp2 detect flag. +*\*\ - RTC_FLAG_TAMP1F : Tamp1 detect flag. +*\*\ - RTC_FLAG_TISOVF : Time Stamp Overflow flag. +*\*\ - RTC_FLAG_TISF : Time Stamp event flag. +*\*\ - RTC_FLAG_WTF : WakeUp Timer flag +*\*\ - RTC_FLAG_ALBF : Alarm B flag. +*\*\ - RTC_FLAG_ALAF : Alarm A flag. +*\*\ - RTC_FLAG_RSYF : Registers Synchronized flag. +*\*\return none +**/ +void RTC_ClrFlag(uint32_t RTC_FLAG) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear the Flags in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_INITSTS_INITM) & (uint32_t)0x00FFFFFF) | + (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_GetITStatus +*\*\fun Checks whether the specified RTC interrupt has occurred or not. +*\*\param RTC_INT : specifies the RTC interrupt source to check. +*\*\ - RTC_INT_CAOV : Calendar overflow interrupt. +*\*\ - RTC_INT_TAMP8 : Tamper8 interrupt. +*\*\ - RTC_INT_TAMP7 : Tamper7 interrupt. +*\*\ - RTC_INT_TAMP6 : Tamper6 interrupt. +*\*\ - RTC_INT_TAMP5 : Tamper5 interrupt. +*\*\ - RTC_INT_TAMP4 : Tamper4 interrupt. +*\*\ - RTC_INT_TAMP3 : Tamper3 interrupt. +*\*\ - RTC_INT_TAMP2 : Tamper2 interrupt. +*\*\ - RTC_INT_TAMP1 : Tamper1 interrupt. +*\*\ - RTC_INT_TS : Timestamp interrupt. +*\*\ - RTC_INT_WUT : WakeUp Timer interrupt. +*\*\ - RTC_INT_ALRB : Alarm B interrupt. +*\*\ - RTC_INT_ALRA : Alarm A interrupt. +*\*\return INTStatus +*\*\ - SET : the flag is set +*\*\ - RESET : the flag is reset +**/ +INTStatus RTC_GetITStatus(uint32_t RTC_INT) +{ + INTStatus bitstatus; + uint32_t tmpregister, enablestatus = 0; + uint32_t tamperEnable; + uint32_t tampernum; + uint8_t i; + + /* Get the Interrupt enable Status */ + if ((RTC_INT == RTC_INT_TAMP1) || (RTC_INT == RTC_INT_TAMP2) || (RTC_INT == RTC_INT_TAMP3) || + (RTC_INT == RTC_INT_TAMP4) || (RTC_INT == RTC_INT_TAMP5) || (RTC_INT == RTC_INT_TAMP6) || + (RTC_INT == RTC_INT_TAMP7) || (RTC_INT == RTC_INT_TAMP8)) + { + for(i = 0; i < 9; i++) + { + if((RTC_INT >> (i + 17)) & (uint32_t)0x01) + { + if(i < 3) + { + tampernum = i; + break; + } + else if(i > 3) + { + tampernum = i - 1; + break; + } + } + } + + tamperEnable = RTC->TMPCTRL[tampernum] & RTC_TMPCTRL_TPINTEN; + + if (tamperEnable != (uint32_t)RESET) + { + enablestatus = (uint32_t)0x00000001; + } + } + else + { + enablestatus = (uint32_t)((RTC->CTRL & RTC_INT)); + } + + if(RTC_INT == RTC_INT_CAOV) + { + /* Get the Interrupt pending bit */ + tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 5))); + } + else + { + /* Get the Interrupt pending bit */ + tmpregister = (uint32_t)((RTC->INITSTS & (uint32_t)(RTC_INT >> 4))); + } + + /* Get the status of the Interrupt */ + if ((enablestatus != (uint32_t)RESET) && ((tmpregister & (uint32_t)0x001FFFFF) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name RTC_ClrIntPendingBit +*\*\fun Clears the RTC's interrupt pending bits. +*\*\param RTC_INT : specifies the RTC interrupt pending bit to clear. +*\*\ - RTC_INT_CAOV : Calendar overflow interrupt. +*\*\ - RTC_INT_TAMP8 : Tamper8 interrupt. +*\*\ - RTC_INT_TAMP7 : Tamper7 interrupt. +*\*\ - RTC_INT_TAMP6 : Tamper6 interrupt. +*\*\ - RTC_INT_TAMP5 : Tamper5 interrupt. +*\*\ - RTC_INT_TAMP4 : Tamper4 interrupt. +*\*\ - RTC_INT_TAMP3 : Tamper3 interrupt. +*\*\ - RTC_INT_TAMP2 : Tamper2 interrupt. +*\*\ - RTC_INT_TAMP1 : Tamper1 interrupt. +*\*\ - RTC_INT_TS : Timestamp interrupt. +*\*\ - RTC_INT_WUT : WakeUp Timer interrupt +*\*\ - RTC_INT_ALRB : Alarm B interrupt +*\*\ - RTC_INT_ALRA : Alarm A interrupt +*\*\return none +**/ +void RTC_ClrIntPendingBit(uint32_t RTC_INT) +{ + uint32_t tmpregister; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Get the RTC_INITSTS Interrupt pending bits mask */ + tmpregister = (uint32_t)(RTC_INT >> 4); + + /* Clear the interrupt pending bits in the RTC_INITSTS register */ + RTC->INITSTS = (uint32_t)((uint32_t)(~((tmpregister | RTC_INITSTS_INITM) & (uint32_t)0x01FFFFFF) | + (uint32_t)(RTC->INITSTS & RTC_INITSTS_INITM))); + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_TamperTriggerConfig +*\*\fun Configures the select Tamper pin edge. +*\*\param RTC_Tamper: Selected tamper pin. +*\*\ - RTC_TAMPER_1: Select Tamper 1. +*\*\ - RTC_TAMPER_2: Select Tamper 2. +*\*\ - RTC_TAMPER_3: Select Tamper 3. +*\*\ - RTC_TAMPER_4: Select Tamper 4. +*\*\ - RTC_TAMPER_5: Select Tamper 5. +*\*\ - RTC_TAMPER_6: Select Tamper 6. +*\*\ - RTC_TAMPER_7: Select Tamper 7. +*\*\ - RTC_TAMPER_8: Select Tamper 8. +*\*\param RTC_TamperTrigger: Specifies the trigger on the tamper pin that stimulates tamper event. +*\*\ - RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. +*\*\ - RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. +*\*\ - RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. +*\*\ - RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. +*\*\return none +**/ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + uint32_t tmaper_trigger = RTC_TamperTrigger; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + RTC->TMPCTRL[RTC_Tamper] &= (uint32_t)(~RTC_TMPCTRL_TPTRG); + + /* Configure the RTC_TAMPCTRL register */ + RTC->TMPCTRL[RTC_Tamper] |= tmaper_trigger; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; + +} + +/** +*\*\name RTC_TamperCmd +*\*\fun Enables or disables the specified Tamper detection. +*\*\param RTC_Tamper: Selected tamper pin. +*\*\ - RTC_TAMPER_1: Select Tamper 1. +*\*\ - RTC_TAMPER_2: Select Tamper 2. +*\*\ - RTC_TAMPER_3: Select Tamper 3. +*\*\ - RTC_TAMPER_4: Select Tamper 4. +*\*\ - RTC_TAMPER_5: Select Tamper 5. +*\*\ - RTC_TAMPER_6: Select Tamper 6. +*\*\ - RTC_TAMPER_7: Select Tamper 7. +*\*\ - RTC_TAMPER_8: Select Tamper 8. +*\*\param NewState : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCTRL[RTC_Tamper] |= (uint32_t)RTC_TMPCTRL_TPEN; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCTRL[RTC_Tamper] &= (uint32_t)~RTC_TMPCTRL_TPEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_TamperFilterConfig +*\*\fun Configures the Tampers Filter. +*\*\param RTC_TamperFilter: Selected tamper pin. +*\*\ - RTC_TamperFilter_Disable: Tamper filter is disabled. +*\*\ - RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive samples at the active level. +*\*\ - RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive samples at the active level. +*\*\ - RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive samples at the active level. +*\*\return none +**/ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear TAMPFLT[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPFLT); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperFilter; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_TamperSamplingFreqConfig +*\*\fun Configures the Tampers Sampling Frequency. +*\*\param RTC_TamperSamplingFreq: Selected tamper pin. +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div32768 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div16384 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div8192 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div4096 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div2048 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div1024 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div512 +*\*\ - RTC_TamperSamplingFreq_RTCCLK_Div256 +*\*\return none +**/ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TAMPCR_TAMPFREQ); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperSamplingFreq; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_TamperPinsPrechargeDuration +*\*\fun Configures the Tampers Pins input Precharge Duration. +*\*\param RTC_TamperPrechargeDuration: Selected tamper pin. +*\*\ - RTC_TamperPrechargeDuration_1RTCCLK +*\*\ - RTC_TamperPrechargeDuration_2RTCCLK +*\*\ - RTC_TamperPrechargeDuration_4RTCCLK +*\*\ - RTC_TamperPrechargeDuration_8RTCCLK +*\*\return none +**/ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAMPCR register */ + RTC->TMPCFG &= (uint32_t)~(RTC_TMPCFG_TPPRCH); + + /* Configure the RTC_TAMPCR register */ + RTC->TMPCFG |= (uint32_t)RTC_TamperPrechargeDuration; + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + + +/** +*\*\name RTC_TimeStampOnTamperDetectionCmd +*\*\fun The timestamp is valid or invalid even the TSEN bit in tamper control register is reset. +*\*\param NewState : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPTS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_TamperPullUpCmd +*\*\fun Enables or disables the Precharge of Tamper pin. +*\*\param NewState : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + RTC->TMPCFG &= (uint32_t)~RTC_TMPCFG_TPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + RTC->TMPCFG |= (uint32_t)RTC_TMPCFG_TPPUDIS; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_EnableTampErase +*\*\fun Enables or disables the tamper event erase backup register. +*\*\param RTC_Tamper: Selected tamper event. +*\*\ - RTC_TAMPER_1: Select Tamper 1 erase backup register. +*\*\ - RTC_TAMPER_2: Select Tamper 2 erase backup register. +*\*\ - RTC_TAMPER_3: Select Tamper 3 erase backup register. +*\*\ - RTC_TAMPER_4: Select Tamper 4 erase backup register. +*\*\ - RTC_TAMPER_5: Select Tamper 5 erase backup register. +*\*\ - RTC_TAMPER_6: Select Tamper 6 erase backup register. +*\*\ - RTC_TAMPER_7: Select Tamper 7 erase backup register. +*\*\ - RTC_TAMPER_8: Select Tamper 8 erase backup register. +*\*\param NewState : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_EnableTampErase(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (NewState != DISABLE) + { + /* Enable tamper event erase backup register */ + RTC->TMPCTRL[RTC_Tamper] &= (uint32_t)~RTC_TMPCTRL_TPNOE; + } + else + { + /* Disable tamper event erase backup register */ + RTC->TMPCTRL[RTC_Tamper] |= (uint32_t)RTC_TMPCTRL_TPNOE; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_TamperAllIECmd +*\*\fun Enables or disables all Tamper interrupt. +*\*\param RTC_Tamper: Selected tamper pin. +*\*\ - RTC_TAMPER_1: Select Tamper 1. +*\*\ - RTC_TAMPER_2: Select Tamper 2. +*\*\ - RTC_TAMPER_3: Select Tamper 3. +*\*\ - RTC_TAMPER_4: Select Tamper 4. +*\*\ - RTC_TAMPER_5: Select Tamper 5. +*\*\ - RTC_TAMPER_6: Select Tamper 6. +*\*\ - RTC_TAMPER_7: Select Tamper 7. +*\*\ - RTC_TAMPER_8: Select Tamper 8. +*\*\param NewState : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_TamperMskCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (NewState != DISABLE) + { + /* Enable the selected Tamper mask */ + RTC->TMPCTRL[RTC_Tamper] |= (uint32_t)RTC_TMPCTRL_TPMF; + } + else + { + /* Disable the selected Tamper mask */ + RTC->TMPCTRL[RTC_Tamper] &= (uint32_t)~RTC_TMPCTRL_TPMF; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + + +/** +*\*\name RTC_TamperIECmd +*\*\fun Enables or disables the Tamper interrupt. +*\*\param RTC_Tamper: Selected tamper pin. +*\*\ - RTC_TAMPER_1: Select Tamper 1. +*\*\ - RTC_TAMPER_2: Select Tamper 2. +*\*\ - RTC_TAMPER_3: Select Tamper 3. +*\*\ - RTC_TAMPER_4: Select Tamper 4. +*\*\ - RTC_TAMPER_5: Select Tamper 5. +*\*\ - RTC_TAMPER_6: Select Tamper 6. +*\*\ - RTC_TAMPER_7: Select Tamper 7. +*\*\ - RTC_TAMPER_8: Select Tamper 8. +*\*\param NewState : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void RTC_TamperIECmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + if (NewState != DISABLE) + { + /* Enable the selected Tamper pin */ + RTC->TMPCTRL[RTC_Tamper] |= (uint32_t)RTC_TMPCTRL_TPINTEN; + } + else + { + /* Disable the selected Tamper pin */ + RTC->TMPCTRL[RTC_Tamper] &= (uint32_t)~RTC_TMPCTRL_TPINTEN; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_BKUPRgWrite +*\*\fun Write data to backup register. +*\*\param register_num: register_num value can be from 1 to 32 +*\*\param Data : Data write to backup register +*\*\return none +**/ +void RTC_BKUPRgWrite(uint8_t register_num, uint32_t Data) +{ + uint32_t tmpregister; + + /* Disable the write protection for RTC registers */ + RTC->WRP = 0xCA; + RTC->WRP = 0x53; + + tmpregister = (uint32_t) & (RTC->BKP1); + + if(register_num > 0 && register_num <= 32) + { + tmpregister += (((uint32_t)register_num - 1) * 4); + /* Write data to specified register */ + *(__IO uint32_t *)tmpregister = Data; + } + + /* Enable the write protection for RTC registers */ + RTC->WRP = 0xFF; +} + +/** +*\*\name RTC_BKUPRgRead +*\*\fun Read data from backup register. +*\*\param register_num: register_num value can be from 1 to 32 +*\*\param Data : Data write to backup register +*\*\return none +**/ +uint32_t RTC_BKUPRgRead(uint8_t register_num) +{ + uint32_t tmpregister, value = 0; + + tmpregister = (uint32_t) & (RTC->BKP1); + + if(register_num > 0 && register_num <= 32) + { + tmpregister += (((uint32_t)register_num - 1) * 4); + value = *(__IO uint32_t *)tmpregister; + } + + return value; +} + +/** +*\*\name RTC_ByteToBcd2 +*\*\fun Converts a 2 digit decimal to BCD format. +*\*\param value : Value Byte to be converted. +*\*\return Converted byte +**/ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + uint8_t temp_value = Value; + + while (temp_value >= 10) + { + bcdhigh++; + temp_value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | temp_value); +} + +/** +*\*\name RTC_Bcd2ToByte +*\*\fun Convert from 2 digit BCD to Binary. +*\*\param Value : Value BCD value to be converted. +*\*\return Converted byte +**/ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdmmc.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdmmc.c new file mode 100644 index 0000000000..191cbd9ca7 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdmmc.c @@ -0,0 +1,2879 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_sdmmc.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_sdmmc.h" +#include "n32h76x_78x_rcc.h" + +/** + *\*\name SDMMC_DeInit. + *\*\fun Reset the SDMMCx peripheral registers to their default reset values. + *\*\param SDMMCx : + *\*\ - SDMMC1 + *\*\ - SDMMC2 + *\*\return none + */ +void SDMMC_DeInit(SDMMC_Module* SDMMCx) +{ + if (SDMMCx == SDMMC1) + { + RCC_EnableAXIPeriphReset1(RCC_AXI_PERIPHRST_SDMMC1); + RCC_EnableAXIPeriphReset1(RCC_AXI_PERIPHRST_SDHOST1); + } + else if (SDMMCx == SDMMC2) + { + RCC_EnableAHB1PeriphReset1(RCC_AHB1_PERIPHRST_SDMMC2); + RCC_EnableAHB1PeriphReset1(RCC_AHB1_PERIPHRST_SDHOST2); + } + else + { + /* no process */ + } +} + + +/** + *\*\name SDMMC_WrapperConfig. + *\*\fun Initializes the SDMMC peripheral according to the specified + *\*\ parameters in the SDMMC_WrapperParam. + *\*\fun Configure SDMMC wrapper register values. + *\*\param SDMMCx pointer to specified SDMMC,must be one of the following value: + *\*\ - SDMMC1 + *\*\ - SDMMC2 + *\*\param SDMMC_WrapperParam: pointer to a SDMMC_WrapperType structure. + *\*\ - MaxBlockLen : Maximum Block Length supported by the Core/Device + *\*\ - SDMMC_MAXBLOCKLEN_512B + *\*\ - SDMMC_MAXBLOCKLEN_1024B + *\*\ - SDMMC_MAXBLOCKLEN_2048B + *\*\ - SDBaseCLKFreq : xin_clk, Base Clock Frequency for SD Clock + *\*\ - 0x0A~0x68,Unit MHz + *\*\ - TimeOutUnit : the unit of base clock frequency used to detect Data Timeout Error + *\*\ - SDMMC_TIMEOUTCLKUNIT_KHZ + *\*\ - SDMMC_TIMEOUTCLKUNIT_MHZ + *\*\ - TuningCNT : the number of delay taps that are supported for tuning the rxclk_in + *\*\ - 0x00~0x20 + *\*\ - WKUPSignalMode : Wakeup Signal Generation Mode + *\*\ - SDMMC_SYNCWKUP + *\*\ - SDMMC_ASYNCWKUP + *\*\ - SPIBlockMode : SPI Block Mode + *\*\ - SDMMC_SPIBLOCKMODESUPPORT + *\*\ - SDMMC_SPIBLOCKMODEUNSUPPORT + *\*\ - SPIMode : SPI Mode Support + *\*\ - SDMMC_SPIMODESUPPORT + *\*\ - SDMMC_SPIMODEUNSUPPORT + *\*\ - DDR50 : DDR50 Support + *\*\ - SDMMC_DDR50SUPPORT + *\*\ - SDMMC_DDR50UNSUPPORT + *\*\ - SDR104 : SDR104 Support + *\*\ - SDMMC_SDR104SUPPORT + *\*\ - SDMMC_SDR104UNSUPPORT + *\*\ - SDR50 : SDR50 Support + *\*\ - SDMMC_SDR50SUPPORT + *\*\ - SDMMC_SDR50UNSUPPORT + *\*\ - SlotType : Slot Type + *\*\ - SDMMC_SDTYPE + *\*\ - SDMMC_EMMCTYPE + *\*\ - AsyncInt : Asynchronous Interrupt Support + *\*\ - SDMMC_ASYNCINTSUPPORT + *\*\ - SDMMC_ASYNCINTUNSUPPORT + *\*\ - Suspend_Resume : Suspend/Resume Support + *\*\ - SDMMC_SUSRESSUPPORT + *\*\ - SDMMC_SUSRESUNSUPPORT + *\*\ - SDMA : SDMA Support + *\*\ - SDMMC_SDMASUPPORT + *\*\ - SDMMC_SDMAUNSUPPORT + *\*\ - HS : High Speed Support + *\*\ - SDMMC_HSSUPPORT + *\*\ - SDMMC_HSUNSUPPORT + *\*\ - ADMA2 : ADMA2 Support + *\*\ - SDMMC_ADMA2SUPPORT + *\*\ - SDMMC_ADMA2UNSUPPORT + *\*\ - Embedded_8bit : 8-bit Support for Embedded Device + *\*\ - SDMMC_EMBEDDEDSUPPORT + *\*\ - SDMMC_EMBEDDEDUNSUPPORT + *\*\ - UseTuningSDR50 : Use Tuning for SDR50 + *\*\ - SDMMC_SDR50TUNING + *\*\ - SDMMC_SDR50UNTUNING + *\*\ - DSSDCLKFreq : SDCLK Frequency Select Value for Default Speed + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - INITSDCLKFreq :SDCLK Frequency Select Value for Initialization + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR12SDCLKFreq : SDCLK Frequency Select Value for SDR12 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - HSSDCLKFreq : SDCLK Frequency Select Value for High Speed + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR50SDCLKFreq : SDCLK Frequency Select Value for SDR50 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR25SDCLKFreq : SDCLK Frequency Select Value for SDR25 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR104SDCLKFreq : SDCLK Frequency Select Value for SDR104 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - DDR50SDCLKFreq : SDCLK Frequency Select Value for DDR50 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + *\*\note This function can only be used when SDMMC is not working. + *\* Call configuration support function before SD initialization. + */ +ErrorStatus SDMMC_WrapperConfig(SDMMC_Module* SDMMCx, SDMMC_WrapperType *SDMMC_WrapperParam) +{ + uint32_t tempReg; + SDHOST_Module* SDHOSTx; + + if(SDMMCx == SDMMC1) + { + SDHOSTx = SDHOST1; + } + else + { + SDHOSTx = SDHOST2; + } + + /* The SDMMC registers can only be configured when SDMMC is not operational */ + if((SDHOSTx->PRESTS & (SDHOST_PRESTS_RTRANACT | SDHOST_PRESTS_WTRANACT)) != RESET) + { + return ERROR; + } + + /* Configure SDMMC_CFG1, including block length, xin_clk size,Timeout Clock Unit, + Tuning Count, Wakeup Signal Generation Mode */ + tempReg = SDMMCx->CFG1; + tempReg &= (~(SDMMC_CFG1_MBL | SDMMC_CFG1_BCLKF | SDMMC_CFG1_TCLKU | SDMMC_CFG1_TCNT | SDMMC_CFG1_WSGM)); + tempReg |= (SDMMC_WrapperParam->MaxBlockLen | (SDMMC_WrapperParam->SDBaseCLKFreq << SDMMC_CFG1_BCLKF_OFFSET) | SDMMC_WrapperParam->TimeOutUnit \ + | (SDMMC_WrapperParam->TuningCNT << SDMMC_CFG1_TCNT_OFFSET) | SDMMC_WrapperParam->WKUPSignalMode); + SDMMCx->CFG1 = tempReg; + + /* Configure SDMMC_CFG2, including SPI block mode, SPI mode,DDR50,SDR104,SDR50,Slot Type, + Asynchronous Interrupt,Suspend/Resume Support,SDMA,HS,ADMA2,8-bit Support for Embedded Device */ + tempReg = SDMMCx->CFG2; + tempReg &= (~(SDMMC_CFG2_SPIBMOD | SDMMC_CFG2_SPIMOD | SDMMC_CFG2_DDR50 | SDMMC_CFG2_SDR104 | SDMMC_CFG2_SDR50 \ + | SDMMC_CFG2_STYP | SDMMC_CFG2_ASYNCINT | SDMMC_CFG2_SDMA | SDMMC_CFG2_HS | SDMMC_CFG2_ADMA2 | SDMMC_CFG2_EMBUS)); + tempReg |= (SDMMC_WrapperParam->SPIBlockMode | SDMMC_WrapperParam->SPIMode | SDMMC_WrapperParam->DDR50 \ + | SDMMC_WrapperParam->SDR104 | SDMMC_WrapperParam->SDR50 | SDMMC_WrapperParam->SlotType \ + | SDMMC_WrapperParam->AsyncInt | SDMMC_WrapperParam->Suspend_Resume | SDMMC_WrapperParam->SDMA \ + | SDMMC_WrapperParam->HS | SDMMC_WrapperParam->ADMA2 | SDMMC_WrapperParam->Embedded_8bit); + SDMMCx->CFG2 = tempReg; + + /* Configure SDMMC_CFG3, including Use Tuning for SDR50 */ + tempReg = SDMMCx->CFG3; + tempReg &= (~SDMMC_CFG3_UTFSDR50); + tempReg |= SDMMC_WrapperParam->UseTuningSDR50; + SDMMCx->CFG3 = tempReg; + + /* Configure SDMMC_PV0CTRL, including SDCLK Frequency Select Value for Default Speed and Initialization */ + tempReg = SDMMCx->PV0CTRL; + tempReg &= (~(SDMMC_PV0CTRL_CLKFS_DS | SDMMC_PV0CTRL_CLKFS_INIT)); + tempReg |= ((SDMMC_WrapperParam->DSSDCLKFreq << SDMMC_PV0CTRL_CLKFS_OFFSET) | SDMMC_WrapperParam->INITSDCLKFreq); + SDMMCx->PV0CTRL = tempReg; + + /* Configure SDMMC_PV1CTRL, including SDCLK Frequency Select Value for SDR12 and HS */ + tempReg = SDMMCx->PV1CTRL; + tempReg &= (~(SDMMC_PV1CTRL_CLKFS_SDR12 | SDMMC_PV1CTRL_CLKFS_HS)); + tempReg |= ((SDMMC_WrapperParam->SDR12SDCLKFreq << SDMMC_PV0CTRL_CLKFS_OFFSET) | SDMMC_WrapperParam->HSSDCLKFreq); + SDMMCx->PV1CTRL = tempReg; + + /* Configure SDMMC_PV2CTRL, including SDCLK Frequency Select Value for SDR50 and SDR25 */ + tempReg = SDMMCx->PV2CTRL; + tempReg &= (~(SDMMC_PV2CTRL_CLKFS_SDR50 | SDMMC_PV2CTRL_CLKFS_SDR25)); + tempReg |= ((SDMMC_WrapperParam->SDR50SDCLKFreq << SDMMC_PV0CTRL_CLKFS_OFFSET) | SDMMC_WrapperParam->SDR25SDCLKFreq); + SDMMCx->PV2CTRL = tempReg; + + /* Configure SDMMC_PV3CTRL, including SDCLK Frequency Select Value for DDR50 and SDR104 */ + tempReg = SDMMCx->PV3CTRL; + tempReg &= (~(SDMMC_PV3CTRL_CLKFS_SDR104 | SDMMC_PV3CTRL_CLKFS_DDR50)); + tempReg |= ((SDMMC_WrapperParam->SDR104SDCLKFreq << SDMMC_PV0CTRL_CLKFS_OFFSET) | SDMMC_WrapperParam->DDR50SDCLKFreq); + SDMMCx->PV3CTRL = tempReg; + + return SUCCESS; +} + + +/** + *\*\name SDMMC_StructWrapperInit. + *\*\fun Fills each SDMMC_WrapperStruct member with its default value. + *\*\param SDMMC_WrapperStruct: pointer to a SDMMC_WrapperType structure. + *\*\ - MaxBlockLen + *\*\ - SDBaseCLKFreq + *\*\ - TimeOutUnit + *\*\ - TuningCNT + *\*\ - WKUPSignalMode + *\*\ - SPIBlockMode + *\*\ - SPIMode + *\*\ - DDR50 + *\*\ - SDR104 + *\*\ - SDR50 + *\*\ - SlotType + *\*\ - AsyncInt + *\*\ - Suspend_Resume + *\*\ - SDMA + *\*\ - HS + *\*\ - ADMA2 + *\*\ - Embedded_8bit + *\*\ - UseTuningSDR50 + *\*\ - DSSDCLKFreq + *\*\ - INITSDCLKFreq + *\*\ - SDR12SDCLKFreq + *\*\ - HSSDCLKFreq + *\*\ - SDR50SDCLKFreq + *\*\ - SDR25SDCLKFreq + *\*\ - SDR104SDCLKFreq + *\*\ - DDR50SDCLKFreq + *\*\return none + */ +void SDMMC_StructWrapperInit(SDMMC_WrapperType *SDMMC_WrapperStruct) +{ + /* SDMMC_WrapperStruct members default value */ + SDMMC_WrapperStruct->MaxBlockLen = SDMMC_MAXBLOCKLEN_512B; + SDMMC_WrapperStruct->SDBaseCLKFreq = 0x68; + SDMMC_WrapperStruct->TimeOutUnit = SDMMC_TIMEOUTCLKUNIT_KHZ; + SDMMC_WrapperStruct->TuningCNT = 0x20; + SDMMC_WrapperStruct->WKUPSignalMode = SDMMC_ASYNCWKUP; + SDMMC_WrapperStruct->SPIBlockMode = SDMMC_SPIBLOCKMODEUNSUPPORT; + SDMMC_WrapperStruct->SPIMode = SDMMC_SPIMODEUNSUPPORT; + SDMMC_WrapperStruct->DDR50 = SDMMC_DDR50SUPPORT; + SDMMC_WrapperStruct->SDR104 = SDMMC_SDR104SUPPORT; + SDMMC_WrapperStruct->SDR50 = SDMMC_SDR50SUPPORT; + SDMMC_WrapperStruct->SlotType = SDMMC_SDTYPE; + SDMMC_WrapperStruct->AsyncInt = SDMMC_ASYNCINTSUPPORT; + SDMMC_WrapperStruct->Suspend_Resume = SDMMC_SUSRESUNSUPPORT; + SDMMC_WrapperStruct->SDMA = SDMMC_SDMASUPPORT; + SDMMC_WrapperStruct->HS = SDMMC_HSSUPPORT; + SDMMC_WrapperStruct->ADMA2 = SDMMC_ADMA2SUPPORT; + SDMMC_WrapperStruct->Embedded_8bit = SDMMC_EMBEDDEDUNSUPPORT; + SDMMC_WrapperStruct->UseTuningSDR50 = SDMMC_SDR50TUNING; + SDMMC_WrapperStruct->DSSDCLKFreq = 0x04; + SDMMC_WrapperStruct->INITSDCLKFreq = 0x00; + SDMMC_WrapperStruct->SDR12SDCLKFreq = 0x04; + SDMMC_WrapperStruct->HSSDCLKFreq = 0x02; + SDMMC_WrapperStruct->SDR50SDCLKFreq = 0x01; + SDMMC_WrapperStruct->SDR25SDCLKFreq = 0x02; + SDMMC_WrapperStruct->SDR104SDCLKFreq = 0x00; + SDMMC_WrapperStruct->DDR50SDCLKFreq = 0x02; +} + + +/** + *\*\name SDMMC_SoftWareReset. + *\*\fun Software Reset for DAT/CMD/ALL Line. + *\*\param SDHOSTx pointer to specified SDHOST,must be one of the following value: + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param LineMask: + *\*\ - SDHOST_SOFTWARE_DATALINE + *\*\ - SDHOST_SOFTWARE_CMDLINE + *\*\ - SDHOST_SOFTWARE_ALLLINE + *\*\return ErrorStatus + *\*\ - SUCCESS + *\*\ - ERROR + */ +ErrorStatus SDMMC_SoftWareReset(SDHOST_Module* SDHOSTx, uint32_t LineMask) +{ + ErrorStatus stauts_value; + uint32_t timeout = 0; + /* Reset ALL SDHOST. */ + SDHOSTx->CTRL2 |= LineMask; + + while((SDHOSTx->CTRL2 & LineMask) != RESET) + { + timeout++; + + if(timeout >= SDMMC_TIMEOUT_VALUE) + { + break; + } + } + + if(timeout >= SDMMC_TIMEOUT_VALUE) + { + stauts_value = ERROR; + } + else + { + stauts_value = SUCCESS; + } + + return stauts_value; +} + + +/** + *\*\name SDMMC_TransferConfig. + *\*\fun Start transfer according to current transfer state. + *\*\param SDHOSTx pointer to specified SDHOST,must be one of the following value: + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param transferFlags: transfer flags + *\*\ - SDMMC_CommandOnly + *\*\ - SDMMC_CommandAndTxData + *\*\ - SDMMC_CommandAndRxData + *\*\ - SDMMC_DataWithAutoCmd12 + *\*\ - SDMMC_DataWithAutoCmd23 + *\*\ - SDMMC_BootData + *\*\ - SDMMC_BootDataContinuous + *\*\param blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\param blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\param TMODE_struct: pointer to a SDHOST_TMODE_struct structure. + *\*\ - DMAE + *\*\ - SDHOST_TMODE_DMADISABLE + *\*\ - SDHOST_TMODE_DMAENABLE + *\*\ - BCNTE + *\*\ - SDHOST_TMODE_BLOCKCNTDISABLE + *\*\ - SDHOST_TMODE_BLOCKCNTENABLE + *\*\ - ACMDE + *\*\ - SDHOST_TMODE_NOACMDEN + *\*\ - SDHOST_TMODE_AC12EN + *\*\ - SDHOST_TMODE_AC23EN + *\*\ - DATDIR + *\*\ - SDHOST_TMODE_DATDIR_WRITE + *\*\ - SDHOST_TMODE_DATDIR_READ + *\*\ - BLKSEL + *\*\ - SDHOST_TMODE_SINGLEBLK + *\*\ - SDHOST_TMODE_MULTIBLK + *\*\return SDMMC_STS + *\*\ - SDMMC_BusyTransferring + *\*\ - SDMMC_SUCCESS + *\*\ - SDMMC_ERROR + */ +static SDMMC_STS SDMMC_TransferConfig(SDHOST_Module* SDHOSTx, uint32_t transferFlags, uint32_t blockSize, + uint32_t blockCount, SDHOST_TMODE_struct *TMODE_struct) +{ + uint32_t tempReg_BLK; + + if((transferFlags & ((uint32_t)SDMMC_CommandOnly)) != 0U) + { + /* clear data flags */ + TMODE_struct->DATDIR = SDHOST_TMODE_DATDIR_WRITE; + TMODE_struct->BCNTE = SDHOST_TMODE_BLOCKCNTDISABLE; + TMODE_struct->ACMDE = SDHOST_TMODE_NOACMDEN; + TMODE_struct->BLKSEL = SDHOST_TMODE_SINGLEBLK; + + if((SDHOSTx->PRESTS & SDHOST_PRESTS_CMDINHC) == SDHOST_PRESTS_CMDINHC) + { + return SDMMC_BusyTransferring; + } + } + else + { + /* if transfer boot continous, only need set the CONTREQ bit, leave others as it is */ + if((transferFlags & ((uint32_t)SDMMC_BootDataContinuous)) != 0U) + { + /* clear stop at block gap request */ + SDHOSTx->CTRL1 &= ~SDHOST_CTRL1_SABGREQ; + /* continous transfer data */ + SDHOSTx->CTRL1 |= SDHOST_CTRL1_CONTREQ; + return SDMMC_SUCCESS; + } + + /* check data inhibit flag */ + if((SDHOSTx->PRESTS & SDHOST_PRESTS_CMDINHD) == SDHOST_PRESTS_CMDINHD) + { + return SDMMC_BusyTransferring; + } + + /* check transfer block count */ + if ((blockCount > SDHOST_MAX_BLOCK_COUNT)) + { + return SDMMC_ERROR; + } + + /* config mix parameter */ + TMODE_struct->DATDIR = SDHOST_TMODE_DATDIR_WRITE; + TMODE_struct->BCNTE = SDHOST_TMODE_BLOCKCNTDISABLE; + TMODE_struct->ACMDE = SDHOST_TMODE_NOACMDEN; + TMODE_struct->BLKSEL = SDHOST_TMODE_SINGLEBLK; + + if((transferFlags & ((uint32_t)SDMMC_CommandAndRxData)) != 0U) + { + TMODE_struct->DATDIR = SDHOST_TMODE_DATDIR_READ; + } + + if(blockCount > 1U) + { + TMODE_struct->BCNTE = SDHOST_TMODE_BLOCKCNTENABLE; + TMODE_struct->BLKSEL = SDHOST_TMODE_MULTIBLK; + + /* auto command 12 */ + if((transferFlags & ((uint32_t)SDMMC_DataWithAutoCmd12)) != 0U) + { + TMODE_struct->ACMDE = SDHOST_TMODE_AC12EN; + } + } + + /* auto command 23, auto send set block count cmd before multiple read/write */ + if ((transferFlags & ((uint32_t)SDMMC_DataWithAutoCmd23)) != 0U) + { + TMODE_struct->ACMDE = SDHOST_TMODE_AC23EN; + /* config the block count to DS_ADDR */ + SDHOSTx->DSADD = blockCount; + } + + /* if transfer boot data, leave the block count to SDMMC_SetMmcBootConfig function */ + if ((transferFlags & ((uint32_t)SDMMC_BootData)) == 0U) + { + /* config data block size/block count */ + tempReg_BLK = SDHOSTx->BLKCFG; + tempReg_BLK &= (~(SDHOST_BLKCFG_CNT | SDHOST_BLKCFG_SIZE)); + tempReg_BLK |= ((blockCount << SDHOST_BLOCK_COUNT_OFFSET) | blockSize); + SDHOSTx->BLKCFG = tempReg_BLK; + } + else + { + TMODE_struct->BCNTE = SDHOST_TMODE_BLOCKCNTENABLE; + TMODE_struct->BLKSEL = SDHOST_TMODE_MULTIBLK; + } + } + + return SDMMC_SUCCESS; +} + + +/** + *\*\name SDMMC_ReceiveCommandResponse. + *\*\fun Receive command response. + *\*\param SDHOSTx pointer to specified SDHOST,must be one of the following value: + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param command: Command to be sent + *\*\ - index + *\*\ - 0~63 + *\*\ - argument + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - type + *\*\ - CARD_CommandTypeNormal + *\*\ - CARD_CommandTypeSuspend + *\*\ - CARD_CommandTypeResume + *\*\ - CARD_CommandTypeAbort + *\*\ - CARD_CommandTypeEmpty + *\*\ - responseType + *\*\ - CARD_ResponseTypeNone + *\*\ - CARD_ResponseTypeR1 + *\*\ - CARD_ResponseTypeR1b + *\*\ - CARD_ResponseTypeR2 + *\*\ - CARD_ResponseTypeR3 + *\*\ - CARD_ResponseTypeR4 + *\*\ - CARD_ResponseTypeR5 + *\*\ - CARD_ResponseTypeR5b + *\*\ - CARD_ResponseTypeR6 + *\*\ - CARD_ResponseTypeR7 + *\*\ - response[4U]: Response for this command. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - responseErrorFlags: Response error flag, which need to check the command reponse. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - flags: Cmd flags. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\return SDMMC_STS + *\*\ - SDMMC_SendCommandFailed + *\*\ - SDMMC_SUCCESS + */ +static SDMMC_STS SDMMC_ReceiveCommandResponse(SDHOST_Module* SDHOSTx, SDMMC_CMD *command) +{ + uint32_t response0 = SDHOSTx->CMDRSP0; + uint32_t response1 = SDHOSTx->CMDRSP1; + uint32_t response2 = SDHOSTx->CMDRSP2; + + if (command->responseType != CARD_ResponseTypeNone) + { + command->response[0U] = response0; + + if (command->responseType == CARD_ResponseTypeR2) + { + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + command->response[0U] <<= 8U; + command->response[1U] = (response1 << 8U) | ((response0 & 0xFF000000U) >> 24U); + command->response[2U] = (response2 << 8U) | ((response1 & 0xFF000000U) >> 24U); + command->response[3U] = (SDHOSTx->CMDRSP3 << 8U) | ((response2 & 0xFF000000U) >> 24U); + } + } + + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && + ((command->responseType == CARD_ResponseTypeR1) || (command->responseType == CARD_ResponseTypeR1b) || + (command->responseType == CARD_ResponseTypeR6) || (command->responseType == CARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return SDMMC_SendCommandFailed; + } + } + + return SDMMC_SUCCESS; +} + + +/** + *\*\name SDMMC_ReadDataPort. + *\*\fun Read DATAPORT when buffer enable bit is set. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param data Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\param transferredWords The number of data words have been transferred last time transaction. + *\*\ - The available range is 0 ~ 0xFFFFFFFF. + *\*\return transferredWords : The number of total data words have been transferred after this time transaction. + */ +static uint32_t SDMMC_ReadDataPort(SDHOST_Module* SDHOSTx, SDMMC_DATA *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t blockWords; + uint32_t transferredWordsvalue = transferredWords; + + /* If DMA is enable, do not need to polling data port */ + if ((SDHOSTx->TMODE & SDHOST_TMODE_DMAE) == 0U) + { + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if ((data->blockSize % 4U) != 0U) + { + data->blockSize += (4U - (data->blockSize % 4U)); /* make the block size as word-aligned */ + } + + blockWords = data->blockSize / 4U; + + i = 0U; + + while (i < blockWords) + { + data->rxData[transferredWordsvalue] = SDMMC_ReadData(SDHOSTx); + transferredWordsvalue++; + i++; + } + } + + return transferredWordsvalue; +} + +/** + *\*\name SDMMC_ReadByDataPortBlocking. + *\*\fun Read data by using DATAPORT polling way. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param data Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\return error_status. + *\*\ - SUCCESS + *\*\ - ERROR + */ +static ErrorStatus SDMMC_ReadByDataPortBlocking(SDHOST_Module* SDHOSTx, SDMMC_DATA *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U, interruptStatus = 0U; + ErrorStatus error_status = SUCCESS; + uint32_t timeout = 0xFFFFFF; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if ((data->blockSize % 4U) != 0U) + { + data->blockSize += (4U - (data->blockSize % 4U)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / 4U; + + while ((error_status == SUCCESS) && (transferredWords < totalWords)) + { + timeout = 0xFFFFFF; + while((interruptStatus & (((uint32_t)SDHOST_BufferReadReadyFlag | (uint32_t)SDHOST_DataErrorFlag))) == 0) + { + interruptStatus = SDHOSTx->INTSTS; + timeout--; + + if(timeout < 2) + { + break; + } + } + + /* during std tuning process, software do not need to read data, but wait BRR is enough */ + if ((data->dataType == (uint32_t)SDHOST_TransferDataTuning) && + ((interruptStatus & ((uint32_t)SDHOST_BufferReadReadyFlag)) != 0)) + { + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_BufferReadReadyFlag); + return SUCCESS; + } + else if ((interruptStatus & ((uint32_t)SDHOST_DataErrorFlag)) != 0) + { + if (data->enableIgnoreError == ENABLE) + { + error_status = ERROR; + } + + /* clear data error flag */ + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_DataErrorFlag); + } + else + { + /* Intentional empty */ + } + + if (error_status == SUCCESS) + { + /* clear buffer read ready */ + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_BufferReadReadyFlag); + interruptStatus = 0U; + transferredWords = SDMMC_ReadDataPort(SDHOSTx, data, transferredWords); + } + } + + timeout = 0xFFFFFF; + while((interruptStatus & ((uint32_t)SDHOST_DataCompleteFlag)) == 0) + { + interruptStatus = SDHOSTx->INTSTS; + timeout--; + + if(timeout < 2) + { + break; + } + } + /* Clear data complete flag after the last read operation. */ + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_DataCompleteFlag); + + return error_status; +} + + +/** + *\*\name SDMMC_WriteDataPort. + *\*\fun Write DATAPORT when buffer enable bit is set. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param data Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\param transferredWords The number of data words have been transferred last time transaction. + *\*\ - The available range is 0 ~ 0xFFFFFFFF. + *\*\return transferredWords : The number of total data words have been transferred after this time transaction. + */ +static uint32_t SDMMC_WriteDataPort(SDHOST_Module* SDHOSTx, SDMMC_DATA *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t blockWords; + uint32_t transferredWordsvalue = transferredWords; + + /* If DMA is enable, do not need to polling data port */ + if ((SDHOSTx->TMODE & SDHOST_TMODE_DMAE) == 0U) + { + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if ((data->blockSize % sizeof(uint32_t)) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + blockWords = data->blockSize / sizeof(uint32_t); + + i = 0U; + + while (i < blockWords) + { + SDMMC_WriteData(SDHOSTx, data->txData[transferredWordsvalue]); + transferredWordsvalue++; + i++; + } + } + + return transferredWordsvalue; +} + + +/** + *\*\name SDMMC_ReadByDataPortBlocking. + *\*\fun Write data by using DATAPORT polling way. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param data Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\return error_status. + *\*\ - SUCCESS + *\*\ - ERROR + */ +static ErrorStatus SDMMC_WriteByDataPortBlocking(SDHOST_Module* SDHOSTx, SDMMC_DATA *data) +{ + uint32_t totalWords; + + uint32_t transferredWords = 0U, interruptStatus = 0U; + ErrorStatus error_status = SUCCESS; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if ((data->blockSize % sizeof(uint32_t)) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error_status == SUCCESS) && (transferredWords < totalWords)) + { + while((interruptStatus & (((uint32_t)SDHOST_BufferWriteReadyFlag | (uint32_t)SDHOST_DataErrorFlag))) == 0) + { + interruptStatus = SDHOSTx->INTSTS; + } + + if((interruptStatus & ((uint32_t)SDHOST_DataErrorFlag)) != 0) + { + if (data->enableIgnoreError == ENABLE) + { + error_status = ERROR; + } + + /* clear data error flag */ + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_DataErrorFlag); + } + else + { + /* Intentional empty */ + } + + if (error_status == SUCCESS) + { + /* clear buffer write ready */ + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_BufferWriteReadyFlag); + interruptStatus = 0U; + transferredWords = SDMMC_WriteDataPort(SDHOSTx, data, transferredWords); + } + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while((interruptStatus & (((uint32_t)SDHOST_DataCompleteFlag | (uint32_t)SDHOST_DataErrorFlag))) == 0) + { + interruptStatus = SDHOSTx->INTSTS; + } + + if ((interruptStatus & ((uint32_t)SDHOST_DataErrorFlag)) != 0UL) + { + if (data->enableIgnoreError == ENABLE) + { + error_status = ERROR; + } + } + + SDMMC_ClrFlag(SDHOSTx, (((uint32_t)SDHOST_DataCompleteFlag | (uint32_t)SDHOST_DataErrorFlag))); + + return error_status; +} + + +/** + *\*\name SDMMC_SendCommand. + *\*\fun send command function. + *\*\param SDHOSTx pointer to specified SDHOST,must be one of the following value: + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param command: command configuration + *\*\ - index + *\*\ - 0~63 + *\*\ - argument + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - type + *\*\ - CARD_CommandTypeNormal + *\*\ - CARD_CommandTypeSuspend + *\*\ - CARD_CommandTypeResume + *\*\ - CARD_CommandTypeAbort + *\*\ - CARD_CommandTypeEmpty + *\*\ - responseType + *\*\ - CARD_ResponseTypeNone + *\*\ - CARD_ResponseTypeR1 + *\*\ - CARD_ResponseTypeR1b + *\*\ - CARD_ResponseTypeR2 + *\*\ - CARD_ResponseTypeR3 + *\*\ - CARD_ResponseTypeR4 + *\*\ - CARD_ResponseTypeR5 + *\*\ - CARD_ResponseTypeR5b + *\*\ - CARD_ResponseTypeR6 + *\*\ - CARD_ResponseTypeR7 + *\*\ - response[4U]: Response for this command. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - responseErrorFlags: Response error flag, which need to check the command reponse. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - flags: Cmd flags. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\param TMODE_struct: pointer to a SDHOST_TMODE_struct structure. + *\*\ - DMAE + *\*\ - SDHOST_TMODE_DMADISABLE + *\*\ - SDHOST_TMODE_DMAENABLE + *\*\ - BCNTE + *\*\ - SDHOST_TMODE_BLOCKCNTDISABLE + *\*\ - SDHOST_TMODE_BLOCKCNTENABLE + *\*\ - ACMDE + *\*\ - SDHOST_TMODE_NOACMDEN + *\*\ - SDHOST_TMODE_AC12EN + *\*\ - SDHOST_TMODE_AC23EN + *\*\ - DATDIR + *\*\ - SDHOST_TMODE_DATDIR_WRITE + *\*\ - SDHOST_TMODE_DATDIR_READ + *\*\ - BLKSEL + *\*\ - SDHOST_TMODE_SINGLEBLK + *\*\ - SDHOST_TMODE_MULTIBLK + *\*\return none + */ +void SDMMC_SendCommand(SDHOST_Module* SDHOSTx, SDMMC_CMD *command, const SDHOST_TMODE_struct *TMODE_struct) +{ + uint32_t xferType; + uint32_t flags; + flags = command->flags; + + if (((SDHOSTx->PRESTS & ((uint32_t)SDHOST_CommandInhibitFlag)) == 0UL) && (command->type != CARD_CommandTypeEmpty)) + { + if ((command->responseType == CARD_ResponseTypeR1) || (command->responseType == CARD_ResponseTypeR5) || + (command->responseType == CARD_ResponseTypeR6) || (command->responseType == CARD_ResponseTypeR7)) + { + flags |= ((uint32_t)SDHOST_ResponseLength48Flag | (uint32_t)SDHOST_EnableCrcCheckFlag | + (uint32_t)SDHOST_EnableIndexCheckFlag); + } + else if ((command->responseType == CARD_ResponseTypeR1b) || (command->responseType == CARD_ResponseTypeR5b)) + { + flags |= ((uint32_t)SDHOST_ResponseLength48BusyFlag | (uint32_t)SDHOST_EnableCrcCheckFlag | + (uint32_t)SDHOST_EnableIndexCheckFlag); + } + else if (command->responseType == CARD_ResponseTypeR2) + { + flags |= ((uint32_t)SDHOST_ResponseLength136Flag | (uint32_t)SDHOST_EnableCrcCheckFlag); + } + else if ((command->responseType == CARD_ResponseTypeR3) || (command->responseType == CARD_ResponseTypeR4)) + { + flags |= ((uint32_t)SDHOST_ResponseLength48Flag); + } + else + { + /* Intentional empty */ + } + + if (command->type == CARD_CommandTypeAbort) + { + flags |= (uint32_t)SDHOST_CommandTypeAbortFlag; + } + + /* config cmd index */ + xferType = 0x00000000U; + + xferType |= + (((command->index << SDHOST_CMD_INDEX_OFFSET) & SDHOST_TMODE_INDEX) | + ((flags) & (SDHOST_TMODE_TYPE | SDHOST_TMODE_INDEXCK | SDHOST_TMODE_CRCCK | + SDHOST_TMODE_RTYPESEL | SDHOST_TMODE_DPRESEL))); + + xferType |= TMODE_struct->DMAE; + xferType |= TMODE_struct->BCNTE; + xferType |= TMODE_struct->ACMDE; + xferType |= TMODE_struct->DATDIR; + xferType |= TMODE_struct->BLKSEL; + + /* config the command xfertype and argument */ + SDHOSTx->CMDARG1 = command->argument; + SDHOSTx->TMODE = xferType; + } + + if (command->type == CARD_CommandTypeEmpty) + { + /* disable CMD done interrupt for empty command */ + SDHOSTx->ISE &= ~SDHOST_ISE_CMDCSE; + } +} + + +/** + *\*\name SDMMC_WaitCommandDone. + *\*\fun wait command done. + *\*\param SDHOSTx pointer to specified SDHOST,must be one of the following value: + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param command: command configuration + *\*\ - index + *\*\ - 0~63 + *\*\ - argument + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - type + *\*\ - CARD_CommandTypeNormal + *\*\ - CARD_CommandTypeSuspend + *\*\ - CARD_CommandTypeResume + *\*\ - CARD_CommandTypeAbort + *\*\ - CARD_CommandTypeEmpty + *\*\ - responseType + *\*\ - CARD_ResponseTypeNone + *\*\ - CARD_ResponseTypeR1 + *\*\ - CARD_ResponseTypeR1b + *\*\ - CARD_ResponseTypeR2 + *\*\ - CARD_ResponseTypeR3 + *\*\ - CARD_ResponseTypeR4 + *\*\ - CARD_ResponseTypeR5 + *\*\ - CARD_ResponseTypeR5b + *\*\ - CARD_ResponseTypeR6 + *\*\ - CARD_ResponseTypeR7 + *\*\ - response[4U]: Response for this command. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - responseErrorFlags: Response error flag, which need to check the command reponse. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - flags: Cmd flags. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\param pollingCmdDone: polling command done flag + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return SDMMC_STS + *\*\ - SDMMC_ERROR + *\*\ - SDMMC_SUCCESS + *\*\ - SDMMC_SendCommandFailed + */ +SDMMC_STS SDMMC_WaitCommandDone(SDHOST_Module* SDHOSTx, SDMMC_CMD *command, FunctionalState pollingCmdDone) +{ + SDMMC_STS error = SDMMC_SUCCESS; + uint32_t interruptStatus = 0U; + uint32_t timeout_value = 0x20000; + + /* check if need polling command done or not */ + if (pollingCmdDone == ENABLE) + { + /* Wait command complete or SDMMC encounters error. */ + while(((interruptStatus & ((uint32_t)SDHOST_CommandFlag)) == 0) && (timeout_value > 0)) + { + interruptStatus = SDHOSTx->INTSTS; + timeout_value--; + } + + if(timeout_value == 0) + { + interruptStatus = (uint32_t)SDHOST_CommandTimeoutFlag; + } + + if ((interruptStatus & ((uint32_t)SDHOST_CommandErrorFlag)) != 0UL) + { + error = SDMMC_ERROR; + } + + /* Receive response when command completes successfully. */ + if (error == SDMMC_SUCCESS) + { + error = SDMMC_ReceiveCommandResponse(SDHOSTx, command); + } + + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_CommandFlag); + } + + return error; +} + + +/** + *\*\name SDMMC_TransferDataBlocking. + *\*\fun Transfer data by polling way. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param data Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\param DMACmd: DMA flag + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return error. + *\*\ - SDMMC_ERROR + *\*\ - SDMMC_SUCCESS + *\*\ - SDMMC_TransferDataFailed + */ +static SDMMC_STS SDMMC_TransferDataBlocking(SDHOST_Module* SDHOSTx, SDMMC_DATA *data, FunctionalState DMACmd) +{ + SDMMC_STS error = SDMMC_SUCCESS; + ErrorStatus error_status; + uint32_t interruptStatus = 0U; + uint32_t SDMA_address; + + if (DMACmd == ENABLE) + { + /* Wait data complete or SDMMC encounters error. */ + while((interruptStatus & ((uint32_t)SDHOST_DataDMAFlag)) == 0) + { + interruptStatus = SDHOSTx->INTSTS; + + if((interruptStatus & ((uint32_t)SDHOST_DmaCompleteFlag)) == ((uint32_t)SDHOST_DmaCompleteFlag)) + { + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_DmaCompleteFlag); + SDMA_address = SDHOSTx->DSADD; + SDHOSTx->DSADD = SDMA_address; + } + } + + if((interruptStatus & (((uint32_t)SDHOST_DataErrorFlag | (uint32_t)SDHOST_DmaErrorFlag))) != 0) + { + if (((data->enableIgnoreError == ENABLE)) || ((interruptStatus & ((uint32_t)SDHOST_DataTimeoutFlag)) != 0)) + { + error = SDMMC_TransferDataFailed; + } + } + else + { + /* Intentional empty */ + } + + /* load dummy data */ + if ((data->dataType == SDHOST_TransferDataBootcontinous) && (error == SDMMC_SUCCESS)) + { + *(data->rxData) = SDHOST_BOOTDUMMY; + } + + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_DataDMAFlag); + } + else + { + if (data->rxData != NULL) + { + error_status = SDMMC_ReadByDataPortBlocking(SDHOSTx, data); + + if (error_status != SUCCESS) + { + return SDMMC_ERROR; + } + } + else + { + error_status = SDMMC_WriteByDataPortBlocking(SDHOSTx, data); + + if (error_status != SUCCESS) + { + return SDMMC_ERROR; + } + } + } + + return error; +} + + +/** + *\*\name SDMMC_GetCapability. + *\*\fun Get SDHSOT capability structure value. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param capability: pointer to a SDHOST_capability structure. + *\*\ - MaxBlockLen : Maximum Block Length supported by the Core/Device + *\*\ - SDMMC_MAXBLOCKLEN_512B + *\*\ - SDMMC_MAXBLOCKLEN_1024B + *\*\ - SDMMC_MAXBLOCKLEN_2048B + *\*\ - SDBaseCLKFreq : xin_clk, Base Clock Frequency for SD Clock + *\*\ - 0x0A~0x68,Unit MHz + *\*\ - TimeOutUnit : the unit of base clock frequency used to detect Data Timeout Error + *\*\ - SDMMC_TIMEOUTCLKUNIT_KHZ + *\*\ - SDMMC_TIMEOUTCLKUNIT_MHZ + *\*\ - SPIBlockMode : SPI Block Mode + *\*\ - SDMMC_SPIBLOCKMODESUPPORT + *\*\ - SDMMC_SPIBLOCKMODEUNSUPPORT + *\*\ - SPIMode : SPI Mode Support + *\*\ - SDMMC_SPIMODESUPPORT + *\*\ - SDMMC_SPIMODEUNSUPPORT + *\*\ - DDR50 : DDR50 Support + *\*\ - SDMMC_DDR50SUPPORT + *\*\ - SDMMC_DDR50UNSUPPORT + *\*\ - SDR104 : SDR104 Support + *\*\ - SDMMC_SDR104SUPPORT + *\*\ - SDMMC_SDR104UNSUPPORT + *\*\ - SDR50 : SDR50 Support + *\*\ - SDMMC_SDR50SUPPORT + *\*\ - SDMMC_SDR50UNSUPPORT + *\*\ - SlotType : Slot Type + *\*\ - SDMMC_SDTYPE + *\*\ - SDMMC_EMMCTYPE + *\*\ - AsyncInt : Asynchronous Interrupt Support + *\*\ - SDMMC_ASYNCINTSUPPORT + *\*\ - SDMMC_ASYNCINTUNSUPPORT + *\*\ - Suspend_Resume : Suspend/Resume Support + *\*\ - SDMMC_SUSRESSUPPORT + *\*\ - SDMMC_SUSRESUNSUPPORT + *\*\ - SDMA : SDMA Support + *\*\ - SDMMC_SDMASUPPORT + *\*\ - SDMMC_SDMAUNSUPPORT + *\*\ - HS : High Speed Support + *\*\ - SDMMC_HSSUPPORT + *\*\ - SDMMC_HSUNSUPPORT + *\*\ - ADMA2 : ADMA2 Support + *\*\ - SDMMC_ADMA2SUPPORT + *\*\ - SDMMC_ADMA2UNSUPPORT + *\*\ - Embedded_8bit : 8-bit Support for Embedded Device + *\*\ - SDMMC_EMBEDDEDSUPPORT + *\*\ - SDMMC_EMBEDDEDUNSUPPORT + *\*\ - UseTuningSDR50 : Use Tuning for SDR50 + *\*\ - SDMMC_SDR50TUNING + *\*\ - SDMMC_SDR50UNTUNING + *\*\return none + */ +void SDMMC_GetCapability(SDHOST_Module* SDHOSTx, SDHOST_capability *capability) +{ + if((SDHOSTx->CAP0STS & SDHOST_CAP0_ADMA2_MASK) == SDHOST_CAP0_ADMA2_MASK) + { + capability->ADMA2 = SDMMC_ADMA2SUPPORT; + } + else + { + capability->ADMA2 = SDMMC_ADMA2UNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_ASYNCINT_MASK) == SDHOST_CAP0_ASYNCINT_MASK) + { + capability->AsyncInt = SDMMC_ASYNCINTSUPPORT; + } + else + { + capability->AsyncInt = SDMMC_ASYNCINTUNSUPPORT; + } + + if((SDHOSTx->CAP1STS & SDHOST_CAP1_DDR50_MASK) == SDHOST_CAP1_DDR50_MASK) + { + capability->DDR50 = SDMMC_DDR50SUPPORT; + } + else + { + capability->DDR50 = SDMMC_DDR50UNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_EMBUS_MASK) == SDHOST_CAP0_EMBUS_MASK) + { + capability->Embedded_8bit = SDMMC_EMBEDDEDSUPPORT; + } + else + { + capability->Embedded_8bit = SDMMC_EMBEDDEDUNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_HS_MASK) == SDHOST_CAP0_HS_MASK) + { + capability->HS = SDMMC_HSSUPPORT; + } + else + { + capability->HS = SDMMC_HSUNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_MBL_MASK) == SDMMC_MAXBLOCKLEN_512B) + { + capability->MaxBlockLen = SDMMC_MAXBLOCKLEN_512B; + } + else if((SDHOSTx->CAP0STS & SDHOST_CAP0_MBL_MASK) == SDHOST_CAP0STS_MBL_0) + { + capability->MaxBlockLen = SDMMC_MAXBLOCKLEN_1024B; + } + else + { + capability->MaxBlockLen = SDMMC_MAXBLOCKLEN_2048B; + } + + capability->SDBaseCLKFreq = ((SDHOSTx->CAP0STS & SDHOST_CAP0_BCLKF_MASK) >> SDHOST_CAP0_BCLKF_OFFSET); + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_SDMA_MASK) == SDHOST_CAP0_SDMA_MASK) + { + capability->SDMA = SDMMC_SDMASUPPORT; + } + else + { + capability->SDMA = SDMMC_SDMAUNSUPPORT; + } + + if((SDHOSTx->CAP1STS & SDHOST_CAP1_SDR104_MASK) == SDHOST_CAP1_SDR104_MASK) + { + capability->SDR104 = SDMMC_SDR104SUPPORT; + } + else + { + capability->SDR104 = SDMMC_SDR104UNSUPPORT; + } + + if((SDHOSTx->CAP1STS & SDHOST_CAP1_SDR50_MASK) == SDHOST_CAP1_SDR50_MASK) + { + capability->SDR50 = SDMMC_SDR50SUPPORT; + } + else + { + capability->SDR50 = SDMMC_SDR50UNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_SLOTTYPE_MASK) == SDHOST_CAP0STS_STYP_0) + { + capability->SlotType = SDMMC_EMMCTYPE; + } + else + { + capability->SlotType = SDMMC_SDTYPE; + } + + if((SDHOSTx->CAP1STS & SDHOST_CAP1_SPIBMOD_MASK) == SDHOST_CAP1_SPIBMOD_MASK) + { + capability->SPIBlockMode = SDMMC_SPIBLOCKMODESUPPORT; + } + else + { + capability->SPIBlockMode = SDMMC_SPIBLOCKMODEUNSUPPORT; + } + + if((SDHOSTx->CAP1STS & SDHOST_CAP1_SPIMOD_MASK) == SDHOST_CAP1_SPIMOD_MASK) + { + capability->SPIMode = SDMMC_SPIMODESUPPORT; + } + else + { + capability->SPIMode = SDMMC_SPIMODEUNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_SRS_MASK) == SDHOST_CAP0_SRS_MASK) + { + capability->Suspend_Resume = SDMMC_SUSRESSUPPORT; + } + else + { + capability->Suspend_Resume = SDMMC_SUSRESUNSUPPORT; + } + + if((SDHOSTx->CAP0STS & SDHOST_CAP0_TCLKU_MASK) == SDHOST_CAP0_TCLKU_MASK) + { + capability->TimeOutUnit = SDMMC_TIMEOUTCLKUNIT_MHZ; + } + else + { + capability->TimeOutUnit = SDMMC_TIMEOUTCLKUNIT_KHZ; + } + + if((SDHOSTx->CAP1STS & SDHOST_CAP1_UTFSDR50_MASK) == SDHOST_CAP1_UTFSDR50_MASK) + { + capability->UseTuningSDR50 = SDMMC_SDR50TUNING; + } + else + { + capability->UseTuningSDR50 = SDMMC_SDR50UNTUNING; + } +} + + +/** + *\*\name SDMMC_GetPresetvalue. + *\*\fun Get SDHSOT presetvalue structure value. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param presetvalue: pointer to a SDHOST_presetvalue structure. + *\*\ - DSSDCLKFreq : SDCLK Frequency Select Value for Default Speed + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - INITSDCLKFreq :SDCLK Frequency Select Value for Initialization + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR12SDCLKFreq : SDCLK Frequency Select Value for SDR12 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - HSSDCLKFreq : SDCLK Frequency Select Value for High Speed + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR50SDCLKFreq : SDCLK Frequency Select Value for SDR50 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR25SDCLKFreq : SDCLK Frequency Select Value for SDR25 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - SDR104SDCLKFreq : SDCLK Frequency Select Value for SDR104 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\ - DDR50SDCLKFreq : SDCLK Frequency Select Value for DDR50 + *\*\ - 0x00~0x3FF ; 2N frequency division + *\*\return none + */ +void SDMMC_GetPresetvalue(SDHOST_Module* SDHOSTx, SDHOST_presetvalue *presetvalue) +{ + presetvalue->DSSDCLKFreq = ((SDHOSTx->PV0STS & SDHOST_PV0_DSCLKFS_MASK) >> SDHOST_PV0_DSCLKFS_OFFSET); + presetvalue->INITSDCLKFreq = (SDHOSTx->PV0STS & SDHOST_PV0_INITCLKFS_MASK); + presetvalue->SDR12SDCLKFreq = ((SDHOSTx->PV1STS & SDHOST_PV1_SDR12CLKFS_MASK) >> SDHOST_PV1_SDR12CLKFS_OFFSET); + presetvalue->HSSDCLKFreq = (SDHOSTx->PV1STS & SDHOST_PV1_HSCLKFS_MASK); + presetvalue->SDR50SDCLKFreq = ((SDHOSTx->PV2STS & SDHOST_PV2_SDR50CLKFS_MASK) >> SDHOST_PV2_SDR50CLKFS_OFFSET); + presetvalue->SDR25SDCLKFreq = (SDHOSTx->PV2STS & SDHOST_PV2_SDR25CLKFS_MASK); + presetvalue->DDR50SDCLKFreq = ((SDHOSTx->PV3STS & SDHOST_PV3_DDR50CLKFS_MASK) >> SDHOST_PV3_DDR50CLKFS_OFFSET); + presetvalue->SDR104SDCLKFreq = (SDHOSTx->PV3STS & SDHOST_PV3_SDR104CLKFS_MASK); +} + + +/** + *\*\name SDMMC_EnableSDCLK + *\*\fun Enables or disables SD Clock. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableSDCLK(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL2 |= (SDHOST_CTRL2_SDCLKE | SDHOST_CTRL2_INCLKE); + } + else + { + SDHOSTx->CTRL2 &= (~(SDHOST_CTRL2_SDCLKE | SDHOST_CTRL2_INCLKE)); + } +} + +/** + *\*\name SDMMC_WaitSDCLKStable + *\*\fun Waiting for SD clock to stabilize. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return status_value + *\*\ - SDMMC_ERROR + *\*\ - SDMMC_SUCCESS + */ +SDMMC_STS SDMMC_WaitSDCLKStable(SDHOST_Module* SDHOSTx) +{ + SDMMC_STS status_value; + uint32_t timeout = 0xFFFFUL; + + /* Wait until the SD clock is stable. */ + while ((SDHOSTx->CTRL2 & SDHOST_CTRL2_INCLKSTS) != SDHOST_CTRL2_INCLKSTS) + { + timeout--; + + if(timeout < 2) + { + break; + } + } + + if(timeout < 2 ) + { + status_value = SDMMC_ERROR; + } + else + { + status_value = SDMMC_SUCCESS; + } + + return status_value; +} + + +/** + *\*\name SDMMC_SetSdClock. + *\*\fun Sets the SD bus clock frequency. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param PresetCmd: Whether to use preset value settings. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\param prescaler: SD bus clock prescaler value. + *\*\ - 0~0x3FF 1/2N frequency division + *\*\return status_value + *\*\ - SDMMC_ERROR + *\*\ - SDMMC_SUCCESS + */ +SDMMC_STS SDMMC_SetSdClock(SDHOST_Module* SDHOSTx, FunctionalState PresetCmd, uint32_t prescaler) +{ + SDMMC_STS status_value; + uint32_t temp_value; + + SDMMC_EnableSDCLK(SDHOSTx, DISABLE); + + if(PresetCmd == ENABLE) + { + /* Use preset values */ + SDHOSTx->CTRLSTS |= SDHOST_CTRLSTS_PREVE; + } + else + { + /* Use HD config values */ + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_PREVE); + + /* set prescaler value */ + temp_value = SDHOSTx->CTRL2; + temp_value &= (~SDHOST_CTRL2_SDCLKSEL); + temp_value |= (((prescaler & 0xFFUL) << REG_BIT8_OFFSET) | ((prescaler >> REG_BIT8_OFFSET) << REG_BIT6_OFFSET)); + SDHOSTx->CTRL2 = temp_value; + } + + SDMMC_EnableSDCLK(SDHOSTx, ENABLE); + + status_value = SDMMC_WaitSDCLKStable(SDHOSTx); + return status_value; +} + + +/** + *\*\name SDMMC_ConfigemmcBoot. + *\*\fun Configures the MMC boot feature. + *\*\param SDHOSTx pointer to specified SDHOST,must be one of the following value: + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param config: pointer to a SDHOST_boot_config structure. + *\*\ - ackTimeoutCount : Timeout value for the boot ACK + *\*\ - The available range is 0 ~ 0xFFFFFFFF. unit sd clock. + *\*\ - bootMode : Boot mode selection + *\*\ - SDHOST_BOOTMODENORMAL Normal boot + *\*\ - SDHOST_BOOTMODEALIERNATIVE Alternative boot + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - BootAck : + *\*\ - SDHOST_BOOTACKCHECK + *\*\ - SDHOST_BOOTNOACKCHECK + *\*\return none + */ +void SDMMC_ConfigemmcBoot(SDHOST_Module* SDHOSTx, const SDHOST_boot_config *config) +{ + uint32_t temp_value; + SDHOSTx->BOOTTCTRL = config->ackTimeoutCount; + + temp_value = SDHOSTx->CTRL1; + temp_value &= (~(SDHOST_BOOTMODEALIERNATIVE | SDHOST_BOOTACKCHECK)); + temp_value |= (config->BootAck | config->bootMode); + SDHOSTx->CTRL1 = temp_value; + + temp_value = SDHOSTx->BLKCFG; + temp_value &= (~(SDHOST_BLKCFG_CNT | SDHOST_BLKCFG_SIZE)); + temp_value |= ((config->blockCount << 16) | config->blockSize); + SDHOSTx->BLKCFG = temp_value; +} + +/** + *\*\name SDMMC_ConfigInternalDma. + *\*\fun Use to config the Internal DMA related registers. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param dmaConfig + *\*\ - dmaMode. + *\*\ - DmaModeSimple + *\*\ - DmaModeAdma2 + *\*\ - admaTable Adma table address. + *\*\ - The available range is 0 ~ 0xFFFFFFFF. + *\*\ - admaTableWords Adma table length. + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\param dataAddr transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. + *\*\ - The available range is 0 ~ 0xFFFFFFFF. + *\*\param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to DISABLE. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\param TMODE_struct: pointer to a SDHOST_TMODE_struct structure. + *\*\ - DMAE + *\*\ - SDHOST_TMODE_DMADISABLE + *\*\ - SDHOST_TMODE_DMAENABLE + *\*\ - BCNTE + *\*\ - SDHOST_TMODE_BLOCKCNTDISABLE + *\*\ - SDHOST_TMODE_BLOCKCNTENABLE + *\*\ - ACMDE + *\*\ - SDHOST_TMODE_NOACMDEN + *\*\ - SDHOST_TMODE_AC12EN + *\*\ - SDHOST_TMODE_AC23EN + *\*\ - DATDIR + *\*\ - SDHOST_TMODE_DATDIR_WRITE + *\*\ - SDHOST_TMODE_DATDIR_READ + *\*\ - BLKSEL + *\*\ - SDHOST_TMODE_SINGLEBLK + *\*\ - SDHOST_TMODE_MULTIBLK + *\*\return SDMMC_STS + *\*\ - SDMMC_DMADataAddrNotAlign + *\*\ - SDMMC_SUCCESS + */ +static SDMMC_STS SDMMC_ConfigInternalDma(SDHOST_Module* SDHOSTx, SDHOST_ADMAconfig *dmaConfig, const uint32_t *dataAddr, + FunctionalState enAutoCmd23, SDHOST_TMODE_struct *TMODE_struct) +{ + if (dmaConfig->dmaMode == DmaModeSimple) + { + /* check DMA data buffer address align or not */ + if (((uint32_t)dataAddr % SDHOST_ADMA2_ADDRESS_ALIGN) != 0UL) + { + return SDMMC_DMADataAddrNotAlign; + } + + /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, + and block count should load to DS_ADD*/ + if (enAutoCmd23 == ENABLE) + { + SDHOSTx->ASADD0 = ((uint32_t)dataAddr); + } + else + { + SDHOSTx->DSADD = ((uint32_t)dataAddr); + } + } + else + { + /* When use ADMA, disable simple DMA */ + SDHOSTx->DSADD = 0UL; + SDHOSTx->ASADD0 = ((uint32_t)(dmaConfig->admaTable)); + } + + /* select DMA mode */ + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_DMASEL); + SDHOSTx->CTRL1 |= (uint32_t)(dmaConfig->dmaMode); + + /* enable DMA */ + TMODE_struct->DMAE = SDHOST_TMODE_DMAENABLE; + return SDMMC_SUCCESS; +} + +/** + *\*\name SDMMC_SetAdmaTableConfig. + *\*\fun Sets the DMA descriptor table configuration. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param dmaConfig + *\*\ - dmaMode. + *\*\ - DmaModeSimple + *\*\ - DmaModeAdma2 + *\*\ - admaTable Adma table address. + *\*\ - The available range is 0 ~ 0xFFFFFFFF. + *\*\ - admaTableWords Adma table length. + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\param dataConfig Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor. + *\*\ - SDHOST_AdmaDescriptorSingleFlag. + *\*\ - SDHOST_AdmaDescriptorMultipleFlag. + *\*\param TMODE_struct: pointer to a SDHOST_TMODE_struct structure. + *\*\ - DMAE + *\*\ - SDHOST_TMODE_DMADISABLE + *\*\ - SDHOST_TMODE_DMAENABLE + *\*\ - BCNTE + *\*\ - SDHOST_TMODE_BLOCKCNTDISABLE + *\*\ - SDHOST_TMODE_BLOCKCNTENABLE + *\*\ - ACMDE + *\*\ - SDHOST_TMODE_NOACMDEN + *\*\ - SDHOST_TMODE_AC12EN + *\*\ - SDHOST_TMODE_AC23EN + *\*\ - DATDIR + *\*\ - SDHOST_TMODE_DATDIR_WRITE + *\*\ - SDHOST_TMODE_DATDIR_READ + *\*\ - BLKSEL + *\*\ - SDHOST_TMODE_SINGLEBLK + *\*\ - SDHOST_TMODE_MULTIBLK + *\*\return SDMMC_STS + *\*\ - SDMMC_ERROR. + *\*\ - SDMMC_SUCCESS. + *\*\ - SDMMC_DMADataAddrNotAlign + *\*\ - SDMMC_OutOfRange + */ +static SDMMC_STS SDMMC_SetAdmaTableConfig(SDHOST_Module* SDHOSTx, SDHOST_ADMAconfig *dmaConfig, + SDMMC_DATA *dataConfig, SDHOST_TMODE_struct *TMODE_struct) +{ + SDMMC_STS status_value = SDMMC_SUCCESS; + FunctionalState enAutoCmd23; + uint32_t bootDummyOffset = + (dataConfig->dataType == (uint32_t)SDHOST_TransferDataBootcontinous) ? sizeof(uint32_t) : 0UL; + const uint32_t *data = (const uint32_t *)((uint32_t)( + (uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + bootDummyOffset)); + + /* for internal dma, internal DMA configurations should not update the configurations when continous transfer the + * boot data, only the DMA descriptor need update */ + if ((status_value == SDMMC_SUCCESS) && (dataConfig->dataType != SDHOST_TransferDataBootcontinous)) + { + if(dataConfig->AutoCommand12_23 == AutoCommand23) + { + enAutoCmd23 = ENABLE; + } + else + { + enAutoCmd23 = DISABLE; + } + + status_value = SDMMC_ConfigInternalDma(SDHOSTx, dmaConfig, data, enAutoCmd23, TMODE_struct); + } + + return status_value; +} + + +/** + *\*\name SDMMC_TransferBlocking. + *\*\fun Transfers the command/data using a blocking method. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param dmaConfig + *\*\ - dmaMode. + *\*\ - DmaModeSimple + *\*\ - DmaModeAdma2 + *\*\ - admaTable Adma table address. + *\*\ - The available range is 0 ~ 0xFFFFFFFF. + *\*\ - admaTableWords Adma table length. + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\param transfer + *\*\ - data Data descriptor. + *\*\ - AutoCommand12_23. + *\*\ - AutoCommand12 + *\*\ - AutoCommand23 + *\*\ - NoAutoCommand + *\*\ - enableIgnoreError. + *\*\ - ENABLE + *\*\ - DISABLE + *\*\ - dataType. + *\*\ - SDHOST_TransferDataNormal + *\*\ - SDHOST_TransferDataTuning + *\*\ - SDHOST_TransferDataBoot + *\*\ - SDHOST_TransferDataBootcontinous + *\*\ - blockCount : + *\*\ - The available range is 0 ~ 0xFFFF. + *\*\ - blockSize : + *\*\ - The available range is 0 ~ 0x0800. + *\*\ - rxData : Buffer to save data read. + *\*\ - txData : Data buffer to write. + *\*\ - command: command configuration + *\*\ - index + *\*\ - 0~63 + *\*\ - argument + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - type + *\*\ - CARD_CommandTypeNormal + *\*\ - CARD_CommandTypeSuspend + *\*\ - CARD_CommandTypeResume + *\*\ - CARD_CommandTypeAbort + *\*\ - CARD_CommandTypeEmpty + *\*\ - responseType + *\*\ - CARD_ResponseTypeNone + *\*\ - CARD_ResponseTypeR1 + *\*\ - CARD_ResponseTypeR1b + *\*\ - CARD_ResponseTypeR2 + *\*\ - CARD_ResponseTypeR3 + *\*\ - CARD_ResponseTypeR4 + *\*\ - CARD_ResponseTypeR5 + *\*\ - CARD_ResponseTypeR5b + *\*\ - CARD_ResponseTypeR6 + *\*\ - CARD_ResponseTypeR7 + *\*\ - response[4U]: Response for this command. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - responseErrorFlags: Response error flag, which need to check the command reponse. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\ - flags: Cmd flags. + *\*\ - 0x00000000~0xFFFFFFFF + *\*\param TMODE_struct: pointer to a SDHOST_TMODE_struct structure. + *\*\ - DMAE + *\*\ - SDHOST_TMODE_DMADISABLE + *\*\ - SDHOST_TMODE_DMAENABLE + *\*\ - BCNTE + *\*\ - SDHOST_TMODE_BLOCKCNTDISABLE + *\*\ - SDHOST_TMODE_BLOCKCNTENABLE + *\*\ - ACMDE + *\*\ - SDHOST_TMODE_NOACMDEN + *\*\ - SDHOST_TMODE_AC12EN + *\*\ - SDHOST_TMODE_AC23EN + *\*\ - DATDIR + *\*\ - SDHOST_TMODE_DATDIR_WRITE + *\*\ - SDHOST_TMODE_DATDIR_READ + *\*\ - BLKSEL + *\*\ - SDHOST_TMODE_SINGLEBLK + *\*\ - SDHOST_TMODE_MULTIBLK + *\*\return SDMMC_STS + *\*\ - SDMMC_ReTuningRequest + *\*\ - SDMMC_ERROR. + *\*\ - SDMMC_SUCCESS. + *\*\ - SDMMC_DMADataAddrNotAlign + *\*\ - SDMMC_OutOfRange + *\*\ - SDMMC_BusyTransferring + *\*\ - SDMMC_SendCommandFailed + *\*\ - SDMMC_TransferDataFailed + */ +SDMMC_STS SDMMC_TransferBlocking(SDHOST_Module* SDHOSTx, SDHOST_ADMAconfig *dmaConfig, SDMMC_Transfer *transfer, SDHOST_TMODE_struct *TMODE_struct) +{ + SDMMC_STS status_value = SDMMC_ERROR; + SDMMC_CMD *command = &transfer->command; + SDMMC_DATA *data = &transfer->data; + FunctionalState enDMA = ENABLE; + FunctionalState CMDdone; + bool executeTuning = ((data == NULL) ? false : (data->dataType == (uint32_t)SDHOST_TransferDataTuning)); + uint32_t transferFlags = (uint32_t)SDMMC_CommandOnly; + uint32_t blockSize = 0U; + uint32_t blockCount = 0U; + SDHOST_capability Capability; + + SDMMC_GetCapability(SDHOSTx, &Capability); + + if(Capability.SDR50 == SDHOST_CAP1_SDR50_MASK) + { + /*check re-tuning request*/ + if ((SDMMC_GetFlagStatus(SDHOSTx, (uint32_t)SDHOST_ReTuningEventFlag)) != RESET) + { + SDMMC_ClrFlag(SDHOSTx, (uint32_t)SDHOST_ReTuningEventFlag); + return SDMMC_ReTuningRequest; + } + else + { + /* no process */ + } + } + else + { + /* no process */ + } + + if (data != NULL) + { + /* Update ADMA descriptor table according to different DMA mode(SDMA, ADMA2).*/ + if ((dmaConfig != NULL) && (!executeTuning)) + { + status_value = SDMMC_SetAdmaTableConfig(SDHOSTx, dmaConfig, data, TMODE_struct); + } + + blockSize = data->blockSize; + blockCount = data->blockCount; + + if(data->AutoCommand12_23 == AutoCommand12) + { + transferFlags = (uint32_t)SDMMC_DataWithAutoCmd12; + } + else if(data->AutoCommand12_23 == AutoCommand23) + { + transferFlags = (uint32_t)SDMMC_DataWithAutoCmd23; + } + else + { + transferFlags = 0; + } + + transferFlags |= ((data->txData != NULL) ? (uint32_t)SDMMC_CommandAndTxData : (uint32_t)SDMMC_CommandAndRxData); + transferFlags |= ((data->dataType == (uint8_t)SDHOST_TransferDataBoot) ? (uint32_t)SDMMC_BootData : 0U); + transferFlags |= + ((data->dataType == (uint8_t)SDHOST_TransferDataBootcontinous) ? (uint32_t)SDMMC_BootDataContinuous : 0U); + + command->flags |= (uint32_t)SDHOST_DataPresentFlag; + } + + /* if the DMA desciptor configure fail or not needed , disable it */ + if (status_value != SDMMC_SUCCESS) + { + enDMA = DISABLE; + /* disable DMA, using polling mode in this situation */ + TMODE_struct->DMAE = SDHOST_TMODE_DMADISABLE; + } + + /* config the data transfer parameter */ + status_value = SDMMC_TransferConfig(SDHOSTx, transferFlags, blockSize, blockCount, TMODE_struct); + + if (status_value != SDMMC_SUCCESS) + { + return status_value; + } + + /* send command first */ + SDMMC_SendCommand(SDHOSTx, command, TMODE_struct); + + /* wait command done */ + if(data->dataType == (uint32_t)SDHOST_TransferDataNormal) + { + CMDdone = ENABLE; + } + else + { + CMDdone = DISABLE; + } + + status_value = SDMMC_WaitCommandDone(SDHOSTx, command, CMDdone); + + if (SDMMC_SUCCESS != status_value) + { + return SDMMC_SendCommandFailed; + } + + /* wait transfer data finsih */ + if (data != NULL) + { + status_value = SDMMC_TransferDataBlocking(SDHOSTx, data, enDMA); + + if (SDMMC_SUCCESS != status_value) + { + return status_value; + } + } + + return SDMMC_SUCCESS; +} + + + +/** + *\*\name SDMMC_EnableManualTuning. + *\*\fun Manually adjust SDCLK output delay. + *\*\param SDMMCx : + *\*\ - SDMMC1 + *\*\ - SDMMC2 + *\*\param delay : + *\*\ - 0x00~0x0F 1~16 delay tap + *\*\param cmd : + *\*\ - ENABLE + *\*\ - DISABLE + *\*\note When manually adjusting, SDHOST should not be in working state (transmission state). + *\*\note After executing this function, it is necessary to call the enable parameter of SDMMC_SampleClockSet API. + */ +void SDMMC_EnableManualTuningOut(SDMMC_Module* SDMMCx, uint32_t delay, FunctionalState cmd) +{ + SDMMCx->DLYCTRL &= (~SDMMC_MANUALTUNOUT_DELAYMASK); + SDMMCx->DLYCTRL |= (delay << REG_BIT7_OFFSET); + + if (cmd == ENABLE) + { + SDMMCx->DLYCTRL |= SDMMC_MANUALTUNOUT_EN; + } + else + { + SDMMCx->DLYCTRL &= (~SDMMC_MANUALTUNOUT_EN); + } +} + + +/** + *\*\name SDMMC_EnableManualTuningIN. + *\*\fun Manually adjust rxclk input delay. + *\*\param SDMMCx : + *\*\ - SDMMC1 + *\*\ - SDMMC2 + *\*\param delay : + *\*\ - 0x00~0x1F 1~32 delay tap + *\*\param cmd : + *\*\ - ENABLE + *\*\ - DISABLE + *\*\note When manually adjusting, SDHOST should not be in working state (transmission state). + *\*\note After executing this function, it is necessary to call the enable parameter of SDMMC_SampleClockSet API. + */ +void SDMMC_EnableManualTuningIN(SDMMC_Module* SDMMCx, uint32_t delay, FunctionalState cmd) +{ + SDMMCx->DLYCTRL &= (~SDMMC_MANUALTUNGATE_EN); + + SDMMCx->DLYCTRL &= (~SDMMC_MANUALTUNIN_DELAYMASK); + SDMMCx->DLYCTRL |= delay; + + if (cmd == ENABLE) + { + SDMMCx->DLYCTRL |= SDMMC_MANUALTUNIN_EN; + SDMMCx->DLYCTRL |= SDMMC_MANUALTUNGATE_EN; + } + else + { + SDMMCx->DLYCTRL &= (~SDMMC_MANUALTUNIN_EN); + } +} + +/** + *\*\name SDMMC_FixedSampleClock. + *\*\fun Fixed clock for data sampling. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\return none. + */ +void SDMMC_FixedSampleClock(SDHOST_Module* SDHOSTx) +{ + SDHOSTx->CTRLSTS &= (~SDHOST_SAMPCLKSEL); +} + +/** + *\*\name SDMMC_EnableAutoTuning. + *\*\fun the auto tuning enbale for CMD/DATA line. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param cmd : + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none. + */ +void SDMMC_EnableAutoTuning(SDHOST_Module* SDHOSTx, FunctionalState cmd) +{ + if (cmd == ENABLE) + { + SDHOSTx->CTRLSTS |= SDHOST_AUTOTUNE; + } + else + { + SDHOSTx->CTRLSTS &= (~SDHOST_AUTOTUNE); + } +} + + +/** + *\*\name SDMMC_ConfigInt. + *\*\fun Enables or disables the interrupt signal corresponding to the interrupt status flag. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_Flag : + *\*\ - SDHOST_CommandCompleteFlag + *\*\ - SDHOST_DataCompleteFlag + *\*\ - SDHOST_BlockGapEventFlag + *\*\ - SDHOST_DmaCompleteFlag + *\*\ - SDHOST_BufferWriteReadyFlag + *\*\ - SDHOST_BufferReadReadyFlag + *\*\ - SDHOST_CardInsertionFlag + *\*\ - SDHOST_CardRemovalFlag + *\*\ - SDHOST_CardInterruptFlag + *\*\ - SDHOST_ReTuningEventFlag + *\*\ - SDHOST_BootACKRcvFlag + *\*\ - SDHOST_BootTerminateFlag + *\*\ - SDHOST_CommandTimeoutFlag + *\*\ - SDHOST_CommandCrcErrorFlag + *\*\ - SDHOST_CommandEndBitErrorFlag + *\*\ - SDHOST_CommandIndexErrorFlag + *\*\ - SDHOST_DataTimeoutFlag + *\*\ - SDHOST_DataCrcErrorFlag + *\*\ - SDHOST_DataEndBitErrorFlag + *\*\ - SDHOST_AutoCommand12ErrorFlag + *\*\ - SDHOST_DmaErrorFlag + *\*\ - SDHOST_TargetResErrorFlag + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none. + */ +void SDMMC_ConfigInt(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + SDHOSTx->ISE |= SDHOST_Flag; + } + else + { + SDHOSTx->ISE &= (~SDHOST_Flag); + } +} + + +/** + *\*\name SDMMC_EnableFlagStatus. + *\*\fun Can the enable/disable interrupt status be displayed. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_Flag : + *\*\ - SDHOST_CommandCompleteFlag + *\*\ - SDHOST_DataCompleteFlag + *\*\ - SDHOST_BlockGapEventFlag + *\*\ - SDHOST_DmaCompleteFlag + *\*\ - SDHOST_BufferWriteReadyFlag + *\*\ - SDHOST_BufferReadReadyFlag + *\*\ - SDHOST_CardInsertionFlag + *\*\ - SDHOST_CardRemovalFlag + *\*\ - SDHOST_CardInterruptFlag + *\*\ - SDHOST_ReTuningEventFlag + *\*\ - SDHOST_BootACKRcvFlag + *\*\ - SDHOST_BootTerminateFlag + *\*\ - SDHOST_CommandTimeoutFlag + *\*\ - SDHOST_CommandCrcErrorFlag + *\*\ - SDHOST_CommandEndBitErrorFlag + *\*\ - SDHOST_CommandIndexErrorFlag + *\*\ - SDHOST_DataTimeoutFlag + *\*\ - SDHOST_DataCrcErrorFlag + *\*\ - SDHOST_DataEndBitErrorFlag + *\*\ - SDHOST_AutoCommand12ErrorFlag + *\*\ - SDHOST_DmaErrorFlag + *\*\ - SDHOST_TargetResErrorFlag + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none. + */ +void SDMMC_EnableFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + SDHOSTx->IE |= SDHOST_Flag; + } + else + { + SDHOSTx->IE &= (~SDHOST_Flag); + } +} + +/** + *\*\name SDMMC_GetEnableFlagStatus. + *\*\fun Gets the enabled interrupt status. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_Flag : + *\*\ - SDHOST_CommandCompleteFlag + *\*\ - SDHOST_DataCompleteFlag + *\*\ - SDHOST_BlockGapEventFlag + *\*\ - SDHOST_DmaCompleteFlag + *\*\ - SDHOST_BufferWriteReadyFlag + *\*\ - SDHOST_BufferReadReadyFlag + *\*\ - SDHOST_CardInsertionFlag + *\*\ - SDHOST_CardRemovalFlag + *\*\ - SDHOST_CardInterruptFlag + *\*\ - SDHOST_ReTuningEventFlag + *\*\ - SDHOST_BootACKRcvFlag + *\*\ - SDHOST_BootTerminateFlag + *\*\ - SDHOST_CommandTimeoutFlag + *\*\ - SDHOST_CommandCrcErrorFlag + *\*\ - SDHOST_CommandEndBitErrorFlag + *\*\ - SDHOST_CommandIndexErrorFlag + *\*\ - SDHOST_DataTimeoutFlag + *\*\ - SDHOST_DataCrcErrorFlag + *\*\ - SDHOST_DataEndBitErrorFlag + *\*\ - SDHOST_AutoCommand12ErrorFlag + *\*\ - SDHOST_DmaErrorFlag + *\*\ - SDHOST_TargetResErrorFlag + *\*\return none. + */ +FlagStatus SDMMC_GetEnableFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag) +{ + FlagStatus bitstatus; + + if ((SDHOSTx->IE & SDHOST_Flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** + *\*\name SDMMC_GetFlagStatus. + *\*\fun Checks whether the specified SDHOST flag is set or not. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_Flag : + *\*\ - SDHOST_CommandCompleteFlag + *\*\ - SDHOST_DataCompleteFlag + *\*\ - SDHOST_BlockGapEventFlag + *\*\ - SDHOST_DmaCompleteFlag + *\*\ - SDHOST_BufferWriteReadyFlag + *\*\ - SDHOST_BufferReadReadyFlag + *\*\ - SDHOST_CardInsertionFlag + *\*\ - SDHOST_CardRemovalFlag + *\*\ - SDHOST_CardInterruptFlag + *\*\ - SDHOST_ReTuningEventFlag + *\*\ - SDHOST_BootACKRcvFlag + *\*\ - SDHOST_BootTerminateFlag + *\*\ - SDHOST_AllErrorFlag + *\*\ - SDHOST_CommandTimeoutFlag + *\*\ - SDHOST_CommandCrcErrorFlag + *\*\ - SDHOST_CommandEndBitErrorFlag + *\*\ - SDHOST_CommandIndexErrorFlag + *\*\ - SDHOST_DataTimeoutFlag + *\*\ - SDHOST_DataCrcErrorFlag + *\*\ - SDHOST_DataEndBitErrorFlag + *\*\ - SDHOST_AutoCommand12ErrorFlag + *\*\ - SDHOST_DmaErrorFlag + *\*\ - SDHOST_TargetResErrorFlag + *\*\return bitstatus. + *\*\ - SET + *\*\ - RESET + */ +FlagStatus SDMMC_GetFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag) +{ + FlagStatus bitstatus; + + if ((SDHOSTx->INTSTS & SDHOST_Flag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** + *\*\name SDMMC_ClrFlag. + *\*\fun This function is used to clear a specified interrupt status. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_Flag : + *\*\ - SDHOST_CommandCompleteFlag + *\*\ - SDHOST_DataCompleteFlag + *\*\ - SDHOST_BlockGapEventFlag + *\*\ - SDHOST_DmaCompleteFlag + *\*\ - SDHOST_BufferWriteReadyFlag + *\*\ - SDHOST_BufferReadReadyFlag + *\*\ - SDHOST_CardInsertionFlag + *\*\ - SDHOST_CardRemovalFlag + *\*\ - SDHOST_ReTuningEventFlag + *\*\ - SDHOST_BootACKRcvFlag + *\*\ - SDHOST_BootTerminateFlag + *\*\ - SDHOST_CommandTimeoutFlag + *\*\ - SDHOST_CommandCrcErrorFlag + *\*\ - SDHOST_CommandEndBitErrorFlag + *\*\ - SDHOST_CommandIndexErrorFlag + *\*\ - SDHOST_DataTimeoutFlag + *\*\ - SDHOST_DataCrcErrorFlag + *\*\ - SDHOST_DataEndBitErrorFlag + *\*\ - SDHOST_AutoCommand12ErrorFlag + *\*\ - SDHOST_DmaErrorFlag + *\*\ - SDHOST_TargetResErrorFlag + *\*\return none. + */ +void SDMMC_ClrFlag(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag) +{ + SDHOSTx->INTSTS = SDHOST_Flag; +} + + +/** + *\*\name SDMMC_EnableForceEvent. + *\*\fun Forces generating events according to the given mask. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_Flag : + *\*\ - SDHOST_ForceEventAutoCommand12NotExecuted + *\*\ - SDHOST_ForceEventAutoCommand12Timeout + *\*\ - SDHOST_ForceEventAutoCommand12CrcError + *\*\ - SDHOST_ForceEventAutoCommandEndBitError + *\*\ - SDHOST_ForceEventAutoCommand12IndexError + *\*\ - SDHOST_ForceEventAutoCommand12NotIssued + *\*\ - SDHOST_ForceEventCommandTimeout + *\*\ - SDHOST_ForceEventCommandCrcError + *\*\ - SDHOST_ForceEventCommandEndBitError + *\*\ - SDHOST_ForceEventCommandIndexError + *\*\ - SDHOST_ForceEventDataTimeout + *\*\ - SDHOST_ForceEventDataCrcError + *\*\ - SDHOST_ForceEventDataEndBitError + *\*\ - SDHOST_ForceEventAutoCommand12Error + *\*\ - SDHOST_ForceEventAdmaError + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none. + */ +void SDMMC_EnableForceEvent(SDHOST_Module* SDHOSTx, uint32_t SDHOST_Flag, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + SDHOSTx->STSFE |= SDHOST_Flag; + } + else + { + SDHOSTx->STSFE &= (~SDHOST_Flag); + } +} + + +/** + *\*\name SDMMC_GetPresentFlagStatus. + *\*\fun Checks whether the specified SDHOST Present flag is set or not. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_PreFlag : + *\*\ - SDHOST_CommandInhibitFlag + *\*\ - SDHOST_DataInhibitFlag + *\*\ - SDHOST_DataLineActiveFlag + *\*\ - SDHOST_ReTuningRequestFlag + *\*\ - SDHOST_WriteTransferActiveFlag + *\*\ - SDHOST_ReadTransferActiveFlag + *\*\ - SDHOST_BufferWriteEnableFlag + *\*\ - SDHOST_BufferReadEnableFlag + *\*\ - SDHOST_CardInsertedFlag + *\*\ - SDHOST_CardStateStableFlag + *\*\ - SDHOST_CardDetectPinFlag + *\*\ - SDHOST_CardWPSwitchPinFlag + *\*\ - SDHOST_CommandLineLevelFlag + *\*\ - SDHOST_Data0LineLevelFlag + *\*\ - SDHOST_Data1LineLevelFlag + *\*\ - SDHOST_Data2LineLevelFlag + *\*\ - SDHOST_Data3LineLevelFlag + *\*\ - SDHOST_Data4LineLevelFlag + *\*\ - SDHOST_Data5LineLevelFlag + *\*\ - SDHOST_Data6LineLevelFlag + *\*\ - SDHOST_Data7LineLevelFlag + *\*\return bitstatus. + *\*\ - SET + *\*\ - RESET + *\*\return none. + */ +FlagStatus SDMMC_GetPresentFlagStatus(SDHOST_Module* SDHOSTx, uint32_t SDHOST_PreFlag) +{ + FlagStatus bitstatus; + + if ((SDHOSTx->PRESTS & SDHOST_PreFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** + *\*\name SDMMC_GetACMDErrorStatusFlag. + *\*\fun Gets the status of auto command 12/23 error. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_PreFlag : + *\*\ - SDHOST_AutoCommand12NotExecutedFlag + *\*\ - SDHOST_AutoCommand12TimeoutFlag + *\*\ - SDHOST_AutoCommand12EndBitErrorFlag + *\*\ - SDHOST_AutoCommand12CrcErrorFlag + *\*\ - SDHOST_AutoCommand12IndexErrorFlag + *\*\ - SDHOST_AutoCommand12NotIssuedFlag + *\*\return bitstatus. + *\*\ - SET + *\*\ - RESET + *\*\return none. + */ +FlagStatus SDMMC_GetACMDErrorStatusFlag(SDHOST_Module* SDHOSTx, uint32_t SDHOST_ACMDFlag) +{ + FlagStatus bitstatus; + + if ((SDHOSTx->CTRLSTS & SDHOST_ACMDFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** + *\*\name SDMMC_GetADMAErrorStatusFlag. + *\*\fun Gets the status of ADMA error. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param SDHOST_PreFlag : + *\*\ - SDHOST_AdmaLenghMismatchFlag + *\*\return bitstatus. + *\*\ - SET + *\*\ - RESET + *\*\return none. + */ +FlagStatus SDMMC_GetADMAErrorStatusFlag(SDHOST_Module* SDHOSTx, uint32_t SDHOST_ADMAFlag) +{ + FlagStatus bitstatus; + + if ((SDHOSTx->ADMAESTS & SDHOST_ADMAFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** + *\*\name SDMMC_EnableHWReset + *\*\fun Triggers a hardware reset. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableHWReset(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HWRST; + } + else + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_HWRST); + } +} + + +/** + *\*\name SDMMC_ConfigWorkMode + *\*\fun Configure working mode. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param mode (The input parameters must be the following values): + *\*\ - SDMMC_DS + *\*\ - SDMMC_HS + *\*\ - SDMMC_SDR12 + *\*\ - SDMMC_SDR25 + *\*\ - SDMMC_SDR50 + *\*\ - SDMMC_SDR104 + *\*\ - SDMMC_DDR50 + *\*\ - SDMMC_SPI + *\*\return none + */ +void SDMMC_ConfigWorkMode(SDHOST_Module* SDHOSTx, SD_ModeConfig mode) +{ + if(mode == SDMMC_SPI) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_SPIMODE; + } + else + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_SPIMODE); + + if (mode == SDMMC_DS) + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_HSEN); + } + else if (mode == SDMMC_HS) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HSEN; + } + else if(mode == SDMMC_SDR12) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HSEN; + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_UHSMOD); + } + else if(mode == SDMMC_SDR25) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HSEN; + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_UHSMOD); + SDHOSTx->CTRLSTS |= SDHOST_CTRLSTS_UHSMOD_0; + } + else if(mode == SDMMC_SDR50) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HSEN; + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_UHSMOD); + SDHOSTx->CTRLSTS |= SDHOST_CTRLSTS_UHSMOD_1; + } + else if(mode == SDMMC_SDR104) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HSEN; + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_UHSMOD); + SDHOSTx->CTRLSTS |= (SDHOST_CTRLSTS_UHSMOD_0 | SDHOST_CTRLSTS_UHSMOD_1); + } + else + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_HSEN; + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_UHSMOD); + SDHOSTx->CTRLSTS |= SDHOST_CTRLSTS_UHSMOD_2; + } + } +} + + +/** + *\*\name SDMMC_ConfigBusWidth + *\*\fun Sets the data transfer width. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Width (The input parameters must be the following values): + *\*\ - SDHOST_DataBusWidth1Bit + *\*\ - SDHOST_DataBusWidth4Bit + *\*\ - SDHOST_DataBusWidth8Bit + *\*\return none + */ +void SDMMC_ConfigBusWidth(SDHOST_Module* SDHOSTx, SDHOST_BusWidth Width) +{ + if (Width != SDHOST_DataBusWidth8Bit) + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_EDTWIDTH); + + if (Width != SDHOST_DataBusWidth4Bit) + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_DTWIDTH); + } + else + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_DTWIDTH; + } + } + else + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_EDTWIDTH; + } +} + + +/** + *\*\name SDMMC_WriteData. + *\*\fun This function is used to implement the data transfer by Data Port instead of DMA. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\return none. + */ +void SDMMC_WriteData(SDHOST_Module* SDHOSTx, uint32_t data) +{ + SDHOSTx->BUFDAT = data; +} + +/** + *\*\name SDMMC_ReadData. + *\*\fun This function is used to implement the data transfer by Data Port instead of DMA. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\return The data has been read. + */ +uint32_t SDMMC_ReadData(SDHOST_Module* SDHOSTx) +{ + return SDHOSTx->BUFDAT; +} + + +/** + *\*\name SDMMC_EnableWakeupEvent + *\*\fun Enables or disables a wakeup event. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Wakeupevent : + *\*\ - SDHOST_WakeupEventOnCardInt + *\*\ - SDHOST_WakeupEventOnCardInsert + *\*\ - SDHOST_WakeupEventOnCardRemove + *\*\ - SDHOST_WakeupEventsAll + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableWakeupEvent(SDHOST_Module* SDHOSTx, uint32_t Wakeupevent, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL1 |= Wakeupevent; + } + else + { + SDHOSTx->CTRL1 &= (~Wakeupevent); + } +} + + +/** + *\*\name SDMMC_EnableSdioControl + *\*\fun Enables or disables the SDIO card control. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Wakeupevent : + *\*\ - SDHOST_StopAtBlockGapFlag + *\*\ - SDHOST_ReadWaitControlFlag + *\*\ - SDHOST_InterruptAtBlockGapFlag + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableSdioControl(SDHOST_Module* SDHOSTx, uint32_t Sdioflag, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL1 |= Sdioflag; + } + else + { + SDHOSTx->CTRL1 &= (~Sdioflag); + } +} + + +/** + *\*\name SDMMC_EnableContinueRequest + *\*\fun Restarts a transaction which has stopped at the block GAP for the SDIO card. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\return none + */ +void SDMMC_EnableContinueRequest(SDHOST_Module* SDHOSTx) +{ + SDHOSTx->CTRL1 |= SDHOST_CTRL1_CONTREQ; +} + + +/** + *\*\name SDMMC_EnableMmcBoot + *\*\fun Enables or disables the mmc boot mode. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableMmcBoot(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_BOOTEN; + } + else + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_BOOTEN); + } +} + + +/** + *\*\name SDMMC_EnableVolSwitch + *\*\fun Enables or disables voltage switching, signal voltage will change from 3.3V to 1.8V. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableVolSwitch(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRLSTS |= SDHOST_CTRLSTS_V18SE; + } + else + { + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_V18SE); + } +} + + +/** + *\*\name SDMMC_EnablePower + *\*\fun Enables or disables SD Bus Power. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnablePower(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_SDBVSEL; + SDHOSTx->CTRL1 |= SDHOST_CTRL1_SDPWR; + } + else + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_SDPWR); + } +} + + +/** + *\*\name SDMMC_ConfigSDMABufferSize + *\*\fun Config Host SDMA Buffer Size. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Size (The input parameters must be the following values): + *\*\ - SDHOST_SDMABUFFERSIZE_4KB + *\*\ - SDHOST_SDMABUFFERSIZE_8KB + *\*\ - SDHOST_SDMABUFFERSIZE_16KB + *\*\ - SDHOST_SDMABUFFERSIZE_32KB + *\*\ - SDHOST_SDMABUFFERSIZE_64KB + *\*\ - SDHOST_SDMABUFFERSIZE_128KB + *\*\ - SDHOST_SDMABUFFERSIZE_256KB + *\*\ - SDHOST_SDMABUFFERSIZE_512KB + *\*\return none + */ +void SDMMC_ConfigSDMABufferSize(SDHOST_Module* SDHOSTx, SDHOST_SDMA_Buffer_Size Size) +{ + SDHOSTx->BLKCFG &= (~SDHOST_BLKCFG_HDBS); + SDHOSTx->BLKCFG |= (uint32_t)Size; +} + + +/** + *\*\name SDMMC_TModeStructInit. + *\*\fun Fills each TMODE_struct member with its default value.. + *\*\param TMODE_struct: pointer to a SDHOST_TMODE_struct structure. + *\*\ - DMAE + *\*\ - SDHOST_TMODE_DMADISABLE + *\*\ - SDHOST_TMODE_DMAENABLE + *\*\ - BCNTE + *\*\ - SDHOST_TMODE_BLOCKCNTDISABLE + *\*\ - SDHOST_TMODE_BLOCKCNTENABLE + *\*\ - ACMDE + *\*\ - SDHOST_TMODE_NOACMDEN + *\*\ - SDHOST_TMODE_AC12EN + *\*\ - SDHOST_TMODE_AC23EN + *\*\ - DATDIR + *\*\ - SDHOST_TMODE_DATDIR_WRITE + *\*\ - SDHOST_TMODE_DATDIR_READ + *\*\ - BLKSEL + *\*\ - SDHOST_TMODE_SINGLEBLK + *\*\ - SDHOST_TMODE_MULTIBLK + *\*\return none + */ +void SDMMC_TModeStructInit(SDHOST_TMODE_struct *TMODE_struct) +{ + /* TMODE_struct members default value */ + TMODE_struct->DMAE = SDHOST_TMODE_DMADISABLE; + TMODE_struct->BCNTE = SDHOST_TMODE_BLOCKCNTDISABLE; + TMODE_struct->ACMDE = SDHOST_TMODE_NOACMDEN; + TMODE_struct->DATDIR = SDHOST_TMODE_DATDIR_WRITE; + TMODE_struct->BLKSEL = SDHOST_TMODE_SINGLEBLK; +} + + +/** + *\*\name SDMMC_ConfigCardDetectSignal + *\*\fun Config card detect signal source and test level. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Signalsource (The input parameters must be the following values): + *\*\ - SDMMC_CARDDETECT_NORMAL + *\*\ - SDMMC_CARDDETECT_TEST + *\*\param Signallevel (The input parameters must be the following values): + *\*\ - SDMMC_CARDTESTLEVEL_LOW + *\*\ - SDMMC_CARDTESTLEVEL_HIGH + *\*\return none + */ +void SDMMC_ConfigCardDetectSignal(SDHOST_Module* SDHOSTx, uint32_t Signalsource, uint32_t Signallevel) +{ + SDHOSTx->CTRL1 &= (~(SDMMC_CARDDETECT_TEST | SDMMC_CARDTESTLEVEL_HIGH)); + SDHOSTx->CTRL1 |= (Signalsource | Signallevel); +} + + +/** + *\*\name SDMMC_EnableLED + *\*\fun Enables or disables LED. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableLED(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRL1 |= SDHOST_CTRL1_LEDCTRL; + } + else + { + SDHOSTx->CTRL1 &= (~SDHOST_CTRL1_LEDCTRL); + } +} + + +/** + *\*\name SDMMC_EnableAsyncInt + *\*\fun Enables or disables Asynchronous Interrupt. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Cmd (The input parameters must be the following values): + *\*\ - ENABLE + *\*\ - DISABLE + *\*\return none + */ +void SDMMC_EnableAsyncInt(SDHOST_Module* SDHOSTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + SDHOSTx->CTRLSTS |= SDHOST_CTRLSTS_ASYNCIE; + } + else + { + SDHOSTx->CTRLSTS &= (~SDHOST_CTRLSTS_ASYNCIE); + } +} + + +/** + *\*\name SDMMC_ConfigDATATimeoutValue + *\*\fun Config Data Level Timeout Counter Value. + *\*\param SDHOSTx : + *\*\ - SDHOST1 + *\*\ - SDHOST2 + *\*\param Count (The input parameters must be the following values): + *\*\ - 0x0~0xF , The corresponding actual delay value is (1/TMCLK * 2^(Count + 13)) + *\*\return none + */ +void SDMMC_ConfigDATATimeoutValue(SDHOST_Module* SDHOSTx, uint32_t Count) +{ + SDHOSTx->CTRL2 &= (~SDHOST_CTRL2_DTCNT); + SDHOSTx->CTRL2 |= (Count << REG_BIT16_OFFSET); +} + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdram.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdram.c new file mode 100644 index 0000000000..0f91816f70 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_sdram.c @@ -0,0 +1,694 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_sdram.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_sdram.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name SDRAM_DeInit. +*\*\fun Deinitializes the SDRAM module to their default reset values. +*\*\param none +*\*\return none +**/ +void SDRAM_DeInit(void) +{ + /* SDRAM soft reset */ + RCC_EnableAXIPeriphReset4(RCC_AXI_PERIPHRST_SDRAM); +} + +/** +*\*\name SDRAM_TimingInit. +*\*\fun SDRAM Timing Registers Configuration. +*\*\param Timing: The parameter range is as follows +*\*\ - RowActiveTime : from 1 to 64 +*\*\ - RowCycleTime : from 1 to 64 +*\*\ - RowActToRowActDelay : from 1 to 64 +*\*\ - PrechargeTime : from 1 to 64 +*\*\ - WriteRecoveryTime : from 1 to 64 +*\*\ - RefreshCycleTime : from 1 to 64 +*\*\ - RAStoCASDelay : from 1 to 16 +*\*\return none +**/ +void SDRAM_TimingInit(SDRAM_TimingType *Timing) +{ + SDRAM->RAT = Timing->RowActiveTime; + SDRAM->RCT = Timing->RowCycleTime; + SDRAM->RRDLY = Timing->RowActToRowActDelay; + SDRAM->PT = Timing->PrechargeTime; + SDRAM->WRT = Timing->WriteRecoveryTime; + SDRAM->RFCT = Timing->RefreshCycleTime; + SDRAM->RCDLY = Timing->RAStoCASDelay; +} + +/** +*\*\name SDRAM_RefreshIntervalInit. +*\*\fun Configure the refresh interval parameter. +*\*\param The input parameters must be the following values: +*\*\ - RefreshIntervalTime: from 1 to 16777216 +*\*\return none +**/ +void SDRAM_RefreshIntervalInit(uint32_t RefreshIntervalTime) +{ + SDRAM->RI = RefreshIntervalTime; +} + +/** +*\*\name SDRAM_SetAddress. +*\*\fun SDRAM set Base Address and mask address. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - BaseAddr +*\*\ - 0xC0000000 Default value for SDRAM1 +*\*\ - 0xD0000000 Default value for SDRAM2 +*\*\ - AddrMask +*\*\ - (0xFFFFFFFF-(SDRAM SIZE-1)) +*\*\return none +**/ +void SDRAM_SetDeviceAddress(SDRAM_DeviceType DeviceNo, uint32_t BaseAddr, uint32_t AddrMask) +{ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->BADD1 = BaseAddr; + SDRAM->ADDMASK1 = AddrMask; + } + else + { + SDRAM->BADD2 = BaseAddr; + SDRAM->ADDMASK2 = AddrMask; + } +} + +/** +*\*\name SDRAM_EnableDevice. +*\*\fun SDRAM Device enable. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableDevice(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SDRAM Device*/ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 |= SDRAM_DEVICE_ENABLE; + } + else + { + SDRAM->CFG2 |= SDRAM_DEVICE_ENABLE; + } + } + else + { + /* Disable the selected SDRAM Device */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 &= SDRAM_DEVICE_DISABLE; + } + else + { + SDRAM->CFG2 &= SDRAM_DEVICE_DISABLE; + } + } +} + +/** +*\*\name SDRAM_EnableRefreshCMD. +*\*\fun SDRAM Refresh enable of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableRefreshCMD(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SDRAM Refresh */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 |= SDRAM_DEVICE_REFRESH_ENABLE; + } + else + { + SDRAM->CFG2 |= SDRAM_DEVICE_REFRESH_ENABLE; + } + } + else + { + /* Disable the selected SDRAM Refresh */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 &= SDRAM_DEVICE_REFRESH_DISABLE; + } + else + { + SDRAM->CFG2 &= SDRAM_DEVICE_REFRESH_DISABLE; + } + } +} + +/** +*\*\name SDRAM_EnableAutoPrecharge. +*\*\fun SDRAM Auto Precharge enable of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableAutoPrecharge(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SDRAM Auto Precharge */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 |= SDRAM_DEVICE_AUTOPRECHRG_ENABLE; + } + else + { + SDRAM->CFG2 |= SDRAM_DEVICE_AUTOPRECHRG_ENABLE; + } + } + else + { + /* Disable the selected SDRAM Auto Precharge */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 &= SDRAM_DEVICE_AUTOPRECHRG_DISABLE; + } + else + { + SDRAM->CFG2 &= SDRAM_DEVICE_AUTOPRECHRG_DISABLE; + } + } +} + +/** +*\*\name SDRAM_EnablePrefetchRead. +*\*\fun SDRAM Prefetch Read enable of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnablePrefetchRead(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SDRAM Prefetch Read */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 |= SDRAM_DEVICE_PREFETCHREAD_ENABLE; + } + else + { + SDRAM->CFG2 |= SDRAM_DEVICE_PREFETCHREAD_ENABLE; + } + } + else + { + /* Disable the selected SDRAM Prefetch Read */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 &= SDRAM_DEVICE_PREFETCHREADG_DISABLE; + } + else + { + SDRAM->CFG2 &= SDRAM_DEVICE_PREFETCHREADG_DISABLE; + } + } +} + +/** +*\*\name SDRAM_EnableSOM. +*\*\fun SDRAM Store On Miss(SOM) enable of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableSOM(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SDRAM Store On Miss(SOM) */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 |= SDRAM_DEVICE_SOM_ENABLE; + } + else + { + SDRAM->CFG2 |= SDRAM_DEVICE_SOM_ENABLE; + } + } + else + { + /* Disable the selected SDRAM Store On Miss(SOM) */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 &= SDRAM_DEVICE_SOM_DISABLE; + } + else + { + SDRAM->CFG2 &= SDRAM_DEVICE_SOM_DISABLE; + } + } +} + +/** +*\*\name SDRAM_EnableBankInterleave. +*\*\fun SDRAM BankInterleave enable of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableBankInterleave(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SDRAM BankInter leave */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 |= SDRAM_DEVICE_BANKIL_ENABLE; + } + else + { + SDRAM->CFG2 |= SDRAM_DEVICE_BANKIL_ENABLE; + } + } + else + { + /* Disable the selected SDRAM Bank Interleave */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->CFG1 &= SDRAM_DEVICE_BANKIL_DISABLE; + } + else + { + SDRAM->CFG2 &= SDRAM_DEVICE_BANKIL_DISABLE; + } + } +} + +/** +*\*\name SDRAM_ConfigBusWidth. +*\*\fun Configures the SDRAM Bus Width of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - BusWidth: +*\*\ - SDRAM_DEVICE_BUSWID_8BITS +*\*\ - SDRAM_DEVICE_BUSWID_16BITS +*\*\ - SDRAM_DEVICE_BUSWID_32BITS +*\*\return none +**/ +void SDRAM_ConfigBusWidth(SDRAM_DeviceType DeviceNo, uint32_t BusWidth) +{ + uint32_t reg_value; + + /* Configures the selected SDRAM Bus Width */ + if(DeviceNo == SDRAM_DEVICE_1) + { + reg_value = SDRAM->CFG1; + reg_value &= SDRAM_DEVICE_BUSWID_MASK; + reg_value |= BusWidth; + SDRAM->CFG1 = reg_value; + } + else + { + reg_value = SDRAM->CFG2; + reg_value &= SDRAM_DEVICE_BUSWID_MASK; + reg_value |= BusWidth; + SDRAM->CFG2 = reg_value; + } +} + +/** +*\*\name SDRAM_ConfigBurstLength. +*\*\fun Configures the SDRAM Burst Length of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - BurstLength: +*\*\ - SDRAM_DEVICE_BURSTLEN_1 +*\*\ - SDRAM_DEVICE_BURSTLEN_2 +*\*\ - SDRAM_DEVICE_BURSTLEN_4 +*\*\ - SDRAM_DEVICE_BURSTLEN_8 +*\*\return none +**/ +void SDRAM_ConfigBurstLength(SDRAM_DeviceType DeviceNo, uint32_t BurstLength) +{ + uint32_t reg_value; + + /* Configures the selected SDRAM Burst Length */ + if(DeviceNo == SDRAM_DEVICE_1) + { + reg_value = SDRAM->CFG1; + reg_value &= SDRAM_DEVICE_BURSTLEN_MASK; + reg_value |= BurstLength; + SDRAM->CFG1 = reg_value; + } + else + { + reg_value = SDRAM->CFG2; + reg_value &= SDRAM_DEVICE_BURSTLEN_MASK; + reg_value |= BurstLength; + SDRAM->CFG2 = reg_value; + } +} + +/** +*\*\name SDRAM_ConfigCASLatency. +*\*\fun Configures the SDRAM CAS Latency of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - CASLatency: +*\*\ - SDRAM_DEVICE_CASLTCY_0 +*\*\ - SDRAM_DEVICE_CASLTCY_1 +*\*\ - SDRAM_DEVICE_CASLTCY_2 +*\*\ - SDRAM_DEVICE_CASLTCY_3 +*\*\return none +**/ +void SDRAM_ConfigCASLatency(SDRAM_DeviceType DeviceNo, uint32_t Latency) +{ + uint32_t reg_value; + + /* Configures the selected SDRAM CAS Latency */ + if(DeviceNo == SDRAM_DEVICE_1) + { + reg_value = SDRAM->CFG1; + reg_value &= SDRAM_DEVICE_CASLTCY_MASK; + reg_value |= Latency; + SDRAM->CFG1 = reg_value; + } + else + { + reg_value = SDRAM->CFG2; + reg_value &= SDRAM_DEVICE_CASLTCY_MASK; + reg_value |= Latency; + SDRAM->CFG2 = reg_value; + } +} + +/** +*\*\name SDRAM_ConfigAddress. +*\*\fun Configures the SDRAM Address of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Address: +*\*\ - SDRAM_BANK4_ROW4096_COL256 +*\*\ - SDRAM_BANK4_ROW4096_COL512 +*\*\ - SDRAM_BANK4_ROW4096_COL1024 +*\*\ - SDRAM_BANK4_ROW4096_COL2048 +*\*\ - SDRAM_BANK4_ROW8192_COL256 +*\*\ - SDRAM_BANK4_ROW8192_COL512 +*\*\ - SDRAM_BANK4_ROW8192_COL1024 +*\*\ - SDRAM_BANK4_ROW8192_COL2048 +*\*\ - SDRAM_BANK4_ROW2048_COL256 +*\*\ - SDRAM_BANK4_ROW2048_COL512 +*\*\ - SDRAM_BANK4_ROW2048_COL1024 +*\*\ - SDRAM_BANK4_ROW2048_COL2048 +*\*\return none +**/ +void SDRAM_ConfigAddress(SDRAM_DeviceType DeviceNo, uint32_t Address) +{ + uint32_t reg_value; + + /* Configures the selected SDRAM Address */ + if(DeviceNo == SDRAM_DEVICE_1) + { + reg_value = SDRAM->CFG1; + reg_value &= SDRAM_DEVICE_ADDCFG_MASK; + reg_value |= Address; + SDRAM->CFG1 = reg_value; + } + else + { + reg_value = SDRAM->CFG2; + reg_value &= SDRAM_DEVICE_ADDCFG_MASK; + reg_value |= Address; + SDRAM->CFG2 = reg_value; + } +} + +/** +*\*\name SDRAM_EnableClock. +*\*\fun SDRAM Clock enable. +*\*\param The input parameters must be the following values: +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableClock(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the SDRAM Clock */ + SDRAM->OS |= SDRAM_CLOCK_ENABLE; + } + else + { + /* Disable the SDRAM Clock */ + SDRAM->OS &= SDRAM_CLOCK_DISABLE; + } +} + +/** +*\*\name SDRAM_SetOperationCode. +*\*\fun Set the SDRAM Operation Code. +*\*\param The input parameters must be the following values: +*\*\ - OperationCode: +*\*\ - SDRAM_OPCODE_NONE +*\*\ - SDRAM_OPCODE_PRECHRG +*\*\ - SDRAM_OPCODE_REFRESH +*\*\ - SDRAM_OPCODE_LOADMODE +*\*\return none +**/ +void SDRAM_SetOperationCode(uint32_t OperationCode) +{ + uint32_t reg_value; + + reg_value = SDRAM->OS; + /* Clear the SDRAM Operation Code */ + reg_value &= SDRAM_OPCODE_MASK; + /* Set the SDRAM Operation Code */ + reg_value |= OperationCode; + SDRAM->OS = reg_value; +} + +/** +*\*\name SDRAM_SetDeviceSelect. +*\*\fun Set the SDRAM Device. +*\*\param The input parameters must be the following values: +*\*\ - ChipSelect: +*\*\ - SDRAM_CS_ALL +*\*\ - SDRAM_CS_SDRAM2_ONLY +*\*\ - SDRAM_CS_SDRAM1_ONLY +*\*\ - SDRAM_CS_NONE +*\*\return none +**/ +void SDRAM_SetDeviceSelect(uint32_t ChipSelect) +{ + uint32_t reg_value; + + reg_value = SDRAM->OS; + /* Clear the SDRAM Device */ + reg_value &= SDRAM_CS_MASK; + /* Set the SDRAM Device */ + reg_value |= ChipSelect; + SDRAM->OS = reg_value; +} + +/** +*\*\name SDRAM_SetBank. +*\*\fun Set the SDRAM Bank. +*\*\param The input parameters must be the following values: +*\*\ - BankNo: +*\*\ - SDRAM_BANKADD_1 +*\*\ - SDRAM_BANKADD_2 +*\*\ - SDRAM_BANKADD_3 +*\*\ - SDRAM_BANKADD_4 +*\*\return none +**/ +void SDRAM_SetBank(uint32_t BankNo) +{ + uint32_t reg_value; + + reg_value = SDRAM->OS; + /* Clear the SDRAM Bank */ + reg_value &= SDRAM_BANKADD_MASK; + /* Set the SDRAM Bank */ + reg_value |= BankNo; + SDRAM->OS = reg_value; +} + +/** +*\*\name SDRAM_SetAddress. +*\*\fun Set the SDRAM Bank. +*\*\param The input parameters must be the following values: +*\*\ - Address: +*\*\return none +**/ +void SDRAM_SetAddress(uint32_t Address) +{ + uint32_t reg_value; + + reg_value = SDRAM->OS; + /* Clear the SDRAM Address */ + reg_value &= SDRAM_OS_ADDRESS_MASK; + /* Set the SDRAM Address */ + reg_value |= (Address & SDRAM_OS_ADD); + SDRAM->OS = reg_value; +} + +/** +*\*\name SDRAM_EnableWriteProtection. +*\*\fun Write protection enable of the selected device. +*\*\param The input parameters must be the following values: +*\*\ - DeviceNo: +*\*\ - SDRAM_DEVICE_1 +*\*\ - SDRAM_DEVICE_2 +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableWriteProtection(SDRAM_DeviceType DeviceNo, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Write protection of selected SDRAM Device*/ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->WP |= SDRAM_WP_SDRAM1_ENABLE; + } + else + { + SDRAM->WP |= SDRAM_WP_SDRAM2_ENABLE; + } + } + else + { + /* Disable the Write protection of selected SDRAM Device */ + if(DeviceNo == SDRAM_DEVICE_1) + { + SDRAM->WP &= SDRAM_WP_SDRAM1_DISABLE; + } + else + { + SDRAM->WP &= SDRAM_WP_SDRAM2_DISABLE; + } + } +} + +/** +*\*\name SDRAM_EnableAddressRemap. +*\*\fun SDRAM1 address remapped from 0xC0000000 to 0x60000000. +*\*\param The input parameters must be the following values: +*\*\ - Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SDRAM_EnableAddressRemap(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + FEMC->FEMC_REMAP = SDRAM_REMAP_ENABLE; + } + else + { + FEMC->FEMC_REMAP = SDRAM_REMAP_DISABLE; + } +} + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_shrtim.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_shrtim.c new file mode 100644 index 0000000000..af183608e2 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_shrtim.c @@ -0,0 +1,10593 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_shrtim.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_shrtim.h" + +/** +*\*\fun Select the SHRTIM synchronization input source. +*\*\note This function must not be called when the concerned timer(s) is (are) enabled . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SyncInSrc This parameter can be one of the following values: +*\*\ - SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_0 from ATIM1 trgo +*\*\ - SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_1 from ATIM2 trgo +*\*\ - SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_2 from ATIM3 trgo +*\*\ - SHRTIM_SYNCIN_SRC_EXTERNAL_EVENT_3 from IOM +*\*\ - SHRRIM_SYNCIN_SRC_INTERNAL_EVENT_4 from shrtim_out_sync2 of another SHRTIM +*\*\return None +**/ +void SHRTIM_SetSyncInSrc(SHRTIM_Module *SHRTIMx, uint32_t SyncInSrc) +{ + MODIFY_REG(SHRTIMx->sMasterRegs.MCTRL, SHRTIM_MCTRL_SYNCIN, SyncInSrc); +} + +/** +*\*\fun Get actual SHRTIM synchronization input source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return SyncInSrc Returned value can be one of the following values: +*\*\ - SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_0 from ATIM1 trgo +*\*\ - SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_1 from ATIM2 trgo +*\*\ - SHRTIM_SYNCIN_SRC_INTERNAL_EVENT_2 from ATIM3 trgo +*\*\ - SHRTIM_SYNCIN_SRC_EXTERNAL_EVENT_3 from IOM +*\*\ - SHRRIM_SYNCIN_SRC_EXTERNAL_EVENT_4 from shrtim_out_sync2 of another SHRTIM +**/ +uint32_t SHRTIM_GetSyncInSrc(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sMasterRegs.MCTRL, SHRTIM_MCTRL_SYNCIN)); +} + +/** +*\*\fun Configure the SHRTIM synchronization output. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Config This parameter can be one of the following values: +*\*\ - SHRTIM_SYNCOUT_DISABLED +*\*\ - SHRTIM_SYNCOUT_POSITIVE_PULSE +*\*\ - SHRTIM_SYNCOUT_NEGATIVE_PULSE +*\*\param Src This parameter can be one of the following values: +*\*\ - SHRTIM_SYNCOUT_SRC_MASTER_START +*\*\ - SHRTIM_SYNCOUT_SRC_MASTER_CMP1 +*\*\ - SHRTIM_SYNCOUT_SRC_TIMA_START +*\*\ - SHRTIM_SYNCOUT_SRC_TIMA_CMP1 +*\*\return None +**/ +void SHRTIM_ConfigSyncOut(SHRTIM_Module *SHRTIMx, uint32_t Config, uint32_t Src) +{ + MODIFY_REG(SHRTIMx->sMasterRegs.MCTRL, SHRTIM_MCTRL_SYNCOSRC, Src); + MODIFY_REG(SHRTIMx->sMasterRegs.SYNCOUT, SHRTIM_SYNCOUT_SYNCOUTPUS, Config); +} + +/** +*\*\fun Set the routing and conditioning of the syncout event. +*\*\note This function can be called only when the master timer is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SyncOutConfig This parameter can be one of the following values: +*\*\ - SHRTIM_SYNCOUT_DISABLED +*\*\ - SHRTIM_SYNCOUT_POSITIVE_PULSE +*\*\ - SHRTIM_SYNCOUT_NEGATIVE_PULSE +*\*\return None +**/ +void SHRTIM_SetSyncOutConfig(SHRTIM_Module *SHRTIMx, uint32_t SyncOutConfig) +{ + MODIFY_REG(SHRTIMx->sMasterRegs.SYNCOUT, SHRTIM_SYNCOUT_SYNCOUTPUS, SyncOutConfig); +} + +/** +*\*\fun Get actual routing and conditioning of the syncout event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return SyncOutConfig Returned value can be one of the following values: +*\*\ - SHRTIM_SYNCOUT_DISABLED +*\*\ - SHRTIM_SYNCOUT_POSITIVE_PULSE +*\*\ - SHRTIM_SYNCOUT_NEGATIVE_PULSE +**/ +uint32_t SHRTIM_GetSyncOutConfig(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sMasterRegs.SYNCOUT, SHRTIM_SYNCOUT_SYNCOUTPUS)); +} + +/** +*\*\fun Set the source and event to be sent on the SHRTIM synchronization output. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SyncOutSrc This parameter can be one of the following values: +*\*\ - SHRTIM_SYNCOUT_SRC_MASTER_START +*\*\ - SHRTIM_SYNCOUT_SRC_MASTER_CMP1 +*\*\ - SHRTIM_SYNCOUT_SRC_TIMA_START +*\*\ - SHRTIM_SYNCOUT_SRC_TIMA_CMP1 +*\*\return None +**/ +void SHRTIM_SetSyncOutSrc(SHRTIM_Module *SHRTIMx, uint32_t SyncOutSrc) +{ + MODIFY_REG(SHRTIMx->sMasterRegs.MCTRL, SHRTIM_MCTRL_SYNCOSRC, SyncOutSrc); +} + +/** +*\*\fun Get actual source and event sent on the SHRTIM synchronization output. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return SyncOutSrc Returned value can be one of the following values: +*\*\ - SHRTIM_SYNCOUT_SRC_MASTER_START +*\*\ - SHRTIM_SYNCOUT_SRC_MASTER_CMP1 +*\*\ - SHRTIM_SYNCOUT_SRC_TIMA_START +*\*\ - SHRTIM_SYNCOUT_SRC_TIMA_CMP1 +**/ +uint32_t SHRTIM_GetSyncOutSrc(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sMasterRegs.MCTRL, SHRTIM_MCTRL_SYNCOSRC)); +} + +/** +*\*\fun Disable (temporarily) update event generation. +*\*\note Allow to temporarily disable the transfer from preload to active +*\*\ registers, whatever the selected update event. This allows to modify +*\*\ several registers in multiple timers. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timers This parameter can be a combination of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_SuspendUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timers) +{ + /* clear register before applying the new value */ + CLEAR_BIT(SHRTIMx->sCommonRegs.CTRL1, ((SHRTIM_TIMER_ALL >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_CTRL1_UDIS_MASK)); + SET_BIT(SHRTIMx->sCommonRegs.CTRL1, ((Timers >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_CTRL1_UDIS_MASK)); +} + +/** +*\*\fun Enable update event generation. +*\*\note The regular update event takes place. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timers This parameter can be a combination of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ResumeUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timers) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.CTRL1, ((Timers >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_CTRL1_UDIS_MASK)); +} + +/** +*\*\fun Force an immediate transfer from the preload to the active register . +*\*\note Any pending update request is cancelled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timers This parameter can be a combination of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ForceUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timers) +{ + SET_BIT(SHRTIMx->sCommonRegs.CTRL2, ((Timers >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_CTRL2_SWUPD_MASK)); +} + +/** +*\*\fun Reset the SHRTIM timer(s) counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timers This parameter can be a combination of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_CounterReset(SHRTIM_Module *SHRTIMx, uint32_t Timers) +{ + SET_BIT(SHRTIMx->sCommonRegs.CTRL2, (((Timers >> SHRTIM_MCTRL_MCNTEN_Pos) << SHRTIM_CTRL2_MSWCNTRST_Pos) & SHRTIM_CTRL2_SWRST_MASK)); +} + +/** +*\*\fun enable the swap of the Timer Output. +*\*\note the SHRTIM_TASET1 and SHRTIM_TARST1 are coding for the output A2, +*\*\ and the SHRTIM_TASET2 and SHRTIM_TARST2 are coding for the output A1 +*\*\note This bit is not significant when the Push-pull mode is enabled (PP = 1) +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableSwapOutputs(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + + SET_BIT(SHRTIMx->sCommonRegs.CTRL2, (uint32_t)(SHRTIM_CTRL2_SWAPA) << iTimer); +} + +/** +*\*\fun disable the swap of the Timer Output. +*\*\note the SHRTIM_TASET1 and SHRTIM_TARST1 are coding for the output A1, +*\*\ and the SHRTIM_TASET2 and SHRTIM_TARST2 are coding for the output A2 +*\*\note This bit is not significant when the Push-pull mode is enabled (PP = 1) +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableSwapOutputs(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + + CLEAR_BIT(SHRTIMx->sCommonRegs.CTRL2, (SHRTIM_CTRL2_SWAPA << iTimer)); +} + +/** +*\*\fun reports the Timer Outputs swap position. +*\*\note This bit is not significant when the Push-pull mode is enabled (PP = 1) +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return +*\*\ 1: SHRTIM_TASET1 and SHRTIM_TARST1 are coding for the output A2, +*\*\ SHRTIM_TASET2 and SHRTIM_TARST2 are coding for the output A1 +*\*\ 0: SHRTIM_TASET1 and SHRTIM_TARST1 are coding for the output A1, +*\*\ SHRTIM_TASET2 and SHRTIM_TARST2 are coding for the output A2 +**/ +uint32_t SHRTIM_IsEnabledSwapOutputs(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos) & 0x1FU); + + return (READ_BIT(SHRTIMx->sCommonRegs.CTRL2, (uint32_t)(SHRTIM_CTRL2_SWAPA) << iTimer) >> ((SHRTIM_CTRL2_SWAPA_Pos + iTimer))); +} + +/** +*\*\fun Enable the SHRTIM timer(s) output(s) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Outputs This parameter can be a combination of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return None +**/ +void SHRTIM_EnableOutput(SHRTIM_Module *SHRTIMx, uint32_t Outputs) +{ + SET_BIT(SHRTIMx->sCommonRegs.OEN, (Outputs & SHRTIM_OEN_OEN_MASK)); +} + +/** +*\*\fun Disable the SHRTIM timer(s) output(s) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Outputs This parameter can be a combination of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return None +**/ +void SHRTIM_DisableOutput(SHRTIM_Module *SHRTIMx, uint32_t Outputs) +{ + SET_BIT(SHRTIMx->sCommonRegs.ODIS, (Outputs & SHRTIM_ODIS_ODIS_MASK)); +} + +/** +*\*\fun Indicates whether the SHRTIM timer output is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return State of TxyOEN bit in SHRTIM_OEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledOutput(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.OEN, Output) == Output) ? 1UL : 0UL); +} + +/** +*\*\fun Indicates whether the SHRTIM timer output is disabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return State of TxyODIS bit in SHRTIM_OEN register (1 or 0). +**/ +uint32_t SHRTIM_IsDisabledOutput(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.OEN, Output) == 0U) ? 1UL : 0UL); +} + +/** +*\*\fun Configure an ADC trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrigSrcReg This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG1_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG1_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG2_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG2_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG3_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG3_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG4_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG4_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG5_SOURCE +*\*\ - SHRTIM_ADCTRIG6_SOURCE +*\*\ - SHRTIM_ADCTRIG7_SOURCE +*\*\ - SHRTIM_ADCTRIG8_SOURCE +*\*\ - SHRTIM_ADCTRIG9_SOURCE +*\*\ - SHRTIM_ADCTRIG10_SOURCE +*\*\param ADCTrig This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_1 +*\*\ - SHRTIM_ADCTRIG_2 +*\*\ - SHRTIM_ADCTRIG_3 +*\*\ - SHRTIM_ADCTRIG_4 +*\*\ - SHRTIM_ADCTRIG_5 +*\*\ - SHRTIM_ADCTRIG_6 +*\*\ - SHRTIM_ADCTRIG_7 +*\*\ - SHRTIM_ADCTRIG_8 +*\*\ - SHRTIM_ADCTRIG_9 +*\*\ - SHRTIM_ADCTRIG_10 +*\*\param Update This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_UPDATE_MASTER +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_A +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_B +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_C +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_D +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_E +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_F +*\*\param Src This parameter can be a combination of the following values: +*\*\ For ADC trigger 1 group 1 and ADC trigger 3 group 1: +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBRSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TARSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TAPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP1 +*\*\ For ADC trigger 1 group 2 and ADC trigger 3 group 2: +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFRSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TEPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP1 +*\*\ For ADC trigger 2 group 1 and ADC trigger 4 group 1: +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCRSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TAPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP1 +*\*\ For ADC trigger 2 group 2 and ADC trigger 4 group 2: +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV10 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV9 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV8 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV7 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV6 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TERSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDRSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP1 +*\*\ For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter +*\*\ can be one of the following values: +*\*\ - SHRTIM_ADTG579_MCMP1 +*\*\ - SHRTIM_ADTG579_MCMP2 +*\*\ - SHRTIM_ADTG579_MCMP3 +*\*\ - SHRTIM_ADTG579_MCMP4 +*\*\ - SHRTIM_ADTG579_MPRD +*\*\ - SHRTIM_ADTG579_EXEV1 +*\*\ - SHRTIM_ADTG579_EXEV2 +*\*\ - SHRTIM_ADTG579_EXEV3 +*\*\ - SHRTIM_ADTG579_EXEV4 +*\*\ - SHRTIM_ADTG579_EXEV5 +*\*\ - SHRTIM_ADTG579_TACMP1 +*\*\ - SHRTIM_ADTG579_TACMP2 +*\*\ - SHRTIM_ADTG579_TACMP3 +*\*\ - SHRTIM_ADTG579_TACMP4 +*\*\ - SHRTIM_ADTG579_TACMP5 +*\*\ - SHRTIM_ADTG579_TAPRD +*\*\ - SHRTIM_ADTG579_TARSTRO +*\*\ - SHRTIM_ADTG579_TBCMP1 +*\*\ - SHRTIM_ADTG579_TBCMP2 +*\*\ - SHRTIM_ADTG579_TBCMP3 +*\*\ - SHRTIM_ADTG579_TBCMP4 +*\*\ - SHRTIM_ADTG579_TBCMP5 +*\*\ - SHRTIM_ADTG579_TBPRD +*\*\ - SHRTIM_ADTG579_TBRSTRO +*\*\ - SHRTIM_ADTG579_TCCMP1 +*\*\ - SHRTIM_ADTG579_TCCMP2 +*\*\ - SHRTIM_ADTG579_TCCMP3 +*\*\ - SHRTIM_ADTG579_TCCMP4 +*\*\ - SHRTIM_ADTG579_TCCMP5 +*\*\ - SHRTIM_ADTG579_TCPRD +*\*\ - SHRTIM_ADTG579_TDCMP1 +*\*\ - SHRTIM_ADTG579_TDCMP2 +*\*\ - SHRTIM_ADTG579_TDCMP3 +*\*\ - SHRTIM_ADTG579_TDCMP4 +*\*\ - SHRTIM_ADTG579_TDCMP5 +*\*\ - SHRTIM_ADTG579_TDPRD +*\*\ - SHRTIM_ADTG579_TECMP1 +*\*\ - SHRTIM_ADTG579_TECMP2 +*\*\ - SHRTIM_ADTG579_TECMP3 +*\*\ - SHRTIM_ADTG579_TECMP4 +*\*\ - SHRTIM_ADTG579_TECMP5 +*\*\ - SHRTIM_ADTG579_TEPRD +*\*\ - SHRTIM_ADTG579_TFCMP1 +*\*\ - SHRTIM_ADTG579_TFCMP2 +*\*\ - SHRTIM_ADTG579_TFCMP3 +*\*\ - SHRTIM_ADTG579_TFCMP4 +*\*\ - SHRTIM_ADTG579_TFCMP5 +*\*\ - SHRTIM_ADTG579_TFPRD +*\*\ - SHRTIM_ADTG579_TFRSTRO +*\*\ For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter +*\*\ can be one of the following values: +*\*\ - SHRTIM_ADTG6810_MCMP1 +*\*\ - SHRTIM_ADTG6810_MCMP2 +*\*\ - SHRTIM_ADTG6810_MCMP3 +*\*\ - SHRTIM_ADTG6810_MCMP4 +*\*\ - SHRTIM_ADTG6810_MPRD +*\*\ - SHRTIM_ADTG6810_EXEV6 +*\*\ - SHRTIM_ADTG6810_EXEV7 +*\*\ - SHRTIM_ADTG6810_EXEV8 +*\*\ - SHRTIM_ADTG6810_EXEV9 +*\*\ - SHRTIM_ADTG6810_EXEV10 +*\*\ - SHRTIM_ADTG6810_TACMP1 +*\*\ - SHRTIM_ADTG6810_TACMP2 +*\*\ - SHRTIM_ADTG6810_TACMP3 +*\*\ - SHRTIM_ADTG6810_TACMP4 +*\*\ - SHRTIM_ADTG6810_TACMP5 +*\*\ - SHRTIM_ADTG6810_TAPRD +*\*\ - SHRTIM_ADTG6810_TBCMP1 +*\*\ - SHRTIM_ADTG6810_TBCMP2 +*\*\ - SHRTIM_ADTG6810_TBCMP3 +*\*\ - SHRTIM_ADTG6810_TBCMP4 +*\*\ - SHRTIM_ADTG6810_TBCMP5 +*\*\ - SHRTIM_ADTG6810_TBPRD +*\*\ - SHRTIM_ADTG6810_TCCMP1 +*\*\ - SHRTIM_ADTG6810_TCCMP2 +*\*\ - SHRTIM_ADTG6810_TCCMP3 +*\*\ - SHRTIM_ADTG6810_TCCMP4 +*\*\ - SHRTIM_ADTG6810_TCCMP5 +*\*\ - SHRTIM_ADTG6810_TCPRD +*\*\ - SHRTIM_ADTG6810_TCRSTRO +*\*\ - SHRTIM_ADTG6810_TDCMP1 +*\*\ - SHRTIM_ADTG6810_TDCMP2 +*\*\ - SHRTIM_ADTG6810_TDCMP3 +*\*\ - SHRTIM_ADTG6810_TDCMP4 +*\*\ - SHRTIM_ADTG6810_TDCMP5 +*\*\ - SHRTIM_ADTG6810_TDPRD +*\*\ - SHRTIM_ADTG6810_TDRSTRO +*\*\ - SHRTIM_ADTG6810_TECMP1 +*\*\ - SHRTIM_ADTG6810_TECMP2 +*\*\ - SHRTIM_ADTG6810_TECMP3 +*\*\ - SHRTIM_ADTG6810_TECMP4 +*\*\ - SHRTIM_ADTG6810_TECMP5 +*\*\ - SHRTIM_ADTG6810_TERSTRO +*\*\ - SHRTIM_ADTG6810_TFCMP1 +*\*\ - SHRTIM_ADTG6810_TFCMP2 +*\*\ - SHRTIM_ADTG6810_TFCMP3 +*\*\ - SHRTIM_ADTG6810_TFCMP4 +*\*\ - SHRTIM_ADTG6810_TFCMP5 +*\*\ - SHRTIM_ADTG6810_TFPRD +*\*\return None +**/ + +void SHRTIM_ConfigADCTrig(SHRTIM_Module *SHRTIMx, uint32_t ADCTrigSrcReg, uint32_t ADCTrig, uint32_t Update, uint32_t Src) +{ + __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.CTRL1) + + REG_OFFSET_TAB_ADTGUPD[ADCTrig])); + __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.ADTG1SRC1) + + REG_OFFSET_TAB_ADTGSRC[ADCTrigSrcReg])); + MODIFY_REG(*padcur, REG_MASK_TAB_ADTGUPD[ADCTrig], (Update << REG_SHIFT_TAB_ADTGUPD[ADCTrig])); + MODIFY_REG(*padcer, REG_MASK_TAB_ADTGSRC[ADCTrigSrcReg], (Src << REG_SHIFT_TAB_ADTGSRC[ADCTrigSrcReg])); +} + +/** +*\*\fun Associate the ADCx trigger to a timer triggering the update of the SHRTIM_ADTGxSRCy register. +*\*\note When the preload is disabled in the source timer, the SHRTIM_ADTGxSRCy + * registers are not preloaded either: a write access will result in an + * immediate update of the trigger source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrig This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_1 +*\*\ - SHRTIM_ADCTRIG_2 +*\*\ - SHRTIM_ADCTRIG_3 +*\*\ - SHRTIM_ADCTRIG_4 +*\*\ - SHRTIM_ADCTRIG_5 +*\*\ - SHRTIM_ADCTRIG_6 +*\*\ - SHRTIM_ADCTRIG_7 +*\*\ - SHRTIM_ADCTRIG_8 +*\*\ - SHRTIM_ADCTRIG_9 +*\*\ - SHRTIM_ADCTRIG_10 +*\*\param Update This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_UPDATE_MASTER +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_A +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_B +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_C +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_D +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_E +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_F +*\*\return None +**/ +void SHRTIM_SetADCTrigUpdate(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig, uint32_t Update) +{ + __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.CTRL1) + + REG_OFFSET_TAB_ADTGUPD[ADCTrig])); + MODIFY_REG(*preg, REG_MASK_TAB_ADTGUPD[ADCTrig], (Update << REG_SHIFT_TAB_ADTGUPD[ADCTrig])); +} + +/** +*\*\fun Get the source timer triggering the update of the SHRTIM_ADTGxSRCy register. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrig This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_1 +*\*\ - SHRTIM_ADCTRIG_2 +*\*\ - SHRTIM_ADCTRIG_3 +*\*\ - SHRTIM_ADCTRIG_4 +*\*\ - SHRTIM_ADCTRIG_5 +*\*\ - SHRTIM_ADCTRIG_6 +*\*\ - SHRTIM_ADCTRIG_7 +*\*\ - SHRTIM_ADCTRIG_8 +*\*\ - SHRTIM_ADCTRIG_9 +*\*\ - SHRTIM_ADCTRIG_10 +*\*\return Update Returned value can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_UPDATE_MASTER +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_A +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_B +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_C +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_D +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_E +*\*\ - SHRTIM_ADCTRIG_UPDATE_TIMER_F +**/ +uint32_t SHRTIM_GetADCTrigUpdate(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig) +{ + const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.CTRL1) + + REG_OFFSET_TAB_ADTGUPD[ADCTrig])); + return (READ_BIT(*preg, (REG_MASK_TAB_ADTGUPD[ADCTrig])) >> REG_SHIFT_TAB_ADTGUPD[ADCTrig]); +} + +/** +*\*\fun Specify which events (timer events and/or external events) are used as triggers for ADC conversion. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrigSrcReg This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG1_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG1_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG2_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG2_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG3_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG3_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG4_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG4_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG5_SOURCE +*\*\ - SHRTIM_ADCTRIG6_SOURCE +*\*\ - SHRTIM_ADCTRIG7_SOURCE +*\*\ - SHRTIM_ADCTRIG8_SOURCE +*\*\ - SHRTIM_ADCTRIG9_SOURCE +*\*\ - SHRTIM_ADCTRIG10_SOURCE +*\*\param Src This parameter can be a combination of the following values: +*\*\ For ADC trigger 1 (include group 1 and group2) and ADC trigger 3 (include group 1 and group2): +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBRSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TARSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TAPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFRSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TEPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP1 +*\*\ For ADC trigger 2(include group 1 and group2) and ADC trigger 4 (include group 1 and group2): +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCRSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TAPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV10 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV9 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV8 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV7 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV6 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TERSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDRSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP1 +*\*\ For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter +*\*\ can be one of the following values: +*\*\ - SHRTIM_ADTG579_MCMP1 +*\*\ - SHRTIM_ADTG579_MCMP2 +*\*\ - SHRTIM_ADTG579_MCMP3 +*\*\ - SHRTIM_ADTG579_MCMP4 +*\*\ - SHRTIM_ADTG579_MPRD +*\*\ - SHRTIM_ADTG579_EXEV1 +*\*\ - SHRTIM_ADTG579_EXEV2 +*\*\ - SHRTIM_ADTG579_EXEV3 +*\*\ - SHRTIM_ADTG579_EXEV4 +*\*\ - SHRTIM_ADTG579_EXEV5 +*\*\ - SHRTIM_ADTG579_TACMP1 +*\*\ - SHRTIM_ADTG579_TACMP2 +*\*\ - SHRTIM_ADTG579_TACMP3 +*\*\ - SHRTIM_ADTG579_TACMP4 +*\*\ - SHRTIM_ADTG579_TACMP5 +*\*\ - SHRTIM_ADTG579_TAPRD +*\*\ - SHRTIM_ADTG579_TARSTRO +*\*\ - SHRTIM_ADTG579_TBCMP1 +*\*\ - SHRTIM_ADTG579_TBCMP2 +*\*\ - SHRTIM_ADTG579_TBCMP3 +*\*\ - SHRTIM_ADTG579_TBCMP4 +*\*\ - SHRTIM_ADTG579_TBCMP5 +*\*\ - SHRTIM_ADTG579_TBPRD +*\*\ - SHRTIM_ADTG579_TBRSTRO +*\*\ - SHRTIM_ADTG579_TCCMP1 +*\*\ - SHRTIM_ADTG579_TCCMP2 +*\*\ - SHRTIM_ADTG579_TCCMP3 +*\*\ - SHRTIM_ADTG579_TCCMP4 +*\*\ - SHRTIM_ADTG579_TCCMP5 +*\*\ - SHRTIM_ADTG579_TCPRD +*\*\ - SHRTIM_ADTG579_TDCMP1 +*\*\ - SHRTIM_ADTG579_TDCMP2 +*\*\ - SHRTIM_ADTG579_TDCMP3 +*\*\ - SHRTIM_ADTG579_TDCMP4 +*\*\ - SHRTIM_ADTG579_TDCMP5 +*\*\ - SHRTIM_ADTG579_TDPRD +*\*\ - SHRTIM_ADTG579_TECMP1 +*\*\ - SHRTIM_ADTG579_TECMP2 +*\*\ - SHRTIM_ADTG579_TECMP3 +*\*\ - SHRTIM_ADTG579_TECMP4 +*\*\ - SHRTIM_ADTG579_TECMP5 +*\*\ - SHRTIM_ADTG579_TEPRD +*\*\ - SHRTIM_ADTG579_TFCMP1 +*\*\ - SHRTIM_ADTG579_TFCMP2 +*\*\ - SHRTIM_ADTG579_TFCMP3 +*\*\ - SHRTIM_ADTG579_TFCMP4 +*\*\ - SHRTIM_ADTG579_TFCMP5 +*\*\ - SHRTIM_ADTG579_TFPRD +*\*\ - SHRTIM_ADTG579_TFRSTRO +*\*\ For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter +*\*\ can be one of the following values: +*\*\ - SHRTIM_ADTG6810_MCMP1 +*\*\ - SHRTIM_ADTG6810_MCMP2 +*\*\ - SHRTIM_ADTG6810_MCMP3 +*\*\ - SHRTIM_ADTG6810_MCMP4 +*\*\ - SHRTIM_ADTG6810_MPRD +*\*\ - SHRTIM_ADTG6810_EXEV6 +*\*\ - SHRTIM_ADTG6810_EXEV7 +*\*\ - SHRTIM_ADTG6810_EXEV8 +*\*\ - SHRTIM_ADTG6810_EXEV9 +*\*\ - SHRTIM_ADTG6810_EXEV10 +*\*\ - SHRTIM_ADTG6810_TACMP1 +*\*\ - SHRTIM_ADTG6810_TACMP2 +*\*\ - SHRTIM_ADTG6810_TACMP3 +*\*\ - SHRTIM_ADTG6810_TACMP4 +*\*\ - SHRTIM_ADTG6810_TACMP5 +*\*\ - SHRTIM_ADTG6810_TAPRD +*\*\ - SHRTIM_ADTG6810_TBCMP1 +*\*\ - SHRTIM_ADTG6810_TBCMP2 +*\*\ - SHRTIM_ADTG6810_TBCMP3 +*\*\ - SHRTIM_ADTG6810_TBCMP4 +*\*\ - SHRTIM_ADTG6810_TBCMP5 +*\*\ - SHRTIM_ADTG6810_TBPRD +*\*\ - SHRTIM_ADTG6810_TCCMP1 +*\*\ - SHRTIM_ADTG6810_TCCMP2 +*\*\ - SHRTIM_ADTG6810_TCCMP3 +*\*\ - SHRTIM_ADTG6810_TCCMP4 +*\*\ - SHRTIM_ADTG6810_TCCMP5 +*\*\ - SHRTIM_ADTG6810_TCPRD +*\*\ - SHRTIM_ADTG6810_TCRSTRO +*\*\ - SHRTIM_ADTG6810_TDCMP1 +*\*\ - SHRTIM_ADTG6810_TDCMP2 +*\*\ - SHRTIM_ADTG6810_TDCMP3 +*\*\ - SHRTIM_ADTG6810_TDCMP4 +*\*\ - SHRTIM_ADTG6810_TDCMP5 +*\*\ - SHRTIM_ADTG6810_TDPRD +*\*\ - SHRTIM_ADTG6810_TDRSTRO +*\*\ - SHRTIM_ADTG6810_TECMP1 +*\*\ - SHRTIM_ADTG6810_TECMP2 +*\*\ - SHRTIM_ADTG6810_TECMP3 +*\*\ - SHRTIM_ADTG6810_TECMP4 +*\*\ - SHRTIM_ADTG6810_TECMP5 +*\*\ - SHRTIM_ADTG6810_TERSTRO +*\*\ - SHRTIM_ADTG6810_TFCMP1 +*\*\ - SHRTIM_ADTG6810_TFCMP2 +*\*\ - SHRTIM_ADTG6810_TFCMP3 +*\*\ - SHRTIM_ADTG6810_TFCMP4 +*\*\ - SHRTIM_ADTG6810_TFCMP5 +*\*\ - SHRTIM_ADTG6810_TFPRD +*\*\return None +**/ +void SHRTIM_SetADCTrigSrc(SHRTIM_Module *SHRTIMx, uint32_t ADCTrigSrcReg, uint32_t Src) +{ + __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.ADTG1SRC1) + + REG_OFFSET_TAB_ADTGSRC[ADCTrigSrcReg])); + MODIFY_REG(*preg, REG_MASK_TAB_ADTGSRC[ADCTrigSrcReg], (Src << REG_SHIFT_TAB_ADTGSRC[ADCTrigSrcReg])); +} + +/** +*\*\fun Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrigSrcReg This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG1_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG1_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG2_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG2_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG3_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG3_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG4_SOURCE_GROUP1 +*\*\ - SHRTIM_ADCTRIG4_SOURCE_GROUP2 +*\*\ - SHRTIM_ADCTRIG5_SOURCE +*\*\ - SHRTIM_ADCTRIG6_SOURCE +*\*\ - SHRTIM_ADCTRIG7_SOURCE +*\*\ - SHRTIM_ADCTRIG8_SOURCE +*\*\ - SHRTIM_ADCTRIG9_SOURCE +*\*\ - SHRTIM_ADCTRIG10_SOURCE +*\*\return +*\*\ For ADC trigger 1 (include group 1 and group2) and ADC trigger 3 (include group 1 and group2): +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TCCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBRSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TBCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TARSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TAPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_TACMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP1_MCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_EXEV1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFRSTRO +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TFCMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TEPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TECMP1 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDPRD +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP5 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP4 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP3 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP2 +*\*\ - SHRTIM_ADTG13_SOURCE_GROUP2_TDCMP1 +*\*\ For ADC trigger 2(include group 1 and group2) and ADC trigger 4 (include group 1 and group2): +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCRSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TCCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TBCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TAPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_TACMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP1_MCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV10 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV9 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV8 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV7 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_EXEV6 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TFCMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TERSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TECMP1 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDRSTRO +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDPRD +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP5 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP4 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP3 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP2 +*\*\ - SHRTIM_ADTG24_SOURCE_GROUP2_TDCMP1 +*\*\ For ADC trigger 5, ADC trigger 7 and ADC trigger 9 +*\*\ can be one of the following values: +*\*\ - SHRTIM_ADTG579_MCMP1 +*\*\ - SHRTIM_ADTG579_MCMP2 +*\*\ - SHRTIM_ADTG579_MCMP3 +*\*\ - SHRTIM_ADTG579_MCMP4 +*\*\ - SHRTIM_ADTG579_MPRD +*\*\ - SHRTIM_ADTG579_EXEV1 +*\*\ - SHRTIM_ADTG579_EXEV2 +*\*\ - SHRTIM_ADTG579_EXEV3 +*\*\ - SHRTIM_ADTG579_EXEV4 +*\*\ - SHRTIM_ADTG579_EXEV5 +*\*\ - SHRTIM_ADTG579_TACMP1 +*\*\ - SHRTIM_ADTG579_TACMP2 +*\*\ - SHRTIM_ADTG579_TACMP3 +*\*\ - SHRTIM_ADTG579_TACMP4 +*\*\ - SHRTIM_ADTG579_TACMP5 +*\*\ - SHRTIM_ADTG579_TAPRD +*\*\ - SHRTIM_ADTG579_TARSTRO +*\*\ - SHRTIM_ADTG579_TBCMP1 +*\*\ - SHRTIM_ADTG579_TBCMP2 +*\*\ - SHRTIM_ADTG579_TBCMP3 +*\*\ - SHRTIM_ADTG579_TBCMP4 +*\*\ - SHRTIM_ADTG579_TBCMP5 +*\*\ - SHRTIM_ADTG579_TBPRD +*\*\ - SHRTIM_ADTG579_TBRSTRO +*\*\ - SHRTIM_ADTG579_TCCMP1 +*\*\ - SHRTIM_ADTG579_TCCMP2 +*\*\ - SHRTIM_ADTG579_TCCMP3 +*\*\ - SHRTIM_ADTG579_TCCMP4 +*\*\ - SHRTIM_ADTG579_TCCMP5 +*\*\ - SHRTIM_ADTG579_TCPRD +*\*\ - SHRTIM_ADTG579_TDCMP1 +*\*\ - SHRTIM_ADTG579_TDCMP2 +*\*\ - SHRTIM_ADTG579_TDCMP3 +*\*\ - SHRTIM_ADTG579_TDCMP4 +*\*\ - SHRTIM_ADTG579_TDCMP5 +*\*\ - SHRTIM_ADTG579_TDPRD +*\*\ - SHRTIM_ADTG579_TECMP1 +*\*\ - SHRTIM_ADTG579_TECMP2 +*\*\ - SHRTIM_ADTG579_TECMP3 +*\*\ - SHRTIM_ADTG579_TECMP4 +*\*\ - SHRTIM_ADTG579_TECMP5 +*\*\ - SHRTIM_ADTG579_TEPRD +*\*\ - SHRTIM_ADTG579_TFCMP1 +*\*\ - SHRTIM_ADTG579_TFCMP2 +*\*\ - SHRTIM_ADTG579_TFCMP3 +*\*\ - SHRTIM_ADTG579_TFCMP4 +*\*\ - SHRTIM_ADTG579_TFCMP5 +*\*\ - SHRTIM_ADTG579_TFPRD +*\*\ - SHRTIM_ADTG579_TFRSTRO +*\*\ For ADC trigger 6, ADC trigger 8 and ADC trigger 10 +*\*\ can be one of the following values: +*\*\ - SHRTIM_ADTG6810_MCMP1 +*\*\ - SHRTIM_ADTG6810_MCMP2 +*\*\ - SHRTIM_ADTG6810_MCMP3 +*\*\ - SHRTIM_ADTG6810_MCMP4 +*\*\ - SHRTIM_ADTG6810_MPRD +*\*\ - SHRTIM_ADTG6810_EXEV6 +*\*\ - SHRTIM_ADTG6810_EXEV7 +*\*\ - SHRTIM_ADTG6810_EXEV8 +*\*\ - SHRTIM_ADTG6810_EXEV9 +*\*\ - SHRTIM_ADTG6810_EXEV10 +*\*\ - SHRTIM_ADTG6810_TACMP1 +*\*\ - SHRTIM_ADTG6810_TACMP2 +*\*\ - SHRTIM_ADTG6810_TACMP3 +*\*\ - SHRTIM_ADTG6810_TACMP4 +*\*\ - SHRTIM_ADTG6810_TACMP5 +*\*\ - SHRTIM_ADTG6810_TAPRD +*\*\ - SHRTIM_ADTG6810_TBCMP1 +*\*\ - SHRTIM_ADTG6810_TBCMP2 +*\*\ - SHRTIM_ADTG6810_TBCMP3 +*\*\ - SHRTIM_ADTG6810_TBCMP4 +*\*\ - SHRTIM_ADTG6810_TBCMP5 +*\*\ - SHRTIM_ADTG6810_TBPRD +*\*\ - SHRTIM_ADTG6810_TCCMP1 +*\*\ - SHRTIM_ADTG6810_TCCMP2 +*\*\ - SHRTIM_ADTG6810_TCCMP3 +*\*\ - SHRTIM_ADTG6810_TCCMP4 +*\*\ - SHRTIM_ADTG6810_TCCMP5 +*\*\ - SHRTIM_ADTG6810_TCPRD +*\*\ - SHRTIM_ADTG6810_TCRSTRO +*\*\ - SHRTIM_ADTG6810_TDCMP1 +*\*\ - SHRTIM_ADTG6810_TDCMP2 +*\*\ - SHRTIM_ADTG6810_TDCMP3 +*\*\ - SHRTIM_ADTG6810_TDCMP4 +*\*\ - SHRTIM_ADTG6810_TDCMP5 +*\*\ - SHRTIM_ADTG6810_TDPRD +*\*\ - SHRTIM_ADTG6810_TDRSTRO +*\*\ - SHRTIM_ADTG6810_TECMP1 +*\*\ - SHRTIM_ADTG6810_TECMP2 +*\*\ - SHRTIM_ADTG6810_TECMP3 +*\*\ - SHRTIM_ADTG6810_TECMP4 +*\*\ - SHRTIM_ADTG6810_TECMP5 +*\*\ - SHRTIM_ADTG6810_TERSTRO +*\*\ - SHRTIM_ADTG6810_TFCMP1 +*\*\ - SHRTIM_ADTG6810_TFCMP2 +*\*\ - SHRTIM_ADTG6810_TFCMP3 +*\*\ - SHRTIM_ADTG6810_TFCMP4 +*\*\ - SHRTIM_ADTG6810_TFCMP5 +*\*\ - SHRTIM_ADTG6810_TFPRD +**/ +uint32_t SHRTIM_GetADCTrigSrc(SHRTIM_Module *SHRTIMx, uint32_t ADCTrigSrcReg) +{ + const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.ADTG1SRC1) + + REG_OFFSET_TAB_ADTGSRC[ADCTrigSrcReg])); + return (READ_BIT(*preg, (REG_MASK_TAB_ADTGSRC[ADCTrigSrcReg])) >> REG_SHIFT_TAB_ADTGSRC[ADCTrigSrcReg]); +} + +/** +*\*\fun Select the ADC post scaler. +*\*\note This function allows to adjust each ADC trigger rate individually. +*\*\note In center-aligned mode, the ADC trigger rate is also dependent on + * ADCROM[1:0] bitfield, programmed in the source timer + * (see function SHRTIM_TIM_SetADCRollOverMode) +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrig This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_1 +*\*\ - SHRTIM_ADCTRIG_2 +*\*\ - SHRTIM_ADCTRIG_3 +*\*\ - SHRTIM_ADCTRIG_4 +*\*\ - SHRTIM_ADCTRIG_5 +*\*\ - SHRTIM_ADCTRIG_6 +*\*\ - SHRTIM_ADCTRIG_7 +*\*\ - SHRTIM_ADCTRIG_8 +*\*\ - SHRTIM_ADCTRIG_9 +*\*\ - SHRTIM_ADCTRIG_10 +*\*\param PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31 +*\*\return None +**/ +void SHRTIM_SetADCPostScaler(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig, uint32_t PostScaler) +{ + uint64_t mask = (uint64_t)(SHRTIM_ADCPSC1_ADC1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]); + uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]); + + MODIFY_REG(SHRTIMx->sCommonRegs.ADCPSC1, (uint32_t)mask, (uint32_t)ratio); + MODIFY_REG(SHRTIMx->sCommonRegs.ADCPSC2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U)); +} + +/** +*\*\fun Get the selected ADC post scaler. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ADCTrig This parameter can be one of the following values: +*\*\ - SHRTIM_ADCTRIG_1 +*\*\ - SHRTIM_ADCTRIG_2 +*\*\ - SHRTIM_ADCTRIG_3 +*\*\ - SHRTIM_ADCTRIG_4 +*\*\ - SHRTIM_ADCTRIG_5 +*\*\ - SHRTIM_ADCTRIG_6 +*\*\ - SHRTIM_ADCTRIG_7 +*\*\ - SHRTIM_ADCTRIG_8 +*\*\ - SHRTIM_ADCTRIG_9 +*\*\ - SHRTIM_ADCTRIG_10 +*\*\return PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31 +**/ +uint32_t SHRTIM_GetADCPostScaler(SHRTIM_Module *SHRTIMx, uint32_t ADCTrig) +{ + + uint32_t reg1 = READ_REG(SHRTIMx->sCommonRegs.ADCPSC1); + uint32_t reg2 = READ_REG(SHRTIMx->sCommonRegs.ADCPSC2); + + uint64_t mask = (uint64_t)(SHRTIM_ADCPSC1_ADC1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]); + uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U); + + return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])); +} + +/** +*\*\fun Enable timer(s) counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timers This parameter can be a combination of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_CounterEnable(SHRTIM_Module *SHRTIMx, uint32_t Timers) +{ + SET_BIT(SHRTIMx->sMasterRegs.MCTRL, Timers); +} + +/** +*\*\fun Disable timer(s) counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timers This parameter can be a combination of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_CounterDisable(SHRTIM_Module *SHRTIMx, uint32_t Timers) +{ + CLEAR_BIT(SHRTIMx->sMasterRegs.MCTRL, Timers); +} + +/** +*\*\fun Indicate whether the timer counter is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCNTEN or TxCNTEN bit SHRTIM_MCTRL register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsCounterEnabled(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + return ((READ_BIT(SHRTIMx->sMasterRegs.MCTRL, Timer) == (Timer)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the timer clock prescaler ratio. +*\*\note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0]. +*\*\note The prescaling ratio cannot be modified once the timer counter is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_PRESCALERRATIO_MUL32 +*\*\ - SHRTIM_PRESCALERRATIO_MUL16 +*\*\ - SHRTIM_PRESCALERRATIO_MUL8 +*\*\ - SHRTIM_PRESCALERRATIO_MUL4 +*\*\ - SHRTIM_PRESCALERRATIO_MUL2 +*\*\ - SHRTIM_PRESCALERRATIO_DIV1 +*\*\ - SHRTIM_PRESCALERRATIO_DIV2 +*\*\ - SHRTIM_PRESCALERRATIO_DIV4 +*\*\return None +**/ +void SHRTIM_TIM_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Prescaler) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCTRL_CKPSC, Prescaler); +} + +/** +*\*\fun Get the timer clock prescaler ratio +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Prescaler Returned value can be one of the following values: +*\*\ - SHRTIM_PRESCALERRATIO_MUL32 +*\*\ - SHRTIM_PRESCALERRATIO_MUL16 +*\*\ - SHRTIM_PRESCALERRATIO_MUL8 +*\*\ - SHRTIM_PRESCALERRATIO_MUL4 +*\*\ - SHRTIM_PRESCALERRATIO_MUL2 +*\*\ - SHRTIM_PRESCALERRATIO_DIV1 +*\*\ - SHRTIM_PRESCALERRATIO_DIV2 +*\*\ - SHRTIM_PRESCALERRATIO_DIV4 +**/ +uint32_t SHRTIM_TIM_GetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCTRL_CKPSC)); +} + +/** +*\*\fun Set the counter operating mode mode (single-shot, continuous or re-triggerable). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_MODE_CONTINUOUS +*\*\ - SHRTIM_MODE_SINGLESHOT +*\*\ - SHRTIM_MODE_RETRIGGERABLE +*\*\return None +**/ +void SHRTIM_TIM_SetCounterMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, (SHRTIM_TXCTRL_RTG | SHRTIM_MCTRL_CONT), Mode); +} + +/** +*\*\fun Get the counter operating mode mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode Returned value can be one of the following values: +*\*\ - SHRTIM_MODE_CONTINUOUS +*\*\ - SHRTIM_MODE_SINGLESHOT +*\*\ - SHRTIM_MODE_RETRIGGERABLE +**/ +uint32_t SHRTIM_TIM_GetCounterMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, (SHRTIM_MCTRL_RTG | SHRTIM_MCTRL_CONT))); +} + +/** +*\*\fun Enable the half duty-cycle mode. +*\*\note When the half mode is enabled, SHRTIM_MCMP1DAT (or SHRTIM_TXCMP1xDAT) + * active register is automatically updated with SHRTIM_MPRD/2 + * (or SHRTIM_TXPRD/2) value when SHRTIM_MPRD (or SHRTIM_TXPRD) register is written. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MCTRL_HLF); +} + +/** +*\*\fun Disable the half duty-cycle mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MCTRL_HLF); + CLEAR_BIT(*pReg, SHRTIM_MCTRL_ILV << REG_SHIFT_TAB_ILV[iTimer]); +} + +/** +*\*\fun Indicate whether half duty-cycle mode is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of HLF bit to 1 in SHRTIM_MCTRL or SHRTIM_TxCTRL register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MCTRL_HLF) == (SHRTIM_MCTRL_HLF)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the Re-Syncronisation Update. +*\*\note The update coming from adjacent timers (when MUEN, TAUEN, TBUEN, TCUEN, TDUEN, TEUEN, TFUEN bit is set) +*\*\ or from a software update (TxSWUPD bit) is taken into account on the following reset/roll-over. +*\*\note SHRTIM_ForceUpdate must be called prior programming the syncrhonization mode to force +*\*\ immediate update of the slave timer registers. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableResyncUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXCTRL_RSYNCUPD); + /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ +} + +/** +*\*\fun Disable the Re-Syncronisation Update. +*\*\note The update coming from adjacent timers (when MUEN, TAUEN, TBUEN, TCUEN, TDUEN, TEUEN, TFUEN bit is set) +*\*\ or from a software update (TxSWUPD bit) is taken into account immediately. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableResyncUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + + CLEAR_BIT(*pReg, SHRTIM_TXCTRL_RSYNCUPD); + /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ +} + +/** +*\*\fun Indicate whether the Re-Syncronisation Update is enabled. +*\*\note This bit specifies whether update source coming outside +*\*\ from the timing unit must be synchronized +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RSYNCUPD in SHRTIM_TxCTRL register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledResyncUpdate(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXCTRL_RSYNCUPD) == (SHRTIM_TXCTRL_RSYNCUPD)) ? 1UL : 0UL); + /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ +} + +/** +*\*\note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies. +*\*\note When interleaved mode is enabled, the content of the compare registers is overridden. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_INTERLEAVED_MODE_DISABLED +*\*\ - SHRTIM_INTERLEAVED_MODE_DUAL +*\*\ - SHRTIM_INTERLEAVED_MODE_TRIPLE +*\*\ - SHRTIM_INTERLEAVED_MODE_QUAD +*\*\return None +**/ +void SHRTIM_TIM_SetInterleavedMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + MODIFY_REG(*pReg, REG_MASK_TAB_ILV[iTimer], + ((Mode & SHRTIM_MCTRL_HLF) | ((Mode & SHRTIM_MCTRL_ILV) << REG_SHIFT_TAB_ILV[iTimer]))); +} + +/** +*\*\fun get the Interleaved configuration. +*\*\note The interleaved Mode is Triple or Quad if HLF bit is disabled +*\*\ the interleaved Mode is dual if HLF bit is set, + +*\*\ SHRTIM_MCMP1DAT (or SHRTIM_TXCMP1xDAT) active register is automatically updated +*\*\ with SHRTIM_MPRD/2 or SHRTIM_MPRD/4 + * (or SHRTIM_TXPRD/2) value when SHRTIM_MPRD (or SHRTIM_TXPRD) register is written. + +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return This parameter can be one of the following values: +*\*\ - SHRTIM_INTERLEAVED_MODE_DISABLED +*\*\ - SHRTIM_INTERLEAVED_MODE_DUAL +*\*\ - SHRTIM_INTERLEAVED_MODE_TRIPLE +*\*\ - SHRTIM_INTERLEAVED_MODE_QUAD +**/ +uint32_t SHRTIM_TIM_GetInterleavedMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_ILV[iTimer])); + return ((Mode & SHRTIM_MCTRL_HLF) | ((Mode >> REG_SHIFT_TAB_ILV[iTimer]) & SHRTIM_MCTRL_ILV)); +} + +/** +*\*\fun Enable the timer start when receiving a synchronization input event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableStartOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + if (Timer == SHRTIM_TIMER_MASTER) + { + SET_BIT(*pReg, SHRTIM_MCTRL_SYNCSTRT); + } + else + { + SET_BIT(*pReg, SHRTIM_TXCTRL_SYNCSTRT); + } +} + +/** +*\*\fun Disable the timer start when receiving a synchronization input event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableStartOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + if (Timer == SHRTIM_TIMER_MASTER) + { + CLEAR_BIT(*pReg, SHRTIM_MCTRL_SYNCSTRT); + } + else + { + CLEAR_BIT(*pReg, SHRTIM_TXCTRL_SYNCSTRT); + } +} + +/** +*\*\fun Indicate whether the timer start when receiving a synchronization input event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SYNCSTRT bit in SHRTIM_MCTRL or SHRTIM_TxCTRL register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledStartOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + if (Timer == SHRTIM_TIMER_MASTER) + { + return ((READ_BIT(*pReg, SHRTIM_MCTRL_SYNCSTRT) == (SHRTIM_MCTRL_SYNCSTRT)) ? 1UL : 0UL); + } + else + { + return ((READ_BIT(*pReg, SHRTIM_TXCTRL_SYNCSTRT) == (SHRTIM_TXCTRL_SYNCSTRT)) ? 1UL : 0UL); + } +} + +/** +*\*\fun Enable the timer reset when receiving a synchronization input event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableResetOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + if (Timer == SHRTIM_TIMER_MASTER) + { + SET_BIT(*pReg, SHRTIM_MCTRL_SYNCRST); + } + else + { + SET_BIT(*pReg, SHRTIM_TXCTRL_SYNCRST); + } +} + +/** +*\*\fun Disable the timer reset when receiving a synchronization input event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableResetOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + if (Timer == SHRTIM_TIMER_MASTER) + { + CLEAR_BIT(*pReg, SHRTIM_MCTRL_SYNCRST); + } + else + { + CLEAR_BIT(*pReg, SHRTIM_TXCTRL_SYNCRST); + } +} + +/** +*\*\fun Indicate whether the timer reset when receiving a synchronization input event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +uint32_t SHRTIM_TIM_IsEnabledResetOnSync(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + if (Timer == SHRTIM_TIMER_MASTER) + { + return ((READ_BIT(*pReg, SHRTIM_MCTRL_SYNCRST) == (SHRTIM_MCTRL_SYNCRST)) ? 1UL : 0UL); + } + else + { + return ((READ_BIT(*pReg, SHRTIM_TXCTRL_SYNCRST) == (SHRTIM_TXCTRL_SYNCRST)) ? 1UL : 0UL); + } +} + +/** +*\*\fun Set the SHRTIM output the DAC synchronization event is generated on (DACtrigOutx). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param DACTrig This parameter can be one of the following values: +*\*\ - SHRTIM_DACTRIG_NONE +*\*\ - SHRTIM_DACTRIG_DACTRIGOUT_1 +*\*\ - SHRTIM_DACTRIG_DACTRIGOUT_2 +*\*\ - SHRTIM_DACTRIG_DACTRIGOUT_3 +*\*\return None +**/ +void SHRTIM_TIM_SetDACTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t DACTrig) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCTRL_DACTRIG, DACTrig); +} + +/** +*\*\fun Get the SHRTIM output the DAC synchronization event is generated on (DACtrigOutx). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return DACTrig Returned value can be one of the following values: +*\*\ - SHRTIM_DACTRIG_NONE +*\*\ - SHRTIM_DACTRIG_DACTRIGOUT_1 +*\*\ - SHRTIM_DACTRIG_DACTRIGOUT_2 +*\*\ - SHRTIM_DACTRIG_DACTRIGOUT_3 +**/ +uint32_t SHRTIM_TIM_GetDACTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCTRL_DACTRIG)); +} + +/** +*\*\fun Enable the timer registers preload mechanism. +*\*\note When the preload mode is enabled, accessed registers are shadow registers. + * Their content is transferred into the active register after an update request, + * either software or synchronized with an event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnablePreload(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MCTRL_PLEN); +} + +/** +*\*\fun Disable the timer registers preload mechanism. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisablePreload(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MCTRL_PLEN); +} + +/** +*\*\fun Indicate whether the timer registers preload mechanism is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of PLEN bit in SHRTIM_MCTRL or SHRTIM_TxCTRL register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledPreload(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MCTRL_PLEN) == (SHRTIM_MCTRL_PLEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the timer register update trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param UpdateTrig This parameter can be one of the following values: +*\*\ For the master timer this parameter can be one of the following values: +*\*\ - SHRTIM_UPDATETRIG_NONE +*\*\ - SHRTIM_UPDATETRIG_REPETITION +*\*\ For timer A..F this parameter can be: +*\*\ - SHRTIM_UPDATETRIG_NONE +*\*\ or a combination of the following values: +*\*\ - SHRTIM_UPDATETRIG_MASTER +*\*\ - SHRTIM_UPDATETRIG_TIMER_A +*\*\ - SHRTIM_UPDATETRIG_TIMER_B +*\*\ - SHRTIM_UPDATETRIG_TIMER_C +*\*\ - SHRTIM_UPDATETRIG_TIMER_D +*\*\ - SHRTIM_UPDATETRIG_TIMER_E +*\*\ - SHRTIM_UPDATETRIG_TIMER_F +*\*\ - SHRTIM_UPDATETRIG_REPETITION +*\*\ - SHRTIM_UPDATETRIG_RESET +*\*\return None +**/ +void SHRTIM_TIM_SetUpdateTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t UpdateTrig) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); +} + +/** +*\*\fun Get the timer register update trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return UpdateTrig Returned value can be one of the following values: + * +*\*\ For the master timer this parameter can be one of the following values: +*\*\ - SHRTIM_UPDATETRIG_NONE +*\*\ - SHRTIM_UPDATETRIG_MASTER_REPETITION + * +*\*\ For timer A..F this parameter can be: +*\*\ - SHRTIM_UPDATETRIG_NONE +*\*\ or a combination of the following values: +*\*\ - SHRTIM_UPDATETRIG_MASTER +*\*\ - SHRTIM_UPDATETRIG_TIMER_A +*\*\ - SHRTIM_UPDATETRIG_TIMER_B +*\*\ - SHRTIM_UPDATETRIG_TIMER_C +*\*\ - SHRTIM_UPDATETRIG_TIMER_D +*\*\ - SHRTIM_UPDATETRIG_TIMER_E +*\*\ - SHRTIM_UPDATETRIG_TIMER_F +*\*\ - SHRTIM_UPDATETRIG_REPETITION +*\*\ - SHRTIM_UPDATETRIG_RESET +**/ +uint32_t SHRTIM_TIM_GetUpdateTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); +} + +/** +*\*\fun Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param UpdateGating This parameter can be one of the following values: + * +*\*\ For the master timer this parameter can be one of the following values: +*\*\ - SHRTIM_UPDATEGATING_INDEPENDENT +*\*\ - SHRTIM_UPDATEGATING_DMABURST +*\*\ - SHRTIM_UPDATEGATING_DMABURST_UPDATE + * +*\*\ For the timer A..F this parameter can be one of the following values: +*\*\ - SHRTIM_UPDATEGATING_INDEPENDENT +*\*\ - SHRTIM_UPDATEGATING_DMABURST +*\*\ - SHRTIM_UPDATEGATING_DMABURST_UPDATE +*\*\ - SHRTIM_UPDATEGATING_UPDEN1 +*\*\ - SHRTIM_UPDATEGATING_UPDEN2 +*\*\ - SHRTIM_UPDATEGATING_UPDEN3 +*\*\ - SHRTIM_UPDATEGATING_UPDEN1_UPDATE +*\*\ - SHRTIM_UPDATEGATING_UPDEN2_UPDATE +*\*\ - SHRTIM_UPDATEGATING_UPDEN3_UPDATE +*\*\return None +**/ +void SHRTIM_TIM_SetUpdateGating(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t UpdateGating) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); +} + +/** +*\*\fun Get the timer registers update condition. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return UpdateGating Returned value can be one of the following values: + * +*\*\ For the master timer this parameter can be one of the following values: +*\*\ - SHRTIM_UPDATEGATING_INDEPENDENT +*\*\ - SHRTIM_UPDATEGATING_DMABURST +*\*\ - SHRTIM_UPDATEGATING_DMABURST_UPDATE + * +*\*\ For the timer A..F this parameter can be one of the following values: +*\*\ - SHRTIM_UPDATEGATING_INDEPENDENT +*\*\ - SHRTIM_UPDATEGATING_DMABURST +*\*\ - SHRTIM_UPDATEGATING_DMABURST_UPDATE +*\*\ - SHRTIM_UPDATEGATING_UPDEN1 +*\*\ - SHRTIM_UPDATEGATING_UPDEN2 +*\*\ - SHRTIM_UPDATEGATING_UPDEN3 +*\*\ - SHRTIM_UPDATEGATING_UPDEN1_UPDATE +*\*\ - SHRTIM_UPDATEGATING_UPDEN2_UPDATE +*\*\ - SHRTIM_UPDATEGATING_UPDEN3_UPDATE +**/ +uint32_t SHRTIM_TIM_GetUpdateGating(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCTRL) + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); +} + +/** +*\*\fun Enable the push-pull mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnablePushPullMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXCTRL_PP); +} + +/** +*\*\fun Disable the push-pull mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisablePushPullMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXCTRL_PP); +} + +/** +*\*\fun Indicate whether the push-pull mode is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of PP bit in SHRTIM_TxCTRL register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledPushPullMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXCTRL_PP) == (SHRTIM_TXCTRL_PP)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode). +*\*\note In auto-delayed mode the compare match occurs independently from the timer counter value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareUnit This parameter can be one of the following values: +*\*\ - SHRTIM_COMPAREUNIT_2 +*\*\ - SHRTIM_COMPAREUNIT_4 +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_COMPAREMODE_REGULAR +*\*\ - SHRTIM_COMPAREMODE_DELAY_NOTIMEOUT +*\*\ - SHRTIM_COMPAREMODE_DELAY_CMP1 +*\*\ - SHRTIM_COMPAREMODE_DELAY_CMP3 +*\*\return None +**/ +void SHRTIM_TIM_SetCompareMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareUnit, + uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(SHRTIM_COMPAREUNIT_2)) & 0x1FU); + MODIFY_REG(*pReg, (SHRTIM_TXCTRL_DELCMP2M << shift), (Mode << shift)); +} + +/** +*\*\fun Get the functioning mode of the compare unit. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareUnit This parameter can be one of the following values: +*\*\ - SHRTIM_COMPAREUNIT_2 +*\*\ - SHRTIM_COMPAREUNIT_4 +*\*\return Mode Returned value can be one of the following values: +*\*\ - SHRTIM_COMPAREMODE_REGULAR +*\*\ - SHRTIM_COMPAREMODE_DELAY_NOTIMEOUT +*\*\ - SHRTIM_COMPAREMODE_DELAY_CMP1 +*\*\ - SHRTIM_COMPAREMODE_DELAY_CMP3 +**/ +uint32_t SHRTIM_TIM_GetCompareMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareUnit) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL) + + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(SHRTIM_COMPAREUNIT_2)) & 0x1FU); + return (READ_BIT(*pReg, (SHRTIM_TXCTRL_DELCMP2M << shift)) >> shift); +} + +/** +*\*\fun Set the timer counter value. +*\*\note This function can only be called when the timer is stopped. +*\*\note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least + * significant bits of the counter are not significant. They cannot be + * written and return 0 when read. +*\*\note The timer behavior is not guaranteed if the counter value is set above + * the period. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Counter Value between 0 and 0xFFFF +*\*\return None +**/ +void SHRTIM_TIM_SetCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Counter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCNT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCNT_MCOUNT, Counter); +} + +/** +*\*\fun Get actual timer counter value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Counter Value between 0 and 0xFFFF +**/ +uint32_t SHRTIM_TIM_GetCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCNT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCNT_MCOUNT)); +} + +/** +*\*\fun Set the timer period value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Period Value between 0 and 0xFFFF +*\*\return None +**/ +void SHRTIM_TIM_SetPeriod(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Period) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MPRD) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MPRD_MPRD, Period); +} + +/** +*\*\fun Get actual timer period value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Period Value between 0 and 0xFFFF +**/ +uint32_t SHRTIM_TIM_GetPeriod(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MPRD) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MPRD_MPRD)); +} + +/** +*\*\fun Set the timer repetition period value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Repetition Value between 0 and 0xFF +*\*\return None +**/ +void SHRTIM_TIM_SetRepetition(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Repetition) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MREPT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MREPT_MREPT, Repetition); +} + +/** +*\*\fun Get actual timer repetition period value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Repetition Value between 0 and 0xFF +**/ +uint32_t SHRTIM_TIM_GetRepetition(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MREPT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MREPT_MREPT)); +} + +/** +*\*\fun Set the compare value of the compare unit 1. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +*\*\return None +**/ +void SHRTIM_TIM_SetCompare1(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP1DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCMP1DAT_MCMP1DAT, CompareValue); +} + +/** +*\*\fun Get actual compare value of the compare unit 1. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +**/ +uint32_t SHRTIM_TIM_GetCompare1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP1DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCMP1DAT_MCMP1DAT)); +} + +/** +*\*\fun Set the compare value of the compare unit 2. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +*\*\return None +**/ +void SHRTIM_TIM_SetCompare2(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP2DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCMP2DAT_MCMP2DAT, CompareValue); +} + +/** +*\*\fun Get actual compare value of the compare unit 2. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +**/ +uint32_t SHRTIM_TIM_GetCompare2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP2DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCMP2DAT_MCMP2DAT)); +} + +/** +*\*\fun Set the compare value of the compare unit 3. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +*\*\return None +**/ +void SHRTIM_TIM_SetCompare3(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP3DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCMP3DAT_MCMP3DAT, CompareValue); +} + +/** +*\*\fun Get actual compare value of the compare unit 3. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +**/ +uint32_t SHRTIM_TIM_GetCompare3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP3DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCMP3DAT_MCMP3DAT)); +} + +/** +*\*\fun Set the compare value of the compare unit 4. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +*\*\return None +**/ +void SHRTIM_TIM_SetCompare4(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP4DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_MCMP4DAT_MCMP4DAT, CompareValue); +} + +/** +*\*\fun Get actual compare value of the compare unit 4. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return CompareValue Compare value must be above or equal to 3 +*\*\ periods of the fSHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, +*\*\ 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... +**/ +uint32_t SHRTIM_TIM_GetCompare4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MCMP4DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_MCMP4DAT_MCMP4DAT)); +} + +/** +*\*\fun Set the compare value of the compare unit 5. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CompareValue Compare value is regular resolution, not high resolution +*\*\return None +**/ +void SHRTIM_TIM_SetCompare5(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CompareValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCMP5DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCMP5DAT_CMP5DAT, CompareValue); +} + +/** +*\*\fun Get actual compare value of the compare unit 5. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return CompareValue Compare value is regular resolution, not high resolution +**/ +uint32_t SHRTIM_TIM_GetCompare5(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCMP5DAT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCMP5DAT_CMP5DAT)); +} + +/** +*\*\fun Set the reset trigger of a timer counter. +*\*\note The reset of the timer counter can be triggered by up to 30 events + * that can be selected among the following sources: +*\*\ - The timing unit: Compare 2, Compare 4 and Update (3 events). +*\*\ - The master timer: Reset and Compare 1..4 (5 events). +*\*\ - The external events EXTEVNT1..10 (10 events). +*\*\ - All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param ResetTrig This parameter can be a combination of the following values: +*\*\ - SHRTIM_RESETTRIG_NONE +*\*\ - SHRTIM_RESETTRIG_UPDATE +*\*\ - SHRTIM_RESETTRIG_CMP2 +*\*\ - SHRTIM_RESETTRIG_CMP4 +*\*\ - SHRTIM_RESETTRIG_MASTER_PER +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP1 +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP2 +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP3 +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP4 +*\*\ - SHRTIM_RESETTRIG_EXEV_1 +*\*\ - SHRTIM_RESETTRIG_EXEV_2 +*\*\ - SHRTIM_RESETTRIG_EXEV_3 +*\*\ - SHRTIM_RESETTRIG_EXEV_4 +*\*\ - SHRTIM_RESETTRIG_EXEV_5 +*\*\ - SHRTIM_RESETTRIG_EXEV_6 +*\*\ - SHRTIM_RESETTRIG_EXEV_7 +*\*\ - SHRTIM_RESETTRIG_EXEV_8 +*\*\ - SHRTIM_RESETTRIG_EXEV_9 +*\*\ - SHRTIM_RESETTRIG_EXEV_10 +*\*\ - SHRTIM_RESETTRIG_OTHER1_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER1_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER1_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER2_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER2_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER2_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER3_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER3_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER3_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER4_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER4_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER4_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER5_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER5_CMP2 +*\*\return None +**/ +void SHRTIM_TIM_SetResetTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t ResetTrig) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCNTRST) + + REG_OFFSET_TAB_TIMER[iTimer])); + WRITE_REG(*pReg, ResetTrig); +} + +/** +*\*\fun Get actual reset trigger of a timer counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return ResetTrig Returned value can be one of the following values: +*\*\ - SHRTIM_RESETTRIG_NONE +*\*\ - SHRTIM_RESETTRIG_UPDATE +*\*\ - SHRTIM_RESETTRIG_CMP2 +*\*\ - SHRTIM_RESETTRIG_CMP4 +*\*\ - SHRTIM_RESETTRIG_MASTER_PER +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP1 +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP2 +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP3 +*\*\ - SHRTIM_RESETTRIG_MASTER_CMP4 +*\*\ - SHRTIM_RESETTRIG_EXEV_1 +*\*\ - SHRTIM_RESETTRIG_EXEV_2 +*\*\ - SHRTIM_RESETTRIG_EXEV_3 +*\*\ - SHRTIM_RESETTRIG_EXEV_4 +*\*\ - SHRTIM_RESETTRIG_EXEV_5 +*\*\ - SHRTIM_RESETTRIG_EXEV_6 +*\*\ - SHRTIM_RESETTRIG_EXEV_7 +*\*\ - SHRTIM_RESETTRIG_EXEV_8 +*\*\ - SHRTIM_RESETTRIG_EXEV_9 +*\*\ - SHRTIM_RESETTRIG_EXEV_10 +*\*\ - SHRTIM_RESETTRIG_OTHER1_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER1_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER1_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER2_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER2_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER2_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER3_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER3_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER3_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER4_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER4_CMP2 +*\*\ - SHRTIM_RESETTRIG_OTHER4_CMP4 +*\*\ - SHRTIM_RESETTRIG_OTHER5_CMP1 +*\*\ - SHRTIM_RESETTRIG_OTHER5_CMP2 +**/ +uint32_t SHRTIM_TIM_GetResetTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxRST1) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_REG(*pReg)); +} + +/** +*\*\fun Get captured value for capture unit 1. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Captured value +**/ +uint32_t SHRTIM_TIM_GetCapture1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCPT1) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_REG(*pReg)); +} + +/** +*\*\fun Get the counting direction when capture 1 event occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Filter This parameter can be one of the following values: +*\*\ - SHRTIM_COUNTING_MODE_UP +*\*\ - SHRTIM_COUNTING_MODE_UP_DOWN +**/ +uint32_t SHRTIM_TIM_GetCapture1Direction(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCPT1) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXCPT1_UDSTS1) >> SHRTIM_TXCPT1_UDSTS1_Pos) << SHRTIM_TXCTRL2_UPDOWNM_Pos); +} + +/** +*\*\fun Get captured value for capture unit 2. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Captured value +**/ +uint32_t SHRTIM_TIM_GetCapture2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCPT2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_REG(*pReg)); +} + +/** +*\*\fun Get the counting direction when capture 2 event occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Filter This parameter can be one of the following values: +*\*\ - SHRTIM_COUNTING_MODE_UP +*\*\ - SHRTIM_COUNTING_MODE_UP_DOWN +**/ +uint32_t SHRTIM_TIM_GetCapture2Direction(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCPT2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXCPT2_UDSTS2) >> SHRTIM_TXCPT2_UDSTS2_Pos) << SHRTIM_TXCTRL2_UPDOWNM_Pos); +} + +/** +*\*\fun Set the trigger of a capture unit for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CaptureUnit This parameter can be one of the following values: +*\*\ - SHRTIM_CAPTUREUNIT_1 +*\*\ - SHRTIM_CAPTUREUNIT_2 +*\*\param CaptureTrig This parameter can be a combination of the following values: +*\*\ - SHRTIM_CAPTURETRIG_NONE +*\*\ - SHRTIM_CAPTURETRIG_SW +*\*\ - SHRTIM_CAPTURETRIG_UPDATE +*\*\ - SHRTIM_CAPTURETRIG_EXEV_1 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_2 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_3 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_4 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_5 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_6 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_7 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_8 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_9 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_10 +*\*\ - SHRTIM_CAPTURETRIG_TA1_SET +*\*\ - SHRTIM_CAPTURETRIG_TA1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMA_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMA_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TB1_SET +*\*\ - SHRTIM_CAPTURETRIG_TB1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMB_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMB_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TC1_SET +*\*\ - SHRTIM_CAPTURETRIG_TC1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMC_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMC_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TD1_SET +*\*\ - SHRTIM_CAPTURETRIG_TD1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMD_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMD_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TE1_SET +*\*\ - SHRTIM_CAPTURETRIG_TE1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIME_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIME_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TF1_SET +*\*\ - SHRTIM_CAPTURETRIG_TF1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMF_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMF_CMP2 +*\*\return None +**/ +void SHRTIM_TIM_SetCaptureTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CaptureUnit, + uint64_t CaptureTrig) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0U].TxCPT1CTRL) + + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + + uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU); + uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U); + + cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer])); + + WRITE_REG(*pReg, (cfg1 | cfg2)); +} + +/** +*\*\fun Get actual trigger of a capture unit for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param CaptureUnit This parameter can be one of the following values: +*\*\ - SHRTIM_CAPTUREUNIT_1 +*\*\ - SHRTIM_CAPTUREUNIT_2 +*\*\return CaptureTrig This parameter can be a combination of the following values: +*\*\ - SHRTIM_CAPTURETRIG_NONE +*\*\ - SHRTIM_CAPTURETRIG_SW +*\*\ - SHRTIM_CAPTURETRIG_UPDATE +*\*\ - SHRTIM_CAPTURETRIG_EXEV_1 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_2 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_3 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_4 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_5 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_6 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_7 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_8 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_9 +*\*\ - SHRTIM_CAPTURETRIG_EXEV_10 +*\*\ - SHRTIM_CAPTURETRIG_TA1_SET +*\*\ - SHRTIM_CAPTURETRIG_TA1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMA_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMA_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TB1_SET +*\*\ - SHRTIM_CAPTURETRIG_TB1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMB_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMB_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TC1_SET +*\*\ - SHRTIM_CAPTURETRIG_TC1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMC_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMC_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TD1_SET +*\*\ - SHRTIM_CAPTURETRIG_TD1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMD_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMD_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TE1_SET +*\*\ - SHRTIM_CAPTURETRIG_TE1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIME_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIME_CMP2 +*\*\ - SHRTIM_CAPTURETRIG_TF1_SET +*\*\ - SHRTIM_CAPTURETRIG_TF1_RESET +*\*\ - SHRTIM_CAPTURETRIG_TIMF_CMP1 +*\*\ - SHRTIM_CAPTURETRIG_TIMF_CMP2 +**/ +uint64_t SHRTIM_TIM_GetCaptureTrig(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t CaptureUnit) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0U].TxCPT1CTRL) + + (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U))); + + uint64_t cfg; + uint32_t CaptureTrig = READ_REG(*pReg); + + cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer]))); + + return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U))); +} + +/** +*\*\fun Enable deadtime insertion for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableDeadTime(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXOUT_DTEN); +} + +/** +*\*\fun Disable deadtime insertion for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableDeadTime(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXOUT_DTEN); +} + +/** +*\*\fun Indicate whether deadtime insertion is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DTEN bit in SHRTIM_TxOUT register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledDeadTime(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXOUT_DTEN) == (SHRTIM_TXOUT_DTEN)) ? 1UL : 0UL); +} + + +/** +*\*\fun Set the delayed protection (DP) mode. +*\*\note This function must be called prior enabling the delayed protection +*\*\note Balanced Idle mode is only available in push-pull mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param DPMode Delayed protection (DP) mode + * +*\*\ For timers A, B and C this parameter can be one of the following values: +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV6 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV6 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV6 +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV7 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV7 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV7 + * +*\*\ For timers D, E and F this parameter can be one of the following values: +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV8 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV8 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV8 +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV9 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV9 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV9 +*\*\return None +**/ +void SHRTIM_TIM_SetDPMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t DPMode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXOUT_DP, DPMode); +} + +/** +*\*\fun Get the delayed protection (DP) mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return DPMode Delayed protection (DP) mode + * +*\*\ For timers A, B and C this parameter can be one of the following values: +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV6 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV6 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV6 +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV7 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV7 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV7 + * +*\*\ For timers D, E and F this parameter can be one of the following values: +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV8 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV8 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV8 +*\*\ - SHRTIM_DP_DELAYOUT1_EXEV9 +*\*\ - SHRTIM_DP_DELAYOUT2_EXEV9 +*\*\ - SHRTIM_DP_DELAYBOTH_EXEV9 +**/ +uint32_t SHRTIM_TIM_GetDPMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXOUT_DP)); +} + +/** +*\*\fun Enable delayed protection (DP) for a given timer. +*\*\note This function must not be called once the concerned timer is enabled +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableDP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXOUT_DPEN); +} + +/** +*\*\fun Disable delayed protection (DP) for a given timer. +*\*\note This function must not be called once the concerned timer is enabled +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableDP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXOUT_DPEN); +} + +/** +*\*\fun Indicate whether delayed protection (DP) is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DPEN bit in SHRTIM_TxOUT register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledDP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXOUT_DPEN) == (SHRTIM_TXOUT_DPEN)) ? 1UL : 0UL); +} + +/** +*\*\param Enable the Balanced Idle Automatic Resume (BIAR) for a given timer. +*\*\param This function must not be called once the concerned timer is enabled +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableBIAR(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXOUT_BIAR); +} + +/** +*\*\param Disable the Balanced Idle Automatic Resume (BIAR) for a given timer. +*\*\param This function must not be called once the concerned timer is enabled +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableBIAR(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0U].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXOUT_BIAR); +} + +/** +*\*\param Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DPEN bit in SHRTIM_TxOUT register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledBIAR(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXOUT_BIAR) == (SHRTIM_TXOUT_BIAR)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the software delay protection +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SoftDP This parameter can be a combination of the following values: +*\*\ - SHRTIM_SOFT_DP_TA1 +*\*\ - SHRTIM_SOFT_DP_TA2 +*\*\ - SHRTIM_SOFT_DP_TB1 +*\*\ - SHRTIM_SOFT_DP_TB2 +*\*\ - SHRTIM_SOFT_DP_TC1 +*\*\ - SHRTIM_SOFT_DP_TC2 +*\*\ - SHRTIM_SOFT_DP_TD1 +*\*\ - SHRTIM_SOFT_DP_TD2 +*\*\ - SHRTIM_SOFT_DP_TE1 +*\*\ - SHRTIM_SOFT_DP_TE2 +*\*\ - SHRTIM_SOFT_DP_TF1 +*\*\ - SHRTIM_SOFT_DP_TF2 +*\*\return None +**/ +void SHRTIM_TIM_EnableSoftDP(SHRTIM_Module *SHRTIMx, uint32_t SoftDP) +{ + SET_BIT(SHRTIMx->sCommonRegs.SFTDP, (SoftDP & SHRTIM_SFTDP_CONFIG_MASK)); +} + +/** +*\*\fun Indicate whether the soft delay protection is enabled for a given channel. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SoftDP This parameter can be a combination of the following values: +*\*\ - SHRTIM_SOFT_DP_TA1 +*\*\ - SHRTIM_SOFT_DP_TA2 +*\*\ - SHRTIM_SOFT_DP_TB1 +*\*\ - SHRTIM_SOFT_DP_TB2 +*\*\ - SHRTIM_SOFT_DP_TC1 +*\*\ - SHRTIM_SOFT_DP_TC2 +*\*\ - SHRTIM_SOFT_DP_TD1 +*\*\ - SHRTIM_SOFT_DP_TD2 +*\*\ - SHRTIM_SOFT_DP_TE1 +*\*\ - SHRTIM_SOFT_DP_TE2 +*\*\ - SHRTIM_SOFT_DP_TF1 +*\*\ - SHRTIM_SOFT_DP_TF2 +*\*\return State of SFTDPxy bit in SHRTIM_SFTDP register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledSoftDP(SHRTIM_Module *SHRTIMx, uint32_t SoftDP) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.SFTDP, SoftDP) == (SoftDP)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault channel(s) for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Faults This parameter can be a combination of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_TIM_EnableFault(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Faults) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxFALT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, Faults); +} + +/** +*\*\fun Disable the fault channel(s) for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Faults This parameter can be a combination of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_TIM_DisableFault(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Faults) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxFALT) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, Faults); +} + +/** +*\*\fun Indicate whether the fault channel is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return State of FALTxEN bit in SHRTIM_TxFALT register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledFault(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Fault) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxFALT) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); +} + +/** +*\*\fun Lock the fault conditioning set-up for a given timer. +*\*\note Timer fault-related set-up is frozen until the next SHRTIM or system reset +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_LockFault(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxFALT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXFALT_FALTLCK); +} + +/** +*\*\fun Define how the timer behaves during a burst mode operation. +*\*\note This function must not be called when the burst mode is enabled +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param BurtsModeOption This parameter can be one of the following values: +*\*\ - SHRTIM_BURSTMODE_MAINTAINCLOCK +*\*\ - SHRTIM_BURSTMODE_RESETCOUNTER +*\*\return None +**/ +void SHRTIM_TIM_SetBurstModeOption(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t BurtsModeOption) +{ + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos) & 0x1FU); + MODIFY_REG(SHRTIMx->sCommonRegs.BMCTRL, Timer, BurtsModeOption << iTimer); +} + +/** +*\*\fun Retrieve how the timer behaves during a burst mode operation. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return BurtsMode This parameter can be one of the following values: +*\*\ - SHRTIM_BURSTMODE_MAINTAINCLOCK +*\*\ - SHRTIM_BURSTMODE_RESETCOUNTER +**/ +uint32_t SHRTIM_TIM_GetBurstModeOption(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos) & 0x1FU); + return (READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, Timer) >> iTimer); +} + +/** +*\*\fun Program which registers are to be written by Burst DMA transfers. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Registers Registers to be updated by the DMA request +*\*\ For Master timer this parameter can be can be a combination of the following values: +*\*\ - SHRTIM_BURSTDMA_NONE +*\*\ - SHRTIM_BURSTDMA_MCTRL +*\*\ - SHRTIM_BURSTDMA_MINTCLR +*\*\ - SHRTIM_BURSTDMA_MIDEN +*\*\ - SHRTIM_BURSTDMA_MCNT +*\*\ - SHRTIM_BURSTDMA_MPRD +*\*\ - SHRTIM_BURSTDMA_MREPT +*\*\ - SHRTIM_BURSTDMA_MCMPDAT1 +*\*\ - SHRTIM_BURSTDMA_MCMPDAT2 +*\*\ - SHRTIM_BURSTDMA_MCMPDAT3 +*\*\ - SHRTIM_BURSTDMA_MCMPDAT4 +*\*\ For Timers A..F this parameter can be can be a combination of the following values: +*\*\ - SHRTIM_BURSTDMA_TXCTRL +*\*\ - SHRTIM_BURSTDMA_TXINTCLR +*\*\ - SHRTIM_BURSTDMA_TXIDEN +*\*\ - SHRTIM_BURSTDMA_TXCNT +*\*\ - SHRTIM_BURSTDMA_TXPRD +*\*\ - SHRTIM_BURSTDMA_TXREPT +*\*\ - SHRTIM_BURSTDMA_TXCMP1DAT +*\*\ - SHRTIM_BURSTDMA_TXCMP2DAT +*\*\ - SHRTIM_BURSTDMA_TXCMP3DAT +*\*\ - SHRTIM_BURSTDMA_TXCMP4DAT +*\*\ - SHRTIM_BURSTDMA_TXDT +*\*\ - SHRTIM_BURSTDMA_TXSET1 +*\*\ - SHRTIM_BURSTDMA_TXRST1 +*\*\ - SHRTIM_BURSTDMA_TXSET2 +*\*\ - SHRTIM_BURSTDMA_TXRST2 +*\*\ - SHRTIM_BURSTDMA_TXEXEVFLT1 +*\*\ - SHRTIM_BURSTDMA_TXEXEVFLT2 +*\*\ - SHRTIM_BURSTDMA_TXCNTRST +*\*\ - SHRTIM_BURSTDMA_TXCHOP +*\*\ - SHRTIM_BURSTDMA_TXOUT +*\*\ - SHRTIM_BURSTDMA_TXFALT +*\*\ - SHRTIM_BURSTDMA_TXCTRL2 +*\*\ - SHRTIM_BURSTDMA_TXEXEVFLT3 +*\*\return None +**/ +void SHRTIM_TIM_ConfigBurstDMA(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Registers) +{ + const uint8_t REG_OFFSET_TAB_BDTUPR[] = + { + 0x00U, /* BDMUPR ; offset = 0x000 */ + 0x04U, /* BDAUPR ; offset = 0x05C */ + 0x08U, /* BDBUPR ; offset = 0x060 */ + 0x0CU, /* BDCUPR ; offset = 0x064 */ + 0x10U, /* BDDUPR ; offset = 0x068 */ + 0x14U, /* BDEUPR ; offset = 0x06C */ + 0x1CU /* BDFUPR ; offset = 0x074 */ + }; + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.BDMTUPD) + REG_OFFSET_TAB_BDTUPR[iTimer])); + WRITE_REG(*pReg, Registers); +} + +/** +*\*\fun Indicate on which output the signal is currently applied. +*\*\note Only significant when the timer operates in push-pull mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return CPPSTAT This parameter can be one of the following values: +*\*\ - SHRTIM_CPPSTAT_OUTPUT1 +*\*\ - SHRTIM_CPPSTAT_OUTPUT2 +**/ +uint32_t SHRTIM_TIM_GetCurrentPushPullStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXINTSTS_CPPSTS)); +} + +/** +*\*\fun Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return IPPSTAT This parameter can be one of the following values: +*\*\ - SHRTIM_IPPSTAT_OUTPUT1 +*\*\ - SHRTIM_IPPSTAT_OUTPUT2 +**/ +uint32_t SHRTIM_TIM_GetIdlePushPullStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXINTSTS_IPPSTS)); +} + +/** +*\*\fun Window selection when EXEVxFLT = 0b'1111. +In up-down counting mode (SHRTIM_TxCTRL2.UPDOWNM bit set): windowing from compare 2 +during the up-counting phase to compare 3 during the down-counting phase. +If EXEVWINSEL = 0, compare 2 is from another timer unit(refer to Table 9-19); +if EXEVWINSEL = 1, compare 2 is from timer unit itself. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableEventWindowSelection(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXEXEVFLT1_EXEVWINSEL); +} + +/** +*\*\fun Window selection when EXEVxFLT = 0b'1111. +In up-down counting mode (SHRTIM_TxCTRL2.UPDOWNM bit set): windowing from compare 2 +during the up-counting phase to compare 3 during the down-counting phase. +If EXEVWINSEL = 0, compare 2 is from another timer unit(refer to Table 9-19); +if EXEVWINSEL = 1, compare 2 is from timer unit itself. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisbleEventWindowSelection(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXEXEVFLT1_EXEVWINSEL); +} + +/** +*\*\fun Set the event filter for a given timer. +*\*\note This function must not be called when the timer counter is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param Filter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEVFLT_NONE +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP3 +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF1_TIMBCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF2_TIMBCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF3_TIMBOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF4_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF5_TIMCCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF6_TIMFCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF7_TIMDCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF8_TIMECMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF1_TIMACMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF2_TIMACMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF3_TIMAOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF4_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF5_TIMCCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF6_TIMFCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF7_TIMDCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF8_TIMECMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF1_TIMACMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF2_TIMBCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF3_TIMBCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF4_TIMFCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF5_TIMDCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF6_TIMDCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF7_TIMDOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF8_TIMECMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF1_TIMACMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF2_TIMBCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF3_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF4_TIMCCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF5_TIMCOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF6_TIMECMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF7_TIMECMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF8_TIMFCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF1_TIMACMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF2_TIMBCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF3_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF4_TIMFCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF5_TIMFOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF6_TIMDCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF7_TIMDCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF8_TIMDOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF1_TIMACMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF2_TIMBCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF3_TIMCCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF4_TIMDCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF5_TIMDCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF6_TIMECMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF7_TIMECMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF8_TIMEOUT2 +*\*\ - SHRTIM_EXEVFLT_WINDOWINGCMP2 +*\*\ - SHRTIM_EXEVFLT_WINDOWINGCMP3 +*\*\ - SHRTIM_EXEVFLT_WINDOWINGTIM +*\*\return None +**/ +void SHRTIM_TIM_SetEventFilter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + __IO uint32_t *pRegWinSelBypass = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, (SHRTIM_TXEXEVFLT1_EXEV1FLT << REG_SHIFT_TAB_EXEVx[iEvent]), (Filter << REG_SHIFT_TAB_EXEVx[iEvent])); + SET_BIT(*pRegWinSelBypass, SHRTIM_TXEXEVFLT1_EXEVWINSEL); +} + +/** +*\*\fun Get actual event filter settings for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return Filter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEVFLT_NONE +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP3 +*\*\ - SHRTIM_EXEVFLT_BLANKINGCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF1_TIMBCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF2_TIMBCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF3_TIMBOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF4_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF5_TIMCCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF6_TIMFCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF7_TIMDCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMAEEF8_TIMECMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF1_TIMACMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF2_TIMACMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF3_TIMAOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF4_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF5_TIMCCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF6_TIMFCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF7_TIMDCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMBEEF8_TIMECMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF1_TIMACMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF2_TIMBCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF3_TIMBCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF4_TIMFCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF5_TIMDCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF6_TIMDCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF7_TIMDOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMCEEF8_TIMECMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF1_TIMACMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF2_TIMBCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF3_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF4_TIMCCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF5_TIMCOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF6_TIMECMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF7_TIMECMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMDEEF8_TIMFCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF1_TIMACMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF2_TIMBCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF3_TIMCCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF4_TIMFCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF5_TIMFOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF6_TIMDCMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF7_TIMDCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMEEEF8_TIMDOUT2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF1_TIMACMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF2_TIMBCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF3_TIMCCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF4_TIMDCMP2 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF5_TIMDCMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF6_TIMECMP1 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF7_TIMECMP4 +*\*\ - SHRTIM_EXEVFLT_BLANKING_TIMFEEF8_TIMEOUT2 +*\*\ - SHRTIM_EXEVFLT_WINDOWINGCMP2 +*\*\ - SHRTIM_EXEVFLT_WINDOWINGCMP3 +*\*\ - SHRTIM_EXEVFLT_WINDOWINGTIM +**/ +uint32_t SHRTIM_TIM_GetEventFilter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT1_EXEV1FLT) << (REG_SHIFT_TAB_EXEVx[iEvent])) >> (REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Enable or disable event latch mechanism for a given timer. +*\*\note This function must not be called when the timer counter is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param LatchStatus This parameter can be one of the following values: +*\*\ - SHRTIM_EXEVLATCH_DISABLED +*\*\ - SHRTIM_EXEVLATCH_ENABLED +*\*\return None +**/ +void SHRTIM_TIM_SetEventLatchStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event, + uint32_t LatchStatus) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + MODIFY_REG(*pReg, (SHRTIM_TXEXEVFLT1_EXEV1LATCH << REG_SHIFT_TAB_EXEVx[iEvent]), (LatchStatus << REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Get actual event latch status for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return LatchStatus This parameter can be one of the following values: +*\*\ - SHRTIM_EXEVLATCH_DISABLED +*\*\ - SHRTIM_EXEVLATCH_ENABLED +**/ +uint32_t SHRTIM_TIM_GetEventLatchStatus(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Event) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxEXEVFLT1) + + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT1_EXEV1LATCH) << REG_SHIFT_TAB_EXEVx[iEvent]) >> (REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Select the Trigger-Half operating mode for a given timer. +*\*\note This bitfield defines whether the compare 2 register +*\*\note is behaving in standard mode (compare match issued as soon as counter equal compare) +*\*\note or in triggered-half mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_TRIGHALF_ENABLED +*\*\ - SHRTIM_TRIGHALF_DISABLED +*\*\return None +**/ +void SHRTIM_TIM_SetTriggeredHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_TRGHLF, Mode); +} + +/** +*\*\fun Get the Trigger-Half operating mode for a given timer. +*\*\note This bitfield reports whether the compare 2 register +*\*\note is behaving in standard mode (compare match issued as soon as counter equal compare) +*\*\note or in triggered-half mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode This parameter can be one of the following values: +*\*\ - SHRTIM_TRIGHALF_ENABLED +*\*\ - SHRTIM_TRIGHALF_DISABLED +**/ +uint32_t SHRTIM_TIM_GetTriggeredHalfMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_TRGHLF)); +} + +/** +*\*\fun Select the compare 1 operating mode. +*\*\note This bit defines the compare 1 operating mode: +*\*\note 0: the compare 1 event is generated when the counter is equal to the compare value +*\*\note 1: the compare 1 event is generated when the counter is greater than the compare value +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_GTCMP1_EQUAL +*\*\ - SHRTIM_GTCMP1_GREATER +*\*\return None +**/ +void SHRTIM_TIM_SetComp1Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_GTCMP1, Mode); +} + +/** +*\*\fun Get the selected compare 1 operating mode. +*\*\note This bit reports the compare 1 operating mode: +*\*\note 0: the compare 1 event is generated when the counter is equal to the compare value +*\*\note 1: the compare 1 event is generated when the counter is greater than the compare value +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode This parameter can be one of the following values: +*\*\ - SHRTIM_GTCMP1_EQUAL +*\*\ - SHRTIM_GTCMP1_GREATER +**/ +uint32_t SHRTIM_TIM_GetComp1Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_GTCMP1)); +} + +/** +*\*\fun Select the compare 3 operating mode. +*\*\note This bit defines the compare 3 operating mode: +*\*\note 0: the compare 3 event is generated when the counter is equal to the compare value +*\*\note 1: the compare 3 event is generated when the counter is greater than the compare value +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_GTCMP3_EQUAL +*\*\ - SHRTIM_GTCMP3_GREATER +*\*\return None +**/ +void SHRTIM_TIM_SetComp3Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_GTCMP3, (Mode)); +} + +/** +*\*\fun Get the selected compare 3 operating mode. +*\*\note This bit reports the compare 3 operating mode: +*\*\note 0: the compare 3 event is generated when the counter is equal to the compare value +*\*\note 1: the compare 3 event is generated when the counter is greater than the compare value +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode This parameter can be one of the following values: +*\*\ - SHRTIM_GTCMP3_EQUAL +*\*\ - SHRTIM_GTCMP3_GREATER +**/ +uint32_t SHRTIM_TIM_GetComp3Mode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0U].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_GTCMP3)); +} + +/** +*\*\fun Select the roll-over mode. +*\*\note Only significant in up-down counting mode (see function SHRTIM_TIM_SetCountingMode()). +*\*\note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ + * and DMA requests, repetition counter decrement and External Event filtering. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +*\*\return None +**/ +void SHRTIM_TIM_SetRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_ROM, (Mode << SHRTIM_TXCTRL2_ROM_Pos)); +} + +/** +*\*\fun Get selected the roll-over mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode returned value can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +**/ +uint32_t SHRTIM_TIM_GetRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_ROM) >> SHRTIM_TXCTRL2_ROM_Pos); +} + +/** +*\*\fun Select Fault and Event roll-over mode. +*\*\note Only significant in up-down counting mode (see function SHRTIM_TIM_SetCountingMode()). +*\*\note only concerns the Roll-over event used by the Fault and Event counters. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +*\*\return None +**/ +void SHRTIM_TIM_SetFaultEventRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_FEROM, (Mode << SHRTIM_TXCTRL2_FEROM_Pos)); +} + +/** +*\*\fun Get selected Fault and Event role-over mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode returned value can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +**/ +uint32_t SHRTIM_TIM_GetFaultEventRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_FEROM) >> SHRTIM_TXCTRL2_FEROM_Pos); +} + +/** +*\*\fun Select the Burst mode roll-over mode. +*\*\note Only significant in up-down counting mode (see function SHRTIM_TIM_SetCountingMode()). +*\*\note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +*\*\return None +**/ +void SHRTIM_TIM_SetBMRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_BMROM, (Mode << SHRTIM_TXCTRL2_BMROM_Pos)); +} + +/** +*\*\fun Get selected Burst mode roll-over mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode returned value can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +**/ +uint32_t SHRTIM_TIM_GetBMRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_BMROM) >> SHRTIM_TXCTRL2_BMROM_Pos); +} + +/** +*\*\fun Select the ADC roll-over mode. +*\*\note Only significant in up-down counting mode (see function SHRTIM_TIM_SetCountingMode()). +*\*\note Only concerns the Roll-over event used to trigger the ADC. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +*\*\return None +**/ +void SHRTIM_TIM_SetADCRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_ADCROM, (Mode << SHRTIM_TXCTRL2_ADCROM_Pos)); +} + +/** +*\*\fun Get selected ADC roll-over mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode returned value can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +**/ +uint32_t SHRTIM_TIM_GetADCRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_ADCROM) >> SHRTIM_TXCTRL2_ADCROM_Pos); +} + +/** +*\*\fun Select the ADC roll-over mode. +*\*\note Only significant in up-down counting mode (see function SHRTIM_TIM_SetCountingMode()). +*\*\note Only concerns concerns the Roll-over event which sets and/or resets the outputs, + * as per SHRTIM_SETxyR and SHRTIM_RSTxyR settings (see function SHRTIM_OUT_SetOutputSetSrc() + * and function SHRTIM_OUT_SetOutputResetSrc() respectively). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +*\*\return None +**/ +void SHRTIM_TIM_SetOutputRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_OUTROM, (Mode << SHRTIM_TXCTRL2_OUTROM_Pos)); +} + +/** +*\*\fun Get selected ADC roll-over mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode returned value can be one of the following values: +*\*\ - SHRTIM_ROLLOVER_MODE_PER +*\*\ - SHRTIM_ROLLOVER_MODE_RST +*\*\ - SHRTIM_ROLLOVER_MODE_BOTH +**/ +uint32_t SHRTIM_TIM_GetOutputRollOverMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_OUTROM) >> SHRTIM_TXCTRL2_OUTROM_Pos); +} + +/** +*\*\fun Select the counting mode. +*\*\note The up-down counting mode is available for both continuous and single-shot + * (retriggerable and nonretriggerable) operating modes + * (see function SHRTIM_TIM_SetCounterMode()). +*\*\note The counter roll-over event is defined differently in-up-down counting mode to + * support various operating condition. + * See SHRTIM_TIM_SetCounterMode() +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_COUNTING_MODE_UP +*\*\ - SHRTIM_COUNTING_MODE_UP_DOWN +*\*\return None +**/ +void SHRTIM_TIM_SetCountingMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_UPDOWNM, Mode); +} + +/** +*\*\fun Get selected counting mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Mode returned value can be one of the following values: +*\*\ - SHRTIM_COUNTING_MODE_UP +*\*\ - SHRTIM_COUNTING_MODE_UP_DOWN +*\*\return None +**/ +uint32_t SHRTIM_TIM_GetCountingMode(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_UPDOWNM)); +} + +/** +*\*\fun Select Dual DAC Reset trigger. +*\*\note Significant only when Dual DAC trigger is enabled + * (see function SHRTIM_TIM_EnableDualDacTrigger()). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_DUDACRST_COUNTER +*\*\ - SHRTIM_DUDACRST_OUT1SET +*\*\return None +**/ +void SHRTIM_TIM_SetDualDacResetTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_DUDACRST, Mode); +} + +/** +*\*\fun Get selected Dual DAC Reset trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Trigger returned value can be one of the following values: +*\*\ - SHRTIM_DUDACRST_COUNTER +*\*\ - SHRTIM_DUDACRST_OUT1SET +**/ +uint32_t SHRTIM_TIM_GetDualDacResetTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_DUDACRST)); +} + +/** +*\*\fun Select Dual DAC Step trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_DUDACSTEP_CMP2 +*\*\ - SHRTIM_DUDACSTEP_OUT1RST +*\*\return None +**/ +void SHRTIM_TIM_SetDualDacStepTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCTRL2_DUDACSTEP, Mode); +} + +/** +*\*\fun Get selected Dual DAC Step trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Trigger returned value can be one of the following values: +*\*\ - SHRTIM_DUDACSTEP_CMP2 +*\*\ - SHRTIM_DUDACSTEP_OUT1RST +**/ +uint32_t SHRTIM_TIM_GetDualDacStepTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCTRL2_DUDACSTEP)); +} + +/** +*\*\fun Enable Dual DAC trigger. +*\*\note Only significant when balanced Idle mode is enabled (see function SHRTIM_TIM_SetDPMode()). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_EnableDualDacTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXCTRL2_DUDACEN); +} + +/** +*\*\fun Disable Dual DAC trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_TIM_DisableDualDacTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXCTRL2_DUDACEN); +} + +/** +*\*\fun Indicate whether Dual DAC trigger is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DUDACEN bit in SHRTIM_TxCTRL2 register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledDualDacTrigger(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCTRL2) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXCTRL2_DUDACEN) == (SHRTIM_TXCTRL2_DUDACEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the external event counter threshold. +*\*\note The external event is propagated to the timer only if the number + * of active edges is greater than the external event counter threshold. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63 +*\*\return None +**/ +void SHRTIM_TIM_SetEventCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter, + uint32_t Threshold) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + MODIFY_REG(*pReg, (SHRTIM_TXEXEVFLT3_EXEVCNT << EventCounter), Threshold << (SHRTIM_TXEXEVFLT3_EXEVCNT_Pos + EventCounter)); +} + +/** +*\*\fun Get the programmed external event counter threshold. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return Threshold Value between Min_Data=0 and Max_Data=63 +**/ +uint32_t SHRTIM_TIM_GetEventCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + return ((READ_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT3_EXEVCNT) << EventCounter)) >> ((SHRTIM_TXEXEVFLT3_EXEVCNT_Pos + EventCounter))); +} + +/** +*\*\fun Select the external event counter source. +*\*\note External event counting is only valid for edge-sensitive + * external events (See function SHRTIM_EXEV_Config() and function + * SHRTIM_EXEV_SetSensitivity()). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return None +**/ +void SHRTIM_TIM_SetEventCounterSource(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter, + uint32_t Event) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + uint32_t iEvent = (uint32_t)(POSITION_VAL(Event)); + + /* register SEL value is 0 if SHRTIM_EVENT_1, 1 if SHRTIM_EVENT_1, etc + and 9 if SHRTIM_EVENT_10 */ + MODIFY_REG(*pReg, (SHRTIM_TXEXEVFLT3_EXEVSEL << EventCounter), iEvent << (SHRTIM_TXEXEVFLT3_EXEVSEL_Pos + EventCounter)); +} + +/** +*\*\fun get the selected external event counter source. + * SHRTIM_EXEV_SetSensitivity()). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +**/ +uint32_t SHRTIM_TIM_GetEventCounterSource(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT3_EXEVSEL) << (EventCounter))) >> ((SHRTIM_TXEXEVFLT3_EXEVSEL_Pos + EventCounter)); + + /* returned value is 0 if SEL is SHRTIM_EVENT_1, 1 if SEL is SHRTIM_EVENT_1, etc + and 9 if SEL is SHRTIM_EVENT_10 */ + return ((uint32_t)0x1U << iEvent); +} + +/** +*\*\fun Select the external event counter reset mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_RSTMODE_UNCONDITIONAL +*\*\ - SHRTIM_EXEV_COUNTER_RSTMODE_CONDITIONAL +*\*\return None +**/ +void SHRTIM_TIM_SetEventCounterResetMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter, + uint32_t Mode) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + MODIFY_REG(*pReg, (SHRTIM_TXEXEVFLT3_EXEVRSTM << (EventCounter)), Mode << (EventCounter)); +} + +/** +*\*\fun Get selected external event counter reset mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return Mode This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_RSTMODE_UNCONDITIONAL +*\*\ - SHRTIM_EXEV_COUNTER_RSTMODE_CONDITIONAL +**/ +uint32_t SHRTIM_TIM_GetEventCounterResetMode(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + return ((READ_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT3_EXEVRSTM) << (EventCounter))) >> (EventCounter)); +} + +/** +*\*\fun Reset the external event counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return None +**/ +void SHRTIM_TIM_ResetEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + SET_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT3_EXEVCNTRST) << EventCounter); +} + +/** +*\*\fun Enable the external event counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return None +**/ +void SHRTIM_TIM_EnableEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + SET_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT3_EXEVCNTEN) << EventCounter); +} + +/** +*\*\fun Disable the external event counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return None +**/ +void SHRTIM_TIM_DisableEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + CLEAR_BIT(*pReg, (SHRTIM_TXEXEVFLT3_EXEVCNTEN << EventCounter)); +} + +/** +*\*\fun Indicate whether the external event counter is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param EventCounter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_COUNTER_A +*\*\ - SHRTIM_EXEV_COUNTER_B +*\*\return State of EXEVCNTEN bit in SHRTIM_TxEXEVFLT3 register (1 or 0). +**/ +uint32_t SHRTIM_TIM_IsEnabledEventCounter(SHRTIM_Module *SHRTIMx, uint32_t Timer, + uint32_t EventCounter) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(SHRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[iTimer].TxEXEVFLT3))); + + uint32_t temp; /* MINTSTSAC-2012 compliance */ + temp = READ_BIT(*pReg, (uint32_t)(SHRTIM_TXEXEVFLT3_EXEVCNTEN) << EventCounter); + + return ((temp == ((uint32_t)(SHRTIM_TXEXEVFLT3_EXEVCNTEN) << EventCounter)) ? 1UL : 0UL); +} + +/** @defgroup SHRTIM_EF_Dead_Time_Configuration Dead_Time_Configuration +*\*\{ +**/ + +/** +*\*\fun Configure the dead time insertion feature for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Configuration This parameter must be a combination of all the following values: +*\*\ - SHRTIM_DT_PRESCALER_MUL8 or ... or SHRTIM_DT_PRESCALER_DIV16 +*\*\ - SHRTIM_DT_RISING_POSITIVE or SHRTIM_DT_RISING_NEGATIVE +*\*\ - SHRTIM_DT_FALLING_POSITIVE or SHRTIM_DT_FALLING_NEGATIVE +*\*\return None +**/ +void SHRTIM_DT_Config(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Configuration) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXDT_SDTF | SHRTIM_TXDT_DTPSC | SHRTIM_TXDT_SDTR, Configuration); +} + +/** +*\*\fun Set the deadtime prescaler value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_DT_PRESCALER_MUL8 +*\*\ - SHRTIM_DT_PRESCALER_MUL4 +*\*\ - SHRTIM_DT_PRESCALER_MUL2 +*\*\ - SHRTIM_DT_PRESCALER_DIV1 +*\*\ - SHRTIM_DT_PRESCALER_DIV2 +*\*\ - SHRTIM_DT_PRESCALER_DIV4 +*\*\ - SHRTIM_DT_PRESCALER_DIV8 +*\*\ - SHRTIM_DT_PRESCALER_DIV16 +*\*\return None +**/ +void SHRTIM_DT_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Prescaler) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXDT_DTPSC, Prescaler); +} + +/** +*\*\fun Get actual deadtime prescaler value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_DT_PRESCALER_MUL8 +*\*\ - SHRTIM_DT_PRESCALER_MUL4 +*\*\ - SHRTIM_DT_PRESCALER_MUL2 +*\*\ - SHRTIM_DT_PRESCALER_DIV1 +*\*\ - SHRTIM_DT_PRESCALER_DIV2 +*\*\ - SHRTIM_DT_PRESCALER_DIV4 +*\*\ - SHRTIM_DT_PRESCALER_DIV8 +*\*\ - SHRTIM_DT_PRESCALER_DIV16 +**/ +uint32_t SHRTIM_DT_GetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXDT_DTPSC)); +} + +/** +*\*\fun Set the deadtime rising value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param RisingValue Value between 0 and 0x1FF +*\*\return None +**/ +void SHRTIM_DT_SetRisingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t RisingValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXDT_DTR, RisingValue); +} + +/** +*\*\fun Get actual deadtime rising value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return RisingValue Value between 0 and 0x1FF +**/ +uint32_t SHRTIM_DT_GetRisingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXDT_DTR)); +} + +/** +*\*\fun Set the deadtime sign on rising edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param RisingSign This parameter can be one of the following values: +*\*\ - SHRTIM_DT_RISING_POSITIVE +*\*\ - SHRTIM_DT_RISING_NEGATIVE +*\*\return None +**/ +void SHRTIM_DT_SetRisingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t RisingSign) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXDT_SDTR, RisingSign); +} + +/** +*\*\fun Get actual deadtime sign on rising edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return RisingSign This parameter can be one of the following values: +*\*\ - SHRTIM_DT_RISING_POSITIVE +*\*\ - SHRTIM_DT_RISING_NEGATIVE +**/ +uint32_t SHRTIM_DT_GetRisingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXDT_SDTR)); +} + +/** +*\*\fun Set the deadime falling value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param FallingValue Value between 0 and 0x1FF +*\*\return None +**/ +void SHRTIM_DT_SetFallingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t FallingValue) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXDT_DTF, FallingValue << SHRTIM_TXDT_DTF_Pos); +} + +/** +*\*\fun Get actual deadtime falling value +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return FallingValue Value between 0 and 0x1FF +**/ +uint32_t SHRTIM_DT_GetFallingValue(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXDT_DTF)) >> SHRTIM_TXDT_DTF_Pos); +} + +/** +*\*\fun Set the deadtime sign on falling edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param FallingSign This parameter can be one of the following values: +*\*\ - SHRTIM_DT_FALLING_POSITIVE +*\*\ - SHRTIM_DT_FALLING_NEGATIVE +*\*\return None +**/ +void SHRTIM_DT_SetFallingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t FallingSign) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXDT_SDTF, FallingSign); +} + +/** +*\*\fun Get actual deadtime sign on falling edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return FallingSign This parameter can be one of the following values: +*\*\ - SHRTIM_DT_FALLING_POSITIVE +*\*\ - SHRTIM_DT_FALLING_NEGATIVE +**/ +uint32_t SHRTIM_DT_GetFallingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXDT_SDTF)); +} + +/** +*\*\fun Lock the deadtime value and sign on rising edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DT_LockRising(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXDT_DTRLCK); +} + +/** +*\*\fun Lock the deadtime sign on rising edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DT_LockRisingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXDT_DTRSLCK); +} + +/** +*\*\fun Lock the deadtime value and sign on falling edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DT_LockFalling(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXDT_DTFLCK); +} + +/** +*\*\fun Lock the deadtime sign on falling edge. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DT_LockFallingSign(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxDT) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXDT_DTFSLCK); +} + +/** @defgroup SHRTIM_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration +*\*\{ +**/ + +/** +*\*\fun Configure the chopper stage for a given timer. +*\*\note This function must not be called if the chopper mode is already + * enabled for one of the timer outputs. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Configuration This parameter must be a combination of all the following values: +*\*\ - SHRTIM_CHP_PRESCALER_DIV16 or ... or SHRTIM_CHP_PRESCALER_DIV256 +*\*\ - SHRTIM_CHP_DUTYCYCLE_0 or ... or SHRTIM_CHP_DUTYCYCLE_875 +*\*\ - SHRTIM_CHP_PULSEWIDTH_16 or ... or SHRTIM_CHP_PULSEWIDTH_256 +*\*\return None +**/ +void SHRTIM_CHP_Config(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Configuration) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCHOP_STARTPW | SHRTIM_TXCHOP_CARDCY | SHRTIM_TXCHOP_CARFRQ, Configuration); +} + +/** +*\*\fun Set prescaler determining the carrier frequency to be added on top +*\*\ of the timer output signals when chopper mode is enabled. +*\*\note This function must not be called if the chopper mode is already + * enabled for one of the timer outputs. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_CHP_PRESCALER_DIV16 +*\*\ - SHRTIM_CHP_PRESCALER_DIV32 +*\*\ - SHRTIM_CHP_PRESCALER_DIV48 +*\*\ - SHRTIM_CHP_PRESCALER_DIV64 +*\*\ - SHRTIM_CHP_PRESCALER_DIV80 +*\*\ - SHRTIM_CHP_PRESCALER_DIV96 +*\*\ - SHRTIM_CHP_PRESCALER_DIV112 +*\*\ - SHRTIM_CHP_PRESCALER_DIV128 +*\*\ - SHRTIM_CHP_PRESCALER_DIV144 +*\*\ - SHRTIM_CHP_PRESCALER_DIV160 +*\*\ - SHRTIM_CHP_PRESCALER_DIV176 +*\*\ - SHRTIM_CHP_PRESCALER_DIV192 +*\*\ - SHRTIM_CHP_PRESCALER_DIV208 +*\*\ - SHRTIM_CHP_PRESCALER_DIV224 +*\*\ - SHRTIM_CHP_PRESCALER_DIV240 +*\*\ - SHRTIM_CHP_PRESCALER_DIV256 +*\*\return None +**/ +void SHRTIM_CHP_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t Prescaler) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCHOP_CARFRQ, Prescaler); +} + +/** +*\*\fun Get actual chopper stage prescaler value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_CHP_PRESCALER_DIV16 +*\*\ - SHRTIM_CHP_PRESCALER_DIV32 +*\*\ - SHRTIM_CHP_PRESCALER_DIV48 +*\*\ - SHRTIM_CHP_PRESCALER_DIV64 +*\*\ - SHRTIM_CHP_PRESCALER_DIV80 +*\*\ - SHRTIM_CHP_PRESCALER_DIV96 +*\*\ - SHRTIM_CHP_PRESCALER_DIV112 +*\*\ - SHRTIM_CHP_PRESCALER_DIV128 +*\*\ - SHRTIM_CHP_PRESCALER_DIV144 +*\*\ - SHRTIM_CHP_PRESCALER_DIV160 +*\*\ - SHRTIM_CHP_PRESCALER_DIV176 +*\*\ - SHRTIM_CHP_PRESCALER_DIV192 +*\*\ - SHRTIM_CHP_PRESCALER_DIV208 +*\*\ - SHRTIM_CHP_PRESCALER_DIV224 +*\*\ - SHRTIM_CHP_PRESCALER_DIV240 +*\*\ - SHRTIM_CHP_PRESCALER_DIV256 +**/ +uint32_t SHRTIM_CHP_GetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCHOP_CARFRQ)); +} + +/** +*\*\fun Set the chopper duty cycle. +*\*\note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) +*\*\note This function must not be called if the chopper mode is already + * enabled for one of the timer outputs. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param DutyCycle This parameter can be one of the following values: +*\*\ - SHRTIM_CHP_DUTYCYCLE_0 +*\*\ - SHRTIM_CHP_DUTYCYCLE_125 +*\*\ - SHRTIM_CHP_DUTYCYCLE_250 +*\*\ - SHRTIM_CHP_DUTYCYCLE_375 +*\*\ - SHRTIM_CHP_DUTYCYCLE_500 +*\*\ - SHRTIM_CHP_DUTYCYCLE_625 +*\*\ - SHRTIM_CHP_DUTYCYCLE_750 +*\*\ - SHRTIM_CHP_DUTYCYCLE_875 +*\*\return None +**/ +void SHRTIM_CHP_SetDutyCycle(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t DutyCycle) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCHOP_CARDCY, DutyCycle); +} + +/** +*\*\fun Get actual chopper duty cycle. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return DutyCycle This parameter can be one of the following values: +*\*\ - SHRTIM_CHP_DUTYCYCLE_0 +*\*\ - SHRTIM_CHP_DUTYCYCLE_125 +*\*\ - SHRTIM_CHP_DUTYCYCLE_250 +*\*\ - SHRTIM_CHP_DUTYCYCLE_375 +*\*\ - SHRTIM_CHP_DUTYCYCLE_500 +*\*\ - SHRTIM_CHP_DUTYCYCLE_625 +*\*\ - SHRTIM_CHP_DUTYCYCLE_750 +*\*\ - SHRTIM_CHP_DUTYCYCLE_875 +**/ +uint32_t SHRTIM_CHP_GetDutyCycle(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCHOP_CARDCY)); +} + +/** +*\*\fun Set the start pulse width. +*\*\note This function must not be called if the chopper mode is already + * enabled for one of the timer outputs. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\param PulseWidth This parameter can be one of the following values: +*\*\ - SHRTIM_CHP_PULSEWIDTH_16 +*\*\ - SHRTIM_CHP_PULSEWIDTH_32 +*\*\ - SHRTIM_CHP_PULSEWIDTH_48 +*\*\ - SHRTIM_CHP_PULSEWIDTH_64 +*\*\ - SHRTIM_CHP_PULSEWIDTH_80 +*\*\ - SHRTIM_CHP_PULSEWIDTH_96 +*\*\ - SHRTIM_CHP_PULSEWIDTH_112 +*\*\ - SHRTIM_CHP_PULSEWIDTH_128 +*\*\ - SHRTIM_CHP_PULSEWIDTH_144 +*\*\ - SHRTIM_CHP_PULSEWIDTH_160 +*\*\ - SHRTIM_CHP_PULSEWIDTH_176 +*\*\ - SHRTIM_CHP_PULSEWIDTH_192 +*\*\ - SHRTIM_CHP_PULSEWIDTH_208 +*\*\ - SHRTIM_CHP_PULSEWIDTH_224 +*\*\ - SHRTIM_CHP_PULSEWIDTH_240 +*\*\ - SHRTIM_CHP_PULSEWIDTH_256 +*\*\return None +**/ +void SHRTIM_CHP_SetPulseWidth(SHRTIM_Module *SHRTIMx, uint32_t Timer, uint32_t PulseWidth) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + MODIFY_REG(*pReg, SHRTIM_TXCHOP_STARTPW, PulseWidth); +} + +/** +*\*\fun Get actual start pulse width. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return PulseWidth This parameter can be one of the following values: +*\*\ - SHRTIM_CHP_PULSEWIDTH_16 +*\*\ - SHRTIM_CHP_PULSEWIDTH_32 +*\*\ - SHRTIM_CHP_PULSEWIDTH_48 +*\*\ - SHRTIM_CHP_PULSEWIDTH_64 +*\*\ - SHRTIM_CHP_PULSEWIDTH_80 +*\*\ - SHRTIM_CHP_PULSEWIDTH_96 +*\*\ - SHRTIM_CHP_PULSEWIDTH_112 +*\*\ - SHRTIM_CHP_PULSEWIDTH_128 +*\*\ - SHRTIM_CHP_PULSEWIDTH_144 +*\*\ - SHRTIM_CHP_PULSEWIDTH_160 +*\*\ - SHRTIM_CHP_PULSEWIDTH_176 +*\*\ - SHRTIM_CHP_PULSEWIDTH_192 +*\*\ - SHRTIM_CHP_PULSEWIDTH_208 +*\*\ - SHRTIM_CHP_PULSEWIDTH_224 +*\*\ - SHRTIM_CHP_PULSEWIDTH_240 +*\*\ - SHRTIM_CHP_PULSEWIDTH_256 +**/ +uint32_t SHRTIM_CHP_GetPulseWidth(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxCHOP) + + REG_OFFSET_TAB_TIMER[iTimer])); + return (READ_BIT(*pReg, SHRTIM_TXCHOP_STARTPW)); +} + +/** @defgroup SHRTIM_EF_Output_Management Output_Management +*\*\{ +**/ + +/** +*\*\fun Set the timer output set source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param SetSrc This parameter can be a combination of the following values: +*\*\ - SHRTIM_OUTPUTSET_NONE +*\*\ - SHRTIM_OUTPUTSET_RESYNC +*\*\ - SHRTIM_OUTPUTSET_TIMPRD +*\*\ - SHRTIM_OUTPUTSET_TIMCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCMP4 +*\*\ - SHRTIM_OUTPUTSET_MASTERPER +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP1 +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP2 +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP3 +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 +*\*\ - SHRTIM_OUTPUTSET_EXEV_1 +*\*\ - SHRTIM_OUTPUTSET_EXEV_2 +*\*\ - SHRTIM_OUTPUTSET_EXEV_3 +*\*\ - SHRTIM_OUTPUTSET_EXEV_4 +*\*\ - SHRTIM_OUTPUTSET_EXEV_5 +*\*\ - SHRTIM_OUTPUTSET_EXEV_6 +*\*\ - SHRTIM_OUTPUTSET_EXEV_7 +*\*\ - SHRTIM_OUTPUTSET_EXEV_8 +*\*\ - SHRTIM_OUTPUTSET_EXEV_9 +*\*\ - SHRTIM_OUTPUTSET_EXEV_10 +*\*\ - SHRTIM_OUTPUTSET_UPDATE +*\*\ (source = TIMy and destination = TIMx, Compare Unit = CMPz). +*\*\return None +**/ +void SHRTIM_OUT_SetOutputSetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t SetSrc) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxSET1) + + REG_OFFSET_TAB_TxSET[iOutput])); + WRITE_REG(*pReg, SetSrc); +} + +/** +*\*\fun Get the timer output set source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return SetSrc This parameter can be a combination of the following values: +*\*\ - SHRTIM_OUTPUTSET_NONE +*\*\ - SHRTIM_OUTPUTSET_RESYNC +*\*\ - SHRTIM_OUTPUTSET_TIMPRD +*\*\ - SHRTIM_OUTPUTSET_TIMCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCMP4 +*\*\ - SHRTIM_OUTPUTSET_MASTERPER +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP1 +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP2 +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP3 +*\*\ - SHRTIM_OUTPUTSET_MASTERCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 +*\*\ - SHRTIM_OUTPUTSET_EXEV_1 +*\*\ - SHRTIM_OUTPUTSET_EXEV_2 +*\*\ - SHRTIM_OUTPUTSET_EXEV_3 +*\*\ - SHRTIM_OUTPUTSET_EXEV_4 +*\*\ - SHRTIM_OUTPUTSET_EXEV_5 +*\*\ - SHRTIM_OUTPUTSET_EXEV_6 +*\*\ - SHRTIM_OUTPUTSET_EXEV_7 +*\*\ - SHRTIM_OUTPUTSET_EXEV_8 +*\*\ - SHRTIM_OUTPUTSET_EXEV_9 +*\*\ - SHRTIM_OUTPUTSET_EXEV_10 +*\*\ - SHRTIM_OUTPUTSET_UPDATE +*\*\ (source = TIMy and destination = TIMx, Compare Unit = CMPz). +**/ +uint32_t SHRTIM_OUT_GetOutputSetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxSET1) + + REG_OFFSET_TAB_TxSET[iOutput])); + return (uint32_t)READ_REG(*pReg); +} + +/** +*\*\fun Set the timer output reset source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param ResetSrc This parameter can be a combination of the following values: +*\*\ - SHRTIM_OUTPUTRESET_NONE +*\*\ - SHRTIM_OUTPUTRESET_RESYNC +*\*\ - SHRTIM_OUTPUTRESET_TIMPRD +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP4 +*\*\ - SHRTIM_OUTPUTRESET_MASTERPER +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP1 +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP2 +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP3 +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_1 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_2 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_3 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_4 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_5 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_6 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_7 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_8 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_9 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_10 +*\*\ - SHRTIM_OUTPUTRESET_UPDATE +*\*\ (source = TIMy and destination = TIMx, Compare Unit = CMPz). +*\*\return None +**/ +void SHRTIM_OUT_SetOutputResetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t ResetSrc) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxRST1) + + REG_OFFSET_TAB_TxSET[iOutput])); + WRITE_REG(*pReg, ResetSrc); +} + +/** +*\*\fun Get the timer output set source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return ResetSrc This parameter can be a combination of the following values: +*\*\ - SHRTIM_OUTPUTRESET_NONE +*\*\ - SHRTIM_OUTPUTRESET_RESYNC +*\*\ - SHRTIM_OUTPUTRESET_TIMPRD +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCMP4 +*\*\ - SHRTIM_OUTPUTRESET_MASTERPER +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP1 +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP2 +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP3 +*\*\ - SHRTIM_OUTPUTRESET_MASTERCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 +*\*\ - SHRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_1 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_2 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_3 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_4 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_5 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_6 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_7 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_8 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_9 +*\*\ - SHRTIM_OUTPUTRESET_EXEV_10 +*\*\ - SHRTIM_OUTPUTRESET_UPDATE +*\*\ (source = TIMy and destination = TIMx, Compare Unit = CMPz). +**/ +uint32_t SHRTIM_OUT_GetOutputResetSrc(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxRST1) + + REG_OFFSET_TAB_TxSET[iOutput])); + return (uint32_t)READ_REG(*pReg); +} + +/** +*\*\fun Configure a timer output. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param Configuration This parameter must be a combination of all the following values: +*\*\ - SHRTIM_OUT_POSITIVE_POLARITY or SHRTIM_OUT_NEGATIVE_POLARITY +*\*\ - SHRTIM_OUT_IDLELEVEL_INACTIVE or SHRTIM_OUT_IDLELEVEL_ACTIVE +*\*\ - SHRTIM_OUT_FAULTSTATE_NO_ACTION or SHRTIM_OUT_FAULTSTATE_ACTIVE or SHRTIM_OUT_FAULTSTATE_INACTIVE or SHRTIM_OUT_FAULTSTATE_HIGHZ +*\*\ - SHRTIM_OUT_CHOPPERMODE_DISABLED or SHRTIM_OUT_CHOPPERMODE_ENABLED +*\*\ - SHRTIM_OUT_BM_ENTRYMODE_REGULAR or SHRTIM_OUT_BM_ENTRYMODE_DELAYED +*\*\return None +**/ +void SHRTIM_OUT_Config(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t Configuration) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + MODIFY_REG(*pReg, (SHRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_TxOUT[iOutput]), + (Configuration << REG_SHIFT_TAB_TxOUT[iOutput])); +} + +/** +*\*\fun Set the polarity of a timer output. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_POSITIVE_POLARITY +*\*\ - SHRTIM_OUT_NEGATIVE_POLARITY +*\*\return None +**/ +void SHRTIM_OUT_SetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t Polarity) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + MODIFY_REG(*pReg, (SHRTIM_TXOUT_POL1 << REG_SHIFT_TAB_TxOUT[iOutput]), (Polarity << REG_SHIFT_TAB_TxOUT[iOutput])); +} + +/** +*\*\fun Get actual polarity of the timer output. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_POSITIVE_POLARITY +*\*\ - SHRTIM_OUT_NEGATIVE_POLARITY +**/ +uint32_t SHRTIM_OUT_GetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXOUT_POL1) << REG_SHIFT_TAB_TxOUT[iOutput]) >> REG_SHIFT_TAB_TxOUT[iOutput]); +} + +/** +*\*\fun Set the output IDLE level. +*\*\note This function must be called prior enabling the timer. +*\*\note Idle level isn't relevant when the output idle mode is set to SHRTIM_OUT_NO_IDLE. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param IdleLevel This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_IDLELEVEL_INACTIVE +*\*\ - SHRTIM_OUT_IDLELEVEL_ACTIVE +*\*\return None +**/ +void SHRTIM_OUT_SetIdleLevel(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t IdleLevel) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + MODIFY_REG(*pReg, (SHRTIM_TXOUT_IDLES1 << REG_SHIFT_TAB_TxOUT[iOutput]), (IdleLevel << REG_SHIFT_TAB_TxOUT[iOutput])); +} + +/** +*\*\fun Get actual output IDLE level. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return IdleLevel This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_IDLELEVEL_INACTIVE +*\*\ - SHRTIM_OUT_IDLELEVEL_ACTIVE +**/ +uint32_t SHRTIM_OUT_GetIdleLevel(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXOUT_IDLES1) << REG_SHIFT_TAB_TxOUT[iOutput]) >> REG_SHIFT_TAB_TxOUT[iOutput]); +} + +/** +*\*\fun Set the output FAULT state. +*\*\note This function must not called when the timer is enabled and a fault + * channel is enabled at timer level. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param FaultState This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_FAULTSTATE_NO_ACTION +*\*\ - SHRTIM_OUT_FAULTSTATE_ACTIVE +*\*\ - SHRTIM_OUT_FAULTSTATE_INACTIVE +*\*\ - SHRTIM_OUT_FAULTSTATE_HIGHZ +*\*\return None +**/ +void SHRTIM_OUT_SetFaultState(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t FaultState) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + MODIFY_REG(*pReg, (SHRTIM_TXOUT_FALT1 << REG_SHIFT_TAB_TxOUT[iOutput]), (FaultState << REG_SHIFT_TAB_TxOUT[iOutput])); +} + +/** +*\*\fun Get actual FAULT state. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return FaultState This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_FAULTSTATE_NO_ACTION +*\*\ - SHRTIM_OUT_FAULTSTATE_ACTIVE +*\*\ - SHRTIM_OUT_FAULTSTATE_INACTIVE +*\*\ - SHRTIM_OUT_FAULTSTATE_HIGHZ +**/ +uint32_t SHRTIM_OUT_GetFaultState(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXOUT_FALT1) << REG_SHIFT_TAB_TxOUT[iOutput]) >> REG_SHIFT_TAB_TxOUT[iOutput]); +} + +/** +*\*\fun Set the output chopper mode. +*\*\note This function must not called when the timer is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param ChopperMode This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_CHOPPERMODE_DISABLED +*\*\ - SHRTIM_OUT_CHOPPERMODE_ENABLED +*\*\return None +**/ +void SHRTIM_OUT_SetChopperMode(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t ChopperMode) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + MODIFY_REG(*pReg, (SHRTIM_TXOUT_CHP1 << REG_SHIFT_TAB_TxOUT[iOutput]), (ChopperMode << REG_SHIFT_TAB_TxOUT[iOutput])); +} + +/** +*\*\fun Get actual output chopper mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return ChopperMode This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_CHOPPERMODE_DISABLED +*\*\ - SHRTIM_OUT_CHOPPERMODE_ENABLED +**/ +uint32_t SHRTIM_OUT_GetChopperMode(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXOUT_CHP1) << REG_SHIFT_TAB_TxOUT[iOutput]) >> REG_SHIFT_TAB_TxOUT[iOutput]); +} + +/** +*\*\fun Set the output burst mode entry mode. +*\*\note This function must not called when the timer is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param BMEntryMode This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_BM_ENTRYMODE_REGULAR +*\*\ - SHRTIM_OUT_BM_ENTRYMODE_DELAYED +*\*\return None +**/ +void SHRTIM_OUT_SetBMEntryMode(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t BMEntryMode) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + MODIFY_REG(*pReg, (SHRTIM_TXOUT_DIDL1 << REG_SHIFT_TAB_TxOUT[iOutput]), (BMEntryMode << REG_SHIFT_TAB_TxOUT[iOutput])); +} + +/** +*\*\fun Get actual output burst mode entry mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return BMEntryMode This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_BM_ENTRYMODE_REGULAR +*\*\ - SHRTIM_OUT_BM_ENTRYMODE_DELAYED +**/ +uint32_t SHRTIM_OUT_GetBMEntryMode(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxOUT) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_TXOUT_DIDL1) << REG_SHIFT_TAB_TxOUT[iOutput]) >> REG_SHIFT_TAB_TxOUT[iOutput]); +} + +/** +*\*\fun Get the level (active or inactive) of the designated output when the +*\*\ delayed protection was triggered. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return OutputLevel This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_LEVEL_INACTIVE +*\*\ - SHRTIM_OUT_LEVEL_ACTIVE +**/ +uint32_t SHRTIM_OUT_GetDPOutStatus(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxINTSTS) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return ((READ_BIT(*pReg, (uint32_t)(SHRTIM_TXINTSTS_O1DIPSTS) << REG_SHIFT_TAB_OxSTS[iOutput]) >> REG_SHIFT_TAB_OxSTS[iOutput]) >> + SHRTIM_TXINTSTS_O1DIPSTS_Pos); +} + +/** +*\*\fun Force the timer output to its active or inactive level. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\param OutputLevel This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_LEVEL_INACTIVE +*\*\ - SHRTIM_OUT_LEVEL_ACTIVE +*\*\return None +**/ +void SHRTIM_OUT_ForceLevel(SHRTIM_Module *SHRTIMx, uint32_t Output, uint32_t OutputLevel) +{ + const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] = + { + 0x04U, /* 0: SHRTIM_OUT_LEVEL_INACTIVE**/ + 0x00U /* 1: SHRTIM_OUT_LEVEL_ACTIVE**/ + }; + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxSET1) + + REG_OFFSET_TAB_TxSET[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + SET_BIT(*pReg, SHRTIM_TXSET1_SWT); +} + +/** +*\*\fun Get actual output level, before the output stage (chopper, polarity). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Output This parameter can be one of the following values: +*\*\ - SHRTIM_OUTPUT_TA1 +*\*\ - SHRTIM_OUTPUT_TA2 +*\*\ - SHRTIM_OUTPUT_TB1 +*\*\ - SHRTIM_OUTPUT_TB2 +*\*\ - SHRTIM_OUTPUT_TC1 +*\*\ - SHRTIM_OUTPUT_TC2 +*\*\ - SHRTIM_OUTPUT_TD1 +*\*\ - SHRTIM_OUTPUT_TD2 +*\*\ - SHRTIM_OUTPUT_TE1 +*\*\ - SHRTIM_OUTPUT_TE2 +*\*\ - SHRTIM_OUTPUT_TF1 +*\*\ - SHRTIM_OUTPUT_TF2 +*\*\return OutputLevel This parameter can be one of the following values: +*\*\ - SHRTIM_OUT_LEVEL_INACTIVE +*\*\ - SHRTIM_OUT_LEVEL_ACTIVE +**/ +uint32_t SHRTIM_OUT_GetLevel(SHRTIM_Module *SHRTIMx, uint32_t Output) +{ + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(SHRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxINTSTS) + + REG_OFFSET_TAB_TxOUT[iOutput])); + return ((READ_BIT(*pReg, (uint32_t)(SHRTIM_TXINTSTS_O1BCKUP) << REG_SHIFT_TAB_OxSTS[iOutput]) >> REG_SHIFT_TAB_OxSTS[iOutput]) >> + SHRTIM_TXINTSTS_O1BCKUP_Pos); +} + + +/** +*\*\fun Configure external event conditioning. +*\*\note This function must not be called when the timer counter is enabled. +*\*\note Event source (EXEVxSRC0..EXEVxSRC10) mapping depends on configured event channel. +*\*\note Fast mode is available for SHRTIM_EVENT_1..10. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param Src This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_SOURCE_1 +*\*\ - SHRTIM_EXEV_SOURCE_2 +*\*\ - SHRTIM_EXEV_SOURCE_3 +*\*\ - SHRTIM_EXEV_SOURCE_4 +*\*\ - SHRTIM_EXEV_SOURCE_5 +*\*\param SrcCompSel This parameter can be one of the following values: +*\*\ - SHRTIM_EXEVXSRC2_COMP1_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP2_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP3_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP4_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP5_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP6_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP7_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP_NONE +*\*\param Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_POLARITY_HIGH +*\*\ - SHRTIM_EXEV_POLARITY_LOW +*\*\param Sensitivity This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_SENSITIVITY_LEVEL +*\*\ - SHRTIM_EXEV_SENSITIVITY_RISINGEDGE +*\*\ - SHRTIM_EXEV_SENSITIVITY_FALLINGEDGE +*\*\ - SHRTIM_EXEV_SENSITIVITY_BOTHEDGES +*\*\param FastMode This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_FASTMODE_DISABLE +*\*\ - SHRTIM_EXEV_FASTMODE_ENABLE +*\*\param Filter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_FILTER_NONE +*\*\ - SHRTIM_EXEV_FILTER_1 +*\*\ - SHRTIM_EXEV_FILTER_2 +*\*\ - SHRTIM_EXEV_FILTER_3 +*\*\ - SHRTIM_EXEV_FILTER_4 +*\*\ - SHRTIM_EXEV_FILTER_5 +*\*\ - SHRTIM_EXEV_FILTER_6 +*\*\ - SHRTIM_EXEV_FILTER_7 +*\*\ - SHRTIM_EXEV_FILTER_8 +*\*\ - SHRTIM_EXEV_FILTER_9 +*\*\ - SHRTIM_EXEV_FILTER_10 +*\*\ - SHRTIM_EXEV_FILTER_11 +*\*\ - SHRTIM_EXEV_FILTER_12 +*\*\ - SHRTIM_EXEV_FILTER_13 +*\*\ - SHRTIM_EXEV_FILTER_14 +*\*\ - SHRTIM_EXEV_FILTER_15 +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_PRESCALER_DIV1 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV2 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV4 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV8 +*\*\return None +*\*\note Polarity configuration is only valid if sensitivity is SHRTIM_EXEV_SENSITIVITY_LEVEL +**/ +void SHRTIM_EXEV_Config(SHRTIM_Module *SHRTIMx, uint32_t Event, + uint32_t Src, uint32_t SrcCompSel, uint32_t Polarity, + uint32_t Sensitivity, uint32_t FastMode, + uint32_t Filter, uint32_t Prescaler) +{ + SHRTIM_EXEV_SetSrc(SHRTIMx, Event, Src); + SHRTIM_EXEV_SetSrcCompSel(SHRTIMx, Event, SrcCompSel); + SHRTIM_EXEV_SetPolarity(SHRTIMx, Event, Polarity); + SHRTIM_EXEV_SetSensitivity(SHRTIMx, Event, Sensitivity); + SHRTIM_EXEV_SetFastMode(SHRTIMx, Event, FastMode); + SHRTIM_EXEV_SetFilter(SHRTIMx, Event, Filter); + SHRTIM_EXEV_SetPrescaler(SHRTIMx, Prescaler); +} + +/** +*\*\fun Set the external event source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param Src This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_SOURCE_1 +*\*\ - SHRTIM_EXEV_SOURCE_2 +*\*\ - SHRTIM_EXEV_SOURCE_3 +*\*\ - SHRTIM_EXEV_SOURCE_4 +*\*\ - SHRTIM_EXEV_SOURCE_5 +*\*\return None +**/ +void SHRTIM_EXEV_SetSrc(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Src) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL1) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + MODIFY_REG(*pReg, (SHRTIM_EXEVCTRL1_EXEV1SRC << REG_SHIFT_TAB_EXEVx[iEvent]), (Src << REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Get actual external event source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return EventSrc This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_SOURCE_1 +*\*\ - SHRTIM_EXEV_SOURCE_2 +*\*\ - SHRTIM_EXEV_SOURCE_3 +*\*\ - SHRTIM_EXEV_SOURCE_4 +*\*\ - SHRTIM_EXEV_SOURCE_5 +**/ +uint32_t SHRTIM_EXEV_GetSrc(SHRTIM_Module *SHRTIMx, uint32_t Event) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL1) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_EXEVCTRL1_EXEV1SRC) << REG_SHIFT_TAB_EXEVx[iEvent]) >> REG_SHIFT_TAB_EXEVx[iEvent]); +} + +/** +*\*\fun Select the analog comparator of SHRTIM_EXEV_SOURCE_2. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param SrcCompSel This parameter can be one of the following values: +*\*\ - SHRTIM_EXEVXSRC2_COMP1_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP2_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP3_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP4_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP5_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP6_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP7_OUT +*\*\ - SHRTIM_EXEVXSRC2_COMP_NONE +*\*\return None +**/ +void SHRTIM_EXEV_SetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t SrcCompSel) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL5)); + MODIFY_REG(*pReg, (SHRTIM_EXEVCTRL5_EXEV1CSEL << REG_SHIFT_TAB_EXEVxCSEL[iEvent]), (SrcCompSel << REG_SHIFT_TAB_EXEVxCSEL[iEvent])); +} + +/** +*\*\fun Get the the selection of analog comparator of external event source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return SrcCompSel This parameter can be one of the following values: +*\*\ - 3'b000: cmp1 out +*\*\ - 3'b001: cmp2 out +*\*\ - 3'b010: cmp3 out +*\*\ - 3'b011: cmp4 out +*\*\ - 3'b100: cmp5 out +*\*\ - 3'b101: cmp6 out +*\*\ - 3'b110: cmp7 out +**/ +uint32_t SHRTIM_EXEV_GetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Event) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL5)); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_EXEVCTRL5_EXEV1CSEL) << REG_SHIFT_TAB_EXEVxCSEL[iEvent]) >> REG_SHIFT_TAB_EXEVxCSEL[iEvent]); +} + +/** +*\*\fun Set the polarity of an external event. +*\*\note This function must not be called when the timer counter is enabled. +*\*\note Event polarity is only significant when event detection is level-sensitive. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_POLARITY_HIGH +*\*\ - SHRTIM_EXEV_POLARITY_LOW +*\*\return None +**/ +void SHRTIM_EXEV_SetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Polarity) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL1) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + MODIFY_REG(*pReg, (SHRTIM_EXEVCTRL1_EXEV1POL << REG_SHIFT_TAB_EXEVx[iEvent]), (Polarity << REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Get actual polarity setting of an external event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_POLARITY_HIGH +*\*\ - SHRTIM_EXEV_POLARITY_LOW +**/ +uint32_t SHRTIM_EXEV_GetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Event) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL1) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_EXEVCTRL1_EXEV1POL) << REG_SHIFT_TAB_EXEVx[iEvent]) >> REG_SHIFT_TAB_EXEVx[iEvent]); +} + +/** +*\*\fun Set the sensitivity of an external event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param Sensitivity This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_SENSITIVITY_LEVEL +*\*\ - SHRTIM_EXEV_SENSITIVITY_RISINGEDGE +*\*\ - SHRTIM_EXEV_SENSITIVITY_FALLINGEDGE +*\*\ - SHRTIM_EXEV_SENSITIVITY_BOTHEDGES +*\*\return None +**/ + +void SHRTIM_EXEV_SetSensitivity(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Sensitivity) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL1) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + MODIFY_REG(*pReg, (SHRTIM_EXEVCTRL1_EXEV1SENS << REG_SHIFT_TAB_EXEVx[iEvent]), (Sensitivity << REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Get actual sensitivity setting of an external event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_SENSITIVITY_LEVEL +*\*\ - SHRTIM_EXEV_SENSITIVITY_RISINGEDGE +*\*\ - SHRTIM_EXEV_SENSITIVITY_FALLINGEDGE +*\*\ - SHRTIM_EXEV_SENSITIVITY_BOTHEDGES +**/ +uint32_t SHRTIM_EXEV_GetSensitivity(SHRTIM_Module *SHRTIMx, uint32_t Event) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL1) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_EXEVCTRL1_EXEV1SENS) << REG_SHIFT_TAB_EXEVx[iEvent]) >> REG_SHIFT_TAB_EXEVx[iEvent]); +} + +/** +*\*\fun Set the fast mode of an external event. +*\*\note This function must not be called when the timer counter is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param FastMode This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_FASTMODE_DISABLE +*\*\ - SHRTIM_EXEV_FASTMODE_ENABLE +*\*\return None +**/ +void SHRTIM_EXEV_SetFastMode(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t FastMode) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL3) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + MODIFY_REG(*pReg, (SHRTIM_EXEVCTRL3_EXEV1FM << REG_SHIFT_TAB_EXEVx[iEvent]), (FastMode << REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Get actual fast mode setting of an external event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return FastMode This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_FASTMODE_DISABLE +*\*\ - SHRTIM_EXEV_FASTMODE_ENABLE +**/ +uint32_t SHRTIM_EXEV_GetFastMode(SHRTIM_Module *SHRTIMx, uint32_t Event) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL3) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_EXEVCTRL3_EXEV1FM) << REG_SHIFT_TAB_EXEVx[iEvent]) >> REG_SHIFT_TAB_EXEVx[iEvent]); +} + +/** +*\*\fun Set the digital noise filter of a external event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\param Filter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_FILTER_NONE +*\*\ - SHRTIM_EXEV_FILTER_1 +*\*\ - SHRTIM_EXEV_FILTER_2 +*\*\ - SHRTIM_EXEV_FILTER_3 +*\*\ - SHRTIM_EXEV_FILTER_4 +*\*\ - SHRTIM_EXEV_FILTER_5 +*\*\ - SHRTIM_EXEV_FILTER_6 +*\*\ - SHRTIM_EXEV_FILTER_7 +*\*\ - SHRTIM_EXEV_FILTER_8 +*\*\ - SHRTIM_EXEV_FILTER_9 +*\*\ - SHRTIM_EXEV_FILTER_10 +*\*\ - SHRTIM_EXEV_FILTER_11 +*\*\ - SHRTIM_EXEV_FILTER_12 +*\*\ - SHRTIM_EXEV_FILTER_13 +*\*\ - SHRTIM_EXEV_FILTER_14 +*\*\ - SHRTIM_EXEV_FILTER_15 +*\*\return None +**/ +void SHRTIM_EXEV_SetFilter(SHRTIM_Module *SHRTIMx, uint32_t Event, uint32_t Filter) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL3) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + MODIFY_REG(*pReg, (SHRTIM_EXEVCTRL3_EXEV1F << REG_SHIFT_TAB_EXEVx[iEvent]), (Filter << REG_SHIFT_TAB_EXEVx[iEvent])); +} + +/** +*\*\fun Get actual digital noise filter setting of a external event. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Event This parameter can be one of the following values: +*\*\ - SHRTIM_EVENT_1 +*\*\ - SHRTIM_EVENT_2 +*\*\ - SHRTIM_EVENT_3 +*\*\ - SHRTIM_EVENT_4 +*\*\ - SHRTIM_EVENT_5 +*\*\ - SHRTIM_EVENT_6 +*\*\ - SHRTIM_EVENT_7 +*\*\ - SHRTIM_EVENT_8 +*\*\ - SHRTIM_EVENT_9 +*\*\ - SHRTIM_EVENT_10 +*\*\return Filter This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_FILTER_NONE +*\*\ - SHRTIM_EXEV_FILTER_1 +*\*\ - SHRTIM_EXEV_FILTER_2 +*\*\ - SHRTIM_EXEV_FILTER_3 +*\*\ - SHRTIM_EXEV_FILTER_4 +*\*\ - SHRTIM_EXEV_FILTER_5 +*\*\ - SHRTIM_EXEV_FILTER_6 +*\*\ - SHRTIM_EXEV_FILTER_7 +*\*\ - SHRTIM_EXEV_FILTER_8 +*\*\ - SHRTIM_EXEV_FILTER_9 +*\*\ - SHRTIM_EXEV_FILTER_10 +*\*\ - SHRTIM_EXEV_FILTER_11 +*\*\ - SHRTIM_EXEV_FILTER_12 +*\*\ - SHRTIM_EXEV_FILTER_13 +*\*\ - SHRTIM_EXEV_FILTER_14 +*\*\ - SHRTIM_EXEV_FILTER_15 +**/ +uint32_t SHRTIM_EXEV_GetFilter(SHRTIM_Module *SHRTIMx, uint32_t Event) +{ + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(SHRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.EXEVCTRL3) + + REG_OFFSET_TAB_EXEVCTRL[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_EXEVCTRL3_EXEV1F) << REG_SHIFT_TAB_EXEVx[iEvent]) >> REG_SHIFT_TAB_EXEVx[iEvent]); +} + +/** +*\*\fun Set the external event prescaler. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_PRESCALER_DIV1 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV2 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV4 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV8 +*\*\return None +**/ +void SHRTIM_EXEV_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Prescaler) +{ + MODIFY_REG(SHRTIMx->sCommonRegs.EXEVCTRL4, SHRTIM_EXEVCTRL4_EXEVSCD, Prescaler); +} + +/** +*\*\fun Get actual external event prescaler setting. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_EXEV_PRESCALER_DIV1 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV2 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV4 +*\*\ - SHRTIM_EXEV_PRESCALER_DIV8 +**/ + +uint32_t SHRTIM_EXEV_GetPrescaler(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sCommonRegs.EXEVCTRL4, SHRTIM_EXEVCTRL4_EXEVSCD)); +} + +/** +*\*\fun Configure fault signal conditioning Polarity and Source. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Configuration This parameter must be a combination of all the following values: +*\*\ - SHRTIM_FALT_SRC_DIGITALINPUT..SHRTIM_FALT_SRC_INTERNAL..SHRTIM_FALT_SRC_EXEVINPUT..SHRTIM_FALT_SRC_DSMU +*\*\ - SHRTIM_FALT_POLARITY_LOW..SHRTIM_FALT_POLARITY_HIGH +*\*\param SrcCompSel This parameter can be one of the following values: +*\*\ - SHRTIM_FALTXSRC2_COMP1_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP2_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP3_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP4_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP5_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP6_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP7_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP_NONE +*\*\return None +**/ +void SHRTIM_FALT_Config(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Configuration, uint32_t SrcCompSel) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + + uint64_t cfg; + uint64_t mask; + + cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)SHRTIM_FALT_CONFIG_MASK) << REG_SHIFT_TAB_FALTxF[iFault]) | /* this for Source 0 and polarity bits */ + (((uint64_t)((uint64_t)Configuration & (uint64_t)SHRTIM_FALT_SRC_1_MASK) << REG_SHIFT_TAB_FALTx[iFault]) << 32U); /* this for Source 1 bit**/ + + mask = ((uint64_t)(SHRTIM_FALTIN1_FALT1POL | SHRTIM_FALTIN1_FALT1SRC0) << REG_SHIFT_TAB_FALTxF[iFault]) | /* this for Source 0 and polarity bits */ + ((uint64_t)(SHRTIM_FALT_SRC_1_MASK) << 32U); /* this for Source bit 1 */ + + MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg)); + MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U)); + + SHRTIM_FALT_SetSrcCompSel(SHRTIMx, Fault, SrcCompSel); +} + +/** +*\*\fun Set the source of a fault signal. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Src This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_SRC_DIGITALINPUT +*\*\ - SHRTIM_FALT_SRC_INTERNAL +*\*\ - SHRTIM_FALT_SRC_EXEVINPUT +*\*\ - SHRTIM_FALT_SRC_DSMU +*\*\return None +**/ +void SHRTIM_FALT_SetSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Src) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + + uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)SHRTIM_FALTIN1_FALT1SRC0) << REG_SHIFT_TAB_FALTxF[iFault]) | /* this for Source 0 bit */ + (((uint64_t)((uint64_t)Src & (uint64_t)SHRTIM_FALT_SRC_1_MASK) << REG_SHIFT_TAB_FALTx[iFault]) << 32U); /* this for Source 1 bit */ + uint64_t mask = ((uint64_t)(SHRTIM_FALTIN1_FALT1SRC0) << REG_SHIFT_TAB_FALTxF[iFault]) | /* this for Source bit 0 */ + (((uint64_t)(SHRTIM_FALTIN2_FALT1SRC1) << REG_SHIFT_TAB_FALTx[iFault]) << 32U); /* this for Source bit 1 */ + + MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg)); + MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U)); +} + +/** +*\*\fun Get actual source of a fault signal. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return Source This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_SRC_DIGITALINPUT +*\*\ - SHRTIM_FALT_SRC_INTERNAL +*\*\ - SHRTIM_FALT_SRC_EXEVINPUT +*\*\ - SHRTIM_FALT_SRC_DSMU +**/ +uint32_t SHRTIM_FALT_GetSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + + uint64_t Src0; + uint32_t Src1; + uint32_t temp1, temp2; /* temp variables used for MINTSTSA-C **/ + + /* this for Source bit 1 */ + Src1 = READ_BIT(*pReg2, SHRTIM_FALT_SRC_1_MASK) >> REG_SHIFT_TAB_FALTx[iFault]; + temp1 = READ_BIT(*pReg2, (uint32_t)(SHRTIM_FALTIN2_FALT5SRC0 | SHRTIM_FALTIN2_FALT6SRC0)); + temp2 = READ_BIT(*pReg1, (uint32_t)(SHRTIM_FALTIN1_FALT1SRC0 | SHRTIM_FALTIN1_FALT2SRC0 | SHRTIM_FALTIN1_FALT3SRC0 | SHRTIM_FALTIN1_FALT4SRC0)); + + /* this for Source bit 0 */ + Src0 = (uint64_t)temp1 << 32U; + Src0 |= (uint64_t)temp2; + Src0 = (Src0 >> REG_SHIFT_TAB_FALTxF[iFault]); + + return ((uint32_t)(Src0 | Src1)); +} + +/** +*\*\fun Select the analog comparator of fault source 2. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param SrcCompSel This parameter can be one of the following values: +*\*\ - SHRTIM_FALTXSRC2_COMP1_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP2_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP3_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP4_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP5_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP6_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP7_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP_NONE +**/ +void SHRTIM_FALT_SetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t SrcCompSel) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN5)); + MODIFY_REG(*pReg, (SHRTIM_FALTIN5_FALT1CSEL << REG_SHIFT_TAB_FALTxCSEL[iFault]), (SrcCompSel << REG_SHIFT_TAB_FALTxCSEL[iFault])); +} + +/** +*\*\fun Get the selection the analog comparator of fault source 2. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return SrcCompSel This parameter can be one of the following values: +*\*\ - SHRTIM_FALTXSRC2_COMP1_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP2_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP3_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP4_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP5_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP6_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP7_OUT +*\*\ - SHRTIM_FALTXSRC2_COMP_NONE +**/ +uint32_t SHRTIM_FALT_GetSrcCompSel(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN5)); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN5_FALT1CSEL) << REG_SHIFT_TAB_FALTxCSEL[iFault]) >> REG_SHIFT_TAB_FALTxCSEL[iFault]); +} + +/** +*\*\fun Set the polarity of a fault signal. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_POLARITY_LOW +*\*\ - SHRTIM_FALT_POLARITY_HIGH +*\*\return None +**/ +void SHRTIM_FALT_SetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Polarity) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + + uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(SHRTIM_FALTIN1_FALT1POL)) << REG_SHIFT_TAB_FALTxF[iFault]; /* this for Polarity bit */ + uint64_t mask = (uint64_t)(SHRTIM_FALTIN1_FALT1POL) << REG_SHIFT_TAB_FALTxF[iFault]; /* this for Polarity bit */ + + /* for Polarity bit */ + MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg)); + MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U)); +} + +/** +*\*\fun Get actual polarity of a fault signal. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return Polarity This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_POLARITY_LOW +*\*\ - SHRTIM_FALT_POLARITY_HIGH +**/ +uint32_t SHRTIM_FALT_GetPolarity(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + uint32_t temp1, temp2; /* temp variables used for MINTSTSA-C**/ + uint64_t cfg; + + temp1 = READ_BIT(*pReg2, (uint32_t)(SHRTIM_FALTIN2_FALT5POL | SHRTIM_FALTIN2_FALT6POL)); + temp2 = READ_BIT(*pReg1, (uint32_t)(SHRTIM_FALTIN1_FALT1POL | SHRTIM_FALTIN1_FALT2POL | SHRTIM_FALTIN1_FALT3POL | SHRTIM_FALTIN1_FALT4POL)); + + cfg = (uint64_t)temp1 << 32; + cfg |= (uint64_t)temp2; + cfg = (cfg >> REG_SHIFT_TAB_FALTxF[iFault]); + + return (uint32_t)(cfg); +} + +/** +*\*\fun Set the digital noise filter of a fault signal. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Filter This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_FILTER_NONE +*\*\ - SHRTIM_FALT_FILTER_1 +*\*\ - SHRTIM_FALT_FILTER_2 +*\*\ - SHRTIM_FALT_FILTER_3 +*\*\ - SHRTIM_FALT_FILTER_4 +*\*\ - SHRTIM_FALT_FILTER_5 +*\*\ - SHRTIM_FALT_FILTER_6 +*\*\ - SHRTIM_FALT_FILTER_7 +*\*\ - SHRTIM_FALT_FILTER_8 +*\*\ - SHRTIM_FALT_FILTER_9 +*\*\ - SHRTIM_FALT_FILTER_10 +*\*\ - SHRTIM_FALT_FILTER_11 +*\*\ - SHRTIM_FALT_FILTER_12 +*\*\ - SHRTIM_FALT_FILTER_13 +*\*\ - SHRTIM_FALT_FILTER_14 +*\*\ - SHRTIM_FALT_FILTER_15 +*\*\return None +**/ +void SHRTIM_FALT_SetFilter(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Filter) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + + uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)SHRTIM_FALTIN1_FALT1FLT) << REG_SHIFT_TAB_FALTxF[iFault]; /* this for filter bits */ + uint64_t mask = (uint64_t)(SHRTIM_FALTIN1_FALT1FLT) << REG_SHIFT_TAB_FALTxF[iFault]; /* this for Polarity bit */ + + MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt)); + MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt >> 32U)); +} + +/** +*\*\fun Get actual digital noise filter setting of a fault signal. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return Filter This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_FILTER_NONE +*\*\ - SHRTIM_FALT_FILTER_1 +*\*\ - SHRTIM_FALT_FILTER_2 +*\*\ - SHRTIM_FALT_FILTER_3 +*\*\ - SHRTIM_FALT_FILTER_4 +*\*\ - SHRTIM_FALT_FILTER_5 +*\*\ - SHRTIM_FALT_FILTER_6 +*\*\ - SHRTIM_FALT_FILTER_7 +*\*\ - SHRTIM_FALT_FILTER_8 +*\*\ - SHRTIM_FALT_FILTER_9 +*\*\ - SHRTIM_FALT_FILTER_10 +*\*\ - SHRTIM_FALT_FILTER_11 +*\*\ - SHRTIM_FALT_FILTER_12 +*\*\ - SHRTIM_FALT_FILTER_13 +*\*\ - SHRTIM_FALT_FILTER_14 +*\*\ - SHRTIM_FALT_FILTER_15 +**/ +uint32_t SHRTIM_FALT_GetFilter(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN2))); + uint32_t temp1, temp2; /* temp variables used for MINTSTSA-C**/ + uint64_t flt; + temp1 = READ_BIT(*pReg2, (uint32_t)(SHRTIM_FALTIN2_FALT5FLT | SHRTIM_FALTIN2_FALT6FLT)); + temp2 = READ_BIT(*pReg1, (uint32_t)(SHRTIM_FALTIN1_FALT1FLT | SHRTIM_FALTIN1_FALT2FLT | SHRTIM_FALTIN1_FALT3FLT | SHRTIM_FALTIN1_FALT4FLT)); + + flt = (uint64_t)temp1 << 32U; + flt |= (uint64_t)temp2; + flt = (flt >> REG_SHIFT_TAB_FALTxF[iFault]); + + return (uint32_t)(flt); +} + +/** +*\*\fun Set the fault circuitry prescaler. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_PRESCALER_DIV1 +*\*\ - SHRTIM_FALT_PRESCALER_DIV2 +*\*\ - SHRTIM_FALT_PRESCALER_DIV4 +*\*\ - SHRTIM_FALT_PRESCALER_DIV8 +*\*\return None +**/ +void SHRTIM_FALT_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Prescaler) +{ + MODIFY_REG(SHRTIMx->sCommonRegs.FALTIN2, SHRTIM_FALTIN2_FALTSCD, Prescaler); +} + +/** +*\*\fun Get actual fault circuitry prescaler setting. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_PRESCALER_DIV1 +*\*\ - SHRTIM_FALT_PRESCALER_DIV2 +*\*\ - SHRTIM_FALT_PRESCALER_DIV4 +*\*\ - SHRTIM_FALT_PRESCALER_DIV8 +**/ +uint32_t SHRTIM_FALT_GetPrescaler(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sCommonRegs.FALTIN2, SHRTIM_FALTIN2_FALTSCD)); +} + +/** +*\*\fun Lock the fault signal conditioning settings. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_Lock(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1) + + REG_OFFSET_TAB_FALTIN[iFault])); + SET_BIT(*pReg, (SHRTIM_FALTIN1_FALT1LCK << REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Enable the fault circuitry for the designated fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_Enable(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1) + + REG_OFFSET_TAB_FALTIN[iFault])); + SET_BIT(*pReg, (SHRTIM_FALTIN1_FALT1E << REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Disable the fault circuitry for for the designated fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_Disable(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1) + + REG_OFFSET_TAB_FALTIN[iFault])); + CLEAR_BIT(*pReg, (SHRTIM_FALTIN1_FALT1E << REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Indicate whether the fault circuitry is enabled for a given fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return State of FALTxE bit in SHRTIM_FALTINx register (1 or 0). +**/ +uint32_t SHRTIM_FALT_IsEnabled(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN1) + + REG_OFFSET_TAB_FALTIN[iFault])); + return (((READ_BIT(*pReg, (SHRTIM_FALTIN1_FALT1E << REG_SHIFT_TAB_FALTxE[iFault])) >> REG_SHIFT_TAB_FALTxE[iFault]) == + (SHRTIM_FALTIN1_FALT1E)) + ? 1UL + : 0UL); +} + +/** +*\*\fun Enable the system fault +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SysFault This parameter can be one of the following values: +*\*\ - SHRTIM_SYSTEM_FAULT_SHRPLLLOCKFAULT +*\*\ - SHRTIM_SYSTEM_FAULT_PVD +*\*\ - SHRTIM_SYSTEM_FAULT_LOCKUP +*\*\ - SHRTIM_SYSTEM_FAULT_SRAMPARITY +*\*\ - SHRTIM_SYSTEM_FAULT_SRAMECC +*\*\ - SHRTIM_SYSTEM_FAULT_CLOCKSECURITY +*\*\return None +**/ +void SHRTIM_FALT_EnableSysFault(SHRTIM_Module *SHRTIMx, uint32_t SysFault) +{ + SET_BIT(SHRTIMx->sCommonRegs.FALTIN2, SysFault); +} + +/** +*\*\fun Indicate whether the system fault is enabled for a given system fault. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param SysFault This parameter can be one of the following values: +*\*\ - SHRTIM_SYSTEM_FAULT_SHRPLLLOCKFAULT +*\*\ - SHRTIM_SYSTEM_FAULT_PVD +*\*\ - SHRTIM_SYSTEM_FAULT_LOCKUP +*\*\ - SHRTIM_SYSTEM_FAULT_SRAMPARITY +*\*\ - SHRTIM_SYSTEM_FAULT_SRAMECC +*\*\ - SHRTIM_SYSTEM_FAULT_CLOCKSECURITY +*\*\return State of system fault enable in SHRTIM_FALTIN2 register +**/ +uint32_t SHRTIM_FALT_IsEnabledSysFault(SHRTIM_Module *SHRTIMx, uint32_t SysFault) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.FALTIN2, SysFault) == (SysFault)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the Blanking of the fault circuitry for the designated fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_EnableBlanking(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + SET_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN3_FALT1BLKEN) << REG_SHIFT_TAB_FALTxE[iFault]); +} + +/** +*\*\fun Disable the Blanking of the fault circuitry for the designated fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_DisableBlanking(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + CLEAR_BIT(*pReg, (SHRTIM_FALTIN3_FALT1BLKEN << REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Indicate whether the Blanking of the fault circuitry is enabled for a given fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return State of FALTxBLKEN bit in SHRTIM_FALTINx register (1 or 0). +**/ +uint32_t SHRTIM_FALT_IsEnabledBlanking(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + uint32_t temp; /* MINTSTSAC-2012 compliance */ + temp = READ_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN3_FALT1BLKEN) << REG_SHIFT_TAB_FALTxE[iFault]) >> REG_SHIFT_TAB_FALTxE[iFault]; + + return ((temp == (SHRTIM_FALTIN3_FALT1BLKEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the Blanking Source of the fault circuitry for a given fault input. +*\*\note Fault inputs can be temporary disabled to blank spurious fault events. +*\*\note This function allows for selection amongst 2 possible blanking sources. +*\*\note Events triggering blanking window start and blanking window end depend + * on both the selected blanking source and the fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Source parameter can be one of the following values: +*\*\ - SHRTIM_FALT_BLANKING_RSTALIGNED +*\*\ - SHRTIM_FALT_BLANKING_MOVING +*\*\return None +**/ +void SHRTIM_FALT_SetBlankingSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Source) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + MODIFY_REG(*pReg, (SHRTIM_FALTIN3_FALT1BLKS << REG_SHIFT_TAB_FALTxE[iFault]), (Source << REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Get the Blanking Source of the fault circuitry is enabled for a given fault input. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +**/ +uint32_t SHRTIM_FALT_GetBlankingSrc(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + return ((READ_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN3_FALT1BLKS) << REG_SHIFT_TAB_FALTxE[iFault]) >> REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Set the Counter threshold value of a fault counter. +*\*\note This function must not be called when the fault channel is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Threshold This parameter can be a number between Min_Data=0 and Max_Data=15 +*\*\return None +**/ +void SHRTIM_FALT_SetCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Threshold) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + MODIFY_REG(*pReg, (SHRTIM_FALTIN3_FALT1CNT << REG_SHIFT_TAB_FALTxE[iFault]), (Threshold << REG_SHIFT_TAB_FALTxE[iFault])); +} + +/** +*\*\fun Get actual the Counter threshold value of a fault counter. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return Threshold This parameter can be a number between Min_Data=0 and Max_Data=15 +**/ +uint32_t SHRTIM_FALT_GetCounterThreshold(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + return (READ_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN3_FALT1CNT) << REG_SHIFT_TAB_FALTxE[iFault]) >> REG_SHIFT_TAB_FALTxE[iFault]); +} + +/** +*\*\fun Enable soft fault for given fault +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_EnableSoftFault(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + SET_BIT(SHRTIMx->sCommonRegs.SFTFALT, Fault); +} + +/** +*\*\fun Indicate whether the soft fault is enabled +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return State of SFTFALTx bit in SHRTIM_SFTFALT register (1 or 0). +**/ +uint32_t SHRTIM_FALT_IsEnabledSoftFault(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.SFTFALT, Fault) == (Fault)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the mode of reset of a fault counter to 'always reset'. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_COUNTERRST_UNCONDITIONAL +*\*\ - SHRTIM_FALT_COUNTERRST_CONDITIONAL +*\*\return None +**/ +void SHRTIM_FALT_SetResetMode(SHRTIM_Module *SHRTIMx, uint32_t Fault, uint32_t Mode) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + MODIFY_REG(*pReg, (SHRTIM_FALTIN3_FALT1RSTM << REG_SHIFT_TAB_FALTxE[iFault]), Mode << REG_SHIFT_TAB_FALTxE[iFault]); +} + +/** +*\*\fun Get the mode of reset of a fault counter to 'reset on event'. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return Mode This parameter can be one of the following values: +*\*\ - SHRTIM_FALT_COUNTERRST_UNCONDITIONAL +*\*\ - SHRTIM_FALT_COUNTERRST_CONDITIONAL +**/ +uint32_t SHRTIM_FALT_GetResetMode(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + return READ_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN3_FALT1RSTM) << REG_SHIFT_TAB_FALTxE[iFault]); +} + +/** +*\*\fun Reset the fault counter for a fault circuitry +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Fault This parameter can be one of the following values: +*\*\ - SHRTIM_FAULT_1 +*\*\ - SHRTIM_FAULT_2 +*\*\ - SHRTIM_FAULT_3 +*\*\ - SHRTIM_FAULT_4 +*\*\ - SHRTIM_FAULT_5 +*\*\ - SHRTIM_FAULT_6 +*\*\return None +**/ +void SHRTIM_FALT_ResetCounter(SHRTIM_Module *SHRTIMx, uint32_t Fault) +{ + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sCommonRegs.FALTIN3) + + REG_OFFSET_TAB_FALTIN[iFault])); + SET_BIT(*pReg, (uint32_t)(SHRTIM_FALTIN3_FALT1CRST) << REG_SHIFT_TAB_FALTxE[iFault]); +} + +/** +*\*\fun Configure the burst mode controller. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Configuration This parameter must be a combination of all the following values: +*\*\ - SHRTIM_BM_MODE_SINGLESHOT or SHRTIM_BM_MODE_CONTINOUS +*\*\ - SHRTIM_BM_CLKSRC_MASTER or ... or SHRTIM_BM_CLKSRC_FSHRTIM +*\*\ - SHRTIM_BM_PRESCALER_DIV1 or ... SHRTIM_BM_PRESCALER_DIV32768 +*\*\return None +**/ +void SHRTIM_BM_Config(SHRTIM_Module *SHRTIMx, uint32_t Configuration) +{ + MODIFY_REG(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BM_CONFIG_MASK, Configuration); +} + +/** +*\*\fun Set the burst mode controller operating mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Mode This parameter can be one of the following values: +*\*\ - SHRTIM_BM_MODE_SINGLESHOT +*\*\ - SHRTIM_BM_MODE_CONTINOUS +*\*\return None +**/ +void SHRTIM_BM_SetMode(SHRTIM_Module *SHRTIMx, uint32_t Mode) +{ + MODIFY_REG(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMOM, Mode); +} + +/** +*\*\fun Get actual burst mode controller operating mode. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return Mode This parameter can be one of the following values: +*\*\ - SHRTIM_BM_MODE_SINGLESHOT +*\*\ - SHRTIM_BM_MODE_CONTINOUS +**/ +uint32_t SHRTIM_BM_GetMode(SHRTIM_Module *SHRTIMx) +{ + return (uint32_t)READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMOM); +} + +/** +*\*\fun Set the burst mode controller clock source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param ClockSrc This parameter can be one of the following values: +*\*\ - SHRTIM_BM_CLKSRC_MASTER +*\*\ - SHRTIM_BM_CLKSRC_TIMER_A +*\*\ - SHRTIM_BM_CLKSRC_TIMER_B +*\*\ - SHRTIM_BM_CLKSRC_TIMER_C +*\*\ - SHRTIM_BM_CLKSRC_TIMER_D +*\*\ - SHRTIM_BM_CLKSRC_TIMER_E +*\*\ - SHRTIM_BM_CLKSRC_TIMER_F +*\*\ - SHRTIM_BM_CLKSRC_GTIMB1_OC1 +*\*\ - SHRTIM_BM_CLKSRC_GTIMB2_OC1 +*\*\ - SHRTIM_BM_CLKSRC_GTIMB3_OC1 +*\*\ - SHRTIM_BM_CLKSRC_BTIM1_TRGO +*\*\ - SHRTIM_BM_CLKSRC_FSHRTIM +*\*\return None +**/ +void SHRTIM_BM_SetClockSrc(SHRTIM_Module *SHRTIMx, uint32_t ClockSrc) +{ + MODIFY_REG(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMCK, ClockSrc); +} + +/** +*\*\fun Get actual burst mode controller clock source. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return ClockSrc This parameter can be one of the following values: +*\*\ - SHRTIM_BM_CLKSRC_MASTER +*\*\ - SHRTIM_BM_CLKSRC_TIMER_A +*\*\ - SHRTIM_BM_CLKSRC_TIMER_B +*\*\ - SHRTIM_BM_CLKSRC_TIMER_C +*\*\ - SHRTIM_BM_CLKSRC_TIMER_D +*\*\ - SHRTIM_BM_CLKSRC_TIMER_E +*\*\ - SHRTIM_BM_CLKSRC_TIMER_F +*\*\ - SHRTIM_BM_CLKSRC_GTIMB1_OC1 +*\*\ - SHRTIM_BM_CLKSRC_GTIMB2_OC1 +*\*\ - SHRTIM_BM_CLKSRC_GTIMB3_OC1 +*\*\ - SHRTIM_BM_CLKSRC_BTIM1_TRGO +*\*\ - SHRTIM_BM_CLKSRC_FSHRTIM +**/ +uint32_t SHRTIM_BM_GetClockSrc(SHRTIM_Module *SHRTIMx) +{ + return (uint32_t)READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMCK); +} + +/** +*\*\fun Set the burst mode controller prescaler. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_BM_PRESCALER_DIV1 +*\*\ - SHRTIM_BM_PRESCALER_DIV2 +*\*\ - SHRTIM_BM_PRESCALER_DIV4 +*\*\ - SHRTIM_BM_PRESCALER_DIV8 +*\*\ - SHRTIM_BM_PRESCALER_DIV16 +*\*\ - SHRTIM_BM_PRESCALER_DIV32 +*\*\ - SHRTIM_BM_PRESCALER_DIV64 +*\*\ - SHRTIM_BM_PRESCALER_DIV128 +*\*\ - SHRTIM_BM_PRESCALER_DIV256 +*\*\ - SHRTIM_BM_PRESCALER_DIV512 +*\*\ - SHRTIM_BM_PRESCALER_DIV1024 +*\*\ - SHRTIM_BM_PRESCALER_DIV2048 +*\*\ - SHRTIM_BM_PRESCALER_DIV4096 +*\*\ - SHRTIM_BM_PRESCALER_DIV8192 +*\*\ - SHRTIM_BM_PRESCALER_DIV16384 +*\*\ - SHRTIM_BM_PRESCALER_DIV32768 +*\*\return None +**/ +void SHRTIM_BM_SetPrescaler(SHRTIM_Module *SHRTIMx, uint32_t Prescaler) +{ + MODIFY_REG(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMPSC, Prescaler); +} + +/** +*\*\fun Get actual burst mode controller prescaler setting. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return Prescaler This parameter can be one of the following values: +*\*\ - SHRTIM_BM_PRESCALER_DIV1 +*\*\ - SHRTIM_BM_PRESCALER_DIV2 +*\*\ - SHRTIM_BM_PRESCALER_DIV4 +*\*\ - SHRTIM_BM_PRESCALER_DIV8 +*\*\ - SHRTIM_BM_PRESCALER_DIV16 +*\*\ - SHRTIM_BM_PRESCALER_DIV32 +*\*\ - SHRTIM_BM_PRESCALER_DIV64 +*\*\ - SHRTIM_BM_PRESCALER_DIV128 +*\*\ - SHRTIM_BM_PRESCALER_DIV256 +*\*\ - SHRTIM_BM_PRESCALER_DIV512 +*\*\ - SHRTIM_BM_PRESCALER_DIV1024 +*\*\ - SHRTIM_BM_PRESCALER_DIV2048 +*\*\ - SHRTIM_BM_PRESCALER_DIV4096 +*\*\ - SHRTIM_BM_PRESCALER_DIV8192 +*\*\ - SHRTIM_BM_PRESCALER_DIV16384 +*\*\ - SHRTIM_BM_PRESCALER_DIV32768 +**/ +uint32_t SHRTIM_BM_GetPrescaler(SHRTIM_Module *SHRTIMx) +{ + return (uint32_t)READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMPSC); +} + +/** +*\*\fun Enable burst mode compare and period registers preload. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_BM_EnablePreload(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMPLEN); +} + +/** +*\*\fun Disable burst mode compare and period registers preload. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_BM_DisablePreload(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMPLEN); +} + +/** +*\*\fun Indicate whether burst mode compare and period registers are preloaded. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of BMPLEN bit in SHRTIM_BMCTRL register (1 or 0). +**/ +uint32_t SHRTIM_BM_IsEnabledPreload(SHRTIM_Module *SHRTIMx) +{ + uint32_t temp; /* MINTSTSAC-2012 compliance */ + temp = READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMPLEN); + + return ((temp == (SHRTIM_BMCTRL_BMPLEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Set the burst mode controller trigger +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Trig This parameter can be a combination of the following values: +*\*\ - SHRTIM_BM_TRIG_NONE +*\*\ - SHRTIM_BM_TRIG_MASTER_RESET +*\*\ - SHRTIM_BM_TRIG_MASTER_REPETITION +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP1 +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP2 +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP3 +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP4 +*\*\ - SHRTIM_BM_TRIG_TIMA_RESET +*\*\ - SHRTIM_BM_TRIG_TIMA_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMA_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMA_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIMB_RESET +*\*\ - SHRTIM_BM_TRIG_TIMB_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMB_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMB_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIMC_RESET +*\*\ - SHRTIM_BM_TRIG_TIMC_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMC_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMD_RESET +*\*\ - SHRTIM_BM_TRIG_TIMD_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMD_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIME_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIME_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIME_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIMF_RESET +*\*\ - SHRTIM_BM_TRIG_TIMF_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMF_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMA_EVENT7 +*\*\ - SHRTIM_BM_TRIG_TIMD_EVENT8 +*\*\ - SHRTIM_BM_TRIG_EVENT_7 +*\*\ - SHRTIM_BM_TRIG_EVENT_8 +*\*\ - SHRTIM_BM_TRIG_EVENT_ONCHIP +*\*\return None +**/ +void SHRTIM_BM_SetTrig(SHRTIM_Module *SHRTIMx, uint32_t Trig) +{ + WRITE_REG(SHRTIMx->sCommonRegs.BMTG, Trig); +} + +/** +*\*\fun Get actual burst mode controller trigger. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return Trig This parameter can be a combination of the following values: +*\*\ - SHRTIM_BM_TRIG_NONE +*\*\ - SHRTIM_BM_TRIG_MASTER_RESET +*\*\ - SHRTIM_BM_TRIG_MASTER_REPETITION +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP1 +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP2 +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP3 +*\*\ - SHRTIM_BM_TRIG_MASTER_CMP4 +*\*\ - SHRTIM_BM_TRIG_TIMA_RESET +*\*\ - SHRTIM_BM_TRIG_TIMA_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMA_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMA_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIMB_RESET +*\*\ - SHRTIM_BM_TRIG_TIMB_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMB_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMB_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIMC_RESET +*\*\ - SHRTIM_BM_TRIG_TIMC_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMC_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMD_RESET +*\*\ - SHRTIM_BM_TRIG_TIMD_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMD_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIME_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIME_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIME_CMP2 +*\*\ - SHRTIM_BM_TRIG_TIMF_RESET +*\*\ - SHRTIM_BM_TRIG_TIMF_REPETITION +*\*\ - SHRTIM_BM_TRIG_TIMF_CMP1 +*\*\ - SHRTIM_BM_TRIG_TIMA_EVENT7 +*\*\ - SHRTIM_BM_TRIG_TIMD_EVENT8 +*\*\ - SHRTIM_BM_TRIG_EVENT_7 +*\*\ - SHRTIM_BM_TRIG_EVENT_8 +*\*\ - SHRTIM_BM_TRIG_EVENT_ONCHIP +**/ +uint32_t SHRTIM_BM_GetTrig(SHRTIM_Module *SHRTIMx) +{ + return (uint32_t)READ_REG(SHRTIMx->sCommonRegs.BMTG); +} + +/** +*\*\fun Set the burst mode controller compare value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param CompareValue +*\*\return None +**/ +void SHRTIM_BM_SetCompare(SHRTIM_Module *SHRTIMx, uint32_t CompareValue) +{ + WRITE_REG(SHRTIMx->sCommonRegs.BMCMP, CompareValue); +} + +/** +*\*\fun Get actual burst mode controller compare value. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return CompareValue +*\*\note The IDLE time in burst mode must greater than the period of PWM output +**/ +uint32_t SHRTIM_BM_GetCompare(SHRTIM_Module *SHRTIMx) +{ + return (uint32_t)READ_REG(SHRTIMx->sCommonRegs.BMCMP); +} + +/** +*\*\fun Set the burst mode controller period. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Period +*\*\return None +*\*\note The RUN time in burst mode must greater than the period of PWM output +**/ +void SHRTIM_BM_SetPeriod(SHRTIM_Module *SHRTIMx, uint32_t Period) +{ + WRITE_REG(SHRTIMx->sCommonRegs.BMPRD, Period); +} + +/** +*\*\fun Get actual burst mode controller period. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return period +**/ +uint32_t SHRTIM_BM_GetPeriod(SHRTIM_Module *SHRTIMx) +{ + return (uint32_t)READ_REG(SHRTIMx->sCommonRegs.BMPRD); +} + +/** +*\*\fun Enable the burst mode controller +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_BM_Enable(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMEN); +} + +/** +*\*\fun Disable the burst mode controller +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_BM_Disable(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMEN); +} + +/** +*\*\fun Indicate whether the burst mode controller is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of BMEN bit in SHRTIM_BMCTRL register (1 or 0). +**/ +uint32_t SHRTIM_BM_IsEnabled(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMEN) == (SHRTIM_BMCTRL_BMEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Trigger the burst operation (software trigger) +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_BM_Start(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.BMTG, SHRTIM_BMTG_SWSTRT); +} + +/** +*\*\fun Stop the burst mode operation. +*\*\note Causes a burst mode early termination. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_BM_Stop(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMSTS); +} + +/** +*\*\fun Get actual burst mode status +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return Status This parameter can be one of the following values: +*\*\ - SHRTIM_BM_STATUS_NORMAL +*\*\ - SHRTIM_BM_STATUS_BURST_ONGOING +**/ +uint32_t SHRTIM_BM_GetStatus(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sCommonRegs.BMCTRL, SHRTIM_BMCTRL_BMSTS)); +} + +/** +*\*\fun Clear the Fault 1 interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_FALT1(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_FALT1IC); +} + +/** +*\*\fun Indicate whether Fault 1 interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT1ITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_FALT1(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_FALT1ITF) == (SHRTIM_INTSTS_FALT1ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Fault 2 interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_FALT2(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_FALT2IC); +} + +/** +*\*\fun Indicate whether Fault 2 interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT2ITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_FALT2(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_FALT2ITF) == (SHRTIM_INTSTS_FALT2ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Fault 3 interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_FALT3(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_FALT3IC); +} + +/** +*\*\fun Indicate whether Fault 3 interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT3ITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_FALT3(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_FALT3ITF) == (SHRTIM_INTSTS_FALT3ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Fault 4 interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_FALT4(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_FALT4IC); +} + +/** +*\*\fun Indicate whether Fault 4 interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT4ITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_FALT4(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_FALT4ITF) == (SHRTIM_INTSTS_FALT4ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Fault 5 interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_FALT5(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_FALT5IC); +} + +/** +*\*\fun Indicate whether Fault 5 interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT5ITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_FALT5(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_FALT5ITF) == (SHRTIM_INTSTS_FALT5ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Fault 6 interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_FALT6(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_FALT6IC); +} + +/** +*\*\fun Indicate whether Fault 6 interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT6ITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_FALT6(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_FALT6ITF) == (SHRTIM_INTSTS_FALT6ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the System Fault interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_SYSFALT(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_SYSFALTIC); +} + +/** +*\*\fun Indicate whether System Fault interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of SYSFALTITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_SYSFALT(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_SYSFALTITF) == (SHRTIM_INTSTS_SYSFALTITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Burst Mode period interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_BMPRD(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTCLR, SHRTIM_INTCLR_BMPRDIC); +} + +/** +*\*\fun Indicate whether Burst Mode period interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of BMPRDITF bit in SHRTIM_INTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_BMPRD(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTSTS, SHRTIM_INTSTS_BMPRDITF) == (SHRTIM_INTSTS_BMPRDITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the Synchronization Input interrupt flag. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_ClearFlag_SYNC(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sMasterRegs.MINTCLR, SHRTIM_MINTCLR_SYNCINIC); +} + +/** +*\*\fun Indicate whether the Synchronization Input interrupt occurred. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of SYNCINITF bit in SHRTIM_MINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_SYNC(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sMasterRegs.MINTSTS, SHRTIM_MINTSTS_SYNCINITF) == (SHRTIM_MINTSTS_SYNCINITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the update interrupt flag for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MINTCLR_MUPDIC); +} + +/** +*\*\fun Indicate whether the update interrupt has occurred for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MUPDITF/UPDITF bit in SHRTIM_MINTSTS/SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MINTSTS_MUPDITF) == (SHRTIM_MINTSTS_MUPDITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the repetition interrupt flag for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +*\*\note For master timer, repetition interrupt enabled bit is bit4, for TA~TF, is bit5 +**/ +void SHRTIM_ClearFlag_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer; + __IO uint32_t *pReg; + + if(Timer != SHRTIM_TIMER_MASTER) + { + iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_REPTIC); + } + else + { + pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR)); + SET_BIT(*pReg, SHRTIM_MINTCLR_MREPTIC); + } +} + +/** +*\*\fun Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MREPTITF/REPTITF bit in SHRTIM_MINTSTS/SHRTIM_TxINTSTS register (1 or 0). +*\*\note For master timer, repetition interrupt enabled bit is bit4, for TA~TF, is bit5 +**/ +uint32_t SHRTIM_IsActiveFlag_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer; + __IO uint32_t *pReg; + + if(Timer != SHRTIM_TIMER_MASTER) + { + iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_REPTITF) == (SHRTIM_TXINTSTS_REPTITF)) ? 1UL : 0UL); + } + else + { + pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS)); + return ((READ_BIT(*pReg, SHRTIM_MINTSTS_MREPTITF) == (SHRTIM_MINTSTS_MREPTITF)) ? 1UL : 0UL); + } +} + +/** +*\*\fun Clear the compare 1 match interrupt for a given timer (including the master timer). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MINTCLR_MCMP1IC); +} + +/** +*\*\fun Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP1ITF/CMP1ITF bit in SHRTIM_MINTSTS/SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MINTSTS_MCMP1ITF) == (SHRTIM_MINTSTS_MCMP1ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the compare 2 match interrupt for a given timer (including the master timer). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MINTCLR_MCMP2IC); +} + +/** +*\*\fun Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP2ITF/CMP2ITF bit in SHRTIM_MINTSTS/SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MINTSTS_MCMP2ITF) == (SHRTIM_MINTSTS_MCMP2ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the compare 3 match interrupt for a given timer (including the master timer). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MINTCLR_MCMP3IC); +} + +/** +*\*\fun Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP3ITF/CMP3ITF bit in SHRTIM_MINTSTS/SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MINTSTS_MCMP3ITF) == (SHRTIM_MINTSTS_MCMP3ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the compare 4 match interrupt for a given timer (including the master timer). +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MINTCLR_MCMP4IC); +} + +/** +*\*\fun Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP4ITF/CMP4ITF bit in SHRTIM_MINTSTS/SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MINTSTS_MCMP4ITF) == (SHRTIM_MINTSTS_MCMP4ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the compare 5 match for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CMP5(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_CMP5IC); +} + +/** +*\*\fun Indicate whether the compare match 5 has occurred for a given timer . +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CMP5ITF bit in SHRTIM_TXINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CMP5(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_CMP5ITF) == (SHRTIM_TXINTSTS_CMP5ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the capture 1 interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_CPT1IC); +} + +/** +*\*\fun Indicate whether the capture 1 interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CPT1ITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_CPT1ITF) == (SHRTIM_TXINTSTS_CPT1ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the capture 2 interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_CPT2IC); +} + +/** +*\*\fun Indicate whether the capture 2 interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CPT2ITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_CPT2ITF) == (SHRTIM_TXINTSTS_CPT2ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the output 1 set interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_SET1IC); +} + +/** +*\*\fun Indicate whether the output 1 set interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SET1ITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_SET1ITF) == (SHRTIM_TXINTSTS_SET1ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the output 1 reset interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_RST1IC); +} + +/** +*\*\fun Indicate whether the output 1 reset interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RST1ITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_RST1ITF) == (SHRTIM_TXINTSTS_RST1ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the output 2 set interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_SET2IC); +} + +/** +*\*\fun Indicate whether the output 2 set interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SET2ITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_SET2ITF) == (SHRTIM_TXINTSTS_SET2ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the output 2reset interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_RST2IC); +} + +/** +*\*\fun Indicate whether the output 2 reset interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RST2ITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_RST2ITF) == (SHRTIM_TXINTSTS_RST2ITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the reset and/or roll-over interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_RSTROIC); +} + +/** +*\*\fun Indicate whether the reset and/or roll-over interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RSTROITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_RSTROITF) == (SHRTIM_TXINTSTS_RSTROITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Clear the delayed protection interrupt flag for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_ClearFlag_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTCLR) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXINTCLR_DPIC); +} + +/** +*\*\fun Indicate whether the delayed protection interrupt occurred for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DPITF bit in SHRTIM_TxINTSTS register (1 or 0). +**/ +uint32_t SHRTIM_IsActiveFlag_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MINTSTS) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXINTSTS_DPITF) == (SHRTIM_TXINTSTS_DPITF)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault 1 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_FALT1(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT1IEN); +} + +/** +*\*\fun Disable the fault 1 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_FALT1(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT1IEN); +} + +/** +*\*\fun Indicate whether the fault 1 interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT1IEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_FALT1(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT1IEN) == (SHRTIM_INTEN_FALT1IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault 2 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_FALT2(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT2IEN); +} + +/** +*\*\fun Disable the fault 2 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_FALT2(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT2IEN); +} + +/** +*\*\fun Indicate whether the fault 2 interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT2IEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_FALT2(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT2IEN) == (SHRTIM_INTEN_FALT2IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault 3 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_FALT3(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT3IEN); +} + +/** +*\*\fun Disable the fault 3 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_FALT3(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT3IEN); +} + +/** +*\*\fun Indicate whether the fault 3 interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT3IEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_FALT3(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT3IEN) == (SHRTIM_INTEN_FALT3IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault 4 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_FALT4(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT4IEN); +} + +/** +*\*\fun Disable the fault 4 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_FALT4(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT4IEN); +} + +/** +*\*\fun Indicate whether the fault 4 interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT4IEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_FALT4(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT4IEN) == (SHRTIM_INTEN_FALT4IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault 5 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_FALT5(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT5IEN); +} + +/** +*\*\fun Disable the fault 5 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_FALT5(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT5IEN); +} + +/** +*\*\fun Indicate whether the fault 5 interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT5IEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_FALT5(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT5IEN) == (SHRTIM_INTEN_FALT5IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the fault 6 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_FALT6(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT6IEN); +} + +/** +*\*\fun Disable the fault 6 interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_FALT6(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT6IEN); +} + +/** +*\*\fun Indicate whether the fault 6 interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of FALT6IEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_FALT6(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_FALT6IEN) == (SHRTIM_INTEN_FALT6IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the system fault interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_SYSFALT(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_SYSFALTIEN); +} + +/** +*\*\fun Disable the system fault interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_SYSFALT(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_SYSFALTIEN); +} + +/** +*\*\fun Indicate whether the system fault interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of SYSFALTIEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_SYSFALT(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_SYSFALTIEN) == (SHRTIM_INTEN_SYSFALTIEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the burst mode period interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_BMPRD(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_BMPRDIEN); +} + +/** +*\*\fun Disable the burst mode period interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_BMPRD(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_BMPRDIEN); +} + +/** +*\*\fun Indicate whether the burst mode period interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of BMPRDIEN bit in SHRTIM_INTEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_BMPRD(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sCommonRegs.INTEN, SHRTIM_INTEN_BMPRDIEN) == (SHRTIM_INTEN_BMPRDIEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the synchronization input interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableIT_SYNC(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sMasterRegs.MIDEN, SHRTIM_MIDEN_SYNCINIEN); +} + +/** +*\*\fun Disable the synchronization input interrupt. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableIT_SYNC(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sMasterRegs.MIDEN, SHRTIM_MIDEN_SYNCINIEN); +} + +/** +*\*\fun Indicate whether the synchronization input interrupt is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of SYNCINIEN bit in SHRTIM_MIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_SYNC(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sMasterRegs.MIDEN, SHRTIM_MIDEN_SYNCINIEN) == (SHRTIM_MIDEN_SYNCINIEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the update interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MUPDIEN); +} + +/** +*\*\fun Disable the update interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MUPDIEN); +} + +/** +*\*\fun Indicate whether the update interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MUPDIEN/UPDIEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MUPDIEN) == (SHRTIM_MIDEN_MUPDIEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the repetition interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +*\*\note For master timer, repetition interrupt enabled bit is bit4, for TA~TF, is bit5 +**/ +void SHRTIM_EnableIT_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer; + __IO uint32_t *pReg; + + if(Timer != SHRTIM_TIMER_MASTER) + { + iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_REPTIEN); + } + else + { + pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN)); + SET_BIT(*pReg, SHRTIM_MIDEN_MREPTIEN); + } +} + +/** +*\*\fun Disable the repetition interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +*\*\note For master timer, repetition interrupt enabled bit is bit4, for TA~TF, is bit5 +**/ +void SHRTIM_DisableIT_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer; + __IO uint32_t *pReg; + + if(Timer != SHRTIM_TIMER_MASTER) + { + iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_REPTIEN); + } + else + { + pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN)); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MREPTIEN); + } +} + +/** +*\*\fun Indicate whether the repetition interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MREPTIEN/REPTIEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer; + __IO uint32_t *pReg; + + if(Timer != SHRTIM_TIMER_MASTER) + { + iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_TACNTEN_Pos); + pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sTimerxRegs[0].TxIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_REPTIEN) == (SHRTIM_TXIDEN_REPTIEN)) ? 1UL : 0UL); + } + else + { + pReg = (__IO uint32_t *)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN)); + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MREPTIEN) == (SHRTIM_MIDEN_MREPTIEN)) ? 1UL : 0UL); + } +} + +/** +*\*\fun Enable the compare 1 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP1IEN); +} + +/** +*\*\fun Disable the compare 1 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP1IEN); +} + +/** +*\*\fun Indicate whether the compare 1 interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP1IEN/CMP1IEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP1IEN) == (SHRTIM_MIDEN_MCMP1IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 2 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP2IEN); +} + +/** +*\*\fun Disable the compare 2 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP2IEN); +} + +/** +*\*\fun Indicate whether the compare 2 interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP2IEN/CMP2IEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP2IEN) == (SHRTIM_MIDEN_MCMP2IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 3 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP3IEN); +} + +/** +*\*\fun Disable the compare 3 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP3IEN); +} + +/** +*\*\fun Indicate whether the compare 3 interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP3IEN/CMP3IEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP3IEN) == (SHRTIM_MIDEN_MCMP3IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 4 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP4IEN); +} + +/** +*\*\fun Disable the compare 4 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP4IEN); +} + +/** +*\*\fun Indicate whether the compare 4 interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP4IEN/CMP4IEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP4IEN) == (SHRTIM_MIDEN_MCMP4IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the capture 1 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_CPT1IEN); +} + +/** +*\*\fun Enable the capture 1 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_CPT1IEN); +} + +/** +*\*\fun Indicate whether the capture 1 interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CPT1IEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_CPT1IEN) == (SHRTIM_TXIDEN_CPT1IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the capture 2 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_CPT2IEN); +} + +/** +*\*\fun Enable the capture 2 interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_CPT2IEN); +} + +/** +*\*\fun Indicate whether the capture 2 interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CPT2IEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_CPT2IEN) == (SHRTIM_TXIDEN_CPT2IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 1 set interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_SET1IEN); +} + +/** +*\*\fun Disable the output 1 set interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_SET1IEN); +} + +/** +*\*\fun Indicate whether the output 1 set interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SET1IEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_SET1IEN) == (SHRTIM_TXIDEN_SET1IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 1 reset interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_RST1IEN); +} + +/** +*\*\fun Disable the output 1 reset interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_RST1IEN); +} + +/** +*\*\fun Indicate whether the output 1 reset interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RST1IEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_RST1IEN) == (SHRTIM_TXIDEN_RST1IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 2 set interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_SET2IEN); +} + +/** +*\*\fun Disable the output 2 set interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_SET2IEN); +} + +/** +*\*\fun Indicate whether the output 2 set interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SET2IEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_SET2IEN) == (SHRTIM_TXIDEN_SET2IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 2 reset interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_RST2IEN); +} + +/** +*\*\fun Disable the output 2 reset interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_RST2IEN); +} + +/** +*\*\fun Indicate whether the output 2 reset SHRTIM_IsEnabledIT_RST2 is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RST2IEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_RST2IEN) == (SHRTIM_TXIDEN_RST2IEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the reset/roll-over interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_RSTROIEN); +} + +/** +*\*\fun Disable the reset/roll-over interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_RSTROIEN); +} + +/** +*\*\fun Indicate whether the reset/roll-over interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RSTROIEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_RSTROIEN) == (SHRTIM_TXIDEN_RSTROIEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the delayed protection interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableIT_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_DPIEN); +} + +/** +*\*\fun Disable the delayed protection interrupt for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableIT_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_DPIEN); +} + +/** +*\*\fun Indicate whether the delayed protection interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DPIEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledIT_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_DPIEN) == (SHRTIM_TXIDEN_DPIEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the synchronization input DMA request. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableDMAReq_SYNC(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sMasterRegs.MIDEN, SHRTIM_MIDEN_SYNCINDEN); +} + +/** +*\*\fun Disable the synchronization input DMA request +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableDMAReq_SYNC(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sMasterRegs.MIDEN, SHRTIM_MIDEN_SYNCINDEN); +} + +/** +*\*\fun Indicate whether the synchronization input DMA request is enabled. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return State of SYNCINDEN bit in SHRTIM_MIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_SYNC(SHRTIM_Module *SHRTIMx) +{ + return ((READ_BIT(SHRTIMx->sMasterRegs.MIDEN, SHRTIM_MIDEN_SYNCINDEN) == (SHRTIM_MIDEN_SYNCINDEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the update DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MUPDDEN); +} + +/** +*\*\fun Disable the update DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MUPDDEN); +} + +/** +*\*\fun Indicate whether the update DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MUPDDEN/UPDDEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_UPDATE(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MUPDDEN) == (SHRTIM_MIDEN_MUPDDEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the repetition DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MREPTDEN); +} + +/** +*\*\fun Disable the repetition DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MREPTDEN); +} + +/** +*\*\fun Indicate whether the repetition DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MREPTDEN/REPTDEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_REP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MREPTDEN) == (SHRTIM_MIDEN_MREPTDEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 1 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP1DEN); +} + +/** +*\*\fun Disable the compare 1 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP1DEN); +} + +/** +*\*\fun Indicate whether the compare 1 DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP1DEN/CMP1DEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_CMP1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP1DEN) == (SHRTIM_MIDEN_MCMP1DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 2 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP2DEN); +} + +/** +*\*\fun Disable the compare 2 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP2DEN); +} + +/** +*\*\fun Indicate whether the compare 2 DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP2DEN/CMP2DEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_CMP2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP2DEN) == (SHRTIM_MIDEN_MCMP2DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 3 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP3DEN); +} + +/** +*\*\fun Disable the compare 3 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP3DEN); +} + +/** +*\*\fun Indicate whether the compare 3 DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP3DEN/CMP3DEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_CMP3(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP3DEN) == (SHRTIM_MIDEN_MCMP3DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the compare 4 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_MIDEN_MCMP4DEN); +} + +/** +*\*\fun Disable the compare 4 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_MIDEN_MCMP4DEN); +} + +/** +*\*\fun Indicate whether the compare 4 DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of MCMP4DEN/CMP4DEN bit in SHRTIM_MIDEN/SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_CMP4(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_MIDEN_MCMP4DEN) == (SHRTIM_MIDEN_MCMP4DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the capture 1 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_CPT1DEN); +} + +/** +*\*\fun Disable the capture 1 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_CPT1DEN); +} + +/** +*\*\fun Indicate whether the capture 1 DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CPT1DEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_CPT1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_CPT1DEN) == (SHRTIM_TXIDEN_CPT1DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the capture 2 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_CPT2DEN); +} + +/** +*\*\fun Disable the capture 2 DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_CPT2DEN); +} + +/** +*\*\fun Indicate whether the capture 2 DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of CPT2DEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_CPT2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_CPT2DEN) == (SHRTIM_TXIDEN_CPT2DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 1 set DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_SET1DEN); +} + +/** +*\*\fun Disable the output 1 set DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_SET1DEN); +} + +/** +*\*\fun Indicate whether the output 1 set DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SET1DEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_SET1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_SET1DEN) == (SHRTIM_TXIDEN_SET1DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 1 reset DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_RST1DEN); +} + +/** +*\*\fun Disable the output 1 reset DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_RST1DEN); +} + +/** +*\*\fun Indicate whether the output 1 reset interrupt is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RST1DEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_RST1(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_RST1DEN) == (SHRTIM_TXIDEN_RST1DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 2 set DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_SET2DEN); +} + +/** +*\*\fun Disable the output 2 set DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_SET2DEN); +} + +/** +*\*\fun Indicate whether the output 2 set DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of SET2DEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_SET2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_SET2DEN) == (SHRTIM_TXIDEN_SET2DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the output 2 reset DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_RST2DEN); +} + +/** +*\*\fun Disable the output 2 reset DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_RST2DEN); +} + +/** +*\*\fun Indicate whether the output 2 reset DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RST2DEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_RST2(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_RST2DEN) == (SHRTIM_TXIDEN_RST2DEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the reset/roll-over DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_RSTRODEN); +} + +/** +*\*\fun Disable the reset/roll-over DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_RSTRODEN); +} + +/** +*\*\fun Indicate whether the reset/roll-over DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of RSTRODEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_RST(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_RSTRODEN) == (SHRTIM_TXIDEN_RSTRODEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Enable the delayed protection DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDMAReq_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + SET_BIT(*pReg, SHRTIM_TXIDEN_DPDEN); +} + +/** +*\*\fun Disable the delayed protection DMA request for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDMAReq_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + CLEAR_BIT(*pReg, SHRTIM_TXIDEN_DPDEN); +} + +/** +*\*\fun Indicate whether the delayed protection DMA request is enabled for a given timer. +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return State of DPDEN bit in SHRTIM_TxIDEN register (1 or 0). +**/ +uint32_t SHRTIM_IsEnabledDMAReq_DP(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - SHRTIM_MCTRL_MCNTEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&SHRTIMx->sMasterRegs.MIDEN) + + REG_OFFSET_TAB_TIMER[iTimer])); + + return ((READ_BIT(*pReg, SHRTIM_TXIDEN_DPDEN) == (SHRTIM_TXIDEN_DPDEN)) ? 1UL : 0UL); +} + +/** +*\*\fun Disable halt all timers counter(master + slave) while in debug mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_DisableDebugHaltAllTimers(SHRTIM_Module *SHRTIMx) +{ + SET_BIT(SHRTIMx->sMasterRegs.FRZDIS, SHRTIM_FRZDIS_ALLTIMDBGEN); +} + +/** +*\*\fun Enable halt all timers counter(master + slave) while in debug mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +void SHRTIM_EnableDebugHaltAllTimers(SHRTIM_Module *SHRTIMx) +{ + CLEAR_BIT(SHRTIMx->sMasterRegs.FRZDIS, SHRTIM_FRZDIS_ALLTIMDBGEN); +} + +/** +*\*\fun Is all timers counter(master + slave) be halted while in debug mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return None +**/ +uint32_t SHRTIM_IsEnabledDebugHaltAllTimers(SHRTIM_Module *SHRTIMx) +{ + return (READ_BIT(SHRTIMx->sMasterRegs.FRZDIS, SHRTIM_FRZDIS_ALLTIMDBGEN) == 0UL) ? 1UL : 0UL; +} +/** +*\*\fun Enable halt a given timer counter while in debug mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_EnableDebugHaltTimer(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + CLEAR_BIT(SHRTIMx->sMasterRegs.FRZDIS, ((Timer >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_FRZDIS_CONFIG_MASK)); +} + +/** +*\*\fun Disable halt a given timer counter while in debug mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +void SHRTIM_DisableDebugHaltTimer(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + SET_BIT(SHRTIMx->sMasterRegs.FRZDIS, ((Timer >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_FRZDIS_CONFIG_MASK)); +} + +/** +*\*\fun Is a given timer counter halted while in debug mode +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param Timer This parameter can be one of the following values: +*\*\ - SHRTIM_TIMER_MASTER +*\*\ - SHRTIM_TIMER_A +*\*\ - SHRTIM_TIMER_B +*\*\ - SHRTIM_TIMER_C +*\*\ - SHRTIM_TIMER_D +*\*\ - SHRTIM_TIMER_E +*\*\ - SHRTIM_TIMER_F +*\*\return None +**/ +uint32_t SHRTIM_IsEnabledDebugHaltTimer(SHRTIM_Module *SHRTIMx, uint32_t Timer) +{ + return (READ_BIT(SHRTIMx->sMasterRegs.FRZDIS, ((Timer >> SHRTIM_MCTRL_MCNTEN_Pos) & SHRTIM_FRZDIS_CONFIG_MASK)) == 0UL) ? 1UL : 0UL; +} + +/** +*\*\fun Set Auxilira output bypass +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\param AuxBypa This parameter can be one of the following values: +*\*\ - SHRTIM_AUXOUTPUT_DEFAULT aunxiliary output signals is follow main output +*\*\ - SHRTIM_AUXOUTPUT_FOLLOW_CROSSBAR aunxiliary output signals is follow crossbar +*\*\ - SHRTIM_AUXOUTPUT_FOLLOW_MAINOUTPUT aunxiliary output signals is follow main output +*\*\return None +**/ +void SHRTIM_SetAuxliaryBypass(SHRTIM_Module *SHRTIMx, uint32_t AuxBypa) +{ + SET_BIT(SHRTIMx->sCommonRegs.EXTEND, AuxBypa); +} + +/** +*\*\fun get Auxilira output bypass +*\*\param SHRTIMx Super High Resolution Timer instance +*\*\return +*\*\ - SHRTIM_AUXOUTPUT_DEFAULT aunxiliary output signals is follow main output +*\*\ - SHRTIM_AUXOUTPUT_FOLLOW_CROSSBAR aunxiliary output signals is follow crossbar +*\*\ - SHRTIM_AUXOUTPUT_FOLLOW_MAINOUTPUT aunxiliary output signals is follow main output +**/ +uint32_t SHRTIM_GetAuxliaryBypass(SHRTIM_Module *SHRTIMx) +{ + return READ_BIT(SHRTIMx->sCommonRegs.EXTEND, SHRITM_AUXOUTPUT_BYPASS); +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_smu.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_smu.c new file mode 100644 index 0000000000..1a1c2e01e9 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_smu.c @@ -0,0 +1,136 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_smu.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_smu.h" + +/* SMU Driving Functions Declaration */ + +/* SMU_Private_Defines */ + +/** +*\*\name SMU_GetM4BootAddr. +*\*\fun Read boot address of CM4 +*\*\param none +*\*\return CM4 boot address +**/ +uint32_t SMU_GetM4BootAddr( void ) +{ + return (*(uint32_t (*)(void))GET_M4ADDR)(); +} + +/** +*\*\name SMU_SetM4BootAddr. +*\*\fun Setting boot address of CM4 +*\*\param CM4 boot address +*\*\return Status flag +*\*\ -SMU_SUCCESS +*\*\ -SMU_ERR +**/ +uint32_t SMU_SetM4BootAddr( uint32_t addr ) +{ + return (*(uint32_t (*)(uint32_t))(SET_M4ADDR))( addr ); +} + +/** +*\*\name SMU_GetM7BootAddr. +*\*\fun Read boot address of CM7 +*\*\param none +*\*\return CM7 boot address +**/ +uint32_t SMU_GetM7BootAddr( void ) +{ + return (*(uint32_t (*)(void))GET_M7ADDR)(); +} + +/** +*\*\name SMU_SetM4BootAddr. +*\*\fun Setting boot address of CM7 +*\*\param CM7 boot address +*\*\return Status flag +*\*\ -SMU_SUCCESS +*\*\ -SMU_ERR +**/ +uint32_t SMU_SetM7BootAddr( uint32_t addr ) +{ + return (*(uint32_t (*)(uint32_t))(SET_M7ADDR))( addr ); +} + +/** +*\*\name SMU_EraseFlash. +*\*\fun Flash erase +*\*\param Flash start address, erase the 4KB sector where the start address is located +*\*\return Error flag +*\*\ -FLASH_SUCCESS +*\*\ -FLASH_FAILED +*\*\note Erase in 4KB units +**/ +uint32_t SMU_EraseFlash(uint32_t StrAddr) +{ + return (*(uint32_t (*)(uint32_t))(ER_FLASH))( StrAddr ); +} + +/** +*\*\name SMU_WriteFlash. +*\*\fun Write data to internal xSPI flash +*\*\param Flash start address +*\*\param The pointer of data buffer +*\*\param Data lenght +*\*\return Error flag +*\*\ -FLASH_SUCCESS +*\*\ -FLASH_FAILED +**/ +uint32_t SMU_WriteFlash(uint32_t StrAddr, uint8_t *SrcBuf, uint32_t Len) +{ + return (*(uint32_t (*)(uint32_t, uint8_t*, uint32_t))(WR_FLASH))( StrAddr, SrcBuf, Len ); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_spi.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_spi.c new file mode 100644 index 0000000000..5f7dfa4f5a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_spi.c @@ -0,0 +1,962 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_spi.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_spi.h" +#include "n32h76x_78x_rcc.h" + +/* SPI Driving Functions Declaration */ + +/* SPI_Private_Defines */ + +/* SPI SPE mask */ +#define CTRL2_SPIEN_ENABLE ((uint16_t)0x0001U) +#define CTRL2_SPIEN_DISABLE ((uint16_t)0xFFFEU) + +/* SPI CRCNext mask */ +#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x0200U) + +/* SPI CRCEN mask */ +#define CTRL2_CRCEN_ENABLE ((uint16_t)0x0008U) +#define CTRL2_CRCEN_DISABLE ((uint16_t)0xFFF7U) + +/* SPI SSOE mask */ +#define CTRL1_SSOEN_ENABLE ((uint16_t)0x0400U) +#define CTRL1_SSOEN_DISABLE ((uint16_t)0xFBFFU) + +/* SPI registers Masks */ +#define CTRL1_CLR_MASK ((uint16_t)0xF9F7U) +#define I2SCFG_CLR_MASK ((uint16_t)0x05FCU) +#define I2SPR_CLEAR_Mask ((uint16_t)0x0FFFU) + +/* SPI or I2S mode selection masks */ +#define SPI_MODE_ENABLE ((uint16_t)0xFFFDU) +#define I2S_MODE_ENABLE ((uint16_t)0x0002U) + +/** +*\*\name SPI_I2S_DeInit. +*\*\fun Deinitializes the SPIx peripheral registers to their default reset values (Affects also the I2Ss) +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\return none +**/ +void SPI_I2S_DeInit(const SPI_Module* SPIx) +{ + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_SPI1); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_EnableAPB2PeriphReset2(RCC_APB2_PERIPHRST_SPI2); + } + else if(SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_EnableAPB1PeriphReset2(RCC_APB1_PERIPHRST_SPI3); + } + else if (SPIx == SPI4) + { + /* Enable SPI4 reset state */ + RCC_EnableAPB5PeriphReset1(RCC_APB5_PERIPHRST_SPI4); + } + else if (SPIx == SPI5) + { + /* Enable SPI5 reset state */ + RCC_EnableAPB5PeriphReset1(RCC_APB5_PERIPHRST_SPI5); + } + else if (SPIx == SPI6) + { + /* Enable SPI6 reset state */ + RCC_EnableAPB5PeriphReset1(RCC_APB5_PERIPHRST_SPI6); + } + else if (SPIx == SPI7) + { + /* Enable SPI7 reset state */ + RCC_EnableAPB5PeriphReset1(RCC_APB5_PERIPHRST_SPI7); + } + else {} +} + + +/** +*\*\name SPI_Init. +*\*\fun Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param SPI_InitStruct : +*\*\ - DataDirection +*\*\ - SPI_DIR_DOUBLELINE_FULLDUPLEX +*\*\ - SPI_DIR_DOUBLELINE_RONLY +*\*\ - SPI_DIR_SINGLELINE_RX +*\*\ - SPI_DIR_SINGLELINE_TX +*\*\ - SpiMode +*\*\ - SPI_MODE_MASTER +*\*\ - SPI_MODE_SLAVE +*\*\ - DataLen +*\*\ - SPI_DATA_SIZE_16BITS +*\*\ - SPI_DATA_SIZE_8BITS +*\*\ - CLKPOL +*\*\ - SPI_CLKPOL_LOW +*\*\ - SPI_CLKPOL_HIGH +*\*\ - CLKPHA +*\*\ - SPI_CLKPHA_FIRST_EDGE +*\*\ - SPI_CLKPHA_SECOND_EDGE +*\*\ - NSS +*\*\ - SPI_NSS_SOFT +*\*\ - SPI_NSS_HARD +*\*\ - BaudRatePres +*\*\ - SPI_BR_PRESCALER_2 +*\*\ - SPI_BR_PRESCALER_4 +*\*\ - SPI_BR_PRESCALER_8 +*\*\ - SPI_BR_PRESCALER_16 +*\*\ - SPI_BR_PRESCALER_32 +*\*\ - SPI_BR_PRESCALER_64 +*\*\ - SPI_BR_PRESCALER_128 +*\*\ - SPI_BR_PRESCALER_256 +*\*\ - FirstBit +*\*\ - SPI_FB_MSB +*\*\ - SPI_FB_LSB +*\*\ - CRCPoly default 0x0007, max 0xffff +*\*\return none +**/ +void SPI_Init(SPI_Module* SPIx, const SPI_InitType* SPI_InitStruct) +{ + uint16_t tmpregister; + + /*---------------------------- SPIx CTRL1 Configuration ------------------------*/ + /* Get the SPIx CTRL1 value */ + tmpregister = SPIx->CTRL1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpregister &= CTRL1_CLR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */ + /* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */ + /* Set LSBFirst bit according to FirstBit value */ + /* Set BR bits according to BaudRatePres value */ + /* Set CPOL bit according to CLKPOL value */ + /* Set CPHA bit according to CLKPHA value */ + tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode + | SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA + | SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit); + /* Write to SPIx CTRL1 */ + SPIx->CTRL1 = tmpregister; + + /* Activate the SPI mode (Reset I2SMOD bit in SPI_I2S_CFGR register) */ + SPIx->SPI_I2S_CFGR &= SPI_MODE_ENABLE; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPOLY = SPI_InitStruct->CRCPoly; +} + +/** +*\*\name SPI_InitStruct. +*\*\fun Fills each SPI_InitStruct member with its default value. +*\*\param SPI_InitStruct : +*\*\ - DataDirection +*\*\ - SpiMode +*\*\ - DataLen +*\*\ - CLKPOL +*\*\ - CLKPHA +*\*\ - NSS +*\*\ - BaudRatePres +*\*\ - FirstBit +*\*\ - CRCPoly +*\*\return none +**/ +void SPI_InitStruct(SPI_InitType* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the DataDirection member */ + SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + /* initialize the SpiMode member */ + SPI_InitStruct->SpiMode = SPI_MODE_SLAVE; + /* initialize the DataLen member */ + SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS; + /* Initialize the CLKPOL member */ + SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW; + /* Initialize the CLKPHA member */ + SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE; + /* Initialize the NSS member */ + SPI_InitStruct->NSS = SPI_NSS_HARD; + /* Initialize the BaudRatePres member */ + SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2; + /* Initialize the FirstBit member */ + SPI_InitStruct->FirstBit = SPI_FB_MSB; + /* Initialize the CRCPoly member */ + SPI_InitStruct->CRCPoly = 7; +} + + +/** +*\*\name SPI_Enable. +*\*\fun Enables or disables the specified SPI peripheral. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CTRL2 |= CTRL2_SPIEN_ENABLE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CTRL2 &= CTRL2_SPIEN_DISABLE; + } +} + +/** +*\*\name SPI_I2S_EnableInt. +*\*\fun Enables or disables the specified SPI/I2S interrupts. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_I2S_INT_TE +*\*\ - SPI_I2S_INT_RNE +*\*\ - SPI_I2S_INT_ERR +*\*\ - SPI_I2S_INT_RXONLYC +*\*\ - SPI_I2S_INT_RXFIFOF +*\*\ - SPI_I2S_INT_RXFIFOHF +*\*\ - SPI_I2S_INT_TXFIFOHE +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd) +{ + uint16_t itpos, itmask; + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CTRL2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CTRL2 &= (uint16_t)~itmask; + } +} + + +/** +*\*\name SPI_I2S_EnableDma. +*\*\fun Enables or disables the SPIx/I2Sx DMA interface. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_DMAReq : +*\*\ - SPI_I2S_DMA_TX +*\*\ - SPI_I2S_DMA_RX +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + + +/** +*\*\name SPI_I2S_TransmitData. +*\*\fun Transmits a Data through the SPIx/I2Sx peripheral. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param Data \* Data to be transmitted *\ +*\*\return none +**/ +void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data) +{ + /* Write in the DAT register the data to be sent */ + SPIx->DAT = Data; +} + + +/** +*\*\name SPI_I2S_ReceiveData. +*\*\fun Returns the most recent received data by the SPIx/I2Sx peripheral. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\return The data in the SPI_DAT register. +**/ +uint16_t SPI_I2S_ReceiveData(const SPI_Module* SPIx) +{ + /* Return the data in the DAT register */ + return SPIx->DAT; +} + + +/** +*\*\name SPI_SetNssLevel. +*\*\fun Configures internally by software the NSS pin for the selected SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param SPI_NSSInternalSoft : +*\*\ - SPI_NSS_HIGH +*\*\ - SPI_NSS_LOW +*\*\return none +**/ +void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft) +{ + if (SPI_NSSInternalSoft != SPI_NSS_LOW) + { + /* Set NSS pin internally by software */ + SPIx->CTRL1 |= SPI_NSS_HIGH; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CTRL1 &= SPI_NSS_LOW; + } +} + + +/** +*\*\name SPI_SSOutputEnable. +*\*\fun Enables or disables the SS output for the selected SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CTRL1 |= CTRL1_SSOEN_ENABLE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CTRL1 &= CTRL1_SSOEN_DISABLE; + } +} + +/** +*\*\name SPI_ConfigDataLen. +*\*\fun Configures the data size for the selected SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param DataLen : +*\*\ - SPI_DATA_SIZE_16BITS +*\*\ - SPI_DATA_SIZE_8BITS +*\*\return none +**/ +void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen) +{ + /* Clear DFF bit */ + SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS; + /* Set new DFF bit value */ + SPIx->CTRL1 |= DataLen; +} + + +/** +*\*\name SPI_TransmitCrcNext. +*\*\fun Transmit the SPIx CRC value. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SPI_TransmitCrcNext(SPI_Module* SPIx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI CRC transmission */ + SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE; + } + else + { + /* Disable the selected SPI CRC transmission */ + SPIx->CTRL1 &= (~CTRL1_CRCNEXT_ENABLE); + } +} + + +/** +*\*\name SPI_EnableCalculateCrc. +*\*\fun Enables or disables the CRC value calculation of the transferred bytes. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CTRL2 |= CTRL2_CRCEN_ENABLE; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CTRL2 &= CTRL2_CRCEN_DISABLE; + } +} + +/** +*\*\name SPI_GetCRCDat. +*\*\fun Returns the transmit or the receive CRC register value for the specified SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param Cmd : +*\*\ - SPI_CRC_TX +*\*\ - SPI_CRC_RX +*\*\return Tx/Rx CRC register value. +**/ +uint16_t SPI_GetCRCDat(const SPI_Module* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg; + + if (SPI_CRC != SPI_CRC_RX) + { + /* Get the Tx CRC register */ + crcreg = SPIx->CRCTDAT; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->CRCRDAT; + } + + /* Return the selected CRC register */ + return crcreg; +} + +/** +*\*\name SPI_GetCRCPoly. +*\*\fun Returns the CRC Polynomial register value for the specified SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\return The CRC Polynomial register value. +**/ +uint16_t SPI_GetCRCPoly(const SPI_Module* SPIx) +{ + /* Return the CRC polynomial register */ + return SPIx->CRCPOLY; +} + +/** +*\*\name SPI_SetCRCPoly. +*\*\fun Set the CRC Polynomial register value for the specified SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\return The CRC Polynomial register value. +**/ +void SPI_SetCRCPoly(SPI_Module* SPIx, uint16_t SpiCrcPoly) +{ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPOLY = SpiCrcPoly; + return; +} + +/** +*\*\name SPI_ConfigBidirectionalMode. +*\*\fun Selects the data transfer direction in bi-directional mode for the specified SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param DataDirection : +*\*\ - SPI_BIDIRECTION_TX +*\*\ - SPI_BIDIRECTION_RX +*\*\return none. +**/ +void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection) +{ + if (DataDirection == SPI_BIDIRECTION_TX) + { + /* Set the Tx only mode */ + SPIx->CTRL1 |= SPI_BIDIRECTION_TX; + } + else + { + /* Set the Rx only mode */ + SPIx->CTRL1 &= SPI_BIDIRECTION_RX; + } +} + + +/** +*\*\name SPI_SetDataDirection. +*\*\fun Selects the data transfer direction in bi-directional mode for the specified SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param DataDirection : +*\*\ - SPI_DIR_DOUBLELINE_FULLDUPLEX +*\*\ - SPI_DIR_DOUBLELINE_RONLY +*\*\ - SPI_DIR_DOUBLELINE_TONLY +*\*\ - SPI_DIR_SINGLELINE_RX +*\*\ - SPI_DIR_SINGLELINE_TX +*\*\return none. +**/ +void SPI_SetDataDirection(SPI_Module* SPIx, uint16_t DataDirection) +{ + uint16_t tmpregister; + /* Get the SPIx CTRL1 value */ + tmpregister = SPIx->CTRL1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpregister &= SPI_DIR_MASK; + tmpregister |= DataDirection; + SPIx->CTRL1 = tmpregister; +} + +/** +*\*\name SPI_I2S_GetStatus. +*\*\fun Checks whether the specified SPI/I2S flag is set or not. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_FLAG : +*\*\ - SPI_I2S_BUSY_FLAG +*\*\ - SPI_I2S_OVER_FLAG +*\*\ - SPI_MODERR_FLAG +*\*\ - SPI_CRCERR_FLAG +*\*\ - I2S_UNDER_FLAG +*\*\ - I2S_CHSIDE_FLAG +*\*\ - SPI_I2S_TE_FLAG +*\*\ - SPI_I2S_RNE_FLAG +*\*\ - SPI_I2S_RXONLYC_FLAG +*\*\ - SPI_I2S_RXFIFOF_FLAG +*\*\ - SPI_I2S_TXFIFOE_FLAG +*\*\ - SPI_I2S_RXFIFOHF_FLAG +*\*\ - SPI_I2S_TXFIFOHE_FLAG +*\*\return The new state of SPI_I2S_FLAG (SET or RESET). +**/ +FlagStatus SPI_I2S_GetStatus(const SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus; + + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** +*\*\name SPI_I2S_ClrCRCErrFlag. +*\*\fun Clears the SPIx CRC Error (CRCERR) flag. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 +*\*\param SPI_I2S_FLAG : +*\*\ - SPI_CRCERR_FLAG +*\*\return none. +**/ +void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->STS = (uint16_t)~SPI_I2S_FLAG; +} + +/** +*\*\name SPI_I2S_GetIntStatus. +*\*\fun Checks whether the specified SPI/I2S interrupt has occurred or not. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_I2S_INT_TE +*\*\ - SPI_I2S_INT_RNE +*\*\ - SPI_I2S_INT_RXONLYC +*\*\ - SPI_I2S_INT_RXFIFOF +*\*\ - SPI_I2S_INT_RXFIFOHF +*\*\ - SPI_I2S_INT_TXFIFOHE +*\*\ - SPI_I2S_INT_CRCERR +*\*\ - SPI_I2S_INT_MODERR +*\*\ - SPI_I2S_INT_OVERERR +*\*\ - I2S_I2S_INT_UNDER +*\*\return The new state of SPI_I2S_IT (SET or RESET). +**/ + +INTStatus SPI_I2S_GetIntStatus(const SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + INTStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CTRL2 & itmask); + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** +*\*\name SPI_I2S_ClrITPendingBit. +*\*\fun Clears the SPIx CRC Error (CRCERR) interrupt pending bit. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_IT : +*\*\ - SPI_I2S_INT_TE +*\*\ - SPI_I2S_INT_RNE +*\*\ - SPI_I2S_INT_ERR +*\*\ - SPI_I2S_INT_RXONLYC +*\*\ - SPI_I2S_INT_RXFIFOF +*\*\ - SPI_I2S_INT_RXFIFOHF +*\*\ - SPI_I2S_INT_TXFIFOHE +*\*\ - SPI_I2S_INT_MODERR +*\*\ - SPI_I2S_INT_CRCERR +*\*\ - SPI_I2S_INT_OVERERR +*\*\ - SPI_I2S_INT_UNDER +*\*\return none. +**/ +void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos; + + /* Get the SPI IT index */ + itpos = 0x0001 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->STS = (uint16_t)~itpos; +} + +/** +*\*\name SPI_I2S_FIFO_Cmd. +*\*\fun Enables or disables the FIFO (in SPI/I2S mode). +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void SPI_I2S_FIFO_Cmd(SPI_Module* SPIx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the FIFO (in SPI/I2S mode) */ + SPIx->CTRL2 |= SPI_I2S_FIFO_Enable; + } + else + { + /* Disable the FIFO (in SPI/I2S mode) */ + SPIx->CTRL2 &= SPI_I2S_FIFO_Disable; + } +} + +/** +*\*\name SPI_I2S_ClearFIFOBit. +*\*\fun Clears the SPIx FIFO bit. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_I2S_FIFO_Clear : +*\*\ - SPI_I2S_FIFO_CLR +*\*\return none. +**/ +void SPI_I2S_ClearFIFOBit(SPI_Module* SPIx, uint16_t SPI_I2S_FIFO_Clear) +{ + /* Clear the FIFO bit */ + SPIx->CTRL2 |= SPI_I2S_FIFO_Clear; + SPIx->CTRL2 &= ~SPI_I2S_FIFO_Clear; +} + +/** +*\*\name SPI_RxFIFOSizeConfig. +*\*\fun Configures the Rx FIFO size for the selected SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_FIFOSize : +*\*\ - SPI_RX_FIF0NUM_7 +*\*\ - SPI_RX_FIF0NUM_6 +*\*\ - SPI_RX_FIF0NUM_5 +*\*\ - SPI_RX_FIF0NUM_4 +*\*\ - SPI_RX_FIF0NUM_3 +*\*\ - SPI_RX_FIF0NUM_2 +*\*\ - SPI_RX_FIF0NUM_1 +*\*\ - SPI_RX_FIF0NUM_0 +*\*\return none. +**/ +void SPI_RxFIFOSizeConfig(SPI_Module* SPIx, uint16_t SPI_FIFOSize) +{ + /* Clear DFF bit */ + SPIx->FIFONUM &= (uint16_t)~SPI_RX_FIF0NUM_7; + /* Set new DFF bit value */ + SPIx->FIFONUM |= SPI_FIFOSize; +} + +/** +*\*\name SPI_TxFIFOSizeConfig. +*\*\fun Configures the Tx FIFO size for the selected SPI. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param SPI_FIFOSize : +*\*\ - SPI_TX_FIF0NUM_7 +*\*\ - SPI_TX_FIF0NUM_6 +*\*\ - SPI_TX_FIF0NUM_5 +*\*\ - SPI_TX_FIF0NUM_4 +*\*\ - SPI_TX_FIF0NUM_3 +*\*\ - SPI_TX_FIF0NUM_2 +*\*\ - SPI_TX_FIF0NUM_1 +*\*\ - SPI_TX_FIF0NUM_0 +*\*\return none. +**/ +void SPI_TxFIFOSizeConfig(SPI_Module* SPIx, uint16_t SPI_FIFOSize) +{ + /* Clear DFF bit */ + SPIx->FIFONUM &= (uint16_t)~SPI_TX_FIF0NUM_7; + /* Set new DFF bit value */ + SPIx->FIFONUM |= SPI_FIFOSize; +} + +uint16_t SPI_GetFIFOLevel(SPI_Module* SPIx) +{ + return SPIx->FIFONUM; +} +/** +*\*\name SPI_RX_FIFO_SET. +*\*\fun In FIFIO mode, write the data in the receiving FIFO. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param Data \* Data to be transmitted *\ +*\*\return none. +**/ +void SPI_RX_FIFO_SET(SPI_Module* SPIx, uint16_t Data) +{ + /* Write in the RX_FIFO register the data to be sent */ + SPIx->RX_FIFO = Data; +} + +/** +*\*\name SPI_RX_FIFO_GET. +*\*\fun In FIFIO mode, read the data in the receiving FIFO. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\return Receive data in FIFO. +**/ +uint16_t SPI_RX_FIFO_GET(const SPI_Module* SPIx) +{ + /* Return the data in the receive FIFO */ + return SPIx->RX_FIFO; +} + +/** +*\*\name SPI_RX_FIFO_CNT_GET. +*\*\fun In FIFO mode, the current number of valid FIFOs. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\return Current effective number of FIFOs. +**/ +uint16_t SPI_RX_FIFO_CNT_GET(const SPI_Module* SPIx) +{ + /* Return The RX Data Count in FIFO*/ + return ((uint8_t)((SPIx->FIFOCNT & 0x00F0U) >> 4)); +} + +/** +*\*\name SPI_TX_FIFO_CNT_GET. +*\*\fun In FIFO mode, the current number of valid FIFOs. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\return Current effective number of FIFOs. +**/ +uint16_t SPI_TX_FIFO_CNT_GET(const SPI_Module* SPIx) +{ + /* Return the TX Data Count in FIFO*/ + return ((uint8_t)(SPIx->FIFOCNT & 0x000FU)); +} + +/** +*\*\name SPI_TRANSNUM_SET. +*\*\fun When in FIFO mode with CRC function, +*\*\ the user needs to write the number of data to be transmitted in advance. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\param Data \* Data to be transmitted *\ +*\*\return none. +**/ +void SPI_TRANSNUM_SET(SPI_Module* SPIx, uint16_t Data) +{ + /* Write in the TRANSNUM register the data to be sent */ + SPIx->TRANSNUM = Data; +} + +/** +*\*\name SPI_TRANSNUM_GET. +*\*\fun When in FIFO mode with CRC function, +*\*\ the user write the number of data to be transmitted in advance. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\ - 2 or 3 in I2S mode +*\*\return The number of data transferred. +**/ +uint16_t SPI_TRANSNUM_GET(const SPI_Module* SPIx) +{ + /* Return the number of data transferred. */ + return SPIx->TRANSNUM; +} + +/** +*\*\name SPI_DELAYTIME_SET. +*\*\fun SPI master clock delay time configuration. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\param Data \* Data to be transmitted *\ +*\*\return none. +**/ +void SPI_DELAYTIME_SET(SPI_Module* SPIx, uint16_t Data) +{ + /* Write in the CR3 register the data to be sent */ + SPIx->CR3 = Data; +} + +/** +*\*\name SPI_DELAYTIME_GET. +*\*\fun Get SPI master clock delay time. +*\*\param SPIx : +*\*\ - 1, 2, 3, 4, 5 or 6 in SPI mode +*\*\return The clock delay time. +**/ +uint16_t SPI_DELAYTIME_GET(const SPI_Module* SPIx) +{ + /* Return clock delay time. */ + return SPIx->CR3; +} + + +/** +*\*\name SPI_Mode_Select. +*\*\fun Select working on SPI mode or I2S mode. +*\*\param SPIx : +*\*\ - SPI1 +*\*\ - SPI2 +*\*\ - SPI3 +*\*\ - SPI4 +*\*\return none +*\*\note Must be used with I2S or SPI OFF. +**/ +void SPIModeSelect(SPI_Module* SPIx) +{ + /* Select the mode */ + SPIx->SPI_I2S_CFGR &= (~SPI_I2SCFG_I2SMOD); +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_tim.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_tim.c new file mode 100644 index 0000000000..94d31ff528 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_tim.c @@ -0,0 +1,6437 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_tim.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ + +#include "n32h76x_78x_tim.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name TIM_DeInit +*\*\fun Deinitializes the TIMx registers. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\return none +**/ +void TIM_DeInit(TIM_Module* TIMx) +{ + if (TIMx == ATIM1) + { + RCC_EnableAPB2PeriphReset1(RCC_APB2_PERIPHRST_ATIM1); + } + else if (TIMx == ATIM2) + { + RCC_EnableAPB2PeriphReset1(RCC_APB2_PERIPHRST_ATIM2); + } + else if (TIMx == ATIM3) + { + RCC_EnableAPB5PeriphReset1(RCC_APB5_PERIPHRST_ATIM3); + } + else if (TIMx == ATIM4) + { + RCC_EnableAPB5PeriphReset1(RCC_APB5_PERIPHRST_ATIM4); + } + else if (TIMx == GTIMA1) + { + RCC_EnableAPB2PeriphReset1(RCC_APB2_PERIPHRST_GTIMA1); + } + else if (TIMx == GTIMA2) + { + RCC_EnableAPB2PeriphReset1(RCC_APB2_PERIPHRST_GTIMA2); + } + else if (TIMx == GTIMA3) + { + RCC_EnableAPB2PeriphReset1(RCC_APB2_PERIPHRST_GTIMA3); + } + else if (TIMx == GTIMA4) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_GTIMA4); + } + else if (TIMx == GTIMA5) + { + RCC_EnableAPB1PeriphReset2(RCC_APB1_PERIPHRST_GTIMA5); + } + else if (TIMx == GTIMA6) + { + RCC_EnableAPB1PeriphReset2(RCC_APB1_PERIPHRST_GTIMA6); + } + else if (TIMx == GTIMA7) + { + RCC_EnableAPB1PeriphReset2(RCC_APB1_PERIPHRST_GTIMA7); + } + else if (TIMx == GTIMB1) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_GTIMB1); + } + else if (TIMx == GTIMB2) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_GTIMB2); + } + else if (TIMx == GTIMB3) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_GTIMB3); + } + else if (TIMx == BTIM1) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_BTIM1); + } + else if (TIMx == BTIM2) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_BTIM2); + } + else if (TIMx == BTIM3) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_BTIM3); + } + else if (TIMx == BTIM4) + { + RCC_EnableAPB1PeriphReset1(RCC_APB1_PERIPHRST_BTIM4); + } + else + { + + } +} + +/** +*\*\name TIM_InitTimeBase +*\*\fun Initializes the TIMx time base unit. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_TimeBaseInitStruct: refer to the definition of TIM_TimeBaseInitType +*\*\ - Prescaler +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - CounterMode +*\*\ * TIM_CNT_MODE_UP +*\*\ * TIM_CNT_MODE_DOWN +*\*\ * TIM_CNT_MODE_CENTER_ALIGN1 +*\*\ * TIM_CNT_MODE_CENTER_ALIGN2 +*\*\ * TIM_CNT_MODE_CENTER_ALIGN3 +*\*\ - Period +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - ClkDiv +*\*\ * TIM_CLK_DIV1 +*\*\ * TIM_CLK_DIV2 +*\*\ * TIM_CLK_DIV4 +*\*\ - RepetCnt +*\*\ * 0x00 ~ 0xFF +*\*\ - CapCh1Sel +*\*\ * TIM_CAPCH1SEL_0 +*\*\ * TIM_CAPCH1SEL_1 +*\*\ * TIM_CAPCH1SEL_2 +*\*\ * TIM_CAPCH1SEL_3 +*\*\ * TIM_CAPCH1SEL_4 +*\*\ * TIM_CAPCH1SEL_5 +*\*\ * TIM_CAPCH1SEL_6 +*\*\ * TIM_CAPCH1SEL_7 +*\*\ - CapCh2Sel +*\*\ * TIM_CAPCH2SEL_0 +*\*\ * TIM_CAPCH2SEL_1 +*\*\ * TIM_CAPCH2SEL_2 +*\*\ * TIM_CAPCH2SEL_3 +*\*\ * TIM_CAPCH2SEL_4 +*\*\ * TIM_CAPCH2SEL_TIMXCAPLSE +*\*\ - CapCh3Sel +*\*\ * TIM_CAPCH3SEL_0 +*\*\ * TIM_CAPCH3SEL_1 +*\*\ * TIM_CAPCH3SEL_TIMXCAPLSI +*\*\ - CapCh4Sel +*\*\ * TIM_CAPCH4SEL_0 +*\*\ * TIM_CAPCH4SEL_1 +*\*\ * TIM_CAPCH4SEL_2 +*\*\ * TIM_CAPCH4SEL_TIMXCAPHSEDIV128 +*\*\ - EtrOrClr +*\*\ * TIM_ETRSEL +*\*\ * TIM_CLRSEL +*\*\ - CapEtrClrSel +*\*\ * TIM_CAPETRSEL_0 +*\*\ * TIM_CAPETRSEL_1 +*\*\ * TIM_CAPETRSEL_2 +*\*\ * TIM_CAPETRSEL_3 +*\*\ * TIM_CAPETRSEL_4 +*\*\ * TIM_CAPETRSEL_5 +*\*\ * TIM_CAPETRSEL_6 +*\*\ * TIM_CAPETRSEL_7 +*\*\ * TIM_CAPETRSEL_8 +*\*\ * TIM_CAPETRSEL_10 +*\*\ * TIM_CAPETRSEL_11 +*\*\ * TIM_CAPETRSEL_12 +*\*\ * TIM_CAPETRSEL_13 +*\*\ * TIM_OCCLRSEL_0 +*\*\ * TIM_OCCLRSEL_1 +*\*\ * TIM_OCCLRSEL_2 +*\*\ * TIM_OCCLRSEL_3 +*\*\ * TIM_OCCLRSEL_4 +*\*\ * TIM_OCCLRSEL_5 +*\*\ * TIM_OCCLRSEL_6 +*\*\ * TIM_OCCLRSEL_7 +*\*\return none +**/ +void TIM_InitTimeBase(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + uint32_t tmpctrl1, tmpinsel; + tmpctrl1 = TIMx->CTRL1; + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Select the Counter Mode */ + tmpctrl1 &= (uint32_t)(~(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)); + tmpctrl1 |= (uint32_t)TIM_TimeBaseInitStruct->CounterMode; + } + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Set the clock division */ + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_CLKD); + tmpctrl1 |= (uint32_t)TIM_TimeBaseInitStruct->ClkDiv; + } + + TIMx->CTRL1 = tmpctrl1; + + /* Set the Autoreload value */ + TIMx->AR = TIM_TimeBaseInitStruct->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->Prescaler; + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Set the Repetition Counter value */ + TIMx->REPCNT = TIM_TimeBaseInitStruct->RepetCnt; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EVTGEN = TIM_PSC_RELOAD_MODE_IMMEDIATE; + + /* Channel 1/2/3/4 & OCxclr select capture in */ + tmpctrl1 = TIMx->CTRL1; + tmpinsel = TIMx->INSEL; + + /* Channel 1 select capture in */ + if (((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) && (TIMx != GTIMA1)) + { + /* Channel 1 select capture in */ + tmpinsel &= (uint32_t)(~TIM_INSEL_TI1S); + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh1Sel; + } + else if (TIMx == GTIMA1) + { + /* Channel 1 select capture in */ + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_C1SEL); + tmpinsel &= (uint32_t)(~TIM_INSEL_TI1S); + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh1Sel; + } + else + { + } + + /* Channel 2 select capture in */ + if (((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) && (TIMx != GTIMA1)) + { + /* Channel 2 select capture in */ + tmpinsel &= (uint32_t)(~TIM_INSEL_TI2S); + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh2Sel; + } + else if (TIMx == GTIMA1) + { + /* Channel 2 select capture in */ + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_C2SEL); + tmpinsel &= (uint32_t)(~TIM_INSEL_TI2S); + + if ((TIM_TimeBaseInitStruct->CapCh2Sel != TIM_CAPCH2SEL_TIMXCAPLSE)) + { + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh2Sel; + } + else /* TIM_CAPCH2SEL_TIMXCAPLSE */ + { + tmpctrl1 |= (uint32_t)TIM_TimeBaseInitStruct->CapCh2Sel; + } + } + else + { + } + + /* Channel 3 select capture in */ + if (((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) && (TIMx != GTIMA1)) + { + /* Channel 3 select capture in */ + tmpinsel &= (uint32_t)(~TIM_INSEL_TI3S); + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh3Sel; + } + else if (TIMx == GTIMA1) + { + /* Channel 3 select capture in */ + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_C3SEL); + tmpinsel &= (uint32_t)(~TIM_INSEL_TI3S); + + if ((TIM_TimeBaseInitStruct->CapCh3Sel != TIM_CAPCH3SEL_TIMXCAPLSI)) + { + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh3Sel; + } + else /* TIM_CAPCH3SEL_TIMXCAPLSI */ + { + tmpctrl1 |= (uint32_t)TIM_TimeBaseInitStruct->CapCh3Sel; + } + } + else + { + } + + /* Channel 4 select capture in */ + if (((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) && (TIMx != GTIMA1)) + { + /* Channel 4 select capture in */ + tmpinsel &= (uint32_t)(~TIM_INSEL_TI4S); + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh4Sel; + } + else if (TIMx == GTIMA1) + { + /* Channel 4 select capture in */ + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_C4SEL); + tmpinsel &= (uint32_t)(~TIM_INSEL_TI4S); + + if ((TIM_TimeBaseInitStruct->CapCh4Sel != TIM_CAPCH4SEL_TIMXCAPHSEDIV128)) + { + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapCh4Sel; + } + else /* TIM_CAPCH4SEL_TIMXCAPHSEDIV128 */ + { + tmpctrl1 |= (uint32_t)TIM_TimeBaseInitStruct->CapCh4Sel; + } + } + else + { + } + + /* CLR or ETR select capture in */ + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_CLRSEL); + tmpinsel &= (uint32_t)(~TIM_INSEL_ETRS); + tmpinsel &= (uint32_t)(~TIM_INSEL_CLRS); + + if ((TIM_TimeBaseInitStruct->EtrOrClr) == 0) + { + /* ETR select capture in */ + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapEtrClrSel; + } + else + { + /* CLR select capture in */ + tmpctrl1 |= (uint32_t)TIM_CTRL1_CLRSEL; + tmpinsel |= (uint32_t)TIM_TimeBaseInitStruct->CapEtrClrSel; + } + } + + TIMx->CTRL1 = tmpctrl1; + TIMx->INSEL = tmpinsel; + +} + +/** +*\*\name TIM_InitOc1 +*\*\fun Initializes the TIMx Channel 1. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ * TIM_OCMODE_OPMOD_RETRIG1 +*\*\ * TIM_OCMODE_OPMOD_RETRIG2 +*\*\ * TIM_OCMODE_COMBI_PWM1 +*\*\ * TIM_OCMODE_COMBI_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOc1(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint32_t tmpccmodx; + uint32_t tmpccen, tmpctrl2; + + /* Disable the Channel 1: Reset the CC1EN Bit */ + TIMx->CCEN &= (uint32_t)(~TIM_CCEN_CC1EN); + /* Get the TIMx_CCEN register value */ + tmpccen = TIMx->CCEN; + /* Get the TIMx_CTRL2 register value */ + tmpctrl2 = TIMx->CTRL2; + /* Get the TIMx_CCMOD1 register value */ + tmpccmodx = TIMx->CCMOD1; + + /* Reset the Output Compare Mode Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC1MD); + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC1MD_3); + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_CC1SEL); + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode); + + /* Reset the Output Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC1P); + /* Set the Output Compare Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCPolarity); + /* Set the Output State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputState); + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Reset the Output N Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC1NP); + /* Set the Output N Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCNPolarity); + /* Reset the Output N State */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC1NEN); + /* Set the Output N State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputNState); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI1); + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI1N); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState); + /* Set the Output N Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCNIdleState); + } + + /* Write to TIMx_CTRL2 */ + TIMx->CTRL2 = tmpctrl2; + + /* Write to TIMx_CCMOD1 */ + TIMx->CCMOD1 = tmpccmodx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT1 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx_CCEN */ + TIMx->CCEN = tmpccen; + +} + +/** +*\*\name TIM_InitOc2 +*\*\fun Initializes the TIMx Channel 2. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ * TIM_OCMODE_OPMOD_RETRIG1 +*\*\ * TIM_OCMODE_OPMOD_RETRIG2 +*\*\ * TIM_OCMODE_COMBI_PWM1 +*\*\ * TIM_OCMODE_COMBI_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOc2(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmpctrl2; + + /* Disable the Channel 2: Reset the CC2EN Bit */ + TIMx->CCEN &= (uint32_t)(~TIM_CCEN_CC2EN); + + /* Get the TIMx_CCEN register value */ + tmpccen = TIMx->CCEN; + /* Get the TIMx_CTRL2 register value */ + tmpctrl2 = TIMx->CTRL2; + + /* Get the TIMx_CCMOD1 register value */ + tmpccmodx = TIMx->CCMOD1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC2MD); + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC2MD_3); + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_CC2SEL); + + if (((TIM_OCInitStruct->OCMode) == TIM_OCMODE_OPMOD_RETRIG1) || ((TIM_OCInitStruct->OCMode) == TIM_OCMODE_OPMOD_RETRIG2) || \ + ((TIM_OCInitStruct->OCMode) == TIM_OCMODE_COMBI_PWM1) || ((TIM_OCInitStruct->OCMode) == TIM_OCMODE_COMBI_PWM2)) + { + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode << 8); + tmpccmodx |= (uint32_t)TIM_CCMOD1_OC2MD_3; + } + else + { + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode << 8); + } + + /* Reset the Output Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC2P); + /* Set the Output Compare Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCPolarity << 4); + /* Set the Output State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputState << 4); + + if (IS_ATIM1_4_DEVICE(TIMx)) + { + /* Reset the Output N Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC2NP); + /* Set the Output N Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCNPolarity << 4); + /* Reset the Output N State */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC2NEN); + /* Set the Output N State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI2); + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI2N); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 2); + /* Set the Output N Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCNIdleState << 2); + } + + if (IS_GTIMB1_3_DEVICE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI2); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 2); + } + + /* Write to TIMx_CTRL2 */ + TIMx->CTRL2 = tmpctrl2; + + /* Write to TIMx_CCMOD1 */ + TIMx->CCMOD1 = tmpccmodx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT2 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx_CCEN */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_InitOc3 +*\*\fun Initializes the TIMx Channel 3. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ * TIM_OCMODE_OPMOD_RETRIG1 +*\*\ * TIM_OCMODE_OPMOD_RETRIG2 +*\*\ * TIM_OCMODE_COMBI_PWM1 +*\*\ * TIM_OCMODE_COMBI_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOc3(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmpctrl2 ; + + /* Disable the Channel 3: Reset the CC3EN Bit */ + TIMx->CCEN &= (uint32_t)(~TIM_CCEN_CC3EN); + + /* Get the TIMx_CCEN register value */ + tmpccen = TIMx->CCEN; + + /* Get the TIMx_CTRL2 register value */ + tmpctrl2 = TIMx->CTRL2; + + /* Get the TIMx_CCMOD2 register value */ + tmpccmodx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC3MD); + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC3MD_3); + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_CC3SEL); + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode); + + /* Reset the Output Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC3P); + /* Set the Output Compare Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCPolarity << 8); + /* Set the Output State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputState << 8); + + if (IS_ATIM1_4_DEVICE(TIMx)) + { + /* Reset the Output N Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC3NP); + /* Set the Output N Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCNPolarity << 8); + /* Reset the Output N State */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC3NEN); + /* Set the Output N State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputNState << 8); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI3); + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI3N); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 4); + /* Set the Output N Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCNIdleState << 4); + } + + if (IS_GTIMB1_3_DEVICE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI3); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 4); + } + + /* Write to TIMx_CTRL2 */ + TIMx->CTRL2 = tmpctrl2; + + /* Write to TIMx_CCMOD2 */ + TIMx->CCMOD2 = tmpccmodx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT3 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_InitOc4 +*\*\fun Initializes the TIMx Channel 4. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ * TIM_OCMODE_OPMOD_RETRIG1 +*\*\ * TIM_OCMODE_OPMOD_RETRIG2 +*\*\ * TIM_OCMODE_COMBI_PWM1 +*\*\ * TIM_OCMODE_COMBI_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOc4(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmpctrl2 ; + + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t)(~TIM_CCEN_CC4EN); + + /* Get the TIMx_CCEN register value */ + tmpccen = TIMx->CCEN; + + /* Get the TIMx_CTRL2 register value */ + tmpctrl2 = TIMx->CTRL2; + + /* Get the TIMx_CCMOD2 register value */ + tmpccmodx = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC4MD); + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC4MD_3); + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_CC4SEL); + + if (((TIM_OCInitStruct->OCMode) == TIM_OCMODE_OPMOD_RETRIG1) || ((TIM_OCInitStruct->OCMode) == TIM_OCMODE_OPMOD_RETRIG2) || \ + ((TIM_OCInitStruct->OCMode) == TIM_OCMODE_COMBI_PWM1) || ((TIM_OCInitStruct->OCMode) == TIM_OCMODE_COMBI_PWM2)) + { + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode << 8); + tmpccmodx |= (uint32_t)TIM_CCMOD2_OC4MD_3; + } + else + { + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode << 8); + } + + /* Reset the Output Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC4P); + /* Set the Output Compare Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCPolarity << 12); + /* Set the Output State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputState << 12); + + if ((IS_ATIM1_4_DEVICE(TIMx))) + { + /* Reset the Output N Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC4NP) ; + /* Set the Output N Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCNPolarity << 12); + /* Reset the Output N State */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC4NEN); + /* Set the Output N State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputNState << 12); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI4); + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI4N); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 6); + /* Set the Output N Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCNIdleState << 6); + } + + if (IS_GTIMB1_3_DEVICE(TIMx)) + { + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI4); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 6); + } + + /* Write to TIMx_CTRL2 */ + TIMx->CTRL2 = tmpctrl2; + + /* Write to TIMx_CCMOD2 */ + TIMx->CCMOD2 = tmpccmodx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT4 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx_CCEN */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_InitOc5 +*\*\fun Initializes the TIMx Channel 5. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOc5(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmpctrl2 ; + + /* Disable the Channel 5: Reset the CC5EN Bit */ + TIMx->CCEN &= (uint32_t)(~TIM_CCEN_CC5EN); + + /* Get the TIMx_CCEN register value */ + tmpccen = TIMx->CCEN; + + /* Get the TIMx_CTRL2 register value */ + tmpctrl2 = TIMx->CTRL2; + + /* Get the TIMx_CCMOD3 register value */ + tmpccmodx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC5MD); + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode); + + /* Reset the Output Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC5P); + /* Set the Output Compare Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCPolarity << 16); + /* Set the Output State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputState << 16); + + /* Reset the Output Compare IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI5); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 8); + + /* Write to TIMx CR2 */ + TIMx->CTRL2 = tmpctrl2; + + /* Write to TIMx_CCMOD3 */ + TIMx->CCMOD3 = tmpccmodx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT5 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_InitOc6 +*\*\fun Initializes the TIMx Channel 6. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOc6(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmpctrl2 ; + + /* Disable the Channel 6: Reset the CC6EN Bit */ + TIMx->CCEN &= (uint32_t)(~TIM_CCEN_CC6EN); + + /* Get the TIMx_CCEN register value */ + tmpccen = TIMx->CCEN; + + /* Get the TIMx_CTRL2 register value */ + tmpctrl2 = TIMx->CTRL2; + + /* Get the TIMx_CCMOD3 register value */ + tmpccmodx = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC6MD); + /* Select the Output Compare Mode */ + tmpccmodx |= (uint32_t)(TIM_OCInitStruct->OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccen &= (uint32_t)(~TIM_CCEN_CC6P); + /* Set the Output Compare Polarity */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OCPolarity << 20); + /* Set the Output State */ + tmpccen |= (uint32_t)(TIM_OCInitStruct->OutputState << 20); + + /* Reset the Output Compare IDLE State */ + tmpctrl2 &= (uint32_t)(~TIM_CTRL2_OI6); + /* Set the Output Idle state */ + tmpctrl2 |= (uint32_t)(TIM_OCInitStruct->OCIdleState << 10); + + /* Write to TIMx CR2 */ + TIMx->CTRL2 = tmpctrl2; + + /* Write to TIMx_CCMOD3 */ + TIMx->CCMOD3 = tmpccmodx; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT6 = TIM_OCInitStruct->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ICInit +*\*\fun Initializes the TIM peripheral according to the specified +*\*\ parameters in the TIM_ICInitStruct. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ICInitStruct: refer to the definition of TIM_ICInitType +*\*\ - Channel +*\*\ * TIM_CH_1 +*\*\ * TIM_CH_2 +*\*\ * TIM_CH_3 +*\*\ * TIM_CH_4 +*\*\ - ICPolarity +*\*\ * TIM_IC_POLARITY_RISING +*\*\ * TIM_IC_POLARITY_FALLING +*\*\ - ICSelection +*\*\ * TIM_IC_SELECTION_DIRECTTI +*\*\ * TIM_IC_SELECTION_INDIRECTTI +*\*\ * TIM_IC_SELECTION_TRC +*\*\ - ICPrescaler +*\*\ * TIM_IC_PSC_DIV1 +*\*\ * TIM_IC_PSC_DIV2 +*\*\ * TIM_IC_PSC_DIV4 +*\*\ * TIM_IC_PSC_DIV8 +*\*\ - ICFilter +*\*\ * ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_ICInit(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->ICPolarity, TIM_ICInitStruct->ICSelection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_2) + { + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->ICPolarity, TIM_ICInitStruct->ICSelection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_3) + { + /* TI3 Configuration */ + ConfigTI3(TIMx, TIM_ICInitStruct->ICPolarity, TIM_ICInitStruct->ICSelection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap3Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_4) + { + /* TI4 Configuration */ + ConfigTI4(TIMx, TIM_ICInitStruct->ICPolarity, TIM_ICInitStruct->ICSelection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap4Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + } + else + { + } +} + +/** +*\*\name TIM_ConfigPwmIc +*\*\fun Configures the TIM peripheral according to the specified +*\*\ parameters in the TIM_ICInitStruct to measure an external PWM signal. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ICInitStruct: refer to the definition of TIM_ICInitType +*\*\ - Channel +*\*\ * TIM_CH_1 +*\*\ * TIM_CH_2 +*\*\ - ICPolarity +*\*\ * TIM_IC_POLARITY_RISING +*\*\ * TIM_IC_POLARITY_FALLING +*\*\ - ICSelection +*\*\ * TIM_IC_SELECTION_DIRECTTI +*\*\ * TIM_IC_SELECTION_INDIRECTTI +*\*\ - ICPrescaler +*\*\ * TIM_IC_PSC_DIV1 +*\*\ * TIM_IC_PSC_DIV2 +*\*\ * TIM_IC_PSC_DIV4 +*\*\ * TIM_IC_PSC_DIV8 +*\*\ - ICFilter +*\*\ * ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_ConfigPwmIc(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + uint32_t icoppositepolarity ; + uint32_t icoppositeselection ; + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->ICPolarity == TIM_IC_POLARITY_RISING) + { + icoppositepolarity = TIM_IC_POLARITY_FALLING; + } + else + { + icoppositepolarity = TIM_IC_POLARITY_RISING; + } + + /* Select the Opposite Input */ + if (TIM_ICInitStruct->ICSelection == TIM_IC_SELECTION_DIRECTTI) + { + icoppositeselection = TIM_IC_SELECTION_INDIRECTTI; + } + else + { + icoppositeselection = TIM_IC_SELECTION_DIRECTTI; + } + + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + ConfigTI1(TIMx, TIM_ICInitStruct->ICPolarity, TIM_ICInitStruct->ICSelection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + /* TI2 Configuration */ + ConfigTI2(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + } + else + { + /* TI2 Configuration */ + ConfigTI2(TIMx, TIM_ICInitStruct->ICPolarity, TIM_ICInitStruct->ICSelection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap2Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + /* TI1 Configuration */ + ConfigTI1(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetInCap1Prescaler(TIMx, TIM_ICInitStruct->ICPrescaler); + } +} + +/** +*\*\name TIM_ConfigBkdt +*\*\fun Configures the: Break feature, dead time, Lock level, the OSSI, +*\*\ the OSSR State and the AOE(automatic output enable). +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_BDTRInitStruct: refer to the definition of TIM_BDTRInitType +*\*\ - OSSRState +*\*\ * TIM_OSSR_STATE_ENABLE +*\*\ * TIM_OSSR_STATE_DISABLE +*\*\ - OSSIState +*\*\ * TIM_OSSI_STATE_ENABLE +*\*\ * TIM_OSSI_STATE_DISABLE +*\*\ - LOCKLevel +*\*\ * TIM_LOCK_LEVEL_OFF +*\*\ * TIM_LOCK_LEVEL_1 +*\*\ * TIM_LOCK_LEVEL_2 +*\*\ * TIM_LOCK_LEVEL_3 +*\*\ - DeadTime +*\*\ * DeadTime can be a number between 0x00 and 0xFF +*\*\ - Break +*\*\ * TIM_BREAK_IN_ENABLE +*\*\ * TIM_BREAK_IN_DISABLE +*\*\ - BreakPolarity +*\*\ * TIM_BREAK_POLARITY_LOW +*\*\ * TIM_BREAK_POLARITY_HIGH +*\*\ - Bidirection +*\*\ * TIM_BREAK_BID_ENABLE +*\*\ * TIM_BREAK_BID_DISABLE +*\*\ - AutomaticOutput +*\*\ * TIM_AUTO_OUTPUT_ENABLE +*\*\ * TIM_AUTO_OUTPUT_DISABLE +*\*\ - Break2 +*\*\ * TIM_BREAK2_IN_ENABLE +*\*\ * TIM_BREAK2_IN_DISABLE +*\*\ - Break2Polarity +*\*\ * TIM_BREAK2_POLARITY_LOW +*\*\ * TIM_BREAK2_POLARITY_HIGH +*\*\ - Bidirection2 +*\*\ * TIM_BREAK2_BID_ENABLE +*\*\ * TIM_BREAK2_BID_DISABLE +*\*\return none +**/ +void TIM_ConfigBkdt(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + uint32_t tmpbkdt; + + /* Set the Lock level, the OSSR State, the OSSI State, + the dead time value and the Automatic Output Enable Bit */ + tmpbkdt = TIMx->BKDT; + tmpbkdt &= (uint32_t)(~(TIM_BKDT_OSSR | TIM_BKDT_OSSI | TIM_BKDT_LCKCFG | TIM_BKDT_DTGN | TIM_BKDT_AOEN)); + tmpbkdt |= (uint32_t)(TIM_BDTRInitStruct->OSSRState | TIM_BDTRInitStruct->OSSIState | TIM_BDTRInitStruct->LOCKLevel | \ + TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->AutomaticOutput); + + /* Set the Break enable Bit and the Ploarity */ + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + tmpbkdt &= (uint32_t)(~(TIM_BKDT_BKEN | TIM_BKDT_BKP | TIM_BKDT_BRKBID)); + tmpbkdt |= (uint32_t)(TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity | TIM_BDTRInitStruct->Bidirection); + } + + /* Set the Break2 enable Bit and the Ploarity */ + if (IS_ATIM1_4_DEVICE(TIMx)) + { + tmpbkdt &= (uint32_t)(~(TIM_BKDT_BK2EN | TIM_BKDT_BK2P | TIM_BKDT_BRK2BID)); + tmpbkdt |= (uint32_t)(TIM_BDTRInitStruct->Break2 | TIM_BDTRInitStruct->Break2Polarity | TIM_BDTRInitStruct->Bidirection2); + } + + TIMx->BKDT = tmpbkdt; +} + +/** +*\*\name TIM_BreakFiltConfig +*\*\fun Config the filter of break input. +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_FiltInitStruct: +*\*\ - refer to the definition of TIM_FiltInitType +*\*\return none +**/ +void TIM_BreakFiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct) +{ + uint32_t tempbkfr; + + tempbkfr = TIMx->BKFR; + + tempbkfr &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_BKFR_THRESH)) & + ((uint32_t) ~((uint32_t)TIM_BKFR_WSIZE)) & + ((uint32_t) ~((uint32_t)TIM_BKFR_SFPSC))); + + tempbkfr |= (uint32_t)((TIM_FiltInitStruct->ThreshHold << (uint32_t)(0x18)) | + (TIM_FiltInitStruct->WindowSize << (uint32_t)(0x11)) | + (TIM_FiltInitStruct->Prescaler)); + TIMx->BKFR = tempbkfr; + + +} + +/** +*\*\name TIM_Break2FiltConfig +*\*\fun Config the filter of break2 input. +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_FiltInitStruct: +*\*\ - refer to the definition of TIM_FiltInitType +*\*\return none +**/ +void TIM_Break2FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct) +{ + uint32_t tempbkfr2; + + tempbkfr2 = TIMx->BKFR2; + + tempbkfr2 &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_BKFR2_THRESH)) & + ((uint32_t) ~((uint32_t)TIM_BKFR2_WSIZE)) & + ((uint32_t) ~((uint32_t)TIM_BKFR2_SFPSC))); + + tempbkfr2 |= (uint32_t)((TIM_FiltInitStruct->ThreshHold << (uint32_t)(0x18)) | + (TIM_FiltInitStruct->WindowSize << (uint32_t)(0x11)) | + (TIM_FiltInitStruct->Prescaler)); + TIMx->BKFR2 = tempbkfr2; + +} + +/** +*\*\name TIM_BreakFiltEnable +*\*\fun Enable or disable the filter of break input. +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_BreakFiltEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the filter of break input */ + TIMx->BKFR |= (uint32_t)TIM_BKFR_FILTEN; + } + else + { + /* Disable the filter of break input */ + TIMx->BKFR &= (uint32_t)(~TIM_BKFR_FILTEN); + } +} + +/** +*\*\name TIM_Break2FiltEnable +*\*\fun Enable or disable the filter of break2 input. +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_Break2FiltEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the filter of break2 input */ + TIMx->BKFR2 |= (uint32_t)TIM_BKFR2_FILTEN; + } + else + { + /* Disable the filter of break2 input */ + TIMx->BKFR2 &= (uint32_t)(~TIM_BKFR2_FILTEN); + } +} + +/** +*\*\name TIM_BreakInputSourceEnable +*\*\fun Enable or disable the break input source , and set the polarity of the break input source. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Source +*\*\ - TIM_BREAK_LOCKUP +*\*\ - TIM_BREAK_PVD +*\*\ - TIM_BREAK_SMPAR +*\*\ - TIM_BREAK_FLECC +*\*\ - TIM_BREAK_SMECC +*\*\ - TIM_BREAK_IOM +*\*\ - TIM_BREAK_COMP1 +*\*\ - TIM_BREAK_COMP2 +*\*\ - TIM_BREAK_COMP3 +*\*\ - TIM_BREAK_DSMU0 +*\*\ - TIM_BREAK_DSMU1 +*\*\ - TIM_BREAK_DSMU2 +*\*\ - TIM_BREAK_DSMU3 +*\*\param Polarity +*\*\ - TIM_BREAK_SOURCE_POLARITY_INVERT +*\*\ - TIM_BREAK_SOURCE_POLARITY_NONINVERT +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_BreakInputSourceEnable(TIM_Module* TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd) +{ + uint32_t tempctrl1; + uint32_t tempaf1; + tempctrl1 = TIMx->CTRL1; + tempaf1 = TIMx->AF1; + + if (Cmd != DISABLE) + { + if (IS_SYS_BREAK(Source)) + { + tempctrl1 |= (uint32_t)(Source); + } + else + { + /* Enable break input source */ + tempaf1 |= (uint32_t)(Source); + /* Set break input source polarity */ + tempaf1 &= (uint32_t)(~((Source & 0x1F) << 9)); + tempaf1 |= (uint32_t)(Polarity & ((Source & 0x1F) << 9)); + } + + } + else + { + if (IS_SYS_BREAK(Source)) + { + tempctrl1 &= (uint32_t)(~Source); + } + else + { + /* Disable break input source */ + tempaf1 &= (uint32_t)(~Source); + /* Set break input source polarity */ + tempaf1 &= (uint32_t)(~((Source & 0x1F) << 9)); + tempaf1 |= (uint32_t)(Polarity & ((Source & 0x1F) << 9)); + } + } + + TIMx->CTRL1 = tempctrl1; + TIMx->AF1 = tempaf1; +} + +/** +*\*\name TIM_Break2InputSourceEnable +*\*\fun Enable or disable the break2 input source , and set the polarity of the break2 input source. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param Source +*\*\ - TIM_BREAK2_IOM +*\*\ - TIM_BREAK2_COMP1 +*\*\ - TIM_BREAK2_COMP2 +*\*\ - TIM_BREAK2_COMP3 +*\*\ - TIM_BREAK2_COMP4 +*\*\ - TIM_BREAK2_DSMU0 +*\*\ - TIM_BREAK2_DSMU1 +*\*\ - TIM_BREAK2_DSMU2 +*\*\ - TIM_BREAK2_DSMU3 +*\*\param Polarity +*\*\ - TIM_BREAK2_SOURCE_POLARITY_INVERT +*\*\ - TIM_BREAK2_SOURCE_POLARITY_NONINVERT +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_Break2InputSourceEnable(TIM_Module* TIMx, uint32_t Source, uint32_t Polarity, FunctionalState Cmd) +{ + uint32_t tempaf2; + tempaf2 = TIMx->AF2; + + if (Cmd != DISABLE) + { + /* Enable break2 input source */ + tempaf2 |= (uint32_t)(Source); + /* Set break2 input source polarity */ + tempaf2 &= (uint32_t)(~((Source & 0x1F) << 9)); + tempaf2 |= (uint32_t)(Polarity & ((Source & 0x1F) << 9)); + } + else + { + /* Disable break2 input source */ + tempaf2 &= (uint32_t)(~Source); + /* Set break2 input source polarity */ + tempaf2 &= (uint32_t)(~((Source & 0x1F) << 9)); + tempaf2 |= (uint32_t)(Polarity & ((Source & 0x1F) << 9)); + } + + TIMx->AF2 = tempaf2; +} + +/** +*\*\name TIM_BidirectionDisarm +*\*\fun Disarm bidirection of break. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return none +**/ +void TIM_BidirectionDisarm(TIM_Module* TIMx) +{ + TIMx->BKDT |= (uint32_t)TIM_BKDT_BRKDSRM; +} + +/** +*\*\name TIM_BidirectionRearm +*\*\fun Rearm bidirection of break. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return none +**/ +void TIM_BidirectionRearm(TIM_Module* TIMx) +{ + TIMx->BKDT &= (uint32_t)(~TIM_BKDT_BRKDSRM); +} + +/** +*\*\name TIM_Bidirection2Disarm +*\*\fun Disarm bidirection of break2. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return none +**/ +void TIM_Bidirection2Disarm(TIM_Module* TIMx) +{ + TIMx->BKDT |= (uint32_t)TIM_BKDT_BRK2DSRM; +} + +/** +*\*\name TIM_Bidirection2Rearm +*\*\fun Rearm bidirection of break2. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return none +**/ +void TIM_Bidirection2Rearm(TIM_Module* TIMx) +{ + TIMx->BKDT &= (uint32_t)(~TIM_BKDT_BRK2DSRM); +} + +/** +*\*\name TIM_InitTimBaseStruct +*\*\fun Fills each TIM_TimeBaseInitStruct member with its default value. +*\*\param TIM_TimeBaseInitStruct: refer to the definition of TIM_TimeBaseInitType +*\*\ - Prescaler +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - CounterMode +*\*\ * TIM_CNT_MODE_UP +*\*\ * TIM_CNT_MODE_DOWN +*\*\ * TIM_CNT_MODE_CENTER_ALIGN1 +*\*\ * TIM_CNT_MODE_CENTER_ALIGN2 +*\*\ * TIM_CNT_MODE_CENTER_ALIGN3 +*\*\ - Period +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - ClkDiv +*\*\ * TIM_CLK_DIV1 +*\*\ * TIM_CLK_DIV2 +*\*\ * TIM_CLK_DIV4 +*\*\ - RepetCnt +*\*\ * 0x00 ~ 0xFF +*\*\ - CapCh1Sel +*\*\ * TIM_CAPCH1SEL_0 +*\*\ * TIM_CAPCH1SEL_1 +*\*\ * TIM_CAPCH1SEL_2 +*\*\ * TIM_CAPCH1SEL_3 +*\*\ * TIM_CAPCH1SEL_4 +*\*\ * TIM_CAPCH1SEL_5 +*\*\ * TIM_CAPCH1SEL_6 +*\*\ * TIM_CAPCH1SEL_7 +*\*\ - CapCh2Sel +*\*\ * TIM_CAPCH2SEL_0 +*\*\ * TIM_CAPCH2SEL_1 +*\*\ * TIM_CAPCH2SEL_2 +*\*\ * TIM_CAPCH2SEL_3 +*\*\ * TIM_CAPCH2SEL_4 +*\*\ * TIM_CAPCH2SEL_TIMXCAPLSE +*\*\ - CapCh3Sel +*\*\ * TIM_CAPCH3SEL_0 +*\*\ * TIM_CAPCH3SEL_1 +*\*\ * TIM_CAPCH3SEL_TIMXCAPLSI +*\*\ - CapCh4Sel +*\*\ * TIM_CAPCH4SEL_0 +*\*\ * TIM_CAPCH4SEL_1 +*\*\ * TIM_CAPCH4SEL_2 +*\*\ * TIM_CAPCH4SEL_TIMXCAPHSEDIV128 +*\*\ - CapEtrClrSel +*\*\ * TIM_CAPETRSEL_0 +*\*\ * TIM_CAPETRSEL_1 +*\*\ * TIM_CAPETRSEL_2 +*\*\ * TIM_CAPETRSEL_3 +*\*\ * TIM_CAPETRSEL_4 +*\*\ * TIM_CAPETRSEL_5 +*\*\ * TIM_CAPETRSEL_6 +*\*\ * TIM_CAPETRSEL_7 +*\*\ * TIM_CAPETRSEL_8 +*\*\ * TIM_CAPETRSEL_10 +*\*\ * TIM_CAPETRSEL_11 +*\*\ * TIM_CAPETRSEL_12 +*\*\ * TIM_CAPETRSEL_13 +*\*\return none +**/ +void TIM_InitTimBaseStruct(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->Prescaler = 0x00000000; + TIM_TimeBaseInitStruct->CounterMode = TIM_CNT_MODE_UP; + TIM_TimeBaseInitStruct->Period = 0x0000FFFF; + TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseInitStruct->RepetCnt = 0x00000000; + + /* CH1/CH2/CH3/CH4/ETR from IOM */ + TIM_TimeBaseInitStruct->CapCh1Sel = TIM_CAPCH1SEL_0; + TIM_TimeBaseInitStruct->CapCh2Sel = TIM_CAPCH2SEL_0; + TIM_TimeBaseInitStruct->CapCh3Sel = TIM_CAPCH3SEL_0; + TIM_TimeBaseInitStruct->CapCh4Sel = TIM_CAPCH4SEL_0; + TIM_TimeBaseInitStruct->CapEtrClrSel = TIM_CAPETRSEL_0; +} + +/** +*\*\name TIM_InitOcStruct +*\*\fun Fills each TIM_OCInitStruct member with its default value. +*\*\param TIM_OCInitStruct: refer to the definition of OCInitType +*\*\ - OCMode +*\*\ * TIM_OCMODE_TIMING +*\*\ * TIM_OCMODE_ACTIVE +*\*\ * TIM_OCMODE_INACTIVE +*\*\ * TIM_OCMODE_TOGGLE +*\*\ * TIM_FORCED_ACTION_INACTIVE +*\*\ * TIM_FORCED_ACTION_ACTIVE +*\*\ * TIM_OCMODE_PWM1 +*\*\ * TIM_OCMODE_PWM2 +*\*\ * TIM_OCMODE_OPMOD_RETRIG1 +*\*\ * TIM_OCMODE_OPMOD_RETRIG2 +*\*\ * TIM_OCMODE_COMBI_PWM1 +*\*\ * TIM_OCMODE_COMBI_PWM2 +*\*\ - OutputState +*\*\ * TIM_OUTPUT_STATE_DISABLE +*\*\ * TIM_OUTPUT_STATE_ENABLE +*\*\ - OutputNState +*\*\ * TIM_OUTPUT_NSTATE_DISABLE +*\*\ * TIM_OUTPUT_NSTATE_ENABLE +*\*\ - Pulse +*\*\ * 0x0000 ~ 0xFFFF +*\*\ - OCPolarity +*\*\ * TIM_OC_POLARITY_HIGH +*\*\ * TIM_OC_POLARITY_LOW +*\*\ - OCNPolarity +*\*\ * TIM_OCN_POLARITY_HIGH +*\*\ * TIM_OCN_POLARITY_LOW +*\*\ - OCIdleState +*\*\ * TIM_OC_IDLE_STATE_SET +*\*\ * TIM_OC_IDLE_STATE_RESET +*\*\ - OCNIdleState +*\*\ * TIM_OCN_IDLE_STATE_SET +*\*\ * TIM_OCN_IDLE_STATE_RESET +*\*\return none +**/ +void TIM_InitOcStruct(OCInitType* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->OCMode = TIM_OCMODE_TIMING; + TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE; + TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE; + TIM_OCInitStruct->Pulse = 0x00000000; + TIM_OCInitStruct->OCPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OCNPolarity = TIM_OCN_POLARITY_HIGH; + TIM_OCInitStruct->OCIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStruct->OCNIdleState = TIM_OCN_IDLE_STATE_RESET; +} + +/** +*\*\name TIM_InitIcStruct +*\*\fun Fills each TIM_ICInitStruct member with its default value. +*\*\param TIM_ICInitStruct: refer to the definition of TIM_ICInitType +*\*\ - Channel +*\*\ * TIM_CH_1 +*\*\ * TIM_CH_2 +*\*\ * TIM_CH_3 +*\*\ * TIM_CH_4 +*\*\ - ICPolarity +*\*\ * TIM_IC_POLARITY_RISING +*\*\ * TIM_IC_POLARITY_FALLING +*\*\ - ICSelection +*\*\ * TIM_IC_SELECTION_DIRECTTI +*\*\ * TIM_IC_SELECTION_INDIRECTTI +*\*\ * TIM_IC_SELECTION_TRC +*\*\ - ICPrescaler +*\*\ * TIM_IC_PSC_DIV1 +*\*\ * TIM_IC_PSC_DIV2 +*\*\ * TIM_IC_PSC_DIV4 +*\*\ * TIM_IC_PSC_DIV8 +*\*\ - ICFilter +*\*\ * ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_InitIcStruct(TIM_ICInitType* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->Channel = TIM_CH_1; + TIM_ICInitStruct->ICPolarity = TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICSelection = TIM_IC_SELECTION_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = TIM_IC_PSC_DIV1; + TIM_ICInitStruct->ICFilter = 0x00000000; +} + +/** +*\*\name TIM_InitBkdtStruct +*\*\fun Fills each TIM_BDTRInitStruct member with its default value. +*\*\param TIM_BDTRInitStruct: refer to the definition of TIM_BDTRInitType +*\*\ - OSSRState +*\*\ * TIM_OSSR_STATE_ENABLE +*\*\ * TIM_OSSR_STATE_DISABLE +*\*\ - OSSIState +*\*\ * TIM_OSSI_STATE_ENABLE +*\*\ * TIM_OSSI_STATE_DISABLE +*\*\ - LOCKLevel +*\*\ * TIM_LOCK_LEVEL_OFF +*\*\ * TIM_LOCK_LEVEL_1 +*\*\ * TIM_LOCK_LEVEL_2 +*\*\ * TIM_LOCK_LEVEL_3 +*\*\ - DeadTime +*\*\ * DeadTime can be a number between 0x00 and 0xFF +*\*\ - Break +*\*\ * TIM_BREAK_IN_ENABLE +*\*\ * TIM_BREAK_BID_DISABLE +*\*\ - BreakPolarity +*\*\ * TIM_BREAK_POLARITY_LOW +*\*\ * TIM_BREAK_POLARITY_HIGH +*\*\ - Bidirection +*\*\ * TIM_BREAK_BID_ENABLE +*\*\ * TIM_BREAK_BID_DISABLE +*\*\ - AutomaticOutput +*\*\ * TIM_AUTO_OUTPUT_ENABLE +*\*\ * TIM_AUTO_OUTPUT_DISABLE +*\*\ - Break2 +*\*\ * TIM_BREAK2_IN_ENABLE +*\*\ * TIM_BREAK2_IN_DISABLE +*\*\ - Break2Polarity +*\*\ * TIM_BREAK2_POLARITY_LOW +*\*\ * TIM_BREAK2_POLARITY_HIGH +*\*\ - Bidirection2 +*\*\ * TIM_BREAK2_BID_ENABLE +*\*\ * TIM_BREAK2_BID_DISABLE +*\*\return none +**/ +void TIM_InitBkdtStruct(TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = TIM_OSSR_STATE_DISABLE; + TIM_BDTRInitStruct->OSSIState = TIM_OSSI_STATE_DISABLE; + TIM_BDTRInitStruct->LOCKLevel = TIM_LOCK_LEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = 0x00000000; + TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->Bidirection = TIM_BREAK_BID_DISABLE; + TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE; + TIM_BDTRInitStruct->Break2 = TIM_BREAK2_IN_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Bidirection2 = TIM_BREAK2_BID_DISABLE; +} + +/** +*\*\name TIM_Enable +*\*\fun Enables or disables the specified TIM peripheral. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_Enable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CTRL1 |= (uint32_t)TIM_CTRL1_CNTEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CTRL1 &= (uint32_t)(~TIM_CTRL1_CNTEN); + } +} + +/** +*\*\name TIM_EnableCtrlPwmOutputs +*\*\fun Enables or disables the TIM peripheral Main Outputs. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_EnableCtrlPwmOutputs(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BKDT |= (uint32_t)TIM_BKDT_MOEN; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BKDT &= (uint32_t)(~TIM_BKDT_MOEN); + } +} + +/** +*\*\name TIM_ConfigInt +*\*\fun Enables or disables the specified TIM interrupts. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_IT: +*\*\ - TIM_INT_CC1 +*\*\ - TIM_INT_CC2 +*\*\ - TIM_INT_CC3 +*\*\ - TIM_INT_CC4 +*\*\ - TIM_INT_CC5 +*\*\ - TIM_INT_CC6 +*\*\ - TIM_INT_CC7 +*\*\ - TIM_INT_CC8 +*\*\ - TIM_INT_CC9 +*\*\ - TIM_INT_UPDATE +*\*\ - TIM_INT_TRIG +*\*\ - TIM_INT_BREAK +*\*\ - TIM_INT_COM +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_ConfigInt(TIM_Module* TIMx, uint32_t TIM_IT, FunctionalState Cmd) +{ + + if (Cmd != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DINTEN |= (uint32_t)TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DINTEN &= (uint32_t)(~(uint32_t)TIM_IT); + } +} + +/** +*\*\name TIM_GenerateEvent +*\*\fun Configures the TIMx event to be generate by software. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_EventSource: +*\*\ - TIM_EVT_SRC_CC1 +*\*\ - TIM_EVT_SRC_CC2 +*\*\ - TIM_EVT_SRC_CC3 +*\*\ - TIM_EVT_SRC_CC4 +*\*\ - TIM_EVT_SRC_UPDATE +*\*\ - TIM_EVT_SRC_COM +*\*\ - TIM_EVT_SRC_TRIG +*\*\ - TIM_EVT_SRC_BREAK +*\*\ - TIM_EVT_SRC_BREAK2 +*\*\return none +**/ +void TIM_GenerateEvent(TIM_Module* TIMx, uint32_t TIM_EventSource) +{ + /* Set the event sources */ + TIMx->EVTGEN = TIM_EventSource; +} + +/** +*\*\name TIM_ConfigDma +*\*\fun Configures the TIMx's DMA interface. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_DMABase: +*\*\ - TIM_DMABASE_CTRL1 +*\*\ - TIM_DMABASE_CTRL2 +*\*\ - TIM_DMABASE_STS +*\*\ - TIM_DMABASE_EVTGEN +*\*\ - TIM_DMABASE_SMCTRL +*\*\ - TIM_DMABASE_DMAINTEN +*\*\ - TIM_DMABASE_CAPCMPMOD1 +*\*\ - TIM_DMABASE_CAPCMPMOD2 +*\*\ - TIM_DMABASE_CAPCMPMOD3 +*\*\ - TIM_DMABASE_CAPCMPEN +*\*\ - TIM_DMABASE_CAPCMPDAT1 +*\*\ - TIM_DMABASE_CAPCMPDAT2 +*\*\ - TIM_DMABASE_CAPCMPDAT3 +*\*\ - TIM_DMABASE_CAPCMPDAT4 +*\*\ - TIM_DMABASE_CAPCMPDAT5 +*\*\ - TIM_DMABASE_CAPCMPDAT6 +*\*\ - TIM_DMABASE_PSC +*\*\ - TIM_DMABASE_AR +*\*\ - TIM_DMABASE_CNT +*\*\ - TIM_DMABASE_REPCNT +*\*\ - TIM_DMABASE_BKDT +*\*\ - TIM_DMABASE_CAPCMPDAT7 +*\*\ - TIM_DMABASE_CAPCMPDAT8 +*\*\ - TIM_DMABASE_CAPCMPDAT9 +*\*\ - TIM_DMABASE_BKFR +*\*\ - TIM_DMABASE_C1FILT +*\*\ - TIM_DMABASE_C2FILT +*\*\ - TIM_DMABASE_C3FILT +*\*\ - TIM_DMABASE_C4FILT +*\*\ - TIM_DMABASE_FILTO +*\*\ - TIM_DMABASE_INSEL +*\*\ - TIM_DMABASE_AF1 +*\*\ - TIM_DMABASE_AF2 +*\*\ - TIM_DMABASE_BKFR2 +*\*\ - TIM_DMABASE_SLIDFPSC +*\*\param TIM_DMABurstLength: +*\*\ - This parameter can be one value between: +*\*\ TIM_DMABURST_LENGTH_1TRANSFER and TIM_DMABURST_LENGTH_35TRANSFERS. +*\*\return none +**/ +void TIM_ConfigDma(TIM_Module* TIMx, uint32_t TIM_DMABase, uint32_t TIM_DMABurstLength) +{ + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCTRL = TIM_DMABase | TIM_DMABurstLength; +} + +/** +*\*\name TIM_EnableDma +*\*\fun Enables or disables the TIMx's DMA Requests. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_DMASource: +*\*\ - TIM_DMA_CC1 +*\*\ - TIM_DMA_CC2 +*\*\ - TIM_DMA_CC3 +*\*\ - TIM_DMA_CC4 +*\*\ - TIM_DMA_UPDATE +*\*\ - TIM_DMA_COM +*\*\ - TIM_DMA_TRIG +*\*\param Cmd: +*\*\ - DISABLE +*\*\ - ENABLE +*\*\return none +**/ +void TIM_EnableDma(TIM_Module* TIMx, uint32_t TIM_DMASource, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DINTEN |= (uint32_t)TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DINTEN &= (uint32_t)(~((uint32_t)TIM_DMASource)); + } +} + +/** +*\*\name TIM_ConfigInternalClk +*\*\fun Configures the TIMx internal Clock +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return none +**/ +void TIM_ConfigInternalClk(TIM_Module* TIMx) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCTRL &= (uint32_t)(~((uint32_t)TIM_SMCTRL_SMSEL)); +} + +/** +*\*\name TIM_ConfigInternalTrigToExt +*\*\fun Configures the TIMx Internal Trigger as External Clock +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_InputTriggerSource: +*\*\ - TIM_TRIG_SEL_IN_TR0 +*\*\ - TIM_TRIG_SEL_IN_TR1 +*\*\ - TIM_TRIG_SEL_IN_TR2 +*\*\ - TIM_TRIG_SEL_IN_TR3 +*\*\ - TIM_TRIG_SEL_IN_TR4 +*\*\ - TIM_TRIG_SEL_IN_TR5 +*\*\ - TIM_TRIG_SEL_IN_TR6 +*\*\ - TIM_TRIG_SEL_IN_TR7 +*\*\ - TIM_TRIG_SEL_IN_TR8 +*\*\ - TIM_TRIG_SEL_IN_TR9 +*\*\ - TIM_TRIG_SEL_IN_TR10 +*\*\ - TIM_TRIG_SEL_IN_TR11 +*\*\ - TIM_TRIG_SEL_IN_TR12 +*\*\ - TIM_TRIG_SEL_IN_TR13 +*\*\ - TIM_TRIG_SEL_IN_TR14 +*\*\return none +**/ +void TIM_ConfigInternalTrigToExt(TIM_Module* TIMx, uint32_t TIM_InputTriggerSource) +{ + /* Select the Internal Trigger */ + TIM_SelectInputTrig(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= (uint32_t)TIM_SLAVE_MODE_EXT1; +} + +/** +*\*\name TIM_ConfigExtTrigAsClk +*\*\fun Configures the TIMx Trigger as External Clock +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_TIxExternalCLKSource: +*\*\ - TIM_TRIG_SEL_TI1F_ED +*\*\ - TIM_TRIG_SEL_TI1FP1 +*\*\ - TIM_TRIG_SEL_TI2FP2 +*\*\param ICPolarity +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param ICFilter +*\*\ - ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_ConfigExtTrigAsClk(TIM_Module* TIMx, uint32_t TIM_TIxExternalCLKSource, uint32_t IcPolarity, uint32_t ICFilter) +{ + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TRIG_SEL_TI2FP2) + { + ConfigTI2(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + else + { + ConfigTI1(TIMx, IcPolarity, TIM_IC_SELECTION_DIRECTTI, ICFilter); + } + + /* Select the Trigger source */ + TIM_SelectInputTrig(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= (uint32_t)TIM_SLAVE_MODE_EXT1; +} + +/** +*\*\name TIM_ConfigExtClkMode1 +*\*\fun Configures the External clock Mode1 +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ETRInputSource: +*\*\ - TIM_CAPETRSEL_0 +*\*\ - TIM_CAPETRSEL_1 +*\*\ - TIM_CAPETRSEL_2 +*\*\ - TIM_CAPETRSEL_3 +*\*\ - TIM_CAPETRSEL_4 +*\*\ - TIM_CAPETRSEL_5 +*\*\ - TIM_CAPETRSEL_6 +*\*\ - TIM_CAPETRSEL_7 +*\*\ - TIM_CAPETRSEL_8 +*\*\ - TIM_CAPETRSEL_9 +*\*\ - TIM_CAPETRSEL_10 +*\*\ - TIM_CAPETRSEL_11 +*\*\ - TIM_CAPETRSEL_12 +*\*\ - TIM_CAPETRSEL_13 +*\*\param TIM_ExtTRGPrescaler: +*\*\ - TIM_EXT_TRG_PSC_OFF +*\*\ - TIM_EXT_TRG_PSC_DIV2 +*\*\ - TIM_EXT_TRG_PSC_DIV4 +*\*\ - TIM_EXT_TRG_PSC_DIV8 +*\*\param TIM_ExtTRGPolarity +*\*\ - TIM_EXT_TRIG_POLARITY_INVERTED +*\*\ - TIM_EXT_TRIG_POLARITY_NONINVERTED +*\*\param ExtTRGFilter +*\*\ - ExtTRGFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_ConfigExtClkMode1(TIM_Module* TIMx, uint32_t TIM_ETRInputSource, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmctrl ; + /* Configure the ETR input source */ + TIM_SelectETRInputSource(TIMx, TIM_ETRInputSource); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCTRL register value */ + tmpsmctrl = TIMx->SMCTRL; + /* Reset the SMS Bits */ + tmpsmctrl &= (uint32_t)(~((uint32_t)TIM_SMCTRL_SMSEL)); + /* Select the External clock mode1 */ + tmpsmctrl |= (uint32_t)TIM_SLAVE_MODE_EXT1; + /* Select the Trigger selection : ETRF */ + tmpsmctrl &= (uint32_t)(~((uint32_t)TIM_SMCTRL_TSEL)); + tmpsmctrl |= (uint32_t)TIM_TRIG_SEL_ETRF; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmctrl; +} + +/** +*\*\name TIM_ConfigExtClkMode2 +*\*\fun Configures the External clock Mode2 +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ETRInputSource: +*\*\ - TIM_CAPETRSEL_0 +*\*\ - TIM_CAPETRSEL_1 +*\*\ - TIM_CAPETRSEL_2 +*\*\ - TIM_CAPETRSEL_3 +*\*\ - TIM_CAPETRSEL_4 +*\*\ - TIM_CAPETRSEL_5 +*\*\ - TIM_CAPETRSEL_6 +*\*\ - TIM_CAPETRSEL_7 +*\*\ - TIM_CAPETRSEL_8 +*\*\ - TIM_CAPETRSEL_9 +*\*\ - TIM_CAPETRSEL_10 +*\*\ - TIM_CAPETRSEL_11 +*\*\ - TIM_CAPETRSEL_12 +*\*\ - TIM_CAPETRSEL_13 +*\*\param TIM_ExtTRGPrescaler: +*\*\ - TIM_EXT_TRG_PSC_OFF +*\*\ - TIM_EXT_TRG_PSC_DIV2 +*\*\ - TIM_EXT_TRG_PSC_DIV4 +*\*\ - TIM_EXT_TRG_PSC_DIV8 +*\*\param TIM_ExtTRGPolarity +*\*\ - TIM_EXT_TRIG_POLARITY_INVERTED +*\*\ - TIM_EXT_TRIG_POLARITY_NONINVERTED +*\*\param ExtTRGFilter +*\*\ - ExtTRGFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_ConfigExtClkMode2(TIM_Module* TIMx, uint32_t TIM_ETRInputSource, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + /* Configure the ETR input source */ + TIM_SelectETRInputSource(TIMx, TIM_ETRInputSource); + /* Configure the ETR Clock source */ + TIM_ConfigExtTrig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCTRL |= (uint32_t)TIM_SMCTRL_EXCEN; +} + +/** +*\*\name TIM_ConfigPrescaler +*\*\fun Configures the TIMx Prescaler. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param Prescaler: +*\*\ - 0x0000 ~ 0xFFFF +*\*\param TIM_PSCReloadMode +*\*\ - TIM_PSC_RELOAD_MODE_UPDATE +*\*\ - TIM_PSC_RELOAD_MODE_IMMEDIATE +*\*\return none +**/ +void TIM_ConfigPrescaler(TIM_Module* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode) +{ + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EVTGEN = TIM_PSCReloadMode; +} + +/** +*\*\name TIM_ConfigCntMode +*\*\fun Specifies the TIMx Counter Mode to be used. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param CntMode +*\*\ - TIM_CNT_MODE_UP +*\*\ - TIM_CNT_MODE_DOWN +*\*\ - TIM_CNT_MODE_CENTER_ALIGN1 +*\*\ - TIM_CNT_MODE_CENTER_ALIGN2 +*\*\ - TIM_CNT_MODE_CENTER_ALIGN3 +*\*\return none +**/ +void TIM_ConfigCntMode(TIM_Module* TIMx, uint32_t CntMode) +{ + uint32_t tmpctrl1 ; + tmpctrl1 = TIMx->CTRL1; + /* Reset the CMS and DIR Bits */ + tmpctrl1 &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + /* Set the Counter Mode */ + tmpctrl1 |= (uint32_t)CntMode; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = tmpctrl1; +} + +/** +*\*\name TIM_ConfigEncoderInterface +*\*\fun Configures the TIMx Encoder Interface. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_EncoderMode +*\*\ - TIM_ENCODE_QUA_MODE_TI1 +*\*\ - TIM_ENCODE_QUA_MODE_TI2 +*\*\ - TIM_ENCODE_QUA_MODE_TI12 +*\*\ - TIM_ENCODE_QUA_MODE_SINGLE_TI1 +*\*\ - TIM_ENCODE_QUA_MODE_SINGLE_TI2 +*\*\ - TIM_ENCODE_DUL_CLKPLUS_MODE1 +*\*\ - TIM_ENCODE_DUL_CLKPLUS_MODE2 +*\*\ - TIM_ENCODE_SINGLE_CLKPLUS_MODE1 +*\*\ - TIM_ENCODE_SINGLE_CLKPLUS_MODE2 +*\*\param TIM_IC1Polarity +*\*\ - TIM_IC_POLARITY_FALLING +*\*\ - TIM_IC_POLARITY_RISING +*\*\param TIM_IC2Polarity +*\*\ - TIM_IC_POLARITY_FALLING +*\*\ - TIM_IC_POLARITY_RISING +*\*\return none +**/ +void TIM_ConfigEncoderInterface(TIM_Module* TIMx, uint32_t TIM_EncoderMode, uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity) +{ + uint32_t tmpsmctrl ; + uint32_t tmpccmodx ; + uint32_t tmpccen ; + + /* Get the TIMx SMCTRL register value */ + tmpsmctrl = TIMx->SMCTRL; + + /* Get the TIMx CCMOD1 register value */ + tmpccmodx = TIMx->CCMOD1; + + /* Get the TIMx CCEN register value */ + tmpccen = TIMx->CCEN; + + /* Set the encoder Mode */ + tmpsmctrl &= (uint32_t)(~((uint32_t)TIM_SMCTRL_SMSEL)); + tmpsmctrl |= (uint32_t)TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmodx &= (uint32_t)((~TIM_CCMOD1_CC1SEL) & (~TIM_CCMOD1_CC2SEL)); + tmpccmodx |= (uint32_t)(TIM_CCMOD1_CC1SEL_0 | TIM_CCMOD1_CC2SEL_0); + + /* Set the TI1 and the TI2 Polarities */ + tmpccen &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCEN_CC1P)) & ((uint32_t) ~((uint32_t)TIM_CCEN_CC2P))); + tmpccen |= (uint32_t)(TIM_IC1Polarity | (uint32_t)(TIM_IC2Polarity << (uint32_t)4)); + + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmctrl; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmodx; + /* Write to TIMx CCEN */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigForcedOc1 +*\*\fun Forces the TIMx output 1 waveform to active or inactive level. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ForcedAction +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\return none +**/ +void TIM_ConfigForcedOc1(TIM_Module* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmodx; + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC1MD); + /* Configure The Forced output Mode */ + tmpccmodx |= (uint32_t)TIM_ForcedAction; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigForcedOc2 +*\*\fun Forces the TIMx output 2 waveform to active or inactive level. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ForcedAction +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\return none +**/ +void TIM_ConfigForcedOc2(TIM_Module* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC2M Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC2MD); + /* Configure The Forced output Mode */ + tmpccmodx |= (uint32_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigForcedOc3 +*\*\fun Forces the TIMx output 3 waveform to active or inactive level. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ForcedAction +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\return none +**/ +void TIM_ConfigForcedOc3(TIM_Module* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC3MD); + /* Configure The Forced output Mode */ + tmpccmodx |= (uint32_t)TIM_ForcedAction; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigForcedOc4 +*\*\fun Forces the TIMx output 4 waveform to active or inactive level. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ForcedAction +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\return none +**/ +void TIM_ConfigForcedOc4(TIM_Module* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC2M Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC4MD); + /* Configure The Forced output Mode */ + tmpccmodx |= (uint32_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigForcedOc5 +*\*\fun Forces the TIMx output 5 waveform to active or inactive level. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ForcedAction +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\return none +**/ +void TIM_ConfigForcedOc5(TIM_Module* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC5MD); + /* Configure The Forced output Mode */ + tmpccmodx |= (uint32_t)(TIM_ForcedAction); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigForcedOc6 +*\*\fun Forces the TIMx output 6 waveform to active or inactive level. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_ForcedAction +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\return none +**/ +void TIM_ConfigForcedOc6(TIM_Module* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC2M Bits */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC6MD); + /* Configure The Forced output Mode */ + tmpccmodx |= (uint32_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigArPreload +*\*\fun Enables or disables TIMx peripheral Preload register on AR. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_ConfigArPreload(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the AR Preload Bit */ + TIMx->CTRL1 |= (uint32_t)TIM_CTRL1_ARPEN; + } + else + { + /* Reset the AR Preload Bit */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_ARPEN)); + } +} + +/** +*\*\name TIM_SelectComEvt +*\*\fun Selects the TIM peripheral Commutation event. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_SelectComEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the CCUSEL Bit */ + TIMx->CTRL2 |= (uint32_t)TIM_CTRL2_CCUSEL; + } + else + { + /* Reset the CCUSEL Bit */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_CCUSEL)); + } +} + +/** +*\*\name TIM_SelectCapCmpDmaSrc +*\*\fun Selects the TIMx peripheral Capture Compare DMA source. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_SelectCapCmpDmaSrc(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the CCDSEL Bit */ + TIMx->CTRL2 |= (uint32_t)TIM_CTRL2_CCDSEL; + } + else + { + /* Reset the CCDSEL Bit */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_CCDSEL)); + } +} + +/** +*\*\name TIM_EnableCapCmpPreloadControl +*\*\fun Sets or Resets the TIM peripheral Capture Compare Preload Control bit. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_EnableCapCmpPreloadControl(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CTRL2 |= (uint32_t)TIM_CTRL2_CCPCTL; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_CCPCTL)); + } +} + +/** +*\*\name TIM_ConfigOc1Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT1. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc1Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC1PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC1PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)TIM_OCPreload; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc2Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT2. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc2Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC2PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC2PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc3Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT3. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc3Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC3PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC3PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)TIM_OCPreload; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc4Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT4. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc4Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC4PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC4PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc5Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT5. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc5Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC5PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC5PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc6Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT6. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc6Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC6PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC6PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc7Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT6. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc7Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC7PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC7PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload << 14); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc8Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT6. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc8Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC8PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC8PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload << 18); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc9Preload +*\*\fun Enables or disables the TIMx peripheral Preload register on CCDAT6. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_PRE_LOAD_ENABLE +*\*\ - TIM_OC_PRE_LOAD_DISABLE +*\*\return none +**/ +void TIM_ConfigOc9Preload(TIM_Module* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmodx; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC9PEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC9PEN); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmodx |= (uint32_t)(TIM_OCPreload << 22); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc1Fast +*\*\fun Configures the TIMx Output Compare 1 Fast feature. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_FAST_ENABLE +*\*\ - TIM_OC_FAST_DISABLE +*\*\return none +**/ +void TIM_ConfigOc1Fast(TIM_Module* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmodx ; + /* Get the TIMx CCMOD1 register value */ + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC1FEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC1FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmodx |= (uint32_t)TIM_OCFast; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc2Fast +*\*\fun Configures the TIMx Output Compare 2 Fast feature. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_FAST_ENABLE +*\*\ - TIM_OC_FAST_DISABLE +*\*\return none +**/ +void TIM_ConfigOc2Fast(TIM_Module* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmodx ; + /* Get the TIMx CCMOD1 register value */ + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC2FEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC2FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmodx |= (uint32_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc3Fast +*\*\fun Configures the TIMx Output Compare 3 Fast feature. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_FAST_ENABLE +*\*\ - TIM_OC_FAST_DISABLE +*\*\return none +**/ +void TIM_ConfigOc3Fast(TIM_Module* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmodx ; + /* Get the TIMx CCMOD2 register value */ + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC3FEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC3FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmodx |= (uint32_t)TIM_OCFast; + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc4Fast +*\*\fun Configures the TIMx Output Compare 4 Fast feature. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_FAST_ENABLE +*\*\ - TIM_OC_FAST_DISABLE +*\*\return none +**/ +void TIM_ConfigOc4Fast(TIM_Module* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmodx ; + /* Get the TIMx CCMOD2 register value */ + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC4FEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC4FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmodx |= (uint32_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc5Fast +*\*\fun Configures the TIMx Output Compare 5 Fast feature. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_FAST_ENABLE +*\*\ - TIM_OC_FAST_DISABLE +*\*\return none +**/ +void TIM_ConfigOc5Fast(TIM_Module* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmodx ; + /* Get the TIMx CCMOD2 register value */ + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC4FEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC5FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmodx |= (uint32_t)(TIM_OCFast); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ConfigOc6Fast +*\*\fun Configures the TIMx Output Compare 6 Fast feature. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_FAST_ENABLE +*\*\ - TIM_OC_FAST_DISABLE +*\*\return none +**/ +void TIM_ConfigOc6Fast(TIM_Module* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmodx ; + /* Get the TIMx CCMOD2 register value */ + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC4FEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC6FEN); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmodx |= (uint32_t)(TIM_OCFast << 8); + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOc1Ref +*\*\fun Clears or safeguards the OCREF1 signal on an external event +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_CLR_ENABLE +*\*\ - TIM_OC_CLR_DISABLE +*\*\return none +**/ +void TIM_ClrOc1Ref(TIM_Module* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC1CEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC1CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmodx |= (uint32_t)TIM_OCClear; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOc2Ref +*\*\fun Clears or safeguards the OCREF2 signal on an external event +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_CLR_ENABLE +*\*\ - TIM_OC_CLR_DISABLE +*\*\return none +**/ +void TIM_ClrOc2Ref(TIM_Module* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD1; + /* Reset the OC2CEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD1_OC2CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmodx |= (uint32_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOc3Ref +*\*\fun Clears or safeguards the OCREF3 signal on an external event +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_CLR_ENABLE +*\*\ - TIM_OC_CLR_DISABLE +*\*\return none +**/ +void TIM_ClrOc3Ref(TIM_Module* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC3CEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC3CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmodx |= (uint32_t)TIM_OCClear; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOc4Ref +*\*\fun Clears or safeguards the OCREF4 signal on an external event +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_CLR_ENABLE +*\*\ - TIM_OC_CLR_DISABLE +*\*\return none +**/ +void TIM_ClrOc4Ref(TIM_Module* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD2; + /* Reset the OC4CEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD2_OC4CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmodx |= (uint32_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOc5Ref +*\*\fun Clears or safeguards the OCREF5 signal on an external event +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_CLR_ENABLE +*\*\ - TIM_OC_CLR_DISABLE +*\*\return none +**/ +void TIM_ClrOc5Ref(TIM_Module* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC4CEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC5CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmodx |= (uint32_t)(TIM_OCClear); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOc6Ref +*\*\fun Clears or safeguards the OCREF6 signal on an external event +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_CLR_ENABLE +*\*\ - TIM_OC_CLR_DISABLE +*\*\return none +**/ +void TIM_ClrOc6Ref(TIM_Module* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmodx ; + tmpccmodx = TIMx->CCMOD3; + /* Reset the OC4CEN Bit */ + tmpccmodx &= (uint32_t)(~TIM_CCMOD3_OC6CEN); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmodx |= (uint32_t)(TIM_OCClear << 8); + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = tmpccmodx; +} + +/** +*\*\name TIM_ClrOcRefInputSource +*\*\fun Set the OCREF clear input source +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param OCRefClearInputSelect +*\*\ - TIM_ETRSEL +*\*\ - TIM_CLRSEL +*\*\param OCRefClearInputSource +*\*\ - TIM_CAPETRSEL_0 +*\*\ - TIM_CAPETRSEL_1 +*\*\ - TIM_CAPETRSEL_2 +*\*\ - TIM_CAPETRSEL_3 +*\*\ - TIM_CAPETRSEL_4 +*\*\ - TIM_CAPETRSEL_5 +*\*\ - TIM_CAPETRSEL_6 +*\*\ - TIM_CAPETRSEL_7 +*\*\ - TIM_CAPETRSEL_8 +*\*\ - TIM_CAPETRSEL_9 +*\*\ - TIM_CAPETRSEL_10 +*\*\ - TIM_CAPETRSEL_11 +*\*\ - TIM_CAPETRSEL_12 +*\*\ - TIM_CAPETRSEL_13 +*\*\ - TIM_OCCLRSEL_0 +*\*\ - TIM_OCCLRSEL_1 +*\*\ - TIM_OCCLRSEL_2 +*\*\ - TIM_OCCLRSEL_3 +*\*\ - TIM_OCCLRSEL_4 +*\*\ - TIM_OCCLRSEL_5 +*\*\ - TIM_OCCLRSEL_6 +*\*\ - TIM_OCCLRSEL_7 +*\*\return none +**/ +void TIM_ClrOcRefInputSource(TIM_Module* TIMx, uint32_t OCRefClearInputSelect, uint32_t OCRefClearInputSource) +{ + uint32_t tmpctrl1 ; + uint32_t tmpinsel ; + /* Get the value of TIMx_CTRL1 and TIMx_INSEL */ + tmpctrl1 = TIMx->CTRL1; + tmpinsel = TIMx->INSEL; + /* Reset the CTRL1_CLRSEL\INSEL_ETRS\INSEL_CLRS bits */ + tmpctrl1 &= (uint32_t)(~TIM_CTRL1_CLRSEL); + tmpinsel &= (uint32_t)(~TIM_INSEL_ETRS); + tmpinsel &= (uint32_t)(~TIM_INSEL_CLRS); + + if (OCRefClearInputSelect) + { + /* CLR select capture in */ + tmpctrl1 |= (uint32_t)TIM_OCCLRSEL_COMP; + tmpinsel |= (uint32_t)OCRefClearInputSource; + } + else + { + /* ETR select capture in */ + tmpinsel |= (uint32_t)OCRefClearInputSource; + } + + TIMx->CTRL1 = tmpctrl1; + TIMx->INSEL = tmpinsel; +} + +/** +*\*\name TIM_ConfigOc1Polarity +*\*\fun Configures the TIMx channel 1 polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_POLARITY_HIGH +*\*\ - TIM_OC_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc1Polarity(TIM_Module* TIMx, uint32_t OcPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC1P Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1P)); + tmpccen |= (uint32_t)OcPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc1NPolarity +*\*\fun Configures the TIMx channel 1N polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OCN_POLARITY_HIGH +*\*\ - TIM_OCN_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc1NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC1NP Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1NP)); + tmpccen |= (uint32_t)OcNPolarity; + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc2Polarity +*\*\fun Configures the TIMx channel 2 polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_POLARITY_HIGH +*\*\ - TIM_OC_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc2Polarity(TIM_Module* TIMx, uint32_t OcPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC2P Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2P)); + tmpccen |= (uint32_t)(OcPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc2NPolarity +*\*\fun Configures the TIMx channel 2N polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OCN_POLARITY_HIGH +*\*\ - TIM_OCN_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc2NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC2NP Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2NP)); + tmpccen |= (uint32_t)(OcNPolarity << 4); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc3Polarity +*\*\fun Configures the TIMx channel 3 polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_POLARITY_HIGH +*\*\ - TIM_OC_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc3Polarity(TIM_Module* TIMx, uint32_t OcPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC3P Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3P)); + tmpccen |= (uint32_t)(OcPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc3NPolarity +*\*\fun Configures the TIMx channel 3N polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OCN_POLARITY_HIGH +*\*\ - TIM_OCN_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc3NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC3NP Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3NP)); + tmpccen |= (uint32_t)(OcNPolarity << 8); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc4Polarity +*\*\fun Configures the TIMx channel 4 polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_POLARITY_HIGH +*\*\ - TIM_OC_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc4Polarity(TIM_Module* TIMx, uint32_t OcPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC4P Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4P)); + tmpccen |= (uint32_t)(OcPolarity << 12); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc4NPolarity +*\*\fun Configures the TIMx channel 4N polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OCN_POLARITY_HIGH +*\*\ - TIM_OCN_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc4NPolarity(TIM_Module* TIMx, uint32_t OcNPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC3NP Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4NP)); + tmpccen |= (uint32_t)(OcNPolarity << 12); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc5Polarity +*\*\fun Configures the TIMx channel 5 polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_POLARITY_HIGH +*\*\ - TIM_OC_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc5Polarity(TIM_Module* TIMx, uint32_t OcPolarity) +{ + uint32_t tmpccen; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC5P Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC5P)); + tmpccen |= (uint32_t)(OcPolarity << 16); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_ConfigOc6Polarity +*\*\fun Configures the TIMx channel 6 polarity. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_OCPreload +*\*\ - TIM_OC_POLARITY_HIGH +*\*\ - TIM_OC_POLARITY_LOW +*\*\return none +**/ +void TIM_ConfigOc6Polarity(TIM_Module* TIMx, uint32_t OcPolarity) +{ + uint32_t tmpccen ; + tmpccen = TIMx->CCEN; + /* Set or Reset the CC6P Bit */ + tmpccen &= (uint32_t)(~((uint32_t)TIM_CCEN_CC6P)); + tmpccen |= (uint32_t)(OcPolarity << 20); + /* Write to TIMx CCEN register */ + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_EnableCapCmpCh +*\*\fun Enables or disables the TIM Capture Compare Channel x. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Channel +*\*\ - TIM_CH_1 +*\*\ - TIM_CH_2 +*\*\ - TIM_CH_3 +*\*\ - TIM_CH_4 +*\*\ - TIM_CH_5 +*\*\ - TIM_CH_6 +*\*\param TIM_CCx +*\*\ - TIM_CAP_CMP_ENABLE +*\*\ - TIM_CAP_CMP_DISABLE +*\*\return none +**/ +void TIM_EnableCapCmpCh(TIM_Module* TIMx, uint32_t Channel, uint32_t TIM_CCx) +{ + uint32_t tmp ; + tmp = CAPCMPEN_CCE_SET << Channel; + /* Reset the CCxEN Bit */ + TIMx->CCEN &= (uint32_t)(~tmp); + /* Set or reset the CCxEN Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCx << Channel); +} + +/** +*\*\name TIM_EnableCapCmpChN +*\*\fun Enables or disables the TIM Capture Compare Channel xN. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Channel +*\*\ - TIM_CH_1 +*\*\ - TIM_CH_2 +*\*\ - TIM_CH_3 +*\*\ - TIM_CH_4 +*\*\param TIM_CCx +*\*\ - TIM_CAP_CMP_N_ENABLE +*\*\ - TIM_CAP_CMP_N_DISABLE +*\*\return none +**/ +void TIM_EnableCapCmpChN(TIM_Module* TIMx, uint32_t Channel, uint32_t TIM_CCxN) +{ + uint32_t tmp ; + tmp = CAPCMPEN_CCNE_SET << Channel; + /* Reset the CCxNEN Bit */ + TIMx->CCEN &= (uint32_t)(~tmp); + /* Set or reset the CCxNEN Bit */ + TIMx->CCEN |= (uint32_t)(TIM_CCxN << Channel); +} + +/** +*\*\name TIM_SelectOcMode +*\*\fun Selects the TIM Output Compare Mode. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Channel +*\*\ - TIM_CH_1 +*\*\ - TIM_CH_2 +*\*\ - TIM_CH_3 +*\*\ - TIM_CH_4 +*\*\ - TIM_CH_5 +*\*\ - TIM_CH_6 +*\*\param OcMode +*\*\ - TIM_OCMODE_TIMING +*\*\ - TIM_OCMODE_ACTIVE +*\*\ - TIM_OCMODE_INACTIVE +*\*\ - TIM_OCMODE_TOGGLE +*\*\ - TIM_OCMODE_PWM1 +*\*\ - TIM_OCMODE_PWM2 +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\ - TIM_OCMODE_OPMOD_RETRIG1 +*\*\ - TIM_OCMODE_OPMOD_RETRIG2 +*\*\ - TIM_OCMODE_COMBI_PWM1 +*\*\ - TIM_OCMODE_COMBI_PWM2 +*\*\return none +**/ +void TIM_SelectOcMode(TIM_Module* TIMx, uint32_t Channel, uint32_t OcMode) +{ + uint32_t tmp ; + uint32_t tmp1 ; + + tmp = (uint32_t)TIMx; + tmp += CAPCMPMOD_OFFSET; + + tmp1 = CAPCMPEN_CCE_SET << Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCEN &= (uint32_t)(~tmp1); + + if ((Channel == TIM_CH_1) || (Channel == TIM_CH_3) || (Channel == TIM_CH_5)) + { + tmp += (uint32_t)(Channel >> 1); + + /* Reset the OCxMD bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t) (~((uint32_t)(TIM_CCMOD1_OC1MD | TIM_CCMOD1_OC1MD_3))); + + /* Configure the OCxMD bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= (uint32_t)OcMode; + } + else + { + tmp += (uint32_t)((Channel - 4) >> 1); + + /* Reset the OCxMD bits in the CCMRx register */ + *(__IO uint32_t*)tmp &= (uint32_t)(~((uint32_t)(TIM_CCMOD1_OC2MD | TIM_CCMOD1_OC2MD_3))); + + /* Configure the OCxMD bits in the CCMRx register */ + *(__IO uint32_t*)tmp |= (uint32_t)(((OcMode << 8) & (0x0000E000)) | ((OcMode << 1) & (0x00040000))); + } +} + +/** +*\*\name TIM_EnableUpdateEvt +*\*\fun Enables or Disables the TIMx Update event. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_EnableUpdateEvt(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CTRL1 |= (uint32_t)TIM_CTRL1_UPDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_UPDIS)); + } +} + +/** +*\*\name TIM_ConfigUpdateRequestIntSrc +*\*\fun Configures the TIMx Update Request Interrupt source. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_UpdateSource +*\*\ - TIM_UPDATE_SRC_GLOBAL +*\*\ - TIM_UPDATE_SRC_REGULAR +*\*\return none +**/ +void TIM_ConfigUpdateRequestIntSrc(TIM_Module* TIMx, uint32_t TIM_UpdateSource) +{ + if (TIM_UpdateSource != TIM_UPDATE_SRC_GLOBAL) + { + /* Set the UPRS Bit */ + TIMx->CTRL1 |= (uint32_t)TIM_CTRL1_UPRS; + } + else + { + /* Reset the UPRS Bit */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_UPRS)); + } +} + +/** +*\*\name TIM_SelectHallSensor +*\*\fun Enables or disables the TIMx's Hall sensor interface. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_SelectHallSensor(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the TI1SEL Bit */ + TIMx->CTRL2 |= (uint32_t)TIM_CTRL2_TI1SEL; + } + else + { + /* Reset the TI1SEL Bit */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_TI1SEL)); + } +} + +/** +*\*\name TIM_SelectOnePulseMode +*\*\fun Selects the TIMx's One Pulse Mode. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_OPMode +*\*\ - TIM_OPMODE_SINGLE +*\*\ - TIM_OPMODE_REPET +*\*\return none +**/ +void TIM_SelectOnePulseMode(TIM_Module* TIMx, uint32_t TIM_OPMode) +{ + /* Reset the ONEPM Bit */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_ONEPM)); + /* Configure the ONEPM Mode */ + TIMx->CTRL1 |= (uint32_t)TIM_OPMode; +} + +/** +*\*\name TIM_SelectOutputTrig +*\*\fun Selects the TIMx Trigger Output Mode. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_TRGOSource +*\*\ - TIM_TRGO_SRC_RESET +*\*\ - TIM_TRGO_SRC_ENABLE +*\*\ - TIM_TRGO_SRC_UPDATE +*\*\ - TIM_TRGO_SRC_OC1 +*\*\ - TIM_TRGO_SRC_OC1REF +*\*\ - TIM_TRGO_SRC_OC2REF +*\*\ - TIM_TRGO_SRC_OC3REF +*\*\ - TIM_TRGO_SRC_OC4REF +*\*\ - TIM_TRGO_SRC_OC4_7_8_9REF +*\*\return none +**/ +void TIM_SelectOutputTrig(TIM_Module* TIMx, uint32_t TIM_TRGOSource) +{ + /* Reset the MMSEL Bits */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_MMSEL)); + /* Select the TRGO source */ + TIMx->CTRL2 |= TIM_TRGOSource; +} + +/** +*\*\name TIM_SelectOutputTrig2 +*\*\fun Selects the TIMx Trigger Output Mode. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_TRGO2Source +*\*\ - TIM_TRGO2_SRC_RESET +*\*\ - TIM_TRGO2_SRC_ENABLE +*\*\ - TIM_TRGO2_SRC_UPDATE +*\*\ - TIM_TRGO2_SRC_OC1 +*\*\ - TIM_TRGO2_SRC_OC1REF +*\*\ - TIM_TRGO2_SRC_OC2REF +*\*\ - TIM_TRGO2_SRC_OC3REF +*\*\ - TIM_TRGO2_SRC_OC4REF +*\*\ - TIM_TRGO2_SRC_OC5REF +*\*\ - TIM_TRGO2_SRC_OC6REF +*\*\ - LL_TIM_TRGO2_OC4_RISINGFALLING +*\*\ - LL_TIM_TRGO2_OC6_RISINGFALLING +*\*\ - LL_TIM_TRGO2_OC4_RISING_OC6_RISING +*\*\ - LL_TIM_TRGO2_OC4_RISING_OC6_FALLING +*\*\ - LL_TIM_TRGO2_OC5_RISING_OC6_RISING +*\*\ - LL_TIM_TRGO2_OC5_RISING_OC6_FALLING +*\*\return none +**/ +void TIM_SelectOutputTrig2(TIM_Module* TIMx, uint32_t TIM_TRGO2Source) +{ + /* Reset the MMSEL2 Bits */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)TIM_CTRL2_MMSEL2)); + /* Select the TRGO2 source */ + TIMx->CTRL2 |= TIM_TRGO2Source; +} + +/** +*\*\name TIM_SelectSlaveMode +*\*\fun Selects the TIMx Slave Mode. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_SlaveMode +*\*\ - TIM_SLAVE_MODE_DISABLE +*\*\ - TIM_SLAVE_MODE_RESET +*\*\ - TIM_SLAVE_MODE_GATED +*\*\ - TIM_SLAVE_MODE_TRIG +*\*\ - TIM_SLAVE_MODE_EXT1 +*\*\ - TIM_SLAVE_MODE_GATED_RESET +*\*\ - TIM_SLAVE_MODE_TRIG_RESET +*\*\return none +**/ +void TIM_SelectSlaveMode(TIM_Module* TIMx, uint32_t TIM_SlaveMode) +{ + /* Reset the SMSEL Bits */ + TIMx->SMCTRL &= (uint32_t)(~((uint32_t)TIM_SMCTRL_SMSEL)); + /* Select the Slave Mode */ + TIMx->SMCTRL |= (uint32_t)TIM_SlaveMode; +} + +/** +*\*\name TIM_SelectMasterSlaveMode +*\*\fun Sets or Resets the TIMx Master/Slave Mode. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_SlaveMode +*\*\ - TIM_MASTER_SLAVE_MODE_ENABLE +*\*\ - TIM_MASTER_SLAVE_MODE_DISABLE +*\*\return none +**/ +void TIM_SelectMasterSlaveMode(TIM_Module* TIMx, uint32_t TIM_MasterSlaveMode) +{ + /* Reset the MSMD Bit */ + TIMx->SMCTRL &= (uint32_t)(~((uint32_t)TIM_SMCTRL_MSMD)); + /* Set or Reset the MSMD Bit */ + TIMx->SMCTRL |= (uint32_t)TIM_MasterSlaveMode; +} + +/** +*\*\name TIM_SetCnt +*\*\fun Sets the TIMx Counter Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param Counter +*\*\ - Counter can be a number between 0x00000000 and 0xFFFFFFFF +*\*\return none +**/ +void TIM_SetCnt(TIM_Module* TIMx, uint32_t Counter) +{ + /* Set the Counter Register value */ + TIMx->CNT = (uint32_t)((uint32_t)Counter); +} + +/** +*\*\name TIM_SetAutoReload +*\*\fun Sets the TIMx Autoreload Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param Autoreload +*\*\ - Autoreload can be a number between 0x00000000 and 0xFFFFFFFF +*\*\return none +**/ +void TIM_SetAutoReload(TIM_Module* TIMx, uint32_t Autoreload) +{ + /* Set the Autoreload Register value */ + TIMx->AR = (uint32_t)((uint32_t)Autoreload); +} + +/** +*\*\name TIM_SetCmp1 +*\*\fun Sets the TIMx Capture Compare1 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Compare1 +*\*\ - Compare1 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp1(TIM_Module* TIMx, uint16_t Compare1) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT1 ; + /* Reset the Capture Compare1 Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT1_CCDAT1); + tmpccdatx |= (uint32_t)Compare1; + /* Set the Capture Compare1 Register value */ + TIMx->CCDAT1 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp2 +*\*\fun Sets the TIMx Capture Compare2 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Compare2 +*\*\ - Compare2 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp2(TIM_Module* TIMx, uint16_t Compare2) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT2 ; + /* Reset the Capture Compare2 Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT2_CCDAT2); + tmpccdatx |= (uint32_t)Compare2; + /* Set the Capture Compare2 Register value */ + TIMx->CCDAT2 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp3 +*\*\fun Sets the TIMx Capture Compare3 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Compare3 +*\*\ - Compare3 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp3(TIM_Module* TIMx, uint16_t Compare3) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT3 ; + /* Reset the Capture Compare3 Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT3_CCDAT3); + tmpccdatx |= (uint32_t)Compare3; + /* Set the Capture Compare3 Register value */ + TIMx->CCDAT3 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp4 +*\*\fun Sets the TIMx Capture Compare4 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Compare4 +*\*\ - Compare4 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp4(TIM_Module* TIMx, uint16_t Compare4) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT4 ; + /* Reset the Capture Compare4 Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT4_CCDAT4); + tmpccdatx |= (uint32_t)Compare4; + /* Set the Capture Compare4 Register value */ + TIMx->CCDAT4 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp5 +*\*\fun Sets the TIMx Capture Compare5 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Compare5 +*\*\ - Compare5 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp5(TIM_Module* TIMx, uint16_t Compare5) +{ + /* Set the Capture Compare5 Register value */ + TIMx->CCDAT5 = (uint32_t)Compare5; +} + +/** +*\*\name TIM_SetCmp6 +*\*\fun Sets the TIMx Capture Compare6 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param Compare6 +*\*\ - Compare6 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp6(TIM_Module* TIMx, uint16_t Compare6) +{ + /* Set the Capture Compare6 Register value */ + TIMx->CCDAT6 = (uint32_t)Compare6; +} + +/** +*\*\name TIM_SetCmp7 +*\*\fun Sets the TIMx Capture Compare7 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param Compare7 +*\*\ - Compare7 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp7(TIM_Module* TIMx, uint16_t Compare7) +{ + /* Set the Capture Compare7 Register value */ + TIMx->CCDAT7 = (uint32_t)Compare7; +} + +/** +*\*\name TIM_SetCmp8 +*\*\fun Sets the TIMx Capture Compare8 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param Compare8 +*\*\ - Compare8 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp8(TIM_Module* TIMx, uint16_t Compare8) +{ + /* Set the Capture Compare8 Register value */ + TIMx->CCDAT8 = (uint32_t)Compare8; +} + +/** +*\*\name TIM_SetCmp9 +*\*\fun Sets the TIMx Capture Compare9 Register value +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param Compare9 +*\*\ - Compare9 can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp9(TIM_Module* TIMx, uint16_t Compare9) +{ + /* Set the Capture Compare9 Register value */ + TIMx->CCDAT9 = (uint32_t)Compare9; +} + +/** +*\*\name TIM_SetCmp1D +*\*\fun Sets the CCDDAT1[16:31] in TIM1_CCDAT1 register +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param compare1D +*\*\ - compare1D can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp1D(TIM_Module* TIMx, uint16_t compare1D) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT1 ; + /* Reset the Capture compare1D Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT1_CCDDAT1); + tmpccdatx |= (uint32_t)(((uint32_t)compare1D) << 0x00000010); + /* Set the Capture compare1D Register value */ + TIMx->CCDAT1 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp2D +*\*\fun Sets the CCDDAT2[16:31] in TIM1_CCDAT2 register +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param compare2D +*\*\ - compare2D can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp2D(TIM_Module* TIMx, uint16_t compare2D) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT2 ; + /* Reset the Capture compare2D Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT2_CCDDAT2); + tmpccdatx |= (uint32_t)(((uint32_t)compare2D) << 0x00000010); + /* Set the Capture compare2D Register value */ + TIMx->CCDAT2 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp3D +*\*\fun Sets the CCDDAT3[16:31] in TIM1_CCDAT3 register +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param compare3D +*\*\ - compare3D can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp3D(TIM_Module* TIMx, uint16_t compare3D) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT3 ; + /* Reset the Capture compare3D Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT3_CCDDAT3); + tmpccdatx |= (uint32_t)(((uint32_t)compare3D) << 0x00000010); + /* Set the Capture compare3D Register value */ + TIMx->CCDAT3 = tmpccdatx; +} + +/** +*\*\name TIM_SetCmp4D +*\*\fun Sets the CCDDAT4[16:31] in TIM1_CCDAT4 register +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param compare4D +*\*\ - compare4D can be a number between 0x0000 and 0xFFFF +*\*\return none +**/ +void TIM_SetCmp4D(TIM_Module* TIMx, uint16_t compare4D) +{ + uint32_t tmpccdatx ; + tmpccdatx = TIMx->CCDAT4 ; + /* Reset the Capture compare4D Register value */ + tmpccdatx &= (uint32_t)(~TIM_CCDAT4_CCDDAT4); + tmpccdatx |= (uint32_t)(((uint32_t)compare4D) << 0x00000010); + /* Set the Capture compare4D Register value */ + TIMx->CCDAT4 = tmpccdatx; +} + +/** +*\*\name ConfigTI1 +*\*\fun Configure the TI1 as Input. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPolarity +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param ICSelection +*\*\ - TIM_IC_SELECTION_DIRECTTI +*\*\ - TIM_IC_SELECTION_INDIRECTTI +*\*\ - TIM_IC_SELECTION_TRC +*\*\param ICFilter +*\*\ - ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void ConfigTI1(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen ; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC1EN)); + + /* Get the TIMx_CCMOD1 and TIMx_CCEN register value */ + tmpccmodx = TIMx->CCMOD1; + tmpccen = TIMx->CCEN; + + /* Select the Input and set the filter */ + tmpccmodx &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCMOD1_CC1SEL)) & ((uint32_t) ~((uint32_t)TIM_CCMOD1_IC1F))); + tmpccmodx |= (uint32_t)(ICSelection | (uint32_t)(ICFilter << (uint32_t)4)); + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccen &= (uint32_t)(~((uint32_t)(TIM_CCEN_CC1P))); + tmpccen |= (uint32_t)(ICPolarity | (uint32_t)TIM_CCEN_CC1EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmodx; + TIMx->CCEN = tmpccen; +} + +/** +*\*\name ConfigTI2 +*\*\fun Configure the TI2 as Input. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPolarity +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param ICSelection +*\*\ - TIM_IC_SELECTION_DIRECTTI +*\*\ - TIM_IC_SELECTION_INDIRECTTI +*\*\ - TIM_IC_SELECTION_TRC +*\*\param ICFilter +*\*\ - ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void ConfigTI2(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmp ; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC2EN)); + + /* Get the TIMx_CCMOD1 and TIMx_CCEN register value */ + tmpccmodx = TIMx->CCMOD1; + tmpccen = TIMx->CCEN; + + tmp = (uint32_t)(ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmodx &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCMOD1_CC2SEL)) & ((uint32_t) ~((uint32_t)TIM_CCMOD1_IC2F))); + tmpccmodx |= (uint32_t)(ICFilter << 12); + tmpccmodx |= (uint32_t)(ICSelection << 8); + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccen &= (uint32_t)(~((uint32_t)(TIM_CCEN_CC2P))); + tmpccen |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC2EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = tmpccmodx; + TIMx->CCEN = tmpccen; +} + +/** +*\*\name ConfigTI3 +*\*\fun Configure the TI3 as Input. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPolarity +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param ICSelection +*\*\ - TIM_IC_SELECTION_DIRECTTI +*\*\ - TIM_IC_SELECTION_INDIRECTTI +*\*\ - TIM_IC_SELECTION_TRC +*\*\param ICFilter +*\*\ - ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void ConfigTI3(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmp ; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC3EN)); + + /* Get the TIMx_CCMOD2 and TIMx_CCEN register value */ + tmpccmodx = TIMx->CCMOD2; + tmpccen = TIMx->CCEN; + + tmp = (uint32_t)(ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmodx &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_CCMOD2_CC3SEL)) & ((uint32_t) ~((uint32_t)TIM_CCMOD2_IC3F))); + tmpccmodx |= (uint32_t)(ICSelection | (uint32_t)(ICFilter << (uint32_t)4)); + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccen &= (uint32_t)(~((uint32_t)(TIM_CCEN_CC3P))); + tmpccen |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC3EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmodx; + TIMx->CCEN = tmpccen; +} + +/** +*\*\name ConfigTI4 +*\*\fun Configure the TI4 as Input. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPolarity +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param ICSelection +*\*\ - TIM_IC_SELECTION_DIRECTTI +*\*\ - TIM_IC_SELECTION_INDIRECTTI +*\*\ - TIM_IC_SELECTION_TRC +*\*\param ICFilter +*\*\ - ICFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void ConfigTI4(TIM_Module* TIMx, uint32_t ICPolarity, uint32_t ICSelection, uint32_t ICFilter) +{ + uint32_t tmpccmodx ; + uint32_t tmpccen, tmp ; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t)(~((uint32_t)TIM_CCEN_CC4EN)); + + /* Get the TIMx_CCMOD2 and TIMx_CCEN register value */ + tmpccmodx = TIMx->CCMOD2; + tmpccen = TIMx->CCEN; + + tmp = (uint32_t)(ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmodx &= (uint32_t)((uint32_t)(~(uint32_t)TIM_CCMOD2_CC4SEL) & ((uint32_t) ~((uint32_t)TIM_CCMOD2_IC4F))); + tmpccmodx |= (uint32_t)(ICSelection << 8); + tmpccmodx |= (uint32_t)(ICFilter << 12); + + if ((IS_ATIM1_4_DEVICE(TIMx)) || (IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccen &= (uint32_t)(~((uint32_t)(TIM_CCEN_CC4P))); + tmpccen |= (uint32_t)(tmp | (uint32_t)TIM_CCEN_CC4EN); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccen &= (uint32_t)(~((uint32_t)(TIM_CCEN_CC4P))); + tmpccen |= (uint32_t)(ICPolarity | (uint32_t)TIM_CCEN_CC4EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = tmpccmodx; + TIMx->CCEN = tmpccen; +} + +/** +*\*\name TIM_SetInCap1Prescaler +*\*\fun Sets the TIMx Input Capture 1 prescaler. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPrescaler +*\*\ - TIM_IC_PSC_DIV1 +*\*\ - TIM_IC_PSC_DIV2 +*\*\ - TIM_IC_PSC_DIV4 +*\*\ - TIM_IC_PSC_DIV8 +*\*\return none +**/ +void TIM_SetInCap1Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler) +{ + /* Reset the IC1PSC Bits */ + TIMx->CCMOD1 &= (uint32_t)(~TIM_CCMOD1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= (uint32_t)ICPrescaler; +} + +/** +*\*\name TIM_SetInCap2Prescaler +*\*\fun Sets the TIMx Input Capture 2 prescaler. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPrescaler +*\*\ - TIM_IC_PSC_DIV1 +*\*\ - TIM_IC_PSC_DIV2 +*\*\ - TIM_IC_PSC_DIV4 +*\*\ - TIM_IC_PSC_DIV8 +*\*\return none +**/ +void TIM_SetInCap2Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler) +{ + /* Reset the IC2PSC Bits */ + TIMx->CCMOD1 &= (uint32_t)(~TIM_CCMOD1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMOD1 |= (uint32_t)(ICPrescaler << 8); +} + +/** +*\*\name TIM_SetInCap3Prescaler +*\*\fun Sets the TIMx Input Capture 3 prescaler. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPrescaler +*\*\ - TIM_IC_PSC_DIV1 +*\*\ - TIM_IC_PSC_DIV2 +*\*\ - TIM_IC_PSC_DIV4 +*\*\ - TIM_IC_PSC_DIV8 +*\*\return none +**/ +void TIM_SetInCap3Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler) +{ + /* Reset the IC3PSC Bits */ + TIMx->CCMOD2 &= (uint32_t)(~TIM_CCMOD2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMOD2 |= (uint32_t)ICPrescaler; +} + +/** +*\*\name TIM_SetInCap4Prescaler +*\*\fun Sets the TIMx Input Capture 4 prescaler. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param ICPrescaler +*\*\ - TIM_IC_PSC_DIV1 +*\*\ - TIM_IC_PSC_DIV2 +*\*\ - TIM_IC_PSC_DIV4 +*\*\ - TIM_IC_PSC_DIV8 +*\*\return none +**/ +void TIM_SetInCap4Prescaler(TIM_Module* TIMx, uint32_t ICPrescaler) +{ + /* Reset the IC4PSC Bits */ + TIMx->CCMOD2 &= (uint32_t)(~TIM_CCMOD2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMOD2 |= (uint32_t)(ICPrescaler << 8); +} + +/** +*\*\name TIM_SelectInputTrig +*\*\fun Selects the Input Trigger source +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_InputTriggerSource: +*\*\ - TIM_TRIG_SEL_IN_TR0 +*\*\ - TIM_TRIG_SEL_IN_TR1 +*\*\ - TIM_TRIG_SEL_IN_TR2 +*\*\ - TIM_TRIG_SEL_IN_TR3 +*\*\ - TIM_TRIG_SEL_IN_TR4 +*\*\ - TIM_TRIG_SEL_IN_TR5 +*\*\ - TIM_TRIG_SEL_IN_TR6 +*\*\ - TIM_TRIG_SEL_IN_TR7 +*\*\ - TIM_TRIG_SEL_IN_TR8 +*\*\ - TIM_TRIG_SEL_IN_TR9 +*\*\ - TIM_TRIG_SEL_IN_TR10 +*\*\ - TIM_TRIG_SEL_IN_TR11 +*\*\ - TIM_TRIG_SEL_IN_TR12 +*\*\ - TIM_TRIG_SEL_IN_TR13 +*\*\ - TIM_TRIG_SEL_IN_TR14 +*\*\ - TIM_TRIG_SEL_TI1F_ED +*\*\ - TIM_TRIG_SEL_TI1FP1 +*\*\ - TIM_TRIG_SEL_TI2FP2 +*\*\ - TIM_TRIG_SEL_ETRF +*\*\return none +**/ +void TIM_SelectInputTrig(TIM_Module* TIMx, uint32_t TIM_InputTriggerSource) +{ + uint32_t tmpsmctrl ; + uint32_t tmpinsel ; + /* Get the TIMx SMCTRL and TIMx INSEL register value */ + tmpsmctrl = TIMx->SMCTRL; + tmpinsel = TIMx->INSEL; + + /* Reset the TS Bits */ + tmpsmctrl &= (uint32_t)(~((uint32_t)TIM_SMCTRL_TSEL)); + /* Reset the ITRS Bits */ + tmpinsel &= (uint32_t)(~((uint32_t)TIM_INSEL_ITRS)); + + if (IS_ITR_SEL(TIM_InputTriggerSource)) + { + /* Set the Input Trigger source */ + tmpinsel |= (uint32_t)TIM_InputTriggerSource; + } + else + { + /* Set the Input Trigger source */ + tmpsmctrl |= (uint32_t)TIM_InputTriggerSource; + + } + + /* Write to TIMx SMCTRL and INSEL */ + TIMx->SMCTRL = tmpsmctrl; + TIMx->INSEL = tmpinsel; +} + +/** +*\*\name TIM_ConfigExtTrig +*\*\fun Configures the TIMx External Trigger (ETR). +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ExtTRGPrescaler: +*\*\ - TIM_EXT_TRG_PSC_OFF +*\*\ - TIM_EXT_TRG_PSC_DIV2 +*\*\ - TIM_EXT_TRG_PSC_DIV4 +*\*\ - TIM_EXT_TRG_PSC_DIV8 +*\*\param TIM_ExtTRGPolarity +*\*\ - TIM_EXT_TRIG_POLARITY_INVERTED +*\*\ - TIM_EXT_TRIG_POLARITY_NONINVERTED +*\*\param ExtTRGFilter +*\*\ - ExtTRGFilter can be a number between 0x0 and 0xF +*\*\return none +**/ +void TIM_ConfigExtTrig(TIM_Module* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmctrl ; + tmpsmctrl = TIMx->SMCTRL; + /* Reset the ETR Bits */ + tmpsmctrl &= (uint32_t)(~(TIM_SMCTRL_EXTPS | TIM_SMCTRL_EXTP | TIM_SMCTRL_EXTF)); + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmctrl |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << (uint32_t)12))); + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = tmpsmctrl; +} + +/** +*\*\name TIM_SelectETRInputSource +*\*\fun Configures the source of tim_etr_in. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_ETRInputSource: +*\*\ - TIM_CAPETRSEL_0 +*\*\ - TIM_CAPETRSEL_1 +*\*\ - TIM_CAPETRSEL_2 +*\*\ - TIM_CAPETRSEL_3 +*\*\ - TIM_CAPETRSEL_4 +*\*\ - TIM_CAPETRSEL_5 +*\*\ - TIM_CAPETRSEL_6 +*\*\ - TIM_CAPETRSEL_7 +*\*\ - TIM_CAPETRSEL_8 +*\*\ - TIM_CAPETRSEL_10 +*\*\ - TIM_CAPETRSEL_11 +*\*\ - TIM_CAPETRSEL_12 +*\*\ - TIM_CAPETRSEL_13 +*\*\return none +**/ +void TIM_SelectETRInputSource(TIM_Module* TIMx, uint32_t TIM_ETRInputSource) +{ + uint32_t tmpinsel ; + tmpinsel = TIMx->INSEL; + /* Reset the ETRS Bits */ + tmpinsel &= (uint32_t)(~TIM_INSEL_ETRS); + /* Set the ETRS Bits */ + tmpinsel |= (uint32_t)TIM_ETRInputSource; + /* Write to TIMx SMCTRL */ + TIMx->INSEL = tmpinsel; +} + +/** +*\*\name TIM_SetClkDiv +*\*\fun Sets the TIMx Clock Division value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_CKD: +*\*\ - TIM_CLK_DIV1 +*\*\ - TIM_CLK_DIV2 +*\*\ - TIM_CLK_DIV4 +*\*\return none +**/ +void TIM_SetClkDiv(TIM_Module* TIMx, uint32_t TIM_CKD) +{ + /* Reset the CKD Bits */ + TIMx->CTRL1 &= (uint32_t)(~TIM_CTRL1_CLKD); + /* Set the CKD value */ + TIMx->CTRL1 |= (uint32_t)TIM_CKD; +} + +/** +*\*\name TIM_GetCap1 +*\*\fun Gets the TIMx Input Capture 1 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return Capture Compare 1 Register value. +**/ +uint16_t TIM_GetCap1(TIM_Module* TIMx) +{ + /* Get the Capture 1 Register value */ + return (uint16_t)(TIMx->CCDAT1); +} + +/** +*\*\name TIM_GetCap2 +*\*\fun Gets the TIMx Input Capture 2 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return Capture Compare 2 Register value. +**/ +uint16_t TIM_GetCap2(TIM_Module* TIMx) +{ + /* Get the Capture 2 Register value */ + return (uint16_t)(TIMx->CCDAT2); +} + +/** +*\*\name TIM_GetCap3 +*\*\fun Gets the TIMx Input Capture 3 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return Capture Compare 3 Register value. +**/ +uint16_t TIM_GetCap3(TIM_Module* TIMx) +{ + /* Get the Capture 3 Register value */ + return (uint16_t)(TIMx->CCDAT3); +} + +/** +*\*\name TIM_GetCap4 +*\*\fun Gets the TIMx Input Capture 4 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return Capture Compare 4 Register value. +**/ +uint16_t TIM_GetCap4(TIM_Module* TIMx) +{ + /* Get the Capture 4 Register value */ + return (uint16_t)(TIMx->CCDAT4); +} + +/** +*\*\name TIM_GetCap5 +*\*\fun Gets the TIMx Input Capture 5 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\return Capture Compare 5 Register value. +**/ +uint16_t TIM_GetCap5(TIM_Module* TIMx) +{ + /* Get the Capture 5 Register value */ + return (uint16_t)(TIMx->CCDAT5); +} + + +/** +*\*\name TIM_GetCap6 +*\*\fun Gets the TIMx Input Capture 6 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 6 Register value. +**/ +uint16_t TIM_GetCap6(TIM_Module* TIMx) +{ + /* Get the Capture 1 Register value */ + return (uint16_t)(TIMx->CCDAT6); +} + +/** +*\*\name TIM_GetCap7 +*\*\fun Gets the TIMx Input Capture 7 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 7 Register value. +**/ +uint16_t TIM_GetCap7(TIM_Module* TIMx) +{ + /* Get the Capture 7 Register value */ + return (uint16_t)(TIMx->CCDAT7); +} + +/** +*\*\name TIM_GetCap8 +*\*\fun Gets the TIMx Input Capture 8 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 8 Register value. +**/ +uint16_t TIM_GetCap8(TIM_Module* TIMx) +{ + /* Get the Capture 8 Register value */ + return (uint16_t)(TIMx->CCDAT8); +} + +/** +*\*\name TIM_GetCap9 +*\*\fun Gets the TIMx Input Capture 9 value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 9 Register value. +**/ +uint16_t TIM_GetCap9(TIM_Module* TIMx) +{ + /* Get the Capture 9 Register value */ + return (uint16_t)(TIMx->CCDAT9); +} + +/** +*\*\name TIM_GetCap1D +*\*\fun Gets the TIMx Input Capture 1D value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 1D Register value. +**/ +uint16_t TIM_GetCap1D(TIM_Module* TIMx) +{ + /* Get the Capture 1D Register value */ + return (uint16_t)((TIMx->CCDAT1) >> 0x00000010); +} + +/** +*\*\name TIM_GetCap2D +*\*\fun Gets the TIMx Input Capture 2D value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 2D Register value. +**/ +uint16_t TIM_GetCap2D(TIM_Module* TIMx) +{ + /* Get the Capture 2D Register value */ + return (uint16_t)((TIMx->CCDAT2) >> 0x00000010); +} + +/** +*\*\name TIM_GetCap3D +*\*\fun Gets the TIMx Input Capture 3D value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 3D Register value. +**/ +uint16_t TIM_GetCap3D(TIM_Module* TIMx) +{ + /* Get the Capture 3D Register value */ + return (uint16_t)((TIMx->CCDAT3) >> 0x00000010); +} + +/** +*\*\name TIM_GetCap4D +*\*\fun Gets the TIMx Input Capture 4D value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\return Capture Compare 4D Register value. +**/ +uint16_t TIM_GetCap4D(TIM_Module* TIMx) +{ + /* Get the Capture 4D Register value */ + return (uint16_t)((TIMx->CCDAT4) >> 0x00000010); +} + +/** +*\*\name TIM_GetCnt +*\*\fun Gets the TIMx Counter value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\return Counter Register value. +**/ +uint32_t TIM_GetCnt(TIM_Module* TIMx) +{ + /* Get the Counter Register value */ + return (uint32_t)(TIMx->CNT); +} + +/** +*\*\name TIM_GetPrescaler +*\*\fun Gets the TIMx Prescaler value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\return Prescaler Register value. +**/ +uint16_t TIM_GetPrescaler(TIM_Module* TIMx) +{ + /* Get the Prescaler Register value */ + return (uint16_t)(TIMx->PSC); +} + +/** +*\*\name TIM_GetAutoReload +*\*\fun Gets the TIMx AR value. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\return AR Register value. +**/ +uint32_t TIM_GetAutoReload(TIM_Module* TIMx) +{ + /* Get the Prescaler Register value */ + return (uint32_t)(TIMx->AR); +} + +/** +*\*\name TIM_GetCCENStatus +*\*\fun Checks whether the specified TIM flag is set or not. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_CCEN : +*\*\ - TIM_CC1EN +*\*\ - TIM_CC1NEN +*\*\ - TIM_CC2EN +*\*\ - TIM_CC2NEN +*\*\ - TIM_CC3EN +*\*\ - TIM_CC3NEN +*\*\ - TIM_CC4EN +*\*\ - TIM_CC4NEN +*\*\ - TIM_CC5EN +*\*\ - TIM_CC6EN +*\*\return The new state of TIM_FLAG (SET or RESET). +**/ +FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN) +{ + FlagStatus bitstatus; + + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + bitstatus = SET; + } + + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name TIM_GetFlagStatus +*\*\fun Checks whether the specified TIM flag is set or not. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_FLAG : +*\*\ - TIM_FLAG_UPDATE +*\*\ - TIM_FLAG_CC1 +*\*\ - TIM_FLAG_CC2 +*\*\ - TIM_FLAG_CC3 +*\*\ - TIM_FLAG_CC4 +*\*\ - TIM_FLAG_CC5 +*\*\ - TIM_FLAG_CC6 +*\*\ - TIM_FLAG_CC7 +*\*\ - TIM_FLAG_CC8 +*\*\ - TIM_FLAG_CC9 +*\*\ - TIM_FLAG_COM +*\*\ - TIM_FLAG_TRIG +*\*\ - TIM_FLAG_BREAK +*\*\ - TIM_FLAG_BREAK2 +*\*\ - TIM_FLAG_SYS_BREAK +*\*\ - TIM_FLAG_CC1OF +*\*\ - TIM_FLAG_CC2OF +*\*\ - TIM_FLAG_CC3OF +*\*\ - TIM_FLAG_CC4OF +*\*\return The new state of TIM_FLAG (SET or RESET). +**/ +FlagStatus TIM_GetFlagStatus(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + FlagStatus bitstatus; + + if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name TIM_ClearFlag +*\*\fun Clears the TIMx's pending flags. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_FLAG : +*\*\ - TIM_FLAG_UPDATE +*\*\ - TIM_FLAG_CC1 +*\*\ - TIM_FLAG_CC2 +*\*\ - TIM_FLAG_CC3 +*\*\ - TIM_FLAG_CC4 +*\*\ - TIM_FLAG_CC5 +*\*\ - TIM_FLAG_CC6 +*\*\ - TIM_FLAG_CC7 +*\*\ - TIM_FLAG_CC8 +*\*\ - TIM_FLAG_CC9 +*\*\ - TIM_FLAG_COM +*\*\ - TIM_FLAG_TRIG +*\*\ - TIM_FLAG_BREAK +*\*\ - TIM_FLAG_BREAK2 +*\*\ - TIM_FLAG_SYS_BREAK +*\*\ - TIM_FLAG_CC1OF +*\*\ - TIM_FLAG_CC2OF +*\*\ - TIM_FLAG_CC3OF +*\*\ - TIM_FLAG_CC4OF +*\*\return none. +**/ +void TIM_ClearFlag(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + /* Clear the flags */ + TIMx->STS = (uint32_t)(~TIM_FLAG); +} + +/** +*\*\name TIM_GetIntStatus +*\*\fun Checks whether the TIM interrupt has occurred or not. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_IT : +*\*\ - TIM_INT_UPDATE +*\*\ - TIM_INT_CC1 +*\*\ - TIM_INT_CC2 +*\*\ - TIM_INT_CC3 +*\*\ - TIM_INT_CC4 +*\*\ - TIM_INT_CC5 +*\*\ - TIM_INT_CC6 +*\*\ - TIM_INT_CC7 +*\*\ - TIM_INT_CC8 +*\*\ - TIM_INT_CC9 +*\*\ - TIM_INT_COM +*\*\ - TIM_INT_TRIG +*\*\ - TIM_INT_BREAK +*\*\ - TIM_INT_BREAK2 +*\*\ - TIM_INT_SYS_BREAK +*\*\return The new state of the TIM_IT(SET or RESET). +**/ +INTStatus TIM_GetIntStatus(TIM_Module* TIMx, uint32_t TIM_IT) +{ + INTStatus bitstatus; + uint32_t itstatus = 0x0, itenable; + + if(TIM_IT == TIM_INT_UPDATE) + { + itstatus = TIMx->STS & TIM_FLAG_UPDATE; + } + else if(TIM_IT == TIM_INT_CC1) + { + itstatus = TIMx->STS & TIM_FLAG_CC1; + } + else if(TIM_IT == TIM_INT_CC2) + { + itstatus = TIMx->STS & TIM_FLAG_CC2; + } + else if(TIM_IT == TIM_INT_CC3) + { + itstatus = TIMx->STS & TIM_FLAG_CC3; + } + else if(TIM_IT == TIM_INT_CC4) + { + itstatus = TIMx->STS & TIM_FLAG_CC4; + } + else if(TIM_IT == TIM_INT_CC5) + { + itstatus = TIMx->STS & TIM_FLAG_CC5; + } + else if(TIM_IT == TIM_INT_CC6) + { + itstatus = TIMx->STS & TIM_FLAG_CC6; + } + else if(TIM_IT == TIM_INT_CC7) + { + itstatus = TIMx->STS & TIM_FLAG_CC7; + } + else if(TIM_IT == TIM_INT_CC8) + { + itstatus = TIMx->STS & TIM_FLAG_CC8; + } + else if(TIM_IT == TIM_INT_CC9) + { + itstatus = TIMx->STS & TIM_FLAG_CC9; + } + else if(TIM_IT == TIM_INT_COM) + { + itstatus = TIMx->STS & TIM_FLAG_COM; + } + else if(TIM_IT == TIM_INT_TRIG) + { + itstatus = TIMx->STS & TIM_FLAG_TRIG; + } + else if(TIM_IT == TIM_INT_BREAK) + { + itstatus = TIMx->STS & TIM_FLAG_BREAK; + } + else if(TIM_IT == TIM_INT_BREAK2) + { + itstatus = TIMx->STS & TIM_FLAG_BREAK2; + } + else if(TIM_IT == TIM_INT_SYS_BREAK) + { + itstatus = TIMx->STS & TIM_FLAG_SYS_BREAK; + } + else + { + + } + + if((TIM_IT == TIM_INT_BREAK) || (TIM_IT == TIM_INT_BREAK2) || (TIM_IT == TIM_INT_SYS_BREAK)) + { + itenable = TIMx->DINTEN & TIM_INT_BREAK; + } + else + { + itenable = TIMx->DINTEN & TIM_IT; + } + + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name TIM_ClrIntPendingBit +*\*\fun Clears the TIMx's interrupt pending bits. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\ - BTIM1 +*\*\ - BTIM2 +*\*\ - BTIM3 +*\*\ - BTIM4 +*\*\param TIM_IT : +*\*\ - TIM_INT_UPDATE +*\*\ - TIM_INT_CC1 +*\*\ - TIM_INT_CC2 +*\*\ - TIM_INT_CC3 +*\*\ - TIM_INT_CC4 +*\*\ - TIM_INT_CC5 +*\*\ - TIM_INT_CC6 +*\*\ - TIM_INT_CC7 +*\*\ - TIM_INT_CC8 +*\*\ - TIM_INT_CC9 +*\*\ - TIM_INT_COM +*\*\ - TIM_INT_TRIG +*\*\ - TIM_INT_BREAK +*\*\ - TIM_INT_BREAK2 +*\*\ - TIM_INT_SYS_BREAK +*\*\return none. +**/ +void TIM_ClrIntPendingBit(TIM_Module* TIMx, uint32_t TIM_IT) +{ + /* Clear the IT pending Bit */ + if(TIM_IT == TIM_INT_UPDATE) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_UPDATE); + } + else if(TIM_IT == TIM_INT_CC1) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC1); + } + else if(TIM_IT == TIM_INT_CC2) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC2); + } + else if(TIM_IT == TIM_INT_CC3) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC3); + } + else if(TIM_IT == TIM_INT_CC4) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC4); + } + else if(TIM_IT == TIM_INT_CC5) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC5); + } + else if(TIM_IT == TIM_INT_CC6) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC6); + } + else if(TIM_IT == TIM_INT_CC7) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC7); + } + else if(TIM_IT == TIM_INT_CC8) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC8); + } + else if(TIM_IT == TIM_INT_CC9) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_CC9); + } + else if(TIM_IT == TIM_INT_COM) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_COM); + } + else if(TIM_IT == TIM_INT_TRIG) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_TRIG); + } + else if(TIM_IT == TIM_INT_BREAK) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_BREAK); + } + else if(TIM_IT == TIM_INT_BREAK2) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_BREAK2); + } + else if(TIM_IT == TIM_INT_SYS_BREAK) + { + TIMx->STS = (uint32_t)(~TIM_FLAG_SYS_BREAK); + } + else + { + + } +} + +/** +*\*\name TIM_SelectCenterAlignTrig. +*\*\fun Setting the trigger mode in central alignment mode. +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param TIM_CenterAlignTriggerSource +*\*\ - TIM_UP_COUNTING +*\*\ - TIM_DOWN_COUNTING +*\*\ - TIM_UP_DOWN_COUNTING +*\*\return none +**/ +void TIM_SelectCenterAlignTrig(TIM_Module* TIMx, uint32_t TIM_CenterAlignTriggerSource) +{ + uint32_t temp_value ; + + temp_value = TIMx->CTRL1; + /* Reset the CMODE Bits */ + temp_value &= (uint32_t)(~((uint32_t)TIM_CTRL1_CMODE)); + /* Set the trigger source */ + temp_value |= (uint32_t)TIM_CenterAlignTriggerSource; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = temp_value; +} + +/** +*\*\name TIM_Asymmetric_Enable. +*\*\fun Enable or disable asymmetric mode in center-aligned. +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_AsymmetricEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the ASMMETRIC Bit */ + TIMx->CTRL1 |= (uint32_t)TIM_CTRL1_ASMMETRIC; + } + else + { + /* Reset the ASMMETRIC Bit */ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_CTRL1_ASMMETRIC)); + } +} + +/** +*\*\name TIM_OCxRefTriggerADC. +*\*\fun Enable or disable OCxREF to trigger ADC(x = 4,7,8 or 9). +*\*\param TIMx: +*\*\ - ATIM1 +*\*\ - ATIM2 +*\*\ - ATIM3 +*\*\ - ATIM4 +*\*\param OCxRef +*\*\ - TIM_CTRL2_TRIG4 +*\*\ - TIM_CTRL2_TRIG7 +*\*\ - TIM_CTRL2_TRIG8 +*\*\ - TIM_CTRL2_TRIG9 +*\*\param Cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_OCxRefTriggerADC(TIM_Module* TIMx, uint32_t OCxRef, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Set the TRIGx Bit */ + TIMx->CTRL2 |= (uint32_t)OCxRef; + } + else + { + /* Reset the TRIGx Bit */ + TIMx->CTRL2 &= (uint32_t)(~((uint32_t)OCxRef)); + } +} + +/** +*\*\name TIM_IC1FiltConfig +*\*\fun Config the filter of channel1. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_FiltInitStruct: +*\*\ - refer to the definition of TIM_FiltInitType +*\*\return none +**/ +void TIM_IC1FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct) +{ + uint32_t temp_chxfilt = 0; + + temp_chxfilt &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_C1FILT_THRESH)) & + ((uint32_t) ~((uint32_t)TIM_C1FILT_WSIZE)) & + ((uint32_t) ~((uint32_t)TIM_C1FILT_SFPSC))); + + temp_chxfilt |= (uint32_t)((TIM_FiltInitStruct->ThreshHold << (uint32_t)(0x18)) | + (TIM_FiltInitStruct->WindowSize << (uint32_t)(0x11)) | + (TIM_FiltInitStruct->Prescaler)); + + if ((IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + TIMx->C1FILT = temp_chxfilt; + } + else + { + /* none */ + } +} + +/** +*\*\name TIM_IC2FiltConfig +*\*\fun Config the filter of channel2. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_FiltInitStruct: +*\*\ - refer to the definition of TIM_FiltInitType +*\*\return none +**/ +void TIM_IC2FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct) +{ + uint32_t temp_chxfilt = 0; + + temp_chxfilt &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_C2FILT_THRESH)) & + ((uint32_t) ~((uint32_t)TIM_C2FILT_WSIZE)) & + ((uint32_t) ~((uint32_t)TIM_C2FILT_SFPSC))); + + temp_chxfilt |= (uint32_t)((TIM_FiltInitStruct->ThreshHold << (uint32_t)(0x18)) | + (TIM_FiltInitStruct->WindowSize << (uint32_t)(0x11)) | + (TIM_FiltInitStruct->Prescaler)); + + if ((IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + TIMx->C2FILT = temp_chxfilt; + } + else + { + /* none */ + } +} + +/** +*\*\name TIM_IC3FiltConfig +*\*\fun Config the filter of channel3. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_FiltInitStruct: +*\*\ - refer to the definition of TIM_FiltInitType +*\*\return none +**/ +void TIM_IC3FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct) +{ + uint32_t temp_chxfilt = 0; + + temp_chxfilt &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_C3FILT_THRESH)) & + ((uint32_t) ~((uint32_t)TIM_C3FILT_WSIZE)) & + ((uint32_t) ~((uint32_t)TIM_C3FILT_SFPSC))); + + temp_chxfilt |= (uint32_t)((TIM_FiltInitStruct->ThreshHold << (uint32_t)(0x18)) | + (TIM_FiltInitStruct->WindowSize << (uint32_t)(0x11)) | + (TIM_FiltInitStruct->Prescaler)); + + if ((IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + TIMx->C3FILT = temp_chxfilt; + } + else + { + /* none */ + } +} + +/** +*\*\name TIM_IC4FiltConfig +*\*\fun Config the filter of channel4. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_FiltInitStruct: +*\*\ - refer to the definition of TIM_FiltInitType +*\*\return none +**/ +void TIM_IC4FiltConfig(TIM_Module* TIMx, TIM_FiltInitType* TIM_FiltInitStruct) +{ + uint32_t temp_chxfilt = 0; + + temp_chxfilt &= (uint32_t)(((uint32_t) ~((uint32_t)TIM_C4FILT_THRESH)) & + ((uint32_t) ~((uint32_t)TIM_C4FILT_WSIZE)) & + ((uint32_t) ~((uint32_t)TIM_C4FILT_SFPSC))); + + temp_chxfilt |= (uint32_t)((TIM_FiltInitStruct->ThreshHold << (uint32_t)(0x18)) | + (TIM_FiltInitStruct->WindowSize << (uint32_t)(0x11)) | + (TIM_FiltInitStruct->Prescaler)); + + if ((IS_GTIMA1_7_DEVICE(TIMx)) || (IS_GTIMB1_3_DEVICE(TIMx))) + { + TIMx->C4FILT = temp_chxfilt; + } + else + { + /* none */ + } +} + +/** +*\*\name TIM_IC1FiltEnable +*\*\fun Enable or disable the filter of channel1. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_IC1FiltEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the filter of CH1 */ + TIMx->C1FILT |= (uint32_t)TIM_C1FILT_FILTEN; + } + else + { + /* Disable the filter of CH1 */ + TIMx->C1FILT &= (uint32_t)(~TIM_C1FILT_FILTEN); + } +} + +/** +*\*\name TIM_IC2FiltEnable +*\*\fun Enable or disable the filter of channel2. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_IC2FiltEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the filter of CH2 */ + TIMx->C2FILT |= (uint32_t)TIM_C2FILT_FILTEN; + } + else + { + /* Disable the filter of CH2 */ + TIMx->C2FILT &= (uint32_t)(~TIM_C2FILT_FILTEN); + } +} + +/** +*\*\name TIM_IC3FiltEnable +*\*\fun Enable or disable the filter of channel3. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_IC3FiltEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the filter of CH3 */ + TIMx->C3FILT |= (uint32_t)TIM_C3FILT_FILTEN; + } + else + { + /* Disable the filter of CH3 */ + TIMx->C3FILT &= (uint32_t)(~TIM_C3FILT_FILTEN); + } +} + +/** +*\*\name TIM_IC4FiltEnable +*\*\fun Enable or disable the filter of channel4. +*\*\param TIMx: +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void TIM_IC4FiltEnable(TIM_Module* TIMx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the filter of CH4 */ + TIMx->C4FILT |= (uint32_t)TIM_C4FILT_FILTEN; + } + else + { + /* Disable the filter of CH4 */ + TIMx->C4FILT &= (uint32_t)(~TIM_C4FILT_FILTEN); + } +} + +/** +*\*\name TIM_GetFiltStatus +*\*\fun Checks the specified filter status. +*\*\param TIMx (The input parameters must be the following values): +*\*\ - GTIMA1 +*\*\ - GTIMA2 +*\*\ - GTIMA3 +*\*\ - GTIMA4 +*\*\ - GTIMA5 +*\*\ - GTIMA6 +*\*\ - GTIMA7 +*\*\ - GTIMB1 +*\*\ - GTIMB2 +*\*\ - GTIMB3 +*\*\param TIM_FiltFlag : +*\*\ - TIM_C1FILTO +*\*\ - TIM_C2FILTO +*\*\ - TIM_C3FILTO +*\*\ - TIM_C4FILTO +*\*\return The new state of TIM_FiltFlag (SET or RESET). +**/ +FlagStatus TIM_GetFiltStatus(TIM_Module* TIMx, uint32_t TIM_FiltFlag) +{ + FlagStatus bitstatus; + + if ((TIMx->FILTO & TIM_FiltFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_usart.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_usart.c new file mode 100644 index 0000000000..6091bc0a8e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_usart.c @@ -0,0 +1,1850 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_usart.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "n32h76x_78x_usart.h" +#include "n32h76x_78x_rcc.h" + + +/** +*\*\name USART_DeInit +*\*\fun Deinitializes the USARTx peripheral registers to their default reset values. +*\*\param U(S)ARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return none +**/ +void USART_DeInit(USART_Module* USARTx) +{ + if (USARTx == USART1) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_USART1); + } + else if (USARTx == USART2) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_USART2); + } + else if (USARTx == USART3) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_USART3); + } + else if (USARTx == USART4) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_USART4); + } + else if (USARTx == USART5) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_USART5); + } + else if (USARTx == USART6) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_USART6); + } + else if (USARTx == USART7) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_USART7); + } + else if (USARTx == USART8) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_USART8); + } + else if (USARTx == UART9) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_UART9); + } + else if (USARTx == UART10) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_UART10); + } + else if (USARTx == UART11) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_UART11); + } + else if (USARTx == UART12) + { + RCC_EnableAPB1PeriphReset3(RCC_APB1_PERIPHRST_UART12); + } + else if (USARTx == UART13) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_UART13); + } + else if (USARTx == UART14) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_UART14); + } + else + { + if (USARTx == UART15) + { + RCC_EnableAPB2PeriphReset3(RCC_APB2_PERIPHRST_UART15); + } + } +} + + +/** +*\*\name USART_Init +*\*\fun Initializes the USARTx peripheral according to USART_InitStruct. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 + +*\*\param USART_InitStruct (The input parameters must be the following values): +*\*\ - buad_rate : +*\*\ - (((buad_rate) > 0) && ((buad_rate) < 0x00E4E1C0)) +*\*\ - WordLength +*\*\ - USART_WL_8B +*\*\ - USART_WL_9B +*\*\ - StopBits +*\*\ - USART_STPB_1 +*\*\ - USART_STPB_0_5 +*\*\ - USART_STPB_2 +*\*\ - USART_STPB_1_5 +*\*\ - Parity +*\*\ - USART_PE_NO +*\*\ - USART_PE_EVEN +*\*\ - USART_PE_ODD +*\*\ - Mode +*\*\ - USART_MODE_RX +*\*\ - USART_MODE_TX +*\*\ - HardwareFlowControl +*\*\ - USART_HFCTRL_NONE +*\*\ - USART_HFCTRL_RTS +*\*\ - USART_HFCTRL_CTS +*\*\ - USART_HFCTRL_RTS_CTS +*\*\ - OverSampling +*\*\ - USART_8OVER +*\*\ - USART_16OVER +*\*\return none +**/ +void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct) +{ + uint32_t tmpregister; + uint32_t apbclock; + uint32_t integerdivider; + uint32_t fractionaldivider; + uint32_t usartxbase; + RCC_ClocksTypeDef RCC_ClocksStatus; + const uint8_t ApbPresTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + usartxbase = (uint32_t)USARTx; + + /* USART CTRL2 Configuration */ + tmpregister = USARTx->CTRL2; + /* Clear STOP[1:0] bits */ + tmpregister &= CTRL2_STPB_CLR_MASK; + /* Configure the USART Stop Bits */ + /* Set STOP[1:0] bits according to StopBits value */ + tmpregister |= (uint32_t)USART_InitStruct->StopBits; + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint32_t)tmpregister; + + + /* USART CTRL1 Configuration */ + tmpregister = USARTx->CTRL1; + /* Clear RXEN, TXEN, PSEL, PCEN, WL and OSPM bits */ + tmpregister &= USART_CTRL1_CLR_MASK; + /* Configure the USART Word Length, Parity, OverSampling and mode */ + /* Set the WL bits according to WordLength value */ + /* Set PSEL and PCEN bits according to Parity value */ + /* Set RXEN and TXEN bits according to Mode value */ + /* Set OSPM bits according to OverSampling value */ + tmpregister |= (uint32_t)USART_InitStruct->WordLength | USART_InitStruct->Parity \ + | USART_InitStruct->OverSampling | USART_InitStruct->Mode; + /* Write to USART CTRL1 */ + USARTx->CTRL1 = (uint32_t)tmpregister; + + /* USART CTRL3 Configuration */ + tmpregister = USARTx->CTRL3; + /* Clear CTSE and RTSE bits */ + tmpregister &= CTRL3_CLR_MASK; + /* Configure the USART HFC */ + /* Set CTSE and RTSE bits according to HardwareFlowControl value */ + tmpregister |= USART_InitStruct->HardwareFlowControl; + /* Write to USART CTRL3 */ + USARTx->CTRL3 = (uint32_t)tmpregister; + + /* USART PBC Configuration */ + /* Configure the USART Baud Rate */ + RCC_GetClocksFreqValue(&RCC_ClocksStatus); + + if ((usartxbase == USART5_BASE) || (usartxbase == USART6_BASE) \ + || (usartxbase == USART7_BASE) || (usartxbase == USART8_BASE) \ + || (usartxbase == UART13_BASE) || (usartxbase == UART14_BASE) \ + || (usartxbase == UART15_BASE)) + { + apbclock = RCC_ClocksStatus.APB2ClkFreq; + } + else if ((usartxbase == USART1_BASE) || (usartxbase == USART2_BASE)) + { + apbclock = RCC_ClocksStatus.AHB1ClkFreq >> (ApbPresTable[(RCC->APB1DIV1 & RCC_APB1DIV1_APB1USARTDIV) >> 28]); + } + else + { + apbclock = RCC_ClocksStatus.APB1ClkFreq; + } + + /* Determine the integer part */ + if((USARTx->CTRL1 & USART_8OVER) == 0) + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * (apbclock / 4)) / (USART_InitStruct->BaudRate)); + } + else + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * (apbclock / 2)) / (USART_InitStruct->BaudRate)); + } + + tmpregister = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpregister >> 4)); + + /*Determine whether the fractional part needs to carried*/ + if((USARTx->CTRL1 & USART_8OVER) != 0) + { + /* Oversampling mode is 8 Samples */ + fractionaldivider = ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x0F); + + if(fractionaldivider == 0x08) + { + tmpregister = tmpregister + 0x10; + } + else + { + tmpregister |= fractionaldivider; + } + } + else + { + /* Oversampling mode is 16 Samples */ + tmpregister += ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x1F); + } + + /* Write to USART PBC */ + USARTx->BRCF = (uint32_t)tmpregister; +} + +/** +*\*\name USART_StructInit. +*\*\fun Fills each USART_InitStruct member with its default value. +*\*\param USART_InitStruct (The input parameters must be the following values): +*\*\ - BaudRate +*\*\ - WordLength +*\*\ - StopBits +*\*\ - Parity +*\*\ - Mode +*\*\ - OverSampling +*\*\return none +**/ +void USART_StructInit(USART_InitType* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->BaudRate = 9600; + USART_InitStruct->WordLength = USART_WL_8B; + USART_InitStruct->StopBits = USART_STPB_1; + USART_InitStruct->Parity = USART_PE_NO; + USART_InitStruct->Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStruct->HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStruct->OverSampling = USART_16OVER; +} + + +/** +*\*\name USART_ClockInit +*\*\fun Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\param USART_ClockInitStruct (The input parameters must be the following values): +*\*\ - Clock : +*\*\ - USART_CLK_DISABLE +*\*\ - USART_CLK_ENABLE +*\*\ - USART_Clock_Polarity +*\*\ - USART_CLKPOL_LOW +*\*\ - USART_CLKPOL_HIGH +*\*\ - USART_Clock_Phase +*\*\ - USART_CLKPHA_1EDGE +*\*\ - USART_CLKPHA_2EDGE +*\*\ - USART_Last_Bit +*\*\ - USART_CLKLB_DISABLE +*\*\ - USART_CLKLB_ENABLE +*\*\return none +*\*\note The Smart Card and Synchronous modes are not available for UART5/UART6/UART7/UART8. +**/ +void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct) +{ + uint32_t tmpregister; + + /* USART CTRL2 Configuration */ + tmpregister = USARTx->CTRL2; + /* Clear CLKEN, CPOL, CPHA and LBCLK bits */ + tmpregister &= CTRL2_CLOCK_CLR_MASK; + /* Configure the USART Clock, CPOL, CPHA and LastBit */ + /* Set CLKEN bit according to Clock value */ + /* Set CLKPOL bit according to Polarity value */ + /* Set CLKPHA bit according to Phase value */ + /* Set LBCLK bit according to LastBit value */ + tmpregister |= (uint32_t)USART_ClockInitStruct->Clock | USART_ClockInitStruct->Polarity + | USART_ClockInitStruct->Phase | USART_ClockInitStruct->LastBit; + /* Write to USART CTRL2 */ + USARTx->CTRL2 = (uint32_t)tmpregister; +} + +/** +*\*\name USART_ClockStructInit +*\*\fun Fills each USART_ClockInitStruct member with its default value. +*\*\param USART_ClockInitStruct (The input parameters must be the following values): +*\*\ - Clock +*\*\ - USART_Clock_Polarity +*\*\ - USART_Clock_Phase +*\*\ - USART_Last_Bit +*\*\return none +**/ +void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->Clock = USART_CLK_DISABLE; + USART_ClockInitStruct->Polarity = USART_CLKPOL_LOW; + USART_ClockInitStruct->Phase = USART_CLKPHA_1EDGE; + USART_ClockInitStruct->LastBit = USART_CLKLB_DISABLE; +} + + +/** +*\*\name USART_Enable +*\*\fun Enables or disables the specified USART peripheral. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_Enable(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_UEN_SET; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_UEN_RESET; + } +} + + +/** +*\*\name USART_ConfigInt +*\*\fun Enables or disables the specified USART interrupts. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_INT (The input parameters must be the following values): +*\*\ - USART_INT_PEF Parity Error interrupt +*\*\ - USART_INT_TXC Transmission complete interrupt +*\*\ - USART_INT_TXDE Transmit Data Register empty interrupt +*\*\ - USART_INT_RXDNE Receive Data register not empty interrupt +*\*\ - USART_INT_IDLEF Idle line detection interrupt +*\*\ - USART_INT_RTOE Receiver timeout interrupt +*\*\ - USART_INT_LINBD LIN Break detection interrupt +*\*\ - USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error) +*\*\ - USART_INT_CTSF CTS change interrupt +*\*\ - USART_INT_TXFTE TXFIFO threshold interrupt enable +*\*\ - USART_INT_RXFTE RXFIFO threshold interrupt enable +*\*\ - USART_INT_RXFEE RXFIFO empty interrupt enable +*\*\ - USART_INT_TXFEE TXFIFO empty interrupt enable +*\*\ - USART_INT_RXFFE RXFIFO full interrupt enable +*\*\ - USART_INT_TXFFE TXFIFO full interrupt enable +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_ConfigInt(USART_Module* USARTx, uint32_t USART_INT, FunctionalState Cmd) +{ + uint32_t itmask; + uint32_t usartxbase; + + usartxbase = (uint32_t)USARTx; + + /* Get the interrupt position */ + itmask = USART_INT & USART_INT_MASK; + + if((USART_INT & USART_CTRL1_INTMASK) != (uint32_t)0x00) /* The IT is in CTRL1 register */ + { + usartxbase += 0x00; + } + else if((USART_INT & USART_CTRL2_INTMASK) != (uint32_t)0x00) /* The IT is in CTRL2 register */ + { + usartxbase += 0x04; + } + else if((USART_INT & USART_CTRL3_INTMASK) != (uint32_t)0x00) /* The IT is in CTRL3 register */ + { + usartxbase += 0x08; + } + else /* The IT is in FIFO register */ + { + usartxbase += 0x1C; + } + + if (Cmd != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + + +/** +*\*\name USART_EnableDMA +*\*\fun Enables or disables the USART's DMA interface. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_DMAReq (The input parameters must be the following values): +*\*\ - USART_DMAREQ_TX USART DMA transmit request +*\*\ - USART_DMAREQ_RX USART DMA receive request +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_EnableDMA(USART_Module* USARTx, uint32_t USART_DMAReq, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DADDR bits in the USART CTRL3 register */ + USARTx->CTRL3 &= (uint32_t)~USART_DMAReq; + } +} + +/** +*\*\name USART_SetAddr +*\*\fun Sets the address of the USART node. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_Addr (The input parameters must be the following values): +*\*\ - (((USART_Addr)>=0x00)&&((USART_Addr)<0x10)) +*\*\return none +**/ +void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr) +{ + /* Clear the USART address */ + USARTx->CTRL2 &= CTRL2_ADDR_MASK; + /* Set the USART address node */ + USARTx->CTRL2 |= USART_Addr; +} + + +/** +*\*\name USART_ConfigWakeUpMode +*\*\fun Selects the USART WakeUp method. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_WakeUpMode (The input parameters must be the following values): +*\*\ - USART_WUM_IDLELINE WakeUp by an idle line detection +*\*\ - USART_WUM_ADDRMASK WakeUp by an address mark +*\*\return none +**/ +void USART_ConfigWakeUpMode(USART_Module* USARTx, uint32_t USART_WakeUpMode) +{ + USARTx->CTRL1 &= CTRL1_WUM_MASK; + USARTx->CTRL1 |= USART_WakeUpMode; +} + + +/** +*\*\name USART_EnableRcvWakeUp +*\*\fun Determines if the USART is in mute mode or not. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CTRL1 register */ + USARTx->CTRL1 |= CTRL1_RCVWU_SET; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CTRL1 register */ + USARTx->CTRL1 &= CTRL1_RCVWU_RESET; + } +} + + +/** +*\*\name USART_ConfigLINBreakDetectLength +*\*\fun Sets the USART LIN Break detection length. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_LINBreakDetectLength (The input parameters must be the following values): +*\*\ - USART_LINBDL_10B 10-bit break detection +*\*\ - USART_LINBDL_11B 11-bit break detection +*\*\return none +**/ +void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint32_t USART_LINBreakDetectLength) +{ + USARTx->CTRL2 &= CTRL2_LINBDL_MASK; + USARTx->CTRL2 |= USART_LINBreakDetectLength; +} + + +/** +*\*\name USART_EnableLIN +*\*\fun Enables or disables the USART's LIN mode. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 |= CTRL2_LINMEN_SET; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CTRL2 register */ + USARTx->CTRL2 &= CTRL2_LINMEN_RESET; + } +} + +/** +*\*\name USART_SendData +*\*\fun Transmits single data through the USARTx peripheral. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Data : +*\*\ - the data to transmit +*\*\return none +**/ +void USART_SendData(USART_Module* USARTx, uint32_t Data) +{ + /* Transmit Data */ + USARTx->DAT = (Data & (uint32_t)0x01FF); +} + +/** +*\*\name USART_ReceiveData +*\*\fun Returns the most recent received data by the USARTx peripheral. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return none +**/ +uint32_t USART_ReceiveData(USART_Module* USARTx) +{ + /* Receive Data */ + return (uint32_t)(USARTx->DAT & (uint32_t)0x01FF); +} + +/** +*\*\name USART_SendBreak +*\*\fun Transmits break characters. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return none +**/ +void USART_SendBreak(USART_Module* USARTx) +{ + /* Send break characters */ + USARTx->CTRL1 |= CTRL1_SDBRK_SET; +} + + +/** +*\*\name USART_SetGuardTime +*\*\fun Sets the specifies USART guard time. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\param USART_GuardTime: +*\*\ - specifies the guard time +*\*\return none +**/ +void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime) +{ + /* Clear the USART Guard time */ + USARTx->GTP &= GTP_LSB_MASK; + /* Set the USART guard time */ + USARTx->GTP |= (uint32_t)((uint32_t)USART_GuardTime << 0x08); +} + +/** +*\*\name USART_SetPrescaler +*\*\fun Sets the system clock prescaler. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_Prescaler: +*\*\ - specifies the prescaler clock +*\*\return none +**/ +void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler) +{ + /* Clear the USART prescaler */ + USARTx->GTP &= GTP_MSB_MASK; + /* Set the USART prescaler */ + USARTx->GTP |= USART_Prescaler; +} + +/** +*\*\name USART_EnableSmartCard +*\*\fun Enables or disables the USART's Smart Card mode. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCMEN_SET; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCMEN_RESET; + } +} + +/** +*\*\name USART_SetSmartCardNACK +*\*\fun Enables or disables NACK transmission. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_SCNACK_SET; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_SCNACK_RESET; + } +} + + +/** +*\*\name USART_EnableHalfDuplex +*\*\fun Enables or disables the USART's Half Duplex communication. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_HDMEN_SET; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_HDMEN_RESET; + } +} + + +/** +*\*\name USART_ConfigIrDAMode +*\*\fun Configures the USART's IrDA interface. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_IrDAMode (The input parameters must be the following values): +*\*\ - USART_IRDAMODE_LOWPPWER +*\*\ - USART_IRDAMODE_NORMAL +*\*\return none +**/ +void USART_ConfigIrDAMode(USART_Module* USARTx, uint32_t USART_IrDAMode) +{ + USARTx->CTRL3 &= CTRL3_IRDALP_MASK; + USARTx->CTRL3 |= USART_IrDAMode; +} + + +/** +*\*\name USART_EnableIrDA +*\*\fun Enables or disables the USART's IrDA interface. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CTRL3 register */ + USARTx->CTRL3 |= CTRL3_IRDAMEN_SET; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CTRL3 register */ + USARTx->CTRL3 &= CTRL3_IRDAMEN_RESET; + } +} + + +/** +*\*\name USART_GetFlagStatus +*\*\fun Checks whether the specified USART flag is set or not. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_FLAG (The input parameters must be the following values): +*\*\ - USART_FLAG_FELOSE Received Data FE Error Discard Flag +*\*\ - USART_FLAG_NELOSE Received Data NE Error Discard Flag +*\*\ - USART_FLAG_PELOSE Received Data PE Error Discard Flag +*\*\ - USART_FLAG_RTO recevier timeout Flag +*\*\ - USART_FLAG_FEF Framing error Flag +*\*\ - USART_FLAG_NEF Noise error flag Flag +*\*\ - USART_FLAG_OREF Overrun error +*\*\ - USART_FLAG_PEF Parity error +*\*\ - USART_FLAG_LINBD LIN break detection flag +*\*\ - USART_FLAG_CTSF CTS Change flag +*\*\ - USART_FLAG_RXDNE Receive data register not empty flag +*\*\ - USART_FLAG_TXC Transmission Complete flag +*\*\ - USART_FLAG_TXDE Transmit data register empty flag +*\*\ - USART_FLAG_IDLEF Idle Line detection flag +*\*\ - USART_FLAG_TXFT TX FIFO threshold flag +*\*\ - USART_FLAG_RXFT RX FIFO threshold flag +*\*\ - USART_FLAG_RXFE RX FIFO empty flag +*\*\ - USART_FLAG_TXFE TX FIFO empty flag +*\*\ - USART_FLAG_RXFF RX FIFO full flag +*\*\ - USART_FLAG_TXFF TX FIFO full flag +*\*\return USART_FLAG +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint32_t USART_FLAG) +{ + FlagStatus bitstatus; + + if ((USARTx->STS & USART_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name USART_ClrFlag +*\*\fun Clears the USARTx's pending flags. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_FLAG (The input parameters must be the following values): +*\*\ - USART_FLAG_FELOSE Received Data FE Error Discard Flag +*\*\ - USART_FLAG_NELOSE Received Data NE Error Discard Flag +*\*\ - USART_FLAG_PELOSE Received Data PE Error Discard Flag +*\*\ - USART_FLAG_LINBD LIN break detection flag +*\*\ - USART_FLAG_CTSF CTS Change flag +*\*\ - USART_FLAG_RXDNE Receive data register not empty flag +*\*\ - USART_FLAG_TXC Transmission Complete flag +*\*\return none +*\*\note +*\*\ - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun +*\*\ error) and IDLE (Idle line detected) flags are cleared by software +*\*\ sequence: a read operation to USART_STS register (USART_GetFlagStatus()) +*\*\ followed by a read operation to USART_DAT register (USART_ReceiveData()). +*\*\ - RXNE flag can be also cleared by a read to the USART_DAT register +*\*\ (USART_ReceiveData()). +*\*\ - TC flag can be also cleared by software sequence: a read operation to +*\*\ USART_SR register (USART_GetFlagStatus()) followed by a write operation +*\*\ to USART_DAT register (USART_SendData()). +*\*\ - TXE flag is cleared only by a write to the USART_DAT register +*\*\ (USART_SendData()). +*\*\ - RTO flag is cleared only by a write 1 to the USART_CTRL2.RTOCF bit. +*\*\ (USART_ClrRTOFlag()). +**/ +void USART_ClrFlag(USART_Module* USARTx, uint32_t USART_FLAG) +{ + if((USART_FLAG & USART_FLAG_LOSEMASK) != (uint32_t)RESET) + { + USARTx->STS = USART_FLAG; + } + else + { + USARTx->STS = (~(USART_FLAG | USART_FLAG_LOSEMASK)); + } +} + + +/** +*\*\name USART_ClrRTOFlag +*\*\fun Clears the USARTx's RTO pending flag. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return none +**/ +void USART_ClrRTOFlag(USART_Module* USARTx) +{ + uint32_t time_out; + USARTx->CTRL2 |= USART_FLAG_RTO; + time_out = 0xFFFF; + + while((USART_GetFlagStatus(USARTx, USART_FLAG_RTO) == SET) && (time_out--)); + + USARTx->CTRL2 &= (~USART_FLAG_RTO); +} + +/** +*\*\name USART_GetIntStatus +*\*\fun Checks whether the specified USART interrupt has set or not. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param USART_INT (The input parameters must be the following values): +*\*\ - USART_INT_PEF Parity Error interrupt +*\*\ - USART_INT_TXC Transmission complete interrupt +*\*\ - USART_INT_TXDE Transmit Data Register empty interrupt +*\*\ - USART_INT_RXDNE Receive Data register not empty interrupt +*\*\ - USART_INT_IDLEF Idle line detection interrupt +*\*\ - USART_INT_RTOE Receiver timeout interrupt +*\*\ - USART_INT_LINBD LIN Break detection interrupt +*\*\ - USART_INT_ERRF Error interrupt(Frame error, noise error, overrun error) +*\*\ - USART_INT_CTSF CTS change interrupt +*\*\ - USART_INT_TXFTE TXFIFO threshold interrupt enable +*\*\ - USART_INT_RXFTE RXFIFO threshold interrupt enable +*\*\ - USART_INT_RXFEE RXFIFO empty interrupt enable +*\*\ - USART_INT_TXFEE TXFIFO empty interrupt enable +*\*\ - USART_INT_RXFFE RXFIFO full interrupt enable +*\*\ - USART_INT_TXFFE TXFIFO full interrupt enable +*\*\return bitstatus +*\*\ - SET +*\*\ - RESET +**/ +INTStatus USART_GetIntStatus(USART_Module* USARTx, uint32_t USART_INT) +{ + uint32_t itmask; + INTStatus bitstatus; + + /* Get the interrupt position */ + itmask = USART_INT & USART_INT_MASK; + + if ((USART_INT & USART_CTRL1_INTMASK) != 0x00) /* The IT is in CTRL1 register */ + { + itmask &= USARTx->CTRL1; + } + else if ((USART_INT & USART_CTRL2_INTMASK) != 0x00) /* The IT is in CTRL2 register */ + { + itmask &= USARTx->CTRL2; + } + else if ((USART_INT & USART_CTRL3_INTMASK) != 0x00) /* The IT is in CTRL3 register */ + { + itmask &= USARTx->CTRL3; + } + else + { + itmask &= USARTx->FIFO; + } + + if (itmask != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name USART_IdleFrameSet +*\*\fun Idle frame controllable enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_IdleFrameSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL1 |= CTRL1_IFCEN_ENABLE; + } + else + { + USARTx->CTRL1 &= CTRL1_IFCEN_DISABLE; + } +} + + +/** +*\*\name USART_PinSwapSet +*\*\fun Swap TX/RX pins enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_PinSwapSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL1 |= CTRL1_SWAP_ENABLE; + } + else + { + USARTx->CTRL1 &= CTRL1_SWAP_DISABLE; + } +} + + +/** +*\*\name USART_CfgDriverAssertTime +*\*\fun Set Driver Enable assertion time. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Time:(The input parameters must be the following values) +*\*\ - 0x01 ~ 0x1F +*\*\return none +**/ +void USART_CfgDriverAssertTime(USART_Module* USARTx, uint32_t Time) +{ + USARTx->CTRL1 &= (~USART_CTRL1_DEAT_MASK); + USARTx->CTRL1 |= (Time << 21); +} + + + + +/** +*\*\name USART_CfgDriverdeassertTime +*\*\fun Set Driver Enable deassertion time. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Time:(The input parameters must be the following values) +*\*\ - 0x01 ~ 0x1F +*\*\return none +**/ +void USART_CfgDriverdeassertTime(USART_Module* USARTx, uint32_t Time) +{ + USARTx->CTRL1 &= (~USART_CTRL1_DEDT_MASK); + USARTx->CTRL1 |= (Time << 16); +} + + +/** +*\*\name USART_DriverPolaritySet +*\*\fun Driver enable polarity selection. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_DriverPolaritySet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL1 |= CTRL1_DEP_ENABLE; + } + else + { + USARTx->CTRL1 &= CTRL1_DEP_DISABLE; + } +} + + +/** +*\*\name USART_DriverModeSet +*\*\fun Driver enable mode selection. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_DriverModeSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL1 |= CTRL1_DEM_ENABLE; + } + else + { + USARTx->CTRL1 &= CTRL1_DEM_DISABLE; + } +} + + +/** +*\*\name USART_FEFDiscardSet +*\*\fun FEF Data Discard enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_FEFDiscardSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL2 |= CTRL2_FEFLOSE_ENABLE; + } + else + { + USARTx->CTRL2 &= CTRL2_FEFLOSE_DISABLE; + } +} + + +/** +*\*\name USART_NEFDiscardSet +*\*\fun NEF Data Discard enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_NEFDiscardSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL2 |= CTRL2_NEFLOSE_ENABLE; + } + else + { + USARTx->CTRL2 &= CTRL2_NEFLOSE_DISABLE; + } +} + + +/** +*\*\name USART_PEFDiscardSet +*\*\fun PEF Data Discard enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_PEFDiscardSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL2 |= CTRL2_PEFLOSE_ENABLE; + } + else + { + USARTx->CTRL2 &= CTRL2_PEFLOSE_DISABLE; + } +} + + +/** +*\*\name USART_RTOSet +*\*\fun Receiver timeout enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_RTOSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->CTRL2 |= CTRL2_RTO_ENABLE; + } + else + { + USARTx->CTRL2 &= CTRL2_RTO_DISABLE; + } +} + + +/** +*\*\name USART_GetTxFIFO_Num +*\*\fun number of TXFIFO valid data. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return 0x00~0x08 +**/ +uint32_t USART_GetTxFIFO_Num(USART_Module* USARTx) +{ + return ((USARTx->FIFO & USART_FIFO_TXCNT_MASK) >> 18); +} + + +/** +*\*\name USART_GetRxFIFO_Num +*\*\fun number of RXFIFO valid data. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return 0x00~0x08 +**/ +uint32_t USART_GetRxFIFO_Num(USART_Module* USARTx) +{ + return ((USARTx->FIFO & USART_FIFO_RXCNT_MASK) >> 14); +} + + +/** +*\*\name USART_CfgRxFIFOThreshold +*\*\fun RXFIFO threshold configuration. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param threshold (The input parameters must be the following values): +*\*\ - USART_FIFO_DEEP1 +*\*\ - USART_FIFO_DEEP2 +*\*\ - USART_FIFO_DEEP4 +*\*\ - USART_FIFO_DEEP6 +*\*\ - USART_FIFO_DEEP7 +*\*\ - USART_FIFO_DEEP8 +*\*\return none +**/ +void USART_CfgRxFIFOThreshold(USART_Module* USARTx, uint32_t threshold) +{ + USARTx->FIFO &= (~USART_FIFO_RXFTCFG_MASK); + USARTx->FIFO |= (threshold << 5); +} + + +/** +*\*\name USART_CfgTxFIFOThreshold +*\*\fun TXFIFO threshold configuration. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param threshold (The input parameters must be the following values): +*\*\ - USART_FIFO_DEEP1 +*\*\ - USART_FIFO_DEEP2 +*\*\ - USART_FIFO_DEEP4 +*\*\ - USART_FIFO_DEEP6 +*\*\ - USART_FIFO_DEEP7 +*\*\ - USART_FIFO_DEEP8 +*\*\return none +**/ +void USART_CfgTxFIFOThreshold(USART_Module* USARTx, uint32_t threshold) +{ + USARTx->FIFO &= (~USART_FIFO_TXFTCFG_MASK); + USARTx->FIFO |= (threshold << 2); +} + + +/** +*\*\name USART_ClrFIFO +*\*\fun FIFO clear. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\return none +**/ +void USART_ClrFIFO(USART_Module* USARTx) +{ + USARTx->FIFO |= USART_CLEAR_FIFO; +} + + +/** +*\*\name USART_FIFOModeSet +*\*\fun FIFO mode enable or disable. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Cmd:(The input parameters must be the following values) +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void USART_FIFOModeSet(USART_Module* USARTx, FunctionalState Cmd) +{ + if(Cmd == ENABLE) + { + USARTx->FIFO |= USART_FIFO_ENABLE; + } + else + { + USARTx->FIFO &= USART_FIFO_DISABLE; + } +} + + +/** +*\*\name USART_CfgIdleFrameWidth +*\*\fun configure Idle frame width. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Width:(The input parameters must be the following values) +*\*\ - 0x0000 ~ 0xFFFF +*\*\return none +**/ +void USART_IdleFrameWidthSet(USART_Module* USARTx, uint32_t Width) +{ + USARTx->IFW = Width; +} + + +/** +*\*\name USART_CfgRTOWidth +*\*\fun configure receive timeout width. +*\*\param USARTx (The input parameters must be the following values): +*\*\ - USART1 +*\*\ - USART2 +*\*\ - USART3 +*\*\ - USART4 +*\*\ - USART5 +*\*\ - USART6 +*\*\ - USART7 +*\*\ - USART8 +*\*\ - UART9 +*\*\ - UART10 +*\*\ - UART11 +*\*\ - UART12 +*\*\ - UART13 +*\*\ - UART14 +*\*\ - UART15 +*\*\param Width:(The input parameters must be the following values) +*\*\ - 0x00000000 ~ 0x0FFFFFFF +*\*\return none +**/ +void USART_CfgRTOWidth(USART_Module* USARTx, uint32_t Width) +{ + USARTx->RTO = Width; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_vrefbuf.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_vrefbuf.c new file mode 100644 index 0000000000..4be47b5d73 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_vrefbuf.c @@ -0,0 +1,191 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_vrefbuf.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_vrefbuf.h" + +/** VREFBUF Driving Functions Declaration **/ + +/** +*\*\name VREFBUF_SetVoltageScale. +*\*\fun Set the Voltage reference scale. +*\*\param Scale +*\*\ - VREFBUF_VOLTAGE_SCALE_2_5V +*\*\ - VREFBUF_VOLTAGE_SCALE_2_0V +*\*\ - VREFBUF_VOLTAGE_SCALE_1_8V +*\*\ - VREFBUF_VOLTAGE_SCALE_1_5V +*\*\return none +**/ +void VREFBUF_SetVoltageScale(uint32_t Scale) +{ + uint32_t tempreg; + /* Get the old register value */ + tempreg = *(uint32_t * )VREFBUF_CTRL2_REG_ADDR; + /* Clear vrefbuf voltage scale select bits */ + tempreg &= (~VREFBUF_VOLTAGE_SCALE_MASK); + /* Set vrefbuf voltage scale select bits */ + tempreg |= Scale; + /* Store the new register value */ + *(uint32_t * )VREFBUF_CTRL2_REG_ADDR = tempreg; +} + +/** +*\*\name VREFBUF_GetVoltageScale. +*\*\fun Get the Voltage reference scale. +*\*\param none +*\*\return the Voltage reference scale; +*\*\ - VREFBUF_VOLTAGE_SCALE_2_5V +*\*\ - VREFBUF_VOLTAGE_SCALE_2_0V +*\*\ - VREFBUF_VOLTAGE_SCALE_1_8V +*\*\ - VREFBUF_VOLTAGE_SCALE_1_5V +**/ +uint32_t VREFBUF_GetVoltageScale(void) +{ + /* Clear vrefbuf voltage scale select bits */ + return ( (*(uint32_t * )VREFBUF_CTRL2_REG_ADDR) &VREFBUF_VOLTAGE_SCALE_MASK); +} +/** +*\*\name VREFBUF_Enable. +*\*\fun Enable or disable internal voltage reference. +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void VREFBUF_Enable(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + *(uint32_t * )VREFBUF_CTRL1_REG_ADDR |= VREFBUF_EN_MASK; + } + else + { + *(uint32_t * )VREFBUF_CTRL1_REG_ADDR &= (~VREFBUF_EN_MASK); + } +} + +/** +*\*\name VREFBUF_EnableHIM. +*\*\fun Enable or disable high impedance (VREF+ pin is high impedance). +*\*\param Cmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void VREFBUF_EnableHIM(FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + *(uint32_t * )VREFBUF_CTRL1_REG_ADDR |= VREFBUF_HIM_EN_MASK; + } + else + { + *(uint32_t * )VREFBUF_CTRL1_REG_ADDR &= (~VREFBUF_HIM_EN_MASK); + } +} + +/** +*\*\name VREFBUF_SetTrimming. +*\*\fun Set the trimming code for VREFBUF calibration. +*\*\param Value :Value Between 0 and 0x3F +*\*\return none +**/ +void VREFBUF_SetTrimming(uint32_t Value) +{ + uint32_t tempreg, tempreg1; + tempreg = ((*(uint32_t * )VREFBUF_CTRL2_REG_ADDR)&VREFBUF_VOLTAGE_SCALE_MASK); + + if(tempreg == VREFBUF_VOLTAGE_SCALE_2_5V) + { + tempreg1 = *(uint32_t * )VREFBUF_TRIM1_REG_ADDR; + tempreg1 &= (~VREFBUF_TRIMING_2_5V_MASK); + tempreg1 |= (Value << VREFBUF_TRIMING_2_5V_POS); + /* Store the new register value */ + *(uint32_t * )VREFBUF_TRIM1_REG_ADDR = tempreg1; + } + else if(tempreg == VREFBUF_VOLTAGE_SCALE_2_048V) + { + tempreg1 = *(uint32_t * )VREFBUF_TRIM1_REG_ADDR; + tempreg1 &= (~VREFBUF_TRIMING_2_0V_MASK); + tempreg1 |= (Value << VREFBUF_TRIMING_2_0V_POS); + /* Store the new register value */ + *(uint32_t * )VREFBUF_TRIM1_REG_ADDR = tempreg1; + } + else if(tempreg == VREFBUF_VOLTAGE_SCALE_1_8V) + { + tempreg1 = *(uint32_t * )VREFBUF_TRIM2_REG_ADDR; + tempreg1 &= (~VREFBUF_TRIMING_1_8V_MASK); + tempreg1 |= (Value << VREFBUF_TRIMING_1_8V_POS); + /* Store the new register value */ + *(uint32_t * )VREFBUF_TRIM2_REG_ADDR = tempreg1; + } + else + { + tempreg1 = *(uint32_t * )VREFBUF_TRIM2_REG_ADDR; + tempreg1 &= (~VREFBUF_TRIMING_1_5V_MASK); + tempreg1 |= (Value << VREFBUF_TRIMING_1_5V_POS); + /* Store the new register value */ + *(uint32_t * )VREFBUF_TRIM2_REG_ADDR = tempreg1; + } +} + +/** +*\*\name VREFBUF_IsVREFReady. +*\*\fun Checks whether VREFBUF ready flag is set or not. +*\*\param none +*\*\return The new state of VREFBUF_READY (SET or RESET). +**/ +FlagStatus VREFBUF_IsVREFReady(void) +{ + return (((*(uint32_t * )VREFBUF_STS_REG_ADDR) & VREFBUF_READY_MASK) != 0U) ? SET : RESET; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_wwdg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_wwdg.c new file mode 100644 index 0000000000..a85d008032 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_wwdg.c @@ -0,0 +1,216 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_wwdg.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_wwdg.h" +#include "n32h76x_78x_rcc.h" + +/** +*\*\name WWDG_DeInit. +*\*\fun Resets the WWDG peripheral registers to their default reset values. +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\return none +**/ +void WWDG_DeInit(WWDG_Module* WWDGx) +{ + if (WWDGx == WWDG1) + { + RCC_EnableAXIPeriphReset2(RCC_AXI_PERIPHRST_WWDG1); + } + else + { + if (WWDGx == WWDG2) + { + RCC_EnableAPB1PeriphReset2(RCC_APB1_PERIPHRST_WWDG2); + } + } +} + +/** +*\*\name WWDG_SetPrescalerDiv. +*\*\fun Set the WWDOG Prescaler Division Value. +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\param WWDG_Prescaler : +*\*\ - WWDG_PRESCALER_DIV1 WWDG Counter Clock (PCLK1 / 4096) / 1 +*\*\ - WWDG_PRESCALER_DIV2 WWDG Counter Clock (PCLK1 / 4096) / 2 +*\*\ - WWDG_PRESCALER_DIV4 WWDG Counter Clock (PCLK1 / 4096) / 4 +*\*\ - WWDG_PRESCALER_DIV8 WWDG Counter Clock (PCLK1 / 4096) / 8 +*\*\return none +**/ +void WWDG_SetPrescalerDiv(WWDG_Module* WWDGx, uint32_t WWDG_Prescaler) +{ + uint32_t tmpregister; + + /* Clear TIMERB[1:0] bits */ + tmpregister = WWDGx->CFG & CFG_TIMERB_MASK; + /* Set TIMERB[1:0] bits according to WWDG_Prescaler value */ + tmpregister |= WWDG_Prescaler; + /* Store the new value */ + WWDGx->CFG = tmpregister; +} + +/** +*\*\name WWDG_SetWValue. +*\*\fun Set the WWDOG Window Value. +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\param WindowValue : WWDOG Window Value +*\*\ The value range of this parameter : +*\*\ - 0x0040 ~ 0x3FFF +*\*\return none +**/ +void WWDG_SetWValue(WWDG_Module* WWDGx, uint16_t WindowValue) +{ + __IO uint32_t tmpregister = 0; + + /* Clear W[13:0] bits */ + tmpregister = WWDGx->CFG & CFG_W_MASK; + + /* Set W[13:0] bits according to WindowValue value */ + tmpregister |= WindowValue & (uint32_t)BIT_MASK; + + /* Store the new value */ + WWDGx->CFG = tmpregister; +} + +/** +*\*\name WWDG_EnableInt. +*\*\fun Enable WWDG Early Wakeup interrupt(EWINT). +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\return none +**/ +void WWDG_EnableInt(WWDG_Module* WWDGx) +{ + WWDGx->CFG |= EARLY_WAKEUP_INT; +} + +/** +*\*\name WWDG_SetCnt. +*\*\fun Set the WWDOG Counter Value. +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\param Counter : WWDOG Counter value +*\*\ The value range of this parameter : +*\*\ - 0x40 ~ 0x3FFF +*\*\return none +**/ +void WWDG_SetCnt(WWDG_Module* WWDGx, uint16_t Counter) +{ + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDGx->CTRL = (uint32_t)Counter & (uint32_t)BIT_MASK; +} + +/** +*\*\name WWDG_Enable. +*\*\fun Set the WWDOG Counter Value and Enable WWDOG . +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\param Counter : WWDOG Counter value +*\*\ The value range of this parameter : +*\*\ - 0x40 ~ 0x3FFF +*\*\return none +**/ +//uint32_t data; +void WWDG_Enable(WWDG_Module* WWDGx, uint16_t Counter) +{ + //data=CTRL_ACTB_SET | Counter; + WWDGx->CTRL = CTRL_ACTB_SET | Counter; +} + +/** +*\*\name WWDG_GetEWINTF. +*\*\fun Get WWDOG Early Wake-up Interrupt Flag. +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\param none +*\*\return SET or RESET +**/ +FlagStatus WWDG_GetEWINTF(WWDG_Module* WWDGx) +{ + FlagStatus bitstatus; + + /* Return the status of the flag */ + if ((WWDGx->STS & EARLY_WAKEUP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name WWDG_ClrEWINTF. +*\*\fun Clear WWDOG Early Wake-up Interrupt Flag. +*\*\param WWDGx (The input parameters must be the following values): +*\*\ - WWDG1 +*\*\ - WWDG2 +*\*\return none +**/ +void WWDG_ClrEWINTF(WWDG_Module* WWDGx) +{ + WWDGx->STS = (uint32_t)RESET; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_xspi.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_xspi.c new file mode 100644 index 0000000000..a813172dbc --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_std_periph_driver/src/n32h76x_78x_xspi.c @@ -0,0 +1,1272 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file n32h76x_78x_xspi.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "n32h76x_78x_xspi.h" +#include "n32h76x_78x_rcc.h" + +/** N32H76X_78X_StdPeriph_Driver **/ + +/** +*\*\name XSPI_DeInit. +*\*\fun Deinitializes the XSPI peripheral registers to its default reset values. +*\*\return none +**/ +void XSPI_DeInit(XSPI_Module* xSPIx) +{ + if(xSPIx == xSPI1) + { + RCC_EnableAXIPeriphReset4(RCC_AXI_PERIPHRST_XSPI1); + } + else if(xSPIx == xSPI2) + { + RCC_EnableAXIPeriphReset4(RCC_AXI_PERIPHRST_XSPI2); + } +} + +/** +*\*\name XSPIInitConfig. +*\*\fun Merge configuration from the buffer of XSPI para struct, then write it into related registers. +*\*\param XSPI_InitStruct : +*\*\ - FRF +*\*\ - SPIFRF +*\*\ - TMOD +*\*\ - SCPOL +*\*\ - SCPH +*\*\ - DFS +*\*\ - SSTE +*\*\ - SEN +*\*\ - CLKDIV +*\*\ - WAITCYCLES +*\*\ - INST_L +*\*\ - ADDRL +*\*\ - NDF +*\*\ - TXFT +*\*\ - RXFT +*\*\ - ENHANCED_WAITCYCLES +*\*\ - ENHANCED_CLKSTREN +*\*\ - ENHANCED_ADDR_L +*\*\ - ENHANCED_INST_L +*\*\ - ENHANCED_TRANSTYPE +*\*\ - ENHANCED_WRSPIDDREN; +*\*\ - ENHANCED_WRINDDREN; +*\*\ - XIP_FRF +*\*\ - XIP_TRANSTYPE +*\*\ - XIP_ADDRL +*\*\ - XIP_INST_L +*\*\ - XIP_WAITCYCLES +*\*\ - XIPDFSHC +*\*\ - XIPINSTEN +*\*\ - XIPCTEN +*\*\ - XIPINSTEN +*\*\ - XIPMBL +*\*\ - XIP_WRINDDREN +*\*\ - XIP_DDREN +*\*\ - XIPDFSHC +*\*\ - XIPMDBITS +*\*\ - ITOC +*\*\ - WTOC +*\*\ - XTOUT +*\*\ - CFS +*\*\ - MWMOD +*\*\ - MCDIR +*\*\ - MHSEN +*\*\ - TXFN +*\*\ - RXFN +*\*\ - SDCN +*\*\ - SES +*\*\ - TXDE +*\*\return none +**/ +void XSPI_Init(XSPI_Module* xSPIx, XSPI_InitType* XSPI_InitStruct) +{ + uint32_t tmpregister = 0; + + if((XSPI_InitStruct->SPIFRF) == XSPI_CTRL0_SPIFRF_STANDARD_FORMAT) + { + tmpregister |= (uint32_t)(XSPI_InitStruct->MST | XSPI_InitStruct->FRF | XSPI_InitStruct->SPIFRF | XSPI_InitStruct->SSTE + | XSPI_InitStruct->TMOD | XSPI_InitStruct->SCPOL | XSPI_InitStruct->SCPH | XSPI_InitStruct->DFS | XSPI_InitStruct->CFS); + + xSPIx->CTRL0 = tmpregister; + + tmpregister = xSPIx->CTRL1; + tmpregister &= XSPI_NDF_MASK; + tmpregister |= XSPI_InitStruct->NDF; + xSPIx->CTRL1 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(XSPI_InitStruct->MWMOD | XSPI_InitStruct->MCDIR | XSPI_InitStruct->MHSEN); + xSPIx->MW_CTRL = tmpregister; + + xSPIx->BAUD = XSPI_InitStruct->CLKDIV; + + tmpregister = xSPIx->TXFT; + tmpregister &= XSPI_TXFT_MASK; + tmpregister = tmpregister | ((XSPI_InitStruct->TXFTST << 16) | XSPI_InitStruct->TXFTTEI); + xSPIx->TXFT = tmpregister; + + xSPIx->RXFT = XSPI_InitStruct->RXFT; + + xSPIx->DDR_TXDE = XSPI_InitStruct->TXDE; + + tmpregister = 0; + tmpregister = (uint32_t)(((XSPI_InitStruct->SES << 16) | XSPI_InitStruct->SDCN) & 0x000100ff); + xSPIx->RX_DELAY = tmpregister; + + tmpregister = (uint32_t)(XSPI_InitStruct->ENHANCED_CLKSTREN | XSPI_InitStruct->ENHANCED_INST_L + | XSPI_InitStruct->ENHANCED_ADDR_L | XSPI_InitStruct->ENHANCED_TRANSTYPE | XSPI_InitStruct->ENHANCED_INST_L | XSPI_InitStruct->ENHANCED_WAITCYCLES + | XSPI_InitStruct->ENHANCED_WAITCYCLES | XSPI_InitStruct->ENHANCED_INST_L | XSPI_InitStruct->ENHANCED_ADDR_L); + + + xSPIx->ENH_CTRL0 = tmpregister; + } + else if((XSPI_InitStruct->SPIFRF) == XSPI_CTRL0_SPIFRF_DUAL_FORMAT) + { + tmpregister |= (uint32_t)(XSPI_InitStruct->MST | XSPI_InitStruct->SPIFRF | XSPI_InitStruct->TMOD + | XSPI_InitStruct->SSTE | XSPI_InitStruct->SCPOL | XSPI_InitStruct->SCPH | XSPI_InitStruct->DFS | XSPI_InitStruct->CFS); + + xSPIx->CTRL0 = tmpregister; + + tmpregister = xSPIx->CTRL1; + tmpregister &= XSPI_NDF_MASK; + tmpregister |= XSPI_InitStruct->NDF; + xSPIx->CTRL1 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(XSPI_InitStruct->MWMOD | XSPI_InitStruct->MCDIR | XSPI_InitStruct->MHSEN); + xSPIx->MW_CTRL = tmpregister; + + xSPIx->BAUD = XSPI_InitStruct->CLKDIV; + + tmpregister = xSPIx->TXFT; + tmpregister &= XSPI_TXFT_MASK; + tmpregister = tmpregister | ((XSPI_InitStruct->TXFTST << 16) | XSPI_InitStruct->TXFTTEI); + xSPIx->TXFT = tmpregister; + + xSPIx->RXFT = XSPI_InitStruct->RXFT; + + xSPIx->DDR_TXDE = XSPI_InitStruct->TXDE; + + tmpregister = 0; + tmpregister = (uint32_t)(((XSPI_InitStruct->SES << 16) | XSPI_InitStruct->SDCN) & 0x000100ff); + xSPIx->RX_DELAY = tmpregister; + + tmpregister = 0; + tmpregister |= (uint32_t)(XSPI_InitStruct->ENHANCED_CLKSTREN | XSPI_InitStruct->ENHANCED_ADDR_L | XSPI_InitStruct->ENHANCED_INST_L + | XSPI_InitStruct->ENHANCED_WAITCYCLES | XSPI_InitStruct->ENHANCED_TRANSTYPE | XSPI_InitStruct->ENHANCED_WRINDDREN + | XSPI_InitStruct->ENHANCED_WRSPIDDREN ); + xSPIx->ENH_CTRL0 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(XSPI_InitStruct->XIPMBL | XSPI_InitStruct->XIPCTEN | XSPI_InitStruct->XIPINSTEN | XSPI_InitStruct->XIP_WRINDDREN + | XSPI_InitStruct->XIP_DDREN | XSPI_InitStruct->XIPDFSHC | XSPI_InitStruct->XIP_WAITCYCLES | XSPI_InitStruct->XIPMDBITS_EN + | XSPI_InitStruct->XIP_INST_L | XSPI_InitStruct->XIP_ADDRL | XSPI_InitStruct->XIP_TRANSTYPE | XSPI_InitStruct->XIP_FRF | XSPI_InitStruct->XIPPREEN); + xSPIx->XIP_CTRL = tmpregister; + + xSPIx->XIP_MODE = XSPI_InitStruct->XIPMDBITS; + xSPIx->XIP_INCR_TOC = XSPI_InitStruct->ITOC; + xSPIx->XIP_WRAP_TOC = XSPI_InitStruct->WTOC; + xSPIx->XIP_TOUT = XSPI_InitStruct->XTOUT; + } + else if((XSPI_InitStruct->SPIFRF) == XSPI_CTRL0_SPIFRF_QUAD_FORMAT || (XSPI_InitStruct->SPIFRF) == XSPI_CTRL0_SPIFRF_OCTAL_FORMAT) + { + tmpregister |= (uint32_t)(XSPI_InitStruct->MST | XSPI_InitStruct->SPIFRF | XSPI_InitStruct->SSTE | XSPI_InitStruct->TMOD + | XSPI_InitStruct->SCPOL | XSPI_InitStruct->SCPH | XSPI_InitStruct->DFS); + + xSPIx->CTRL0 = tmpregister; + + tmpregister = xSPIx->CTRL1; + tmpregister &= XSPI_NDF_MASK; + tmpregister |= XSPI_InitStruct->NDF; + xSPIx->CTRL1 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(XSPI_InitStruct->MWMOD | XSPI_InitStruct->MCDIR | XSPI_InitStruct->MHSEN); + xSPIx->MW_CTRL = tmpregister; + + xSPIx->BAUD = XSPI_InitStruct->CLKDIV; + + tmpregister = xSPIx->TXFT; + tmpregister &= XSPI_TXFT_MASK; + tmpregister = tmpregister | ((XSPI_InitStruct->TXFTST << 16) | XSPI_InitStruct->TXFTTEI); + xSPIx->TXFT = tmpregister; + + xSPIx->RXFT = XSPI_InitStruct->RXFT; + + xSPIx->DDR_TXDE = XSPI_InitStruct->TXDE; + + tmpregister = 0; + tmpregister = (uint32_t)(((XSPI_InitStruct->SES << 16) | XSPI_InitStruct->SDCN) & 0x000100ff); + xSPIx->RX_DELAY = tmpregister; + + tmpregister = 0; + tmpregister |= (uint32_t)(XSPI_InitStruct->ENHANCED_CLKSTREN | XSPI_InitStruct->ENHANCED_ADDR_L | XSPI_InitStruct->ENHANCED_INST_L + | XSPI_InitStruct->ENHANCED_WAITCYCLES | XSPI_InitStruct->ENHANCED_TRANSTYPE | XSPI_InitStruct->ENHANCED_WRINDDREN + | XSPI_InitStruct->ENHANCED_WRSPIDDREN ); + xSPIx->ENH_CTRL0 = tmpregister; + + tmpregister = 0; + tmpregister = (uint32_t)(XSPI_InitStruct->XIPMBL | XSPI_InitStruct->XIPCTEN | XSPI_InitStruct->XIPINSTEN | XSPI_InitStruct->XIP_WRINDDREN + | XSPI_InitStruct->XIP_DDREN | XSPI_InitStruct->XIPDFSHC | XSPI_InitStruct->XIP_WAITCYCLES | XSPI_InitStruct->XIPMDBITS_EN + | XSPI_InitStruct->XIP_INST_L | XSPI_InitStruct->XIP_ADDRL | XSPI_InitStruct->XIP_TRANSTYPE | XSPI_InitStruct->XIP_FRF | XSPI_InitStruct->XIPPREEN); + xSPIx->XIP_CTRL = tmpregister; + + xSPIx->XIP_MODE = XSPI_InitStruct->XIPMDBITS; + xSPIx->XIP_INCR_TOC = XSPI_InitStruct->ITOC; + xSPIx->XIP_WRAP_TOC = XSPI_InitStruct->WTOC; + xSPIx->XIP_TOUT = XSPI_InitStruct->XTOUT; + + } + else {} + + xSPIx->SLAVE_EN = XSPI_InitStruct->SEN; +} + +/** +*\*\name XSPI_StructInit. +*\*\fun Fills each XSPI_InitStruct member with its default value. +*\*\param XSPI_InitStruct : +*\*\ - FRF +*\*\ - SPIFRF +*\*\ - TMOD +*\*\ - SCPOL +*\*\ - SCPH +*\*\ - DFS +*\*\ - SSTE +*\*\ - SEN +*\*\ - CLKDIV +*\*\ - WAITCYCLES +*\*\ - INST_L +*\*\ - ADDRL +*\*\ - NDF +*\*\ - TXFT +*\*\ - RXFT +*\*\ - ENHANCED_WAITCYCLES +*\*\ - ENHANCED_CLKSTREN +*\*\ - ENHANCED_ADDR_L +*\*\ - ENHANCED_INST_L +*\*\ - ENHANCED_TRANSTYPE +*\*\ - ENHANCED_WRSPIDDREN; +*\*\ - ENHANCED_WRINDDREN; +*\*\ - XIP_FRF +*\*\ - XIP_TRANSTYPE +*\*\ - XIP_ADDRL +*\*\ - XIP_INST_L +*\*\ - XIP_WAITCYCLES +*\*\ - XIPDFSHC +*\*\ - XIPINSTEN +*\*\ - XIPCTEN +*\*\ - XIPINSTEN +*\*\ - XIPMBL +*\*\ - XIP_WRINDDREN +*\*\ - XIP_DDREN +*\*\ - XIPDFSHC +*\*\ - XIPMDBITS +*\*\ - ITOC +*\*\ - WTOC +*\*\ - XTOUT +*\*\ - CFS +*\*\ - MWMOD +*\*\ - MCDIR +*\*\ - MHSEN +*\*\ - TXFN +*\*\ - RXFN +*\*\ - SDCN +*\*\ - SES +*\*\ - TXDE +*\*\return none +**/ +void XSPI_StructInit(XSPI_InitType* XSPI_InitStruct) +{ + XSPI_InitStruct-> FRF = 0; + XSPI_InitStruct-> SPIFRF = 0; + XSPI_InitStruct-> TMOD = 0; + XSPI_InitStruct-> SCPOL = 0; + XSPI_InitStruct-> SCPH = 0; + XSPI_InitStruct-> DFS = 0; + XSPI_InitStruct-> SSTE = 0; + XSPI_InitStruct-> SEN = 0; + XSPI_InitStruct-> CLKDIV = 0; + XSPI_InitStruct-> WAITCYCLES = 0; + XSPI_InitStruct-> INST_L = 0; + XSPI_InitStruct-> ADDR_L = 0; + XSPI_InitStruct-> NDF = 0; + XSPI_InitStruct-> TXFTST = 0; + XSPI_InitStruct-> TXFTTEI = 0; + XSPI_InitStruct-> RXFT = 0; + XSPI_InitStruct-> ENHANCED_WAITCYCLES = 0; + XSPI_InitStruct-> ENHANCED_CLKSTREN = 0; + XSPI_InitStruct-> ENHANCED_ADDR_L = 0; + XSPI_InitStruct-> ENHANCED_INST_L = 0; + XSPI_InitStruct-> ENHANCED_TRANSTYPE = 0; + XSPI_InitStruct-> ENHANCED_WRSPIDDREN = 0; + XSPI_InitStruct-> ENHANCED_WRINDDREN = 0; + XSPI_InitStruct-> XIP_FRF = 0; + XSPI_InitStruct-> XIP_TRANSTYPE = 0; + XSPI_InitStruct-> XIP_ADDRL = 0; + XSPI_InitStruct-> XIP_INST_L = 0; + XSPI_InitStruct-> XIP_WAITCYCLES = 0; + XSPI_InitStruct-> XIPDFSHC = 0; + XSPI_InitStruct-> XIPMBL = 0; + XSPI_InitStruct-> XIPINSTEN = 0; + XSPI_InitStruct-> XIPPREEN = 0; + XSPI_InitStruct-> XIPCTEN = 0; + XSPI_InitStruct-> XIP_WRINDDREN = 0; + XSPI_InitStruct-> XIP_DDREN = 0; + XSPI_InitStruct-> XIPMDBITS_EN = 0; + XSPI_InitStruct-> XIPMDBITS = 0; + XSPI_InitStruct-> ITOC = 0; + XSPI_InitStruct-> WTOC = 0; + XSPI_InitStruct-> XTOUT = 0; + XSPI_InitStruct-> CFS = 0; + XSPI_InitStruct-> MWMOD = 0; + XSPI_InitStruct-> MCDIR = 0; + XSPI_InitStruct-> MHSEN = 0; + XSPI_InitStruct-> SDCN = 0; + XSPI_InitStruct-> SES = 0; + XSPI_InitStruct-> TXDE = 0; +} + +/** +*\*\name XSPI_Cmd. +*\*\fun Control XSPI function switch. +*\*\param cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void XSPI_Cmd(XSPI_Module* xSPIx, FunctionalState cmd) +{ + if (cmd != DISABLE) + { + xSPIx->SSIENR |= XSPI_EN_XSPIEN; + } + else + { + xSPIx->SSIENR &= ~XSPI_EN_XSPIEN; + } +} + +/** +*\*\name XSPI_XIP_Cmd. +*\*\fun Control XSPI XIP function switch. +*\*\param cmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void XSPI_XIP_Cmd(XSPI_Module* xSPIx, FunctionalState cmd) +{ + if (cmd != DISABLE) + { + xSPIx->XIP_SLAVE_EN |= XSPI_XIP_SLAVE_EN_SEN; + } + else + { + xSPIx->XIP_SLAVE_EN &= ~XSPI_XIP_SLAVE_EN_SEN; + } +} + + +/** +*\*\name XSPI_Slave_Enable. +*\*\fun XSPI_Slave_Enable register config. +*\*\param cmdData: config data +*\*\ +*\*\return none +**/ +void XSPI_Slave_Enable(XSPI_Module* xSPIx, uint8_t cmdData) +{ + xSPIx->SLAVE_EN = cmdData; +} + +/** +*\*\name XSPI_SetTransType. +*\*\fun Set the format of address and instruction sending (1/2/4/8 wire mode) +*\*\param TransType +*\*\ - XSPI_ENH_CTRL0_TRANSTYPE_STANDARD +*\*\ - XSPI_ENH_CTRL0_TRANSTYPE_ADDRESS_BY_FRF +*\*\ - XSPI_ENH_CTRL0_TRANSTYPE_ALL_BY_FRF +*\*\return none +**/ +void XSPI_SetTransType(XSPI_Module* xSPIx, uint32_t TransType) +{ + xSPIx->ENH_CTRL0 &= XSPI_TRANSTYPE_MASK; + xSPIx->ENH_CTRL0 |= TransType; +} + + +/** +*\*\name XSPI_SetWaitCycles. +*\*\fun Set the number of empty instruction cycles to wait +*\*\param WAITCYCLES: +*\*\ - XSPI_ENH_CTRL0_WAIT_1CYCLES +*\*\ - ... +*\*\ - XSPI_ENH_CTRL0_WAIT_31CYCLES +*\*\return none +**/ +void XSPI_SetWaitCycles(XSPI_Module* xSPIx, uint32_t WAITCYCLES) +{ + xSPIx->ENH_CTRL0 &= XSPI_WAITCYCLES_MASK; + xSPIx->ENH_CTRL0 |= WAITCYCLES; +} + +/** +*\*\name XSPI_SetRXFIFOLevel. +*\*\fun Set Rx fifo transmission threshold, trigger full interrupt threshold +*\*\param fifo_len: +*\*\ - 0x0-0xF +*\*\return none +**/ +void XSPI_SetRXFIFOLevel(XSPI_Module* xSPIx, uint32_t fifo_len) +{ + xSPIx->RXFT &= XSPI_RXFTLR_MASK; + xSPIx->RXFT |= fifo_len; +} + +/** +*\*\name XSPI_SetTXFIFOLevel. +*\*\fun Set the Tx fifo transmission threshold and trigger the interrupt threshold +*\*\param fifo_len: +*\*\ - 0x0-0xF +*\*\return none +**/ +void XSPI_SetTXFIFOLevel(XSPI_Module* xSPIx, uint32_t fifo_len) +{ + xSPIx->TXFT &= XSPI_TXFTLITR_MASK; + xSPIx->TXFT |= fifo_len; +} + +/** +*\*\name XSPI_SetTXFIFOStartLevel. +*\*\fun Set Tx fifo start transmission threshold +*\*\param fifo_len: +*\*\ - 0x0-0xF +*\*\return none +**/ +void XSPI_SetTXFIFOStartLevel(XSPI_Module* xSPIx, uint32_t fifo_len) +{ + xSPIx->TXFT &= XSPI_TXFTLR_MASK; + xSPIx->TXFT |= (fifo_len << 16); +} + + +/** +*\*\name XSPI_GetRXFIFOLevel. +*\*\fun Get the amount of data in the Rx fifo +*\*\return Amount of data in Rx fifo. +**/ +uint8_t XSPI_GetRXFIFOLevel(XSPI_Module* xSPIx) +{ + return xSPIx->RXFT; +} + +/** +*\*\name XSPI_GetTXFIFOLevel. +*\*\fun Get the amount of data in the Tx fifo +*\*\return Amount of data in Tx fifo. +**/ +uint8_t XSPI_GetTXFIFOLevel(XSPI_Module* xSPIx) +{ + return xSPIx->TXFT; +} + +/** +*\*\name XSPIGetDataPointer. +*\*\fun Get Pointer of XSPI DAT0 register. +*\*\return The pointer of XSPI DAT0 register. +**/ +uint32_t XSPI_GetDataPointer(XSPI_Module* xSPIx) +{ + return (uint32_t)&xSPIx->DAT0; +} + +/** +*\*\name XSPI_ReadRxFifoNum. +*\*\fun Read value from XSPI RXFN register which shows the number of the data from receive fifo. +*\*\return The number of the data from receive fifo. +**/ +void XSPI_SetTxFifoStartTransferLevel(XSPI_Module* xSPIx, uint16_t Level) +{ + u32 tmp = xSPIx->TXFT; + tmp &= ~(0XFFFF0000); + tmp |= (Level << 16); + xSPIx->TXFT = tmp; +} +/** +*\*\name XSPI_ReadRxFifoNum. +*\*\fun Read value from XSPI RXFN register which shows the number of the data from receive fifo. +*\*\return The number of the data from receive fifo. +**/ +uint32_t XSPI_ReadRxFifoNum(XSPI_Module* xSPIx) +{ + return xSPIx->RXFN; +} + +/** +*\*\name XSPI_ReadTxFifoNum. +*\*\fun Read value from XSPI TXFN register which shows the number of the data from tx fifo. +*\*\return The number of the data from tx fifo. +**/ +uint32_t XSPI_ReadTxFifoNum(XSPI_Module* xSPIx) +{ + return xSPIx->TXFN; +} + +/** +*\*\name XSPI_SendData. +*\*\fun Write one data direct to XSPI DAT0 register to send. +*\*\param SendData: +*\*\ - data to be send +*\*\return none +**/ +void XSPI_SendData(XSPI_Module* xSPIx, uint32_t SendData) +{ + /* Write in the DAT0 register the data to be sent */ + xSPIx->DAT0 = SendData; +} + + +/** +*\*\name XSPI_ReceiveData. +*\*\fun Read one data from XSPI DAT0 register. +*\*\return The value of XSPI DAT0 register. +**/ +uint32_t XSPI_ReceiveData(XSPI_Module* xSPIx) +{ + /* Return the data in the DAT0 register */ + return xSPIx->DAT0; +} + + +/** +*\*\name XSPI_GetFlagStatus. +*\*\fun Checks whether the specified XSPI flag is set or not. +*\*\param XSPI_FLAG: +*\*\ - XSPI_STS_BUSY +*\*\ - XSPI_STS_TXFNF +*\*\ - XSPI_STS_TXFE +*\*\ - XSPI_STS_RXFNE +*\*\ - XSPI_STS_RXFF +*\*\ - XSPI_STS_TXE +*\*\ - XSPI_STS_DCERR +*\*\return The new state of XSPI_FLAG (SET or RESET). +**/ +FlagStatus XSPI_GetFlagStatus(XSPI_Module* xSPIx, uint32_t XSPI_FLAG) +{ + FlagStatus bitstatus ; + + /* Check the status of the specified XSPI flag */ + if ((xSPIx->STS & XSPI_FLAG) != (uint32_t)RESET) + { + /* XSPI_FLAG is set */ + bitstatus = SET; + } + else + { + /* XSPI_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the XSPI_FLAG status */ + return bitstatus; +} + + +/** +*\*\name XSPI_GetINTStatus. +*\*\fun Checks whether the specified XSPI interrupt has occurred or not. +*\*\param FLAG: +*\*\ - XSPI_ISTS_TXFEIS +*\*\ - XSPI_ISTS_TXFOIS +*\*\ - XSPI_ISTS_RXFUIS +*\*\ - XSPI_ISTS_RXFOIS +*\*\ - XSPI_ISTS_RXFFIS +*\*\ - XSPI_ISTS_MMCIS +*\*\ - XSPI_ISTS_XRXOIS +*\*\ - XSPI_ISTS_TXUIS +*\*\return The new state of XSPI_IT (SET or RESET). +**/ +uint16_t XSPI_GetINTStatus(XSPI_Module* xSPIx, uint16_t FLAG) +{ + uint16_t tmp; + tmp = xSPIx->ISTS & FLAG; + + if (tmp == 1) + return 1; + else + return 0; +} + +/** +*\*\name XSPI_ClearITBit. +*\*\fun Checks whether the specified XSPI interrupt has occurred or not. +*\*\param XSPI_IT: +*\*\ - XSPI_IT_TXUIM +*\*\ - XSPI_IT_XRXOIM +*\*\ - XSPI_IT_MMCIM +*\*\ - XSPI_IT_RXFFIM +*\*\ - XSPI_IT_RXFOIM +*\*\ - XSPI_IT_RXFUIM +*\*\ - XSPI_IT_TXFOIM +*\*\ - XSPI_IT_TXFEIM +*\*\return none. +**/ +void XSPI_ClearITBit(XSPI_Module* xSPIx, uint16_t XSPI_IT) +{ + uint16_t itpos; + + /* Get the SPI IT index */ + itpos = (XSPI_IT & 0x0F); + + /* Clear the selected Error interrupt pending bit */ + if(itpos == 1) + { + (void)xSPIx->TXEICR_CLR; //Clear Transmit FIFO Overflow/Underflow Interrupt + } + else if(itpos == 2) + { + (void)xSPIx->RXFOI_CLR; //Clear Receive FIFO Overflow Interrupt. + } + else if(itpos == 3) + { + (void)xSPIx->RXFUI_CLR; //Clear Receive FIFO Underflow Interrupt. + } + else if(itpos == 4) //Receive FIFO Underflow Interrupt Clear + { + (void)xSPIx->MMCI_CLR; //Clear Multi-Master Contention Interrupt + } + else if(itpos == 6) + { + (void)xSPIx->XIP_RXFOI_CLR; //Clear XIP Receive FIFO Overflow Interrupt. + } + else + { + (void)xSPIx->ICLR; + } +} + +/** +*\*\name XSPI_ConfigInt. +*\*\fun Enables or disables the specified XSPI interrupts. +*\*\param XSPI_IT: +*\*\ - XSPI_IT_TXUIM +*\*\ - XSPI_IT_XRXOIM +*\*\ - XSPI_IT_MMCIM +*\*\ - XSPI_IT_RXFFIM +*\*\ - XSPI_IT_RXFOIM +*\*\ - XSPI_IT_RXFUIM +*\*\ - XSPI_IT_TXFOIM +*\*\ - XSPI_IT_TXFEIM +*\*\param Cmd: +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none. +**/ +void XSPI_ConfigInt(XSPI_Module* xSPIx, uint16_t XSPI_IT, FunctionalState Cmd) +{ + uint16_t itpos, itmask; + + /* Get the XSPI IT index */ + itpos = XSPI_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (Cmd != DISABLE) + { + /* Enable the selected XSPI interrupt */ + xSPIx->IMASK |= itmask; + } + else + { + /* Disable the selected XSPI interrupt */ + xSPIx->IMASK &= (uint16_t)~itmask; + } +} + +/** +*\*\name XSPI_ConfigDMATxLevel. +*\*\fun Configuration of XSPI DMA Tx Level. +*\*\param TxDataLevel(transmit data): +*\*\ - 0~0x1F +*\*\return none. +**/ +void XSPI_ConfigDMATxLevel(XSPI_Module* xSPIx, uint32_t TxDataLevel) +{ + xSPIx->DMATDL_CTRL = TxDataLevel; +} + + +/** +*\*\name XSPI_ConfigDMARxLevel. +*\*\fun Configuration of XSPI DMA Rx Level. +*\*\param RxDataLevel(receive data): +*\*\ - 0~0x1F +*\*\return none. +**/ +void XSPI_ConfigDMARxLevel(XSPI_Module* xSPIx, uint32_t RxDataLevel) +{ + xSPIx->DMARDL_CTRL = RxDataLevel; +} + +/** +*\*\name XSPI_EnableDMA +*\*\fun Enables or disables the XSPI's DMA interface. +*\*\param XSPI_DMAReq (The input parameters must be the following values): +*\*\ - XSPI_DMAREQ_TX XSPI DMA transmit request +*\*\ - XSPI_DMAREQ_RX XSPI DMA receive request +*\*\param Cmd (The input parameters must be the following values): +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +*\*\note Configured when xSPI_EN.XSPIEN disabled +**/ +void XSPI_EnableDMA(XSPI_Module* xSPIx, uint32_t XSPI_DMAReq, FunctionalState Cmd) +{ + if (Cmd != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DADDR bits in the USART CTRL3 register */ + xSPIx->DMA_CTRL |= XSPI_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DADDR bits in the USART CTRL3 register */ + xSPIx->DMA_CTRL &= (uint32_t)~XSPI_DMAReq; + } +} + +/** +*\*\name XSPI_GetBusyStatus. +*\*\fun Get XSPI status,busy or not. +*\*\return SET:XSPI busy; +*\*\ RESET:XSPI idle. +**/ +FlagStatus XSPI_GetBusyStatus(XSPI_Module* xSPIx) +{ + FlagStatus bitstatus; + + if ((xSPIx->STS & XSPI_STS_BUSY) == XSPI_STS_BUSY) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name XSPI_GetTxDataBusyStatus. +*\*\fun Check transmit fifo full or not. +*\*\return SET: Transmit fifo full; +*\*\ RESET: Transmit fifo not full. +**/ +FlagStatus XSPI_GetTxDataBusyStatus(XSPI_Module* xSPIx) +{ + FlagStatus bitstatus; + + if ((xSPIx->STS & XSPI_STS_TXFNF) == 0x00) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name XSPI_GetTxDataEmptyStatus. +*\*\fun Check transmit fifo empty or not. +*\*\return SET: Transmit fifo empty; +*\*\ RESET: Transmit fifo not empty. +**/ +FlagStatus XSPI_GetTxDataEmptyStatus(XSPI_Module* xSPIx) +{ + FlagStatus bitstatus; + + if ((xSPIx->STS & XSPI_STS_TXFE) == XSPI_STS_TXFE) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name XSPI_GetRxHaveDataStatus. +*\*\fun Check receive fifo have data or not. +*\*\return SET:Receive fifo have data; +*\*\ RESET:Receive fifo empty. +**/ +FlagStatus XSPI_GetRxHaveDataStatus(XSPI_Module* xSPIx) +{ + FlagStatus bitstatus; + + if ((xSPIx->STS & XSPI_STS_RXFNE) == XSPI_STS_RXFNE) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name XSPI_GetRxDataFullStatus. +*\*\fun Check receive fifo full or not. +*\*\return SET: Receive fifo full; +*\*\ RESET: Receive fifo not full. +**/ +FlagStatus XSPI_GetRxDataFullStatus(XSPI_Module* xSPIx) +{ + FlagStatus bitstatus; + + if ((xSPIx->STS & XSPI_STS_RXFF) == XSPI_STS_RXFF) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + + +/** +*\*\name XSPI_GetDataConflictErrorStatus. +*\*\fun Check data conflict error or not. +*\*\return SET: Data conflict error; +*\*\ RESET: No data conflict error. +**/ +FlagStatus XSPI_GetDataConflictErrorStatus(XSPI_Module* xSPIx) +{ + FlagStatus bitstatus; + + if ((xSPIx->STS & XSPI_STS_DCERR) == XSPI_STS_DCERR) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** +*\*\name ClrFifo. +*\*\fun Read DAT0 register to clear fifo. +*\*\return none. +**/ +void XSPI_ClrFifo(XSPI_Module* xSPIx) +{ + uint32_t timeout = 0; + + while (XSPI_GetRxHaveDataStatus(xSPIx)) + { + XSPI_ReceiveData(xSPIx); + + if(++timeout >= 200) + { + break; + } + } +} +/** +*\*\name GetFifoData +*\*\fun Get data from fifo. +*\*\param pData pointer to buffer of getting fifo data. +*\*\param Len length of getting fifo data. +*\*\return XSPI_SUCCESS or XSPI_NULL. +**/ +uint32_t XSPI_GetFifoData(XSPI_Module* xSPIx, uint32_t* pData, uint32_t Len) +{ + uint32_t cnt; + + for (cnt = 0; cnt < Len; cnt++) + { + if (XSPI_GetRxHaveDataStatus(xSPIx)) + { + *pData++ = XSPI_ReceiveData(xSPIx); + } + else + { + return XSPI_NULL; + } + } + + return XSPI_SUCCESS; +} +/** +*\*\name XSPISendAndGetWords. +*\*\fun Send words out from source data buffer and get returned datas into destination data buffer. +*\*\param pSrcData: +*\*\ - pSrcData pointer to buffer of sending datas. +*\*\param pDstData: +*\*\ - pDstData pointer to buffer of getting returned datas. +*\*\param cnt: +*\*\ - cnt number of sending datas. +*\*\return none. +**/ +void XSPI_SendAndGetWords(XSPI_Module* xSPIx, uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt) +{ + uint32_t num = 0; + uint32_t timeout = 0; + + while (num < cnt) + { + XSPI_SendData(xSPIx, *(pSrcData++)); + num++; + } + + while (!XSPI_GetRxHaveDataStatus(xSPIx)) + { + if(++timeout >= XSPI_TIME_OUT_CNT) + { + break; + } + } + + timeout = 0; + + while (xSPIx->RXFN < cnt) + { + if(++timeout >= XSPI_TIME_OUT_CNT) + { + break; + } + } + + num = 0; + + while (num < cnt) + { + *(pDstData++) = XSPI_ReceiveData(xSPIx); + num++; + } +} + +/** +*\*\name XSPISendWordAndGetWords. +*\*\fun Send one word data and get returned words into destination data buffer. +*\*\param WrData: +*\*\ - WrData one word to be sent. +*\*\param pRdData: +*\*\ - pRdData pointer to buffer of getting returned datas. +*\*\param LastRd: +*\*\ - 1:go on to get returned datas. +*\*\ - 0:end to get returned datas. +*\*\return none. +**/ +uint32_t XSPI_SendWordAndGetWords(XSPI_Module* xSPIx, uint32_t WrData, uint32_t* pRdData, uint8_t LastRd) +{ + uint32_t timeout1 = 0; + + XSPI_SendData(xSPIx, WrData); //trammit + *pRdData = XSPI_ReceiveData(xSPIx); + + if(LastRd != 0) + { + while(!XSPI_GetRxHaveDataStatus(xSPIx)) //wait for data + { + if(++timeout1 >= XSPI_TIME_OUT_CNT) + { + return XSPI_NULL; //time out + } + } + + *pRdData = XSPI_ReceiveData(xSPIx); //read data + return XSPI_SUCCESS; + } + + return XSPI_NULL; +} + +/** +*\*\name xSPI_Wait_Flag. +*\*\fun xspi Waiting for status register flag. +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param flag: +*\*\ - status register flag to be wait. +*\*\param sta: +*\*\ - SET or RESET. +*\*\param wtime: +*\*\ - timeout. +*\*\return 0:ture 1:false +**/ +uint8_t xSPI_Wait_Flag(XSPI_Module* xSPIx, uint32_t flag, uint8_t sta, uint64_t wtime) +{ + uint8_t flagsta = 0; + + while(wtime) + { + flagsta = (xSPIx->STS & flag) ? 1 : 0; + + if(flagsta == sta)break; + + wtime--; + } + + if(wtime)return 0; + else return 1; +} + +/** +*\*\name xSPI_Wait_TransferComplete. +*\*\fun xspi wait Transfer Complete. +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param wtime: +*\*\ - timeout. +*\*\return 0:ture 1:false +**/ +uint8_t xSPI_Wait_TransferComplete(XSPI_Module* xSPIx, uint64_t wtime) +{ + uint8_t ret = 0; + ret |= xSPI_Wait_Flag(xSPIx, XSPI_STS_TXFE, SET, wtime); //wait for Transmit FIFO is empty:(0x1 EMPTY) + ret |= xSPI_Wait_Flag(xSPIx, XSPI_STS_BUSY, RESET, wtime); //wait for xSPI is idle or disabled:(0x0 idle) + return ret; +} + +/** +*\*\name xSPI_TXFifoLevel. +*\*\fun xspi set tx fifo level. +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param FifoLevel: +*\*\ - tx fifo level to be set. +*\*\return 0:none +**/ +void xSPI_TXFifoLevel(XSPI_Module* xSPIx, u16 FifoLevel) +{ + u32 tmp = 0; + + xSPIx->SSIENR = DISABLE; //disable QSPI + + tmp = xSPIx->TXFT; + //[20:16] TXFTHR + tmp &= ~(0x001f0000); + tmp |= (FifoLevel << 16); + xSPIx->TXFT = tmp; + + xSPIx->SSIENR = ENABLE;//enable QSPI +} + +/** +*\*\name xSPI_BaudRateSelect. +*\*\fun xspi set BaudRate. +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param BAUDR_Value: +*\*\ - Baud Rate to be set. +*\*\return 0:none +**/ +void xSPI_BaudRateSelect(XSPI_Module* xSPIx, uint32_t BAUDR_Value) +{ + xSPIx->SSIENR = DISABLE; //disable QSPI + xSPIx->BAUD = BAUDR_Value; + xSPIx->SSIENR = ENABLE;//enable QSPI +} + +void xSPI_RXSampleDelay(XSPI_Module* xSPIx, uint32_t Sampling_Edge, uint32_t SampleDelay) +{ + xSPIx->SSIENR = DISABLE; //disable QSPI + xSPIx->RX_DELAY = (Sampling_Edge | SampleDelay); + xSPIx->SSIENR = ENABLE;//enable QSPI +} + +/** +*\*\name SetXspi_InstAddrWaitcycle_phase. +*\*\fun Set the data length of xSPIx instruction, address stage, and null instruction in each stage. +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param inst_l: +*\*\ - instruction length. +*\*\param addr_l: +*\*\ - address stage length. +*\*\param wait_cycle: +*\*\ - wait cycle. +*\*\return 0:none +**/ +void SetXspi_InstAddrWaitcycle_phase(XSPI_Module* xSPIx, u32 inst_l, u32 addr_l, u32 wait_cycle) +{ + xSPIx->SSIENR = DISABLE; //disable QSPI + + xSPIx->ENH_CTRL0 &= XSPI_INST_L_MASK; + xSPIx->ENH_CTRL0 |= inst_l; + + xSPIx->ENH_CTRL0 &= XSPI_ADDRL_MASK; + xSPIx->ENH_CTRL0 |= addr_l; + + xSPIx->ENH_CTRL0 &= XSPI_WAITCYCLES_MASK; + xSPIx->ENH_CTRL0 |= wait_cycle; + + xSPIx->SSIENR = ENABLE;//enable QSPI +} + +/** +*\*\name SetXspi_TransType +*\*\fun Set address and instruction transmission format +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param type: +*\*\ - address and instruction transmission format +*\*\return 0:none +**/ +void SetXspi_TransType(XSPI_Module* xSPIx, u32 type) +{ + xSPIx->SSIENR = DISABLE; //disable QSPI + + xSPIx->ENH_CTRL0 &= XSPI_TRANSTYPE_MASK; + xSPIx->ENH_CTRL0 |= type; + xSPIx->SSIENR = ENABLE;//enable QSPI +} + +/** +*\*\name Set_xSPI_DDR +*\*\fun Set DDR Enable:This will enable Dual-data rate transfers in Dual/Quad/Octal frame formats of SPI +*\*\ and Instruction DDR Enable bit. +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\param set_type: +*\*\ - DDR enable type +*\*\return 0:none +**/ +void Set_xSPI_DDR(XSPI_Module* xSPIx, u32 set_type) +{ + xSPIx->SSIENR = DISABLE; //disable QSPI + + //Send edge settings + //The maximum value of this register is = (BAUDR/2) -1 + xSPIx->DDR_TXDE = ((xSPIx->BAUD / 2) / 2) > 255 ? 255 : ((xSPIx->BAUD / 2) / 2); + + switch(set_type) + { + case XSPI_INST_DDR_EN://Setting the inst ddd separately will not take effect. You must first set the SPI ddd and then set the inst ddd for it to take effect + { + xSPIx->ENH_CTRL0 |= (1 << 16); //spi ddr + xSPIx->ENH_CTRL0 |= (1 << 17); //inst ddr + } + break; + + case XSPI_SPI_DDR_EN: + { + xSPIx->ENH_CTRL0 |= (1 << 16); //spi ddr + } + break; + + case XIP_READ_INST_DDR_EN: + { + xSPIx->XIP_CTRL |= (1 << 19); //spi ddr + xSPIx->XIP_CTRL |= (1 << 20); //inst ddr + } + break; + + case XIP_READ_IDDR_EN: + { + xSPIx->XIP_CTRL |= (1 << 19); //spi ddr + } + break; + + case XIP_WRITE_INST_DDR_EN: + { + xSPIx->XIP_WRITE_CTRL |= (1 << 10); //spi ddr + xSPIx->XIP_WRITE_CTRL |= (1 << 11); //inst ddr + } + break; + + case XIP_WRITE_IDDR_EN: + { + xSPIx->XIP_WRITE_CTRL |= (1 << 10); //spi ddr + } + break; + + } + + xSPIx->SSIENR = ENABLE;//enable QSPI +} + +/** +*\*\name xSPI_Clear_RXFIFO +*\*\fun clear rx fifo data +*\*\param xSPIx: +*\*\ - xSPI2. +*\*\return 0:none +**/ +void xSPI_Clear_RXFIFO(XSPI_Module* xSPIx) +{ + //clear rx FIFO + while(xSPIx->STS & XSPI_FLAG_RFNE)// RX FIFO Not Empty flag set + { + xSPIx->DAT0; + } +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_core.h new file mode 100644 index 0000000000..d4716f6fde --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_core.h @@ -0,0 +1,128 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_audio_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USB_AUDIO_CORE_H_ +#define __USB_AUDIO_CORE_H_ + +#include "usbd_ioreq.h" +#include "usbd_req.h" +#include "usbd_desc.h" + +/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ +#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000)) + +/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure + that it is an even number and higher than 3 */ +#define OUT_PACKET_NUM 4 +/* Total size of the audio transfer buffer */ +#define TOTAL_OUT_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * OUT_PACKET_NUM)) + +#define AUDIO_CONFIG_DESC_SIZE 109 +#define AUDIO_INTERFACE_DESC_SIZE 9 +#define USB_AUDIO_DESC_SIZ 0x09 +#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 +#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 + +#define AUDIO_DESCRIPTOR_TYPE 0x21 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_STREAMING_GENERAL 0x01 +#define AUDIO_STREAMING_FORMAT_TYPE 0x02 + +/* Audio Descriptor Types */ +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + +/* Audio Control Interface Descriptor Subtypes */ +#define AUDIO_CONTROL_HEADER 0x01 +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 +#define AUDIO_CONTROL_FEATURE_UNIT 0x06 + +#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C +#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 +#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 + +#define AUDIO_CONTROL_MUTE 0x01 + +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_III 0x03 + +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define AUDIO_ENDPOINT_GENERAL 0x01 + +#define AUDIO_REQ_GET_CUR 0x81 +#define AUDIO_REQ_SET_CUR 0x01 + +#define AUDIO_OUT_STREAMING_CTRL 0x02 + +typedef struct _Audio_Fops +{ + uint8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options); + uint8_t (*DeInit) (uint32_t options); + uint8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); + uint8_t (*VolumeCtrl) (uint8_t vol); + uint8_t (*MuteCtrl) (uint8_t cmd); + uint8_t (*PeriodicTC) (uint8_t cmd); + uint8_t (*GetState) (void); +}AUDIO_FOPS_TypeDef; + +#define AUDIO_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF) +#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) + + +extern USBD_Class_cb_TypeDef USBD_AUDIO_cb; + +#endif /* __USB_AUDIO_CORE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_out_if.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_out_if.h new file mode 100644 index 0000000000..82392d444f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/inc/usbd_audio_out_if.h @@ -0,0 +1,87 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_audio_out_if.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_AUDIO_OUT_IF_H__ +#define __USB_AUDIO_OUT_IF_H__ + +#include "usbd_audio_core.h" + +/* Audio Commands enumeration */ +typedef enum +{ + AUDIO_CMD_PLAY = 1, + AUDIO_CMD_PAUSE, + AUDIO_CMD_STOP, +}AUDIO_CMD_TypeDef; + +/* Mute commands */ +#define AUDIO_MUTE 0x01 +#define AUDIO_UNMUTE 0x00 + +/* Functions return value */ +#define AUDIO_OK 0x00 +#define AUDIO_FAIL 0xFF + +/* Audio Machine States */ +#define AUDIO_STATE_INACTIVE 0x00 +#define AUDIO_STATE_ACTIVE 0x01 +#define AUDIO_STATE_PLAYING 0x02 +#define AUDIO_STATE_PAUSED 0x03 +#define AUDIO_STATE_STOPPED 0x04 +#define AUDIO_STATE_ERROR 0x05 + + +extern AUDIO_FOPS_TypeDef AUDIO_OUT_fops; + +#endif /* __USB_AUDIO_OUT_IF_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_core.c new file mode 100644 index 0000000000..196f2f0d0a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_core.c @@ -0,0 +1,548 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_audio_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_audio_core.h" +#include "usbd_audio_out_if.h" + +/********************************************* + AUDIO Device library callbacks + *********************************************/ +static uint8_t USBD_AUDIO_Init (void *pdev, uint8_t cfgidx); +static uint8_t USBD_AUDIO_DeInit (void *pdev, uint8_t cfgidx); +static uint8_t USBD_AUDIO_Setup (void *pdev, USB_SETUP_REQ *req); +static uint8_t USBD_AUDIO_EP0_RxReady(void *pdev); +static uint8_t USBD_AUDIO_DataIn (void *pdev, uint8_t epnum); +static uint8_t USBD_AUDIO_DataOut (void *pdev, uint8_t epnum); +static uint8_t USBD_AUDIO_SOF (void *pdev); +static uint8_t USBD_AUDIO_OUT_Incplt (void *pdev); + +static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req); +static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req); +static uint8_t *USBD_AUDIO_GetCfgDesc (uint8_t speed, uint16_t *length); + +/* Main Buffer for Audio Data Out transfers and its relative pointers */ +uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE * 2]; +uint8_t* IsocOutWrPtr = IsocOutBuff; +uint8_t* IsocOutRdPtr = IsocOutBuff; + +/* Main Buffer for Audio Control Requests transfers and its relative variables */ +uint8_t AudioCtrl[64]; +uint8_t AudioCtrlCmd = 0; +uint32_t AudioCtrlLen = 0; +uint8_t AudioCtrlUnit = 0; + +static uint32_t PlayFlag = 0; + +static __IO uint32_t USBD_AUDIO_AltSet = 0; +static uint8_t USBD_AUDIO_CfgDesc[AUDIO_CONFIG_DESC_SIZE]; + +/* AUDIO interface class callbacks structure */ +USBD_Class_cb_TypeDef USBD_AUDIO_cb = +{ + USBD_AUDIO_Init, + USBD_AUDIO_DeInit, + USBD_AUDIO_Setup, + NULL, /* EP0_TxSent */ + USBD_AUDIO_EP0_RxReady, + USBD_AUDIO_DataIn, + USBD_AUDIO_DataOut, + USBD_AUDIO_SOF, + NULL, + USBD_AUDIO_OUT_Incplt, + USBD_AUDIO_GetCfgDesc, + USBD_AUDIO_GetCfgDesc, +}; + +/* USB AUDIO device Configuration Descriptor */ +static uint8_t USBD_AUDIO_CfgDesc[AUDIO_CONFIG_DESC_SIZE] = +{ + /* Configuration 1 */ + 0x09, /* bLength */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ + LOBYTE(AUDIO_CONFIG_DESC_SIZE), /* wTotalLength 109 bytes*/ + HIBYTE(AUDIO_CONFIG_DESC_SIZE), + 0x02, /* bNumInterfaces */ + 0x01, /* bConfigurationValue */ + 0x00, /* iConfiguration */ + 0xC0, /* bmAttributes BUS Powred*/ + 0x32, /* bMaxPower = 100 mA*/ + /* 09 byte*/ + + /* USB Speaker Standard interface descriptor */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x00, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x00, /* bNumEndpoints */ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ + AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* 09 byte*/ + + /* USB Speaker Class-specific AC Interface Descriptor */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ + 0x00, /* 1.00 */ /* bcdADC */ + 0x01, + 0x27, /* wTotalLength = 39*/ + 0x00, + 0x01, /* bInCollection */ + 0x01, /* baInterfaceNr */ + /* 09 byte*/ + + /* USB Speaker Input Terminal Descriptor */ + AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ + 0x01, /* bTerminalID */ + 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */ + 0x01, + 0x00, /* bAssocTerminal */ + 0x01, /* bNrChannels */ + 0x00, /* wChannelConfig 0x0000 Mono */ + 0x00, + 0x00, /* iChannelNames */ + 0x00, /* iTerminal */ + /* 12 byte*/ + + /* USB Speaker Audio Feature Unit Descriptor */ + 0x09, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ + AUDIO_OUT_STREAMING_CTRL, /* bUnitID */ + 0x01, /* bSourceID */ + 0x01, /* bControlSize */ + AUDIO_CONTROL_MUTE, /* bmaControls(0) */ + 0x00, /* bmaControls(1) */ + 0x00, /* iTerminal */ + /* 09 byte*/ + + /*USB Speaker Output Terminal Descriptor */ + 0x09, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ + 0x03, /* bTerminalID */ + 0x01, /* wTerminalType 0x0301*/ + 0x03, + 0x00, /* bAssocTerminal */ + 0x02, /* bSourceID */ + 0x00, /* iTerminal */ + /* 09 byte*/ + + /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */ + /* Interface 1, Alternate Setting 0 */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x01, /* bInterfaceNumber */ + 0x00, /* bAlternateSetting */ + 0x00, /* bNumEndpoints */ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* 09 byte*/ + + /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */ + /* Interface 1, Alternate Setting 1 */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x01, /* bInterfaceNumber */ + 0x01, /* bAlternateSetting */ + 0x01, /* bNumEndpoints */ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + /* 09 byte*/ + + /* USB Speaker Audio Streaming Interface Descriptor */ + AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ + 0x01, /* bTerminalLink */ + 0x01, /* bDelay */ + 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/ + 0x00, + /* 07 byte*/ + + /* USB Speaker Audio Type III Format Interface Descriptor */ + 0x0B, /* bLength */ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ + AUDIO_FORMAT_TYPE_III, /* bFormatType */ + 0x02, /* bNrChannels */ + 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */ + 16, /* bBitResolution (16-bits per sample) */ + 0x01, /* bSamFreqType only one frequency supported */ + SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */ + /* 11 byte*/ + + /* Endpoint 9 - Standard Descriptor */ + AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_OUT_EP, /* bEndpointAddress 9 out endpoint*/ + USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */ + AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */ + 0x01, /* bInterval */ + 0x00, /* bRefresh */ + 0x00, /* bSynchAddress */ + /* 09 byte*/ + + /* Endpoint - Audio Streaming Descriptor*/ + AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ + 0x00, /* bmAttributes */ + 0x00, /* bLockDelayUnits */ + 0x00, /* wLockDelay */ + 0x00, + /* 07 byte*/ +} ; + +/** +*\*\name USBD_AUDIO_Init. +*\*\fun Initializes the AUDIO interface. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return status. +**/ +static uint8_t USBD_AUDIO_Init (void *pdev, uint8_t cfgidx) +{ + /* Open EP OUT */ + USBDEV_EP_Open(pdev, AUDIO_OUT_EP, AUDIO_OUT_PACKET, USB_EP_ISOC); + + /* Initialize the Audio output Hardware layer */ + if (AUDIO_OUT_fops.Init(USBD_AUDIO_FREQ, DEFAULT_VOLUME, 0) != USBD_OK) + { + return USBD_FAIL; + } + + /* Prepare Out endpoint to receive audio data */ + USBDEV_EP_PrepareRx(pdev, AUDIO_OUT_EP, (uint8_t*)IsocOutBuff, AUDIO_OUT_PACKET); + + return USBD_OK; +} + +/** +*\*\name USBD_AUDIO_DeInit. +*\*\fun DeInitializes the AUDIO layer. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return status. +**/ +static uint8_t USBD_AUDIO_DeInit (void *pdev, uint8_t cfgidx) +{ + USBDEV_EP_Close(pdev , AUDIO_OUT_EP); + + /* DeInitialize the Audio output Hardware layer */ + if (AUDIO_OUT_fops.DeInit(0) != USBD_OK) + { + return USBD_FAIL; + } + + return USBD_OK; +} + +/** +*\*\name USBD_AUDIO_Setup. +*\*\fun Handles the Audio control request parsing. +*\*\param pdev: device instance. +*\*\param req: usb requests +*\*\return status. +**/ +static uint8_t USBD_AUDIO_Setup (void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len=USB_AUDIO_DESC_SIZ; + uint8_t *pbuf=USBD_AUDIO_CfgDesc + 18; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* AUDIO Class Requests */ + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case AUDIO_REQ_GET_CUR: + AUDIO_Req_GetCurrent(pdev, req); + break; + + case AUDIO_REQ_SET_CUR: + AUDIO_Req_SetCurrent(pdev, req); + break; + + default: + USBD_CtrlError (pdev, req); + return USBD_FAIL; + } + break; + + /* Standard Requests */ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE) + { + pbuf = USBD_AUDIO_CfgDesc + 18; + len = MIN(USB_AUDIO_DESC_SIZ , req->wLength); + } + USBD_CtrlSendData (pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData (pdev, (uint8_t *)&USBD_AUDIO_AltSet, 1); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM) + { + USBD_AUDIO_AltSet = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtrlError (pdev, req); + } + break; + } + } + return USBD_OK; +} + +/** +*\*\name USBD_AUDIO_EP0_RxReady. +*\*\fun Handles audio control requests data. +*\*\param pdev: device instance. +*\*\return status. +**/ +static uint8_t USBD_AUDIO_EP0_RxReady (void *pdev) +{ + /* Check if an AudioControl request has been issued */ + if (AudioCtrlCmd == AUDIO_REQ_SET_CUR) + {/* In this driver, to simplify code, only SET_CUR request is managed */ + /* Check for which addressed unit the AudioControl request has been issued */ + if (AudioCtrlUnit == AUDIO_OUT_STREAMING_CTRL) + {/* In this driver, to simplify code, only one unit is manage */ + /* Call the audio interface mute function */ + AUDIO_OUT_fops.MuteCtrl(AudioCtrl[0]); + + /* Reset the AudioCtrlCmd variable to prevent re-entering this function */ + AudioCtrlCmd = 0; + AudioCtrlLen = 0; + } + } + + return USBD_OK; +} + +/** +*\*\name USBD_AUDIO_DataIn. +*\*\fun Handles the audio IN data stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint number +*\*\return status. +**/ +static uint8_t USBD_AUDIO_DataIn (void *pdev, uint8_t epnum) +{ + return USBD_OK; +} + +__IO uint32_t DataOutCounter = 0; +/** +*\*\name USBD_AUDIO_DataOut. +*\*\fun Handles the Audio Out data stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint number +*\*\return status. +**/ +static uint8_t USBD_AUDIO_DataOut (void *pdev, uint8_t epnum) +{ + DataOutCounter++; + if (epnum == AUDIO_OUT_EP) + { + /* Increment the Buffer pointer or roll it back when all buffers are full */ + if (IsocOutWrPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) + {/* All buffers are full: roll back */ + IsocOutWrPtr = IsocOutBuff; + } + else + {/* Increment the buffer pointer */ + IsocOutWrPtr += AUDIO_OUT_PACKET; + } + + /* Toggle the frame index */ + ((USB_CORE_MODULE*)pdev)->dev.out_ep[epnum].even_odd_frame = + (((USB_CORE_MODULE*)pdev)->dev.out_ep[epnum].even_odd_frame)? 0:1; + + /* Prepare Out endpoint to receive next audio packet */ + USBDEV_EP_PrepareRx(pdev, AUDIO_OUT_EP, (uint8_t*)(IsocOutWrPtr), AUDIO_OUT_PACKET); + + /* Trigger the start of streaming only when half buffer is full */ + if ((PlayFlag == 0) && (IsocOutWrPtr >= (IsocOutBuff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2)))) + { + /* Enable start of Streaming */ + PlayFlag = 1; + } + } + + return USBD_OK; +} + +/** +*\*\name USBD_AUDIO_SOF. +*\*\fun Handles the SOF event (data buffer update and synchronization). +*\*\param pdev: device instance. +*\*\return status. +**/ +static uint8_t USBD_AUDIO_SOF (void *pdev) +{ + /* Check if there are available data in stream buffer. + In this function, a single variable (PlayFlag) is used to avoid software delays. + The play operation must be executed as soon as possible after the SOF detection. */ + if (PlayFlag) + { + /* Start playing received packet */ + AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutRdPtr), /* Samples buffer pointer */ + AUDIO_OUT_PACKET, /* Number of samples in Bytes */ + AUDIO_CMD_PLAY); /* Command to be processed */ + + /* Increment the Buffer pointer or roll it back when all buffers all full */ + if (IsocOutRdPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) + {/* Roll back to the start of buffer */ + IsocOutRdPtr = IsocOutBuff; + } + else + {/* Increment to the next sub-buffer */ + IsocOutRdPtr += AUDIO_OUT_PACKET; + } + + /* If all available buffers have been consumed, stop playing */ + if (IsocOutRdPtr == IsocOutWrPtr) + { + /* Pause the audio stream */ + AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutBuff), /* Samples buffer pointer */ + AUDIO_OUT_PACKET, /* Number of samples in Bytes */ + AUDIO_CMD_PAUSE); /* Command to be processed */ + + /* Stop entering play loop */ + PlayFlag = 0; + + /* Reset buffer pointers */ + IsocOutRdPtr = IsocOutBuff; + IsocOutWrPtr = IsocOutBuff; + } + } + + return USBD_OK; +} + +/** +*\*\name USBD_AUDIO_OUT_Incplt. +*\*\fun Handles the iso out incomplete event. +*\*\param pdev: device instance. +*\*\return status. +**/ +static uint8_t USBD_AUDIO_OUT_Incplt (void *pdev) +{ + return USBD_OK; +} + +/** +*\*\name AUDIO_Req_GetCurrent. +*\*\fun Handles the GET_CUR Audio control request. +*\*\param pdev: device instance. +*\*\param req: setup class request +*\*\return status. +**/ +static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req) +{ + /* Send the current mute state */ + USBD_CtrlSendData (pdev, AudioCtrl, req->wLength); +} + +/** +*\*\name AUDIO_Req_SetCurrent. +*\*\fun Handles the SET_CUR Audio control request. +*\*\param pdev: device instance. +*\*\param req: setup class request +*\*\return status. +**/ +static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req) +{ + if (req->wLength) + { + /* Prepare the reception of the buffer over EP0 */ + USBD_CtrlPrepareRx (pdev, AudioCtrl, req->wLength); + + /* Set the global variables indicating current request and its length + to the function USBD_AUDIO_EP0_RxReady() which will process the request */ + AudioCtrlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */ + AudioCtrlLen = req->wLength; /* Set the request data length */ + AudioCtrlUnit = HIBYTE(req->wIndex); /* Set the request target unit */ + } +} + +/** +*\*\name USBD_AUDIO_GetCfgDesc. +*\*\fun Returns configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +**/ +static uint8_t *USBD_AUDIO_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_AUDIO_CfgDesc); + return USBD_AUDIO_CfgDesc; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_out_if.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_out_if.c new file mode 100644 index 0000000000..d64497270f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/audio/src/usbd_audio_out_if.c @@ -0,0 +1,247 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_audio_out_if.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_audio_core.h" +#include "usbd_audio_out_if.h" +#include "bsp_wm8978.h" + +static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options); +static uint8_t DeInit (uint32_t options); +static uint8_t AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); +static uint8_t VolumeCtrl (uint8_t vol); +static uint8_t MuteCtrl (uint8_t cmd); +static uint8_t PeriodicTC (uint8_t cmd); +static uint8_t GetState (void); + +AUDIO_FOPS_TypeDef AUDIO_OUT_fops = +{ + Init, + DeInit, + AudioCmd, + VolumeCtrl, + MuteCtrl, + PeriodicTC, + GetState +}; + +static uint8_t AudioState = AUDIO_STATE_INACTIVE; + +/** +*\*\name Init. +*\*\fun Initialize and configures all required resources for audio play function. +*\*\param AudioFreq: Startup audio frequency. +*\*\param Volume: Startup volume to be set. +*\*\param options: specific options passed to low layer function. +*\*\return AUDIO_OK if all operations succeed, AUDIO_FAIL else. +**/ +static uint8_t Init(uint32_t AudioFreq, uint32_t Volume, uint32_t options) +{ + static uint32_t Initialized = 0; + + /* Check if the low layer has already been initialized */ + if (Initialized == 0) + { + /* Call low layer function */ + if (WM8978_Speaker_Init(Volume, AudioFreq) != 0) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + /* Set the Initialization flag to prevent reinitializing the interface again */ + Initialized = 1; + } + + /* Update the Audio state machine */ + AudioState = AUDIO_STATE_ACTIVE; + + return AUDIO_OK; +} + +/** +*\*\name DeInit. +*\*\fun Free all resources used by low layer and stops audio-play function. +*\*\param options: specific options passed to low layer function. +*\*\return AUDIO_OK if all operations succeed, AUDIO_FAIL else. +**/ +static uint8_t DeInit (uint32_t options) +{ + /* Update the Audio state machine */ + AudioState = AUDIO_STATE_INACTIVE; + + return AUDIO_OK; +} + +uint8_t txbuff[0xC0] = {0}; +/** +*\*\name AudioCmd. +*\*\fun Play, Stop, Pause or Resume current file. +*\*\param pbuf: address from which file should be played. +*\*\param size: size of the current buffer/file. +*\*\param cmd: command to be executed, can be AUDIO_CMD_PLAY , AUDIO_CMD_PAUSE, AUDIO_CMD_RESUME or AUDIO_CMD_STOP. +*\*\return AUDIO_OK if all operations succeed, AUDIO_FAIL else. +**/ +static uint8_t AudioCmd(uint8_t* pbuf, uint32_t size, uint8_t cmd) +{ + /* Check the current state */ + if ((AudioState == AUDIO_STATE_INACTIVE) || (AudioState == AUDIO_STATE_ERROR)) + { + AudioState = AUDIO_STATE_ERROR; + return AUDIO_FAIL; + } + + switch (cmd) + { + /* Process the PLAY command ----------------------------*/ + case AUDIO_CMD_PLAY: + /* If current state is Active or Stopped */ + if ((AudioState == AUDIO_STATE_ACTIVE) || (AudioState == AUDIO_STATE_STOPPED) || (AudioState == AUDIO_STATE_PLAYING)) + { + I2S_TX_DMA_Add_SIZE_Set(pbuf, (size/2)); + + AudioState = AUDIO_STATE_PLAYING; + return AUDIO_OK; + } + /* If current state is Paused */ + else if (AudioState == AUDIO_STATE_PAUSED) + { + I2S_Play_Start(); + AudioState = AUDIO_STATE_PLAYING; + return AUDIO_OK; + } + else /* Not allowed command */ + { + return AUDIO_FAIL; + } + + /* Process the STOP command ----------------------------*/ + case AUDIO_CMD_STOP: + if (AudioState != AUDIO_STATE_PLAYING) + { + /* Unsupported command */ + return AUDIO_FAIL; + } + else + { + I2S_Play_Stop(); + AudioState = AUDIO_STATE_STOPPED; + return AUDIO_OK; + } + + /* Process the PAUSE command */ + case AUDIO_CMD_PAUSE: + if (AudioState != AUDIO_STATE_PLAYING) + { + /* Unsupported command */ + return AUDIO_FAIL; + } + else + { + I2S_Play_Stop(); + AudioState = AUDIO_STATE_PAUSED; + return AUDIO_OK; + } + + /* Unsupported command ---------------------------------*/ + default: + return AUDIO_FAIL; + } +} + +/** +*\*\name VolumeCtrl. +*\*\fun Set the volume level in % +*\*\param vol: volume level to be set in % (from 0% to 100%) +*\*\return AUDIO_OK if all operations succeed, AUDIO_FAIL else. +**/ +static uint8_t VolumeCtrl(uint8_t vol) +{ + /* Call low layer volume setting function */ + WM8978_SetOUT1Volume(vol); + + return AUDIO_OK; +} + +/** +*\*\name MuteCtrl. +*\*\fun Mute or Unmute the audio current output +*\*\param cmd: can be 0 to unmute, or 1 to mute. +*\*\return AUDIO_OK if all operations succeed, AUDIO_FAIL else. +**/ +static uint8_t MuteCtrl(uint8_t cmd) +{ + /* Call low layer mute setting function */ + WM8978_OutMute(cmd); + return AUDIO_OK; +} + +/** +*\*\name PeriodicTC. +*\*\fun PeriodicTC. +*\*\param none +*\*\return AUDIO_OK if all operations succeed, AUDIO_FAIL else. +**/ +static uint8_t PeriodicTC(uint8_t cmd) +{ + return AUDIO_OK; +} + +/** +*\*\name GetState. +*\*\fun Return the current state of the audio machine +*\*\param none +*\*\return Current State. +**/ +static uint8_t GetState(void) +{ + return AudioState; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core.h new file mode 100644 index 0000000000..62288096dc --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core.h @@ -0,0 +1,97 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_cdc_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_CDC_CORE_H_ +#define __USB_CDC_CORE_H_ + +#include "usbd_ioreq.h" + +#define USB_CDC_CONFIG_DESC_SIZ (67) + +#define DEVICE_CLASS_CDC 0x02 +#define DEVICE_SUBCLASS_CDC 0x00 + + +#define STANDARD_ENDPOINT_DESC_SIZE 0x09 + +#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE + +#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE + +/* CDC Requests */ +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 +#define NO_CMD 0xFF + +typedef struct _CDC_IF_PROP +{ + uint16_t (*pIf_Init) (void); + uint16_t (*pIf_DeInit) (void); + uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len); + uint16_t (*pIf_DataTx) (void); + uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len); +}CDC_IF_Prop_TypeDef; + + +extern USBD_Class_cb_TypeDef USBD_CDC_cb; + + +#endif /* __USB_CDC_CORE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core_loopback.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core_loopback.h new file mode 100644 index 0000000000..264a81fc09 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/inc/usbd_cdc_core_loopback.h @@ -0,0 +1,80 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_cdc_core_loopback.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_CDC_CORE_H_ +#define __USB_CDC_CORE_H_ + +#include "usbd_ioreq.h" + +#define USB_CDC_CONFIG_DESC_SIZ (67) +#define USB_CDC_DESC_SIZ (67-9) + +#define DEVICE_CLASS_CDC 0x02 +#define DEVICE_SUBCLASS_CDC 0x00 + +#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE + +#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE + +typedef struct _CDC_IF_PROP +{ + uint16_t (*pIf_DataTx) (void); + uint16_t (*pIf_DataRx) (uint32_t Len); +}CDC_IF_Prop_TypeDef; + + +extern USBD_Class_cb_TypeDef USBD_CDC_cb; + + +#endif /* __USB_CDC_CORE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core.c new file mode 100644 index 0000000000..699869e912 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core.c @@ -0,0 +1,695 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_cdc_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_cdc_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "usbhs_bsp.h" + +#define USB_CDC_IDLE 0 +#define USB_CDC_BUSY 1 +#define USB_CDC_ZLP 2 + +/* CDC Device library callbacks */ +uint8_t USBD_CDC_Init (void *pdev, uint8_t cfgidx); +uint8_t USBD_CDC_DeInit (void *pdev, uint8_t cfgidx); +uint8_t USBD_CDC_Setup (void *pdev, USB_SETUP_REQ *req); +uint8_t USBD_CDC_EP0_RxReady (void *pdev); +uint8_t USBD_CDC_DataIn (void *pdev, uint8_t epnum); +uint8_t USBD_CDC_DataOut (void *pdev, uint8_t epnum); +uint8_t USBD_CDC_SOF (void *pdev); + +/* CDC specific management functions */ +static void Handle_USBAsynchXfer (void *pdev); +static uint8_t *USBD_CDC_GetCfgDesc (uint8_t speed, uint16_t *length); +static uint8_t *USBD_CDC_GetOtherCfgDesc (uint8_t speed, uint16_t *length); + + +extern CDC_IF_Prop_TypeDef APP_FOPS; +extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_CDC_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static __IO uint32_t USBD_CDC_AltSet __ALIGN_END = 0; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ; + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SIZE] __ALIGN_END ; + +uint32_t APP_Rx_ptr_in = 0; +uint32_t APP_Rx_ptr_out = 0; +uint32_t APP_Rx_length = 0; + +uint8_t USB_Tx_State = USB_CDC_IDLE; + +static uint32_t cdcCmd = 0xFF; +static uint32_t cdcLen = 0; + +/* CDC interface class callbacks structure */ +USBD_Class_cb_TypeDef USBD_CDC_cb = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + USBD_CDC_SOF, + NULL, + NULL, + USBD_CDC_GetCfgDesc, + USBD_CDC_GetOtherCfgDesc, /* use same cobfig as per FS */ +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength */ + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 100 mA */ + + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval */ + /*---------------------------------------------------------------------------*/ + + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass */ + 0x00, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval */ +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_CDC_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; + +/** +*\*\name USBD_CDC_Init. +*\*\fun Initialize the CDC interface. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CDC_Init (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Open(pdev, CDC_IN_EP, CDC_DATA_IN_PACKET_SIZE, USB_EP_BULK); + + /* Open EP OUT */ + USBDEV_EP_Open(pdev, CDC_OUT_EP, CDC_DATA_OUT_PACKET_SIZE, USB_EP_BULK); + + /* Open Command IN EP */ + USBDEV_EP_Open(pdev, CDC_CMD_EP, CDC_CMD_PACKET_SIZE, USB_EP_INT); + + /* Initialize the Interface physical components */ + APP_FOPS.pIf_Init(); + + /* Prepare Out endpoint to receive next packet */ + USBDEV_EP_PrepareRx(pdev, CDC_OUT_EP, (uint8_t*)(USB_Rx_Buffer), CDC_DATA_OUT_PACKET_SIZE); + + return USBD_OK; +} + +/** +*\*\name USBD_CDC_DeInit. +*\*\fun DeInitialize the CDC layer. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CDC_DeInit (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Close(pdev, CDC_IN_EP); + + /* Open EP OUT */ + USBDEV_EP_Close(pdev, CDC_OUT_EP); + + /* Open Command IN EP */ + USBDEV_EP_Close(pdev, CDC_CMD_EP); + + /* Restore default state of the Interface physical components */ + APP_FOPS.pIf_DeInit(); + + return USBD_OK; +} + +/** +*\*\name USBD_CDC_Setup +*\*\fun Handle the CDC specific requests. +*\*\param pdev: device instance. +*\*\param req: usb requests +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_Setup (void *pdev, USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* CDC Class Requests -------------------------------*/ + case USB_REQ_TYPE_CLASS : + /* Check if the request is a data setup packet */ + if (req->wLength) + { + /* Check if the request is Device-to-Host */ + if (req->bmRequest & 0x80) + { + /* Get the data to be sent to Host from interface layer */ + APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength); + + /* Send the data to the host */ + USBD_CtrlSendData(pdev, CmdBuff, req->wLength); + } + else /* Host-to-Device request */ + { + /* Set the value of the current command to be processed */ + cdcCmd = req->bRequest; + cdcLen = req->wLength; + + /* Prepare the reception of the buffer over EP0 + Next step: the received data will be managed in usbd_cdc_EP0_TxSent() + function. */ + USBD_CtrlPrepareRx (pdev, CmdBuff, req->wLength); + } + } + else /* No Data request */ + { + /* Transfer the command to the interface layer */ + APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0); + } + break; + + /* Standard Requests -------------------------------*/ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_CtrlError (pdev, req); + return USBD_FAIL; + + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData (pdev, (uint8_t *)&USBD_CDC_AltSet, 1); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) + { + USBD_CDC_AltSet = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtrlError (pdev, req); + } + break; + + default: + break; + } + break; + + default: + USBD_CtrlError (pdev, req); + return USBD_FAIL; + } + return USBD_OK; +} + +/** +*\*\name USBD_CDC_EP0_RxReady +*\*\fun Data received on control endpoint. +*\*\param pdev: device instance. +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_EP0_RxReady (void *pdev) +{ + if (cdcCmd != NO_CMD) + { + /* Process the data */ + APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen); + /* Reset the command variable to default value */ + cdcCmd = NO_CMD; + } + + return USBD_OK; +} + + +/** +*\*\name USBD_CDC_DataIn. +*\*\fun handle data IN Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CDC_DataIn (void *pdev, uint8_t epnum) +{ + uint16_t USB_Tx_ptr; + uint16_t USB_Tx_length; + + if (USB_Tx_State == USB_CDC_BUSY) + { + if (APP_Rx_length == 0) + { + USB_Tx_State = USB_CDC_IDLE; + } + else + { + if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; + + APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; + APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; + } + else + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = APP_Rx_length; + + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0; + if(USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_State = USB_CDC_ZLP; + } + } + + /* Prepare the available data buffer to be sent on IN endpoint */ + USBDEV_EP_Tx (pdev, CDC_IN_EP, (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], USB_Tx_length); + return USBD_OK; + } + } + + /* Avoid any asynchronous transfer during ZLP */ + if (USB_Tx_State == USB_CDC_ZLP) + { + /*Send ZLP to indicate the end of the current transfer */ + USBDEV_EP_Tx (pdev, CDC_IN_EP, NULL, 0); + + USB_Tx_State = USB_CDC_IDLE; + } + return USBD_OK; +} + +/** +*\*\name USBD_CDC_DataOut. +*\*\fun handle data OUT Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CDC_DataOut (void *pdev, uint8_t epnum) +{ + uint16_t USB_Rx_Cnt; + + /* Get the received data buffer and update the counter */ + USB_Rx_Cnt = ((USB_CORE_MODULE*)pdev)->dev.out_ep[epnum].xfer_count; + + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application Xfer */ + APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt); + + /* Prepare Out endpoint to receive next packet */ + USBDEV_EP_PrepareRx(pdev, CDC_OUT_EP, (uint8_t*)(USB_Rx_Buffer), CDC_DATA_OUT_PACKET_SIZE); + + return USBD_OK; +} + +/** +*\*\name USBD_CDC_SOF. +*\*\fun Start Of Frame event management. +*\*\param pdev: device instance. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CDC_SOF (void *pdev) +{ + static uint32_t FrameCount = 0; + + if (FrameCount++ == CDC_IN_FRAME_INTERVAL) + { + /* Reset the frame counter */ + FrameCount = 0; + + /* Check the data to be sent through IN pipe */ + Handle_USBAsynchXfer(pdev); + } + + return USBD_OK; +} + +/** +*\*\name Handle_USBAsynchXfer. +*\*\fun process the data received from usart and send through USB to host. +*\*\param pdev: device instance. +*\*\return USBD_OK. +*\*\ +**/ +static void Handle_USBAsynchXfer (void *pdev) +{ + uint16_t USB_Tx_ptr; + uint16_t USB_Tx_length; + + if(USB_Tx_State == USB_CDC_IDLE) + { + if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) + { + APP_Rx_ptr_out = 0; + } + + if(APP_Rx_ptr_out == APP_Rx_ptr_in) + { + USB_Tx_State = USB_CDC_IDLE; + return; + } + + if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */ + { + APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; + } + else + { + APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; + } + + if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; + + APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; + APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; + USB_Tx_State = USB_CDC_BUSY; + } + else + { + USB_Tx_ptr = APP_Rx_ptr_out; + USB_Tx_length = APP_Rx_length; + + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0; + if(USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) + { + USB_Tx_State = USB_CDC_ZLP; + } + else + { + USB_Tx_State = USB_CDC_BUSY; + } + } + USBDEV_EP_Tx (pdev, CDC_IN_EP, (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], USB_Tx_length); + } +} + +/** +*\*\name USBD_CDC_GetCfgDesc. +*\*\fun Return configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +*\*\ +**/ +static uint8_t *USBD_CDC_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; +} + +/** +*\*\name USBD_CDC_GetOtherCfgDesc. +*\*\fun Return configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +*\*\ +**/ +static uint8_t *USBD_CDC_GetOtherCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_CDC_OtherCfgDesc); + return USBD_CDC_OtherCfgDesc; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core_loopback.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core_loopback.c new file mode 100644 index 0000000000..1c34ca15d6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/cdc/src/usbd_cdc_core_loopback.c @@ -0,0 +1,511 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_cdc_core_loopback.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_cdc_core_loopback.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +#define USB_CDC_IDLE 0 +#define USB_CDC_BUSY 1 +#define USB_CDC_ZLP 2 + +/********************************************* + CDC Device library callbacks + *********************************************/ +uint8_t USBD_CDC_Init (void *pdev, uint8_t cfgidx); +uint8_t USBD_CDC_DeInit (void *pdev, uint8_t cfgidx); +uint8_t USBD_CDC_Setup (void *pdev, USB_SETUP_REQ *req); +uint8_t USBD_CDC_EP0_RxReady (void *pdev); +uint8_t USBD_CDC_DataIn (void *pdev, uint8_t epnum); +uint8_t USBD_CDC_DataOut (void *pdev, uint8_t epnum); + +/********************************************* + CDC specific management functions + *********************************************/ +static uint8_t *USBD_CDC_GetCfgDesc (uint8_t speed, uint16_t *length); +static uint8_t *USBD_CDC_GetOtherCfgDesc (uint8_t speed, uint16_t *length); + +extern CDC_IF_Prop_TypeDef APP_FOPS; +extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; + +extern uint8_t Rxbuffer[CDC_DATA_MAX_PACKET_SIZE]; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_CDC_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static __IO uint32_t USBD_CDC_AltSet __ALIGN_END = 0; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SIZE] __ALIGN_END ; + +/* CDC interface class callbacks structure */ +USBD_Class_cb_TypeDef USBD_CDC_cb = +{ + USBD_CDC_Init, + USBD_CDC_DeInit, + USBD_CDC_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_EP0_RxReady, + USBD_CDC_DataIn, + USBD_CDC_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_GetCfgDesc, + USBD_CDC_GetOtherCfgDesc, /* use same cobfig as per FS */ +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength */ + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 100 mA */ + + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0x10, /* bInterval */ + /*---------------------------------------------------------------------------*/ + + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass */ + 0x00, /* bInterfaceProtocol */ + 0x00, /* iInterface */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval */ +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_CDC_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval */ +}; + +/** +*\*\name USBD_CDC_Init. +*\*\fun Initialize the CDC interface. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_Init (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Open(pdev, CDC_IN_EP, CDC_DATA_IN_PACKET_SIZE, USB_EP_BULK); + + /* Open EP OUT */ + USBDEV_EP_Open(pdev, CDC_OUT_EP, CDC_DATA_OUT_PACKET_SIZE, USB_EP_BULK); + + /* Open Command IN EP */ + USBDEV_EP_Open(pdev, CDC_CMD_EP, CDC_CMD_PACKET_SIZE, USB_EP_INT); + + /* Prepare Out endpoint to receive next packet */ + USBDEV_EP_PrepareRx(pdev, CDC_OUT_EP, (uint8_t*)(Rxbuffer), CDC_DATA_OUT_PACKET_SIZE); + + return USBD_OK; +} + +/** +*\*\name USBD_CDC_DeInit. +*\*\fun DeInitialize the CDC layer. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_DeInit (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Close(pdev, CDC_IN_EP); + + /* Open EP OUT */ + USBDEV_EP_Close(pdev, CDC_OUT_EP); + + /* Open Command IN EP */ + USBDEV_EP_Close(pdev, CDC_CMD_EP); + + return USBD_OK; +} + +/** +*\*\name USBD_CDC_Setup +*\*\fun Handle the CDC specific requests. +*\*\param pdev: device instance. +*\*\param req: usb requests +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_Setup (void *pdev, USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* CDC Class Requests -------------------------------*/ + case USB_REQ_TYPE_CLASS : + /* Check if the request is a data setup packet */ + if (req->wLength) + { + /* Check if the request is Device-to-Host */ + if (req->bmRequest & 0x80) + { + /* STALL request */ + USBD_CtrlError (pdev, req); + } + else /* Host-to-Device request */ + { + /* Prepare the reception of the buffer over EP0 + Next step: the received data will be managed in USBD_CDC_EP0_TxSent() + function. */ + USBD_CtrlPrepareRx (pdev, CmdBuff, req->wLength); + } + } + else /* No Data request */ + { + /* do nothing */ + } + + return USBD_OK; + + default: + USBD_CtrlError (pdev, req); + return USBD_FAIL; + + /* Standard Requests -------------------------------*/ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_CtrlError (pdev, req); + return USBD_FAIL; + + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData (pdev, (uint8_t *)&USBD_CDC_AltSet, 1); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) + { + USBD_CDC_AltSet = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtrlError (pdev, req); + } + break; + } + } + return USBD_OK; +} + +/** +*\*\name USBD_CDC_EP0_RxReady +*\*\fun Data received on control endpoint. +*\*\param pdev: device instance. +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_EP0_RxReady (void *pdev) +{ + return USBD_OK; +} + + +/** +*\*\name USBD_CDC_DataIn. +*\*\fun handle data IN Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_DataIn (void *pdev, uint8_t epnum) +{ + /* inform application layer that data was sent */ + APP_FOPS.pIf_DataTx(); + return USBD_OK; +} + +/** +*\*\name USBD_CDC_DataOut. +*\*\fun handle data OUT Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +**/ +uint8_t USBD_CDC_DataOut (void *pdev, uint8_t epnum) +{ + uint16_t USB_Rx_Cnt; + + /* Get the received data buffer and update the counter */ + USB_Rx_Cnt = ((USB_CORE_MODULE*)pdev)->dev.out_ep[epnum].xfer_count; + + /* pass received data count to application layer */ + APP_FOPS.pIf_DataRx(USB_Rx_Cnt); + + return USBD_OK; +} + +/** +*\*\name USBD_CDC_GetCfgDesc. +*\*\fun Return configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +**/ +static uint8_t *USBD_CDC_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_CDC_CfgDesc); + return USBD_CDC_CfgDesc; +} + +/** +*\*\name USBD_CDC_GetOtherCfgDesc. +*\*\fun Return configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +**/ +static uint8_t *USBD_CDC_GetOtherCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_CDC_OtherCfgDesc); + return USBD_CDC_OtherCfgDesc; +} + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/inc/usbd_customhid_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/inc/usbd_customhid_core.h new file mode 100644 index 0000000000..645ea268b0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/inc/usbd_customhid_core.h @@ -0,0 +1,97 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_customhid_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USB_CUSTOMHID_CORE_H_ +#define __USB_CUSTOMHID_CORE_H_ + +#include "usbd_ioreq.h" + +#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 116+4+3+3 + +#define USB_CUSTOM_HID_CONFIG_DESC_SIZ 41+2 +#define USB_CUSTOM_HID_DESC_SIZ 9 + +#define CUSTOM_HID_DESCRIPTOR_TYPE 0x21 +#define CUSTOM_HID_REPORT_DESC 0x22 + + +#define CUSTOM_HID_REQ_SET_PROTOCOL 0x0B +#define CUSTOM_HID_REQ_GET_PROTOCOL 0x03 + +#define CUSTOM_HID_REQ_SET_IDLE 0x0A +#define CUSTOM_HID_REQ_GET_IDLE 0x02 + +#define CUSTOM_HID_REQ_SET_REPORT 0x09 +#define CUSTOM_HID_REQ_GET_REPORT 0x01 + +#define LED1_REPORT_ID 0x01 +#define LED1_REPORT_COUNT 0x01 + +#define LED2_REPORT_ID 0x02 +#define LED2_REPORT_COUNT 0x01 + +#define LED3_REPORT_ID 0x03 +#define LED3_REPORT_COUNT 0x01 + +#define LED4_REPORT_ID 0x04 +#define LED4_REPORT_COUNT 0x01 + +#define KEY_REPORT_ID 0x05 +#define TAMPER_REPORT_ID 0x06 +#define ADC_REPORT_ID 0x07 + +extern USBD_Class_cb_TypeDef USBD_CUSTOMHID_cb; + +uint8_t USBD_CUSTOM_HID_SendReport (USB_CORE_MODULE *pdev, uint8_t *report, uint16_t len); + +#endif /* __USB_CUSTOMHID_CORE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/src/usbd_customhid_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/src/usbd_customhid_core.c new file mode 100644 index 0000000000..58124c4c9d --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/customhid/src/usbd_customhid_core.c @@ -0,0 +1,584 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_customhid_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_customhid_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "n32h76x_78x_gpio.h" +#include "usbhs_bsp.h" + +uint8_t USBD_CUSTOM_HID_Init (void *pdev, uint8_t cfgidx); +uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, uint8_t cfgidx); +uint8_t USBD_CUSTOM_HID_Setup (void *pdev, USB_SETUP_REQ *req); +uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length); +uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, uint8_t epnum); +uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, uint8_t epnum); +uint8_t USBD_CUSTOM_HID_EP0_RxReady (void *pdev); + + +USBD_Class_cb_TypeDef USBD_CUSTOMHID_cb = +{ + USBD_CUSTOM_HID_Init, + USBD_CUSTOM_HID_DeInit, + USBD_CUSTOM_HID_Setup, + NULL, /*EP0_TxSent*/ + USBD_CUSTOM_HID_EP0_RxReady, /*EP0_RxReady*/ /* STATUS STAGE IN */ + USBD_CUSTOM_HID_DataIn, /*DataIn*/ + USBD_CUSTOM_HID_DataOut, + NULL, /*SOF */ + NULL, /*IsoINIncomplete*/ + NULL, /*IsoOUTIncomplete)*/ + USBD_CUSTOM_HID_GetCfgDesc, + USBD_CUSTOM_HID_GetCfgDesc, +}; + +uint8_t Report_buf[4]; +uint8_t USBD_HID_Report_ID=0; +__IO uint32_t IsReportAvailable = 0; +extern uint8_t PrevXferDone; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t Report_buf[4] __ALIGN_END; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_CUSTOM_HID_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Custom HID interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + 0x00, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x02, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0x00, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Custom HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x10, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Custom HID endpoints ***********/ + /* 27 */ + 0x08, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + LOBYTE(HID_IN_PACKET), /* wMaxPacketSize: */ + HIBYTE(HID_IN_PACKET), + 0x00, + 0x01, /* bInterval: Polling Interval (1 ms) */ + /* 34 */ + + 0x08, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + /* Endpoint descriptor type */ + HID_OUT_EP, /* bEndpointAddress: */ + /* Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + LOBYTE(HID_OUT_PACKET), /* wMaxPacketSize: */ + HIBYTE(HID_OUT_PACKET), + 0x00, + 0x10, /* bInterval: Polling Interval (16 ms) */ + /* 41 */ +} ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif + +__ALIGN_BEGIN static uint8_t CustomHID_ReportDesc[USBD_CUSTOM_HID_REPORT_DESC_SIZE] __ALIGN_END = +{ + 0x06, 0xFF, 0x00, /* USAGE_PAGE (Vendor Page: 0xFF00) */ + 0x09, 0x01, /* USAGE (Demo Kit) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + /* 6 */ + + /* Led 1 */ + 0x85, 0x01, /* REPORT_ID (1) */ + 0x09, 0x01, /* USAGE (LED 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0x00, 0x0C, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, 0x01, /* REPORT_ID (1) */ + 0x09, 0x01, /* USAGE (LED 1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 26 */ + + /* Led 2 */ + 0x85, 0x02, /* REPORT_ID 2 a */ + 0x09, 0x02, /* USAGE (LED 2) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0x00, 0x0C, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, 0x02, /* REPORT_ID (2) */ + 0x09, 0x02, /* USAGE (LED 2) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 46 */ + + /* Led 3 */ + 0x85, 0x03, /* REPORT_ID (3) */ + 0x09, 0x03, /* USAGE (LED 3) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0x00, 0x0C, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, 0x03, /* REPORT_ID (3) */ + 0x09, 0x03, /* USAGE (LED 3) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 66 */ + + /* Led 4 */ + 0x85, 0x04, /* REPORT_ID (4) */ + 0x09, 0x04, /* USAGE (LED 4) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0x00, 0x0C, /* REPORT_COUNT (1) */ + 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x85, 0x04, /* REPORT_ID (4) */ + 0x09, 0x04, /* USAGE (LED 4) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + /* 86 */ + + /* key Push Button */ + 0x85, 0x05, /* REPORT_ID (5) */ + 0x09, 0x05, /* USAGE (Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x02, /* REPORT_SIZE (1) */ + 0x96, 0x00, 0x0C, /* REPORT_COUNT (1) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + + 0x09, 0x05, /* USAGE (Push Button) */ + 0x75, 0x02, /* REPORT_SIZE (1) */ + 0x96, 0x00, 0x0C, /* REPORT_COUNT (1) */ + 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */ + 0x85, 0x05, /* REPORT_ID (2) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */ + /* 114 */ + + 0xc0 /* END_COLLECTION */ +}; + +/** +*\*\name USBD_CUSTOM_HID_Init. +*\*\fun Initialize the HID interface. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_Init (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Open(pdev, HID_IN_EP, HID_IN_PACKET, USB_EP_INT); + /* Open EP OUT */ + USBDEV_EP_Open(pdev, HID_OUT_EP, HID_OUT_PACKET, USB_EP_INT); + /*Receive Data*/ + USBDEV_EP_PrepareRx(pdev, HID_OUT_EP, Report_buf, 2); + + return USBD_OK; +} + +/** +*\*\name USBD_CUSTOM_HID_DeInit. +*\*\fun DeInitialize the HID layer. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, uint8_t cfgidx) +{ + /* Close HID EPs */ + USBDEV_EP_Close (pdev , HID_IN_EP); + USBDEV_EP_Close (pdev , HID_OUT_EP); + return USBD_OK; +} + +/** +*\*\name USBD_CUSTOM_HID_Setup. +*\*\fun Handle the HID specific requests. +*\*\param pdev: device instance. +*\*\param req: usb requests +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_Setup (void *pdev, USB_SETUP_REQ *req) +{ + uint8_t USBD_HID_Report_LENGTH=0; + uint16_t len = 0; + uint8_t *pbuf = NULL; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case CUSTOM_HID_REQ_SET_PROTOCOL: + USBD_HID_Protocol = (uint8_t)(req->wValue); + break; + + case CUSTOM_HID_REQ_GET_PROTOCOL: + USBD_CtrlSendData(pdev, (uint8_t *)&USBD_HID_Protocol, 1); + break; + + case CUSTOM_HID_REQ_SET_IDLE: + USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); + break; + + case CUSTOM_HID_REQ_GET_IDLE: + USBD_CtrlSendData(pdev, (uint8_t *)&USBD_HID_IdleState, 1); + break; + + case CUSTOM_HID_REQ_SET_REPORT: + IsReportAvailable = 1; + USBD_HID_Report_ID = (uint8_t)(req->wValue); + USBD_HID_Report_LENGTH = (uint8_t)(req->wLength); + USBD_CtrlPrepareRx (pdev, Report_buf, USBD_HID_Report_LENGTH); + break; + + default: + USBD_CtrlError (pdev, req); + return USBD_FAIL; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if( req->wValue >> 8 == CUSTOM_HID_REPORT_DESC) + { + len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE , req->wLength); + pbuf = (uint8_t*)CustomHID_ReportDesc; + } + else if( req->wValue >> 8 == CUSTOM_HID_DESCRIPTOR_TYPE) + { + pbuf = (uint8_t*)USBD_CUSTOM_HID_CfgDesc + 0x12; + len = MIN(USB_CUSTOM_HID_DESC_SIZ , req->wLength); + } + + USBD_CtrlSendData (pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData (pdev, (uint8_t *)&USBD_HID_AltSet, 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_HID_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + } + return USBD_OK; +} + +/** +*\*\name USBD_CUSTOM_HID_SendReport. +*\*\fun Send HID Report. +*\*\param pdev: device instance. +*\*\param report: pointer to report. +*\*\param len: length of report. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_SendReport (USB_CORE_MODULE *pdev, uint8_t *report, uint16_t len) +{ + if (pdev->dev.device_status == USB_CONFIGURED) + { + USBDEV_EP_Tx(pdev, HID_IN_EP, report, len); + } + return USBD_OK; +} + +/** +*\*\name USBD_CUSTOM_HID_GetCfgDesc. +*\*\fun return configuration descriptor. +*\*\param speed : current device speed. +*\*\param length : pointer data length. +*\*\return pointer to descriptor buffer. +*\*\ +**/ +uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_CUSTOM_HID_CfgDesc); + return USBD_CUSTOM_HID_CfgDesc; +} + +/** +*\*\name USBD_CUSTOM_HID_DataIn. +*\*\fun handle data IN Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, uint8_t epnum) +{ + /* Ensure that the FIFO is empty before a new transfer, this condition could + be caused by a new transfer before the end of the previous transfer */ + USBDEV_EP_Flush(pdev, HID_IN_EP); + + if (epnum == (HID_IN_EP & 0x0F)) + { + PrevXferDone = 1; + } + + return USBD_OK; +} + +/** +*\*\name USBD_CUSTOM_HID_DataOut. +*\*\fun handle data OUT Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, uint8_t epnum) +{ + Bit_OperateType Led_State; + if (epnum == HID_OUT_EP) + { + if (Report_buf[1] == 0u) + { + Led_State = Bit_RESET; + } + else + { + Led_State = Bit_SET; + } + switch (Report_buf[0]) + { + case 1: /* Led 1 */ + if (Led_State != Bit_RESET) + { + LED_On(LED1_PORT, LED1_PIN); + } + else + { + LED_Off(LED1_PORT, LED1_PIN); + } + break; + + case 2: /* Led 2 */ + if (Led_State != Bit_RESET) + { + LED_On(LED2_PORT, LED2_PIN); + } + else + { + LED_Off(LED2_PORT, LED2_PIN); + } + break; + case 3: /* Led 3 */ + if (Led_State != Bit_RESET) + { + LED_On(LED3_PORT, LED3_PIN); + } + else + { + LED_Off(LED3_PORT, LED3_PIN); + } + break; + default: + LED_Off(LED1_PORT, LED1_PIN); + LED_Off(LED2_PORT, LED2_PIN); + LED_Off(LED3_PORT, LED3_PIN); + break; + } + } + + USBDEV_EP_PrepareRx(pdev, HID_OUT_EP,Report_buf,2); + USBDEV_SetEPStatus(pdev, HID_OUT_EP, USB_EP_RX_VALID); + + return USBD_OK; +} + +/** +*\*\name USBD_CUSTOM_HID_EP0_RxReady. +*\*\fun Handles control request data. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_CUSTOM_HID_EP0_RxReady(void *pdev) +{ + Bit_OperateType Led_State; + + if (IsReportAvailable == 1) + { + IsReportAvailable = 0; + if (Report_buf[1] == 0) + { + Led_State = Bit_RESET; + } + else + { + Led_State = Bit_SET; + } + + switch (Report_buf[0]) + { + case 1: /* Led 1 */ + if (Led_State != Bit_RESET) + { + LED_On(LED1_PORT, LED1_PIN); + } + else + { + LED_Off(LED1_PORT, LED1_PIN); + } + break; + + case 2: /* Led 2 */ + if (Led_State != Bit_RESET) + { + LED_On(LED2_PORT, LED2_PIN); + } + else + { + LED_Off(LED2_PORT, LED2_PIN); + } + break; + case 3: /* Led 3 */ + if (Led_State != Bit_RESET) + { + LED_On(LED3_PORT, LED3_PIN); + } + else + { + LED_Off(LED3_PORT, LED3_PIN); + } + break; + default: + LED_Off(LED1_PORT, LED1_PIN); + LED_Off(LED2_PORT, LED2_PIN); + LED_Off(LED3_PORT, LED3_PIN); + break; + } + } + return USBD_OK; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/inc/usbd_hid_cdc_composite.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/inc/usbd_hid_cdc_composite.h new file mode 100644 index 0000000000..03f1e54886 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/inc/usbd_hid_cdc_composite.h @@ -0,0 +1,63 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_hid_cdc_composite.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_HID_CDC_COMPOSITE_H_ +#define __USB_HID_CDC_COMPOSITE_H_ + +#include "usbd_ioreq.h" + + +extern USBD_Class_cb_TypeDef USBD_HID_CDC_cb; + +#endif /* __USB_HID_CDC_COMPOSITE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/src/usbd_hid_cdc_composite.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/src/usbd_hid_cdc_composite.c new file mode 100644 index 0000000000..9c2a37e760 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_cdc_composite/src/usbd_hid_cdc_composite.c @@ -0,0 +1,402 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_hid_cdc_composite.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_customhid_core.h" +#include "usbd_cdc_core.h" +#include "usbd_hid_cdc_composite.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/* CDC Device library callbacks */ +extern uint8_t USBD_CDC_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CDC_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CDC_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_CDC_EP0_RxReady (void *pdev); +extern uint8_t USBD_CDC_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_CDC_DataOut (void *pdev, uint8_t epnum); +extern uint8_t USBD_CDC_SOF (void *pdev); + +/* HID Device library callbacks */ +extern uint8_t USBD_CUSTOM_HID_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CUSTOM_HID_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, uint8_t epnum); +extern uint8_t USBD_CUSTOM_HID_EP0_RxReady (void *pdev); + + +static uint8_t USBD_HID_CDC_Init (void *pdev , uint8_t cfgidx); +static uint8_t USBD_HID_CDC_DeInit (void *pdev , uint8_t cfgidx); + +/* Control Endpoints*/ +static uint8_t USBD_HID_CDC_Setup (void *pdev , USB_SETUP_REQ *req); +static uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev ); + +/* Class Specific Endpoints*/ +static uint8_t USBD_HID_CDC_DataIn (void *pdev , uint8_t epnum); +static uint8_t USBD_HID_CDC_DataOut (void *pdev , uint8_t epnum); +static uint8_t USBD_HID_CDC_SOF (void *pdev); +static uint8_t* USBD_HID_CDC_GetConfigDescriptor(uint8_t speed , uint16_t *length); + +#define USB_HID_CDC_CONFIG_DESC_SIZ (USB_CUSTOM_HID_CONFIG_DESC_SIZ -9 + USB_CDC_CONFIG_DESC_SIZ + 8) + +#define HID_INTERFACE 0x00 +#define CDC_COM_INTERFACE 0x01 + + +USBD_Class_cb_TypeDef USBD_HID_CDC_cb = +{ + USBD_HID_CDC_Init, + USBD_HID_CDC_DeInit, + USBD_HID_CDC_Setup, + NULL, + USBD_HID_CDC_EP0_RxReady, + USBD_HID_CDC_DataIn, + USBD_HID_CDC_DataOut, + USBD_HID_CDC_SOF, + NULL, + NULL, + USBD_HID_CDC_GetConfigDescriptor, + USBD_HID_CDC_GetConfigDescriptor, +}; + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB MSC/CDC device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_HID_CDC_CfgDesc[USB_HID_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_HID_CDC_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /*bNumInterfaces: 3 interfaces (2 for CDC, 1 for HID)*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of Custom HID interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + HID_INTERFACE,/*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x02, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x01, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0x00, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x10, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Custom HID endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x20, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ + + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + /* Endpoint descriptor type */ + HID_OUT_EP, /* bEndpointAddress: */ + /* Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize */ + 0x00, + 0x20, /* bInterval: Polling Interval (10 ms) */ + + /******** /IAD should be positioned just before the CDC interfaces ****** + IAD to associate the two CDC interfaces */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x01, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x01, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x02, /* bDataInterface: 2 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x01, /* bMasterInterface: Communication class interface */ + 0x02, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval */ +} ; + +/** + * @brief USBD_MSC_CDC_Init + * Initialize the MSC & CDC interfaces + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_CDC_Init (void *pdev, uint8_t cfgidx) +{ + /* HID initialization */ + USBD_CUSTOM_HID_Init(pdev, cfgidx); + + /* CDC initialization */ + USBD_CDC_Init(pdev, cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_Init + * DeInitialize the MSC/CDC interfaces + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_HID_CDC_DeInit(void *pdev, uint8_t cfgidx) +{ + /* HID De-initialization */ + USBD_CUSTOM_HID_DeInit(pdev,cfgidx); + + /* CDC De-initialization */ + USBD_CDC_DeInit(pdev,cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_Setup + * Handle the MSC/CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_HID_CDC_Setup(void *pdev, USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == HID_INTERFACE) + { + return (USBD_CUSTOM_HID_Setup(pdev, req)); + } + else + { + return (USBD_CDC_Setup(pdev, req)); + } + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) + { + return (USBD_CUSTOM_HID_Setup(pdev, req)); + } + else + { + return (USBD_CDC_Setup(pdev, req)); + } + + default: + break; + } + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_HID_CDC_GetConfigDescriptor(uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_HID_CDC_CfgDesc); + return USBD_HID_CDC_CfgDesc; +} + +/** + * @brief USBD_MSC_CDC_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_HID_CDC_DataIn (void *pdev, uint8_t epnum) +{ + /*DataIN can be for CDC or MSC */ + if (epnum == (CDC_IN_EP&0x0F)) + { + return (USBD_CDC_DataIn(pdev, epnum)); + } + else + { + return (USBD_CUSTOM_HID_DataIn(pdev, epnum)); + } +} + + +static uint8_t USBD_HID_CDC_DataOut(void *pdev , uint8_t epnum) +{ + /*DataOut can be for CDC */ + if(epnum == (CDC_OUT_EP&0x0F)) + { + return (USBD_CDC_DataOut(pdev, epnum)); + } + else + { + return (USBD_CUSTOM_HID_DataOut(pdev, epnum)); + } +} + + +static uint8_t USBD_HID_CDC_SOF (void *pdev) +{ + /*SOF processing needed for CDC */ + return (USBD_CDC_SOF(pdev)); +} + + +static uint8_t USBD_HID_CDC_EP0_RxReady(void *pdev) +{ + /*RxReady processing needed for CDC only*/ + return (USBD_CDC_EP0_RxReady(pdev)); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/inc/usbd_keyboard_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/inc/usbd_keyboard_core.h new file mode 100644 index 0000000000..5cadc59731 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/inc/usbd_keyboard_core.h @@ -0,0 +1,79 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_keyboard_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBD_KEYBOARD_CORE_H__ +#define __USBD_KEYBOARD_CORE_H__ + +#include "usbd_ioreq.h" + +#define KEYBOARD_CFGDESC_SIZE (41u) +#define KEYBOARD_DESC_SIZE (9u) +#define KEYBOARD_REPORT_DESC_SIZE (66u) + +#define KEYBOARD_DESCRIPTOR_TYPE (0x21u) +#define KEYBOARD_REPORT_DESC (0x22u) + + +#define KEYBOARD_REQ_SET_PROTOCOL (0x0Bu) +#define KEYBOARD_REQ_GET_PROTOCOL (0x03u) + +#define KEYBOARD_REQ_SET_IDLE (0x0Au) +#define KEYBOARD_REQ_GET_IDLE (0x02u) + + +extern USBD_Class_cb_TypeDef USBD_HID_Keyboard_cb; + +extern uint8_t usb_dev_mouse_txreport(USB_CORE_MODULE *pdev, uint8_t *report, uint16_t len); + +#endif // __USBD_KEYBOARD_CORE_H__ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/src/usbd_keyboard_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/src/usbd_keyboard_core.c new file mode 100644 index 0000000000..e0d296164f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_keyboard/src/usbd_keyboard_core.c @@ -0,0 +1,351 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_keyboard_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_keyboard_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "n32h76x_78x_gpio.h" +#include "usbhs_bsp.h" + +static uint8_t USBD_Keyboard_Init(void *pdev, uint8_t cfgidx); +static uint8_t USBD_Keyboard_Deinit(void *pdev, uint8_t cfgidx); +static uint8_t USBD_Keyboard_Setup(void *pdev, USB_SETUP_REQ *req); +static uint8_t *USBD_Keyboard_Getcfgdesc(uint8_t speed,uint16_t *length); +static uint8_t USBD_Keyboard_Datain(void *pdev, uint8_t epnum); +static uint8_t USBD_Keyboard_Dataout(void *pdev, uint8_t epnum); + +USBD_Class_cb_TypeDef USBD_HID_Keyboard_cb= +{ + USBD_Keyboard_Init, + USBD_Keyboard_Deinit, + USBD_Keyboard_Setup, + NULL, /*EP0_TxSent*/ + NULL, + USBD_Keyboard_Datain, + USBD_Keyboard_Dataout, + NULL, + NULL, + NULL, + USBD_Keyboard_Getcfgdesc, + USBD_Keyboard_Getcfgdesc, +}; + +__ALIGN_BEGIN static uint32_t USBD_Keyboard_AltSet __ALIGN_END = 0u; +__ALIGN_BEGIN static uint32_t USBD_Keyboard_Protocol __ALIGN_END = 0u; +__ALIGN_BEGIN static uint32_t USBD_Keyboard_IdleState __ALIGN_END = 0u; + +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_Keyboard_CfgDesc[KEYBOARD_CFGDESC_SIZE] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE,/* bDescriptorType: Configuration */ + KEYBOARD_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /*bNumInterfaces: 1 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing the configuration*/ + 0x80, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE, /*bDescriptorType: Interface descriptor type*/ + 0x00, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x02, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x01, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0x00, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + KEYBOARD_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x10, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x21, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + KEYBOARD_REPORT_DESC_SIZE, /*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + 0x08, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + HID_OUT_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_OUT_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 41 */ +} ; + +__ALIGN_BEGIN static uint8_t HID_KEYBOARD_ReportDesc[KEYBOARD_REPORT_DESC_SIZE] __ALIGN_END = +{ + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x00, // USAGE_MAXIMUM (Reserved (no event indicated)) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + 0x95, 0x06, // REPORT_COUNT (6) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x26, 0xff, 0x00, // LOGICAL_MAXIMUM (255) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0x15, 0x01, // LOGICAL_MINIMUM (1) + 0x95, 0x05, // REPORT_COUNT (5) + 0x75, 0x01, // REPORT_SIZE (1) + 0x05, 0x08, // USAGE_PAGE (LEDs) + 0x19, 0x01, // USAGE_MINIMUM (Num Lock) + 0x29, 0x05, // USAGE_MAXIMUM (Kana) + 0x91, 0x02, // OUTPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x03, // REPORT_SIZE (3) + 0x91, 0x03, // OUTPUT (Cnst,Var,Abs) + 0xc0 // END_COLLECTION +}; + +__IO uint8_t Report_buf[64]; + +/** +*\*\name USBD_Keyboard_Init. +*\*\fun Initialize the interface of KEYBOARD HID. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t USBD_Keyboard_Init(void *pdev, uint8_t cfgidx) +{ + USBDEV_EP_Open(pdev, HID_IN_EP, 8, USB_EP_INT); + USBDEV_EP_Open(pdev, HID_OUT_EP, HID_OUT_PACKET, USB_EP_INT); + USBDEV_EP_PrepareRx(pdev, HID_OUT_EP, (uint8_t *)Report_buf, 64); + USBDEV_SetEPStatus(pdev, HID_OUT_EP, USB_EP_RX_VALID); + + return USBD_OK; +} + +/** +*\*\name USBD_Keyboard_Deinit. +*\*\fun DeInitialize the interface of KEYBOARD HID. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t USBD_Keyboard_Deinit(void *pdev, uint8_t cfgidx) +{ + USBDEV_EP_Close(pdev, HID_IN_EP); + USBDEV_EP_Close(pdev, HID_OUT_EP); + + return USBD_OK; +} + +/** +*\*\name USBD_Keyboard_Setup. +*\*\fun Handle the KEYBOARD HID SETUP request. +*\*\param pdev: device instance. +*\*\param req: usb requests +*\*\return status. +*\*\ +**/ +static uint8_t USBD_Keyboard_Setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = 0u; + uint8_t *pbuf = NULL; + uint8_t status = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case KEYBOARD_REQ_SET_PROTOCOL: + USBD_Keyboard_Protocol = (uint8_t)(req->wValue); + break; + case KEYBOARD_REQ_GET_PROTOCOL: + USBD_CtrlSendData(pdev, (uint8_t *)&USBD_Keyboard_Protocol, 1u); + break; + case KEYBOARD_REQ_SET_IDLE: + USBD_Keyboard_IdleState = (uint8_t)(req->wValue >> 8u); + break; + case KEYBOARD_REQ_GET_IDLE: + USBD_CtrlSendData(pdev, (uint8_t *)&USBD_Keyboard_IdleState, 1u); + break; + default: + USBD_CtrlError(pdev, req); + status = USBD_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if((req->wValue >> 8u) == (uint16_t)KEYBOARD_REPORT_DESC) + { + len = (uint16_t)MIN(KEYBOARD_REPORT_DESC_SIZE , req->wLength); + pbuf = HID_KEYBOARD_ReportDesc; + } + else if((req->wValue >> 8u) == (uint16_t)KEYBOARD_DESCRIPTOR_TYPE) + { + pbuf = USBD_Keyboard_CfgDesc + 0x12; + len = (uint16_t)MIN(KEYBOARD_DESC_SIZE , req->wLength); + } + else + { + // + } + USBD_CtrlSendData(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData(pdev, (uint8_t *)&USBD_Keyboard_AltSet, 1u); + break; + case USB_REQ_SET_INTERFACE : + USBD_Keyboard_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return status; +} + +/** +*\*\name USBD_Keyboard_Getcfgdesc. +*\*\fun return configuration descriptor. +*\*\param speed : current device speed. +*\*\param length : pointer data length. +*\*\return pointer to descriptor buffer. +*\*\ +**/ +static uint8_t *USBD_Keyboard_Getcfgdesc(uint8_t speed, uint16_t *length) +{ + *length = (uint16_t)sizeof (USBD_Keyboard_CfgDesc); + return USBD_Keyboard_CfgDesc; +} + +/** +*\*\name USBD_Keyboard_Datain. +*\*\fun handle data IN Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t USBD_Keyboard_Datain(void *pdev, uint8_t epnum) +{ + USBDEV_EP_Flush(pdev, HID_IN_EP); + + return USBD_OK; +} + +/** +*\*\name USBD_Keyboard_Dataout. +*\*\fun handle the OUT data Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t USBD_Keyboard_Dataout(void *pdev, uint8_t epnum) +{ + if (epnum == HID_OUT_EP) + { + if(Report_buf[0] & 0x02) + { + LED_On(LED1_PORT, LED1_PIN); + } + else + { + LED_Off(LED1_PORT, LED1_PIN); + } + if(Report_buf[0] & 0x01) + { + LED_On(LED2_PORT, LED2_PIN); + } + else + { + LED_Off(LED2_PORT, LED2_PIN); + } + } + + USBDEV_EP_PrepareRx(pdev, HID_OUT_EP, (uint8_t *)Report_buf, 64); + USBDEV_SetEPStatus(pdev, HID_OUT_EP, USB_EP_RX_VALID); + + return USBD_OK; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/inc/usbd_msc_hid_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/inc/usbd_msc_hid_core.h new file mode 100644 index 0000000000..c01ad12743 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/inc/usbd_msc_hid_core.h @@ -0,0 +1,63 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_hid_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_MSC_HID_CORE_H_ +#define __USB_MSC_HID_CORE_H_ + +#include "usbd_ioreq.h" + + +extern USBD_Class_cb_TypeDef USBD_MSC_HID_cb; + +#endif /* __USB_HID_CORE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/src/usbd_msc_hid_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/src/usbd_msc_hid_core.c new file mode 100644 index 0000000000..f0aa0d972d --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/hid_msc_composite/src/usbd_msc_hid_core.c @@ -0,0 +1,338 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_hid_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_msc_hid_core.h" +#include "usbd_msc_core.h" +#include "usbd_customhid_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +static uint8_t USBD_MSC_HID_Init (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_MSC_HID_DeInit (void *pdev, + uint8_t cfgidx); + +static uint8_t USBD_MSC_HID_Setup (void *pdev, + USB_SETUP_REQ *req); + +static uint8_t *USBD_MSC_HID_GetCfgDesc (uint8_t speed, uint16_t *length); + +static uint8_t USBD_MSC_HID_DataIn (void *pdev, uint8_t epnum); +static uint8_t USBD_MSC_HID_DataOut(void *pdev , uint8_t epnum); + +#define HID_INTERFACE 0x0 +#define MSC_INTERFACE 0x1 + + +#define USB_MSC_HID_CONFIG_DESC_SIZ (USB_CUSTOM_HID_CONFIG_DESC_SIZ -9 + USB_MSC_CONFIG_DESC_SIZ) + +USBD_Class_cb_TypeDef USBD_MSC_HID_cb = +{ + USBD_MSC_HID_Init, + USBD_MSC_HID_DeInit, + USBD_MSC_HID_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_MSC_HID_DataIn, /*DataIn*/ + USBD_MSC_HID_DataOut, /*DataOut*/ + NULL, /*SOF */ + NULL, + NULL, + USBD_MSC_HID_GetCfgDesc, + USBD_MSC_HID_GetCfgDesc, /* use same config as per FS */ +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_MSC_HID_CfgDesc[USB_MSC_HID_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_HID_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x02, /*bNumInterfaces: 2 interface*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of HID interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x02, /*bNumEndpoints*/ + 0x03, /*bInterfaceClass: HID*/ + 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ + 0x01, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ + 0, /*iInterface: Index of string descriptor*/ + /******************** Descriptor of HID ********************/ + /* 18 */ + 0x09, /*bLength: HID Descriptor size*/ + CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ + 0x10, /*bcdHID: HID Class Spec release number*/ + 0x01, + 0x00, /*bCountryCode: Hardware target country*/ + 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ + 0x22, /*bDescriptorType*/ + USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, + /******************** Descriptor of HID endpoint ********************/ + /* 27 */ + 0x07, /*bLength: Endpoint Descriptor size*/ + USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ + + HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ + 0x03, /*bmAttributes: Interrupt endpoint*/ + HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 34 */ + + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + /* Endpoint descriptor type */ + HID_OUT_EP, /* bEndpointAddress: */ + /* Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize */ + 0x00, + 0x20, /* bInterval: Polling Interval (10 ms) */ + /* 41 */ + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + MSC_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /*Polling interval in milliseconds*/ +} ; + +/* Private function prototypes */ + +/********************************************* + MSC Device library callbacks +*********************************************/ +extern uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum); +extern uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length); +extern uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; + +/********************************************* + HID Device library callbacks +*********************************************/ +extern uint8_t USBD_CUSTOM_HID_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CUSTOM_HID_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CUSTOM_HID_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t *USBD_CUSTOM_HID_GetCfgDesc (uint8_t speed, uint16_t *length); +extern uint8_t USBD_CUSTOM_HID_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_CUSTOM_HID_DataOut (void *pdev, uint8_t epnum); +extern uint8_t USBD_CUSTOM_HID_EP0_RxReady (void *pdev); + +/** + * @brief USBD_MSC_HID_Init + * Initialize the MSC-HID interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_MSC_HID_Init (void *pdev, + uint8_t cfgidx) +{ + /* HID initialization */ + USBD_CUSTOM_HID_Init (pdev,cfgidx); + + /* MSC initialization */ + USBD_MSC_Init (pdev,cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_HID_DeInit + * DeInitialize the MSC_HID layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_MSC_HID_DeInit (void *pdev, + uint8_t cfgidx) +{ + /* HID De-initialization */ + USBD_CUSTOM_HID_DeInit (pdev,cfgidx); + + /* MSC De-initialization */ + USBD_MSC_DeInit (pdev,cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_HID_Setup + * Handle the MSC_HID specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_MSC_HID_Setup (void *pdev, + USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == HID_INTERFACE) + { + return (USBD_CUSTOM_HID_Setup(pdev, req)); + } + else + { + return (USBD_MSC_Setup(pdev, req)); + } + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) + { + return (USBD_CUSTOM_HID_Setup(pdev, req)); + } + else + { + return (USBD_MSC_Setup(pdev, req)); + } + } + return USBD_OK; +} + +/** + * @brief USBD_MSC_HID_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_MSC_HID_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_MSC_HID_CfgDesc); + return USBD_MSC_HID_CfgDesc; +} + +/** + * @brief USBD_MSC_HID_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_MSC_HID_DataIn (void *pdev, + uint8_t epnum) +{ + /*DataIN can be for MSC or HID */ + if (epnum == (MSC_IN_EP&~0x80) ) + { + return (USBD_MSC_DataIn(pdev, epnum)); + } + else + { + return (USBD_CUSTOM_HID_DataIn(pdev, epnum)); + } +} + +/** + * @brief USBD_MSC_HID_DataOut + * handle data OUT Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_MSC_HID_DataOut(void *pdev , uint8_t epnum) +{ + /*DataOut can be for MSC*/ + if (epnum == (MSC_OUT_EP&~0x80) ) + { + return (USBD_MSC_DataOut(pdev, epnum)); + } + else + { + return (USBD_CUSTOM_HID_DataOut(pdev, epnum)); + } +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/inc/usbd_mouse_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/inc/usbd_mouse_core.h new file mode 100644 index 0000000000..029eec4a16 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/inc/usbd_mouse_core.h @@ -0,0 +1,120 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_mouse_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_DEV_MOUSE_CLASS_H__ +#define __USB_DEV_MOUSE_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usbd_ioreq.h" + + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MOUSE_CFGDESC_SIZE (41U) +#define MOUSE_DESC_SIZE (9U) +#define MOUSE_REPORT_DESC_SIZE (74U) + +#define MOUSE_DESCRIPTOR_TYPE (0x21U) +#define MOUSE_REPORT_DESC (0x22U) + +#define MOUSE_REQ_SET_PROTOCOL (0x0BU) +#define MOUSE_REQ_GET_PROTOCOL (0x03U) + +#define MOUSE_REQ_SET_IDLE (0x0AU) +#define MOUSE_REQ_GET_IDLE (0x02U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern USBD_Class_cb_TypeDef USBD_MOUSE_cb; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_dev_mouse_txreport(USB_CORE_MODULE *pdev, uint8_t *report, uint16_t len); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MOUSE_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/src/usbd_mouse_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/src/usbd_mouse_core.c new file mode 100644 index 0000000000..1c08f43aa4 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/mouse/src/usbd_mouse_core.c @@ -0,0 +1,355 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_mouse_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + *//* Includes ------------------------------------------------------------------*/ +#include "usbd_mouse_core.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "n32h76x_78x_gpio.h" +#include "usbhs_bsp.h" + +static uint8_t usb_dev_mouse_init(void *pdev, uint8_t cfgidx); +static uint8_t usb_dev_mouse_deinit(void *pdev, uint8_t cfgidx); +static uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req); +static uint8_t *usb_dev_mouse_getcfgdesc(uint8_t speed, uint16_t *length); +static uint8_t usb_dev_mouse_datain(void *pdev, uint8_t epnum); +static uint8_t usb_dev_mouse_dataout(void *pdev, uint8_t epnum); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +USBD_Class_cb_TypeDef USBD_MOUSE_cb = { + usb_dev_mouse_init, + usb_dev_mouse_deinit, + usb_dev_mouse_setup, + NULL, + NULL, + usb_dev_mouse_datain, + usb_dev_mouse_dataout, + NULL, + NULL, + NULL, + usb_dev_mouse_getcfgdesc, + usb_dev_mouse_getcfgdesc, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_AltSet = 0UL; +__ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_Protocol = 0UL; +__ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_IdleState = 0UL; + +/* USB HID device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USB_DEV_MOUSE_CfgDesc[MOUSE_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE,/* bDescriptorType: Configuration */ + MOUSE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 41 */ +} ; + +__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, + 0x09, 0x02, + 0xA1, 0x01, + 0x09, 0x01, + + 0xA1, 0x00, + 0x05, 0x09, + 0x19, 0x01, + 0x29, 0x03, + + 0x15, 0x00, + 0x25, 0x01, + 0x95, 0x03, + 0x75, 0x01, + + 0x81, 0x02, + 0x95, 0x01, + 0x75, 0x05, + 0x81, 0x01, + + 0x05, 0x01, + 0x09, 0x30, + 0x09, 0x31, + 0x09, 0x38, + + 0x15, 0x81, + 0x25, 0x7F, + 0x75, 0x08, + 0x95, 0x03, + + 0x81, 0x06, + 0xC0, 0x09, + 0x3C, 0x05, + 0xFF, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xB1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xB1, + + 0x01, 0xC0 +}; + +static uint8_t u8HidRevBuf[4]; + +/** +*\*\name usb_dev_mouse_init. +*\*\fun Initialize the interface of MOUSE HID. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index. +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t usb_dev_mouse_init(void *pdev, uint8_t cfgidx) +{ + USBDEV_EP_Open(pdev, HID_IN_EP, HID_IN_PACKET, USB_EP_INT); + USBDEV_EP_Open(pdev, HID_OUT_EP, HID_OUT_PACKET, USB_EP_INT); + USBDEV_EP_PrepareRx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t))); + USBDEV_SetEPStatus(pdev, HID_OUT_EP, USB_EP_RX_VALID); + return USBD_OK; +} + +/** +*\*\name usb_dev_mouse_deinit. +*\*\fun DeInitialize the interface of MOUSE HID. +*\*\param pdev�� device instance. +*\*\param cfgidx: cfg instance. +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t usb_dev_mouse_deinit(void *pdev, uint8_t cfgidx) +{ + USBDEV_EP_Close(pdev, HID_IN_EP); + USBDEV_EP_Close(pdev, HID_OUT_EP); + return USBD_OK; +} + +/** +*\*\name usb_dev_mouse_setup. +*\*\fun Handle the MOUSE HID SETUP request. +*\*\param pdev: device instance. +*\*\param req: usb requests. +*\*\return status. +*\*\ +**/ +static uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Res = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case MOUSE_REQ_SET_PROTOCOL: + USB_DEV_MOUSE_Protocol = (uint8_t)(req->wValue); + break; + case MOUSE_REQ_GET_PROTOCOL: + USBD_CtrlSendData(pdev, (uint8_t *)&USB_DEV_MOUSE_Protocol, 1U); + break; + case MOUSE_REQ_SET_IDLE: + USB_DEV_MOUSE_IdleState = (uint8_t)(req->wValue >> 8U); + break; + case MOUSE_REQ_GET_IDLE: + USBD_CtrlSendData(pdev, (uint8_t *)&USB_DEV_MOUSE_IdleState, 1U); + break; + default: + USBD_CtrlError(pdev, req); + u8Res = USBD_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8U) == (uint16_t)MOUSE_REPORT_DESC) { + len = (uint16_t)MIN(MOUSE_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_MOUSE_ReportDesc; + } else if ((req->wValue >> 8U) == (uint16_t)MOUSE_DESCRIPTOR_TYPE) { + pbuf = USB_DEV_MOUSE_CfgDesc + 0x12; + len = (uint16_t)MIN(MOUSE_DESC_SIZE, req->wLength); + } else { + ; + } + USBD_CtrlSendData(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData(pdev, (uint8_t *)&USB_DEV_MOUSE_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_MOUSE_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** +*\*\name usb_dev_mouse_txreport. +*\*\fun Send MOUSE HID report to the host. +*\*\param pdev: device instance. +*\*\param report: pointer to the report buffer +*\*\param length: the length of the report buffer in bytes +*\*\return USBD_OK. +*\*\ +**/ +uint8_t usb_dev_mouse_txreport(USB_CORE_MODULE *pdev, uint8_t *report, uint16_t length) +{ + if (pdev->dev.device_status == USB_CONFIGURED) + { + USBDEV_EP_Tx(pdev, HID_IN_EP, report, (uint32_t)length); + } + return USBD_OK; +} + +/** +*\*\name usb_dev_mouse_getcfgdesc. +*\*\fun get the configuration descriptor. +*\*\param speed: device speed. +*\*\param length:pointer data length of the configuration descriptor in bytes +*\*\return pointer of configuration descriptor buffer. +*\*\ +**/ +static uint8_t *usb_dev_mouse_getcfgdesc(uint8_t speed, uint16_t *length) +{ + *length = (uint16_t)sizeof(USB_DEV_MOUSE_CfgDesc); + return USB_DEV_MOUSE_CfgDesc; +} + +/** +*\*\name usb_dev_mouse_datain. +*\*\fun handle the IN data Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t usb_dev_mouse_datain(void *pdev, uint8_t epnum) +{ + USBDEV_EP_Flush(pdev, HID_IN_EP); + return USBD_OK; +} + +/** +*\*\name usb_dev_mouse_dataout. +*\*\fun handle the OUT data Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index +*\*\return USBD_OK. +*\*\ +**/ +static uint8_t usb_dev_mouse_dataout(void *pdev, uint8_t epnum) +{ + USBDEV_EP_PrepareRx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t))); + USBDEV_SetEPStatus(pdev, HID_OUT_EP, USB_EP_RX_VALID); + return USBD_OK; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_bot.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_bot.h new file mode 100644 index 0000000000..2c054cc76f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_bot.h @@ -0,0 +1,127 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_bot.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_core.h" + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_MSC_BOT_H +#define __USBD_MSC_BOT_H + +#define BOT_IDLE 0 /* Idle state */ +#define BOT_DATA_OUT 1 /* Data Out state */ +#define BOT_DATA_IN 2 /* Data In state */ +#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ +#define BOT_SEND_DATA 4 /* Send Immediate data */ + +#define BOT_CBW_SIGNATURE 0x43425355 +#define BOT_CSW_SIGNATURE 0x53425355 +#define BOT_CBW_LENGTH 31 +#define BOT_CSW_LENGTH 13 + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED 0x00 +#define CSW_CMD_FAILED 0x01 +#define CSW_PHASE_ERROR 0x02 + +/* BOT Status */ +#define BOT_STATE_NORMAL 0 +#define BOT_STATE_RECOVERY 1 +#define BOT_STATE_ERROR 2 + + +#define DIR_IN 0 +#define DIR_OUT 1 +#define BOTH_DIR 2 + +typedef struct _MSC_BOT_CBW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} +MSC_BOT_CBW_TypeDef; + + +typedef struct _MSC_BOT_CSW +{ + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} +MSC_BOT_CSW_TypeDef; + +extern uint8_t MSC_BOT_Data[]; +extern uint16_t MSC_BOT_DataLen; +extern uint8_t MSC_BOT_State; +extern uint8_t MSC_BOT_BurstMode; +extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; +extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; + +void MSC_BOT_Init (USB_CORE_MODULE *pdev); +void MSC_BOT_Reset (USB_CORE_MODULE *pdev); +void MSC_BOT_DeInit (USB_CORE_MODULE *pdev); +void MSC_BOT_DataIn (USB_CORE_MODULE *pdev, uint8_t epnum); + +void MSC_BOT_DataOut (USB_CORE_MODULE *pdev, uint8_t epnum); + +void MSC_BOT_SendCSW (USB_CORE_MODULE *pdev,uint8_t CSW_Status); + +void MSC_BOT_CplClrFeature (USB_CORE_MODULE *pdev, uint8_t epnum); + +#endif /* __USBD_MSC_BOT_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_core.h new file mode 100644 index 0000000000..dd0afbf7da --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_core.h @@ -0,0 +1,70 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef _USB_MSC_CORE_H_ +#define _USB_MSC_CORE_H_ + +#include "usbd_ioreq.h" + +#define BOT_GET_MAX_LUN 0xFE +#define BOT_RESET 0xFF +#define USB_MSC_CONFIG_DESC_SIZ 32 + +#define MSC_EPIN_SIZE MSC_MAX_PACKET +#define MSC_EPOUT_SIZE MSC_MAX_PACKET + + +extern USBD_Class_cb_TypeDef USBD_MSC_cb; + +#endif /* _USB_MSC_CORE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_data.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_data.h new file mode 100644 index 0000000000..f5a0dc618a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_data.h @@ -0,0 +1,73 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_data.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ + +#ifndef _USBD_MSC_DATA_H_ +#define _USBD_MSC_DATA_H_ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_conf.h" +#include "n32h76x_78x.h" + +#define MODE_SENSE6_LEN 8 +#define MODE_SENSE10_LEN 8 +#define LENGTH_INQUIRY_PAGE00 7 +#define LENGTH_FORMAT_CAPACITIES 20 + +extern const uint8_t MSC_Page00_Inquiry_Data[]; +extern const uint8_t MSC_Mode_Sense6_data[]; +extern const uint8_t MSC_Mode_Sense10_data[] ; + + +#endif /* _USBD_MSC_DATA_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_scsi.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_scsi.h new file mode 100644 index 0000000000..e36d5d0480 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/inc/usbd_msc_scsi.h @@ -0,0 +1,157 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_scsi.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBD_MSC_SCSI_H +#define __USBD_MSC_SCSI_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" + +#define SENSE_LIST_DEEPTH 4 + +/* SCSI Commands */ +#define SCSI_FORMAT_UNIT 0x04 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SELECT6 0x15 +#define SCSI_MODE_SELECT10 0x55 +#define SCSI_MODE_SENSE6 0x1A +#define SCSI_MODE_SENSE10 0x5A +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_READ6 0x08 +#define SCSI_READ10 0x28 +#define SCSI_READ12 0xA8 +#define SCSI_READ16 0x88 + +#define SCSI_READ_CAPACITY10 0x25 +#define SCSI_READ_CAPACITY16 0x9E + +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_START_STOP_UNIT 0x1B +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_WRITE6 0x0A +#define SCSI_WRITE10 0x2A +#define SCSI_WRITE12 0xAA +#define SCSI_WRITE16 0x8A + +#define SCSI_VERIFY10 0x2F +#define SCSI_VERIFY12 0xAF +#define SCSI_VERIFY16 0x8F + +#define SCSI_SEND_DIAGNOSTIC 0x1D +#define SCSI_READ_FORMAT_CAPACITIES 0x23 + +#define NO_SENSE 0 +#define RECOVERED_ERROR 1 +#define NOT_READY 2 +#define MEDIUM_ERROR 3 +#define HARDWARE_ERROR 4 +#define ILLEGAL_REQUEST 5 +#define UNIT_ATTENTION 6 +#define DATA_PROTECT 7 +#define BLANK_CHECK 8 +#define VENDOR_SPECIFIC 9 +#define COPY_ABORTED 10 +#define ABORTED_COMMAND 11 +#define VOLUME_OVERFLOW 13 +#define MISCOMPARE 14 + + +#define INVALID_CDB 0x20 +#define INVALID_FIELED_IN_COMMAND 0x24 +#define PARAMETER_LIST_LENGTH_ERROR 0x1A +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 +#define ADDRESS_OUT_OF_RANGE 0x21 +#define MEDIUM_NOT_PRESENT 0x3A +#define MEDIUM_HAVE_CHANGED 0x28 +#define WRITE_PROTECTED 0x27 +#define UNRECOVERED_READ_ERROR 0x11 +#define WRITE_FAULT 0x03 + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C +#define READ_CAPACITY10_DATA_LEN 0x08 +#define MODE_SENSE10_DATA_LEN 0x08 +#define MODE_SENSE6_DATA_LEN 0x04 +#define REQUEST_SENSE_DATA_LEN 0x12 +#define STANDARD_INQUIRY_DATA_LEN 0x24 +#define BLKVFY 0x04 + +extern uint8_t Page00_Inquiry_Data[]; +extern uint8_t Standard_Inquiry_Data[]; +extern uint8_t Standard_Inquiry_Data2[]; +extern uint8_t Mode_Sense6_data[]; +extern uint8_t Mode_Sense10_data[]; +extern uint8_t Scsi_Sense_Data[]; +extern uint8_t ReadCapacity10_Data[]; +extern uint8_t ReadFormatCapacity_Data []; + +typedef struct _SENSE_ITEM { + char Skey; + union { + struct _ASCs { + char ASC; + char ASCQ; + }b; + unsigned int ASC; + char *pData; + } w; +} SCSI_Sense_TypeDef; + +extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +extern uint8_t SCSI_Sense_Head; +extern uint8_t SCSI_Sense_Tail; + +int8_t SCSI_ProcessCmd(USB_CORE_MODULE *pdev, uint8_t lun, uint8_t *cmd); + +void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC); + +#endif /* __USBD_MSC_SCSI_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_bot.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_bot.c new file mode 100644 index 0000000000..2647cf6acb --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_bot.c @@ -0,0 +1,311 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_bot.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_ioreq.h" +#include "usbd_msc_mem.h" + +uint16_t MSC_BOT_DataLen; +uint8_t MSC_BOT_State; +uint8_t MSC_BOT_Status; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; + +static void MSC_BOT_CBW_Decode (USB_CORE_MODULE *pdev); + +static void MSC_BOT_SendData (USB_CORE_MODULE *pdev, uint8_t* pbuf, uint16_t len); + +static void MSC_BOT_Abort(USB_CORE_MODULE *pdev); + +/** +*\*\name MSC_BOT_Init. +*\*\fun Initialize the BOT Process. +*\*\param pdev : USB device +*\*\return none +**/ +void MSC_BOT_Init (USB_CORE_MODULE *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_NORMAL; + USBD_STORAGE_fops->Init(0); + + USBDEV_EP_Flush(pdev, MSC_OUT_EP); + USBDEV_EP_Flush(pdev, MSC_IN_EP); + /* Prapare EP to Receive First BOT Cmd */ + USBDEV_EP_PrepareRx (pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** +*\*\name MSC_BOT_Reset. +*\*\fun Reset the BOT Machine. +*\*\param pdev : USB device +*\*\return none +**/ +void MSC_BOT_Reset (USB_CORE_MODULE *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_RECOVERY; + /* Prapare EP to Receive First BOT Cmd */ + USBDEV_EP_PrepareRx (pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** +*\*\name MSC_BOT_DeInit. +*\*\fun Uninitialize the BOT Machine. +*\*\param pdev : USB device +*\*\return none +**/ +void MSC_BOT_DeInit (USB_CORE_MODULE *pdev) +{ + MSC_BOT_State = BOT_IDLE; +} + +/** +*\*\name MSC_BOT_DataIn. +*\*\fun Handle BOT IN data stage. +*\*\param pdev : USB device +*\*\param epnum: endpoint index +*\*\return none +**/ +void MSC_BOT_DataIn (USB_CORE_MODULE *pdev, uint8_t epnum) +{ + switch (MSC_BOT_State) + { + case BOT_DATA_IN: + if(SCSI_ProcessCmd(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + break; + + case BOT_SEND_DATA: + case BOT_LAST_DATA_IN: + MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); + break; + + default: + break; + } +} + +/** +*\*\name MSC_BOT_DataOut. +*\*\fun Handle BOT OUT data stage. +*\*\param pdev : USB device +*\*\param epnum: endpoint index +*\*\return none +**/ +void MSC_BOT_DataOut (USB_CORE_MODULE *pdev, uint8_t epnum) +{ + switch (MSC_BOT_State) + { + case BOT_IDLE: + MSC_BOT_CBW_Decode(pdev); + break; + + case BOT_DATA_OUT: + if(SCSI_ProcessCmd(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } + break; + + default: + break; + } +} + +/** +*\*\name MSC_BOT_CBW_Decode. +*\*\fun Decode the CBW command and set the BOT state machine accordingtly. +*\*\param pdev : USB device +*\*\return none +**/ +static void MSC_BOT_CBW_Decode (USB_CORE_MODULE *pdev) +{ + + MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; + MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; + + if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || + (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| + (MSC_BOT_cbw.bLUN > 1) || + (MSC_BOT_cbw.bCBLength < 1) || + (MSC_BOT_cbw.bCBLength > 16)) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, + ILLEGAL_REQUEST, + INVALID_CDB); + MSC_BOT_Status = BOT_STATE_ERROR; + MSC_BOT_Abort(pdev); + } + else + { + if(SCSI_ProcessCmd(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) + { + MSC_BOT_Abort(pdev); + } + /*Burst xfer handled internally*/ + else if ((MSC_BOT_State != BOT_DATA_IN) && (MSC_BOT_State != BOT_DATA_OUT) && (MSC_BOT_State != BOT_LAST_DATA_IN)) + { + if (MSC_BOT_DataLen > 0) + { + MSC_BOT_SendData(pdev, MSC_BOT_Data, MSC_BOT_DataLen); + } + else if (MSC_BOT_DataLen == 0) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); + } + } + } +} + + +/** +*\*\name MSC_BOT_SendData. +*\*\fun Send the requested data. +*\*\param pdev : USB device +*\*\param buf: pointer to data buffer +*\*\param len: Data Length +*\*\return none +**/ +static void MSC_BOT_SendData(USB_CORE_MODULE *pdev, uint8_t* buf, uint16_t len) +{ + len = MIN (MSC_BOT_cbw.dDataLength, len); + MSC_BOT_csw.dDataResidue -= len; + MSC_BOT_csw.bStatus = CSW_CMD_PASSED; + MSC_BOT_State = BOT_SEND_DATA; + + USBDEV_EP_Tx(pdev, MSC_IN_EP, buf, len); +} + +/** +*\*\name MSC_BOT_SendCSW. +*\*\fun Send the Command Status Wrapper. +*\*\param pdev : USB device +*\*\param CSW_Status : CSW status +*\*\return none +**/ +void MSC_BOT_SendCSW (USB_CORE_MODULE *pdev, uint8_t CSW_Status) +{ + MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; + MSC_BOT_csw.bStatus = CSW_Status; + MSC_BOT_State = BOT_IDLE; + + USBDEV_EP_Tx (pdev, MSC_IN_EP, (uint8_t *)&MSC_BOT_csw, BOT_CSW_LENGTH); + + /* Prepare EP to Receive next Cmd */ + USBDEV_EP_PrepareRx (pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); + +} + +/** +*\*\name MSC_BOT_Abort. +*\*\fun Abort the current transfer. +*\*\param pdev : USB device +*\*\return none +**/ +static void MSC_BOT_Abort (USB_CORE_MODULE *pdev) +{ + if ((MSC_BOT_cbw.bmFlags == 0) && (MSC_BOT_cbw.dDataLength != 0) && (MSC_BOT_Status == BOT_STATE_NORMAL)) + { + USBDEV_EP_Stall(pdev, MSC_OUT_EP); + } + USBDEV_EP_Stall(pdev, MSC_IN_EP); + + if(MSC_BOT_Status == BOT_STATE_ERROR) + { + USBDEV_EP_PrepareRx (pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); + } +} + +/** +*\*\name MSC_BOT_CplClrFeature. +*\*\fun Complete the clear feature request. +*\*\param pdev : USB device +*\*\param epnum: endpoint index +*\*\return none +**/ +void MSC_BOT_CplClrFeature (USB_CORE_MODULE *pdev, uint8_t epnum) +{ + if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ + { + USBDEV_EP_Stall(pdev, MSC_IN_EP); + MSC_BOT_Status = BOT_STATE_NORMAL; + } + else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) + { + MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); + } +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_core.c new file mode 100644 index 0000000000..ceafd8228c --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_core.c @@ -0,0 +1,389 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_msc_mem.h" +#include "usbd_msc_core.h" +#include "usbd_msc_bot.h" +#include "usbd_req.h" + + +uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx); + +uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx); + +uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req); + +uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum); + +uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum); + +uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length); + +uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, uint16_t *length); + + +uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; + + +USBD_Class_cb_TypeDef USBD_MSC_cb = +{ + USBD_MSC_Init, + USBD_MSC_DeInit, + USBD_MSC_Setup, + NULL, /*EP0_TxSent*/ + NULL, /*EP0_RxReady*/ + USBD_MSC_DataIn, + USBD_MSC_DataOut, + NULL, /*SOF */ + NULL, + NULL, + USBD_MSC_GetCfgDesc, + USBD_MSC_GetOtherCfgDesc, +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB Mass storage device Configuration Descriptor */ +/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ +__ALIGN_BEGIN uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_MSC_CONFIG_DESC_SIZ, + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /*Polling interval in milliseconds*/ +}; + + #ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif + #endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_MSC_CONFIG_DESC_SIZ, + + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + 0x40, + 0x00, + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + 0x40, + 0x00, + 0x00 /*Polling interval in milliseconds*/ +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; + + +/** +*\*\name USBD_MSC_Init. +*\*\fun Initialize the mass storage configuration. +*\*\param pdev : USB device +*\*\param cfgidx: configuration index +*\*\return status +**/ +uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx) +{ + USBD_MSC_DeInit(pdev , cfgidx ); + + /* Open EP IN */ + USBDEV_EP_Open(pdev, MSC_IN_EP, MSC_EPIN_SIZE, USB_EP_BULK); + + /* Open EP OUT */ + USBDEV_EP_Open(pdev, MSC_OUT_EP, MSC_EPOUT_SIZE, USB_EP_BULK); + + /* Init the BOT layer */ + MSC_BOT_Init(pdev); + + return USBD_OK; +} + +/** +*\*\name USBD_MSC_DeInit. +*\*\fun DeInitilaize the mass storage configuration. +*\*\param pdev : USB device +*\*\param cfgidx: configuration index +*\*\return status +**/ +uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx) +{ + /* Close MSC EPs */ + USBDEV_EP_Close (pdev , MSC_IN_EP); + USBDEV_EP_Close (pdev , MSC_OUT_EP); + + /* Un Init the BOT layer */ + MSC_BOT_DeInit(pdev); + return USBD_OK; +} + +/** +*\*\name USBD_MSC_Setup. +*\*\fun Handle the MSC specific requests. +*\*\param pdev : USB device +*\*\param req: USB request +*\*\return status +**/ +uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + + /* Class request */ + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case BOT_GET_MAX_LUN : + if((req->wValue == 0) && (req->wLength == 1) && ((req->bmRequest & 0x80) == 0x80)) + { + USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); + if(USBD_MSC_MaxLun > 0) + { + USBD_CtrlSendData (pdev, &USBD_MSC_MaxLun, 1); + } + else + { + USBD_CtrlError(pdev , req); + return USBD_FAIL; + } + } + else + { + USBD_CtrlError(pdev , req); + return USBD_FAIL; + } + break; + + case BOT_RESET : + if((req->wValue == 0) && (req->wLength == 0) && ((req->bmRequest & 0x80) != 0x80)) + { + MSC_BOT_Reset(pdev); + } + else + { + USBD_CtrlError(pdev , req); + return USBD_FAIL; + } + break; + + default: + USBD_CtrlError(pdev , req); + return USBD_FAIL; + } + break; + + /* Interface & Endpoint request */ + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_INTERFACE : + USBD_CtrlSendData (pdev, &USBD_MSC_AltSet, 1); + break; + + case USB_REQ_SET_INTERFACE : + USBD_MSC_AltSet = (uint8_t)(req->wValue); + break; + + case USB_REQ_CLEAR_FEATURE: + + /* Flush the FIFO and Clear the stall status */ + USBDEV_EP_Flush(pdev, (uint8_t)req->wIndex); + + /* Re-activate the EP */ + USBDEV_EP_Close (pdev , (uint8_t)req->wIndex); + if((((uint8_t)req->wIndex) & 0x80) == 0x80) + { + USBDEV_EP_Open(pdev, ((uint8_t)req->wIndex), MSC_EPIN_SIZE, USB_EP_BULK); + } + else + { + USBDEV_EP_Open(pdev, ((uint8_t)req->wIndex), MSC_EPOUT_SIZE, USB_EP_BULK); + } + /* Handle BOT error */ + MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); + break; + + } + break; + + default: + break; + } + return USBD_OK; +} + +/** +*\*\name USBD_MSC_DataIn. +*\*\fun Handle data IN Stage. +*\*\param pdev : USB device +*\*\param epnum: endpoint index +*\*\return status +**/ +uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum) +{ + MSC_BOT_DataIn(pdev , epnum); + return USBD_OK; +} + +/** +*\*\name USBD_MSC_DataOut. +*\*\fun Handle data OUT Stage. +*\*\param pdev : USB device +*\*\param epnum: endpoint index +*\*\return status +**/ +uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum) +{ + MSC_BOT_DataOut(pdev , epnum); + return USBD_OK; +} + +/** +*\*\name USBD_MSC_GetCfgDesc. +*\*\fun return configuration descriptor. +*\*\param speed: current device speed +*\*\param length: pointer data length +*\*\return pointer to descriptor buffer +**/ +uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_MSC_CfgDesc); + return USBD_MSC_CfgDesc; +} + +/** +*\*\name USBD_MSC_GetOtherCfgDesc. +*\*\fun return configuration descriptor. +*\*\param speed: current device speed +*\*\param length: pointer data length +*\*\return pointer to descriptor buffer +**/ +uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_MSC_OtherCfgDesc); + return USBD_MSC_OtherCfgDesc; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_data.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_data.c new file mode 100644 index 0000000000..c4e43a5390 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_data.c @@ -0,0 +1,90 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_data.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_msc_data.h" + +/* USB Mass storage Page 0 Inquiry Data */ +const uint8_t MSC_Page00_Inquiry_Data[] = +{//7 + 0x00, + 0x00, + 0x00, + (LENGTH_INQUIRY_PAGE00 - 4), + 0x00, + 0x80, + 0x83 +}; +/* USB Mass storage sense 6 Data */ +const uint8_t MSC_Mode_Sense6_data[] = +{ + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/* USB Mass storage sense 10 Data */ +const uint8_t MSC_Mode_Sense10_data[] = +{ + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_scsi.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_scsi.c new file mode 100644 index 0000000000..5f02612e71 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc/src/usbd_msc_scsi.c @@ -0,0 +1,616 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_scsi.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_msc_bot.h" +#include "usbd_msc_scsi.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_data.h" + +SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +uint8_t SCSI_Sense_Head; +uint8_t SCSI_Sense_Tail; + +uint32_t SCSI_blk_size; +uint32_t SCSI_blk_nbr; + +uint32_t SCSI_blk_addr; +uint32_t SCSI_blk_len; + +USB_CORE_MODULE *cdev; + +static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); +static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); +static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); +static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); +static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); +static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); +static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); +static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); +static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); +static int8_t SCSI_CheckAddressRange (uint8_t lun , + uint32_t blk_offset , + uint16_t blk_nbr); +static int8_t SCSI_ProcessRead (uint8_t lun); + +static int8_t SCSI_ProcessWrite (uint8_t lun); + +/** +*\*\name SCSI_ProcessCmd. +*\*\fun Process SCSI commands. +*\*\param pdev: USB device +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +int8_t SCSI_ProcessCmd(USB_CORE_MODULE *pdev, uint8_t lun, uint8_t *params) +{ + cdev = pdev; + + switch (params[0]) + { + case SCSI_TEST_UNIT_READY: + return SCSI_TestUnitReady(lun, params); + + case SCSI_REQUEST_SENSE: + return SCSI_RequestSense (lun, params); + case SCSI_INQUIRY: + return SCSI_Inquiry(lun, params); + + case SCSI_START_STOP_UNIT: + return SCSI_StartStopUnit(lun, params); + + case SCSI_ALLOW_MEDIUM_REMOVAL: + return SCSI_StartStopUnit(lun, params); + + case SCSI_MODE_SENSE6: + return SCSI_ModeSense6 (lun, params); + + case SCSI_MODE_SENSE10: + return SCSI_ModeSense10 (lun, params); + + case SCSI_READ_FORMAT_CAPACITIES: + return SCSI_ReadFormatCapacity(lun, params); + + case SCSI_READ_CAPACITY10: + return SCSI_ReadCapacity10(lun, params); + + case SCSI_READ10: + return SCSI_Read10(lun, params); + + case SCSI_WRITE10: + return SCSI_Write10(lun, params); + + case SCSI_VERIFY10: + return SCSI_Verify10(lun, params); + + default: + SCSI_SenseCode(lun, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } +} + +/** +*\*\name SCSI_TestUnitReady. +*\*\fun Process SCSI Test Unit Ready Command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) +{ + /* case 9 : Hi > D0 */ + if (MSC_BOT_cbw.dDataLength != 0) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + MSC_BOT_DataLen = 0; + return 0; +} + +/** +*\*\name SCSI_Inquiry. +*\*\fun Process Inquiry command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) +{ + uint8_t* pPage; + uint16_t len; + + if (params[1] & 0x01)/*Evpd is set*/ + { + pPage = (uint8_t *)MSC_Page00_Inquiry_Data; + len = LENGTH_INQUIRY_PAGE00; + } + else + { + pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; + len = pPage[4] + 5; + if (params[4] <= len) + { + len = params[4]; + } + } + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = pPage[len]; + } + return 0; +} + +/** +*\*\name SCSI_ReadCapacity10. +*\*\fun Process Read Capacity 10 command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) +{ + if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + else + { + MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); + MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); + MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); + MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); + + MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); + MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); + MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); + MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); + + MSC_BOT_DataLen = 8; + return 0; + } +} + +/** +*\*\name SCSI_ReadFormatCapacity. +*\*\fun Process Read Format Capacity command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) +{ + uint32_t blk_size; + uint32_t blk_nbr; + uint16_t i; + + for(i=0 ; i < 12 ; i++) + { + MSC_BOT_Data[i] = 0; + } + + if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + else + { + MSC_BOT_Data[3] = 0x08; + MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); + MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); + MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); + MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); + + MSC_BOT_Data[8] = 0x02; + MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); + MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); + MSC_BOT_Data[11] = (uint8_t)(blk_size); + + MSC_BOT_DataLen = 12; + return 0; + } +} + +/** +*\*\name SCSI_ModeSense6. +*\*\fun Process Mode Sense6 command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) +{ + uint16_t len = 8 ; + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; + } + return 0; +} + +/** +*\*\name SCSI_ModeSense10. +*\*\fun Process Mode Sense10 command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) +{ + uint16_t len = 8; + + MSC_BOT_DataLen = len; + + while (len) + { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; + } + return 0; +} + +/** +*\*\name SCSI_RequestSense. +*\*\fun Process Request Sense command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) +{ + uint8_t i; + + for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) + { + MSC_BOT_Data[i] = 0; + } + + MSC_BOT_Data[0] = 0x70; + MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; + + if((SCSI_Sense_Head != SCSI_Sense_Tail)) + { + + MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; + MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; + MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; + SCSI_Sense_Head++; + + if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) + { + SCSI_Sense_Head = 0; + } + } + MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; + + if (params[4] <= REQUEST_SENSE_DATA_LEN) + { + MSC_BOT_DataLen = params[4]; + } + return 0; +} + +/** +*\*\name SCSI_SenseCode. +*\*\fun Load the last error code in the error list. +*\*\param lun: Logical unit number +*\*\param sKey: Sense Key +*\*\param ASC: Additional Sense Key +*\*\return none +**/ +void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) +{ + SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; + SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; + SCSI_Sense_Tail++; + if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) + { + SCSI_Sense_Tail = 0; + } +} + +/** +*\*\name SCSI_StartStopUnit. +*\*\fun Process Start Stop Unit command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) +{ + MSC_BOT_DataLen = 0; + return 0; +} + +/** +*\*\name SCSI_Read10. +*\*\fun Process Read10 command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) +{ + if(MSC_BOT_State == BOT_IDLE) /* Idle */ + { + + /* case 10 : Ho <> Di */ + + if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + SCSI_blk_addr = (params[2] << 24) | (params[3] << 16) | (params[4] << 8) | params[5]; + SCSI_blk_len = (params[7] << 8) | params[8]; + + if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + + MSC_BOT_State = BOT_DATA_IN; + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + + /* cases 4,5 : Hi <> Dn */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + } + MSC_BOT_DataLen = MSC_MEDIA_PACKET; + + return SCSI_ProcessRead(lun); +} + +/** +*\*\name SCSI_Write10. +*\*\fun Process Write10 command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) +{ + if (MSC_BOT_State == BOT_IDLE) /* Idle */ + { + /* case 8 : Hi <> Do */ + + if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + /* Check whether Media is ready */ + if(USBD_STORAGE_fops->IsReady(lun) !=0 ) + { + SCSI_SenseCode(lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + /* Check If media is write-protected */ + if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) + { + SCSI_SenseCode(lun, NOT_READY, WRITE_PROTECTED); + return -1; + } + + + SCSI_blk_addr = (params[2] << 24) | (params[3] << 16) | (params[4] << 8) | params[5]; + SCSI_blk_len = (params[7] << 8) | params[8]; + + /* check if LBA address is in the right range */ + if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) + { + SCSI_SenseCode(MSC_BOT_cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + /* Prepare EP to receive first data packet */ + MSC_BOT_State = BOT_DATA_OUT; + USBDEV_EP_PrepareRx (cdev, MSC_OUT_EP, MSC_BOT_Data, MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); + } + else /* Write Process ongoing */ + { + return SCSI_ProcessWrite(lun); + } + return 0; +} + +/** +*\*\name SCSI_Verify10. +*\*\fun Process Verify10 command. +*\*\param lun: Logical unit number +*\*\param params: Command parameters +*\*\return status +**/ +static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params) +{ + if ((params[1]& 0x02) == 0x02) + { + SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + return -1; /* Error, Verify Mode Not supported*/ + } + + SCSI_blk_addr = (params[2] << 24) | (params[3] << 16) | (params[4] << 8) | params[5]; + SCSI_blk_len = (params[7] << 8) | params[8]; + + if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) + { + return -1; /* error */ + } + MSC_BOT_DataLen = 0; + return 0; +} + +/** +*\*\name SCSI_CheckAddressRange. +*\*\fun Check address range. +*\*\param lun: Logical unit number +*\*\param blk_offset: first block address +*\*\param blk_nbr: number of block to be processed +*\*\return status +**/ +static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) +{ + if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) + { + SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + return -1; + } + return 0; +} + +/** +*\*\name SCSI_ProcessRead. +*\*\fun Handle Read Process. +*\*\param lun: Logical unit number +*\*\return status +**/ +static int8_t SCSI_ProcessRead (uint8_t lun) +{ + uint32_t len; + + len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); + + if( USBD_STORAGE_fops->Read(lun , MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) + { + SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + return -1; + } + + USBDEV_EP_Tx (cdev, MSC_IN_EP, MSC_BOT_Data, len); + + SCSI_blk_addr += len; + SCSI_blk_len -= len; + + /* case 6 : Hi = Di */ + MSC_BOT_csw.dDataResidue -= len; + + if (SCSI_blk_len == 0) + { + MSC_BOT_State = BOT_LAST_DATA_IN; + } + return 0; +} + +/** +*\*\name SCSI_ProcessWrite. +*\*\fun Handle Write Process. +*\*\param lun: Logical unit number +*\*\return status +**/ +static int8_t SCSI_ProcessWrite (uint8_t lun) +{ + uint32_t len; + + len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); + + if(USBD_STORAGE_fops->Write(lun , MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) + { + SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); + return -1; + } + + + SCSI_blk_addr += len; + SCSI_blk_len -= len; + + /* case 12 : Ho = Do */ + MSC_BOT_csw.dDataResidue -= len; + + if (SCSI_blk_len == 0) + { + MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); + } + else + { + /* Prapare EP to Receive next packet */ + USBDEV_EP_PrepareRx (cdev, MSC_OUT_EP, MSC_BOT_Data, MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); + } + + return 0; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/inc/usbd_msc_cdc_composite.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/inc/usbd_msc_cdc_composite.h new file mode 100644 index 0000000000..99248ad7cd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/inc/usbd_msc_cdc_composite.h @@ -0,0 +1,63 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_cdc_composite.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_MSC_CDC_COMPOSITE_H_ +#define __USB_MSC_CDC_COMPOSITE_H_ + +#include "usbd_ioreq.h" + + +extern USBD_Class_cb_TypeDef USBD_MSC_CDC_cb; + +#endif /* __USB_MSC_CDC_COMPOSITE_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/src/usbd_msc_cdc_composite.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/src/usbd_msc_cdc_composite.c new file mode 100644 index 0000000000..c5bab34261 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/msc_cdc_composite/src/usbd_msc_cdc_composite.c @@ -0,0 +1,385 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_msc_cdc_composite.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_msc_core.h" +#include "usbd_cdc_core.h" +#include "usbd_msc_cdc_composite.h" +#include "usbd_desc.h" +#include "usbd_req.h" + + +/* CDC Device library callbacks */ +extern uint8_t USBD_CDC_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CDC_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_CDC_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_CDC_EP0_RxReady (void *pdev); +extern uint8_t USBD_CDC_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_CDC_DataOut (void *pdev, uint8_t epnum); +extern uint8_t USBD_CDC_SOF (void *pdev); + +/* MSC Device library callbacks */ +extern uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx); +extern uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req); +extern uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum); +extern uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum); + + +static uint8_t USBD_MSC_CDC_Init (void *pdev , uint8_t cfgidx); +static uint8_t USBD_MSC_CDC_DeInit (void *pdev , uint8_t cfgidx); + +/* Control Endpoints*/ +static uint8_t USBD_MSC_CDC_Setup (void *pdev , USB_SETUP_REQ *req); +static uint8_t USBD_MSC_CDC_EP0_RxReady (void *pdev ); + +/* Class Specific Endpoints*/ +static uint8_t USBD_MSC_CDC_DataIn (void *pdev , uint8_t epnum); +static uint8_t USBD_MSC_CDC_DataOut (void *pdev , uint8_t epnum); +static uint8_t USBD_MSC_CDC_SOF (void *pdev); +static uint8_t* USBD_MSC_CDC_GetConfigDescriptor(uint8_t speed , uint16_t *length); + +#define USB_MSC_CDC_CONFIG_DESC_SIZ (USB_MSC_CONFIG_DESC_SIZ -9 + USB_CDC_CONFIG_DESC_SIZ + 8) + +#define MSC_INTERFACE 0x00 +#define CDC_COM_INTERFACE 0x01 + + +USBD_Class_cb_TypeDef USBD_MSC_CDC_cb = +{ + USBD_MSC_CDC_Init, + USBD_MSC_CDC_DeInit, + USBD_MSC_CDC_Setup, + NULL, + USBD_MSC_CDC_EP0_RxReady, + USBD_MSC_CDC_DataIn, + USBD_MSC_CDC_DataOut, + USBD_MSC_CDC_SOF, + NULL, + NULL, + USBD_MSC_CDC_GetConfigDescriptor, + USBD_MSC_CDC_GetConfigDescriptor, +}; + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB MSC/CDC device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_MSC_CDC_CfgDesc[USB_MSC_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_CDC_CONFIG_DESC_SIZ, + /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /*bNumInterfaces: 3 interfaces (2 for CDC, 1 for MSC)*/ + 0x01, /*bConfigurationValue: Configuration value*/ + 0x00, /*iConfiguration: Index of string descriptor describing + the configuration*/ + 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + + /************** Descriptor of MSC interface ****************/ + /* 09 */ + 0x09, /*bLength: Interface Descriptor size*/ + USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ + MSC_INTERFACE,/*bInterfaceNumber: Number of Interface*/ + 0x00, /*bAlternateSetting: Alternate setting*/ + 0x02, /*bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /*iInterface: Index of string descriptor*/ + /******************** Mass Storage Endpoints ********************/ + 0x07, /*Endpoint descriptor length = 7*/ + 0x05, /*Endpoint descriptor type */ + MSC_IN_EP, /*Endpoint address (IN, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds */ + + 0x07, /*Endpoint descriptor length = 7 */ + 0x05, /*Endpoint descriptor type */ + MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ + 0x02, /*Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /*Polling interval in milliseconds*/ + + /******** /IAD should be positioned just before the CDC interfaces ****** + IAD to associate the two CDC interfaces */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x01, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x01, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x02, /* bDataInterface: 2 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x01, /* bMasterInterface: Communication class interface */ + 0x02, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval */ +} ; + +/** + * @brief USBD_MSC_CDC_Init + * Initialize the MSC & CDC interfaces + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_MSC_CDC_Init (void *pdev, uint8_t cfgidx) +{ + /* MSC initialization */ + USBD_MSC_Init(pdev, cfgidx); + + /* CDC initialization */ + USBD_CDC_Init(pdev, cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_Init + * DeInitialize the MSC/CDC interfaces + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_MSC_CDC_DeInit(void *pdev, uint8_t cfgidx) +{ + /* MSC De-initialization */ + USBD_MSC_DeInit(pdev,cfgidx); + + /* CDC De-initialization */ + USBD_CDC_DeInit(pdev,cfgidx); + + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_Setup + * Handle the MSC/CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_MSC_CDC_Setup(void *pdev, USB_SETUP_REQ *req) +{ + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == MSC_INTERFACE) + { + return (USBD_MSC_Setup(pdev, req)); + } + else + { + return (USBD_CDC_Setup(pdev, req)); + } + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == MSC_IN_EP) + { + return (USBD_MSC_Setup(pdev, req)); + } + else + { + return (USBD_CDC_Setup(pdev, req)); + } + + default: + break; + } + return USBD_OK; +} + +/** + * @brief USBD_MSC_CDC_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_MSC_CDC_GetConfigDescriptor(uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_MSC_CDC_CfgDesc); + return USBD_MSC_CDC_CfgDesc; +} + +/** + * @brief USBD_MSC_CDC_DataIn + * handle data IN Stage + * @param pdev: device instance + * @param epnum: endpoint index + * @retval status + */ +static uint8_t USBD_MSC_CDC_DataIn (void *pdev, uint8_t epnum) +{ + /*DataIN can be for CDC or MSC */ + if (epnum == (CDC_IN_EP&0x0F)) + { + return (USBD_CDC_DataIn(pdev, epnum)); + } + else + { + return (USBD_MSC_DataIn(pdev, epnum)); + } +} + + +static uint8_t USBD_MSC_CDC_DataOut(void *pdev , uint8_t epnum) +{ + /*DataOut can be for CDC */ + if(epnum == (CDC_OUT_EP&0x0F)) + { + return (USBD_CDC_DataOut(pdev, epnum)); + } + else + { + return (USBD_MSC_DataOut(pdev, epnum)); + } +} + + +static uint8_t USBD_MSC_CDC_SOF (void *pdev) +{ + /*SOF processing needed for CDC */ + return (USBD_CDC_SOF(pdev)); +} + + +static uint8_t USBD_MSC_CDC_EP0_RxReady(void *pdev) +{ + /*RxReady processing needed for CDC only*/ + return (USBD_CDC_EP0_RxReady(pdev)); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/inc/usbd_printer.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/inc/usbd_printer.h new file mode 100644 index 0000000000..c006335dc6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/inc/usbd_printer.h @@ -0,0 +1,90 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_printer.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_PRINTER_H_ +#define __USB_PRINTER_H_ + +#include "usbd_ioreq.h" + +#define USB_PRNT_CONFIG_DESC_SIZ (32U) + + +#define USB_PRNT_BIDIRECTIONAL (0x02U) + + +#define PRINTER_DATA_IN_PACKET_SIZE PRINTER_DATA_MAX_PACKET_SIZE +#define PRINTER_DATA_OUT_PACKET_SIZE PRINTER_DATA_MAX_PACKET_SIZE + +#define PRINTER_STATUS_PAPER_EMPTY 0x10U +#define PRINTER_STATUS_SELECTED 0x08U +#define PRINTER_STATUS_NO_ERROR 0x00U + +/* printing device specific-class request */ +#define PRINTER_GET_DEVICE_ID 0x00U /*!< get device id request */ +#define PRINTER_GET_PORT_STATUS 0x01U /*!< get port status request */ +#define PRINTER_SOFT_RESET 0x02U /*!< soft reset request */ + + +typedef struct _USBD_PRNT_Itf +{ + int8_t (* Init)(void); + int8_t (* DeInit)(void); + int8_t (* Control_req)(uint8_t req, uint8_t *pbuf, uint16_t *length); + int8_t (* Receive)(uint8_t *Buf, uint16_t *Len); + +} USBD_PRNT_ItfTypeDef; + +extern USBD_Class_cb_TypeDef USBD_PRINTER_cb; + +#endif /* __USB_PRINTER_H_ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/src/usbd_printer.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/src/usbd_printer.c new file mode 100644 index 0000000000..c83a5ae6b0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/class/printer/src/usbd_printer.c @@ -0,0 +1,400 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_printer.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_printer.h" +#include "usbd_desc.h" +#include "usbd_req.h" +#include "usbhs_bsp.h" + +/* Printer Device library callbacks */ +static uint8_t USBD_PRNTER_Init(void *pdev, uint8_t cfgidx); +static uint8_t USBD_PRNTER_DeInit(void *pdev, uint8_t cfgidx); +static uint8_t USBD_PRNTER_Setup(void *pdev, USB_SETUP_REQ *req); +static uint8_t USBD_PRNTER_DataIn(void *pdev, uint8_t epnum); +static uint8_t USBD_PRNTER_DataOut(void *pdev, uint8_t epnum); + +/* Printer specific management functions */ +static uint8_t *USBD_PRNTER_GetCfgDesc(uint8_t speed, uint16_t *length); +static uint8_t *USBD_PRNTER_GetOtherCfgDesc(uint8_t speed, uint16_t *length); + +extern USBD_PRNT_ItfTypeDef APP_FOPS; +static uint8_t PRNTInEpAdd = PRINTER_IN_EP; +static uint8_t PRNTOutEpAdd = PRINTER_OUT_EP; + +/* Printer interface class callbacks structure */ +USBD_Class_cb_TypeDef USBD_PRINTER_cb = +{ + USBD_PRNTER_Init, + USBD_PRNTER_DeInit, + USBD_PRNTER_Setup, + NULL, + NULL, + USBD_PRNTER_DataIn, + USBD_PRNTER_DataOut, + NULL, + NULL, + NULL, + USBD_PRNTER_GetCfgDesc, + USBD_PRNTER_GetOtherCfgDesc, +}; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBD_PRNT_CfgDesc [USB_PRNT_CONFIG_DESC_SIZ] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN static __IO uint32_t USBD_PRINTER_AltSet __ALIGN_END = 0; + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USB_Rx_Buffer [PRINTER_DATA_MAX_PACKET_SIZE] __ALIGN_END ; + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t CmdBuff[PRINTER_CMD_PACKET_SIZE] __ALIGN_END ; + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +/* USB PRNT device Configuration Descriptor */ +__ALIGN_BEGIN uint8_t USBD_PRNT_CfgDesc[] __ALIGN_END = +{ + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_PRNT_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xA0, /* bmAttributes: Self Powered according to user configuration */ + 0x32, /* MaxPower 100 mA */ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: 2 endpoints used */ + 0x07, /* bInterfaceClass: Communication Interface Class */ + 0x01, /* bInterfaceSubClass: Abstract Control Model */ + USB_PRNT_BIDIRECTIONAL, /* bDeviceProtocol */ + 0x00, /* iInterface */ + + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + PRINTER_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(PRINTER_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize */ + HIBYTE(PRINTER_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval */ + + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + PRINTER_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(PRINTER_DATA_MAX_PACKET_SIZE),/* wMaxPacketSize */ + HIBYTE(PRINTER_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval */ +}; + + +/** +*\*\name USBD_PRNTER_Init. +*\*\fun Initialize the printer interface. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_PRNTER_Init (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Open(pdev, PRNTInEpAdd, PRINTER_DATA_IN_PACKET_SIZE, USB_EP_BULK); + + /* Open EP OUT */ + USBDEV_EP_Open(pdev, PRNTOutEpAdd, PRINTER_DATA_OUT_PACKET_SIZE, USB_EP_BULK); + + /* Initialize the Interface physical components */ + APP_FOPS.Init(); + + /* Prepare Out endpoint to receive next packet */ + USBDEV_EP_PrepareRx(pdev, PRNTOutEpAdd, (uint8_t*)(USB_Rx_Buffer), PRINTER_DATA_OUT_PACKET_SIZE); + + return USBD_OK; +} + + +/** +*\*\name USBD_PRNTER_DeInit. +*\*\fun DeInitialize the printer layer. +*\*\param pdev: device instance. +*\*\param cfgidx: Configuration index +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_PRNTER_DeInit (void *pdev, uint8_t cfgidx) +{ + /* Open EP IN */ + USBDEV_EP_Close(pdev, PRNTInEpAdd); + + /* Open EP OUT */ + USBDEV_EP_Close(pdev, PRNTOutEpAdd); + + /* Restore default state of the Interface physical components */ + APP_FOPS.DeInit(); + + return USBD_OK; +} + +/** +*\*\name USBD_PRNTER_Setup +*\*\fun Handle the printer specific requests. +*\*\param pdev: device instance. +*\*\param req: usb requests +*\*\return USBD_OK. +**/ +uint8_t USBD_PRNTER_Setup (void *pdev, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + uint16_t status_info = 0U; + uint16_t data_length; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + /* PRNTER Class Requests -------------------------------*/ + case USB_REQ_TYPE_CLASS : + { + /* Check if the request is a data setup packet */ + if (req->wLength != 0U) + { + data_length = MIN(req->wLength, PRINTER_DATA_MAX_PACKET_SIZE); + + if ((req->bmRequest & 0x80U) != 0U) + { + /* Call the User class interface function to process the command */ + APP_FOPS.Control_req(req->bRequest, CmdBuff, &data_length); + + /* Return the answer to host */ + USBD_CtrlSendData(pdev, (uint8_t *)CmdBuff, data_length); + } + else /* Host-to-Device request */ + { + /* Prepare for control data reception */ + USBD_CtrlPrepareRx(pdev, (uint8_t *)CmdBuff, data_length); + } + } + else /* No Data request */ + { + data_length = 0U; + APP_FOPS.Control_req(req->bRequest, (uint8_t *)req, &data_length); + } + + break; + } + + /* Standard Requests -------------------------------*/ + case USB_REQ_TYPE_STANDARD : + { + switch (req->bRequest) + { + case USB_REQ_GET_STATUS : + { + if (((USB_CORE_MODULE *)pdev)->dev.device_status == USB_CONFIGURED) + { + USBD_CtrlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtrlError (pdev, req); + ret = USBD_FAIL; + } + + break; + } + + case USB_REQ_GET_INTERFACE : + { + if (((USB_CORE_MODULE *)pdev)->dev.device_status == USB_CONFIGURED) + { + USBD_CtrlSendData(pdev, (uint8_t *)&USBD_PRINTER_AltSet, 1U); + } + else + { + USBD_CtrlError (pdev, req); + ret = USBD_FAIL; + } + + break; + } + + case USB_REQ_SET_INTERFACE : + { + if (((USB_CORE_MODULE *)pdev)->dev.device_status != USB_CONFIGURED) + { + USBD_CtrlError (pdev, req); + ret = USBD_FAIL; + } + + break; + } + + case USB_REQ_CLEAR_FEATURE : + break; + + default : + USBD_CtrlError(pdev, req); + ret = USBD_FAIL; + } + + break; + } + + default : + USBD_CtrlError (pdev, req); + ret = USBD_FAIL; + } + + return (uint8_t)ret; +} + +/** +*\*\name USBD_PRNTER_DataIn. +*\*\fun handle data IN Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_PRNTER_DataIn (void *pdev, uint8_t epnum) +{ + if ((((USB_CORE_MODULE *)pdev)->dev.in_ep[epnum].total_data_len > 0U) && + (((USB_CORE_MODULE *)pdev)->dev.in_ep[epnum].total_data_len % ((USB_CORE_MODULE *)pdev)->dev.in_ep[epnum].maxpacket == 0U)) + { + /* Update the packet total length */ + ((USB_CORE_MODULE *)pdev)->dev.in_ep[epnum].total_data_len = 0U; + + USBDEV_EP_Tx(pdev, epnum, NULL, 0U); + } + + return USBD_OK; +} + + +/** +*\*\name USBD_PRNTER_DataOut. +*\*\fun handle data OUT Stage. +*\*\param pdev: device instance. +*\*\param epnum: endpoint index. +*\*\return USBD_OK. +*\*\ +**/ +uint8_t USBD_PRNTER_DataOut (void *pdev, uint8_t epnum) +{ + uint16_t recv_length; + + /* Get the received data length */ + recv_length = USBD_GetRxCount(pdev, epnum); + + APP_FOPS.Receive(USB_Rx_Buffer, &recv_length); + + return USBD_OK; +} + +/** +*\*\name USBD_PRNTER_GetCfgDesc. +*\*\fun Return configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +*\*\ +**/ +static uint8_t *USBD_PRNTER_GetCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_PRNT_CfgDesc); + return USBD_PRNT_CfgDesc; +} + +/** +*\*\name USBD_PRNTER_GetOtherCfgDesc. +*\*\fun Return configuration descriptor. +*\*\param speed : current device speed +*\*\param length : pointer data length +*\*\return pointer to descriptor buffer. +*\*\ +**/ +static uint8_t *USBD_PRNTER_GetOtherCfgDesc (uint8_t speed, uint16_t *length) +{ + *length = sizeof (USBD_PRNT_CfgDesc); + return USBD_PRNT_CfgDesc; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_core.h new file mode 100644 index 0000000000..8a022dbd28 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_core.h @@ -0,0 +1,78 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBD_CORE_H__ +#define __USBD_CORE_H__ + +#include "usbhs_dcd.h" +#include "usbd_def.h" +#include "usbd_conf.h" + + +typedef enum +{ + USBD_OK = 0, + USBD_BUSY, + USBD_FAIL, +}USBD_Status; + +void USBD_Init(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID, USBD_DEVICE_DESC *pDevice, USBD_Class_cb_TypeDef *class_cb, USBD_User_cb_TypeDef *user_cb); + +USBD_Status USBD_DeInit(USB_CORE_MODULE *USBx); + +USBD_Status USBD_ClrCfg(USB_CORE_MODULE *USBx, uint8_t cfgidx); + +USBD_Status USBD_SetCfg(USB_CORE_MODULE *USBx, uint8_t cfgidx); + +#endif /* __USBD_CORE_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_def.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_def.h new file mode 100644 index 0000000000..ebfbcf36ad --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_def.h @@ -0,0 +1,124 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_def.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBD_DEF_H__ +#define __USBD_DEF_H__ + + +#include "usbd_conf.h" +#include "n32h76x_78x.h" + +#ifndef NULL +#define NULL 0 +#endif + +#define USB_LEN_DEV_QUALIFIER_DESC 0x0A +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 + + +#define USBD_IDX_LANGID_STR 0x00 +#define USBD_IDX_MFC_STR 0x01 +#define USBD_IDX_PRODUCT_STR 0x02 +#define USBD_IDX_SERIAL_STR 0x03 +#define USBD_IDX_CONFIG_STR 0x04 +#define USBD_IDX_INTERFACE_STR 0x05 + +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_MASK 0x60 + +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_MASK 0x03 + +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 +#define USB_DESC_TYPE_BOS 0x0F + +#define USB_CONFIG_REMOTE_WAKEUP 2 +#define USB_CONFIG_SELF_POWERED 1 + +#define USB_FEATURE_EP_HALT 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 + + +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) + +#define LOBYTE(x) ((uint8_t)((x) & 0x00FF)) +#define HIBYTE(x) ((uint8_t)(((x) & 0xFF00) >>8)) + +#endif /* __USBD_DEF_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_ioreq.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_ioreq.h new file mode 100644 index 0000000000..b88b48adbd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_ioreq.h @@ -0,0 +1,78 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_ioreq.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBD_IOREQ_H__ +#define __USBD_IOREQ_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_def.h" +#include "usbd_core.h" + + +USBD_Status USBD_CtrlSendData (USB_CORE_MODULE *USBx, uint8_t *buf, uint16_t len); + +USBD_Status USBD_CtrlContinueSendData (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len); + +USBD_Status USBD_CtrlSendStatus (USB_CORE_MODULE *USBx); + +USBD_Status USBD_CtrlPrepareRx (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len); + +USBD_Status USBD_CtrlContinueRx (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len); + +USBD_Status USBD_CtrlReceiveStatus (USB_CORE_MODULE *USBx); + +uint16_t USBD_GetRxCount (USB_CORE_MODULE *USBx , uint8_t epnum); + + +#endif /* __USBD_IOREQ_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_req.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_req.h new file mode 100644 index 0000000000..8d7af54c46 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/inc/usbd_req.h @@ -0,0 +1,73 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_req.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USB_REQUEST_H__ +#define __USB_REQUEST_H__ + +#include "usbd_def.h" +#include "usbd_core.h" +#include "usbd_conf.h" + + +USBD_Status USBD_StdDevReq(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +USBD_Status USBD_StdItfReq(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +USBD_Status USBD_StdEPReq(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +void USBD_ParseSetupRequest(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); + +void USBD_CtrlError(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); + +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); + + +#endif /* __USB_REQUEST_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_core.c new file mode 100644 index 0000000000..af10bdc884 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_core.c @@ -0,0 +1,441 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbd_core.h" +#include "usbd_req.h" +#include "usbd_ioreq.h" +#include "usbhs_dcd_int.h" +#include "usbhs_bsp.h" + +static uint8_t USBD_SetupStage(USB_CORE_MODULE *USBx); +static uint8_t USBD_DataOutStage(USB_CORE_MODULE *USBx , uint8_t epnum); +static uint8_t USBD_DataInStage(USB_CORE_MODULE *USBx , uint8_t epnum); +static uint8_t USBD_SOF(USB_CORE_MODULE *USBx); +static uint8_t USBD_Reset(USB_CORE_MODULE *USBx); +static uint8_t USBD_Suspend(USB_CORE_MODULE *USBx); +static uint8_t USBD_Resume(USB_CORE_MODULE *USBx); +static uint8_t USBD_IsoINIncomplete(USB_CORE_MODULE *USBx); +static uint8_t USBD_IsoOUTIncomplete(USB_CORE_MODULE *USBx); +static uint8_t USBD_RunTestMode (USB_CORE_MODULE *USBx) ; + +static uint8_t USBD_DevConnected(USB_CORE_MODULE *pdev); +static uint8_t USBD_DevDisconnected(USB_CORE_MODULE *pdev); + + + +USBD_DEV_INT_cb_TypeDef USBD_DEV_INT_cb = +{ + USBD_DataOutStage, + USBD_DataInStage, + USBD_SetupStage, + USBD_SOF, + USBD_Reset, + USBD_Suspend, + USBD_Resume, + USBD_IsoINIncomplete, + USBD_IsoOUTIncomplete, + USBD_DevConnected, + USBD_DevDisconnected, +}; + +USBD_DEV_INT_cb_TypeDef *USBD_DEV_INT_fops = &USBD_DEV_INT_cb; + +uint32_t SET_TEST_MODE = 0; + +/** +*\*\name USBD_Init. +*\*\fun Initializes the device stack and load the class driver. +*\*\param USBx : USB device +*\*\param pDevice: device instance +*\*\param class_cb: Class callback structure address +*\*\param user_cb: User callback structure address +*\*\return none +**/ +void USBD_Init(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID, USBD_DEVICE_DESC *pDevice, USBD_Class_cb_TypeDef *class_cb, USBD_User_cb_TypeDef *user_cb) +{ + /* Hardware Init */ + USB_BSP_Init(); + + /*Register class and user callbacks */ + USBx->dev.class_cb = class_cb; + USBx->dev.user_cb = user_cb; + USBx->dev.user_device = pDevice; + + /* Initializes the USB core*/ + USBDEV_CoreInit(USBx, coreID); + + /* Upon Init call user callback */ + USBx->dev.user_cb->Init(); + + /* Enable Interrupts */ + USB_BSP_EnableInterrupt(USBx, coreID); +} + +/** +*\*\name USBD_DeInit. +*\*\fun Re-Initialize the device library +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +USBD_Status USBD_DeInit(USB_CORE_MODULE *USBx) +{ + /* Software Init */ + return USBD_OK; +} + +/** +*\*\name USBD_SetupStage. +*\*\fun Handle the setup stage +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_SetupStage(USB_CORE_MODULE *USBx) +{ + USB_SETUP_REQ req; + + USBD_ParseSetupRequest(USBx , &req); + + switch (req.bmRequest & 0x1F) + { + case USB_REQ_RECIPIENT_DEVICE: + USBD_StdDevReq (USBx, &req); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + USBD_StdItfReq(USBx, &req); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + USBD_StdEPReq(USBx, &req); + break; + + default: + USBDEV_EP_Stall(USBx , req.bmRequest & 0x80U); + break; + } + return USBD_OK; +} + +/** +*\*\name USBD_DataOutStage. +*\*\fun Handle data out stage +*\*\param USBx : USB device +*\*\param epnum: endpoint index +*\*\return USBD_OK +**/ +static uint8_t USBD_DataOutStage(USB_CORE_MODULE *USBx , uint8_t epnum) +{ + USB_EP *ep; + + if(epnum == 0) + { + ep = &USBx->dev.out_ep[0]; + if ( USBx->dev.device_state == USB_EP0_DATA_OUT) + { + if(ep->rem_data_len > ep->maxpacket) + { + ep->rem_data_len -= ep->maxpacket; + + if(USBx->cfg.dma_enable == 1) + { + /* in slave mode this, is handled by the RxSTSQLvl ISR */ + ep->xfer_buff += ep->maxpacket; + } + USBD_CtrlContinueRx (USBx, ep->xfer_buff, MIN(ep->rem_data_len ,ep->maxpacket)); + } + else + { + if((USBx->dev.class_cb->EP0_RxReady != NULL) && (USBx->dev.device_status == USB_CONFIGURED)) + { + USBx->dev.class_cb->EP0_RxReady(USBx); + } + USBD_CtrlSendStatus(USBx); + } + } + } + else if((USBx->dev.class_cb->DataOut != NULL) && (USBx->dev.device_status == USB_CONFIGURED)) + { + USBx->dev.class_cb->DataOut(USBx, epnum); + } + + else + { + /* Do Nothing */ + } + return USBD_OK; +} + +/** +*\*\name USBD_DataInStage. +*\*\fun Handle data in stage +*\*\param USBx : USB device +*\*\param epnum: endpoint index +*\*\return USBD_OK +**/ +static uint8_t USBD_DataInStage(USB_CORE_MODULE *USBx , uint8_t epnum) +{ + USB_EP *ep; + + if(epnum == 0) + { + ep = &USBx->dev.in_ep[0]; + if ( USBx->dev.device_state == USB_EP0_DATA_IN) + { + if(ep->rem_data_len > ep->maxpacket) + { + ep->rem_data_len -= ep->maxpacket; + if(USBx->cfg.dma_enable == 1) + { + /* in slave mode this, is handled by the TxFifoEmpty ISR */ + ep->xfer_buff += ep->maxpacket; + } + USBD_CtrlContinueSendData (USBx, ep->xfer_buff, ep->rem_data_len); + + /* Start the transfer */ + USBDEV_EP_PrepareRx (USBx, 0, ep->xfer_buff, 0); + } + else + { /* last packet is MPS multiple, so send ZLP packet */ + if((ep->total_data_len % ep->maxpacket == 0) &&(ep->total_data_len >= ep->maxpacket) && (ep->total_data_len < ep->ctrl_data_len )) + { + USBD_CtrlContinueSendData(USBx , ep->xfer_buff, 0); + ep->ctrl_data_len = 0; + /* Start the transfer */ + USBDEV_EP_PrepareRx (USBx, 0, ep->xfer_buff, 0); + } + else + { + if((USBx->dev.class_cb->EP0_TxSent != NULL) && (USBx->dev.device_status == USB_CONFIGURED)) + { + USBx->dev.class_cb->EP0_TxSent(USBx); + } + USBD_CtrlReceiveStatus(USBx); + } + } + } + if (USBx->dev.test_mode == 1) + { + USBD_RunTestMode(USBx); + USBx->dev.test_mode = 0; + } + } + else if((USBx->dev.class_cb->DataIn != NULL) && (USBx->dev.device_status == USB_CONFIGURED)) + { + USBx->dev.class_cb->DataIn(USBx, epnum); + } + + else + { + /* Do Nothing */ + } + return USBD_OK; +} + +/** +*\*\name USBD_RunTestMode. +*\*\fun Launch test mode process +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_RunTestMode (USB_CORE_MODULE *USBx) +{ + USB_WRITE_REG32(&USBx->regs.DCSR->DCTRL, SET_TEST_MODE); + return USBD_OK; +} + +/** +*\*\name USBD_Reset. +*\*\fun Handle Reset event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_Reset(USB_CORE_MODULE *USBx) +{ + /* Open EP0 OUT */ + USBDEV_EP_Open(USBx, 0x00, USB_MAX_EP0_SIZE, EP_TYPE_CTRL); + /* Open EP0 IN */ + USBDEV_EP_Open(USBx, 0x80, USB_MAX_EP0_SIZE, EP_TYPE_CTRL); + + /* Upon Reset call user call back */ + USBx->dev.device_status = USB_DEFAULT; + USBx->dev.user_cb->DeviceReset(USBx->cfg.speed); + + return USBD_OK; +} + +/** +*\*\name USBD_Resume. +*\*\fun Handle Resume event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_Resume(USB_CORE_MODULE *USBx) +{ + /* Upon Resume call user call back */ + USBx->dev.user_cb->DeviceResumed(); + USBx->dev.device_status = USBx->dev.device_old_status; + USBx->dev.device_status = USB_CONFIGURED; + return USBD_OK; +} + +/** +*\*\name USBD_Suspend. +*\*\fun Handle Suspend event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_Suspend(USB_CORE_MODULE *USBx) +{ + USBx->dev.device_old_status = USBx->dev.device_status; + USBx->dev.device_status = USB_SUSPENDED; + /* Upon Resume call user call back */ + USBx->dev.user_cb->DeviceSuspended(); + return USBD_OK; +} + +/** +*\*\name USBD_SOF. +*\*\fun Handle SOF event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_SOF(USB_CORE_MODULE *USBx) +{ + if(USBx->dev.class_cb->SOF) + { + USBx->dev.class_cb->SOF(USBx); + } + return USBD_OK; +} + +/** +*\*\name USBD_SetCfg. +*\*\fun Configure device and start the interface +*\*\param USBx : USB device +*\*\param cfgidx: configuration index +*\*\return USBD_OK +**/ +USBD_Status USBD_SetCfg(USB_CORE_MODULE *USBx, uint8_t cfgidx) +{ + USBx->dev.class_cb->Init(USBx, cfgidx); + + /* Upon set config call user call back */ + USBx->dev.user_cb->DeviceConfigured(); + return USBD_OK; +} + +/** +*\*\name USBD_ClrCfg. +*\*\fun Clear current configuration +*\*\param USBx : USB device +*\*\param cfgidx: configuration index +*\*\return USBD_OK +**/ +USBD_Status USBD_ClrCfg(USB_CORE_MODULE *USBx, uint8_t cfgidx) +{ + USBx->dev.class_cb->DeInit(USBx, cfgidx); + return USBD_OK; +} + +/** +*\*\name USBD_IsoINIncomplete. +*\*\fun Handle iso in incomplete event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_IsoINIncomplete(USB_CORE_MODULE *USBx) +{ + USBx->dev.class_cb->IsoINIncomplete(USBx); + return USBD_OK; +} + +/** +*\*\name USBD_IsoOUTIncomplete. +*\*\fun Handle iso out incomplete event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_IsoOUTIncomplete(USB_CORE_MODULE *USBx) +{ + USBx->dev.class_cb->IsoOUTIncomplete(USBx); + return USBD_OK; +} + +/** +*\*\name USBD_DevConnected. +*\*\fun Handle device connection event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_DevConnected(USB_CORE_MODULE *USBx) +{ + USBx->dev.user_cb->DeviceConnected(); + USBx->dev.connection_status = 1; + return USBD_OK; +} + +/** +*\*\name USBD_DevDisconnected. +*\*\fun Handle device disconnection event +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +static uint8_t USBD_DevDisconnected(USB_CORE_MODULE *USBx) +{ + USBx->dev.user_cb->DeviceDisconnected(); + USBx->dev.class_cb->DeInit(USBx, 0); + USBx->dev.connection_status = 0; + return USBD_OK; +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_ioreq.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_ioreq.c new file mode 100644 index 0000000000..3b1e5d393b --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_ioreq.c @@ -0,0 +1,175 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_ioreq.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_ioreq.h" + +/** +*\*\name USBD_CtrlSendData. +*\*\fun send data on the ctrl pipe +*\*\param USBx : USB device +*\*\param pbuf: pointer to data buffer +*\*\param len: length of data to be sent +*\*\return USBD_OK +**/ +USBD_Status USBD_CtrlSendData (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len) +{ + USBD_Status ret = USBD_OK; + + USBx->dev.in_ep[0].total_data_len = len; + USBx->dev.in_ep[0].rem_data_len = len; + USBx->dev.device_state = USB_EP0_DATA_IN; + + USBDEV_EP_Tx (USBx, 0, pbuf, len); + + return ret; +} + +/** +*\*\name USBD_CtrlContinueSendData. +*\*\fun continue sending data on the ctrl pipe +*\*\param USBx : USB device +*\*\param pbuf: pointer to data buffer +*\*\param len: length of data to be sent +*\*\return USBD_OK +**/ +USBD_Status USBD_CtrlContinueSendData (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len) +{ + USBD_Status ret = USBD_OK; + + USBDEV_EP_Tx (USBx, 0, pbuf, len); + + return ret; +} + +/** +*\*\name USBD_CtrlPrepareRx. +*\*\fun receive data on the ctrl pipe +*\*\param USBx : USB device +*\*\param pbuf: pointer to data buffer +*\*\param len: length of data to be sent +*\*\return USBD_OK +**/ +USBD_Status USBD_CtrlPrepareRx (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len) +{ + USBD_Status ret = USBD_OK; + + USBx->dev.out_ep[0].total_data_len = len; + USBx->dev.out_ep[0].rem_data_len = len; + USBx->dev.device_state = USB_EP0_DATA_OUT; + + USBDEV_EP_PrepareRx (USBx, 0, pbuf, len); + + return ret; +} + +/** +*\*\name USBD_CtrlContinueRx. +*\*\fun continue receive data on the ctrl pipe +*\*\param USBx : USB device +*\*\param pbuf: pointer to data buffer +*\*\param len: length of data to be sent +*\*\return USBD_OK +**/ +USBD_Status USBD_CtrlContinueRx (USB_CORE_MODULE *USBx, uint8_t *pbuf, uint16_t len) +{ + USBD_Status ret = USBD_OK; + + USBDEV_EP_PrepareRx (USBx, 0, pbuf, len); + return ret; +} + +/** +*\*\name USBD_CtrlSendStatus. +*\*\fun send zero length packet on the ctrl pipe +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +USBD_Status USBD_CtrlSendStatus (USB_CORE_MODULE *USBx) +{ + USBD_Status ret = USBD_OK; + USBx->dev.device_state = USB_EP0_STATUS_IN; + USBDEV_EP_Tx (USBx, 0, USBx->dev.out_ep[0].xfer_buff, 0); + + USB_EP0_OutStart(USBx); + + return ret; +} + +/** +*\*\name USBD_CtrlReceiveStatus. +*\*\fun receive zero length packet on the ctrl pipe +*\*\param USBx : USB device +*\*\return USBD_OK +**/ +USBD_Status USBD_CtrlReceiveStatus (USB_CORE_MODULE *USBx) +{ + USBD_Status ret = USBD_OK; + USBx->dev.device_state = USB_EP0_STATUS_OUT; + USBDEV_EP_PrepareRx ( USBx, 0, USBx->dev.setup_packet, 0); + + USB_EP0_OutStart(USBx); + + return ret; +} + +/** +*\*\name USBD_GetRxCount. +*\*\fun returns the received data length +*\*\param USBx : USB device +*\*\param epnum: endpoint index +*\*\return USBD_OK +**/ +uint16_t USBD_GetRxCount (USB_CORE_MODULE *USBx , uint8_t epnum) +{ + return USBx->dev.out_ep[epnum].xfer_count; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_req.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_req.c new file mode 100644 index 0000000000..03822cc62c --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/device/core/src/usbd_req.c @@ -0,0 +1,758 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbd_req.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbd_req.h" +#include "usbd_ioreq.h" +#include "usbd_desc.h" + + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0; + +#ifdef USB_HS_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_HS_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; + + +static void USBD_GetDescriptor(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static void USBD_SetAddress(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static void USBD_SetConfig(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static void USBD_GetConfig(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static void USBD_GetStatus(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static void USBD_SetFeature(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static void USBD_ClrFeature(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req); +static uint8_t USBD_GetLen(uint8_t *buf); + +extern uint32_t SET_TEST_MODE; + +/** +*\*\name USBD_StdDevReq. +*\*\fun Handle standard usb device requests +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return USBD_OK +**/ +USBD_Status USBD_StdDevReq (USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor (USBx, req) ; + break; + + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(USBx, req); + break; + + case USB_REQ_SET_CONFIGURATION: + USBD_SetConfig (USBx , req); + break; + + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig (USBx , req); + break; + + case USB_REQ_GET_STATUS: + USBD_GetStatus (USBx , req); + break; + + case USB_REQ_SET_FEATURE: + USBD_SetFeature (USBx , req); + break; + + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature (USBx , req); + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + return ret; +} + +/** +*\*\name USBD_StdItfReq. +*\*\fun Handle standard usb interface requests +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return USBD_OK +**/ +USBD_Status USBD_StdItfReq(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + USBD_Status ret = USBD_OK; + + switch (USBx->dev.device_status) + { + case USB_CONFIGURED: + if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) + { + USBx->dev.class_cb->Setup (USBx, req); + if((req->wLength == 0) && (ret == USBD_OK)) + { + USBD_CtrlSendStatus(USBx); + } + } + else + { + USBD_CtrlError(USBx , req); + } + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + return ret; +} + +/** +*\*\name USBD_StdEPReq. +*\*\fun Handle standard usb endpoint requests +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return USBD_OK +**/ +USBD_Status USBD_StdEPReq(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + uint8_t ep_addr; + USBD_Status ret = USBD_OK; + + ep_addr = LOBYTE(req->wIndex); + + /* Check the class specific requests before going to standard request */ + if ((req->bmRequest & USB_REQ_TYPE_MASK) == USB_REQ_TYPE_CLASS) + { + USBx->dev.class_cb->Setup (USBx, req); + return ret; + } + + switch (req->bRequest) + { + case USB_REQ_SET_FEATURE : + switch (USBx->dev.device_status) + { + case USB_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBDEV_EP_Stall(USBx , ep_addr); + } + break; + + case USB_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBDEV_EP_Stall(USBx , ep_addr); + } + } + USBx->dev.class_cb->Setup(USBx, req); + USBD_CtrlSendStatus(USBx); + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + break; + + case USB_REQ_CLEAR_FEATURE : + + switch (USBx->dev.device_status) + { + case USB_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBDEV_EP_Stall(USBx , ep_addr); + } + break; + + case USB_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBDEV_EP_ClrStall(USBx , ep_addr); + USBx->dev.class_cb->Setup (USBx, req); + } + USBD_CtrlSendStatus(USBx); + } + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (USBx->dev.device_status) + { + case USB_ADDRESSED: + if ((ep_addr != 0x00) && (ep_addr != 0x80)) + { + USBDEV_EP_Stall(USBx , ep_addr); + } + break; + + case USB_CONFIGURED: + if ((ep_addr & 0x80)== 0x80) + { + if(USBx->dev.in_ep[ep_addr & 0x7F].is_stall) + { + USBD_ep_status = 0x0001; + } + else + { + USBD_ep_status = 0x0000; + } + } + else if ((ep_addr & 0x80)== 0x00) + { + if(USBx->dev.out_ep[ep_addr].is_stall) + { + USBD_ep_status = 0x0001; + } + else + { + USBD_ep_status = 0x0000; + } + } + else + { + /* Do Nothing */ + } + USBD_CtrlSendData (USBx, (uint8_t *)&USBD_ep_status, 2); + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + break; + + default: + break; + } + return ret; +} + +/** +*\*\name USBD_GetDescriptor. +*\*\fun Handle standard usb Descriptor requests +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return USBD_OK +**/ +static void USBD_GetDescriptor(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + uint16_t len; + uint8_t *pbuf; + len = req->wLength ; + + switch (req->wValue >> 8) + { +#if (USBD_LPM_ENABLED == 1) + case USB_DESC_TYPE_BOS: + pbuf = USBx->pDesc->GetBOSDescriptor(USBx->dev_speed, &len); + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = USBx->dev.user_device->GetDeviceDescriptor(USBx->cfg.speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + pbuf = (uint8_t *)USBx->dev.class_cb->GetConfigDescriptor(USBx->cfg.speed, &len); + if(USBx->cfg.speed == USB_SPEED_FULL) + { + pbuf = (uint8_t *)USBx->dev.class_cb->GetOtherConfigDescriptor(USBx->cfg.speed, &len); + } + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + USBx->dev.pConfig_descriptor = pbuf; + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + pbuf = USBx->dev.user_device->GetLangIDStrDescriptor(USBx->cfg.speed, &len); + break; + + case USBD_IDX_MFC_STR: + pbuf = USBx->dev.user_device->GetManufacturerStrDescriptor(USBx->cfg.speed, &len); + break; + + case USBD_IDX_PRODUCT_STR: + pbuf = USBx->dev.user_device->GetProductStrDescriptor(USBx->cfg.speed, &len); + break; + + case USBD_IDX_SERIAL_STR: + pbuf = USBx->dev.user_device->GetSerialStrDescriptor(USBx->cfg.speed, &len); + break; + + case USBD_IDX_CONFIG_STR: + pbuf = USBx->dev.user_device->GetConfigurationStrDescriptor(USBx->cfg.speed, &len); + break; + + case USBD_IDX_INTERFACE_STR: + pbuf = USBx->dev.user_device->GetInterfaceStrDescriptor(USBx->cfg.speed, &len); + break; + + default: +#ifdef USB_SUPPORT_USER_STRING_DESC + pbuf = USBx->dev.class_cb->GetUserStrDescriptor(USBx->cfg.speed, (req->wValue) , &len); + break; +#else + USBD_CtrlError(USBx , req); + return; +#endif /* USBD_CtrlError(USBx , req)*/ + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: + if(USBx->cfg.speed == USB_SPEED_HIGH) + { + pbuf = (uint8_t *)USBx->dev.class_cb->GetConfigDescriptor(USBx->cfg.speed, &len); + + USBD_DeviceQualifierDesc[4]= pbuf[14]; + USBD_DeviceQualifierDesc[5]= pbuf[15]; + USBD_DeviceQualifierDesc[6]= pbuf[16]; + + pbuf = USBD_DeviceQualifierDesc; + len = USB_LEN_DEV_QUALIFIER_DESC; + break; + } + else + { + USBD_CtrlError(USBx , req); + return; + } + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if(USBx->cfg.speed == USB_SPEED_HIGH) + { + pbuf = (uint8_t *)USBx->dev.class_cb->GetOtherConfigDescriptor(USBx->cfg.speed, &len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + break; + } + else + { + USBD_CtrlError(USBx , req); + return; + } + + default: + USBD_CtrlError(USBx , req); + + return; + } + if((len != 0)&& (req->wLength != 0)) + { + len = MIN(len , req->wLength); + USBD_CtrlSendData (USBx, pbuf, len); + } +} + +/** +*\*\name USBD_SetAddress. +*\*\fun Set device address +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +static void USBD_SetAddress(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0) && (req->wLength == 0)) + { + dev_addr = (uint8_t)(req->wValue) & 0x7F; + + if (USBx->dev.device_status == USB_CONFIGURED) + { + USBD_CtrlError(USBx , req); + } + else + { + USBx->dev.device_address = dev_addr; + USBDEV_EP_SetAddress(USBx, dev_addr); + USBD_CtrlSendStatus(USBx); + + if (dev_addr != 0) + { + USBx->dev.device_status = USB_ADDRESSED; + } + else + { + USBx->dev.device_status = USB_DEFAULT; + } + } + } + else + { + USBD_CtrlError(USBx , req); + } +} + +/** +*\*\name USBD_SetConfig. +*\*\fun Handle Set device configuration request +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +static void USBD_SetConfig(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + static uint8_t cfgidx; + + cfgidx = (uint8_t)(req->wValue); + + if (cfgidx > USBD_CFG_MAX_NUM ) + { + USBD_CtrlError(USBx , req); + } + else + { + switch (USBx->dev.device_status) + { + case USB_ADDRESSED: + if (cfgidx) + { + USBx->dev.device_config = cfgidx; + USBx->dev.device_status = USB_CONFIGURED; + USBD_SetCfg(USBx, cfgidx); + USBD_CtrlSendStatus(USBx); + } + else + { + USBD_CtrlSendStatus(USBx); + } + break; + + case USB_CONFIGURED: + if (cfgidx == 0) + { + USBx->dev.device_status = USB_ADDRESSED; + USBx->dev.device_config = cfgidx; + USBD_ClrCfg(USBx, cfgidx); + USBD_CtrlSendStatus(USBx); + } + else if (cfgidx != USBx->dev.device_config) + { + /* Clear old configuration */ + USBD_ClrCfg(USBx, USBx->dev.device_config); + + /* set new configuration */ + USBx->dev.device_config = cfgidx; + USBD_SetCfg(USBx, cfgidx); + USBD_CtrlSendStatus(USBx); + } + else + { + USBD_CtrlSendStatus(USBx); + } + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + } +} + +/** +*\*\name USBD_GetConfig. +*\*\fun Handle Get device configuration request +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +static void USBD_GetConfig(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + if (req->wLength != 1) + { + USBD_CtrlError(USBx , req); + } + else + { + switch (USBx->dev.device_status ) + { + case USB_ADDRESSED: + USBD_CtrlSendData (USBx, (uint8_t *)&USBD_default_cfg, 1); + break; + + case USB_CONFIGURED: + USBD_CtrlSendData (USBx, &USBx->dev.device_config, 1); + break; + + default: + USBD_CtrlError(USBx , req); + break; + } + } +} + +/** +*\*\name USBD_GetStatus. +*\*\fun Handle Get Status request +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +static void USBD_GetStatus(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + switch (USBx->dev.device_status) + { + case USB_ADDRESSED: + case USB_CONFIGURED: + +#ifdef USBD_SELF_POWERED + USBD_cfg_status = USB_CONFIG_SELF_POWERED; +#else + USBD_cfg_status = 0x00; +#endif + + if (USBx->dev.DevRemoteWakeup) + { + USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + USBD_CtrlSendData (USBx, (uint8_t *)&USBD_cfg_status, 2); + break; + + default : + USBD_CtrlError(USBx, req); + break; + } +} + +/** +*\*\name USBD_SetFeature. +*\*\fun Handle Set Status request +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +static void USBD_SetFeature(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + uint32_t dctl; + uint8_t test_mode = 0; + + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + USBx->dev.DevRemoteWakeup = 1; + USBx->dev.class_cb->Setup (USBx, req); + USBD_CtrlSendStatus(USBx); + } + + else if ((req->wValue == USB_FEATURE_TEST_MODE) && ((req->wIndex & 0xFF) == 0)) + { + dctl = USB_READ_REG32(&USBx->regs.DCSR->DCTRL); + + test_mode = req->wIndex >> 8; + switch (test_mode) + { + case 1: /* TEST_J */ + dctl |= 1<<4; + break; + + case 2: /* TEST_K */ + dctl |= 2<<4; + break; + + case 3: /* TEST_SE0_NAK */ + dctl |= 3<<4; + break; + + case 4: /* TEST_PACKET */ + dctl |= 4<<4; + break; + + case 5: /* TEST_FORCE_ENABLE */ + dctl |= 5<<4; + break; + + default : + dctl |= 1<<4; + break; + } + USB_WRITE_REG32(&USBx->regs.DCSR->DCTRL, dctl); + SET_TEST_MODE = dctl; + USBx->dev.test_mode = 1; + USBD_CtrlSendStatus(USBx); + } + else + { + /* Do Nothing */ + } +} + +/** +*\*\name USBD_ClrFeature. +*\*\fun Handle clear device feature request +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +static void USBD_ClrFeature(USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + switch (USBx->dev.device_status) + { + case USB_ADDRESSED: + case USB_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + { + USBx->dev.DevRemoteWakeup = 0; + USBx->dev.class_cb->Setup (USBx, req); + USBD_CtrlSendStatus(USBx); + } + break; + + default : + USBD_CtrlError(USBx , req); + break; + } +} + +/** +*\*\name USBD_ParseSetupRequest. +*\*\fun Copy buffer into setup structure +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +void USBD_ParseSetupRequest( USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + req->bmRequest = *(uint8_t *) (USBx->dev.setup_packet); + req->bRequest = *(uint8_t *) (USBx->dev.setup_packet + 1); + req->wValue = SWAPBYTE (USBx->dev.setup_packet + 2); + req->wIndex = SWAPBYTE (USBx->dev.setup_packet + 4); + req->wLength = SWAPBYTE (USBx->dev.setup_packet + 6); + + USBx->dev.in_ep[0].ctrl_data_len = req->wLength ; + USBx->dev.device_state = USB_EP0_SETUP; +} + +/** +*\*\name USBD_CtrlError. +*\*\fun Handle USB low level Error +*\*\param USBx : USB device +*\*\param req: usb request +*\*\return none +**/ +void USBD_CtrlError( USB_CORE_MODULE *USBx, USB_SETUP_REQ *req) +{ + USBDEV_EP_Stall(USBx , 0x80); + USBDEV_EP_Stall(USBx , 0); + USB_EP0_OutStart(USBx); +} + +/** +*\*\name USBD_GetString. +*\*\fun Convert Ascii string into unicode one +*\*\param desc : descriptor buffer +*\*\param unicode : Formatted string buffer (unicode) +*\*\param len : descriptor length +*\*\return none +**/ +void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0; + + if (desc != NULL) + { + *len = USBD_GetLen(desc) * 2 + 2; + unicode[idx++] = *len; + unicode[idx++] = USB_DESC_TYPE_STRING; + + while (*desc != '\0') + { + unicode[idx++] = *desc++; + unicode[idx++] = 0x00; + } + } +} + +/** +*\*\name USBD_GetLen. +*\*\fun return the string length +*\*\param buf : pointer to the ascii string buffer +*\*\return string length +**/ +static uint8_t USBD_GetLen(uint8_t *buf) +{ + uint8_t len = 0; + + while (*buf != '\0') + { + len++; + buf++; + } + + return len; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_core.h new file mode 100644 index 0000000000..78d0ea719f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_core.h @@ -0,0 +1,344 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBHS_CORE_H__ +#define __USBHS_CORE_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbhs_conf.h" +#include "usbhs_regs.h" +#include "usbhs_defines.h" + + +#define USB_EP0_IDLE 0 +#define USB_EP0_SETUP 1 +#define USB_EP0_DATA_IN 2 +#define USB_EP0_DATA_OUT 3 +#define USB_EP0_STATUS_IN 4 +#define USB_EP0_STATUS_OUT 5 +#define USB_EP0_STALL 6 + +#define USB_EP_TX_DIS 0x0000 +#define USB_EP_TX_STALL 0x0010 +#define USB_EP_TX_NAK 0x0020 +#define USB_EP_TX_VALID 0x0030 + +#define USB_EP_RX_DIS 0x0000 +#define USB_EP_RX_STALL 0x1000 +#define USB_EP_RX_NAK 0x2000 +#define USB_EP_RX_VALID 0x3000 + +#define MAX_DATA_LENGTH 0x200 + + +typedef enum +{ + USB_OK = 0, + USB_FAIL +}USB_STS; + +typedef enum +{ + HCH_IDLE = 0, + HCH_XFRC, + HCH_HALTED, + HCH_NAK, + HCH_NYET, + HCH_STALL, + HCH_XACTERR, + HCH_BBLERR, + HCH_DATATGLERR, +}HCH_STATUS; /* USB Host channel status */ + +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL +}URB_STATE; /* USB Request Block */ + +typedef enum +{ + CTRL_START = 0, + CTRL_XFRC, + CTRL_HALTED, + CTRL_NAK, + CTRL_STALL, + CTRL_XACTERR, + CTRL_BBLERR, + CTRL_DATATGLERR, + CTRL_FAIL +}CTRL_STATUS; + + +typedef struct +{ + uint8_t dev_addr; + uint8_t ep_num; + uint8_t ep_is_in; + uint8_t speed; + uint8_t do_ping; + uint8_t ep_type; + uint16_t max_packet; + uint8_t data_pid; + uint8_t *xfer_buff; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t toggle_in; + uint8_t toggle_out; + uint32_t dma_addr; +}USB_HCH; + +typedef struct +{ + uint8_t num; + uint8_t is_in; + uint8_t is_stall; + uint8_t type; + uint8_t data_pid_start; + uint8_t even_odd_frame; + uint16_t tx_fifo_num; + uint32_t maxpacket; + /* transaction level variables*/ + uint8_t *xfer_buff; + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + /* Transfer level variables*/ + uint32_t rem_data_len; + uint32_t total_data_len; + uint32_t ctrl_data_len; +}USB_EP; + + +typedef struct +{ + uint8_t host_channels_num; + uint8_t dev_endpoints_num; + uint8_t speed; + uint8_t dma_enable; + uint16_t mps; + uint16_t TotalFifoSize; + uint8_t low_power; + uint8_t Reseved[3]; +}USB_CORE_CFGS; + + +typedef struct +{ + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +}USB_SETUP_REQ; + +typedef struct +{ + uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); +} USBD_DEVICE_DESC; + +typedef struct +{ + uint8_t (*Init) (void *USBx, uint8_t cfgidx); + uint8_t (*DeInit) (void *USBx, uint8_t cfgidx); + /* Control Endpoints*/ + uint8_t (*Setup) (void *USBx, USB_SETUP_REQ *req); + uint8_t (*EP0_TxSent) (void *USBx); + uint8_t (*EP0_RxReady) (void *USBx); + /* Class Specific Endpoints*/ + uint8_t (*DataIn) (void *USBx, uint8_t epnum); + uint8_t (*DataOut) (void *USBx, uint8_t epnum); + uint8_t (*SOF) (void *USBx); + uint8_t (*IsoINIncomplete) (void *USBx); + uint8_t (*IsoOUTIncomplete) (void *USBx); + uint8_t *(*GetConfigDescriptor)( uint8_t speed, uint16_t *length); + uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); + +#ifdef USB_SUPPORT_USER_STRING_DESC + uint8_t *(*GetUserStrDescriptor)( uint8_t speed,uint8_t index, uint16_t *length); +#endif +} USBD_Class_cb_TypeDef; + + +typedef struct +{ + void (*Init)(void); + void (*DeviceReset)(uint8_t speed); + void (*DeviceConfigured)(void); + void (*DeviceSuspended)(void); + void (*DeviceResumed)(void); + void (*DeviceConnected)(void); + void (*DeviceDisconnected)(void); +}USBD_User_cb_TypeDef; + +typedef struct +{ + uint8_t device_config; + uint8_t device_state; + uint8_t device_status; + uint8_t device_old_status; + uint8_t device_address; + uint8_t connection_status; + uint8_t test_mode; + uint32_t DevRemoteWakeup; + USB_EP in_ep[USB_MAX_TX_FIFOS]; + USB_EP out_ep[USB_MAX_TX_FIFOS]; + uint8_t setup_packet[24]; + USBD_Class_cb_TypeDef *class_cb; + USBD_User_cb_TypeDef *user_cb; + USBD_DEVICE_DESC *user_device; + uint8_t *pConfig_descriptor; +}USB_DEV; + + +typedef struct +{ + uint8_t Rx_Buffer [MAX_DATA_LENGTH]; + __IO uint32_t ConnSts; + __IO uint32_t PortEnabled; + __IO uint32_t ErrCnt[USB_MAX_TX_FIFOS]; + __IO uint32_t XferCnt[USB_MAX_TX_FIFOS]; + __IO HCH_STATUS HCH_Status[USB_MAX_TX_FIFOS]; + __IO URB_STATE URB_State[USB_MAX_TX_FIFOS]; + USB_HCH hch[USB_MAX_TX_FIFOS]; + uint16_t channel[USB_MAX_TX_FIFOS]; +}USB_HOST; + + +typedef struct +{ + USB_CORE_CFGS cfg; + USB_Register regs; + +#ifdef USE_DEVICE_MODE + USB_DEV dev; +#endif +#ifdef USE_HOST_MODE + USB_HOST host; +#endif +}USB_CORE_MODULE; + + +USB_STS USB_BasicInit(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID); +USB_STS USB_CoreInit(USB_CORE_MODULE *USBx); + +USB_STS USB_EnableGlobalInt(USB_CORE_MODULE *USBx, FunctionalState cmd); + +void* USB_ReadPacket(USB_CORE_MODULE *USBx , uint8_t *dest, uint16_t len); +USB_STS USB_WritePacket(USB_CORE_MODULE *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); +USB_STS USB_FlushTxFifo(USB_CORE_MODULE *USBx , uint32_t num); +USB_STS USB_FlushRxFifo(USB_CORE_MODULE *USBx); + +uint32_t USB_ReadCoreItr(USB_CORE_MODULE *USBx); +uint8_t USB_IsHostMode(USB_CORE_MODULE *USBx); +uint8_t USB_IsDeviceMode(USB_CORE_MODULE *USBx); +uint32_t USB_GetMode(USB_CORE_MODULE *USBx); +USB_STS USB_PhyInit(USB_CORE_MODULE *USBx); +USB_STS USB_SetCurrentMode(USB_CORE_MODULE *USBx, uint8_t mode); + +/*********************** HOST APIs ********************************************/ +#ifdef USE_HOST_MODE +USB_STS USB_CoreInitHost(USB_CORE_MODULE *USBx); +USB_STS USB_EnableHostInt(USB_CORE_MODULE *USBx); +USB_STS USB_HCH_Init(USB_CORE_MODULE *USBx, uint8_t hch_num); +USB_STS USB_HCH_Halt(USB_CORE_MODULE *USBx, uint8_t hch_num); +USB_STS USB_HCH_StartXfer(USB_CORE_MODULE *USBx, uint8_t hch_num); +USB_STS USB_HCH_DoPing(USB_CORE_MODULE *USBx , uint8_t hch_num); + +uint32_t USB_ReadHostAllChannels_intr(USB_CORE_MODULE *USBx); +uint32_t USB_ResetPort(USB_CORE_MODULE *USBx); +uint32_t USB_ReadHPCS(USB_CORE_MODULE *USBx); +void USB_DriveVbus(USB_CORE_MODULE *USBx, uint8_t state); +void USB_InitFSLSPClkSel(USB_CORE_MODULE *USBx ,uint8_t freq); +uint8_t USB_IsEvenFrame(USB_CORE_MODULE *USBx) ; +void USB_StopHost(USB_CORE_MODULE *USBx); +#endif + +/********************* DEVICE APIs ********************************************/ +#ifdef USE_DEVICE_MODE +USB_STS USB_CoreInitDev(USB_CORE_MODULE *USBx); +USB_STS USB_EnableDevInt(USB_CORE_MODULE *USBx); +uint32_t USB_ReadDevAllInEPItr(USB_CORE_MODULE *USBx); +enum USB_SPEED USB_GetDeviceSpeed(USB_CORE_MODULE *USBx); +USB_STS USB_EP0Activate (USB_CORE_MODULE *USBx); +USB_STS USB_EPActivate (USB_CORE_MODULE *USBx, USB_EP *ep); +USB_STS USB_EPDeactivate(USB_CORE_MODULE *USBx, USB_EP *ep); +USB_STS USB_EPStartXfer (USB_CORE_MODULE *USBx, USB_EP *ep); +USB_STS USB_EP0StartXfer(USB_CORE_MODULE *USBx, USB_EP *ep); +USB_STS USB_EPSetStall(USB_CORE_MODULE *USBx, USB_EP *ep); +USB_STS USB_EPClearStall(USB_CORE_MODULE *USBx, USB_EP *ep); +uint32_t USB_ReadDevAllOutEp_itr(USB_CORE_MODULE *USBx); +uint32_t USB_ReadDevOutEP_itr(USB_CORE_MODULE *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEPItr(USB_CORE_MODULE *USBx); +uint32_t USB_ReadDevEachInEPItr(USB_CORE_MODULE *USBx); +uint32_t USB_ReadDevEachOutEPItr(USB_CORE_MODULE *USBx); +void USB_InitDevSpeed(USB_CORE_MODULE *USBx, uint8_t speed); +uint8_t USBH_IsEvenFrame(USB_CORE_MODULE *USBx); +void USB_EP0_OutStart(USB_CORE_MODULE *USBx); +void USB_ActiveRemoteWakeup(USB_CORE_MODULE *USBx); +void USB_UngateClock(USB_CORE_MODULE *USBx); +void USB_StopDevice(USB_CORE_MODULE *USBx); +void USB_SetEPStatus(USB_CORE_MODULE *USBx, USB_EP *ep, uint32_t Status); +uint32_t USB_GetEPStatus(USB_CORE_MODULE *USBx ,USB_EP *ep); +#endif + +#endif /* __USBHS_CORE_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd.h new file mode 100644 index 0000000000..5e0529431a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd.h @@ -0,0 +1,100 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_dcd.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBHS_DEV_H__ +#define __USBHS_DEV_H__ + +#include "usbhs_core.h" + +#define USB_EP_CONTROL 0 +#define USB_EP_ISOC 1 +#define USB_EP_BULK 2 +#define USB_EP_INT 3 +#define USB_EP_MASK 3 + +/* Device Status */ +#define USB_DEFAULT 1 +#define USB_ADDRESSED 2 +#define USB_CONFIGURED 3 +#define USB_SUSPENDED 4 + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +}EP_DESCRIPTOR; + +void USBDEV_CoreInit(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID); + +void USBDEV_DevConnect(USB_CORE_MODULE *USBx); +void USBDEV_DevDisconnect(USB_CORE_MODULE *USBx); + +void USBDEV_EP_SetAddress(USB_CORE_MODULE *USBx, uint8_t address); +uint32_t USBDEV_EP_Open(USB_CORE_MODULE *USBx , uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +uint32_t USBDEV_EP_Close(USB_CORE_MODULE *USBx, uint8_t ep_addr); +uint32_t USBDEV_EP_PrepareRx(USB_CORE_MODULE *USBx, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +uint32_t USBDEV_EP_Tx (USB_CORE_MODULE *USBx, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); +uint32_t USBDEV_EP_Stall (USB_CORE_MODULE *USBx, uint8_t epnum); +uint32_t USBDEV_EP_ClrStall (USB_CORE_MODULE *USBx, uint8_t epnum); +uint32_t USBDEV_EP_Flush(USB_CORE_MODULE *USBx, uint8_t epnum); + +uint32_t USBDEV_Handle_ISTR(USB_CORE_MODULE *USBx); +uint32_t USBDEV_GetEPStatus(USB_CORE_MODULE *USBx, uint8_t epnum); + +void USBDEV_SetEPStatus(USB_CORE_MODULE *USBx , uint8_t epnum , uint32_t Status); + +#endif /* __USBHS_DEV_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd_int.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd_int.h new file mode 100644 index 0000000000..d3f4d76aea --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_dcd_int.h @@ -0,0 +1,84 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_dcd_int.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBHS_DEV_INT_H__ +#define __USBHS_DEV_INT_H__ + + +#include "usbhs_dcd.h" + +typedef struct _USBD_DEV_INT +{ + uint8_t (* DataOutStage) (USB_CORE_MODULE *USBx , uint8_t epnum); + uint8_t (* DataInStage) (USB_CORE_MODULE *USBx , uint8_t epnum); + uint8_t (* SetupStage) (USB_CORE_MODULE *USBx); + uint8_t (* SOF) (USB_CORE_MODULE *USBx); + uint8_t (* Reset) (USB_CORE_MODULE *USBx); + uint8_t (* Suspend) (USB_CORE_MODULE *USBx); + uint8_t (* Resume) (USB_CORE_MODULE *USBx); + uint8_t (* IsoINIncomplete) (USB_CORE_MODULE *USBx); + uint8_t (* IsoOUTIncomplete) (USB_CORE_MODULE *USBx); + + uint8_t (* DevConnected) (USB_CORE_MODULE *USBx); + uint8_t (* DevDisconnected) (USB_CORE_MODULE *USBx); + +}USBD_DEV_INT_cb_TypeDef; + +extern USBD_DEV_INT_cb_TypeDef *USBD_DEV_INT_fops; + +uint32_t USBD_ISTR_Handler(USB_CORE_MODULE *USBx); +void USBD_ISTR_WKUP_handler(USB_CORE_MODULE *USBx); +void USBD_EP_OUT_ISTR_Handler(USB_CORE_MODULE *USBx); +void USBD_EP_IN_ISTR_Handler(USB_CORE_MODULE *USBx); + +#endif /* __USBHS_DEV_INT_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_defines.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_defines.h new file mode 100644 index 0000000000..abee0df2ae --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_defines.h @@ -0,0 +1,174 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_defines.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBHS_DEF_H__ +#define __USBHS_DEF_H__ + +#include "usbhs_conf.h" + + +#define USB_SPEED_PARAM_HIGH 0 +#define USB_SPEED_PARAM_HIGH_IN_FULL 1 + +#define USB_EMBEDDED_PHY 1 + +#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +#define GAHBCFG_GLBINT_ENABLE 1 +#define GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define GAHBCFG_INT_DMA_BURST_INCR 1 +#define GAHBCFG_INT_DMA_BURST_INCR4 3 +#define GAHBCFG_INT_DMA_BURST_INCR8 5 +#define GAHBCFG_INT_DMA_BURST_INCR16 7 +#define GAHBCFG_DMAENABLE 1 +#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +#define GRXSTS_PKTSTS_IN 2 +#define GRXSTS_PKTSTS_IN_XFER_COMP 3 +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 +#define GRXSTS_PKTSTS_CH_HALTED 7 + + +#define A_HOST 1 +#define A_SUSPEND 2 +#define A_PERIPHERAL 3 +#define B_PERIPHERAL 4 +#define B_HOST 5 +#define DEVICE_MODE 0 +#define HOST_MODE 1 +#define OTG_MODE 2 + +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 + +#define DCFG_FRAME_INTERVAL_80 0 +#define DCFG_FRAME_INTERVAL_85 1 +#define DCFG_FRAME_INTERVAL_90 2 +#define DCFG_FRAME_INTERVAL_95 3 + +#define DEP0CTRL_MPS_64 0 +#define DEP0CTRL_MPS_32 1 +#define DEP0CTRL_MPS_16 2 +#define DEP0CTRL_MPS_8 3 + +#define EP_SPEED_LOW 0 +#define EP_SPEED_FULL 1 +#define EP_SPEED_HIGH 2 + +#define EP_TYPE_CTRL 0 +#define EP_TYPE_ISOC 1 +#define EP_TYPE_BULK 2 +#define EP_TYPE_INTR 3 +#define EP_TYPE_MSK 3 + +#define STS_GOUT_NAK 1 +#define STS_DATA_UPDT 2 +#define STS_XFER_COMP 3 +#define STS_SETUP_COMP 4 +#define STS_SETUP_UPDT 6 + +#define HCH_PID_DATA0 0 +#define HCH_PID_DATA2 1 +#define HCH_PID_DATA1 2 +#define HCH_PID_SETUP 3 + +#define HPCS_PRTSPD_HIGH_SPEED 0 +#define HPCS_PRTSPD_FULL_SPEED 1 +#define HPCS_PRTSPD_LOW_SPEED 2 + +#define HCFG_30_60_MHZ 0 +#define HCFG_48_MHZ 1 +#define HCFG_6_MHZ 2 + +#define HCHCTRL_CTRL 0 +#define HCHCTRL_ISOC 1 +#define HCHCTRL_BULK 2 +#define HCHCTRL_INTR 3 + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) + +typedef enum +{ + USBHS1_CORE_ID = 0, + USBHS2_CORE_ID = 1 +}USB_CORE_ID_TypeDef; + +typedef enum +{ + USB_ENUM_HS = 0, + USB_ENUM_FS = 1 +}USB_ENUM_CORE; + + +#define USB_READ_REG32(REG) (*(__IO uint32_t *)(REG)) +#define USB_WRITE_REG32(REG, VAL) (*(__IO uint32_t *)(REG) = (VAL)) +#define USB_MODIFY_REG32(REG, clear_mask, set_mask) USB_WRITE_REG32((REG), (((USB_READ_REG32(REG)) & ~(clear_mask)) | (set_mask))) + +#define USB_SET_REG32_BIT(REG, BIT) ((*(__IO uint32_t *)(REG)) |= ((uint32_t)(BIT))) +#define USB_READ_REG32_BIT(REG, BIT) ((*(__IO uint32_t *)(REG)) &= ((uint32_t)(BIT))) +#define USB_CLR_REG32_BIT(REG, BIT) ((*(__IO uint32_t *)(REG)) &= ((uint32_t)(~((uint32_t)(BIT))))) + +#define USB_CLR_REG32(REG) (*(__IO uint32_t *)(REG) = ((uint32_t)(0UL))) + +/** ENUMERATION TYPE **/ +enum USB_SPEED +{ + USB_SPEED_UNKNOWN = 0, + USB_SPEED_LOW, + USB_SPEED_FULL, + USB_SPEED_HIGH +}; + +#endif /* __USB_DEFINES__H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd.h new file mode 100644 index 0000000000..65d5620f6e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd.h @@ -0,0 +1,75 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_hcd.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBHS_HCD__H__ +#define __USBHS_HCD__H__ + +#include "usbhs_regs.h" +#include "usbhs_core.h" + +void USBHOST_CoreInit(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID); +uint32_t HOST_HC_Init(USB_CORE_MODULE *USBx , uint8_t ch_num); +uint32_t HOST_SubmitRequest(USB_CORE_MODULE *USBx , uint8_t ch_num) ; +uint32_t HOST_GetCurrentSpeed(USB_CORE_MODULE *USBx); +uint32_t HOST_ResetPort(USB_CORE_MODULE *USBx); +uint32_t HOST_IsDeviceConnected(USB_CORE_MODULE *USBx); +uint32_t HOST_IsPortEnabled(USB_CORE_MODULE *USBx); + +uint32_t HOST_GetCurrentFrame(USB_CORE_MODULE *USBx) ; +URB_STATE HOST_GetURB_State(USB_CORE_MODULE *USBx, uint8_t ch_num); +uint32_t HOST_GetXferCnt(USB_CORE_MODULE *USBx, uint8_t ch_num); +HCH_STATUS HOST_GetHCState(USB_CORE_MODULE *USBx, uint8_t ch_num) ; + +#endif //__USBHS_HCD__H__ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd_int.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd_int.h new file mode 100644 index 0000000000..a6e434bc9f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_hcd_int.h @@ -0,0 +1,78 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_hcd_int.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBHS_HOST_INT_H__ +#define __USBHS_HOST_INT_H__ + +#include "usbhs_hcd.h" + +typedef struct +{ + uint8_t (* SOF)(USB_CORE_MODULE *USBx); + uint8_t (* DevConnected)(USB_CORE_MODULE *USBx); + uint8_t (* DevDisconnected)(USB_CORE_MODULE *USBx); + uint8_t (* DevPortEnabled)(USB_CORE_MODULE *USBx); + uint8_t (* DevPortDisabled)(USB_CORE_MODULE *USBx); +}USBHOST_INT_cb_TypeDef; + +extern USBHOST_INT_cb_TypeDef *USBHOST_INT_fops; + +/* Callbacks handler */ +void ConnectCallback_Handler(USB_CORE_MODULE *USBx); +void Disconnect_Callback_Handler(USB_CORE_MODULE *USBx); +void Overcurrent_Callback_Handler(USB_CORE_MODULE *USBx); +uint32_t USBHOST_ISTR_Handler (USB_CORE_MODULE *USBx); +void USBHOST_ISTR_WKUP_handler(USB_CORE_MODULE *USBx); + + +#endif //__USBHS_HOST_INT_H__ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_regs.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_regs.h new file mode 100644 index 0000000000..ddfbb70673 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/inc/usbhs_regs.h @@ -0,0 +1,107 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_regs.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBHS_REGS_H__ +#define __USBHS_REGS_H__ + +#include "n32h76x_78x.h" +#include "usbhs_conf.h" + + +#define USBHS1_BASE_ADDR (0x40100000) +#define USBHS1_WARP_BASE_ADDR (0x40140000) +#define USBHS2_BASE_ADDR (0x40060000) +#define USBHS2_WARP_BASE_ADDR (0x400A0000) + +#define USB_GLOBAL_REGS_OFFSET (0x000) +#define USB_DEV_GLOBAL_REG_OFFSET (0x800) +#define USB_DEV_IN_EP_REG_OFFSET (0x900) +#define USB_EP_REG_OFFSET (0x20) +#define USB_DEV_OUT_EP_REG_OFFSET (0xB00) +#define USB_HOST_GLOBAL_REG_OFFSET (0x400) +#define USB_HOST_PORT_REGS_OFFSET (0x440) +#define USB_HOST_CHANNEL_REGS_OFFSET (0x500) +#define USB_CHANNEL_REGS_OFFSET (0x20) +#define USB_PWRCTRL_OFFSET (0xE00) +#define USB_PWRCTRL1_OFFSET (0xE04) +#define USB_DATA_FIFO_OFFSET (0x1000) +#define USB_DATA_FIFO_SIZE (0x1000) + +#define USB_MAX_TX_FIFOS (16U) +#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS) +#define USB_MAX_EP_NUM (16U) +#define USB_MAX_EP0_SIZE (64U) + +#define USB_HS_MAX_PACKET_SIZE (1024U) +#define USB_FS_MAX_PACKET_SIZE (64U) +#define USB_MAX_CHANNEL_NUM (16U) /* USBHS host channel count */ +#define USB_MAX_FIFO_WORDLEN (1280U) /* USBHS max fifo size in words */ + + +typedef struct +{ + USB_Global_Registers *GCSR; + USB_Device_Registers *DCSR; + USB_Host_Registers *HCSR; + USB_INEP_Registers *INEPCSR[USB_MAX_EP_NUM]; + USB_OUTEP_Registers *OUTEPCSR[USB_MAX_EP_NUM]; + USB_HostCH_Registers *HCHCSR[USB_MAX_CH_NUM]; + __IO uint32_t *HPCS; + __IO uint32_t *DFIFO[USB_MAX_TX_FIFOS]; + __IO uint32_t *PWRCTRL; + __IO uint32_t *PWRCTRL1; + + USB_Wrapper_Registers *WRAPCSR; +}USB_Register; + +#endif /* __USBHS_REGS_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_core.c new file mode 100644 index 0000000000..d3eabfb457 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_core.c @@ -0,0 +1,2063 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbhs_core.h" +#include "usbhs_bsp.h" +#include "n32h76x_78x_rcc.h" +#include "usbhs_dcd.h" +#include "usbhs_defines.h" + +/** +*\*\name USB_EnableCommonInt. +*\*\fun Initializes the commmon interrupts, used in both device and modes. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +static void USB_EnableCommonInt(USB_CORE_MODULE *USBx) +{ + /* Clear any pending interrupts */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, 0xFFFFFFFFU); + /* Enable the interrupts in the INTEN */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTEN, (USBHS_GINTEN_WKUPIEN | USBHS_GINTEN_USBSUSPIEN)); +} + +/** +*\*\name USB_CoreReset. +*\*\fun Soft reset of the core. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +static USB_STS USB_CoreReset(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + uint32_t u32grstctrl; + uint32_t count = 0; + + /* Wait for AHB master IDLE state. */ + do + { + USB_BSP_uDelay(3); + u32grstctrl = USB_READ_REG32(&USBx->regs.GCSR->GRSTCTRL); + if (++count > 200000UL) + { + return USB_OK; + } + }while((u32grstctrl & USBHS_GRSTCTRL_AHBIDLE) == 0); + + if(status == USB_OK) + { + /* Core Soft Reset */ + count = 0; + u32grstctrl |= USBHS_GRSTCTRL_CSRST; + USB_WRITE_REG32(&USBx->regs.GCSR->GRSTCTRL, u32grstctrl); + do + { + u32grstctrl = USB_READ_REG32(&USBx->regs.GCSR->GRSTCTRL); + if (++count > 200000UL) + { + break; + } + } while ((u32grstctrl & USBHS_GRSTCTRL_SRSTDNE) == 0); + /* clear CSRST bit*/ + u32grstctrl &= (~USBHS_GRSTCTRL_CSRST); + USB_WRITE_REG32(&USBx->regs.GCSR->GRSTCTRL, u32grstctrl); + + USB_BSP_uDelay(3); + } + return status; +} + + +/** +*\*\name USB_WritePacket. +*\*\fun Writes a packet into the Tx FIFO associated with the EP. +*\*\param USBx: selected device. +*\*\param src : source pointer. +*\*\param ch_ep_num : end point number. +*\*\param len : length of bytes. +*\*\return status. +*\*\ +**/ +USB_STS USB_WritePacket(USB_CORE_MODULE *USBx, uint8_t *src,uint8_t ch_ep_num, uint16_t len) +{ + USB_STS status = USB_OK; + uint32_t u32Count32b = 0, i = 0; + __IO uint32_t *fifo; + + if(USBx->cfg.dma_enable == 0) + { + u32Count32b = (len + 3) / 4; + fifo = USBx->regs.DFIFO[ch_ep_num]; + for (i=0; iregs.DFIFO[0]; + u32Count32b = (len + 3) / 4; + + for(i=0; icfg.dma_enable = 0; + + /* Configure startup the core is in FS mode */ + USBx->cfg.speed = USB_SPEED_FULL; + USBx->cfg.mps = USB_FS_MAX_PACKET_SIZE; + /* initialize device cfg following its address */ + USBx->cfg.dev_endpoints_num = USB_MAX_EP_NUM; + USBx->cfg.host_channels_num = USB_MAX_CHANNEL_NUM; + USBx->cfg.TotalFifoSize = USB_MAX_FIFO_WORDLEN; + +#ifdef USB_INTERNAL_DMA_ENABLED + USBx->cfg.dma_enable = 1; +#endif + + USBx->regs.GCSR = (USB_Global_Registers *)(baseAddress + USB_GLOBAL_REGS_OFFSET); + USBx->regs.DCSR = (USB_Device_Registers *)(baseAddress + USB_DEV_GLOBAL_REG_OFFSET); + USBx->regs.HCSR = (USB_Host_Registers *)(baseAddress + USB_HOST_GLOBAL_REG_OFFSET); + USBx->regs.HPCS = (uint32_t *)(baseAddress + USB_HOST_PORT_REGS_OFFSET); + USBx->regs.PWRCTRL = (uint32_t *)(baseAddress + USB_PWRCTRL_OFFSET); + USBx->regs.PWRCTRL1 = (uint32_t *)(baseAddress + USB_PWRCTRL1_OFFSET); + + USBx->regs.WRAPCSR = (USB_Wrapper_Registers *)(wrapperAddress); + + for (i = 0; i < USBx->cfg.dev_endpoints_num; i++) + { + USBx->regs.INEPCSR[i] = (USB_INEP_Registers *) (baseAddress + USB_DEV_IN_EP_REG_OFFSET + (i * USB_EP_REG_OFFSET)); + USBx->regs.OUTEPCSR[i] = (USB_OUTEP_Registers *)(baseAddress + USB_DEV_OUT_EP_REG_OFFSET + (i * USB_EP_REG_OFFSET)); + } + for (i = 0; i < USBx->cfg.host_channels_num; i++) + { + USBx->regs.HCHCSR[i] = (USB_HostCH_Registers *)(baseAddress + USB_HOST_CHANNEL_REGS_OFFSET + (i * USB_CHANNEL_REGS_OFFSET)); + } + for (i = 0; i < USBx->cfg.host_channels_num; i++) + { + USBx->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + temp = USBx->regs.WRAPCSR->WRPCFG; + /* Select PHY clock source */ + temp &= ~USBHS_WRPCFG_PHYCLKSEL; + temp |= USBHS_PHYCLKSel(); + /* Enable PHY PLL */ + temp |= USBHS_WRPCFG_PLLEN; + +#ifdef USE_HOST_MODE + /* Set ID internal signal */ + temp &= ~USBHS_WRPCFG_IDSIG; +#endif + + USBx->regs.WRAPCSR->WRPCFG = temp; + + temp = USBx->regs.WRAPCSR->WRPCTRL; + temp |= USBHS_WRPCTRL_PINDETEN; + USBx->regs.WRAPCSR->WRPCTRL = temp; + + return status; +} + +/** +*\*\name USB_CoreInit. +*\*\fun Initializes the USBHS controller registers and prepares the core device mode or host mode operation. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_CoreInit(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + + /* HS Interface */ + USB_MODIFY_REG32(&USBx->regs.GCSR->GCFG, USBHS_GCFG_PHYSEL, 0); + + /* set phy 8bit */ + USB_MODIFY_REG32(&USBx->regs.GCSR->GCFG, USBHS_GCFG_PHYIF, USBHS_GCFG_PHYIF); + + /* Reset after a PHY select and set Host mode */ + USB_CoreReset(USBx); + + USB_BSP_mDelay(20); + + /* case the HS core is working in FS mode */ + if(USBx->cfg.dma_enable == 1) + { + USB_MODIFY_REG32(&USBx->regs.GCSR->GAHBCFG, USBHS_GAHBCFG_BURSTTYP, 5 << USBHS_GAHBCFG_BURSTTYP_POS); + USB_MODIFY_REG32(&USBx->regs.GCSR->GAHBCFG, 0, USBHS_GAHBCFG_DMAEN); + } + return status; +} + +/** +*\*\name USB_EnableGlobalInt. +*\*\fun Enables or Disables the usb Global Int. +*\*\param USBx: selected device. +*\*\param Cmd : ENABLE or DISABLE +*\*\return status. +*\*\ +**/ +USB_STS USB_EnableGlobalInt(USB_CORE_MODULE *USBx, FunctionalState Cmd) +{ + USB_STS status = USB_OK; + if (Cmd != DISABLE) + { + /* Enable interrupts */ + USB_MODIFY_REG32(&USBx->regs.GCSR->GAHBCFG, 0, USBHS_GAHBCFG_GINTEN); + } + else + { + /* Disable interrupts */ + USB_MODIFY_REG32(&USBx->regs.GCSR->GAHBCFG, USBHS_GAHBCFG_GINTEN, 0); + } + return status; +} + +/** +*\*\name USB_FlushTxFifo. +*\*\fun Flush a Tx FIFO. +*\*\param USBx: selected device. +*\*\param num : FIFO num. +*\*\return status. +*\*\ +**/ +USB_STS USB_FlushTxFifo(USB_CORE_MODULE *USBx , uint32_t num) +{ + USB_STS status = USB_OK; + uint32_t grstctrl = 0; + uint32_t count = 0; + + do + { + grstctrl = USB_READ_REG32(&USBx->regs.GCSR->GRSTCTRL); + if (++count > 200000) + { + break; + } + }while ((grstctrl & USBHS_GRSTCTRL_AHBIDLE) == 0); + + count = 0; + grstctrl = 0; + grstctrl |= USBHS_GRSTCTRL_TXFFLSH; + grstctrl |= ((num & 0x1FU) << USBHS_GRSTCTRL_TXFNUM_POS); + USB_WRITE_REG32(&USBx->regs.GCSR->GRSTCTRL, grstctrl); + do + { + grstctrl = USB_READ_REG32(&USBx->regs.GCSR->GRSTCTRL); + if (++count > 200000) + { + break; + } + }while ((grstctrl & USBHS_GRSTCTRL_TXFFLSH) != 0); + return status; +} + +/** +*\*\name USB_FlushRxFifo. +*\*\fun Flush a Rx FIFO. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_FlushRxFifo(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + uint32_t grstctrl = 0; + uint32_t count = 0; + + do + { + grstctrl = USB_READ_REG32(&USBx->regs.GCSR->GRSTCTRL); + if (++count > 200000) + { + break; + } + }while ((grstctrl & USBHS_GRSTCTRL_AHBIDLE) == 0); + + count = 0; + + USB_WRITE_REG32(&USBx->regs.GCSR->GRSTCTRL, USBHS_GRSTCTRL_RXFFLSH); + + do + { + grstctrl = USB_READ_REG32(&USBx->regs.GCSR->GRSTCTRL); + if(++count > 200000) + { + break; + } + }while ((grstctrl & USBHS_GRSTCTRL_RXFFLSH) != 0); + return status; +} + + +/** +*\*\name USB_SetCurrentMode. +*\*\fun Set ID line. +*\*\param USBx: selected device. +*\*\param mode: (Host/device). +*\*\return status. +*\*\ +**/ +USB_STS USB_SetCurrentMode(USB_CORE_MODULE *USBx , uint8_t mode) +{ + USB_STS status = USB_OK; + + if(mode == HOST_MODE) + { + USB_MODIFY_REG32(&USBx->regs.GCSR->GCFG, USBHS_GCFG_FHMODE | USBHS_GCFG_FDMODE, USBHS_GCFG_FHMODE); + } + else + { + USB_MODIFY_REG32(&USBx->regs.GCSR->GCFG, USBHS_GCFG_FHMODE | USBHS_GCFG_FDMODE, USBHS_GCFG_FDMODE); + } + USB_BSP_mDelay(50); + return status; +} + + +/** +*\*\name USB_GetMode. +*\*\fun Get current mode. +*\*\param USBx: selected device. +*\*\return current mode. +*\*\ +**/ +uint32_t USB_GetMode(USB_CORE_MODULE *USBx) +{ + return (USB_READ_REG32(&USBx->regs.GCSR->GINTSTS) & 0x1); +} + +/** +*\*\name USB_IsDeviceMode. +*\*\fun Check if it is device mode. +*\*\param USBx: selected device. +*\*\return 1 or 0. +*\*\ +**/ +uint8_t USB_IsDeviceMode(USB_CORE_MODULE *USBx) +{ + if(USB_GetMode(USBx) != HOST_MODE) + { + return 1; + } + else + { + return 0; + } +} + +/** +*\*\name USB_IsHostMode. +*\*\fun Check if it is host mode. +*\*\param USBx: selected device. +*\*\return 1 or 0. +*\*\ +**/ +uint8_t USB_IsHostMode(USB_CORE_MODULE *USBx) +{ + if(USB_GetMode(USBx) != HOST_MODE) + { + return 0; + } + else + { + return 1; + } +} + +/** +*\*\name USB_ReadCoreItr. +*\*\fun returns the Core Interrupt register. +*\*\param USBx: selected device. +*\*\return v. +*\*\ +**/ +uint32_t USB_ReadCoreItr(USB_CORE_MODULE *USBx) +{ + uint32_t v; + v = USB_READ_REG32(&USBx->regs.GCSR->GINTSTS); + v &= USB_READ_REG32(&USBx->regs.GCSR->GINTEN); + return v; +} + +#ifdef USE_HOST_MODE +/** +*\*\name USB_CoreInitHost. +*\*\fun Initializes USBHS controller for host mode. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_CoreInitHost(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + + uint32_t i = 0; + + /* configure charge pump IO */ + USB_BSP_ConfigVBUS(USBx); + + /* Restart the Phy Clock */ + USB_WRITE_REG32(USBx->regs.PWRCTRL, 0); + + USB_ResetPort(USBx); + + USB_CLR_REG32_BIT(&USBx->regs.HCSR->HCFG, USBHS_HCFG_SPSEL); + + /* Configure data FIFO sizes */ + /* set Rx FIFO size */ + USB_WRITE_REG32(&USBx->regs.GCSR->GRXFSIZ, RX_FIFO_HS_SIZE); + USB_WRITE_REG32(&USBx->regs.GCSR->GNPTXFSIZ_DINEP0TXFSIZ, ( RX_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS | TXH_NP_HS_FIFOSIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + USB_WRITE_REG32(&USBx->regs.GCSR->HPTXFSIZ, ((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZE) << USBHS_HPTXFSIZ_HPTXFSADD_POS | TXH_P_HS_FIFOSIZE << USBHS_HPTXFSIZ_HPTXFDEP_POS)); + + /* Make sure the FIFOs are flushed. */ + USB_FlushTxFifo(USBx, 0x10); /* all Tx FIFOs */ + USB_FlushRxFifo(USBx); + + /* Clear all pending HC Interrupts */ + for (i = 0; i < USBx->cfg.host_channels_num; i++) + { + USB_WRITE_REG32(&USBx->regs.HCHCSR[i]->HCHINTSTS, 0xFFFFFFFF); + USB_WRITE_REG32(&USBx->regs.HCHCSR[i]->HCHINTEN, 0); + } + + USB_DriveVbus(USBx, 1); + + USB_EnableHostInt(USBx); + return status; +} + +/** +*\*\name USB_IsEvenFrame. +*\*\fun This function returns the frame number for sof packet. +*\*\param USBx: selected device. +*\*\return Frame number. +*\*\ +**/ +uint8_t USB_IsEvenFrame(USB_CORE_MODULE *USBx) +{ + return !(USB_READ_REG32(&USBx->regs.HCSR->HFNUM) & 0x1); +} + +/** +*\*\name USB_DriveVbus. +*\*\fun set/reset vbus. +*\*\param USBx: selected device. +*\*\param state : VBUS state +*\*\return none. +*\*\ +**/ +void USB_DriveVbus(USB_CORE_MODULE *USBx, uint8_t state) +{ + uint32_t hpcs = 0; + + /* enable disable the external charge pump */ + USB_BSP_DriveVBUS(USBx, state); + + /* Turn on the Host port power. */ + hpcs = USB_ReadHPCS(USBx); + if(((hpcs & USBHS_HPCS_PPWR) == 0) && (state == 1)) + { + hpcs |= USBHS_HPCS_PPWR; + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); + } + if(((hpcs & USBHS_HPCS_PPWR) != 0) && (state == 0)) + { + hpcs &= (~USBHS_HPCS_PPWR); + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); + } + USB_BSP_mDelay(200); +} + +/** +*\*\name USB_EnableHostInt. +*\*\fun Enables the Host mode interrupts. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EnableHostInt(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + uint32_t ginten = 0; + + /* Disable all interrupts. */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTEN, 0); + + /* Clear any pending interrupts. */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, 0xFFFFFFFF); + + /* Enable the common interrupts */ + USB_EnableCommonInt(USBx); + + if(USBx->cfg.dma_enable == 0) + { + USB_SET_REG32_BIT(&USBx->regs.GCSR->GINTEN, USBHS_GINTEN_RXFNEIEN); + } + ginten |= (USBHS_GINTEN_PTNCIEN_ISOUTNCIEN + | USBHS_GINTEN_HCHIEN + | USBHS_GINTEN_HPIEN + | USBHS_GINTEN_DISCIEN + | USBHS_GINTEN_SOFIEN); + USB_SET_REG32_BIT(&USBx->regs.GCSR->GINTEN, ginten); + + return status; +} + +/** +*\*\name USB_InitFSLSPClkSel. +*\*\fun Initializes the FSLSPClkSel field of the HCFG register on the PHY type. +*\*\param USBx: selected device. +*\*\param freq : clock frequency. +*\*\return none. +*\*\ +**/ +void USB_InitFSLSPClkSel(USB_CORE_MODULE *USBx , uint8_t freq) +{ + uint32_t hcfg = 0; + + hcfg = USB_READ_REG32(&USBx->regs.HCSR->HCFG); + hcfg &= (~(uint32_t)0x03); + hcfg |= freq; + + USB_WRITE_REG32(&USBx->regs.HCSR->HCFG, hcfg); +} + +/** +*\*\name USB_ReadHPCS. +*\*\fun Reads HPCS to modify later. +*\*\param USBx: selected device. +*\*\return HPCS value. +*\*\ +**/ +uint32_t USB_ReadHPCS(USB_CORE_MODULE *USBx) +{ + uint32_t hpcs; + hpcs = USB_READ_REG32(USBx->regs.HPCS); + hpcs &= ~(USBHS_HPCS_PEN | USBHS_HPCS_PCDET | USBHS_HPCS_PENC | USBHS_HPCS_POCC); + return hpcs; +} + +/** +*\*\name USB_ReadHostAllChannels_intr. +*\*\fun Register PCD Callbacks. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint32_t USB_ReadHostAllChannels_intr(USB_CORE_MODULE *USBx) +{ + return (USB_READ_REG32(&USBx->regs.HCSR->HACHINT)); +} + +/** +*\*\name USB_ResetPort. +*\*\fun Reset Host Port. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint32_t USB_ResetPort(USB_CORE_MODULE *USBx) +{ + uint32_t hpcs = 0; + + hpcs = USB_ReadHPCS(USBx); + hpcs |= USBHS_HPCS_PRST; + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); + USB_BSP_mDelay(100); + hpcs &= (~USBHS_HPCS_PRST); + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); + USB_BSP_mDelay(20); + return 1; +} + +/** +*\*\name USB_HCH_Init. +*\*\fun Prepares a host channel for transferring packets. +*\*\param USBx: selected device. +*\*\param hch_num: channel number. +*\*\return status. +*\*\ +**/ +USB_STS USB_HCH_Init(USB_CORE_MODULE *USBx , uint8_t hch_num) +{ + USB_STS status = USB_OK; + uint32_t intr_enable = 0; + uint32_t hchinten = 0; + uint32_t hchctrl = 0; + + /* Clear old interrupt conditions for this host channel. */ + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHINTSTS, 0xFFFFFFFF); + + /* Enable channel interrupts required for this transfer. */ + + if (USBx->cfg.dma_enable == 1) + { + hchinten |= USBHS_HCHINTEN_AHBERRIEN; + } + + switch (USBx->host.hch[hch_num].ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + hchinten |= USBHS_HCHINTEN_TXCIEN; + hchinten |= USBHS_HCHINTEN_STALLIEN; + hchinten |= USBHS_HCHINTEN_TXERRIEN; + hchinten |= USBHS_HCHINTEN_DTERRIEN; + hchinten |= USBHS_HCHINTEN_NAKIEN; + + if (USBx->host.hch[hch_num].ep_is_in) + { + hchinten |= USBHS_HCHINTEN_BBERRIEN; + } + else + { + hchinten |= USBHS_HCHINTEN_NYETIEN; + if (USBx->host.hch[hch_num].do_ping) + { + hchinten |= USBHS_HCHINTEN_ACKIEN; + } + } + break; + case EP_TYPE_INTR: + hchinten |= USBHS_HCHINTEN_TXCIEN; + hchinten |= USBHS_HCHINTEN_NAKIEN; + hchinten |= USBHS_HCHINTEN_STALLIEN; + hchinten |= USBHS_HCHINTEN_TXERRIEN; + hchinten |= USBHS_HCHINTEN_DTERRIEN; + hchinten |= USBHS_HCHINTEN_FOVRIEN; + + if (USBx->host.hch[hch_num].ep_is_in) + { + hchinten |= USBHS_HCHINTEN_BBERRIEN; + } + + break; + case EP_TYPE_ISOC: + hchinten |= USBHS_HCHINTEN_TXCIEN; + hchinten |= USBHS_HCHINTEN_FOVRIEN; + hchinten |= USBHS_HCHINTEN_ACKIEN; + + if (USBx->host.hch[hch_num].ep_is_in) + { + hchinten |= USBHS_HCHINTEN_TXERRIEN; + hchinten |= USBHS_HCHINTEN_BBERRIEN; + } + break; + } + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHINTEN, hchinten); + + /* Enable the top level host channel interrupt. */ + intr_enable = (1 << hch_num); + USB_MODIFY_REG32(&USBx->regs.HCSR->HACHINTEN, 0, intr_enable); + + /* Make sure host channel interrupts are enabled. */ + USB_SET_REG32_BIT(&USBx->regs.GCSR->GINTEN, USBHS_GINTEN_HCHIEN); + + /* Program the HCHCTRL register */ + hchctrl |= ((uint32_t)(USBx->host.hch[hch_num].dev_addr) << USBHS_HCHCTRL_DEVADDR_POS); + hchctrl |= ((uint32_t)(USBx->host.hch[hch_num].ep_num) << USBHS_HCHCTRL_EPNUM_POS); + hchctrl |= ((uint32_t)(USBx->host.hch[hch_num].ep_is_in) << USBHS_HCHCTRL_EPDIR_POS); + hchctrl |= ((uint32_t)(USBx->host.hch[hch_num].ep_type) << USBHS_HCHCTRL_EPTYPE_POS); + hchctrl |= ((uint32_t)(USBx->host.hch[hch_num].max_packet) << USBHS_HCHCTRL_MPS_POS); + if(USBx->host.hch[hch_num].speed == HPCS_PRTSPD_LOW_SPEED) + { + hchctrl |= USBHS_HCHCTRL_LSPDDEV; + } + if (USBx->host.hch[hch_num].ep_type == HCHCTRL_INTR) + { + hchctrl |= USBHS_HCHCTRL_ODDFRM; + } + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL, hchctrl); + return status; +} + + +/** +*\*\name USB_HCH_StartXfer. +*\*\fun Start transfer. +*\*\param USBx: selected device. +*\*\param hch_num: channel number. +*\*\return status. +*\*\ +**/ +USB_STS USB_HCH_StartXfer(USB_CORE_MODULE *USBx , uint8_t hch_num) +{ + USB_STS status = USB_OK; + + uint16_t len_words = 0; + uint16_t num_packets = 0; + uint16_t max_hch_pkt_count = 0; + + uint32_t hchtxsiz = 0; + uint32_t hchctrl = 0; + uint32_t gnptxfsts = 0; + uint32_t hptxfqsts = 0; + + max_hch_pkt_count = 256; + + + /* Compute the expected number of packets associated to the transfer */ + if(USBx->host.hch[hch_num].xfer_len > 0) + { + num_packets = (USBx->host.hch[hch_num].xfer_len + USBx->host.hch[hch_num].max_packet - 1) / USBx->host.hch[hch_num].max_packet; + + if(num_packets > max_hch_pkt_count) + { + num_packets = max_hch_pkt_count; + USBx->host.hch[hch_num].xfer_len = num_packets * USBx->host.hch[hch_num].max_packet; + } + } + else + { + num_packets = 1; + } + if(USBx->host.hch[hch_num].ep_is_in) + { + USBx->host.hch[hch_num].xfer_len = num_packets * USBx->host.hch[hch_num].max_packet; + } + /* Initialize the HCHTXSIZn register */ + hchtxsiz |= ((uint32_t)(USBx->host.hch[hch_num].xfer_len) << USBHS_HCHTXSIZ_TXSIZ_POS); + hchtxsiz |= ((uint32_t)(num_packets) << USBHS_HCHTXSIZ_PKCNT_POS); + hchtxsiz |= ((uint32_t)(USBx->host.hch[hch_num].data_pid) << USBHS_HCHTXSIZ_PID_POS); + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHTXSIZ, hchtxsiz); + + if(USBx->cfg.dma_enable == 1) + { + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHDMADD, (unsigned int)USBx->host.hch[hch_num].xfer_buff); + } + + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL); + hchctrl &= (~USBHS_HCHCTRL_ODDFRM); + hchctrl |= (USB_IsEvenFrame(USBx) << USBHS_HCHCTRL_ODDFRM_POS); + + /* Set host channel enable */ + hchctrl |= USBHS_HCHCTRL_CHEN; + hchctrl &= (~USBHS_HCHCTRL_CHDIS); + + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL, hchctrl); + + if (USBx->cfg.dma_enable == 0) /* Slave mode */ + { + if((USBx->host.hch[hch_num].ep_is_in == 0) && + (USBx->host.hch[hch_num].xfer_len > 0)) + { + switch(USBx->host.hch[hch_num].ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + gnptxfsts = USB_READ_REG32(&USBx->regs.GCSR->GNPTXFSTS); + len_words = (USBx->host.hch[hch_num].xfer_len + 3) / 4; + + /* check if there is enough space in FIFO space */ + if(len_words > (gnptxfsts & USBHS_GNPTXFSTS_NPTXFSAV) >> USBHS_GNPTXFSTS_NPTXFSAV_POS) + { + /* need to process data in nptxfempty interrupt */ + USB_SET_REG32_BIT(&USBx->regs.GCSR->GINTEN, USBHS_GINTEN_NPTXFEIEN); + } + break; + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + hptxfqsts = USB_READ_REG32(&USBx->regs.HCSR->HPTXFQSTS); + len_words = (USBx->host.hch[hch_num].xfer_len + 3) / 4; + /* check if there is enough space in FIFO space */ + if(len_words > (hptxfqsts & USBHS_HPTXFQSTS_PTXFSAVL) >> USBHS_HPTXFQSTS_PTXFSAVL_POS) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USB_SET_REG32_BIT(&USBx->regs.GCSR->GINTEN, USBHS_GINTEN_PTXFEIEN); + } + break; + + default: + break; + } + /* Write packet into the Tx FIFO. */ + USB_WritePacket(USBx, USBx->host.hch[hch_num].xfer_buff, hch_num, USBx->host.hch[hch_num].xfer_len); + } + } + return status; +} + + + +/** +*\*\name USB_HCH_Halt. +*\*\fun Halt channel. +*\*\param USBx: selected device. +*\*\param hch_num: channel number. +*\*\return status. +*\*\ +**/ +USB_STS USB_HCH_Halt(USB_CORE_MODULE *USBx , uint8_t hch_num) +{ + USB_STS status = USB_OK; + + uint32_t gnptxfsts = 0; + uint32_t hptxfqsts = 0; + uint32_t hchctrl = 0; + + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL); + + hchctrl |= USBHS_HCHCTRL_CHDIS; + + /* Check for space in the request queue to issue the halt. */ + if(((hchctrl & USBHS_HCHCTRL_EPTYPE) >> USBHS_HCHCTRL_EPTYPE_POS) == HCHCTRL_CTRL + || ((hchctrl & USBHS_HCHCTRL_EPTYPE) >> USBHS_HCHCTRL_EPTYPE_POS) == HCHCTRL_BULK) + { + gnptxfsts = USB_READ_REG32(&USBx->regs.GCSR->GNPTXFSTS); + if(((gnptxfsts & USBHS_GNPTXFSTS_NPTXRQSAV) >> USBHS_GNPTXFSTS_NPTXRQSAV_POS) == 0) + { + hchctrl &= (~USBHS_HCHCTRL_CHEN); + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL, hchctrl); + } + } + else + { + hptxfqsts = USB_READ_REG32(&USBx->regs.HCSR->HPTXFQSTS); + if(((hptxfqsts & USBHS_HPTXFQSTS_PTXRQSAV) >> USBHS_HPTXFQSTS_PTXRQSAV_POS) == 0) + { + hchctrl &= (~USBHS_HCHCTRL_CHEN); + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL, hchctrl); + } + } + hchctrl |= USBHS_HCHCTRL_CHEN; + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL, hchctrl); + return status; +} + + +/** +*\*\name USB_HCH_DoPing. +*\*\fun Issue a ping token. +*\*\param USBx: selected device. +*\*\param hch_num: channel number. +*\*\return status. +*\*\ +**/ +USB_STS USB_HCH_DoPing(USB_CORE_MODULE *USBx , uint8_t hch_num) +{ + USB_STS status = USB_OK; + uint32_t hchctrl = 0; + uint32_t hchtxsiz = 0; + + hchtxsiz |= USBHS_HCHCTRL_DPING; + hchtxsiz |= 1 << USBHS_HCHTXSIZ_PKCNT_POS; + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHTXSIZ, hchtxsiz); + + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL); + hchctrl |= USBHS_HCHCTRL_CHEN; + hchctrl &= (~USBHS_HCHCTRL_CHDIS); + USB_WRITE_REG32(&USBx->regs.HCHCSR[hch_num]->HCHCTRL, hchctrl); + return status; +} + +/** +*\*\name USB_StopHost. +*\*\fun Stop the device and clean up fifo's. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_StopHost(USB_CORE_MODULE *USBx) +{ + uint32_t i = 0; + uint32_t hchctrl = 0; + + USB_WRITE_REG32(&USBx->regs.HCSR->HACHINTEN, 0); + USB_WRITE_REG32(&USBx->regs.HCSR->HACHINT, 0xFFFFFFFF); + /* Flush out any leftover queued requests. */ + for (i = 0; i < USBx->cfg.host_channels_num; i++) + { + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[i]->HCHCTRL); + hchctrl &= (~USBHS_HCHCTRL_CHEN); + hchctrl |= USBHS_HCHCTRL_CHDIS; + hchctrl &= (~USBHS_HCHCTRL_EPDIR); + USB_WRITE_REG32(&USBx->regs.HCHCSR[i]->HCHCTRL, hchctrl); + } + /* Flush the FIFO */ + USB_FlushRxFifo(USBx); + USB_FlushTxFifo(USBx, 0x10); +} +#endif +#ifdef USE_DEVICE_MODE + +/** +*\*\name USB_InitDevSpeed. +*\*\fun Initializes the DevSpd field of DCFG register depending the PHY type and the enumeration speed of the device. +*\*\param USBx: selected device. +*\*\param speed: device speed. +*\*\return none. +*\*\ +**/ +void USB_InitDevSpeed(USB_CORE_MODULE *USBx , uint8_t speed) +{ + uint32_t dcfg = 0; + + dcfg = USB_READ_REG32(&USBx->regs.DCSR->DCFG); + dcfg &= (~USBHS_DCFG_DEVSPD); + dcfg |= speed; + USB_WRITE_REG32(&USBx->regs.DCSR->DCFG, dcfg); +} + + +/** +*\*\name USB_DevHSFifoConfig. +*\*\fun Initializes device fifo. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +static void USB_DevHSFifoConfig(USB_CORE_MODULE *USBx) +{ + uint32_t StardAddr = RX_FIFO_HS_SIZE; + /* set Rx FIFO size */ + USB_WRITE_REG32(&USBx->regs.GCSR->GRXFSIZ, RX_FIFO_HS_SIZE); + + /* EP0 TX*/ + USB_WRITE_REG32(&USBx->regs.GCSR->GNPTXFSIZ_DINEP0TXFSIZ, + (RX_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX0_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP1 TX*/ + StardAddr += TX0_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[0], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX1_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP2 TX*/ + StardAddr += TX1_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[1], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX2_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP3 TX*/ + StardAddr += TX2_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[2], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX3_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP4 TX*/ + StardAddr += TX3_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[3], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX4_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP5 TX*/ + StardAddr += TX4_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[4], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX5_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP6 TX*/ + StardAddr += TX5_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[5], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX6_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP7 TX*/ + StardAddr += TX6_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[6], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX7_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); + + /* EP8 TX*/ + StardAddr += TX7_FIFO_HS_SIZE; + USB_WRITE_REG32(&USBx->regs.GCSR->DINEPPTXFSIZ[7], + (StardAddr << USBHS_DINEP0TXSIZ_IEP0TXFRSADD_POS) | (TX8_FIFO_HS_SIZE << USBHS_DINEP0TXSIZ_NPTXFDEP_POS)); +} + + +/** +*\*\name USB_CoreInitDev. +*\*\fun Initializes the USBHS controller registers for device mode. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_CoreInitDev (USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + uint32_t i=0; + uint32_t dinepctrl; + uint32_t doutepctrl; + uint32_t dinepinten; + uint32_t dthrctrl; + + /* Restart the Phy Clock */ + USB_WRITE_REG32(USBx->regs.PWRCTRL, 0); + /* Device configuration register */ + USB_MODIFY_REG32(&USBx->regs.DCSR->DCFG, USBHS_DCFG_PFRITVL, DCFG_FRAME_INTERVAL_80 << USBHS_DCFG_PFRITVL_POS); + +#ifdef USE_USB_HS_IN_HS + /* Set High speed phy */ + USB_InitDevSpeed(USBx , USB_SPEED_PARAM_HIGH); +#else + /* set High speed phy in Full speed mode */ + USB_InitDevSpeed(USBx , USB_SPEED_PARAM_HIGH_IN_FULL); +#endif + + USB_DevHSFifoConfig(USBx); + + /* Flush the FIFOs */ + USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ + USB_FlushRxFifo(USBx); + /* Clear all pending Device Interrupts */ + USB_WRITE_REG32(&USBx->regs.DCSR->DINEPINTEN, 0U); + USB_WRITE_REG32(&USBx->regs.DCSR->DOUTEPINTEN, 0U); + USB_WRITE_REG32(&USBx->regs.DCSR->DAEPINTSTS, 0xFFFFFFFFU); + USB_WRITE_REG32(&USBx->regs.DCSR->DAEPINTEN, 0U); + + for(i=0; icfg.dev_endpoints_num; i++) + { + dinepctrl = USB_READ_REG32_BIT(&USBx->regs.INEPCSR[i]->DINEPCTRL, USBHS_DINEPCTRL_EPEN); + if(dinepctrl) + { + dinepctrl = 0; + dinepctrl |= (USBHS_DINEPCTRL_EPDIS | USBHS_DINEPCTRL_SNAK); + } + else + { + dinepctrl= 0; + } + USB_WRITE_REG32(&USBx->regs.INEPCSR[i]->DINEPCTRL, dinepctrl); + USB_WRITE_REG32(&USBx->regs.INEPCSR[i]->DINEPTXSIZ, 0U); + USB_WRITE_REG32(&USBx->regs.INEPCSR[i]->DINEPINTSTS, 0xFFU); + } + for(i=0; icfg.dev_endpoints_num; i++) + { + doutepctrl = USB_READ_REG32_BIT(&USBx->regs.OUTEPCSR[i]->DOUTEPCTRL, USBHS_DOUTEPCTRL_EPEN); + if(doutepctrl) + { + doutepctrl = 0; + doutepctrl |= (USBHS_DOUTEPCTRL_EPDIS | USBHS_DOUTEPCTRL_SNAK); + } + else + { + doutepctrl = 0; + } + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[i]->DOUTEPCTRL, doutepctrl); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[i]->DOUTEPTXSIZ, 0U); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[i]->DOUTEPINTSTS, 0xFFU); + } + dinepinten = 0; + dinepinten |= USBHS_DINEPINTEN_TXFUDIEN; + USB_MODIFY_REG32(&USBx->regs.DCSR->DINEPINTEN, dinepinten, dinepinten); + + if (USBx->cfg.dma_enable == 1) + { + dthrctrl = 0; + dthrctrl |= USBHS_DTHRCTRL_NISOINEPTHREN; + dthrctrl |= USBHS_DTHRCTRL_ISOINEPTHREN; + dthrctrl |= 64 << USBHS_DTHRCTRL_TXTHRLEN_POS; + dthrctrl |= USBHS_DTHRCTRL_RXTHREN; + dthrctrl |= 64 << USBHS_DTHRCTRL_RXTHRLEN_POS; + USB_WRITE_REG32(&USBx->regs.DCSR->DTHRCTRL, dthrctrl); + } + USBDEV_DevConnect(USBx); + USB_EnableDevInt(USBx); + return status; +} + +/** +*\*\name USB_EnableDevInt. +*\*\fun Enables the Device mode interrupts. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EnableDevInt(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + uint32_t ginten = 0; + + /* Disable all interrupts. */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTEN, 0U); + /* Clear any pending interrupts */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, 0xBFFFFFFFU); + /* Enable the common interrupts */ + USB_EnableCommonInt(USBx); + + if (USBx->cfg.dma_enable == 0) + { + ginten |= USBHS_GINTEN_RXFNEIEN; + } +#ifdef USB_DEDICATED_EP_ENABLED + /* Enable interrupts matching to the Device mode ONLY */ + ginten |= USBHS_GINTEN_USBSUSPIEN | USBHS_GINTEN_USBRSTIEN | USBHS_GINTEN_ENUMDIEN + | USBHS_GINTEN_SOFIEN + | USBHS_GINTEN_ISOINCIEN | USBHS_GINTEN_PTNCIEN_ISOUTNCIEN; +#else + /* Enable interrupts matching to the Device mode ONLY */ + ginten |= USBHS_GINTEN_USBSUSPIEN | USBHS_GINTEN_USBRSTIEN | USBHS_GINTEN_ENUMDIEN + | USBHS_GINTEN_INEPIEN | USBHS_GINTEN_OUTEPIEN | USBHS_GINTEN_SOFIEN + | USBHS_GINTEN_ISOINCIEN | USBHS_GINTEN_PTNCIEN_ISOUTNCIEN; +#endif + + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, ginten, ginten); + return status; +} + + + +/** +*\*\name USB_GetDeviceSpeed. +*\*\fun Get the device speed from the device status register. +*\*\param USBx: selected device. +*\*\return speed. +*\*\ +**/ +enum USB_SPEED USB_GetDeviceSpeed (USB_CORE_MODULE *USBx) +{ + enum USB_SPEED speed = USB_SPEED_UNKNOWN; + uint32_t dsts = 0; + + dsts = USB_READ_REG32(&USBx->regs.DCSR->DSTS); + + switch ((dsts & USBHS_DSTS_ENUMSPD) >> USBHS_DSTS_ENUMSPD_POS) + { + case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + speed = USB_SPEED_HIGH; + break; + case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + speed = USB_SPEED_FULL; + break; + case DSTS_ENUMSPD_LS_PHY_6MHZ: + speed = USB_SPEED_LOW; + break; + + default: + speed = USB_SPEED_FULL; + break; + } + return speed; +} + +/** +*\*\name USB_EP0Activate. +*\*\fun enables EP0 OUT to receive SETUP packets and configures EP0 for transmitting packets. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EP0Activate(USB_CORE_MODULE *USBx) +{ + USB_STS status = USB_OK; + uint32_t dsts; + uint32_t dinepctrl; + + /* Read the Device Status and Endpoint 0 Control registers */ + dsts = USB_READ_REG32(&USBx->regs.DCSR->DSTS); + dinepctrl = USB_READ_REG32(&USBx->regs.INEPCSR[0]->DINEPCTRL); + dinepctrl &= (~USBHS_DINEP0CTRL_MPLEN); + /* Set the MPS of the IN EP based on the enumeration speed */ + switch ((dsts & USBHS_DSTS_ENUMSPD) >> USBHS_DSTS_ENUMSPD_POS) + { + case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + dinepctrl |= (DEP0CTRL_MPS_64 << USBHS_DINEP0CTRL_MPLEN_POS); + break; + case DSTS_ENUMSPD_LS_PHY_6MHZ: + dinepctrl |= (DEP0CTRL_MPS_8 << USBHS_DINEP0CTRL_MPLEN_POS); + break; + + default: + dinepctrl |= (DEP0CTRL_MPS_64 << USBHS_DINEP0CTRL_MPLEN_POS); + break; + } + USB_WRITE_REG32(&USBx->regs.INEPCSR[0]->DINEPCTRL, dinepctrl); + USB_MODIFY_REG32(&USBx->regs.DCSR->DCTRL, USBHS_DCTRL_CGNPINAK, USBHS_DCTRL_CGNPINAK); + return status; +} + + +/** +*\*\name USB_EPActivate. +*\*\fun Activates an EP. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EPActivate(USB_CORE_MODULE *USBx, USB_EP *ep) +{ + USB_STS status = USB_OK; + __IO uint32_t *addr; + + uint32_t depctrl; + uint32_t depinten; + + /* Read DEPCTRLn register */ + if (ep->is_in == 1) + { + addr = &USBx->regs.INEPCSR[ep->num]->DINEPCTRL; + depinten = (1 << ep->num) << USBHS_DEEPINTEN_INEPIEN_POS; + } + else + { + addr = &USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL; + depinten = (1 << ep->num) << USBHS_DEEPINTEN_OUTEPIEN_POS; + } + /* If the EP is already active don't change the EP Control + * register. */ + depctrl = USB_READ_REG32(addr); + if (!(depctrl & USBHS_DINEPCTRL_EPACT)) + { + depctrl |= ep->maxpacket << USBHS_DINEPCTRL_MPLEN_POS; + depctrl |= ep->type << USBHS_DINEPCTRL_EPTYPE_POS; + depctrl |= ep->tx_fifo_num << USBHS_DINEPCTRL_TXFNUM_POS; + depctrl |= USBHS_DINEPCTRL_SD0PID_SEVNFRM; + depctrl |= USBHS_DINEPCTRL_EPACT; + + USB_WRITE_REG32(addr, depctrl); + } +#ifdef USB_DEDICATED_EP_ENABLED + USB_SET_REG32_BIT(&USBx->regs.DCSR->DEEPINTEN, depinten); +#else + /* Enable the Interrupt for this EP */ + USB_SET_REG32_BIT(&USBx->regs.DCSR->DAEPINTEN, depinten); +#endif + return status; +} + + +/** +*\*\name USB_EPDeactivate. +*\*\fun Deactivates an EP. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EPDeactivate(USB_CORE_MODULE *USBx , USB_EP *ep) +{ + USB_STS status = USB_OK; + uint32_t depctrl = 0; + + /* Read DEPCTRLn register and Disable the IN endpoint*/ + if(ep->is_in == 1) + { + depctrl = USB_READ_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPCTRL); + if(depctrl & USBHS_DINEPCTRL_EPEN) + { + depctrl = 0; + depctrl |= USBHS_DINEPCTRL_EPDIS; + depctrl |= USBHS_DINEPCTRL_SNAK; + } + else + { + depctrl = 0; + } + USB_WRITE_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPCTRL, depctrl); + } + else /* Disable the OUT endpoint */ + { + depctrl = USB_READ_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL); + if(depctrl & USBHS_DOUTEPCTRL_EPEN) + { + depctrl = 0; + depctrl |= USBHS_DOUTEPCTRL_EPDIS; + depctrl |= USBHS_DOUTEPCTRL_SNAK; + } + else + { + depctrl = 0; + } + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL, depctrl); + } + return status; +} + + +/** +*\*\name USB_EPStartXfer. +*\*\fun Handle the setup for data xfer for an EP and starts the xfer. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EPStartXfer(USB_CORE_MODULE *USBx, USB_EP *ep) +{ + USB_STS status = USB_OK; + uint32_t fifoemptymsk = 0; + uint32_t dinepctrl, doutepctrl; + uint32_t dineptxsiz, douteptxsiz; + uint32_t dsts = 0; + + /* IN endpoint */ + if(ep->is_in == 1) + { + dinepctrl = USB_READ_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPCTRL); + dineptxsiz = USB_READ_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPTXSIZ); + /* Zero Length Packet */ + if (ep->xfer_len == 0) + { + dineptxsiz = 1 << USBHS_DINEPTXSIZ_PKTCNT_POS; + dineptxsiz |= 1 << USBHS_DINEPTXSIZ_MCNT_POS; + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + dineptxsiz &= (~USBHS_DINEPTXSIZ_TLEN) ; + dineptxsiz |= ep->xfer_len << USBHS_DINEPTXSIZ_TLEN_POS; + dineptxsiz &= (~USBHS_DINEPTXSIZ_PKTCNT) ; + dineptxsiz |= ((ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket) << USBHS_DINEPTXSIZ_PKTCNT_POS; + if (ep->type == EP_TYPE_ISOC) + { + dineptxsiz &= (~USBHS_DINEPTXSIZ_MCNT) ; + dineptxsiz |= 1 << USBHS_DINEPTXSIZ_MCNT_POS; + } + else if (ep->type == EP_TYPE_INTR) + { + dineptxsiz &= (~USBHS_DINEPTXSIZ_MCNT) ; + if(((ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket) <=3) + { + dineptxsiz |= ((ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket) << USBHS_DINEPTXSIZ_MCNT_POS; + } + } + } + USB_WRITE_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPTXSIZ, dineptxsiz); + + if (USBx->cfg.dma_enable == 1) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPDMADD, ep->dma_addr); + } + else + { + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) + { + fifoemptymsk = 1 << ep->num; + USB_SET_REG32_BIT(&USBx->regs.DCSR->DINEPFEINTEN, fifoemptymsk); + } + } + } + if (ep->type == EP_TYPE_ISOC) + { + dsts = USB_READ_REG32(&USBx->regs.DCSR->DSTS); + if ((((dsts & USBHS_DSTS_SOFFN)>>USBHS_DSTS_SOFFN_POS) & 0x1) == 0) + { + dinepctrl |= USBHS_DINEPCTRL_SD1PID_SODDFRM; + } + else + { + dinepctrl |= USBHS_DINEPCTRL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + dinepctrl |= USBHS_DINEPCTRL_CNAK; + dinepctrl |= USBHS_DINEPCTRL_EPEN; + + USB_WRITE_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPCTRL, dinepctrl); + + if (ep->type == EP_TYPE_ISOC) + { + USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len); + } + } + else + { + /* OUT endpoint */ + doutepctrl = USB_READ_REG32((&USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL)); + douteptxsiz = USB_READ_REG32((&USBx->regs.OUTEPCSR[ep->num]->DOUTEPTXSIZ)); + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + if (ep->xfer_len == 0) + { + douteptxsiz &= (~USBHS_DOUTEPTXSIZ_TLEN); + douteptxsiz |= ep->maxpacket << USBHS_DOUTEPTXSIZ_TLEN_POS; + douteptxsiz &= (~USBHS_DOUTEPTXSIZ_PKTCNT); + douteptxsiz |= 1 << USBHS_DOUTEPTXSIZ_PKTCNT_POS; + } + else + { + douteptxsiz &= (~USBHS_DOUTEPTXSIZ_PKTCNT); + douteptxsiz |= ((ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket) << USBHS_DOUTEPTXSIZ_PKTCNT_POS; + douteptxsiz &= (~USBHS_DOUTEPTXSIZ_TLEN); + douteptxsiz |= (((douteptxsiz & USBHS_DOUTEPTXSIZ_PKTCNT) >> USBHS_DOUTEPTXSIZ_PKTCNT_POS) * ep->maxpacket); + ep->xfer_len = (((douteptxsiz & USBHS_DOUTEPTXSIZ_PKTCNT) >> USBHS_DOUTEPTXSIZ_PKTCNT_POS) * ep->maxpacket); + } + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPTXSIZ, douteptxsiz); + + if (USBx->cfg.dma_enable == 1) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPDMADD, ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if (ep->even_odd_frame) + { + doutepctrl |= USBHS_DOUTEPCTRL_SD1PID_SODDFRM; + } + else + { + doutepctrl |= USBHS_DOUTEPCTRL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + doutepctrl |= (USBHS_DOUTEPCTRL_CNAK | USBHS_DOUTEPCTRL_EPEN); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL, doutepctrl); + } + return status; +} + + +/** +*\*\name USB_EP0StartXfer. +*\*\fun Handle the setup for a data xfer for EP0 and starts the xfer. +*\*\param USBx: selected device. +*\*\return status. +*\*\ +**/ +USB_STS USB_EP0StartXfer(USB_CORE_MODULE *USBx , USB_EP *ep) +{ + USB_STS status = USB_OK; + USB_INEP_Registers *in_regs; + uint32_t fifoemptymsk = 0; + uint32_t dinepctrl = 0, doutepctrl = 0; + uint32_t dineptxsiz = 0, douteptxsiz = 0; + + /* IN endpoint */ + if(ep->is_in == 1) + { + in_regs = USBx->regs.INEPCSR[0]; + dinepctrl = USB_READ_REG32(&in_regs->DINEPCTRL); + dineptxsiz = USB_READ_REG32(&in_regs->DINEPTXSIZ); + /* Zero Length Packet */ + if(ep->xfer_len == 0) + { + dineptxsiz &= (~USBHS_DINEP0TXSIZ_TLEN); + dineptxsiz &= (~USBHS_DINEP0TXSIZ_PKTCNT); + dineptxsiz |= 1 << USBHS_DINEP0TXSIZ_PKTCNT_POS; + } + else + { + if(ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + dineptxsiz &= (~USBHS_DINEP0TXSIZ_TLEN); + dineptxsiz |= ep->maxpacket << USBHS_DINEP0TXSIZ_TLEN_POS; + } + else + { + dineptxsiz &= (~USBHS_DINEP0TXSIZ_TLEN); + dineptxsiz |= ep->xfer_len << USBHS_DINEP0TXSIZ_TLEN_POS; + } + dineptxsiz &= (~USBHS_DINEP0TXSIZ_PKTCNT); + dineptxsiz |= 1 << USBHS_DINEP0TXSIZ_PKTCNT_POS; + } + USB_WRITE_REG32(&in_regs->DINEPTXSIZ, dineptxsiz); + + if(USBx->cfg.dma_enable == 1) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[ep->num]->DINEPDMADD, ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + dinepctrl |= ( USBHS_DINEP0CTRL_CNAK | USBHS_DINEP0CTRL_EPEN); + USB_WRITE_REG32(&in_regs->DINEPCTRL, dinepctrl); + + if(USBx->cfg.dma_enable == 0) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) + { + { + fifoemptymsk |= 1 << ep->num; + USB_MODIFY_REG32(&USBx->regs.DCSR->DINEPFEINTEN, 0, fifoemptymsk); + } + } + } + } + else + { + /* OUT endpoint */ + doutepctrl = USB_READ_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL); + douteptxsiz = USB_READ_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPTXSIZ); + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if(ep->xfer_len == 0) + { + douteptxsiz &= (~USBHS_DOUTEP0TXSIZ_TLEN); + douteptxsiz |= ep->maxpacket << USBHS_DOUTEP0TXSIZ_TLEN_POS; + douteptxsiz &= (~USBHS_DOUTEP0TXSIZ_PKTCNT); + douteptxsiz |= 1 << USBHS_DOUTEP0TXSIZ_PKTCNT_POS; + } + else + { + ep->xfer_len = ep->maxpacket; + douteptxsiz &= (~USBHS_DOUTEP0TXSIZ_TLEN); + douteptxsiz |= ep->maxpacket << USBHS_DOUTEP0TXSIZ_TLEN_POS; + douteptxsiz &= (~USBHS_DOUTEP0TXSIZ_PKTCNT); + douteptxsiz |= 1 << USBHS_DOUTEP0TXSIZ_PKTCNT_POS; + } + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPTXSIZ, douteptxsiz); + if(USBx->cfg.dma_enable == 1) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPDMADD, ep->dma_addr); + } + /* EP enable */ + doutepctrl |= (USBHS_DOUTEP0CTRL_CNAK | USBHS_DOUTEP0CTRL_EPEN); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL, doutepctrl); + } + return status; +} + + + +/** +*\*\name USB_EPSetStall. +*\*\fun Set the EP STALL. +*\*\param USBx: selected device. +*\*\param ep: endpoint instance +*\*\return status. +*\*\ +**/ +USB_STS USB_EPSetStall(USB_CORE_MODULE *USBx , USB_EP *ep) +{ + USB_STS status = USB_OK; + __IO uint32_t *depctrl_addr; + uint32_t depctrl; + + if(ep->is_in == 1) + { + depctrl_addr = &(USBx->regs.INEPCSR[ep->num]->DINEPCTRL); + depctrl = USB_READ_REG32(depctrl_addr); + /* set the disable and stall bits */ + if (depctrl & USBHS_DINEPCTRL_EPEN) + { + depctrl |= USBHS_DINEPCTRL_EPDIS; + } + depctrl |= USBHS_DINEPCTRL_STALL; + USB_WRITE_REG32(depctrl_addr, depctrl); + } + else + { + depctrl_addr = &(USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL); + depctrl = USB_READ_REG32(depctrl_addr); + /* set the stall bit */ + depctrl |= USBHS_DOUTEPCTRL_STALL; + USB_WRITE_REG32(depctrl_addr, depctrl); + } + return status; +} + + +/** +*\*\name USB_EPClearStall. +*\*\fun Clear the EP STALL. +*\*\param USBx: selected device. +*\*\param ep: endpoint instance +*\*\return status. +*\*\ +**/ +USB_STS USB_EPClearStall(USB_CORE_MODULE *USBx , USB_EP *ep) +{ + USB_STS status = USB_OK; + __IO uint32_t *depctrl_addr; + uint32_t depctrl; + + + if (ep->is_in == 1) + { + depctrl_addr = &(USBx->regs.INEPCSR[ep->num]->DINEPCTRL); + } + else + { + depctrl_addr = &(USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL); + } + depctrl = USB_READ_REG32(depctrl_addr); + /* clear the stall bits */ + depctrl &= (~USBHS_DINEPCTRL_STALL); + if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) + { + depctrl |= USBHS_DINEPCTRL_SD0PID_SEVNFRM; /* DATA0 */ + } + USB_WRITE_REG32(depctrl_addr, depctrl); + return status; +} + +/** +*\*\name USB_ReadDevAllOutEp_itr. +*\*\fun returns OUT endpoint interrupt bits. +*\*\param USBx: selected device. +*\*\return OUT endpoint interrupt bits. +*\*\ +**/ +uint32_t USB_ReadDevAllOutEp_itr(USB_CORE_MODULE *USBx) +{ + uint32_t v; + v = USB_READ_REG32(&USBx->regs.DCSR->DAEPINTSTS); + v &= USB_READ_REG32(&USBx->regs.DCSR->DAEPINTEN); + return ((v & 0xffff0000) >> 16); +} + +/** +*\*\name USB_ReadDevOutEP_itr. +*\*\fun returns Device OUT EP Interrupt register. +*\*\param USBx: selected device. +*\*\param ep : end point number +*\*\return Device OUT EP Interrupt register. +*\*\ +**/ +uint32_t USB_ReadDevOutEP_itr(USB_CORE_MODULE *USBx , uint8_t epnum) +{ + uint32_t v; + v = USB_READ_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS); + v &= USB_READ_REG32(&USBx->regs.DCSR->DOUTEPINTEN); + return v; +} + +/** +*\*\name USB_ReadDevAllInEPItr. +*\*\fun Get int status register. +*\*\param USBx: selected device. +*\*\return int status register. +*\*\ +**/ +uint32_t USB_ReadDevAllInEPItr(USB_CORE_MODULE *USBx) +{ + uint32_t v; + v = USB_READ_REG32(&USBx->regs.DCSR->DAEPINTSTS); + v &= USB_READ_REG32(&USBx->regs.DCSR->DAEPINTEN); + return (v & 0xffff); +} + +/** +*\*\name USB_ReadDevEachInEPItr. +*\*\fun Get int status register. +*\*\param USBx: selected device. +*\*\return int status register. +**/ +uint32_t USB_ReadDevEachInEPItr(USB_CORE_MODULE *USBx) +{ + uint32_t v; + v = USB_READ_REG32(&USBx->regs.DCSR->DEEPINTSTS); + v = USB_READ_REG32(&USBx->regs.DCSR->DEEPINTEN); + return (v & 0xFFFF); +} + +/** +*\*\name USB_ReadDevEachOutEPItr. +*\*\fun Get int status register. +*\*\param USBx: selected device. +*\*\return int status register. +**/ +uint32_t USB_ReadDevEachOutEPItr(USB_CORE_MODULE *USBx) +{ + uint32_t v; + v = USB_READ_REG32(&USBx->regs.DCSR->DEEPINTSTS); + v = USB_READ_REG32(&USBx->regs.DCSR->DEEPINTEN); + return (v & 0xFFFF0000) >> 16; +} + +/** +*\*\name USB_EP0_OutStart. +*\*\fun configures EP0 to receive SETUP packets. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_EP0_OutStart(USB_CORE_MODULE *USBx) +{ + uint32_t douteptxsiz = 0; + uint32_t doutepctrl; + + douteptxsiz |= 3 << USBHS_DOUTEP0TXSIZ_STUPPCNT_POS; + douteptxsiz |= 1 << USBHS_DOUTEP0TXSIZ_PKTCNT_POS; + douteptxsiz |= 64 << USBHS_DOUTEP0TXSIZ_TLEN_POS; + + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[0]->DOUTEPTXSIZ, douteptxsiz); + + if(USBx->cfg.dma_enable == 1) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[0]->DOUTEPDMADD, (uint32_t)&USBx->dev.setup_packet); + + /* EP enable */ + doutepctrl = (USBHS_DOUTEP0CTRL_EPEN | USBHS_DOUTEP0CTRL_EPACT); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[0]->DOUTEPCTRL, doutepctrl); + } +} + + +/** +*\*\name USB_ActiveRemoteWakeup. +*\*\fun active remote wakeup signalling. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_ActiveRemoteWakeup(USB_CORE_MODULE *USBx) +{ + uint32_t dsts; + uint32_t pwrctrl; + + if(USBx->dev.DevRemoteWakeup) + { + dsts = USB_READ_REG32(&USBx->regs.DCSR->DSTS); + if(dsts & USBHS_DSTS_SUSPF) + { + if(USBx->cfg.low_power) + { + /* un-gate USB Core clock */ + pwrctrl = USB_READ_REG32(USBx->regs.PWRCTRL); + pwrctrl &= (~USBHS_PWRCTRL_GATEHCLK); + pwrctrl &= (~USBHS_PWRCTRL_PHYSTP); + USB_WRITE_REG32(USBx->regs.PWRCTRL, pwrctrl); + } + /* active Remote wakeup signaling */ + USB_SET_REG32_BIT(&USBx->regs.DCSR->DCTRL, USBHS_DCTRL_RMWKUP); + USB_BSP_mDelay(5); + USB_MODIFY_REG32(&USBx->regs.DCSR->DCTRL, USBHS_DCTRL_RMWKUP, 0); + } + } +} + + +/** +*\*\name USB_UngateClock. +*\*\fun active USB Core clock. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_UngateClock(USB_CORE_MODULE *USBx) +{ + uint32_t dsts; + uint32_t pwrctrl; + if(USBx->cfg.low_power) + { + dsts = USB_READ_REG32(&USBx->regs.DCSR->DSTS); + + if(dsts & USBHS_DSTS_SUSPF) + { + /* un-gate USB Core clock */ + pwrctrl = USB_READ_REG32(USBx->regs.PWRCTRL); + pwrctrl &= (~USBHS_PWRCTRL_GATEHCLK); + pwrctrl &= (~USBHS_PWRCTRL_PHYSTP); + USB_WRITE_REG32(USBx->regs.PWRCTRL, pwrctrl); + } + } +} + + +/** +*\*\name USB_StopDevice. +*\*\fun Stop the device and clean up fifo's. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_StopDevice(USB_CORE_MODULE *USBx) +{ + uint32_t i; + + USBx->dev.device_status = 1; + + for (i = 0; i < USBx->cfg.dev_endpoints_num ; i++) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[i]->DINEPINTSTS, 0xFF); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[i]->DOUTEPINTSTS, 0xFF); + } + + USB_WRITE_REG32(&USBx->regs.DCSR->DINEPINTEN, 0); + USB_WRITE_REG32(&USBx->regs.DCSR->DOUTEPINTEN, 0); + USB_WRITE_REG32(&USBx->regs.DCSR->DAEPINTEN, 0); + USB_WRITE_REG32(&USBx->regs.DCSR->DAEPINTSTS, 0xFFFFFFFF ); + + /* Flush the FIFO */ + USB_FlushRxFifo(USBx); + USB_FlushTxFifo(USBx, 0x10); +} + + +/** +*\*\name USB_GetEPStatus. +*\*\fun returns the EP Status. +*\*\param USBx: selected device. +*\*\param ep: endpoint instance. +*\*\return EP status. +*\*\ +**/ +uint32_t USB_GetEPStatus(USB_CORE_MODULE *USBx, USB_EP *ep) +{ + __IO uint32_t *depctrl_addr; + uint32_t Status = 0; + uint32_t depctrl = 0; + + if(ep->is_in == 1) + { + depctrl_addr = &(USBx->regs.INEPCSR[ep->num]->DINEPCTRL); + depctrl = USB_READ_REG32(depctrl_addr); + + if((depctrl & USBHS_DINEPCTRL_STALL) >> USBHS_DINEPCTRL_STALL_POS) + { + Status = USB_EP_TX_STALL; + } + else if((depctrl & USBHS_DINEPCTRL_NAKSTS) >> USBHS_DINEPCTRL_NAKSTS_POS) + { + Status = USB_EP_TX_NAK; + } + else + { + Status = USB_EP_TX_VALID; + } + } + else + { + depctrl_addr = &(USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL); + depctrl = USB_READ_REG32(depctrl_addr); + if((depctrl & USBHS_DOUTEPCTRL_STALL) >> USBHS_DOUTEPCTRL_STALL_POS) + { + Status = USB_EP_RX_STALL; + } + else if((depctrl & USBHS_DOUTEPCTRL_NAKSTS) >> USBHS_DOUTEPCTRL_NAKSTS_POS) + { + Status = USB_EP_RX_NAK; + } + else + { + Status = USB_EP_RX_VALID; + } + } + /* Return the current status */ + return Status; +} + + +/** +*\*\name USB_SetEPStatus. +*\*\fun Set the EP Status. +*\*\param USBx: selected device. +*\*\param ep: endpoint instance. +*\*\param Status : new Status +*\*\return none. +*\*\ +**/ +void USB_SetEPStatus(USB_CORE_MODULE *USBx, USB_EP *ep, uint32_t Status) +{ + __IO uint32_t *depctrl_addr; + uint32_t depctrl = 0; + + /* Process for IN endpoint */ + if(ep->is_in == 1) + { + depctrl_addr = &(USBx->regs.INEPCSR[ep->num]->DINEPCTRL); + depctrl = USB_READ_REG32(depctrl_addr); + + if(Status == USB_EP_TX_STALL) + { + USB_EPSetStall(USBx, ep); + return; + } + else if(Status == USB_EP_TX_NAK) + { + depctrl |= USBHS_DINEPCTRL_SNAK; + } + else if(Status == USB_EP_TX_VALID) + { + if ((depctrl & USBHS_DINEPCTRL_STALL) >> USBHS_DINEPCTRL_STALL_POS) + { + ep->even_odd_frame = 0; + USB_EPClearStall(USBx, ep); + return; + } + depctrl |= USBHS_DINEPCTRL_CNAK; + depctrl |= USBHS_DINEPCTRL_EPACT; + depctrl |= USBHS_DINEPCTRL_EPEN; + } + else if (Status == USB_EP_TX_DIS) + { + depctrl &= (~USBHS_DINEPCTRL_EPACT); + } + else + { + /* Do Nothing */ + } + } + else /* Process for OUT endpoint */ + { + depctrl_addr = &(USBx->regs.OUTEPCSR[ep->num]->DOUTEPCTRL); + depctrl = USB_READ_REG32(depctrl_addr); + + if(Status == USB_EP_RX_STALL) + { + depctrl |= USBHS_DOUTEPCTRL_STALL; + } + else if (Status == USB_EP_RX_NAK) + { + depctrl |= USBHS_DOUTEPCTRL_SNAK; + } + else if(Status == USB_EP_RX_VALID) + { + if((depctrl & USBHS_DOUTEPCTRL_STALL) >> USBHS_DOUTEPCTRL_STALL_POS) + { + ep->even_odd_frame = 0; + USB_EPClearStall(USBx, ep); + return; + } + depctrl |= USBHS_DOUTEPCTRL_CNAK; + depctrl |= USBHS_DOUTEPCTRL_EPACT; + depctrl |= USBHS_DOUTEPCTRL_EPEN; + } + else if (Status == USB_EP_RX_DIS) + { + depctrl &= (~USBHS_DOUTEPCTRL_EPACT); + } + else + { + /* Do Nothing */ + } + } + USB_WRITE_REG32(depctrl_addr, depctrl); +} + +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd.c new file mode 100644 index 0000000000..296a6ba7a9 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd.c @@ -0,0 +1,434 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_dcd.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbhs_dcd.h" +#include "usbhs_bsp.h" + + +/** +*\*\name USBDEV_CoreInit. +*\*\fun Initialize the device core. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USBDEV_CoreInit(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID) +{ + uint32_t i; + USB_EP *ep; + + USB_BasicInit(USBx, coreID); + + USBx->dev.device_status = USB_DEFAULT; + USBx->dev.device_address = 0; + + /* Init ep structure */ + for(i=0; icfg.dev_endpoints_num; i++) + { + ep = &USBx->dev.in_ep[i]; + /* Init ep structure */ + ep->is_in = 1; + ep->num = i; + ep->tx_fifo_num = i; + /* Control until ep is activated */ + ep->type = EP_TYPE_CTRL; + ep->maxpacket = USB_MAX_EP0_SIZE; + ep->xfer_buff = 0; + ep->xfer_len = 0; + } + for(i = 0; icfg.dev_endpoints_num; i++) + { + ep = &USBx->dev.out_ep[i]; + /* Init ep structure */ + ep->is_in = 0; + ep->num = i; + ep->tx_fifo_num = i; + /* Control until ep is activated */ + ep->type = EP_TYPE_CTRL; + ep->maxpacket = USB_MAX_EP0_SIZE; + ep->xfer_buff = 0; + ep->xfer_len = 0; + } + + USB_EnableGlobalInt(USBx, DISABLE); + + /*Init the Core (common init.) */ + USB_CoreInit(USBx); + + /* Force Device Mode*/ + USB_SetCurrentMode(USBx, DEVICE_MODE); + + /* Init Device */ + USB_CoreInitDev(USBx); + + /* Enable USB Global interrupt */ + USB_EnableGlobalInt(USBx, ENABLE); +} + +/** +*\*\name USBDEV_EP_Open. +*\*\fun Configure an EP. +*\*\param USBx: selected device. +*\*\param ep_addr : Endpoint address. +*\*\param ep_mps: Endpoint max packet size. +*\*\param ep_type: Endpoint type. +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_Open(USB_CORE_MODULE *USBx , uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + USB_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = ep_addr>>7; //EP type, it is IN(=1) or OUT(=0) + tmp_2 = ep_addr & 0x7f; //EP number + + if(tmp_1 == 1) + { + ep = &USBx->dev.in_ep[tmp_2]; + } + else + { + ep = &USBx->dev.out_ep[tmp_2]; + } + ep->num = tmp_2; + + ep->is_in = tmp_1; + ep->maxpacket = ep_mps; + ep->type = ep_type; + if(ep->is_in) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = tmp_2; + } + /* Set initial data PID. */ + if(ep_type == USB_EP_BULK ) + { + ep->data_pid_start = 0; + } + USB_EPActivate(USBx , ep); + return 0; +} + +/** +*\*\name USBDEV_EP_Close. +*\*\fun Called when an EP is disabled. +*\*\param USBx: selected device. +*\*\param ep_addr : Endpoint address. +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_Close(USB_CORE_MODULE *USBx , uint8_t ep_addr) +{ + USB_EP *ep; + + if((ep_addr&0x80) == 0x80) + { + ep = &USBx->dev.in_ep[ep_addr & 0x7F]; + } + else + { + ep = &USBx->dev.out_ep[ep_addr & 0x7F]; + } + ep->num = ep_addr & 0x7F; + ep->is_in = (0x80 & ep_addr) != 0; + USB_EPDeactivate(USBx , ep); + return 0; +} + +/** +*\*\name USBDEV_EP_PrepareRx. +*\*\fun Enable endpoint receive. +*\*\param USBx: selected device. +*\*\param ep_addr : Endpoint address. +*\*\param pbuf: pointer to Rx buffer +*\*\param buf_len: data length +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_PrepareRx( USB_CORE_MODULE *USBx, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + USB_EP *ep; + __IO uint8_t tmp_1; + + tmp_1 = ep_addr & 0x7f; //EP number + + ep = &USBx->dev.out_ep[tmp_1]; + + /*setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = buf_len; + ep->xfer_count = 0; + ep->is_in = 0; + ep->num = tmp_1; + + if(USBx->cfg.dma_enable == 1) + { + ep->dma_addr = (uint32_t)pbuf; + } + if(tmp_1 == 0) + { + USB_EP0StartXfer(USBx , ep); + } + else + { + USB_EPStartXfer(USBx, ep); + } + return 0; +} + +/** +*\*\name USBDEV_EP_Tx. +*\*\fun Transmit data over USB. +*\*\param USBx: selected device. +*\*\param ep_addr : Endpoint address. +*\*\param pbuf: pointer to Tx buffer +*\*\param buf_len: data length +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_Tx (USB_CORE_MODULE *USBx, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) +{ + USB_EP *ep; + + ep = &USBx->dev.in_ep[ep_addr & 0x7F]; + + /* Setup and start the Transfer */ + ep->is_in = 1; + ep->num = ep_addr & 0x7F; + ep->xfer_buff = pbuf; + ep->xfer_count = 0; + ep->xfer_len = buf_len; + + if(USBx->cfg.dma_enable == 1) + { + ep->dma_addr = (uint32_t)pbuf; + } + if(ep->num == 0) + { + USB_EP0StartXfer(USBx, ep); + } + else + { + USB_EPStartXfer(USBx, ep); + } + return 0; +} + +/** +*\*\name USBDEV_EP_Stall. +*\*\fun Stall an endpoint. +*\*\param USBx: selected device. +*\*\param epnum: endpoint number +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_Stall (USB_CORE_MODULE *USBx, uint8_t epnum) +{ + USB_EP *ep; + if((0x80 & epnum) == 0x80) + { + ep = &USBx->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &USBx->dev.out_ep[epnum]; + } + + ep->is_stall = 1; + ep->num = epnum & 0x7F; + ep->is_in = ((epnum & 0x80) == 0x80); + + USB_EPSetStall(USBx , ep); + return (0); +} + +/** +*\*\name USBDEV_EP_ClrStall. +*\*\fun Clear stall condition on endpoints. +*\*\param USBx: selected device. +*\*\param epnum: endpoint number +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_ClrStall(USB_CORE_MODULE *USBx, uint8_t epnum) +{ + USB_EP *ep; + if((0x80 & epnum) == 0x80) + { + ep = &USBx->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &USBx->dev.out_ep[epnum]; + } + + ep->is_stall = 0; + ep->num = epnum & 0x7F; + ep->is_in = ((epnum & 0x80) == 0x80); + + USB_EPClearStall(USBx , ep); + return (0); +} + +/** +*\*\name USBDEV_EP_Flush. +*\*\fun This Function flushes the FIFOs. +*\*\param USBx: selected device. +*\*\param epnum: endpoint number +*\*\return status. +*\*\ +**/ +uint32_t USBDEV_EP_Flush(USB_CORE_MODULE *USBx , uint8_t epnum) +{ + if((epnum & 0x80) == 0x80) + { + USB_FlushTxFifo(USBx, epnum & 0x7F); + } + else + { + USB_FlushRxFifo(USBx); + } + return (0); +} + +/** +*\*\name USBDEV_EP_SetAddress. +*\*\fun This Function set USB device address. +*\*\param USBx: selected device. +*\*\param address: new device address +*\*\return status. +*\*\ +**/ +void USBDEV_EP_SetAddress(USB_CORE_MODULE *USBx, uint8_t address) +{ + uint32_t dcfg = 0; + dcfg |= (address << USBHS_DCFG_DEVARR_POS); + USB_MODIFY_REG32(&USBx->regs.DCSR->DCFG, USBHS_DCFG_DEVARR, dcfg); +} + +/** +*\*\name USBDEV_DevConnect. +*\*\fun Connect device (enable internal pull-up) +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USBDEV_DevConnect(USB_CORE_MODULE *USBx) +{ + USB_CLR_REG32_BIT(&USBx->regs.DCSR->DCTRL, USBHS_DCTRL_SFTDIS); +} + +/** +*\*\name USBDEV_DevDisconnect. +*\*\fun Disconnect device (disable internal pull-up) +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USBDEV_DevDisconnect(USB_CORE_MODULE *USBx) +{ + /* Disconnect device for 3ms */ + USB_MODIFY_REG32(&USBx->regs.DCSR->DCTRL, 0, USBHS_DCTRL_SFTDIS); + USB_BSP_mDelay(3); +} + +/** +*\*\name USBDEV_GetEPStatus. +*\*\fun returns the EP Status. +*\*\param USBx: selected device. +*\*\param epnum : endpoint number +*\*\return EP status. +*\*\ +**/ +uint32_t USBDEV_GetEPStatus(USB_CORE_MODULE *USBx ,uint8_t epnum) +{ + USB_EP *ep; + uint32_t Status = 0; + + if((0x80 & epnum) == 0x80) + { + ep = &USBx->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &USBx->dev.out_ep[epnum]; + } + Status = USB_GetEPStatus(USBx ,ep); + /* Return the current status */ + return Status; +} + +/** +*\*\name USBDEV_SetEPStatus. +*\*\fun Set the EP Status. +*\*\param USBx: selected device. +*\*\param epnum : endpoint number. +*\*\param Status : new Status. +*\*\return none. +*\*\ +**/ +void USBDEV_SetEPStatus(USB_CORE_MODULE *USBx , uint8_t epnum , uint32_t Status) +{ + USB_EP *ep; + + if((0x80 & epnum) == 0x80) + { + ep = &USBx->dev.in_ep[epnum & 0x7F]; + } + else + { + ep = &USBx->dev.out_ep[epnum]; + } + USB_SetEPStatus(USBx , ep , Status); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd_int.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd_int.c new file mode 100644 index 0000000000..d2d8feed42 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_dcd_int.c @@ -0,0 +1,1002 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_dcd_int.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbhs_dcd_int.h" +#include "usbhs_regs.h" +#include "n32h76x_78x_rcc.h" +#include "n32h76x_78x_pwr.h" + +/* static functions */ +static uint32_t USBDEV_ReadDevInEP(USB_CORE_MODULE *USBx, uint8_t epnum); + +/* Interrupt Handlers */ +static uint32_t USBDEV_HandleInEP_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_HandleOutEP_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_HandleSof_ISTR(USB_CORE_MODULE *USBx); + +static uint32_t USBDEV_HandleRxStatusQueueLevel_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_WriteEmptyTxFifo(USB_CORE_MODULE *USBx , uint32_t epnum); + +static uint32_t USBDEV_HandleUsbReset_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_HandleEnumDone_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_HandleResume_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_HandleUSBSuspend_ISTR(USB_CORE_MODULE *USBx); + +static uint32_t USBDEV_IsoINIncomplete_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBDEV_IsoOUTIncomplete_ISTR(USB_CORE_MODULE *USBx); + +/** +*\*\name USBD_ISTR_Handler. +*\*\fun Handles all USB Interrupts. +*\*\param USBx: device instance. +*\*\return status. +**/ +uint32_t USBD_ISTR_Handler(USB_CORE_MODULE *USBx) +{ + uint32_t retval = 0; + uint32_t gintsts = 0; + + if(USB_IsDeviceMode(USBx)) /* ensure that we are in device mode */ + { + gintsts = USB_ReadCoreItr(USBx); + if(gintsts == 0U) /* avoid spurious interrupt */ + { + return 0; + } + if(gintsts & USBHS_GINTSTS_OUTEPIF) + { + retval |= USBDEV_HandleOutEP_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_INEPIF) + { + retval |= USBDEV_HandleInEP_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_MODMISIF) + { + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_MODMISIF); + } + if(gintsts & USBHS_GINTSTS_WKUPIF) + { + retval |= USBDEV_HandleResume_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_USBSUSPIF) + { + retval |= USBDEV_HandleUSBSuspend_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_SOFIF) + { + retval |= USBDEV_HandleSof_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_RXFNEIF) + { + retval |= USBDEV_HandleRxStatusQueueLevel_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_USBRSTIF) + { + retval |= USBDEV_HandleUsbReset_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_ENUMDIF) + { + retval |= USBDEV_HandleEnumDone_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_ISOINCIF) + { + retval |= USBDEV_IsoINIncomplete_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_PTNCIF_ISOUTNCIF) + { + retval |= USBDEV_IsoOUTIncomplete_ISTR(USBx); + } + } + return retval; +} + +/** +*\*\name USBDEV_HandleResume_ISTR. +*\*\fun Indicates that the USBHS controller has detected a resume or remote Wake-up sequence. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleResume_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t pwrctrl; + + if(USBx->cfg.low_power) + { + /* un-gate USB Core clock */ + pwrctrl = USB_READ_REG32(USBx->regs.PWRCTRL); + pwrctrl &= (~USBHS_PWRCTRL_PHYSTP); + USB_WRITE_REG32(USBx->regs.PWRCTRL, pwrctrl); + } + + /* Clear the Remote Wake-up Signaling */ + USB_MODIFY_REG32(&USBx->regs.DCSR->DCTRL, USBHS_DCTRL_RMWKUP, 0); + + /* Inform upper layer by the Resume Event */ + USBD_DEV_INT_fops->Resume(USBx); + + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_WKUPIF); + return 1; +} + +/** +*\*\name USBDEV_HandleUSBSuspend_ISTR. +*\*\fun Indicates that SUSPEND state has been detected on the USB. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleUSBSuspend_ISTR(USB_CORE_MODULE *USBx) +{ + uint8_t prev_status; + uint32_t dsts; + + prev_status = USBx->dev.device_status; + USBD_DEV_INT_fops->Suspend(USBx); + + dsts = USB_READ_REG32(&USBx->regs.DCSR->DSTS); + + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_USBSUSPIF); + + if((USBx->cfg.low_power) && (dsts & USBHS_DSTS_SUSPF) && (prev_status == USB_CONFIGURED)) + { + /* switch-off the clocks */ + USB_WRITE_REG32(USBx->regs.PWRCTRL, USBHS_PWRCTRL_PHYSTP); + /* Request to enter SLEEP mode*/ + PWR_EnterSLEEPMode(PWR_SLEEP_NOW, PWR_SLEEPENTRY_WFI); + } + return 1; +} + +/** +*\*\name USBDEV_HandleInEP_ISTR. +*\*\fun Indicates that an IN EP has a pending Interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleInEP_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t ep_intr; + uint32_t epnum = 0; + uint32_t fifoemptymsk; + uint32_t dinepintsts; + + ep_intr = USB_ReadDevAllInEPItr(USBx); + + while(ep_intr) + { + if((ep_intr & 0x1) == 0x01) /* In ITR */ + { + dinepintsts = USBDEV_ReadDevInEP(USBx, epnum); /* Get In ITR status */ + if(dinepintsts & USBHS_DINEPINTSTS_TXCIF) + { + fifoemptymsk = 0x1 << epnum; + USB_MODIFY_REG32(&USBx->regs.DCSR->DINEPFEINTEN, fifoemptymsk, 0); + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_TXCIF); + /* TX COMPLETE */ + USBD_DEV_INT_fops->DataInStage(USBx , epnum); + + if (USBx->cfg.dma_enable == 1 && (epnum == 0)) + { + if(USBx->dev.out_ep[epnum].xfer_len == 0) + { + /* prepare to rx more setup packets */ + USB_EP0_OutStart(USBx); + } + } + } + if(dinepintsts & USBHS_DINEPINTSTS_EPDISIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_EPDISIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_TOUTIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_TOUTIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_TXFERINTIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_TXFERINTIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_INEPNAKEIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_INEPNAKEIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_TXFEIF) + { + USBDEV_WriteEmptyTxFifo(USBx, epnum); + } + } + epnum++; + ep_intr >>= 1; + } + + return 1; +} + +/** +*\*\name USBDEV_HandleOutEP_ISTR. +*\*\fun Indicates that an OUT EP has a pending Interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleOutEP_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t ep_intr; + uint32_t epnum = 0; + uint32_t doutepintsts; + uint32_t douteptxsiz; + uint32_t doutepintsts_v; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEp_itr(USBx); + + while(ep_intr) + { + if(ep_intr&0x1) + { + doutepintsts = USB_ReadDevOutEP_itr(USBx, epnum); + doutepintsts_v = USB_READ_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS); + /* Transfer complete */ + if(doutepintsts & USBHS_DOUTEPINTSTS_TXCIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_TXCIF); + if(USBx->cfg.dma_enable == 1) + { + /* Setup Phase Done (control EPs) */ + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPDNEIF) + { + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPRXIF); + } + } + else if(doutepintsts_v & USBHS_DOUTEPINTSTS_STSPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STSPRXIF); + } + else if((doutepintsts_v & (USBHS_DOUTEPINTSTS_STUPPDNEIF | USBHS_DOUTEPINTSTS_STSPRXIF)) == 0) + { + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPRXIF); + } + } + douteptxsiz = USB_READ_REG32((&USBx->regs.OUTEPCSR[epnum]->DOUTEPTXSIZ)); + /*ToDo : handle more than one single MPS size packet */ + USBx->dev.out_ep[epnum].xfer_count = USBx->dev.out_ep[epnum].maxpacket - (douteptxsiz & USBHS_DOUTEPTXSIZ_TLEN); + + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DEV_INT_fops->DataOutStage(USBx , epnum); + if((epnum == 0) && (USBx->dev.out_ep[epnum].xfer_len == 0)) + { + /* prepare to rx more setup packets */ + USB_EP0_OutStart(USBx); + } + } + else + { + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DEV_INT_fops->DataOutStage(USBx , epnum); + } + } + if(doutepintsts & USBHS_DOUTEPINTSTS_OUTTRXEPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_OUTTRXEPDISIF); + } + /* Endpoint disable */ + if(doutepintsts & USBHS_DOUTEPINTSTS_EPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_EPDISIF); + + } + /* Setup Phase Done (control EPs) */ + if(doutepintsts & USBHS_DOUTEPINTSTS_STUPPDNEIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPDNEIF); + /* inform the upper layer that a setup packet is available */ + /* SETUP COMPLETE */ + USBD_DEV_INT_fops->SetupStage(USBx); + + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPRXIF); + } + if((epnum == 0) && (USBx->cfg.dma_enable == 1) && (USBx->dev.out_ep[epnum].xfer_len == 0)) + { + /* prepare to rx more setup packets */ + USB_EP0_OutStart(USBx); + } + } + + if(doutepintsts & USBHS_DOUTEPINTSTS_OUTTRXEPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_OUTTRXEPDISIF); + + } + + /* Endpoint disable */ + if(doutepintsts & USBHS_DOUTEPINTSTS_EPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_EPDISIF); + } + } + epnum++; + ep_intr >>= 1; + } + return 1; +} + +/** +*\*\name USBDEV_HandleSof_ISTR. +*\*\fun Handles the SOF Interrupts. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleSof_ISTR(USB_CORE_MODULE *USBx) +{ + USBD_DEV_INT_fops->SOF(USBx); + /* Clear SOF interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_SOFIF); + + return 1; +} + +/** +*\*\name USBDEV_HandleRxStatusQueueLevel_ISTR. +*\*\fun Handles the Rx Status Queue Level Interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleRxStatusQueueLevel_ISTR(USB_CORE_MODULE *USBx) +{ + USB_EP *ep; + uint32_t grxstsp; + uint32_t bcnt; + + /* Disable the Rx Status Queue Level interrupt */ + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, USBHS_GINTEN_RXFNEIEN, 0); + + /* Get the Status from the top of the FIFO */ + grxstsp = USB_READ_REG32(&USBx->regs.GCSR->GRXSTSP); + bcnt = (grxstsp & USBHS_GRXSTS_BCNT) >> USBHS_GRXSTS_BCNT_POS; + + ep = &USBx->dev.out_ep[(grxstsp & USBHS_GRXSTS_CHEPNUM) >> USBHS_GRXSTS_CHEPNUM_POS]; + + switch ((grxstsp & USBHS_GRXSTS_PKTSTS) >> USBHS_GRXSTS_PKTSTS_POS) + { + case STS_GOUT_NAK: + break; + case STS_DATA_UPDT: + if(bcnt) + { + USB_ReadPacket(USBx,ep->xfer_buff, bcnt); + ep->xfer_buff += bcnt; + ep->xfer_count += bcnt; + } + break; + case STS_XFER_COMP: + break; + case STS_SETUP_COMP: + break; + case STS_SETUP_UPDT: + /* Copy the setup packet received in FIFO into the setup buffer in RAM */ + USB_ReadPacket(USBx , USBx->dev.setup_packet, 8); + ep->xfer_count += bcnt; + break; + default: + break; + } + /* Enable the Rx Status Queue Level interrupt */ + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, 0, USBHS_GINTEN_RXFNEIEN); + return 1; +} + +/** +*\*\name USBDEV_WriteEmptyTxFifo. +*\*\fun Check FIFO for the next packet to be loaded. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_WriteEmptyTxFifo(USB_CORE_MODULE *USBx, uint32_t epnum) +{ + USB_EP *ep; + uint32_t len; + uint32_t len32; + uint32_t fifoemptymsk; + uint32_t dineptxfsts; + + ep = &USBx->dev.in_ep[epnum]; + + len = ep->xfer_len - ep->xfer_count; + + if(len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32 = (len + 3) / 4; + dineptxfsts = USB_READ_REG32(&USBx->regs.INEPCSR[epnum]->DINEPTXFSTS); + + while(((dineptxfsts & USBHS_DINEPTXFSTS_TXFSPCAVL) >> USBHS_DINEPTXFSTS_TXFSPCAVL_POS) > len32 && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + if(len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32 = (len + 3) / 4; + + USB_WritePacket(USBx , ep->xfer_buff, epnum, len); + + ep->xfer_buff += len; + ep->xfer_count += len; + + dineptxfsts = USB_READ_REG32(&USBx->regs.INEPCSR[epnum]->DINEPTXFSTS); + + /* Mask the TxFIFOEmpty interrupt */ + if(ep->xfer_len == ep->xfer_count) + { + fifoemptymsk = 0x1 << ep->num; + USB_MODIFY_REG32(&USBx->regs.DCSR->DINEPFEINTEN, fifoemptymsk, 0); + } + } + + return 1; +} + +/** +*\*\name USBDEV_HandleUsbReset_ISTR. +*\*\fun This interrupt occurs when a USB Reset is detected. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleUsbReset_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t i; + uint32_t depinten = 0; + uint32_t doutepinten = 0; + uint32_t dinepinten = 0; + uint32_t dcfg; + + /* Clear the Remote Wake-up Signaling */ + USB_MODIFY_REG32(&USBx->regs.DCSR->DCTRL, USBHS_DCTRL_RMWKUP, 0); + + /* Flush the Tx FIFO */ + USB_FlushTxFifo(USBx , 0x10); + + for (i=0; icfg.dev_endpoints_num; i++) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[i]->DINEPINTSTS, 0xFFFFU); + USB_MODIFY_REG32(&USBx->regs.INEPCSR[i]->DINEPCTRL, USBHS_DINEPCTRL_STALL, 0); + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[i]->DOUTEPINTSTS, 0xFFFFU); + USB_MODIFY_REG32(&USBx->regs.OUTEPCSR[i]->DOUTEPCTRL, USBHS_DOUTEPCTRL_STALL, USBHS_DOUTEPCTRL_SNAK); + } +#ifdef USB_DEDICATED_EP_ENABLED + USB_WRITE_REG32(&USBx->regs.DCSR->DEEPINTSTS, 0xFFFFFFFF); + depinten |= 1 << USBHS_DEEPINTSTS_INEPINT_POS; + depinten |= 1 << USBHS_DEEPINTSTS_OUTEPINT_POS; + USB_WRITE_REG32(&USBx->regs.DCSR->DEEPINTEN, depinten); +#else + USB_WRITE_REG32(&USBx->regs.DCSR->DAEPINTSTS, 0xFFFFFFFF); + depinten |= 1 << USBHS_DAEPINTEN_INEPIEN_POS; + depinten |= 1 << USBHS_DAEPINTEN_OUTEPIEN_POS; + USB_WRITE_REG32(&USBx->regs.DCSR->DAEPINTEN, depinten); +#endif /* USB_DEDICATED_EP_ENABLED */ + + doutepinten |= USBHS_DOUTEPINTEN_STUPDNEIEN; + doutepinten |= USBHS_DOUTEPINTEN_TXCIEN; + doutepinten |= USBHS_DOUTEPINTEN_EPDIEN; + +#ifdef USB_DEDICATED_EP_ENABLED + for (i = 0UL; i < USBx->cfg.dev_endpoints_num ; i++) + { + if(i<=8) + { + USB_WRITE_REG32(&USBx->regs.DCSR->DOUTEPXINTEN[i], doutepinten); + } + } +#else + + USB_WRITE_REG32(&USBx->regs.DCSR->DOUTEPINTEN, doutepinten); +#endif /* USB_DEDICATED_EP_ENABLED */ + + dinepinten |= USBHS_DINEPINTEN_TXCIEN; + dinepinten |= USBHS_DINEPINTEN_TOIEN; + dinepinten |= USBHS_DINEPINTEN_EPDIEN; + +#ifdef USB_DEDICATED_EP_ENABLED + for (i = 0UL; i < USBx->cfg.dev_endpoints_num ; i++) + { + if(i<=8) + { + USB_WRITE_REG32(&USBx->regs.DCSR->DINEPXINTEN[i], dinepinten); + } + } +#else + USB_WRITE_REG32(&USBx->regs.DCSR->DINEPINTEN, dinepinten); +#endif /* USB_DEDICATED_EP_ENABLED */ + + /* Reset Device Address */ + dcfg = USB_READ_REG32(&USBx->regs.DCSR->DCFG); + dcfg &= (~USBHS_DCFG_DEVARR); + USB_WRITE_REG32(&USBx->regs.DCSR->DCFG, dcfg); + + /* setup EP0 to receive SETUP packets */ + USB_EP0_OutStart(USBx); + + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_USBRSTIF); + + /*Reset internal state machine */ + USBD_DEV_INT_fops->Reset(USBx); + return 1; +} + +/** +*\*\name USBDEV_HandleEnumDone_ISTR. +*\*\fun Read the device status register and set the device speed. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleEnumDone_ISTR(USB_CORE_MODULE *USBx) +{ + RCC_ClocksTypeDef RCC_Clocks; + uint32_t hclk; + uint32_t gcfg; + + USB_EP0Activate(USBx); + + /* Get HCLK frequency */ + RCC_GetClocksFreqValue(&RCC_Clocks); + hclk = RCC_Clocks.AHB2ClkFreq; + + /* Clear default TRDT value and Set USB turn-around time based on device speed and PHY interface. */ + gcfg = USB_READ_REG32(&USBx->regs.GCSR->GCFG); + gcfg &= (~USBHS_GCFG_TRDTIM); + USB_WRITE_REG32(&USBx->regs.GCSR->GCFG, gcfg); + + /* Full or High speed */ + if(USB_GetDeviceSpeed(USBx) == USB_SPEED_HIGH) + { + USBx->cfg.speed = USB_SPEED_HIGH; + USBx->cfg.mps = USB_HS_MAX_PACKET_SIZE ; + /*USBTRD min For HS device*/ + gcfg |= (9 << USBHS_GCFG_TRDTIM_POS); + } + else + { + USBx->cfg.speed = USB_SPEED_FULL; + USBx->cfg.mps = USB_FS_MAX_PACKET_SIZE ; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + + if((hclk >= 15000000)&&(hclk < 16000000)) + { + /* hclk Clock Range between 15-16 MHz */ + gcfg |= (0xE << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 16000000)&&(hclk < 17100000)) + { + /* hclk Clock Range between 16-17.1 MHz */ + gcfg |= (0xD << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 17100000)&&(hclk < 18400000)) + { + /* hclk Clock Range between 17-18.4 MHz */ + gcfg |= (0xC << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 18400000)&&(hclk < 20000000)) + { + /* hclk Clock Range between 18.4-20 MHz */ + gcfg |= (0xB << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 20000000)&&(hclk < 21800000)) + { + /* hclk Clock Range between 20-21.8 MHz */ + gcfg |= (0xA << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 21800000)&&(hclk < 24000000)) + { + /* hclk Clock Range between 21.8-24 MHz */ + gcfg |= (0x9 << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 24000000)&&(hclk < 26600000)) + { + /* hclk Clock Range between 24-26.6 MHz */ + gcfg |= (0x8 << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 26600000)&&(hclk < 30000000)) + { + /* hclk Clock Range between 26.6-30 MHz */ + gcfg |= (0x7 << USBHS_GCFG_TRDTIM_POS); + } + + else if((hclk >= 30000000)&&(hclk < 34300000)) + { + /* hclk Clock Range between 30-34.3 MHz */ + gcfg |= (0x6 << USBHS_GCFG_TRDTIM_POS); + } + + else /* if(hclk >= 34300000) */ + { + /* hclk Clock Range between 34.3-240 MHz */ + gcfg |= (0x5 << USBHS_GCFG_TRDTIM_POS); + } + } + USB_MODIFY_REG32(&USBx->regs.GCSR->GCFG, 0, gcfg); + + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_ENUMDIF); + return 1; +} + +/** +*\*\name USBDEV_IsoINIncomplete_ISTR. +*\*\fun Handle the ISO IN incomplete interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_IsoINIncomplete_ISTR(USB_CORE_MODULE *USBx) +{ + USBD_DEV_INT_fops->IsoINIncomplete (USBx); + + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_ISOINCIF); + + return 1; +} + +/** +*\*\name USBDEV_IsoOUTIncomplete_ISTR. +*\*\fun Handle the ISO OUT incomplete interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_IsoOUTIncomplete_ISTR(USB_CORE_MODULE *USBx) +{ + USBD_DEV_INT_fops->IsoOUTIncomplete(USBx); + + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_PTNCIF_ISOUTNCIF); + return 1; +} + +/** +*\*\name USBDEV_ReadDevInEP. +*\*\fun Reads IN ep flags. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_ReadDevInEP (USB_CORE_MODULE *USBx, uint8_t epnum) +{ + uint32_t v; + uint32_t dinepinten; + uint32_t dinepfeinten; + + dinepinten = USB_READ_REG32(&USBx->regs.DCSR->DINEPINTEN); + dinepfeinten = USB_READ_REG32(&USBx->regs.DCSR->DINEPFEINTEN); + dinepinten |= ((dinepfeinten >> epnum) & 0x1) << 7; + v = USB_READ_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS) & dinepinten; + return v; +} + +/** +*\*\name USBD_ISTR_WKUP_handler. +*\*\fun Handle Wake up interrupt. +*\*\param USBx: device instance. +*\*\return none. +**/ +void USBD_ISTR_WKUP_handler(USB_CORE_MODULE *USBx) +{ + uint32_t gintsts; + if(USB_IsDeviceMode(USBx)) + { + gintsts= USB_ReadCoreItr(USBx); + if(gintsts & USBHS_GINTSTS_WKUPIF) + { + USBDEV_HandleResume_ISTR(USBx); + } + } +} + +#ifdef USB_DEDICATED_EP_ENABLED + +/** +*\*\name USBDEV_HandleEachInEP_ISTR. +*\*\fun Indicates that Each IN EP has a pending Interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleEachInEP_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t ep_intr; + uint32_t epnum = 0; + uint32_t fifoemptymsk; + uint32_t dinepintsts, dinepinten; + + ep_intr = USB_ReadDevEachInEPItr(USBx); + + while(ep_intr) + { + if((ep_intr & 0x1) == 0x01) /* In ITR */ + { + dinepinten = USB_READ_REG32(&USBx->regs.DCSR->DINEPXINTEN[epnum]); /* Get In ITR status */ + dinepinten |= (((USB_READ_REG32(&USBx->regs.DCSR->DINEPFEINTEN) >> epnum) & 0x1UL) << 7U); + dinepintsts = (USB_READ_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS) & dinepinten); + if(dinepintsts & USBHS_DINEPINTSTS_TXCIF) + { + fifoemptymsk = 0x1 << epnum; + USB_MODIFY_REG32(&USBx->regs.DCSR->DINEPFEINTEN, fifoemptymsk, 0); + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_TXCIF); + /* TX COMPLETE */ + USBD_DEV_INT_fops->DataInStage(USBx , epnum); + + if (USBx->cfg.dma_enable == 1 && (epnum == 0)) + { + if(USBx->dev.out_ep[epnum].xfer_len == 0) + { + /* prepare to rx more setup packets */ + USB_EP0_OutStart(USBx); + } + } + } + if(dinepintsts & USBHS_DINEPINTSTS_EPDISIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_EPDISIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_TOUTIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_TOUTIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_TXFERINTIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_TXFERINTIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_INEPNAKEIF) + { + USB_WRITE_REG32(&USBx->regs.INEPCSR[epnum]->DINEPINTSTS, USBHS_DINEPINTSTS_INEPNAKEIF); + } + if(dinepintsts & USBHS_DINEPINTSTS_TXFEIF) + { + USBDEV_WriteEmptyTxFifo(USBx, epnum); + } + } + epnum++; + ep_intr >>= 1; + } + + return 1; +} + +/** +*\*\name USBDEV_HandleEachOutEP_ISTR. +*\*\fun Indicates that Each OUT EP has a pending Interrupt. +*\*\param USBx: device instance. +*\*\return status. +**/ +static uint32_t USBDEV_HandleEachOutEP_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t ep_intr; + uint32_t epnum = 0; + uint32_t doutepintsts; + uint32_t douteptxsiz; + uint32_t doutepintsts_v; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevEachOutEPItr(USBx); + + while(ep_intr) + { + if(ep_intr&0x1) + { + doutepintsts = USB_READ_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS); + doutepintsts &= USB_READ_REG32(&USBx->regs.DCSR->DOUTEPXINTEN[epnum]); + doutepintsts_v = USB_READ_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS); + /* Transfer complete */ + if(doutepintsts & USBHS_DOUTEPINTSTS_TXCIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_TXCIF); + if(USBx->cfg.dma_enable == 1) + { + /* Setup Phase Done (control EPs) */ + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPDNEIF) + { + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPRXIF); + } + } + else if(doutepintsts_v & USBHS_DOUTEPINTSTS_STSPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STSPRXIF); + } + else if((doutepintsts_v & (USBHS_DOUTEPINTSTS_STUPPDNEIF | USBHS_DOUTEPINTSTS_STSPRXIF)) == 0) + { + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPRXIF); + } + } + douteptxsiz = USB_READ_REG32((&USBx->regs.OUTEPCSR[epnum]->DOUTEPTXSIZ)); + /*ToDo : handle more than one single MPS size packet */ + USBx->dev.out_ep[epnum].xfer_count = USBx->dev.out_ep[epnum].maxpacket - (douteptxsiz & USBHS_DOUTEPTXSIZ_TLEN); + + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DEV_INT_fops->DataOutStage(USBx , epnum); + if((epnum == 0) && (USBx->dev.out_ep[epnum].xfer_len == 0)) + { + /* prepare to rx more setup packets */ + USB_EP0_OutStart(USBx); + } + } + else + { + /* Inform upper layer: data ready */ + /* RX COMPLETE */ + USBD_DEV_INT_fops->DataOutStage(USBx , epnum); + } + } + if(doutepintsts & USBHS_DOUTEPINTSTS_OUTTRXEPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_OUTTRXEPDISIF); + } + /* Endpoint disable */ + if(doutepintsts & USBHS_DOUTEPINTSTS_EPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_EPDISIF); + + } + /* Setup Phase Done (control EPs) */ + if(doutepintsts & USBHS_DOUTEPINTSTS_STUPPDNEIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPDNEIF); + /* inform the upper layer that a setup packet is available */ + /* SETUP COMPLETE */ + USBD_DEV_INT_fops->SetupStage(USBx); + + if(doutepintsts_v & USBHS_DOUTEPINTSTS_STUPPRXIF) + { + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_STUPPRXIF); + } + if((epnum == 0) && (USBx->cfg.dma_enable == 1) && (USBx->dev.out_ep[epnum].xfer_len == 0)) + { + /* prepare to rx more setup packets */ + USB_EP0_OutStart(USBx); + } + } + + if(doutepintsts & USBHS_DOUTEPINTSTS_OUTTRXEPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_OUTTRXEPDISIF); + } + + /* Endpoint disable */ + if(doutepintsts & USBHS_DOUTEPINTSTS_EPDISIF) + { + /* Clear the bit in DOUTEPINTSTSn for this interrupt */ + USB_WRITE_REG32(&USBx->regs.OUTEPCSR[epnum]->DOUTEPINTSTS, USBHS_DOUTEPINTSTS_EPDISIF); + } + } + epnum++; + ep_intr >>= 1; + } + return 1; +} + +/** +*\*\name USBD_EP_IN_ISTR_Handler. +*\*\fun Handle IN EP interrupt. +*\*\param USBx: device instance. +*\*\return none. +**/ +void USBD_EP_IN_ISTR_Handler(USB_CORE_MODULE *USBx) +{ + uint32_t ep_intr; + if (USB_IsDeviceMode(USBx)) + { + ep_intr = USB_ReadDevEachInEPItr(USBx); + + if (ep_intr == 0UL) + { + return; + } + USBDEV_HandleEachInEP_ISTR(USBx); + } +} + +/** +*\*\name USBD_EP_OUT_ISTR_Handler. +*\*\fun Handle OUT EP interrupt. +*\*\param USBx: device instance. +*\*\return none. +**/ +void USBD_EP_OUT_ISTR_Handler(USB_CORE_MODULE *USBx) +{ + uint32_t ep_intr; + if (USB_IsDeviceMode(USBx)) + { + ep_intr = USB_ReadDevEachOutEPItr(USBx); + if (ep_intr == 0UL) + { + return; + } + USBDEV_HandleEachOutEP_ISTR(USBx); + } +} + +#endif /* USB_DEDICATED_EP_ENABLED */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd.c new file mode 100644 index 0000000000..2f664ea07e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd.c @@ -0,0 +1,220 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_hcd.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbhs_core.h" +#include "usbhs_hcd.h" +#include "usbhs_conf.h" +#include "usbhs_bsp.h" + +/** +*\*\name USBHOST_CoreInit. +*\*\fun Initialize the HOST portion of the driver. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USBHOST_CoreInit(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID) +{ + uint8_t i = 0; + USBx->host.ConnSts = 0; + + for (i= 0; i< USB_MAX_TX_FIFOS; i++) + { + USBx->host.ErrCnt[i] = 0; + USBx->host.XferCnt[i] = 0; + USBx->host.HCH_Status[i] = HCH_IDLE; + } + USBx->host.hch[0].max_packet = 8; + + USB_BasicInit(USBx, coreID); + + USB_EnableGlobalInt(USBx, DISABLE); + USB_CoreInit(USBx); + + /* Force Host Mode*/ + USB_SetCurrentMode(USBx, HOST_MODE); + /* Init Host */ + USB_CoreInitHost(USBx); + /* Enable USB Global interrupt */ + USB_EnableGlobalInt(USBx, ENABLE); +} + +/** +*\*\name HOST_GetCurrentSpeed. +*\*\fun Get Current device Speed. +*\*\param USBx: selected device. +*\*\return speed. +*\*\ +**/ +uint32_t HOST_GetCurrentSpeed(USB_CORE_MODULE *USBx) +{ + uint32_t hpcs = 0; + hpcs = USB_READ_REG32(USBx->regs.HPCS); + return (hpcs & USBHS_HPCS_PSPD) >> USBHS_HPCS_PSPD_POS; +} + +/** +*\*\name HOST_ResetPort. +*\*\fun Issues the reset command to device. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +uint32_t HOST_ResetPort(USB_CORE_MODULE *USBx) +{ + USB_ResetPort(USBx); + return 0; +} + +/** +*\*\name HOST_IsDeviceConnected. +*\*\fun Check if the device is connected. +*\*\param USBx: selected device. +*\*\return Device connection status. 1 -> connected and 0 -> disconnected. +*\*\ +**/ +uint32_t HOST_IsDeviceConnected(USB_CORE_MODULE *USBx) +{ + return (USBx->host.ConnSts); +} + +/** +*\*\name HOST_IsPortEnabled. +*\*\fun This function checks if port is enabled. +*\*\param USBx: selected device. +*\*\return port enable or disable. +*\*\ +**/ +uint32_t HOST_IsPortEnabled(USB_CORE_MODULE *USBx) +{ + return (USBx->host.PortEnabled); +} + +/** +*\*\name HOST_GetCurrentFrame. +*\*\fun This function returns the frame number for sof packet. +*\*\param USBx: selected device. +*\*\return Frame number. +*\*\ +**/ +uint32_t HOST_GetCurrentFrame(USB_CORE_MODULE *USBx) +{ + return (USB_READ_REG32(&USBx->regs.HCSR->HFNUM) & 0xFFFF) ; +} + +/** +*\*\name HOST_GetCurrentFrame. +*\*\fun This function returns the last URBstate. +*\*\param USBx: selected device. +*\*\param ch_num: channel number. +*\*\return URB_STATE. +*\*\ +**/ +URB_STATE HOST_GetURB_State(USB_CORE_MODULE *USBx, uint8_t ch_num) +{ + return USBx->host.URB_State[ch_num] ; +} + +/** +*\*\name HOST_GetXferCnt. +*\*\fun This function returns the last URBstate. +*\*\param USBx: selected device. +*\*\param ch_num: channel number. +*\*\return Number of data bytes transferred. +*\*\ +**/ +uint32_t HOST_GetXferCnt(USB_CORE_MODULE *USBx, uint8_t ch_num) +{ + return USBx->host.XferCnt[ch_num] ; +} + +/** +*\*\name HOST_GetHCState. +*\*\fun This function returns the HC Status. +*\*\param USBx: selected device. +*\*\param ch_num: channel number. +*\*\return HCH_STATUS. +*\*\ +**/ +HCH_STATUS HOST_GetHCState(USB_CORE_MODULE *USBx, uint8_t ch_num) +{ + return USBx->host.HCH_Status[ch_num] ; +} + +/** +*\*\name HOST_HC_Init. +*\*\fun This function prepare a HC and start a transfer. +*\*\param USBx: selected device. +*\*\param ch_num: channel number. +*\*\return status. +*\*\ +**/ +uint32_t HOST_HC_Init(USB_CORE_MODULE *USBx, uint8_t ch_num) +{ + return USB_HCH_Init(USBx, ch_num); +} + +/** +*\*\name HOST_SubmitRequest. +*\*\fun This function prepare a HC and start a transfer. +*\*\param USBx: selected device. +*\*\param ch_num: channel number. +*\*\return status. +*\*\ +**/ +uint32_t HOST_SubmitRequest(USB_CORE_MODULE *USBx, uint8_t ch_num) +{ + USBx->host.URB_State[ch_num] = URB_IDLE; + USBx->host.hch[ch_num].xfer_count = 0 ; + return USB_HCH_StartXfer(USBx, ch_num); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd_int.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd_int.c new file mode 100644 index 0000000000..a7d4c8bf43 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/driver/src/usbhs_hcd_int.c @@ -0,0 +1,787 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbhs_hcd_int.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbhs_core.h" +#include "usbhs_defines.h" +#include "usbhs_hcd_int.h" + +#if defined (__CC_ARM) /*!< ARM Compiler */ +#pragma O0 +#elif defined (__GNUC__) /*!< GNU Compiler */ +#pragma GCC optimize ("O0") + +#endif /* __CC_ARM */ + + +static uint32_t USBHOST_handle_sof_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_port_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_hch_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_hch_n_In_ISTR(USB_CORE_MODULE *USBx, uint32_t num); +static uint32_t USBHOST_handle_hch_n_Out_ISTR(USB_CORE_MODULE *USBx, uint32_t num); +static uint32_t USBHOST_handle_rx_qlvl_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_nptxfempty_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_ptxfempty_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_Disconnect_ISTR(USB_CORE_MODULE *USBx); +static uint32_t USBHOST_handle_IncompletePeriodicXfer_ISTR(USB_CORE_MODULE *USBx); + +/** +*\*\name USBHOST_handle_Wakeup_ISTR. +*\*\fun process the resume/remote wakeup detected interrupt. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +static void USBHOST_handle_Wakeup_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t hpcs; + + hpcs = USB_ReadHPCS(USBx); + hpcs &= ~USBHS_HPCS_PRES; + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); +} + +/** +*\*\name USBHOST_ISTR_WKUP_handler. +*\*\fun process the resume/remote wakeup detected interrupt. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USBHOST_ISTR_WKUP_handler(USB_CORE_MODULE *pdev) +{ + uint32_t gintsts; + if (0U != USB_GetMode(pdev)) + { + gintsts = USB_ReadCoreItr(pdev); + if (gintsts == 0UL) + { + return; + } + if (0UL != (gintsts & USBHS_GINTSTS_WKUPIF)) + { + USBHOST_handle_Wakeup_ISTR(pdev); + } + } +} + +/** +*\*\name USBHOST_ISTR_Handler. +*\*\fun This function handles all USB Host Interrupts. +*\*\param USBx: selected device. +*\*\return retval. +*\*\ +**/ +uint32_t USBHOST_ISTR_Handler(USB_CORE_MODULE *USBx) +{ + uint32_t retval = 0; + uint32_t gintsts = 0; + + /* Check if HOST Mode */ + if(USB_IsHostMode(USBx)) + { + gintsts = USB_ReadCoreItr(USBx); + if(!gintsts) + { + return 0; + } + if(gintsts & USBHS_GINTSTS_SOFIF) + { + retval |= USBHOST_handle_sof_ISTR(USBx); + } + + if(gintsts & USBHS_GINTSTS_RXFNEIF) + { + retval |= USBHOST_handle_rx_qlvl_ISTR(USBx); + } + + if(gintsts & USBHS_GINTSTS_NPTXFEIF) + { + retval |= USBHOST_handle_nptxfempty_ISTR(USBx); + } + + if(gintsts & USBHS_GINTSTS_PTXFEIF) + { + retval |= USBHOST_handle_ptxfempty_ISTR(USBx); + } + + if(gintsts & USBHS_GINTSTS_HCHIF) + { + retval |= USBHOST_handle_hch_ISTR(USBx); + } + + if(gintsts & USBHS_GINTSTS_HPIF) + { + retval |= USBHOST_handle_port_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_DISCIF) + { + retval |= USBHOST_handle_Disconnect_ISTR(USBx); + } + if(gintsts & USBHS_GINTSTS_PTNCIF_ISOUTNCIF) + { + retval |= USBHOST_handle_IncompletePeriodicXfer_ISTR(USBx); + } + } + return retval; +} + + +/** +*\*\name USBHOST_handle_hch_ISTR. +*\*\fun This function indicates that one or more host channels has a pending. +*\*\param USBx: selected device. +*\*\return retval. +*\*\ +**/ +static uint32_t USBHOST_handle_hch_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t i = 0; + uint32_t retval = 0; + uint32_t hachint = 0; + uint32_t hchctrl = 0; + + /* Clear appropriate bits in HCHINTSTSn to clear the interrupt bit in GINTSTS */ + hachint = USB_ReadHostAllChannels_intr(USBx); + + for(i=0; icfg.host_channels_num; i++) + { + if(((hachint & USBHS_HACHINT) >> USBHS_HACHINT_POS) & (1 << i)) + { + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[i]->HCHCTRL); + if(hchctrl & USBHS_HCHCTRL_EPDIR) + { + retval |= USBHOST_handle_hch_n_In_ISTR(USBx, i); + } + else + { + retval |= USBHOST_handle_hch_n_Out_ISTR(USBx, i); + } + } + } + return retval; +} + + +/** +*\*\name USBHOST_handle_sof_ISTR. +*\*\fun Handles the start-of-frame interrupt in host mode. +*\*\param USBx: selected device. +*\*\return 1. +*\*\ +**/ +static uint32_t USBHOST_handle_sof_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t gintsts = 0; + + USBHOST_INT_fops->SOF(USBx); + + /* Clear interrupt */ + gintsts |= USBHS_GINTSTS_SOFIF; + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, gintsts); + + return 1; +} + + +/** +*\*\name USBHOST_handle_Disconnect_ISTR. +*\*\fun Handles disconnect event. +*\*\param USBx: selected device. +*\*\return 1. +*\*\ +**/ +static uint32_t USBHOST_handle_Disconnect_ISTR(USB_CORE_MODULE *USBx) +{ + USBHOST_INT_fops->DevDisconnected(USBx); + /* Clear interrupt */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, USBHS_GINTSTS_DISCIF); + return 1; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_nptxfempty_ISTR. +*\*\fun Handles non periodic tx fifo empty. +*\*\param USBx: selected device. +*\*\return 1. +*\*\ +**/ +static uint32_t USBHOST_handle_nptxfempty_ISTR(USB_CORE_MODULE *USBx) +{ + uint16_t len_words = 0, len = 0; + uint32_t ginten = 0; + uint32_t gnptxfsts = 0; + uint8_t chnum = 0; + + gnptxfsts = USB_READ_REG32(&USBx->regs.GCSR->GNPTXFSTS); + + chnum = (gnptxfsts & USBHS_GNPTXFSTS_NPTXRQTOP_CHNUM) >> USBHS_GNPTXFSTS_NPTXRQTOP_CHNUM_POS; + len_words = (USBx->host.hch[chnum].xfer_len + 3) / 4; + + while(((gnptxfsts & USBHS_GNPTXFSTS_NPTXFSAV) > len_words) && (USBx->host.hch[chnum].xfer_len != 0)) + { + len = (gnptxfsts & USBHS_GNPTXFSTS_NPTXFSAV) * 4; + + if(len > USBx->host.hch[chnum].xfer_len) + { + /* Last packet */ + len = USBx->host.hch[chnum].xfer_len; + + ginten |= USBHS_GINTEN_NPTXFEIEN; + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, ginten, 0); + } + + len_words = (USBx->host.hch[chnum].xfer_len + 3) / 4; + + USB_WritePacket(USBx , USBx->host.hch[chnum].xfer_buff, chnum, len); + + USBx->host.hch[chnum].xfer_buff += len; + USBx->host.hch[chnum].xfer_len -= len; + USBx->host.hch[chnum].xfer_count += len; + + gnptxfsts = USB_READ_REG32(&USBx->regs.GCSR->GNPTXFSTS); + } + return 1; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_ptxfempty_ISTR. +*\*\fun Handles periodic tx fifo empty. +*\*\param USBx: selected device. +*\*\return 1. +*\*\ +**/ +static uint32_t USBHOST_handle_ptxfempty_ISTR(USB_CORE_MODULE *USBx) +{ + uint16_t len_words = 0, len = 0; + uint32_t ginten = 0; + uint32_t hptxfqsts = 0; + uint8_t chnum = 0; + + hptxfqsts = USB_READ_REG32(&USBx->regs.HCSR->HPTXFQSTS); + chnum = (hptxfqsts & USBHS_HPTXFQSTS_PTXRQTOP_CHNUM) >> USBHS_HPTXFQSTS_PTXRQTOP_CHNUM_POS; + len_words = (USBx->host.hch[chnum].xfer_len + 3) / 4; + + while (((hptxfqsts & USBHS_HPTXFQSTS_PTXFSAVL) > len_words)&& (USBx->host.hch[chnum].xfer_len != 0)) + { + len = (hptxfqsts & USBHS_HPTXFQSTS_PTXFSAVL) * 4; + if(len > USBx->host.hch[chnum].xfer_len) + { + len = USBx->host.hch[chnum].xfer_len; + /* Last packet */ + ginten |= USBHS_GINTEN_PTXFEIEN; + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, ginten, 0); + } + + len_words = (USBx->host.hch[chnum].xfer_len + 3) / 4; + + USB_WritePacket(USBx , USBx->host.hch[chnum].xfer_buff, chnum, len); + + USBx->host.hch[chnum].xfer_buff += len; + USBx->host.hch[chnum].xfer_len -= len; + USBx->host.hch[chnum].xfer_count += len; + + hptxfqsts = USB_READ_REG32(&USBx->regs.HCSR->HPTXFQSTS); + } + return 1; +} + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_port_ISTR. +*\*\fun This function determines which interrupt conditions have occurred. +*\*\param USBx: selected device. +*\*\return retval. +*\*\ +**/ +static uint32_t USBHOST_handle_port_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t retval = 0; + uint32_t ginten = 0; + uint32_t hpcs = 0, hpcs_dup = 0; + uint8_t portspeed = 0; + + hpcs = USB_READ_REG32(USBx->regs.HPCS); + hpcs_dup = USB_READ_REG32(USBx->regs.HPCS); + + /* Clear the interrupt bits in GINTSTS */ + hpcs_dup &= ~(USBHS_HPCS_PEN | USBHS_HPCS_PCDET | USBHS_HPCS_PENC | USBHS_HPCS_POCC); + + /* Port Connect Detected */ + if(hpcs & USBHS_HPCS_PCDET) + { + hpcs_dup |= USBHS_HPCS_PCDET; + USBHOST_INT_fops->DevConnected(USBx); + retval |= 1; + } + + /* Port Enable Changed */ + if(hpcs & USBHS_HPCS_PENC) + { + hpcs_dup |= USBHS_HPCS_PENC; + if(hpcs & USBHS_HPCS_PEN) + { + portspeed = (hpcs & USBHS_HPCS_PSPD) >> USBHS_HPCS_PSPD_POS; + if((portspeed == HPCS_PRTSPD_LOW_SPEED) || (portspeed == HPCS_PRTSPD_FULL_SPEED)) + { + USB_WRITE_REG32(&USBx->regs.HCSR->HFRI, 60000); + } + USBHOST_INT_fops->DevPortEnabled(USBx); + + /* Enable disconnect interrupt */ + ginten |= USBHS_GINTEN_DISCIEN; + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, ginten, ginten); + } + else + { + USBHOST_INT_fops->DevPortDisabled(USBx); + } + } + + /* Overcurrent Change Interrupt */ + if((hpcs & USBHS_HPCS_POCC) >> USBHS_HPCS_POCC_POS) + { + hpcs_dup |= USBHS_HPCS_POCC; + retval |= 1; + } + /* Clear Port Interrupts */ + USB_WRITE_REG32(USBx->regs.HPCS, hpcs_dup); + return retval; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_hch_n_Out_ISTR. +*\*\fun Handles interrupt for a specific Host Channel. +*\*\param USBx: selected device. +*\*\param num: Channel number. +*\*\return 1. +*\*\ +**/ +uint32_t USBHOST_handle_hch_n_Out_ISTR(USB_CORE_MODULE *USBx , uint32_t num) +{ + USB_HostCH_Registers *hostchreg; + + uint32_t hchintsts = 0; + uint32_t hchinten = 0; + uint32_t hchctrl = 0; + + hostchreg = USBx->regs.HCHCSR[num]; + hchintsts = USB_READ_REG32(&hostchreg->HCHINTSTS); + hchinten = USB_READ_REG32(&hostchreg->HCHINTEN); + hchintsts &= hchinten; + + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[num]->HCHCTRL); + + if(hchintsts & USBHS_HCHINTSTS_AHBERRIF) + { + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_AHBERRIF); + + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + } + else if(hchintsts & USBHS_HCHINTSTS_ACKIF) + { + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_ACKIF); + } + else if(hchintsts & USBHS_HCHINTSTS_FOVRIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_FOVRIF); + } + else if(hchintsts & USBHS_HCHINTSTS_TXCFIF) + { + USBx->host.ErrCnt[num] = 0; + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_TXCFIF); + USBx->host.HCH_Status[num] = HCH_XFRC; + } + else if(hchintsts & USBHS_HCHINTSTS_STALLIF) + { + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_STALLIF); + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USBx->host.HCH_Status[num] = HCH_STALL; + } + else if(hchintsts & USBHS_HCHINTSTS_NAKIF) + { + USBx->host.ErrCnt[num] = 0; + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + if(USBx->cfg.dma_enable == 0) + { + USB_HCH_Halt(USBx, num); + } + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NAKIF); + USBx->host.HCH_Status[num] = HCH_NAK; + } + + else if(hchintsts & USBHS_HCHINTSTS_TXERRIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USBx->host.HCH_Status[num] = HCH_XACTERR; + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_TXERRIF); + } + else if(hchintsts & USBHS_HCHINTSTS_NYETIF) + { + USBx->host.ErrCnt[num] = 0; + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + if(USBx->cfg.dma_enable == 0) + { + USB_HCH_Halt(USBx, num); + } + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NYETIF); + USBx->host.HCH_Status[num] = HCH_NYET; + } + else if(hchintsts & USBHS_HCHINTSTS_DTERRIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NAKIF); + USBx->host.HCH_Status[num] = HCH_DATATGLERR; + + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_DTERRIF); + } + else if(hchintsts & USBHS_HCHINTSTS_CHHTDIF) + { + USB_MODIFY_REG32(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN, 0); + + if(USBx->host.HCH_Status[num] == HCH_XFRC) + { + USBx->host.URB_State[num] = URB_DONE; + + if((hchctrl & USBHS_HCHCTRL_EPTYPE) >> USBHS_HCHCTRL_EPTYPE_POS == EP_TYPE_BULK) + { + USBx->host.hch[num].toggle_out ^= 1; + } + } + else if(USBx->host.HCH_Status[num] == HCH_NAK) + { + USBx->host.URB_State[num] = URB_NOTREADY; + } + else if(USBx->host.HCH_Status[num] == HCH_NYET) + { + if(USBx->host.hch[num].do_ping == 1) + { + USB_HCH_DoPing(USBx, num); + } + USBx->host.URB_State[num] = URB_NOTREADY; + } + else if(USBx->host.HCH_Status[num] == HCH_STALL) + { + USBx->host.URB_State[num] = URB_STALL; + } + else if(USBx->host.HCH_Status[num] == HCH_XACTERR) + { + USBx->host.URB_State[num] = URB_ERROR; + } + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_CHHTDIF); + } + return 1; +} +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_hch_n_In_ISTR. +*\*\fun Handles interrupt for a specific Host Channel. +*\*\param USBx: selected device. +*\*\param num: Channel number. +*\*\return 1. +*\*\ +**/ +uint32_t USBHOST_handle_hch_n_In_ISTR(USB_CORE_MODULE *USBx, uint32_t num) +{ + USB_HostCH_Registers *hostchreg; + + uint32_t hchintsts = 0; + uint32_t hchinten = 0; + uint32_t hchctrl = 0; + uint32_t hchtxsiz = 0; + uint8_t eptype = 0; + + hostchreg = USBx->regs.HCHCSR[num]; + hchintsts = USB_READ_REG32(&hostchreg->HCHINTSTS); + hchinten = USB_READ_REG32(&hostchreg->HCHINTEN); + hchintsts &= hchinten; + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[num]->HCHCTRL); + + + eptype = (hchctrl & USBHS_HCHCTRL_EPTYPE) >> USBHS_HCHCTRL_EPTYPE_POS; + + if(hchintsts & USBHS_HCHINTSTS_AHBERRIF) + { + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_AHBERRIF); + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + } + else if(hchintsts & USBHS_HCHINTSTS_ACKIF) + { + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_ACKIF); + } + else if(hchintsts & USBHS_HCHINTSTS_STALLIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USBx->host.HCH_Status[num] = HCH_STALL; + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NAKIF); /* Clear the NAK Condition */ + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_STALLIF); /* Clear the STALL Condition */ + hchintsts &= (~USBHS_HCHINTSTS_NAKIF); /* NOTE: When there is a 'stall', reset also nak, + else, the USBx->host.HCH_Status = HCH_STALL + will be overwritten by 'nak' in code below */ + USB_HCH_Halt(USBx, num); + } + else if(hchintsts & USBHS_HCHINTSTS_DTERRIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NAKIF); + USBx->host.HCH_Status[num] = HCH_DATATGLERR; + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_DTERRIF); + } + + if(hchintsts & USBHS_HCHINTSTS_FOVRIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_FOVRIF); + } + else if(hchintsts & USBHS_HCHINTSTS_TXCFIF) + { + if(USBx->cfg.dma_enable == 1) + { + hchtxsiz = USB_READ_REG32(&USBx->regs.HCHCSR[num]->HCHTXSIZ); + USBx->host.XferCnt[num] = USBx->host.hch[num].xfer_len - ((hchtxsiz & USBHS_HCHTXSIZ_TXSIZ) >> USBHS_HCHTXSIZ_TXSIZ_POS); + } + + USBx->host.HCH_Status[num] = HCH_XFRC; + USBx->host.ErrCnt[num] = 0; + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_TXCFIF); + + if((eptype == EP_TYPE_CTRL) || (eptype == EP_TYPE_BULK)) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NAKIF); + USBx->host.hch[num].toggle_in ^= 1; + } + else if(eptype == EP_TYPE_INTR) + { + hchctrl |= USBHS_HCHCTRL_ODDFRM; + USB_WRITE_REG32(&USBx->regs.HCHCSR[num]->HCHCTRL, hchctrl); + USBx->host.URB_State[num] = URB_DONE; + } + } + else if(hchintsts & USBHS_HCHINTSTS_CHHTDIF) + { + USB_MODIFY_REG32(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN, 0); + + if(USBx->host.HCH_Status[num] == HCH_XFRC) + { + USBx->host.URB_State[num] = URB_DONE; + } + else if(USBx->host.HCH_Status[num] == HCH_STALL) + { + USBx->host.URB_State[num] = URB_STALL; + } + + else if((USBx->host.HCH_Status[num] == HCH_XACTERR) || (USBx->host.HCH_Status[num] == HCH_DATATGLERR)) + { + USBx->host.ErrCnt[num] = 0; + USBx->host.URB_State[num] = URB_ERROR; + } + else if(eptype == EP_TYPE_INTR) + { + USBx->host.hch[num].toggle_in ^= 1; + } + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_CHHTDIF); + } + else if(hchintsts & USBHS_HCHINTSTS_TXERRIF) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + USBx->host.HCH_Status[num] = HCH_XACTERR; + USB_HCH_Halt(USBx, num); + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_TXERRIF); + } + else if(hchintsts & USBHS_HCHINTSTS_NAKIF) + { + if(eptype == EP_TYPE_INTR) + { + USB_SET_REG32_BIT(&USBx->regs.HCHCSR[num]->HCHINTEN, USBHS_HCHINTEN_CHHTDIEN); + if(USBx->cfg.dma_enable == 0) + { + USB_HCH_Halt(USBx, num); + } + } + USBx->host.HCH_Status[num] = HCH_NAK; + USB_WRITE_REG32(&hostchreg->HCHINTSTS, USBHS_HCHINTSTS_NAKIF); + if((eptype == EP_TYPE_CTRL)|| (eptype == EP_TYPE_BULK)) + { + /* re-activate the channel */ + hchctrl |= USBHS_HCHCTRL_CHEN; + hchctrl &= (~USBHS_HCHCTRL_CHDIS); + USB_WRITE_REG32(&USBx->regs.HCHCSR[num]->HCHCTRL, hchctrl); + } + } + return 1; +} + + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_rx_qlvl_ISTR. +*\*\fun Handles the Rx Status Queue Level Interrupt. +*\*\param USBx: selected device. +*\*\return 1. +*\*\ +**/ +static uint32_t USBHOST_handle_rx_qlvl_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t grxstsp = 0; + uint32_t ginten = 0; + uint32_t hchctrl = 0; + uint32_t hchtxsiz = 0; + + __IO uint8_t chnum =0; + uint32_t count = 0; + uint32_t bcnt = 0; + + /* Disable the Rx Status Queue Level interrupt */ + ginten |= USBHS_GINTEN_RXFNEIEN; + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, ginten, 0); + + grxstsp = USB_READ_REG32(&USBx->regs.GCSR->GRXSTSP); + chnum = (grxstsp & USBHS_GRXSTS_CHEPNUM) >> USBHS_GRXSTS_CHEPNUM_POS; + bcnt = (grxstsp & USBHS_GRXSTS_BCNT) >> USBHS_GRXSTS_BCNT_POS; + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[chnum]->HCHCTRL); + + switch((grxstsp & USBHS_GRXSTS_PKTSTS) >> USBHS_GRXSTS_PKTSTS_POS) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if(((bcnt > 0) && (USBx->host.hch[chnum].xfer_buff != (void *)0))) + { + USB_ReadPacket(USBx, USBx->host.hch[chnum].xfer_buff, bcnt); + /*manage multiple Xfer */ + USBx->host.hch[chnum].xfer_buff += bcnt; + USBx->host.hch[chnum].xfer_count += bcnt; + + count = USBx->host.hch[chnum].xfer_count; + USBx->host.XferCnt[chnum] = count; + + hchtxsiz = USB_READ_REG32(&USBx->regs.HCHCSR[chnum]->HCHTXSIZ); + if(((hchtxsiz & USBHS_HCHTXSIZ_PKCNT) >> USBHS_HCHTXSIZ_PKCNT_POS) > 0) + { + /* re-activate the channel when more packets are expected */ + hchctrl |= USBHS_HCHCTRL_CHEN; + hchctrl &= (~USBHS_HCHCTRL_CHDIS); + USB_WRITE_REG32(&USBx->regs.HCHCSR[chnum]->HCHCTRL, hchctrl); + } + } + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } + + /* Enable the Rx Status Queue Level interrupt */ + ginten |= USBHS_GINTEN_RXFNEIEN; + USB_MODIFY_REG32(&USBx->regs.GCSR->GINTEN, 0, ginten); + return 1; +} + + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma optimize = none +#endif /* __CC_ARM */ + +/** +*\*\name USBHOST_handle_IncompletePeriodicXfer_ISTR. +*\*\fun Handles the incomplete Periodic transfer Interrupt. +*\*\param USBx: selected device. +*\*\return 1. +*\*\ +**/ +static uint32_t USBHOST_handle_IncompletePeriodicXfer_ISTR(USB_CORE_MODULE *USBx) +{ + uint32_t gintsts = 0; + uint32_t hchctrl = 0; + + hchctrl = USB_READ_REG32(&USBx->regs.HCHCSR[0]->HCHCTRL); + hchctrl |= USBHS_HCHCTRL_CHEN; + hchctrl |= USBHS_HCHCTRL_CHDIS; + USB_WRITE_REG32(&USBx->regs.HCHCSR[0]->HCHCTRL, hchctrl); + + /* Clear interrupt */ + gintsts |= USBHS_GINTSTS_PTNCIF_ISOUTNCIF; + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, gintsts); + + return 1; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_core.h new file mode 100644 index 0000000000..62a1fcf470 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_core.h @@ -0,0 +1,164 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_cdc_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBH_CDC_CORE_H +#define __USBH_CDC_CORE_H + + +#include "usbh_cdc_funct.h" + + + +/*Comuncation Calss codes*/ +#define COMMUNICATION_DEVICE_CLASS_CODE 0x02 +#define COMMUNICATION_INTERFACE_CLASS_CODE 0x02 + +/*Data Interface Class Codes*/ +#define DATA_INTERFACE_CLASS_CODE 0x0A + +/*Communcation sub class codes*/ +#define RESERVED 0x00 +#define DIRECT_LINE_CONTROL_MODEL 0x01 +#define ABSTRACT_CONTROL_MODEL 0x02 +#define TELEPHONE_CONTROL_MODEL 0x03 +#define MULTICHANNEL_CONTROL_MODEL 0x04 +#define CAPI_CONTROL_MODEL 0x05 +#define ETHERNET_NETWORKING_CONTROL_MODEL 0x06 +#define ATM_NETWORKING_CONTROL_MODEL 0x07 + + +/*Communication Interface Class Control Protocol Codes*/ +#define NO_CLASS_SPECIFIC_PROTOCOL_CODE 0x00 +#define COMMON_AT_COMMAND 0x01 +#define VENDOR_SPECIFIC 0xFF + + +#define CS_INTERFACE 0x24 +#define CDC_PAGE_SIZE_64 0x40 + + +/* States for CDC State Machine */ +typedef enum +{ + CDC_IDLE= 0, + CDC_READ_DATA, + CDC_SEND_DATA, + CDC_DATA_SENT, + CDC_BUSY, + CDC_GET_DATA, + CDC_POLL, + CDC_CTRL_STATE +} +CDC_State; + +/* CDC Transfer State */ +typedef struct _CDCXfer +{ + volatile CDC_State CDCState; + uint8_t* pRxTxBuff; + uint8_t* pFillBuff; + uint8_t* pEmptyBuff; + uint32_t BufferLen; + uint16_t DataLength; +} CDC_Xfer_TypeDef; + +typedef struct CDC_UserCb +{ + void (*Send) (uint8_t *); + void (*Receive) (uint8_t *); + +} CDC_Usercb_TypeDef; + +/* Structure for CDC process */ +typedef struct _CDC_CommInterface +{ + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t notificationEp; + CDC_State state; + uint8_t buff[8]; + uint16_t length; + uint8_t ep_addr; +} +CDC_CommInterface_Typedef ; + +typedef struct _CDC_DataInterface +{ + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t cdcOutEp; + uint8_t cdcInEp; + CDC_State state; + uint8_t buff[8]; + uint16_t length; + uint8_t ep_addr; +} +CDC_DataInterface_Typedef ; + +/* Structure for CDC process */ +typedef struct _CDC_Process +{ + CDC_CommInterface_Typedef CDC_CommItf; + CDC_DataInterface_Typedef CDC_DataItf; +} +CDC_Machine_TypeDef; + +extern USBH_Class_cb_TypeDef USBH_CDC_cb; + +void CDC_SendData(uint8_t *data, uint16_t length); +void CDC_StartReception( USB_CORE_MODULE *pdev); +void CDC_StopReception( USB_CORE_MODULE *pdev); + + +#endif /* __USBH_CDC_CORE_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_funct.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_funct.h new file mode 100644 index 0000000000..68759b283b --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/inc/usbh_cdc_funct.h @@ -0,0 +1,294 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_cdc_funct.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBH_CDC_FUNCT_H +#define __USBH_CDC_FUNCT_H + + +#include "usbh_core.h" +#include "usbh_stdreq.h" +#include "usbhs_bsp.h" +#include "usbh_ioreq.h" +#include "usbh_hcs.h" + +/*Class-Specific Request Codes*/ +#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_SET_COMM_FEATURE 0x02 +#define CDC_GET_COMM_FEATURE 0x03 +#define CDC_CLEAR_COMM_FEATURE 0x04 + +#define CDC_SET_AUX_LINE_STATE 0x10 +#define CDC_SET_HOOK_STATE 0x11 +#define CDC_PULSE_SETUP 0x12 +#define CDC_SEND_PULSE 0x13 +#define CDC_SET_PULSE_TIME 0x14 +#define CDC_RING_AUX_JACK 0x15 + +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 +#define CDC_SEND_BREAK 0x23 + +#define CDC_SET_RINGER_PARMS 0x30 +#define CDC_GET_RINGER_PARMS 0x31 +#define CDC_SET_OPERATION_PARMS 0x32 +#define CDC_GET_OPERATION_PARMS 0x33 +#define CDC_SET_LINE_PARMS 0x34 +#define CDC_GET_LINE_PARMS 0x35 +#define CDC_DIAL_DIGITS 0x36 +#define CDC_SET_UNIT_PARAMETER 0x37 +#define CDC_GET_UNIT_PARAMETER 0x38 +#define CDC_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_GET_PROFILE 0x3A + +#define CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x41 +#define CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x42 +#define CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_GET_ETHERNET_STATISTIC 0x44 + +#define CDC_SET_ATM_DATA_FORMAT 0x50 +#define CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_SET_ATM_DEFAULT_VC 0x52 +#define CDC_GET_ATM_VC_STATISTICS 0x53 + + +/* wValue for SetControlLineState*/ +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS 0x0002 +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS 0x0000 +#define CDC_ACTIVATE_SIGNAL_DTR 0x0001 +#define CDC_DEACTIVATE_SIGNAL_DTR 0x0000 + +#define LINE_CODING_STRUCTURE_SIZE 0x07 + +/* States for CDC class State Machine */ +typedef enum +{ + CDC_SET_LINE_CODING_RQUEST = 0, + CDC_GET_LINE_CODING_RQUEST, + CDC_SET_CONTROL_LINE_STATE_REQUEST, + CDC_ERROR_STATE +} +CDC_Requests; + +/*Line coding structure*/ +typedef union _CDC_LineCodingStructure +{ + uint8_t Array[LINE_CODING_STRUCTURE_SIZE]; + + struct + { + uint32_t dwDTERate; /*Data terminal rate, in bits per second*/ + uint8_t bCharFormat; /*Stop bits + 0 - 1 Stop bit + 1 - 1.5 Stop bits + 2 - 2 Stop bits*/ + uint8_t bParityType; /* Parity + 0 - None + 1 - Odd + 2 - Even + 3 - Mark + 4 - Space*/ + uint8_t bDataBits; /* Data bits (5, 6, 7, 8 or 16). */ + }b; +} +CDC_LineCodingTypeDef; + + + +/* Header Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of this descriptor. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Identifier (ID) of functional + | | | | descriptor. +3 | bcdCDC | 2 | | + | | | Number | USB Class Definitions for + | | | | Communication Devices Specification + | | | | release number in binary-coded + | | | | decimal +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _FunctionalDescriptorHeader +{ + uint8_t bLength; /*Size of this descriptor.*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Header functional descriptor subtype as*/ + uint16_t bcdCDC; /* USB Class Definitions for Communication + Devices Specification release number in + binary-coded decimal. */ +} +CDC_HeaderFuncDesc_TypeDef; +/* Call Management Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of this descriptor. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Call Management functional + | | | | descriptor subtype. +3 | bmCapabilities | 1 | Bitmap | The capabilities that this configuration + | | | | supports: + | | | | D7..D2: RESERVED (Reset to zero) + | | | | D1: 0 - Device sends/receives call + | | | | management information only over + | | | | the Communication Class + | | | | interface. + | | | | 1 - Device can send/receive call + | \ | | management information over a + | | | | Data Class interface. + | | | | D0: 0 - Device does not handle call + | | | | management itself. + | | | | 1 - Device handles call + | | | | management itself. + | | | | The previous bits, in combination, identify + | | | | which call management scenario is used. If bit + | | | | D0 is reset to 0, then the value of bit D1 is + | | | | ignored. In this case, bit D1 is reset to zero for + | | | | future compatibility. +4 | bDataInterface | 1 | Number | Interface number of Data Class interface + | | | | optionally used for call management. +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _CallMgmtFunctionalDescriptor +{ + uint8_t bLength; /*Size of this functional descriptor, in bytes.*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Call Management functional descriptor subtype*/ + uint8_t bmCapabilities; /* bmCapabilities: D0+D1 */ + uint8_t bDataInterface; /*bDataInterface: 1*/ +} +CDC_CallMgmtFuncDesc_TypeDef; +/* Abstract Control Management Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of functional descriptor, in bytes. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Abstract Control Management + | | | | functional descriptor subtype. +3 | bmCapabilities | 1 | Bitmap | The capabilities that this configuration + | | | | supports ((A bit value of zero means that the + | | | | request is not supported.) ) + D7..D4: RESERVED (Reset to zero) + | | | | D3: 1 - Device supports the notification + | | | | Network_Connection. + | | | | D2: 1 - Device supports the request + | | | | Send_Break + | | | | D1: 1 - Device supports the request + | \ | | combination of Set_Line_Coding, + | | | | Set_Control_Line_State, Get_Line_Coding, and the + notification Serial_State. + | | | | D0: 1 - Device supports the request + | | | | combination of Set_Comm_Feature, + | | | | Clear_Comm_Feature, and Get_Comm_Feature. + | | | | The previous bits, in combination, identify + | | | | which requests/notifications are supported by + | | | | a Communication Class interface with the + | | | | SubClass code of Abstract Control Model. +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _AbstractCntrlMgmtFunctionalDescriptor +{ + uint8_t bLength; /*Size of this functional descriptor, in bytes.*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Abstract Control Management functional + descriptor subtype*/ + uint8_t bmCapabilities; /* The capabilities that this configuration supports */ +} +CDC_AbstCntrlMgmtFuncDesc_TypeDef; +/* Union Functional Descriptor +-------------------------------------------------------------------------------- +Offset| field | Size | Value | Description +------|---------------------|-------|------------|------------------------------ +0 | bFunctionLength | 1 | number | Size of this descriptor. +1 | bDescriptorType | 1 | Constant | CS_INTERFACE (0x24) +2 | bDescriptorSubtype | 1 | Constant | Union functional + | | | | descriptor subtype. +3 | bMasterInterface | 1 | Constant | The interface number of the + | | | | Communication or Data Class interface +4 | bSlaveInterface0 | 1 | Number | nterface number of first slave or associated + | | | | interface in the union. +------|---------------------|-------|------------|------------------------------ +*/ +typedef struct _UnionFunctionalDescriptor +{ + uint8_t bLength; /*Size of this functional descriptor, in bytes*/ + uint8_t bDescriptorType; /*CS_INTERFACE (0x24)*/ + uint8_t bDescriptorSubType; /* Union functional descriptor SubType*/ + uint8_t bMasterInterface; /* The interface number of the Communication or + Data Class interface,*/ + uint8_t bSlaveInterface0; /*Interface number of first slave*/ +} +CDC_UnionFuncDesc_TypeDef; + +typedef struct _USBH_CDCInterfaceDesc +{ + CDC_HeaderFuncDesc_TypeDef CDC_HeaderFuncDesc; + CDC_CallMgmtFuncDesc_TypeDef CDC_CallMgmtFuncDesc; + CDC_AbstCntrlMgmtFuncDesc_TypeDef CDC_AbstCntrlMgmtFuncDesc; + CDC_UnionFuncDesc_TypeDef CDC_UnionFuncDesc; +} +CDC_InterfaceDesc_Typedef; + +USBH_Status CDC_GETLineCoding(USB_CORE_MODULE *pdev, USBH_HOST *phost); +USBH_Status CDC_SETLineCoding(USB_CORE_MODULE *pdev, USBH_HOST *phost); +USBH_Status CDC_SETControlLineState(USB_CORE_MODULE *pdev, USBH_HOST *phost); +void CDC_ChangeStateToIssueSetConfig(USB_CORE_MODULE *pdev, USBH_HOST *phost); +void CDC_IssueGetConfig(USB_CORE_MODULE *pdev, USBH_HOST *phost); + +#endif /* __USBH_CDC_FUNCT_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_core.c new file mode 100644 index 0000000000..b28f5eb0a6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_core.c @@ -0,0 +1,568 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_cdc_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbh_cdc_core.h" + +#define CDC_BUFFER_SIZE 1024 + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN CDC_Machine_TypeDef CDC_Machine __ALIGN_END ; + +CDC_Requests CDC_ReqState; +CDC_Xfer_TypeDef CDC_TxParam; +CDC_Xfer_TypeDef CDC_RxParam; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t TxBuf [CDC_BUFFER_SIZE] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t RxBuf [CDC_BUFFER_SIZE] __ALIGN_END ; + +CDC_Usercb_TypeDef UserCb; +uint8_t RX_Enabled = 0; + +static void CDC_InitTxRxParam(void); + +static void CDC_ReceiveData(CDC_Xfer_TypeDef *cdc_Data); + +static void CDC_ProcessTransmission(USB_CORE_MODULE *pdev, USBH_HOST *phost); + +static void CDC_ProcessReception(USB_CORE_MODULE *pdev, USBH_HOST *phost); + +static USBH_Status CDC_InterfaceInit(USB_CORE_MODULE *pdev , void *phost); + +void CDC_InterfaceDeInit(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status CDC_Handle(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status CDC_ClassRequest(USB_CORE_MODULE *pdev , void *phost); + + +USBH_Class_cb_TypeDef USBH_CDC_cb = +{ + CDC_InterfaceInit, + CDC_InterfaceDeInit, + CDC_ClassRequest, + CDC_Handle +}; + +/** +*\*\name CDC_InterfaceInit. +*\*\fun The function init the CDC class. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return USBH_Status :Response for USB CDC driver intialization. +*\*\ +**/ +static USBH_Status CDC_InterfaceInit ( USB_CORE_MODULE *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + USBH_Status status = USBH_OK ; + + /* Communication Interface */ + if((pphost->device_prop.Itf_Desc[0].bInterfaceClass == COMMUNICATION_DEVICE_CLASS_CODE)&& \ + (pphost->device_prop.Itf_Desc[0].bInterfaceSubClass == ABSTRACT_CONTROL_MODEL) && \ + (pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == COMMON_AT_COMMAND)) + { + /*Collect the notification endpoint address and length*/ + CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.Ep_Desc[0][0].bEndpointAddress; + CDC_Machine.CDC_CommItf.length = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize; + + if(pphost->device_prop.Ep_Desc[0][0].bEndpointAddress & 0x80) + { + CDC_Machine.CDC_CommItf.notificationEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress); + } + /*Allocate the length for host channel number in*/ + CDC_Machine.CDC_CommItf.hc_num_in = USBH_Alloc_Channel(pdev, CDC_Machine.CDC_CommItf.notificationEp ); + /* Open channel for IN endpoint */ + USBH_Open_Channel (pdev, CDC_Machine.CDC_CommItf.hc_num_in,pphost->device_prop.address, pphost->device_prop.speed, EP_TYPE_INTR, CDC_Machine.CDC_CommItf.length); + } + else + { + pphost->usr_cb->DeviceNotSupported(); + } + + + /* Data Interface */ + if((pphost->device_prop.Itf_Desc[1].bInterfaceClass == DATA_INTERFACE_CLASS_CODE)&& \ + (pphost->device_prop.Itf_Desc[1].bInterfaceSubClass == RESERVED) && \ + (pphost->device_prop.Itf_Desc[1].bInterfaceProtocol == NO_CLASS_SPECIFIC_PROTOCOL_CODE)) + { + /*Collect the class specific endpoint address and length*/ + CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.Ep_Desc[1][0].bEndpointAddress; + CDC_Machine.CDC_DataItf.length = pphost->device_prop.Ep_Desc[1][0].wMaxPacketSize; + + if(pphost->device_prop.Ep_Desc[1][0].bEndpointAddress & 0x80) + { + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.Ep_Desc[1][0].bEndpointAddress); + } + else + { + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.Ep_Desc[1][0].bEndpointAddress); + } + + if(pphost->device_prop.Ep_Desc[1][1].bEndpointAddress & 0x80) + { + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.Ep_Desc[1][1].bEndpointAddress); + } + else + { + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.Ep_Desc[1][1].bEndpointAddress); + } + + /*Allocate the length for host channel number out*/ + CDC_Machine.CDC_DataItf.hc_num_out = USBH_Alloc_Channel(pdev, CDC_Machine.CDC_DataItf.cdcOutEp); + /*Allocate the length for host channel number in*/ + CDC_Machine.CDC_DataItf.hc_num_in = USBH_Alloc_Channel(pdev, CDC_Machine.CDC_DataItf.cdcInEp); + + /* Open channel for OUT endpoint */ + USBH_Open_Channel(pdev, CDC_Machine.CDC_DataItf.hc_num_out, pphost->device_prop.address, pphost->device_prop.speed, EP_TYPE_BULK, CDC_Machine.CDC_DataItf.length); + /* Open channel for IN endpoint */ + USBH_Open_Channel(pdev, CDC_Machine.CDC_DataItf.hc_num_in, pphost->device_prop.address, pphost->device_prop.speed, EP_TYPE_BULK, CDC_Machine.CDC_DataItf.length); + + /*Initilise the Tx/Rx Params*/ + CDC_InitTxRxParam(); + + /*Initialize the class specific request with "GET_LINE_CODING"*/ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST ; + } + else + { + pphost->usr_cb->DeviceNotSupported(); + } + return status; + +} + +/** +*\*\name CDC_InterfaceDeInit. +*\*\fun The function DeInit the Host Channels used for the CDC class. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return none. +*\*\ +**/ +void CDC_InterfaceDeInit ( USB_CORE_MODULE *pdev, void *phost) +{ + if (CDC_Machine.CDC_CommItf.hc_num_in) + { + USB_HCH_Halt(pdev, CDC_Machine.CDC_CommItf.hc_num_in); + USBH_Free_Channel(pdev,CDC_Machine.CDC_CommItf.hc_num_in); + CDC_Machine.CDC_CommItf.hc_num_in = 0; /* Reset the Channel as Free */ + } + + if (CDC_Machine.CDC_DataItf.hc_num_out) + { + USB_HCH_Halt(pdev, CDC_Machine.CDC_DataItf.hc_num_out); + USBH_Free_Channel(pdev,CDC_Machine.CDC_DataItf.hc_num_out); + CDC_Machine.CDC_DataItf.hc_num_out = 0; /* Reset the Channel as Free */ + } + + if (CDC_Machine.CDC_DataItf.hc_num_in) + { + USB_HCH_Halt(pdev, CDC_Machine.CDC_DataItf.hc_num_in); + USBH_Free_Channel (pdev,CDC_Machine.CDC_DataItf.hc_num_in); + CDC_Machine.CDC_DataItf.hc_num_in = 0; /* Reset the Channel as Free */ + } +} + +/** +*\*\name CDC_ClassRequest. +*\*\fun The function is responsible for handling CDC Class requests for CDC class. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return USBH_Status :Response for USB Set Protocol request. +*\*\ +**/ +static USBH_Status CDC_ClassRequest(USB_CORE_MODULE *pdev , void *phost) +{ + USBH_HOST *pphost = phost; + + USBH_Status status = USBH_BUSY; + USBH_Status ClassReqStatus = USBH_BUSY; + + switch(CDC_ReqState) + { + + case CDC_GET_LINE_CODING_RQUEST: + /*Issue the get line coding request*/ + ClassReqStatus = CDC_GETLineCoding(pdev, phost); + if( ClassReqStatus == USBH_OK ) + { /*Change the state */ + CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST; + } + break; + + case CDC_SET_LINE_CODING_RQUEST: + /*Issue the set line coding request*/ + ClassReqStatus = CDC_SETLineCoding(pdev, phost); + if(ClassReqStatus == USBH_OK ) + { + /*Change the state */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST ; + } + if(ClassReqStatus == USBH_NOT_SUPPORTED ) + { + /* a Clear Feature should be issued here */ + CDC_ReqState = CDC_ERROR_STATE; + } + break; + + case CDC_SET_CONTROL_LINE_STATE_REQUEST: + /*Issue the set control line coding */ + ClassReqStatus = CDC_SETControlLineState(pdev, phost); + if( ClassReqStatus == USBH_OK ) + { + /*Change the state */ + CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST; + /*Also set the state of receive CDCRxParam to IDLE*/ + CDC_RxParam.CDCState = CDC_IDLE; + status = USBH_OK; /*This return from class specific routinues request*/ + } + break; + + case CDC_ERROR_STATE: + + ClassReqStatus = USBH_ClrFeature(pdev, phost, 0x00, pphost->Control.hch_num_out); + + if(ClassReqStatus == USBH_OK ) + { + /*Change the state to waiting*/ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST ; + } + break; + } + + return status; +} + + + +/** +*\*\name CDC_Handle. +*\*\fun The function is for managing state machine for CDC data transfers. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return status. +*\*\ +**/ +static USBH_Status CDC_Handle(USB_CORE_MODULE *pdev , void *phost) +{ + USBH_Status status = USBH_OK; + USBH_HOST *pphost = phost; + + /* Call Application process */ + pphost->usr_cb->UserApplication(); + + /*Handle the transmission */ + CDC_ProcessTransmission(pdev, pphost); + + /*Always send in packet to device*/ + CDC_ProcessReception(pdev, pphost); + + return status; +} + + + +/** +*\*\name CDC_ProcessTransmission. +*\*\fun The function is responsible for sending data to the device. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return none. +*\*\ +**/ +void CDC_ProcessTransmission(USB_CORE_MODULE *pdev, USBH_HOST *phost) +{ + static uint32_t len ; + URB_STATE URB_StatusTx = URB_IDLE; + + URB_StatusTx = HOST_GetURB_State(pdev , CDC_Machine.CDC_DataItf.hc_num_out); + + switch(CDC_TxParam.CDCState) + { + case CDC_IDLE: + break; + + case CDC_SEND_DATA: + if(( URB_StatusTx == URB_DONE ) || (URB_StatusTx == URB_IDLE)) + { + /*Check the data length is more then the CDC_Machine.CDC_DataItf.CDC_DataItf.length */ + if(CDC_TxParam.DataLength > CDC_Machine.CDC_DataItf.length) + { + + len = CDC_Machine.CDC_DataItf.length ; + /*Send the data */ + USBH_BulkSendData (pdev, CDC_TxParam.pRxTxBuff, len , CDC_Machine.CDC_DataItf.hc_num_out); + } + else + { + len = CDC_TxParam.DataLength ; + /*Send the remaining data */ + USBH_BulkSendData (pdev, CDC_TxParam.pRxTxBuff, len, CDC_Machine.CDC_DataItf.hc_num_out); + } + CDC_TxParam.CDCState = CDC_DATA_SENT; + } + break; + + case CDC_DATA_SENT: + /*Check the status done for transmssion*/ + if(URB_StatusTx == URB_DONE ) + { + /*Point to next chunc of data*/ + CDC_TxParam.pRxTxBuff += len ; + + /*decrease the data length*/ + CDC_TxParam.DataLength -= len; + + if(CDC_TxParam.DataLength == 0) + { + CDC_TxParam.CDCState = CDC_IDLE; + } + else + { + CDC_TxParam.CDCState = CDC_SEND_DATA; + } + } + else if( URB_StatusTx == URB_NOTREADY ) + { + /*Send the same data */ + USBH_BulkSendData (pdev, (CDC_TxParam.pRxTxBuff), len, CDC_Machine.CDC_DataItf.hc_num_out); + } + break; + + case CDC_READ_DATA: + break; + + case CDC_BUSY: + break; + + case CDC_GET_DATA: + break; + + case CDC_POLL: + break; + + case CDC_CTRL_STATE: + break; + } +} + +/** +*\*\name CDC_ProcessReception. +*\*\fun This function responsible for reception of data from the device. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return none. +*\*\ +**/ +static void CDC_ProcessReception(USB_CORE_MODULE *pdev, USBH_HOST *phost) +{ + if(RX_Enabled == 1) + { + URB_STATE URB_StatusRx = HOST_GetURB_State(pdev , CDC_Machine.CDC_DataItf.hc_num_in); + + switch(CDC_RxParam.CDCState) + { + case CDC_IDLE: + /*check the received length lesser then the remaining space available in the + buffer */ + if(CDC_RxParam.DataLength < (CDC_RxParam.BufferLen - CDC_Machine.CDC_DataItf.length)) + { + /*Receive the data */ + USBH_BulkReceiveData(pdev, CDC_RxParam.pFillBuff, CDC_Machine.CDC_DataItf.length, CDC_Machine.CDC_DataItf.hc_num_in); + + /*change the cdc state to USBH_CDC_GET_DATA*/ + CDC_RxParam.CDCState = CDC_GET_DATA; + } + break; + + case CDC_GET_DATA: + /*Check the last state of the device is URB_DONE */ + if(URB_StatusRx == URB_DONE) + { + /* Move the pointer as well as datalength */ + CDC_RxParam.DataLength += pdev->host.XferCnt[CDC_Machine.CDC_DataItf.hc_num_in]; + CDC_RxParam.pFillBuff += pdev->host.XferCnt[CDC_Machine.CDC_DataItf.hc_num_in]; + + + /* Process the recived data */ + CDC_ReceiveData(&CDC_RxParam); + + /*change the state od the CDC state*/ + CDC_RxParam.CDCState = CDC_IDLE; + } + break; + + case CDC_READ_DATA: + break; + + case CDC_BUSY: + break; + + case CDC_SEND_DATA: + break; + + case CDC_DATA_SENT: + break; + + case CDC_POLL: + break; + + case CDC_CTRL_STATE: + break; + } + } +} + + +/** +*\*\name CDC_InitTxRxParam. +*\*\fun Initialize the transmit and receive buffer and its parameter. +*\*\param none. +*\*\return none. +*\*\ +**/ +static void CDC_InitTxRxParam(void) +{ + /*Initialize the Transmit buffer and its parameter*/ + CDC_TxParam.CDCState = CDC_IDLE; + CDC_TxParam.DataLength = 0; + CDC_TxParam.pRxTxBuff = TxBuf; + + /*Initialize the Receive buffer and its parameter*/ + CDC_RxParam.CDCState = CDC_IDLE; + CDC_RxParam.DataLength = 0; + CDC_RxParam.pFillBuff = RxBuf; + CDC_RxParam.pEmptyBuff = RxBuf; + CDC_RxParam.BufferLen = sizeof(RxBuf); +} + +/** +*\*\name CDC_ReceiveData. +*\*\fun This is a call back function from cdc core layer to redirect the received data on the user out put system. +*\*\param cdc_Data: type of USBH_CDCXfer_TypeDef. +*\*\return none. +*\*\ +**/ +static void CDC_ReceiveData(CDC_Xfer_TypeDef *cdc_Data) +{ + uint8_t *ptr; + + if(cdc_Data->pEmptyBuff < cdc_Data->pFillBuff) + { + ptr = cdc_Data->pFillBuff; + *ptr = 0x00; + + /* redirect the received data on the user out put system */ + UserCb.Receive(cdc_Data->pEmptyBuff); + + cdc_Data->pFillBuff = cdc_Data->pEmptyBuff ; + cdc_Data->DataLength = 0; /*Reset the data length to zero*/ + } +} + + +/** +*\*\name CDC_SendData. +*\*\fun This function send data to the device. +*\*\param data : the pointer of send data +*\*\param length : length of data +*\*\return none. +**/ +void CDC_SendData(uint8_t *data, uint16_t length) +{ + if(CDC_TxParam.CDCState == CDC_IDLE) + { + CDC_TxParam.pRxTxBuff = data; + CDC_TxParam.DataLength = length; + CDC_TxParam.CDCState = CDC_SEND_DATA; + } +} + +/** +*\*\name CDC_StartReception. +*\*\fun CDC start reception. +*\*\param pdev: Selected device +*\*\return none. +**/ +void CDC_StartReception(USB_CORE_MODULE *pdev) +{ + RX_Enabled = 1; +} + +/** +*\*\name CDC_StopReception. +*\*\fun CDC stop reception. +*\*\param pdev: Selected device +*\*\return none. +**/ +void CDC_StopReception(USB_CORE_MODULE *pdev) +{ + RX_Enabled = 0; + USB_HCH_Halt(pdev, CDC_Machine.CDC_DataItf.hc_num_in); + USBH_Free_Channel(pdev,CDC_Machine.CDC_DataItf.hc_num_in); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_funct.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_funct.c new file mode 100644 index 0000000000..a8018a4e47 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/CDC/src/usbh_cdc_funct.c @@ -0,0 +1,151 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_cdc_funct.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbh_cdc_funct.h" + +CDC_InterfaceDesc_Typedef CDC_Desc; +CDC_LineCodingTypeDef CDC_GetLineCode; +CDC_LineCodingTypeDef CDC_SetLineCode; + +extern CDC_Requests CDC_ReqState; + +/** +*\*\name CDC_GETLineCoding. +*\*\fun This request allows the host to find out the currently configured line coding. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return status. +**/ +USBH_Status CDC_GETLineCoding(USB_CORE_MODULE *pdev , USBH_HOST *phost) +{ + phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_GET_LINE_CODING; + phost->Control.setup.b.wValue.w = 0; + phost->Control.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bMasterInterface; /*At to be checked*/ + phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + return USBH_CtrlReq(pdev, phost, CDC_GetLineCode.Array, LINE_CODING_STRUCTURE_SIZE); +} + +/** +*\*\name CDC_SETLineCoding. +*\*\fun This request allows the host to specify typical asynchronous line-character formatting properties. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return status. +**/ +USBH_Status CDC_SETLineCoding(USB_CORE_MODULE *pdev, USBH_HOST *phost) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_SET_LINE_CODING; + phost->Control.setup.b.wValue.w = 0; + + phost->Control.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bMasterInterface; + + phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + return USBH_CtrlReq(pdev, phost, CDC_SetLineCode.Array , LINE_CODING_STRUCTURE_SIZE ); +} + +/** +*\*\name CDC_SETControlLineState. +*\*\fun This request generates RS-232/V.24 style control signals. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return status. +**/ +USBH_Status CDC_SETControlLineState(USB_CORE_MODULE *pdev, USBH_HOST *phost) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = CDC_SET_CONTROL_LINE_STATE; + /*Control Signal Bitmap Values for SetControlLineState*/ + phost->Control.setup.b.wValue.w = CDC_DEACTIVATE_CARRIER_SIGNAL_RTS | CDC_DEACTIVATE_SIGNAL_DTR; + + phost->Control.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bMasterInterface; + + /*Length feild is zero*/ + phost->Control.setup.b.wLength.w = 0; + + return USBH_CtrlReq(pdev, phost, 0 , 0 ); +} + +/** +*\*\name CDC_ChangeStateToIssueSetConfig. +*\*\fun This function prepares the state before issuing the class specific commands. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return none. +**/ +void CDC_ChangeStateToIssueSetConfig(USB_CORE_MODULE *pdev, USBH_HOST *phost) +{ + phost->gStateBkp = phost->gState ; + phost->gState = HOST_CLASS_REQUEST; + CDC_ReqState = CDC_SET_LINE_CODING_RQUEST; +} + +/** +*\*\name CDC_ChangeStateToIssueSetConfig. +*\*\fun This function prepares the state before issuing the class specific commands. +*\*\param pdev: Selected device +*\*\param phost: Selected device property +*\*\return none. +**/ +void CDC_IssueGetConfig(USB_CORE_MODULE *pdev, USBH_HOST *phost) +{ + phost->gStateBkp = phost->gState ; + phost->gState = HOST_CLASS_REQUEST; + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_core.h new file mode 100644 index 0000000000..d2ad2564fd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_core.h @@ -0,0 +1,212 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hid_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_HID_CORE_H +#define __USBH_HID_CORE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" +#include "usbh_stdreq.h" +#include "usbhs_bsp.h" +#include "usbh_ioreq.h" +#include "usbh_hcs.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_CLASS + * @{ + */ + +/** @addtogroup USBH_HID_CLASS + * @{ + */ + +/** @defgroup USBH_HID_CORE + * @brief This file is the Header file for USBH_HID_CORE.c + * @{ + */ + + +/** @defgroup USBH_HID_CORE_Exported_Types + * @{ + */ + +#define HID_MIN_POLL 10 + +/* States for HID State Machine */ +typedef enum +{ + HID_IDLE= 0, + HID_SEND_DATA, + HID_BUSY, + HID_GET_DATA, + HID_SYNC, + HID_POLL, + HID_ERROR, +} +HID_State; + +typedef enum +{ + HID_REQ_IDLE = 0, + HID_REQ_GET_REPORT_DESC, + HID_REQ_GET_HID_DESC, + HID_REQ_SET_IDLE, + HID_REQ_SET_PROTOCOL, + HID_REQ_SET_REPORT, + +} +HID_CtlState; + +typedef struct HID_cb +{ + void (*Init) (void); + void (*Decode) (uint8_t *data); + +} HID_cb_TypeDef; + +typedef struct _HID_Report +{ + uint8_t ReportID; + uint8_t ReportType; + uint16_t UsagePage; + uint32_t Usage[2]; + uint32_t NbrUsage; + uint32_t UsageMin; + uint32_t UsageMax; + int32_t LogMin; + int32_t LogMax; + int32_t PhyMin; + int32_t PhyMax; + int32_t UnitExp; + uint32_t Unit; + uint32_t ReportSize; + uint32_t ReportCnt; + uint32_t Flag; + uint32_t PhyUsage; + uint32_t AppUsage; + uint32_t LogUsage; +} +HID_Report_TypeDef; + +/* Structure for HID process */ +typedef struct _HID_Process +{ + uint8_t buff[64]; + uint8_t hc_num_in; + uint8_t hc_num_out; + HID_State state; + uint8_t HIDIntOutEp; + uint8_t HIDIntInEp; + HID_CtlState ctl_state; + uint16_t length; + uint8_t ep_addr; + uint16_t poll; + __IO uint16_t timer; + HID_cb_TypeDef *cb; +} +HID_Machine_TypeDef; + +/** + * @} + */ + +/** @defgroup USBH_HID_CORE_Exported_Defines + * @{ + */ + +#define USB_HID_REQ_GET_REPORT 0x01 +#define USB_HID_GET_IDLE 0x02 +#define USB_HID_GET_PROTOCOL 0x03 +#define USB_HID_SET_REPORT 0x09 +#define USB_HID_SET_IDLE 0x0A +#define USB_HID_SET_PROTOCOL 0x0B +/** + * @} + */ + +/** @defgroup USBH_HID_CORE_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_HID_CORE_Exported_Variables + * @{ + */ +extern USBH_Class_cb_TypeDef USBH_HID_cb; +/** + * @} + */ + +/** @defgroup USBH_HID_CORE_Exported_FunctionsPrototype + * @{ + */ + +USBH_Status USBH_Set_Report (USB_CORE_MODULE *pdev, + USBH_HOST *phost, + uint8_t reportType, + uint8_t reportId, + uint8_t reportLen, + uint8_t* reportBuff); +/** + * @} + */ + + +#endif /* __USBH_HID_CORE_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_keyboard.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_keyboard.h new file mode 100644 index 0000000000..fb5eaf1494 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_keyboard.h @@ -0,0 +1,81 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hid_keyboard.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBH_HID_KEYBD_H +#define __USBH_HID_KEYBD_H + +#include "usbhs_conf.h" +#include "usbh_hid_core.h" + +#define QWERTY_KEYBOARD +//#define AZERTY_KEYBOARD + +#define KBD_LEFT_CTRL 0x01 +#define KBD_LEFT_SHIFT 0x02 +#define KBD_LEFT_ALT 0x04 +#define KBD_LEFT_GUI 0x08 +#define KBD_RIGHT_CTRL 0x10 +#define KBD_RIGHT_SHIFT 0x20 +#define KBD_RIGHT_ALT 0x40 +#define KBD_RIGHT_GUI 0x80 + +#define KBR_MAX_NBR_PRESSED 6 + +extern HID_cb_TypeDef HID_KEYBRD_cb; + +void USER_KEYBRD_Init (void); +void USER_KEYBRD_ProcessData (uint8_t pbuf); + +#endif /* __USBH_HID_KEYBD_H */ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_mouse.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_mouse.h new file mode 100644 index 0000000000..22dcd955ab --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/inc/usbh_hid_mouse.h @@ -0,0 +1,129 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hid_mouse.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_HID_MOUSE_H +#define __USBH_HID_MOUSE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_hid_core.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_CLASS + * @{ + */ + +/** @addtogroup USBH_HID_CLASS + * @{ + */ + +/** @defgroup USBH_HID_MOUSE + * @brief This file is the Header file for USBH_HID_MOUSE.c + * @{ + */ + + +/** @defgroup USBH_HID_MOUSE_Exported_Types + * @{ + */ +typedef struct _HID_MOUSE_Data +{ + uint8_t x; + uint8_t y; + uint8_t z; /* Not Supported */ + uint8_t button; +} +HID_MOUSE_Data_TypeDef; + +/** + * @} + */ + +/** @defgroup USBH_HID_MOUSE_Exported_Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_HID_MOUSE_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_HID_MOUSE_Exported_Variables + * @{ + */ + +extern HID_cb_TypeDef HID_MOUSE_cb; +extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data; +/** + * @} + */ + +/** @defgroup USBH_HID_MOUSE_Exported_FunctionsPrototype + * @{ + */ +void USER_MOUSE_Init (void); +void USER_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data); +/** + * @} + */ + +#endif /* __USBH_HID_MOUSE_H */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_core.c new file mode 100644 index 0000000000..6eb145c207 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_core.c @@ -0,0 +1,559 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hid_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Includes ------------------------------------------------------------------*/ +#include "usbh_hid_core.h" +#include "usbh_hid_mouse.h" +#include "usbh_hid_keyboard.h" +#include "usbhs_conf.h" +#include "n32h76x_78x_gpio.h" +#include "log.h" + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN HID_Machine_TypeDef HID_Machine __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN HID_Report_TypeDef HID_Report __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN USB_Setup_TypeDef HID_Setup __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN USBH_HIDDesc_TypeDef HID_Desc __ALIGN_END ; + +__IO uint8_t start_toggle = 0; + +static USBH_Status USBH_HID_InterfaceInit (USB_CORE_MODULE *pdev , void *phost); + +static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf); + +static void USBH_HID_InterfaceDeInit (USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status USBH_HID_Handle(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status USBH_HID_ClassRequest(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status USBH_Get_HID_ReportDescriptor (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint16_t length); + +static USBH_Status USBH_Get_HID_Descriptor (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint16_t length); + +static USBH_Status USBH_Set_Idle (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint8_t duration, uint8_t reportId); + +static USBH_Status USBH_Set_Protocol (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint8_t protocol); + + +USBH_Class_cb_TypeDef USBH_HID_cb = +{ + USBH_HID_InterfaceInit, + USBH_HID_InterfaceDeInit, + USBH_HID_ClassRequest, + USBH_HID_Handle +}; + +/** +*\*\name USBH_HID_InterfaceInit. +*\*\fun The function init the HID class. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_HID_InterfaceInit(USB_CORE_MODULE *pdev, void *phost) +{ + uint8_t maxEP; + USBH_HOST *pphost = phost; + + uint8_t num =0; + USBH_Status status = USBH_BUSY ; + HID_Machine.state = HID_ERROR; + + + if(pphost->device_prop.Itf_Desc[0].bInterfaceSubClass == HID_BOOT_CODE) + { + /*Decode Bootclass Protocol: Mouse or Keyboard*/ + if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_KEYBRD_BOOT_CODE) + { + HID_Machine.cb = &HID_KEYBRD_cb; + } + else if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_MOUSE_BOOT_CODE) + { + HID_Machine.cb = &HID_MOUSE_cb; + } + + HID_Machine.state = HID_IDLE; + HID_Machine.ctl_state = HID_REQ_IDLE; + HID_Machine.ep_addr = pphost->device_prop.Ep_Desc[0][0].bEndpointAddress; + HID_Machine.length = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize; + HID_Machine.poll = pphost->device_prop.Ep_Desc[0][0].bInterval ; + + if (HID_Machine.poll < HID_MIN_POLL) + { + HID_Machine.poll = HID_MIN_POLL; + } + + /* Check fo available number of endpoints */ + /* Find the number of EPs in the Interface Descriptor */ + /* Choose the lower number in order not to overrun the buffer allocated */ + maxEP = ( (pphost->device_prop.Itf_Desc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ? + pphost->device_prop.Itf_Desc[0].bNumEndpoints : USBH_MAX_NUM_ENDPOINTS); + + /* Decode endpoint IN and OUT address from interface descriptor */ + for (num=0; num < maxEP; num++) + { + if(pphost->device_prop.Ep_Desc[0][num].bEndpointAddress & 0x80) + { + HID_Machine.HIDIntInEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); + HID_Machine.hc_num_in = USBH_Alloc_Channel(pdev, pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); + + /* Open channel for IN endpoint */ + USBH_Open_Channel(pdev, + HID_Machine.hc_num_in, + pphost->device_prop.address, + pphost->device_prop.speed, + EP_TYPE_INTR, + HID_Machine.length); + } + else + { + HID_Machine.HIDIntOutEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); + HID_Machine.hc_num_out = USBH_Alloc_Channel(pdev, pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); + + /* Open channel for OUT endpoint */ + USBH_Open_Channel(pdev, + HID_Machine.hc_num_out, + pphost->device_prop.address, + pphost->device_prop.speed, + EP_TYPE_INTR, + HID_Machine.length); + } + } + + start_toggle =0; + status = USBH_OK; + } + else + { + if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_HUB) + { + log_info("Hub is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_CDCC) + { + log_info("Communications and CDC Control device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_MSC) + { + log_info("MSC device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_PRINTER) + { + log_info("Printer device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_SMARTCARD) + { + log_info("Smart Card device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_VIDEO) + { + log_info("Video device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_AVD) + { + log_info("Audio/Video Devices is not supported.\n"); + } + else + { + log_info("The attached device is not supported. \n"); + } + pphost->usr_cb->DeviceNotSupported(); + } + return status; +} + + + + +/** +*\*\name USBH_HID_InterfaceDeInit. +*\*\fun The function DeInit the Host Channels used for the HID class. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\return none. +*\*\ +**/ +void USBH_HID_InterfaceDeInit ( USB_CORE_MODULE *pdev, void *phost) +{ + if(HID_Machine.hc_num_in != 0x00) + { + USB_HCH_Halt(pdev, HID_Machine.hc_num_in); + USBH_Free_Channel(pdev, HID_Machine.hc_num_in); + HID_Machine.hc_num_in = 0; /* Reset the Channel as Free */ + } + + if(HID_Machine.hc_num_out != 0x00) + { + USB_HCH_Halt(pdev, HID_Machine.hc_num_out); + USBH_Free_Channel(pdev, HID_Machine.hc_num_out); + HID_Machine.hc_num_out = 0; /* Reset the Channel as Free */ + } + + start_toggle = 0; +} + +/** +*\*\name USBH_HID_ClassRequest. +*\*\fun The function is responsible for handling HID Class requests for HID class. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\return USBH_Status :Response for USB Set Protocol request. +*\*\ +**/ +static USBH_Status USBH_HID_ClassRequest(USB_CORE_MODULE *pdev , void *phost) +{ + USBH_HOST *pphost = phost; + + USBH_Status status = USBH_BUSY; + USBH_Status classReqStatus = USBH_BUSY; + + + /* Switch HID state machine */ + switch (HID_Machine.ctl_state) + { + case HID_IDLE: + case HID_REQ_GET_HID_DESC: + /* Get HID Desc */ + if (USBH_Get_HID_Descriptor (pdev, pphost, USB_HID_DESC_SIZE)== USBH_OK) + { + USBH_ParseHIDDesc(&HID_Desc, pdev->host.Rx_Buffer); + HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC; + } + break; + case HID_REQ_GET_REPORT_DESC: + /* Get Report Desc */ + if (USBH_Get_HID_ReportDescriptor(pdev , pphost, HID_Desc.wItemLength) == USBH_OK) + { + HID_Machine.ctl_state = HID_REQ_SET_IDLE; + } + + break; + + case HID_REQ_SET_IDLE: + classReqStatus = USBH_Set_Idle (pdev, pphost, 0, 0); + + /* set Idle */ + if (classReqStatus == USBH_OK) + { + HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; + } + else if(classReqStatus == USBH_NOT_SUPPORTED) + { + HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; + } + break; + + case HID_REQ_SET_PROTOCOL: + /* set protocol */ + if (USBH_Set_Protocol (pdev ,pphost, 0) == USBH_OK) + { + HID_Machine.ctl_state = HID_REQ_IDLE; + + /* all requests performed*/ + status = USBH_OK; + } + break; + + default: + break; + } + + return status; +} + +/** +*\*\name USBH_HID_Handle. +*\*\fun The function is for managing state machine for HID data transfers . +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_HID_Handle(USB_CORE_MODULE *pdev , void *phost) +{ + USBH_HOST *pphost = phost; + USBH_Status status = USBH_OK; + + switch (HID_Machine.state) + { + case HID_IDLE: + HID_Machine.cb->Init(); + HID_Machine.state = HID_SYNC; + + case HID_SYNC: + /* Sync with start of Even Frame */ + if(USB_IsEvenFrame(pdev) == TRUE) + { + HID_Machine.state = HID_GET_DATA; + } + break; + + case HID_GET_DATA: + USBH_InterruptReceiveData(pdev, HID_Machine.buff, HID_Machine.length, HID_Machine.hc_num_in); + start_toggle = 1; + HID_Machine.state = HID_POLL; + HID_Machine.timer = HOST_GetCurrentFrame(pdev); + break; + + case HID_POLL: + if(( HOST_GetCurrentFrame(pdev) - HID_Machine.timer) >= HID_Machine.poll) + { + HID_Machine.state = HID_GET_DATA; + } + else if(HOST_GetURB_State(pdev , HID_Machine.hc_num_in) == URB_DONE) + { + if(start_toggle == 1) /* handle data once */ + { + start_toggle = 0; + HID_Machine.cb->Decode(HID_Machine.buff); + } + } + else if(HOST_GetURB_State(pdev, HID_Machine.hc_num_in) == URB_STALL) /* IN Endpoint Stalled */ + { + /* Issue Clear Feature on interrupt IN endpoint */ + if( (USBH_ClrFeature(pdev, pphost, HID_Machine.ep_addr, HID_Machine.hc_num_in)) == USBH_OK) + { + /* Change state to issue next IN token */ + HID_Machine.state = HID_GET_DATA; + } + } + break; + + default: + break; + } + return status; +} + + + +/** +*\*\name USBH_Get_HID_ReportDescriptor. +*\*\fun Issue report Descriptor command to the device. Once the response received, parse the report descriptor and update the status. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\param Length : HID Report Descriptor Length +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_Get_HID_ReportDescriptor (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint16_t length) +{ + USBH_Status status; + + status = USBH_GetDescriptor(pdev, + phost, + USB_REQ_RECIPIENT_INTERFACE + | USB_REQ_TYPE_STANDARD, + USB_DESC_HID_REPORT, + pdev->host.Rx_Buffer, + length); + + /* HID report descriptor is available in pdev->host.Rx_Buffer. + In case of USB Boot Mode devices for In report handling , + HID report descriptor parsing is not required. + In case, for supporting Non-Boot Protocol devices and output reports, + user may parse the report descriptor*/ + + return status; +} + + +/** +*\*\name USBH_Get_HID_Descriptor. +*\*\fun Issue HID Descriptor command to the device. Once the response received, parse the report descriptor and update the status. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\param Length : HID Descriptor Length +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_Get_HID_Descriptor (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint16_t length) +{ + USBH_Status status; + + status = USBH_GetDescriptor(pdev, + phost, + USB_REQ_RECIPIENT_INTERFACE + | USB_REQ_TYPE_STANDARD, + USB_DESC_HID, + pdev->host.Rx_Buffer, + length); + + return status; +} + +/** +*\*\name USBH_Set_Idle. +*\*\fun Set Idle State. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\param duration: Duration for HID Idle request +*\*\param reportID: Targeted report ID for Set Idle request +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_Set_Idle (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint8_t duration, uint8_t reportId) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + + phost->Control.setup.b.bRequest = USB_HID_SET_IDLE; + phost->Control.setup.b.wValue.w = (duration << 8 ) | reportId; + + phost->Control.setup.b.wIndex.w = 0; + phost->Control.setup.b.wLength.w = 0; + + return USBH_CtrlReq(pdev, phost, 0 , 0 ); +} + +/** +*\*\name USBH_Set_Report. +*\*\fun Issues Set Report. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\param reportType : Report type to be sent +*\*\param reportID : Targeted report ID for Set Report request +*\*\param reportLen : Length of data report to be send +*\*\param reportBuff : Report Buffer +*\*\return status. +*\*\ +**/ +USBH_Status USBH_Set_Report (USB_CORE_MODULE *pdev, USBH_HOST *phost, uint8_t reportType, uint8_t reportId, uint8_t reportLen, uint8_t* reportBuff) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ + USB_REQ_TYPE_CLASS; + + phost->Control.setup.b.bRequest = USB_HID_SET_REPORT; + phost->Control.setup.b.wValue.w = (reportType << 8 ) | reportId; + + phost->Control.setup.b.wIndex.w = 0; + phost->Control.setup.b.wLength.w = reportLen; + + return USBH_CtrlReq(pdev, phost, reportBuff , reportLen ); +} + +/** +*\*\name USBH_Set_Protocol. +*\*\fun Set protocol State. +*\*\param pdev: selected device. +*\*\param phost: Selected device property +*\*\param protocol : Set Protocol for HID : boot/report protocol +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_Set_Protocol(USB_CORE_MODULE *pdev, USBH_HOST *phost, uint8_t protocol) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ + USB_REQ_TYPE_CLASS; + + phost->Control.setup.b.bRequest = USB_HID_SET_PROTOCOL; + + if(protocol != 0) + { + /* Boot Protocol */ + phost->Control.setup.b.wValue.w = 0; + } + else + { + /*Report Protocol*/ + phost->Control.setup.b.wValue.w = 1; + } + + phost->Control.setup.b.wIndex.w = 0; + phost->Control.setup.b.wLength.w = 0; + + return USBH_CtrlReq(pdev, phost, 0 , 0 ); +} + +/** +*\*\name USBH_ParseHIDDesc. +*\*\fun This function Parse the HID descriptor. +*\*\param desc: used to get the fields parsed from the data buffer. +*\*\param buf: Buffer where the source descriptor is available +*\*\return none. +*\*\ +**/ +static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf) +{ + desc->bLength = *(uint8_t *) (buf + 0); + desc->bDescriptorType = *(uint8_t *) (buf + 1); + desc->bcdHID = LE16 (buf + 2); + desc->bCountryCode = *(uint8_t *) (buf + 4); + desc->bNumDescriptors = *(uint8_t *) (buf + 5); + desc->bReportDescriptorType = *(uint8_t *) (buf + 6); + desc->wItemLength = LE16 (buf + 7); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_keyboard.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_keyboard.c new file mode 100644 index 0000000000..07c47d657e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_keyboard.c @@ -0,0 +1,291 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hid_keyboard.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbh_hid_keyboard.h" + +static void KEYBRD_Init (void); +static void KEYBRD_Decode(uint8_t *data); + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined (__CC_ARM) /*!< ARM Compiler */ + __align(4) + #elif defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #elif defined (__GNUC__) /*!< GNU Compiler */ + #pragma pack(4) + #endif /* __CC_ARM */ +#endif + +HID_cb_TypeDef HID_KEYBRD_cb= +{ + KEYBRD_Init, + KEYBRD_Decode +}; + +static const uint8_t HID_KEYBRD_Codes[] = { + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD +static const int8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const int8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const int8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1','\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const int8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; +#endif + +/** +*\*\name KEYBRD_Init. +*\*\fun Initialize the keyboard function. +*\*\param none. +*\*\return none. +*\*\ +**/ +static void KEYBRD_Init (void) +{ + /* Call User Init*/ + USER_KEYBRD_Init(); +} + +/** +*\*\name KEYBRD_Decode. +*\*\fun The function is to decode the pressed keys. +*\*\param pbuf: Pointer to the HID IN report data buffer. +*\*\return none. +*\*\ +**/ +static void KEYBRD_Decode(uint8_t *pbuf) +{ + static uint8_t shift; + static uint8_t keys[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_new[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_last[KBR_MAX_NBR_PRESSED]; + static uint8_t key_newest; + static uint8_t nbr_keys; + static uint8_t nbr_keys_new; + static uint8_t nbr_keys_last; + uint8_t ix; + uint8_t jx; + uint8_t error; + uint8_t output; + + nbr_keys = 0; + nbr_keys_new = 0; + nbr_keys_last = 0; + key_newest = 0x00; + + + /* Check if Shift key is pressed */ + if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) + { + shift = TRUE; + } + else + { + shift = FALSE; + } + + error = FALSE; + + /* Check for the value of pressed key */ + for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) + { + if ((pbuf[ix] == 0x01) || (pbuf[ix] == 0x02) || (pbuf[ix] == 0x03)) + { + error = TRUE; + } + } + + if (error == TRUE) + { + return; + } + + nbr_keys = 0; + nbr_keys_new = 0; + for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) + { + if (pbuf[ix] != 0) + { + keys[nbr_keys] = pbuf[ix]; + nbr_keys++; + for (jx = 0; jx < nbr_keys_last; jx++) + { + if (pbuf[ix] == keys_last[jx]) + { + break; + } + } + + if (jx == nbr_keys_last) + { + keys_new[nbr_keys_new] = pbuf[ix]; + nbr_keys_new++; + } + } + } + + if (nbr_keys_new == 1) + { + key_newest = keys_new[0]; + + if (shift == TRUE) + { + output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]]; + } + else + { + output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]]; + } + /* call user process handle */ + USER_KEYBRD_ProcessData(output); + } + else + { + key_newest = 0x00; + } + + nbr_keys_last = nbr_keys; + for (ix = 0; ix < KBR_MAX_NBR_PRESSED; ix++) + { + keys_last[ix] = keys[ix]; + } +} + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_mouse.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_mouse.c new file mode 100644 index 0000000000..0ba7f61258 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/HID/src/usbh_hid_mouse.c @@ -0,0 +1,106 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hid_mouse.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbh_hid_mouse.h" + +static void MOUSE_Init (void); +static void MOUSE_Decode(uint8_t *data); + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined (__CC_ARM) /*!< ARM Compiler */ + __align(4) + #elif defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #elif defined (__GNUC__) /*!< GNU Compiler */ + #pragma pack(4) + #endif /* __CC_ARM */ +#endif + + +HID_MOUSE_Data_TypeDef HID_MOUSE_Data; +HID_cb_TypeDef HID_MOUSE_cb = +{ + MOUSE_Init, + MOUSE_Decode, +}; + +/** +*\*\name MOUSE_Init. +*\*\fun Init Mouse State. +*\*\param none. +*\*\return none. +*\*\ +**/ +static void MOUSE_Init(void) +{ + /* Call User Init*/ + USER_MOUSE_Init(); +} + +/** +*\*\name MOUSE_Decode. +*\*\fun Decode Mouse data. +*\*\param data: Pointer to Mouse HID data buffer. +*\*\return none. +*\*\ +**/ +static void MOUSE_Decode(uint8_t *data) +{ + HID_MOUSE_Data.button = data[0]; + + HID_MOUSE_Data.x = data[1]; + HID_MOUSE_Data.y = data[2]; + + USER_MOUSE_ProcessData(&HID_MOUSE_Data); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_bot.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_bot.h new file mode 100644 index 0000000000..c0a9d7bc71 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_bot.h @@ -0,0 +1,236 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_bot.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_MSC_BOT_H__ +#define __USBH_MSC_BOT_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_stdreq.h" + + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_CLASS + * @{ + */ + +/** @addtogroup USBH_MSC_CLASS + * @{ + */ + +/** @defgroup USBH_MSC_BOT + * @brief This file is the Header file for usbh_msc_core.c + * @{ + */ + + +/** @defgroup USBH_MSC_BOT_Exported_Types + * @{ + */ + +typedef union _USBH_CBW_Block +{ + struct __CBW + { + uint32_t CBWSignature; + uint32_t CBWTag; + uint32_t CBWTransferLength; + uint8_t CBWFlags; + uint8_t CBWLUN; + uint8_t CBWLength; + uint8_t CBWCB[16]; +}field; + uint8_t CBWArray[31]; +}HostCBWPkt_TypeDef; + +typedef enum +{ + USBH_MSC_BOT_INIT_STATE = 0, + USBH_MSC_BOT_RESET, + USBH_MSC_GET_MAX_LUN, + USBH_MSC_TEST_UNIT_READY, + USBH_MSC_READ_CAPACITY10, + USBH_MSC_MODE_SENSE6, + USBH_MSC_REQUEST_SENSE, + USBH_MSC_BOT_USB_TRANSFERS, + USBH_MSC_DEFAULT_APPLI_STATE, + USBH_MSC_CTRL_ERROR_STATE, + USBH_MSC_UNRECOVERED_STATE +} +MSCState; + + +typedef struct _BOTXfer +{ +uint8_t MSCState; +uint8_t MSCStateBkp; +uint8_t MSCStateCurrent; +uint8_t CmdStateMachine; +uint8_t BOTState; +uint8_t BOTStateBkp; +uint8_t* pRxTxBuff; +uint16_t DataLength; +uint8_t BOTXferErrorCount; +uint8_t BOTXferStatus; +} USBH_BOTXfer_TypeDef; + + +typedef union _USBH_CSW_Block +{ + struct __CSW + { + uint32_t CSWSignature; + uint32_t CSWTag; + uint32_t CSWDataResidue; + uint8_t CSWStatus; + }field; + uint8_t CSWArray[13]; +}HostCSWPkt_TypeDef; + +/** + * @} + */ + + + +/** @defgroup USBH_MSC_BOT_Exported_Defines + * @{ + */ +#define USBH_MSC_SEND_CBW 1 +#define USBH_MSC_SENT_CBW 2 +#define USBH_MSC_BOT_DATAIN_STATE 3 +#define USBH_MSC_BOT_DATAOUT_STATE 4 +#define USBH_MSC_RECEIVE_CSW_STATE 5 +#define USBH_MSC_DECODE_CSW 6 +#define USBH_MSC_BOT_ERROR_IN 7 +#define USBH_MSC_BOT_ERROR_OUT 8 + + +#define USBH_MSC_BOT_CBW_SIGNATURE 0x43425355 +#define USBH_MSC_BOT_CBW_TAG 0x20304050 +#define USBH_MSC_BOT_CSW_SIGNATURE 0x53425355 +#define USBH_MSC_CSW_DATA_LENGTH 0x000D +#define USBH_MSC_BOT_CBW_PACKET_LENGTH 31 +#define USBH_MSC_CSW_LENGTH 13 +#define USBH_MSC_CSW_MAX_LENGTH 63 + +/* CSW Status Definitions */ +#define USBH_MSC_CSW_CMD_PASSED 0x00 +#define USBH_MSC_CSW_CMD_FAILED 0x01 +#define USBH_MSC_CSW_PHASE_ERROR 0x02 + +#define USBH_MSC_SEND_CSW_DISABLE 0 +#define USBH_MSC_SEND_CSW_ENABLE 1 + +#define USBH_MSC_DIR_IN 0 +#define USBH_MSC_DIR_OUT 1 +#define USBH_MSC_BOTH_DIR 2 + +//#define USBH_MSC_PAGE_LENGTH 0x40 +#define USBH_MSC_PAGE_LENGTH 512 + + +#define CBW_CB_LENGTH 16 +#define CBW_LENGTH 10 +#define CBW_LENGTH_TEST_UNIT_READY 6 + +#define USB_REQ_BOT_RESET 0xFF +#define USB_REQ_GET_MAX_LUN 0xFE + +#define MAX_BULK_STALL_COUNT_LIMIT 0x04 /* If STALL is seen on Bulk + Endpoint continuously, this means + that device and Host has phase error + Hence a Reset is needed */ + +/** + * @} + */ + +/** @defgroup USBH_MSC_BOT_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_MSC_BOT_Exported_Variables + * @{ + */ +extern USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam; +extern HostCBWPkt_TypeDef USBH_MSC_CBWData; +extern HostCSWPkt_TypeDef USBH_MSC_CSWData; +/** + * @} + */ + +/** @defgroup USBH_MSC_BOT_Exported_FunctionsPrototype + * @{ + */ +void USBH_MSC_HandleBOTXfer(USB_CORE_MODULE *pdev, + USBH_HOST *phost); +uint8_t USBH_MSC_DecodeCSW(USB_CORE_MODULE *pdev, + USBH_HOST *phost); +void USBH_MSC_Init(USB_CORE_MODULE *pdev); +USBH_Status USBH_MSC_BOT_Abort(USB_CORE_MODULE *pdev, + USBH_HOST *phost, + uint8_t direction); +/** + * @} + */ + +#endif //__USBH_MSC_BOT_H__ + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_core.h new file mode 100644 index 0000000000..7b72fdfdf3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_core.h @@ -0,0 +1,155 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_MSC_CORE_H +#define __USBH_MSC_CORE_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" +#include "usbh_stdreq.h" +#include "usbhs_bsp.h" +#include "usbh_ioreq.h" +#include "usbh_hcs.h" +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bot.h" + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_CLASS + * @{ + */ + +/** @addtogroup USBH_MSC_CLASS + * @{ + */ + +/** @defgroup USBH_MSC_CORE + * @brief This file is the Header file for usbh_msc_core.c + * @{ + */ + + +/** @defgroup USBH_MSC_CORE_Exported_Types + * @{ + */ + + +/* Structure for MSC process */ +typedef struct _MSC_Process +{ + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t MSBulkOutEp; + uint8_t MSBulkInEp; + uint16_t MSBulkInEpSize; + uint16_t MSBulkOutEpSize; + uint8_t buff[USBH_MSC_MPS_SIZE]; + uint8_t maxLun; +} +MSC_Machine_TypeDef; + + +/** + * @} + */ + + + +/** @defgroup USBH_MSC_CORE_Exported_Defines + * @{ + */ + +#define USB_REQ_BOT_RESET 0xFF +#define USB_REQ_GET_MAX_LUN 0xFE + + +/** + * @} + */ + +/** @defgroup USBH_MSC_CORE_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup USBH_MSC_CORE_Exported_Variables + * @{ + */ +extern USBH_Class_cb_TypeDef USBH_MSC_cb; +extern MSC_Machine_TypeDef MSC_Machine; +extern uint8_t MSCErrorCount; + +/** + * @} + */ + +/** @defgroup USBH_MSC_CORE_Exported_FunctionsPrototype + * @{ + */ + + + +/** + * @} + */ + +#endif /* __USBH_MSC_CORE_H */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_scsi.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_scsi.h new file mode 100644 index 0000000000..2382890c2f --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/inc/usbh_msc_scsi.h @@ -0,0 +1,174 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_scsi.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Define to prevent recursive ----------------------------------------------*/ +#ifndef __USBH_MSC_SCSI_H__ +#define __USBH_MSC_SCSI_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_stdreq.h" + + +/** @addtogroup USBH_LIB + * @{ + */ + +/** @addtogroup USBH_CLASS + * @{ + */ + +/** @addtogroup USBH_MSC_CLASS + * @{ + */ + +/** @defgroup USBH_MSC_SCSI + * @brief This file is the Header file for usbh_msc_scsi.c + * @{ + */ + + +/** @defgroup USBH_MSC_SCSI_Exported_Types + * @{ + */ +typedef enum { + USBH_MSC_OK = 0, + USBH_MSC_FAIL = 1, + USBH_MSC_PHASE_ERROR = 2, + USBH_MSC_BUSY = 3 +}USBH_MSC_Status_TypeDef; + +typedef enum { + CMD_UNINITIALIZED_STATE =0, + CMD_SEND_STATE, + CMD_WAIT_STATUS +} CMD_STATES_TypeDef; + + + +typedef struct __MassStorageParameter +{ + uint32_t MSCapacity; + uint32_t MSSenseKey; + uint16_t MSPageLength; + uint8_t MSBulkOutEp; + uint8_t MSBulkInEp; + uint8_t MSWriteProtect; +} MassStorageParameter_TypeDef; +/** + * @} + */ + + + +/** @defgroup USBH_MSC_SCSI_Exported_Defines + * @{ + */ + + + +#define OPCODE_TEST_UNIT_READY 0X00 +#define OPCODE_READ_CAPACITY10 0x25 +#define OPCODE_MODE_SENSE6 0x1A +#define OPCODE_READ10 0x28 +#define OPCODE_WRITE10 0x2A +#define OPCODE_REQUEST_SENSE 0x03 + +#define DESC_REQUEST_SENSE 0X00 +#define ALLOCATION_LENGTH_REQUEST_SENSE 63 +#define XFER_LEN_READ_CAPACITY10 8 +#define XFER_LEN_MODE_SENSE6 63 + +#define MASK_MODE_SENSE_WRITE_PROTECT 0x80 +#define MODE_SENSE_PAGE_CONTROL_FIELD 0x00 +#define MODE_SENSE_PAGE_CODE 0x3F +#define DISK_WRITE_PROTECTED 0x01 +/** + * @} + */ + +/** @defgroup USBH_MSC_SCSI_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup _Exported_Variables + * @{ + */ +extern MassStorageParameter_TypeDef USBH_MSC_Param; +/** + * @} + */ + +/** @defgroup USBH_MSC_SCSI_Exported_FunctionsPrototype + * @{ + */ +uint8_t USBH_MSC_TestUnitReady(USB_CORE_MODULE *pdev); +uint8_t USBH_MSC_ReadCapacity10(USB_CORE_MODULE *pdev); +uint8_t USBH_MSC_ModeSense6(USB_CORE_MODULE *pdev); +uint8_t USBH_MSC_RequestSense(USB_CORE_MODULE *pdev); +uint8_t USBH_MSC_Write10(USB_CORE_MODULE *pdev, uint8_t *,uint32_t , + uint32_t ); +uint8_t USBH_MSC_Read10(USB_CORE_MODULE *pdev, + uint8_t *, + uint32_t , + uint32_t ); +void USBH_MSC_StateMachine(USB_CORE_MODULE *pdev); + +/** + * @} + */ + +#endif //__USBH_MSC_SCSI_H__ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_bot.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_bot.c new file mode 100644 index 0000000000..d2c8932baa --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_bot.c @@ -0,0 +1,618 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_bot.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bot.h" +#include "usbh_ioreq.h" +#include "usbh_def.h" +#include "usbhs_hcd_int.h" + + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN HostCSWPkt_TypeDef USBH_MSC_CSWData __ALIGN_END ; + + +static uint32_t BOTStallErrorCount; /* Keeps count of STALL Error Cases*/ +static uint8_t xfer_error_count; + + +USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam; + +/** +*\*\name USBH_MSC_Init. +*\*\fun Initializes the mass storage parameters. +*\*\param pdev: selected device. +*\*\return none. +*\*\ +**/ +void USBH_MSC_Init(USB_CORE_MODULE *pdev) +{ + if(HOST_IsDeviceConnected(pdev)) + { + USBH_MSC_CBWData.field.CBWSignature = USBH_MSC_BOT_CBW_SIGNATURE; + USBH_MSC_CBWData.field.CBWTag = USBH_MSC_BOT_CBW_TAG; + USBH_MSC_CBWData.field.CBWLUN = 0; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + } + + BOTStallErrorCount = 0; + MSCErrorCount = 0; +} + +/** +*\*\name USBH_MSC_HandleBOTXfer. +*\*\fun This function manages the different states of BOT transfer and updates the status to upper layer. +*\*\param pdev: selected device. +*\*\param phost: host state set. +*\*\return none. +*\*\ +**/ +void USBH_MSC_HandleBOTXfer (USB_CORE_MODULE *pdev ,USBH_HOST *phost) +{ + uint8_t xferDirection, index; + static uint32_t remainingDataLength; + static uint8_t *datapointer , *datapointer_prev; + static uint8_t error_direction; + USBH_Status status; + + URB_STATE URB_Status = URB_IDLE; + + if(HOST_IsDeviceConnected(pdev)) + { + + switch (USBH_MSC_BOTXferParam.BOTState) + { + case USBH_MSC_SEND_CBW: + /* send CBW */ + USBH_BulkSendData (pdev, + &USBH_MSC_CBWData.CBWArray[0], + USBH_MSC_BOT_CBW_PACKET_LENGTH , + MSC_Machine.hc_num_out); + + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_SEND_CBW; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SENT_CBW; + xfer_error_count= 0; + break; + + case USBH_MSC_SENT_CBW: + URB_Status = HOST_GetURB_State(pdev , MSC_Machine.hc_num_out); + + if(URB_Status == URB_DONE) + { + BOTStallErrorCount = 0; + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_SENT_CBW; + + /* If the CBW Pkt is sent successful, then change the state */ + xferDirection = (USBH_MSC_CBWData.field.CBWFlags & USB_REQ_DIR_MASK); + + if ( USBH_MSC_CBWData.field.CBWTransferLength != 0 ) + { + remainingDataLength = USBH_MSC_CBWData.field.CBWTransferLength ; + datapointer = USBH_MSC_BOTXferParam.pRxTxBuff; + datapointer_prev = datapointer; + + /* If there is Data Transfer Stage */ + if (xferDirection == USB_D2H) + { + /* Data Direction is IN */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_DATAIN_STATE; + } + else + { + /* Data Direction is OUT */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_DATAOUT_STATE; + } + } + + else + {/* If there is NO Data Transfer Stage */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE; + } + + } + else if(URB_Status == URB_NOTREADY) + { + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + else if(URB_Status == URB_STALL) + { + error_direction = USBH_MSC_DIR_OUT; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT; + } + else if(URB_Status == URB_ERROR) + { + xfer_error_count++; + + if (xfer_error_count < 3) + { + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + else + { + /* unrecoverd error */ + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; + } + } + break; + + case USBH_MSC_BOT_DATAIN_STATE: + URB_Status = HOST_GetURB_State(pdev , MSC_Machine.hc_num_in); + /* BOT DATA IN stage */ + if((URB_Status == URB_DONE) ||(USBH_MSC_BOTXferParam.BOTStateBkp != USBH_MSC_BOT_DATAIN_STATE)) + { + BOTStallErrorCount = 0; + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_BOT_DATAIN_STATE; + + if(remainingDataLength > MSC_Machine.MSBulkInEpSize) + { + USBH_BulkReceiveData (pdev, + datapointer, + MSC_Machine.MSBulkInEpSize , + MSC_Machine.hc_num_in); + + remainingDataLength -= MSC_Machine.MSBulkInEpSize; + datapointer = datapointer + MSC_Machine.MSBulkInEpSize; + } + else if ( remainingDataLength == 0) + { + /* If value was 0, and successful transfer, then change the state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE; + } + else + { + USBH_BulkReceiveData (pdev, + datapointer, + remainingDataLength , + MSC_Machine.hc_num_in); + + remainingDataLength = 0; /* Reset this value and keep in same state */ + } + } + else if(URB_Status == URB_STALL) + { + /* This is Data Stage STALL Condition */ + error_direction = USBH_MSC_DIR_IN; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_IN; + + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + 6.7.2 Host expects to receive data from the device + 3. On a STALL condition receiving data, then: + The host shall accept the data received. + The host shall clear the Bulk-In pipe. + 4. The host shall attempt to receive a CSW. + + USBH_MSC_BOTXferParam.BOTStateBkp is used to switch to the Original + state after the ClearFeature Command is issued. + */ + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; + + } + + else if(URB_Status == URB_ERROR) + { + xfer_error_count++; + + if (xfer_error_count < 3) + { + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + else + { + /* unrecoverd error */ + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; + } + } + break; + + case USBH_MSC_BOT_DATAOUT_STATE: + /* BOT DATA OUT stage */ + URB_Status = HOST_GetURB_State(pdev , MSC_Machine.hc_num_out); + if(URB_Status == URB_DONE) + { + BOTStallErrorCount = 0; + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_BOT_DATAOUT_STATE; + if(remainingDataLength > MSC_Machine.MSBulkOutEpSize) + { + USBH_BulkSendData (pdev, + datapointer, + MSC_Machine.MSBulkOutEpSize , + MSC_Machine.hc_num_out); + datapointer_prev = datapointer; + datapointer = datapointer + MSC_Machine.MSBulkOutEpSize; + + remainingDataLength = remainingDataLength - MSC_Machine.MSBulkOutEpSize; + xfer_error_count=0; + } + else if ( remainingDataLength == 0) + { + /* If value was 0, and successful transfer, then change the state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE; + } + else + { + USBH_BulkSendData (pdev, + datapointer, + remainingDataLength , + MSC_Machine.hc_num_out); + + remainingDataLength = 0; /* Reset this value and keep in same state */ + } + } + + else if(URB_Status == URB_NOTREADY) + { + if(datapointer != datapointer_prev) + { + USBH_BulkSendData (pdev, + (datapointer - MSC_Machine.MSBulkOutEpSize), + MSC_Machine.MSBulkOutEpSize , + MSC_Machine.hc_num_out); + } + else + { + USBH_BulkSendData (pdev, + datapointer, + MSC_Machine.MSBulkOutEpSize , + MSC_Machine.hc_num_out); + } + } + + else if(URB_Status == URB_STALL) + { + error_direction = USBH_MSC_DIR_OUT; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT; + + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + 6.7.3 Ho - Host expects to send data to the device + 3. On a STALL condition sending data, then: + " The host shall clear the Bulk-Out pipe. + 4. The host shall attempt to receive a CSW. + + The Above statement will do the clear the Bulk-Out pipe. + The Below statement will help in Getting the CSW. + + USBH_MSC_BOTXferParam.BOTStateBkp is used to switch to the Original + state after the ClearFeature Command is issued. + */ + + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; + + } + else if(URB_Status == URB_ERROR) + { + xfer_error_count++; + + if (xfer_error_count < 3) + { + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + else + { + /* unrecoverd error */ + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; + } + } + break; + + case USBH_MSC_RECEIVE_CSW_STATE: + /* BOT CSW stage */ + /* NOTE: We cannot reset the BOTStallErrorCount here as it may come from + the clearFeature from previous command */ + + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; + + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; + USBH_MSC_BOTXferParam.DataLength = USBH_MSC_CSW_MAX_LENGTH; + + for(index = USBH_MSC_CSW_LENGTH-1; index != 0; index--) + { + USBH_MSC_CSWData.CSWArray[index] = 0; + } + + USBH_MSC_CSWData.CSWArray[0] = 0; + + USBH_BulkReceiveData (pdev, + USBH_MSC_BOTXferParam.pRxTxBuff, + USBH_MSC_CSW_MAX_LENGTH , + MSC_Machine.hc_num_in); + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_DECODE_CSW; + xfer_error_count=0; + + break; + + case USBH_MSC_DECODE_CSW: + URB_Status = HOST_GetURB_State(pdev , MSC_Machine.hc_num_in); + /* Decode CSW */ + if(URB_Status == URB_DONE) + { + BOTStallErrorCount = 0; + USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; + + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateCurrent ; + + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_DecodeCSW(pdev , phost); + } + else if(URB_Status == URB_STALL) + { + error_direction = USBH_MSC_DIR_IN; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_IN; + } + + else if(URB_Status == URB_ERROR) + { + xfer_error_count++; + + if (xfer_error_count < 3) + { + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + else + { + /* unrecovered error */ + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; + } + } + break; + + case USBH_MSC_BOT_ERROR_IN: + status = USBH_MSC_BOT_Abort(pdev, phost, USBH_MSC_DIR_IN); + if (status == USBH_OK) + { + /* Check if the error was due in Both the directions */ + if (error_direction == USBH_MSC_BOTH_DIR) + {/* If Both directions are Needed, Switch to OUT Direction */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT; + } + else + { + /* Switch Back to the Original State, In many cases this will be + USBH_MSC_RECEIVE_CSW_STATE state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + } + else if (status == USBH_UNRECOVERED_ERROR) + { + /* This means that there is a STALL Error limit, Do Reset Recovery */ + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; + } + break; + + case USBH_MSC_BOT_ERROR_OUT: + status = USBH_MSC_BOT_Abort(pdev,phost, USBH_MSC_DIR_OUT); + if ( status == USBH_OK) + { /* Switch Back to the Original State */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + else if (status == USBH_UNRECOVERED_ERROR) + { + /* This means that there is a STALL Error limit, Do Reset Recovery */ + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; + } + break; + + default: + break; + } + } +} + + +/** +*\*\name USBH_MSC_BOT_Abort. +*\*\fun This function manages the different Error handling for STALL. +*\*\param pdev: selected device. +*\*\param phost: host state set. +*\*\param direction : USBH_MSC_DIR_IN / USBH_MSC_DIR_OUT. +*\*\return status. +*\*\ +**/ +USBH_Status USBH_MSC_BOT_Abort(USB_CORE_MODULE *pdev, USBH_HOST *phost, uint8_t direction) +{ + USBH_Status status; + + status = USBH_BUSY; + + switch (direction) + { + case USBH_MSC_DIR_IN : + /* send ClrFeture on Bulk IN endpoint */ + status = USBH_ClrFeature(pdev, + phost, + MSC_Machine.MSBulkInEp, + MSC_Machine.hc_num_in); + + break; + + case USBH_MSC_DIR_OUT : + /*send ClrFeature on Bulk OUT endpoint */ + status = USBH_ClrFeature(pdev, + phost, + MSC_Machine.MSBulkOutEp, + MSC_Machine.hc_num_out); + break; + + default: + break; + } + + BOTStallErrorCount++; /* Check Continuous Number of times, STALL has Occurred */ + if (BOTStallErrorCount > MAX_BULK_STALL_COUNT_LIMIT ) + { + status = USBH_UNRECOVERED_ERROR; + } + + return status; +} + + +/** +*\*\name USBH_MSC_DecodeCSW. +*\*\fun This function decodes the CSW received by the device and updates the same to upper layer. +*\*\param pdev: selected device. +*\*\param phost: host state set. +*\*\return On success USBH_MSC_OK, on failure USBH_MSC_FAIL. +*\*\ +**/ +uint8_t USBH_MSC_DecodeCSW(USB_CORE_MODULE *pdev , USBH_HOST *phost) +{ + uint8_t status; + uint32_t dataXferCount = 0; + status = USBH_MSC_FAIL; + + if(HOST_IsDeviceConnected(pdev)) + { + /*Checking if the transfer length is different than 13*/ + dataXferCount = HOST_GetXferCnt(pdev, MSC_Machine.hc_num_in); + + if(dataXferCount != USBH_MSC_CSW_LENGTH) + { + /*(4) Hi > Dn (Host expects to receive data from the device, + Device intends to transfer no data) + (5) Hi > Di (Host expects to receive data from the device, + Device intends to send data to the host) + (9) Ho > Dn (Host expects to send data to the device, + Device intends to transfer no data) + (11) Ho > Do (Host expects to send data to the device, + Device intends to receive data from the host)*/ + + status = USBH_MSC_PHASE_ERROR; + } + else + { /* CSW length is Correct */ + + /* Check validity of the CSW Signature and CSWStatus */ + if(USBH_MSC_CSWData.field.CSWSignature == USBH_MSC_BOT_CSW_SIGNATURE) + {/* Check Condition 1. dCSWSignature is equal to 53425355h */ + + if(USBH_MSC_CSWData.field.CSWTag == USBH_MSC_CBWData.field.CBWTag) + { + /* Check Condition 3. dCSWTag matches the dCBWTag from the + corresponding CBW */ + + if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_OK) + { + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + + Hn Host expects no data transfers + Hi Host expects to receive data from the device + Ho Host expects to send data to the device + + Dn Device intends to transfer no data + Di Device intends to send data to the host + Do Device intends to receive data from the host + + Section 6.7 + (1) Hn = Dn (Host expects no data transfers, + Device intends to transfer no data) + (6) Hi = Di (Host expects to receive data from the device, + Device intends to send data to the host) + (12) Ho = Do (Host expects to send data to the device, + Device intends to receive data from the host) + + */ + + status = USBH_MSC_OK; + } + else if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_FAIL) + { + status = USBH_MSC_FAIL; + } + + else if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_PHASE_ERROR) + { + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + Section 6.7 + (2) Hn < Di ( Host expects no data transfers, + Device intends to send data to the host) + (3) Hn < Do ( Host expects no data transfers, + Device intends to receive data from the host) + (7) Hi < Di ( Host expects to receive data from the device, + Device intends to send data to the host) + (8) Hi <> Do ( Host expects to receive data from the device, + Device intends to receive data from the host) + (10) Ho <> Di (Host expects to send data to the device, + Di Device intends to send data to the host) + (13) Ho < Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + + status = USBH_MSC_PHASE_ERROR; + } + } /* CSW Tag Matching is Checked */ + } /* CSW Signature Correct Checking */ + else + { + /* If the CSW Signature is not valid, We Sall return the Phase Error to + Upper Layers for Reset Recovery */ + + status = USBH_MSC_PHASE_ERROR; + } + } /* CSW Length Check*/ + } + + USBH_MSC_BOTXferParam.BOTXferStatus = status; + return status; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_core.c new file mode 100644 index 0000000000..eb6bdc4fb1 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_core.c @@ -0,0 +1,458 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Includes ------------------------------------------------------------------*/ + +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bot.h" +#include "usbh_core.h" +#include "log.h" + + +#define USBH_MSC_ERROR_RETRY_LIMIT 10 + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN USB_Setup_TypeDef MSC_Setup __ALIGN_END ; +uint8_t MSCErrorCount = 0; + +static USBH_Status USBH_MSC_InterfaceInit(USB_CORE_MODULE *pdev , void *phost); + +static void USBH_MSC_InterfaceDeInit(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status USBH_MSC_Handle(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status USBH_MSC_ClassRequest(USB_CORE_MODULE *pdev , void *phost); + +static USBH_Status USBH_MSC_GETMaxLUN(USB_CORE_MODULE *pdev, USBH_HOST *phost); + +USBH_Class_cb_TypeDef USBH_MSC_cb = +{ + USBH_MSC_InterfaceInit, + USBH_MSC_InterfaceDeInit, + USBH_MSC_ClassRequest, + USBH_MSC_Handle, +}; + +void USBH_MSC_ErrorHandle(uint8_t status); + +/** +*\*\name USBH_MSC_InterfaceInit. +*\*\fun Interface initialization for MSC class. +*\*\param pdev: selected device. +*\*\param phost: Selected device property. +*\*\return Status of class request handled. +*\*\ +**/ +static USBH_Status USBH_MSC_InterfaceInit (USB_CORE_MODULE *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + + if((pphost->device_prop.Itf_Desc[0].bInterfaceClass == MSC_CLASS) && \ + (pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == MSC_PROTOCOL)) + { + if(pphost->device_prop.Ep_Desc[0][0].bEndpointAddress & 0x80) + { + MSC_Machine.MSBulkInEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress); + MSC_Machine.MSBulkInEpSize = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize; + } + else + { + MSC_Machine.MSBulkOutEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress); + MSC_Machine.MSBulkOutEpSize = pphost->device_prop.Ep_Desc[0] [0].wMaxPacketSize; + } + + if(pphost->device_prop.Ep_Desc[0][1].bEndpointAddress & 0x80) + { + MSC_Machine.MSBulkInEp = (pphost->device_prop.Ep_Desc[0][1].bEndpointAddress); + MSC_Machine.MSBulkInEpSize = pphost->device_prop.Ep_Desc[0][1].wMaxPacketSize; + } + else + { + MSC_Machine.MSBulkOutEp = (pphost->device_prop.Ep_Desc[0][1].bEndpointAddress); + MSC_Machine.MSBulkOutEpSize = pphost->device_prop.Ep_Desc[0][1].wMaxPacketSize; + } + + MSC_Machine.hc_num_out = USBH_Alloc_Channel(pdev, MSC_Machine.MSBulkOutEp); + MSC_Machine.hc_num_in = USBH_Alloc_Channel(pdev, MSC_Machine.MSBulkInEp); + + /* Open the new channels */ + USBH_Open_Channel (pdev, + MSC_Machine.hc_num_out, + pphost->device_prop.address, + pphost->device_prop.speed, + EP_TYPE_BULK, + MSC_Machine.MSBulkOutEpSize); + + USBH_Open_Channel (pdev, + MSC_Machine.hc_num_in, + pphost->device_prop.address, + pphost->device_prop.speed, + EP_TYPE_BULK, + MSC_Machine.MSBulkInEpSize); + } + + else + { + if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_HUB) + { + printf("Hub is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_CDCC) + { + printf("Communications and CDC Control device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_HID) + { + printf("HID device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_PRINTER) + { + printf("Printer device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_SMARTCARD) + { + printf("Smart Card device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_VIDEO) + { + printf("Video device is not supported.\n"); + } + else if (pphost->device_prop.Itf_Desc[0].bInterfaceClass == USB_AVD) + { + printf("Audio/Video Devices is not supported.\n"); + } + else + { + printf ("The attached device is not supported. \n"); + } + + pphost->usr_cb->DeviceNotSupported(); + } + + return USBH_OK ; + +} + + + +/** +*\*\name USBH_MSC_InterfaceDeInit. +*\*\fun De-Initialize interface by freeing host channels allocated to interface. +*\*\param pdev: selected device. +*\*\param phost: Selected device property. +*\*\return none. +*\*\ +**/ +void USBH_MSC_InterfaceDeInit ( USB_CORE_MODULE *pdev, void *phost) +{ + if ( MSC_Machine.hc_num_out) + { + USB_HCH_Halt(pdev, MSC_Machine.hc_num_out); + USBH_Free_Channel (pdev, MSC_Machine.hc_num_out); + MSC_Machine.hc_num_out = 0; /* Reset the Channel as Free */ + } + + if ( MSC_Machine.hc_num_in) + { + USB_HCH_Halt(pdev, MSC_Machine.hc_num_in); + USBH_Free_Channel (pdev, MSC_Machine.hc_num_in); + MSC_Machine.hc_num_in = 0; /* Reset the Channel as Free */ + } +} + + +/** +*\*\name USBH_MSC_ClassRequest. +*\*\fun This function will only initialize the MSC state machine. +*\*\param pdev: selected device. +*\*\param phost: Selected device property. +*\*\return Status of class request handled. +*\*\ +**/ +static USBH_Status USBH_MSC_ClassRequest(USB_CORE_MODULE *pdev , void *phost) +{ + USBH_Status status = USBH_OK ; + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_INIT_STATE; + + return status; +} + +/** +*\*\name USBH_MSC_Handle. +*\*\fun MSC state machine handler. +*\*\param pdev: selected device. +*\*\param phost: Selected device property. +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_MSC_Handle(USB_CORE_MODULE *pdev , void *phost) +{ + USBH_HOST *pphost = phost; + + USBH_Status status = USBH_BUSY; + uint8_t mscStatus = USBH_MSC_BUSY; + uint8_t appliStatus = 0; + + + static uint8_t maxLunExceed = FALSE; + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.MSCState) + { + case USBH_MSC_BOT_INIT_STATE: + USBH_MSC_Init(pdev); + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_GET_MAX_LUN; + break; + case USBH_MSC_GET_MAX_LUN: + /* Issue GetMaxLUN request */ + status = USBH_MSC_GETMaxLUN(pdev, phost); + + if(status == USBH_OK ) + { + MSC_Machine.maxLun = *(MSC_Machine.buff) ; + + /* If device has more that one logical unit then it is not supported */ + if((MSC_Machine.maxLun > 0) && (maxLunExceed == FALSE)) + { + maxLunExceed = TRUE; + pphost->usr_cb->DeviceNotSupported(); + + break; + } + + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_TEST_UNIT_READY; + } + if(status == USBH_NOT_SUPPORTED ) + { + /* If the Command has failed, then we need to move to Next State, after + STALL condition is cleared by Control-Transfer */ + USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_TEST_UNIT_READY; + /* a Clear Feature should be issued here */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_CTRL_ERROR_STATE; + } + break; + + case USBH_MSC_CTRL_ERROR_STATE: + /* Issue Clearfeature request */ + status = USBH_ClrFeature(pdev, + phost, + 0x00, + pphost->Control.hch_num_out); + if(status == USBH_OK ) + { + /* If GetMaxLun Request not support, assume Single LUN configuration */ + MSC_Machine.maxLun = 0; + + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; + } + break; + + case USBH_MSC_TEST_UNIT_READY: + /* Issue SCSI command TestUnitReady */ + mscStatus = USBH_MSC_TestUnitReady(pdev); + + if(mscStatus == USBH_MSC_OK ) + { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_READ_CAPACITY10; + MSCErrorCount = 0; + status = USBH_OK; + } + else + { + USBH_MSC_ErrorHandle(mscStatus); + } + break; + + case USBH_MSC_READ_CAPACITY10: + /* Issue READ_CAPACITY10 SCSI command */ + mscStatus = USBH_MSC_ReadCapacity10(pdev); + if(mscStatus == USBH_MSC_OK ) + { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_MODE_SENSE6; + MSCErrorCount = 0; + status = USBH_OK; + } + else + { + USBH_MSC_ErrorHandle(mscStatus); + } + break; + + case USBH_MSC_MODE_SENSE6: + /* Issue ModeSense6 SCSI command for detecting if device is write-protected */ + mscStatus = USBH_MSC_ModeSense6(pdev); + if(mscStatus == USBH_MSC_OK ) + { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_DEFAULT_APPLI_STATE; + MSCErrorCount = 0; + status = USBH_OK; + } + else + { + USBH_MSC_ErrorHandle(mscStatus); + } + break; + + case USBH_MSC_BOT_USB_TRANSFERS: + /* Process the BOT state machine */ + USBH_MSC_HandleBOTXfer(pdev,phost); + break; + + case USBH_MSC_DEFAULT_APPLI_STATE: + /* Process Application callback for MSC */ + appliStatus = pphost->usr_cb->UserApplication(); + if(appliStatus == 0) + { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_DEFAULT_APPLI_STATE; + } + else if (appliStatus == 1) + { + /* De-init requested from application layer */ + status = USBH_APPLY_DEINIT; + } + break; + + case USBH_MSC_UNRECOVERED_STATE: + status = USBH_UNRECOVERED_ERROR; + break; + + case USBH_MSC_REQUEST_SENSE: + /* Issue RequestSense SCSI command for retrieving error code */ + mscStatus = USBH_MSC_RequestSense(pdev); + if(mscStatus == USBH_MSC_OK ) + { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; + status = USBH_OK; + } + else + { + USBH_MSC_ErrorHandle(mscStatus); + } + break; + default: + break; + } + } + return status; +} + + + +/** +*\*\name USBH_MSC_GETMaxLUN. +*\*\fun This request is used to reset the mass storage device and its associated interface. This class-specific request shall ready the device for the next CBW from the host. +*\*\param pdev: selected device. +*\*\param phost: Selected device property. +*\*\return status: USB ctrl xfer status. +*\*\ +**/ +static USBH_Status USBH_MSC_GETMaxLUN(USB_CORE_MODULE *pdev , USBH_HOST *phost) +{ + phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | USB_REQ_RECIPIENT_INTERFACE; + + phost->Control.setup.b.bRequest = USB_REQ_GET_MAX_LUN; + phost->Control.setup.b.wValue.w = 0; + phost->Control.setup.b.wIndex.w = 0; + phost->Control.setup.b.wLength.w = 1; + + return USBH_CtrlReq(pdev, phost, MSC_Machine.buff , 1 ); +} + +/** +*\*\name USBH_MSC_ErrorHandle. +*\*\fun The function is for handling errors occurring during the MSC state machine. +*\*\param status: selected device. +*\*\return none: USB ctrl xfer status. +*\*\ +**/ +void USBH_MSC_ErrorHandle(uint8_t status) +{ + if(status == USBH_MSC_FAIL) + { + MSCErrorCount++; + if(MSCErrorCount < USBH_MSC_ERROR_RETRY_LIMIT) + { /* Try MSC level error recovery, Issue the request Sense to get + Drive error reason */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_REQUEST_SENSE; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + } + else + { + /* Error trials exceeded the limit, go to unrecovered state */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_UNRECOVERED_STATE; + } + } + else if(status == USBH_MSC_PHASE_ERROR) + { + /* Phase error, Go to Unrecovered state */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_UNRECOVERED_STATE; + } + else if(status == USBH_MSC_BUSY) + { + /*No change in state*/ + } +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_fatfs.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_fatfs.c new file mode 100644 index 0000000000..ddd4d5a037 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_fatfs.c @@ -0,0 +1,235 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_fatfs.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbhs_conf.h" +#include "usbh_core.h" +#include "diskio.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bot.h" + +DWORD get_fattime(void); + +static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */ + +extern USB_CORE_MODULE USBHS_Core; +extern USBH_HOST USB_Host; + +/** +*\*\name disk_initialize. +*\*\fun Initialize Disk Drive. +*\*\param drv: Physical drive number. +*\*\return Stat. +*\*\ +**/ +DSTATUS disk_initialize(BYTE drv)/* Physical drive number (0) */ +{ + if(HOST_IsDeviceConnected(&USBHS_Core)) + { + Stat &= ~STA_NOINIT; + } + + return Stat; +} + +/** +*\*\name disk_status. +*\*\fun Get Disk Status. +*\*\param drv: Physical drive number. +*\*\return Stat. +*\*\ +**/ +DSTATUS disk_status(BYTE drv) /* Physical drive number (0) */ +{ + if (drv) return STA_NOINIT; /* Supports only single drive */ + return Stat; +} + +/** +*\*\name disk_read. +*\*\fun Read Sector(s). +*\*\param pdrv: Physical drive number. +*\*\param buff: Pointer to the data buffer to store read data. +*\*\param sector: Start sector number. +*\*\param count: Sector count. +*\*\return Stat. +*\*\ +**/ +DRESULT disk_read (BYTE pdrv, BYTE *buff, DWORD sector, UINT count) +{ + BYTE status = USBH_MSC_OK; + + if (pdrv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + + + if(HOST_IsDeviceConnected(&USBHS_Core)) + { + do + { + status = USBH_MSC_Read10(&USBHS_Core, buff,sector,512 * count); + USBH_MSC_HandleBOTXfer(&USBHS_Core ,&USB_Host); + + if(!HOST_IsDeviceConnected(&USBHS_Core)) + { + return RES_ERROR; + } + } + while(status == USBH_MSC_BUSY ); + } + if(status == USBH_MSC_OK) + return RES_OK; + return RES_ERROR; +} + +#if _READONLY == 0 + +/** +*\*\name disk_write. +*\*\fun Write Sector(s). +*\*\param pdrv: Physical drive number. +*\*\param buff: Pointer to the data buffer to be written. +*\*\param sector: Start sector number. +*\*\param count: Sector count. +*\*\return Stat. +*\*\ +**/ +DRESULT disk_write (BYTE pdrv, const BYTE *buff, DWORD sector, UINT count) +{ + BYTE status = USBH_MSC_OK; + if (pdrv || !count) return RES_PARERR; + if (Stat & STA_NOINIT) return RES_NOTRDY; + if (Stat & STA_PROTECT) return RES_WRPRT; + + + if(HOST_IsDeviceConnected(&USBHS_Core)) + { + do + { + status = USBH_MSC_Write10(&USBHS_Core,(BYTE*)buff,sector,512 * count); + USBH_MSC_HandleBOTXfer(&USBHS_Core, &USB_Host); + + if(!HOST_IsDeviceConnected(&USBHS_Core)) + { + return RES_ERROR; + } + } + while(status == USBH_MSC_BUSY ); + } + + if(status == USBH_MSC_OK) + return RES_OK; + return RES_ERROR; +} +#endif /* _READONLY == 0 */ + +#if _USE_IOCTL != 0 +/** +*\*\name disk_ioctl. +*\*\fun Miscellaneous Functions. +*\*\param pdrv: Physical drive number. +*\*\param ctrl: Control code. +*\*\param buff: Buffer to send/receive control data. +*\*\return res. +*\*\ +**/ +DRESULT disk_ioctl (BYTE drv, BYTE ctrl, void *buff) +{ + DRESULT res = RES_OK; + + if (drv) return RES_PARERR; + + res = RES_ERROR; + + if (Stat & STA_NOINIT) return RES_NOTRDY; + + switch (ctrl) + { + case CTRL_SYNC : /* Make sure that no pending write process */ + res = RES_OK; + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + + *(DWORD*)buff = (DWORD) USBH_MSC_Param.MSCapacity; + res = RES_OK; + break; + + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD*)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + *(DWORD*)buff = 512; + break; + + default: + res = RES_PARERR; + } + return res; +} + +/** +*\*\name get_fattime. +*\*\fun Gets Time from RTC . +*\*\param none. +*\*\return Time in DWORD. +*\*\ +**/ +DWORD get_fattime(void) +{ + return 0; +} + +#endif /* _USE_IOCTL != 0 */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_scsi.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_scsi.c new file mode 100644 index 0000000000..017084c486 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/class/MSC/src/usbh_msc_scsi.c @@ -0,0 +1,593 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_msc_scsi.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +/* Includes ------------------------------------------------------------------*/ +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bot.h" +#include "usbh_ioreq.h" +#include "usbh_def.h" + +MassStorageParameter_TypeDef USBH_MSC_Param; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBH_DataInBuffer[512] __ALIGN_END ; + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBH_DataOutBuffer[512] __ALIGN_END ; + +/** +*\*\name USBH_MSC_TestUnitReady. +*\*\fun Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer. +*\*\param pdev: selected device. +*\*\return status. +*\*\ +**/ +uint8_t USBH_MSC_TestUnitReady (USB_CORE_MODULE *pdev) +{ + uint8_t index; + USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.CmdStateMachine) + { + case CMD_SEND_STATE: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = 0; /* No Data Transfer */ + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH_TEST_UNIT_READY; + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; + USBH_MSC_BOTXferParam.DataLength = USBH_MSC_CSW_MAX_LENGTH; + USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_TEST_UNIT_READY; + + for(index = CBW_CB_LENGTH - 1; index != 0; index--) + { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_TEST_UNIT_READY; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; + /* Start the transfer, then let the state + machine magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) + { + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + break; + + default: + break; + } + } + return status; +} + + + +/** +*\*\name USBH_MSC_ReadCapacity10. +*\*\fun Issue the read capacity command to the device. Once the response received, it updates the status to upper layer. +*\*\param pdev: selected device. +*\*\return status. +*\*\ +**/ +uint8_t USBH_MSC_ReadCapacity10(USB_CORE_MODULE *pdev) +{ + uint8_t index; + USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.CmdStateMachine) + { + case CMD_SEND_STATE: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_READ_CAPACITY10; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer; + USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_READ_CAPACITY10; + + for(index = CBW_CB_LENGTH -1; index != 0; index--) + { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ_CAPACITY10; + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; + + /* Start the transfer, then let the state machine manage the other + transactions */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) + { + /*assign the capacity*/ + (((uint8_t*)&USBH_MSC_Param.MSCapacity )[3]) = USBH_DataInBuffer[0]; + (((uint8_t*)&USBH_MSC_Param.MSCapacity )[2]) = USBH_DataInBuffer[1]; + (((uint8_t*)&USBH_MSC_Param.MSCapacity )[1]) = USBH_DataInBuffer[2]; + (((uint8_t*)&USBH_MSC_Param.MSCapacity )[0]) = USBH_DataInBuffer[3]; + + /*assign the page length*/ + (((uint8_t*)&USBH_MSC_Param.MSPageLength )[1]) = USBH_DataInBuffer[6]; + (((uint8_t*)&USBH_MSC_Param.MSPageLength )[0]) = USBH_DataInBuffer[7]; + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + else + { + /* Wait for the Commands to get Completed */ + /* NO Change in state Machine */ + } + break; + + default: + break; + } + } + return status; +} + + + +/** +*\*\name USBH_MSC_ModeSense6. +*\*\fun Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device. +*\*\param pdev: selected device. +*\*\return status. +*\*\ +**/ +uint8_t USBH_MSC_ModeSense6(USB_CORE_MODULE *pdev) +{ + uint8_t index; + USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.CmdStateMachine) + { + case CMD_SEND_STATE: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_MODE_SENSE6; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer; + USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_MODE_SENSE6; + + for(index = CBW_CB_LENGTH - 1; index != 0; index--) + { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_MODE_SENSE6; + USBH_MSC_CBWData.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; + + USBH_MSC_CBWData.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; + + /* Start the transfer, then let the state machine manage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + break; + + case CMD_WAIT_STATUS: + if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) + { + /* Assign the Write Protect status */ + /* If WriteProtect = 0, Writing is allowed + If WriteProtect != 0, Disk is Write Protected */ + if ( USBH_DataInBuffer[2] & MASK_MODE_SENSE_WRITE_PROTECT) + { + USBH_MSC_Param.MSWriteProtect = DISK_WRITE_PROTECTED; + } + else + { + USBH_MSC_Param.MSWriteProtect = 0; + } + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + else + { + /* Wait for the Commands to get Completed */ + /* NO Change in state Machine */ + } + break; + + default: + break; + } + } + return status; +} + +/** +*\*\name USBH_MSC_RequestSense. +*\*\fun Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer. +*\*\param pdev: selected device. +*\*\return status. +*\*\ +**/ +uint8_t USBH_MSC_RequestSense(USB_CORE_MODULE *pdev) +{ + USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; + + uint8_t index; + + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.CmdStateMachine) + { + case CMD_SEND_STATE: + /*Prepare the CBW and relevant field*/ + USBH_MSC_CBWData.field.CBWTransferLength = \ + ALLOCATION_LENGTH_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer; + USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_BOTXferParam.MSCStateCurrent; + USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_REQUEST_SENSE; + + for(index = CBW_CB_LENGTH - 1; index != 0; index--) + { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWCB[1] = DESC_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; + /* Start the transfer, then let the state machine manage + the other transactions */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + + break; + + case CMD_WAIT_STATUS: + if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) + { + /* Get Sense data*/ + (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[3]) = USBH_DataInBuffer[0]; + (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[2]) = USBH_DataInBuffer[1]; + (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[1]) = USBH_DataInBuffer[2]; + (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[0]) = USBH_DataInBuffer[3]; + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_FAIL; + } + + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + + else + { + /* Wait for the Commands to get Completed */ + /* NO Change in state Machine */ + } + break; + + default: + break; + } + } + return status; +} + +/** +*\*\name USBH_MSC_Write10. +*\*\fun Issue the write command to the device. Once the response received, it updates the status to upper layer. +*\*\param pdev: selected device. +*\*\param dataBuffer : DataBuffer contains the data to write. +*\*\param address : Address to which the data will be written. +*\*\param nbOfbytes : NbOfbytes to be written. +*\*\return status. +*\*\ +**/ +uint8_t USBH_MSC_Write10(USB_CORE_MODULE *pdev, uint8_t *dataBuffer, uint32_t address, uint32_t nbOfbytes) +{ + uint8_t index; + USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; + uint16_t nbOfPages; + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.CmdStateMachine) + { + case CMD_SEND_STATE: + USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; + + + for(index = CBW_CB_LENGTH - 1; index != 0; index--) + { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_WRITE10; + + /*logical block address*/ + USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t*)&address)[3]) ; + USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t*)&address)[2]); + USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t*)&address)[1]); + USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t*)&address)[0]); + + /*USBH_MSC_PAGE_LENGTH = 512*/ + nbOfPages = nbOfbytes/ USBH_MSC_PAGE_LENGTH; + + /*Transfer length */ + USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; + USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; + + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; + /* Start the transfer, then let the state machine + manage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + + break; + + case CMD_WAIT_STATUS: + if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) + { + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + break; + + default: + break; + } + } + return status; +} + + +/** +*\*\name USBH_MSC_Read10. +*\*\fun Issue the read command to the device. Once the response received, it updates the status to upper layer. +*\*\param pdev: selected device. +*\*\param dataBuffer : DataBuffer contains the data to read. +*\*\param address : Address to which the data will be read. +*\*\param nbOfbytes : NbOfbytes to be read. +*\*\return status. +*\*\ +**/ +uint8_t USBH_MSC_Read10(USB_CORE_MODULE *pdev, uint8_t *dataBuffer, uint32_t address, uint32_t nbOfbytes) +{ + uint8_t index; + static USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; + uint16_t nbOfPages; + status = USBH_MSC_BUSY; + + if(HOST_IsDeviceConnected(pdev)) + { + switch(USBH_MSC_BOTXferParam.CmdStateMachine) + { + case CMD_SEND_STATE: + /*Prepare the CBW and relevant field*/ + USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; + + for(index = CBW_CB_LENGTH - 1; index != 0; index--) + { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ10; + + /*logical block address*/ + + USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t*)&address)[3]); + USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t*)&address)[2]); + USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t*)&address)[1]); + USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t*)&address)[0]); + + /*USBH_MSC_PAGE_LENGTH = 512*/ + nbOfPages = nbOfbytes/ USBH_MSC_PAGE_LENGTH; + + /*Transfer length */ + USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; + USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; + + + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; + /* Start the transfer, then let the state machine + manage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; + + status = USBH_MSC_BUSY; + + break; + + case CMD_WAIT_STATUS: + if((USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) && (HOST_IsDeviceConnected(pdev))) + { + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_OK; + } + else if ((USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) && (HOST_IsDeviceConnected(pdev))) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + } + else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) + { + /* Failure Mode */ + USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; + status = USBH_MSC_PHASE_ERROR; + } + else + { + /* Wait for the Commands to get Completed */ + /* NO Change in state Machine */ + } + break; + + default: + break; + } + } + return status; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_core.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_core.h new file mode 100644 index 0000000000..1936898201 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_core.h @@ -0,0 +1,250 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_core.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBH_CORE_H__ +#define __USBH_CORE_H__ + +/* Includes ------------------------------------------------------------------*/ +#include "usbhs_hcd.h" +#include "usbh_def.h" +#include "usbh_conf.h" +#include "usbhs_core.h" + + +#define MSC_CLASS 0x08 /* MSC */ +#define HID_CLASS 0x03 /* HID */ + +#define USB_AUDIO 0x01 /* Audio */ +#define USB_CDCC 0x02 /* Communications and CDC Control */ +#define USB_HID 0x03 /* HID (Human Interface Device) */ +#define USB_PRINTER 0x07 /* Printer */ +#define USB_MSC 0x08 /* Mass Storage */ +#define USB_HUB 0x09 /* Hub */ +#define USB_CDCD 0x0A /* CDC-Data */ +#define USB_SMARTCARD 0x0B /* Smart Card */ +#define USB_VIDEO 0x0E /* Video */ +#define USB_AVD 0x10 /* Audio/Video Devices */ + + + +#define MSC_PROTOCOL 0x50 +#define CBI_PROTOCOL 0x01 + + +#define USBH_MAX_ERROR_COUNT 2 +#define USBH_DEVICE_ADDRESS_DEFAULT 0 +#define USBH_DEVICE_ADDRESS 1 +#define CFG_DESC_MAX_SIZE 512 + + +typedef enum +{ + USBH_OK = 0, + USBH_BUSY, + USBH_FAIL, + USBH_NOT_SUPPORTED, + USBH_UNRECOVERED_ERROR, + USBH_ERROR_SPEED_UNKNOWN, + USBH_APPLY_DEINIT +}USBH_Status; + +/* Following states are used for gState */ +typedef enum +{ + HOST_IDLE =0, + HOST_WAIT_PRT_ENABLED, + HOST_DEV_ATTACHED, + HOST_DEV_DISCONNECTED, + HOST_DETECT_DEVICE_SPEED, + HOST_ENUMERATION, + HOST_CLASS_REQUEST, + HOST_CLASS, + HOST_CTRL_XFER, + HOST_USR_INPUT, + HOST_SUSPENDED, + HOST_WAKEUP, + HOST_ERROR_STATE +}HOST_State; + + +/* Following states are used for EnumerationState */ +typedef enum +{ + ENUM_IDLE = 0, + ENUM_GET_FULL_DEV_DESC, + ENUM_SET_ADDR, + ENUM_GET_CFG_DESC, + ENUM_GET_FULL_CFG_DESC, + ENUM_GET_MFC_STRING_DESC, + ENUM_GET_PRODUCT_STRING_DESC, + ENUM_GET_SERIALNUM_STRING_DESC, + ENUM_SET_CONFIGURATION, + ENUM_DEV_CONFIGURED +}ENUM_State; + + + +/* Following states are used for CtrlXferStateMachine */ +typedef enum +{ + CTRL_IDLE =0, + CTRL_SETUP, + CTRL_SETUP_WAIT, + CTRL_DATA_IN, + CTRL_DATA_IN_WAIT, + CTRL_DATA_OUT, + CTRL_DATA_OUT_WAIT, + CTRL_STATUS_IN, + CTRL_STATUS_IN_WAIT, + CTRL_STATUS_OUT, + CTRL_STATUS_OUT_WAIT, + CTRL_ERROR, + CTRL_STALLED, + CTRL_COMPLETE +}CTRL_State; + +typedef enum +{ + USBH_USER_NO_RESP = 0, + USBH_USER_RESP_OK = 1, +}USBH_USER_Status; + +/* Following states are used for RequestState */ +typedef enum +{ + CMD_IDLE =0, + CMD_SEND, + CMD_WAIT +}CMD_State; + +typedef struct +{ + uint8_t hch_num_in; + uint8_t hch_num_out; + uint8_t ep0size; + uint8_t *buff; + uint16_t length; + uint8_t errorcount; + uint16_t timer; + CTRL_STATUS status; + USB_Setup_TypeDef setup; + CTRL_State state; + +}USBH_Ctrl_TypeDef; + +typedef struct +{ + uint8_t address; + uint8_t speed; + USBH_DevDesc_TypeDef Dev_Desc; + USBH_CfgDesc_TypeDef Cfg_Desc; + USBH_InterfaceDesc_TypeDef Itf_Desc[USBH_MAX_NUM_INTERFACES]; + USBH_EpDesc_TypeDef Ep_Desc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]; + USBH_HIDDesc_TypeDef HID_Desc; +}USBH_Device_TypeDef; + +typedef struct +{ + USBH_Status (*Init)(USB_CORE_MODULE *USBx , void *phost); + void (*DeInit)(USB_CORE_MODULE *USBx , void *phost); + USBH_Status (*Requests)(USB_CORE_MODULE *USBx ,void *phost); + USBH_Status (*Machine)(USB_CORE_MODULE *USBx, void *phost); +}USBH_Class_cb_TypeDef; + + +typedef struct +{ + void (*Init)(void); /* HostLibInitialized */ + void (*DeInit)(void); /* HostLibInitialized */ + void (*DeviceAttached)(void); /* DeviceAttached */ + void (*ResetDevice)(void); + void (*DeviceDisconnected)(void); + void (*OverCurrentDetected)(void); + void (*DeviceSpeedDetected)(uint8_t DeviceSpeed); /* DeviceSpeed */ + void (*DeviceDescAvailable)(void *); /* DeviceDescriptor is available */ + void (*DeviceAddressAssigned)(void); /* Address is assigned to USB Device */ + void (*ConfigurationDescAvailable)(USBH_CfgDesc_TypeDef *, + USBH_InterfaceDesc_TypeDef *, + USBH_EpDesc_TypeDef *); + /* Configuration Descriptor available */ + void (*ManufacturerString)(void *); /* ManufacturerString*/ + void (*ProductString)(void *); /* ProductString*/ + void (*SerialNumString)(void *); /* SerialNubString*/ + void (*EnumerationDone)(void); /* Enumeration finished */ + USBH_USER_Status (*UserInput)(void); + int (*UserApplication) (void); + void (*DeviceNotSupported)(void); /* Device is not supported*/ + void (*UnrecoveredError)(void); +}USBH_User_cb_TypeDef; + +typedef struct +{ + HOST_State gState; /* Host State Machine Value */ + HOST_State gStateBkp; /* backup of previous State machine value */ + ENUM_State EnumState; /* Enumeration state Machine */ + CMD_State RequestState; + USBH_Ctrl_TypeDef Control; + + USBH_Device_TypeDef device_prop; + + USBH_Class_cb_TypeDef *class_cb; + USBH_User_cb_TypeDef *usr_cb; +} USBH_HOST; + +void USBH_Init(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID, USBH_HOST *host, USBH_Class_cb_TypeDef *class_cb, USBH_User_cb_TypeDef *user_cb); + +USBH_Status USBH_DeInit(USB_CORE_MODULE *USBx, USBH_HOST *phost); +void USBH_Main_Process(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID, USBH_HOST *phost); +void USBH_ErrorHandle(USBH_HOST *phost, USBH_Status errType); + +#endif /* __USBH_CORE_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_def.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_def.h new file mode 100644 index 0000000000..dfdad096a9 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_def.h @@ -0,0 +1,285 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_def.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBH_DEF_H__ +#define __USBH_DEF_H__ + +#include "n32h76x_78x.h" + +#ifndef USBH_NULL +#define USBH_NULL ((void *)0) +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + + +#define ValBit(VAR,POS) (VAR & (1 << POS)) +#define SetBit(VAR,POS) (VAR |= (1 << POS)) +#define ClrBit(VAR,POS) (VAR &= ((1 << POS)^255)) + +#define LE16(addr) (((u16)(*((u8 *)(addr)))) + (((u16)(*(((u8 *)(addr)) + 1))) << 8)) + +#define USB_LEN_DESC_HDR 0x02 +#define USB_LEN_DEV_DESC 0x12 +#define USB_LEN_CFG_DESC 0x09 +#define USB_LEN_IF_DESC 0x09 +#define USB_LEN_EP_DESC 0x07 +#define USB_LEN_SETUP_PKT 0x08 + +/* bmRequestType :D7 Data Phase Transfer Direction */ +#define USB_REQ_DIR_MASK 0x80 +#define USB_H2D 0x00 +#define USB_D2H 0x80 + +/* bmRequestType D6..5 Type */ +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_RESERVED 0x60 + +/* bmRequestType D4..0 Recipient */ +#define USB_REQ_RECIPIENT_DEVICE 0x00 +#define USB_REQ_RECIPIENT_INTERFACE 0x01 +#define USB_REQ_RECIPIENT_ENDPOINT 0x02 +#define USB_REQ_RECIPIENT_OTHER 0x03 + +/* Table 9-4. Standard Request Codes */ +/* bRequest , Value */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +/* Table 9-5. Descriptor Types of USB Specifications */ +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 +#define USB_DESC_TYPE_INTERFACE_POWER 8 +#define USB_DESC_TYPE_HID 0x21 +#define USB_DESC_TYPE_HID_REPORT 0x22 + + +#define USB_DEVICE_DESC_SIZE 18 +#define USB_CONFIGURATION_DESC_SIZE 9 +#define USB_HID_DESC_SIZE 9 +#define USB_INTERFACE_DESC_SIZE 9 +#define USB_ENDPOINT_DESC_SIZE 7 + +/* Descriptor Type and Descriptor Index */ +/* Use the following values when calling the function USBH_GetDescriptor */ +#define USB_DESC_DEVICE ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00) +#define USB_DESC_CONFIGURATION ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00) +#define USB_DESC_STRING ((USB_DESC_TYPE_STRING << 8) & 0xFF00) +#define USB_DESC_INTERFACE ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00) +#define USB_DESC_ENDPOINT ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00) +#define USB_DESC_DEVICE_QUALIFIER ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00) +#define USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00) +#define USB_DESC_INTERFACE_POWER ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00) +#define USB_DESC_HID_REPORT ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00) +#define USB_DESC_HID ((USB_DESC_TYPE_HID << 8) & 0xFF00) + + +#define USB_EP_TYPE_CTRL 0x00 +#define USB_EP_TYPE_ISOC 0x01 +#define USB_EP_TYPE_BULK 0x02 +#define USB_EP_TYPE_INTR 0x03 + +#define USB_EP_DIR_OUT 0x00 +#define USB_EP_DIR_IN 0x80 +#define USB_EP_DIR_MSK 0x80 + +/* supported classes */ +#define USB_MSC_CLASS 0x08 +#define USB_HID_CLASS 0x03 + +/* Interface Descriptor field values for HID Boot Protocol */ +#define HID_BOOT_CODE 0x01 +#define HID_KEYBRD_BOOT_CODE 0x01 +#define HID_MOUSE_BOOT_CODE 0x02 + +/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec + Standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000 +#define NODATA_STAGE_TIMEOUT 50 + +/** + * @} + */ + + +#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE + USB_INTERFACE_DESC_SIZE + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE)) + +#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.ConfigurationDescriptor.wTotalLength) + +/* This Union is copied from usbhs_core.h */ +typedef union +{ + uint16_t w; + struct BW + { + uint8_t msb; + uint8_t lsb; + } + bw; +}uint16_t_uint8_t; + + +typedef union +{ + uint8_t d8[8]; + + struct _SetupPkt_Struc + { + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t_uint8_t wValue; + uint16_t_uint8_t wIndex; + uint16_t_uint8_t wLength; + } b; +}USB_Setup_TypeDef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; +}USBH_DescHeader_t; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; /* USB Specification Number which device complies too */ + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + /* If equal to Zero, each interface specifies its own class + code if equal to 0xFF, the class code is vendor specified. + Otherwise field is valid Class Code.*/ + uint8_t bMaxPacketSize; + uint16_t idVendor; /* Vendor ID (Assigned by USB Org) */ + uint16_t idProduct; /* Product ID (Assigned by Manufacturer) */ + uint16_t bcdDevice; /* Device Release Number */ + uint8_t iManufacturer; /* Index of Manufacturer String Descriptor */ + uint8_t iProduct; /* Index of Product String Descriptor */ + uint8_t iSerialNumber; /* Index of Serial Number String Descriptor */ + uint8_t bNumConfigurations; /* Number of Possible Configurations */ +}USBH_DevDesc_TypeDef; + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; /* Total Length of Data Returned */ + uint8_t bNumInterfaces; /* Number of Interfaces */ + uint8_t bConfigurationValue; /* Value to use as an argument to select this configuration*/ + uint8_t iConfiguration; /*Index of String Descriptor Describing this configuration */ + uint8_t bmAttributes; /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/ + uint8_t bMaxPower; /*Maximum Power Consumption */ +}USBH_CfgDesc_TypeDef; + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */ + uint8_t bCountryCode; /* specifies the transfer type. */ + uint8_t bNumDescriptors; /* specifies the transfer type. */ + uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */ + uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */ +}USBH_HIDDesc_TypeDef; + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; /* Value used to select alternative setting */ + uint8_t bNumEndpoints; /* Number of Endpoints used for this interface */ + uint8_t bInterfaceClass; /* Class Code (Assigned by USB Org) */ + uint8_t bInterfaceSubClass; /* Subclass Code (Assigned by USB Org) */ + uint8_t bInterfaceProtocol; /* Protocol Code */ + uint8_t iInterface; /* Index of String Descriptor Describing this interface */ + +}USBH_InterfaceDesc_TypeDef; + + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; /* indicates what endpoint this descriptor is describing */ + uint8_t bmAttributes; /* specifies the transfer type. */ + uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving */ + uint8_t bInterval; /* is used to specify the polling interval of certain transfers. */ +}USBH_EpDesc_TypeDef; +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_hcs.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_hcs.h new file mode 100644 index 0000000000..5537829d48 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_hcs.h @@ -0,0 +1,80 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hcs.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#ifndef __USBH_HCS_H__ +#define __USBH_HCS_H__ + +#include "usbh_core.h" + + +#define HC_MAX 16 + +#define HC_OK 0x0000 +#define HC_USED 0x8000 +#define HC_ERROR 0xFFFF +#define HC_USED_MASK 0x7FFF + + +uint8_t USBH_Alloc_Channel(USB_CORE_MODULE *USBx, uint8_t ep_addr); + +uint8_t USBH_Free_Channel(USB_CORE_MODULE *USBx, uint8_t idx); + +uint8_t USBH_DeAllocate_AllChannel(USB_CORE_MODULE *USBx); + +uint8_t USBH_Open_Channel(USB_CORE_MODULE *USBx, uint8_t ch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + +uint8_t USBH_Modify_Channel(USB_CORE_MODULE *USBx, uint8_t hch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + + +#endif /* __USBH_HCS_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_ioreq.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_ioreq.h new file mode 100644 index 0000000000..8620e08655 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_ioreq.h @@ -0,0 +1,85 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_ioreq.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBH_IOREQ_H__ +#define __USBH_IOREQ_H__ + +#include "usbhs_conf.h" +#include "usbh_core.h" +#include "usbh_def.h" + +#define USBH_SETUP_PKT_SIZE 8 +#define USBH_EP0_EP_NUM 0 +#define USBH_MAX_PACKET_SIZE 0x40 + +USBH_Status USBH_CtrlSendSetup(USB_CORE_MODULE *USBx, uint8_t *buff, uint8_t hch_num); + +USBH_Status USBH_CtrlSendData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num); + +USBH_Status USBH_CtrlReceiveData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num); + +USBH_Status USBH_BulkReceiveData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num); + +USBH_Status USBH_BulkSendData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num); + +USBH_Status USBH_InterruptReceiveData(USB_CORE_MODULE *USBx, uint8_t *buff, uint8_t length, uint8_t hch_num); + +USBH_Status USBH_InterruptSendData(USB_CORE_MODULE *USBx, uint8_t *buff, uint8_t length, uint8_t hch_num); + +USBH_Status USBH_CtrlReq(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t *buff,uint16_t length); + +USBH_Status USBH_IsocReceiveData(USB_CORE_MODULE *USBx, uint8_t *buff, uint32_t length, uint8_t hch_num); + +USBH_Status USBH_IsocSendData(USB_CORE_MODULE *USBx, uint8_t *buff, uint32_t length, uint8_t hch_num); + +#endif /* __USBH_IOREQ_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_stdreq.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_stdreq.h new file mode 100644 index 0000000000..ea5c77a330 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/inc/usbh_stdreq.h @@ -0,0 +1,96 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_stdreq.h + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#ifndef __USBH_STDREQ_H__ +#define __USBH_STDREQ_H__ + +#include "usbhs_conf.h" +#include "usbhs_hcd.h" +#include "usbh_core.h" +#include "usbh_def.h" + +/*Standard Feature Selector for clear feature command*/ +#define FEATURE_SELECTOR_ENDPOINT 0X00 +#define FEATURE_SELECTOR_DEVICE 0X01 + + +#define INTERFACE_DESC_TYPE 0x04 +#define ENDPOINT_DESC_TYPE 0x05 +#define INTERFACE_DESC_SIZE 0x09 + + +#define USBH_HID_CLASS 0x03 + +extern uint8_t USBH_CfgDesc[512]; + +USBH_Status USBH_GetDescriptor(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t req_type,uint16_t value_idx, uint8_t* buff, uint16_t length ); + +USBH_Status USBH_Get_DevDesc(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t length); + +USBH_Status USBH_Get_StringDesc(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length); + +USBH_Status USBH_SetCfg(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint16_t configuration_value); + +USBH_Status USBH_Get_CfgDesc(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint16_t length); + +USBH_Status USBH_SetAddress(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t DeviceAddress); + +USBH_Status USBH_ClrFeature(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t ep_num, uint8_t hch_num); + +USBH_Status USBH_SetInterface(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t ep_num, uint8_t altSetting); + +USBH_Status USBH_Issue_ClrFeature(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t ep_num); + +USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr); + +#endif /* __USBH_STDREQ_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_core.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_core.c new file mode 100644 index 0000000000..35effc44fb --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_core.c @@ -0,0 +1,825 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_core.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbh_ioreq.h" +#include "usbhs_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#include "usbhs_hcd_int.h" +#include "usbhs_hcd.h" +#include "n32h76x_78x_gpio.h" +#include "n32h76x_78x_pwr.h" +#include "n32h76x_78x_dbg.h" + +uint8_t USBH_Disconnected (USB_CORE_MODULE *USBx); +uint8_t USBH_Connected (USB_CORE_MODULE *USBx); +uint8_t USBH_SOF (USB_CORE_MODULE *USBx); +uint8_t USBH_PortEnabled (USB_CORE_MODULE *USBx); +uint8_t USBH_PortDisabled (USB_CORE_MODULE *USBx); + +USBHOST_INT_cb_TypeDef USBHOST_INT_cb = +{ + USBH_SOF, + USBH_Connected, + USBH_Disconnected, + USBH_PortEnabled, + USBH_PortDisabled +}; + +USBHOST_INT_cb_TypeDef *USBHOST_INT_fops = &USBHOST_INT_cb; + +__IO uint32_t suspend_flag = 0; + +static USBH_Status USBH_HandleEnum(USB_CORE_MODULE *USBx, USBH_HOST *host); +USBH_Status USBH_HandleControl(USB_CORE_MODULE *USBx, USBH_HOST *host); + +void USB_BSP_Resume(USB_CORE_MODULE *USBx); +void USB_BSP_Suspend(USB_CORE_MODULE *USBx); + +/** +*\*\name USBH_Connected. +*\*\fun USB Connect callback function from the Interrupt. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint8_t USBH_Connected(USB_CORE_MODULE *USBx) +{ + USBx->host.ConnSts = 1; + return 0; +} + +/** +*\*\name USBH_Connected. +*\*\fun USB Port Enable function. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint8_t USBH_PortEnabled(USB_CORE_MODULE *USBx) +{ + USBx->host.PortEnabled = 1; + return 0; +} + +/** +*\*\name USBH_PortDisabled. +*\*\fun USB Port Disable function. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint8_t USBH_PortDisabled(USB_CORE_MODULE *USBx) +{ + USBx->host.PortEnabled = 0; + return 0; +} + +/** +*\*\name USBH_Disconnected. +*\*\fun USB Disconnect callback function from the Interrupt. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint8_t USBH_Disconnected (USB_CORE_MODULE *USBx) +{ + USB_BSP_DriveVBUS(USBx,0); + /* Disable all interrupts. */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTEN, 0); + + /* Clear any pending interrupts. */ + USB_WRITE_REG32(&USBx->regs.GCSR->GINTSTS, 0xFFFFFFFF); + USB_EnableGlobalInt(USBx, DISABLE); + USBx->host.ConnSts = 0; + return 0; +} + +/** +*\*\name USBH_SOF. +*\*\fun USB SOF callback function from the Interrupt. +*\*\param USBx: selected device. +*\*\return Status. +*\*\ +**/ +uint8_t USBH_SOF (USB_CORE_MODULE *USBx) +{ + /* This callback could be used to implement a scheduler process */ + return 0; +} + +/** +*\*\name USBH_Init. +*\*\fun Host hardware and stack initializations . +*\*\param USBx: selected device. +*\*\param class_cb: Class callback structure address. +*\*\param user_cb: User callback structure address. +*\*\return none. +*\*\ +**/ +void USBH_Init(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID, USBH_HOST *host, USBH_Class_cb_TypeDef *class_cb, USBH_User_cb_TypeDef *user_cb) +{ + /* Hardware Init */ + USB_BSP_Init(); + + /* Host de-initializations */ + USBH_DeInit(USBx, host); + + /*Register class and user callbacks */ + host->class_cb = class_cb; + host->usr_cb = user_cb; + + /* Start the USB core */ + USBHOST_CoreInit(USBx, coreID); + + /* Upon Init call usr call back */ + host->usr_cb->Init(); + + /* Enable Interrupts */ + USB_BSP_EnableInterrupt(USBx, coreID); +} + +/** +*\*\name USBH_DeInit. +*\*\fun Re-Initialize Host. +*\*\param USBx: selected device. +*\*\param host: host state set. +*\*\return status: USBH_Status. +*\*\ +**/ +USBH_Status USBH_DeInit(USB_CORE_MODULE *USBx, USBH_HOST *host) +{ + /* Software Init */ + host->gState = HOST_IDLE; + host->gStateBkp = HOST_IDLE; + host->EnumState = ENUM_IDLE; + host->RequestState = CMD_SEND; + + host->Control.state = CTRL_SETUP; + host->Control.ep0size = USB_MAX_EP0_SIZE; + + host->device_prop.address = USBH_DEVICE_ADDRESS_DEFAULT; + host->device_prop.speed = HPCS_PRTSPD_FULL_SPEED; + + USBH_Free_Channel(USBx, host->Control.hch_num_in); + USBH_Free_Channel(USBx, host->Control.hch_num_out); + return USBH_OK; +} + +/** +*\*\name USBH_Main_Process. +*\*\fun USB Host core main state machine process +*\*\param USBx: selected device. +*\*\param host: host state set. +*\*\return none. +*\*\ +**/ +void USBH_Main_Process(USB_CORE_MODULE *USBx, USB_CORE_ID_TypeDef coreID, USBH_HOST *host) +{ + volatile USBH_Status status = USBH_FAIL; + + /* check for Host port events */ + if(((HOST_IsDeviceConnected(USBx) == 0) || (HOST_IsPortEnabled(USBx) == 0)) && (host->gState != HOST_IDLE)) + { + if(host->gState != HOST_DEV_DISCONNECTED) + { + host->gState = HOST_DEV_DISCONNECTED; + } + } + + switch (host->gState) + { + case HOST_IDLE: + if (HOST_IsDeviceConnected(USBx)) + { + host->gState = HOST_WAIT_PRT_ENABLED; + + /*wait denounce delay */ + USB_BSP_mDelay(100); + + /* Apply a port RESET */ + HOST_ResetPort(USBx); + + /* User RESET callback*/ + host->usr_cb->ResetDevice(); + } + break; + + case HOST_WAIT_PRT_ENABLED: + if (USBx->host.PortEnabled == 1) + { + host->gState = HOST_DEV_ATTACHED; + USB_BSP_mDelay(50); + } + break; + + case HOST_DEV_ATTACHED : + host->usr_cb->DeviceAttached(); + host->Control.hch_num_out = USBH_Alloc_Channel(USBx, 0x00); + host->Control.hch_num_in = USBH_Alloc_Channel(USBx, 0x80); + + /* Reset USB Device */ + if ( HOST_ResetPort(USBx) == 0) + { + host->usr_cb->ResetDevice(); + + /* Host is Now ready to start the Enumeration */ + host->device_prop.speed = HOST_GetCurrentSpeed(USBx); + + host->gState = HOST_ENUMERATION; + host->usr_cb->DeviceSpeedDetected(host->device_prop.speed); + + /* Open Control pipes */ + USBH_Open_Channel (USBx, + host->Control.hch_num_in, + host->device_prop.address, + host->device_prop.speed, + EP_TYPE_CTRL, + host->Control.ep0size); + + /* Open Control pipes */ + USBH_Open_Channel (USBx, + host->Control.hch_num_out, + host->device_prop.address, + host->device_prop.speed, + EP_TYPE_CTRL, + host->Control.ep0size); + } + break; + + case HOST_ENUMERATION: + /* Check for enumeration status */ + if (USBH_HandleEnum(USBx , host) == USBH_OK) + { + /* The function shall return USBH_OK when full enumeration is complete */ + + /* user callback for end of device basic enumeration */ + host->usr_cb->EnumerationDone(); + host->gState = HOST_USR_INPUT; + } + break; + + case HOST_USR_INPUT: + /*The function should return user response true to move to class state */ + if ( host->usr_cb->UserInput() == USBH_USER_RESP_OK) + { + if((host->class_cb->Init(USBx, host)) == USBH_OK) + { + host->gState = HOST_CLASS_REQUEST; + } + } + break; + + case HOST_CLASS_REQUEST: + /* process class standard control requests state machine */ + status = host->class_cb->Requests(USBx, host); + + if(status == USBH_OK) + { + host->gState = HOST_CLASS; + } + else + { + USBH_ErrorHandle(host, status); + } + break; + case HOST_CLASS: + /* process class state machine */ + status = host->class_cb->Machine(USBx, host); + USBH_ErrorHandle(host, status); + break; + + case HOST_CTRL_XFER: + /* process control transfer state machine */ + USBH_HandleControl(USBx, host); + break; + case HOST_ERROR_STATE: + /* Re-Initialize Host for new Enumeration */ + USBH_DeInit(USBx, host); + host->usr_cb->DeInit(); + host->class_cb->DeInit(USBx, &host->device_prop); + break; + + case HOST_DEV_DISCONNECTED : + /* Manage User disconnect operations*/ + host->usr_cb->DeviceDisconnected(); + + /* Re-Initialize Host for new Enumeration */ + USBH_DeInit(USBx, host); + host->usr_cb->DeInit(); + host->class_cb->DeInit(USBx, &host->device_prop); + USBH_DeAllocate_AllChannel(USBx); + host->gState = HOST_IDLE; + + /* Re-Initialize Host for new Enumeration */ + USBHOST_CoreInit(USBx, coreID); + break; + + default : + break; + } + +} + +/** +*\*\name USBH_ErrorHandle. +*\*\fun This function handles the Error on Host side. +*\*\param host: host state set. +*\*\param errType : Type of Error or Busy/OK state +*\*\return none. +*\*\ +**/ +void USBH_ErrorHandle(USBH_HOST *host, USBH_Status errType) +{ + /* Error unrecovered or not supported device speed */ + if ( (errType == USBH_ERROR_SPEED_UNKNOWN) || (errType == USBH_UNRECOVERED_ERROR) ) + { + host->usr_cb->UnrecoveredError(); + host->gState = HOST_ERROR_STATE; + } + /* USB host restart requested from application layer */ + else if(errType == USBH_APPLY_DEINIT) + { + host->gState = HOST_ERROR_STATE; + /* user callback for initialization */ + host->usr_cb->Init(); + } +} + +/** +*\*\name USBH_HandleEnum. +*\*\fun This function includes the complete enumeration process. +*\*\param USBx: selected device. +*\*\param host: host state set. +*\*\return status: USBH_Status. +*\*\ +**/ +static USBH_Status USBH_HandleEnum(USB_CORE_MODULE *USBx, USBH_HOST *host) +{ + USBH_Status Status = USBH_BUSY; + uint8_t Local_Buffer[64]; + + switch (host->EnumState) + { + case ENUM_IDLE: + /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */ + if( USBH_Get_DevDesc(USBx , host, 8) == USBH_OK) + { + host->Control.ep0size = host->device_prop.Dev_Desc.bMaxPacketSize; + + host->EnumState = ENUM_GET_FULL_DEV_DESC; + + /* modify control channels configuration for MaxPacket size */ + USBH_Modify_Channel (USBx, host->Control.hch_num_out, 0, 0, 0, host->Control.ep0size); + USBH_Modify_Channel (USBx, host->Control.hch_num_in, 0, 0, 0, host->Control.ep0size); + } + break; + + case ENUM_GET_FULL_DEV_DESC: + /* Get FULL Device Desc */ + if( USBH_Get_DevDesc(USBx, host, USB_DEVICE_DESC_SIZE) == USBH_OK) + { + /* user callback for device descriptor available */ + host->usr_cb->DeviceDescAvailable(&host->device_prop.Dev_Desc); + host->EnumState = ENUM_SET_ADDR; + } + break; + + case ENUM_SET_ADDR: + /* set address */ + if( USBH_SetAddress(USBx, host, USBH_DEVICE_ADDRESS) == USBH_OK) + { + USB_BSP_mDelay(2); + host->device_prop.address = USBH_DEVICE_ADDRESS; + + /* user callback for device address assigned */ + host->usr_cb->DeviceAddressAssigned(); + host->EnumState = ENUM_GET_CFG_DESC; + + /* modify control channels to update device address */ + USBH_Modify_Channel (USBx, host->Control.hch_num_in, host->device_prop.address, 0, 0, 0); + USBH_Modify_Channel (USBx, host->Control.hch_num_out, host->device_prop.address, 0, 0, 0); + } + break; + + case ENUM_GET_CFG_DESC: + /* get standard configuration descriptor */ + if( USBH_Get_CfgDesc(USBx, host, USB_CONFIGURATION_DESC_SIZE) == USBH_OK) + { + /* before getting full config descriptor, check if it does not exceed + buffer size allocated to config descriptor USBH_MAX_DATA_BUFFER + in the usbh_conf.h*/ + if (host->device_prop.Cfg_Desc.wTotalLength <= USBH_MAX_DATA_BUFFER) + { + host->EnumState = ENUM_GET_FULL_CFG_DESC; + } + } + break; + + case ENUM_GET_FULL_CFG_DESC: + /* get FULL config descriptor (config, interface, endpoints) */ + if(USBH_Get_CfgDesc(USBx, host, host->device_prop.Cfg_Desc.wTotalLength) == USBH_OK) + { + /* User callback for configuration descriptors available */ + host->usr_cb->ConfigurationDescAvailable(&host->device_prop.Cfg_Desc, host->device_prop.Itf_Desc, host->device_prop.Ep_Desc[0]); + + host->EnumState = ENUM_GET_MFC_STRING_DESC; + } + break; + + case ENUM_GET_MFC_STRING_DESC: + if(host->device_prop.Dev_Desc.iManufacturer != 0) + { /* Check that Manufacturer String is available */ + + if ( USBH_Get_StringDesc(USBx, host, host->device_prop.Dev_Desc.iManufacturer, Local_Buffer, 0xff) == USBH_OK) + { + /* User callback for Manufacturing string */ + host->usr_cb->ManufacturerString(Local_Buffer); + host->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + } + } + else + { + host->usr_cb->ManufacturerString("N/A"); + host->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + } + break; + + case ENUM_GET_PRODUCT_STRING_DESC: + if(host->device_prop.Dev_Desc.iProduct != 0) + { /* Check that Product string is available */ + if(USBH_Get_StringDesc(USBx, host, host->device_prop.Dev_Desc.iProduct, Local_Buffer, 0xff) == USBH_OK) + { + /* User callback for Product string */ + host->usr_cb->ProductString(Local_Buffer); + host->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + } + } + else + { + host->usr_cb->ProductString("N/A"); + host->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + } + break; + + case ENUM_GET_SERIALNUM_STRING_DESC: + if(host->device_prop.Dev_Desc.iSerialNumber != 0) + { /* Check that Serial number string is available */ + if(USBH_Get_StringDesc(USBx, host, host->device_prop.Dev_Desc.iSerialNumber, Local_Buffer, 0xff) == USBH_OK) + { + /* User callback for Serial number string */ + host->usr_cb->SerialNumString(Local_Buffer); + host->EnumState = ENUM_SET_CONFIGURATION; + } + } + else + { + host->usr_cb->SerialNumString("N/A"); + host->EnumState = ENUM_SET_CONFIGURATION; + } + break; + + case ENUM_SET_CONFIGURATION: + /* set configuration (default config) */ + if(USBH_SetCfg(USBx, host, host->device_prop.Cfg_Desc.bConfigurationValue) == USBH_OK) + { + host->EnumState = ENUM_DEV_CONFIGURED; + } + break; + + + case ENUM_DEV_CONFIGURED: + /* user callback for enumeration done */ + Status = USBH_OK; + break; + + default: + break; + } + return Status; +} + +/** +*\*\name USBH_HandleControl. +*\*\fun Handles the USB control transfer state machine. +*\*\param USBx: selected device. +*\*\param host: host state set. +*\*\return status: USBH_Status. +*\*\ +**/ +USBH_Status USBH_HandleControl(USB_CORE_MODULE *USBx, USBH_HOST *host) +{ + uint8_t direction; + static uint16_t timeout = 0; + USBH_Status status = USBH_OK; + URB_STATE URB_Status = URB_IDLE; + + host->Control.status = CTRL_START; + + switch(host->Control.state) + { + case CTRL_SETUP: + /* send a SETUP packet */ + USBH_CtrlSendSetup(USBx, host->Control.setup.d8, host->Control.hch_num_out); + host->Control.state = CTRL_SETUP_WAIT; + break; + + case CTRL_SETUP_WAIT: + + URB_Status = HOST_GetURB_State(USBx, host->Control.hch_num_out); + /* case SETUP packet sent successfully */ + if(URB_Status == URB_DONE) + { + direction = (host->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK); + + /* check if there is a data stage */ + if(host->Control.setup.b.wLength.w != 0 ) + { + timeout = DATA_STAGE_TIMEOUT; + if(direction == USB_D2H) + { + /* Data Direction is IN */ + host->Control.state = CTRL_DATA_IN; + } + else + { + /* Data Direction is OUT */ + host->Control.state = CTRL_DATA_OUT; + } + } + /* No DATA stage */ + else + { + timeout = NODATA_STAGE_TIMEOUT; + /* If there is No Data Transfer Stage */ + if (direction == USB_D2H) + { + /* Data Direction is IN */ + host->Control.state = CTRL_STATUS_OUT; + } + else + { + /* Data Direction is OUT */ + host->Control.state = CTRL_STATUS_IN; + } + } + /* Set the delay timer to enable timeout for data stage completion */ + host->Control.timer = HOST_GetCurrentFrame(USBx); + } + else if(URB_Status == URB_ERROR) + { + host->Control.state = CTRL_ERROR; + host->Control.status = CTRL_XACTERR; + } + break; + + case CTRL_DATA_IN: + /* Issue an IN token */ + USBH_CtrlReceiveData(USBx, host->Control.buff, host->Control.length, host->Control.hch_num_in); + + host->Control.state = CTRL_DATA_IN_WAIT; + break; + + case CTRL_DATA_IN_WAIT: + + URB_Status = HOST_GetURB_State(USBx , host->Control.hch_num_in); + + /* check is DATA packet transferred successfully */ + if (URB_Status == URB_DONE) + { + host->Control.state = CTRL_STATUS_OUT; + } + + /* manage error cases*/ + if (URB_Status == URB_STALL) + { + /* In stall case, return to previous machine state*/ + host->gState = host->gStateBkp; + host->Control.state = CTRL_STALLED; + } + else if (URB_Status == URB_ERROR) + { + /* Device error */ + host->Control.state = CTRL_ERROR; + } + else if ((HOST_GetCurrentFrame(USBx)- host->Control.timer) > timeout) + { + /* timeout for IN transfer */ + host->Control.state = CTRL_ERROR; + } + break; + + case CTRL_DATA_OUT: + /* Start DATA out transfer (only one DATA packet)*/ + USBx->host.hch[host->Control.hch_num_out].toggle_out = 1; + + USBH_CtrlSendData (USBx, host->Control.buff, host->Control.length, host->Control.hch_num_out); + + host->Control.state = CTRL_DATA_OUT_WAIT; + break; + + case CTRL_DATA_OUT_WAIT: + + URB_Status = HOST_GetURB_State(USBx , host->Control.hch_num_out); + if(URB_Status == URB_DONE) + { /* If the Setup Pkt is sent successful, then change the state */ + host->Control.state = CTRL_STATUS_IN; + } + /* handle error cases */ + else if(URB_Status == URB_STALL) + { + /* In stall case, return to previous machine state*/ + host->gState = host->gStateBkp; + host->Control.state = CTRL_STALLED; + } + else if(URB_Status == URB_NOTREADY) + { + /* Nack received from device */ + host->Control.state = CTRL_DATA_OUT; + } + else if(URB_Status == URB_ERROR) + { + /* device error */ + host->Control.state = CTRL_ERROR; + } + break; + + + case CTRL_STATUS_IN: + /* Send 0 bytes out packet */ + USBH_CtrlReceiveData(USBx, 0, 0,host->Control.hch_num_in); + host->Control.state = CTRL_STATUS_IN_WAIT; + break; + + case CTRL_STATUS_IN_WAIT: + URB_Status = HOST_GetURB_State(USBx , host->Control.hch_num_in); + if(URB_Status == URB_DONE) + { /* Control transfers completed, Exit the State Machine */ + host->gState = host->gStateBkp; + host->Control.state = CTRL_COMPLETE; + } + else if(URB_Status == URB_ERROR) + { + host->Control.state = CTRL_ERROR; + } + else if((HOST_GetCurrentFrame(USBx) - host->Control.timer) > timeout) + { + host->Control.state = CTRL_ERROR; + } + else if(URB_Status == URB_STALL) + { + /* Control transfers completed, Exit the State Machine */ + host->gState = host->gStateBkp; + host->Control.state = CTRL_STALLED; + status = USBH_NOT_SUPPORTED; + } + break; + + case CTRL_STATUS_OUT: + USBx->host.hch[host->Control.hch_num_out].toggle_out ^= 1; + USBH_CtrlSendData(USBx, 0, 0, host->Control.hch_num_out); + + host->Control.state = CTRL_STATUS_OUT_WAIT; + break; + + case CTRL_STATUS_OUT_WAIT: + + URB_Status = HOST_GetURB_State(USBx , host->Control.hch_num_out); + if(URB_Status == URB_DONE) + { + host->gState = host->gStateBkp; + host->Control.state = CTRL_COMPLETE; + } + else if(URB_Status == URB_NOTREADY) + { + host->Control.state = CTRL_STATUS_OUT; + } + else if(URB_Status == URB_ERROR) + { + host->Control.state = CTRL_ERROR; + } + break; + + case CTRL_ERROR: + /* + After a halt condition is encountered or an error is detected by the + host, a control endpoint is allowed to recover by accepting the next Setup + PID; i.e., recovery actions via some other pipe are not required for control + endpoints. For the Default Control Pipe, a device reset will ultimately be + required to clear the halt or error condition if the next Setup PID is not + accepted. + */ + if(++host->Control.errorcount <= USBH_MAX_ERROR_COUNT) + { + /* Do the transmission again, starting from SETUP Packet */ + host->Control.state = CTRL_SETUP; + } + else + { + host->Control.status = CTRL_FAIL; + host->gState = host->gStateBkp; + + status = USBH_FAIL; + } + break; + + default: + break; + } + return status; +} + +/** +*\*\name USB_BSP_Resume. +*\*\fun Handles the USB Resume from Suspend Mode. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_BSP_Resume(USB_CORE_MODULE *USBx) +{ + uint32_t hpcs = 0; + + /* switch-off the clocks */ + USB_CLR_REG32_BIT(USBx->regs.PWRCTRL, USBHS_PWRCTRL_PHYSTP); + + hpcs = USB_ReadHPCS(USBx); + hpcs &= (~USBHS_HPCS_PSUSP); + hpcs |= USBHS_HPCS_PRES; + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); + USB_BSP_mDelay (20); + + hpcs &= (~USBHS_HPCS_PRES); + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); +} + +/** +*\*\name USB_BSP_Suspend. +*\*\fun Handles the Enter USB to Suspend Mode. +*\*\param USBx: selected device. +*\*\return none. +*\*\ +**/ +void USB_BSP_Suspend(USB_CORE_MODULE *USBx) +{ + uint32_t hpcs; + + hpcs = USB_ReadHPCS(USBx); + hpcs |= USBHS_HPCS_PSUSP; + USB_WRITE_REG32(USBx->regs.HPCS, hpcs); + + /* switch-off the clocks */ + USB_SET_REG32_BIT(USBx->regs.PWRCTRL, USBHS_PWRCTRL_PHYSTP); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_hcs.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_hcs.c new file mode 100644 index 0000000000..29bf329333 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_hcs.c @@ -0,0 +1,200 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_hcs.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */#include "usbh_hcs.h" +#include "usbhs_core.h" + +static uint16_t USBH_GetFreeChannel(USB_CORE_MODULE *USBx); + +/** +*\*\name USBH_Open_Channel. +*\*\fun Open a pipe. +*\*\param USBx: selected device. +*\*\param hch_num: Host channel Number +*\*\param dev_address: USB Device address allocated to attached device +*\*\param speed : USB device speed (Full/Low) +*\*\param ep_type: end point type (Bulk/int/ctl) +*\*\param mps: max pkt size +*\*\return HC_OK. +*\*\ +**/ +uint8_t USBH_Open_Channel(USB_CORE_MODULE *USBx, uint8_t hch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + USBx->host.hch[hch_num].ep_num = USBx->host.channel[hch_num]& 0x7F; + USBx->host.hch[hch_num].ep_is_in = (USBx->host.channel[hch_num] & 0x80) == 0x80; + USBx->host.hch[hch_num].dev_addr = dev_address; + USBx->host.hch[hch_num].ep_type = ep_type; + USBx->host.hch[hch_num].max_packet = mps; + USBx->host.hch[hch_num].speed = speed; + USBx->host.hch[hch_num].toggle_in = 0; + USBx->host.hch[hch_num].toggle_out = 0; + if(speed == HPCS_PRTSPD_HIGH_SPEED) + { + USBx->host.hch[hch_num].do_ping = 1; + } + + USB_HCH_Init(USBx, hch_num) ; + + return HC_OK; +} + +/** +*\*\name USBH_Modify_Channel. +*\*\fun Modify a pipe. +*\*\param USBx: selected device. +*\*\param hch_num: Host channel Number +*\*\param dev_address: USB Device address allocated to attached device +*\*\param speed : USB device speed (Full/Low) +*\*\param ep_type: end point type (Bulk/int/ctl) +*\*\param mps: max pkt size +*\*\return HC_OK. +*\*\ +**/ +uint8_t USBH_Modify_Channel(USB_CORE_MODULE *USBx, uint8_t hch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + if(dev_address != 0) + { + USBx->host.hch[hch_num].dev_addr = dev_address; + } + + if((USBx->host.hch[hch_num].max_packet != mps) && (mps != 0)) + { + USBx->host.hch[hch_num].max_packet = mps; + } + + if((USBx->host.hch[hch_num].speed != speed ) && (speed != 0 )) + { + USBx->host.hch[hch_num].speed = speed; + } + + USB_HCH_Init(USBx, hch_num); + return HC_OK; + +} + +/** +*\*\name USBH_Alloc_Channel. +*\*\fun Allocate a new channel for the pipe. +*\*\param USBx: selected device. +*\*\param ep_addr: End point for which the channel to be allocated +*\*\return hch_num: Host channel number. +*\*\ +**/ +uint8_t USBH_Alloc_Channel(USB_CORE_MODULE *USBx, uint8_t ep_addr) +{ + uint16_t hch_num; + + hch_num = USBH_GetFreeChannel(USBx); + + if (hch_num != HC_ERROR) + { + USBx->host.channel[hch_num & (USB_MAX_TX_FIFOS - 1U)] = HC_USED | ep_addr; + } + return hch_num; +} + +/** +*\*\name USBH_Free_Channel. +*\*\fun Free the USB host channel. +*\*\param USBx: selected device. +*\*\param idx: Channel number to be freed. +*\*\return USBH_OK. +*\*\ +**/ +uint8_t USBH_Free_Channel(USB_CORE_MODULE *USBx, uint8_t idx) +{ + if(idx < HC_MAX) + { + USBx->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] = 0; + } + return USBH_OK; +} + +/** +*\*\name USBH_DeAllocate_AllChannel. +*\*\fun Free all USB host channel. +*\*\param USBx: selected device. +*\*\return USBH_OK. +*\*\ +**/ +uint8_t USBH_DeAllocate_AllChannel(USB_CORE_MODULE *USBx) +{ + uint8_t idx; + + for (idx = 2; idx < HC_MAX ; idx ++) + { + USBx->host.channel[idx] = 0; + } + return USBH_OK; +} + +/** +*\*\name USBH_GetFreeChannel. +*\*\fun Get a free channel number for allocation to a device endpoint. +*\*\param USBx: selected device. +*\*\return idx: Free Channel number. +*\*\ +**/ +static uint16_t USBH_GetFreeChannel(USB_CORE_MODULE *USBx) +{ + uint8_t idx = 0; + + for (idx = 0 ; idx < HC_MAX ; idx++) + { + if ((USBx->host.channel[idx] & HC_USED) == 0) + { + return idx; + } + } + return HC_ERROR; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_ioreq.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_ioreq.c new file mode 100644 index 0000000000..0f4f68c074 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_ioreq.c @@ -0,0 +1,377 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_ioreq.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbh_ioreq.h" + +static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost, uint8_t* buff, uint16_t length); + +/** +*\*\name USBH_CtrlReq. +*\*\fun USBH_CtrlReq sends a control request and provide the status after completion of the request +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param buff: data buffer address to store the response +*\*\param length: length of the response +*\*\return status. +*\*\ +**/ +USBH_Status USBH_CtrlReq(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t *buff, uint16_t length) +{ + USBH_Status status; + status = USBH_BUSY; + + switch(phost->RequestState) + { + case CMD_SEND: + /* Start a SETUP transfer */ + USBH_SubmitSetupRequest(phost, buff, length); + phost->RequestState = CMD_WAIT; + status = USBH_BUSY; + break; + + case CMD_WAIT: + if(phost->Control.state == CTRL_COMPLETE) + { + /* Commands successfully sent and Response Received */ + phost->RequestState = CMD_SEND; + phost->Control.state =CTRL_IDLE; + status = USBH_OK; + } + else if(phost->Control.state == CTRL_ERROR) + { + /* Failure Mode */ + phost->RequestState = CMD_SEND; + status = USBH_FAIL; + } + else if(phost->Control.state == CTRL_STALLED) + { + /* Commands successfully sent and Response Received */ + phost->RequestState = CMD_SEND; + status = USBH_NOT_SUPPORTED; + } + break; + + default: + break; + } + return status; +} + +/** +*\*\name USBH_CtrlSendSetup. +*\*\fun Sends the Setup Packet to the Device. +*\*\param USBx: selected device. +*\*\param buff: data buffer address to store the response +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_CtrlSendSetup(USB_CORE_MODULE *USBx, uint8_t *buff, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 0; + USBx->host.hch[hch_num].data_pid = HCH_PID_SETUP; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = USBH_SETUP_PKT_SIZE; + + return (USBH_Status)HOST_SubmitRequest (USBx , hch_num); +} + +/** +*\*\name USBH_CtrlSendSetup. +*\*\fun Sends the Setup Packet to the Device. +*\*\param USBx: selected device. +*\*\param buff: data buffer address to store the response +*\*\param length: Length of the data to be sent +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_CtrlSendData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 0; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + + if(length == 0) + { /* For Status OUT stage, Length==0, Status Out PID = 1 */ + USBx->host.hch[hch_num].toggle_out = 1; + } + + /* Set the Data Toggle bit as per the Flag */ + if(USBx->host.hch[hch_num].toggle_out == 0) + { /* Put the PID 0 */ + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + } + else + { /* Put the PID 1 */ + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA1 ; + } + + HOST_SubmitRequest (USBx , hch_num); + + return USBH_OK; +} + +/** +*\*\name USBH_CtrlReceiveData. +*\*\fun Receives the Device Response to the Setup Packet. +*\*\param USBx: selected device. +*\*\param buff: data buffer address to store the response +*\*\param length: Length of the data to be sent +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_CtrlReceiveData(USB_CORE_MODULE *USBx, uint8_t* buff, uint16_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 1; + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA1; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + + HOST_SubmitRequest (USBx , hch_num); + + return USBH_OK; +} + +/** +*\*\name USBH_BulkSendData. +*\*\fun Sends the Bulk Packet to the device. +*\*\param USBx: selected device. +*\*\param buff: Buffer pointer from which the Data will be sent to Device +*\*\param length: Length of the data to be sent +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_BulkSendData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 0; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + + /* Set the Data Toggle bit as per the Flag */ + if(USBx->host.hch[hch_num].toggle_out == 0) + { /* Put the PID 0 */ + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + } + else + { /* Put the PID 1 */ + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA1 ; + } + + HOST_SubmitRequest (USBx , hch_num); + return USBH_OK; +} + +/** +*\*\name USBH_BulkReceiveData. +*\*\fun Receives IN bulk packet from device. +*\*\param USBx: selected device. +*\*\param buff: Buffer pointer from which the received data packet to be copied. +*\*\param length: Length of the data to be received. +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_BulkReceiveData(USB_CORE_MODULE *USBx, uint8_t *buff, uint16_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 1; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + + if( USBx->host.hch[hch_num].toggle_in == 0) + { + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + } + else + { + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA1; + } + + HOST_SubmitRequest (USBx , hch_num); + return USBH_OK; +} + +/** +*\*\name USBH_InterruptReceiveData. +*\*\fun Receives the Device Response to the Interrupt IN token. +*\*\param USBx: selected device. +*\*\param buff: Buffer pointer from which the received data packet to be copied. +*\*\param length: Length of the data to be received. +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_InterruptReceiveData(USB_CORE_MODULE *USBx, uint8_t *buff, uint8_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 1; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + + if(USBx->host.hch[hch_num].toggle_in == 0) + { + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + } + else + { + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA1; + } + + /* toggle DATA PID */ + USBx->host.hch[hch_num].toggle_in ^= 1; + + HOST_SubmitRequest (USBx , hch_num); + + return USBH_OK; +} + +/** +*\*\name USBH_InterruptSendData. +*\*\fun Sends the data on Interrupt OUT Endpoint. +*\*\param USBx: selected device. +*\*\param buff: Buffer pointer from where the data needs to be copied. +*\*\param length: Length of the data to be sent. +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_InterruptSendData( USB_CORE_MODULE *USBx, uint8_t *buff, uint8_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 0; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + + if(USBx->host.hch[hch_num].toggle_in == 0) + { + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + } + else + { + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA1; + } + + USBx->host.hch[hch_num].toggle_in ^= 1; + + HOST_SubmitRequest (USBx , hch_num); + + return USBH_OK; +} + +/** +*\*\name USBH_SubmitSetupRequest. +*\*\fun Start a setup transfer by changing the state-machine and initializing the required variables needed for the Control Transfer. +*\*\param USBx: selected device. +*\*\param buff: Buffer used for setup request. +*\*\param length: Length of the data. +*\*\return status. +*\*\ +**/ +static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost, uint8_t* buff, uint16_t length) +{ + /* Save Global State */ + phost->gStateBkp = phost->gState; + + /* Prepare the Transactions */ + phost->gState = HOST_CTRL_XFER; + phost->Control.buff = buff; + phost->Control.length = length; + phost->Control.state = CTRL_SETUP; + + return USBH_OK; +} + +/** +*\*\name USBH_IsocReceiveData. +*\*\fun Receives the Device Response to the Isochronous IN token. +*\*\param USBx: selected device. +*\*\param buff: Buffer pointer in which the response needs to be copied. +*\*\param length: Length of the data to be received. +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_IsocReceiveData( USB_CORE_MODULE *USBx, uint8_t *buff, uint32_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 1; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + + HOST_SubmitRequest (USBx , hch_num); + + return USBH_OK; +} + +/** +*\*\name USBH_IsocSendData. +*\*\fun Sends the data on Isochronous OUT Endpoint. +*\*\param USBx: selected device. +*\*\param buff: Buffer pointer from where the data needs to be copied. +*\*\param length: Length of the data to be sent. +*\*\param hch_num: Host channel Number +*\*\return status. +*\*\ +**/ +USBH_Status USBH_IsocSendData( USB_CORE_MODULE *USBx, uint8_t *buff, uint32_t length, uint8_t hch_num) +{ + USBx->host.hch[hch_num].ep_is_in = 0; + USBx->host.hch[hch_num].xfer_buff = buff; + USBx->host.hch[hch_num].xfer_len = length; + USBx->host.hch[hch_num].data_pid = HCH_PID_DATA0; + + HOST_SubmitRequest (USBx , hch_num); + + return USBH_OK; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_stdreq.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_stdreq.c new file mode 100644 index 0000000000..b9290b14d1 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Driver/n32h76x_78x_usbhs_driver/host/core/src/usbh_stdreq.c @@ -0,0 +1,512 @@ +/** +* Copyright (c) 2025, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** + * @file usbh_stdreq.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2025, Nations Technologies Inc. All rights reserved. + */ +#include "usbh_ioreq.h" +#include "usbh_stdreq.h" + +#ifdef USB_INTERNAL_DMA_ENABLED + #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 + #endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__ALIGN_BEGIN uint8_t USBH_CfgDesc[CFG_DESC_MAX_SIZE] __ALIGN_END ; + + +static void USBH_ParseDevDesc(USBH_DevDesc_TypeDef* , uint8_t *buf, uint16_t length); + +USBH_Status USBH_ParseCfgDesc(USBH_CfgDesc_TypeDef* cfg_desc, + USBH_InterfaceDesc_TypeDef* itf_desc, + USBH_EpDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], + uint8_t *buf, + uint16_t length); + + +static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor, uint8_t *buf); +static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor, uint8_t *buf); +static void USBH_ParseStringDesc (uint8_t* psrc, uint8_t* pdest, uint16_t length); + +/** +*\*\name USBH_Get_DevDesc. +*\*\fun Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param length: Length of the descriptor +*\*\return status. +*\*\ +**/ +USBH_Status USBH_Get_DevDesc(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t length) +{ + USBH_Status status; + + if((status = USBH_GetDescriptor(USBx, phost, USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, USB_DESC_DEVICE, USBx->host.Rx_Buffer, length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseDevDesc(&phost->device_prop.Dev_Desc, USBx->host.Rx_Buffer, length); + } + return status; +} + +/** +*\*\name USBH_Get_CfgDesc. +*\*\fun Issues Configuration Descriptor to the device. Once the response received, it parses the configuration descriptor and updates the status. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param length: Length of the descriptor +*\*\return status. +*\*\ +**/ +USBH_Status USBH_Get_CfgDesc(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint16_t length) +{ + USBH_Status status, result; + uint16_t index = 0; + + if((status = USBH_GetDescriptor(USBx, phost, USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, USB_DESC_CONFIGURATION, USBx->host.Rx_Buffer, length)) == USBH_OK) + { + /*save Cfg descriptor for class parsing usage */ + for( ; index < length ; index ++) + { + USBH_CfgDesc[index] = USBx->host.Rx_Buffer[index]; + } + /* Commands successfully sent and Response Received */ + result = USBH_ParseCfgDesc(&phost->device_prop.Cfg_Desc, phost->device_prop.Itf_Desc, phost->device_prop.Ep_Desc, USBx->host.Rx_Buffer, length); + if(result != USBH_OK) + { + status= result; + } + } + return status; +} + +/** +*\*\name USBH_Get_StringDesc. +*\*\fun Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param string_index: String index for the descriptor +*\*\param buff: Buffer address for the descriptor +*\*\param length: Length of the descriptor +*\*\return status. +*\*\ +**/ +USBH_Status USBH_Get_StringDesc(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length) +{ + USBH_Status status; + + if((status = USBH_GetDescriptor(USBx, phost, USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, USB_DESC_STRING | string_index, USBx->host.Rx_Buffer, length)) == USBH_OK) + { + /* Commands successfully sent and Response Received */ + USBH_ParseStringDesc(USBx->host.Rx_Buffer,buff, length); + } + return status; +} + +/** +*\*\name USBH_GetDescriptor. +*\*\fun Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param req_type: Descriptor type. +*\*\param value_idx: wValue for the GetDescriptr request +*\*\param buff: Buffer to store the descriptor +*\*\param length: Length of the descriptor +*\*\return status. +*\*\ +**/ +USBH_Status USBH_GetDescriptor(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t req_type, uint16_t value_idx, uint8_t* buff, uint16_t length) +{ + phost->Control.setup.b.bmRequestType = USB_D2H | req_type; + phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; + phost->Control.setup.b.wValue.w = value_idx; + + if ((value_idx & 0xff00) == USB_DESC_STRING) + { + phost->Control.setup.b.wIndex.w = 0x0409; + } + else + { + phost->Control.setup.b.wIndex.w = 0; + } + phost->Control.setup.b.wLength.w = length; + return USBH_CtrlReq(USBx, phost, buff , length); +} + +/** +*\*\name USBH_SetAddress. +*\*\fun This command sets the address to the connected device. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param DeviceAddress: Device address to assign. +*\*\return status. +*\*\ +**/ +USBH_Status USBH_SetAddress(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t DeviceAddress) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS; + + phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress; + phost->Control.setup.b.wIndex.w = 0; + phost->Control.setup.b.wLength.w = 0; + + return USBH_CtrlReq(USBx, phost, 0 , 0 ); +} + +/** +*\*\name USBH_SetCfg. +*\*\fun The command sets the configuration value to the connected device. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param cfg_idx: Configuration value. +*\*\return status. +*\*\ +**/ +USBH_Status USBH_SetCfg(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint16_t cfg_idx) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD; + phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; + phost->Control.setup.b.wValue.w = cfg_idx; + phost->Control.setup.b.wIndex.w = 0; + phost->Control.setup.b.wLength.w = 0; + + return USBH_CtrlReq(USBx, phost, 0 , 0 ); +} + +/** +*\*\name USBH_SetInterface. +*\*\fun The command sets the Interface value to the connected device. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param ep_num: the index of the endpoint. +*\*\param altSetting: the value for the setup of set interface. +*\*\return status. +*\*\ +**/ +USBH_Status USBH_SetInterface(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t ep_num, uint8_t altSetting) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD; + + phost->Control.setup.b.bRequest = USB_REQ_SET_INTERFACE; + phost->Control.setup.b.wValue.w = altSetting; + phost->Control.setup.b.wIndex.w = ep_num; + phost->Control.setup.b.wLength.w = 0; + + return USBH_CtrlReq(USBx, phost, 0 , 0 ); +} + +/** +*\*\name USBH_ClrFeature. +*\*\fun This request is used to clear or disable a specific feature. +*\*\param USBx: selected device. +*\*\param phost: host state set. +*\*\param ep_num: endpoint number. +*\*\param hch_num: Host channel number. +*\*\return status. +*\*\ +**/ +USBH_Status USBH_ClrFeature(USB_CORE_MODULE *USBx, USBH_HOST *phost, uint8_t ep_num, uint8_t hch_num) +{ + phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_ENDPOINT | USB_REQ_TYPE_STANDARD; + phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; + phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; + phost->Control.setup.b.wIndex.w = ep_num; + phost->Control.setup.b.wLength.w = 0; + + if((ep_num & USB_REQ_DIR_MASK) == USB_D2H) + { /* EP Type is IN */ + USBx->host.hch[hch_num].toggle_in = 0; + } + else + {/* EP Type is OUT */ + USBx->host.hch[hch_num].toggle_out = 0; + } + + return USBH_CtrlReq(USBx, phost, 0 , 0 ); +} + +/** +*\*\name USBH_ParseDevDesc. +*\*\fun This function Parses the device descriptor. +*\*\param dev_desc: device_descriptor destination address. +*\*\param buf: Buffer where the source descriptor is available. +*\*\param length: Length of the descriptor. +*\*\return status. +*\*\ +**/ +static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* dev_desc, uint8_t *buf, uint16_t length) +{ + dev_desc->bLength = *(uint8_t *) (buf + 0); + dev_desc->bDescriptorType = *(uint8_t *) (buf + 1); + dev_desc->bcdUSB = LE16(buf + 2); + dev_desc->bDeviceClass = *(uint8_t *) (buf + 4); + dev_desc->bDeviceSubClass = *(uint8_t *) (buf + 5); + dev_desc->bDeviceProtocol = *(uint8_t *) (buf + 6); + dev_desc->bMaxPacketSize = *(uint8_t *) (buf + 7); + + if (length > 8) + { /* For 1st time after device connection, Host may issue only 8 bytes for Device Descriptor Length */ + dev_desc->idVendor = LE16(buf + 8); + dev_desc->idProduct = LE16(buf + 10); + dev_desc->bcdDevice = LE16(buf + 12); + dev_desc->iManufacturer = *(uint8_t *) (buf + 14); + dev_desc->iProduct = *(uint8_t *) (buf + 15); + dev_desc->iSerialNumber = *(uint8_t *) (buf + 16); + dev_desc->bNumConfigurations = *(uint8_t *) (buf + 17); + } +} + +/** +*\*\name USBH_ParseCfgDesc. +*\*\fun This function Parses the configuration descriptor. +*\*\param cfg_desc: Configuration Descriptor address. +*\*\param itf_desc: Interface Descriptor address. +*\*\param ep_desc: Endpoint Descriptor address. +*\*\param buf: Buffer where the source descriptor is available. +*\*\param length: Length of the descriptor. +*\*\return status. +*\*\ +**/ +USBH_Status USBH_ParseCfgDesc(USBH_CfgDesc_TypeDef* cfg_desc, + USBH_InterfaceDesc_TypeDef* itf_desc, + USBH_EpDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], + uint8_t *buf, + uint16_t length) +{ + USBH_InterfaceDesc_TypeDef *pif ; + USBH_InterfaceDesc_TypeDef temp_pif ; + USBH_EpDesc_TypeDef *pep; + USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)buf; + uint16_t ptr; + int8_t if_ix = 0; + int8_t ep_ix = 0; + static uint16_t prev_ep_size = 0; + static uint8_t prev_itf = 0; + USBH_Status status; + + + pdesc = (USBH_DescHeader_t *)buf; + + /* Parse configuration descriptor */ + cfg_desc->bLength = *(uint8_t *) (buf + 0); + cfg_desc->bDescriptorType = *(uint8_t *) (buf + 1); + cfg_desc->wTotalLength = LE16 (buf + 2); + cfg_desc->bNumInterfaces = *(uint8_t *) (buf + 4); + cfg_desc->bConfigurationValue = *(uint8_t *) (buf + 5); + cfg_desc->iConfiguration = *(uint8_t *) (buf + 6); + cfg_desc->bmAttributes = *(uint8_t *) (buf + 7); + cfg_desc->bMaxPower = *(uint8_t *) (buf + 8); + + + if(length > USB_CONFIGURATION_DESC_SIZE) + { + ptr = USB_LEN_CFG_DESC; + + if(cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) + { + pif = (USBH_InterfaceDesc_TypeDef *)0; + while (ptr < cfg_desc->wTotalLength ) + { + pdesc = USBH_GetNextDesc((uint8_t *)pdesc, &ptr); + if(pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) + { + if_ix = *(((uint8_t *)pdesc ) + 2); + pif = &itf_desc[if_ix]; + if((*((uint8_t *)pdesc + 3)) < 3) + { + USBH_ParseInterfaceDesc (&temp_pif, (uint8_t *)pdesc); + ep_ix = 0; + + /* Parse Ep descriptors relative to the current interface */ + if(temp_pif.bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) + { + while(ep_ix < temp_pif.bNumEndpoints) + { + pdesc = USBH_GetNextDesc((void* )pdesc, &ptr); + if(pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) + { + pep = &ep_desc[if_ix][ep_ix]; + if(prev_itf != if_ix) + { + prev_itf = if_ix; + USBH_ParseInterfaceDesc(pif, (uint8_t *)&temp_pif); + } + else + { + if(prev_ep_size > LE16((uint8_t *)pdesc + 4)) + { + break; + } + else + { + USBH_ParseInterfaceDesc(pif, (uint8_t *)&temp_pif); + } + } + USBH_ParseEPDesc(pep, (uint8_t *)pdesc); + prev_ep_size = LE16((uint8_t *)pdesc + 4); + ep_ix++; + } + } + } + else /*num endpoints exceeded */ + { + status = USBH_NOT_SUPPORTED; + return status; + } + } + } + } + } + else /*num interfaces exceeded */ + { + status = USBH_NOT_SUPPORTED; + return status; + } + prev_ep_size = 0; + prev_itf = 0; + } + return USBH_OK ; +} + +/** +*\*\name USBH_ParseInterfaceDesc. +*\*\fun This function Parses the interface descriptor. +*\*\param if_descriptor : Interface descriptor destination. +*\*\param buf: Buffer where the descriptor data is available. +*\*\return none. +*\*\ +**/ +static void USBH_ParseInterfaceDesc(USBH_InterfaceDesc_TypeDef *if_descriptor, uint8_t *buf) +{ + if_descriptor->bLength = *(uint8_t *)(buf + 0); + if_descriptor->bDescriptorType = *(uint8_t *)(buf + 1); + if_descriptor->bInterfaceNumber = *(uint8_t *)(buf + 2); + if_descriptor->bAlternateSetting = *(uint8_t *)(buf + 3); + if_descriptor->bNumEndpoints = *(uint8_t *)(buf + 4); + if_descriptor->bInterfaceClass = *(uint8_t *)(buf + 5); + if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6); + if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7); + if_descriptor->iInterface = *(uint8_t *)(buf + 8); +} + +/** +*\*\name USBH_ParseEPDesc. +*\*\fun This function Parses the endpoint descriptor. +*\*\param ep_descriptor: Endpoint descriptor destination address. +*\*\param buf: Buffer where the parsed descriptor stored. +*\*\return none. +*\*\ +**/ +static void USBH_ParseEPDesc(USBH_EpDesc_TypeDef *ep_descriptor, uint8_t *buf) +{ + ep_descriptor->bLength = *(uint8_t *) (buf + 0); + ep_descriptor->bDescriptorType = *(uint8_t *) (buf + 1); + ep_descriptor->bEndpointAddress = *(uint8_t *) (buf + 2); + ep_descriptor->bmAttributes = *(uint8_t *) (buf + 3); + ep_descriptor->bInterval = *(uint8_t *) (buf + 6); + ep_descriptor->wMaxPacketSize = LE16 (buf + 4); +} + +/** +*\*\name USBH_ParseStringDesc. +*\*\fun This function Parses the string descriptor. +*\*\param psrc: Source pointer containing the descriptor data. +*\*\param pdest: Destination address pointer. +*\*\param length: Length of the descriptor. +*\*\return none. +*\*\ +**/ +static void USBH_ParseStringDesc (uint8_t* psrc, uint8_t* pdest, uint16_t length) +{ + uint16_t strlength; + uint16_t idx; + + /* The UNICODE string descriptor is not NULL-terminated. The string length is + computed by subtracting two from the value of the first byte of the descriptor. + */ + + /* Check which is lower size, the Size of string or the length of bytes read + from the device */ + + if(psrc[1] == USB_DESC_TYPE_STRING) + { /* Make sure the Descriptor is String Type */ + /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + strlength = ( ( (psrc[0]-2) <= length) ? (psrc[0]-2) :length); + psrc += 2; /* Adjust the offset ignoring the String Len and Descriptor type */ + + for (idx = 0; idx < strlength; idx+=2 ) + {/* Copy Only the string and ignore the UNICODE ID, hence add the src */ + *pdest = psrc[idx]; + pdest++; + } + *pdest = 0; /* mark end of string */ + } +} + +/** +*\*\name USBH_GetNextDesc. +*\*\fun This function return the next descriptor header. +*\*\param buf: Buffer where the cfg descriptor is available. +*\*\param ptr: data pointer inside the cfg descriptor. +*\*\return next header. +*\*\ +**/ +USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) +{ + USBH_DescHeader_t *pnext; + + *ptr += ((USBH_DescHeader_t *)pbuf)->bLength; + pnext = (USBH_DescHeader_t *)((uint8_t *)pbuf + ((USBH_DescHeader_t *)pbuf)->bLength); + + return(pnext); +} diff --git a/bsp/n32/n32g457qel-stb/project.uvoptx b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvoptx similarity index 91% rename from bsp/n32/n32g457qel-stb/project.uvoptx rename to bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvoptx index f318274860..2fed9f27c2 100644 --- a/bsp/n32/n32g457qel-stb/project.uvoptx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvoptx @@ -1,4 +1,5 @@ + 1.0 @@ -12,7 +13,7 @@ *.lib *.txt; *.h; *.inc; *.md *.plm - *.cpp + *.cpp; *.cc; *.cxx 0 @@ -22,7 +23,7 @@ - rt-thread + Cube_Config 0x4 ARM-ADS @@ -45,7 +46,7 @@ 79 66 8 - .\build\ + .\Listings\ 1 @@ -73,7 +74,7 @@ 0 - 1 + 0 0 1 @@ -120,7 +121,7 @@ 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457QEL7$Flash\N32G45x.FLM) + UL2CM3(-S0 -C0 -P0 -FD24000000 -FC8000 -FN1 -FF0N32H76x_2048 -FS015000000 -FL01E0000 -FP0($$Device:N32H760xIx7$Flash/N32H76x_2048.FLM)) @@ -168,13 +169,4 @@ - - - ::CMSIS - 0 - 0 - 0 - 1 - - diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvprojx b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvprojx new file mode 100644 index 0000000000..870839aa56 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config.uvprojx @@ -0,0 +1,482 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Cube_Config + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32H760xIx7 + Nationstech + Nationstech.N32H76x_DFP.1.1.0 + http://www.keil.com/pack/ + IRAM1(0x24000000,0x100000) IROM1(0x15000000,0x1E0000) CPUTYPE(Cortex-M7) FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD24000000 -FC8000 -FN1 -FF0N32H76x_2048 -FS015000000 -FL01E0000 -FP0($$Device:N32H760xIx7$Flash/N32H76x_2048.FLM)) + 0 + $$Device:N32H760xIx7$firmware\CMSIS\device\n32h76x_78x.h + + + + + + + + + + $$Device:N32H760xIx7$s + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Cube_Config + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin --output=.\bin\Cube_Config.bin .\Objects\Cube_Config.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x24000000 + 0x100000 + + + 1 + 0x15000000 + 0x1E0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x15000000 + 0x1E0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x24000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + N32H76x, USE_STDPERIPH_DRIVER,CORE_CM7,USING_TCM + + ..\USER\inc;..\Driver\CMSIS\core;..\Driver\CMSIS\device;..\Driver\n32h76x_78x_std_periph_driver\inc;..\Driver\n32h76x_78x_periph_app\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x15000000 + 0x24000000 + + .\Cube_Config_CM7.sct + + + + + + + + + + + + STARTUP + + + startup_N32H76x.s + 2 + ..\Driver\CMSIS\device\startup\startup_N32H76x.s + + + + + + CMSIS + + + system_n32h76x_78x.c + 1 + ..\Driver\CMSIS\device\system_n32h76x_78x.c + + + + + + USER + + + main.c + 1 + ..\USER\src\main.c + + + n32h76x_78x_it.c + 1 + ..\USER\src\n32h76x_78x_it.c + + + n32h76x_78x_cfg.c + 1 + ..\USER\src\n32h76x_78x_cfg.c + + + + + FWLB + + + n32h76x_78x_rcc.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_rcc.c + + + misc.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/misc.c + + + n32h76x_78x_dma.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_dma.c + + + n32h76x_78x_gpio.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_gpio.c + + + n32h76x_78x_usart.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_usart.c + + + n32h76x_78x_pwr.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_pwr.c + + + n32h76x_78x_dmamux.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_dmamux.c + + + n32h76x_78x_mdma.c + 1 + ..\Driver\n32h76x_78x_std_periph_driver\src\/n32h76x_78x_mdma.c + + + + + + + + + + + + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config_CM7.sct b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config_CM7.sct new file mode 100644 index 0000000000..0f429eae37 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/MDK-ARM/Cube_Config_CM7.sct @@ -0,0 +1,26 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +; *** NTFx CODE START *** +LR_IROM1 0x15000000 0x80000 { ; load region size_region + ER_IROM1 0x15000000 0x80000 { ; load address = execution address + *.o (RESET, +First) ; Reset vector table + *(InRoot$$Sections) ; All library sections that must be in a root region, + ;for example, __main.o, __scatter*.o, __dc*.o, and * Region$$Table + startup_n32h7*.o (+RO) + system_n32h76x_78x.o (+RO) + + } + QuickCodes_ITCM 0x400 0x3fc00 { ; offset 0x400 for VECTOR TABLE + .ANY (+RO +XO) + } + RW_SRAM 0x24000000 0x80000 { + *(STACK) + .ANY1 (+RW +ZI) + } + DTCM 0x20000000 0x40000 { + .ANY2 (+RW +ZI) ;ANYx: The larger the x, the higher the priority + } +; *** NTFx CODE END *** +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Nationstech.N32H76x_DFP.1.1.0.pack b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Nationstech.N32H76x_DFP.1.1.0.pack new file mode 100644 index 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USART1;","m4Linker":{"QuickCodeSRAM":{"Size":131072,"StartAddress":805306368},"RW_SRAM":{"Size":131072,"StartAddress":805437440},"heapSize":1280,"stackSize":1280,"startupROM":{"Size":1441792,"StartAddress":352845824}},"m7Linker":{"DTCM":{"Size":262144,"StartAddress":536870912},"ITCM":{"Size":262144,"StartAddress":0},"RO_SRAM":{"Size":131072,"StartAddress":603979776},"RW_SRAM":{"Size":524288,"StartAddress":603979776},"heapSize":512,"stackSize":512,"startupROM":{"Size":524288,"StartAddress":352321536}},"mcuName_packg":"N32H760ZIL7_LQFP144","projectIDE":0,"projectName":"Cube_Config","projectPath":"D:\\RT-Thread\\rtthread-latest\\bsp\\n32\\n32hxxx\\n32h760zil7-stb\\board\\Cube_Config"}]} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/main.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/main.h new file mode 100644 index 0000000000..86c19917b0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/main.h @@ -0,0 +1,26 @@ +/** + * @file main.h + * @author N32cube + */ +#ifndef __MAIN_H__ +#define __MAIN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* NTFx CODE START Include*/ +#include "n32h76x_78x.h" +#include "n32h76x_78x_cfg.h" +/* NTFx CODE END Include*/ + +#ifdef __cplusplus + } +#endif + +#endif /* __MAIN_H__ */ +/** + * @} + */ + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_cfg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_cfg.h new file mode 100644 index 0000000000..4ee2d781fd --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_cfg.h @@ -0,0 +1,40 @@ + +/** + * @file n32h76x_78x_cfg.h + * @author N32cube + */ +#ifndef __N32H76X_78X_CFG_H__ +#define __N32H76X_78X_CFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/* NTFx CODE START INCLUDE*/ +#include "n32h76x_78x.h" +#include "n32h76x_78x_rcc.h" +#include "misc.h" +#include "n32h76x_78x_dma.h" +#include "n32h76x_78x_gpio.h" +#include "n32h76x_78x_usart.h" +#include "n32h76x_78x_pwr.h" +#include "n32h76x_78x_dmamux.h" +#include "n32h76x_78x_mdma.h" +/* NTFx CODE END INCLUDE*/ +/* NTFx CODE START Extern*/ +extern void SysTick_Delayms(uint32_t Delayms); +extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize ); +extern bool RCC_Configuration(void); +extern bool NVIC_Configuration(void); +extern bool DMA_Configuration(void); +extern bool GPIO_Configuration(void); +extern bool USART_Configuration(void); +/* NTFx CODE END Extern*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H__ */ +/** + * @} + */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_it.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_it.h new file mode 100644 index 0000000000..edcf7b9fe3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h76x_78x_it.h @@ -0,0 +1,22 @@ +/** + * @file n32h76x_78x_it.h + * @author N32cube + */ +#ifndef __N32H76X_78X_IT_H__ +#define __N32H76X_78X_IT_H__ +#ifdef __cplusplus +extern "C" { +#endif + +/* NTFx CODE START Include*/ +#include "n32h76x_78x.h" +#include "n32h76x_78x_cfg.h" +/* NTFx CODE END Include*/ +#ifdef __cplusplus +} +#endif + +#endif /* __N32h76x_78x_IT_H__ */ +/** + * @} + */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/main.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/main.c new file mode 100644 index 0000000000..35b2f44fb1 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/main.c @@ -0,0 +1,35 @@ +/** + * @file main.c + * @author N32cube + */ + + //!!!!!!!!!!!!!!!!NOTE!!!!!!!!!!!!!!! + // Code cannot be added between /* NTFx CODE START xxxxx*/ and /* NTFx CODE END xxxxx*/ + + /* NTFx CODE START Include*/ +#include "main.h" +#include +#include +/* NTFx CODE END Include*/ +/** + * @brief Main program. + */ +int main(void) +{ + /* NTFx CODE START Config*/ + CopyVectTable(0x15000000,0x0,VECT_SIZE); + RCC_Configuration(); + GPIO_Configuration(); + DMA_Configuration(); + NVIC_Configuration(); + USART_Configuration(); + /* Configure the SysTick to have interrupt in 1ms time basis,then call SysTick_Delayms(ms)*/ + SysTick_Config(600000); + /* NTFx CODE END Config*/ + while(1) + { + + } +} + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_cfg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_cfg.c new file mode 100644 index 0000000000..b35cf485cc --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_cfg.c @@ -0,0 +1,233 @@ +/** + * @file n32h76x_78x_cfg.c + * @author N32cube + */ + +#include "n32h76x_78x_cfg.h" +/* NTFx CODE START */ +__IO uint32_t mwTick; +void SysTick_Delayms(uint32_t Delayms) +{ + uint32_t tickstart = mwTick; + uint32_t wait=Delayms; + /* Add 1 to guarantee minimum wait */ + if (wait < 0xFFFFFFFFU) + { + wait +=1; + } + while ((mwTick - tickstart) < wait) + { + } +} + /** + *@name DMA_SetSrcDstAddr. + *@brief Set peripher address and memory address of DMA + *param DMAy (The input parameters must be the following values): + * - DMA1 + * - DMA2 + * - DMA3 + *param ChNum (The input parameters must be the following values): + * - DMA_CHANNEL_0 + * - DMA_CHANNEL_1 + * - DMA_CHANNEL_2 + * - DMA_CHANNEL_3 + * - DMA_CHANNEL_4 + * - DMA_CHANNEL_5 + * - DMA_CHANNEL_6 + * - DMA_CHANNEL_7 + *@param SrcAddr Source address + *@param DstAddr Destination address + *@return status + */ + void DMA_SetSrcDstAddr(DMA_Module *const DMAy,DMA_ChNumType ChNum, uint32_t SrcAddr,uint32_t DstAddr ) + { + /* Sets channel n source address register */ + WRITE_REG(DMAy->CH[ChNum].SA, SrcAddr); + /* Sets channel n destination address register */ + WRITE_REG(DMAy->CH[ChNum].DA, DstAddr); + } + /** + *@name MDMA_SetSrcDstAddr. + *@brief Set peripher address and memory address of MDMA + *param MDMAy (The input parameters must be the following values): + * - MDMA + *param ChNum (The input parameters must be the following values): + * - MDMA_CHANNEL_0 + * - MDMA_CHANNEL_1 + * - MDMA_CHANNEL_2 + * - MDMA_CHANNEL_3 + * - MDMA_CHANNEL_4 + * - MDMA_CHANNEL_5 + * - MDMA_CHANNEL_6 + * - MDMA_CHANNEL_7 + * - MDMA_CHANNEL_8 + * - MDMA_CHANNEL_9 + * - MDMA_CHANNEL_10 + * - MDMA_CHANNEL_11 + * - MDMA_CHANNEL_12 + * - MDMA_CHANNEL_13 + * - MDMA_CHANNEL_14 + * - MDMA_CHANNEL_15 + *@param SrcAddr Source address + *@param DstAddr Destination address + *@return status + */ + void MDMA_SetSrcDstAddr(MDMA_Module *const MDMAy,MDMA_ChNumType ChNum, uint32_t SrcAddr,uint32_t DstAddr ) + { + /* Sets channel n source address register */ + WRITE_REG(MDMAy->CH[ChNum].SA, SrcAddr); + /* Sets channel n destination address register */ + WRITE_REG(MDMAy->CH[ChNum].DA, DstAddr); + } +/* NTFx CODE END */ + /* NTFx CODE START */ +/** + *@brief Initializes the clock tree + *@param null + *@return status + */ +bool RCC_Configuration(void) +{ + ErrorStatus ClockStatus; + + RCC_ConfigHSIclkDivider(RCC_HSICLK_DIV1); + RCC_EnableHsi(ENABLE); + /* Wait till HSI is ready */ + ClockStatus = RCC_WaitHsiStable(); + if (ClockStatus != SUCCESS) return false; + RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); + RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); + /*Configures the Periph clock source as HSI*/ + RCC_ConfigPeriphClk(RCC_PERIPHCLK_SRC_HSI); + + /* Configure APB1 clock is AHB1/2 = 150.000M */ + /* Configure APB2 clock is AHB2/2 = 150.000M */ + /* Configure APB5 clock is AHB5/2 = 150.000M */ + /* Configure APB6 clock is AHB6/2 = 150.000M */ + RCC_ConfigAPBclkDivider(RCC_APB1CLK_DIV2, RCC_APB2CLK_DIV2, RCC_APB5CLK_DIV2, RCC_APB6CLK_DIV2); + /*Configures the PLL1 clock source and multiplication factor,Fin=64M,Fout=600M*/ + //RCC_ConfigPll1(RCC_PLL_SRC_HSI,64000000,600000000,ENABLE); + RCC_ConfigPll1_NoCalculate(RCC_PLL_SRC_HSI,0,153600,3,ENABLE); + /*Configure PLL1 divider value to Pll1A*/ + RCC_ConfigPLL1ADivider(RCC_PLLA_DIV1); + /*Configure PLL1 divider value to Pll1B*/ + RCC_ConfigPLL1BDivider(RCC_PLLB_DIV2); + /*Configure PLL1 divider value to Pll1C*/ + RCC_ConfigPLL1CDivider(RCC_PLLC_DIV2); + /*Configure AXI clock source and divider*/ + RCC_ConfigAXIClk(RCC_AXIHYPERCLK_SRC_PLL1A); + RCC_ConfigAXIclkDivider(RCC_AXICLK_DIV2); + /*Configure M7 clock source and divider*/ + RCC_ConfigM7SystickClkDivider(RCC_STCLK_DIV1); + RCC_ConfigM7Clk(RCC_M7HYPERCLK_SRC_PLL1A); + /* configure sys_clk source is PLL1A */ + RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL1A); + /* Check if sys_clk source is PLL1A */ + while(RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A); + + /*Config the USART1/2 PCLK divider from ahb1*/ + RCC_ConfigUSARTPClk(RCC_USARTPCLK_AHB1_DIV1); + + /*Config the TRNG clock*/ + RCC_ConfigTRNGClk(RCC_TRNGCLK_SRC_SYSBUSDIV,RCC_TRNGCLK_SYSBUSDIV2); + + + /*Enables the APB1 peripheral clock 3 .*/ + RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1 ,ENABLE); +/* NTFx CODE END */ + + return true; +} +/* NTFx CODE START */ +/** + *@brief Initializes the NVIC + *@param null + *@return status + */ +bool NVIC_Configuration(void) +{ + +/* NTFx CODE END */ + + return true; +} +/* NTFx CODE START */ +/** + *@brief Initializes the DMA + *@param null + *@return status + */ +bool DMA_Configuration(void) +{ + +/* NTFx CODE END */ + + return true; +} +/* NTFx CODE START */ +/** + *@brief Initializes the GPIO + *@param null + *@return status + */ +bool GPIO_Configuration(void) +{ + + GPIO_InitType GPIO_InitStructure; + GPIO_InitStruct(&GPIO_InitStructure); + /* Enable the GPIO clock*/ + RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA | RCC_AHB5_PERIPHEN_M4_GPIOA, ENABLE); + RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO|RCC_AHB5_PERIPHEN_M4_AFIO,ENABLE); + + + /*Initialize AF_PP GPIO */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW; + GPIO_InitStructure.GPIO_Current = GPIO_DS_2mA; + GPIO_InitStructure.GPIO_Alternate = GPIO_AF7; + GPIO_InitStructure.Pin = GPIO_PIN_9; + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + + /*Initialize input GPIO */ + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; + GPIO_InitStructure.Pin = GPIO_PIN_10; + GPIO_InitPeripheral(GPIOA,&GPIO_InitStructure); + +/* NTFx CODE END */ + + return true; +} +/* NTFx CODE START */ +/** + *@brief Initializes the USART + *@param null + *@return status + */ +bool USART_Configuration(void) +{ + USART_InitType USART_InitStructure; + USART_StructInit(&USART_InitStructure); + + + /*********initialize the USART1************/ + USART_DeInit(USART1); + USART_InitStructure.BaudRate = 115200; + USART_InitStructure.WordLength = USART_WL_8B; + USART_InitStructure.StopBits = USART_STPB_1; + USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER ; + /* Configure USART1 */ + USART_Init(USART1, &USART_InitStructure); + + + /* Enable the USART1 */ + USART_Enable(USART1, ENABLE); +/* NTFx CODE END */ + + return true; +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_it.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_it.c new file mode 100644 index 0000000000..a2ca2d4c23 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h76x_78x_it.c @@ -0,0 +1,100 @@ +/** + * @file n32h76x_78x_it.c + * @author N32cube + */ + + /* NTFx CODE START */ +#include "n32h76x_78x_it.h" +#include "n32h76x_78x.h" +/* NTFx CODE END */ + +/* NTFx CODE START */ +extern __IO uint32_t mwTick; +/** + * @brief This function handles NMI exception. + */ +void NMI_Handler(void) +{ +/* NTFx CODE END */ + +} +/* NTFx CODE START */ +/** + * @brief This function handles Hard Fault exception. + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + /* NTFx CODE END */ + + } +} +/* NTFx CODE START */ +/** + * @brief This function handles Memory Manage exception. + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { +/* NTFx CODE END */ + + } +} +/* NTFx CODE START */ +/** + * @brief This function handles Bus Fault exception. + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { +/* NTFx CODE END */ + + } +} +/* NTFx CODE START */ +/** + * @brief This function handles Usage Fault exception. + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { +/* NTFx CODE END */ + + } +} +/* NTFx CODE START */ +/** + * @brief This function handles SVCall exception. + */ +void SVC_Handler(void) +{ +/* NTFx CODE END */ + +} +/* NTFx CODE START */ +/** + * @brief This function handles Debug Monitor exception. + */ +void DebugMon_Handler(void) +{ +/* NTFx CODE END */ + +} +/* NTFx CODE START */ +/** + * @brief This function handles SysTick Handler. + */ +void SysTick_Handler(void) +{ + mwTick++; +/* NTFx CODE END */ + +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/Clock.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/Clock.dat new file mode 100644 index 0000000000..850c2e0a4e --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/Clock.dat @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/ConfigModList.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/ConfigModList.dat new file mode 100644 index 0000000000..6965db9360 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/ConfigModList.dat @@ -0,0 +1 @@ +{"configModDic":[{"Key":"Clock","Value":{"initByCoreX":0,"runOnCoreX":0}},{"Key":"SYS","Value":{"initByCoreX":0,"runOnCoreX":0}},{"Key":"NVIC_M7","Value":{"initByCoreX":0,"runOnCoreX":0}},{"Key":"DMA","Value":{"initByCoreX":0,"runOnCoreX":0}},{"Key":"GPIO","Value":{"initByCoreX":0,"runOnCoreX":0}},{"Key":"USART1","Value":{"initByCoreX":0,"runOnCoreX":0}}]} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/DMAStates.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/DMAStates.dat new file mode 100644 index 0000000000..c9da3f5c67 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/DMAStates.dat @@ -0,0 +1 @@ +{"DMAs":[],"MDMAs":[]} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/LastLoadProject.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/LastLoadProject.dat new file mode 100644 index 0000000000..a302eebbf3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/LastLoadProject.dat @@ -0,0 +1 @@ +{"AXIsRAM2_3_max":512,"DTCM_max":256,"ITCM_max":256,"TcmSizeValue":32,"dateTime":"2026\/01\/28_09:58:33","info":"N32H760ZIL7_LQFP144; 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\ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/PinStates.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/PinStates.dat new file mode 100644 index 0000000000..f2251d72ab --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/PinStates.dat @@ -0,0 +1 @@ +{"list":[{"Key":"PA13","Value":{"driveStrength":6,"extiTrigger":0,"fuctionOnPin":"SYS.SWDIO","mode":7,"outLevel":2,"pullUpDown":3,"runOn":2,"toggleRate":2}},{"Key":"PA14","Value":{"driveStrength":6,"extiTrigger":0,"fuctionOnPin":"SYS.SWCLK","mode":7,"outLevel":2,"pullUpDown":3,"runOn":2,"toggleRate":2}},{"Key":"PA9","Value":{"driveStrength":0,"extiTrigger":0,"fuctionOnPin":"USART1.TX","mode":2,"outLevel":2,"pullUpDown":1,"runOn":2,"toggleRate":1}},{"Key":"PA10","Value":{"driveStrength":6,"extiTrigger":0,"fuctionOnPin":"USART1.RX","mode":1,"outLevel":2,"pullUpDown":1,"runOn":2,"toggleRate":2}}]} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/SYS.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/SYS.dat new file mode 100644 index 0000000000..268488083a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/SYS.dat @@ -0,0 +1 @@ +{"debug":1,"isEnSysTickM4":true,"isEnSysTickM7":true,"wakeUPn":[0,0,0,0,0,0]} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/USART1.dat b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/USART1.dat new file mode 100644 index 0000000000..153ab3d4d1 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/data/USART1.dat @@ -0,0 +1 @@ +{"CTSIEN":false,"DEassertionTime":0,"DEdeassertionTIme":0,"DEpolarity":0,"ERRIEN":false,"IDLEIEN":false,"LINBDFIEN":false,"PEFIEN":false,"RTOITE":false,"RXDNEIEN":false,"RXFEITE":false,"RXFFITE":false,"RXFTITE":false,"RxFiFoThreshold":0,"TXCIEN":false,"TXDEIEN":false,"TXFEITE":false,"TXFFITE":false,"TXFTITE":false,"TxFiFoThreshold":0,"baud":115200,"clockPhase":0,"clockPolarity":0,"clockPrescaler":1,"dataDirection":0,"flowCtrl":0,"guardTime":0,"idleFrameLength":0,"irDaMode":0,"isFiFoEnable":false,"isIdleFrameCtrlEnable":false,"isLastBitClockEnable":false,"isNACKenable":false,"isReceiverTimeoutEnable":false,"isSwapTX_RX":false,"linBreakDetectLength":0,"overSample":0,"parity":0,"receiverTimeoutLength":0,"stopBits":0,"uartMode":1,"wakeUpAddr":0,"wakeUpMethod":0,"wordLength":1} \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x.s new file mode 100644 index 0000000000..0482eea3ed --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x.s @@ -0,0 +1,892 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; Reserved + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_IRQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +N32SysTick_Handler PROC + EXPORT N32SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG1_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel0_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA3_Channel0_IRQHandler [WEAK] + EXPORT DMA3_Channel1_IRQHandler [WEAK] + EXPORT DMA3_Channel2_IRQHandler [WEAK] + EXPORT DMA3_Channel3_IRQHandler [WEAK] + EXPORT DMA3_Channel4_IRQHandler [WEAK] + EXPORT DMA3_Channel5_IRQHandler [WEAK] + EXPORT DMA3_Channel6_IRQHandler [WEAK] + EXPORT DMA3_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel0_IRQHandler [WEAK] + EXPORT MDMA_Channel1_IRQHandler [WEAK] + EXPORT MDMA_Channel2_IRQHandler [WEAK] + EXPORT MDMA_Channel3_IRQHandler [WEAK] + EXPORT MDMA_Channel4_IRQHandler [WEAK] + EXPORT MDMA_Channel5_IRQHandler [WEAK] + EXPORT MDMA_Channel6_IRQHandler [WEAK] + EXPORT MDMA_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel8_IRQHandler [WEAK] + EXPORT MDMA_Channel9_IRQHandler [WEAK] + EXPORT MDMA_Channel10_IRQHandler [WEAK] + EXPORT MDMA_Channel11_IRQHandler [WEAK] + EXPORT MDMA_Channel12_IRQHandler [WEAK] + EXPORT MDMA_Channel13_IRQHandler [WEAK] + EXPORT MDMA_Channel14_IRQHandler [WEAK] + EXPORT MDMA_Channel15_IRQHandler [WEAK] + EXPORT SDPU_IRQHandler [WEAK] + EXPORT FPU_CPU1_IRQHandler [WEAK] + EXPORT ECCMON_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT I2C6_EV_IRQHandler [WEAK] + EXPORT I2C6_ER_IRQHandler [WEAK] + EXPORT I2C7_EV_IRQHandler [WEAK] + EXPORT I2C7_ER_IRQHandler [WEAK] + EXPORT I2C8_EV_IRQHandler [WEAK] + EXPORT I2C8_ER_IRQHandler [WEAK] + EXPORT I2C9_EV_IRQHandler [WEAK] + EXPORT I2C9_ER_IRQHandler [WEAK] + EXPORT I2C10_EV_IRQHandler [WEAK] + EXPORT I2C10_ER_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT I2S4_IRQHandler [WEAK] + EXPORT xSPI1_IRQHandler [WEAK] + EXPORT xSPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT LCD_EV_IRQHandler [WEAK] + EXPORT LCD_ER_IRQHandler [WEAK] + EXPORT DVP1_IRQHandler [WEAK] + EXPORT DVP2_IRQHandler [WEAK] + EXPORT DMAMUX2_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB1_HS_WKUP_IRQHandler [WEAK] + EXPORT USB1_HS_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB2_HS_WKUP_IRQHandler [WEAK] + EXPORT USB2_HS_IRQHandler [WEAK] + EXPORT ETH1_IRQHandler [WEAK] + EXPORT ETH1_PMT_LPI_IRQHandler [WEAK] + EXPORT ETH2_IRQHandler [WEAK] + EXPORT ETH2_PMT_LPI_IRQHandler [WEAK] + EXPORT FDCAN1_INT0_IRQHandler [WEAK] + EXPORT FDCAN2_INT0_IRQHandler [WEAK] + EXPORT FDCAN3_INT0_IRQHandler [WEAK] + EXPORT FDCAN4_INT0_IRQHandler [WEAK] + EXPORT FDCAN1_INT1_IRQHandler [WEAK] + EXPORT FDCAN2_INT1_IRQHandler [WEAK] + EXPORT FDCAN3_INT1_IRQHandler [WEAK] + EXPORT FDCAN4_INT1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPUART2_IRQHandler [WEAK] + EXPORT GPU_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT COMP1_2_IRQHandler [WEAK] + EXPORT COMP3_4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT1_IRQHandler [WEAK] + EXPORT SHRTIM1_INT2_IRQHandler [WEAK] + EXPORT SHRTIM1_INT3_IRQHandler [WEAK] + EXPORT SHRTIM1_INT4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT5_IRQHandler [WEAK] + EXPORT SHRTIM1_INT6_IRQHandler [WEAK] + EXPORT SHRTIM1_INT7_IRQHandler [WEAK] + EXPORT SHRTIM1_INT8_IRQHandler [WEAK] + EXPORT SHRTIM2_INT1_IRQHandler [WEAK] + EXPORT SHRTIM2_INT2_IRQHandler [WEAK] + EXPORT SHRTIM2_INT3_IRQHandler [WEAK] + EXPORT SHRTIM2_INT4_IRQHandler [WEAK] + EXPORT SHRTIM2_INT5_IRQHandler [WEAK] + EXPORT SHRTIM2_INT6_IRQHandler [WEAK] + EXPORT SHRTIM2_INT7_IRQHandler [WEAK] + EXPORT SHRTIM2_INT8_IRQHandler [WEAK] + EXPORT FDCAN5_INT0_IRQHandler [WEAK] + EXPORT FDCAN6_INT0_IRQHandler [WEAK] + EXPORT FDCAN7_INT0_IRQHandler [WEAK] + EXPORT FDCAN8_INT0_IRQHandler [WEAK] + EXPORT FDCAN5_INT1_IRQHandler [WEAK] + EXPORT FDCAN6_INT1_IRQHandler [WEAK] + EXPORT FDCAN7_INT1_IRQHandler [WEAK] + EXPORT FDCAN8_INT1_IRQHandler [WEAK] + EXPORT LPTIM5_WKUP_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_H2P_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_P2H_IRQHandler [WEAK] + EXPORT WAKEUP_IO_IRQHandler [WEAK] + EXPORT SEMA4_INT1_IRQHandler [WEAK] + EXPORT WWDG2_RST_IRQHandler [WEAK] + EXPORT OTPC_IRQHandler [WEAK] + EXPORT FEMC_IRQHandler [WEAK] + EXPORT DCMUB_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT MDMA_AHBS_ER_IRQHandler [WEAK] + EXPORT CM7_CATCH_READ_ER_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT DAC4_IRQHandler [WEAK] + EXPORT EMC_IRQHandler [WEAK] + EXPORT DAC5_IRQHandler [WEAK] + EXPORT DAC6_IRQHandler [WEAK] + EXPORT ESC_OPB_IRQHandler [WEAK] + EXPORT ESC_SYNC0_IRQHandler [WEAK] + EXPORT ESC_SYNC1_IRQHandler [WEAK] + EXPORT ESC_WRP_IRQHandler [WEAK] + EXPORT ATIM1_BRK_IRQHandler [WEAK] + EXPORT ATIM1_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM1_CC_IRQHandler [WEAK] + EXPORT ATIM1_UP_IRQHandler [WEAK] + EXPORT ATIM2_BRK_IRQHandler [WEAK] + EXPORT ATIM2_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM2_CC_IRQHandler [WEAK] + EXPORT ATIM2_UP_IRQHandler [WEAK] + EXPORT ATIM3_BRK_IRQHandler [WEAK] + EXPORT ATIM3_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM3_CC_IRQHandler [WEAK] + EXPORT ATIM3_UP_IRQHandler [WEAK] + EXPORT ATIM4_BRK_IRQHandler [WEAK] + EXPORT ATIM4_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM4_CC_IRQHandler [WEAK] + EXPORT ATIM4_UP_IRQHandler [WEAK] + EXPORT GTIMA1_IRQHandler [WEAK] + EXPORT GTIMA2_IRQHandler [WEAK] + EXPORT GTIMA3_IRQHandler [WEAK] + EXPORT GTIMA4_IRQHandler [WEAK] + EXPORT GTIMA5_IRQHandler [WEAK] + EXPORT GTIMA6_IRQHandler [WEAK] + EXPORT GTIMA7_IRQHandler [WEAK] + EXPORT GTIMB1_IRQHandler [WEAK] + EXPORT GTIMB2_IRQHandler [WEAK] + EXPORT GTIMB3_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT BTIM4_IRQHandler [WEAK] + EXPORT LPTIM1_WKUP_IRQHandler [WEAK] + EXPORT LPTIM2_WKUP_IRQHandler [WEAK] + EXPORT LPTIM3_WKUP_IRQHandler [WEAK] + EXPORT LPTIM4_WKUP_IRQHandler [WEAK] + EXPORT DSMU_FLT0_IRQHandler [WEAK] + EXPORT DSMU_FLT1_IRQHandler [WEAK] + EXPORT DSMU_FLT2_IRQHandler [WEAK] + EXPORT DSMU_FLT3_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT DMAMUX1_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT SysTick_Handler [WEAK] + +WWDG1_IRQHandler +PVD_IRQHandler +RTC_TAMPER_IRQHandler +RTC_WKUP_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI9_5_IRQHandler +EXTI15_10_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +DMA2_Channel0_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA3_Channel0_IRQHandler +DMA3_Channel1_IRQHandler +DMA3_Channel2_IRQHandler +DMA3_Channel3_IRQHandler +DMA3_Channel4_IRQHandler +DMA3_Channel5_IRQHandler +DMA3_Channel6_IRQHandler +DMA3_Channel7_IRQHandler +MDMA_Channel0_IRQHandler +MDMA_Channel1_IRQHandler +MDMA_Channel2_IRQHandler +MDMA_Channel3_IRQHandler +MDMA_Channel4_IRQHandler +MDMA_Channel5_IRQHandler +MDMA_Channel6_IRQHandler +MDMA_Channel7_IRQHandler +MDMA_Channel8_IRQHandler +MDMA_Channel9_IRQHandler +MDMA_Channel10_IRQHandler +MDMA_Channel11_IRQHandler +MDMA_Channel12_IRQHandler +MDMA_Channel13_IRQHandler +MDMA_Channel14_IRQHandler +MDMA_Channel15_IRQHandler +SDPU_IRQHandler +FPU_CPU1_IRQHandler +ECCMON_IRQHandler +RTC_ALARM_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +I2C6_EV_IRQHandler +I2C6_ER_IRQHandler +I2C7_EV_IRQHandler +I2C7_ER_IRQHandler +I2C8_EV_IRQHandler +I2C8_ER_IRQHandler +I2C9_EV_IRQHandler +I2C9_ER_IRQHandler +I2C10_EV_IRQHandler +I2C10_ER_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +I2S3_IRQHandler +I2S4_IRQHandler +xSPI1_IRQHandler +xSPI2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SPI7_IRQHandler +LCD_EV_IRQHandler +LCD_ER_IRQHandler +DVP1_IRQHandler +DVP2_IRQHandler +DMAMUX2_IRQHandler +USB1_HS_EPx_OUT_IRQHandler +USB1_HS_EPx_IN_IRQHandler +USB1_HS_WKUP_IRQHandler +USB1_HS_IRQHandler +USB2_HS_EPx_OUT_IRQHandler +USB2_HS_EPx_IN_IRQHandler +USB2_HS_WKUP_IRQHandler +USB2_HS_IRQHandler +ETH1_IRQHandler +ETH1_PMT_LPI_IRQHandler +ETH2_IRQHandler +ETH2_PMT_LPI_IRQHandler +FDCAN1_INT0_IRQHandler +FDCAN2_INT0_IRQHandler +FDCAN3_INT0_IRQHandler +FDCAN4_INT0_IRQHandler +FDCAN1_INT1_IRQHandler +FDCAN2_INT1_IRQHandler +FDCAN3_INT1_IRQHandler +FDCAN4_INT1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +LPUART1_IRQHandler +LPUART2_IRQHandler +GPU_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +ADC3_IRQHandler +COMP1_2_IRQHandler +COMP3_4_IRQHandler +SHRTIM1_INT1_IRQHandler +SHRTIM1_INT2_IRQHandler +SHRTIM1_INT3_IRQHandler +SHRTIM1_INT4_IRQHandler +SHRTIM1_INT5_IRQHandler +SHRTIM1_INT6_IRQHandler +SHRTIM1_INT7_IRQHandler +SHRTIM1_INT8_IRQHandler +SHRTIM2_INT1_IRQHandler +SHRTIM2_INT2_IRQHandler +SHRTIM2_INT3_IRQHandler +SHRTIM2_INT4_IRQHandler +SHRTIM2_INT5_IRQHandler +SHRTIM2_INT6_IRQHandler +SHRTIM2_INT7_IRQHandler +SHRTIM2_INT8_IRQHandler +FDCAN5_INT0_IRQHandler +FDCAN6_INT0_IRQHandler +FDCAN7_INT0_IRQHandler +FDCAN8_INT0_IRQHandler +FDCAN5_INT1_IRQHandler +FDCAN6_INT1_IRQHandler +FDCAN7_INT1_IRQHandler +FDCAN8_INT1_IRQHandler +LPTIM5_WKUP_IRQHandler +JPEG_SGDMA_H2P_IRQHandler +JPEG_SGDMA_P2H_IRQHandler +WAKEUP_IO_IRQHandler +SEMA4_INT1_IRQHandler +WWDG2_RST_IRQHandler +OTPC_IRQHandler +FEMC_IRQHandler +DCMUB_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +MDMA_AHBS_ER_IRQHandler +CM7_CATCH_READ_ER_IRQHandler +DAC3_IRQHandler +DAC4_IRQHandler +EMC_IRQHandler +DAC5_IRQHandler +DAC6_IRQHandler +ESC_OPB_IRQHandler +ESC_SYNC0_IRQHandler +ESC_SYNC1_IRQHandler +ESC_WRP_IRQHandler +ATIM1_BRK_IRQHandler +ATIM1_TRG_COM_IRQHandler +ATIM1_CC_IRQHandler +ATIM1_UP_IRQHandler +ATIM2_BRK_IRQHandler +ATIM2_TRG_COM_IRQHandler +ATIM2_CC_IRQHandler +ATIM2_UP_IRQHandler +ATIM3_BRK_IRQHandler +ATIM3_TRG_COM_IRQHandler +ATIM3_CC_IRQHandler +ATIM3_UP_IRQHandler +ATIM4_BRK_IRQHandler +ATIM4_TRG_COM_IRQHandler +ATIM4_CC_IRQHandler +ATIM4_UP_IRQHandler +GTIMA1_IRQHandler +GTIMA2_IRQHandler +GTIMA3_IRQHandler +GTIMA4_IRQHandler +GTIMA5_IRQHandler +GTIMA6_IRQHandler +GTIMA7_IRQHandler +GTIMB1_IRQHandler +GTIMB2_IRQHandler +GTIMB3_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +BTIM4_IRQHandler +LPTIM1_WKUP_IRQHandler +LPTIM2_WKUP_IRQHandler +LPTIM3_WKUP_IRQHandler +LPTIM4_WKUP_IRQHandler +DSMU_FLT0_IRQHandler +DSMU_FLT1_IRQHandler +DSMU_FLT2_IRQHandler +DSMU_FLT3_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +DMAMUX1_IRQHandler +MMU_IRQHandler +SysTick_Handler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_EWARM.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_EWARM.s new file mode 100644 index 0000000000..af54dada4b --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_EWARM.s @@ -0,0 +1,1529 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + + __iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; Reserved + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_RQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + ;need check to user manual of exti chapter + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK N32SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +N32SysTick_Handler + B N32SysTick_Handler + + PUBWEAK WWDG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG1_IRQHandler + B WWDG1_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_TAMPER_IRQHandler + B RTC_TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK DMA2_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel0_IRQHandler + B DMA2_Channel0_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA3_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel0_IRQHandler + B DMA3_Channel0_IRQHandler + + PUBWEAK DMA3_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel1_IRQHandler + B DMA3_Channel1_IRQHandler + + PUBWEAK DMA3_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel2_IRQHandler + B DMA3_Channel2_IRQHandler + + PUBWEAK DMA3_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel3_IRQHandler + B DMA3_Channel3_IRQHandler + + PUBWEAK DMA3_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel4_IRQHandler + B DMA3_Channel4_IRQHandler + + PUBWEAK DMA3_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel5_IRQHandler + B DMA3_Channel5_IRQHandler + + PUBWEAK DMA3_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel6_IRQHandler + B DMA3_Channel6_IRQHandler + + PUBWEAK DMA3_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel7_IRQHandler + B DMA3_Channel7_IRQHandler + + PUBWEAK MDMA_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel0_IRQHandler + B MDMA_Channel0_IRQHandler + + PUBWEAK MDMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel1_IRQHandler + B MDMA_Channel1_IRQHandler + + PUBWEAK MDMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel2_IRQHandler + B MDMA_Channel2_IRQHandler + + PUBWEAK MDMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel3_IRQHandler + B MDMA_Channel3_IRQHandler + + PUBWEAK MDMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel4_IRQHandler + B MDMA_Channel4_IRQHandler + + PUBWEAK MDMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel5_IRQHandler + B MDMA_Channel5_IRQHandler + + PUBWEAK MDMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel6_IRQHandler + B MDMA_Channel6_IRQHandler + + PUBWEAK MDMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel7_IRQHandler + B MDMA_Channel7_IRQHandler + + PUBWEAK MDMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel8_IRQHandler + B MDMA_Channel8_IRQHandler + + PUBWEAK MDMA_Channel9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel9_IRQHandler + B MDMA_Channel9_IRQHandler + + PUBWEAK MDMA_Channel10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel10_IRQHandler + B MDMA_Channel10_IRQHandler + + PUBWEAK MDMA_Channel11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel11_IRQHandler + B MDMA_Channel11_IRQHandler + + PUBWEAK MDMA_Channel12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel12_IRQHandler + B MDMA_Channel12_IRQHandler + + PUBWEAK MDMA_Channel13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel13_IRQHandler + B MDMA_Channel13_IRQHandler + + PUBWEAK MDMA_Channel14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel14_IRQHandler + B MDMA_Channel14_IRQHandler + + PUBWEAK MDMA_Channel15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel15_IRQHandler + B MDMA_Channel15_IRQHandler + + PUBWEAK SDPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDPU_IRQHandler + B SDPU_IRQHandler + + PUBWEAK FPU_CPU1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_CPU1_IRQHandler + B FPU_CPU1_IRQHandler + + PUBWEAK ECCMON_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECCMON_IRQHandler + B ECCMON_IRQHandler + + PUBWEAK RTC_ALARM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_ALARM_IRQHandler + B RTC_ALARM_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK I2C6_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_EV_IRQHandler + B I2C6_EV_IRQHandler + + PUBWEAK I2C6_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_ER_IRQHandler + B I2C6_ER_IRQHandler + + PUBWEAK I2C7_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_EV_IRQHandler + B I2C7_EV_IRQHandler + + PUBWEAK I2C7_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_ER_IRQHandler + B I2C7_ER_IRQHandler + + PUBWEAK I2C8_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_EV_IRQHandler + B I2C8_EV_IRQHandler + + PUBWEAK I2C8_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_ER_IRQHandler + B I2C8_ER_IRQHandler + + PUBWEAK I2C9_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_EV_IRQHandler + B I2C9_EV_IRQHandler + + PUBWEAK I2C9_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_ER_IRQHandler + B I2C9_ER_IRQHandler + + PUBWEAK I2C10_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_EV_IRQHandler + B I2C10_EV_IRQHandler + + PUBWEAK I2C10_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_ER_IRQHandler + B I2C10_ER_IRQHandler + + PUBWEAK I2S1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S1_IRQHandler + B I2S1_IRQHandler + + PUBWEAK I2S2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S2_IRQHandler + B I2S2_IRQHandler + + PUBWEAK I2S3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S3_IRQHandler + B I2S3_IRQHandler + + PUBWEAK I2S4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S4_IRQHandler + B I2S4_IRQHandler + + PUBWEAK xSPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI1_IRQHandler + B xSPI1_IRQHandler + + PUBWEAK xSPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI2_IRQHandler + B xSPI2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SPI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI7_IRQHandler + B SPI7_IRQHandler + + PUBWEAK LCD_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_EV_IRQHandler + B LCD_EV_IRQHandler + + PUBWEAK LCD_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_ER_IRQHandler + B LCD_ER_IRQHandler + + PUBWEAK DVP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP1_IRQHandler + B DVP1_IRQHandler + + PUBWEAK DVP2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP2_IRQHandler + B DVP2_IRQHandler + + PUBWEAK DMAMUX2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX2_IRQHandler + B DMAMUX2_IRQHandler + + PUBWEAK USB1_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_OUT_IRQHandler + B USB1_HS_EPx_OUT_IRQHandler + + PUBWEAK USB1_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_IN_IRQHandler + B USB1_HS_EPx_IN_IRQHandler + + PUBWEAK USB1_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_WKUP_IRQHandler + B USB1_HS_WKUP_IRQHandler + + PUBWEAK USB1_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_IRQHandler + B USB1_HS_IRQHandler + + PUBWEAK USB2_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_OUT_IRQHandler + B USB2_HS_EPx_OUT_IRQHandler + + PUBWEAK USB2_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_IN_IRQHandler + B USB2_HS_EPx_IN_IRQHandler + + PUBWEAK USB2_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_WKUP_IRQHandler + B USB2_HS_WKUP_IRQHandler + + PUBWEAK USB2_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_IRQHandler + B USB2_HS_IRQHandler + + PUBWEAK ETH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_IRQHandler + B ETH1_IRQHandler + + PUBWEAK ETH1_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_PMT_LPI_IRQHandler + B ETH1_PMT_LPI_IRQHandler + + PUBWEAK ETH2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_IRQHandler + B ETH2_IRQHandler + + PUBWEAK ETH2_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_PMT_LPI_IRQHandler + B ETH2_PMT_LPI_IRQHandler + + PUBWEAK FDCAN1_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT0_IRQHandler + B FDCAN1_INT0_IRQHandler + + PUBWEAK FDCAN2_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT0_IRQHandler + B FDCAN2_INT0_IRQHandler + + PUBWEAK FDCAN3_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT0_IRQHandler + B FDCAN3_INT0_IRQHandler + + PUBWEAK FDCAN4_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT0_IRQHandler + B FDCAN4_INT0_IRQHandler + + PUBWEAK FDCAN1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT1_IRQHandler + B FDCAN1_INT1_IRQHandler + + PUBWEAK FDCAN2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT1_IRQHandler + B FDCAN2_INT1_IRQHandler + + PUBWEAK FDCAN3_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT1_IRQHandler + B FDCAN3_INT1_IRQHandler + + PUBWEAK FDCAN4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT1_IRQHandler + B FDCAN4_INT1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK USART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART7_IRQHandler + B USART7_IRQHandler + + PUBWEAK USART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART8_IRQHandler + B USART8_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK UART11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART11_IRQHandler + B UART11_IRQHandler + + PUBWEAK UART12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART12_IRQHandler + B UART12_IRQHandler + + PUBWEAK UART13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART13_IRQHandler + B UART13_IRQHandler + + PUBWEAK UART14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART14_IRQHandler + B UART14_IRQHandler + + PUBWEAK UART15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART15_IRQHandler + B UART15_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPUART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART2_IRQHandler + B LPUART2_IRQHandler + + PUBWEAK GPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPU_IRQHandler + B GPU_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK COMP1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP1_2_IRQHandler + B COMP1_2_IRQHandler + + PUBWEAK COMP3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP3_4_IRQHandler + B COMP3_4_IRQHandler + + PUBWEAK SHRTIM1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT1_IRQHandler + B SHRTIM1_INT1_IRQHandler + + PUBWEAK SHRTIM1_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT2_IRQHandler + B SHRTIM1_INT2_IRQHandler + + PUBWEAK SHRTIM1_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT3_IRQHandler + B SHRTIM1_INT3_IRQHandler + + PUBWEAK SHRTIM1_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT4_IRQHandler + B SHRTIM1_INT4_IRQHandler + + PUBWEAK SHRTIM1_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT5_IRQHandler + B SHRTIM1_INT5_IRQHandler + + PUBWEAK SHRTIM1_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT6_IRQHandler + B SHRTIM1_INT6_IRQHandler + + PUBWEAK SHRTIM1_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT7_IRQHandler + B SHRTIM1_INT7_IRQHandler + + PUBWEAK SHRTIM1_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT8_IRQHandler + B SHRTIM1_INT8_IRQHandler + + PUBWEAK SHRTIM2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT1_IRQHandler + B SHRTIM2_INT1_IRQHandler + + PUBWEAK SHRTIM2_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT2_IRQHandler + B SHRTIM2_INT2_IRQHandler + + PUBWEAK SHRTIM2_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT3_IRQHandler + B SHRTIM2_INT3_IRQHandler + + PUBWEAK SHRTIM2_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT4_IRQHandler + B SHRTIM2_INT4_IRQHandler + + PUBWEAK SHRTIM2_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT5_IRQHandler + B SHRTIM2_INT5_IRQHandler + + PUBWEAK SHRTIM2_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT6_IRQHandler + B SHRTIM2_INT6_IRQHandler + + PUBWEAK SHRTIM2_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT7_IRQHandler + B SHRTIM2_INT7_IRQHandler + + PUBWEAK SHRTIM2_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT8_IRQHandler + B SHRTIM2_INT8_IRQHandler + + PUBWEAK FDCAN5_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT0_IRQHandler + B FDCAN5_INT0_IRQHandler + + PUBWEAK FDCAN6_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT0_IRQHandler + B FDCAN6_INT0_IRQHandler + + PUBWEAK FDCAN7_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT0_IRQHandler + B FDCAN7_INT0_IRQHandler + + PUBWEAK FDCAN8_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT0_IRQHandler + B FDCAN8_INT0_IRQHandler + + PUBWEAK FDCAN5_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT1_IRQHandler + B FDCAN5_INT1_IRQHandler + + PUBWEAK FDCAN6_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT1_IRQHandler + B FDCAN6_INT1_IRQHandler + + PUBWEAK FDCAN7_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT1_IRQHandler + B FDCAN7_INT1_IRQHandler + + PUBWEAK FDCAN8_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT1_IRQHandler + B FDCAN8_INT1_IRQHandler + + PUBWEAK LPTIM5_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM5_WKUP_IRQHandler + B LPTIM5_WKUP_IRQHandler + + PUBWEAK JPEG_SGDMA_H2P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_H2P_IRQHandler + B JPEG_SGDMA_H2P_IRQHandler + + PUBWEAK JPEG_SGDMA_P2H_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_P2H_IRQHandler + B JPEG_SGDMA_P2H_IRQHandler + + PUBWEAK WAKEUP_IO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WAKEUP_IO_IRQHandler + B WAKEUP_IO_IRQHandler + + PUBWEAK SEMA4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_INT1_IRQHandler + B SEMA4_INT1_IRQHandler + + PUBWEAK WWDG2_RST_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_RST_IRQHandler + B WWDG2_RST_IRQHandler + + PUBWEAK OTPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTPC_IRQHandler + B OTPC_IRQHandler + + PUBWEAK FEMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FEMC_IRQHandler + B FEMC_IRQHandler + + PUBWEAK DCMUB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMUB_IRQHandler + B DCMUB_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK MDMA_AHBS_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_AHBS_ER_IRQHandler + B MDMA_AHBS_ER_IRQHandler + + PUBWEAK CM7_CATCH_READ_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CM7_CATCH_READ_ER_IRQHandler + B CM7_CATCH_READ_ER_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK DAC4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC4_IRQHandler + B DAC4_IRQHandler + + PUBWEAK EMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMC_IRQHandler + B EMC_IRQHandler + + PUBWEAK DAC5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC5_IRQHandler + B DAC5_IRQHandler + + PUBWEAK DAC6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC6_IRQHandler + B DAC6_IRQHandler + + PUBWEAK ESC_OPB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_OPB_IRQHandler + B ESC_OPB_IRQHandler + + PUBWEAK ESC_SYNC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC0_IRQHandler + B ESC_SYNC0_IRQHandler + + PUBWEAK ESC_SYNC1_RQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC1_RQHandler + B ESC_SYNC1_RQHandler + + PUBWEAK ESC_WRP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_WRP_IRQHandler + B ESC_WRP_IRQHandler + + PUBWEAK ATIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_BRK_IRQHandler + B ATIM1_BRK_IRQHandler + + PUBWEAK ATIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_TRG_COM_IRQHandler + B ATIM1_TRG_COM_IRQHandler + + PUBWEAK ATIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_CC_IRQHandler + B ATIM1_CC_IRQHandler + + PUBWEAK ATIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_UP_IRQHandler + B ATIM1_UP_IRQHandler + + PUBWEAK ATIM2_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_BRK_IRQHandler + B ATIM2_BRK_IRQHandler + + PUBWEAK ATIM2_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_TRG_COM_IRQHandler + B ATIM2_TRG_COM_IRQHandler + + PUBWEAK ATIM2_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_CC_IRQHandler + B ATIM2_CC_IRQHandler + + PUBWEAK ATIM2_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_UP_IRQHandler + B ATIM2_UP_IRQHandler + + PUBWEAK ATIM3_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_BRK_IRQHandler + B ATIM3_BRK_IRQHandler + + PUBWEAK ATIM3_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_TRG_COM_IRQHandler + B ATIM3_TRG_COM_IRQHandler + + PUBWEAK ATIM3_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_CC_IRQHandler + B ATIM3_CC_IRQHandler + + PUBWEAK ATIM3_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_UP_IRQHandler + B ATIM3_UP_IRQHandler + + PUBWEAK ATIM4_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_BRK_IRQHandler + B ATIM4_BRK_IRQHandler + + PUBWEAK ATIM4_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_TRG_COM_IRQHandler + B ATIM4_TRG_COM_IRQHandler + + PUBWEAK ATIM4_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_CC_IRQHandler + B ATIM4_CC_IRQHandler + + PUBWEAK ATIM4_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_UP_IRQHandler + B ATIM4_UP_IRQHandler + + PUBWEAK GTIMA1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA1_IRQHandler + B GTIMA1_IRQHandler + + PUBWEAK GTIMA2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA2_IRQHandler + B GTIMA2_IRQHandler + + PUBWEAK GTIMA3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA3_IRQHandler + B GTIMA3_IRQHandler + + PUBWEAK GTIMA4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA4_IRQHandler + B GTIMA4_IRQHandler + + PUBWEAK GTIMA5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA5_IRQHandler + B GTIMA5_IRQHandler + + PUBWEAK GTIMA6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA6_IRQHandler + B GTIMA6_IRQHandler + + PUBWEAK GTIMA7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA7_IRQHandler + B GTIMA7_IRQHandler + + PUBWEAK GTIMB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB1_IRQHandler + B GTIMB1_IRQHandler + + PUBWEAK GTIMB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB2_IRQHandler + B GTIMB2_IRQHandler + + PUBWEAK GTIMB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB3_IRQHandler + B GTIMB3_IRQHandler + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + PUBWEAK BTIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM4_IRQHandler + B BTIM4_IRQHandler + + PUBWEAK LPTIM1_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_WKUP_IRQHandler + B LPTIM1_WKUP_IRQHandler + + PUBWEAK LPTIM2_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM2_WKUP_IRQHandler + B LPTIM2_WKUP_IRQHandler + + PUBWEAK LPTIM3_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM3_WKUP_IRQHandler + B LPTIM3_WKUP_IRQHandler + + PUBWEAK LPTIM4_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM4_WKUP_IRQHandler + B LPTIM4_WKUP_IRQHandler + + PUBWEAK DSMU_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT0_IRQHandler + B DSMU_FLT0_IRQHandler + + PUBWEAK DSMU_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT1_IRQHandler + B DSMU_FLT1_IRQHandler + + PUBWEAK DSMU_FLT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT2_IRQHandler + B DSMU_FLT2_IRQHandler + + PUBWEAK DSMU_FLT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT3_IRQHandler + B DSMU_FLT3_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK DMAMUX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX1_IRQHandler + B DMAMUX1_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_gcc.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_gcc.s new file mode 100644 index 0000000000..cc03a036ab --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h73x_76x_gcc.s @@ -0,0 +1,1099 @@ +/********************************************************************************************************* + Copyright (c) 2024, Nations Technologies Inc. + + All rights reserved. + + This software is the exclusive property of Nations Technologies Inc. (Hereinafter + referred to as NATIONS). This software, and the product of NATIONS described herein + (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties + of the People's Republic of China and other applicable jurisdictions worldwide. + + NATIONS does not grant any license under its patents, copyrights, trademarks, or other + intellectual property rights. Names and brands of third party may be mentioned or referred + thereto (if any) for identification purposes only. + + NATIONS reserves the right to make changes, corrections, enhancements, modifications, and + improvements to this software at any time without notice. Please contact NATIONS and obtain + the latest version of this software before placing orders. + + Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes + no responsibility for the accuracy and reliability of this software. + + It is the responsibility of the user of this software to properly design, program, and test + the functionality and safety of any application made of this information and any resulting product. + In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or + consequential damages arising in any way out of the use of this software or the Product. + + NATIONS Products are neither intended nor warranted for usage in systems or equipment, any + malfunction or failure of which may cause loss of human life, bodily injury or severe property + damage. Such applications are deemed, "Insecure Usage". + + All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS + harmless from and against all claims, costs, damages, and other liabilities, arising from or related + to any customer's Insecure Usage. + + Any express or implied warranty with regard to this software or the Product, including,but not + limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement + are disclaimed to the fullest extent permitted by law. + + Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe + or otherwise distribute this software for any purposes, in whole or in part. + + NATIONS products and technologies shall not be used for or incorporated into any products or systems + whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. + User shall comply with any applicable export control laws and regulations promulgated and administered by + the governments of any countries asserting jurisdiction over the parties or transactions. + ************************************************************************************************************/ + + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** +\*fun This is the code that gets called when the processor receives an +\* unexpected interrupt. This simply enters an infinite loop, preserving +\* the system state for examination by a debugger. +**/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/** +\* The minimal vector table for a Cortex M0. Note that the proper constructs +\* must be placed on this to ensure that it ends up at physical address 0x00000000. +**/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word N32SysTick_Handler + /* External Interrupts */ + .word WWDG1_IRQHandler /* Window1 Watchdog interrupt */ + .word PVD_IRQHandler /* PVD through EXTI Line16 detection interrupt */ + .word RTC_TAMPER_IRQHandler /* RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup timer through EXTI line 19 interrupt */ + .word RCC_IRQHandler /* RCC interrupt */ + .word EXTI0_IRQHandler /* EXTI Line 0 interrupt */ + .word EXTI1_IRQHandler /* EXTI Line 1 interrupt */ + .word EXTI2_IRQHandler /* EXTI Line 2 interrupt */ + .word EXTI3_IRQHandler /* EXTI Line 3 interrupt */ + .word EXTI4_IRQHandler /* EXTI Line 4 interrupt */ + .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupt */ + .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupt */ + .word DMA1_Channel0_IRQHandler /* DMA1 Channel 0 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA2_Channel0_IRQHandler /* DMA2 Channel 0 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA3_Channel0_IRQHandler /* DMA3 Channel 0 */ + .word DMA3_Channel1_IRQHandler /* DMA3 Channel 1 */ + .word DMA3_Channel2_IRQHandler /* DMA3 Channel 2 */ + .word DMA3_Channel3_IRQHandler /* DMA3 Channel 3 */ + .word DMA3_Channel4_IRQHandler /* DMA3 Channel 4 */ + .word DMA3_Channel5_IRQHandler /* DMA3 Channel 5 */ + .word DMA3_Channel6_IRQHandler /* DMA3 Channel 6 */ + .word DMA3_Channel7_IRQHandler /* DMA3 Channel 7 */ + .word MDMA_Channel0_IRQHandler /* MDMA Channel 0 */ + .word MDMA_Channel1_IRQHandler /* MDMA Channel 1 */ + .word MDMA_Channel2_IRQHandler /* MDMA Channel 2 */ + .word MDMA_Channel3_IRQHandler /* MDMA Channel 3 */ + .word MDMA_Channel4_IRQHandler /* MDMA Channel 4 */ + .word MDMA_Channel5_IRQHandler /* MDMA Channel 5 */ + .word MDMA_Channel6_IRQHandler /* MDMA Channel 6 */ + .word MDMA_Channel7_IRQHandler /* MDMA Channel 7 */ + .word MDMA_Channel8_IRQHandler /* MDMA Channel 8 */ + .word MDMA_Channel9_IRQHandler /* MDMA Channel 9 */ + .word MDMA_Channel10_IRQHandler /* MDMA Channel 10 */ + .word MDMA_Channel11_IRQHandler /* MDMA Channel 11 */ + .word MDMA_Channel12_IRQHandler /* MDMA Channel 12 */ + .word MDMA_Channel13_IRQHandler /* MDMA Channel 13 */ + .word MDMA_Channel14_IRQHandler /* MDMA Channel 14 */ + .word MDMA_Channel15_IRQHandler /* MDMA Channel 15 */ + .word SDPU_IRQHandler /* SDPU global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_CPU1_IRQHandler /* FPU_CM7 global interrupt */ + .word ECCMON_IRQHandler /* ECCMON global interrupt */ + .word RTC_ALARM_IRQHandler /* RTC Alarm via EXTI17 interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ + .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 event interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 error interrupt */ + .word I2C6_EV_IRQHandler /* I2C6 event interrupt */ + .word I2C6_ER_IRQHandler /* I2C6 error interrupt */ + .word I2C7_EV_IRQHandler /* I2C7 event interrupt */ + .word I2C7_ER_IRQHandler /* I2C7 error interrupt */ + .word I2C8_EV_IRQHandler /* I2C8 event interrupt */ + .word I2C8_ER_IRQHandler /* I2C8 error interrupt */ + .word I2C9_EV_IRQHandler /* I2C9 event interrupt */ + .word I2C9_ER_IRQHandler /* I2C9 error interrupt */ + .word I2C10_EV_IRQHandler /* I2C10 event interrupt */ + .word I2C10_ER_IRQHandler /* I2C10 error interrupt */ + .word I2S1_IRQHandler /* I2S1 global interrupt */ + .word I2S2_IRQHandler /* I2S1 global interrupt */ + .word I2S3_IRQHandler /* I2S1 global interrupt */ + .word I2S4_IRQHandler /* I2S1 global interrupt */ + .word xSPI1_IRQHandler /* xSPI1 global interrupt */ + .word xSPI2_IRQHandler /* xSPI1 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word SPI3_IRQHandler /* SPI3 global interrupt */ + .word SPI4_IRQHandler /* SPI4 global interrupt */ + .word SPI5_IRQHandler /* SPI5 global interrupt */ + .word SPI6_IRQHandler /* SPI6 global interrupt */ + .word SPI7_IRQHandler /* SPI7 global interrupt */ + .word LCD_EV_IRQHandler /* TFT LCD Controller event interrupt */ + .word LCD_ER_IRQHandler /* TFT LCD Controller error interrupt */ + .word DVP1_IRQHandler /* DVP1 global interrupt */ + .word DVP2_IRQHandler /* DVP2 global interrupt */ + .word DMAMUX2_IRQHandler /* DMAMUX2 (MDMA MUX) global interrupt */ + .word USB1_HS_EPx_OUT_IRQHandler /* USB1_HS endpoint out global interrupt */ + .word USB1_HS_EPx_IN_IRQHandler /* USB1_HS endpoint in global interrupt */ + .word USB1_HS_WKUP_IRQHandler /* USB1_HS WKUP interrupt through EXTI line 62 */ + .word USB1_HS_IRQHandler /* USB1_HS global interrupt */ + .word USB2_HS_EPx_OUT_IRQHandler /* USB2_HS endpoint out global interrupt */ + .word USB2_HS_EPx_IN_IRQHandler /* USB2_HS endpoint in global interrupt */ + .word USB2_HS_WKUP_IRQHandler /* USB2_HS WKUP interrupt through EXTI line 63 */ + .word USB2_HS_IRQHandler /* USB2_HS global interrupt */ + .word ETH1_IRQHandler /* Ethernet 1 global interrupt */ + .word ETH1_PMT_LPI_IRQHandler /* Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 */ + .word ETH2_IRQHandler /* Ethernet 2 global interrupt */ + .word ETH2_PMT_LPI_IRQHandler /* Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 */ + .word FDCAN1_INT0_IRQHandler /* FDCAN1 global interrupt line 0 */ + .word FDCAN2_INT0_IRQHandler /* FDCAN2 global interrupt line 0 */ + .word FDCAN3_INT0_IRQHandler /* FDCAN3 global interrupt line 0 */ + .word FDCAN4_INT0_IRQHandler /* FDCAN4 global interrupt line 0 */ + .word FDCAN1_INT1_IRQHandler /* FDCAN1 global interrupt line 1 */ + .word FDCAN2_INT1_IRQHandler /* FDCAN2 global interrupt line 1 */ + .word FDCAN3_INT1_IRQHandler /* FDCAN3 global interrupt line 1 */ + .word FDCAN4_INT1_IRQHandler /* FDCAN4 global interrupt line 1 */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word USART3_IRQHandler /* USART3 global interrupt */ + .word USART4_IRQHandler /* USART4 global interrupt */ + .word USART5_IRQHandler /* USART5 global interrupt */ + .word USART6_IRQHandler /* USART6 global interrupt */ + .word USART7_IRQHandler /* USART7 global interrupt */ + .word USART8_IRQHandler /* USART8 global interrupt */ + .word UART9_IRQHandler /* UART9 global interrupt */ + .word UART10_IRQHandler /* UART10 global interrupt */ + .word UART11_IRQHandler /* UART11 global interrupt */ + .word UART12_IRQHandler /* UART12 global interrupt */ + .word UART13_IRQHandler /* UART13 global interrupt */ + .word UART14_IRQHandler /* UART14 global interrupt */ + .word UART15_IRQHandler /* UART15 global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt + wakeup through EXTI line 49 */ + .word LPUART2_IRQHandler /* LPUART2 global interrupt + wakeup through EXTI line 52 */ + .word GPU_IRQHandler /* GPU global interrupt */ + .word 0 /* Reserved */ + .word SDMMC1_IRQHandler /* SDMMC1_IRQ + WKUP through EXTI line 24 */ + .word SDMMC2_IRQHandler /* SDMMC2_IRQ + WKUP through EXTI line 25 */ + .word ADC1_IRQHandler /* ADC1 global interrupt */ + .word ADC2_IRQHandler /* ADC2 global interrupt */ + .word ADC3_IRQHandler /* ADC3 global interrupt */ + .word COMP1_2_IRQHandler /* COMP1 and COMP2 through EXTI line 20 and 21 */ + .word COMP3_4_IRQHandler /* COMP3 and COMP4 through EXTI line 22 and 23 */ + .word SHRTIM1_INT1_IRQHandler /* High Resolution timer 1 interrupt 1 */ + .word SHRTIM1_INT2_IRQHandler /* High Resolution timer 1 interrupt 2 */ + .word SHRTIM1_INT3_IRQHandler /* High Resolution timer 1 interrupt 3 */ + .word SHRTIM1_INT4_IRQHandler /* High Resolution timer 1 interrupt 4 */ + .word SHRTIM1_INT5_IRQHandler /* High Resolution timer 1 interrupt 5 */ + .word SHRTIM1_INT6_IRQHandler /* High Resolution timer 1 interrupt 6 */ + .word SHRTIM1_INT7_IRQHandler /* High Resolution timer 1 interrupt 7 */ + .word SHRTIM1_INT8_IRQHandler /* High Resolution timer 1 interrupt 8 */ + .word SHRTIM2_INT1_IRQHandler /* High Resolution timer 2 interrupt 1 */ + .word SHRTIM2_INT2_IRQHandler /* High Resolution timer 2 interrupt 2 */ + .word SHRTIM2_INT3_IRQHandler /* High Resolution timer 2 interrupt 3 */ + .word SHRTIM2_INT4_IRQHandler /* High Resolution timer 2 interrupt 4 */ + .word SHRTIM2_INT5_IRQHandler /* High Resolution timer 2 interrupt 5 */ + .word SHRTIM2_INT6_IRQHandler /* High Resolution timer 2 interrupt 6 */ + .word SHRTIM2_INT7_IRQHandler /* High Resolution timer 2 interrupt 7 */ + .word SHRTIM2_INT8_IRQHandler /* High Resolution timer 2 interrupt 8 */ + .word FDCAN5_INT0_IRQHandler /* FDCAN5 global interrupt line 0 */ + .word FDCAN6_INT0_IRQHandler /* FDCAN6 global interrupt line 0 */ + .word FDCAN7_INT0_IRQHandler /* FDCAN7 global interrupt line 0 */ + .word FDCAN8_INT0_IRQHandler /* FDCAN8 global interrupt line 0 */ + .word FDCAN5_INT1_IRQHandler /* FDCAN5 global interrupt line 1 */ + .word FDCAN6_INT1_IRQHandler /* FDCAN6 global interrupt line 1 */ + .word FDCAN7_INT1_IRQHandler /* FDCAN7 global interrupt line 1 */ + .word FDCAN8_INT1_IRQHandler /* FDCAN8 global interrupt line 1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word LPTIM5_WKUP_IRQHandler /* LPTIM5 wakeup through EXTI 86 */ + .word JPEG_SGDMA_H2P_IRQHandler /* JPEG SGDMA Host to Peripheral Interrupt */ + .word JPEG_SGDMA_P2H_IRQHandler /* JPEG SGDMA Peripheral to Host Interrupt */ + .word WAKEUP_IO_IRQHandler /* 6 WAKEUP IOs through EXTI line 70-75 */ + .word SEMA4_INT1_IRQHandler /* SEMA4 interrupt1 */ + .word 0 /* Reserved */ + .word WWDG2_RST_IRQHandler /* WWDG2 reset interrupt through EXTI line 82 */ + .word OTPC_IRQHandler /* OTPC interrupt */ + .word FEMC_IRQHandler /* FEMC interrupt */ + .word DCMUB_IRQHandler /* DCMUB interrupt */ + .word DAC1_IRQHandler /* DAC1 interrupt */ + .word DAC2_IRQHandler /* DAC2 interrupt */ + .word MDMA_AHBS_ER_IRQHandler /* MDMA HABS ERROR through EXTI line55-56 */ + .word CM7_CATCH_READ_ER_IRQHandler /* CM7 Error on Cache Read through EXTI line 64-65 */ + .word DAC3_IRQHandler /* DAC3 interrupt */ + .word DAC4_IRQHandler /* DAC4 interrupt */ + .word EMC_IRQHandler /* EMC event interrupt through EXTI line 88-89 */ + .word DAC5_IRQHandler /* DAC5 interrupt */ + .word DAC6_IRQHandler /* DAC6 interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ATIM1_BRK_IRQHandler /* Advanced timer 1 break interrupt */ + .word ATIM1_TRG_COM_IRQHandler /* Advanced timer 1 trigger and commutation interrupts */ + .word ATIM1_CC_IRQHandler /* Advanced timer 1 capture/compare interrupt */ + .word ATIM1_UP_IRQHandler /* Advanced timer 1 update interrupt */ + .word ATIM2_BRK_IRQHandler /* Advanced timer 2 break interrupt */ + .word ATIM2_TRG_COM_IRQHandler /* advanced timer 2 trigger and commutation interrupts */ + .word ATIM2_CC_IRQHandler /* Advanced timer 2 capture/compare interrupt */ + .word ATIM2_UP_IRQHandler /* Advanced timer 2 update interrupt */ + .word ATIM3_BRK_IRQHandler /* Advanced timer 3 break interrupt */ + .word ATIM3_TRG_COM_IRQHandler /* Advanced timer 3 trigger and commutation interrupts */ + .word ATIM3_CC_IRQHandler /* Advanced timer 3 capture/compare interrupt */ + .word ATIM3_UP_IRQHandler /* Advanced timer 3 update interrupt */ + .word ATIM4_BRK_IRQHandler /* Advanced timer 4 break interrupt */ + .word ATIM4_TRG_COM_IRQHandler /* Advanced timer 4 trigger and commutation interrupts */ + .word ATIM4_CC_IRQHandler /* Advanced timer 4 capture/compare interrupt */ + .word ATIM4_UP_IRQHandler /* Advanced timer 4 update interrupt */ + .word GTIMA1_IRQHandler /* General timer A1 global interrupt */ + .word GTIMA2_IRQHandler /* General timer A2 global interrupt */ + .word GTIMA3_IRQHandler /* General timer A3 global interrupt */ + .word GTIMA4_IRQHandler /* General timer A4 global interrupt */ + .word GTIMA5_IRQHandler /* General timer A5 global interrupt */ + .word GTIMA6_IRQHandler /* General timer A6 global interrupt */ + .word GTIMA7_IRQHandler /* General timer A7 global interrupt */ + .word GTIMB1_IRQHandler /* General timer B1 global interrupt */ + .word GTIMB2_IRQHandler /* General timer B2 global interrupt */ + .word GTIMB3_IRQHandler /* General timer B3 global interrupt */ + .word BTIM1_IRQHandler /* Base timer 1 global interrupt */ + .word BTIM2_IRQHandler /* Base timer 2 global interrupt */ + .word BTIM3_IRQHandler /* Base timer 3 global interrupt */ + .word BTIM4_IRQHandler /* Base timer 4 global interrupt */ + .word LPTIM1_WKUP_IRQHandler /* LPTIM1 wakeup interrupt */ + .word LPTIM2_WKUP_IRQHandler /* LPTIM2 wakeup interrupt */ + .word LPTIM3_WKUP_IRQHandler /* LPTIM3 wakeup interrupt */ + .word LPTIM4_WKUP_IRQHandler /* LPTIM4 wakeup interrupt */ + .word DSMU_FLT0_IRQHandler /* DSMU Filter interrupt 0 */ + .word DSMU_FLT1_IRQHandler /* DSMU Filter interrupt 1 */ + .word DSMU_FLT2_IRQHandler /* DSMU Filter interrupt 2 */ + .word DSMU_FLT3_IRQHandler /* DSMU Filter interrupt 3 */ + .word FMAC_IRQHandler /* FMAC global interrupt */ + .word CORDIC_IRQHandler /* Cordic global interrupt */ + .word DMAMUX1_IRQHandler /* DMAMUX1 interrupt */ + .word MMU_IRQHandler /* MMU interrupt */ + .word SysTick_Handler + /* need check to user manual of exti chapter */ + +/** +\* Provide weak aliases for each Exception handler to the Default_Handler. +\* As they are weak aliases, any function with the same name will override +\* this definition. +**/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak N32SysTick_Handler + .thumb_set N32SysTick_Handler,Default_Handler + + .weak WWDG1_IRQHandler + .thumb_set WWDG1_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMPER_IRQHandler + .thumb_set RTC_TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak DMA1_Channel0_IRQHandler + .thumb_set DMA1_Channel0_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel0_IRQHandler + .thumb_set DMA2_Channel0_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA3_Channel0_IRQHandler + .thumb_set DMA3_Channel0_IRQHandler,Default_Handler + + .weak DMA3_Channel1_IRQHandler + .thumb_set DMA3_Channel1_IRQHandler,Default_Handler + + .weak DMA3_Channel2_IRQHandler + .thumb_set DMA3_Channel2_IRQHandler,Default_Handler + + .weak DMA3_Channel3_IRQHandler + .thumb_set DMA3_Channel3_IRQHandler,Default_Handler + + .weak DMA3_Channel4_IRQHandler + .thumb_set DMA3_Channel4_IRQHandler,Default_Handler + + .weak DMA3_Channel5_IRQHandler + .thumb_set DMA3_Channel5_IRQHandler,Default_Handler + + .weak DMA3_Channel6_IRQHandler + .thumb_set DMA3_Channel6_IRQHandler,Default_Handler + + .weak DMA3_Channel7_IRQHandler + .thumb_set DMA3_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel0_IRQHandler + .thumb_set MDMA_Channel0_IRQHandler,Default_Handler + + .weak MDMA_Channel1_IRQHandler + .thumb_set MDMA_Channel1_IRQHandler,Default_Handler + + .weak MDMA_Channel2_IRQHandler + .thumb_set MDMA_Channel2_IRQHandler,Default_Handler + + .weak MDMA_Channel3_IRQHandler + .thumb_set MDMA_Channel3_IRQHandler,Default_Handler + + .weak MDMA_Channel4_IRQHandler + .thumb_set MDMA_Channel4_IRQHandler,Default_Handler + + .weak MDMA_Channel5_IRQHandler + .thumb_set MDMA_Channel5_IRQHandler,Default_Handler + + .weak MDMA_Channel6_IRQHandler + .thumb_set MDMA_Channel6_IRQHandler,Default_Handler + + .weak MDMA_Channel7_IRQHandler + .thumb_set MDMA_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel8_IRQHandler + .thumb_set MDMA_Channel8_IRQHandler,Default_Handler + + .weak MDMA_Channel9_IRQHandler + .thumb_set MDMA_Channel9_IRQHandler,Default_Handler + + .weak MDMA_Channel10_IRQHandler + .thumb_set MDMA_Channel10_IRQHandler,Default_Handler + + .weak MDMA_Channel11_IRQHandler + .thumb_set MDMA_Channel11_IRQHandler,Default_Handler + + .weak MDMA_Channel12_IRQHandler + .thumb_set MDMA_Channel12_IRQHandler,Default_Handler + + .weak MDMA_Channel13_IRQHandler + .thumb_set MDMA_Channel13_IRQHandler,Default_Handler + + .weak MDMA_Channel14_IRQHandler + .thumb_set MDMA_Channel14_IRQHandler,Default_Handler + + .weak MDMA_Channel15_IRQHandler + .thumb_set MDMA_Channel15_IRQHandler,Default_Handler + + .weak SDPU_IRQHandler + .thumb_set SDPU_IRQHandler,Default_Handler + + .weak FPU_CPU1_IRQHandler + .thumb_set FPU_CPU1_IRQHandler,Default_Handler + + .weak ECCMON_IRQHandler + .thumb_set ECCMON_IRQHandler,Default_Handler + + .weak RTC_ALARM_IRQHandler + .thumb_set RTC_ALARM_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak I2C6_EV_IRQHandler + .thumb_set I2C6_EV_IRQHandler,Default_Handler + + .weak I2C6_ER_IRQHandler + .thumb_set I2C6_ER_IRQHandler,Default_Handler + + .weak I2C7_EV_IRQHandler + .thumb_set I2C7_EV_IRQHandler,Default_Handler + + .weak I2C7_ER_IRQHandler + .thumb_set I2C7_ER_IRQHandler,Default_Handler + + .weak I2C8_EV_IRQHandler + .thumb_set I2C8_EV_IRQHandler,Default_Handler + + .weak I2C8_ER_IRQHandler + .thumb_set I2C8_ER_IRQHandler,Default_Handler + + .weak I2C9_EV_IRQHandler + .thumb_set I2C9_EV_IRQHandler,Default_Handler + + .weak I2C9_ER_IRQHandler + .thumb_set I2C9_ER_IRQHandler,Default_Handler + + .weak I2C10_EV_IRQHandler + .thumb_set I2C10_EV_IRQHandler,Default_Handler + + .weak I2C10_ER_IRQHandler + .thumb_set I2C10_ER_IRQHandler,Default_Handler + + .weak I2S1_IRQHandler + .thumb_set I2S1_IRQHandler,Default_Handler + + .weak I2S2_IRQHandler + .thumb_set I2S2_IRQHandler,Default_Handler + + .weak I2S3_IRQHandler + .thumb_set I2S3_IRQHandler,Default_Handler + + .weak I2S4_IRQHandler + .thumb_set I2S4_IRQHandler,Default_Handler + + .weak xSPI1_IRQHandler + .thumb_set xSPI1_IRQHandler,Default_Handler + + .weak xSPI2_IRQHandler + .thumb_set xSPI2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SPI7_IRQHandler + .thumb_set SPI7_IRQHandler,Default_Handler + + .weak LCD_EV_IRQHandler + .thumb_set LCD_EV_IRQHandler,Default_Handler + + .weak LCD_ER_IRQHandler + .thumb_set LCD_ER_IRQHandler,Default_Handler + + .weak DVP1_IRQHandler + .thumb_set DVP1_IRQHandler,Default_Handler + + .weak DVP2_IRQHandler + .thumb_set DVP2_IRQHandler,Default_Handler + + .weak DMAMUX2_IRQHandler + .thumb_set DMAMUX2_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_OUT_IRQHandler + .thumb_set USB1_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_IN_IRQHandler + .thumb_set USB1_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB1_HS_WKUP_IRQHandler + .thumb_set USB1_HS_WKUP_IRQHandler,Default_Handler + + .weak USB1_HS_IRQHandler + .thumb_set USB1_HS_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_OUT_IRQHandler + .thumb_set USB2_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_IN_IRQHandler + .thumb_set USB2_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB2_HS_WKUP_IRQHandler + .thumb_set USB2_HS_WKUP_IRQHandler,Default_Handler + + .weak USB2_HS_IRQHandler + .thumb_set USB2_HS_IRQHandler,Default_Handler + + .weak ETH1_IRQHandler + .thumb_set ETH1_IRQHandler,Default_Handler + + .weak ETH1_PMT_LPI_IRQHandler + .thumb_set ETH1_PMT_LPI_IRQHandler,Default_Handler + + .weak ETH2_IRQHandler + .thumb_set ETH2_IRQHandler,Default_Handler + + .weak ETH2_PMT_LPI_IRQHandler + .thumb_set ETH2_PMT_LPI_IRQHandler,Default_Handler + + .weak FDCAN1_INT0_IRQHandler + .thumb_set FDCAN1_INT0_IRQHandler,Default_Handler + + .weak FDCAN2_INT0_IRQHandler + .thumb_set FDCAN2_INT0_IRQHandler,Default_Handler + + .weak FDCAN3_INT0_IRQHandler + .thumb_set FDCAN3_INT0_IRQHandler,Default_Handler + + .weak FDCAN4_INT0_IRQHandler + .thumb_set FDCAN4_INT0_IRQHandler,Default_Handler + + .weak FDCAN1_INT1_IRQHandler + .thumb_set FDCAN1_INT1_IRQHandler,Default_Handler + + .weak FDCAN2_INT1_IRQHandler + .thumb_set FDCAN2_INT1_IRQHandler,Default_Handler + + .weak FDCAN3_INT1_IRQHandler + .thumb_set FDCAN3_INT1_IRQHandler,Default_Handler + + .weak FDCAN4_INT1_IRQHandler + .thumb_set FDCAN4_INT1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak UART10_IRQHandler + .thumb_set UART10_IRQHandler,Default_Handler + + .weak UART11_IRQHandler + .thumb_set UART11_IRQHandler,Default_Handler + + .weak UART12_IRQHandler + .thumb_set UART12_IRQHandler,Default_Handler + + .weak UART13_IRQHandler + .thumb_set UART13_IRQHandler,Default_Handler + + .weak UART14_IRQHandler + .thumb_set UART14_IRQHandler,Default_Handler + + .weak UART15_IRQHandler + .thumb_set UART15_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPUART2_IRQHandler + .thumb_set LPUART2_IRQHandler,Default_Handler + + .weak GPU_IRQHandler + .thumb_set GPU_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler,Default_Handler + + .weak COMP3_4_IRQHandler + .thumb_set COMP3_4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT1_IRQHandler + .thumb_set SHRTIM1_INT1_IRQHandler,Default_Handler + + .weak SHRTIM1_INT2_IRQHandler + .thumb_set SHRTIM1_INT2_IRQHandler,Default_Handler + + .weak SHRTIM1_INT3_IRQHandler + .thumb_set SHRTIM1_INT3_IRQHandler,Default_Handler + + .weak SHRTIM1_INT4_IRQHandler + .thumb_set SHRTIM1_INT4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT5_IRQHandler + .thumb_set SHRTIM1_INT5_IRQHandler,Default_Handler + + .weak SHRTIM1_INT6_IRQHandler + .thumb_set SHRTIM1_INT6_IRQHandler,Default_Handler + + .weak SHRTIM1_INT7_IRQHandler + .thumb_set SHRTIM1_INT7_IRQHandler,Default_Handler + + .weak SHRTIM1_INT8_IRQHandler + .thumb_set SHRTIM1_INT8_IRQHandler,Default_Handler + + .weak SHRTIM2_INT1_IRQHandler + .thumb_set SHRTIM2_INT1_IRQHandler,Default_Handler + + .weak SHRTIM2_INT2_IRQHandler + .thumb_set SHRTIM2_INT2_IRQHandler,Default_Handler + + .weak SHRTIM2_INT3_IRQHandler + .thumb_set SHRTIM2_INT3_IRQHandler,Default_Handler + + .weak SHRTIM2_INT4_IRQHandler + .thumb_set SHRTIM2_INT4_IRQHandler,Default_Handler + + .weak SHRTIM2_INT5_IRQHandler + .thumb_set SHRTIM2_INT5_IRQHandler,Default_Handler + + .weak SHRTIM2_INT6_IRQHandler + .thumb_set SHRTIM2_INT6_IRQHandler,Default_Handler + + .weak SHRTIM2_INT7_IRQHandler + .thumb_set SHRTIM2_INT7_IRQHandler,Default_Handler + + .weak SHRTIM2_INT8_IRQHandler + .thumb_set SHRTIM2_INT8_IRQHandler,Default_Handler + + .weak FDCAN5_INT0_IRQHandler + .thumb_set FDCAN5_INT0_IRQHandler,Default_Handler + + .weak FDCAN6_INT0_IRQHandler + .thumb_set FDCAN6_INT0_IRQHandler,Default_Handler + + .weak FDCAN7_INT0_IRQHandler + .thumb_set FDCAN7_INT0_IRQHandler,Default_Handler + + .weak FDCAN8_INT0_IRQHandler + .thumb_set FDCAN8_INT0_IRQHandler,Default_Handler + + .weak FDCAN5_INT1_IRQHandler + .thumb_set FDCAN5_INT1_IRQHandler,Default_Handler + + .weak FDCAN6_INT1_IRQHandler + .thumb_set FDCAN6_INT1_IRQHandler,Default_Handler + + .weak FDCAN7_INT1_IRQHandler + .thumb_set FDCAN7_INT1_IRQHandler,Default_Handler + + .weak FDCAN8_INT1_IRQHandler + .thumb_set FDCAN8_INT1_IRQHandler,Default_Handler + + .weak LPTIM5_WKUP_IRQHandler + .thumb_set LPTIM5_WKUP_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_H2P_IRQHandler + .thumb_set JPEG_SGDMA_H2P_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_P2H_IRQHandler + .thumb_set JPEG_SGDMA_P2H_IRQHandler,Default_Handler + + .weak WAKEUP_IO_IRQHandler + .thumb_set WAKEUP_IO_IRQHandler,Default_Handler + + .weak SEMA4_INT1_IRQHandler + .thumb_set SEMA4_INT1_IRQHandler,Default_Handler + + .weak WWDG2_RST_IRQHandler + .thumb_set WWDG2_RST_IRQHandler,Default_Handler + + .weak OTPC_IRQHandler + .thumb_set OTPC_IRQHandler,Default_Handler + + .weak FEMC_IRQHandler + .thumb_set FEMC_IRQHandler,Default_Handler + + .weak DCMUB_IRQHandler + .thumb_set DCMUB_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak DAC2_IRQHandler + .thumb_set DAC2_IRQHandler,Default_Handler + + .weak MDMA_AHBS_ER_IRQHandler + .thumb_set MDMA_AHBS_ER_IRQHandler,Default_Handler + + .weak CM7_CATCH_READ_ER_IRQHandler + .thumb_set CM7_CATCH_READ_ER_IRQHandler,Default_Handler + + .weak DAC3_IRQHandler + .thumb_set DAC3_IRQHandler,Default_Handler + + .weak DAC4_IRQHandler + .thumb_set DAC4_IRQHandler,Default_Handler + + .weak EMC_IRQHandler + .thumb_set EMC_IRQHandler,Default_Handler + + .weak DAC5_IRQHandler + .thumb_set DAC5_IRQHandler,Default_Handler + + .weak DAC6_IRQHandler + .thumb_set DAC6_IRQHandler,Default_Handler + + .weak ATIM1_BRK_IRQHandler + .thumb_set ATIM1_BRK_IRQHandler,Default_Handler + + .weak ATIM1_TRG_COM_IRQHandler + .thumb_set ATIM1_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM1_CC_IRQHandler + .thumb_set ATIM1_CC_IRQHandler,Default_Handler + + .weak ATIM1_UP_IRQHandler + .thumb_set ATIM1_UP_IRQHandler,Default_Handler + + .weak ATIM2_BRK_IRQHandler + .thumb_set ATIM2_BRK_IRQHandler,Default_Handler + + .weak ATIM2_TRG_COM_IRQHandler + .thumb_set ATIM2_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM2_CC_IRQHandler + .thumb_set ATIM2_CC_IRQHandler,Default_Handler + + .weak ATIM2_UP_IRQHandler + .thumb_set ATIM2_UP_IRQHandler,Default_Handler + + .weak ATIM3_BRK_IRQHandler + .thumb_set ATIM3_BRK_IRQHandler,Default_Handler + + .weak ATIM3_TRG_COM_IRQHandler + .thumb_set ATIM3_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM3_CC_IRQHandler + .thumb_set ATIM3_CC_IRQHandler,Default_Handler + + .weak ATIM3_UP_IRQHandler + .thumb_set ATIM3_UP_IRQHandler,Default_Handler + + .weak ATIM4_BRK_IRQHandler + .thumb_set ATIM4_BRK_IRQHandler,Default_Handler + + .weak ATIM4_TRG_COM_IRQHandler + .thumb_set ATIM4_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM4_CC_IRQHandler + .thumb_set ATIM4_CC_IRQHandler,Default_Handler + + .weak ATIM4_UP_IRQHandler + .thumb_set ATIM4_UP_IRQHandler,Default_Handler + + .weak GTIMA1_IRQHandler + .thumb_set GTIMA1_IRQHandler,Default_Handler + + .weak GTIMA2_IRQHandler + .thumb_set GTIMA2_IRQHandler,Default_Handler + + .weak GTIMA3_IRQHandler + .thumb_set GTIMA3_IRQHandler,Default_Handler + + .weak GTIMA4_IRQHandler + .thumb_set GTIMA4_IRQHandler,Default_Handler + + .weak GTIMA5_IRQHandler + .thumb_set GTIMA5_IRQHandler,Default_Handler + + .weak GTIMA6_IRQHandler + .thumb_set GTIMA6_IRQHandler,Default_Handler + + .weak GTIMA7_IRQHandler + .thumb_set GTIMA7_IRQHandler,Default_Handler + + .weak GTIMB1_IRQHandler + .thumb_set GTIMB1_IRQHandler,Default_Handler + + .weak GTIMB2_IRQHandler + .thumb_set GTIMB2_IRQHandler,Default_Handler + + .weak GTIMB3_IRQHandler + .thumb_set GTIMB3_IRQHandler,Default_Handler + + .weak BTIM1_IRQHandler + .thumb_set BTIM1_IRQHandler,Default_Handler + + .weak BTIM2_IRQHandler + .thumb_set BTIM2_IRQHandler,Default_Handler + + .weak BTIM3_IRQHandler + .thumb_set BTIM3_IRQHandler,Default_Handler + + .weak BTIM4_IRQHandler + .thumb_set BTIM4_IRQHandler,Default_Handler + + .weak LPTIM1_WKUP_IRQHandler + .thumb_set LPTIM1_WKUP_IRQHandler,Default_Handler + + .weak LPTIM2_WKUP_IRQHandler + .thumb_set LPTIM2_WKUP_IRQHandler,Default_Handler + + .weak LPTIM3_WKUP_IRQHandler + .thumb_set LPTIM3_WKUP_IRQHandler,Default_Handler + + .weak LPTIM4_WKUP_IRQHandler + .thumb_set LPTIM4_WKUP_IRQHandler,Default_Handler + + .weak DSMU_FLT0_IRQHandler + .thumb_set DSMU_FLT0_IRQHandler,Default_Handler + + .weak DSMU_FLT1_IRQHandler + .thumb_set DSMU_FLT1_IRQHandler,Default_Handler + + .weak DSMU_FLT2_IRQHandler + .thumb_set DSMU_FLT2_IRQHandler,Default_Handler + + .weak DSMU_FLT3_IRQHandler + .thumb_set DSMU_FLT3_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak DMAMUX1_IRQHandler + .thumb_set DMAMUX1_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h76x_ITCM_gcc.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h76x_ITCM_gcc.s new file mode 100644 index 0000000000..9283bf1383 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h76x_ITCM_gcc.s @@ -0,0 +1,1126 @@ +/********************************************************************************************************* + Copyright (c) 2024, Nations Technologies Inc. + + All rights reserved. + + This software is the exclusive property of Nations Technologies Inc. (Hereinafter + referred to as NATIONS). This software, and the product of NATIONS described herein + (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties + of the People's Republic of China and other applicable jurisdictions worldwide. + + NATIONS does not grant any license under its patents, copyrights, trademarks, or other + intellectual property rights. Names and brands of third party may be mentioned or referred + thereto (if any) for identification purposes only. + + NATIONS reserves the right to make changes, corrections, enhancements, modifications, and + improvements to this software at any time without notice. Please contact NATIONS and obtain + the latest version of this software before placing orders. + + Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes + no responsibility for the accuracy and reliability of this software. + + It is the responsibility of the user of this software to properly design, program, and test + the functionality and safety of any application made of this information and any resulting product. + In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or + consequential damages arising in any way out of the use of this software or the Product. + + NATIONS Products are neither intended nor warranted for usage in systems or equipment, any + malfunction or failure of which may cause loss of human life, bodily injury or severe property + damage. Such applications are deemed, "Insecure Usage". + + All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS + harmless from and against all claims, costs, damages, and other liabilities, arising from or related + to any customer's Insecure Usage. + + Any express or implied warranty with regard to this software or the Product, including,but not + limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement + are disclaimed to the fullest extent permitted by law. + + Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe + or otherwise distribute this software for any purposes, in whole or in part. + + NATIONS products and technologies shall not be used for or incorporated into any products or systems + whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. + User shall comply with any applicable export control laws and regulations promulgated and administered by + the governments of any countries asserting jurisdiction over the parties or transactions. + ************************************************************************************************************/ + + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/*some param defined in linker script*/ +.word _siram_code +.word _s_ram_code +.word _e_ram_code +.word _fp_flash_rodata +.word _fp_s_rodata +.word _fp_e_rodata +.word __exidx_start +.word __exidx_end +.word _fp_exidx +.word __preinit_array_start +.word __preinit_array_end +.word _sipreinit_array +.word __init_array_start +.word __init_array_end +.word _siinit_array +.word __fini_array_start +.word __fini_array_end +.word _sifini_array + +/* 宏定义：统一复制过程 */ +.macro COPY_SECTION section_start, section_end, load_address + ldr r0, =\section_start /* RAM目标地址 */ + ldr r2, =\load_address /* Flash源地址 */ + ldr r1, =\section_end /* RAM结束地址 */ + subs r3, r1, r0 /* 计算长度 */ + ble 1f /* 如果长度为0则跳过 */ +/* 复制循环（每次4字节） */ +0: ldr r4, [r2], #4 + str r4, [r0], #4 + subs r3, r3, #4 + bgt 0b +1: +.endm + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + + /* 复制所有需要初始化的段 */ + COPY_SECTION _s_ram_code, _e_ram_code, _siram_code /* 代码段 */ + COPY_SECTION _fp_s_rodata, _fp_e_rodata, _fp_flash_rodata /* 只读数据 */ + COPY_SECTION _sdata, _edata, _sidata /* 数据段 */ +/* COPY_SECTION __exidx_start, __exidx_end, _fp_exidx ARM异常索引 */ +/* COPY_SECTION __preinit_array_start, __preinit_array_end, _sipreinit_array + COPY_SECTION __init_array_start, __init_array_end, _siinit_array + COPY_SECTION __fini_array_start, __fini_array_end, _sifini_array + COPY_SECTION _sisr_vector_ram, _eisr_vector_ram, _sivector 中断向量表 */ +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** +\*fun This is the code that gets called when the processor receives an +\* unexpected interrupt. This simply enters an infinite loop, preserving +\* the system state for examination by a debugger. +**/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/** +\* The minimal vector table for a Cortex M0. Note that the proper constructs +\* must be placed on this to ensure that it ends up at physical address 0x00000000. +**/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word N32SysTick_Handler + /* External Interrupts */ + .word WWDG1_IRQHandler /* Window1 Watchdog interrupt */ + .word PVD_IRQHandler /* PVD through EXTI Line16 detection interrupt */ + .word RTC_TAMPER_IRQHandler /* RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup timer through EXTI line 19 interrupt */ + .word RCC_IRQHandler /* RCC interrupt */ + .word EXTI0_IRQHandler /* EXTI Line 0 interrupt */ + .word EXTI1_IRQHandler /* EXTI Line 1 interrupt */ + .word EXTI2_IRQHandler /* EXTI Line 2 interrupt */ + .word EXTI3_IRQHandler /* EXTI Line 3 interrupt */ + .word EXTI4_IRQHandler /* EXTI Line 4 interrupt */ + .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupt */ + .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupt */ + .word DMA1_Channel0_IRQHandler /* DMA1 Channel 0 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA2_Channel0_IRQHandler /* DMA2 Channel 0 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA3_Channel0_IRQHandler /* DMA3 Channel 0 */ + .word DMA3_Channel1_IRQHandler /* DMA3 Channel 1 */ + .word DMA3_Channel2_IRQHandler /* DMA3 Channel 2 */ + .word DMA3_Channel3_IRQHandler /* DMA3 Channel 3 */ + .word DMA3_Channel4_IRQHandler /* DMA3 Channel 4 */ + .word DMA3_Channel5_IRQHandler /* DMA3 Channel 5 */ + .word DMA3_Channel6_IRQHandler /* DMA3 Channel 6 */ + .word DMA3_Channel7_IRQHandler /* DMA3 Channel 7 */ + .word MDMA_Channel0_IRQHandler /* MDMA Channel 0 */ + .word MDMA_Channel1_IRQHandler /* MDMA Channel 1 */ + .word MDMA_Channel2_IRQHandler /* MDMA Channel 2 */ + .word MDMA_Channel3_IRQHandler /* MDMA Channel 3 */ + .word MDMA_Channel4_IRQHandler /* MDMA Channel 4 */ + .word MDMA_Channel5_IRQHandler /* MDMA Channel 5 */ + .word MDMA_Channel6_IRQHandler /* MDMA Channel 6 */ + .word MDMA_Channel7_IRQHandler /* MDMA Channel 7 */ + .word MDMA_Channel8_IRQHandler /* MDMA Channel 8 */ + .word MDMA_Channel9_IRQHandler /* MDMA Channel 9 */ + .word MDMA_Channel10_IRQHandler /* MDMA Channel 10 */ + .word MDMA_Channel11_IRQHandler /* MDMA Channel 11 */ + .word MDMA_Channel12_IRQHandler /* MDMA Channel 12 */ + .word MDMA_Channel13_IRQHandler /* MDMA Channel 13 */ + .word MDMA_Channel14_IRQHandler /* MDMA Channel 14 */ + .word MDMA_Channel15_IRQHandler /* MDMA Channel 15 */ + .word SDPU_IRQHandler /* SDPU global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_CPU1_IRQHandler /* FPU_CM7 global interrupt */ + .word ECCMON_IRQHandler /* ECCMON global interrupt */ + .word RTC_ALARM_IRQHandler /* RTC Alarm via EXTI17 interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ + .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 event interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 error interrupt */ + .word I2C6_EV_IRQHandler /* I2C6 event interrupt */ + .word I2C6_ER_IRQHandler /* I2C6 error interrupt */ + .word I2C7_EV_IRQHandler /* I2C7 event interrupt */ + .word I2C7_ER_IRQHandler /* I2C7 error interrupt */ + .word I2C8_EV_IRQHandler /* I2C8 event interrupt */ + .word I2C8_ER_IRQHandler /* I2C8 error interrupt */ + .word I2C9_EV_IRQHandler /* I2C9 event interrupt */ + .word I2C9_ER_IRQHandler /* I2C9 error interrupt */ + .word I2C10_EV_IRQHandler /* I2C10 event interrupt */ + .word I2C10_ER_IRQHandler /* I2C10 error interrupt */ + .word I2S1_IRQHandler /* I2S1 global interrupt */ + .word I2S2_IRQHandler /* I2S1 global interrupt */ + .word I2S3_IRQHandler /* I2S1 global interrupt */ + .word I2S4_IRQHandler /* I2S1 global interrupt */ + .word xSPI1_IRQHandler /* xSPI1 global interrupt */ + .word xSPI2_IRQHandler /* xSPI1 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word SPI3_IRQHandler /* SPI3 global interrupt */ + .word SPI4_IRQHandler /* SPI4 global interrupt */ + .word SPI5_IRQHandler /* SPI5 global interrupt */ + .word SPI6_IRQHandler /* SPI6 global interrupt */ + .word SPI7_IRQHandler /* SPI7 global interrupt */ + .word LCD_EV_IRQHandler /* TFT LCD Controller event interrupt */ + .word LCD_ER_IRQHandler /* TFT LCD Controller error interrupt */ + .word DVP1_IRQHandler /* DVP1 global interrupt */ + .word DVP2_IRQHandler /* DVP2 global interrupt */ + .word DMAMUX2_IRQHandler /* DMAMUX2 (MDMA MUX) global interrupt */ + .word USB1_HS_EPx_OUT_IRQHandler /* USB1_HS endpoint out global interrupt */ + .word USB1_HS_EPx_IN_IRQHandler /* USB1_HS endpoint in global interrupt */ + .word USB1_HS_WKUP_IRQHandler /* USB1_HS WKUP interrupt through EXTI line 62 */ + .word USB1_HS_IRQHandler /* USB1_HS global interrupt */ + .word USB2_HS_EPx_OUT_IRQHandler /* USB2_HS endpoint out global interrupt */ + .word USB2_HS_EPx_IN_IRQHandler /* USB2_HS endpoint in global interrupt */ + .word USB2_HS_WKUP_IRQHandler /* USB2_HS WKUP interrupt through EXTI line 63 */ + .word USB2_HS_IRQHandler /* USB2_HS global interrupt */ + .word ETH1_IRQHandler /* Ethernet 1 global interrupt */ + .word ETH1_PMT_LPI_IRQHandler /* Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 */ + .word ETH2_IRQHandler /* Ethernet 2 global interrupt */ + .word ETH2_PMT_LPI_IRQHandler /* Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 */ + .word FDCAN1_INT0_IRQHandler /* FDCAN1 global interrupt line 0 */ + .word FDCAN2_INT0_IRQHandler /* FDCAN2 global interrupt line 0 */ + .word FDCAN3_INT0_IRQHandler /* FDCAN3 global interrupt line 0 */ + .word FDCAN4_INT0_IRQHandler /* FDCAN4 global interrupt line 0 */ + .word FDCAN1_INT1_IRQHandler /* FDCAN1 global interrupt line 1 */ + .word FDCAN2_INT1_IRQHandler /* FDCAN2 global interrupt line 1 */ + .word FDCAN3_INT1_IRQHandler /* FDCAN3 global interrupt line 1 */ + .word FDCAN4_INT1_IRQHandler /* FDCAN4 global interrupt line 1 */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word USART3_IRQHandler /* USART3 global interrupt */ + .word USART4_IRQHandler /* USART4 global interrupt */ + .word USART5_IRQHandler /* USART5 global interrupt */ + .word USART6_IRQHandler /* USART6 global interrupt */ + .word USART7_IRQHandler /* USART7 global interrupt */ + .word USART8_IRQHandler /* USART8 global interrupt */ + .word UART9_IRQHandler /* UART9 global interrupt */ + .word UART10_IRQHandler /* UART10 global interrupt */ + .word UART11_IRQHandler /* UART11 global interrupt */ + .word UART12_IRQHandler /* UART12 global interrupt */ + .word UART13_IRQHandler /* UART13 global interrupt */ + .word UART14_IRQHandler /* UART14 global interrupt */ + .word UART15_IRQHandler /* UART15 global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt + wakeup through EXTI line 49 */ + .word LPUART2_IRQHandler /* LPUART2 global interrupt + wakeup through EXTI line 52 */ + .word GPU_IRQHandler /* GPU global interrupt */ + .word 0 /* Reserved */ + .word SDMMC1_IRQHandler /* SDMMC1_IRQ + WKUP through EXTI line 24 */ + .word SDMMC2_IRQHandler /* SDMMC2_IRQ + WKUP through EXTI line 25 */ + .word ADC1_IRQHandler /* ADC1 global interrupt */ + .word ADC2_IRQHandler /* ADC2 global interrupt */ + .word ADC3_IRQHandler /* ADC3 global interrupt */ + .word COMP1_2_IRQHandler /* COMP1 and COMP2 through EXTI line 20 and 21 */ + .word COMP3_4_IRQHandler /* COMP3 and COMP4 through EXTI line 22 and 23 */ + .word SHRTIM1_INT1_IRQHandler /* High Resolution timer 1 interrupt 1 */ + .word SHRTIM1_INT2_IRQHandler /* High Resolution timer 1 interrupt 2 */ + .word SHRTIM1_INT3_IRQHandler /* High Resolution timer 1 interrupt 3 */ + .word SHRTIM1_INT4_IRQHandler /* High Resolution timer 1 interrupt 4 */ + .word SHRTIM1_INT5_IRQHandler /* High Resolution timer 1 interrupt 5 */ + .word SHRTIM1_INT6_IRQHandler /* High Resolution timer 1 interrupt 6 */ + .word SHRTIM1_INT7_IRQHandler /* High Resolution timer 1 interrupt 7 */ + .word SHRTIM1_INT8_IRQHandler /* High Resolution timer 1 interrupt 8 */ + .word SHRTIM2_INT1_IRQHandler /* High Resolution timer 2 interrupt 1 */ + .word SHRTIM2_INT2_IRQHandler /* High Resolution timer 2 interrupt 2 */ + .word SHRTIM2_INT3_IRQHandler /* High Resolution timer 2 interrupt 3 */ + .word SHRTIM2_INT4_IRQHandler /* High Resolution timer 2 interrupt 4 */ + .word SHRTIM2_INT5_IRQHandler /* High Resolution timer 2 interrupt 5 */ + .word SHRTIM2_INT6_IRQHandler /* High Resolution timer 2 interrupt 6 */ + .word SHRTIM2_INT7_IRQHandler /* High Resolution timer 2 interrupt 7 */ + .word SHRTIM2_INT8_IRQHandler /* High Resolution timer 2 interrupt 8 */ + .word FDCAN5_INT0_IRQHandler /* FDCAN5 global interrupt line 0 */ + .word FDCAN6_INT0_IRQHandler /* FDCAN6 global interrupt line 0 */ + .word FDCAN7_INT0_IRQHandler /* FDCAN7 global interrupt line 0 */ + .word FDCAN8_INT0_IRQHandler /* FDCAN8 global interrupt line 0 */ + .word FDCAN5_INT1_IRQHandler /* FDCAN5 global interrupt line 1 */ + .word FDCAN6_INT1_IRQHandler /* FDCAN6 global interrupt line 1 */ + .word FDCAN7_INT1_IRQHandler /* FDCAN7 global interrupt line 1 */ + .word FDCAN8_INT1_IRQHandler /* FDCAN8 global interrupt line 1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word LPTIM5_WKUP_IRQHandler /* LPTIM5 wakeup through EXTI 86 */ + .word JPEG_SGDMA_H2P_IRQHandler /* JPEG SGDMA Host to Peripheral Interrupt */ + .word JPEG_SGDMA_P2H_IRQHandler /* JPEG SGDMA Peripheral to Host Interrupt */ + .word WAKEUP_IO_IRQHandler /* 6 WAKEUP IOs through EXTI line 70-75 */ + .word SEMA4_INT1_IRQHandler /* SEMA4 interrupt1 */ + .word 0 /* Reserved */ + .word WWDG2_RST_IRQHandler /* WWDG2 reset interrupt through EXTI line 82 */ + .word OTPC_IRQHandler /* OTPC interrupt */ + .word FEMC_IRQHandler /* FEMC interrupt */ + .word DCMUB_IRQHandler /* DCMUB interrupt */ + .word DAC1_IRQHandler /* DAC1 interrupt */ + .word DAC2_IRQHandler /* DAC2 interrupt */ + .word MDMA_AHBS_ER_IRQHandler /* MDMA HABS ERROR through EXTI line55-56 */ + .word CM7_CATCH_READ_ER_IRQHandler /* CM7 Error on Cache Read through EXTI line 64-65 */ + .word DAC3_IRQHandler /* DAC3 interrupt */ + .word DAC4_IRQHandler /* DAC4 interrupt */ + .word EMC_IRQHandler /* EMC event interrupt through EXTI line 88-89 */ + .word DAC5_IRQHandler /* DAC5 interrupt */ + .word DAC6_IRQHandler /* DAC6 interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ATIM1_BRK_IRQHandler /* Advanced timer 1 break interrupt */ + .word ATIM1_TRG_COM_IRQHandler /* Advanced timer 1 trigger and commutation interrupts */ + .word ATIM1_CC_IRQHandler /* Advanced timer 1 capture/compare interrupt */ + .word ATIM1_UP_IRQHandler /* Advanced timer 1 update interrupt */ + .word ATIM2_BRK_IRQHandler /* Advanced timer 2 break interrupt */ + .word ATIM2_TRG_COM_IRQHandler /* advanced timer 2 trigger and commutation interrupts */ + .word ATIM2_CC_IRQHandler /* Advanced timer 2 capture/compare interrupt */ + .word ATIM2_UP_IRQHandler /* Advanced timer 2 update interrupt */ + .word ATIM3_BRK_IRQHandler /* Advanced timer 3 break interrupt */ + .word ATIM3_TRG_COM_IRQHandler /* Advanced timer 3 trigger and commutation interrupts */ + .word ATIM3_CC_IRQHandler /* Advanced timer 3 capture/compare interrupt */ + .word ATIM3_UP_IRQHandler /* Advanced timer 3 update interrupt */ + .word ATIM4_BRK_IRQHandler /* Advanced timer 4 break interrupt */ + .word ATIM4_TRG_COM_IRQHandler /* Advanced timer 4 trigger and commutation interrupts */ + .word ATIM4_CC_IRQHandler /* Advanced timer 4 capture/compare interrupt */ + .word ATIM4_UP_IRQHandler /* Advanced timer 4 update interrupt */ + .word GTIMA1_IRQHandler /* General timer A1 global interrupt */ + .word GTIMA2_IRQHandler /* General timer A2 global interrupt */ + .word GTIMA3_IRQHandler /* General timer A3 global interrupt */ + .word GTIMA4_IRQHandler /* General timer A4 global interrupt */ + .word GTIMA5_IRQHandler /* General timer A5 global interrupt */ + .word GTIMA6_IRQHandler /* General timer A6 global interrupt */ + .word GTIMA7_IRQHandler /* General timer A7 global interrupt */ + .word GTIMB1_IRQHandler /* General timer B1 global interrupt */ + .word GTIMB2_IRQHandler /* General timer B2 global interrupt */ + .word GTIMB3_IRQHandler /* General timer B3 global interrupt */ + .word BTIM1_IRQHandler /* Base timer 1 global interrupt */ + .word BTIM2_IRQHandler /* Base timer 2 global interrupt */ + .word BTIM3_IRQHandler /* Base timer 3 global interrupt */ + .word BTIM4_IRQHandler /* Base timer 4 global interrupt */ + .word LPTIM1_WKUP_IRQHandler /* LPTIM1 wakeup interrupt */ + .word LPTIM2_WKUP_IRQHandler /* LPTIM2 wakeup interrupt */ + .word LPTIM3_WKUP_IRQHandler /* LPTIM3 wakeup interrupt */ + .word LPTIM4_WKUP_IRQHandler /* LPTIM4 wakeup interrupt */ + .word DSMU_FLT0_IRQHandler /* DSMU Filter interrupt 0 */ + .word DSMU_FLT1_IRQHandler /* DSMU Filter interrupt 1 */ + .word DSMU_FLT2_IRQHandler /* DSMU Filter interrupt 2 */ + .word DSMU_FLT3_IRQHandler /* DSMU Filter interrupt 3 */ + .word FMAC_IRQHandler /* FMAC global interrupt */ + .word CORDIC_IRQHandler /* Cordic global interrupt */ + .word DMAMUX1_IRQHandler /* DMAMUX1 interrupt */ + .word MMU_IRQHandler /* MMU interrupt */ + .word SysTick_Handler + /* need check to user manual of exti chapter */ + +/** +\* Provide weak aliases for each Exception handler to the Default_Handler. +\* As they are weak aliases, any function with the same name will override +\* this definition. +**/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak N32SysTick_Handler + .thumb_set N32SysTick_Handler,Default_Handler + + .weak WWDG1_IRQHandler + .thumb_set WWDG1_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMPER_IRQHandler + .thumb_set RTC_TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak DMA1_Channel0_IRQHandler + .thumb_set DMA1_Channel0_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel0_IRQHandler + .thumb_set DMA2_Channel0_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA3_Channel0_IRQHandler + .thumb_set DMA3_Channel0_IRQHandler,Default_Handler + + .weak DMA3_Channel1_IRQHandler + .thumb_set DMA3_Channel1_IRQHandler,Default_Handler + + .weak DMA3_Channel2_IRQHandler + .thumb_set DMA3_Channel2_IRQHandler,Default_Handler + + .weak DMA3_Channel3_IRQHandler + .thumb_set DMA3_Channel3_IRQHandler,Default_Handler + + .weak DMA3_Channel4_IRQHandler + .thumb_set DMA3_Channel4_IRQHandler,Default_Handler + + .weak DMA3_Channel5_IRQHandler + .thumb_set DMA3_Channel5_IRQHandler,Default_Handler + + .weak DMA3_Channel6_IRQHandler + .thumb_set DMA3_Channel6_IRQHandler,Default_Handler + + .weak DMA3_Channel7_IRQHandler + .thumb_set DMA3_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel0_IRQHandler + .thumb_set MDMA_Channel0_IRQHandler,Default_Handler + + .weak MDMA_Channel1_IRQHandler + .thumb_set MDMA_Channel1_IRQHandler,Default_Handler + + .weak MDMA_Channel2_IRQHandler + .thumb_set MDMA_Channel2_IRQHandler,Default_Handler + + .weak MDMA_Channel3_IRQHandler + .thumb_set MDMA_Channel3_IRQHandler,Default_Handler + + .weak MDMA_Channel4_IRQHandler + .thumb_set MDMA_Channel4_IRQHandler,Default_Handler + + .weak MDMA_Channel5_IRQHandler + .thumb_set MDMA_Channel5_IRQHandler,Default_Handler + + .weak MDMA_Channel6_IRQHandler + .thumb_set MDMA_Channel6_IRQHandler,Default_Handler + + .weak MDMA_Channel7_IRQHandler + .thumb_set MDMA_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel8_IRQHandler + .thumb_set MDMA_Channel8_IRQHandler,Default_Handler + + .weak MDMA_Channel9_IRQHandler + .thumb_set MDMA_Channel9_IRQHandler,Default_Handler + + .weak MDMA_Channel10_IRQHandler + .thumb_set MDMA_Channel10_IRQHandler,Default_Handler + + .weak MDMA_Channel11_IRQHandler + .thumb_set MDMA_Channel11_IRQHandler,Default_Handler + + .weak MDMA_Channel12_IRQHandler + .thumb_set MDMA_Channel12_IRQHandler,Default_Handler + + .weak MDMA_Channel13_IRQHandler + .thumb_set MDMA_Channel13_IRQHandler,Default_Handler + + .weak MDMA_Channel14_IRQHandler + .thumb_set MDMA_Channel14_IRQHandler,Default_Handler + + .weak MDMA_Channel15_IRQHandler + .thumb_set MDMA_Channel15_IRQHandler,Default_Handler + + .weak SDPU_IRQHandler + .thumb_set SDPU_IRQHandler,Default_Handler + + .weak FPU_CPU1_IRQHandler + .thumb_set FPU_CPU1_IRQHandler,Default_Handler + + .weak ECCMON_IRQHandler + .thumb_set ECCMON_IRQHandler,Default_Handler + + .weak RTC_ALARM_IRQHandler + .thumb_set RTC_ALARM_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak I2C6_EV_IRQHandler + .thumb_set I2C6_EV_IRQHandler,Default_Handler + + .weak I2C6_ER_IRQHandler + .thumb_set I2C6_ER_IRQHandler,Default_Handler + + .weak I2C7_EV_IRQHandler + .thumb_set I2C7_EV_IRQHandler,Default_Handler + + .weak I2C7_ER_IRQHandler + .thumb_set I2C7_ER_IRQHandler,Default_Handler + + .weak I2C8_EV_IRQHandler + .thumb_set I2C8_EV_IRQHandler,Default_Handler + + .weak I2C8_ER_IRQHandler + .thumb_set I2C8_ER_IRQHandler,Default_Handler + + .weak I2C9_EV_IRQHandler + .thumb_set I2C9_EV_IRQHandler,Default_Handler + + .weak I2C9_ER_IRQHandler + .thumb_set I2C9_ER_IRQHandler,Default_Handler + + .weak I2C10_EV_IRQHandler + .thumb_set I2C10_EV_IRQHandler,Default_Handler + + .weak I2C10_ER_IRQHandler + .thumb_set I2C10_ER_IRQHandler,Default_Handler + + .weak I2S1_IRQHandler + .thumb_set I2S1_IRQHandler,Default_Handler + + .weak I2S2_IRQHandler + .thumb_set I2S2_IRQHandler,Default_Handler + + .weak I2S3_IRQHandler + .thumb_set I2S3_IRQHandler,Default_Handler + + .weak I2S4_IRQHandler + .thumb_set I2S4_IRQHandler,Default_Handler + + .weak xSPI1_IRQHandler + .thumb_set xSPI1_IRQHandler,Default_Handler + + .weak xSPI2_IRQHandler + .thumb_set xSPI2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SPI7_IRQHandler + .thumb_set SPI7_IRQHandler,Default_Handler + + .weak LCD_EV_IRQHandler + .thumb_set LCD_EV_IRQHandler,Default_Handler + + .weak LCD_ER_IRQHandler + .thumb_set LCD_ER_IRQHandler,Default_Handler + + .weak DVP1_IRQHandler + .thumb_set DVP1_IRQHandler,Default_Handler + + .weak DVP2_IRQHandler + .thumb_set DVP2_IRQHandler,Default_Handler + + .weak DMAMUX2_IRQHandler + .thumb_set DMAMUX2_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_OUT_IRQHandler + .thumb_set USB1_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_IN_IRQHandler + .thumb_set USB1_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB1_HS_WKUP_IRQHandler + .thumb_set USB1_HS_WKUP_IRQHandler,Default_Handler + + .weak USB1_HS_IRQHandler + .thumb_set USB1_HS_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_OUT_IRQHandler + .thumb_set USB2_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_IN_IRQHandler + .thumb_set USB2_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB2_HS_WKUP_IRQHandler + .thumb_set USB2_HS_WKUP_IRQHandler,Default_Handler + + .weak USB2_HS_IRQHandler + .thumb_set USB2_HS_IRQHandler,Default_Handler + + .weak ETH1_IRQHandler + .thumb_set ETH1_IRQHandler,Default_Handler + + .weak ETH1_PMT_LPI_IRQHandler + .thumb_set ETH1_PMT_LPI_IRQHandler,Default_Handler + + .weak ETH2_IRQHandler + .thumb_set ETH2_IRQHandler,Default_Handler + + .weak ETH2_PMT_LPI_IRQHandler + .thumb_set ETH2_PMT_LPI_IRQHandler,Default_Handler + + .weak FDCAN1_INT0_IRQHandler + .thumb_set FDCAN1_INT0_IRQHandler,Default_Handler + + .weak FDCAN2_INT0_IRQHandler + .thumb_set FDCAN2_INT0_IRQHandler,Default_Handler + + .weak FDCAN3_INT0_IRQHandler + .thumb_set FDCAN3_INT0_IRQHandler,Default_Handler + + .weak FDCAN4_INT0_IRQHandler + .thumb_set FDCAN4_INT0_IRQHandler,Default_Handler + + .weak FDCAN1_INT1_IRQHandler + .thumb_set FDCAN1_INT1_IRQHandler,Default_Handler + + .weak FDCAN2_INT1_IRQHandler + .thumb_set FDCAN2_INT1_IRQHandler,Default_Handler + + .weak FDCAN3_INT1_IRQHandler + .thumb_set FDCAN3_INT1_IRQHandler,Default_Handler + + .weak FDCAN4_INT1_IRQHandler + .thumb_set FDCAN4_INT1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak UART10_IRQHandler + .thumb_set UART10_IRQHandler,Default_Handler + + .weak UART11_IRQHandler + .thumb_set UART11_IRQHandler,Default_Handler + + .weak UART12_IRQHandler + .thumb_set UART12_IRQHandler,Default_Handler + + .weak UART13_IRQHandler + .thumb_set UART13_IRQHandler,Default_Handler + + .weak UART14_IRQHandler + .thumb_set UART14_IRQHandler,Default_Handler + + .weak UART15_IRQHandler + .thumb_set UART15_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPUART2_IRQHandler + .thumb_set LPUART2_IRQHandler,Default_Handler + + .weak GPU_IRQHandler + .thumb_set GPU_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler,Default_Handler + + .weak COMP3_4_IRQHandler + .thumb_set COMP3_4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT1_IRQHandler + .thumb_set SHRTIM1_INT1_IRQHandler,Default_Handler + + .weak SHRTIM1_INT2_IRQHandler + .thumb_set SHRTIM1_INT2_IRQHandler,Default_Handler + + .weak SHRTIM1_INT3_IRQHandler + .thumb_set SHRTIM1_INT3_IRQHandler,Default_Handler + + .weak SHRTIM1_INT4_IRQHandler + .thumb_set SHRTIM1_INT4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT5_IRQHandler + .thumb_set SHRTIM1_INT5_IRQHandler,Default_Handler + + .weak SHRTIM1_INT6_IRQHandler + .thumb_set SHRTIM1_INT6_IRQHandler,Default_Handler + + .weak SHRTIM1_INT7_IRQHandler + .thumb_set SHRTIM1_INT7_IRQHandler,Default_Handler + + .weak SHRTIM1_INT8_IRQHandler + .thumb_set SHRTIM1_INT8_IRQHandler,Default_Handler + + .weak SHRTIM2_INT1_IRQHandler + .thumb_set SHRTIM2_INT1_IRQHandler,Default_Handler + + .weak SHRTIM2_INT2_IRQHandler + .thumb_set SHRTIM2_INT2_IRQHandler,Default_Handler + + .weak SHRTIM2_INT3_IRQHandler + .thumb_set SHRTIM2_INT3_IRQHandler,Default_Handler + + .weak SHRTIM2_INT4_IRQHandler + .thumb_set SHRTIM2_INT4_IRQHandler,Default_Handler + + .weak SHRTIM2_INT5_IRQHandler + .thumb_set SHRTIM2_INT5_IRQHandler,Default_Handler + + .weak SHRTIM2_INT6_IRQHandler + .thumb_set SHRTIM2_INT6_IRQHandler,Default_Handler + + .weak SHRTIM2_INT7_IRQHandler + .thumb_set SHRTIM2_INT7_IRQHandler,Default_Handler + + .weak SHRTIM2_INT8_IRQHandler + .thumb_set SHRTIM2_INT8_IRQHandler,Default_Handler + + .weak FDCAN5_INT0_IRQHandler + .thumb_set FDCAN5_INT0_IRQHandler,Default_Handler + + .weak FDCAN6_INT0_IRQHandler + .thumb_set FDCAN6_INT0_IRQHandler,Default_Handler + + .weak FDCAN7_INT0_IRQHandler + .thumb_set FDCAN7_INT0_IRQHandler,Default_Handler + + .weak FDCAN8_INT0_IRQHandler + .thumb_set FDCAN8_INT0_IRQHandler,Default_Handler + + .weak FDCAN5_INT1_IRQHandler + .thumb_set FDCAN5_INT1_IRQHandler,Default_Handler + + .weak FDCAN6_INT1_IRQHandler + .thumb_set FDCAN6_INT1_IRQHandler,Default_Handler + + .weak FDCAN7_INT1_IRQHandler + .thumb_set FDCAN7_INT1_IRQHandler,Default_Handler + + .weak FDCAN8_INT1_IRQHandler + .thumb_set FDCAN8_INT1_IRQHandler,Default_Handler + + .weak LPTIM5_WKUP_IRQHandler + .thumb_set LPTIM5_WKUP_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_H2P_IRQHandler + .thumb_set JPEG_SGDMA_H2P_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_P2H_IRQHandler + .thumb_set JPEG_SGDMA_P2H_IRQHandler,Default_Handler + + .weak WAKEUP_IO_IRQHandler + .thumb_set WAKEUP_IO_IRQHandler,Default_Handler + + .weak SEMA4_INT1_IRQHandler + .thumb_set SEMA4_INT1_IRQHandler,Default_Handler + + .weak WWDG2_RST_IRQHandler + .thumb_set WWDG2_RST_IRQHandler,Default_Handler + + .weak OTPC_IRQHandler + .thumb_set OTPC_IRQHandler,Default_Handler + + .weak FEMC_IRQHandler + .thumb_set FEMC_IRQHandler,Default_Handler + + .weak DCMUB_IRQHandler + .thumb_set DCMUB_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak DAC2_IRQHandler + .thumb_set DAC2_IRQHandler,Default_Handler + + .weak MDMA_AHBS_ER_IRQHandler + .thumb_set MDMA_AHBS_ER_IRQHandler,Default_Handler + + .weak CM7_CATCH_READ_ER_IRQHandler + .thumb_set CM7_CATCH_READ_ER_IRQHandler,Default_Handler + + .weak DAC3_IRQHandler + .thumb_set DAC3_IRQHandler,Default_Handler + + .weak DAC4_IRQHandler + .thumb_set DAC4_IRQHandler,Default_Handler + + .weak EMC_IRQHandler + .thumb_set EMC_IRQHandler,Default_Handler + + .weak DAC5_IRQHandler + .thumb_set DAC5_IRQHandler,Default_Handler + + .weak DAC6_IRQHandler + .thumb_set DAC6_IRQHandler,Default_Handler + + .weak ATIM1_BRK_IRQHandler + .thumb_set ATIM1_BRK_IRQHandler,Default_Handler + + .weak ATIM1_TRG_COM_IRQHandler + .thumb_set ATIM1_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM1_CC_IRQHandler + .thumb_set ATIM1_CC_IRQHandler,Default_Handler + + .weak ATIM1_UP_IRQHandler + .thumb_set ATIM1_UP_IRQHandler,Default_Handler + + .weak ATIM2_BRK_IRQHandler + .thumb_set ATIM2_BRK_IRQHandler,Default_Handler + + .weak ATIM2_TRG_COM_IRQHandler + .thumb_set ATIM2_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM2_CC_IRQHandler + .thumb_set ATIM2_CC_IRQHandler,Default_Handler + + .weak ATIM2_UP_IRQHandler + .thumb_set ATIM2_UP_IRQHandler,Default_Handler + + .weak ATIM3_BRK_IRQHandler + .thumb_set ATIM3_BRK_IRQHandler,Default_Handler + + .weak ATIM3_TRG_COM_IRQHandler + .thumb_set ATIM3_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM3_CC_IRQHandler + .thumb_set ATIM3_CC_IRQHandler,Default_Handler + + .weak ATIM3_UP_IRQHandler + .thumb_set ATIM3_UP_IRQHandler,Default_Handler + + .weak ATIM4_BRK_IRQHandler + .thumb_set ATIM4_BRK_IRQHandler,Default_Handler + + .weak ATIM4_TRG_COM_IRQHandler + .thumb_set ATIM4_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM4_CC_IRQHandler + .thumb_set ATIM4_CC_IRQHandler,Default_Handler + + .weak ATIM4_UP_IRQHandler + .thumb_set ATIM4_UP_IRQHandler,Default_Handler + + .weak GTIMA1_IRQHandler + .thumb_set GTIMA1_IRQHandler,Default_Handler + + .weak GTIMA2_IRQHandler + .thumb_set GTIMA2_IRQHandler,Default_Handler + + .weak GTIMA3_IRQHandler + .thumb_set GTIMA3_IRQHandler,Default_Handler + + .weak GTIMA4_IRQHandler + .thumb_set GTIMA4_IRQHandler,Default_Handler + + .weak GTIMA5_IRQHandler + .thumb_set GTIMA5_IRQHandler,Default_Handler + + .weak GTIMA6_IRQHandler + .thumb_set GTIMA6_IRQHandler,Default_Handler + + .weak GTIMA7_IRQHandler + .thumb_set GTIMA7_IRQHandler,Default_Handler + + .weak GTIMB1_IRQHandler + .thumb_set GTIMB1_IRQHandler,Default_Handler + + .weak GTIMB2_IRQHandler + .thumb_set GTIMB2_IRQHandler,Default_Handler + + .weak GTIMB3_IRQHandler + .thumb_set GTIMB3_IRQHandler,Default_Handler + + .weak BTIM1_IRQHandler + .thumb_set BTIM1_IRQHandler,Default_Handler + + .weak BTIM2_IRQHandler + .thumb_set BTIM2_IRQHandler,Default_Handler + + .weak BTIM3_IRQHandler + .thumb_set BTIM3_IRQHandler,Default_Handler + + .weak BTIM4_IRQHandler + .thumb_set BTIM4_IRQHandler,Default_Handler + + .weak LPTIM1_WKUP_IRQHandler + .thumb_set LPTIM1_WKUP_IRQHandler,Default_Handler + + .weak LPTIM2_WKUP_IRQHandler + .thumb_set LPTIM2_WKUP_IRQHandler,Default_Handler + + .weak LPTIM3_WKUP_IRQHandler + .thumb_set LPTIM3_WKUP_IRQHandler,Default_Handler + + .weak LPTIM4_WKUP_IRQHandler + .thumb_set LPTIM4_WKUP_IRQHandler,Default_Handler + + .weak DSMU_FLT0_IRQHandler + .thumb_set DSMU_FLT0_IRQHandler,Default_Handler + + .weak DSMU_FLT1_IRQHandler + .thumb_set DSMU_FLT1_IRQHandler,Default_Handler + + .weak DSMU_FLT2_IRQHandler + .thumb_set DSMU_FLT2_IRQHandler,Default_Handler + + .weak DSMU_FLT3_IRQHandler + .thumb_set DSMU_FLT3_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak DMAMUX1_IRQHandler + .thumb_set DMAMUX1_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4.s new file mode 100644 index 0000000000..d651a057ca --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4.s @@ -0,0 +1,897 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG2_IRQHandler ; Window2 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD AHB_ICACHE_IRQHandler ; CM4 AHB iCache interrupt + DCD AHB_DCACHE_IRQHandler ; CM4 AHB dCache interrupt + DCD FPU_CPU2_IRQHandler ; FPU_CM4 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD AHB_CACHE_PARMON_IRQHandler ; AHB i/dCACHE parity error intertupt + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD 0 ; + DCD SEMA4_INT2_IRQHandler ; SEMA4 interrupt2 + DCD WWDG1_RST_IRQHandler ; WWDG1 reset interrupt through EXTI line 81 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUA_IRQHandler ; DCMUA interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_IRQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG2_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel0_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA3_Channel0_IRQHandler [WEAK] + EXPORT DMA3_Channel1_IRQHandler [WEAK] + EXPORT DMA3_Channel2_IRQHandler [WEAK] + EXPORT DMA3_Channel3_IRQHandler [WEAK] + EXPORT DMA3_Channel4_IRQHandler [WEAK] + EXPORT DMA3_Channel5_IRQHandler [WEAK] + EXPORT DMA3_Channel6_IRQHandler [WEAK] + EXPORT DMA3_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel0_IRQHandler [WEAK] + EXPORT MDMA_Channel1_IRQHandler [WEAK] + EXPORT MDMA_Channel2_IRQHandler [WEAK] + EXPORT MDMA_Channel3_IRQHandler [WEAK] + EXPORT MDMA_Channel4_IRQHandler [WEAK] + EXPORT MDMA_Channel5_IRQHandler [WEAK] + EXPORT MDMA_Channel6_IRQHandler [WEAK] + EXPORT MDMA_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel8_IRQHandler [WEAK] + EXPORT MDMA_Channel9_IRQHandler [WEAK] + EXPORT MDMA_Channel10_IRQHandler [WEAK] + EXPORT MDMA_Channel11_IRQHandler [WEAK] + EXPORT MDMA_Channel12_IRQHandler [WEAK] + EXPORT MDMA_Channel13_IRQHandler [WEAK] + EXPORT MDMA_Channel14_IRQHandler [WEAK] + EXPORT MDMA_Channel15_IRQHandler [WEAK] + EXPORT SDPU_IRQHandler [WEAK] + EXPORT AHB_ICACHE_IRQHandler [WEAK] + EXPORT AHB_DCACHE_IRQHandler [WEAK] + EXPORT FPU_CPU2_IRQHandler [WEAK] + EXPORT ECCMON_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT I2C6_EV_IRQHandler [WEAK] + EXPORT I2C6_ER_IRQHandler [WEAK] + EXPORT I2C7_EV_IRQHandler [WEAK] + EXPORT I2C7_ER_IRQHandler [WEAK] + EXPORT I2C8_EV_IRQHandler [WEAK] + EXPORT I2C8_ER_IRQHandler [WEAK] + EXPORT I2C9_EV_IRQHandler [WEAK] + EXPORT I2C9_ER_IRQHandler [WEAK] + EXPORT I2C10_EV_IRQHandler [WEAK] + EXPORT I2C10_ER_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT I2S4_IRQHandler [WEAK] + EXPORT xSPI1_IRQHandler [WEAK] + EXPORT xSPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT LCD_EV_IRQHandler [WEAK] + EXPORT LCD_ER_IRQHandler [WEAK] + EXPORT DVP1_IRQHandler [WEAK] + EXPORT DVP2_IRQHandler [WEAK] + EXPORT DMAMUX2_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB1_HS_WKUP_IRQHandler [WEAK] + EXPORT USB1_HS_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB2_HS_WKUP_IRQHandler [WEAK] + EXPORT USB2_HS_IRQHandler [WEAK] + EXPORT ETH1_IRQHandler [WEAK] + EXPORT ETH1_PMT_LPI_IRQHandler [WEAK] + EXPORT ETH2_IRQHandler [WEAK] + EXPORT ETH2_PMT_LPI_IRQHandler [WEAK] + EXPORT FDCAN1_INT0_IRQHandler [WEAK] + EXPORT FDCAN2_INT0_IRQHandler [WEAK] + EXPORT FDCAN3_INT0_IRQHandler [WEAK] + EXPORT FDCAN4_INT0_IRQHandler [WEAK] + EXPORT FDCAN1_INT1_IRQHandler [WEAK] + EXPORT FDCAN2_INT1_IRQHandler [WEAK] + EXPORT FDCAN3_INT1_IRQHandler [WEAK] + EXPORT FDCAN4_INT1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPUART2_IRQHandler [WEAK] + EXPORT GPU_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT COMP1_2_IRQHandler [WEAK] + EXPORT COMP3_4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT1_IRQHandler [WEAK] + EXPORT SHRTIM1_INT2_IRQHandler [WEAK] + EXPORT SHRTIM1_INT3_IRQHandler [WEAK] + EXPORT SHRTIM1_INT4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT5_IRQHandler [WEAK] + EXPORT SHRTIM1_INT6_IRQHandler [WEAK] + EXPORT SHRTIM1_INT7_IRQHandler [WEAK] + EXPORT SHRTIM1_INT8_IRQHandler [WEAK] + EXPORT SHRTIM2_INT1_IRQHandler [WEAK] + EXPORT SHRTIM2_INT2_IRQHandler [WEAK] + EXPORT SHRTIM2_INT3_IRQHandler [WEAK] + EXPORT SHRTIM2_INT4_IRQHandler [WEAK] + EXPORT SHRTIM2_INT5_IRQHandler [WEAK] + EXPORT SHRTIM2_INT6_IRQHandler [WEAK] + EXPORT SHRTIM2_INT7_IRQHandler [WEAK] + EXPORT SHRTIM2_INT8_IRQHandler [WEAK] + EXPORT FDCAN5_INT0_IRQHandler [WEAK] + EXPORT FDCAN6_INT0_IRQHandler [WEAK] + EXPORT FDCAN7_INT0_IRQHandler [WEAK] + EXPORT FDCAN8_INT0_IRQHandler [WEAK] + EXPORT FDCAN5_INT1_IRQHandler [WEAK] + EXPORT FDCAN6_INT1_IRQHandler [WEAK] + EXPORT FDCAN7_INT1_IRQHandler [WEAK] + EXPORT FDCAN8_INT1_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT AHB_CACHE_PARMON_IRQHandler [WEAK] + EXPORT LPTIM5_WKUP_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_H2P_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_P2H_IRQHandler [WEAK] + EXPORT WAKEUP_IO_IRQHandler [WEAK] + EXPORT SEMA4_INT2_IRQHandler [WEAK] + EXPORT WWDG1_RST_IRQHandler [WEAK] + EXPORT OTPC_IRQHandler [WEAK] + EXPORT FEMC_IRQHandler [WEAK] + EXPORT DCMUA_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT MDMA_AHBS_ER_IRQHandler [WEAK] + EXPORT CM7_CATCH_READ_ER_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT DAC4_IRQHandler [WEAK] + EXPORT EMC_IRQHandler [WEAK] + EXPORT DAC5_IRQHandler [WEAK] + EXPORT DAC6_IRQHandler [WEAK] + EXPORT ESC_OPB_IRQHandler [WEAK] + EXPORT ESC_SYNC0_IRQHandler [WEAK] + EXPORT ESC_SYNC1_IRQHandler [WEAK] + EXPORT ESC_WRP_IRQHandler [WEAK] + EXPORT ATIM1_BRK_IRQHandler [WEAK] + EXPORT ATIM1_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM1_CC_IRQHandler [WEAK] + EXPORT ATIM1_UP_IRQHandler [WEAK] + EXPORT ATIM2_BRK_IRQHandler [WEAK] + EXPORT ATIM2_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM2_CC_IRQHandler [WEAK] + EXPORT ATIM2_UP_IRQHandler [WEAK] + EXPORT ATIM3_BRK_IRQHandler [WEAK] + EXPORT ATIM3_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM3_CC_IRQHandler [WEAK] + EXPORT ATIM3_UP_IRQHandler [WEAK] + EXPORT ATIM4_BRK_IRQHandler [WEAK] + EXPORT ATIM4_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM4_CC_IRQHandler [WEAK] + EXPORT ATIM4_UP_IRQHandler [WEAK] + EXPORT GTIMA1_IRQHandler [WEAK] + EXPORT GTIMA2_IRQHandler [WEAK] + EXPORT GTIMA3_IRQHandler [WEAK] + EXPORT GTIMA4_IRQHandler [WEAK] + EXPORT GTIMA5_IRQHandler [WEAK] + EXPORT GTIMA6_IRQHandler [WEAK] + EXPORT GTIMA7_IRQHandler [WEAK] + EXPORT GTIMB1_IRQHandler [WEAK] + EXPORT GTIMB2_IRQHandler [WEAK] + EXPORT GTIMB3_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT BTIM4_IRQHandler [WEAK] + EXPORT LPTIM1_WKUP_IRQHandler [WEAK] + EXPORT LPTIM2_WKUP_IRQHandler [WEAK] + EXPORT LPTIM3_WKUP_IRQHandler [WEAK] + EXPORT LPTIM4_WKUP_IRQHandler [WEAK] + EXPORT DSMU_FLT0_IRQHandler [WEAK] + EXPORT DSMU_FLT1_IRQHandler [WEAK] + EXPORT DSMU_FLT2_IRQHandler [WEAK] + EXPORT DSMU_FLT3_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT DMAMUX1_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + + +WWDG2_IRQHandler +PVD_IRQHandler +RTC_TAMPER_IRQHandler +RTC_WKUP_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI9_5_IRQHandler +EXTI15_10_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +DMA2_Channel0_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA3_Channel0_IRQHandler +DMA3_Channel1_IRQHandler +DMA3_Channel2_IRQHandler +DMA3_Channel3_IRQHandler +DMA3_Channel4_IRQHandler +DMA3_Channel5_IRQHandler +DMA3_Channel6_IRQHandler +DMA3_Channel7_IRQHandler +MDMA_Channel0_IRQHandler +MDMA_Channel1_IRQHandler +MDMA_Channel2_IRQHandler +MDMA_Channel3_IRQHandler +MDMA_Channel4_IRQHandler +MDMA_Channel5_IRQHandler +MDMA_Channel6_IRQHandler +MDMA_Channel7_IRQHandler +MDMA_Channel8_IRQHandler +MDMA_Channel9_IRQHandler +MDMA_Channel10_IRQHandler +MDMA_Channel11_IRQHandler +MDMA_Channel12_IRQHandler +MDMA_Channel13_IRQHandler +MDMA_Channel14_IRQHandler +MDMA_Channel15_IRQHandler +SDPU_IRQHandler +AHB_ICACHE_IRQHandler +AHB_DCACHE_IRQHandler +FPU_CPU2_IRQHandler +ECCMON_IRQHandler +RTC_ALARM_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +I2C6_EV_IRQHandler +I2C6_ER_IRQHandler +I2C7_EV_IRQHandler +I2C7_ER_IRQHandler +I2C8_EV_IRQHandler +I2C8_ER_IRQHandler +I2C9_EV_IRQHandler +I2C9_ER_IRQHandler +I2C10_EV_IRQHandler +I2C10_ER_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +I2S3_IRQHandler +I2S4_IRQHandler +xSPI1_IRQHandler +xSPI2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SPI7_IRQHandler +LCD_EV_IRQHandler +LCD_ER_IRQHandler +DVP1_IRQHandler +DVP2_IRQHandler +DMAMUX2_IRQHandler +USB1_HS_EPx_OUT_IRQHandler +USB1_HS_EPx_IN_IRQHandler +USB1_HS_WKUP_IRQHandler +USB1_HS_IRQHandler +USB2_HS_EPx_OUT_IRQHandler +USB2_HS_EPx_IN_IRQHandler +USB2_HS_WKUP_IRQHandler +USB2_HS_IRQHandler +ETH1_IRQHandler +ETH1_PMT_LPI_IRQHandler +ETH2_IRQHandler +ETH2_PMT_LPI_IRQHandler +FDCAN1_INT0_IRQHandler +FDCAN2_INT0_IRQHandler +FDCAN3_INT0_IRQHandler +FDCAN4_INT0_IRQHandler +FDCAN1_INT1_IRQHandler +FDCAN2_INT1_IRQHandler +FDCAN3_INT1_IRQHandler +FDCAN4_INT1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +LPUART1_IRQHandler +LPUART2_IRQHandler +GPU_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +ADC3_IRQHandler +COMP1_2_IRQHandler +COMP3_4_IRQHandler +SHRTIM1_INT1_IRQHandler +SHRTIM1_INT2_IRQHandler +SHRTIM1_INT3_IRQHandler +SHRTIM1_INT4_IRQHandler +SHRTIM1_INT5_IRQHandler +SHRTIM1_INT6_IRQHandler +SHRTIM1_INT7_IRQHandler +SHRTIM1_INT8_IRQHandler +SHRTIM2_INT1_IRQHandler +SHRTIM2_INT2_IRQHandler +SHRTIM2_INT3_IRQHandler +SHRTIM2_INT4_IRQHandler +SHRTIM2_INT5_IRQHandler +SHRTIM2_INT6_IRQHandler +SHRTIM2_INT7_IRQHandler +SHRTIM2_INT8_IRQHandler +FDCAN5_INT0_IRQHandler +FDCAN6_INT0_IRQHandler +FDCAN7_INT0_IRQHandler +FDCAN8_INT0_IRQHandler +FDCAN5_INT1_IRQHandler +FDCAN6_INT1_IRQHandler +FDCAN7_INT1_IRQHandler +FDCAN8_INT1_IRQHandler +DSI_IRQHandler +AHB_CACHE_PARMON_IRQHandler +LPTIM5_WKUP_IRQHandler +JPEG_SGDMA_H2P_IRQHandler +JPEG_SGDMA_P2H_IRQHandler +WAKEUP_IO_IRQHandler +SEMA4_INT2_IRQHandler +WWDG1_RST_IRQHandler +OTPC_IRQHandler +FEMC_IRQHandler +DCMUA_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +MDMA_AHBS_ER_IRQHandler +CM7_CATCH_READ_ER_IRQHandler +DAC3_IRQHandler +DAC4_IRQHandler +EMC_IRQHandler +DAC5_IRQHandler +DAC6_IRQHandler +ESC_OPB_IRQHandler +ESC_SYNC0_IRQHandler +ESC_SYNC1_IRQHandler +ESC_WRP_IRQHandler +ATIM1_BRK_IRQHandler +ATIM1_TRG_COM_IRQHandler +ATIM1_CC_IRQHandler +ATIM1_UP_IRQHandler +ATIM2_BRK_IRQHandler +ATIM2_TRG_COM_IRQHandler +ATIM2_CC_IRQHandler +ATIM2_UP_IRQHandler +ATIM3_BRK_IRQHandler +ATIM3_TRG_COM_IRQHandler +ATIM3_CC_IRQHandler +ATIM3_UP_IRQHandler +ATIM4_BRK_IRQHandler +ATIM4_TRG_COM_IRQHandler +ATIM4_CC_IRQHandler +ATIM4_UP_IRQHandler +GTIMA1_IRQHandler +GTIMA2_IRQHandler +GTIMA3_IRQHandler +GTIMA4_IRQHandler +GTIMA5_IRQHandler +GTIMA6_IRQHandler +GTIMA7_IRQHandler +GTIMB1_IRQHandler +GTIMB2_IRQHandler +GTIMB3_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +BTIM4_IRQHandler +LPTIM1_WKUP_IRQHandler +LPTIM2_WKUP_IRQHandler +LPTIM3_WKUP_IRQHandler +LPTIM4_WKUP_IRQHandler +DSMU_FLT0_IRQHandler +DSMU_FLT1_IRQHandler +DSMU_FLT2_IRQHandler +DSMU_FLT3_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +DMAMUX1_IRQHandler +MMU_IRQHandler + + + + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_EWARM.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_EWARM.s new file mode 100644 index 0000000000..052c5d55d3 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_EWARM.s @@ -0,0 +1,1543 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + + __iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + + ; External Interrupts + DCD WWDG2_IRQHandler ; Window2 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD AHB_ICACHE_IRQHandler ; CM4 AHB iCache interrupt + DCD AHB_DCACHE_IRQHandler ; CM4 AHB dCache interrupt + DCD FPU_CPU2_IRQHandler ; FPU_CM4 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD CACHE_PARITY_ER_IRQHandler ; AHB i/dCACHE parity error intertupt + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD 0 ; Reserved + DCD SEMA4_INT2_IRQHandler ; SEMA4 interrupt2 + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUA_IRQHandler ; DCMUA interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_RQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + ;need check to user manual of exti chapter + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_IRQHandler + B WWDG2_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_TAMPER_IRQHandler + B RTC_TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK DMA2_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel0_IRQHandler + B DMA2_Channel0_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA3_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel0_IRQHandler + B DMA3_Channel0_IRQHandler + + PUBWEAK DMA3_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel1_IRQHandler + B DMA3_Channel1_IRQHandler + + PUBWEAK DMA3_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel2_IRQHandler + B DMA3_Channel2_IRQHandler + + PUBWEAK DMA3_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel3_IRQHandler + B DMA3_Channel3_IRQHandler + + PUBWEAK DMA3_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel4_IRQHandler + B DMA3_Channel4_IRQHandler + + PUBWEAK DMA3_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel5_IRQHandler + B DMA3_Channel5_IRQHandler + + PUBWEAK DMA3_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel6_IRQHandler + B DMA3_Channel6_IRQHandler + + PUBWEAK DMA3_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel7_IRQHandler + B DMA3_Channel7_IRQHandler + + PUBWEAK MDMA_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel0_IRQHandler + B MDMA_Channel0_IRQHandler + + PUBWEAK MDMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel1_IRQHandler + B MDMA_Channel1_IRQHandler + + PUBWEAK MDMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel2_IRQHandler + B MDMA_Channel2_IRQHandler + + PUBWEAK MDMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel3_IRQHandler + B MDMA_Channel3_IRQHandler + + PUBWEAK MDMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel4_IRQHandler + B MDMA_Channel4_IRQHandler + + PUBWEAK MDMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel5_IRQHandler + B MDMA_Channel5_IRQHandler + + PUBWEAK MDMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel6_IRQHandler + B MDMA_Channel6_IRQHandler + + PUBWEAK MDMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel7_IRQHandler + B MDMA_Channel7_IRQHandler + + PUBWEAK MDMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel8_IRQHandler + B MDMA_Channel8_IRQHandler + + PUBWEAK MDMA_Channel9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel9_IRQHandler + B MDMA_Channel9_IRQHandler + + PUBWEAK MDMA_Channel10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel10_IRQHandler + B MDMA_Channel10_IRQHandler + + PUBWEAK MDMA_Channel11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel11_IRQHandler + B MDMA_Channel11_IRQHandler + + PUBWEAK MDMA_Channel12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel12_IRQHandler + B MDMA_Channel12_IRQHandler + + PUBWEAK MDMA_Channel13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel13_IRQHandler + B MDMA_Channel13_IRQHandler + + PUBWEAK MDMA_Channel14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel14_IRQHandler + B MDMA_Channel14_IRQHandler + + PUBWEAK MDMA_Channel15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel15_IRQHandler + B MDMA_Channel15_IRQHandler + + PUBWEAK SDPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDPU_IRQHandler + B SDPU_IRQHandler + + PUBWEAK AHB_ICACHE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AHB_ICACHE_IRQHandler + B AHB_ICACHE_IRQHandler + + PUBWEAK AHB_DCACHE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AHB_DCACHE_IRQHandler + B AHB_DCACHE_IRQHandler + + PUBWEAK FPU_CPU2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_CPU2_IRQHandler + B FPU_CPU2_IRQHandler + + PUBWEAK ECCMON_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECCMON_IRQHandler + B ECCMON_IRQHandler + + PUBWEAK RTC_ALARM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_ALARM_IRQHandler + B RTC_ALARM_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK I2C6_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_EV_IRQHandler + B I2C6_EV_IRQHandler + + PUBWEAK I2C6_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_ER_IRQHandler + B I2C6_ER_IRQHandler + + PUBWEAK I2C7_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_EV_IRQHandler + B I2C7_EV_IRQHandler + + PUBWEAK I2C7_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_ER_IRQHandler + B I2C7_ER_IRQHandler + + PUBWEAK I2C8_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_EV_IRQHandler + B I2C8_EV_IRQHandler + + PUBWEAK I2C8_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_ER_IRQHandler + B I2C8_ER_IRQHandler + + PUBWEAK I2C9_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_EV_IRQHandler + B I2C9_EV_IRQHandler + + PUBWEAK I2C9_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_ER_IRQHandler + B I2C9_ER_IRQHandler + + PUBWEAK I2C10_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_EV_IRQHandler + B I2C10_EV_IRQHandler + + PUBWEAK I2C10_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_ER_IRQHandler + B I2C10_ER_IRQHandler + + PUBWEAK I2S1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S1_IRQHandler + B I2S1_IRQHandler + + PUBWEAK I2S2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S2_IRQHandler + B I2S2_IRQHandler + + PUBWEAK I2S3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S3_IRQHandler + B I2S3_IRQHandler + + PUBWEAK I2S4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S4_IRQHandler + B I2S4_IRQHandler + + PUBWEAK xSPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI1_IRQHandler + B xSPI1_IRQHandler + + PUBWEAK xSPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI2_IRQHandler + B xSPI2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SPI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI7_IRQHandler + B SPI7_IRQHandler + + PUBWEAK LCD_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_EV_IRQHandler + B LCD_EV_IRQHandler + + PUBWEAK LCD_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_ER_IRQHandler + B LCD_ER_IRQHandler + + PUBWEAK DVP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP1_IRQHandler + B DVP1_IRQHandler + + PUBWEAK DVP2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP2_IRQHandler + B DVP2_IRQHandler + + PUBWEAK DMAMUX2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX2_IRQHandler + B DMAMUX2_IRQHandler + + PUBWEAK USB1_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_OUT_IRQHandler + B USB1_HS_EPx_OUT_IRQHandler + + PUBWEAK USB1_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_IN_IRQHandler + B USB1_HS_EPx_IN_IRQHandler + + PUBWEAK USB1_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_WKUP_IRQHandler + B USB1_HS_WKUP_IRQHandler + + PUBWEAK USB1_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_IRQHandler + B USB1_HS_IRQHandler + + PUBWEAK USB2_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_OUT_IRQHandler + B USB2_HS_EPx_OUT_IRQHandler + + PUBWEAK USB2_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_IN_IRQHandler + B USB2_HS_EPx_IN_IRQHandler + + PUBWEAK USB2_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_WKUP_IRQHandler + B USB2_HS_WKUP_IRQHandler + + PUBWEAK USB2_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_IRQHandler + B USB2_HS_IRQHandler + + PUBWEAK ETH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_IRQHandler + B ETH1_IRQHandler + + PUBWEAK ETH1_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_PMT_LPI_IRQHandler + B ETH1_PMT_LPI_IRQHandler + + PUBWEAK ETH2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_IRQHandler + B ETH2_IRQHandler + + PUBWEAK ETH2_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_PMT_LPI_IRQHandler + B ETH2_PMT_LPI_IRQHandler + + PUBWEAK FDCAN1_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT0_IRQHandler + B FDCAN1_INT0_IRQHandler + + PUBWEAK FDCAN2_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT0_IRQHandler + B FDCAN2_INT0_IRQHandler + + PUBWEAK FDCAN3_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT0_IRQHandler + B FDCAN3_INT0_IRQHandler + + PUBWEAK FDCAN4_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT0_IRQHandler + B FDCAN4_INT0_IRQHandler + + PUBWEAK FDCAN1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT1_IRQHandler + B FDCAN1_INT1_IRQHandler + + PUBWEAK FDCAN2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT1_IRQHandler + B FDCAN2_INT1_IRQHandler + + PUBWEAK FDCAN3_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT1_IRQHandler + B FDCAN3_INT1_IRQHandler + + PUBWEAK FDCAN4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT1_IRQHandler + B FDCAN4_INT1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK USART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART7_IRQHandler + B USART7_IRQHandler + + PUBWEAK USART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART8_IRQHandler + B USART8_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK UART11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART11_IRQHandler + B UART11_IRQHandler + + PUBWEAK UART12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART12_IRQHandler + B UART12_IRQHandler + + PUBWEAK UART13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART13_IRQHandler + B UART13_IRQHandler + + PUBWEAK UART14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART14_IRQHandler + B UART14_IRQHandler + + PUBWEAK UART15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART15_IRQHandler + B UART15_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPUART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART2_IRQHandler + B LPUART2_IRQHandler + + PUBWEAK GPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPU_IRQHandler + B GPU_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK COMP1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP1_2_IRQHandler + B COMP1_2_IRQHandler + + PUBWEAK COMP3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP3_4_IRQHandler + B COMP3_4_IRQHandler + + PUBWEAK SHRTIM1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT1_IRQHandler + B SHRTIM1_INT1_IRQHandler + + PUBWEAK SHRTIM1_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT2_IRQHandler + B SHRTIM1_INT2_IRQHandler + + PUBWEAK SHRTIM1_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT3_IRQHandler + B SHRTIM1_INT3_IRQHandler + + PUBWEAK SHRTIM1_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT4_IRQHandler + B SHRTIM1_INT4_IRQHandler + + PUBWEAK SHRTIM1_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT5_IRQHandler + B SHRTIM1_INT5_IRQHandler + + PUBWEAK SHRTIM1_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT6_IRQHandler + B SHRTIM1_INT6_IRQHandler + + PUBWEAK SHRTIM1_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT7_IRQHandler + B SHRTIM1_INT7_IRQHandler + + PUBWEAK SHRTIM1_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT8_IRQHandler + B SHRTIM1_INT8_IRQHandler + + PUBWEAK SHRTIM2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT1_IRQHandler + B SHRTIM2_INT1_IRQHandler + + PUBWEAK SHRTIM2_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT2_IRQHandler + B SHRTIM2_INT2_IRQHandler + + PUBWEAK SHRTIM2_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT3_IRQHandler + B SHRTIM2_INT3_IRQHandler + + PUBWEAK SHRTIM2_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT4_IRQHandler + B SHRTIM2_INT4_IRQHandler + + PUBWEAK SHRTIM2_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT5_IRQHandler + B SHRTIM2_INT5_IRQHandler + + PUBWEAK SHRTIM2_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT6_IRQHandler + B SHRTIM2_INT6_IRQHandler + + PUBWEAK SHRTIM2_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT7_IRQHandler + B SHRTIM2_INT7_IRQHandler + + PUBWEAK SHRTIM2_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT8_IRQHandler + B SHRTIM2_INT8_IRQHandler + + PUBWEAK FDCAN5_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT0_IRQHandler + B FDCAN5_INT0_IRQHandler + + PUBWEAK FDCAN6_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT0_IRQHandler + B FDCAN6_INT0_IRQHandler + + PUBWEAK FDCAN7_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT0_IRQHandler + B FDCAN7_INT0_IRQHandler + + PUBWEAK FDCAN8_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT0_IRQHandler + B FDCAN8_INT0_IRQHandler + + PUBWEAK FDCAN5_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT1_IRQHandler + B FDCAN5_INT1_IRQHandler + + PUBWEAK FDCAN6_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT1_IRQHandler + B FDCAN6_INT1_IRQHandler + + PUBWEAK FDCAN7_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT1_IRQHandler + B FDCAN7_INT1_IRQHandler + + PUBWEAK FDCAN8_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT1_IRQHandler + B FDCAN8_INT1_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK CACHE_PARITY_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CACHE_PARITY_ER_IRQHandler + B CACHE_PARITY_ER_IRQHandler + + PUBWEAK LPTIM5_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM5_WKUP_IRQHandler + B LPTIM5_WKUP_IRQHandler + + PUBWEAK JPEG_SGDMA_H2P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_H2P_IRQHandler + B JPEG_SGDMA_H2P_IRQHandler + + PUBWEAK JPEG_SGDMA_P2H_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_P2H_IRQHandler + B JPEG_SGDMA_P2H_IRQHandler + + PUBWEAK WAKEUP_IO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WAKEUP_IO_IRQHandler + B WAKEUP_IO_IRQHandler + + PUBWEAK SEMA4_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_INT2_IRQHandler + B SEMA4_INT2_IRQHandler + + PUBWEAK WWDG2_RST_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_RST_IRQHandler + B WWDG2_RST_IRQHandler + + PUBWEAK OTPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTPC_IRQHandler + B OTPC_IRQHandler + + PUBWEAK FEMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FEMC_IRQHandler + B FEMC_IRQHandler + + PUBWEAK DCMUA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMUA_IRQHandler + B DCMUA_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK MDMA_AHBS_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_AHBS_ER_IRQHandler + B MDMA_AHBS_ER_IRQHandler + + PUBWEAK CM7_CATCH_READ_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CM7_CATCH_READ_ER_IRQHandler + B CM7_CATCH_READ_ER_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK DAC4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC4_IRQHandler + B DAC4_IRQHandler + + PUBWEAK EMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMC_IRQHandler + B EMC_IRQHandler + + PUBWEAK DAC5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC5_IRQHandler + B DAC5_IRQHandler + + PUBWEAK DAC6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC6_IRQHandler + B DAC6_IRQHandler + + PUBWEAK ESC_OPB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_OPB_IRQHandler + B ESC_OPB_IRQHandler + + PUBWEAK ESC_SYNC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC0_IRQHandler + B ESC_SYNC0_IRQHandler + + PUBWEAK ESC_SYNC1_RQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC1_RQHandler + B ESC_SYNC1_RQHandler + + PUBWEAK ESC_WRP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_WRP_IRQHandler + B ESC_WRP_IRQHandler + + PUBWEAK ATIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_BRK_IRQHandler + B ATIM1_BRK_IRQHandler + + PUBWEAK ATIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_TRG_COM_IRQHandler + B ATIM1_TRG_COM_IRQHandler + + PUBWEAK ATIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_CC_IRQHandler + B ATIM1_CC_IRQHandler + + PUBWEAK ATIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_UP_IRQHandler + B ATIM1_UP_IRQHandler + + PUBWEAK ATIM2_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_BRK_IRQHandler + B ATIM2_BRK_IRQHandler + + PUBWEAK ATIM2_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_TRG_COM_IRQHandler + B ATIM2_TRG_COM_IRQHandler + + PUBWEAK ATIM2_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_CC_IRQHandler + B ATIM2_CC_IRQHandler + + PUBWEAK ATIM2_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_UP_IRQHandler + B ATIM2_UP_IRQHandler + + PUBWEAK ATIM3_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_BRK_IRQHandler + B ATIM3_BRK_IRQHandler + + PUBWEAK ATIM3_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_TRG_COM_IRQHandler + B ATIM3_TRG_COM_IRQHandler + + PUBWEAK ATIM3_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_CC_IRQHandler + B ATIM3_CC_IRQHandler + + PUBWEAK ATIM3_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_UP_IRQHandler + B ATIM3_UP_IRQHandler + + PUBWEAK ATIM4_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_BRK_IRQHandler + B ATIM4_BRK_IRQHandler + + PUBWEAK ATIM4_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_TRG_COM_IRQHandler + B ATIM4_TRG_COM_IRQHandler + + PUBWEAK ATIM4_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_CC_IRQHandler + B ATIM4_CC_IRQHandler + + PUBWEAK ATIM4_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_UP_IRQHandler + B ATIM4_UP_IRQHandler + + PUBWEAK GTIMA1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA1_IRQHandler + B GTIMA1_IRQHandler + + PUBWEAK GTIMA2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA2_IRQHandler + B GTIMA2_IRQHandler + + PUBWEAK GTIMA3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA3_IRQHandler + B GTIMA3_IRQHandler + + PUBWEAK GTIMA4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA4_IRQHandler + B GTIMA4_IRQHandler + + PUBWEAK GTIMA5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA5_IRQHandler + B GTIMA5_IRQHandler + + PUBWEAK GTIMA6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA6_IRQHandler + B GTIMA6_IRQHandler + + PUBWEAK GTIMA7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA7_IRQHandler + B GTIMA7_IRQHandler + + PUBWEAK GTIMB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB1_IRQHandler + B GTIMB1_IRQHandler + + PUBWEAK GTIMB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB2_IRQHandler + B GTIMB2_IRQHandler + + PUBWEAK GTIMB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB3_IRQHandler + B GTIMB3_IRQHandler + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + PUBWEAK BTIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM4_IRQHandler + B BTIM4_IRQHandler + + PUBWEAK LPTIM1_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_WKUP_IRQHandler + B LPTIM1_WKUP_IRQHandler + + PUBWEAK LPTIM2_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM2_WKUP_IRQHandler + B LPTIM2_WKUP_IRQHandler + + PUBWEAK LPTIM3_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM3_WKUP_IRQHandler + B LPTIM3_WKUP_IRQHandler + + PUBWEAK LPTIM4_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM4_WKUP_IRQHandler + B LPTIM4_WKUP_IRQHandler + + PUBWEAK DSMU_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT0_IRQHandler + B DSMU_FLT0_IRQHandler + + PUBWEAK DSMU_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT1_IRQHandler + B DSMU_FLT1_IRQHandler + + PUBWEAK DSMU_FLT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT2_IRQHandler + B DSMU_FLT2_IRQHandler + + PUBWEAK DSMU_FLT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT3_IRQHandler + B DSMU_FLT3_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK DMAMUX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX1_IRQHandler + B DMAMUX1_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_gcc.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_gcc.s new file mode 100644 index 0000000000..37ed8e9dc2 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm4_gcc.s @@ -0,0 +1,1117 @@ +/********************************************************************************************************* + Copyright (c) 2024, Nations Technologies Inc. + + All rights reserved. + + This software is the exclusive property of Nations Technologies Inc. (Hereinafter + referred to as NATIONS). This software, and the product of NATIONS described herein + (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties + of the People's Republic of China and other applicable jurisdictions worldwide. + + NATIONS does not grant any license under its patents, copyrights, trademarks, or other + intellectual property rights. Names and brands of third party may be mentioned or referred + thereto (if any) for identification purposes only. + + NATIONS reserves the right to make changes, corrections, enhancements, modifications, and + improvements to this software at any time without notice. Please contact NATIONS and obtain + the latest version of this software before placing orders. + + Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes + no responsibility for the accuracy and reliability of this software. + + It is the responsibility of the user of this software to properly design, program, and test + the functionality and safety of any application made of this information and any resulting product. + In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or + consequential damages arising in any way out of the use of this software or the Product. + + NATIONS Products are neither intended nor warranted for usage in systems or equipment, any + malfunction or failure of which may cause loss of human life, bodily injury or severe property + damage. Such applications are deemed, "Insecure Usage". + + All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS + harmless from and against all claims, costs, damages, and other liabilities, arising from or related + to any customer's Insecure Usage. + + Any express or implied warranty with regard to this software or the Product, including,but not + limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement + are disclaimed to the fullest extent permitted by law. + + Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe + or otherwise distribute this software for any purposes, in whole or in part. + + NATIONS products and technologies shall not be used for or incorporated into any products or systems + whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. + User shall comply with any applicable export control laws and regulations promulgated and administered by + the governments of any countries asserting jurisdiction over the parties or transactions. + ************************************************************************************************************/ + + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** +\*fun This is the code that gets called when the processor receives an +\* unexpected interrupt. This simply enters an infinite loop, preserving +\* the system state for examination by a debugger. +**/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/** +\* The minimal vector table for a Cortex M0. Note that the proper constructs +\* must be placed on this to ensure that it ends up at physical address 0x00000000. +**/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word WWDG2_IRQHandler /* Window1 Watchdog interrupt */ + .word PVD_IRQHandler /* PVD through EXTI Line16 detection interrupt */ + .word RTC_TAMPER_IRQHandler /* RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup timer through EXTI line 19 interrupt */ + .word RCC_IRQHandler /* RCC interrupt */ + .word EXTI0_IRQHandler /* EXTI Line 0 interrupt */ + .word EXTI1_IRQHandler /* EXTI Line 1 interrupt */ + .word EXTI2_IRQHandler /* EXTI Line 2 interrupt */ + .word EXTI3_IRQHandler /* EXTI Line 3 interrupt */ + .word EXTI4_IRQHandler /* EXTI Line 4 interrupt */ + .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupt */ + .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupt */ + .word DMA1_Channel0_IRQHandler /* DMA1 Channel 0 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA2_Channel0_IRQHandler /* DMA2 Channel 0 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA3_Channel0_IRQHandler /* DMA3 Channel 0 */ + .word DMA3_Channel1_IRQHandler /* DMA3 Channel 1 */ + .word DMA3_Channel2_IRQHandler /* DMA3 Channel 2 */ + .word DMA3_Channel3_IRQHandler /* DMA3 Channel 3 */ + .word DMA3_Channel4_IRQHandler /* DMA3 Channel 4 */ + .word DMA3_Channel5_IRQHandler /* DMA3 Channel 5 */ + .word DMA3_Channel6_IRQHandler /* DMA3 Channel 6 */ + .word DMA3_Channel7_IRQHandler /* DMA3 Channel 7 */ + .word MDMA_Channel0_IRQHandler /* MDMA Channel 0 */ + .word MDMA_Channel1_IRQHandler /* MDMA Channel 1 */ + .word MDMA_Channel2_IRQHandler /* MDMA Channel 2 */ + .word MDMA_Channel3_IRQHandler /* MDMA Channel 3 */ + .word MDMA_Channel4_IRQHandler /* MDMA Channel 4 */ + .word MDMA_Channel5_IRQHandler /* MDMA Channel 5 */ + .word MDMA_Channel6_IRQHandler /* MDMA Channel 6 */ + .word MDMA_Channel7_IRQHandler /* MDMA Channel 7 */ + .word MDMA_Channel8_IRQHandler /* MDMA Channel 8 */ + .word MDMA_Channel9_IRQHandler /* MDMA Channel 9 */ + .word MDMA_Channel10_IRQHandler /* MDMA Channel 10 */ + .word MDMA_Channel11_IRQHandler /* MDMA Channel 11 */ + .word MDMA_Channel12_IRQHandler /* MDMA Channel 12 */ + .word MDMA_Channel13_IRQHandler /* MDMA Channel 13 */ + .word MDMA_Channel14_IRQHandler /* MDMA Channel 14 */ + .word MDMA_Channel15_IRQHandler /* MDMA Channel 15 */ + .word SDPU_IRQHandler /* SDPU global interrupt */ + .word AHB_ICACHE_IRQHandler /* CM4 AHB iCache interrupt */ + .word AHB_DCACHE_IRQHandler /* CM4 AHB dCache interrupt */ + .word FPU_CPU2_IRQHandler /* FPU_CM4 global interrupt */ + .word ECCMON_IRQHandler /* ECCMON global interrupt */ + .word RTC_ALARM_IRQHandler /* RTC Alarm via EXTI17 interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ + .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 event interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 error interrupt */ + .word I2C6_EV_IRQHandler /* I2C6 event interrupt */ + .word I2C6_ER_IRQHandler /* I2C6 error interrupt */ + .word I2C7_EV_IRQHandler /* I2C7 event interrupt */ + .word I2C7_ER_IRQHandler /* I2C7 error interrupt */ + .word I2C8_EV_IRQHandler /* I2C8 event interrupt */ + .word I2C8_ER_IRQHandler /* I2C8 error interrupt */ + .word I2C9_EV_IRQHandler /* I2C9 event interrupt */ + .word I2C9_ER_IRQHandler /* I2C9 error interrupt */ + .word I2C10_EV_IRQHandler /* I2C10 event interrupt */ + .word I2C10_ER_IRQHandler /* I2C10 error interrupt */ + .word I2S1_IRQHandler /* I2S1 global interrupt */ + .word I2S2_IRQHandler /* I2S1 global interrupt */ + .word I2S3_IRQHandler /* I2S1 global interrupt */ + .word I2S4_IRQHandler /* I2S1 global interrupt */ + .word xSPI1_IRQHandler /* xSPI1 global interrupt */ + .word xSPI2_IRQHandler /* xSPI1 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word SPI3_IRQHandler /* SPI3 global interrupt */ + .word SPI4_IRQHandler /* SPI4 global interrupt */ + .word SPI5_IRQHandler /* SPI5 global interrupt */ + .word SPI6_IRQHandler /* SPI6 global interrupt */ + .word SPI7_IRQHandler /* SPI7 global interrupt */ + .word LCD_EV_IRQHandler /* TFT LCD Controller event interrupt */ + .word LCD_ER_IRQHandler /* TFT LCD Controller error interrupt */ + .word DVP1_IRQHandler /* DVP1 global interrupt */ + .word DVP2_IRQHandler /* DVP2 global interrupt */ + .word DMAMUX2_IRQHandler /* DMAMUX2 (MDMA MUX) global interrupt */ + .word USB1_HS_EPx_OUT_IRQHandler /* USB1_HS endpoint out global interrupt */ + .word USB1_HS_EPx_IN_IRQHandler /* USB1_HS endpoint in global interrupt */ + .word USB1_HS_WKUP_IRQHandler /* USB1_HS WKUP interrupt through EXTI line 62 */ + .word USB1_HS_IRQHandler /* USB1_HS global interrupt */ + .word USB2_HS_EPx_OUT_IRQHandler /* USB2_HS endpoint out global interrupt */ + .word USB2_HS_EPx_IN_IRQHandler /* USB2_HS endpoint in global interrupt */ + .word USB2_HS_WKUP_IRQHandler /* USB2_HS WKUP interrupt through EXTI line 63 */ + .word USB2_HS_IRQHandler /* USB2_HS global interrupt */ + .word ETH1_IRQHandler /* Ethernet 1 global interrupt */ + .word ETH1_PMT_LPI_IRQHandler /* Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 */ + .word ETH2_IRQHandler /* Ethernet 2 global interrupt */ + .word ETH2_PMT_LPI_IRQHandler /* Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 */ + .word FDCAN1_INT0_IRQHandler /* FDCAN1 global interrupt line 0 */ + .word FDCAN2_INT0_IRQHandler /* FDCAN2 global interrupt line 0 */ + .word FDCAN3_INT0_IRQHandler /* FDCAN3 global interrupt line 0 */ + .word FDCAN4_INT0_IRQHandler /* FDCAN4 global interrupt line 0 */ + .word FDCAN1_INT1_IRQHandler /* FDCAN1 global interrupt line 1 */ + .word FDCAN2_INT1_IRQHandler /* FDCAN2 global interrupt line 1 */ + .word FDCAN3_INT1_IRQHandler /* FDCAN3 global interrupt line 1 */ + .word FDCAN4_INT1_IRQHandler /* FDCAN4 global interrupt line 1 */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word USART3_IRQHandler /* USART3 global interrupt */ + .word USART4_IRQHandler /* USART4 global interrupt */ + .word USART5_IRQHandler /* USART5 global interrupt */ + .word USART6_IRQHandler /* USART6 global interrupt */ + .word USART7_IRQHandler /* USART7 global interrupt */ + .word USART8_IRQHandler /* USART8 global interrupt */ + .word UART9_IRQHandler /* UART9 global interrupt */ + .word UART10_IRQHandler /* UART10 global interrupt */ + .word UART11_IRQHandler /* UART11 global interrupt */ + .word UART12_IRQHandler /* UART12 global interrupt */ + .word UART13_IRQHandler /* UART13 global interrupt */ + .word UART14_IRQHandler /* UART14 global interrupt */ + .word UART15_IRQHandler /* UART15 global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt + wakeup through EXTI line 49 */ + .word LPUART2_IRQHandler /* LPUART2 global interrupt + wakeup through EXTI line 52 */ + .word GPU_IRQHandler /* GPU global interrupt */ + .word 0 /* Reserved */ + .word SDMMC1_IRQHandler /* SDMMC1_IRQ + WKUP through EXTI line 24 */ + .word SDMMC2_IRQHandler /* SDMMC2_IRQ + WKUP through EXTI line 25 */ + .word ADC1_IRQHandler /* ADC1 global interrupt */ + .word ADC2_IRQHandler /* ADC2 global interrupt */ + .word ADC3_IRQHandler /* ADC3 global interrupt */ + .word COMP1_2_IRQHandler /* COMP1 and COMP2 through EXTI line 20 and 21 */ + .word COMP3_4_IRQHandler /* COMP3 and COMP4 through EXTI line 22 and 23 */ + .word SHRTIM1_INT1_IRQHandler /* High Resolution timer 1 interrupt 1 */ + .word SHRTIM1_INT2_IRQHandler /* High Resolution timer 1 interrupt 2 */ + .word SHRTIM1_INT3_IRQHandler /* High Resolution timer 1 interrupt 3 */ + .word SHRTIM1_INT4_IRQHandler /* High Resolution timer 1 interrupt 4 */ + .word SHRTIM1_INT5_IRQHandler /* High Resolution timer 1 interrupt 5 */ + .word SHRTIM1_INT6_IRQHandler /* High Resolution timer 1 interrupt 6 */ + .word SHRTIM1_INT7_IRQHandler /* High Resolution timer 1 interrupt 7 */ + .word SHRTIM1_INT8_IRQHandler /* High Resolution timer 1 interrupt 8 */ + .word SHRTIM2_INT1_IRQHandler /* High Resolution timer 2 interrupt 1 */ + .word SHRTIM2_INT2_IRQHandler /* High Resolution timer 2 interrupt 2 */ + .word SHRTIM2_INT3_IRQHandler /* High Resolution timer 2 interrupt 3 */ + .word SHRTIM2_INT4_IRQHandler /* High Resolution timer 2 interrupt 4 */ + .word SHRTIM2_INT5_IRQHandler /* High Resolution timer 2 interrupt 5 */ + .word SHRTIM2_INT6_IRQHandler /* High Resolution timer 2 interrupt 6 */ + .word SHRTIM2_INT7_IRQHandler /* High Resolution timer 2 interrupt 7 */ + .word SHRTIM2_INT8_IRQHandler /* High Resolution timer 2 interrupt 8 */ + .word FDCAN5_INT0_IRQHandler /* FDCAN5 global interrupt line 0 */ + .word FDCAN6_INT0_IRQHandler /* FDCAN6 global interrupt line 0 */ + .word FDCAN7_INT0_IRQHandler /* FDCAN7 global interrupt line 0 */ + .word FDCAN8_INT0_IRQHandler /* FDCAN8 global interrupt line 0 */ + .word FDCAN5_INT1_IRQHandler /* FDCAN5 global interrupt line 1 */ + .word FDCAN6_INT1_IRQHandler /* FDCAN6 global interrupt line 1 */ + .word FDCAN7_INT1_IRQHandler /* FDCAN7 global interrupt line 1 */ + .word FDCAN8_INT1_IRQHandler /* FDCAN8 global interrupt line 1 */ + .word DSI_IRQHandler /* MIPI DSI Interrupt through EXTI line 87 */ + .word AHB_CACHE_PARMON_IRQHandler /* AHB i/dCACHE parity error intertupt */ + .word LPTIM5_WKUP_IRQHandler /* LPTIM5 wakeup through EXTI 86 */ + .word JPEG_SGDMA_H2P_IRQHandler /* JPEG SGDMA Host to Peripheral Interrupt */ + .word JPEG_SGDMA_P2H_IRQHandler /* JPEG SGDMA Peripheral to Host Interrupt */ + .word WAKEUP_IO_IRQHandler /* 6 WAKEUP IOs through EXTI line 70-75 */ + .word 0 /* Reserved */ + .word SEMA4_INT2_IRQHandler /* SEMA4 interrupt2 */ + .word WWDG1_RST_IRQHandler /* WWDG1 reset interrupt through EXTI line 81 */ + .word OTPC_IRQHandler /* OTPC interrupt */ + .word FEMC_IRQHandler /* FEMC interrupt */ + .word DCMUB_IRQHandler /* DCMUB interrupt */ + .word DAC1_IRQHandler /* DAC1 interrupt */ + .word DAC2_IRQHandler /* DAC2 interrupt */ + .word MDMA_AHBS_ER_IRQHandler /* MDMA HABS ERROR through EXTI line55-56 */ + .word CM7_CATCH_READ_ER_IRQHandler /* CM7 Error on Cache Read through EXTI line 64-65 */ + .word DAC3_IRQHandler /* DAC3 interrupt */ + .word DAC4_IRQHandler /* DAC4 interrupt */ + .word EMC_IRQHandler /* EMC event interrupt through EXTI line 88-89 */ + .word DAC5_IRQHandler /* DAC5 interrupt */ + .word DAC6_IRQHandler /* DAC6 interrupt */ + .word ESC_OPB_IRQHandler /* ETHERCAT OPB Interrupt */ + .word ESC_SYNC0_IRQHandler /* ETHERCAT SYNC0 Interrupt */ + .word ESC_SYNC1_IRQHandler /* ETHERCAT SYNC1 Interrupt */ + .word ESC_WRP_IRQHandler /* ETHERCAT WRAPPER Interrupt */ + .word 0 /* Reserved */ + .word ATIM1_BRK_IRQHandler /* Advanced timer 1 break interrupt */ + .word ATIM1_TRG_COM_IRQHandler /* Advanced timer 1 trigger and commutation interrupts */ + .word ATIM1_CC_IRQHandler /* Advanced timer 1 capture/compare interrupt */ + .word ATIM1_UP_IRQHandler /* Advanced timer 1 update interrupt */ + .word ATIM2_BRK_IRQHandler /* Advanced timer 2 break interrupt */ + .word ATIM2_TRG_COM_IRQHandler /* advanced timer 2 trigger and commutation interrupts */ + .word ATIM2_CC_IRQHandler /* Advanced timer 2 capture/compare interrupt */ + .word ATIM2_UP_IRQHandler /* Advanced timer 2 update interrupt */ + .word ATIM3_BRK_IRQHandler /* Advanced timer 3 break interrupt */ + .word ATIM3_TRG_COM_IRQHandler /* Advanced timer 3 trigger and commutation interrupts */ + .word ATIM3_CC_IRQHandler /* Advanced timer 3 capture/compare interrupt */ + .word ATIM3_UP_IRQHandler /* Advanced timer 3 update interrupt */ + .word ATIM4_BRK_IRQHandler /* Advanced timer 4 break interrupt */ + .word ATIM4_TRG_COM_IRQHandler /* Advanced timer 4 trigger and commutation interrupts */ + .word ATIM4_CC_IRQHandler /* Advanced timer 4 capture/compare interrupt */ + .word ATIM4_UP_IRQHandler /* Advanced timer 4 update interrupt */ + .word GTIMA1_IRQHandler /* General timer A1 global interrupt */ + .word GTIMA2_IRQHandler /* General timer A2 global interrupt */ + .word GTIMA3_IRQHandler /* General timer A3 global interrupt */ + .word GTIMA4_IRQHandler /* General timer A4 global interrupt */ + .word GTIMA5_IRQHandler /* General timer A5 global interrupt */ + .word GTIMA6_IRQHandler /* General timer A6 global interrupt */ + .word GTIMA7_IRQHandler /* General timer A7 global interrupt */ + .word GTIMB1_IRQHandler /* General timer B1 global interrupt */ + .word GTIMB2_IRQHandler /* General timer B2 global interrupt */ + .word GTIMB3_IRQHandler /* General timer B3 global interrupt */ + .word BTIM1_IRQHandler /* Base timer 1 global interrupt */ + .word BTIM2_IRQHandler /* Base timer 2 global interrupt */ + .word BTIM3_IRQHandler /* Base timer 3 global interrupt */ + .word BTIM4_IRQHandler /* Base timer 4 global interrupt */ + .word LPTIM1_WKUP_IRQHandler /* LPTIM1 wakeup interrupt */ + .word LPTIM2_WKUP_IRQHandler /* LPTIM2 wakeup interrupt */ + .word LPTIM3_WKUP_IRQHandler /* LPTIM3 wakeup interrupt */ + .word LPTIM4_WKUP_IRQHandler /* LPTIM4 wakeup interrupt */ + .word DSMU_FLT0_IRQHandler /* DSMU Filter interrupt 0 */ + .word DSMU_FLT1_IRQHandler /* DSMU Filter interrupt 1 */ + .word DSMU_FLT2_IRQHandler /* DSMU Filter interrupt 2 */ + .word DSMU_FLT3_IRQHandler /* DSMU Filter interrupt 3 */ + .word FMAC_IRQHandler /* FMAC global interrupt */ + .word CORDIC_IRQHandler /* Cordic global interrupt */ + .word DMAMUX1_IRQHandler /* DMAMUX1 interrupt */ + .word MMU_IRQHandler /* MMU interrupt */ + /* need check to user manual of exti chapter */ + +/** +\* Provide weak aliases for each Exception handler to the Default_Handler. +\* As they are weak aliases, any function with the same name will override +\* this definition. +**/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG2_IRQHandler + .thumb_set WWDG2_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMPER_IRQHandler + .thumb_set RTC_TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak DMA1_Channel0_IRQHandler + .thumb_set DMA1_Channel0_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel0_IRQHandler + .thumb_set DMA2_Channel0_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA3_Channel0_IRQHandler + .thumb_set DMA3_Channel0_IRQHandler,Default_Handler + + .weak DMA3_Channel1_IRQHandler + .thumb_set DMA3_Channel1_IRQHandler,Default_Handler + + .weak DMA3_Channel2_IRQHandler + .thumb_set DMA3_Channel2_IRQHandler,Default_Handler + + .weak DMA3_Channel3_IRQHandler + .thumb_set DMA3_Channel3_IRQHandler,Default_Handler + + .weak DMA3_Channel4_IRQHandler + .thumb_set DMA3_Channel4_IRQHandler,Default_Handler + + .weak DMA3_Channel5_IRQHandler + .thumb_set DMA3_Channel5_IRQHandler,Default_Handler + + .weak DMA3_Channel6_IRQHandler + .thumb_set DMA3_Channel6_IRQHandler,Default_Handler + + .weak DMA3_Channel7_IRQHandler + .thumb_set DMA3_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel0_IRQHandler + .thumb_set MDMA_Channel0_IRQHandler,Default_Handler + + .weak MDMA_Channel1_IRQHandler + .thumb_set MDMA_Channel1_IRQHandler,Default_Handler + + .weak MDMA_Channel2_IRQHandler + .thumb_set MDMA_Channel2_IRQHandler,Default_Handler + + .weak MDMA_Channel3_IRQHandler + .thumb_set MDMA_Channel3_IRQHandler,Default_Handler + + .weak MDMA_Channel4_IRQHandler + .thumb_set MDMA_Channel4_IRQHandler,Default_Handler + + .weak MDMA_Channel5_IRQHandler + .thumb_set MDMA_Channel5_IRQHandler,Default_Handler + + .weak MDMA_Channel6_IRQHandler + .thumb_set MDMA_Channel6_IRQHandler,Default_Handler + + .weak MDMA_Channel7_IRQHandler + .thumb_set MDMA_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel8_IRQHandler + .thumb_set MDMA_Channel8_IRQHandler,Default_Handler + + .weak MDMA_Channel9_IRQHandler + .thumb_set MDMA_Channel9_IRQHandler,Default_Handler + + .weak MDMA_Channel10_IRQHandler + .thumb_set MDMA_Channel10_IRQHandler,Default_Handler + + .weak MDMA_Channel11_IRQHandler + .thumb_set MDMA_Channel11_IRQHandler,Default_Handler + + .weak MDMA_Channel12_IRQHandler + .thumb_set MDMA_Channel12_IRQHandler,Default_Handler + + .weak MDMA_Channel13_IRQHandler + .thumb_set MDMA_Channel13_IRQHandler,Default_Handler + + .weak MDMA_Channel14_IRQHandler + .thumb_set MDMA_Channel14_IRQHandler,Default_Handler + + .weak MDMA_Channel15_IRQHandler + .thumb_set MDMA_Channel15_IRQHandler,Default_Handler + + .weak SDPU_IRQHandler + .thumb_set SDPU_IRQHandler,Default_Handler + + .weak AHB_ICACHE_IRQHandler + .thumb_set AHB_ICACHE_IRQHandler,Default_Handler + + .weak AHB_DCACHE_IRQHandler + .thumb_set AHB_DCACHE_IRQHandler,Default_Handler + + .weak FPU_CPU2_IRQHandler + .thumb_set FPU_CPU2_IRQHandler,Default_Handler + + .weak ECCMON_IRQHandler + .thumb_set ECCMON_IRQHandler,Default_Handler + + .weak RTC_ALARM_IRQHandler + .thumb_set RTC_ALARM_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak I2C6_EV_IRQHandler + .thumb_set I2C6_EV_IRQHandler,Default_Handler + + .weak I2C6_ER_IRQHandler + .thumb_set I2C6_ER_IRQHandler,Default_Handler + + .weak I2C7_EV_IRQHandler + .thumb_set I2C7_EV_IRQHandler,Default_Handler + + .weak I2C7_ER_IRQHandler + .thumb_set I2C7_ER_IRQHandler,Default_Handler + + .weak I2C8_EV_IRQHandler + .thumb_set I2C8_EV_IRQHandler,Default_Handler + + .weak I2C8_ER_IRQHandler + .thumb_set I2C8_ER_IRQHandler,Default_Handler + + .weak I2C9_EV_IRQHandler + .thumb_set I2C9_EV_IRQHandler,Default_Handler + + .weak I2C9_ER_IRQHandler + .thumb_set I2C9_ER_IRQHandler,Default_Handler + + .weak I2C10_EV_IRQHandler + .thumb_set I2C10_EV_IRQHandler,Default_Handler + + .weak I2C10_ER_IRQHandler + .thumb_set I2C10_ER_IRQHandler,Default_Handler + + .weak I2S1_IRQHandler + .thumb_set I2S1_IRQHandler,Default_Handler + + .weak I2S2_IRQHandler + .thumb_set I2S2_IRQHandler,Default_Handler + + .weak I2S3_IRQHandler + .thumb_set I2S3_IRQHandler,Default_Handler + + .weak I2S4_IRQHandler + .thumb_set I2S4_IRQHandler,Default_Handler + + .weak xSPI1_IRQHandler + .thumb_set xSPI1_IRQHandler,Default_Handler + + .weak xSPI2_IRQHandler + .thumb_set xSPI2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SPI7_IRQHandler + .thumb_set SPI7_IRQHandler,Default_Handler + + .weak LCD_EV_IRQHandler + .thumb_set LCD_EV_IRQHandler,Default_Handler + + .weak LCD_ER_IRQHandler + .thumb_set LCD_ER_IRQHandler,Default_Handler + + .weak DVP1_IRQHandler + .thumb_set DVP1_IRQHandler,Default_Handler + + .weak DVP2_IRQHandler + .thumb_set DVP2_IRQHandler,Default_Handler + + .weak DMAMUX2_IRQHandler + .thumb_set DMAMUX2_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_OUT_IRQHandler + .thumb_set USB1_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_IN_IRQHandler + .thumb_set USB1_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB1_HS_WKUP_IRQHandler + .thumb_set USB1_HS_WKUP_IRQHandler,Default_Handler + + .weak USB1_HS_IRQHandler + .thumb_set USB1_HS_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_OUT_IRQHandler + .thumb_set USB2_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_IN_IRQHandler + .thumb_set USB2_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB2_HS_WKUP_IRQHandler + .thumb_set USB2_HS_WKUP_IRQHandler,Default_Handler + + .weak USB2_HS_IRQHandler + .thumb_set USB2_HS_IRQHandler,Default_Handler + + .weak ETH1_IRQHandler + .thumb_set ETH1_IRQHandler,Default_Handler + + .weak ETH1_PMT_LPI_IRQHandler + .thumb_set ETH1_PMT_LPI_IRQHandler,Default_Handler + + .weak ETH2_IRQHandler + .thumb_set ETH2_IRQHandler,Default_Handler + + .weak ETH2_PMT_LPI_IRQHandler + .thumb_set ETH2_PMT_LPI_IRQHandler,Default_Handler + + .weak FDCAN1_INT0_IRQHandler + .thumb_set FDCAN1_INT0_IRQHandler,Default_Handler + + .weak FDCAN2_INT0_IRQHandler + .thumb_set FDCAN2_INT0_IRQHandler,Default_Handler + + .weak FDCAN3_INT0_IRQHandler + .thumb_set FDCAN3_INT0_IRQHandler,Default_Handler + + .weak FDCAN4_INT0_IRQHandler + .thumb_set FDCAN4_INT0_IRQHandler,Default_Handler + + .weak FDCAN1_INT1_IRQHandler + .thumb_set FDCAN1_INT1_IRQHandler,Default_Handler + + .weak FDCAN2_INT1_IRQHandler + .thumb_set FDCAN2_INT1_IRQHandler,Default_Handler + + .weak FDCAN3_INT1_IRQHandler + .thumb_set FDCAN3_INT1_IRQHandler,Default_Handler + + .weak FDCAN4_INT1_IRQHandler + .thumb_set FDCAN4_INT1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak UART10_IRQHandler + .thumb_set UART10_IRQHandler,Default_Handler + + .weak UART11_IRQHandler + .thumb_set UART11_IRQHandler,Default_Handler + + .weak UART12_IRQHandler + .thumb_set UART12_IRQHandler,Default_Handler + + .weak UART13_IRQHandler + .thumb_set UART13_IRQHandler,Default_Handler + + .weak UART14_IRQHandler + .thumb_set UART14_IRQHandler,Default_Handler + + .weak UART15_IRQHandler + .thumb_set UART15_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPUART2_IRQHandler + .thumb_set LPUART2_IRQHandler,Default_Handler + + .weak GPU_IRQHandler + .thumb_set GPU_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler,Default_Handler + + .weak COMP3_4_IRQHandler + .thumb_set COMP3_4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT1_IRQHandler + .thumb_set SHRTIM1_INT1_IRQHandler,Default_Handler + + .weak SHRTIM1_INT2_IRQHandler + .thumb_set SHRTIM1_INT2_IRQHandler,Default_Handler + + .weak SHRTIM1_INT3_IRQHandler + .thumb_set SHRTIM1_INT3_IRQHandler,Default_Handler + + .weak SHRTIM1_INT4_IRQHandler + .thumb_set SHRTIM1_INT4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT5_IRQHandler + .thumb_set SHRTIM1_INT5_IRQHandler,Default_Handler + + .weak SHRTIM1_INT6_IRQHandler + .thumb_set SHRTIM1_INT6_IRQHandler,Default_Handler + + .weak SHRTIM1_INT7_IRQHandler + .thumb_set SHRTIM1_INT7_IRQHandler,Default_Handler + + .weak SHRTIM1_INT8_IRQHandler + .thumb_set SHRTIM1_INT8_IRQHandler,Default_Handler + + .weak SHRTIM2_INT1_IRQHandler + .thumb_set SHRTIM2_INT1_IRQHandler,Default_Handler + + .weak SHRTIM2_INT2_IRQHandler + .thumb_set SHRTIM2_INT2_IRQHandler,Default_Handler + + .weak SHRTIM2_INT3_IRQHandler + .thumb_set SHRTIM2_INT3_IRQHandler,Default_Handler + + .weak SHRTIM2_INT4_IRQHandler + .thumb_set SHRTIM2_INT4_IRQHandler,Default_Handler + + .weak SHRTIM2_INT5_IRQHandler + .thumb_set SHRTIM2_INT5_IRQHandler,Default_Handler + + .weak SHRTIM2_INT6_IRQHandler + .thumb_set SHRTIM2_INT6_IRQHandler,Default_Handler + + .weak SHRTIM2_INT7_IRQHandler + .thumb_set SHRTIM2_INT7_IRQHandler,Default_Handler + + .weak SHRTIM2_INT8_IRQHandler + .thumb_set SHRTIM2_INT8_IRQHandler,Default_Handler + + .weak FDCAN5_INT0_IRQHandler + .thumb_set FDCAN5_INT0_IRQHandler,Default_Handler + + .weak FDCAN6_INT0_IRQHandler + .thumb_set FDCAN6_INT0_IRQHandler,Default_Handler + + .weak FDCAN7_INT0_IRQHandler + .thumb_set FDCAN7_INT0_IRQHandler,Default_Handler + + .weak FDCAN8_INT0_IRQHandler + .thumb_set FDCAN8_INT0_IRQHandler,Default_Handler + + .weak FDCAN5_INT1_IRQHandler + .thumb_set FDCAN5_INT1_IRQHandler,Default_Handler + + .weak FDCAN6_INT1_IRQHandler + .thumb_set FDCAN6_INT1_IRQHandler,Default_Handler + + .weak FDCAN7_INT1_IRQHandler + .thumb_set FDCAN7_INT1_IRQHandler,Default_Handler + + .weak FDCAN8_INT1_IRQHandler + .thumb_set FDCAN8_INT1_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak AHB_CACHE_PARMON_IRQHandler + .thumb_set AHB_CACHE_PARMON_IRQHandler,Default_Handler + + .weak LPTIM5_WKUP_IRQHandler + .thumb_set LPTIM5_WKUP_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_H2P_IRQHandler + .thumb_set JPEG_SGDMA_H2P_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_P2H_IRQHandler + .thumb_set JPEG_SGDMA_P2H_IRQHandler,Default_Handler + + .weak WAKEUP_IO_IRQHandler + .thumb_set WAKEUP_IO_IRQHandler,Default_Handler + + .weak SEMA4_INT2_IRQHandler + .thumb_set SEMA4_INT2_IRQHandler,Default_Handler + + .weak WWDG1_RST_IRQHandler + .thumb_set WWDG1_RST_IRQHandler,Default_Handler + + .weak OTPC_IRQHandler + .thumb_set OTPC_IRQHandler,Default_Handler + + .weak FEMC_IRQHandler + .thumb_set FEMC_IRQHandler,Default_Handler + + .weak DCMUB_IRQHandler + .thumb_set DCMUB_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak DAC2_IRQHandler + .thumb_set DAC2_IRQHandler,Default_Handler + + .weak MDMA_AHBS_ER_IRQHandler + .thumb_set MDMA_AHBS_ER_IRQHandler,Default_Handler + + .weak CM7_CATCH_READ_ER_IRQHandler + .thumb_set CM7_CATCH_READ_ER_IRQHandler,Default_Handler + + .weak DAC3_IRQHandler + .thumb_set DAC3_IRQHandler,Default_Handler + + .weak DAC4_IRQHandler + .thumb_set DAC4_IRQHandler,Default_Handler + + .weak EMC_IRQHandler + .thumb_set EMC_IRQHandler,Default_Handler + + .weak DAC5_IRQHandler + .thumb_set DAC5_IRQHandler,Default_Handler + + .weak DAC6_IRQHandler + .thumb_set DAC6_IRQHandler,Default_Handler + + .weak ESC_OPB_IRQHandler + .thumb_set ESC_OPB_IRQHandler,Default_Handler + + .weak ESC_SYNC0_IRQHandler + .thumb_set ESC_SYNC0_IRQHandler,Default_Handler + + .weak ESC_SYNC1_IRQHandler + .thumb_set ESC_SYNC1_IRQHandler,Default_Handler + + .weak ESC_WRP_IRQHandler + .thumb_set ESC_WRP_IRQHandler,Default_Handler + + .weak ATIM1_BRK_IRQHandler + .thumb_set ATIM1_BRK_IRQHandler,Default_Handler + + .weak ATIM1_TRG_COM_IRQHandler + .thumb_set ATIM1_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM1_CC_IRQHandler + .thumb_set ATIM1_CC_IRQHandler,Default_Handler + + .weak ATIM1_UP_IRQHandler + .thumb_set ATIM1_UP_IRQHandler,Default_Handler + + .weak ATIM2_BRK_IRQHandler + .thumb_set ATIM2_BRK_IRQHandler,Default_Handler + + .weak ATIM2_TRG_COM_IRQHandler + .thumb_set ATIM2_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM2_CC_IRQHandler + .thumb_set ATIM2_CC_IRQHandler,Default_Handler + + .weak ATIM2_UP_IRQHandler + .thumb_set ATIM2_UP_IRQHandler,Default_Handler + + .weak ATIM3_BRK_IRQHandler + .thumb_set ATIM3_BRK_IRQHandler,Default_Handler + + .weak ATIM3_TRG_COM_IRQHandler + .thumb_set ATIM3_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM3_CC_IRQHandler + .thumb_set ATIM3_CC_IRQHandler,Default_Handler + + .weak ATIM3_UP_IRQHandler + .thumb_set ATIM3_UP_IRQHandler,Default_Handler + + .weak ATIM4_BRK_IRQHandler + .thumb_set ATIM4_BRK_IRQHandler,Default_Handler + + .weak ATIM4_TRG_COM_IRQHandler + .thumb_set ATIM4_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM4_CC_IRQHandler + .thumb_set ATIM4_CC_IRQHandler,Default_Handler + + .weak ATIM4_UP_IRQHandler + .thumb_set ATIM4_UP_IRQHandler,Default_Handler + + .weak GTIMA1_IRQHandler + .thumb_set GTIMA1_IRQHandler,Default_Handler + + .weak GTIMA2_IRQHandler + .thumb_set GTIMA2_IRQHandler,Default_Handler + + .weak GTIMA3_IRQHandler + .thumb_set GTIMA3_IRQHandler,Default_Handler + + .weak GTIMA4_IRQHandler + .thumb_set GTIMA4_IRQHandler,Default_Handler + + .weak GTIMA5_IRQHandler + .thumb_set GTIMA5_IRQHandler,Default_Handler + + .weak GTIMA6_IRQHandler + .thumb_set GTIMA6_IRQHandler,Default_Handler + + .weak GTIMA7_IRQHandler + .thumb_set GTIMA7_IRQHandler,Default_Handler + + .weak GTIMB1_IRQHandler + .thumb_set GTIMB1_IRQHandler,Default_Handler + + .weak GTIMB2_IRQHandler + .thumb_set GTIMB2_IRQHandler,Default_Handler + + .weak GTIMB3_IRQHandler + .thumb_set GTIMB3_IRQHandler,Default_Handler + + .weak BTIM1_IRQHandler + .thumb_set BTIM1_IRQHandler,Default_Handler + + .weak BTIM2_IRQHandler + .thumb_set BTIM2_IRQHandler,Default_Handler + + .weak BTIM3_IRQHandler + .thumb_set BTIM3_IRQHandler,Default_Handler + + .weak BTIM4_IRQHandler + .thumb_set BTIM4_IRQHandler,Default_Handler + + .weak LPTIM1_WKUP_IRQHandler + .thumb_set LPTIM1_WKUP_IRQHandler,Default_Handler + + .weak LPTIM2_WKUP_IRQHandler + .thumb_set LPTIM2_WKUP_IRQHandler,Default_Handler + + .weak LPTIM3_WKUP_IRQHandler + .thumb_set LPTIM3_WKUP_IRQHandler,Default_Handler + + .weak LPTIM4_WKUP_IRQHandler + .thumb_set LPTIM4_WKUP_IRQHandler,Default_Handler + + .weak DSMU_FLT0_IRQHandler + .thumb_set DSMU_FLT0_IRQHandler,Default_Handler + + .weak DSMU_FLT1_IRQHandler + .thumb_set DSMU_FLT1_IRQHandler,Default_Handler + + .weak DSMU_FLT2_IRQHandler + .thumb_set DSMU_FLT2_IRQHandler,Default_Handler + + .weak DSMU_FLT3_IRQHandler + .thumb_set DSMU_FLT3_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak DMAMUX1_IRQHandler + .thumb_set DMAMUX1_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7.s new file mode 100644 index 0000000000..fc64b849b0 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7.s @@ -0,0 +1,892 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD 0 ; + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_IRQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +N32SysTick_Handler PROC + EXPORT N32SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG1_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMPER_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT DMA1_Channel0_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel0_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA3_Channel0_IRQHandler [WEAK] + EXPORT DMA3_Channel1_IRQHandler [WEAK] + EXPORT DMA3_Channel2_IRQHandler [WEAK] + EXPORT DMA3_Channel3_IRQHandler [WEAK] + EXPORT DMA3_Channel4_IRQHandler [WEAK] + EXPORT DMA3_Channel5_IRQHandler [WEAK] + EXPORT DMA3_Channel6_IRQHandler [WEAK] + EXPORT DMA3_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel0_IRQHandler [WEAK] + EXPORT MDMA_Channel1_IRQHandler [WEAK] + EXPORT MDMA_Channel2_IRQHandler [WEAK] + EXPORT MDMA_Channel3_IRQHandler [WEAK] + EXPORT MDMA_Channel4_IRQHandler [WEAK] + EXPORT MDMA_Channel5_IRQHandler [WEAK] + EXPORT MDMA_Channel6_IRQHandler [WEAK] + EXPORT MDMA_Channel7_IRQHandler [WEAK] + EXPORT MDMA_Channel8_IRQHandler [WEAK] + EXPORT MDMA_Channel9_IRQHandler [WEAK] + EXPORT MDMA_Channel10_IRQHandler [WEAK] + EXPORT MDMA_Channel11_IRQHandler [WEAK] + EXPORT MDMA_Channel12_IRQHandler [WEAK] + EXPORT MDMA_Channel13_IRQHandler [WEAK] + EXPORT MDMA_Channel14_IRQHandler [WEAK] + EXPORT MDMA_Channel15_IRQHandler [WEAK] + EXPORT SDPU_IRQHandler [WEAK] + EXPORT FPU_CPU1_IRQHandler [WEAK] + EXPORT ECCMON_IRQHandler [WEAK] + EXPORT RTC_ALARM_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT I2C6_EV_IRQHandler [WEAK] + EXPORT I2C6_ER_IRQHandler [WEAK] + EXPORT I2C7_EV_IRQHandler [WEAK] + EXPORT I2C7_ER_IRQHandler [WEAK] + EXPORT I2C8_EV_IRQHandler [WEAK] + EXPORT I2C8_ER_IRQHandler [WEAK] + EXPORT I2C9_EV_IRQHandler [WEAK] + EXPORT I2C9_ER_IRQHandler [WEAK] + EXPORT I2C10_EV_IRQHandler [WEAK] + EXPORT I2C10_ER_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT I2S4_IRQHandler [WEAK] + EXPORT xSPI1_IRQHandler [WEAK] + EXPORT xSPI2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT LCD_EV_IRQHandler [WEAK] + EXPORT LCD_ER_IRQHandler [WEAK] + EXPORT DVP1_IRQHandler [WEAK] + EXPORT DVP2_IRQHandler [WEAK] + EXPORT DMAMUX2_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB1_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB1_HS_WKUP_IRQHandler [WEAK] + EXPORT USB1_HS_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_OUT_IRQHandler [WEAK] + EXPORT USB2_HS_EPx_IN_IRQHandler [WEAK] + EXPORT USB2_HS_WKUP_IRQHandler [WEAK] + EXPORT USB2_HS_IRQHandler [WEAK] + EXPORT ETH1_IRQHandler [WEAK] + EXPORT ETH1_PMT_LPI_IRQHandler [WEAK] + EXPORT ETH2_IRQHandler [WEAK] + EXPORT ETH2_PMT_LPI_IRQHandler [WEAK] + EXPORT FDCAN1_INT0_IRQHandler [WEAK] + EXPORT FDCAN2_INT0_IRQHandler [WEAK] + EXPORT FDCAN3_INT0_IRQHandler [WEAK] + EXPORT FDCAN4_INT0_IRQHandler [WEAK] + EXPORT FDCAN1_INT1_IRQHandler [WEAK] + EXPORT FDCAN2_INT1_IRQHandler [WEAK] + EXPORT FDCAN3_INT1_IRQHandler [WEAK] + EXPORT FDCAN4_INT1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPUART2_IRQHandler [WEAK] + EXPORT GPU_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT COMP1_2_IRQHandler [WEAK] + EXPORT COMP3_4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT1_IRQHandler [WEAK] + EXPORT SHRTIM1_INT2_IRQHandler [WEAK] + EXPORT SHRTIM1_INT3_IRQHandler [WEAK] + EXPORT SHRTIM1_INT4_IRQHandler [WEAK] + EXPORT SHRTIM1_INT5_IRQHandler [WEAK] + EXPORT SHRTIM1_INT6_IRQHandler [WEAK] + EXPORT SHRTIM1_INT7_IRQHandler [WEAK] + EXPORT SHRTIM1_INT8_IRQHandler [WEAK] + EXPORT SHRTIM2_INT1_IRQHandler [WEAK] + EXPORT SHRTIM2_INT2_IRQHandler [WEAK] + EXPORT SHRTIM2_INT3_IRQHandler [WEAK] + EXPORT SHRTIM2_INT4_IRQHandler [WEAK] + EXPORT SHRTIM2_INT5_IRQHandler [WEAK] + EXPORT SHRTIM2_INT6_IRQHandler [WEAK] + EXPORT SHRTIM2_INT7_IRQHandler [WEAK] + EXPORT SHRTIM2_INT8_IRQHandler [WEAK] + EXPORT FDCAN5_INT0_IRQHandler [WEAK] + EXPORT FDCAN6_INT0_IRQHandler [WEAK] + EXPORT FDCAN7_INT0_IRQHandler [WEAK] + EXPORT FDCAN8_INT0_IRQHandler [WEAK] + EXPORT FDCAN5_INT1_IRQHandler [WEAK] + EXPORT FDCAN6_INT1_IRQHandler [WEAK] + EXPORT FDCAN7_INT1_IRQHandler [WEAK] + EXPORT FDCAN8_INT1_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT LPTIM5_WKUP_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_H2P_IRQHandler [WEAK] + EXPORT JPEG_SGDMA_P2H_IRQHandler [WEAK] + EXPORT WAKEUP_IO_IRQHandler [WEAK] + EXPORT SEMA4_INT1_IRQHandler [WEAK] + EXPORT WWDG2_RST_IRQHandler [WEAK] + EXPORT OTPC_IRQHandler [WEAK] + EXPORT FEMC_IRQHandler [WEAK] + EXPORT DCMUB_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT MDMA_AHBS_ER_IRQHandler [WEAK] + EXPORT CM7_CATCH_READ_ER_IRQHandler [WEAK] + EXPORT DAC3_IRQHandler [WEAK] + EXPORT DAC4_IRQHandler [WEAK] + EXPORT EMC_IRQHandler [WEAK] + EXPORT DAC5_IRQHandler [WEAK] + EXPORT DAC6_IRQHandler [WEAK] + EXPORT ESC_OPB_IRQHandler [WEAK] + EXPORT ESC_SYNC0_IRQHandler [WEAK] + EXPORT ESC_SYNC1_IRQHandler [WEAK] + EXPORT ESC_WRP_IRQHandler [WEAK] + EXPORT ATIM1_BRK_IRQHandler [WEAK] + EXPORT ATIM1_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM1_CC_IRQHandler [WEAK] + EXPORT ATIM1_UP_IRQHandler [WEAK] + EXPORT ATIM2_BRK_IRQHandler [WEAK] + EXPORT ATIM2_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM2_CC_IRQHandler [WEAK] + EXPORT ATIM2_UP_IRQHandler [WEAK] + EXPORT ATIM3_BRK_IRQHandler [WEAK] + EXPORT ATIM3_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM3_CC_IRQHandler [WEAK] + EXPORT ATIM3_UP_IRQHandler [WEAK] + EXPORT ATIM4_BRK_IRQHandler [WEAK] + EXPORT ATIM4_TRG_COM_IRQHandler [WEAK] + EXPORT ATIM4_CC_IRQHandler [WEAK] + EXPORT ATIM4_UP_IRQHandler [WEAK] + EXPORT GTIMA1_IRQHandler [WEAK] + EXPORT GTIMA2_IRQHandler [WEAK] + EXPORT GTIMA3_IRQHandler [WEAK] + EXPORT GTIMA4_IRQHandler [WEAK] + EXPORT GTIMA5_IRQHandler [WEAK] + EXPORT GTIMA6_IRQHandler [WEAK] + EXPORT GTIMA7_IRQHandler [WEAK] + EXPORT GTIMB1_IRQHandler [WEAK] + EXPORT GTIMB2_IRQHandler [WEAK] + EXPORT GTIMB3_IRQHandler [WEAK] + EXPORT BTIM1_IRQHandler [WEAK] + EXPORT BTIM2_IRQHandler [WEAK] + EXPORT BTIM3_IRQHandler [WEAK] + EXPORT BTIM4_IRQHandler [WEAK] + EXPORT LPTIM1_WKUP_IRQHandler [WEAK] + EXPORT LPTIM2_WKUP_IRQHandler [WEAK] + EXPORT LPTIM3_WKUP_IRQHandler [WEAK] + EXPORT LPTIM4_WKUP_IRQHandler [WEAK] + EXPORT DSMU_FLT0_IRQHandler [WEAK] + EXPORT DSMU_FLT1_IRQHandler [WEAK] + EXPORT DSMU_FLT2_IRQHandler [WEAK] + EXPORT DSMU_FLT3_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT DMAMUX1_IRQHandler [WEAK] + EXPORT MMU_IRQHandler [WEAK] + EXPORT SysTick_Handler [WEAK] + +WWDG1_IRQHandler +PVD_IRQHandler +RTC_TAMPER_IRQHandler +RTC_WKUP_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +EXTI9_5_IRQHandler +EXTI15_10_IRQHandler +DMA1_Channel0_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +DMA2_Channel0_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA3_Channel0_IRQHandler +DMA3_Channel1_IRQHandler +DMA3_Channel2_IRQHandler +DMA3_Channel3_IRQHandler +DMA3_Channel4_IRQHandler +DMA3_Channel5_IRQHandler +DMA3_Channel6_IRQHandler +DMA3_Channel7_IRQHandler +MDMA_Channel0_IRQHandler +MDMA_Channel1_IRQHandler +MDMA_Channel2_IRQHandler +MDMA_Channel3_IRQHandler +MDMA_Channel4_IRQHandler +MDMA_Channel5_IRQHandler +MDMA_Channel6_IRQHandler +MDMA_Channel7_IRQHandler +MDMA_Channel8_IRQHandler +MDMA_Channel9_IRQHandler +MDMA_Channel10_IRQHandler +MDMA_Channel11_IRQHandler +MDMA_Channel12_IRQHandler +MDMA_Channel13_IRQHandler +MDMA_Channel14_IRQHandler +MDMA_Channel15_IRQHandler +SDPU_IRQHandler +FPU_CPU1_IRQHandler +ECCMON_IRQHandler +RTC_ALARM_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +I2C6_EV_IRQHandler +I2C6_ER_IRQHandler +I2C7_EV_IRQHandler +I2C7_ER_IRQHandler +I2C8_EV_IRQHandler +I2C8_ER_IRQHandler +I2C9_EV_IRQHandler +I2C9_ER_IRQHandler +I2C10_EV_IRQHandler +I2C10_ER_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +I2S3_IRQHandler +I2S4_IRQHandler +xSPI1_IRQHandler +xSPI2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SPI7_IRQHandler +LCD_EV_IRQHandler +LCD_ER_IRQHandler +DVP1_IRQHandler +DVP2_IRQHandler +DMAMUX2_IRQHandler +USB1_HS_EPx_OUT_IRQHandler +USB1_HS_EPx_IN_IRQHandler +USB1_HS_WKUP_IRQHandler +USB1_HS_IRQHandler +USB2_HS_EPx_OUT_IRQHandler +USB2_HS_EPx_IN_IRQHandler +USB2_HS_WKUP_IRQHandler +USB2_HS_IRQHandler +ETH1_IRQHandler +ETH1_PMT_LPI_IRQHandler +ETH2_IRQHandler +ETH2_PMT_LPI_IRQHandler +FDCAN1_INT0_IRQHandler +FDCAN2_INT0_IRQHandler +FDCAN3_INT0_IRQHandler +FDCAN4_INT0_IRQHandler +FDCAN1_INT1_IRQHandler +FDCAN2_INT1_IRQHandler +FDCAN3_INT1_IRQHandler +FDCAN4_INT1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +LPUART1_IRQHandler +LPUART2_IRQHandler +GPU_IRQHandler +SDMMC1_IRQHandler +SDMMC2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +ADC3_IRQHandler +COMP1_2_IRQHandler +COMP3_4_IRQHandler +SHRTIM1_INT1_IRQHandler +SHRTIM1_INT2_IRQHandler +SHRTIM1_INT3_IRQHandler +SHRTIM1_INT4_IRQHandler +SHRTIM1_INT5_IRQHandler +SHRTIM1_INT6_IRQHandler +SHRTIM1_INT7_IRQHandler +SHRTIM1_INT8_IRQHandler +SHRTIM2_INT1_IRQHandler +SHRTIM2_INT2_IRQHandler +SHRTIM2_INT3_IRQHandler +SHRTIM2_INT4_IRQHandler +SHRTIM2_INT5_IRQHandler +SHRTIM2_INT6_IRQHandler +SHRTIM2_INT7_IRQHandler +SHRTIM2_INT8_IRQHandler +FDCAN5_INT0_IRQHandler +FDCAN6_INT0_IRQHandler +FDCAN7_INT0_IRQHandler +FDCAN8_INT0_IRQHandler +FDCAN5_INT1_IRQHandler +FDCAN6_INT1_IRQHandler +FDCAN7_INT1_IRQHandler +FDCAN8_INT1_IRQHandler +DSI_IRQHandler +LPTIM5_WKUP_IRQHandler +JPEG_SGDMA_H2P_IRQHandler +JPEG_SGDMA_P2H_IRQHandler +WAKEUP_IO_IRQHandler +SEMA4_INT1_IRQHandler +WWDG2_RST_IRQHandler +OTPC_IRQHandler +FEMC_IRQHandler +DCMUB_IRQHandler +DAC1_IRQHandler +DAC2_IRQHandler +MDMA_AHBS_ER_IRQHandler +CM7_CATCH_READ_ER_IRQHandler +DAC3_IRQHandler +DAC4_IRQHandler +EMC_IRQHandler +DAC5_IRQHandler +DAC6_IRQHandler +ESC_OPB_IRQHandler +ESC_SYNC0_IRQHandler +ESC_SYNC1_IRQHandler +ESC_WRP_IRQHandler +ATIM1_BRK_IRQHandler +ATIM1_TRG_COM_IRQHandler +ATIM1_CC_IRQHandler +ATIM1_UP_IRQHandler +ATIM2_BRK_IRQHandler +ATIM2_TRG_COM_IRQHandler +ATIM2_CC_IRQHandler +ATIM2_UP_IRQHandler +ATIM3_BRK_IRQHandler +ATIM3_TRG_COM_IRQHandler +ATIM3_CC_IRQHandler +ATIM3_UP_IRQHandler +ATIM4_BRK_IRQHandler +ATIM4_TRG_COM_IRQHandler +ATIM4_CC_IRQHandler +ATIM4_UP_IRQHandler +GTIMA1_IRQHandler +GTIMA2_IRQHandler +GTIMA3_IRQHandler +GTIMA4_IRQHandler +GTIMA5_IRQHandler +GTIMA6_IRQHandler +GTIMA7_IRQHandler +GTIMB1_IRQHandler +GTIMB2_IRQHandler +GTIMB3_IRQHandler +BTIM1_IRQHandler +BTIM2_IRQHandler +BTIM3_IRQHandler +BTIM4_IRQHandler +LPTIM1_WKUP_IRQHandler +LPTIM2_WKUP_IRQHandler +LPTIM3_WKUP_IRQHandler +LPTIM4_WKUP_IRQHandler +DSMU_FLT0_IRQHandler +DSMU_FLT1_IRQHandler +DSMU_FLT2_IRQHandler +DSMU_FLT3_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +DMAMUX1_IRQHandler +MMU_IRQHandler +SysTick_Handler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_EWARM.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_EWARM.s new file mode 100644 index 0000000000..38a38fa117 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_EWARM.s @@ -0,0 +1,1535 @@ +; ********************************************************************************************************* +; Copyright (c) 2024, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. +; ************************************************************************************************************ + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA + + __iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD N32SysTick_Handler ; N32SysTick Handler + + + + ; External Interrupts + DCD WWDG1_IRQHandler ; Window1 Watchdog interrupt + DCD PVD_IRQHandler ; PVD through EXTI Line16 detection interrupt + DCD RTC_TAMPER_IRQHandler ; RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt + DCD RTC_WKUP_IRQHandler ; RTC Wakeup timer through EXTI line 19 interrupt + DCD RCC_IRQHandler ; RCC interrupt + DCD EXTI0_IRQHandler ; EXTI Line 0 interrupt + DCD EXTI1_IRQHandler ; EXTI Line 1 interrupt + DCD EXTI2_IRQHandler ; EXTI Line 2 interrupt + DCD EXTI3_IRQHandler ; EXTI Line 3 interrupt + DCD EXTI4_IRQHandler ; EXTI Line 4 interrupt + DCD EXTI9_5_IRQHandler ; EXTI Line[9:5] interrupt + DCD EXTI15_10_IRQHandler ; EXTI Line[15:10] interrupt + DCD DMA1_Channel0_IRQHandler ; DMA1 Channel 0 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD DMA2_Channel0_IRQHandler ; DMA2 Channel 0 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA3_Channel0_IRQHandler ; DMA3 Channel 0 + DCD DMA3_Channel1_IRQHandler ; DMA3 Channel 1 + DCD DMA3_Channel2_IRQHandler ; DMA3 Channel 2 + DCD DMA3_Channel3_IRQHandler ; DMA3 Channel 3 + DCD DMA3_Channel4_IRQHandler ; DMA3 Channel 4 + DCD DMA3_Channel5_IRQHandler ; DMA3 Channel 5 + DCD DMA3_Channel6_IRQHandler ; DMA3 Channel 6 + DCD DMA3_Channel7_IRQHandler ; DMA3 Channel 7 + DCD MDMA_Channel0_IRQHandler ; MDMA Channel 0 + DCD MDMA_Channel1_IRQHandler ; MDMA Channel 1 + DCD MDMA_Channel2_IRQHandler ; MDMA Channel 2 + DCD MDMA_Channel3_IRQHandler ; MDMA Channel 3 + DCD MDMA_Channel4_IRQHandler ; MDMA Channel 4 + DCD MDMA_Channel5_IRQHandler ; MDMA Channel 5 + DCD MDMA_Channel6_IRQHandler ; MDMA Channel 6 + DCD MDMA_Channel7_IRQHandler ; MDMA Channel 7 + DCD MDMA_Channel8_IRQHandler ; MDMA Channel 8 + DCD MDMA_Channel9_IRQHandler ; MDMA Channel 9 + DCD MDMA_Channel10_IRQHandler ; MDMA Channel 10 + DCD MDMA_Channel11_IRQHandler ; MDMA Channel 11 + DCD MDMA_Channel12_IRQHandler ; MDMA Channel 12 + DCD MDMA_Channel13_IRQHandler ; MDMA Channel 13 + DCD MDMA_Channel14_IRQHandler ; MDMA Channel 14 + DCD MDMA_Channel15_IRQHandler ; MDMA Channel 15 + DCD SDPU_IRQHandler ; SDPU global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_CPU1_IRQHandler ; FPU_CM7 global interrupt + DCD ECCMON_IRQHandler ; ECCMON global interrupt + DCD RTC_ALARM_IRQHandler ; RTC Alarm via EXTI17 interrupt + DCD I2C1_EV_IRQHandler ; I2C1 event interrupt + DCD I2C1_ER_IRQHandler ; I2C1 error interrupt + DCD I2C2_EV_IRQHandler ; I2C2 event interrupt + DCD I2C2_ER_IRQHandler ; I2C2 error interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event interrupt + DCD I2C3_ER_IRQHandler ; I2C3 error interrupt + DCD I2C4_EV_IRQHandler ; I2C4 event interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error interrupt + DCD I2C5_EV_IRQHandler ; I2C5 event interrupt + DCD I2C5_ER_IRQHandler ; I2C5 error interrupt + DCD I2C6_EV_IRQHandler ; I2C6 event interrupt + DCD I2C6_ER_IRQHandler ; I2C6 error interrupt + DCD I2C7_EV_IRQHandler ; I2C7 event interrupt + DCD I2C7_ER_IRQHandler ; I2C7 error interrupt + DCD I2C8_EV_IRQHandler ; I2C8 event interrupt + DCD I2C8_ER_IRQHandler ; I2C8 error interrupt + DCD I2C9_EV_IRQHandler ; I2C9 event interrupt + DCD I2C9_ER_IRQHandler ; I2C9 error interrupt + DCD I2C10_EV_IRQHandler ; I2C10 event interrupt + DCD I2C10_ER_IRQHandler ; I2C10 error interrupt + DCD I2S1_IRQHandler ; I2S1 global interrupt + DCD I2S2_IRQHandler ; I2S1 global interrupt + DCD I2S3_IRQHandler ; I2S1 global interrupt + DCD I2S4_IRQHandler ; I2S1 global interrupt + DCD 0 ; Reserved + DCD xSPI2_IRQHandler ; xSPI2 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD SPI3_IRQHandler ; SPI3 global interrupt + DCD SPI4_IRQHandler ; SPI4 global interrupt + DCD SPI5_IRQHandler ; SPI5 global interrupt + DCD SPI6_IRQHandler ; SPI6 global interrupt + DCD SPI7_IRQHandler ; SPI7 global interrupt + DCD LCD_EV_IRQHandler ; TFT LCD Controller event interrupt + DCD LCD_ER_IRQHandler ; TFT LCD Controller error interrupt + DCD DVP1_IRQHandler ; DVP1 global interrupt + DCD DVP2_IRQHandler ; DVP2 global interrupt + DCD DMAMUX2_IRQHandler ; DMAMUX2 (MDMA MUX) global interrupt + DCD USB1_HS_EPx_OUT_IRQHandler ; USB1_HS endpoint out global interrupt + DCD USB1_HS_EPx_IN_IRQHandler ; USB1_HS endpoint in global interrupt + DCD USB1_HS_WKUP_IRQHandler ; USB1_HS WKUP interrupt through EXTI line 62 + DCD USB1_HS_IRQHandler ; USB1_HS global interrupt + DCD USB2_HS_EPx_OUT_IRQHandler ; USB2_HS endpoint out global interrupt + DCD USB2_HS_EPx_IN_IRQHandler ; USB2_HS endpoint in global interrupt + DCD USB2_HS_WKUP_IRQHandler ; USB2_HS WKUP interrupt through EXTI line 63 + DCD USB2_HS_IRQHandler ; USB2_HS global interrupt + DCD ETH1_IRQHandler ; Ethernet 1 global interrupt + DCD ETH1_PMT_LPI_IRQHandler ; Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 + DCD ETH2_IRQHandler ; Ethernet 2 global interrupt + DCD ETH2_PMT_LPI_IRQHandler ; Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 + DCD FDCAN1_INT0_IRQHandler ; FDCAN1 global interrupt line 0 + DCD FDCAN2_INT0_IRQHandler ; FDCAN2 global interrupt line 0 + DCD FDCAN3_INT0_IRQHandler ; FDCAN3 global interrupt line 0 + DCD FDCAN4_INT0_IRQHandler ; FDCAN4 global interrupt line 0 + DCD FDCAN1_INT1_IRQHandler ; FDCAN1 global interrupt line 1 + DCD FDCAN2_INT1_IRQHandler ; FDCAN2 global interrupt line 1 + DCD FDCAN3_INT1_IRQHandler ; FDCAN3 global interrupt line 1 + DCD FDCAN4_INT1_IRQHandler ; FDCAN4 global interrupt line 1 + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_IRQHandler ; USART2 global interrupt + DCD USART3_IRQHandler ; USART3 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD USART5_IRQHandler ; USART5 global interrupt + DCD USART6_IRQHandler ; USART6 global interrupt + DCD USART7_IRQHandler ; USART7 global interrupt + DCD USART8_IRQHandler ; USART8 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD UART10_IRQHandler ; UART10 global interrupt + DCD UART11_IRQHandler ; UART11 global interrupt + DCD UART12_IRQHandler ; UART12 global interrupt + DCD UART13_IRQHandler ; UART13 global interrupt + DCD UART14_IRQHandler ; UART14 global interrupt + DCD UART15_IRQHandler ; UART15 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 global interrupt + wakeup through EXTI line 49 + DCD LPUART2_IRQHandler ; LPUART2 global interrupt + wakeup through EXTI line 52 + DCD GPU_IRQHandler ; GPU global interrupt + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1_IRQ + WKUP through EXTI line 24 + DCD SDMMC2_IRQHandler ; SDMMC2_IRQ + WKUP through EXTI line 25 + DCD ADC1_IRQHandler ; ADC1 global interrupt + DCD ADC2_IRQHandler ; ADC2 global interrupt + DCD ADC3_IRQHandler ; ADC3 global interrupt + DCD COMP1_2_IRQHandler ; COMP1 and COMP2 through EXTI line 20 and 21 + DCD COMP3_4_IRQHandler ; COMP3 and COMP4 through EXTI line 22 and 23 + DCD SHRTIM1_INT1_IRQHandler ; High Resolution timer 1 interrupt 1 + DCD SHRTIM1_INT2_IRQHandler ; High Resolution timer 1 interrupt 2 + DCD SHRTIM1_INT3_IRQHandler ; High Resolution timer 1 interrupt 3 + DCD SHRTIM1_INT4_IRQHandler ; High Resolution timer 1 interrupt 4 + DCD SHRTIM1_INT5_IRQHandler ; High Resolution timer 1 interrupt 5 + DCD SHRTIM1_INT6_IRQHandler ; High Resolution timer 1 interrupt 6 + DCD SHRTIM1_INT7_IRQHandler ; High Resolution timer 1 interrupt 7 + DCD SHRTIM1_INT8_IRQHandler ; High Resolution timer 1 interrupt 8 + DCD SHRTIM2_INT1_IRQHandler ; High Resolution timer 2 interrupt 1 + DCD SHRTIM2_INT2_IRQHandler ; High Resolution timer 2 interrupt 2 + DCD SHRTIM2_INT3_IRQHandler ; High Resolution timer 2 interrupt 3 + DCD SHRTIM2_INT4_IRQHandler ; High Resolution timer 2 interrupt 4 + DCD SHRTIM2_INT5_IRQHandler ; High Resolution timer 2 interrupt 5 + DCD SHRTIM2_INT6_IRQHandler ; High Resolution timer 2 interrupt 6 + DCD SHRTIM2_INT7_IRQHandler ; High Resolution timer 2 interrupt 7 + DCD SHRTIM2_INT8_IRQHandler ; High Resolution timer 2 interrupt 8 + DCD FDCAN5_INT0_IRQHandler ; FDCAN5 global interrupt line 0 + DCD FDCAN6_INT0_IRQHandler ; FDCAN6 global interrupt line 0 + DCD FDCAN7_INT0_IRQHandler ; FDCAN7 global interrupt line 0 + DCD FDCAN8_INT0_IRQHandler ; FDCAN8 global interrupt line 0 + DCD FDCAN5_INT1_IRQHandler ; FDCAN5 global interrupt line 1 + DCD FDCAN6_INT1_IRQHandler ; FDCAN6 global interrupt line 1 + DCD FDCAN7_INT1_IRQHandler ; FDCAN7 global interrupt line 1 + DCD FDCAN8_INT1_IRQHandler ; FDCAN8 global interrupt line 1 + DCD DSI_IRQHandler ; MIPI DSI Interrupt through EXTI line 87 + DCD 0 ; Reserved + DCD LPTIM5_WKUP_IRQHandler ; LPTIM5 wakeup through EXTI 86 + DCD JPEG_SGDMA_H2P_IRQHandler ; JPEG SGDMA Host to Peripheral Interrupt + DCD JPEG_SGDMA_P2H_IRQHandler ; JPEG SGDMA Peripheral to Host Interrupt + DCD WAKEUP_IO_IRQHandler ; 6 WAKEUP IOs through EXTI line 70-75 + DCD SEMA4_INT1_IRQHandler ; SEMA4 interrupt1 + DCD 0 ; Reserved + DCD WWDG2_RST_IRQHandler ; WWDG2 reset interrupt through EXTI line 82 + DCD OTPC_IRQHandler ; OTPC interrupt + DCD FEMC_IRQHandler ; FEMC interrupt + DCD DCMUB_IRQHandler ; DCMUB interrupt + DCD DAC1_IRQHandler ; DAC1 interrupt + DCD DAC2_IRQHandler ; DAC2 interrupt + DCD MDMA_AHBS_ER_IRQHandler ; MDMA HABS ERROR through EXTI line55-56 + DCD CM7_CATCH_READ_ER_IRQHandler ; CM7 Error on Cache Read through EXTI line 64-65 + DCD DAC3_IRQHandler ; DAC3 interrupt + DCD DAC4_IRQHandler ; DAC4 interrupt + DCD EMC_IRQHandler ; EMC event interrupt through EXTI line 88-89 + DCD DAC5_IRQHandler ; DAC5 interrupt + DCD DAC6_IRQHandler ; DAC6 interrupt + DCD ESC_OPB_IRQHandler ; ETHERCAT OPB Interrupt + DCD ESC_SYNC0_IRQHandler ; ETHERCAT SYNC0 Interrupt + DCD ESC_SYNC1_RQHandler ; ETHERCAT SYNC1 Interrupt + DCD ESC_WRP_IRQHandler ; ETHERCAT WRAPPER Interrupt + DCD 0 ; Reserved + DCD ATIM1_BRK_IRQHandler ; Advanced timer 1 break interrupt + DCD ATIM1_TRG_COM_IRQHandler ; Advanced timer 1 trigger and commutation interrupts + DCD ATIM1_CC_IRQHandler ; Advanced timer 1 capture/compare interrupt + DCD ATIM1_UP_IRQHandler ; Advanced timer 1 update interrupt + DCD ATIM2_BRK_IRQHandler ; Advanced timer 2 break interrupt + DCD ATIM2_TRG_COM_IRQHandler ; advanced timer 2 trigger and commutation interrupts + DCD ATIM2_CC_IRQHandler ; Advanced timer 2 capture/compare interrupt + DCD ATIM2_UP_IRQHandler ; Advanced timer 2 update interrupt + DCD ATIM3_BRK_IRQHandler ; Advanced timer 3 break interrupt + DCD ATIM3_TRG_COM_IRQHandler ; Advanced timer 3 trigger and commutation interrupts + DCD ATIM3_CC_IRQHandler ; Advanced timer 3 capture/compare interrupt + DCD ATIM3_UP_IRQHandler ; Advanced timer 3 update interrupt + DCD ATIM4_BRK_IRQHandler ; Advanced timer 4 break interrupt + DCD ATIM4_TRG_COM_IRQHandler ; Advanced timer 4 trigger and commutation interrupts + DCD ATIM4_CC_IRQHandler ; Advanced timer 4 capture/compare interrupt + DCD ATIM4_UP_IRQHandler ; Advanced timer 4 update interrupt + DCD GTIMA1_IRQHandler ; General timer A1 global interrupt + DCD GTIMA2_IRQHandler ; General timer A2 global interrupt + DCD GTIMA3_IRQHandler ; General timer A3 global interrupt + DCD GTIMA4_IRQHandler ; General timer A4 global interrupt + DCD GTIMA5_IRQHandler ; General timer A5 global interrupt + DCD GTIMA6_IRQHandler ; General timer A6 global interrupt + DCD GTIMA7_IRQHandler ; General timer A7 global interrupt + DCD GTIMB1_IRQHandler ; General timer B1 global interrupt + DCD GTIMB2_IRQHandler ; General timer B2 global interrupt + DCD GTIMB3_IRQHandler ; General timer B3 global interrupt + DCD BTIM1_IRQHandler ; Base timer 1 global interrupt + DCD BTIM2_IRQHandler ; Base timer 2 global interrupt + DCD BTIM3_IRQHandler ; Base timer 3 global interrupt + DCD BTIM4_IRQHandler ; Base timer 4 global interrupt + DCD LPTIM1_WKUP_IRQHandler ; LPTIM1 wakeup interrupt + DCD LPTIM2_WKUP_IRQHandler ; LPTIM2 wakeup interrupt + DCD LPTIM3_WKUP_IRQHandler ; LPTIM3 wakeup interrupt + DCD LPTIM4_WKUP_IRQHandler ; LPTIM4 wakeup interrupt + DCD DSMU_FLT0_IRQHandler ; DSMU Filter interrupt 0 + DCD DSMU_FLT1_IRQHandler ; DSMU Filter interrupt 1 + DCD DSMU_FLT2_IRQHandler ; DSMU Filter interrupt 2 + DCD DSMU_FLT3_IRQHandler ; DSMU Filter interrupt 3 + DCD FMAC_IRQHandler ; FMAC global interrupt + DCD CORDIC_IRQHandler ; Cordic global interrupt + DCD DMAMUX1_IRQHandler ; DMAMUX1 interrupt + DCD MMU_IRQHandler ; MMU interrupt + DCD SysTick_Handler ; SysTick Handler + ;need check to user manual of exti chapter + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK N32SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +N32SysTick_Handler + B N32SysTick_Handler + + PUBWEAK WWDG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG1_IRQHandler + B WWDG1_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMPER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_TAMPER_IRQHandler + B RTC_TAMPER_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK DMA1_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel0_IRQHandler + B DMA1_Channel0_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK DMA2_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel0_IRQHandler + B DMA2_Channel0_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA3_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel0_IRQHandler + B DMA3_Channel0_IRQHandler + + PUBWEAK DMA3_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel1_IRQHandler + B DMA3_Channel1_IRQHandler + + PUBWEAK DMA3_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel2_IRQHandler + B DMA3_Channel2_IRQHandler + + PUBWEAK DMA3_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel3_IRQHandler + B DMA3_Channel3_IRQHandler + + PUBWEAK DMA3_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel4_IRQHandler + B DMA3_Channel4_IRQHandler + + PUBWEAK DMA3_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel5_IRQHandler + B DMA3_Channel5_IRQHandler + + PUBWEAK DMA3_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel6_IRQHandler + B DMA3_Channel6_IRQHandler + + PUBWEAK DMA3_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA3_Channel7_IRQHandler + B DMA3_Channel7_IRQHandler + + PUBWEAK MDMA_Channel0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel0_IRQHandler + B MDMA_Channel0_IRQHandler + + PUBWEAK MDMA_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel1_IRQHandler + B MDMA_Channel1_IRQHandler + + PUBWEAK MDMA_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel2_IRQHandler + B MDMA_Channel2_IRQHandler + + PUBWEAK MDMA_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel3_IRQHandler + B MDMA_Channel3_IRQHandler + + PUBWEAK MDMA_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel4_IRQHandler + B MDMA_Channel4_IRQHandler + + PUBWEAK MDMA_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel5_IRQHandler + B MDMA_Channel5_IRQHandler + + PUBWEAK MDMA_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel6_IRQHandler + B MDMA_Channel6_IRQHandler + + PUBWEAK MDMA_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel7_IRQHandler + B MDMA_Channel7_IRQHandler + + PUBWEAK MDMA_Channel8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel8_IRQHandler + B MDMA_Channel8_IRQHandler + + PUBWEAK MDMA_Channel9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel9_IRQHandler + B MDMA_Channel9_IRQHandler + + PUBWEAK MDMA_Channel10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel10_IRQHandler + B MDMA_Channel10_IRQHandler + + PUBWEAK MDMA_Channel11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel11_IRQHandler + B MDMA_Channel11_IRQHandler + + PUBWEAK MDMA_Channel12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel12_IRQHandler + B MDMA_Channel12_IRQHandler + + PUBWEAK MDMA_Channel13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel13_IRQHandler + B MDMA_Channel13_IRQHandler + + PUBWEAK MDMA_Channel14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel14_IRQHandler + B MDMA_Channel14_IRQHandler + + PUBWEAK MDMA_Channel15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_Channel15_IRQHandler + B MDMA_Channel15_IRQHandler + + PUBWEAK SDPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDPU_IRQHandler + B SDPU_IRQHandler + + PUBWEAK FPU_CPU1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_CPU1_IRQHandler + B FPU_CPU1_IRQHandler + + PUBWEAK ECCMON_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECCMON_IRQHandler + B ECCMON_IRQHandler + + PUBWEAK RTC_ALARM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_ALARM_IRQHandler + B RTC_ALARM_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK I2C6_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_EV_IRQHandler + B I2C6_EV_IRQHandler + + PUBWEAK I2C6_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C6_ER_IRQHandler + B I2C6_ER_IRQHandler + + PUBWEAK I2C7_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_EV_IRQHandler + B I2C7_EV_IRQHandler + + PUBWEAK I2C7_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C7_ER_IRQHandler + B I2C7_ER_IRQHandler + + PUBWEAK I2C8_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_EV_IRQHandler + B I2C8_EV_IRQHandler + + PUBWEAK I2C8_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C8_ER_IRQHandler + B I2C8_ER_IRQHandler + + PUBWEAK I2C9_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_EV_IRQHandler + B I2C9_EV_IRQHandler + + PUBWEAK I2C9_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C9_ER_IRQHandler + B I2C9_ER_IRQHandler + + PUBWEAK I2C10_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_EV_IRQHandler + B I2C10_EV_IRQHandler + + PUBWEAK I2C10_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C10_ER_IRQHandler + B I2C10_ER_IRQHandler + + PUBWEAK I2S1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S1_IRQHandler + B I2S1_IRQHandler + + PUBWEAK I2S2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S2_IRQHandler + B I2S2_IRQHandler + + PUBWEAK I2S3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S3_IRQHandler + B I2S3_IRQHandler + + PUBWEAK I2S4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S4_IRQHandler + B I2S4_IRQHandler + + PUBWEAK xSPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI1_IRQHandler + B xSPI1_IRQHandler + + PUBWEAK xSPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +xSPI2_IRQHandler + B xSPI2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SPI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI7_IRQHandler + B SPI7_IRQHandler + + PUBWEAK LCD_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_EV_IRQHandler + B LCD_EV_IRQHandler + + PUBWEAK LCD_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_ER_IRQHandler + B LCD_ER_IRQHandler + + PUBWEAK DVP1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP1_IRQHandler + B DVP1_IRQHandler + + PUBWEAK DVP2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DVP2_IRQHandler + B DVP2_IRQHandler + + PUBWEAK DMAMUX2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX2_IRQHandler + B DMAMUX2_IRQHandler + + PUBWEAK USB1_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_OUT_IRQHandler + B USB1_HS_EPx_OUT_IRQHandler + + PUBWEAK USB1_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_EPx_IN_IRQHandler + B USB1_HS_EPx_IN_IRQHandler + + PUBWEAK USB1_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_WKUP_IRQHandler + B USB1_HS_WKUP_IRQHandler + + PUBWEAK USB1_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB1_HS_IRQHandler + B USB1_HS_IRQHandler + + PUBWEAK USB2_HS_EPx_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_OUT_IRQHandler + B USB2_HS_EPx_OUT_IRQHandler + + PUBWEAK USB2_HS_EPx_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_EPx_IN_IRQHandler + B USB2_HS_EPx_IN_IRQHandler + + PUBWEAK USB2_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_WKUP_IRQHandler + B USB2_HS_WKUP_IRQHandler + + PUBWEAK USB2_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB2_HS_IRQHandler + B USB2_HS_IRQHandler + + PUBWEAK ETH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_IRQHandler + B ETH1_IRQHandler + + PUBWEAK ETH1_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH1_PMT_LPI_IRQHandler + B ETH1_PMT_LPI_IRQHandler + + PUBWEAK ETH2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_IRQHandler + B ETH2_IRQHandler + + PUBWEAK ETH2_PMT_LPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH2_PMT_LPI_IRQHandler + B ETH2_PMT_LPI_IRQHandler + + PUBWEAK FDCAN1_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT0_IRQHandler + B FDCAN1_INT0_IRQHandler + + PUBWEAK FDCAN2_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT0_IRQHandler + B FDCAN2_INT0_IRQHandler + + PUBWEAK FDCAN3_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT0_IRQHandler + B FDCAN3_INT0_IRQHandler + + PUBWEAK FDCAN4_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT0_IRQHandler + B FDCAN4_INT0_IRQHandler + + PUBWEAK FDCAN1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN1_INT1_IRQHandler + B FDCAN1_INT1_IRQHandler + + PUBWEAK FDCAN2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN2_INT1_IRQHandler + B FDCAN2_INT1_IRQHandler + + PUBWEAK FDCAN3_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN3_INT1_IRQHandler + B FDCAN3_INT1_IRQHandler + + PUBWEAK FDCAN4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN4_INT1_IRQHandler + B FDCAN4_INT1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK USART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART5_IRQHandler + B USART5_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK USART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART7_IRQHandler + B USART7_IRQHandler + + PUBWEAK USART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART8_IRQHandler + B USART8_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK UART10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART10_IRQHandler + B UART10_IRQHandler + + PUBWEAK UART11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART11_IRQHandler + B UART11_IRQHandler + + PUBWEAK UART12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART12_IRQHandler + B UART12_IRQHandler + + PUBWEAK UART13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART13_IRQHandler + B UART13_IRQHandler + + PUBWEAK UART14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART14_IRQHandler + B UART14_IRQHandler + + PUBWEAK UART15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART15_IRQHandler + B UART15_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK LPUART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPUART2_IRQHandler + B LPUART2_IRQHandler + + PUBWEAK GPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPU_IRQHandler + B GPU_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_IRQHandler + B ADC2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK COMP1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP1_2_IRQHandler + B COMP1_2_IRQHandler + + PUBWEAK COMP3_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP3_4_IRQHandler + B COMP3_4_IRQHandler + + PUBWEAK SHRTIM1_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT1_IRQHandler + B SHRTIM1_INT1_IRQHandler + + PUBWEAK SHRTIM1_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT2_IRQHandler + B SHRTIM1_INT2_IRQHandler + + PUBWEAK SHRTIM1_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT3_IRQHandler + B SHRTIM1_INT3_IRQHandler + + PUBWEAK SHRTIM1_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT4_IRQHandler + B SHRTIM1_INT4_IRQHandler + + PUBWEAK SHRTIM1_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT5_IRQHandler + B SHRTIM1_INT5_IRQHandler + + PUBWEAK SHRTIM1_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT6_IRQHandler + B SHRTIM1_INT6_IRQHandler + + PUBWEAK SHRTIM1_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT7_IRQHandler + B SHRTIM1_INT7_IRQHandler + + PUBWEAK SHRTIM1_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM1_INT8_IRQHandler + B SHRTIM1_INT8_IRQHandler + + PUBWEAK SHRTIM2_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT1_IRQHandler + B SHRTIM2_INT1_IRQHandler + + PUBWEAK SHRTIM2_INT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT2_IRQHandler + B SHRTIM2_INT2_IRQHandler + + PUBWEAK SHRTIM2_INT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT3_IRQHandler + B SHRTIM2_INT3_IRQHandler + + PUBWEAK SHRTIM2_INT4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT4_IRQHandler + B SHRTIM2_INT4_IRQHandler + + PUBWEAK SHRTIM2_INT5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT5_IRQHandler + B SHRTIM2_INT5_IRQHandler + + PUBWEAK SHRTIM2_INT6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT6_IRQHandler + B SHRTIM2_INT6_IRQHandler + + PUBWEAK SHRTIM2_INT7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT7_IRQHandler + B SHRTIM2_INT7_IRQHandler + + PUBWEAK SHRTIM2_INT8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SHRTIM2_INT8_IRQHandler + B SHRTIM2_INT8_IRQHandler + + PUBWEAK FDCAN5_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT0_IRQHandler + B FDCAN5_INT0_IRQHandler + + PUBWEAK FDCAN6_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT0_IRQHandler + B FDCAN6_INT0_IRQHandler + + PUBWEAK FDCAN7_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT0_IRQHandler + B FDCAN7_INT0_IRQHandler + + PUBWEAK FDCAN8_INT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT0_IRQHandler + B FDCAN8_INT0_IRQHandler + + PUBWEAK FDCAN5_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN5_INT1_IRQHandler + B FDCAN5_INT1_IRQHandler + + PUBWEAK FDCAN6_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN6_INT1_IRQHandler + B FDCAN6_INT1_IRQHandler + + PUBWEAK FDCAN7_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN7_INT1_IRQHandler + B FDCAN7_INT1_IRQHandler + + PUBWEAK FDCAN8_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FDCAN8_INT1_IRQHandler + B FDCAN8_INT1_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK LPTIM5_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM5_WKUP_IRQHandler + B LPTIM5_WKUP_IRQHandler + + PUBWEAK JPEG_SGDMA_H2P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_H2P_IRQHandler + B JPEG_SGDMA_H2P_IRQHandler + + PUBWEAK JPEG_SGDMA_P2H_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +JPEG_SGDMA_P2H_IRQHandler + B JPEG_SGDMA_P2H_IRQHandler + + PUBWEAK WAKEUP_IO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WAKEUP_IO_IRQHandler + B WAKEUP_IO_IRQHandler + + PUBWEAK SEMA4_INT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_INT1_IRQHandler + B SEMA4_INT1_IRQHandler + + PUBWEAK WWDG2_RST_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG2_RST_IRQHandler + B WWDG2_RST_IRQHandler + + PUBWEAK OTPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTPC_IRQHandler + B OTPC_IRQHandler + + PUBWEAK FEMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FEMC_IRQHandler + B FEMC_IRQHandler + + PUBWEAK DCMUB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMUB_IRQHandler + B DCMUB_IRQHandler + + PUBWEAK DAC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC1_IRQHandler + B DAC1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK MDMA_AHBS_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MDMA_AHBS_ER_IRQHandler + B MDMA_AHBS_ER_IRQHandler + + PUBWEAK CM7_CATCH_READ_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CM7_CATCH_READ_ER_IRQHandler + B CM7_CATCH_READ_ER_IRQHandler + + PUBWEAK DAC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC3_IRQHandler + B DAC3_IRQHandler + + PUBWEAK DAC4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC4_IRQHandler + B DAC4_IRQHandler + + PUBWEAK EMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMC_IRQHandler + B EMC_IRQHandler + + PUBWEAK DAC5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC5_IRQHandler + B DAC5_IRQHandler + + PUBWEAK DAC6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC6_IRQHandler + B DAC6_IRQHandler + + PUBWEAK ESC_OPB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_OPB_IRQHandler + B ESC_OPB_IRQHandler + + PUBWEAK ESC_SYNC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC0_IRQHandler + B ESC_SYNC0_IRQHandler + + PUBWEAK ESC_SYNC1_RQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_SYNC1_RQHandler + B ESC_SYNC1_RQHandler + + PUBWEAK ESC_WRP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ESC_WRP_IRQHandler + B ESC_WRP_IRQHandler + + PUBWEAK ATIM1_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_BRK_IRQHandler + B ATIM1_BRK_IRQHandler + + PUBWEAK ATIM1_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_TRG_COM_IRQHandler + B ATIM1_TRG_COM_IRQHandler + + PUBWEAK ATIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_CC_IRQHandler + B ATIM1_CC_IRQHandler + + PUBWEAK ATIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM1_UP_IRQHandler + B ATIM1_UP_IRQHandler + + PUBWEAK ATIM2_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_BRK_IRQHandler + B ATIM2_BRK_IRQHandler + + PUBWEAK ATIM2_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_TRG_COM_IRQHandler + B ATIM2_TRG_COM_IRQHandler + + PUBWEAK ATIM2_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_CC_IRQHandler + B ATIM2_CC_IRQHandler + + PUBWEAK ATIM2_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM2_UP_IRQHandler + B ATIM2_UP_IRQHandler + + PUBWEAK ATIM3_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_BRK_IRQHandler + B ATIM3_BRK_IRQHandler + + PUBWEAK ATIM3_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_TRG_COM_IRQHandler + B ATIM3_TRG_COM_IRQHandler + + PUBWEAK ATIM3_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_CC_IRQHandler + B ATIM3_CC_IRQHandler + + PUBWEAK ATIM3_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM3_UP_IRQHandler + B ATIM3_UP_IRQHandler + + PUBWEAK ATIM4_BRK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_BRK_IRQHandler + B ATIM4_BRK_IRQHandler + + PUBWEAK ATIM4_TRG_COM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_TRG_COM_IRQHandler + B ATIM4_TRG_COM_IRQHandler + + PUBWEAK ATIM4_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_CC_IRQHandler + B ATIM4_CC_IRQHandler + + PUBWEAK ATIM4_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ATIM4_UP_IRQHandler + B ATIM4_UP_IRQHandler + + PUBWEAK GTIMA1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA1_IRQHandler + B GTIMA1_IRQHandler + + PUBWEAK GTIMA2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA2_IRQHandler + B GTIMA2_IRQHandler + + PUBWEAK GTIMA3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA3_IRQHandler + B GTIMA3_IRQHandler + + PUBWEAK GTIMA4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA4_IRQHandler + B GTIMA4_IRQHandler + + PUBWEAK GTIMA5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA5_IRQHandler + B GTIMA5_IRQHandler + + PUBWEAK GTIMA6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA6_IRQHandler + B GTIMA6_IRQHandler + + PUBWEAK GTIMA7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMA7_IRQHandler + B GTIMA7_IRQHandler + + PUBWEAK GTIMB1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB1_IRQHandler + B GTIMB1_IRQHandler + + PUBWEAK GTIMB2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB2_IRQHandler + B GTIMB2_IRQHandler + + PUBWEAK GTIMB3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GTIMB3_IRQHandler + B GTIMB3_IRQHandler + + PUBWEAK BTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM1_IRQHandler + B BTIM1_IRQHandler + + PUBWEAK BTIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM2_IRQHandler + B BTIM2_IRQHandler + + PUBWEAK BTIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM3_IRQHandler + B BTIM3_IRQHandler + + PUBWEAK BTIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIM4_IRQHandler + B BTIM4_IRQHandler + + PUBWEAK LPTIM1_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_WKUP_IRQHandler + B LPTIM1_WKUP_IRQHandler + + PUBWEAK LPTIM2_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM2_WKUP_IRQHandler + B LPTIM2_WKUP_IRQHandler + + PUBWEAK LPTIM3_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM3_WKUP_IRQHandler + B LPTIM3_WKUP_IRQHandler + + PUBWEAK LPTIM4_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM4_WKUP_IRQHandler + B LPTIM4_WKUP_IRQHandler + + PUBWEAK DSMU_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT0_IRQHandler + B DSMU_FLT0_IRQHandler + + PUBWEAK DSMU_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT1_IRQHandler + B DSMU_FLT1_IRQHandler + + PUBWEAK DSMU_FLT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT2_IRQHandler + B DSMU_FLT2_IRQHandler + + PUBWEAK DSMU_FLT3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSMU_FLT3_IRQHandler + B DSMU_FLT3_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK DMAMUX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMAMUX1_IRQHandler + B DMAMUX1_IRQHandler + + PUBWEAK MMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MMU_IRQHandler + B MMU_IRQHandler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + END + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_gcc.s b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_gcc.s new file mode 100644 index 0000000000..6ecb108e55 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/startup/startup_n32h78x_cm7_gcc.s @@ -0,0 +1,1108 @@ +/********************************************************************************************************* + Copyright (c) 2024, Nations Technologies Inc. + + All rights reserved. + + This software is the exclusive property of Nations Technologies Inc. (Hereinafter + referred to as NATIONS). This software, and the product of NATIONS described herein + (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties + of the People's Republic of China and other applicable jurisdictions worldwide. + + NATIONS does not grant any license under its patents, copyrights, trademarks, or other + intellectual property rights. Names and brands of third party may be mentioned or referred + thereto (if any) for identification purposes only. + + NATIONS reserves the right to make changes, corrections, enhancements, modifications, and + improvements to this software at any time without notice. Please contact NATIONS and obtain + the latest version of this software before placing orders. + + Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes + no responsibility for the accuracy and reliability of this software. + + It is the responsibility of the user of this software to properly design, program, and test + the functionality and safety of any application made of this information and any resulting product. + In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or + consequential damages arising in any way out of the use of this software or the Product. + + NATIONS Products are neither intended nor warranted for usage in systems or equipment, any + malfunction or failure of which may cause loss of human life, bodily injury or severe property + damage. Such applications are deemed, "Insecure Usage". + + All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS + harmless from and against all claims, costs, damages, and other liabilities, arising from or related + to any customer's Insecure Usage. + + Any express or implied warranty with regard to this software or the Product, including,but not + limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement + are disclaimed to the fullest extent permitted by law. + + Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe + or otherwise distribute this software for any purposes, in whole or in part. + + NATIONS products and technologies shall not be used for or incorporated into any products or systems + whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. + User shall comply with any applicable export control laws and regulations promulgated and administered by + the governments of any countries asserting jurisdiction over the parties or transactions. + ************************************************************************************************************/ + + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** +\*fun This is the code that gets called when the processor receives an +\* unexpected interrupt. This simply enters an infinite loop, preserving +\* the system state for examination by a debugger. +**/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/** +\* The minimal vector table for a Cortex M0. Note that the proper constructs +\* must be placed on this to ensure that it ends up at physical address 0x00000000. +**/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word WWDG1_IRQHandler /* Window1 Watchdog interrupt */ + .word PVD_IRQHandler /* PVD through EXTI Line16 detection interrupt */ + .word RTC_TAMPER_IRQHandler /* RTC Tamper_Timestamp_Overflow or LSE-CSS through EXTI Line18 interrupt */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup timer through EXTI line 19 interrupt */ + .word RCC_IRQHandler /* RCC interrupt */ + .word EXTI0_IRQHandler /* EXTI Line 0 interrupt */ + .word EXTI1_IRQHandler /* EXTI Line 1 interrupt */ + .word EXTI2_IRQHandler /* EXTI Line 2 interrupt */ + .word EXTI3_IRQHandler /* EXTI Line 3 interrupt */ + .word EXTI4_IRQHandler /* EXTI Line 4 interrupt */ + .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupt */ + .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupt */ + .word DMA1_Channel0_IRQHandler /* DMA1 Channel 0 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word DMA2_Channel0_IRQHandler /* DMA2 Channel 0 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA3_Channel0_IRQHandler /* DMA3 Channel 0 */ + .word DMA3_Channel1_IRQHandler /* DMA3 Channel 1 */ + .word DMA3_Channel2_IRQHandler /* DMA3 Channel 2 */ + .word DMA3_Channel3_IRQHandler /* DMA3 Channel 3 */ + .word DMA3_Channel4_IRQHandler /* DMA3 Channel 4 */ + .word DMA3_Channel5_IRQHandler /* DMA3 Channel 5 */ + .word DMA3_Channel6_IRQHandler /* DMA3 Channel 6 */ + .word DMA3_Channel7_IRQHandler /* DMA3 Channel 7 */ + .word MDMA_Channel0_IRQHandler /* MDMA Channel 0 */ + .word MDMA_Channel1_IRQHandler /* MDMA Channel 1 */ + .word MDMA_Channel2_IRQHandler /* MDMA Channel 2 */ + .word MDMA_Channel3_IRQHandler /* MDMA Channel 3 */ + .word MDMA_Channel4_IRQHandler /* MDMA Channel 4 */ + .word MDMA_Channel5_IRQHandler /* MDMA Channel 5 */ + .word MDMA_Channel6_IRQHandler /* MDMA Channel 6 */ + .word MDMA_Channel7_IRQHandler /* MDMA Channel 7 */ + .word MDMA_Channel8_IRQHandler /* MDMA Channel 8 */ + .word MDMA_Channel9_IRQHandler /* MDMA Channel 9 */ + .word MDMA_Channel10_IRQHandler /* MDMA Channel 10 */ + .word MDMA_Channel11_IRQHandler /* MDMA Channel 11 */ + .word MDMA_Channel12_IRQHandler /* MDMA Channel 12 */ + .word MDMA_Channel13_IRQHandler /* MDMA Channel 13 */ + .word MDMA_Channel14_IRQHandler /* MDMA Channel 14 */ + .word MDMA_Channel15_IRQHandler /* MDMA Channel 15 */ + .word SDPU_IRQHandler /* SDPU global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_CPU1_IRQHandler /* FPU_CM7 global interrupt */ + .word ECCMON_IRQHandler /* ECCMON global interrupt */ + .word RTC_ALARM_IRQHandler /* RTC Alarm via EXTI17 interrupt */ + .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ + .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ + .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ + .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ + .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ + .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ + .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ + .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 event interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 error interrupt */ + .word I2C6_EV_IRQHandler /* I2C6 event interrupt */ + .word I2C6_ER_IRQHandler /* I2C6 error interrupt */ + .word I2C7_EV_IRQHandler /* I2C7 event interrupt */ + .word I2C7_ER_IRQHandler /* I2C7 error interrupt */ + .word I2C8_EV_IRQHandler /* I2C8 event interrupt */ + .word I2C8_ER_IRQHandler /* I2C8 error interrupt */ + .word I2C9_EV_IRQHandler /* I2C9 event interrupt */ + .word I2C9_ER_IRQHandler /* I2C9 error interrupt */ + .word I2C10_EV_IRQHandler /* I2C10 event interrupt */ + .word I2C10_ER_IRQHandler /* I2C10 error interrupt */ + .word I2S1_IRQHandler /* I2S1 global interrupt */ + .word I2S2_IRQHandler /* I2S1 global interrupt */ + .word I2S3_IRQHandler /* I2S1 global interrupt */ + .word I2S4_IRQHandler /* I2S1 global interrupt */ + .word xSPI1_IRQHandler /* xSPI1 global interrupt */ + .word xSPI2_IRQHandler /* xSPI1 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word SPI3_IRQHandler /* SPI3 global interrupt */ + .word SPI4_IRQHandler /* SPI4 global interrupt */ + .word SPI5_IRQHandler /* SPI5 global interrupt */ + .word SPI6_IRQHandler /* SPI6 global interrupt */ + .word SPI7_IRQHandler /* SPI7 global interrupt */ + .word LCD_EV_IRQHandler /* TFT LCD Controller event interrupt */ + .word LCD_ER_IRQHandler /* TFT LCD Controller error interrupt */ + .word DVP1_IRQHandler /* DVP1 global interrupt */ + .word DVP2_IRQHandler /* DVP2 global interrupt */ + .word DMAMUX2_IRQHandler /* DMAMUX2 (MDMA MUX) global interrupt */ + .word USB1_HS_EPx_OUT_IRQHandler /* USB1_HS endpoint out global interrupt */ + .word USB1_HS_EPx_IN_IRQHandler /* USB1_HS endpoint in global interrupt */ + .word USB1_HS_WKUP_IRQHandler /* USB1_HS WKUP interrupt through EXTI line 62 */ + .word USB1_HS_IRQHandler /* USB1_HS global interrupt */ + .word USB2_HS_EPx_OUT_IRQHandler /* USB2_HS endpoint out global interrupt */ + .word USB2_HS_EPx_IN_IRQHandler /* USB2_HS endpoint in global interrupt */ + .word USB2_HS_WKUP_IRQHandler /* USB2_HS WKUP interrupt through EXTI line 63 */ + .word USB2_HS_IRQHandler /* USB2_HS global interrupt */ + .word ETH1_IRQHandler /* Ethernet 1 global interrupt */ + .word ETH1_PMT_LPI_IRQHandler /* Ethernet 1 PMT wakeup interrupt and LPI interrupt through EXTI line 83 */ + .word ETH2_IRQHandler /* Ethernet 2 global interrupt */ + .word ETH2_PMT_LPI_IRQHandler /* Ethernet 2 PMT wakeup interrupt and LPI interrupt through EXTI line 84 */ + .word FDCAN1_INT0_IRQHandler /* FDCAN1 global interrupt line 0 */ + .word FDCAN2_INT0_IRQHandler /* FDCAN2 global interrupt line 0 */ + .word FDCAN3_INT0_IRQHandler /* FDCAN3 global interrupt line 0 */ + .word FDCAN4_INT0_IRQHandler /* FDCAN4 global interrupt line 0 */ + .word FDCAN1_INT1_IRQHandler /* FDCAN1 global interrupt line 1 */ + .word FDCAN2_INT1_IRQHandler /* FDCAN2 global interrupt line 1 */ + .word FDCAN3_INT1_IRQHandler /* FDCAN3 global interrupt line 1 */ + .word FDCAN4_INT1_IRQHandler /* FDCAN4 global interrupt line 1 */ + .word USART1_IRQHandler /* USART1 global interrupt */ + .word USART2_IRQHandler /* USART2 global interrupt */ + .word USART3_IRQHandler /* USART3 global interrupt */ + .word USART4_IRQHandler /* USART4 global interrupt */ + .word USART5_IRQHandler /* USART5 global interrupt */ + .word USART6_IRQHandler /* USART6 global interrupt */ + .word USART7_IRQHandler /* USART7 global interrupt */ + .word USART8_IRQHandler /* USART8 global interrupt */ + .word UART9_IRQHandler /* UART9 global interrupt */ + .word UART10_IRQHandler /* UART10 global interrupt */ + .word UART11_IRQHandler /* UART11 global interrupt */ + .word UART12_IRQHandler /* UART12 global interrupt */ + .word UART13_IRQHandler /* UART13 global interrupt */ + .word UART14_IRQHandler /* UART14 global interrupt */ + .word UART15_IRQHandler /* UART15 global interrupt */ + .word LPUART1_IRQHandler /* LPUART1 global interrupt + wakeup through EXTI line 49 */ + .word LPUART2_IRQHandler /* LPUART2 global interrupt + wakeup through EXTI line 52 */ + .word GPU_IRQHandler /* GPU global interrupt */ + .word 0 /* Reserved */ + .word SDMMC1_IRQHandler /* SDMMC1_IRQ + WKUP through EXTI line 24 */ + .word SDMMC2_IRQHandler /* SDMMC2_IRQ + WKUP through EXTI line 25 */ + .word ADC1_IRQHandler /* ADC1 global interrupt */ + .word ADC2_IRQHandler /* ADC2 global interrupt */ + .word ADC3_IRQHandler /* ADC3 global interrupt */ + .word COMP1_2_IRQHandler /* COMP1 and COMP2 through EXTI line 20 and 21 */ + .word COMP3_4_IRQHandler /* COMP3 and COMP4 through EXTI line 22 and 23 */ + .word SHRTIM1_INT1_IRQHandler /* High Resolution timer 1 interrupt 1 */ + .word SHRTIM1_INT2_IRQHandler /* High Resolution timer 1 interrupt 2 */ + .word SHRTIM1_INT3_IRQHandler /* High Resolution timer 1 interrupt 3 */ + .word SHRTIM1_INT4_IRQHandler /* High Resolution timer 1 interrupt 4 */ + .word SHRTIM1_INT5_IRQHandler /* High Resolution timer 1 interrupt 5 */ + .word SHRTIM1_INT6_IRQHandler /* High Resolution timer 1 interrupt 6 */ + .word SHRTIM1_INT7_IRQHandler /* High Resolution timer 1 interrupt 7 */ + .word SHRTIM1_INT8_IRQHandler /* High Resolution timer 1 interrupt 8 */ + .word SHRTIM2_INT1_IRQHandler /* High Resolution timer 2 interrupt 1 */ + .word SHRTIM2_INT2_IRQHandler /* High Resolution timer 2 interrupt 2 */ + .word SHRTIM2_INT3_IRQHandler /* High Resolution timer 2 interrupt 3 */ + .word SHRTIM2_INT4_IRQHandler /* High Resolution timer 2 interrupt 4 */ + .word SHRTIM2_INT5_IRQHandler /* High Resolution timer 2 interrupt 5 */ + .word SHRTIM2_INT6_IRQHandler /* High Resolution timer 2 interrupt 6 */ + .word SHRTIM2_INT7_IRQHandler /* High Resolution timer 2 interrupt 7 */ + .word SHRTIM2_INT8_IRQHandler /* High Resolution timer 2 interrupt 8 */ + .word FDCAN5_INT0_IRQHandler /* FDCAN5 global interrupt line 0 */ + .word FDCAN6_INT0_IRQHandler /* FDCAN6 global interrupt line 0 */ + .word FDCAN7_INT0_IRQHandler /* FDCAN7 global interrupt line 0 */ + .word FDCAN8_INT0_IRQHandler /* FDCAN8 global interrupt line 0 */ + .word FDCAN5_INT1_IRQHandler /* FDCAN5 global interrupt line 1 */ + .word FDCAN6_INT1_IRQHandler /* FDCAN6 global interrupt line 1 */ + .word FDCAN7_INT1_IRQHandler /* FDCAN7 global interrupt line 1 */ + .word FDCAN8_INT1_IRQHandler /* FDCAN8 global interrupt line 1 */ + .word DSI_IRQHandler /* MIPI DSI Interrupt through EXTI line 87 */ + .word 0 /* Reserved */ + .word LPTIM5_WKUP_IRQHandler /* LPTIM5 wakeup through EXTI 86 */ + .word JPEG_SGDMA_H2P_IRQHandler /* JPEG SGDMA Host to Peripheral Interrupt */ + .word JPEG_SGDMA_P2H_IRQHandler /* JPEG SGDMA Peripheral to Host Interrupt */ + .word WAKEUP_IO_IRQHandler /* 6 WAKEUP IOs through EXTI line 70-75 */ + .word SEMA4_INT1_IRQHandler /* SEMA4 interrupt1 */ + .word 0 /* Reserved */ + .word WWDG2_RST_IRQHandler /* WWDG2 reset interrupt through EXTI line 82 */ + .word OTPC_IRQHandler /* OTPC interrupt */ + .word FEMC_IRQHandler /* FEMC interrupt */ + .word DCMUB_IRQHandler /* DCMUB interrupt */ + .word DAC1_IRQHandler /* DAC1 interrupt */ + .word DAC2_IRQHandler /* DAC2 interrupt */ + .word MDMA_AHBS_ER_IRQHandler /* MDMA HABS ERROR through EXTI line55-56 */ + .word CM7_CATCH_READ_ER_IRQHandler /* CM7 Error on Cache Read through EXTI line 64-65 */ + .word DAC3_IRQHandler /* DAC3 interrupt */ + .word DAC4_IRQHandler /* DAC4 interrupt */ + .word EMC_IRQHandler /* EMC event interrupt through EXTI line 88-89 */ + .word DAC5_IRQHandler /* DAC5 interrupt */ + .word DAC6_IRQHandler /* DAC6 interrupt */ + .word ESC_OPB_IRQHandler /* ETHERCAT OPB Interrupt */ + .word ESC_SYNC0_IRQHandler /* ETHERCAT SYNC0 Interrupt */ + .word ESC_SYNC1_IRQHandler /* ETHERCAT SYNC1 Interrupt */ + .word ESC_WRP_IRQHandler /* ETHERCAT WRAPPER Interrupt */ + .word 0 /* Reserved */ + .word ATIM1_BRK_IRQHandler /* Advanced timer 1 break interrupt */ + .word ATIM1_TRG_COM_IRQHandler /* Advanced timer 1 trigger and commutation interrupts */ + .word ATIM1_CC_IRQHandler /* Advanced timer 1 capture/compare interrupt */ + .word ATIM1_UP_IRQHandler /* Advanced timer 1 update interrupt */ + .word ATIM2_BRK_IRQHandler /* Advanced timer 2 break interrupt */ + .word ATIM2_TRG_COM_IRQHandler /* advanced timer 2 trigger and commutation interrupts */ + .word ATIM2_CC_IRQHandler /* Advanced timer 2 capture/compare interrupt */ + .word ATIM2_UP_IRQHandler /* Advanced timer 2 update interrupt */ + .word ATIM3_BRK_IRQHandler /* Advanced timer 3 break interrupt */ + .word ATIM3_TRG_COM_IRQHandler /* Advanced timer 3 trigger and commutation interrupts */ + .word ATIM3_CC_IRQHandler /* Advanced timer 3 capture/compare interrupt */ + .word ATIM3_UP_IRQHandler /* Advanced timer 3 update interrupt */ + .word ATIM4_BRK_IRQHandler /* Advanced timer 4 break interrupt */ + .word ATIM4_TRG_COM_IRQHandler /* Advanced timer 4 trigger and commutation interrupts */ + .word ATIM4_CC_IRQHandler /* Advanced timer 4 capture/compare interrupt */ + .word ATIM4_UP_IRQHandler /* Advanced timer 4 update interrupt */ + .word GTIMA1_IRQHandler /* General timer A1 global interrupt */ + .word GTIMA2_IRQHandler /* General timer A2 global interrupt */ + .word GTIMA3_IRQHandler /* General timer A3 global interrupt */ + .word GTIMA4_IRQHandler /* General timer A4 global interrupt */ + .word GTIMA5_IRQHandler /* General timer A5 global interrupt */ + .word GTIMA6_IRQHandler /* General timer A6 global interrupt */ + .word GTIMA7_IRQHandler /* General timer A7 global interrupt */ + .word GTIMB1_IRQHandler /* General timer B1 global interrupt */ + .word GTIMB2_IRQHandler /* General timer B2 global interrupt */ + .word GTIMB3_IRQHandler /* General timer B3 global interrupt */ + .word BTIM1_IRQHandler /* Base timer 1 global interrupt */ + .word BTIM2_IRQHandler /* Base timer 2 global interrupt */ + .word BTIM3_IRQHandler /* Base timer 3 global interrupt */ + .word BTIM4_IRQHandler /* Base timer 4 global interrupt */ + .word LPTIM1_WKUP_IRQHandler /* LPTIM1 wakeup interrupt */ + .word LPTIM2_WKUP_IRQHandler /* LPTIM2 wakeup interrupt */ + .word LPTIM3_WKUP_IRQHandler /* LPTIM3 wakeup interrupt */ + .word LPTIM4_WKUP_IRQHandler /* LPTIM4 wakeup interrupt */ + .word DSMU_FLT0_IRQHandler /* DSMU Filter interrupt 0 */ + .word DSMU_FLT1_IRQHandler /* DSMU Filter interrupt 1 */ + .word DSMU_FLT2_IRQHandler /* DSMU Filter interrupt 2 */ + .word DSMU_FLT3_IRQHandler /* DSMU Filter interrupt 3 */ + .word FMAC_IRQHandler /* FMAC global interrupt */ + .word CORDIC_IRQHandler /* Cordic global interrupt */ + .word DMAMUX1_IRQHandler /* DMAMUX1 interrupt */ + .word MMU_IRQHandler /* MMU interrupt */ + /* need check to user manual of exti chapter */ + +/** +\* Provide weak aliases for each Exception handler to the Default_Handler. +\* As they are weak aliases, any function with the same name will override +\* this definition. +**/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG1_IRQHandler + .thumb_set WWDG1_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMPER_IRQHandler + .thumb_set RTC_TAMPER_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak DMA1_Channel0_IRQHandler + .thumb_set DMA1_Channel0_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel0_IRQHandler + .thumb_set DMA2_Channel0_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA3_Channel0_IRQHandler + .thumb_set DMA3_Channel0_IRQHandler,Default_Handler + + .weak DMA3_Channel1_IRQHandler + .thumb_set DMA3_Channel1_IRQHandler,Default_Handler + + .weak DMA3_Channel2_IRQHandler + .thumb_set DMA3_Channel2_IRQHandler,Default_Handler + + .weak DMA3_Channel3_IRQHandler + .thumb_set DMA3_Channel3_IRQHandler,Default_Handler + + .weak DMA3_Channel4_IRQHandler + .thumb_set DMA3_Channel4_IRQHandler,Default_Handler + + .weak DMA3_Channel5_IRQHandler + .thumb_set DMA3_Channel5_IRQHandler,Default_Handler + + .weak DMA3_Channel6_IRQHandler + .thumb_set DMA3_Channel6_IRQHandler,Default_Handler + + .weak DMA3_Channel7_IRQHandler + .thumb_set DMA3_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel0_IRQHandler + .thumb_set MDMA_Channel0_IRQHandler,Default_Handler + + .weak MDMA_Channel1_IRQHandler + .thumb_set MDMA_Channel1_IRQHandler,Default_Handler + + .weak MDMA_Channel2_IRQHandler + .thumb_set MDMA_Channel2_IRQHandler,Default_Handler + + .weak MDMA_Channel3_IRQHandler + .thumb_set MDMA_Channel3_IRQHandler,Default_Handler + + .weak MDMA_Channel4_IRQHandler + .thumb_set MDMA_Channel4_IRQHandler,Default_Handler + + .weak MDMA_Channel5_IRQHandler + .thumb_set MDMA_Channel5_IRQHandler,Default_Handler + + .weak MDMA_Channel6_IRQHandler + .thumb_set MDMA_Channel6_IRQHandler,Default_Handler + + .weak MDMA_Channel7_IRQHandler + .thumb_set MDMA_Channel7_IRQHandler,Default_Handler + + .weak MDMA_Channel8_IRQHandler + .thumb_set MDMA_Channel8_IRQHandler,Default_Handler + + .weak MDMA_Channel9_IRQHandler + .thumb_set MDMA_Channel9_IRQHandler,Default_Handler + + .weak MDMA_Channel10_IRQHandler + .thumb_set MDMA_Channel10_IRQHandler,Default_Handler + + .weak MDMA_Channel11_IRQHandler + .thumb_set MDMA_Channel11_IRQHandler,Default_Handler + + .weak MDMA_Channel12_IRQHandler + .thumb_set MDMA_Channel12_IRQHandler,Default_Handler + + .weak MDMA_Channel13_IRQHandler + .thumb_set MDMA_Channel13_IRQHandler,Default_Handler + + .weak MDMA_Channel14_IRQHandler + .thumb_set MDMA_Channel14_IRQHandler,Default_Handler + + .weak MDMA_Channel15_IRQHandler + .thumb_set MDMA_Channel15_IRQHandler,Default_Handler + + .weak SDPU_IRQHandler + .thumb_set SDPU_IRQHandler,Default_Handler + + .weak FPU_CPU1_IRQHandler + .thumb_set FPU_CPU1_IRQHandler,Default_Handler + + .weak ECCMON_IRQHandler + .thumb_set ECCMON_IRQHandler,Default_Handler + + .weak RTC_ALARM_IRQHandler + .thumb_set RTC_ALARM_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak I2C6_EV_IRQHandler + .thumb_set I2C6_EV_IRQHandler,Default_Handler + + .weak I2C6_ER_IRQHandler + .thumb_set I2C6_ER_IRQHandler,Default_Handler + + .weak I2C7_EV_IRQHandler + .thumb_set I2C7_EV_IRQHandler,Default_Handler + + .weak I2C7_ER_IRQHandler + .thumb_set I2C7_ER_IRQHandler,Default_Handler + + .weak I2C8_EV_IRQHandler + .thumb_set I2C8_EV_IRQHandler,Default_Handler + + .weak I2C8_ER_IRQHandler + .thumb_set I2C8_ER_IRQHandler,Default_Handler + + .weak I2C9_EV_IRQHandler + .thumb_set I2C9_EV_IRQHandler,Default_Handler + + .weak I2C9_ER_IRQHandler + .thumb_set I2C9_ER_IRQHandler,Default_Handler + + .weak I2C10_EV_IRQHandler + .thumb_set I2C10_EV_IRQHandler,Default_Handler + + .weak I2C10_ER_IRQHandler + .thumb_set I2C10_ER_IRQHandler,Default_Handler + + .weak I2S1_IRQHandler + .thumb_set I2S1_IRQHandler,Default_Handler + + .weak I2S2_IRQHandler + .thumb_set I2S2_IRQHandler,Default_Handler + + .weak I2S3_IRQHandler + .thumb_set I2S3_IRQHandler,Default_Handler + + .weak I2S4_IRQHandler + .thumb_set I2S4_IRQHandler,Default_Handler + + .weak xSPI1_IRQHandler + .thumb_set xSPI1_IRQHandler,Default_Handler + + .weak xSPI2_IRQHandler + .thumb_set xSPI2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SPI7_IRQHandler + .thumb_set SPI7_IRQHandler,Default_Handler + + .weak LCD_EV_IRQHandler + .thumb_set LCD_EV_IRQHandler,Default_Handler + + .weak LCD_ER_IRQHandler + .thumb_set LCD_ER_IRQHandler,Default_Handler + + .weak DVP1_IRQHandler + .thumb_set DVP1_IRQHandler,Default_Handler + + .weak DVP2_IRQHandler + .thumb_set DVP2_IRQHandler,Default_Handler + + .weak DMAMUX2_IRQHandler + .thumb_set DMAMUX2_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_OUT_IRQHandler + .thumb_set USB1_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB1_HS_EPx_IN_IRQHandler + .thumb_set USB1_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB1_HS_WKUP_IRQHandler + .thumb_set USB1_HS_WKUP_IRQHandler,Default_Handler + + .weak USB1_HS_IRQHandler + .thumb_set USB1_HS_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_OUT_IRQHandler + .thumb_set USB2_HS_EPx_OUT_IRQHandler,Default_Handler + + .weak USB2_HS_EPx_IN_IRQHandler + .thumb_set USB2_HS_EPx_IN_IRQHandler,Default_Handler + + .weak USB2_HS_WKUP_IRQHandler + .thumb_set USB2_HS_WKUP_IRQHandler,Default_Handler + + .weak USB2_HS_IRQHandler + .thumb_set USB2_HS_IRQHandler,Default_Handler + + .weak ETH1_IRQHandler + .thumb_set ETH1_IRQHandler,Default_Handler + + .weak ETH1_PMT_LPI_IRQHandler + .thumb_set ETH1_PMT_LPI_IRQHandler,Default_Handler + + .weak ETH2_IRQHandler + .thumb_set ETH2_IRQHandler,Default_Handler + + .weak ETH2_PMT_LPI_IRQHandler + .thumb_set ETH2_PMT_LPI_IRQHandler,Default_Handler + + .weak FDCAN1_INT0_IRQHandler + .thumb_set FDCAN1_INT0_IRQHandler,Default_Handler + + .weak FDCAN2_INT0_IRQHandler + .thumb_set FDCAN2_INT0_IRQHandler,Default_Handler + + .weak FDCAN3_INT0_IRQHandler + .thumb_set FDCAN3_INT0_IRQHandler,Default_Handler + + .weak FDCAN4_INT0_IRQHandler + .thumb_set FDCAN4_INT0_IRQHandler,Default_Handler + + .weak FDCAN1_INT1_IRQHandler + .thumb_set FDCAN1_INT1_IRQHandler,Default_Handler + + .weak FDCAN2_INT1_IRQHandler + .thumb_set FDCAN2_INT1_IRQHandler,Default_Handler + + .weak FDCAN3_INT1_IRQHandler + .thumb_set FDCAN3_INT1_IRQHandler,Default_Handler + + .weak FDCAN4_INT1_IRQHandler + .thumb_set FDCAN4_INT1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak UART10_IRQHandler + .thumb_set UART10_IRQHandler,Default_Handler + + .weak UART11_IRQHandler + .thumb_set UART11_IRQHandler,Default_Handler + + .weak UART12_IRQHandler + .thumb_set UART12_IRQHandler,Default_Handler + + .weak UART13_IRQHandler + .thumb_set UART13_IRQHandler,Default_Handler + + .weak UART14_IRQHandler + .thumb_set UART14_IRQHandler,Default_Handler + + .weak UART15_IRQHandler + .thumb_set UART15_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPUART2_IRQHandler + .thumb_set LPUART2_IRQHandler,Default_Handler + + .weak GPU_IRQHandler + .thumb_set GPU_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler,Default_Handler + + .weak COMP3_4_IRQHandler + .thumb_set COMP3_4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT1_IRQHandler + .thumb_set SHRTIM1_INT1_IRQHandler,Default_Handler + + .weak SHRTIM1_INT2_IRQHandler + .thumb_set SHRTIM1_INT2_IRQHandler,Default_Handler + + .weak SHRTIM1_INT3_IRQHandler + .thumb_set SHRTIM1_INT3_IRQHandler,Default_Handler + + .weak SHRTIM1_INT4_IRQHandler + .thumb_set SHRTIM1_INT4_IRQHandler,Default_Handler + + .weak SHRTIM1_INT5_IRQHandler + .thumb_set SHRTIM1_INT5_IRQHandler,Default_Handler + + .weak SHRTIM1_INT6_IRQHandler + .thumb_set SHRTIM1_INT6_IRQHandler,Default_Handler + + .weak SHRTIM1_INT7_IRQHandler + .thumb_set SHRTIM1_INT7_IRQHandler,Default_Handler + + .weak SHRTIM1_INT8_IRQHandler + .thumb_set SHRTIM1_INT8_IRQHandler,Default_Handler + + .weak SHRTIM2_INT1_IRQHandler + .thumb_set SHRTIM2_INT1_IRQHandler,Default_Handler + + .weak SHRTIM2_INT2_IRQHandler + .thumb_set SHRTIM2_INT2_IRQHandler,Default_Handler + + .weak SHRTIM2_INT3_IRQHandler + .thumb_set SHRTIM2_INT3_IRQHandler,Default_Handler + + .weak SHRTIM2_INT4_IRQHandler + .thumb_set SHRTIM2_INT4_IRQHandler,Default_Handler + + .weak SHRTIM2_INT5_IRQHandler + .thumb_set SHRTIM2_INT5_IRQHandler,Default_Handler + + .weak SHRTIM2_INT6_IRQHandler + .thumb_set SHRTIM2_INT6_IRQHandler,Default_Handler + + .weak SHRTIM2_INT7_IRQHandler + .thumb_set SHRTIM2_INT7_IRQHandler,Default_Handler + + .weak SHRTIM2_INT8_IRQHandler + .thumb_set SHRTIM2_INT8_IRQHandler,Default_Handler + + .weak FDCAN5_INT0_IRQHandler + .thumb_set FDCAN5_INT0_IRQHandler,Default_Handler + + .weak FDCAN6_INT0_IRQHandler + .thumb_set FDCAN6_INT0_IRQHandler,Default_Handler + + .weak FDCAN7_INT0_IRQHandler + .thumb_set FDCAN7_INT0_IRQHandler,Default_Handler + + .weak FDCAN8_INT0_IRQHandler + .thumb_set FDCAN8_INT0_IRQHandler,Default_Handler + + .weak FDCAN5_INT1_IRQHandler + .thumb_set FDCAN5_INT1_IRQHandler,Default_Handler + + .weak FDCAN6_INT1_IRQHandler + .thumb_set FDCAN6_INT1_IRQHandler,Default_Handler + + .weak FDCAN7_INT1_IRQHandler + .thumb_set FDCAN7_INT1_IRQHandler,Default_Handler + + .weak FDCAN8_INT1_IRQHandler + .thumb_set FDCAN8_INT1_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak LPTIM5_WKUP_IRQHandler + .thumb_set LPTIM5_WKUP_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_H2P_IRQHandler + .thumb_set JPEG_SGDMA_H2P_IRQHandler,Default_Handler + + .weak JPEG_SGDMA_P2H_IRQHandler + .thumb_set JPEG_SGDMA_P2H_IRQHandler,Default_Handler + + .weak WAKEUP_IO_IRQHandler + .thumb_set WAKEUP_IO_IRQHandler,Default_Handler + + .weak SEMA4_INT1_IRQHandler + .thumb_set SEMA4_INT1_IRQHandler,Default_Handler + + .weak WWDG2_RST_IRQHandler + .thumb_set WWDG2_RST_IRQHandler,Default_Handler + + .weak OTPC_IRQHandler + .thumb_set OTPC_IRQHandler,Default_Handler + + .weak FEMC_IRQHandler + .thumb_set FEMC_IRQHandler,Default_Handler + + .weak DCMUB_IRQHandler + .thumb_set DCMUB_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak DAC2_IRQHandler + .thumb_set DAC2_IRQHandler,Default_Handler + + .weak MDMA_AHBS_ER_IRQHandler + .thumb_set MDMA_AHBS_ER_IRQHandler,Default_Handler + + .weak CM7_CATCH_READ_ER_IRQHandler + .thumb_set CM7_CATCH_READ_ER_IRQHandler,Default_Handler + + .weak DAC3_IRQHandler + .thumb_set DAC3_IRQHandler,Default_Handler + + .weak DAC4_IRQHandler + .thumb_set DAC4_IRQHandler,Default_Handler + + .weak EMC_IRQHandler + .thumb_set EMC_IRQHandler,Default_Handler + + .weak DAC5_IRQHandler + .thumb_set DAC5_IRQHandler,Default_Handler + + .weak DAC6_IRQHandler + .thumb_set DAC6_IRQHandler,Default_Handler + + .weak ESC_OPB_IRQHandler + .thumb_set ESC_OPB_IRQHandler,Default_Handler + + .weak ESC_SYNC0_IRQHandler + .thumb_set ESC_SYNC0_IRQHandler,Default_Handler + + .weak ESC_SYNC1_IRQHandler + .thumb_set ESC_SYNC1_IRQHandler,Default_Handler + + .weak ESC_WRP_IRQHandler + .thumb_set ESC_WRP_IRQHandler,Default_Handler + + .weak ATIM1_BRK_IRQHandler + .thumb_set ATIM1_BRK_IRQHandler,Default_Handler + + .weak ATIM1_TRG_COM_IRQHandler + .thumb_set ATIM1_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM1_CC_IRQHandler + .thumb_set ATIM1_CC_IRQHandler,Default_Handler + + .weak ATIM1_UP_IRQHandler + .thumb_set ATIM1_UP_IRQHandler,Default_Handler + + .weak ATIM2_BRK_IRQHandler + .thumb_set ATIM2_BRK_IRQHandler,Default_Handler + + .weak ATIM2_TRG_COM_IRQHandler + .thumb_set ATIM2_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM2_CC_IRQHandler + .thumb_set ATIM2_CC_IRQHandler,Default_Handler + + .weak ATIM2_UP_IRQHandler + .thumb_set ATIM2_UP_IRQHandler,Default_Handler + + .weak ATIM3_BRK_IRQHandler + .thumb_set ATIM3_BRK_IRQHandler,Default_Handler + + .weak ATIM3_TRG_COM_IRQHandler + .thumb_set ATIM3_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM3_CC_IRQHandler + .thumb_set ATIM3_CC_IRQHandler,Default_Handler + + .weak ATIM3_UP_IRQHandler + .thumb_set ATIM3_UP_IRQHandler,Default_Handler + + .weak ATIM4_BRK_IRQHandler + .thumb_set ATIM4_BRK_IRQHandler,Default_Handler + + .weak ATIM4_TRG_COM_IRQHandler + .thumb_set ATIM4_TRG_COM_IRQHandler,Default_Handler + + .weak ATIM4_CC_IRQHandler + .thumb_set ATIM4_CC_IRQHandler,Default_Handler + + .weak ATIM4_UP_IRQHandler + .thumb_set ATIM4_UP_IRQHandler,Default_Handler + + .weak GTIMA1_IRQHandler + .thumb_set GTIMA1_IRQHandler,Default_Handler + + .weak GTIMA2_IRQHandler + .thumb_set GTIMA2_IRQHandler,Default_Handler + + .weak GTIMA3_IRQHandler + .thumb_set GTIMA3_IRQHandler,Default_Handler + + .weak GTIMA4_IRQHandler + .thumb_set GTIMA4_IRQHandler,Default_Handler + + .weak GTIMA5_IRQHandler + .thumb_set GTIMA5_IRQHandler,Default_Handler + + .weak GTIMA6_IRQHandler + .thumb_set GTIMA6_IRQHandler,Default_Handler + + .weak GTIMA7_IRQHandler + .thumb_set GTIMA7_IRQHandler,Default_Handler + + .weak GTIMB1_IRQHandler + .thumb_set GTIMB1_IRQHandler,Default_Handler + + .weak GTIMB2_IRQHandler + .thumb_set GTIMB2_IRQHandler,Default_Handler + + .weak GTIMB3_IRQHandler + .thumb_set GTIMB3_IRQHandler,Default_Handler + + .weak BTIM1_IRQHandler + .thumb_set BTIM1_IRQHandler,Default_Handler + + .weak BTIM2_IRQHandler + .thumb_set BTIM2_IRQHandler,Default_Handler + + .weak BTIM3_IRQHandler + .thumb_set BTIM3_IRQHandler,Default_Handler + + .weak BTIM4_IRQHandler + .thumb_set BTIM4_IRQHandler,Default_Handler + + .weak LPTIM1_WKUP_IRQHandler + .thumb_set LPTIM1_WKUP_IRQHandler,Default_Handler + + .weak LPTIM2_WKUP_IRQHandler + .thumb_set LPTIM2_WKUP_IRQHandler,Default_Handler + + .weak LPTIM3_WKUP_IRQHandler + .thumb_set LPTIM3_WKUP_IRQHandler,Default_Handler + + .weak LPTIM4_WKUP_IRQHandler + .thumb_set LPTIM4_WKUP_IRQHandler,Default_Handler + + .weak DSMU_FLT0_IRQHandler + .thumb_set DSMU_FLT0_IRQHandler,Default_Handler + + .weak DSMU_FLT1_IRQHandler + .thumb_set DSMU_FLT1_IRQHandler,Default_Handler + + .weak DSMU_FLT2_IRQHandler + .thumb_set DSMU_FLT2_IRQHandler,Default_Handler + + .weak DSMU_FLT3_IRQHandler + .thumb_set DSMU_FLT3_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak DMAMUX1_IRQHandler + .thumb_set DMAMUX1_IRQHandler,Default_Handler + + .weak MMU_IRQHandler + .thumb_set MMU_IRQHandler,Default_Handler diff --git "a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/\346\226\260\347\211\210keil_pack\345\214\205\350\243\205\344\270\215\344\270\212\347\232\204\347\202\271\346\210\221.txt" "b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/\346\226\260\347\211\210keil_pack\345\214\205\350\243\205\344\270\215\344\270\212\347\232\204\347\202\271\346\210\221.txt" new file mode 100644 index 0000000000..0e68390e48 --- /dev/null +++ "b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/\346\226\260\347\211\210keil_pack\345\214\205\350\243\205\344\270\215\344\270\212\347\232\204\347\202\271\346\210\221.txt" @@ -0,0 +1,4 @@ +由于keil更改了pack包的安装方式。导致pack安装失败。 +参考解决方法： +鼠标右键，打开方式中，更改一下安装包的执行文件，以此执行： +*/Keil_v5/UV4/PackUnzip.exe \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig new file mode 100644 index 0000000000..0ac364d0bf --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig @@ -0,0 +1,165 @@ +menu "Hardware Drivers Config" + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 64 + default 22 + + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 64 + default 23 + endif + + menuconfig BSP_USING_HARD_I2C + bool "Enable Hard I2C BUS" + default n + select RT_USING_I2C + if BSP_USING_HARD_I2C + config BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS" + default n + + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + depends on BSP_USING_HARD_I2C1 + default n + + config BSP_I2C1_TX_USING_DMA + bool "Enable i2c1 TX DMA" + depends on BSP_USING_HARD_I2C1 + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + + source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/SConscript b/bsp/n32/n32hxxx/n32h760zil7-stb/board/SConscript new file mode 100644 index 0000000000..5b2e3b94e6 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/SConscript @@ -0,0 +1,93 @@ +from building import * +import os + +# Import environment variables +Import('env') + +# Defined groups +groups = [] +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') +path = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) +# Append Drivers group to groups +groups.append(group) + +# add std-library file +path = [os.path.join(cwd, 'Cube_Config/Driver/CMSIS/core')] +path += [os.path.join(cwd, 'Cube_Config/Driver/CMSIS/device')] +path += [os.path.join(cwd, 'Cube_Config/Driver/n32h76x_78x_std_periph_driver/inc')] + +# You can select chips from the list above +CPPDEFINES = ['N32H76x', 'CORE_CM7', 'USING_TCM', 'USE_STDPERIPH_DRIVER'] + +# You can select chip's startup file +if rtconfig.PLATFORM in ['gcc', 'llvm-arm']: + src = [os.path.join(cwd, 'Cube_Config', 'startup', 'startup_n32h73x_76x_gcc.s')] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src = [os.path.join(cwd, 'Cube_Config', 'startup', 'startup_n32h73x_76x.s')] +elif rtconfig.PLATFORM in ['iccarm']: + src = [os.path.join(cwd, 'Cube_Config', 'startup', 'startup_n32h73x_76x_EWARM.s')] + +src_path = os.path.join(cwd, 'Cube_Config/Driver') + +# You can select library file +src += [ +os.path.join(src_path, 'CMSIS/device/system_n32h76x_78x.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/misc.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_gpio.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_mmu.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_dma.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_dmamux.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_pwr.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_rcc.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_dbg.c'), +os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_exti.c'), +] + +if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']): + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_usart.c')] + +if GetDepend(['RT_USING_I2C']): + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_i2c.c')] + +if GetDepend(['RT_USING_SPI']): + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_spi.c')] + +if GetDepend(['RT_USING_ADC']): + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_adc.c')] + +if GetDepend(['RT_USING_RTC']): + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_rtc.c')] + +if GetDepend(['RT_USING_WDT']): + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_iwdg.c')] + src += [os.path.join(src_path, 'n32h76x_78x_std_periph_driver/src/n32h76x_78x_wwdg.c')] + +# Defined Libraries group +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +# Append Libraries group to groups +groups.append(group) + +# Defined Drivers group sorece file +src = [os.path.join(cwd, 'Cube_Config', 'USER', 'src', 'n32h76x_78x_cfg.c')] +# Defined Drivers group header file path +path = [os.path.join(cwd, 'Cube_Config/USER/inc')] +# Defined Drivers group +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) +# Append Drivers group to groups +groups.append(group) + +# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')): +# group = group + SConscript(os.path.join("ports", 'SConscript')) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('groups') diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c new file mode 100644 index 0000000000..ccf54527af --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#include "board.h" + + +/** + * @brief System_Initialize + * @param None + * @retval None + */ +void System_Initialize(void) +{ + /* Copy Vert Table to ITCM */ + CopyVectTable(FLASH_BASE, ITCM_BASE, VECT_SIZE); + + /* Initialize system clock and enable Peripheral clock */ + RCC_Configuration(); + +#ifdef N32H78x + /* Enable Cortex-M4 boot*/ + RCC_EnableCM4(0x15080000); +#endif + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + + /* Config Peripheral GPIO */ + GPIO_Configuration(); +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h new file mode 100644 index 0000000000..beff185963 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/board.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-24 ox-horse first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "n32h76x_78x.h" +#include "n32h76x_78x_gpio.h" +#include "n32h76x_78x_exti.h" +#include "n32h76x_78x_usart.h" +#include "n32h76x_78x_dbg.h" +#include "n32h76x_78x_pwr.h" +#include "n32h76x_78x_cfg.h" +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define N32_FLASH_START_ADRESS ((uint32_t)0x15000000) +#define N32_FLASH_SIZE ((2 *1024 * 1024) - (128 * 1024)) +#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE)) + +#define N32_SRAM_SIZE (128) +#define N32_SRAM_END (0x24000000 + N32_SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_AXI_SRAM$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_AXI_SRAM$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END N32_SRAM_END + +void System_Initialize(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.icf b/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.icf new file mode 100644 index 0000000000..00962f0740 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.icf @@ -0,0 +1,63 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x15000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x15000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x151DFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x0; +define symbol __ICFEDIT_region_IROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x24000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2401FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region EROM_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__] + | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__] + | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; +define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] + | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] + | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in IROM_region { readonly }; +place in EROM_region { readonly section application_specific_ro }; +place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; +place in ERAM_region { readwrite section application_specific_rw }; \ No newline at end of file diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.lds b/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.lds new file mode 100644 index 0000000000..ce67ebfbf8 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for N32H76x with GNU ld + * SummerGift 2026.1.24 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x15000000, LENGTH = 1920k /* 1920KB flash */ + RAM (rw) : ORIGIN = 0x24000000, LENGTH = 128k /* 128K AXI_SRAM */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.sct b/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.sct new file mode 100644 index 0000000000..73bdb11713 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/linker_scripts/link.sct @@ -0,0 +1,25 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; 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board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_usart.c + n32h76x_78x_usart.c + 0 + 0 + + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx new file mode 100644 index 0000000000..6c5944875d --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx @@ -0,0 +1,2150 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
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+ 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startup_n32h73x_76x.s + 2 + board\Cube_Config\startup\startup_n32h73x_76x.s + + + system_n32h76x_78x.c + 1 + board\Cube_Config\Driver\CMSIS\device\system_n32h76x_78x.c + + + misc.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\misc.c + + + n32h76x_78x_gpio.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_gpio.c + + + n32h76x_78x_mmu.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_mmu.c + + + n32h76x_78x_dma.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_dma.c + + + n32h76x_78x_dmamux.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_dmamux.c + + + n32h76x_78x_pwr.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_pwr.c + + + n32h76x_78x_rcc.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_rcc.c + + + n32h76x_78x_dbg.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_dbg.c + + + n32h76x_78x_exti.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_exti.c + + + n32h76x_78x_usart.c + 1 + board\Cube_Config\Driver\n32h76x_78x_std_periph_driver\src\n32h76x_78x_usart.c + + + + + + + + + + + + + +     diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.h b/bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.h new file mode 100644 index 0000000000..ffa1cb5879 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.h @@ -0,0 +1,424 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_N32H760ZIL7 + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 32 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 512 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_CACHE +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 512 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_N32 +#define SOC_SERIES_N32H7xx + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.py b/bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.py new file mode 100644 index 0000000000..15ddd3158a --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/rtconfig.py @@ -0,0 +1,185 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M7 ' + CFLAGS += ' -mcpu=cortex-M7 -mfpu=fpv4-sp-d16 ' + CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu VFPv5_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32g4frml-stb/project.uvoptx b/bsp/n32/n32hxxx/n32h760zil7-stb/template.uvoptx similarity index 89% rename from bsp/n32/n32g4frml-stb/project.uvoptx rename to bsp/n32/n32hxxx/n32h760zil7-stb/template.uvoptx index 19f6087d18..d4cb02535c 100644 --- a/bsp/n32/n32g4frml-stb/project.uvoptx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/template.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -120,12 +120,12 @@ 0 CMSIS_AGDI - -X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0N32G4FR.FLM -FS08000000 -FL080000 -FP0($$Device:N32G4FRMEL7$Flash\N32G4FR.FLM) + -X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD24000000 -FC8000 -FN1 -FF0N32H76x_2048.FLM -FS015000000 -FL01E0000 -FP0($$Device:N32H760xIx7$Flash\N32H76x_2048.FLM) 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G4FR -FL080000 -FS08000000 -FP0($$Device:N32G4FRMEL7$Flash\N32G4FR.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC8000 -FD24000000 -FF0N32H76x_2048 -FL01E0000 -FS015000000 -FP0($$Device:N32H760xIx7$Flash\N32H76x_2048.FLM) @@ -171,15 +171,14 @@ + + 1 + 1 + 0 + 2 + 10000000 + - - ::CMSIS - 0 - 0 - 0 - 1 - - diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/template.uvprojx b/bsp/n32/n32hxxx/n32h760zil7-stb/template.uvprojx new file mode 100644 index 0000000000..6fdc74b753 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + N32H760xIx7 + Nationstech + Nationstech.N32H76x_DFP.1.1.0 + http://www.keil.com/pack/ + IRAM(0x24000000,0x20000) IROM(0x15000000,0x1E0000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD24000000 -FC8000 -FN1 -FF0N32H76x_2048 -FS015000000 -FL01E0000 -FP0($$Device:N32H760xIx7$Flash\N32H76x_2048.FLM)) + 0 + $$Device:N32H760xIx7$firmware\CMSIS\device\N32H76x.h + + + + + + + + + + $$Device:N32H760xIx7$svd\N32H76x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rt-thread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x24000000 + 0x20000 + + + 1 + 0x15000000 + 0x1e0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x15000000 + 0x1e0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x24000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + +     diff --git a/bsp/n32/n32hxxx/tools/sdk_dist.py b/bsp/n32/n32hxxx/tools/sdk_dist.py new file mode 100644 index 0000000000..a45e959c93 --- /dev/null +++ b/bsp/n32/n32hxxx/tools/sdk_dist.py @@ -0,0 +1,23 @@ +import os +import sys +import shutil + +cwd_path = os.getcwd() +sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools')) + + +# BSP dist function +def dist_do_building(BSP_ROOT, dist_dir): + from mkdist import bsp_copy_files + import rtconfig + + print("=> copy n32 bsp library") + library_dir = os.path.join(dist_dir, 'libraries') + library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries') + if rtconfig.BSP_LIBRARY_TYPE is not None: + bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), + os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE)) + + print("=> copy bsp drivers") + bsp_copy_files(os.path.join(library_path, 'N32_Drivers'), os.path.join(library_dir, 'N32_Drivers')) + shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) diff --git a/bsp/n32/n32l40xcl-stb/Kconfig b/bsp/n32/n32l40xcl-stb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32l40xcl-stb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32l40xcl-stb/project.uvoptx b/bsp/n32/n32l40xcl-stb/project.uvoptx deleted file mode 100644 index 12d7f7bb31..0000000000 --- a/bsp/n32/n32l40xcl-stb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
    ### uVision Project, (C) Keil Software
    - - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L40x -FL020000 -FS08000000 -FP0($$Device:N32L406CB$Flash\N32L40x.FLM) - - - 0 - CMSIS_AGDI - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L40x -FL020000 -FS08000000 -FP0($$Device:N32L406CB$Flash\N32L40x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - -     diff --git a/bsp/n32/n32l40xcl-stb/rtconfig.py b/bsp/n32/n32l40xcl-stb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32l40xcl-stb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l436-evb/Kconfig b/bsp/n32/n32l436-evb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32l436-evb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32l436-evb/project.uvoptx b/bsp/n32/n32l436-evb/project.uvoptx deleted file mode 100644 index ea197b3c15..0000000000 --- a/bsp/n32/n32l436-evb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
    ### uVision Project, (C) Keil Software
    - - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) - - - 0 - CMSIS_AGDI - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - -     diff --git a/bsp/n32/n32l436-evb/rtconfig.py b/bsp/n32/n32l436-evb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32l436-evb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l43xml-stb/Kconfig b/bsp/n32/n32l43xml-stb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32l43xml-stb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32l43xml-stb/project.uvoptx b/bsp/n32/n32l43xml-stb/project.uvoptx deleted file mode 100644 index ea197b3c15..0000000000 --- a/bsp/n32/n32l43xml-stb/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
    ### uVision Project, (C) Keil Software
    - - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) - - - 0 - CMSIS_AGDI - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32L43x -FL020000 -FS08000000 -FP0($$Device:N32L436MB$Flash\N32L43x.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - -     diff --git a/bsp/n32/n32l43xml-stb/rtconfig.py b/bsp/n32/n32l43xml-stb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32l43xml-stb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32l43xrl-stb/Kconfig b/bsp/n32/n32l43xrl-stb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32l43xrl-stb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32l43xrl-stb/rtconfig.py b/bsp/n32/n32l43xrl-stb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32l43xrl-stb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/n32/n32wb45xl-evb/Kconfig b/bsp/n32/n32wb45xl-evb/Kconfig deleted file mode 100644 index 73238d3a13..0000000000 --- a/bsp/n32/n32wb45xl-evb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -mainmenu "RT-Thread Configuration" - -BSP_DIR := . - -RTT_DIR := ../../.. - -PKGS_DIR := packages - -source "$(RTT_DIR)/Kconfig" -osource "$PKGS_DIR/Kconfig" -rsource "../libraries/Kconfig" -rsource "board/Kconfig" diff --git a/bsp/n32/n32wb45xl-evb/project.uvoptx b/bsp/n32/n32wb45xl-evb/project.uvoptx deleted file mode 100644 index 74548decd6..0000000000 --- a/bsp/n32/n32wb45xl-evb/project.uvoptx +++ /dev/null @@ -1,180 +0,0 @@ - - - - 1.0 - -
    ### uVision Project, (C) Keil Software
    - - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc; *.md - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32WB452 -FL080000 -FS08000000 -FP0($$Device:N32WB452LEQ6$Flash\N32WB452.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - -     diff --git a/bsp/n32/n32wb45xl-evb/rtconfig.py b/bsp/n32/n32wb45xl-evb/rtconfig.py deleted file mode 100644 index 2a0371110c..0000000000 --- a/bsp/n32/n32wb45xl-evb/rtconfig.py +++ /dev/null @@ -1,184 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4.fp ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' - CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread.map ' - LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv4_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu VFPv4_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) -- Gitee From 5e04105723f6de5ffcd5e6b843b489f52cdc679b Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Mon, 2 Feb 2026 09:45:19 +0000 Subject: [PATCH 27/45] rename i2c mutex Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> --- components/drivers/i2c/dev_i2c_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/drivers/i2c/dev_i2c_core.c b/components/drivers/i2c/dev_i2c_core.c index 9d9bf6b23d..97c860f829 100644 --- a/components/drivers/i2c/dev_i2c_core.c +++ b/components/drivers/i2c/dev_i2c_core.c @@ -24,7 +24,7 @@ rt_err_t rt_i2c_bus_device_register(struct rt_i2c_bus_device *bus, { rt_err_t res = RT_EOK; - rt_mutex_init(&bus->lock, "i2c_bus_lock", RT_IPC_FLAG_PRIO); + rt_mutex_init(&bus->lock, "i2c_lock", RT_IPC_FLAG_PRIO); if (bus->timeout == 0) bus->timeout = RT_TICK_PER_SECOND; -- Gitee From 68da10625347cfe34fad8b73a78feffbe311d561 Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Wed, 4 Feb 2026 16:45:30 +0800 Subject: [PATCH 28/45] [components][drivers]:fix wlan err --- components/drivers/wlan/dev_wlan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/drivers/wlan/dev_wlan.c b/components/drivers/wlan/dev_wlan.c index a3ed0347a9..f9c7f33c2b 100644 --- a/components/drivers/wlan/dev_wlan.c +++ b/components/drivers/wlan/dev_wlan.c @@ -944,7 +944,7 @@ static rt_err_t _rt_wlan_dev_control(rt_device_t dev, int cmd, void *args) case RT_WLAN_CMD_GET_FAST_CONNECT_INFO: { - LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_FAST_INFO, "RT_WLAN_CMD_GET_FAST_INFO"); + LOG_D("%s %d cmd[%d]:%s run......", __FUNCTION__, __LINE__, RT_WLAN_CMD_GET_FAST_CONNECT_INFO, "RT_WLAN_CMD_GET_FAST_CONNECT_INFO"); if (wlan->ops->wlan_get_fast_info) { err = wlan->ops->wlan_get_fast_info(args); -- Gitee From 25b6953501e7ec8eeb7e8c72d2b11e8e49dbecf7 Mon Sep 17 00:00:00 2001 From: CYFS <2805686936@qq.com> Date: Thu, 5 Feb 2026 14:30:11 +0800 Subject: [PATCH 29/45] [components][lwip]: fix ping timeout handling and support LWIP_SO_SNDRCVTIMEO_NONSTANDARD --- components/net/lwip/lwip-1.4.1/src/apps/ping/ping.c | 9 +++++---- components/net/lwip/lwip-2.0.3/src/apps/ping/ping.c | 9 +++++---- components/net/lwip/lwip-2.1.2/src/apps/ping/ping.c | 9 +++++---- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/components/net/lwip/lwip-1.4.1/src/apps/ping/ping.c b/components/net/lwip/lwip-1.4.1/src/apps/ping/ping.c index 6251504f59..d2b1f805f7 100644 --- a/components/net/lwip/lwip-1.4.1/src/apps/ping/ping.c +++ b/components/net/lwip/lwip-1.4.1/src/apps/ping/ping.c @@ -135,11 +135,12 @@ int lwip_ping_recv(int s, int *ttl) /* using the lwIP custom ping */ rt_err_t ping(char* target_name, rt_uint32_t times, rt_size_t size) { -#if LWIP_VERSION_MAJOR >= 2U - struct timeval timeout = { PING_RCV_TIMEO / RT_TICK_PER_SECOND, PING_RCV_TIMEO % RT_TICK_PER_SECOND }; + +#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD + int timeout = (int)PING_RCV_TIMEO; #else - int timeout = PING_RCV_TIMEO * 1000UL / RT_TICK_PER_SECOND; -#endif + struct timeval timeout = { PING_RCV_TIMEO / RT_TICK_PER_SECOND, PING_RCV_TIMEO % RT_TICK_PER_SECOND }; +#endif / * LWIP_SO_SNDRCVTIMEO_NONSTANDARD */ int s, ttl, recv_len; ip_addr_t target_addr; diff --git a/components/net/lwip/lwip-2.0.3/src/apps/ping/ping.c b/components/net/lwip/lwip-2.0.3/src/apps/ping/ping.c index 989fb0507a..3039ecf14d 100644 --- a/components/net/lwip/lwip-2.0.3/src/apps/ping/ping.c +++ b/components/net/lwip/lwip-2.0.3/src/apps/ping/ping.c @@ -135,11 +135,12 @@ int lwip_ping_recv(int s, int *ttl) /* using the lwIP custom ping */ rt_err_t ping(char* target_name, rt_uint32_t times, rt_size_t size) { -#if LWIP_VERSION_MAJOR >= 2U - struct timeval timeout = { PING_RCV_TIMEO / RT_TICK_PER_SECOND, PING_RCV_TIMEO % RT_TICK_PER_SECOND }; + +#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD + int timeout = (int)PING_RCV_TIMEO; #else - int timeout = PING_RCV_TIMEO * 1000UL / RT_TICK_PER_SECOND; -#endif + struct timeval timeout = { PING_RCV_TIMEO / RT_TICK_PER_SECOND, PING_RCV_TIMEO % RT_TICK_PER_SECOND }; +#endif / * LWIP_SO_SNDRCVTIMEO_NONSTANDARD */ int s, ttl, recv_len; ip_addr_t target_addr; diff --git a/components/net/lwip/lwip-2.1.2/src/apps/ping/ping.c b/components/net/lwip/lwip-2.1.2/src/apps/ping/ping.c index 6251504f59..d2b1f805f7 100644 --- a/components/net/lwip/lwip-2.1.2/src/apps/ping/ping.c +++ b/components/net/lwip/lwip-2.1.2/src/apps/ping/ping.c @@ -135,11 +135,12 @@ int lwip_ping_recv(int s, int *ttl) /* using the lwIP custom ping */ rt_err_t ping(char* target_name, rt_uint32_t times, rt_size_t size) { -#if LWIP_VERSION_MAJOR >= 2U - struct timeval timeout = { PING_RCV_TIMEO / RT_TICK_PER_SECOND, PING_RCV_TIMEO % RT_TICK_PER_SECOND }; + +#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD + int timeout = (int)PING_RCV_TIMEO; #else - int timeout = PING_RCV_TIMEO * 1000UL / RT_TICK_PER_SECOND; -#endif + struct timeval timeout = { PING_RCV_TIMEO / RT_TICK_PER_SECOND, PING_RCV_TIMEO % RT_TICK_PER_SECOND }; +#endif / * LWIP_SO_SNDRCVTIMEO_NONSTANDARD */ int s, ttl, recv_len; ip_addr_t target_addr; -- Gitee From 1254af44f253a11e2fe7351bb0242a6dbd219544 Mon Sep 17 00:00:00 2001 From: haitaoZhang <49626779+zhang-haitao-repo@users.noreply.github.com> Date: Thu, 5 Feb 2026 22:14:48 +0800 Subject: [PATCH 30/45] [gd32][uart] Add GD32VW553 series UART driver support (#11147) * feat(gd32): add GD32VW55x series USART driver support - Add support for GD32VW55x series UART/USART peripherals - Implement proper GPIO alternate function configuration for GD32VW55x - Add conditional compilation for different GD32 series (GD32VF103V vs GD32VW55x) - Remove unused UART3/UART4 configurations from Kconfig * Update drv_usart.c * Update drv_usart.h follow AI Review. * Update bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * feat: optimize gd32 uart driver error messages --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig | 20 ------ .../risc-v/libraries/gd32_drivers/drv_usart.c | 68 +++++++++++++++++-- .../risc-v/libraries/gd32_drivers/drv_usart.h | 4 ++ 3 files changed, 67 insertions(+), 25 deletions(-) diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig index 8d0f34949a..433c305712 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig @@ -56,26 +56,6 @@ menu "On-chip Peripheral Drivers" depends on BSP_USING_UART2 select RT_SERIAL_USING_DMA default n - - config BSP_USING_UART3 - bool "Enable UART3" - default n - - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 - select RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART4 - bool "Enable UART4" - default n - - config BSP_UART4_RX_USING_DMA - bool "Enable UART4 RX DMA" - depends on BSP_USING_UART4 - select RT_SERIAL_USING_DMA - default n endif menuconfig BSP_USING_PWM diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c index 2b3f8881d1..feba6f0004 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c @@ -7,6 +7,7 @@ * Date Author Notes * 2021-08-20 BruceOu first implementation * 2025-07-11 Wangshun adapt to GD32VV553H + * 2026-01-22 HaitaoZhang adapt to GD32VW553H UART1/2 */ #include "drv_usart.h" @@ -45,6 +46,7 @@ void USART0_IRQHandler(void) #if defined(BSP_USING_UART1) struct rt_serial_device serial1; +#if defined (SOC_SERIES_GD32VF103V) void USART1_IRQHandler(void) { /* enter interrupt */ @@ -55,12 +57,27 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#elif defined (SOC_SERIES_GD32VW55x) +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + GD32_UART_IRQHandler(&serial1); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#else +#error "Uart1 ISR name not compatible with current MCU series" +#endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) struct rt_serial_device serial2; +#if defined (SOC_SERIES_GD32VF103V) void USART2_IRQHandler(void) { /* enter interrupt */ @@ -71,6 +88,20 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } +#elif defined (SOC_SERIES_GD32VW55x) +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + GD32_UART_IRQHandler(&serial2); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#else +#error "Uart2 ISR name not compatible with current MCU series" +#endif #endif /* BSP_USING_UART2 */ @@ -161,6 +192,9 @@ static const struct gd32_uart uart_obj[] = { RCU_USART0, RCU_GPIOB, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ GPIOB, GPIO_PIN_15, /* tx port, tx pin */ GPIOA, GPIO_PIN_8, /* rx port, rx pin */ +#if defined (SOC_SERIES_GD32VW55x) + GPIO_AF_8, GPIO_AF_2, +#endif &serial0, "uart0", }, @@ -168,11 +202,22 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART1 { +#if defined (SOC_SERIES_GD32VF103V) USART1, /* uart peripheral index */ USART1_IRQn, /* uart iqrn */ RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ GPIOA, GPIO_PIN_2, /* tx port, tx pin */ GPIOA, GPIO_PIN_3, /* rx port, rx pin */ +#elif defined (SOC_SERIES_GD32VW55x) + UART1, /* uart peripheral index */ + UART1_IRQn, /* uart iqrn */ + RCU_UART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_2, /* tx port, tx pin */ + GPIOA, GPIO_PIN_3, /* rx port, rx pin */ + GPIO_AF_7, GPIO_AF_7, +#else +#error "UART1 peripheral config incompatible with current MCU series" +#endif &serial1, "uart1", }, @@ -180,11 +225,22 @@ static const struct gd32_uart uart_obj[] = { #ifdef BSP_USING_UART2 { +#if defined (SOC_SERIES_GD32VF103V) USART2, /* uart peripheral index */ USART2_IRQn, /* uart iqrn */ RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ GPIOB, GPIO_PIN_10, /* tx port, tx pin */ GPIOB, GPIO_PIN_11, /* rx port, rx pin */ +#elif defined (SOC_SERIES_GD32VW55x) + UART2, /* uart peripheral index */ + UART2_IRQn, /* uart iqrn */ + RCU_UART2, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ + GPIOA, GPIO_PIN_6, /* tx port, tx pin */ + GPIOA, GPIO_PIN_7, /* rx port, rx pin */ + GPIO_AF_10, GPIO_AF_8, +#else +#error "UART2 peripheral config incompatible with current MCU series" +#endif &serial2, "uart2", }, @@ -233,17 +289,19 @@ void gd32_uart_gpio_init(struct gd32_uart *uart) rcu_periph_clock_enable(uart->per_clk); /* connect port */ -#if defined SOC_SERIES_GD32VF103V +#if defined (SOC_SERIES_GD32VF103V) gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); -#else - gpio_af_set(uart->tx_port, GPIO_AF_8, uart->tx_pin); +#elif defined (SOC_SERIES_GD32VW55x) + gpio_af_set(uart->tx_port, uart->tx_alt, uart->tx_pin); gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin); gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, uart->tx_pin); - gpio_af_set(uart->rx_port, GPIO_AF_2, uart->rx_pin); + gpio_af_set(uart->rx_port, uart->rx_alt, uart->rx_pin); gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, uart->rx_pin); +#else +#error "Uart GPIO config incompatible with current MCU series" #endif } @@ -328,7 +386,7 @@ static rt_err_t gd32_uart_control(struct rt_serial_device *serial, int cmd, void break; case RT_DEVICE_CTRL_SET_INT: -#ifdef SOC_SERIES_GD32VF103V +#if defined (SOC_SERIES_GD32VF103V) eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); #endif /* SOC_SERIES_GD32VF103V */ /* enable rx irq */ diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h index 6a6f75697e..bff4604876 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.h @@ -32,6 +32,10 @@ struct gd32_uart uint16_t tx_pin; /* Todo: 4bits */ uint32_t rx_port; /* Todo: 4bits */ uint16_t rx_pin; /* Todo: 4bits */ +#if defined (SOC_SERIES_GD32VW55x) + uint32_t tx_alt; /* GPIO alternate function for TX */ + uint32_t rx_alt; /* GPIO alternate function for RX */ +#endif struct rt_serial_device * serial; char *device_name; }; -- Gitee From a69d381828805e8a13e50422471a157dc64692f4 Mon Sep 17 00:00:00 2001 From: Onlyou_tzZ <17393117531@163.com> Date: Wed, 28 Jan 2026 14:58:58 +0800 Subject: [PATCH 31/45] =?UTF-8?q?=E6=9B=B4=E6=96=B0=E5=9B=BD=E6=B0=91?= =?UTF-8?q?=E6=8A=80=E6=9C=AFBSP=E6=9E=B6=E6=9E=84=EF=BC=8C=E6=B7=BB?= =?UTF-8?q?=E5=8A=A0N32H7xx=E7=B3=BB=E5=88=97BSP?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 修改clang_format-ignore文件,根据反馈修改n32h7xxx/libraries/N32_Drivers/nano/*下的文件格式，修改n32h7xxx/n32/n32hxxx/n32h760zil7-stb/applications/main.c文件，区别处理Nano下头文件包含 将N32 BSP的.clang-format-ignore文件放入libraries同级目录 忽略库文件格式检查 fix(cherryusb): fix dwc2 host size check Signed-off-by: sakumisu <1203593632@qq.com> [components][clock_time] Refactor time subsystem around clock_time (#11111) * [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue 解决N32 BSP project.ewp和project.uvprojx冲突 更新RTT最新同步 sdio: fix missing card status polling after CMD6 in eMMC DDR mode switch fix[dfs_v1]: prevent vnode ref underflow and double release on close/fd release feat[STM32][CAN]: drain RX FIFO frames in ISR with a bounded limit to reduce overruns - Add CAN_ISR_DRAIN_LIMIT (default 3) to cap ISR work - Drain multiple frames per RX0/RX1 interrupt to reduce FIFO FULL/OVERRUN docs(can): improve dev_can.h docs for batched RX example fix[STM32][RTC]: Compute tv_usec from SecondFraction/SubSeconds and skip during shift pending Use the generic SecondFraction/SubSeconds formula when SSR/PRER are available. If SHPF is present and a shift is pending, keep tv_usec at 0. Platforms without SSR/PRER (e.g. F1) default to 0. [bsp][gd32]:add gd32vw533xx pwm support Update Nsing's BSP architecture and add N32H7xx series BSPs. (#11159) * 更新国民技术BSP架构，添加N32H7xx系列BSP * 修改clang_format-ignore文件,根据反馈修改n32h7xxx/libraries/N32_Drivers/nano/*下的文件格式，修改n32h7xxx/n32/n32hxxx/n32h760zil7-stb/applications/main.c文件，区别处理Nano下头文件包含 * 将N32 BSP的.clang-format-ignore文件放入libraries同级目录 * 忽略库文件格式检查 * 解决N32 BSP project.ewp和project.uvprojx冲突 * 更新RTT最新同步 rename i2c mutex Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com> Squashed commit of the following: commit cadd095cd34bb2eaab5e39466f56674a9fe3f19b Merge: 5ad4edcf39 68da106253 Author: Onlyou_tzZ <97173915+OnlyoutzZ@users.noreply.github.com> Date: Wed Feb 4 22:50:54 2026 +0800 Merge branch 'RT-Thread:master' into master commit 68da10625347cfe34fad8b73a78feffbe311d561 Author: CYFS <2805686936@qq.com> Date: Wed Feb 4 16:45:30 2026 +0800 [components][drivers]:fix wlan err commit 5ad4edcf39330f01f698d95c322c3d0f8aae2feb Author: Onlyou_tzZ <17393117531@163.com> Date: Wed Feb 4 20:22:40 2026 +0800 更新BSP下README.md中N32相关的描述 更新BSP下README.md中N32相关的描述 [components][drivers]:fix wlan err [components][lwip]: fix ping timeout handling and support LWIP_SO_SNDRCVTIMEO_NONSTANDARD [gd32][uart] Add GD32VW553 series UART driver support (#11147) * feat(gd32): add GD32VW55x series USART driver support - Add support for GD32VW55x series UART/USART peripherals - Implement proper GPIO alternate function configuration for GD32VW55x - Add conditional compilation for different GD32 series (GD32VF103V vs GD32VW55x) - Remove unused UART3/UART4 configurations from Kconfig * Update drv_usart.c * Update drv_usart.h follow AI Review. * Update bsp/gd32/risc-v/libraries/gd32_drivers/drv_usart.c Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * feat: optimize gd32 uart driver error messages --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- bsp/README.md | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/bsp/README.md b/bsp/README.md index 1b77f59626..6bb02cceab 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -317,18 +317,19 @@ This document is based on the RT-Thread mainline repository and categorizes the | BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | |----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----| -| [n32g43xcl-stb](n32/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32g457gel-stb](n32) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32g45xcl-stb](n32/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32g45xml-stb](n32/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32g45xrl-stb](n32/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32g45xvl-stb](n32/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32g47rml-stb](n32/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32l40xcl-stb](n32/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32l436-evb](n32/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32l43xml-stb](n32/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32l43xrl-stb](n32/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32wb45xl-evb](n32/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - | #### 🟡 NRF5x -- Gitee From 4e5c1cfb44d905f87309b3cb7c3c0bde6d7d4f2c Mon Sep 17 00:00:00 2001 From: GuEe-GUI <2991707448@qq.com> Date: Mon, 9 Feb 2026 21:53:17 +0800 Subject: [PATCH 32/45] [bsp][rockchip] fixup rk3500 build and run Linker: https://github.com/RT-Thread/rt-thread/issues/11150 Signed-off-by: GuEe-GUI <2991707448@qq.com> --- bsp/rockchip/dm/Kconfig | 2 +- bsp/rockchip/rk3500/.config | 210 +++++++++++++++++++++----- bsp/rockchip/rk3500/rtconfig.h | 132 ++++++++++++++-- components/drivers/Kconfig | 6 + components/drivers/clk/clk-scmi.c | 4 +- components/drivers/clock_time/Kconfig | 4 + 6 files changed, 305 insertions(+), 53 deletions(-) diff --git a/bsp/rockchip/dm/Kconfig b/bsp/rockchip/dm/Kconfig index 53eca977c9..976548e8eb 100755 --- a/bsp/rockchip/dm/Kconfig +++ b/bsp/rockchip/dm/Kconfig @@ -3,7 +3,7 @@ SOC_DM_CAN_DIR = $(SOC_DM_DIR)/can SOC_DM_CLK_DIR = $(SOC_DM_DIR)/clk SOC_DM_HWCRYPTO_DIR = $(SOC_DM_DIR)/hwcrypto SOC_DM_HWSPINLOCK_DIR = $(SOC_DM_DIR)/hwspinlock -SOC_DM_HWTIMER_DIR = $(SOC_DM_DIR)/hwtimer +SOC_DM_CLOCK_TIME_DIR = $(SOC_DM_DIR)/hwtimer SOC_DM_I2C_DIR = $(SOC_DM_DIR)/i2c SOC_DM_INPUT_MISC_DIR = $(SOC_DM_DIR)/input/misc SOC_DM_MBOX_DIR = $(SOC_DM_DIR)/mailbox diff --git a/bsp/rockchip/rk3500/.config b/bsp/rockchip/rk3500/.config index fc4a8cde21..2a186892fa 100644 --- a/bsp/rockchip/rk3500/.config +++ b/bsp/rockchip/rk3500/.config @@ -116,7 +116,7 @@ CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 # end of rt_strnlen options # end of klibc options -CONFIG_RT_NAME_MAX=12 +CONFIG_RT_NAME_MAX=24 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set CONFIG_RT_USING_SMART=y @@ -266,7 +266,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set CONFIG_RT_USING_DFS_PTYFS=y CONFIG_RT_USING_DFS_PROCFS=y -CONFIG_RT_USING_DFS_CROMFS=y +# CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_TMPFS=y CONFIG_RT_USING_DFS_MQUEUE=y CONFIG_RT_USING_PAGECACHE=y @@ -304,28 +304,59 @@ CONFIG_RT_USING_SERIAL_BYPASS=y # CONFIG_RT_SERIAL_EARLY_HVC is not set # CONFIG_RT_SERIAL_PL011 is not set CONFIG_RT_SERIAL_8250=y -# CONFIG_RT_SERIAL_8250_DW is not set -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_SERIAL_8250_DW=y +# CONFIG_RT_SERIAL_8250_PCI is not set +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +CONFIG_RT_CAN_USING_CANFD=y +CONFIG_RT_CANMSG_BOX_SZ=16 +CONFIG_RT_CANSND_BOX_NUM=1 +CONFIG_RT_CANSND_MSG_TIMEOUT=100 +CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256 +# CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set +CONFIG_RT_CAN_CANFD_ROCKCHIP=y +CONFIG_RT_USING_CLOCK_TIME=y +CONFIG_RT_CLOCK_TIME_ARM_ARCH=y +CONFIG_RT_CLOCK_TIMER_ROCKCHIP=y +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +CONFIG_RT_I2C_RK3X=y # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set +CONFIG_RT_USING_ADC=y +CONFIG_RT_ADC_ROCKCHIP_SARADC=y # CONFIG_RT_USING_DAC is not set CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y -# CONFIG_RT_USING_PWM is not set +CONFIG_RT_USING_PWM=y +CONFIG_RT_PWM_ROCKCHIP=y # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_MTD_NOR is not set +CONFIG_RT_USING_MTD_NOR=y +# CONFIG_RT_USING_MTD_NOR_CFI is not set +CONFIG_RT_USING_MTD_NOR_SPI=y # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set +CONFIG_RT_USING_ALARM=y +CONFIG_RT_ALARM_STACK_SIZE=16384 +CONFIG_RT_ALARM_TIMESLICE=5 +CONFIG_RT_ALARM_PRIORITY=10 +# CONFIG_RT_ALARM_USING_LOCAL_TIME is not set CONFIG_RT_USING_SOFT_RTC=y +# CONFIG_RT_RTC_DS1302 is not set +# CONFIG_RT_RTC_DS1307 is not set # CONFIG_RT_RTC_GOLDFISH is not set +CONFIG_RT_RTC_HYM8563=y +CONFIG_RT_RTC_PCF8523=y +CONFIG_RT_RTC_PCF8563=y # CONFIG_RT_RTC_PL031 is not set +CONFIG_RT_RTC_RX8010=y +CONFIG_RT_RTC_RK8XX=y # CONFIG_RT_RTC_RK_TIMER is not set CONFIG_RT_USING_SDIO=y CONFIG_RT_SDIO_STACK_SIZE=16384 @@ -335,19 +366,77 @@ CONFIG_RT_MMCSD_THREAD_PRIORITY=22 CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SDHCI is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_SDIO_SDHCI_PCI is not set +CONFIG_RT_SDIO_DW_MMC=y +# CONFIG_RT_SDIO_DW_MMC_PCI is not set +CONFIG_RT_SDIO_DW_MMC_ROCKCHIP=y +CONFIG_RT_USING_SPI=y +CONFIG_RT_USING_SPI_ISR=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_SOFT_SPI is not set +CONFIG_RT_USING_QSPI=y +# CONFIG_RT_USING_SPI_MSD is not set +CONFIG_RT_USING_SFUD=y +CONFIG_RT_SFUD_USING_SFDP=y +CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y +# CONFIG_RT_SFUD_USING_QSPI is not set +CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 +# CONFIG_RT_DEBUG_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_SPI_ROCKCHIP_SFC is not set +CONFIG_RT_SPI_ROCKCHIP=y +CONFIG_RT_USING_WDT=y +CONFIG_RT_WDT_DW=y +# CONFIG_RT_WDT_I6300ESB is not set +CONFIG_RT_WDT_RK8XX=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_GRAPHIC is not set -# CONFIG_RT_USING_HWCRYPTO is not set +CONFIG_RT_USING_HWCRYPTO=y +CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto" +CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16 +CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256 +# CONFIG_RT_HWCRYPTO_USING_GCM is not set +# CONFIG_RT_HWCRYPTO_USING_AES is not set +# CONFIG_RT_HWCRYPTO_USING_DES is not set +# CONFIG_RT_HWCRYPTO_USING_3DES is not set +# CONFIG_RT_HWCRYPTO_USING_RC4 is not set +# CONFIG_RT_HWCRYPTO_USING_MD5 is not set +# CONFIG_RT_HWCRYPTO_USING_SHA1 is not set +# CONFIG_RT_HWCRYPTO_USING_SHA2 is not set +CONFIG_RT_HWCRYPTO_USING_RNG=y +# CONFIG_RT_HWCRYPTO_USING_CRC is not set +# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set +CONFIG_RT_HWCRYPTO_RNG_ROCKCHIP=y # CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_LED is not set -# CONFIG_RT_USING_INPUT is not set -# CONFIG_RT_USING_MBOX is not set -# CONFIG_RT_USING_HWSPINLOCK is not set -# CONFIG_RT_USING_PHYE is not set +CONFIG_RT_USING_LED=y +CONFIG_RT_LED_GPIO=y +# CONFIG_RT_LED_PWM is not set +# CONFIG_RT_LED_SYSCON is not set +CONFIG_RT_USING_INPUT=y +CONFIG_RT_INPUT_POWER=y +# CONFIG_RT_INPUT_UAPI is not set +# CONFIG_RT_INPUT_JOYSTICK is not set +# CONFIG_RT_INPUT_KEYBOARD is not set +CONFIG_RT_INPUT_MISC=y +# CONFIG_RT_INPUT_MISC_BUTTON_E3X0 is not set +CONFIG_RT_INPUT_MISC_PWRKEY_RK8XX=y +# CONFIG_RT_INPUT_TOUCHSCREEN is not set +CONFIG_RT_USING_MBOX=y +CONFIG_RT_MBOX_PIC=y +CONFIG_RT_MBOX_ROCKCHIP=y +CONFIG_RT_USING_HWSPINLOCK=y +CONFIG_RT_HWSPINLOCK_ROCKCHIP=y +CONFIG_RT_USING_PHYE=y +# CONFIG_RT_PHYE_GENERIC_USB is not set +CONFIG_RT_PHYE_ROCKCHIP_NANENG_COMBO=y +CONFIG_RT_PHYE_ROCKCHIP_SNPS_PCIE3=y +# CONFIG_RT_USING_ATA is not set +CONFIG_RT_USING_NVME=y +CONFIG_RT_USING_NVME_IO_QUEUE=4 +CONFIG_RT_NVME_PCI=y CONFIG_RT_USING_BLK=y # @@ -358,51 +447,104 @@ CONFIG_RT_BLK_PARTITION_EFI=y # end of Partition Types # CONFIG_RT_USING_SCSI is not set -# CONFIG_RT_USING_FIRMWARE is not set +CONFIG_RT_USING_FIRMWARE=y +CONFIG_RT_FIRMWARE_ARM_SCMI=y +CONFIG_RT_FIRMWARE_ARM_SCMI_TRANSPORT_MAILBOX=y +CONFIG_RT_FIRMWARE_ARM_SCMI_TRANSPORT_SMC=y # CONFIG_RT_USING_HWCACHE is not set -# CONFIG_RT_USING_REGULATOR is not set +CONFIG_RT_USING_REGULATOR=y +CONFIG_RT_REGULATOR_FIXED=y +CONFIG_RT_REGULATOR_GPIO=y +CONFIG_RT_REGULATOR_SCMI=y +CONFIG_RT_REGULATOR_RK8XX=y CONFIG_RT_USING_RESET=y +CONFIG_RT_RESET_SCMI=y # CONFIG_RT_RESET_SIMPLE is not set # # Power Management (PM) Domains device drivers # +CONFIG_RT_PMDOMAIN_SCMI=y +CONFIG_RT_PMDOMAIN_ROCKCHIP=y # end of Power Management (PM) Domains device drivers # CONFIG_RT_USING_POWER_RESET is not set # CONFIG_RT_USING_POWER_SUPPLY is not set -# CONFIG_RT_USING_THERMAL is not set +CONFIG_RT_USING_THERMAL=y + +# +# Thermal Sensors Drivers +# +# CONFIG_RT_THERMAL_SCMI is not set +CONFIG_RT_THERMAL_ROCKCHIP_TSADC=y + +# +# Thermal Cool Drivers +# +CONFIG_RT_THERMAL_COOL_PWM_FAN=y # CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_NVMEM is not set -# CONFIG_RT_USING_DMA is not set +CONFIG_RT_USING_NVMEM=y +CONFIG_RT_NVMEM_ROCKCHIP_OTP=y +CONFIG_RT_USING_DMA=y +CONFIG_RT_DMA_PL330=y CONFIG_RT_USING_MFD=y +# CONFIG_RT_MFD_EDU is not set CONFIG_RT_MFD_SYSCON=y +CONFIG_RT_MFD_RK8XX=y +CONFIG_RT_MFD_RK8XX_I2C=y +CONFIG_RT_MFD_RK8XX_SPI=y CONFIG_RT_USING_OFW=y # CONFIG_RT_USING_BUILTIN_FDT is not set CONFIG_RT_FDT_EARLYCON_MSG_SIZE=128 CONFIG_RT_USING_OFW_BUS_RANGES_NUMBER=8 -# CONFIG_RT_USING_PCI is not set +CONFIG_RT_USING_PCI=y +CONFIG_RT_PCI_MSI=y +CONFIG_RT_PCI_ENDPOINT=y +CONFIG_RT_PCI_SYS_64BIT=y +CONFIG_RT_PCI_CACHE_LINE_SIZE=8 +# CONFIG_RT_PCI_LOCKLESS is not set + +# +# PCI Device Drivers +# +# CONFIG_RT_PCI_ECAM is not set +CONFIG_RT_PCI_DW=y +CONFIG_RT_PCI_DW_HOST=y +CONFIG_RT_PCI_DW_EP=y +CONFIG_RT_PCI_DW_ROCKCHIP=y CONFIG_RT_USING_PIC=y -CONFIG_MAX_HANDLERS=1024 +CONFIG_MAX_HANDLERS=2048 # CONFIG_RT_PIC_ARM_GIC is not set CONFIG_RT_PIC_ARM_GIC_V3=y +CONFIG_RT_PIC_ARM_GIC_V3_ITS=y +CONFIG_RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX=256 CONFIG_RT_USING_PIN=y # CONFIG_RT_PIN_PL061 is not set CONFIG_RT_PIN_ROCKCHIP=y CONFIG_RT_USING_PINCTRL=y +# CONFIG_RT_PINCTRL_SCMI is not set # CONFIG_RT_PINCTRL_SINGLE is not set +CONFIG_RT_PINCTRL_ROCKCHIP_RK8XX=y CONFIG_RT_PINCTRL_ROCKCHIP=y -CONFIG_RT_USING_CLOCK_TIME=y -CONFIG_RT_CLOCK_TIME_ARM_ARCH=y CONFIG_RT_USING_CLK=y +CONFIG_RT_CLK_SCMI=y +CONFIG_RT_CLK_ROCKCHIP_RK8XX_CLKOUT=y CONFIG_RT_CLK_ROCKCHIP_LINK=y CONFIG_RT_CLK_ROCKCHIP=y # CONFIG_RT_CLK_ROCKCHIP_RK3308 is not set CONFIG_RT_CLK_ROCKCHIP_RK3568=y -# CONFIG_RT_CLK_ROCKCHIP_RK3576 is not set +CONFIG_RT_CLK_ROCKCHIP_RK3576=y CONFIG_RT_CLK_ROCKCHIP_RK3588=y -CONFIG_RT_CLOCK_TIMER_ROCKCHIP=y # CONFIG_RT_USING_CHERRYUSB is not set + +# +# SoC (System on Chip) Drivers +# +CONFIG_RT_SOC_ROCKCHIP_FIQ_DEBUGGER=y +CONFIG_RT_SOC_ROCKCHIP_GRF=y +CONFIG_RT_SOC_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_RT_SOC_ROCKCHIP_IODOMAIN=y +# end of SoC (System on Chip) Drivers # end of Device Drivers # @@ -999,7 +1141,6 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set # CONFIG_PKG_USING_THREAD_METRIC is not set -# CONFIG_PKG_USING_UORB is not set # end of tools packages # @@ -1094,7 +1235,6 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set -# CONFIG_PKG_USING_CHERRYECAT is not set # end of system packages # @@ -1251,12 +1391,6 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set # CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set # end of GD32 Drivers - -# -# HPMicro SDK -# -# CONFIG_PKG_USING_HPM_SDK is not set -# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1305,7 +1439,6 @@ CONFIG_RT_UTEST_SMP_CALL_FUNC=y # CONFIG_PKG_USING_MLX90393 is not set # CONFIG_PKG_USING_MLX90392 is not set # CONFIG_PKG_USING_MLX90394 is not set -# CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set # CONFIG_PKG_USING_MS5611 is not set # CONFIG_PKG_USING_MAX31865 is not set @@ -1776,4 +1909,3 @@ CONFIG_PKG_ZLIB_VER="latest" # end of RT-Thread online packages CONFIG_SOC_RK3500=y -CONFIG_SOC_RK3568=y diff --git a/bsp/rockchip/rk3500/rtconfig.h b/bsp/rockchip/rk3500/rtconfig.h index 0518bc0e16..54ff974a0c 100644 --- a/bsp/rockchip/rk3500/rtconfig.h +++ b/bsp/rockchip/rk3500/rtconfig.h @@ -72,7 +72,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 +#define RT_NAME_MAX 24 #define RT_USING_SMART #define RT_USING_SMP #define RT_CPUS_NR 4 @@ -182,7 +182,6 @@ #define RT_USING_DFS_DEVFS #define RT_USING_DFS_PTYFS #define RT_USING_DFS_PROCFS -#define RT_USING_DFS_CROMFS #define RT_USING_DFS_TMPFS #define RT_USING_DFS_MQUEUE #define RT_USING_PAGECACHE @@ -212,17 +211,82 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_SERIAL_BYPASS #define RT_SERIAL_8250 +#define RT_SERIAL_8250_DW +#define RT_USING_CAN +#define RT_CAN_USING_CANFD +#define RT_CANMSG_BOX_SZ 16 +#define RT_CANSND_BOX_NUM 1 +#define RT_CANSND_MSG_TIMEOUT 100 +#define RT_CAN_NB_TX_FIFO_SIZE 256 +#define RT_CAN_CANFD_ROCKCHIP +#define RT_USING_CLOCK_TIME +#define RT_CLOCK_TIME_ARM_ARCH +#define RT_CLOCK_TIMER_ROCKCHIP +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_I2C_RK3X +#define RT_USING_ADC +#define RT_ADC_ROCKCHIP_SARADC #define RT_USING_NULL #define RT_USING_ZERO #define RT_USING_RANDOM +#define RT_USING_PWM +#define RT_PWM_ROCKCHIP +#define RT_USING_MTD_NOR +#define RT_USING_MTD_NOR_SPI #define RT_USING_RTC +#define RT_USING_ALARM +#define RT_ALARM_STACK_SIZE 16384 +#define RT_ALARM_TIMESLICE 5 +#define RT_ALARM_PRIORITY 10 #define RT_USING_SOFT_RTC +#define RT_RTC_HYM8563 +#define RT_RTC_PCF8523 +#define RT_RTC_PCF8563 +#define RT_RTC_RX8010 +#define RT_RTC_RK8XX #define RT_USING_SDIO #define RT_SDIO_STACK_SIZE 16384 #define RT_SDIO_THREAD_PRIORITY 15 #define RT_MMCSD_STACK_SIZE 16384 #define RT_MMCSD_THREAD_PRIORITY 22 #define RT_MMCSD_MAX_PARTITION 16 +#define RT_SDIO_DW_MMC +#define RT_SDIO_DW_MMC_ROCKCHIP +#define RT_USING_SPI +#define RT_USING_SPI_ISR +#define RT_USING_QSPI +#define RT_USING_SFUD +#define RT_SFUD_USING_SFDP +#define RT_SFUD_USING_FLASH_INFO_TABLE +#define RT_SFUD_SPI_MAX_HZ 50000000 +#define RT_SPI_ROCKCHIP +#define RT_USING_WDT +#define RT_WDT_DW +#define RT_WDT_RK8XX +#define RT_USING_HWCRYPTO +#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto" +#define RT_HWCRYPTO_IV_MAX_SIZE 16 +#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256 +#define RT_HWCRYPTO_USING_RNG +#define RT_HWCRYPTO_RNG_ROCKCHIP +#define RT_USING_LED +#define RT_LED_GPIO +#define RT_USING_INPUT +#define RT_INPUT_POWER +#define RT_INPUT_MISC +#define RT_INPUT_MISC_PWRKEY_RK8XX +#define RT_USING_MBOX +#define RT_MBOX_PIC +#define RT_MBOX_ROCKCHIP +#define RT_USING_HWSPINLOCK +#define RT_HWSPINLOCK_ROCKCHIP +#define RT_USING_PHYE +#define RT_PHYE_ROCKCHIP_NANENG_COMBO +#define RT_PHYE_ROCKCHIP_SNPS_PCIE3 +#define RT_USING_NVME +#define RT_USING_NVME_IO_QUEUE 4 +#define RT_NVME_PCI #define RT_USING_BLK /* Partition Types */ @@ -230,31 +294,82 @@ #define RT_BLK_PARTITION_DFS #define RT_BLK_PARTITION_EFI /* end of Partition Types */ +#define RT_USING_FIRMWARE +#define RT_FIRMWARE_ARM_SCMI +#define RT_FIRMWARE_ARM_SCMI_TRANSPORT_MAILBOX +#define RT_FIRMWARE_ARM_SCMI_TRANSPORT_SMC +#define RT_USING_REGULATOR +#define RT_REGULATOR_FIXED +#define RT_REGULATOR_GPIO +#define RT_REGULATOR_SCMI +#define RT_REGULATOR_RK8XX #define RT_USING_RESET +#define RT_RESET_SCMI /* Power Management (PM) Domains device drivers */ +#define RT_PMDOMAIN_SCMI +#define RT_PMDOMAIN_ROCKCHIP /* end of Power Management (PM) Domains device drivers */ +#define RT_USING_THERMAL + +/* Thermal Sensors Drivers */ + +#define RT_THERMAL_ROCKCHIP_TSADC + +/* Thermal Cool Drivers */ + +#define RT_THERMAL_COOL_PWM_FAN +#define RT_USING_NVMEM +#define RT_NVMEM_ROCKCHIP_OTP +#define RT_USING_DMA +#define RT_DMA_PL330 #define RT_USING_MFD #define RT_MFD_SYSCON +#define RT_MFD_RK8XX +#define RT_MFD_RK8XX_I2C +#define RT_MFD_RK8XX_SPI #define RT_USING_OFW #define RT_FDT_EARLYCON_MSG_SIZE 128 #define RT_USING_OFW_BUS_RANGES_NUMBER 8 +#define RT_USING_PCI +#define RT_PCI_MSI +#define RT_PCI_ENDPOINT +#define RT_PCI_SYS_64BIT +#define RT_PCI_CACHE_LINE_SIZE 8 + +/* PCI Device Drivers */ + +#define RT_PCI_DW +#define RT_PCI_DW_HOST +#define RT_PCI_DW_EP +#define RT_PCI_DW_ROCKCHIP #define RT_USING_PIC -#define MAX_HANDLERS 1024 +#define MAX_HANDLERS 2048 #define RT_PIC_ARM_GIC_V3 +#define RT_PIC_ARM_GIC_V3_ITS +#define RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX 256 #define RT_USING_PIN #define RT_PIN_ROCKCHIP #define RT_USING_PINCTRL +#define RT_PINCTRL_ROCKCHIP_RK8XX #define RT_PINCTRL_ROCKCHIP -#define RT_USING_CLOCK_TIME #define RT_USING_CLK +#define RT_CLK_SCMI +#define RT_CLK_ROCKCHIP_RK8XX_CLKOUT #define RT_CLK_ROCKCHIP_LINK #define RT_CLK_ROCKCHIP #define RT_CLK_ROCKCHIP_RK3568 +#define RT_CLK_ROCKCHIP_RK3576 #define RT_CLK_ROCKCHIP_RK3588 -#define RT_CLOCK_TIME_ARM_ARCH -#define RT_CLOCK_TIMER_ROCKCHIP + +/* SoC (System on Chip) Drivers */ + +#define RT_SOC_ROCKCHIP_FIQ_DEBUGGER +#define RT_SOC_ROCKCHIP_GRF +#define RT_SOC_ROCKCHIP_HW_DECOMPRESS +#define RT_SOC_ROCKCHIP_IODOMAIN +/* end of SoC (System on Chip) Drivers */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -594,10 +709,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -680,6 +791,5 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ #define SOC_RK3500 -#define SOC_RK3568 #endif diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 01539009a2..f04d3c7f48 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -49,4 +49,10 @@ rsource "pinctrl/Kconfig" rsource "clk/Kconfig" rsource "usb/Kconfig" +if RT_USING_DM + menu "SoC (System on Chip) Drivers" + osource "$(SOC_DM_SOC_DIR)/Kconfig" + endmenu +endif + endmenu diff --git a/components/drivers/clk/clk-scmi.c b/components/drivers/clk/clk-scmi.c index ca51ee1ddc..d6240fa406 100755 --- a/components/drivers/clk/clk-scmi.c +++ b/components/drivers/clk/clk-scmi.c @@ -47,7 +47,7 @@ struct scmi_clk_data } info; }; -#define cell_to_scmi_clk_data(cell) rt_container_of(cell, struct scmi_clk_data, cell) +#define cell_to_scmi_clk_data(cell_ptr) rt_container_of(cell_ptr, struct scmi_clk_data, cell) static rt_err_t scmi_clk_op_gate(struct scmi_clk *sclk, int clk_id, rt_bool_t enable) { @@ -128,7 +128,7 @@ static rt_base_t scmi_clk_round_rate(struct rt_clk_cell *cell, rt_ubase_t drate, if (clk_data->rate_discrete) { - return rate; + return drate; } fmin = clk_data->info.range.min_rate; diff --git a/components/drivers/clock_time/Kconfig b/components/drivers/clock_time/Kconfig index 7da12ac849..d6259617aa 100644 --- a/components/drivers/clock_time/Kconfig +++ b/components/drivers/clock_time/Kconfig @@ -15,4 +15,8 @@ if RT_USING_CLOCK_TIME depends on RT_USING_DM depends on ARCH_ARM_CORTEX_A || ARCH_ARMV8 default n + +if RT_USING_DM + osource "$(SOC_DM_CLOCK_TIME_DIR)/Kconfig" +endif endif -- Gitee From 1bcd5c8f163baf1d86c42dfa29cfa170ef5592cf Mon Sep 17 00:00:00 2001 From: vandoul Date: Tue, 10 Feb 2026 10:18:45 +0800 Subject: [PATCH 33/45] =?UTF-8?q?=E4=BF=AE=E5=A4=8DMCXN947=E5=BC=80?= =?UTF-8?q?=E5=8F=91=E6=9D=BFarduino=E6=8E=A5=E5=8F=A3=E4=B8=AD=E7=9A=84?= =?UTF-8?q?=E4=B8=B2=E5=8F=A3=E6=97=A0=E6=B3=95=E4=BD=BF=E7=94=A8=E4=BB=A5?= =?UTF-8?q?=E5=8F=8A=E4=B8=B2=E5=8F=A3=E5=86=8D=E9=85=8D=E7=BD=AE=E5=90=8E?= =?UTF-8?q?=E6=97=A0=E6=B3=95=E6=94=B6=E5=88=B0=E6=95=B0=E6=8D=AE=E7=9A=84?= =?UTF-8?q?=E9=97=AE=E9=A2=98.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c | 9 +++- .../mcx/mcxn/frdm-mcxn947/board/SConscript | 2 +- bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c | 51 +++++++++++++++++++ 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c index 31b457d9fe..e1790359d5 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c @@ -133,6 +133,7 @@ static rt_err_t mcx_configure(struct rt_serial_device *serial, struct serial_con { struct mcx_uart *uart; /* Serial port hardware structure, calling the structure initialized above */ lpuart_config_t config;/* It contains basic configuration parameters of the serial port, such as baud rate, data bit, stop bit, and parity check */ + rt_uint32_t irq_regval; RT_ASSERT(serial != RT_NULL); /* assert */ RT_ASSERT(cfg != RT_NULL); @@ -159,8 +160,14 @@ static rt_err_t mcx_configure(struct rt_serial_device *serial, struct serial_con config.enableTx = true; config.enableRx = true; - + + irq_regval = LPUART_GetEnabledInterrupts(uart->uart_base); LPUART_Init(uart->uart_base, &config, CLOCK_GetFreq(uart->clock_src)); + if(irq_regval & kLPUART_RxDataRegFullInterruptEnable) + { + LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); + EnableIRQ(uart->irqn); + } return RT_EOK; } diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript index 277739d361..70958fbab0 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript @@ -24,7 +24,7 @@ if GetDepend(['PKG_USING_CJSON']) and GetDepend(['PKG_USING_WEBCLIENT']): CPPPATH = [cwd, cwd + '/MCUX_Config/board'] -CPPDEFINES = ['DEBUG', 'CPU_MCXN947VDF_cm33_core0'] +CPPDEFINES = ['DEBUG', 'CPU_MCXN947VDF_cm33_core0', 'LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c index c7fd47bac4..871ed972e6 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c @@ -34,6 +34,57 @@ void SysTick_Handler(void) rt_interrupt_leave(); } +/** + * This function will initial the FlexComm mode. + * +--------+----------------+--------+--------+--------------+ + * | Signal | LPSPI | LPUART | LPI2C | LPUART+LPI2C | + * +--------+----------------+--------+--------+--------------+ + * | FC_P0 | SDO/DATA[0] | RXD | SDA | SDA | + * | FC_P1 | SCK | TXD | SCL | SCL | + * | FC_P2 | SDI/DATA[1] | RTS_b | SCLS | TXD | + * | FC_P3 | PCS[0] | CTS_b | SDAS | RXD | + * | FC_P4 | PCS[3]/DATA[3] | DSR_b | HREQ_b | CTS_b | + * | FC_P5 | PCS[2]/DATA[2] | DTR_b | — | RTS_b | + * | FC_P6 | PCS[1]/HREQ | DCD_b | — | HREQ_b | + * +--------+----------------+--------+--------+--------------+ + */ +void rt_hw_flexcomm_mode_init(void) +{ +#ifdef BSP_USING_UART2 + LP_FLEXCOMM_Init(2, LP_FLEXCOMM_PERIPH_LPI2CAndLPUART); /* FLEXCOMM2 used for LPI2C and LPUART */ +#endif +#ifdef BSP_USING_UART4 + LP_FLEXCOMM_Init(4, LP_FLEXCOMM_PERIPH_LPUART); /* FLEXCOMM4 used for LPUART */ +#endif +#ifdef BSP_USING_UART5 + LP_FLEXCOMM_Init(5, LP_FLEXCOMM_PERIPH_LPUART); /* FLEXCOMM5 used for LPUART */ +#endif +#ifdef BSP_USING_UART6 + LP_FLEXCOMM_Init(6, LP_FLEXCOMM_PERIPH_LPUART); /* FLEXCOMM6 used for LPUART */ + #endif +#ifdef BSP_USING_SPI1 + LP_FLEXCOMM_Init(2, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM2 used for LPI2C and LPUART */ +#endif +#ifdef BSP_USING_SPI3 + LP_FLEXCOMM_Init(3, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM3 used for LPSPI */ +#endif +#ifdef BSP_USING_SPI6 + LP_FLEXCOMM_Init(6, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM6 used for LPSPI */ +#endif +#ifdef BSP_USING_SPI7 + LP_FLEXCOMM_Init(7, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM7 used for LPSPI */ +#endif +#ifdef BSP_USING_I2C0 + LP_FLEXCOMM_Init(0, LP_FLEXCOMM_PERIPH_LPI2C); /* FLEXCOMM0 used for LPI2C */ +#endif +#ifdef BSP_USING_I2C1 + LP_FLEXCOMM_Init(1, LP_FLEXCOMM_PERIPH_LPI2C); /* FLEXCOMM1 used for LPI2C */ +#endif +#ifdef BSP_USING_I2C2 + LP_FLEXCOMM_Init(2, LP_FLEXCOMM_PERIPH_LPI2C); /* FLEXCOMM2 used for LPI2C */ +#endif +} + /** * This function will initial board. */ -- Gitee From c2103a5cc9e7771d07bf202ed4a20de0556445b5 Mon Sep 17 00:00:00 2001 From: Rbb666 <64397326+Rbb666@users.noreply.github.com> Date: Tue, 10 Feb 2026 11:16:11 +0800 Subject: [PATCH 34/45] =?UTF-8?q?Revert=20"=E4=BF=AE=E5=A4=8DMCXN947?= =?UTF-8?q?=E5=BC=80=E5=8F=91=E6=9D=BFarduino=E6=8E=A5=E5=8F=A3=E4=B8=AD?= =?UTF-8?q?=E7=9A=84=E4=B8=B2=E5=8F=A3=E6=97=A0=E6=B3=95=E4=BD=BF=E7=94=A8?= =?UTF-8?q?=E4=BB=A5=E5=8F=8A=E4=B8=B2=E5=8F=A3=E5=86=8D=E9=85=8D=E7=BD=AE?= =?UTF-8?q?=E5=90=8E=E6=97=A0=E6=B3=95=E6=94=B6=E5=88=B0=E6=95=B0=E6=8D=AE?= =?UTF-8?q?=E7=9A=84=E9=97=AE=E9=A2=98."?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 1bcd5c8f163baf1d86c42dfa29cfa170ef5592cf. --- bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c | 9 +--- .../mcx/mcxn/frdm-mcxn947/board/SConscript | 2 +- bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c | 51 ------------------- 3 files changed, 2 insertions(+), 60 deletions(-) diff --git a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c index e1790359d5..31b457d9fe 100644 --- a/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c +++ b/bsp/nxp/mcx/mcxn/Libraries/drivers/drv_uart.c @@ -133,7 +133,6 @@ static rt_err_t mcx_configure(struct rt_serial_device *serial, struct serial_con { struct mcx_uart *uart; /* Serial port hardware structure, calling the structure initialized above */ lpuart_config_t config;/* It contains basic configuration parameters of the serial port, such as baud rate, data bit, stop bit, and parity check */ - rt_uint32_t irq_regval; RT_ASSERT(serial != RT_NULL); /* assert */ RT_ASSERT(cfg != RT_NULL); @@ -160,14 +159,8 @@ static rt_err_t mcx_configure(struct rt_serial_device *serial, struct serial_con config.enableTx = true; config.enableRx = true; - - irq_regval = LPUART_GetEnabledInterrupts(uart->uart_base); + LPUART_Init(uart->uart_base, &config, CLOCK_GetFreq(uart->clock_src)); - if(irq_regval & kLPUART_RxDataRegFullInterruptEnable) - { - LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); - EnableIRQ(uart->irqn); - } return RT_EOK; } diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript index 70958fbab0..277739d361 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/SConscript @@ -24,7 +24,7 @@ if GetDepend(['PKG_USING_CJSON']) and GetDepend(['PKG_USING_WEBCLIENT']): CPPPATH = [cwd, cwd + '/MCUX_Config/board'] -CPPDEFINES = ['DEBUG', 'CPU_MCXN947VDF_cm33_core0', 'LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1'] +CPPDEFINES = ['DEBUG', 'CPU_MCXN947VDF_cm33_core0'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c index 871ed972e6..c7fd47bac4 100644 --- a/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn947/board/board.c @@ -34,57 +34,6 @@ void SysTick_Handler(void) rt_interrupt_leave(); } -/** - * This function will initial the FlexComm mode. - * +--------+----------------+--------+--------+--------------+ - * | Signal | LPSPI | LPUART | LPI2C | LPUART+LPI2C | - * +--------+----------------+--------+--------+--------------+ - * | FC_P0 | SDO/DATA[0] | RXD | SDA | SDA | - * | FC_P1 | SCK | TXD | SCL | SCL | - * | FC_P2 | SDI/DATA[1] | RTS_b | SCLS | TXD | - * | FC_P3 | PCS[0] | CTS_b | SDAS | RXD | - * | FC_P4 | PCS[3]/DATA[3] | DSR_b | HREQ_b | CTS_b | - * | FC_P5 | PCS[2]/DATA[2] | DTR_b | — | RTS_b | - * | FC_P6 | PCS[1]/HREQ | DCD_b | — | HREQ_b | - * +--------+----------------+--------+--------+--------------+ - */ -void rt_hw_flexcomm_mode_init(void) -{ -#ifdef BSP_USING_UART2 - LP_FLEXCOMM_Init(2, LP_FLEXCOMM_PERIPH_LPI2CAndLPUART); /* FLEXCOMM2 used for LPI2C and LPUART */ -#endif -#ifdef BSP_USING_UART4 - LP_FLEXCOMM_Init(4, LP_FLEXCOMM_PERIPH_LPUART); /* FLEXCOMM4 used for LPUART */ -#endif -#ifdef BSP_USING_UART5 - LP_FLEXCOMM_Init(5, LP_FLEXCOMM_PERIPH_LPUART); /* FLEXCOMM5 used for LPUART */ -#endif -#ifdef BSP_USING_UART6 - LP_FLEXCOMM_Init(6, LP_FLEXCOMM_PERIPH_LPUART); /* FLEXCOMM6 used for LPUART */ - #endif -#ifdef BSP_USING_SPI1 - LP_FLEXCOMM_Init(2, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM2 used for LPI2C and LPUART */ -#endif -#ifdef BSP_USING_SPI3 - LP_FLEXCOMM_Init(3, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM3 used for LPSPI */ -#endif -#ifdef BSP_USING_SPI6 - LP_FLEXCOMM_Init(6, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM6 used for LPSPI */ -#endif -#ifdef BSP_USING_SPI7 - LP_FLEXCOMM_Init(7, LP_FLEXCOMM_PERIPH_LPSPI); /* FLEXCOMM7 used for LPSPI */ -#endif -#ifdef BSP_USING_I2C0 - LP_FLEXCOMM_Init(0, LP_FLEXCOMM_PERIPH_LPI2C); /* FLEXCOMM0 used for LPI2C */ -#endif -#ifdef BSP_USING_I2C1 - LP_FLEXCOMM_Init(1, LP_FLEXCOMM_PERIPH_LPI2C); /* FLEXCOMM1 used for LPI2C */ -#endif -#ifdef BSP_USING_I2C2 - LP_FLEXCOMM_Init(2, LP_FLEXCOMM_PERIPH_LPI2C); /* FLEXCOMM2 used for LPI2C */ -#endif -} - /** * This function will initial board. */ -- Gitee From 27b2ba5556cf137a346cef4d1ad575e2d1183b48 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Sat, 7 Feb 2026 15:28:02 +0800 Subject: [PATCH 35/45] fix(CAN): Avoid double counting RX overflow drops --- components/drivers/can/dev_can.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/components/drivers/can/dev_can.c b/components/drivers/can/dev_can.c index e0cf0db9b2..04f12620f3 100644 --- a/components/drivers/can/dev_can.c +++ b/components/drivers/can/dev_can.c @@ -968,15 +968,19 @@ rt_err_t rt_hw_can_register(struct rt_can_device *can, */ void rt_hw_can_isr(struct rt_can_device *can, int event) { + rt_bool_t is_rxof_event = RT_FALSE; + switch (event & 0xff) { case RT_CAN_EVENT_RXOF_IND: { rt_base_t level; + is_rxof_event = RT_TRUE; level = rt_hw_local_irq_disable(); can->status.dropedrcvpkg++; rt_hw_local_irq_enable(level); } + /* FALLTHROUGH: RX overflow still tries to fetch one pending frame into software FIFO. */ case RT_CAN_EVENT_RX_IND: { struct rt_can_msg tmpmsg; @@ -1020,7 +1024,10 @@ void rt_hw_can_isr(struct rt_can_device *can, int event) else if (!rt_list_isempty(&rx_fifo->uselist)) { listmsg = rt_list_entry(rx_fifo->uselist.next, struct rt_can_msg_list, list); - can->status.dropedrcvpkg++; + if (!is_rxof_event) + { + can->status.dropedrcvpkg++; + } rt_list_remove(&listmsg->list); #ifdef RT_CAN_USING_HDR rt_list_remove(&listmsg->hdrlist); -- Gitee From ec5f5e678faa97a2f291c78b87ff862a67310b95 Mon Sep 17 00:00:00 2001 From: Just Chen <111217154+moment-NEW@users.noreply.github.com> Date: Tue, 10 Feb 2026 17:33:59 +0800 Subject: [PATCH 36/45] =?UTF-8?q?[docs]=20=E4=BF=AE=E5=A4=8D=20STM32=20BSP?= =?UTF-8?q?=20=E5=88=B6=E4=BD=9C=E6=95=99=E7=A8=8B=E4=B8=AD=E7=9A=84Sconsc?= =?UTF-8?q?rip=E6=96=87=E4=BB=B6=E6=95=99=E7=A8=8B=E9=94=99=E8=AF=AF=20(#1?= =?UTF-8?q?1189)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../How to make a STM32 BSP for RT-Thread.md | 34 +++++++++++++++--- ...66\344\275\234\346\225\231\347\250\213.md" | 35 ++++++++++++++++--- 2 files changed, 59 insertions(+), 10 deletions(-) diff --git a/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md b/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md index d8afb41733..95a798b17a 100644 --- a/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md +++ b/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md @@ -166,11 +166,32 @@ The other two link script files are link.icf used by IAR and link.lds used by th The **SConscript** script determines the files to be added during the generation and compilation of the MDK/IAR project. -In this step, you need to modify the chip model and the address of the chip startup file. The modification content is shown in the figure below: +In this step, you need to modify the chip model and the address of the chip startup file. There are two SConscript files in the BSP directory, and only the one in the root directory needs to be modified, as shown below: -![Modify the startup file and chip model](./figures_en/SConscript.png) +```diff +# for module compiling +import os +Import('RTT_ROOT') +Import('env') +from building import * -Note: If you cannot find the .s file of the corresponding series in the folder, it may be that multiple series of chips reuse the same startup file. At this time, you can generate the target chip project in CubeMX to see which startup file is used. Then modify the startup file name. +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +- # The following macro definition statement exists in the template before modification: +- env.Append(CPPDEFINES = ['STM32H723xx'])# Target chip macro definition, hal library will use this macro definition for judgment ++ # Modify the macro definition to the corresponding chip model. For example, for STM32F103xB, the modified content is as follows: ++ env.Append(CPPDEFINES = ['STM32F103xB']) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') +``` + +Note: Due to the BSP weight loss plan, the templates in the template directory are outdated, and the SConscript file may be different from the example. Please refer to the actual BSP or wait for an update. #### 3.4.3 Modify the project template @@ -190,6 +211,10 @@ Modify the program download method: Env tool is required to regenerate the project. +Before regenerating the project, you must execute the `pkgs --update` command in the Env tool. + +This command will automatically pull the corresponding HAL library package according to the Kconfig configuration, which is the key to subsequent compilation success. + #### 3.5.1 Regenerate the rtconfig.h file Enter the command menuconfig in the Env interface to configure the project and generate a new rtconfig.h file. As shown below: @@ -255,5 +280,4 @@ The specifications of making STM32 BSP are mainly divided into three aspects: en - Only submit documents necessary for the BSP and delete irrelevant intermediate documents. Please check other BSPs for documents that can be submitted. - When submitting libraries of different series of STM32, please refer to the HAL libraries of f1/f4 series and delete redundant library files. - Compile and test the BSP before submission to ensure that it compiles properly under different compilers. -- Perform functional tests on the BSP before submission to ensure that the BSP meets the requirements in the engineering configuration chapter before submission. - +- Perform functional tests on the BSP before submission to ensure that the BSP meets the requirements in the engineering configuration chapter before submission. diff --git "a/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" "b/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" index 4fb48c6757..a0dce17137 100644 --- "a/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" +++ "b/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" @@ -210,13 +210,35 @@ BSP 的制作过程分为如下五个步骤： #### 3.4.2 修改构建脚本 -**SConscript** 脚本决定 MDK/IAR 工程的生成以及编译过程中要添加文件。 +**SConscript** 脚本决定 MDK/IAR 工程的生成以及编译过程中要添加的文件。 -在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示： +在这一步中需要修改芯片型号以及芯片启动文件的地址，在BSP目录中存在两个SConscript文件，其中只有根目录下的需要修改，修改内容如下所示： -![修改启动文件和芯片型号](./figures/SConscript.png) +```diff +# for module compiling +import os +Import('RTT_ROOT') +Import('env') +from building import * -注意：如果在文件夹中找不到相应系列的 .s 文件，可能是多个系列的芯片重用了相同的启动文件，此时可以在 CubeMX 中生成目标芯片的工程，查看使用了哪个启动文件，然后再修改启动文件名。 +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +- # 修改前模板中的存在如下宏定义语句: +- env.Append(CPPDEFINES = ['STM32H723xx'])# 目标芯片宏定义，hal库将使用这个宏定义作判断 ++ # 修改宏定义为对应的芯片型号，例如对于STM32F103xB，修改后的内容如下： ++ env.Append(CPPDEFINES = ['STM32F103xB']) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') + + +``` +注意：由于BSP瘦身计划，template目录下的模板已经过时，SConscript文件可能与示例有所差异，请参考实际BSP或等待更新。 #### 3.4.3 修改工程模板 @@ -233,8 +255,11 @@ BSP 的制作过程分为如下五个步骤： ![配置下载方式](./figures/template_3.png) ### 3.5 重新生成工程 +工程生成需要使用 Env 工具。 + +在进行工程生成前，必须在 Env 工具中执行 `pkgs --update` 命令。 -重新生成工程需要使用 Env 工具。 +该命令会根据 Kconfig 配置自动拉取对应的 HAL 库软件包，这是后续编译成功的关键。 #### 3.5.1 重新生成 rtconfig.h 文件 -- Gitee From 9aff6f86469064f9a488ed62620a8d181eedc25e Mon Sep 17 00:00:00 2001 From: yefeng Date: Sun, 8 Feb 2026 02:01:11 +0800 Subject: [PATCH 37/45] [gd32][i2c] Add GD32VW553xx hardware I2C driver --- .../.ci/attachconfig/ci.attachconfig.yml | 13 +- bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig | 55 ++ .../risc-v/libraries/gd32_drivers/SConscript | 3 + .../risc-v/libraries/gd32_drivers/drv_i2c.c | 744 ++++++++++++++++++ .../risc-v/libraries/gd32_drivers/drv_i2c.h | 33 + 5 files changed, 847 insertions(+), 1 deletion(-) create mode 100644 bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.c create mode 100644 bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.h diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml b/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml index 24dc154586..e8bbc5bc5f 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml @@ -6,4 +6,15 @@ scons.args: &scons component.pwm: kconfig: - CONFIG_BSP_USING_PWM=y - - CONFIG_BSP_USING_PWM0=y \ No newline at end of file + - CONFIG_BSP_USING_PWM0=y + +# ------ devices ------ +devices.i2c: + kconfig: + - CONFIG_BSP_USING_HW_I2C=y + - CONFIG_BSP_USING_HW_I2C0=y + - CONFIG_BSP_HW_I2C0_PIN_PA2_PA3=y + - CONFIG_BSP_HW_I2C0_CLK=100 + - CONFIG_BSP_USING_HW_I2C1=y + - CONFIG_BSP_HW_I2C1_PIN_PB12_PB13=y + - CONFIG_BSP_HW_I2C1_CLK=100 \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig index 433c305712..e0668401c9 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig @@ -79,8 +79,63 @@ menu "On-chip Peripheral Drivers" bool "Enable PWM16" default n endif + menuconfig BSP_USING_HW_I2C + bool "Enable Hardware I2C" + default n + select RT_USING_I2C + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C0 + bool "Enable Hardware I2C0" + default n + # config i2c0 pins + choice + prompt "Select I2C0 pins" + depends on BSP_USING_HW_I2C0 + config BSP_HW_I2C0_PIN_PA2_PA3 + bool "SCL=PA2, SDA=PA3" + config BSP_HW_I2C0_PIN_PA15_PC8 + bool "SCL=PA15, SDA=PC8" + config BSP_HW_I2C0_PIN_PB0_PB1 + bool "SCL=PB0, SDA=PB1" + config BSP_HW_I2C0_PIN_PB15_PA8 + bool "SCL=PB15, SDA=PA8" + endchoice + + # config i2c0 clock + config BSP_HW_I2C0_CLK + int "I2C0 clock frequency(KHz)" + default 100 + depends on BSP_USING_HW_I2C0 + range 10 1000 + + config BSP_USING_HW_I2C1 + bool "Enable Hardware I2C1" + default n + # config i2c1 pins + choice + prompt "Select I2C1 pins" + depends on BSP_USING_HW_I2C1 + config BSP_HW_I2C1_PIN_PA6_PA7 + bool "SCL=PA6, SDA=PA7" + config BSP_HW_I2C1_PIN_PA13_PA14 + bool "SCL=PA13, SDA=PA14" + config BSP_HW_I2C1_PIN_PA15_PC8 + bool "SCL=PA15, SDA=PC8" + config BSP_HW_I2C1_PIN_PB12_PB13 + bool "SCL=PB12, SDA=PB13" + config BSP_HW_I2C1_PIN_PB15_PA8 + bool "SCL=PB15, SDA=PA8" + endchoice + + # config i2c1 clock + config BSP_HW_I2C1_CLK + int "I2C1 clock frequency(KHz)" + default 100 + depends on BSP_USING_HW_I2C1 + range 10 1000 + endif source "$(BSP_DIR)/../libraries/gd32_drivers/Kconfig" diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript b/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript index 4dedb95150..daae3a9fd9 100644 --- a/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/SConscript @@ -20,6 +20,9 @@ if GetDepend(['RT_USING_SERIAL']): if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3'): src += ['drv_soft_i2c.c'] +if GetDepend(['RT_USING_I2C', 'BSP_USING_HW_I2C']): + if GetDepend('BSP_USING_HW_I2C0') or GetDepend('BSP_USING_HW_I2C1'): + src += ['drv_i2c.c'] # add spi drivers. if GetDepend('RT_USING_SPI'): diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.c b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.c new file mode 100644 index 0000000000..2a4de1b6d5 --- /dev/null +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.c @@ -0,0 +1,744 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-13 yefeng first implementation for GD32VW55x + */ + +#include "drv_i2c.h" + +#if defined(RT_USING_I2C) && defined(BSP_USING_HW_I2C) + +#if !defined(BSP_USING_HW_I2C0) && !defined(BSP_USING_HW_I2C1) +#error "Please define at least one BSP_USING_HW_I2Cx" + /* This driver can be enabled in menuconfig: + * Hardware Drivers Config -> + * On-chip Peripheral Drivers -> + * Enable Hardware I2C + */ +#endif + +#if defined(SOC_SERIES_GD32VF103V) +#error "not implement GD32VF103V i2c support!" +#endif + +#define DBG_TAG "drv.i2c" +#ifdef RT_I2C_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_ERROR +#endif +#include + +#define I2C_TIME_OUT (uint32_t)(20000) +#define MAX_RELOAD_SIZE 255 + +typedef enum +{ + I2C_PROC_START = 0, + I2C_PROC_READ_INIT, + I2C_PROC_TRANSMIT_DATA, + I2C_PROC_RELOAD, + I2C_PROC_STOP, + I2C_PROC_END +} i2c_process_enum; + +struct gd32_pin_cfg_param +{ + uint32_t rcu[2]; + uint32_t af[2]; + uint32_t port[2]; + uint32_t pin[2]; +}; + +/** + * @brief i2c configuration params + * + */ +static struct gd32_i2c_config i2c_config[] = { +#ifdef BSP_USING_HW_I2C0 + { + "i2c0", + I2C0, + RCU_I2C0, + BSP_HW_I2C0_CLK, + }, +#endif +#ifdef BSP_USING_HW_I2C1 + { + "i2c1", + I2C1, + RCU_I2C1, + BSP_HW_I2C1_CLK, + }, +#endif +}; + +/** + * @brief i2c pin configuration param array + * + */ +static const struct gd32_pin_cfg_param pin_param[] = { +#if defined(BSP_USING_HW_I2C0) + { +#if defined(BSP_HW_I2C0_PIN_PA2_PA3) + .rcu = { RCU_GPIOA, RCU_GPIOA }, + .af = { GPIO_AF_4, GPIO_AF_4 }, + .port = { GPIOA, GPIOA }, + .pin = { GPIO_PIN_2, GPIO_PIN_3 } +#elif defined(BSP_HW_I2C0_PIN_PA15_PC8) + .rcu = { RCU_GPIOA, RCU_GPIOC }, + .af = { GPIO_AF_4, GPIO_AF_4 }, + .port = { GPIOA, GPIOC }, + .pin = { GPIO_PIN_15, GPIO_PIN_8 } +#elif defined(BSP_HW_I2C0_PIN_PB0_PB1) + .rcu = { RCU_GPIOB, RCU_GPIOB }, + .af = { GPIO_AF_6, GPIO_AF_6 }, + .port = { GPIOB, GPIOB }, + .pin = { GPIO_PIN_0, GPIO_PIN_1 } +#elif defined(BSP_HW_I2C0_PIN_PB15_PA8) + .rcu = { RCU_GPIOB, RCU_GPIOA }, + .af = { GPIO_AF_4, GPIO_AF_5 }, + .port = { GPIOB, GPIOA }, + .pin = { GPIO_PIN_15, GPIO_PIN_8 } +#else +#error "i2c0 not support pin" +#endif + }, +#endif + +#if defined(BSP_USING_HW_I2C1) + { +#if defined(BSP_HW_I2C1_PIN_PA6_PA7) + .rcu = { RCU_GPIOA, RCU_GPIOA }, + .af = { GPIO_AF_4, GPIO_AF_0 }, + .port = { GPIOA, GPIOA }, + .pin = { GPIO_PIN_6, GPIO_PIN_7 } +#elif defined(BSP_HW_I2C1_PIN_PA13_PA14) + .rcu = { RCU_GPIOA, RCU_GPIOA }, + .af = { GPIO_AF_6, GPIO_AF_6 }, + .port = { GPIOA, GPIOA }, + .pin = { GPIO_PIN_13, GPIO_PIN_14 } +#elif defined(BSP_HW_I2C1_PIN_PA15_PC8) + .rcu = { RCU_GPIOA, RCU_GPIOC }, + .af = { GPIO_AF_6, GPIO_AF_6 }, + .port = { GPIOA, GPIOC }, + .pin = { GPIO_PIN_15, GPIO_PIN_8 } +#elif defined(BSP_HW_I2C1_PIN_PB12_PB13) + .rcu = { RCU_GPIOB, RCU_GPIOB }, + .af = { GPIO_AF_6, GPIO_AF_6 }, + .port = { GPIOB, GPIOB }, + .pin = { GPIO_PIN_12, GPIO_PIN_13 } +#elif defined(BSP_HW_I2C1_PIN_PB15_PA8) + .rcu = { RCU_GPIOB, RCU_GPIOA }, + .af = { GPIO_AF_6, GPIO_AF_6 }, + .port = { GPIOB, GPIOA }, + .pin = { GPIO_PIN_15, GPIO_PIN_8 } +#else +#error "i2c1 not support pin" +#endif + }, +#endif +}; + +/** + * @brief Device object + * + */ +static struct gd32_i2c_device i2c_obj[sizeof(i2c_config) / sizeof(i2c_config[0])] = { 0 }; + +/** + * @brief i2c read + * + * @param device operate device + * @param msg deal i2c message pointer + * @return rt_err_t return RT_OK if success, other value failed. + */ +static rt_err_t gd32_i2c_read(struct gd32_i2c_device *device, struct rt_i2c_msg *msg) +{ + rt_err_t ret = RT_EOK; + i2c_process_enum state = I2C_PROC_READ_INIT; + rt_uint32_t timeout = 0; + rt_uint8_t end_flag = 0; + rt_uint8_t first_reload_flag = 1; + rt_uint8_t reload_mode_flag = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(msg != RT_NULL); + + rt_uint32_t i2c_periph = device->config->i2c_periph; + rt_uint16_t nbytes_reload = 0; + rt_uint16_t number_of_byte = msg->len; + rt_uint8_t *p_buffer = msg->buf; + + while (!end_flag) + { + switch (state) + { + case I2C_PROC_START: + /* start */ + i2c_start_on_bus(i2c_periph); + state = I2C_PROC_TRANSMIT_DATA; + break; + case I2C_PROC_READ_INIT: + /* configure the device address */ + i2c_master_addressing(i2c_periph, msg->addr << 1, I2C_MASTER_RECEIVE); + /* disable I2C automatic end mode in master mode */ + i2c_automatic_end_disable(i2c_periph); + state = I2C_PROC_RELOAD; + break; + case I2C_PROC_RELOAD: + if (number_of_byte > MAX_RELOAD_SIZE) + { + number_of_byte = number_of_byte - MAX_RELOAD_SIZE; + nbytes_reload = MAX_RELOAD_SIZE; + reload_mode_flag = 1; + } + else + { + nbytes_reload = number_of_byte; + reload_mode_flag = 0; + } + + LOG_D("configure number of bytes: %d", nbytes_reload); + /* configure number of bytes to be transferred */ + i2c_transfer_byte_number_config(i2c_periph, nbytes_reload); + + if (reload_mode_flag) + { + LOG_D("enable I2C reload mode"); + /* enable I2C reload mode */ + i2c_reload_enable(i2c_periph); + } + else + { + LOG_D("disable I2C reload mode"); + /* disable I2C reload mode */ + i2c_reload_disable(i2c_periph); + } + + if (first_reload_flag) + { + LOG_D("first reload"); + first_reload_flag = 0; + state = I2C_PROC_START; + } + else + { + state = I2C_PROC_TRANSMIT_DATA; + } + break; + case I2C_PROC_TRANSMIT_DATA: + LOG_D("read: transmit data: %d", nbytes_reload); + timeout = 0; + while (nbytes_reload) + { + /* wait until the RBNE bit is set and clear it */ + if (i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) + { + /* read a byte from the device */ + *p_buffer = i2c_data_receive(i2c_periph); + /* point to the next location where the byte read will be saved */ + p_buffer++; + /* decrement the read bytes counter */ + nbytes_reload--; + + /* reset timeout counter */ + timeout = 0; + } + else + { + timeout++; + if (timeout >= I2C_TIME_OUT) + { + LOG_E("receive data timeout, end"); + ret = -RT_ETIMEOUT; + return ret; + } + } + } + + LOG_D("read: transmit data end"); + timeout = 0; + + /* check if the reload mode is enabled or not */ + if (I2C_CTL1(i2c_periph) & I2C_CTL1_RELOAD) + { + /* wait for TCR flag */ + while ((!i2c_flag_get(i2c_periph, I2C_FLAG_TCR)) && (timeout < I2C_TIME_OUT)) + { + timeout++; + } + + if (timeout < I2C_TIME_OUT) + { + LOG_D("reload read complete"); + state = I2C_PROC_RELOAD; + } + else + { + LOG_E("reload read timeout, end"); + ret = -RT_ETIMEOUT; + state = I2C_PROC_END; + } + } + else + { + LOG_D("read complete"); + + /* wait for TCR flag */ + while ((!i2c_flag_get(i2c_periph, I2C_FLAG_TC)) && (timeout < I2C_TIME_OUT)) + { + timeout++; + } + + if (timeout < I2C_TIME_OUT) + { + if (msg->flags & RT_I2C_NO_STOP) + { + LOG_D("no stop end"); + state = I2C_PROC_END; + } + else + { + LOG_D("generate a STOP"); + i2c_stop_on_bus(i2c_periph); + state = I2C_PROC_STOP; + } + } + else + { + LOG_E("read timeout, end"); + ret = -RT_ETIMEOUT; + state = I2C_PROC_END; + } + } + break; + case I2C_PROC_STOP: + /* wait until the stop condition is finished */ + while ((!i2c_flag_get(i2c_periph, I2C_FLAG_STPDET)) && (timeout < I2C_TIME_OUT)) + { + timeout++; + } + + if (timeout < I2C_TIME_OUT) + { + /* clear STPDET flag */ + i2c_flag_clear(i2c_periph, I2C_FLAG_STPDET); + timeout = 0; + state = I2C_PROC_END; + } + else + { + timeout = 0; + state = I2C_PROC_END; + ret = -RT_ETIMEOUT; + LOG_E("i2c master sends stop signal timeout in read!\n"); + } + break; + case I2C_PROC_END: + end_flag = 1; + timeout = 0; + break; + default: + /* default status */ + end_flag = 1; + timeout = 0; + LOG_E("i2c state unknown, end!\n"); + } + } + + return ret; +} + +/** + * @brief i2c write + * + * @param device operate device + * @param msg deal i2c message pointer + * @return rt_err_t return RT_OK if success, other value failed. + */ +static rt_err_t gd32_i2c_write(struct gd32_i2c_device *device, struct rt_i2c_msg *msg) +{ + rt_err_t ret = RT_EOK; + i2c_process_enum state = I2C_PROC_RELOAD; + rt_uint16_t timeout = 0; + rt_uint8_t start_flag = 0; + rt_uint8_t end_flag = 0; + rt_uint8_t reload_mode_flag = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(msg != RT_NULL); + + rt_uint32_t i2c_periph = device->config->i2c_periph; + rt_uint16_t number_of_byte = msg->len; + rt_uint16_t nbytes_reload = 0; + rt_uint8_t *p_buffer = msg->buf; + + if (msg->flags & RT_I2C_NO_START) + { + start_flag = 0; + } + else + { + start_flag = 1; + } + + /* configure the device address */ + i2c_master_addressing(i2c_periph, msg->addr << 1, I2C_MASTER_TRANSMIT); + /* disable I2C automatic end mode in master mode */ + i2c_automatic_end_disable(i2c_periph); + + while (!end_flag) + { + switch (state) + { + case I2C_PROC_START: + /* start */ + LOG_D("generate a START"); + timeout = 0; + i2c_start_on_bus(i2c_periph); + state = I2C_PROC_TRANSMIT_DATA; + break; + case I2C_PROC_RELOAD: + if (number_of_byte > MAX_RELOAD_SIZE) + { + number_of_byte = number_of_byte - MAX_RELOAD_SIZE; + nbytes_reload = MAX_RELOAD_SIZE; + reload_mode_flag = 1; + } + else + { + nbytes_reload = number_of_byte; + reload_mode_flag = 0; + } + + LOG_D("configure number of bytes: %d", nbytes_reload); + + /* configure number of bytes to be transferred */ + i2c_transfer_byte_number_config(i2c_periph, nbytes_reload); + + if (reload_mode_flag) + { + LOG_D("enable I2C reload mode"); + /* enable I2C reload mode */ + i2c_reload_enable(i2c_periph); + } + else + { + LOG_D("disable I2C reload mode"); + /* disable I2C reload mode */ + i2c_reload_disable(i2c_periph); + } + + if (start_flag) + { + start_flag = 0; + state = I2C_PROC_START; + } + else + { + state = I2C_PROC_TRANSMIT_DATA; + } + break; + case I2C_PROC_TRANSMIT_DATA: + timeout = 0; + LOG_D("master transmit bytes: %d", nbytes_reload); + while (nbytes_reload--) + { + /* wait until TI bit is set */ + while ((!i2c_flag_get(i2c_periph, I2C_FLAG_TI)) && (timeout < I2C_TIME_OUT)) + { + timeout++; + } + + if (timeout < I2C_TIME_OUT) + { + /* while there is data to be written */ + i2c_data_transmit(i2c_periph, *p_buffer); + /* point to the next byte to be written */ + p_buffer++; + timeout = 0; + } + else + { + /* wait TI timeout */ + LOG_E("i2c master sends data timeout when write!"); + ret = -RT_ETIMEOUT; + return ret; + } + } + + if (timeout < I2C_TIME_OUT) + { + rt_uint32_t wait_flag; + + /* check if the reload mode is enabled or not */ + if (I2C_CTL1(i2c_periph) & I2C_CTL1_RELOAD) + { + wait_flag = I2C_FLAG_TCR; + } + else + { + wait_flag = I2C_FLAG_TC; + } + + timeout = 0; + + /* wait TCR/TC bit is set */ + while ((!i2c_flag_get(i2c_periph, wait_flag)) && (timeout < I2C_TIME_OUT)) + { + timeout++; + } + + if (timeout < I2C_TIME_OUT) + { + if (reload_mode_flag) + { + state = I2C_PROC_RELOAD; + } + else + { + if (msg->flags & RT_I2C_NO_STOP) + { + state = I2C_PROC_END; + } + else + { + LOG_D("generate a STOP"); + i2c_stop_on_bus(i2c_periph); + state = I2C_PROC_STOP; + } + } + } + else + { + LOG_E("i2c master wait %s timeout, end!", (wait_flag == I2C_FLAG_TCR) ? "TCR" : "TC"); + state = I2C_PROC_END; + ret = -RT_ETIMEOUT; + } + } + else + { + LOG_E("i2c master send data timeout when write!"); + state = I2C_PROC_END; + ret = -RT_ETIMEOUT; + } + break; + case I2C_PROC_STOP: + timeout = 0; + /* wait until the stop condition is finished */ + while ((!i2c_flag_get(i2c_periph, I2C_FLAG_STPDET)) && (timeout < I2C_TIME_OUT)) + { + timeout++; + } + + if (timeout < I2C_TIME_OUT) + { + /* clear STPDET flag */ + i2c_flag_clear(i2c_periph, I2C_FLAG_STPDET); + } + else + { + /* stop detect timeout */ + LOG_E("i2c master sends stop signal timeout when write!"); + ret = -RT_ETIMEOUT; + } + + state = I2C_PROC_END; + break; + case I2C_PROC_END: + LOG_D("END"); + end_flag = 1; + break; + default: + /* default status */ + state = I2C_PROC_START; + end_flag = 1; + timeout = 0; + LOG_E("i2c master unknown state, end!\n"); + } + } + + return ret; +} + +/** + * @brief configure i2c alternate pin + * + * @param param configure param + */ +static void gd32_i2c_pin_configure(const struct gd32_pin_cfg_param *param) +{ + for (rt_uint8_t i = 0; i < 2; i++) + { + /* enable GPIO clock */ + rcu_periph_clock_enable(param->rcu[i]); + + /* connect I2C_SCL_PIN to I2C_SCL */ + gpio_af_set(param->port[i], param->af[i], param->pin[i]); + + /* configure GPIO pins of I2C */ + gpio_mode_set(param->port[i], GPIO_MODE_AF, GPIO_PUPD_PULLUP, param->pin[i]); + gpio_output_options_set(param->port[i], GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, param->pin[i]); + } +} + +/** + * @brief configure i2c timing + * + * @param i2c_cfg param pointer + * + * @note tSCL=tSYNC1+tSYNC2+{[(SCLH[7:0]+1)+(SLLL[7:0]+1)]*(PSC+1)*tI2CCLK} + */ +static void gd32_i2c_timing_configure(struct gd32_i2c_config *i2c_cfg) +{ +#define I2C_CLK_PSC_LOW 15 +#define I2C_CLK_PSC_STAND 7 +#define I2C_CLK_PSC_FAST 1 +#define I2C_SCLDELY_LOW 9 +#define I2C_SCLDELY_FAST 3 +#define I2C_SDADELY 0 + + rt_uint32_t i2c_freq; + rt_uint32_t sclh_scll; + rt_uint8_t clk_psc; + rt_uint8_t scldely; + + if (i2c_cfg->i2c_periph == I2C0) + { + i2c_freq = rcu_clock_freq_get(CK_I2C0); + } + else if (i2c_cfg->i2c_periph == I2C1) + { + /* I2C1 use APB1 clock */ + i2c_freq = rcu_clock_freq_get(CK_APB1); + } + else + { + i2c_freq = rcu_clock_freq_get(CK_APB1); + } + + if (i2c_cfg->speed < 100) + { + clk_psc = I2C_CLK_PSC_LOW; + scldely = I2C_SCLDELY_LOW; + } + else if (i2c_cfg->speed <= 400) + { + clk_psc = I2C_CLK_PSC_STAND; + scldely = I2C_SCLDELY_LOW; + } + else + { + clk_psc = I2C_CLK_PSC_STAND; + scldely = I2C_SCLDELY_FAST; + } + + /* configure I2C timing */ + i2c_timing_config(i2c_cfg->i2c_periph, clk_psc, scldely, I2C_SDADELY); + + sclh_scll = (i2c_freq / (1000 * i2c_cfg->speed) - (I2C_SDADELY * (clk_psc + 1) + 1) - (scldely + 1) * (clk_psc + 1)) / (clk_psc + 1) - 2; + + i2c_master_clock_config(i2c_cfg->i2c_periph, sclh_scll / 2, sclh_scll / 2); +} + +/** + * @brief configure i2c clock, timing, enable i2c + * + * @param i2c_cfg + */ +static void gd32_i2c_configure(struct gd32_i2c_config *i2c_cfg) +{ + RT_ASSERT(i2c_cfg != RT_NULL); + + /* enable i2c clock */ + rcu_periph_clock_enable(i2c_cfg->rcu_clk); + + /* reset I2C */ + i2c_disable(i2c_cfg->i2c_periph); + + /* i2c timing config MUST at I2CEN = 0 */ + gd32_i2c_timing_configure(i2c_cfg); + + /* enable I2C */ + i2c_enable(i2c_cfg->i2c_periph); +} + +static rt_ssize_t gd32_i2c_xfer(struct rt_i2c_bus_device *device, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_uint16_t last_flags; + + RT_ASSERT(device != RT_NULL); + + struct gd32_i2c_device *i2c_obj = (struct gd32_i2c_device *)(device); + struct gd32_i2c_config *i2c_cfg = (struct gd32_i2c_config *)(i2c_obj->config); + + RT_ASSERT(i2c_cfg != RT_NULL); + + for (i = 0; i < num; i++) + { + rt_err_t ret; + msg = &msgs[i]; + + if (msg->flags & RT_I2C_ADDR_10BIT) + { + LOG_E("not implement 10bit address mode"); + return -RT_ENOSYS; + } + + if (msg->flags & RT_I2C_RD) + { + ret = gd32_i2c_read(i2c_obj, msg); + } + else + { + ret = gd32_i2c_write(i2c_obj, msg); + } + + if (ret != RT_EOK) + { + break; + } + } + + return i; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = { gd32_i2c_xfer, RT_NULL, RT_NULL }; + +static int rt_hw_i2c_init(void) +{ + rt_uint8_t index; + rt_size_t obj_num; + rt_err_t result = 0; + + obj_num = sizeof(i2c_obj) / sizeof(struct gd32_i2c_device); + + for (index = 0; index < obj_num; index++) + { + /* init i2c object */ + i2c_obj[index].config = &i2c_config[index]; + i2c_obj[index].parent.ops = &i2c_ops; + + /* init i2c pin */ + gd32_i2c_pin_configure(&pin_param[index]); + + /* init i2c device */ + gd32_i2c_configure(&i2c_config[index]); + + /* register i2c device */ + result = rt_i2c_bus_device_register(&i2c_obj[index].parent, i2c_obj[index].config->name); + RT_ASSERT(result == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* defined(RT_USING_I2C) && defined(BSP_USING_HW_I2C) */ diff --git a/bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.h b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.h new file mode 100644 index 0000000000..e4f60f5ef6 --- /dev/null +++ b/bsp/gd32/risc-v/libraries/gd32_drivers/drv_i2c.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2026, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-01-13 yefeng first implementation. + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include +#include +#include + +struct gd32_i2c_config +{ + const char *name; + rt_uint32_t i2c_periph; + rcu_periph_enum rcu_clk; + rt_uint32_t speed; +}; + +struct gd32_i2c_device +{ + struct rt_i2c_bus_device parent; + struct gd32_i2c_config *config; +}; + +#endif -- Gitee From 9412a2899d08c3ef806accf0335bda2397c326de Mon Sep 17 00:00:00 2001 From: O-O-BOOK Date: Fri, 6 Feb 2026 16:51:55 +0800 Subject: [PATCH 38/45] [style][components/fal_rtt] misrac style --- components/fal/src/fal_rtt.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/components/fal/src/fal_rtt.c b/components/fal/src/fal_rtt.c index 077191e102..5f4492cf57 100644 --- a/components/fal/src/fal_rtt.c +++ b/components/fal/src/fal_rtt.c @@ -167,7 +167,8 @@ struct rt_device *fal_blk_device_create(const char *parition_name) return NULL; } - if ((fal_flash = fal_flash_device_find(fal_part->flash_name)) == NULL) + fal_flash = fal_flash_device_find(fal_part->flash_name); + if (fal_flash == NULL) { LOG_E("Error: the flash device name (%s) is not found.", fal_part->flash_name); return NULL; @@ -309,7 +310,8 @@ struct rt_device *fal_mtd_nor_device_create(const char *parition_name) return NULL; } - if ((fal_flash = fal_flash_device_find(fal_part->flash_name)) == NULL) + fal_flash = fal_flash_device_find(fal_part->flash_name); + if (fal_flash == NULL) { LOG_E("Error: the flash device name (%s) is not found.", fal_part->flash_name); return NULL; @@ -620,19 +622,24 @@ static void fal(rt_uint8_t argc, char **argv) { if (argc >= 3) { char *dev_name = argv[2]; - if ((flash_dev = fal_flash_device_find(dev_name)) != NULL) + flash_dev = fal_flash_device_find(dev_name); + if (flash_dev != NULL) { part_dev = NULL; } - else if ((part_dev = fal_partition_find(dev_name)) != NULL) - { - flash_dev = NULL; - } else { - rt_kprintf("Device %s NOT found. Probe failed.\n", dev_name); - flash_dev = NULL; - part_dev = NULL; + part_dev = fal_partition_find(dev_name); + if (part_dev != NULL) + { + flash_dev = NULL; + } + else + { + rt_kprintf("Device %s NOT found. Probe failed.\n", dev_name); + flash_dev = NULL; + part_dev = NULL; + } } } -- Gitee From db6c0ddbf333be65f5ddc990ee63a200f768a9f7 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 12 Feb 2026 08:57:46 +0800 Subject: [PATCH 39/45] feat(console): Add console output enable switch - rt_console_output_enabled()/rt_console_output_is_enabled() gate rt_kprintf/rt_kputs output with the switch --- include/rtthread.h | 7 +++++++ src/Kconfig | 12 ++++++++++++ src/kservice.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/include/rtthread.h b/include/rtthread.h index 7f97c068cd..a87515907e 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -783,6 +783,13 @@ void rt_components_board_init(void); #else int rt_kprintf(const char *fmt, ...); void rt_kputs(const char *str); +#ifdef RT_USING_CONSOLE_OUTPUT_CTL +void rt_console_output_set_enabled(rt_bool_t enabled); +rt_bool_t rt_console_output_get_enabled(void); +#else +#define rt_console_output_set_enabled(enabled) ((void)0) +#define rt_console_output_get_enabled() (RT_TRUE) +#endif /* RT_USING_CONSOLE_OUTPUT_CTL */ #endif /* RT_USING_CONSOLE */ rt_err_t rt_backtrace(void); diff --git a/src/Kconfig b/src/Kconfig index f57b305ca2..d278169da0 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -430,6 +430,18 @@ if RT_USING_CONSOLE string "the device name for console" default "uart1" + config RT_USING_CONSOLE_OUTPUT_CTL + bool "Enable runtime console output control" + default y + help + Enable runtime control for console output. + When enabled, rt_console_output_set_enabled() and + rt_console_output_get_enabled() can be used to switch + rt_kputs()/rt_kprintf() output on or off dynamically. + + When disabled, these APIs are not compiled as real symbols and + output path has no runtime check, so console output stays enabled. + endif config RT_VER_NUM diff --git a/src/kservice.c b/src/kservice.c index 259eac9a70..29c9022c89 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -208,6 +208,32 @@ rt_device_t rt_console_set_device(const char *name) RTM_EXPORT(rt_console_set_device); #endif /* RT_USING_DEVICE */ +#ifdef RT_USING_CONSOLE_OUTPUT_CTL +static volatile rt_bool_t _console_output_enabled = RT_TRUE; + +/** + * @brief Enable or disable console log output. + * + * @param enabled RT_TRUE to enable output, RT_FALSE to disable output. + */ +void rt_console_output_set_enabled(rt_bool_t enabled) +{ + _console_output_enabled = enabled; +} +RTM_EXPORT(rt_console_output_set_enabled); + +/** + * @brief Get current console log output enable state. + * + * @return RT_TRUE if output is enabled, RT_FALSE otherwise. + */ +rt_bool_t rt_console_output_get_enabled(void) +{ + return _console_output_enabled; +} +RTM_EXPORT(rt_console_output_get_enabled); +#endif /* RT_USING_CONSOLE_OUTPUT_CTL */ + rt_weak void rt_hw_console_output(const char *str) { /* empty console output */ @@ -346,6 +372,11 @@ void rt_kputs(const char *str) return; } + if (!rt_console_output_get_enabled()) + { + return; + } + _kputs(str, rt_strlen(str)); } @@ -362,6 +393,11 @@ rt_weak int rt_kprintf(const char *fmt, ...) rt_size_t length = 0; static char rt_log_buf[RT_CONSOLEBUF_SIZE]; + if (!rt_console_output_get_enabled()) + { + return 0; + } + va_start(args, fmt); PRINTF_BUFFER_TAKE; -- Gitee From aa79cd8ac547caf01f281d81e9c1d12a8405f6ca Mon Sep 17 00:00:00 2001 From: theqengineer Date: Wed, 11 Feb 2026 16:52:34 +0800 Subject: [PATCH 40/45] [bsp][stm32]: correct the errors in README of U series --- bsp/stm32/stm32u575-st-nucleo/README.md | 2 +- bsp/stm32/stm32u585-iot02a/README.md | 335 +++++------------------- bsp/stm32/stm32u585-iot02a/README_zh.md | 2 +- 3 files changed, 64 insertions(+), 275 deletions(-) diff --git a/bsp/stm32/stm32u575-st-nucleo/README.md b/bsp/stm32/stm32u575-st-nucleo/README.md index 4d949ae251..5374cca90b 100644 --- a/bsp/stm32/stm32u575-st-nucleo/README.md +++ b/bsp/stm32/stm32u575-st-nucleo/README.md @@ -2,7 +2,7 @@ **English** | [中文](README_zh.md) -## MCU: STM32U575ZI @110MHz, 2048 KB FLASH, 786 KB RAM +## MCU: STM32U575ZI @160MHz, 2048 KB FLASH, 786 KB RAM The STM32U575xx devices belong to an ultra-low-power microcontrollers family (STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz. diff --git a/bsp/stm32/stm32u585-iot02a/README.md b/bsp/stm32/stm32u585-iot02a/README.md index 4d949ae251..db527711c6 100644 --- a/bsp/stm32/stm32u585-iot02a/README.md +++ b/bsp/stm32/stm32u585-iot02a/README.md @@ -1,317 +1,106 @@ -# Part I : NUCLEO-STM32U575ZI-Q- BSP Introduction +# Part 1: STM32 B-U585I-IOT02A Development Board BSP Description **English** | [中文](README_zh.md) -## MCU: STM32U575ZI @110MHz, 2048 KB FLASH, 786 KB RAM +## Introduction -The STM32U575xx devices belong to an ultra-low-power microcontrollers family (STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz. +This document provides the BSP (Board Support Package) description for the STM32 B-U585I-IOT02A development board, contributed by Zheng-Bicheng. -The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all the Arm® single-precision data-processing instructions and all the data types. +Main contents include: -The Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions and a MPU (memory protection unit) that enhances the application security. +- Development board resource introduction +- BSP quick start guide +- Advanced usage -The devices embed high-speed memories (up to 2 Mbytes of Flash memory and 786 Kbytes of SRAM), a FSMC (flexible external memory controller) for static memories (for devices with packages of 90 pins and more), two Octo-SPI Flash memory interfaces (at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. +By reading the quick start guide, developers can quickly get started with this BSP and run RT-Thread on the development board. The advanced usage guide will introduce more advanced features to help developers utilize RT-Thread to drive more onboard resources. -The devices offer security foundation compliant with the TBSA (trusted-based security architecture) requirements from Arm®. It embeds the necessary security features to implement a secure boot, secure data storage and secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature, that allows the customer to secure the provisioning of the code during its production. A flexible lifecycle is managed thanks to multiple levels of readout protection and debug unlock with password. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories. +## Development Board Introduction -The devices feature several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, secure and hide protection areas. +STM32 B-U585I-IOT02A is a development board launched by ST based on the ARM Cortex-M33 core, with a maximum frequency of 160 MHz. This development board has rich onboard resources and can fully utilize the performance of the STM32U575 chip. -The devices embed several peripherals reinforcing security: with DPA resistancea HASH hardware accelerator, and a true random number generator. +The development board appearance is shown below: -The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications. +![board](https://www.st.com/bin/ecommerce/api/image.PF271412.en.feature-description-include-personalized-no-cpn-large.jpg) -The devices offer one fast 14-bit ADC (2.5 Msps), one 12-bit ADC (2.5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and four 16-bit low-power timers. +Common **onboard resources** of this development board include: -The devices support a MDF (multi-function digital filter) with six filters dedicated to the connection of external sigma-delta modulators. Another low-power digital filter dedicated to audio signals is embedded (ADF), with one filter supporting sound-activity detection. The devices embed also a Chrom-ART Accelerator dedicated to graphic applications, and mathematical accelerators (a trigonometric functions accelerator plus a filter mathematical accelerator). In addition, up to 24 capacitive sensing channels are available. +- MCU: STM32U585AIIxQ, 160 MHz main frequency, 2048KB FLASH, 786KB RAM +- Common interfaces: USB to serial, USB interface, Arduino interface, etc. +- Debug interface: standard ST-Link -The devices also feature standard and advanced communication interfaces such as: four I2Cs, three SPIs, three USARTs, two UARTs, one low-power UART, two SAIs, one digital camera interface (DCMI), two SDMMCs, one FDCAN, one USB OTG full-speed, one USB Type-C /USB Power Delivery controller, and one generic synchronous 8-/16-bit PSSI (parallel data input/output slave interface). +For more detailed information about the development board, please refer to [STM32 B-U585I-IOT02A](https://www.st.com/zh/evaluation-tools/b-u585i-iot02a.html). -The devices operate in the –40 to +85 °C (+105 °C junction) and –40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. +## Peripheral Support -A comprehensive set of power-saving modes allow the design of low-power applications. Many peripherals (including communication, analog, timers and audio peripherals) can be functional and autonomous down to Stop mode with direct memory access, thanks to LPBAM support (low-power background autonomous mode). +Current peripheral support status of this BSP: -Some independent power supplies are supported like an analog independent supply input for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available for connecting a backup battery in order to preserve the RTC functionality and to backup 3232-bit registers and 2-Kbyte SRAM. +| **Onboard Peripherals** | **Support Status** | **Notes** | +|:---------|:--------:|:-------| +| USB Virtual Serial Port | Supported | | +| **On-chip Peripherals** | **Support Status** | **Notes** | +| GPIO | Supported | | +| UART | Supported | UART1 | -The devices offer eight packages from 48 to 169 pins. -#### KEY FEATURES +## Usage Instructions -- Includes ST state-of-the-art patented technology +The usage instructions are divided into the following two sections: -- Ultra-low-power with FlexPowerControl - - 1.71 V to 3.6 V power supply - - –40 °C to +85/125 °C temperature range - - Low-power background autonomous mode (LPBAM): autonomous peripherals with DMA, functional down to Stop 2 mode - - VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM - - 160 nA Shutdown mode (24 wakeup pins) - - 210 nA Standby mode (24 wakeup pins) - - 440 nA Standby mode with RTC - - 1.9 μA Stop 3 mode with 16-Kbyte SRAM4.3 µA Stop 3 mode with full SRAM - - 4.0 µA Stop 2 mode with 16-Kbyte SRAM - - 8.95 µA Stop 2 mode with full SRAM - - 19.5 μA/MHz Run mode @ 3.3 V +- Quick Start Guide -- Core - - Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU + This section is a usage guide for newcomers to RT-Thread. By following simple steps, you can run the RT-Thread operating system on this development board and see the experimental results. -- ART Accelerator - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and external memories: up to 160 MHz, 240 DMIPS - - 4-Kbyte data cache for external memories +- Advanced Usage -- Power management - - Embedded regulator (LDO) and SMPSstep-down converter supporting switchon-the-fly and voltage scaling + This section is prepared for developers who need to use more development board resources on the RT-Thread operating system. By using the ENV tool to configure the BSP, you can enable more onboard resources and achieve more advanced functions. -- Benchmarks - - 1.5 DMIPS/MHz (Drystone 2.1) - - 651 CoreMark® (4.07 CoreMark®/MHz) - - 535 ULPMark™-CP - - 149 ULPMark™-PP - - 58.2 ULPMark™-CM - - 133000 SecureMark™-TLS -- Memories - ​- 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 86-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces +### Quick Start Guide -- Security +This BSP provides MDK5 and IAR projects for developers and supports GCC development environment. The following uses the MDK5 development environment as an example to introduce how to get the system running. - - Arm® TrustZone® and securable I/Os, memories and peripherals - - Flexible life cycle scheme with RDP and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure firmware installation (SFI) thanks to embedded root secure services (RSS) - - Secure firmware upgrade support with TF-M - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte OTP (one-time programmable) - - Active tampers +**Please Note!!!** -- Clock management - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC (±1%) - - Internal low-power 32 kHz RC (±5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by LSE (better than ±0.25% accuracy) - - Internal 48 MHz with clock recovery - - 3 PLLs for system clock, USB, audio, ADC +Before performing the compilation work, please open ENV and execute the following command (this command is used to pull the necessary HAL library and CMSIS library, otherwise compilation will fail): -- General-purpose input/outputs - - Up to 136 fast I/Os with interrupt capability most 5V-tolerant and up to 14 I/Os with independent supply down to 1.08 V +```bash +pkgs --update +``` -- Up to 17 timers and 2 watchdogs - - 19 timers/watchdogs: 2 16-bit advanced motor-control, 4 32-bit, 5 16-bit, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers and 2 watchdogs - - RTC with hardware calendar and calibration +#### Hardware Connection -- Up to 22 communication peripherals - - 1 USB Type-C®/USB power delivery controller - - 1 USB OTG 2.0 full-speed controller - - 2 SAIs (serial-audio interface) - - 4 I2C FM+(1 Mbit/s), SMBus/PMBus™ - - 6 USARTs (ISO 7816, LIN, IrDA, modem) - - 3 SPIs (5x SPIs with the dual OCTOSPI) - - 1 CAN FD controller - - 2 SDMMC interfaces - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with sound-activity detection - - Parallel synchronous slave interface +Use a data cable to connect the development board to the PC and turn on the power switch. -- 16- and 4-channel DMA controllers, functional in Stop mode +#### Compilation and Download -- Graphic features - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface +Double-click the project.uvprojx file to open the MDK5 project, compile and download the program to the development board. -- Mathematical co-processor - - CORDIC for trigonometric functions acceleration - - Filter mathematical accelerator (FMAC) +> The project is configured by default to use the ST_LINK debugger to download the program. After connecting the development board via ST_LINK, click the download button to download the program to the development board. -- Up to 24 capacitive sensing channels - - Support touch key, linear and rotary touch sensors +#### Running Results -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 2 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - - Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM) - -- ECOPACK2 compliant packages - -## Read more - -| Documents | Description | -| :----------------------------------------------------------: | :----------------------------------------------------------: | -| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) | -| [STM32U575ZI ST Official Website](https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html) | STM32U575ZI datasheet and other resources | +After successfully downloading the program, the system will run automatically and the LED will blink. -## Maintained By +Connect the corresponding serial port of the development board to the PC, open the corresponding serial port in the terminal tool (115200-8-1-N), and after resetting the device, you can see the output information of RT-Thread: -[liukang](https://github.com/liukangcc) +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Nov 14 2021 21:15:06 + 2006 - 2021 Copyright by rt-thread team +msh > +``` +### Advanced Usage +This BSP currently only supports GPIO and UART1 functions. New features will be added in the future. -# Part II : NUCLEO-STM32U575ZI-Q Getting Started Guide +## Notes -NUCLEO-U575ZI-Q Getting Started Guide is introduced by using the example of SPI1 driving RW007 module to realize the introduction of NUCLEO-U575ZI-Q. - -## Preparatory Work - -Before NUCLEO-U575ZI-Q driver RW007 runs, the following preparations are essential, and you will need: - -> 1.NUCLEO-U575ZI-Q -> 2.RW007 WiFi module -> 3.Mini-USB Connecting cable (connecting the development board with the computer) -> 4.ENV Compile build environment（[Installation instructions](https://www.rt-thread.org/document/site/#/development-tools/env/env)） -> 5.common software（git,Keil5,STM32CubeMX,Serial debugging, etc） - -## Start on the Road - -RT-Thread contains RW007 software package, so users don't need to write their own drivers. Taking SPI mode as an example, this paper introduces how to drive RW007 module on NUCLEO-U575ZI-Q, and complete basic WiFi functions such as AP scanning and connection. - -## Hardware connection - -Thanks to the Arduino interface on Nucleo, just plug RW007 into the development board, and the hardware connection between them can be completed. - -![](figures/board1.png) - -According to the following schematic diagram, the corresponding table between IO interfaces and functions can be found as follows: - -![](figures/Schematic_diagram.png) - - |STM32 pin name | pin serial number |Arduino Interface serial number|function | - |PA5 | 5 |D13 |BOOT0/CLK | - |PA6 | 6 |D12 |MISO | - |PA7 | 7 |D11 |MOSI | - |PD14 | 62 |D10 |BOOT1/CS | - |PD15 | 63 |D9 |INT/BUSY | - |PF12 | 92 |D8 |RESET | - -## STM32 BSP Deploy（Menuconfig） -### 1.Download RT-Thread Source Code - -GitHub link：[https://github.com/RT-Thread/rt-thread](https://github.com/RT-Thread/rt-thread) -Open the 'rt-thread\bsp\stm32' directory and you will see the development board model supported by rt-thread. It is not difficult to get RT-Thread running on STM32, but bsp needs to be configured briefly before compiling the kernel components.The bsp used in this experiment was stm32u575-st-nucleo. - -### 2.The SPI Initializer is Configured Through CubeMX - -In general, the pin assignment of STM32 series can open the CubeMX project corresponding to the CubeMX_Config.ioc in the board\ CubeMX_Config directory in BSP, configure SPI1, generate code, and save and exit. - -![](figures/CubeMX.png) - -### 3. Configure the RW007 Package Through Menuconfig - -Go to the rt-thread\ bsp\ stm32\ stm32u575-st-nucleo folder, right-click to open the ENV window (provided that the ENV environment has been built under Windows), and type menuconfig to configure the system: - -#### 3.1 Turn on the SPI Device -The communication between the development board and the module depends on the SPI device. The SPI driver has been implemented in bsp and can be used as long as it is opened in the setting. Go to `On-chip Peripheral Drivers` under `On-chip Peripheral-> `, check the `Enable SPI BUS-- >` option, press enter to enter, and further select `Enable SPI1 BUS` to complete the configuration: - -![](figures/menuconfig1.png) -![](figures/menuconfig2.png) -![](figures/menuconfig3.png) -![](figures/menuconfig4.png) - -If there is no configuration for the corresponding spi in the menuconfig in the bsp, you can increase the configuration of the corresponding spi by modifying the Kconfig file. Add the configuration of SPI1 to the path of Kconfig under board/Kconfig, `menu "On-chip Peripheral Drivers" `. - - menuconfig BSP_USING_SPI - bool "Enable SPI BUS" - default n - select RT_USING_SPI - if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - default n - - config BSP_SPI1_TX_USING_DMA - bool "Enable SPI1 TX DMA" - depends on BSP_USING_SPI1 - default n - - config BSP_SPI1_RX_USING_DMA - bool "Enable SPI1 RX DMA" - depends on BSP_USING_SPI1 - select BSP_SPI1_TX_USING_DMA - default n - - endif - -#### 3.2 Configure the RW007 Package. - -RT-Thread provides supporting driver support for RW007 modules in the form of software packages. The default options of the system do not include software packages. Users need to enable them manually: return to the Menuconfig main interface through the Esc key, enter `RT-Thread online packages-- > `, `IoT-internet of things->`, `Wi-Fi-- > `, and check the `rw007: SPI WIFI rw007 driver-- >` option: -![](figures/menuconfig5.png) -RW007 package Github repository link：[RT-Thread-packages/rw007: RW007 (SPI Wi-Fi module) driver for RT-Thread](https://github.com/RT-Thread-packages/rw007) - -Then press Enter key to further set the parameters of the software package, complete the configuration of SPI bus and IO, change the bus device name `RW007 BUS NAME` to spi1, then configure SPI to control IO, and fill in each pin number according to the serial number of the following figure: -![](figures/menuconfig6.png) - -#### 3.3 Open the WiFi framework. - -The RW007 driver uses WLAN-related APIs. Click the following options to open the WiFi framework: `RT-Thread Components-- > `, `Device Drivers-- >`, `Using WiFi-- > `, and check `Using Wi-Fi framework`: - -![](figures/menuconfig7.png) - -#### 3.4 Save Menuconfig configuration. - -After completing the above three steps, the bsp configuration is complete, but the most important step is not to be omitted. Save the Menuconfig configuration: press the Esc key all the way to exit, and select Yes in the Save prompt window to confirm. - -### 4. Modify part of the project code. - -Open the project and replace the content of the `wifi_spi_device_init (void) `function in the `wifi_spi_device_init port.c` file with the following code: - - int wifi_spi_device_init(void) - { - char sn_version[32]; - - rw007_gpio_init(); - rt_hw_spi_device_attach(RW007_SPI_BUS_NAME, "wspi", RW007_CS_PIN); - rt_hw_wifi_init("wspi"); - - rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); - rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); - - rw007_sn_get(sn_version); - rt_kprintf("\nrw007 sn: [%s]\n", sn_version); - rw007_version_get(sn_version); - rt_kprintf("rw007 ver: [%s]\n\n", sn_version); - - return 0; - } - -### 5. Compile and Download the Project. - -Use the Build button of the toolbar to compile the project. 0Error (s) indicates that the compilation is successful. Connect the development board to the computer, and then click the Download button to download the firmware to the development board. - -## Running and Testing Module Functions. - -After downloading the program, it can automatically reset and run, open the serial port tool (recommended to use XShell and other interactive terminals), and set the parameter to 1152008-1mi N. If the system starts normally and there is no problem with the communication between the development board and the module, you will see the following initialization print message: - -![](figures/result1.png) -When rw007 sn and rw007 ver can output normally without garbled code, the RW007 driver is successful! - -Wifi networking test. - -Enter the wifi scan command in shell to search for wifi: - -![](figures/result2.png) - -Connection Target wifi Test: - -![](figures/result3.png) -The figure above shows that wifi successfully connects to the hotspot Meet. -At this point, the basic environment of `STM32U575- NUCLEO` is built and tested! - - -## References： - -1. [STM32F401 Nucleo-64 uses SPI to drive RW007](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/application-note/packages/rw007_module_using/an0034-rw007-module-using?id=rw007) -2. [STM32U575-NUCLEO Schematic Download](https://www.st.com/resource/en/schematic_pack/mb1549-u575ziq-c03_schematic.pdf) - -## Matters Needing Attention： - -1. It is best to use a newer version of MDK, and this experiment was carried out under the MDK5.36 version. -2. Please choose the latest version of the RW007 software package, otherwise the version will not be compatible and the project will report an error. If you have not selected the latest version of the RW007 package, download the RW007 package in the link below and replace the file in `bsp\ stm32\ stm32u575-st-nucleo\ packages\ rw007- xxx`! (however, the above step of modifying part of the project code is also necessary. If the content of the `wifi_spi_device_init (void) `function in the project `wifi_spi_device_init port.c` file is the same as that given, it can be ignored! ). -RW007 package Github repository link: [RT-Thread-packages/rw007: RW007 (SPI Wi-Fi module) driver for RT-Thread](https://github.com/RT-Thread-packages/rw007) -3. At present, in this experimental test, it is found that RW007 will time out, and a suitable solution has not been found, but it does not affect the normal use of RW007 module. +- Debug serial port is UART1, pin mapping description: + ```c + PA9 ------> USART1_TX + PA10 ------> USART1_RX + ``` +- It is recommended to use a newer version of MDK. This experiment was conducted using MDK5.36. \ No newline at end of file diff --git a/bsp/stm32/stm32u585-iot02a/README_zh.md b/bsp/stm32/stm32u585-iot02a/README_zh.md index 88bf688801..b2896a8e7b 100644 --- a/bsp/stm32/stm32u585-iot02a/README_zh.md +++ b/bsp/stm32/stm32u585-iot02a/README_zh.md @@ -1,4 +1,4 @@ -# 第一部分：NUCLEO-U575ZI-Q 开发板 BSP 说明 +# 第一部分：STM32 B-U585I-IOT02A 开发板 BSP 说明 [English](README.md) | **中文** -- Gitee From cbc759d6a51dd2cdce5188068a9c1a5bf1ff23d8 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Sat, 7 Feb 2026 11:45:35 +0800 Subject: [PATCH 41/45] refactor(ulog): Unify ulog warning output with ulog_warn_once --- components/utilities/ulog/ulog.c | 70 ++++++++++++++++++++++++-------- 1 file changed, 54 insertions(+), 16 deletions(-) diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 697aa248bc..e10f11a390 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -421,17 +421,47 @@ rt_weak rt_size_t ulog_tail_formater(char *log_buf, rt_size_t log_len, rt_bool_t return log_len; } -static void ulog_no_enough_buffer_printf(void) +/** + * @brief Print a warning message once (best-effort). + * + * @param[in,out] printed Pointer to a per-call-site flag used to suppress + * repeated prints. + * @param[in] msg Warning message to print. + * + * @details This helper provides a lightweight, best-effort "print-once" + * mechanism for diagnostic warnings. + * + * ulog output may be executed in different contexts (thread or ISR) + * and on single-core or SMP targets. To avoid unsafe blocking, + * excessive latency, or re-entrancy risks in these contexts, this + * function intentionally avoids locks, spinlocks, and atomic CAS. + * + * Under extreme multi-thread or SMP contention, it is therefore + * possible that the warning is printed more than once. This behavior + * is acceptable because the message is diagnostic-only and the + * critical logging path must remain lightweight. + */ +static void ulog_warn_once(rt_bool_t *printed, const char *msg) { - static rt_bool_t already_output = RT_FALSE; - if (already_output == RT_FALSE) + if (*printed == RT_FALSE) { - rt_kprintf("Warning: There is not enough buffer to output the log," - " please increase the ULOG_LINE_BUF_SIZE option.\n"); - already_output = RT_TRUE; + /* Set first to reduce re-entrancy and recursive logging. */ + *printed = RT_TRUE; + rt_kprintf("%s", msg); } } +/** + * @brief Print a "line buffer too small" warning once (best-effort). + */ +static void ulog_no_enough_buffer_printf(void) +{ + static rt_bool_t warned_line_buf = RT_FALSE; + ulog_warn_once(&warned_line_buf, + "Warning: There is not enough buffer to output the log," + " please increase the ULOG_LINE_BUF_SIZE option.\n"); +} + rt_weak rt_size_t ulog_formater(char *log_buf, rt_uint32_t level, const char *tag, rt_bool_t newline, const char *format, va_list args) { @@ -603,21 +633,29 @@ static void do_output(rt_uint32_t level, const char *tag, rt_bool_t is_raw, cons } else { - static rt_bool_t already_output = RT_FALSE; - if (already_output == RT_FALSE) - { - rt_kprintf("Warning: There is no enough buffer for saving async log," - " please increase the ULOG_ASYNC_OUTPUT_BUF_SIZE option.\n"); - already_output = RT_TRUE; - } + static rt_bool_t warned_async_log_buf = RT_FALSE; + ulog_warn_once(&warned_async_log_buf, + "Warning: There is no enough buffer for saving async log," + " please increase the ULOG_ASYNC_OUTPUT_BUF_SIZE option.\n"); } } else if (ulog.async_rb) { /* log_buf_size contain the tail \0, which will lead discard follow char, so only put log_buf_size -1 */ - rt_ringbuffer_put(ulog.async_rb, (const rt_uint8_t *)log_buf, (rt_uint16_t)log_buf_size - 1); - /* send a notice */ - rt_sem_release(&ulog.async_notice); + rt_size_t req_len = (rt_size_t)log_buf_size - 1; + rt_size_t put_len = rt_ringbuffer_put(ulog.async_rb, (const rt_uint8_t *)log_buf, (rt_uint32_t)req_len); + /* send a notice after writing data */ + if (put_len > 0) + { + rt_sem_release(&ulog.async_notice); + } + if (put_len < req_len) + { + static rt_bool_t warned_async_raw_partial = RT_FALSE; + ulog_warn_once(&warned_async_raw_partial, + "Warning: There is no enough buffer for saving async raw log," + " please increase the ULOG_ASYNC_OUTPUT_BUF_SIZE option.\n"); + } } return; -- Gitee From e5e29350b8218f19c7dacafead7a62ddce3b5741 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Thu, 12 Feb 2026 09:01:15 +0800 Subject: [PATCH 42/45] fix(ulog): Avoid async ulog empty wakeups and missed notifications --- components/utilities/ulog/ulog.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index e10f11a390..4918a68339 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -635,7 +635,7 @@ static void do_output(rt_uint32_t level, const char *tag, rt_bool_t is_raw, cons { static rt_bool_t warned_async_log_buf = RT_FALSE; ulog_warn_once(&warned_async_log_buf, - "Warning: There is no enough buffer for saving async log," + "Warning: There is not enough buffer for saving async log," " please increase the ULOG_ASYNC_OUTPUT_BUF_SIZE option.\n"); } } @@ -653,7 +653,7 @@ static void do_output(rt_uint32_t level, const char *tag, rt_bool_t is_raw, cons { static rt_bool_t warned_async_raw_partial = RT_FALSE; ulog_warn_once(&warned_async_raw_partial, - "Warning: There is no enough buffer for saving async raw log," + "Warning: There is not enough buffer for saving async raw log," " please increase the ULOG_ASYNC_OUTPUT_BUF_SIZE option.\n"); } } @@ -1479,7 +1479,6 @@ void ulog_async_output_enabled(rt_bool_t enabled) */ rt_err_t ulog_async_waiting_log(rt_int32_t time) { - rt_sem_control(&ulog.async_notice, RT_IPC_CMD_RESET, RT_NULL); return rt_sem_take(&ulog.async_notice, time); } @@ -1569,6 +1568,12 @@ int ulog_init(void) return -RT_ENOMEM; } rt_sem_init(&ulog.async_notice, "ulog", 0, RT_IPC_FLAG_FIFO); + /* + * Use binary-semaphore semantics for async_notice. + * This relies on ulog_async_output() draining all pending logs in one wakeup, + * so coalescing multiple notices will not lose log data. + */ + rt_sem_control(&ulog.async_notice, RT_IPC_CMD_SET_VLIMIT, (void *)1); #endif /* ULOG_USING_ASYNC_OUTPUT */ #ifdef ULOG_USING_FILTER -- Gitee From b0c55f5bf57bd713108664fc789845dfa2a7f635 Mon Sep 17 00:00:00 2001 From: CXSforHPU <19511928573@163.com> Date: Thu, 12 Feb 2026 22:54:40 +0800 Subject: [PATCH 43/45] [gd32][i2c]Add an example for measuring the onboard peripherals of the I2C board --- .../.ci/attachconfig/ci.attachconfig.yml | 37 +++++++- bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig | 23 +++++ .../risc-v/gd32vw553h-eval/board/SConscript | 5 ++ .../board/linker_scripts/link.lds | 6 ++ .../gd32vw553h-eval/board/port/SConscript | 28 ++++++ .../board/port/at24c02/at24c02.c | 35 ++++++++ .../board/port/at24c02/at24c02.h | 14 +++ .../board/port/at24c02/test_at24c02.c | 89 +++++++++++++++++++ 8 files changed, 236 insertions(+), 1 deletion(-) create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/port/SConscript create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.c create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.h create mode 100644 bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/test_at24c02.c diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml b/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml index e8bbc5bc5f..91f67c427b 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/gd32/risc-v/gd32vw553h-eval/.ci/attachconfig/ci.attachconfig.yml @@ -17,4 +17,39 @@ devices.i2c: - CONFIG_BSP_HW_I2C0_CLK=100 - CONFIG_BSP_USING_HW_I2C1=y - CONFIG_BSP_HW_I2C1_PIN_PB12_PB13=y - - CONFIG_BSP_HW_I2C1_CLK=100 \ No newline at end of file + - CONFIG_BSP_HW_I2C1_CLK=100 + +# ------ peripheral CI ------ +peripheral.at24c02: + kconfig: + - CONFIG_RT_CONSOLEBUF_SIZE=256 + - CONFIG_RT_NAME_MAX=32 + - CONFIG_RT_USING_ULOG=y + - CONFIG_ULOG_OUTPUT_LVL_D=y + - CONFIG_ULOG_OUTPUT_LVL=7 + - CONFIG_ULOG_USING_ISR_LOG=y + - CONFIG_ULOG_ASSERT_ENABLE=y + - CONFIG_ULOG_LINE_BUF_SIZE=128 + - CONFIG_ULOG_USING_COLOR=y + - CONFIG_ULOG_OUTPUT_TIME=y + - CONFIG_ULOG_OUTPUT_LEVEL=y + - CONFIG_ULOG_OUTPUT_TAG=y + - CONFIG_ULOG_BACKEND_USING_CONSOLE=y + - CONFIG_RT_USING_UTEST=y + - CONFIG_UTEST_THR_STACK_SIZE=4096 + - CONFIG_UTEST_THR_PRIORITY=20 + - CONFIG_RT_UTEST_MAX_OPTIONS=64 + - CONFIG_PKG_USING_AT24CXX=y + - CONFIG_PKG_AT24CXX_PATH="/packages/peripherals/at24cxx" + - CONFIG_PKG_AT24CXX_EE_TYPE_AT24C02=y + - CONFIG_PKG_AT24CXX_EE_TYPE=1 + - CONFIG_PKG_USING_AT24CXX_LATEST_VERSION=y + - CONFIG_PKG_AT24CXX_VER="latest" + - CONFIG_BSP_USING_AT24C02=y + - CONFIG_BSP_USING_AT24C02_UTEST=y + - CONFIG_RT_USING_I2C=y + - CONFIG_RT_USING_I2C_BITOPS=y + - CONFIG_BSP_USING_HW_I2C=y + - CONFIG_BSP_USING_HW_I2C0=y + - CONFIG_BSP_HW_I2C0_PIN_PA2_PA3=y + - CONFIG_BSP_HW_I2C0_CLK=100 \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig index e0668401c9..d3a3bf50b5 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/Kconfig @@ -143,6 +143,29 @@ endmenu menu "Board extended module Drivers" + menuconfig BSP_USING_AT24C02 + bool "Enable AT24C02 I2C0( SCL[PA2 : 2] SDA[PA3 : 3] )" + default n + select BSP_USING_HW_I2C + select BSP_USING_HW_I2C0 + select PKG_USING_AT24CXX + select PKG_AT24CXX_EE_TYPE_AT24C02 + + if BSP_USING_AT24C02 + + config BSP_USING_AT24C02_UTEST + bool "Enable the utest of AT24C02" + default n + select RT_USING_UTEST + select RT_USING_ULOG + select ULOG_USING_ISR_LOG + + config BSP_USING_AT24C02_INIT + bool "Init the model and check it" + default y + + endif + endmenu endmenu diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript b/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript index 71fadebe66..fbc2bb9336 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/SConscript @@ -24,4 +24,9 @@ if rtconfig.PLATFORM in ['gcc']: CPPDEFINES = ['GD32VW553H_EVAL'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + Return('group') diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds b/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds index 82516919c2..5667f71c97 100644 --- a/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/linker_scripts/link.lds @@ -62,6 +62,12 @@ SECTIONS __rt_init_end = .; . = ALIGN(4); + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + /* section information for modules */ . = ALIGN(4); __rtmsymtab_start = .; diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/port/SConscript b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/SConscript new file mode 100644 index 0000000000..ecdbf2c6b3 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/SConscript @@ -0,0 +1,28 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() + +# add general drivers +src = [] +path = [cwd] + +if GetDepend(['BSP_USING_AT24C02']): + path += [cwd + "/at24c02"] + + if GetDepend(['BSP_USING_AT24C02_UTEST']): + src += ["./at24c02/test_at24c02.c"] + + if GetDepend(['BSP_USING_AT24C02_INIT']): + src += ['./at24c02/at24c02.c'] + +CPPDEFINES = ['GD32VW553H_EVAL'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.c b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.c new file mode 100644 index 0000000000..49f5d65ef9 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.c @@ -0,0 +1,35 @@ +#include "rtconfig.h" + +#ifdef BSP_USING_AT24C02_INIT + +#include "at24c02.h" + +at24cxx_device_t gd32_at24c02 = RT_NULL; + +static int init_gd32_at24c02(void) +{ + rt_err_t result = RT_EOK; + + gd32_at24c02 = at24cxx_init(AT24C02_I2C_NAME, AT24C02_ADDR_INPUT); + + if (gd32_at24c02 == RT_NULL) + { + rt_kprintf("AT24C02 initialization failed\n"); + return -RT_ERROR; + } + + result = at24cxx_check(gd32_at24c02); + + if (result == -RT_ERROR) + { + rt_kprintf("AT24C02 check failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + + +INIT_DEVICE_EXPORT(init_gd32_at24c02); + +#endif \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.h b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.h new file mode 100644 index 0000000000..49d173e8b7 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/at24c02.h @@ -0,0 +1,14 @@ +#ifndef AT24C02_H +#define AT24C02_H + +#include +#include "at24cxx.h" + +#define AT24C02_I2C_NAME "i2c0" +#define AT24C02_ADDR_INPUT 0x0 + +#ifdef BSP_USING_AT24C02_INIT +extern at24cxx_device_t gd32_at24c02; +#endif // BSP_USING_AT24C02_INIT + +#endif // AT24C02_H \ No newline at end of file diff --git a/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/test_at24c02.c b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/test_at24c02.c new file mode 100644 index 0000000000..d0dc3386b8 --- /dev/null +++ b/bsp/gd32/risc-v/gd32vw553h-eval/board/port/at24c02/test_at24c02.c @@ -0,0 +1,89 @@ +#include "rtconfig.h" + +#ifdef BSP_USING_AT24C02 + +#include "utest.h" +#include "at24c02.h" + +#define TEST_DATA "WELCOME TO RTT" + +static at24cxx_device_t dev = RT_NULL; + +static rt_err_t test_at24c02_init(void) +{ + rt_err_t result = RT_EOK; + uint8_t AddrInput = 0x0; + + dev = at24cxx_init(AT24C02_I2C_NAME, AddrInput); + if (dev == RT_NULL) + { + LOG_E("AT24C02 initialization failed\n"); + result = -RT_ERROR; + } + + return result; +} + +static void test_at24c02_example(void) +{ + uint8_t write_buffer[] = TEST_DATA; + int data_size = sizeof(write_buffer); + rt_err_t result = RT_EOK; + + uint8_t read_buffer[50] = {0}; + + /* 写入数据 */ + result = at24cxx_write(dev, 0, write_buffer, data_size); + + if (result != RT_EOK) + { + LOG_E("Failed to write data to AT24C02\n"); + uassert_true(RT_FALSE); + return; + } + + LOG_I("Successfully wrote to AT24C02: %s\n", write_buffer); + + /* 读取数据 */ + result = at24cxx_read(dev, 0, read_buffer, data_size); + + if (result != RT_EOK) + { + LOG_E("Failed to read data from AT24C02\n"); + uassert_true(RT_FALSE); + return; + } + + LOG_I("Successfully read from AT24C02: %s\n", read_buffer); + + uassert_str_equal(write_buffer, read_buffer); + + /* 检查数据 */ + result = at24cxx_check(dev); + + uassert_true(result == RT_EOK); + + return; +} + +static rt_err_t test_at24c02_deinit(void) +{ + + if (dev != RT_NULL) + { + at24cxx_deinit(dev); + dev = RT_NULL; + return RT_EOK; + } + + return -RT_ERROR; +} + +static void test_case(void) +{ + UTEST_UNIT_RUN(test_at24c02_example); +} + +UTEST_TC_EXPORT(test_case, "bsp.gd32.port.at24c02" , test_at24c02_init, test_at24c02_deinit, 100); + +#endif \ No newline at end of file -- Gitee From 85b656b14dcfe8a3ab27c819e168dde082ab39ef Mon Sep 17 00:00:00 2001 From: theqengineer Date: Fri, 13 Feb 2026 15:04:27 +0800 Subject: [PATCH 44/45] chore: fix typo in components and libcpu --- components/drivers/i2c/dev_i2c_bit_ops.c | 2 +- components/drivers/spi/dev_spi_msd.c | 2 +- components/finsh/msh.c | 2 +- components/lwp/lwp_args.c | 10 +++++----- include/rtdef.h | 4 ++-- libcpu/arm/AT91SAM7S/interrupt.c | 2 +- libcpu/arm/AT91SAM7X/interrupt.c | 2 +- libcpu/arm/AT91SAM7X/trap.c | 2 +- libcpu/arm/cortex-r4/interrupt.c | 2 +- libcpu/arm/lpc214x/cpuport.c | 2 +- libcpu/arm/lpc24xx/interrupt.c | 2 +- libcpu/arm/s3c24x0/interrupt.c | 2 +- libcpu/arm/s3c44b0/interrupt.c | 2 +- libcpu/arm/sep4020/interrupt.c | 2 +- libcpu/ia32/interrupt.c | 2 +- libcpu/mips/gs232/interrupt.c | 2 +- libcpu/ppc/ppc405/interrupt.c | 2 +- libcpu/risc-v/t-head/c906/interrupt.c | 2 +- libcpu/risc-v/t-head/c908/interrupt.c | 2 +- libcpu/sim/posix/cpu_port.c | 2 +- libcpu/unicore32/sep6200/interrupt.c | 2 +- libcpu/xilinx/microblaze/trap.c | 2 +- tools/building.py | 4 ++-- 23 files changed, 29 insertions(+), 29 deletions(-) diff --git a/components/drivers/i2c/dev_i2c_bit_ops.c b/components/drivers/i2c/dev_i2c_bit_ops.c index 005cf9035e..0b055f1c87 100644 --- a/components/drivers/i2c/dev_i2c_bit_ops.c +++ b/components/drivers/i2c/dev_i2c_bit_ops.c @@ -265,7 +265,7 @@ static rt_ssize_t i2c_recv_bytes(struct rt_i2c_bus_device *bus, ptr ++; count --; - LOG_D("recieve bytes: 0x%02x, %s", + LOG_D("receive bytes: 0x%02x, %s", val, (flags & RT_I2C_NO_READ_ACK) ? "(No ACK/NACK)" : (count ? "ACK" : "NACK")); diff --git a/components/drivers/spi/dev_spi_msd.c b/components/drivers/spi/dev_spi_msd.c index 8d81e348af..441e1ea5c5 100644 --- a/components/drivers/spi/dev_spi_msd.c +++ b/components/drivers/spi/dev_spi_msd.c @@ -199,7 +199,7 @@ static rt_err_t _send_cmd( return -RT_ERROR;//fail } - //recieve other byte + //receive other byte if (type == response_r1) { return RT_EOK; diff --git a/components/finsh/msh.c b/components/finsh/msh.c index 7cf93855af..56ef8a1cb0 100644 --- a/components/finsh/msh.c +++ b/components/finsh/msh.c @@ -451,7 +451,7 @@ static char *_msh_exec_search_env(const char *pg_name) or hitting its end */ while (1) { - /* env paths are seperated by ':' */ + /* env paths are separated by ':' */ if (*pos == ':' || *pos == '\0') { tmp_ch = *pos; diff --git a/components/lwp/lwp_args.c b/components/lwp/lwp_args.c index 31ea659da5..f1c723b120 100644 --- a/components/lwp/lwp_args.c +++ b/components/lwp/lwp_args.c @@ -671,21 +671,21 @@ static char *_find_word(char *cp) } /** - * @brief Seperate words in a string and get the next word + * @brief Separate words in a string and get the next word * * @param[in] cp Pointer to the string to process * * @return char* Pointer to the next word in the string * - * @note Finds the next whitespace character, seperates words, and returns a + * @note Finds the next whitespace character, separates words, and returns a * pointer to the next word. */ -static char *_seperate_and_get_nextword(char *cp) +static char *_separate_and_get_nextword(char *cp) { /* find next whitespace */ for (; *cp && (*cp != ' ') && (*cp != '\t'); cp++) ; - /* seperate words */ + /* separate words */ while ((*cp == ' ') || (*cp == '\t')) { *cp++ = '\0'; @@ -762,7 +762,7 @@ rt_err_t lwp_args_load_script(struct lwp_args_info *ai, const char *filename) do { - nextword = _seperate_and_get_nextword(cp); + nextword = _separate_and_get_nextword(cp); args_append(&ow_ai, cp, strlen(cp), LWP_ARGS_TYPE_KARG); cp = nextword; } diff --git a/include/rtdef.h b/include/rtdef.h index f3e10fe51f..0dc919e77e 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -57,8 +57,8 @@ * 2023-12-01 Shell Support of dynamic device * 2023-12-18 xqyjlj add rt_always_inline * 2023-12-22 Shell Support hook list - * 2024-01-18 Shell Seperate basical types to a rttypes.h - * Seperate the compiler portings to rtcompiler.h + * 2024-01-18 Shell Separate basical types to a rttypes.h + * Separate the compiler portings to rtcompiler.h * 2024-03-30 Meco Man update version number to v5.2.0 * 2025-11-10 Rbb666 update version number to v5.3.0 */ diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index 8468d36413..a34fa50994 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/arm/AT91SAM7X/interrupt.c b/libcpu/arm/AT91SAM7X/interrupt.c index 1d473654e2..143d8b661b 100644 --- a/libcpu/arm/AT91SAM7X/interrupt.c +++ b/libcpu/arm/AT91SAM7X/interrupt.c @@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index b2dfdb4949..c8070fac96 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -41,7 +41,7 @@ void rt_hw_trap_fiq(void) extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort(void) { - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->parent.name); + rt_kprintf("Abort occurred!!! Thread [%s] suspended.\n",rt_current_thread->parent.name); rt_thread_suspend(rt_current_thread); rt_schedule(); diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c index 345ca30e43..cd74e5244e 100644 --- a/libcpu/arm/cortex-r4/interrupt.c +++ b/libcpu/arm/cortex-r4/interrupt.c @@ -36,7 +36,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_int_not_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } #define vimRAM (0xFFF82000U) diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 927ae93b4e..cbaa761b63 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -74,7 +74,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/arm/lpc24xx/interrupt.c b/libcpu/arm/lpc24xx/interrupt.c index ec1b29e09e..a8b8199ee6 100644 --- a/libcpu/arm/lpc24xx/interrupt.c +++ b/libcpu/arm/lpc24xx/interrupt.c @@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /*@{*/ void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } void rt_hw_interrupt_init(void) diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c index 79ef42df1a..530b984809 100644 --- a/libcpu/arm/s3c24x0/interrupt.c +++ b/libcpu/arm/s3c24x0/interrupt.c @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/arm/s3c44b0/interrupt.c b/libcpu/arm/s3c44b0/interrupt.c index b69e675741..44cef7f9c0 100644 --- a/libcpu/arm/s3c44b0/interrupt.c +++ b/libcpu/arm/s3c44b0/interrupt.c @@ -34,7 +34,7 @@ unsigned char interrupt_bank3[256]; void rt_hw_interrupt_handle(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index 641472d19f..b32bccf4ee 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index 473bf7714a..b73c146c29 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -56,7 +56,7 @@ void rt_hw_pic_init() void rt_hw_interrupt_handle(int vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } void rt_hw_isr(int vector) diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c index fb80a8c1ec..1fe9b8a627 100644 --- a/libcpu/mips/gs232/interrupt.c +++ b/libcpu/mips/gs232/interrupt.c @@ -35,7 +35,7 @@ static struct gs232_intc_regs volatile *gs232_hw0_icregs static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 571bd6ff06..b2aa5f5603 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -24,7 +24,7 @@ rt_uint32_t rt_thread_switch_interrput_flag; rt_isr_handler_t rt_hw_interrupt_handler(rt_uint32_t vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); return RT_NULL; } diff --git a/libcpu/risc-v/t-head/c906/interrupt.c b/libcpu/risc-v/t-head/c906/interrupt.c index 2f7a86e680..339dde808f 100644 --- a/libcpu/risc-v/t-head/c906/interrupt.c +++ b/libcpu/risc-v/t-head/c906/interrupt.c @@ -23,7 +23,7 @@ struct rt_irq_desc isr_table[INTERRUPTS_MAX]; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/risc-v/t-head/c908/interrupt.c b/libcpu/risc-v/t-head/c908/interrupt.c index 2f7a86e680..339dde808f 100644 --- a/libcpu/risc-v/t-head/c908/interrupt.c +++ b/libcpu/risc-v/t-head/c908/interrupt.c @@ -23,7 +23,7 @@ struct rt_irq_desc isr_table[INTERRUPTS_MAX]; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/libcpu/sim/posix/cpu_port.c b/libcpu/sim/posix/cpu_port.c index 8b578977e3..0e432482f0 100644 --- a/libcpu/sim/posix/cpu_port.c +++ b/libcpu/sim/posix/cpu_port.c @@ -54,7 +54,7 @@ rt_ubase_t rt_thread_switch_interrupt_flag; /* interrupt event mutex */ static pthread_mutex_t *ptr_int_mutex; -static pthread_cond_t cond_int_hit; /* interrupt occured! */ +static pthread_cond_t cond_int_hit; /* interrupt occurred! */ static volatile unsigned int cpu_pending_interrupts; static int (* cpu_isr_table[MAX_INTERRUPT_NUM])(void) = {0}; diff --git a/libcpu/unicore32/sep6200/interrupt.c b/libcpu/unicore32/sep6200/interrupt.c index ca0be86ad7..44f8b193ce 100644 --- a/libcpu/unicore32/sep6200/interrupt.c +++ b/libcpu/unicore32/sep6200/interrupt.c @@ -118,7 +118,7 @@ rt_inline void sep6200_irq_mask(rt_uint32_t irq) } rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); return RT_NULL; } diff --git a/libcpu/xilinx/microblaze/trap.c b/libcpu/xilinx/microblaze/trap.c index 86b99a06a7..1c2ac301ae 100755 --- a/libcpu/xilinx/microblaze/trap.c +++ b/libcpu/xilinx/microblaze/trap.c @@ -33,7 +33,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); } /** diff --git a/tools/building.py b/tools/building.py index 26e13b3f84..b0b4c144c6 100644 --- a/tools/building.py +++ b/tools/building.py @@ -318,7 +318,7 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [ if env['LINK'].find('gcc') != -1: env['LINK'] = env['LINK'].replace('gcc', 'g++') - # we need to seperate the variant_dir for BSPs and the kernels. BSPs could + # we need to separate the variant_dir for BSPs and the kernels. BSPs could # have their own components etc. If they point to the same folder, SCons # would find the wrong source code to compile. bsp_vdir = 'build' @@ -792,7 +792,7 @@ def DoBuilding(target, objects): for group in Projects: local_group(group, objects_in_group) - # sort seperately, because the data type of + # sort separately, because the data type of # the members of the two lists are different objects_in_group = sorted(objects_in_group) objects = sorted(objects) -- Gitee From 0fe17203874973b2565e39d50da3a74639d55bdb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=9F=B3=E9=B8=BF=E8=B6=85?= <13010364+shi-hongchao@user.noreply.gitee.com> Date: Tue, 17 Feb 2026 18:03:19 +0800 Subject: [PATCH 45/45] =?UTF-8?q?fix(bsp/gd32):=20=E8=A7=A3=E5=86=B3?= =?UTF-8?q?=E5=90=88=E5=B9=B6=E5=86=B2=E7=AA=81=E5=B8=A6=E6=9D=A5=E7=9A=84?= =?UTF-8?q?=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/gd32/arm/gd32405rg/.config | 50 ++- .../gd32405rg/RTE/_rt-thread/RTE_Components.h | 2 +- bsp/gd32/arm/gd32405rg/applications/main.c | 66 +++ bsp/gd32/arm/gd32405rg/board/Kconfig | 409 ++++++++--------- bsp/gd32/arm/gd32405rg/board/SConscript | 1 + bsp/gd32/arm/gd32405rg/board/board_ms5611.c | 31 ++ bsp/gd32/arm/gd32405rg/project.uvoptx | 396 ++++++++++------ bsp/gd32/arm/gd32405rg/project.uvprojx | 423 ++++++++++++++---- bsp/gd32/arm/gd32405rg/rtconfig.h | 18 +- .../arm/libraries/gd32_drivers/drv_timer.c | 54 --- 10 files changed, 930 insertions(+), 520 deletions(-) create mode 100644 bsp/gd32/arm/gd32405rg/board/board_ms5611.c diff --git a/bsp/gd32/arm/gd32405rg/.config b/bsp/gd32/arm/gd32405rg/.config index 8dcdda7301..b725106e65 100644 --- a/bsp/gd32/arm/gd32405rg/.config +++ b/bsp/gd32/arm/gd32405rg/.config @@ -178,7 +178,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -241,7 +242,7 @@ CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_CLOCK_TIME=y CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y @@ -254,7 +255,7 @@ CONFIG_RT_USING_I2C_BITOPS=y # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set @@ -265,7 +266,9 @@ CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set +CONFIG_RT_USING_SENSOR=y +# CONFIG_RT_USING_SENSOR_V2 is not set +CONFIG_RT_USING_SENSOR_CMD=y # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set @@ -273,8 +276,6 @@ CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_BLK is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_KTIME is not set -CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers @@ -351,8 +352,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RT_LINK is not set # end of Utilities -# CONFIG_RT_USING_VBUS is not set - # # Using USB legacy version # @@ -361,6 +360,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Using USB legacy version # CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set # end of RT-Thread Components # @@ -952,7 +952,14 @@ CONFIG_PKG_GD32_ARM_SERIES_DRIVER_VER="latest" # CONFIG_PKG_USING_MLX90394 is not set # CONFIG_PKG_USING_MLX90396 is not set # CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set +CONFIG_PKG_USING_MS5611=y +CONFIG_PKG_MS5611_PATH="/packages/peripherals/sensors/ms5611" +CONFIG_PKG_MS5611_USING_SENSOR_V1=y +# CONFIG_PKG_MS5611_USING_TEMP is not set +CONFIG_PKG_MS5611_USING_BARO=y +# CONFIG_PKG_USING_MS5611_V100 is not set +CONFIG_PKG_USING_MS5611_LATEST_VERSION=y +CONFIG_PKG_MS5611_VER="latest" # CONFIG_PKG_USING_MAX31865 is not set # CONFIG_PKG_USING_VL53L0X is not set # CONFIG_PKG_USING_INA260 is not set @@ -1432,14 +1439,15 @@ CONFIG_SOC_GD32405RG=y # CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_SERIAL_V1=y +# CONFIG_BSP_USING_SERIAL_V2 is not set CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_UART0_RX_USING_DMA is not set -# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_TX_PIN="PA9" +CONFIG_BSP_UART0_RX_PIN="PA10" +CONFIG_BSP_UART0_AFIO="AF7" # CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set CONFIG_BSP_USING_HARD_I2C=y CONFIG_BSP_USING_RECEIVING_A=y # CONFIG_BSP_USING_RECEIVING_B is not set @@ -1448,7 +1456,21 @@ CONFIG_BSP_USING_HARD_I2C0=y # CONFIG_BSP_USING_HARD_I2C2 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ADC is not set -# CONFIG_BSP_USING_HWTIMER is not set +CONFIG_BSP_USING_CLOCK_TIMER=y +# CONFIG_BSP_USING_CLOCK_TIMER0 is not set +# CONFIG_BSP_USING_CLOCK_TIMER1 is not set +# CONFIG_BSP_USING_CLOCK_TIMER2 is not set +# CONFIG_BSP_USING_CLOCK_TIMER3 is not set +# CONFIG_BSP_USING_CLOCK_TIMER4 is not set +# CONFIG_BSP_USING_CLOCK_TIMER5 is not set +CONFIG_BSP_USING_CLOCK_TIMER6=y +# CONFIG_BSP_USING_CLOCK_TIMER7 is not set +# CONFIG_BSP_USING_CLOCK_TIMER8 is not set +# CONFIG_BSP_USING_CLOCK_TIMER9 is not set +# CONFIG_BSP_USING_CLOCK_TIMER10 is not set +# CONFIG_BSP_USING_CLOCK_TIMER11 is not set +# CONFIG_BSP_USING_CLOCK_TIMER12 is not set +# CONFIG_BSP_USING_CLOCK_TIMER13 is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_WDT is not set diff --git a/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h b/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h index 29cf3e0e73..722c192a60 100644 --- a/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h +++ b/bsp/gd32/arm/gd32405rg/RTE/_rt-thread/RTE_Components.h @@ -2,7 +2,7 @@ * UVISION generated file: DO NOT EDIT! * Generated by: uVision version 5.42.0.0 * - * Project: 'template' + * Project: 'project' * Target: 'rt-thread' */ diff --git a/bsp/gd32/arm/gd32405rg/applications/main.c b/bsp/gd32/arm/gd32405rg/applications/main.c index fa263c7cca..4e8a7984a0 100644 --- a/bsp/gd32/arm/gd32405rg/applications/main.c +++ b/bsp/gd32/arm/gd32405rg/applications/main.c @@ -135,3 +135,69 @@ static void pwm_test(void) } MSH_CMD_EXPORT(pwm_test, pwm test); #endif // BSP_USING_PWM + +void ms5611_test(void) +{ + rt_device_t i2c_dev = RT_NULL; + rt_err_t result = RT_EOK; + + // 查找气压计 + i2c_dev = rt_device_find("baro_ms5611"); + if(i2c_dev == RT_NULL) + { + rt_kprintf("i2c0 not found\r\n"); + return; + } + + // 打开气压计 + result = rt_device_open(i2c_dev, RT_DEVICE_FLAG_RDWR); + if(result != RT_EOK) + { + rt_kprintf("open i2c0 failed\r\n"); + return; + } + + // 读取气压计数据 + struct rt_sensor_data data = {0}; + if(rt_device_read(i2c_dev, 0, &data, 1) == 1) + { + rt_kprintf("read ms5611: %d\n", data.data.baro); + } + else + { + rt_kprintf("read ms5611 failed\n"); + } + + // 关闭气压计 + rt_device_close(i2c_dev); + + // 查找气压计 + i2c_dev = rt_device_find("temp_ms5611"); + if(i2c_dev == RT_NULL) + { + rt_kprintf("i2c0 not found\r\n"); + return; + } + + // 打开气压计 + result = rt_device_open(i2c_dev, RT_DEVICE_FLAG_RDWR); + if(result != RT_EOK) + { + rt_kprintf("open i2c0 failed\r\n"); + return; + } + + // 读取气压计温度 + if(rt_device_read(i2c_dev, 0, &data, 1) == 1) + { + rt_kprintf("read ms5611: %d\n", data.data.temp); + } + else + { + rt_kprintf("read ms5611 failed\n"); + } + + // 关闭气压计 + rt_device_close(i2c_dev); +} +MSH_CMD_EXPORT(ms5611_test, i2c test); diff --git a/bsp/gd32/arm/gd32405rg/board/Kconfig b/bsp/gd32/arm/gd32405rg/board/Kconfig index 36805b18fb..af223d5b2b 100644 --- a/bsp/gd32/arm/gd32405rg/board/Kconfig +++ b/bsp/gd32/arm/gd32405rg/board/Kconfig @@ -27,209 +27,198 @@ menu "On-chip Peripheral Drivers" default y select RT_USING_SERIAL if BSP_USING_UART - config BSP_USING_UART0 - bool "Enable UART0" - default n - - config BSP_UART0_RX_USING_DMA - bool "Enable UART0 RX DMA" - depends on BSP_USING_UART0 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART0_TX_USING_DMA - bool "Enable UART0 TX DMA" - depends on BSP_USING_UART0 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART0_RX_BUFSIZE - int "Set UART0 RX buffer size" - range 64 65535 - depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 - default 64 - - config BSP_UART0_TX_BUFSIZE - int "Set UART0 TX buffer size" - range 0 65535 - depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 - default 0 - - config BSP_UART0_DMA_PING_BUFSIZE - int "Set UART0 RX DMA ping-pong buffer size" - range 32 65535 - depends on RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA - default 32 + choice + prompt "Select UART framework version" + default BSP_USING_SERIAL_V1 + + config BSP_USING_SERIAL_V1 + bool "Use Serial V1 framework" + select RT_USING_SERIAL + + config BSP_USING_SERIAL_V2 + bool "Use Serial V2 framework" + select RT_USING_SERIAL_V2 + endchoice - config BSP_USING_UART1 - bool "Enable UART1" + menuconfig BSP_USING_UART0 + bool "Enable UART0" default y + if BSP_USING_UART0 + config BSP_UART0_TX_PIN + string "UART0 TX name, such as PA8" + default "PA9" + + config BSP_UART0_RX_PIN + string "UART0 RX name, such as PA9" + default "PA10" + + config BSP_UART0_AFIO + string "UART0 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART0_DMA_PING_BUFSIZE + int "Set UART0 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART0_RX_USING_DMA + default 64 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART1_TX_USING_DMA - bool "Enable UART1 TX DMA" - depends on BSP_USING_UART1 - select RT_SERIAL_USING_DMA + menuconfig BSP_USING_UART1 + bool "Enable UART1" default n + if BSP_USING_UART1 + config BSP_UART1_TX_PIN + string "UART1 TX name, such as PA8" + default "PA2" + + config BSP_UART1_RX_PIN + string "UART1 RX name, such as PA9" + default "PA3" + + config BSP_UART1_AFIO + string "UART1 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART1_RX_USING_DMA + default 64 + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART1_RX_BUFSIZE - int "Set UART1 RX buffer size" - range 64 65535 - depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 - default 64 - - config BSP_UART1_TX_BUFSIZE - int "Set UART1 TX buffer size" - range 0 65535 - depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 - default 0 - - config BSP_UART1_DMA_PING_BUFSIZE - int "Set UART1 RX DMA ping-pong buffer size" - range 32 65535 - depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA - default 32 - - config BSP_USING_UART2 + menuconfig BSP_USING_UART2 bool "Enable UART2" default n + if BSP_USING_UART2 + config BSP_UART2_TX_PIN + string "UART2 TX name, such as PA8" + default "PB10" + + config BSP_UART2_RX_PIN + string "UART2 RX name, such as PA9" + default "PB11" + + config BSP_UART2_AFIO + string "UART2 alternate function, such as AF7" + default "AF7" + + if BSP_USING_SERIAL_V2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART2_RX_USING_DMA + default 64 + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + default 128 + endif + endif - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART2_TX_USING_DMA - bool "Enable UART2 TX DMA" - depends on BSP_USING_UART2 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART2_RX_BUFSIZE - int "Set UART2 RX buffer size" - range 64 65535 - depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 - default 64 - - config BSP_UART2_TX_BUFSIZE - int "Set UART2 TX buffer size" - range 0 65535 - depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 - default 0 - - config BSP_UART2_DMA_PING_BUFSIZE - int "Set UART2 RX DMA ping-pong buffer size" - range 32 65535 - depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA - default 32 - - config BSP_USING_UART3 + menuconfig BSP_USING_UART3 bool "Enable UART3" default n - - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART3_TX_USING_DMA - bool "Enable UART3 TX DMA" - depends on BSP_USING_UART3 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART3_RX_BUFSIZE - int "Set UART3 RX buffer size" - range 64 65535 - depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 - default 64 - - config BSP_UART3_TX_BUFSIZE - int "Set UART3 TX buffer size" - range 0 65535 - depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 - default 0 - - config BSP_UART3_DMA_PING_BUFSIZE - int "Set UART3 RX DMA ping-pong buffer size" - range 32 65535 - depends on RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA - default 32 - - config BSP_USING_UART4 - bool "Enable UART4" - default n - - config BSP_UART4_RX_USING_DMA - bool "Enable UART4 RX DMA" - depends on BSP_USING_UART4 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART4_TX_USING_DMA - bool "Enable UART4 TX DMA" - depends on BSP_USING_UART4 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART4_RX_BUFSIZE - int "Set UART4 RX buffer size" - range 64 65535 - depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 - default 64 - - config BSP_UART4_TX_BUFSIZE - int "Set UART4 TX buffer size" - range 0 65535 - depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 - default 0 - - config BSP_UART4_DMA_PING_BUFSIZE - int "Set UART4 RX DMA ping-pong buffer size" - range 32 65535 - depends on RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA - default 32 - - config BSP_USING_UART5 - bool "Enable UART5" - default n - - config BSP_UART5_RX_USING_DMA - bool "Enable UART5 RX DMA" - depends on BSP_USING_UART5 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART5_TX_USING_DMA - bool "Enable UART5 TX DMA" - depends on BSP_USING_UART5 - select RT_SERIAL_USING_DMA - default n - - config BSP_UART5_RX_BUFSIZE - int "Set UART5 RX buffer size" - range 64 65535 - depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 - default 64 - - config BSP_UART5_TX_BUFSIZE - int "Set UART5 TX buffer size" - range 0 65535 - depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 - default 0 - - config BSP_UART5_DMA_PING_BUFSIZE - int "Set UART5 RX DMA ping-pong buffer size" - range 32 65535 - depends on RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA - default 32 + if BSP_USING_UART3 + config BSP_UART3_TX_PIN + string "UART3 TX name, such as PA8" + default "PC10" + + config BSP_UART3_RX_PIN + string "UART3 RX name, such as PA9" + default "PC11" + + config BSP_UART3_AFIO + string "UART3 alternate function, such as AF7" + default "AF8" + + if BSP_USING_SERIAL_V2 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on RT_SERIAL_USING_DMA + default n + + config BSP_UART3_DMA_PING_BUFSIZE + int "Set UART3 RX DMA ping-pong buffer size" + range 16 65535 + depends on BSP_UART3_RX_USING_DMA + default 64 + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + default 128 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + default 128 + endif + endif endif menuconfig BSP_USING_HARD_I2C @@ -300,64 +289,64 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_HWTIMER + menuconfig BSP_USING_CLOCK_TIMER bool "Enable timer" default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_HWTIMER0 + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_CLOCK_TIMER0 bool "Enable TIM0" default n - config BSP_USING_HWTIMER1 + config BSP_USING_CLOCK_TIMER1 bool "Enable TIM1" default n - config BSP_USING_HWTIMER2 + config BSP_USING_CLOCK_TIMER2 bool "Enable TIM2" default n - config BSP_USING_HWTIMER3 + config BSP_USING_CLOCK_TIMER3 bool "Enable TIM3" default n - config BSP_USING_HWTIMER4 + config BSP_USING_CLOCK_TIMER4 bool "Enable TIM4" default n - config BSP_USING_HWTIMER5 + config BSP_USING_CLOCK_TIMER5 bool "Enable TIM5" default n - config BSP_USING_HWTIMER6 + config BSP_USING_CLOCK_TIMER6 bool "Enable TIM6" default y - config BSP_USING_HWTIMER7 + config BSP_USING_CLOCK_TIMER7 bool "Enable TIM7" default n - config BSP_USING_HWTIMER8 + config BSP_USING_CLOCK_TIMER8 bool "Enable TIM8" default n - config BSP_USING_HWTIMER9 + config BSP_USING_CLOCK_TIMER9 bool "Enable TIM9" default n - config BSP_USING_HWTIMER10 + config BSP_USING_CLOCK_TIMER10 bool "Enable TIM10" default n - config BSP_USING_HWTIMER11 + config BSP_USING_CLOCK_TIMER11 bool "Enable TIM11" default n - config BSP_USING_HWTIMER12 + config BSP_USING_CLOCK_TIMER12 bool "Enable TIM12" default n - config BSP_USING_HWTIMER13 + config BSP_USING_CLOCK_TIMER13 bool "Enable TIM13" default n endif diff --git a/bsp/gd32/arm/gd32405rg/board/SConscript b/bsp/gd32/arm/gd32405rg/board/SConscript index 409d6be0ae..c2ae6e3cf5 100644 --- a/bsp/gd32/arm/gd32405rg/board/SConscript +++ b/bsp/gd32/arm/gd32405rg/board/SConscript @@ -7,6 +7,7 @@ cwd = GetCurrentDir() # add general drivers src = Split(''' board.c +board_ms5611.c ''') path = [cwd] diff --git a/bsp/gd32/arm/gd32405rg/board/board_ms5611.c b/bsp/gd32/arm/gd32405rg/board/board_ms5611.c new file mode 100644 index 0000000000..4aba0b965a --- /dev/null +++ b/bsp/gd32/arm/gd32405rg/board/board_ms5611.c @@ -0,0 +1,31 @@ +/******************************************************************************* + * @file board_ms5611.c + * @author ShiHongchao + * @date 2025-12-14 + * @version V0.1 + * @brief 使用ms5611软件包向传感器框架注册ms5611气压传感器 + ******************************************************************************* +*/ + +#include + +#define LOG_TAR "board.ms5611" +#include + +#include "board.h" +#include "sensor_meas_ms5611.h" + +int board_ms5611_init(void) +{ + int rsult = rt_hw_ms5611_init("ms5611", &(struct rt_sensor_config){ + .intf.dev_name = "hwi2c0", + }); + if(rsult != RT_EOK) + { + LOG_E("ms5611 init failed"); + return rsult; + } + + return rsult; +} +INIT_DEVICE_EXPORT(board_ms5611_init); diff --git a/bsp/gd32/arm/gd32405rg/project.uvoptx b/bsp/gd32/arm/gd32405rg/project.uvoptx index 7fd705460a..4d71ca8e9e 100644 --- a/bsp/gd32/arm/gd32405rg/project.uvoptx +++ b/bsp/gd32/arm/gd32405rg/project.uvoptx @@ -117,6 +117,26 @@ BIN\CMSIS_AGDI.dll + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + 0 CMSIS_AGDI @@ -135,12 +155,12 @@ 0 0 - 0 + 1 0 0 0 0 - 0 + 1 0 0 0 @@ -195,7 +215,7 @@ - Compiler + CPU 0 0 0 @@ -207,8 +227,8 @@ 0 0 0 - ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c - syscall_mem.c + ..\..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c 0 0 @@ -219,8 +239,8 @@ 0 0 0 - ..\..\..\..\components\libc\compilers\armlibc\syscalls.c - syscalls.c + ..\..\..\..\libcpu\arm\common\div0.c + div0.c 0 0 @@ -231,20 +251,20 @@ 0 0 0 - ..\..\..\..\components\libc\compilers\common\cctype.c - cctype.c + ..\..\..\..\libcpu\arm\common\showmem.c + showmem.c 0 0 2 5 - 1 + 2 0 0 0 - ..\..\..\..\components\libc\compilers\common\cstdlib.c - cstdlib.c + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S 0 0 @@ -255,55 +275,55 @@ 0 0 0 - ..\..\..\..\components\libc\compilers\common\cstring.c - cstring.c + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c 0 0 + + + + DeviceDrivers + 0 + 0 + 0 + 0 - 2 + 3 7 1 0 0 0 - ..\..\..\..\components\libc\compilers\common\ctime.c - ctime.c + ..\..\..\..\components\drivers\clock_time\clock_boottime.c + clock_boottime.c 0 0 - 2 + 3 8 1 0 0 0 - ..\..\..\..\components\libc\compilers\common\cunistd.c - cunistd.c + ..\..\..\..\components\drivers\clock_time\clock_hrtimer.c + clock_hrtimer.c 0 0 - 2 + 3 9 1 0 0 0 - ..\..\..\..\components\libc\compilers\common\cwchar.c - cwchar.c + ..\..\..\..\components\drivers\clock_time\clock_time_core.c + clock_time_core.c 0 0 - - - - DeviceDrivers - 0 - 0 - 0 - 0 3 10 @@ -311,8 +331,8 @@ 0 0 0 - ..\..\..\..\components\drivers\core\device.c - device.c + ..\..\..\..\components\drivers\clock_time\clock_timer.c + clock_timer.c 0 0 @@ -323,8 +343,8 @@ 0 0 0 - ..\..\..\..\components\drivers\hwtimer\hwtimer.c - hwtimer.c + ..\..\..\..\components\drivers\core\device.c + device.c 0 0 @@ -479,8 +499,8 @@ 0 0 0 - ..\..\..\..\components\drivers\misc\rt_drv_pwm.c - rt_drv_pwm.c + ..\..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c 0 0 @@ -491,8 +511,8 @@ 0 0 0 - ..\..\..\..\components\drivers\pin\dev_pin.c - dev_pin.c + ..\..\..\..\components\drivers\sensor\v1\sensor.c + sensor.c 0 0 @@ -503,6 +523,18 @@ 0 0 0 + ..\..\..\..\components\drivers\sensor\v1\sensor_cmd.c + sensor_cmd.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 ..\..\..\..\components\drivers\serial\dev_serial.c dev_serial.c 0 @@ -512,13 +544,13 @@ Drivers - 0 + 1 0 0 0 4 - 27 + 28 1 0 0 @@ -530,55 +562,55 @@ 4 - 28 + 29 1 0 0 0 - ..\libraries\gd32_drivers\drv_gpio.c - drv_gpio.c + board\board_ms5611.c + board_ms5611.c 0 0 4 - 29 + 30 1 0 0 0 - ..\libraries\gd32_drivers\drv_hard_i2c.c - drv_hard_i2c.c + ..\libraries\gd32_drivers\drv_gpio.c + drv_gpio.c 0 0 4 - 30 + 31 1 0 0 0 - ..\libraries\gd32_drivers\drv_hwtimer.c - drv_hwtimer.c + ..\libraries\gd32_drivers\drv_hard_i2c.c + drv_hard_i2c.c 0 0 4 - 31 + 32 1 0 0 0 - ..\libraries\gd32_drivers\drv_pwm.c - drv_pwm.c + ..\libraries\gd32_drivers\drv_timer.c + drv_timer.c 0 0 4 - 32 + 33 1 0 0 @@ -598,49 +630,49 @@ 0 5 - 33 + 34 1 0 0 0 - ..\..\..\..\components\finsh\msh.c - msh.c + ..\..\..\..\components\finsh\shell.c + shell.c 0 0 5 - 34 + 35 1 0 0 0 - ..\..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\..\components\finsh\msh.c + msh.c 0 0 5 - 35 + 36 1 0 0 0 - ..\..\..\..\components\finsh\shell.c - shell.c + ..\..\..\..\components\finsh\msh_parse.c + msh_parse.c 0 0 5 - 36 + 37 1 0 0 0 - ..\..\..\..\components\finsh\msh_parse.c - msh_parse.c + ..\..\..\..\components\finsh\cmd.c + cmd.c 0 0 @@ -654,7 +686,7 @@ 0 6 - 37 + 38 1 0 0 @@ -666,7 +698,7 @@ 6 - 38 + 39 1 0 0 @@ -678,7 +710,7 @@ 6 - 39 + 40 1 0 0 @@ -690,7 +722,7 @@ 6 - 40 + 41 1 0 0 @@ -702,7 +734,7 @@ 6 - 41 + 42 1 0 0 @@ -714,7 +746,7 @@ 6 - 42 + 43 1 0 0 @@ -726,7 +758,7 @@ 6 - 43 + 44 1 0 0 @@ -738,7 +770,7 @@ 6 - 44 + 45 1 0 0 @@ -750,7 +782,7 @@ 6 - 45 + 46 1 0 0 @@ -762,7 +794,7 @@ 6 - 46 + 47 1 0 0 @@ -774,7 +806,7 @@ 6 - 47 + 48 1 0 0 @@ -786,7 +818,7 @@ 6 - 48 + 49 1 0 0 @@ -798,7 +830,7 @@ 6 - 49 + 50 1 0 0 @@ -810,7 +842,7 @@ 6 - 50 + 51 1 0 0 @@ -822,7 +854,7 @@ 6 - 51 + 52 1 0 0 @@ -835,23 +867,11 @@ - klibc + Libc 0 0 0 0 - - 7 - 52 - 1 - 0 - 0 - 0 - ..\..\..\..\src\klibc\kerrno.c - kerrno.c - 0 - 0 - 7 53 @@ -859,8 +879,8 @@ 0 0 0 - ..\..\..\..\src\klibc\rt_vsscanf.c - rt_vsscanf.c + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c 0 0 @@ -871,8 +891,8 @@ 0 0 0 - ..\..\..\..\src\klibc\kstring.c - kstring.c + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c 0 0 @@ -883,8 +903,8 @@ 0 0 0 - ..\..\..\..\src\klibc\kstdio.c - kstdio.c + ..\..\..\..\components\libc\compilers\common\cctype.c + cctype.c 0 0 @@ -895,76 +915,116 @@ 0 0 0 - ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c - rt_vsnprintf_tiny.c + ..\..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c 0 0 - - - - libcpu - 0 - 0 - 0 - 0 - 8 + 7 57 1 0 0 0 - ..\..\..\..\libcpu\arm\common\atomic_arm.c - atomic_arm.c + ..\..\..\..\components\libc\compilers\common\cstring.c + cstring.c 0 0 - 8 + 7 58 1 0 0 0 - ..\..\..\..\libcpu\arm\common\div0.c - div0.c + ..\..\..\..\components\libc\compilers\common\ctime.c + ctime.c 0 0 - 8 + 7 59 1 0 0 0 - ..\..\..\..\libcpu\arm\common\showmem.c - showmem.c + ..\..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c 0 0 - 8 + 7 60 - 2 + 1 0 0 0 - ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S + ..\..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c 0 0 - 8 + 7 61 1 0 0 0 - ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c + ..\..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c 0 0 @@ -977,8 +1037,8 @@ 0 0 - 9 - 62 + 8 + 66 2 0 0 @@ -989,8 +1049,8 @@ 0 - 9 - 63 + 8 + 67 1 0 0 @@ -1001,8 +1061,8 @@ 0 - 9 - 64 + 8 + 68 1 0 0 @@ -1013,8 +1073,8 @@ 0 - 9 - 65 + 8 + 69 1 0 0 @@ -1025,8 +1085,8 @@ 0 - 9 - 66 + 8 + 70 1 0 0 @@ -1037,8 +1097,8 @@ 0 - 9 - 67 + 8 + 71 1 0 0 @@ -1049,8 +1109,8 @@ 0 - 9 - 68 + 8 + 72 1 0 0 @@ -1061,8 +1121,8 @@ 0 - 9 - 69 + 8 + 73 1 0 0 @@ -1073,8 +1133,8 @@ 0 - 9 - 70 + 8 + 74 1 0 0 @@ -1085,8 +1145,8 @@ 0 - 9 - 71 + 8 + 75 1 0 0 @@ -1096,6 +1156,50 @@ 0 0 + + 8 + 76 + 1 + 0 + 0 + 0 + .\packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c + gd32f4xx_timer.c + 0 + 0 + + + + + ms5611 + 1 + 0 + 0 + 0 + + 9 + 77 + 1 + 0 + 0 + 0 + packages\ms5611-latest\ms5611.c + ms5611.c + 0 + 0 + + + 9 + 78 + 1 + 0 + 0 + 0 + packages\ms5611-latest\sensor_meas_ms5611.c + sensor_meas_ms5611.c + 0 + 0 + diff --git a/bsp/gd32/arm/gd32405rg/project.uvprojx b/bsp/gd32/arm/gd32405rg/project.uvprojx index 69f501cf6d..8605b02cb0 100644 --- a/bsp/gd32/arm/gd32405rg/project.uvprojx +++ b/bsp/gd32/arm/gd32405rg/project.uvprojx @@ -338,9 +338,9 @@ 0 - RT_USING_LIBC, GD32F405, __RTTHREAD__, USE_STDPERIPH_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, HXTAL_VALUE=8000000U + __STDC_LIMIT_MACROS, HXTAL_VALUE=8000000U, GD32F405, __CLK_TCK=RT_TICK_PER_SECOND, USE_STDPERIPH_DRIVER, __RTTHREAD__, RT_USING_ARMLIBC, RT_USING_LIBC - applications;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\posix\io\eventfd;board;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\smp_call;..\..\..\..\libcpu\arm\common;..\..\..\..\components\drivers\include;..\..\..\..\libcpu\arm\cortex-m4;packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;..\..\..\..\components\libc\posix\io\epoll;..\libraries\gd32_drivers;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\net\utest;..\..\..\..\components\drivers\phy;..\..\..\..\include;packages\gd32-arm-cmsis-latest\GD32F4xx;.;..\..\..\..\components\drivers\include;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\finsh;..\..\..\..\components\drivers\include + ..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\phy;.;..\..\..\..\components\libc\posix\io\epoll;..\libraries\gd32_drivers\config;..\..\..\..\libcpu\arm\common;packages\ms5611-latest;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\net\utest;packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Include;..\..\..\..\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\gd32_drivers;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\posix\io\eventfd;applications;..\..\..\..\components\drivers\include;..\..\..\..\components\finsh;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;packages\gd32-arm-cmsis-latest\GD32F4xx;..\..\..\..\components\drivers\clock_time;..\..\..\..\components\drivers\include;board;packages\gd32-arm-cmsis-latest\GD32F4xx\GD\GD32F4xx\Include;..\..\..\..\components\drivers\include @@ -392,57 +392,210 @@ - Compiler + CPU - syscall_mem.c + atomic_arm.c 1 - ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + ..\..\..\..\libcpu\arm\common\atomic_arm.c - syscalls.c + div0.c 1 - ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + ..\..\..\..\libcpu\arm\common\div0.c - cctype.c + showmem.c 1 - ..\..\..\..\components\libc\compilers\common\cctype.c + ..\..\..\..\libcpu\arm\common\showmem.c - cstdlib.c - 1 - ..\..\..\..\components\libc\compilers\common\cstdlib.c + context_rvds.S + 2 + ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S - cstring.c + cpuport.c 1 - ..\..\..\..\components\libc\compilers\common\cstring.c + ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + DeviceDrivers + - ctime.c + clock_boottime.c 1 - ..\..\..\..\components\libc\compilers\common\ctime.c + ..\..\..\..\components\drivers\clock_time\clock_boottime.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 --gnu + __RT_IPC_SOURCE__ + + + + + + - cunistd.c + clock_hrtimer.c 1 - ..\..\..\..\components\libc\compilers\common\cunistd.c + ..\..\..\..\components\drivers\clock_time\clock_hrtimer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 --gnu + __RT_IPC_SOURCE__ + + + + + + - cwchar.c + clock_time_core.c 1 - ..\..\..\..\components\libc\compilers\common\cwchar.c + ..\..\..\..\components\drivers\clock_time\clock_time_core.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 --gnu + __RT_IPC_SOURCE__ + + + + + + - - - - DeviceDrivers - - device.c + clock_timer.c 1 - ..\..\..\..\components\drivers\core\device.c + ..\..\..\..\components\drivers\clock_time\clock_timer.c 2 @@ -486,7 +639,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -496,9 +649,9 @@ - hwtimer.c + device.c 1 - ..\..\..\..\components\drivers\hwtimer\hwtimer.c + ..\..\..\..\components\drivers\core\device.c 2 @@ -542,7 +695,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -598,7 +751,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -654,7 +807,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -710,7 +863,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -766,7 +919,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -822,7 +975,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -878,7 +1031,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -934,7 +1087,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -990,7 +1143,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1046,7 +1199,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1102,7 +1255,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1158,7 +1311,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1214,7 +1367,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1224,9 +1377,9 @@ - rt_drv_pwm.c + dev_pin.c 1 - ..\..\..\..\components\drivers\misc\rt_drv_pwm.c + ..\..\..\..\components\drivers\pin\dev_pin.c 2 @@ -1270,7 +1423,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1280,9 +1433,9 @@ - dev_pin.c + sensor.c 1 - ..\..\..\..\components\drivers\pin\dev_pin.c + ..\..\..\..\components\drivers\sensor\v1\sensor.c 2 @@ -1326,7 +1479,63 @@ 2 2 - + --c99 --gnu + __RT_IPC_SOURCE__ + + + + + + + + + sensor_cmd.c + 1 + ..\..\..\..\components\drivers\sensor\v1\sensor_cmd.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 --gnu __RT_IPC_SOURCE__ @@ -1382,7 +1591,7 @@ 2 2 - + --c99 --gnu __RT_IPC_SOURCE__ @@ -1401,6 +1610,11 @@ 1 board\board.c + + board_ms5611.c + 1 + board\board_ms5611.c + drv_gpio.c 1 @@ -1412,14 +1626,9 @@ ..\libraries\gd32_drivers\drv_hard_i2c.c - drv_hwtimer.c - 1 - ..\libraries\gd32_drivers\drv_hwtimer.c - - - drv_pwm.c + drv_timer.c 1 - ..\libraries\gd32_drivers\drv_pwm.c + ..\libraries\gd32_drivers\drv_timer.c drv_usart.c @@ -1432,24 +1641,24 @@ Finsh - msh.c + shell.c 1 - ..\..\..\..\components\finsh\msh.c + ..\..\..\..\components\finsh\shell.c - cmd.c + msh.c 1 - ..\..\..\..\components\finsh\cmd.c + ..\..\..\..\components\finsh\msh.c - shell.c + msh_parse.c 1 - ..\..\..\..\components\finsh\shell.c + ..\..\..\..\components\finsh\msh_parse.c - msh_parse.c + cmd.c 1 - ..\..\..\..\components\finsh\msh_parse.c + ..\..\..\..\components\finsh\cmd.c @@ -2299,62 +2508,72 @@ - klibc + Libc - kerrno.c + syscall_mem.c 1 - ..\..\..\..\src\klibc\kerrno.c + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c - rt_vsscanf.c + syscalls.c 1 - ..\..\..\..\src\klibc\rt_vsscanf.c + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c - kstring.c + cctype.c 1 - ..\..\..\..\src\klibc\kstring.c + ..\..\..\..\components\libc\compilers\common\cctype.c - kstdio.c + cstdlib.c 1 - ..\..\..\..\src\klibc\kstdio.c + ..\..\..\..\components\libc\compilers\common\cstdlib.c - rt_vsnprintf_tiny.c + cstring.c 1 - ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + ..\..\..\..\components\libc\compilers\common\cstring.c - - - - libcpu - - atomic_arm.c + ctime.c 1 - ..\..\..\..\libcpu\arm\common\atomic_arm.c + ..\..\..\..\components\libc\compilers\common\ctime.c - div0.c + cunistd.c 1 - ..\..\..\..\libcpu\arm\common\div0.c + ..\..\..\..\components\libc\compilers\common\cunistd.c - showmem.c + cwchar.c 1 - ..\..\..\..\libcpu\arm\common\showmem.c + ..\..\..\..\components\libc\compilers\common\cwchar.c - context_rvds.S - 2 - ..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S + kerrno.c + 1 + ..\..\..\..\src\klibc\kerrno.c - cpuport.c + kstdio.c 1 - ..\..\..\..\libcpu\arm\cortex-m4\cpuport.c + ..\..\..\..\src\klibc\kstdio.c + + + kstring.c + 1 + ..\..\..\..\src\klibc\kstring.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + rt_vsscanf.c + 1 + ..\..\..\..\src\klibc\rt_vsscanf.c @@ -2411,6 +2630,26 @@ 1 packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c + + gd32f4xx_timer.c + 1 + .\packages\gd32-arm-series-latest\GD32F4xx\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c + + + + + ms5611 + + + ms5611.c + 1 + packages\ms5611-latest\ms5611.c + + + sensor_meas_ms5611.c + 1 + packages\ms5611-latest\sensor_meas_ms5611.c + diff --git a/bsp/gd32/arm/gd32405rg/rtconfig.h b/bsp/gd32/arm/gd32405rg/rtconfig.h index ad67872218..509929f1ab 100644 --- a/bsp/gd32/arm/gd32405rg/rtconfig.h +++ b/bsp/gd32/arm/gd32405rg/rtconfig.h @@ -102,7 +102,8 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50201 +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -147,11 +148,12 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CLOCK_TIME #define RT_USING_I2C #define RT_USING_I2C_BITOPS -#define RT_USING_PWM +#define RT_USING_SENSOR +#define RT_USING_SENSOR_CMD #define RT_USING_PIN -#define RT_USING_HWTIMER /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -333,6 +335,10 @@ /* sensors drivers */ +#define PKG_USING_MS5611 +#define PKG_MS5611_USING_SENSOR_V1 +#define PKG_MS5611_USING_BARO +#define PKG_USING_MS5611_LATEST_VERSION /* end of sensors drivers */ /* touch drivers */ @@ -421,10 +427,16 @@ #define BSP_USING_GPIO #define BSP_USING_UART +#define BSP_USING_SERIAL_V1 #define BSP_USING_UART0 +#define BSP_UART0_TX_PIN "PA9" +#define BSP_UART0_RX_PIN "PA10" +#define BSP_UART0_AFIO "AF7" #define BSP_USING_HARD_I2C #define BSP_USING_RECEIVING_A #define BSP_USING_HARD_I2C0 +#define BSP_USING_CLOCK_TIMER +#define BSP_USING_CLOCK_TIMER6 #define BSP_USING_GD_DBG /* end of On-chip Peripheral Drivers */ diff --git a/bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c b/bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c index fe35d21094..be459ffcf6 100644 --- a/bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c +++ b/bsp/gd32/arm/libraries/gd32_drivers/drv_timer.c @@ -6,10 +6,6 @@ * Change Logs: * Date Author Notes * 2021-02-25 iysheng first version - * 2025-12-26 shihongchao Configure GD32F4xx chips interrupt handlers, - * relocate clock and interrupt initialization - * to the _init function, and implement deinit - * functionality */ #include @@ -118,30 +114,16 @@ static void __set_timerx_freq(uint32_t timerx, uint32_t freq) static void gd32_clock_timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { uint32_t timer_base = (uint32_t)timer->parent.user_data; - gd32_hwtimer_device *hwtimer = rt_container_of(timer, gd32_hwtimer_device, hwtimer_dev); timer_parameter_struct initpara; if (state) { - rcu_periph_clock_enable(hwtimer->hw_data.rcu); - NVIC_SetPriority(hwtimer->hw_data.irqn, 0); - NVIC_EnableIRQ(hwtimer->hw_data.irqn); - timer_interrupt_enable(timer_base, TIMER_INT_UP); - timer_internal_clock_config(timer_base); timer_struct_para_init(&initpara); initpara.period = timer->info->maxcnt; timer_init(timer_base, &initpara); __set_timerx_freq(timer_base, timer->info->maxfreq); } - else - { - rcu_periph_clock_disable(hwtimer->hw_data.rcu); - NVIC_DisableIRQ(hwtimer->hw_data.irqn); - timer_interrupt_disable(timer_base, TIMER_INT_UP); - - timer_disable(timer_base); - } } static rt_err_t gd32_clock_timer_start(struct rt_clock_timer_device *timer, \ @@ -218,11 +200,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer0", { TIMER0, -#ifdef SOC_SERIES_GD32F4xx - TIMER0_UP_TIMER9_IRQn, -#else TIMER0_UP_IRQn, -#endif RCU_TIMER0, }, {0}, @@ -307,11 +285,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer5", { TIMER5, -#ifdef SOC_SERIES_GD32F4xx - TIMER5_DAC_IRQn, -#else TIMER5_IRQn, -#endif RCU_TIMER5, }, {0}, @@ -345,11 +319,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer7", { TIMER7, -#ifdef SOC_SERIES_GD32F4xx - TIMER7_UP_TIMER12_IRQn, -#else TIMER7_UP_IRQn, -#endif RCU_TIMER7, }, {0}, @@ -366,11 +336,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer8", { TIMER8, -#ifdef SOC_SERIES_GD32F4xx - TIMER0_BRK_TIMER8_IRQn, -#else TIMER8_IRQn, -#endif RCU_TIMER8, }, {0}, @@ -387,11 +353,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer9", { TIMER9, -#ifdef SOC_SERIES_GD32F4xx - TIMER0_UP_TIMER9_IRQn, -#else TIMER9_IRQn, -#endif RCU_TIMER9, }, {0}, @@ -408,11 +370,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer10", { TIMER10, -#ifdef SOC_SERIES_GD32F4xx - TIMER0_TRG_CMT_TIMER10_IRQn, -#else TIMER10_IRQn, -#endif RCU_TIMER10, }, {0}, @@ -429,11 +387,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer11", { TIMER11, -#ifdef SOC_SERIES_GD32F4xx - TIMER7_BRK_TIMER11_IRQn, -#else TIMER11_IRQn, -#endif RCU_TIMER11, }, {0}, @@ -450,11 +404,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer12", { TIMER12, -#ifdef SOC_SERIES_GD32F4xx - TIMER7_UP_TIMER12_IRQn, -#else TIMER12_IRQn, -#endif RCU_TIMER12, }, {0}, @@ -471,11 +421,7 @@ static gd32_clock_timer_device g_gd32_clock_timer[] = { "timer13", { TIMER13, -#ifdef SOC_SERIES_GD32F4xx - TIMER7_TRG_CMT_TIMER13_IRQn, -#else TIMER13_IRQn, -#endif RCU_TIMER13, }, {0}, -- Gitee

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